From 5353e9f012492596d4f02077fd0715f71abfbdd2 Mon Sep 17 00:00:00 2001
From: Alistair Buxton <a.j.buxton@gmail.com>
Date: Sun, 5 Mar 2023 02:33:25 +0000
Subject: [PATCH] BOARD_32BLIT_ALPHA: Fix quad mode enable for Winbond flash

This makes flashing and erasing blits work. They still don't run.
Either memory mapped mode is not working yet or there is some other
problem with the launcher.
---
 32blit-stm32/Src/quadspi.c | 39 ++++++++++++++++++++++++++++++++++++--
 1 file changed, 37 insertions(+), 2 deletions(-)

diff --git a/32blit-stm32/Src/quadspi.c b/32blit-stm32/Src/quadspi.c
index 52555fc6d..81ecd94d8 100644
--- a/32blit-stm32/Src/quadspi.c
+++ b/32blit-stm32/Src/quadspi.c
@@ -391,6 +391,31 @@ static HAL_StatusTypeDef qspi_enable_quad(QSPI_HandleTypeDef *hqspi)
 {
     QSPI_CommandTypeDef s_command = {0};
 
+    /* In order to write the SR2 we must first enable writing.
+     * We could send a normal WriteEnable - this will cause the value
+     * written to SR2 to be saved in non-volatile memory. This causes
+     * wear on the flash.
+     * We can alternatively send a 0x50 command - this will cause the value
+     * written to SR2 to be saved in volatile memory, and not written to
+     * flash. It will go back to the old value after reset, but we can
+     * just write it again.
+     */
+
+    s_command.Instruction = 0x50;
+    s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE;
+    s_command.AddressMode = QSPI_ADDRESS_NONE;
+    s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
+    s_command.DataMode = QSPI_DATA_NONE;
+    s_command.DummyCycles = 0;
+    s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
+    s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
+    s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
+    s_command.NbData      = 0;
+    if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+    {
+        Error_Handler();
+    }
+
     uint8_t status[1] = {0x02};
     s_command.Instruction = WRITE_STATUS_REG2;
     s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE;
@@ -425,12 +450,19 @@ HAL_StatusTypeDef qspi_enable_memorymapped_mode(void)
     s_command.AddressSize       = QSPI_ADDRESS_SIZE;
     s_command.DataMode          = QSPI_DATA_4_LINES;
     s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
-    s_command.DummyCycles       = 6;
     s_command.SIOOMode          = QSPI_SIOO_INST_EVERY_CMD;
 
+#ifdef BOARD_32BLIT_ALPHA
+    s_command.DummyCycles       = 8;
+    s_command.Instruction       = QUAD_OUT_FAST_READ_CMD;
+    s_command.DdrMode           = QSPI_DDR_MODE_DISABLE;
+    s_command.DdrHoldHalfCycle  = QSPI_DDR_HHC_ANALOG_DELAY;
+#else
+    s_command.DummyCycles       = 6;
     s_command.Instruction       = QUAD_OUT_FAST_READ_DTR_CMD;
     s_command.DdrMode           = QSPI_DDR_MODE_ENABLE;
     s_command.DdrHoldHalfCycle  = QSPI_DDR_HHC_HALF_CLK_DELAY;
+#endif
 
     /* Configure the memory mapped mode */
     s_mem_mapped_cfg.TimeOutActivation = QSPI_TIMEOUT_COUNTER_DISABLE;
@@ -483,8 +515,11 @@ static HAL_StatusTypeDef qspi_enable_4byte_addr(QSPI_HandleTypeDef *hqspi)
 #pragma GCC optimize ("O0")
 int qspi_init(void) {
   qspi_reset(&hqspi);
+#ifdef BOARD_32BLIT_ALPHA
+  // Winbond 8MB flash - must enable quad mode
   qspi_enable_quad(&hqspi);
-#ifndef BOARD_32BLIT_ALPHA
+#else
+  // Micron 32MB flash - must enable 4 byte addresses
   qspi_enable_4byte_addr(&hqspi);
 #endif
   return(0);