fuse.log

Running: C:\Xilinx\12.1\ISE_DS\ISE\bin\nt\unwrapped\fuse.exe -intstyle ise -incremental -lib unisims_ver -lib unimacro_ver -lib xilinxcorelib_ver -lib secureip -o X:/Desktop/Router/uart_tx_test_isim_beh.exe -prj X:/Desktop/Router/uart_tx_test_beh.prj work.uart_tx_test work.glbl 
ISim M.53d (signature 0xb869381d)
Number of CPUs detected in this system: 2
Turning on mult-threading, number of parallel sub-compilation jobs: 4 
Determining compilation order of HDL files
Parsing Verilog file "X:/Desktop/Router/uart_tx.v" into library work
Parsing Verilog file "X:/Desktop/Router/uart_tx_test.v" into library work
Parsing Verilog file "C:/Xilinx/12.1/ISE_DS/ISE/verilog/src/glbl.v" into library work
Starting static elaboration
Completed static elaboration
Fuse Memory Usage: 57552 KB
Fuse CPU Usage: 93 ms
Compiling module uart_tx
Compiling module uart_tx_test
Compiling module glbl
Time Resolution for simulation is 1ps.
Waiting for 1 sub-compilation(s) to finish...
Compiled 3 Verilog Units
Built simulation executable X:/Desktop/Router/uart_tx_test_isim_beh.exe
Fuse Memory Usage: 83152 KB
Fuse CPU Usage: 109 ms