From 5ec731874768aaf64e9184132c124de87798394d Mon Sep 17 00:00:00 2001
From: Afonso Bordado <afonso360@users.noreply.github.com>
Date: Thu, 31 Aug 2023 19:24:25 +0100
Subject: [PATCH] riscv64: Use `PCRelLo12I` relocation on Loads (#6938)

* riscv64: Use `PCRelLo12I` relocation on Loads

* riscv64: Strenghten pattern matching when emitting Load's

* riscv64: Clarify some of the load address logic

* riscv64: Even stronger matching
---
 .../codegen/src/isa/riscv64/inst/args.rs      | 12 +++
 .../codegen/src/isa/riscv64/inst/emit.rs      | 47 ++++++++---
 .../filetests/isa/riscv64/constants.clif      | 78 +++++++++----------
 .../filetests/isa/riscv64/fcvt-small.clif     | 26 +++----
 .../filetests/isa/riscv64/float.clif          | 72 +++++++----------
 .../filetests/isa/riscv64/return-call.clif    |  6 +-
 .../filetests/isa/riscv64/simd-ceil.clif      |  6 +-
 .../filetests/isa/riscv64/simd-floor.clif     |  6 +-
 .../filetests/isa/riscv64/simd-fmax.clif      |  6 +-
 .../filetests/isa/riscv64/simd-fmin.clif      |  6 +-
 .../isa/riscv64/simd-iadd_pairwise.clif       | 30 +++----
 .../filetests/isa/riscv64/simd-nearest.clif   |  6 +-
 .../filetests/isa/riscv64/simd-popcnt.clif    | 20 ++---
 .../filetests/isa/riscv64/simd-trunc.clif     |  6 +-
 14 files changed, 163 insertions(+), 164 deletions(-)

diff --git a/cranelift/codegen/src/isa/riscv64/inst/args.rs b/cranelift/codegen/src/isa/riscv64/inst/args.rs
index 40ebbc94fd1f..18d8ae9b7546 100644
--- a/cranelift/codegen/src/isa/riscv64/inst/args.rs
+++ b/cranelift/codegen/src/isa/riscv64/inst/args.rs
@@ -161,6 +161,18 @@ impl AMode {
         }
     }
 
+    /// Retrieve a MachLabel that corresponds to this addressing mode, if it exists.
+    pub(crate) fn get_label_with_sink(&self, sink: &mut MachBuffer<Inst>) -> Option<MachLabel> {
+        match self {
+            &AMode::Const(addr) => Some(sink.get_label_for_constant(addr)),
+            &AMode::Label(label) => Some(label),
+            &AMode::RegOffset(..)
+            | &AMode::SPOffset(..)
+            | &AMode::FPOffset(..)
+            | &AMode::NominalSPOffset(..) => None,
+        }
+    }
+
     pub(crate) fn to_string_with_alloc(&self, allocs: &mut AllocationConsumer<'_>) -> String {
         format!("{}", self.clone().with_allocs(allocs))
     }
diff --git a/cranelift/codegen/src/isa/riscv64/inst/emit.rs b/cranelift/codegen/src/isa/riscv64/inst/emit.rs
index 10ab5649412f..48b2c8ea3a0e 100644
--- a/cranelift/codegen/src/isa/riscv64/inst/emit.rs
+++ b/cranelift/codegen/src/isa/riscv64/inst/emit.rs
@@ -620,18 +620,49 @@ impl MachInstEmit for Inst {
                 let base = from.get_base_register();
                 let offset = from.get_offset_with_state(state);
                 let offset_imm12 = Imm12::maybe_from_i64(offset);
+                let label = from.get_label_with_sink(sink);
 
-                // TODO: We shouldn't just fall back to `LoadAddr` immediately. For `MachLabel`s
-                // we should try to emit the `auipc` and add a relocation on this load.
-                let (addr, imm12) = match (base, offset_imm12) {
-                    // If the offset fits into an imm12 we can directly encode it.
-                    (Some(base), Some(imm12)) => (base, imm12),
-                    // Otherwise load the address it into a reg and load from it.
-                    _ => {
+                let (addr, imm12) = match (base, offset_imm12, label) {
+                    // When loading from a Reg+Offset, if the offset fits into an imm12 we can directly encode it.
+                    (Some(base), Some(imm12), None) => (base, imm12),
+
+                    // Otherwise, if the offset does not fit into a imm12, we need to materialize it into a
+                    // register and load from that.
+                    (Some(_), None, None) => {
                         let tmp = writable_spilltmp_reg();
                         Inst::LoadAddr { rd: tmp, mem: from }.emit(&[], sink, emit_info, state);
                         (tmp.to_reg(), Imm12::zero())
                     }
+
+                    // If the AMode contains a label we can emit an internal relocation that gets
+                    // resolved with the correct address later.
+                    (None, Some(imm), Some(label)) => {
+                        debug_assert_eq!(imm.as_i16(), 0);
+
+                        // Get the current PC.
+                        sink.use_label_at_offset(sink.cur_offset(), label, LabelUse::PCRelHi20);
+                        Inst::Auipc {
+                            rd,
+                            imm: Imm20::from_bits(0),
+                        }
+                        .emit(&[], sink, emit_info, state);
+
+                        // Emit a relocation for the load. This patches the offset into the instruction.
+                        sink.use_label_at_offset(sink.cur_offset(), label, LabelUse::PCRelLo12I);
+
+                        // Imm12 here is meaningless since it's going to get replaced.
+                        (rd.to_reg(), Imm12::zero())
+                    }
+
+                    // These cases are impossible with the current AModes that we have. We either
+                    // always have a register, or always have a label. Never both, and never neither.
+                    (None, None, None)
+                    | (None, Some(_), None)
+                    | (Some(_), None, Some(_))
+                    | (Some(_), Some(_), Some(_))
+                    | (None, None, Some(_)) => {
+                        unreachable!("Invalid load address")
+                    }
                 };
 
                 let srcloc = state.cur_srcloc();
@@ -650,8 +681,6 @@ impl MachInstEmit for Inst {
                 let offset = to.get_offset_with_state(state);
                 let offset_imm12 = Imm12::maybe_from_i64(offset);
 
-                // TODO: We shouldn't just fall back to `LoadAddr` immediately. For `MachLabel`s
-                // we should try to emit the `auipc` and add a relocation on this store.
                 let (addr, imm12) = match (base, offset_imm12) {
                     // If the offset fits into an imm12 we can directly encode it.
                     (Some(base), Some(imm12)) => (base, imm12),
diff --git a/cranelift/filetests/filetests/isa/riscv64/constants.clif b/cranelift/filetests/filetests/isa/riscv64/constants.clif
index 9a1afa3b29df..ed8ef4192dbd 100644
--- a/cranelift/filetests/filetests/isa/riscv64/constants.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/constants.clif
@@ -81,10 +81,10 @@ block0:
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   auipc t6, 0
-;   addi t6, t6, 0x10
-;   ld a0, 0(t6)
+;   auipc a0, 0
+;   ld a0, 0x10(a0)
 ;   ret
+;   .byte 0x00, 0x00, 0x00, 0x00
 ;   .byte 0x00, 0x00, 0xff, 0xff
 ;   .byte 0x00, 0x00, 0x00, 0x00
 
@@ -101,11 +101,11 @@ block0:
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   auipc t6, 0
-;   addi t6, t6, 0x10
-;   ld a0, 0(t6)
+;   auipc a0, 0
+;   ld a0, 0x10(a0)
 ;   ret
 ;   .byte 0x00, 0x00, 0x00, 0x00
+;   .byte 0x00, 0x00, 0x00, 0x00
 ;   .byte 0xff, 0xff, 0x00, 0x00
 
 function %f() -> i64 {
@@ -121,11 +121,11 @@ block0:
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   auipc t6, 0
-;   addi t6, t6, 0x10
-;   ld a0, 0(t6)
+;   auipc a0, 0
+;   ld a0, 0x10(a0)
 ;   ret
 ;   .byte 0x00, 0x00, 0x00, 0x00
+;   .byte 0x00, 0x00, 0x00, 0x00
 ;   .byte 0x00, 0x00, 0xff, 0xff
 
 function %f() -> i64 {
@@ -173,10 +173,10 @@ block0:
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   auipc t6, 0
-;   addi t6, t6, 0x10
-;   ld a0, 0(t6)
+;   auipc a0, 0
+;   ld a0, 0x10(a0)
 ;   ret
+;   .byte 0x00, 0x00, 0x00, 0x00
 ;   .byte 0xff, 0xff, 0x00, 0x00
 ;   .byte 0xff, 0xff, 0xff, 0xff
 
@@ -193,10 +193,10 @@ block0:
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   auipc t6, 0
-;   addi t6, t6, 0x10
-;   ld a0, 0(t6)
+;   auipc a0, 0
+;   ld a0, 0x10(a0)
 ;   ret
+;   .byte 0x00, 0x00, 0x00, 0x00
 ;   .byte 0xff, 0xff, 0xff, 0xff
 ;   .byte 0x00, 0x00, 0xff, 0xff
 
@@ -213,10 +213,10 @@ block0:
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   auipc t6, 0
-;   addi t6, t6, 0x10
-;   ld a0, 0(t6)
+;   auipc a0, 0
+;   ld a0, 0x10(a0)
 ;   ret
+;   .byte 0x00, 0x00, 0x00, 0x00
 ;   .byte 0xff, 0xff, 0xff, 0xff
 ;   .byte 0xff, 0xff, 0x00, 0x00
 
@@ -233,10 +233,10 @@ block0:
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   auipc t6, 0
-;   addi t6, t6, 0x10
-;   ld a0, 0(t6)
+;   auipc a0, 0
+;   ld a0, 0x10(a0)
 ;   ret
+;   .byte 0x00, 0x00, 0x00, 0x00
 ;   .byte 0x3a, 0x00, 0x12, 0x12
 ;   .byte 0xa3, 0xf0, 0x4b, 0xf3
 
@@ -253,10 +253,10 @@ block0:
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   auipc t6, 0
-;   addi t6, t6, 0x10
-;   ld a0, 0(t6)
+;   auipc a0, 0
+;   ld a0, 0x10(a0)
 ;   ret
+;   .byte 0x00, 0x00, 0x00, 0x00
 ;   .byte 0x00, 0x00, 0xf4, 0x1e
 ;   .byte 0x00, 0x00, 0xe9, 0x12
 
@@ -273,10 +273,10 @@ block0:
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   auipc t6, 0
-;   addi t6, t6, 0x10
-;   ld a0, 0(t6)
+;   auipc a0, 0
+;   ld a0, 0x10(a0)
 ;   ret
+;   .byte 0x00, 0x00, 0x00, 0x00
 ;   .byte 0xff, 0xff, 0xf4, 0x1e
 ;   .byte 0xff, 0xff, 0xe9, 0x12
 
@@ -325,10 +325,10 @@ block0:
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   auipc t6, 0
-;   addi t6, t6, 0x10
-;   ld a0, 0(t6)
+;   auipc a0, 0
+;   ld a0, 0x10(a0)
 ;   ret
+;   .byte 0x00, 0x00, 0x00, 0x00
 ;   .byte 0xf7, 0xff, 0xff, 0xff
 ;   .byte 0x00, 0x00, 0x00, 0x00
 
@@ -362,13 +362,11 @@ block0:
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   auipc t6, 0
-;   addi t6, t6, 0x18
-;   ld t0, 0(t6)
+;   auipc t0, 0
+;   ld t0, 0x10(t0)
 ;   fmv.d.x fa0, t0
 ;   ret
 ;   .byte 0x00, 0x00, 0x00, 0x00
-;   .byte 0x00, 0x00, 0x00, 0x00
 ;   .byte 0x00, 0x00, 0xf0, 0x3f
 
 function %f() -> f32 {
@@ -403,13 +401,11 @@ block0:
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   auipc t6, 0
-;   addi t6, t6, 0x18
-;   ld t0, 0(t6)
+;   auipc t0, 0
+;   ld t0, 0x10(t0)
 ;   fmv.d.x fa0, t0
 ;   ret
 ;   .byte 0x00, 0x00, 0x00, 0x00
-;   .byte 0x00, 0x00, 0x00, 0x00
 ;   .byte 0x00, 0x00, 0x49, 0x40
 
 function %f() -> f32 {
@@ -480,13 +476,11 @@ block0:
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   auipc t6, 0
-;   addi t6, t6, 0x18
-;   ld t0, 0(t6)
+;   auipc t0, 0
+;   ld t0, 0x10(t0)
 ;   fmv.d.x fa0, t0
 ;   ret
 ;   .byte 0x00, 0x00, 0x00, 0x00
-;   .byte 0x00, 0x00, 0x00, 0x00
 ;   .byte 0x00, 0x00, 0x30, 0xc0
 
 function %f() -> f32 {
diff --git a/cranelift/filetests/filetests/isa/riscv64/fcvt-small.clif b/cranelift/filetests/filetests/isa/riscv64/fcvt-small.clif
index feb8e7c7d452..d85137c8e3f2 100644
--- a/cranelift/filetests/filetests/isa/riscv64/fcvt-small.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/fcvt-small.clif
@@ -92,10 +92,9 @@ block0(v0: f32):
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   feq.s a0, fa0, fa0
-;   beqz a0, 0x44
+;   beqz a0, 0x40
 ;   auipc t6, 0
-;   addi t6, t6, 0x10
-;   lw t6, 0(t6)
+;   lw t6, 0xc(t6)
 ;   j 8
 ;   .byte 0x00, 0x00, 0x80, 0xbf
 ;   fmv.w.x ft3, t6
@@ -126,10 +125,9 @@ block0(v0: f64):
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   feq.d a0, fa0, fa0
-;   beqz a0, 0x5c
+;   beqz a0, 0x54
 ;   auipc t6, 0
-;   addi t6, t6, 0x10
-;   ld t6, 0(t6)
+;   ld t6, 0xc(t6)
 ;   j 0xc
 ;   .byte 0x00, 0x00, 0x00, 0x00
 ;   .byte 0x00, 0x00, 0xf0, 0xbf
@@ -138,8 +136,7 @@ block0(v0: f64):
 ;   beqz a0, 8
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_ovf
 ;   auipc t6, 0
-;   addi t6, t6, 0x10
-;   ld t6, 0(t6)
+;   ld t6, 0xc(t6)
 ;   j 0xc
 ;   .byte 0x00, 0x00, 0x00, 0x00
 ;   .byte 0x00, 0x00, 0x70, 0x40
@@ -166,10 +163,9 @@ block0(v0: f32):
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   feq.s a0, fa0, fa0
-;   beqz a0, 0x44
+;   beqz a0, 0x40
 ;   auipc t6, 0
-;   addi t6, t6, 0x10
-;   lw t6, 0(t6)
+;   lw t6, 0xc(t6)
 ;   j 8
 ;   .byte 0x00, 0x00, 0x80, 0xbf
 ;   fmv.w.x ft3, t6
@@ -200,10 +196,9 @@ block0(v0: f64):
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   feq.d a0, fa0, fa0
-;   beqz a0, 0x5c
+;   beqz a0, 0x54
 ;   auipc t6, 0
-;   addi t6, t6, 0x10
-;   ld t6, 0(t6)
+;   ld t6, 0xc(t6)
 ;   j 0xc
 ;   .byte 0x00, 0x00, 0x00, 0x00
 ;   .byte 0x00, 0x00, 0xf0, 0xbf
@@ -212,8 +207,7 @@ block0(v0: f64):
 ;   beqz a0, 8
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_ovf
 ;   auipc t6, 0
-;   addi t6, t6, 0x10
-;   ld t6, 0(t6)
+;   ld t6, 0xc(t6)
 ;   j 0xc
 ;   .byte 0x00, 0x00, 0x00, 0x00
 ;   .byte 0x00, 0x00, 0xf0, 0x40
diff --git a/cranelift/filetests/filetests/isa/riscv64/float.clif b/cranelift/filetests/filetests/isa/riscv64/float.clif
index bf33bab5cf5d..7b839f037b5b 100644
--- a/cranelift/filetests/filetests/isa/riscv64/float.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/float.clif
@@ -453,10 +453,9 @@ block0(v0: f64):
 ; block0: ; offset 0x0
 ;   fmv.d ft5, fa0
 ;   feq.d a0, ft5, ft5
-;   beqz a0, 0x3c
+;   beqz a0, 0x38
 ;   auipc t6, 0
-;   addi t6, t6, 0x10
-;   ld t6, 0(t6)
+;   ld t6, 0xc(t6)
 ;   j 0xc
 ;   .byte 0x00, 0x00, 0x00, 0x00
 ;   .byte 0x00, 0x00, 0x40, 0x43
@@ -520,10 +519,9 @@ block0(v0: f64):
 ; block0: ; offset 0x0
 ;   fmv.d ft5, fa0
 ;   feq.d a0, ft5, ft5
-;   beqz a0, 0x3c
+;   beqz a0, 0x38
 ;   auipc t6, 0
-;   addi t6, t6, 0x10
-;   ld t6, 0(t6)
+;   ld t6, 0xc(t6)
 ;   j 0xc
 ;   .byte 0x00, 0x00, 0x00, 0x00
 ;   .byte 0x00, 0x00, 0x40, 0x43
@@ -587,10 +585,9 @@ block0(v0: f64):
 ; block0: ; offset 0x0
 ;   fmv.d ft5, fa0
 ;   feq.d a0, ft5, ft5
-;   beqz a0, 0x3c
+;   beqz a0, 0x38
 ;   auipc t6, 0
-;   addi t6, t6, 0x10
-;   ld t6, 0(t6)
+;   ld t6, 0xc(t6)
 ;   j 0xc
 ;   .byte 0x00, 0x00, 0x00, 0x00
 ;   .byte 0x00, 0x00, 0x40, 0x43
@@ -654,10 +651,9 @@ block0(v0: f64):
 ; block0: ; offset 0x0
 ;   fmv.d ft5, fa0
 ;   feq.d a0, ft5, ft5
-;   beqz a0, 0x3c
+;   beqz a0, 0x38
 ;   auipc t6, 0
-;   addi t6, t6, 0x10
-;   ld t6, 0(t6)
+;   ld t6, 0xc(t6)
 ;   j 0xc
 ;   .byte 0x00, 0x00, 0x00, 0x00
 ;   .byte 0x00, 0x00, 0x40, 0x43
@@ -752,10 +748,9 @@ block0(v0: f32):
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   feq.s a0, fa0, fa0
-;   beqz a0, 0x44
+;   beqz a0, 0x40
 ;   auipc t6, 0
-;   addi t6, t6, 0x10
-;   lw t6, 0(t6)
+;   lw t6, 0xc(t6)
 ;   j 8
 ;   .byte 0x00, 0x00, 0x80, 0xbf
 ;   fmv.w.x ft3, t6
@@ -786,10 +781,9 @@ block0(v0: f32):
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   feq.s a0, fa0, fa0
-;   beqz a0, 0x44
+;   beqz a0, 0x40
 ;   auipc t6, 0
-;   addi t6, t6, 0x10
-;   lw t6, 0(t6)
+;   lw t6, 0xc(t6)
 ;   j 8
 ;   .byte 0x01, 0x00, 0x00, 0xcf
 ;   fmv.w.x ft3, t6
@@ -820,10 +814,9 @@ block0(v0: f32):
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   feq.s a0, fa0, fa0
-;   beqz a0, 0x44
+;   beqz a0, 0x40
 ;   auipc t6, 0
-;   addi t6, t6, 0x10
-;   lw t6, 0(t6)
+;   lw t6, 0xc(t6)
 ;   j 8
 ;   .byte 0x00, 0x00, 0x80, 0xbf
 ;   fmv.w.x ft3, t6
@@ -854,10 +847,9 @@ block0(v0: f32):
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   feq.s a0, fa0, fa0
-;   beqz a0, 0x44
+;   beqz a0, 0x40
 ;   auipc t6, 0
-;   addi t6, t6, 0x10
-;   lw t6, 0(t6)
+;   lw t6, 0xc(t6)
 ;   j 8
 ;   .byte 0x01, 0x00, 0x00, 0xdf
 ;   fmv.w.x ft3, t6
@@ -888,10 +880,9 @@ block0(v0: f64):
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   feq.d a0, fa0, fa0
-;   beqz a0, 0x5c
+;   beqz a0, 0x54
 ;   auipc t6, 0
-;   addi t6, t6, 0x10
-;   ld t6, 0(t6)
+;   ld t6, 0xc(t6)
 ;   j 0xc
 ;   .byte 0x00, 0x00, 0x00, 0x00
 ;   .byte 0x00, 0x00, 0xf0, 0xbf
@@ -900,8 +891,7 @@ block0(v0: f64):
 ;   beqz a0, 8
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_ovf
 ;   auipc t6, 0
-;   addi t6, t6, 0x10
-;   ld t6, 0(t6)
+;   ld t6, 0xc(t6)
 ;   j 0xc
 ;   .byte 0x00, 0x00, 0x00, 0x00
 ;   .byte 0x00, 0x00, 0xf0, 0x41
@@ -928,10 +918,9 @@ block0(v0: f64):
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   feq.d a0, fa0, fa0
-;   beqz a0, 0x5c
+;   beqz a0, 0x54
 ;   auipc t6, 0
-;   addi t6, t6, 0x10
-;   ld t6, 0(t6)
+;   ld t6, 0xc(t6)
 ;   j 0xc
 ;   .byte 0x00, 0x00, 0x20, 0x00
 ;   .byte 0x00, 0x00, 0xe0, 0xc1
@@ -940,8 +929,7 @@ block0(v0: f64):
 ;   beqz a0, 8
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_ovf
 ;   auipc t6, 0
-;   addi t6, t6, 0x10
-;   ld t6, 0(t6)
+;   ld t6, 0xc(t6)
 ;   j 0xc
 ;   .byte 0x00, 0x00, 0x00, 0x00
 ;   .byte 0x00, 0x00, 0xe0, 0x41
@@ -968,10 +956,9 @@ block0(v0: f64):
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   feq.d a0, fa0, fa0
-;   beqz a0, 0x5c
+;   beqz a0, 0x54
 ;   auipc t6, 0
-;   addi t6, t6, 0x10
-;   ld t6, 0(t6)
+;   ld t6, 0xc(t6)
 ;   j 0xc
 ;   .byte 0x00, 0x00, 0x00, 0x00
 ;   .byte 0x00, 0x00, 0xf0, 0xbf
@@ -980,8 +967,7 @@ block0(v0: f64):
 ;   beqz a0, 8
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_ovf
 ;   auipc t6, 0
-;   addi t6, t6, 0x10
-;   ld t6, 0(t6)
+;   ld t6, 0xc(t6)
 ;   j 0xc
 ;   .byte 0x00, 0x00, 0x00, 0x00
 ;   .byte 0x00, 0x00, 0xf0, 0x43
@@ -1008,10 +994,9 @@ block0(v0: f64):
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   feq.d a0, fa0, fa0
-;   beqz a0, 0x5c
+;   beqz a0, 0x54
 ;   auipc t6, 0
-;   addi t6, t6, 0x10
-;   ld t6, 0(t6)
+;   ld t6, 0xc(t6)
 ;   j 0xc
 ;   .byte 0x01, 0x00, 0x00, 0x00
 ;   .byte 0x00, 0x00, 0xe0, 0xc3
@@ -1020,8 +1005,7 @@ block0(v0: f64):
 ;   beqz a0, 8
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_ovf
 ;   auipc t6, 0
-;   addi t6, t6, 0x10
-;   ld t6, 0(t6)
+;   ld t6, 0xc(t6)
 ;   j 0xc
 ;   .byte 0x00, 0x00, 0x00, 0x00
 ;   .byte 0x00, 0x00, 0xe0, 0x43
diff --git a/cranelift/filetests/filetests/isa/riscv64/return-call.clif b/cranelift/filetests/filetests/isa/riscv64/return-call.clif
index f09e9bf611e7..335e3cb7532d 100644
--- a/cranelift/filetests/filetests/isa/riscv64/return-call.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/return-call.clif
@@ -103,13 +103,13 @@ block0(v0: f64):
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   auipc t6, 0
-;   addi t6, t6, 0x18
-;   ld a0, 0(t6)
+;   auipc a0, 0
+;   ld a0, 0x18(a0)
 ;   fmv.d.x ft5, a0
 ;   fadd.d ft0, ft0, ft5
 ;   ret
 ;   .byte 0x00, 0x00, 0x00, 0x00
+;   .byte 0x00, 0x00, 0x00, 0x00
 ;   .byte 0x00, 0x00, 0x30, 0x40
 
 function %call_f64(f64) -> f64 tail {
diff --git a/cranelift/filetests/filetests/isa/riscv64/simd-ceil.clif b/cranelift/filetests/filetests/isa/riscv64/simd-ceil.clif
index 3cc3b9b21a46..d9fd8fe4ca4e 100644
--- a/cranelift/filetests/filetests/isa/riscv64/simd-ceil.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/simd-ceil.clif
@@ -107,9 +107,8 @@ block0(v0: f64x2):
 ;   .byte 0x87, 0x80, 0x0f, 0x02
 ;   .byte 0x57, 0x70, 0x81, 0xcd
 ;   .byte 0x57, 0x92, 0x10, 0x2a
-;   auipc t6, 0
-;   addi t6, t6, 0x4c
-;   ld a3, 0(t6)
+;   auipc a3, 0
+;   ld a3, 0x4c(a3)
 ;   fmv.d.x fa0, a3
 ;   .byte 0x57, 0x50, 0x45, 0x6e
 ;   fsrmi t4, 3
@@ -127,5 +126,6 @@ block0(v0: f64x2):
 ;   addi sp, sp, 0x10
 ;   ret
 ;   .byte 0x00, 0x00, 0x00, 0x00
+;   .byte 0x00, 0x00, 0x00, 0x00
 ;   .byte 0x00, 0x00, 0x30, 0x43
 
diff --git a/cranelift/filetests/filetests/isa/riscv64/simd-floor.clif b/cranelift/filetests/filetests/isa/riscv64/simd-floor.clif
index 6ecdcc7c88f0..3c045f8f95f6 100644
--- a/cranelift/filetests/filetests/isa/riscv64/simd-floor.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/simd-floor.clif
@@ -107,9 +107,8 @@ block0(v0: f64x2):
 ;   .byte 0x87, 0x80, 0x0f, 0x02
 ;   .byte 0x57, 0x70, 0x81, 0xcd
 ;   .byte 0x57, 0x92, 0x10, 0x2a
-;   auipc t6, 0
-;   addi t6, t6, 0x4c
-;   ld a3, 0(t6)
+;   auipc a3, 0
+;   ld a3, 0x4c(a3)
 ;   fmv.d.x fa0, a3
 ;   .byte 0x57, 0x50, 0x45, 0x6e
 ;   fsrmi t4, 2
@@ -127,5 +126,6 @@ block0(v0: f64x2):
 ;   addi sp, sp, 0x10
 ;   ret
 ;   .byte 0x00, 0x00, 0x00, 0x00
+;   .byte 0x00, 0x00, 0x00, 0x00
 ;   .byte 0x00, 0x00, 0x30, 0x43
 
diff --git a/cranelift/filetests/filetests/isa/riscv64/simd-fmax.clif b/cranelift/filetests/filetests/isa/riscv64/simd-fmax.clif
index d3805bfb9a6e..d576a7dcd744 100644
--- a/cranelift/filetests/filetests/isa/riscv64/simd-fmax.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/simd-fmax.clif
@@ -45,9 +45,8 @@ block0(v0: f64x2, v1: f64x2):
 ;   .byte 0x57, 0x93, 0x10, 0x62
 ;   .byte 0x57, 0x94, 0x31, 0x62
 ;   .byte 0x57, 0x20, 0x64, 0x66
-;   auipc t6, 0
-;   addi t6, t6, 0x34
-;   ld t4, 0(t6)
+;   auipc t4, 0
+;   ld t4, 0x2c(t4)
 ;   .byte 0x57, 0xc7, 0x0e, 0x5e
 ;   .byte 0x57, 0x98, 0x11, 0x1a
 ;   .byte 0x57, 0x09, 0xe8, 0x5c
@@ -58,7 +57,6 @@ block0(v0: f64x2, v1: f64x2):
 ;   addi sp, sp, 0x10
 ;   ret
 ;   .byte 0x00, 0x00, 0x00, 0x00
-;   .byte 0x00, 0x00, 0x00, 0x00
 ;   .byte 0x00, 0x00, 0xf8, 0x7f
 
 function %fmax_f32x4(f32x4, f32x4) -> f32x4 {
diff --git a/cranelift/filetests/filetests/isa/riscv64/simd-fmin.clif b/cranelift/filetests/filetests/isa/riscv64/simd-fmin.clif
index 80fe5210dc69..d653dae0a22e 100644
--- a/cranelift/filetests/filetests/isa/riscv64/simd-fmin.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/simd-fmin.clif
@@ -45,9 +45,8 @@ block0(v0: f64x2, v1: f64x2):
 ;   .byte 0x57, 0x93, 0x10, 0x62
 ;   .byte 0x57, 0x94, 0x31, 0x62
 ;   .byte 0x57, 0x20, 0x64, 0x66
-;   auipc t6, 0
-;   addi t6, t6, 0x34
-;   ld t4, 0(t6)
+;   auipc t4, 0
+;   ld t4, 0x2c(t4)
 ;   .byte 0x57, 0xc7, 0x0e, 0x5e
 ;   .byte 0x57, 0x98, 0x11, 0x12
 ;   .byte 0x57, 0x09, 0xe8, 0x5c
@@ -58,7 +57,6 @@ block0(v0: f64x2, v1: f64x2):
 ;   addi sp, sp, 0x10
 ;   ret
 ;   .byte 0x00, 0x00, 0x00, 0x00
-;   .byte 0x00, 0x00, 0x00, 0x00
 ;   .byte 0x00, 0x00, 0xf8, 0x7f
 
 function %fmin_f32x4(f32x4, f32x4) -> f32x4 {
diff --git a/cranelift/filetests/filetests/isa/riscv64/simd-iadd_pairwise.clif b/cranelift/filetests/filetests/isa/riscv64/simd-iadd_pairwise.clif
index 02ea0cb5766d..c99beb5fa68f 100644
--- a/cranelift/filetests/filetests/isa/riscv64/simd-iadd_pairwise.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/simd-iadd_pairwise.clif
@@ -45,18 +45,16 @@ block0(v0: i8x16, v1: i8x16):
 ;   .byte 0x87, 0x80, 0x0f, 0x02
 ;   addi t6, s0, 0x20
 ;   .byte 0x87, 0x81, 0x0f, 0x02
-;   auipc t6, 0
-;   addi t6, t6, 0x64
-;   ld a3, 0(t6)
+;   auipc a3, 0
+;   ld a3, 0x5c(a3)
 ;   .byte 0x57, 0x70, 0x81, 0xcd
 ;   .byte 0x57, 0xe4, 0x06, 0x42
 ;   .byte 0x57, 0x70, 0x08, 0xcc
 ;   .byte 0x57, 0x26, 0x14, 0x5e
 ;   .byte 0xd7, 0x26, 0x34, 0x5e
 ;   .byte 0x57, 0x36, 0xd4, 0x3a
-;   auipc t6, 0
-;   addi t6, t6, 0x48
-;   ld a1, 0(t6)
+;   auipc a1, 0
+;   ld a1, 0x44(a1)
 ;   .byte 0x57, 0x70, 0x81, 0xcd
 ;   .byte 0x57, 0xe9, 0x05, 0x42
 ;   .byte 0x57, 0x70, 0x08, 0xcc
@@ -118,18 +116,16 @@ block0(v0: i16x8, v1: i16x8):
 ;   .byte 0x87, 0x80, 0x0f, 0x02
 ;   addi t6, s0, 0x20
 ;   .byte 0x87, 0x81, 0x0f, 0x02
-;   auipc t6, 0
-;   addi t6, t6, 0x64
-;   ld a3, 0(t6)
+;   auipc a3, 0
+;   ld a3, 0x5c(a3)
 ;   .byte 0x57, 0x70, 0x81, 0xcd
 ;   .byte 0x57, 0xe4, 0x06, 0x42
 ;   .byte 0x57, 0x70, 0x84, 0xcc
 ;   .byte 0x57, 0x26, 0x14, 0x5e
 ;   .byte 0xd7, 0x26, 0x34, 0x5e
 ;   .byte 0x57, 0x36, 0xd2, 0x3a
-;   auipc t6, 0
-;   addi t6, t6, 0x48
-;   ld a1, 0(t6)
+;   auipc a1, 0
+;   ld a1, 0x44(a1)
 ;   .byte 0x57, 0x70, 0x81, 0xcd
 ;   .byte 0x57, 0xe9, 0x05, 0x42
 ;   .byte 0x57, 0x70, 0x84, 0xcc
@@ -191,18 +187,16 @@ block0(v0: i32x4, v1: i32x4):
 ;   .byte 0x87, 0x80, 0x0f, 0x02
 ;   addi t6, s0, 0x20
 ;   .byte 0x87, 0x81, 0x0f, 0x02
-;   auipc t6, 0
-;   addi t6, t6, 0x64
-;   ld a3, 0(t6)
+;   auipc a3, 0
+;   ld a3, 0x5c(a3)
 ;   .byte 0x57, 0x70, 0x81, 0xcd
 ;   .byte 0x57, 0xe4, 0x06, 0x42
 ;   .byte 0x57, 0x70, 0x02, 0xcd
 ;   .byte 0x57, 0x26, 0x14, 0x5e
 ;   .byte 0xd7, 0x26, 0x34, 0x5e
 ;   .byte 0x57, 0x36, 0xd1, 0x3a
-;   auipc t6, 0
-;   addi t6, t6, 0x48
-;   ld a1, 0(t6)
+;   auipc a1, 0
+;   ld a1, 0x44(a1)
 ;   .byte 0x57, 0x70, 0x81, 0xcd
 ;   .byte 0x57, 0xe9, 0x05, 0x42
 ;   .byte 0x57, 0x70, 0x02, 0xcd
diff --git a/cranelift/filetests/filetests/isa/riscv64/simd-nearest.clif b/cranelift/filetests/filetests/isa/riscv64/simd-nearest.clif
index 359fdf6a1c90..cf2e1892d13a 100644
--- a/cranelift/filetests/filetests/isa/riscv64/simd-nearest.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/simd-nearest.clif
@@ -107,9 +107,8 @@ block0(v0: f64x2):
 ;   .byte 0x87, 0x80, 0x0f, 0x02
 ;   .byte 0x57, 0x70, 0x81, 0xcd
 ;   .byte 0x57, 0x92, 0x10, 0x2a
-;   auipc t6, 0
-;   addi t6, t6, 0x4c
-;   ld a3, 0(t6)
+;   auipc a3, 0
+;   ld a3, 0x4c(a3)
 ;   fmv.d.x fa0, a3
 ;   .byte 0x57, 0x50, 0x45, 0x6e
 ;   fsrmi t4, 0
@@ -127,5 +126,6 @@ block0(v0: f64x2):
 ;   addi sp, sp, 0x10
 ;   ret
 ;   .byte 0x00, 0x00, 0x00, 0x00
+;   .byte 0x00, 0x00, 0x00, 0x00
 ;   .byte 0x00, 0x00, 0x30, 0x43
 
diff --git a/cranelift/filetests/filetests/isa/riscv64/simd-popcnt.clif b/cranelift/filetests/filetests/isa/riscv64/simd-popcnt.clif
index 40246e80ea1f..e81fe132e19f 100644
--- a/cranelift/filetests/filetests/isa/riscv64/simd-popcnt.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/simd-popcnt.clif
@@ -273,29 +273,25 @@ block0(v0: i64x2):
 ;   .byte 0x57, 0x70, 0x08, 0xcc
 ;   addi t6, s0, 0x10
 ;   .byte 0x87, 0x80, 0x0f, 0x02
-;   auipc t6, 0
-;   addi t6, t6, 0x84
-;   ld a1, 0(t6)
+;   auipc a1, 0
+;   ld a1, 0x74(a1)
 ;   .byte 0x57, 0x70, 0x81, 0xcd
 ;   .byte 0x57, 0xb3, 0x10, 0xa2
 ;   .byte 0x57, 0xc4, 0x65, 0x26
 ;   .byte 0x57, 0x05, 0x14, 0x0a
-;   auipc t6, 0
-;   addi t6, t6, 0x70
-;   ld t4, 0(t6)
+;   auipc t4, 0
+;   ld t4, 0x64(t4)
 ;   .byte 0x57, 0x37, 0xa1, 0xa2
 ;   .byte 0x57, 0xc8, 0xee, 0x26
 ;   .byte 0x57, 0xc9, 0xae, 0x26
 ;   .byte 0x57, 0x0a, 0x28, 0x03
-;   auipc t6, 0
-;   addi t6, t6, 0x5c
-;   ld a6, 0(t6)
+;   auipc a6, 0
+;   ld a6, 0x54(a6)
 ;   .byte 0x57, 0x3c, 0x42, 0xa3
 ;   .byte 0x57, 0x0d, 0x4c, 0x03
 ;   .byte 0x57, 0x4e, 0xa8, 0x27
-;   auipc t6, 0
-;   addi t6, t6, 0x4c
-;   ld a1, 0(t6)
+;   auipc a1, 0
+;   ld a1, 0x48(a1)
 ;   .byte 0x57, 0xe0, 0xc5, 0x97
 ;   addi a5, zero, 0x38
 ;   .byte 0x57, 0xc2, 0x07, 0xa2
diff --git a/cranelift/filetests/filetests/isa/riscv64/simd-trunc.clif b/cranelift/filetests/filetests/isa/riscv64/simd-trunc.clif
index 515643924a38..2a9346870bf7 100644
--- a/cranelift/filetests/filetests/isa/riscv64/simd-trunc.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/simd-trunc.clif
@@ -101,9 +101,8 @@ block0(v0: f64x2):
 ;   .byte 0x87, 0x80, 0x0f, 0x02
 ;   .byte 0x57, 0x70, 0x81, 0xcd
 ;   .byte 0x57, 0x92, 0x10, 0x2a
-;   auipc t6, 0
-;   addi t6, t6, 0x44
-;   ld a3, 0(t6)
+;   auipc a3, 0
+;   ld a3, 0x44(a3)
 ;   fmv.d.x fa0, a3
 ;   .byte 0x57, 0x50, 0x45, 0x6e
 ;   .byte 0x57, 0x96, 0x13, 0x4a
@@ -119,5 +118,6 @@ block0(v0: f64x2):
 ;   addi sp, sp, 0x10
 ;   ret
 ;   .byte 0x00, 0x00, 0x00, 0x00
+;   .byte 0x00, 0x00, 0x00, 0x00
 ;   .byte 0x00, 0x00, 0x30, 0x43