diff --git a/vta/hardware/chisel/src/main/scala/core/Core.scala b/vta/hardware/chisel/src/main/scala/core/Core.scala
index 6c29a88548a7..e63a1123b671 100644
--- a/vta/hardware/chisel/src/main/scala/core/Core.scala
+++ b/vta/hardware/chisel/src/main/scala/core/Core.scala
@@ -40,6 +40,9 @@ case class CoreParams (
   outMemDepth: Int = 512,
   instQueueEntries: Int = 32
 )
+{
+  require (uopBits % 8 == 0, s"\n\n[VTA] [CoreParams] uopBits must be byte aligned\n\n")
+}
 
 case object CoreKey extends Field[CoreParams]
 
diff --git a/vta/hardware/chisel/src/main/scala/core/LoadUop.scala b/vta/hardware/chisel/src/main/scala/core/LoadUop.scala
index 5a9c66f06e49..ab8275b6731c 100644
--- a/vta/hardware/chisel/src/main/scala/core/LoadUop.scala
+++ b/vta/hardware/chisel/src/main/scala/core/LoadUop.scala
@@ -69,6 +69,7 @@ class LoadUop(debug: Boolean = false)(implicit p: Parameters) extends Module {
   })
   val numUop = 2 // store two uops per sram word
   val uopBits = p(CoreKey).uopBits
+  val uopBytes = uopBits / 8
   val uopDepth = p(CoreKey).uopMemDepth / numUop
 
   val dec = io.inst.asTypeOf(new MemDecode)
@@ -129,7 +130,7 @@ class LoadUop(debug: Boolean = false)(implicit p: Parameters) extends Module {
     when (offsetIsEven) {
       raddr := io.baddr + dec.dram_offset
     } .otherwise {
-      raddr := io.baddr + dec.dram_offset - 4.U
+      raddr := io.baddr + dec.dram_offset - uopBytes.U
     }
   } .elsewhen (state === sReadData && xcnt === xlen && xrem =/= 0.U) {
     raddr := raddr + xmax_bytes