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parport_ip32.c.STRIPPED
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parport_ip32.c.STRIPPED
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/* Low-level parallel port routines for built-in port on SGI IP32
*
* Author: Arnaud Giersch <[email protected]>
*
* Based on parport_pc.c by
* Phil Blundell, Tim Waugh, Jose Renau, David Campbell,
* Andrea Arcangeli, et al.
*
* Thanks to Ilya A. Volynets-Evenbakh for his help.
*
* Copyright (C) 2005-2007 Arnaud Giersch.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
* Software Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc., 59
* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
/* Current status:
*
* Basic SPP and PS2 modes are supported.
* Support for parallel port IRQ is present.
* Hardware SPP (a.k.a. compatibility), EPP, and ECP modes are
* supported.
* SPP/ECP FIFO can be driven in PIO or DMA mode. PIO mode can work with
* or without interrupt support.
*
* Hardware ECP mode is not fully implemented (ecp_read_data and
* ecp_write_addr are actually missing).
*
* To do:
*
* Fully implement ECP mode.
* EPP and ECP mode need to be tested. I currently do not own any
* peripheral supporting these extended mode, and cannot test them.
* Find and use some io{read,write} equivalent for {read,write}q?
*/
/* The built-in parallel port on the SGI 02 workstation (a.k.a. IP32) is an
* IEEE 1284 parallel port driven by a Texas Instrument TL16PIR552PH chip[1].
* This chip supports SPP, bidirectional, EPP and ECP modes. It has a 16 byte
* FIFO buffer and supports DMA transfers.
*
* [1] http://focus.ti.com/docs/prod/folders/print/tl16pir552.html
*
* Theoretically, we could simply use the parport_pc module. It is however
* not so simple. The parport_pc code assumes that the parallel port
* registers are port-mapped. On the O2, they are memory-mapped.
* Furthermore, each register is replicated on 256 consecutive addresses (as
* it is for the built-in serial ports on the same chip).
*/
/*--- Some configuration defines ---------------------------------------*/
/* DEBUG_PARPORT_IP32
* 0 disable debug
* 1 standard level: pr_debug1 is enabled
* 2 (reserved)
* >=3 verbose level: pr_debug is enabled
*/
#if !defined(DEBUG_PARPORT_IP32)
# define DEBUG_PARPORT_IP32 0 /* 0 (disabled) for production */
#endif
/*----------------------------------------------------------------------*/
/* Setup DEBUG macros. This is done before any includes, just in case we
* activate pr_debug() with DEBUG_PARPORT_IP32 >= 3.
*/
#if DEBUG_PARPORT_IP32 == 1
# warning DEBUG_PARPORT_IP32 == 1
#elif DEBUG_PARPORT_IP32 == 2
# warning DEBUG_PARPORT_IP32 == 2
#elif DEBUG_PARPORT_IP32 >= 3
# warning DEBUG_PARPORT_IP32 >= 3
# if !defined(DEBUG)
# define DEBUG /* enable pr_debug() in kernel.h */
# endif
#endif
#include <linux/completion.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/jiffies.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/parport.h>
#include <linux/sched.h>
#include <linux/spinlock.h>
#include <linux/stddef.h>
#include <linux/types.h>
#include <asm/io.h>
#include <asm/ip32/ip32_ints.h>
#include <asm/ip32/mace.h>
/*--- Global variables -------------------------------------------------*/
/* Verbose probing on by default for debugging. */
#if DEBUG_PARPORT_IP32 >= 1
# define DEFAULT_VERBOSE_PROBING 1
#else
# define DEFAULT_VERBOSE_PROBING 0
#endif
/* Default prefix for printk */
#define PPIP32 "parport_ip32: "
/*
* These are the module parameters:
* @verbose_probing: log chit-chat during initialization
*/
static int verbose_probing = DEFAULT_VERBOSE_PROBING;
/* We do not support more than one port. */
static struct parport *this_port = NULL;
/* Timing constants for FIFO modes. */
#define FIFO_NFAULT_TIMEOUT 100 /* milliseconds */
#define FIFO_POLLING_INTERVAL 50 /* microseconds */
/*--- I/O register definitions -----------------------------------------*/
/**
* struct parport_ip32_regs - virtual addresses of parallel port registers
* @data: Data Register
* @dsr: Device Status Register
* @dcr: Device Control Register
* @eppAddr: EPP Address Register
* @eppData0: EPP Data Register 0
* @eppData1: EPP Data Register 1
* @eppData2: EPP Data Register 2
* @eppData3: EPP Data Register 3
* @ecpAFifo: ECP Address FIFO
* @fifo: General FIFO register. The same address is used for:
* - cFifo, the Parallel Port DATA FIFO
* - ecpDFifo, the ECP Data FIFO
* - tFifo, the ECP Test FIFO
* @cnfgA: Configuration Register A
* @cnfgB: Configuration Register B
* @ecr: Extended Control Register
*/
struct parport_ip32_regs {
void __iomem *data;
void __iomem *dsr;
void __iomem *dcr;
void __iomem *eppAddr;
void __iomem *eppData0;
void __iomem *eppData1;
void __iomem *eppData2;
void __iomem *eppData3;
void __iomem *ecpAFifo;
void __iomem *fifo;
void __iomem *cnfgA;
void __iomem *cnfgB;
void __iomem *ecr;
};
/* Device Status Register */
#define DSR_nBUSY (1U << 7) /* PARPORT_STATUS_BUSY */
#define DSR_nACK (1U << 6) /* PARPORT_STATUS_ACK */
#define DSR_PERROR (1U << 5) /* PARPORT_STATUS_PAPEROUT */
#define DSR_SELECT (1U << 4) /* PARPORT_STATUS_SELECT */
#define DSR_nFAULT (1U << 3) /* PARPORT_STATUS_ERROR */
#define DSR_nPRINT (1U << 2) /* specific to TL16PIR552 */
/* #define DSR_reserved (1U << 1) */
#define DSR_TIMEOUT (1U << 0) /* EPP timeout */
/* Device Control Register */
/* #define DCR_reserved (1U << 7) | (1U << 6) */
#define DCR_DIR (1U << 5) /* direction */
#define DCR_IRQ (1U << 4) /* interrupt on nAck */
#define DCR_SELECT (1U << 3) /* PARPORT_CONTROL_SELECT */
#define DCR_nINIT (1U << 2) /* PARPORT_CONTROL_INIT */
#define DCR_AUTOFD (1U << 1) /* PARPORT_CONTROL_AUTOFD */
#define DCR_STROBE (1U << 0) /* PARPORT_CONTROL_STROBE */
/* ECP Configuration Register A */
#define CNFGA_IRQ (1U << 7)
#define CNFGA_ID_MASK ((1U << 6) | (1U << 5) | (1U << 4))
#define CNFGA_ID_SHIFT 4
#define CNFGA_ID_16 (00U << CNFGA_ID_SHIFT)
#define CNFGA_ID_8 (01U << CNFGA_ID_SHIFT)
#define CNFGA_ID_32 (02U << CNFGA_ID_SHIFT)
/* #define CNFGA_reserved (1U << 3) */
#define CNFGA_nBYTEINTRANS (1U << 2)
#define CNFGA_PWORDLEFT ((1U << 1) | (1U << 0))
/* ECP Configuration Register B */
#define CNFGB_COMPRESS (1U << 7)
#define CNFGB_INTRVAL (1U << 6)
#define CNFGB_IRQ_MASK ((1U << 5) | (1U << 4) | (1U << 3))
#define CNFGB_IRQ_SHIFT 3
#define CNFGB_DMA_MASK ((1U << 2) | (1U << 1) | (1U << 0))
#define CNFGB_DMA_SHIFT 0
/* Extended Control Register */
#define ECR_MODE_MASK ((1U << 7) | (1U << 6) | (1U << 5))
#define ECR_MODE_SHIFT 5
#define ECR_MODE_SPP (00U << ECR_MODE_SHIFT)
#define ECR_MODE_PS2 (01U << ECR_MODE_SHIFT)
#define ECR_MODE_PPF (02U << ECR_MODE_SHIFT)
#define ECR_MODE_ECP (03U << ECR_MODE_SHIFT)
#define ECR_MODE_EPP (04U << ECR_MODE_SHIFT)
/* #define ECR_MODE_reserved (05U << ECR_MODE_SHIFT) */
#define ECR_MODE_TST (06U << ECR_MODE_SHIFT)
#define ECR_MODE_CFG (07U << ECR_MODE_SHIFT)
#define ECR_nERRINTR (1U << 4)
#define ECR_DMAEN (1U << 3)
#define ECR_SERVINTR (1U << 2)
#define ECR_F_FULL (1U << 1)
#define ECR_F_EMPTY (1U << 0)
/*--- Private data -----------------------------------------------------*/
/**
* enum parport_ip32_irq_mode - operation mode of interrupt handler
* @PARPORT_IP32_IRQ_FWD: forward interrupt to the upper parport layer
* @PARPORT_IP32_IRQ_HERE: interrupt is handled locally
*/
enum parport_ip32_irq_mode { PARPORT_IP32_IRQ_FWD, PARPORT_IP32_IRQ_HERE };
/**
* struct parport_ip32_private - private stuff for &struct parport
* @regs: register addresses
* @dcr_cache: cached contents of DCR
* @dcr_writable: bit mask of writable DCR bits
* @pword: number of bytes per PWord
* @fifo_depth: number of PWords that FIFO will hold
* @readIntrThreshold: minimum number of PWords we can read
* if we get an interrupt
* @writeIntrThreshold: minimum number of PWords we can write
* if we get an interrupt
* @irq_mode: operation mode of interrupt handler for this port
* @irq_complete: mutex used to wait for an interrupt to occur
*/
struct parport_ip32_private {
struct parport_ip32_regs regs;
unsigned int dcr_cache;
unsigned int dcr_writable;
unsigned int pword;
unsigned int fifo_depth;
unsigned int readIntrThreshold;
unsigned int writeIntrThreshold;
enum parport_ip32_irq_mode irq_mode;
struct completion irq_complete;
};
/*--- Debug code -------------------------------------------------------*/
/*
* pr_debug1 - print debug messages
*
* This is like pr_debug(), but is defined for %DEBUG_PARPORT_IP32 >= 1
*/
#if DEBUG_PARPORT_IP32 >= 1
# define pr_debug1(...) printk(KERN_DEBUG __VA_ARGS__)
#else /* DEBUG_PARPORT_IP32 < 1 */
# define pr_debug1(...) do { } while (0)
#endif
/*
* pr_trace, pr_trace1 - trace function calls
* @p: pointer to &struct parport
* @fmt: printk format string
* @...: parameters for format string
*
* Macros used to trace function calls. The given string is formatted after
* function name. pr_trace() uses pr_debug(), and pr_trace1() uses
* pr_debug1(). __pr_trace() is the low-level macro and is not to be used
* directly.
*/
#define __pr_trace(pr, p, fmt, ...) \
pr("%s: %s" fmt "\n", \
({ const struct parport *__p = (p); \
__p ? __p->name : "parport_ip32"; }), \
__func__ , ##__VA_ARGS__)
#define pr_trace(p, fmt, ...) __pr_trace(pr_debug, p, fmt , ##__VA_ARGS__)
#define pr_trace1(p, fmt, ...) __pr_trace(pr_debug1, p, fmt , ##__VA_ARGS__)
/*
* __pr_probe, pr_probe - print message if @verbose_probing is true
* @p: pointer to &struct parport
* @fmt: printk format string
* @...: parameters for format string
*
* For new lines, use pr_probe(). Use __pr_probe() for continued lines.
*/
#define __pr_probe(...) \
do { if (verbose_probing) printk(__VA_ARGS__); } while (0)
#define pr_probe(p, fmt, ...) \
__pr_probe(KERN_INFO PPIP32 "0x%lx: " fmt, (p)->base , ##__VA_ARGS__)
/*
* CHECK_EXTRA_BITS - track and log extra bits
* @p: pointer to &struct parport
* @b: byte to inspect
* @m: bit mask of authorized bits
*
* This is used to track and log extra bits that should not be there in
* parport_ip32_write_control() and parport_ip32_frob_control(). It is only
* defined if %DEBUG_PARPORT_IP32 >= 1.
*/
#if DEBUG_PARPORT_IP32 >= 1
#define CHECK_EXTRA_BITS(p, b, m) \
do { \
unsigned int __b = (b), __m = (m); \
if (__b & ~__m) \
pr_debug1(PPIP32 "%s: extra bits in %s(%s): " \
"0x%02x/0x%02x\n", \
(p)->name, __func__, #b, __b, __m); \
} while (0)
#else /* DEBUG_PARPORT_IP32 < 1 */
#define CHECK_EXTRA_BITS(...) do { } while (0)
#endif
/*--- IP32 parallel port DMA operations --------------------------------*/
/**
* struct parport_ip32_dma_data - private data needed for DMA operation
* @dir: DMA direction (from or to device)
* @buf: buffer physical address
* @len: buffer length
* @next: address of next bytes to DMA transfer
* @left: number of bytes remaining
* @ctx: next context to write (0: context_a; 1: context_b)
* @irq_on: are the DMA IRQs currently enabled?
* @lock: spinlock to protect access to the structure
*/
struct parport_ip32_dma_data {
enum dma_data_direction dir;
dma_addr_t buf;
dma_addr_t next;
size_t len;
size_t left;
unsigned int ctx;
unsigned int irq_on;
spinlock_t lock;
};
static struct parport_ip32_dma_data parport_ip32_dma;
/**
* parport_ip32_dma_setup_context - setup next DMA context
* @limit: maximum data size for the context
*
* The alignment constraints must be verified in caller function, and the
* parameter @limit must be set accordingly.
*/
static void parport_ip32_dma_setup_context(unsigned int limit)
{
unsigned long flags;
spin_lock_irqsave(&parport_ip32_dma.lock, flags);
if (parport_ip32_dma.left > 0) {
/* Note: ctxreg is "volatile" here only because
* mace->perif.ctrl.parport.context_a and context_b are
* "volatile". */
volatile u64 __iomem *ctxreg = (parport_ip32_dma.ctx == 0) ?
&mace->perif.ctrl.parport.context_a :
&mace->perif.ctrl.parport.context_b;
u64 count;
u64 ctxval;
if (parport_ip32_dma.left <= limit) {
count = parport_ip32_dma.left;
ctxval = MACEPAR_CONTEXT_LASTFLAG;
} else {
count = limit;
ctxval = 0;
}
pr_trace(NULL,
"(%u): 0x%04x:0x%04x, %u -> %u%s",
limit,
(unsigned int)parport_ip32_dma.buf,
(unsigned int)parport_ip32_dma.next,
(unsigned int)count,
parport_ip32_dma.ctx, ctxval ? "*" : "");
ctxval |= parport_ip32_dma.next &
MACEPAR_CONTEXT_BASEADDR_MASK;
ctxval |= ((count - 1) << MACEPAR_CONTEXT_DATALEN_SHIFT) &
MACEPAR_CONTEXT_DATALEN_MASK;
writeq(ctxval, ctxreg);
parport_ip32_dma.next += count;
parport_ip32_dma.left -= count;
parport_ip32_dma.ctx ^= 1U;
}
/* If there is nothing more to send, disable IRQs to avoid to
* face an IRQ storm which can lock the machine. Disable them
* only once. */
if (parport_ip32_dma.left == 0 && parport_ip32_dma.irq_on) {
pr_debug(PPIP32 "IRQ off (ctx)\n");
disable_irq_nosync(MACEISA_PAR_CTXA_IRQ);
disable_irq_nosync(MACEISA_PAR_CTXB_IRQ);
parport_ip32_dma.irq_on = 0;
}
spin_unlock_irqrestore(&parport_ip32_dma.lock, flags);
}
/**
* parport_ip32_dma_interrupt - DMA interrupt handler
* @irq: interrupt number
* @dev_id: unused
*/
static irqreturn_t parport_ip32_dma_interrupt(int irq, void *dev_id)
{
if (parport_ip32_dma.left)
pr_trace(NULL, "(%d): ctx=%d", irq, parport_ip32_dma.ctx);
parport_ip32_dma_setup_context(MACEPAR_CONTEXT_DATA_BOUND);
return IRQ_HANDLED;
}
/**
* parport_ip32_dma_start - begins a DMA transfer
* @dir: DMA direction: DMA_TO_DEVICE or DMA_FROM_DEVICE
* @addr: pointer to data buffer
* @count: buffer size
*
* Calls to parport_ip32_dma_start() and parport_ip32_dma_stop() must be
* correctly balanced.
*/
static int parport_ip32_dma_start(enum dma_data_direction dir,
void *addr, size_t count)
{
unsigned int limit;
u64 ctrl;
pr_trace(NULL, "(%d, %lu)", dir, (unsigned long)count);
/* FIXME - add support for DMA_FROM_DEVICE. In this case, buffer must
* be 64 bytes aligned. */
BUG_ON(dir != DMA_TO_DEVICE);
/* Reset DMA controller */
ctrl = MACEPAR_CTLSTAT_RESET;
writeq(ctrl, &mace->perif.ctrl.parport.cntlstat);
/* DMA IRQs should normally be enabled */
if (!parport_ip32_dma.irq_on) {
WARN_ON(1);
enable_irq(MACEISA_PAR_CTXA_IRQ);
enable_irq(MACEISA_PAR_CTXB_IRQ);
parport_ip32_dma.irq_on = 1;
}
/* Prepare DMA pointers */
parport_ip32_dma.dir = dir;
parport_ip32_dma.buf = dma_map_single(NULL, addr, count, dir);
parport_ip32_dma.len = count;
parport_ip32_dma.next = parport_ip32_dma.buf;
parport_ip32_dma.left = parport_ip32_dma.len;
parport_ip32_dma.ctx = 0;
/* Setup DMA direction and first two contexts */
ctrl = (dir == DMA_TO_DEVICE) ? 0 : MACEPAR_CTLSTAT_DIRECTION;
writeq(ctrl, &mace->perif.ctrl.parport.cntlstat);
/* Single transfer should not cross a 4K page boundary */
limit = MACEPAR_CONTEXT_DATA_BOUND -
(parport_ip32_dma.next & (MACEPAR_CONTEXT_DATA_BOUND - 1));
parport_ip32_dma_setup_context(limit);
parport_ip32_dma_setup_context(MACEPAR_CONTEXT_DATA_BOUND);
/* Real start of DMA transfer */
ctrl |= MACEPAR_CTLSTAT_ENABLE;
writeq(ctrl, &mace->perif.ctrl.parport.cntlstat);
return 0;
}
/**
* parport_ip32_dma_stop - ends a running DMA transfer
*
* Calls to parport_ip32_dma_start() and parport_ip32_dma_stop() must be
* correctly balanced.
*/
static void parport_ip32_dma_stop(void)
{
u64 ctx_a;
u64 ctx_b;
u64 ctrl;
u64 diag;
size_t res[2]; /* {[0] = res_a, [1] = res_b} */
pr_trace(NULL, "()");
/* Disable IRQs */
spin_lock_irq(&parport_ip32_dma.lock);
if (parport_ip32_dma.irq_on) {
pr_debug(PPIP32 "IRQ off (stop)\n");
disable_irq_nosync(MACEISA_PAR_CTXA_IRQ);
disable_irq_nosync(MACEISA_PAR_CTXB_IRQ);
parport_ip32_dma.irq_on = 0;
}
spin_unlock_irq(&parport_ip32_dma.lock);
/* Force IRQ synchronization, even if the IRQs were disabled
* elsewhere. */
synchronize_irq(MACEISA_PAR_CTXA_IRQ);
synchronize_irq(MACEISA_PAR_CTXB_IRQ);
/* Stop DMA transfer */
ctrl = readq(&mace->perif.ctrl.parport.cntlstat);
ctrl &= ~MACEPAR_CTLSTAT_ENABLE;
writeq(ctrl, &mace->perif.ctrl.parport.cntlstat);
/* Adjust residue (parport_ip32_dma.left) */
ctx_a = readq(&mace->perif.ctrl.parport.context_a);
ctx_b = readq(&mace->perif.ctrl.parport.context_b);
ctrl = readq(&mace->perif.ctrl.parport.cntlstat);
diag = readq(&mace->perif.ctrl.parport.diagnostic);
res[0] = (ctrl & MACEPAR_CTLSTAT_CTXA_VALID) ?
1 + ((ctx_a & MACEPAR_CONTEXT_DATALEN_MASK) >>
MACEPAR_CONTEXT_DATALEN_SHIFT) :
0;
res[1] = (ctrl & MACEPAR_CTLSTAT_CTXB_VALID) ?
1 + ((ctx_b & MACEPAR_CONTEXT_DATALEN_MASK) >>
MACEPAR_CONTEXT_DATALEN_SHIFT) :
0;
if (diag & MACEPAR_DIAG_DMACTIVE)
res[(diag & MACEPAR_DIAG_CTXINUSE) != 0] =
1 + ((diag & MACEPAR_DIAG_CTRMASK) >>
MACEPAR_DIAG_CTRSHIFT);
parport_ip32_dma.left += res[0] + res[1];
/* Reset DMA controller, and re-enable IRQs */
ctrl = MACEPAR_CTLSTAT_RESET;
writeq(ctrl, &mace->perif.ctrl.parport.cntlstat);
pr_debug(PPIP32 "IRQ on (stop)\n");
enable_irq(MACEISA_PAR_CTXA_IRQ);
enable_irq(MACEISA_PAR_CTXB_IRQ);
parport_ip32_dma.irq_on = 1;
dma_unmap_single(NULL, parport_ip32_dma.buf, parport_ip32_dma.len,
parport_ip32_dma.dir);
}
/**
* parport_ip32_dma_get_residue - get residue from last DMA transfer
*
* Returns the number of bytes remaining from last DMA transfer.
*/
static size_t parport_ip32_dma_get_residue(void)
{
return parport_ip32_dma.left;
}
/**
* parport_ip32_dma_register - initialize DMA engine
*
* Returns zero for success.
*/
static int parport_ip32_dma_register(void)
{
int err;
spin_lock_init(&parport_ip32_dma.lock);
parport_ip32_dma.irq_on = 1;
/* Reset DMA controller */
writeq(MACEPAR_CTLSTAT_RESET, &mace->perif.ctrl.parport.cntlstat);
/* Request IRQs */
err = request_irq(MACEISA_PAR_CTXA_IRQ, parport_ip32_dma_interrupt,
0, "parport_ip32", NULL);
if (err)
goto fail_a;
err = request_irq(MACEISA_PAR_CTXB_IRQ, parport_ip32_dma_interrupt,
0, "parport_ip32", NULL);
if (err)
goto fail_b;
return 0;
fail_b:
free_irq(MACEISA_PAR_CTXA_IRQ, NULL);
fail_a:
return err;
}
/**
* parport_ip32_dma_unregister - release and free resources for DMA engine
*/
static void parport_ip32_dma_unregister(void)
{
free_irq(MACEISA_PAR_CTXB_IRQ, NULL);
free_irq(MACEISA_PAR_CTXA_IRQ, NULL);
}
/*--- Interrupt handlers and associates --------------------------------*/
/**
* parport_ip32_wakeup - wakes up code waiting for an interrupt
* @p: pointer to &struct parport
*/
static void parport_ip32_wakeup(struct parport *p)
{
struct parport_ip32_private * const priv = p->physport->private_data;
complete(&priv->irq_complete);
}
/**
* parport_ip32_interrupt - interrupt handler
* @irq: interrupt number
* @dev_id: pointer to &struct parport
*
* Caught interrupts are forwarded to the upper parport layer if IRQ_mode is
* %PARPORT_IP32_IRQ_FWD.
*/
static irqreturn_t parport_ip32_interrupt(int irq, void *dev_id)
{
struct parport * const p = dev_id;
struct parport_ip32_private * const priv = p->physport->private_data;
enum parport_ip32_irq_mode irq_mode = priv->irq_mode;
switch (irq_mode) {
case PARPORT_IP32_IRQ_FWD:
parport_generic_irq(irq, p);
break;
case PARPORT_IP32_IRQ_HERE:
parport_ip32_wakeup(p);
break;
}
return IRQ_HANDLED;
}
/*--- Some utility function to manipulate ECR register -----------------*/
/**
* parport_ip32_read_econtrol - read contents of the ECR register
* @p: pointer to &struct parport
*/
static unsigned int parport_ip32_read_econtrol(struct parport *p)
{
struct parport_ip32_private * const priv = p->physport->private_data;
return ioread8(priv->regs.ecr);
}
/**
* parport_ip32_write_econtrol - write new contents to the ECR register
* @p: pointer to &struct parport
* @c: new value to write
*/
static void parport_ip32_write_econtrol(struct parport *p,
unsigned int c)
{
struct parport_ip32_private * const priv = p->physport->private_data;
iowrite8(c, priv->regs.ecr);
}
/**
* parport_ip32_frob_econtrol - change bits from the ECR register
* @p: pointer to &struct parport
* @mask: bit mask of bits to change
* @val: new value for changed bits
*
* Read from the ECR, mask out the bits in @mask, exclusive-or with the bits
* in @val, and write the result to the ECR.
*/
static void parport_ip32_frob_econtrol(struct parport *p,
unsigned int mask,
unsigned int val)
{
unsigned int c;
c = (parport_ip32_read_econtrol(p) & ~mask) ^ val;
parport_ip32_write_econtrol(p, c);
}
/**
* parport_ip32_set_mode - change mode of ECP port
* @p: pointer to &struct parport
* @mode: new mode to write in ECR
*
* ECR is reset in a sane state (interrupts and DMA disabled), and placed in
* mode @mode. Go through PS2 mode if needed.
*/
static void parport_ip32_set_mode(struct parport *p, unsigned int mode)
{
unsigned int omode;
mode &= ECR_MODE_MASK;
omode = parport_ip32_read_econtrol(p) & ECR_MODE_MASK;
if (!(mode == ECR_MODE_SPP || mode == ECR_MODE_PS2
|| omode == ECR_MODE_SPP || omode == ECR_MODE_PS2)) {
/* We have to go through PS2 mode */
unsigned int ecr = ECR_MODE_PS2 | ECR_nERRINTR | ECR_SERVINTR;
parport_ip32_write_econtrol(p, ecr);
}
parport_ip32_write_econtrol(p, mode | ECR_nERRINTR | ECR_SERVINTR);
}
/*--- Basic functions needed for parport -------------------------------*/
/**
* parport_ip32_read_data - return current contents of the DATA register
* @p: pointer to &struct parport
*/
static unsigned char parport_ip32_read_data(struct parport *p)
{
struct parport_ip32_private * const priv = p->physport->private_data;
return ioread8(priv->regs.data);
}
/**
* parport_ip32_write_data - set new contents for the DATA register
* @p: pointer to &struct parport
* @d: new value to write
*/
static void parport_ip32_write_data(struct parport *p, unsigned char d)
{
struct parport_ip32_private * const priv = p->physport->private_data;
iowrite8(d, priv->regs.data);
}
/**
* parport_ip32_read_status - return current contents of the DSR register
* @p: pointer to &struct parport
*/
static unsigned char parport_ip32_read_status(struct parport *p)
{
struct parport_ip32_private * const priv = p->physport->private_data;
return ioread8(priv->regs.dsr);
}
/**
* __parport_ip32_read_control - return cached contents of the DCR register
* @p: pointer to &struct parport
*/
static unsigned int __parport_ip32_read_control(struct parport *p)
{
struct parport_ip32_private * const priv = p->physport->private_data;
return priv->dcr_cache; /* use soft copy */
}
/**
* __parport_ip32_write_control - set new contents for the DCR register
* @p: pointer to &struct parport
* @c: new value to write
*/
static void __parport_ip32_write_control(struct parport *p,
unsigned int c)
{
struct parport_ip32_private * const priv = p->physport->private_data;
CHECK_EXTRA_BITS(p, c, priv->dcr_writable);
c &= priv->dcr_writable; /* only writable bits */
iowrite8(c, priv->regs.dcr);
priv->dcr_cache = c; /* update soft copy */
}
/**
* __parport_ip32_frob_control - change bits from the DCR register
* @p: pointer to &struct parport
* @mask: bit mask of bits to change
* @val: new value for changed bits
*
* This is equivalent to read from the DCR, mask out the bits in @mask,
* exclusive-or with the bits in @val, and write the result to the DCR.
* Actually, the cached contents of the DCR is used.
*/
static void __parport_ip32_frob_control(struct parport *p,
unsigned int mask,
unsigned int val)
{
unsigned int c;
c = (__parport_ip32_read_control(p) & ~mask) ^ val;
__parport_ip32_write_control(p, c);
}
/**
* parport_ip32_read_control - return cached contents of the DCR register
* @p: pointer to &struct parport
*
* The return value is masked so as to only return the value of %DCR_STROBE,
* %DCR_AUTOFD, %DCR_nINIT, and %DCR_SELECT.
*/
static unsigned char parport_ip32_read_control(struct parport *p)
{
const unsigned int rm =
DCR_STROBE | DCR_AUTOFD | DCR_nINIT | DCR_SELECT;
return __parport_ip32_read_control(p) & rm;
}
/**
* parport_ip32_write_control - set new contents for the DCR register
* @p: pointer to &struct parport
* @c: new value to write
*
* The value is masked so as to only change the value of %DCR_STROBE,
* %DCR_AUTOFD, %DCR_nINIT, and %DCR_SELECT.
*/
static void parport_ip32_write_control(struct parport *p,
unsigned char c)
{
const unsigned int wm =
DCR_STROBE | DCR_AUTOFD | DCR_nINIT | DCR_SELECT;
CHECK_EXTRA_BITS(p, c, wm);
__parport_ip32_frob_control(p, wm, c & wm);
}
/**
* parport_ip32_frob_control - change bits from the DCR register
* @p: pointer to &struct parport
* @mask: bit mask of bits to change
* @val: new value for changed bits
*
* This differs from __parport_ip32_frob_control() in that it only allows to
* change the value of %DCR_STROBE, %DCR_AUTOFD, %DCR_nINIT, and %DCR_SELECT.
*/
static unsigned char parport_ip32_frob_control(struct parport *p,
unsigned char mask,
unsigned char val)
{
const unsigned int wm =
DCR_STROBE | DCR_AUTOFD | DCR_nINIT | DCR_SELECT;
CHECK_EXTRA_BITS(p, mask, wm);
CHECK_EXTRA_BITS(p, val, wm);
__parport_ip32_frob_control(p, mask & wm, val & wm);
return parport_ip32_read_control(p);
}
/**
* parport_ip32_disable_irq - disable interrupts on the rising edge of nACK
* @p: pointer to &struct parport
*/
static void parport_ip32_disable_irq(struct parport *p)
{
__parport_ip32_frob_control(p, DCR_IRQ, 0);
}
/**
* parport_ip32_enable_irq - enable interrupts on the rising edge of nACK
* @p: pointer to &struct parport
*/
static void parport_ip32_enable_irq(struct parport *p)
{
__parport_ip32_frob_control(p, DCR_IRQ, DCR_IRQ);
}
/**
* parport_ip32_data_forward - enable host-to-peripheral communications
* @p: pointer to &struct parport
*
* Enable the data line drivers, for 8-bit host-to-peripheral communications.
*/
static void parport_ip32_data_forward(struct parport *p)
{
__parport_ip32_frob_control(p, DCR_DIR, 0);
}
/**
* parport_ip32_data_reverse - enable peripheral-to-host communications
* @p: pointer to &struct parport
*
* Place the data bus in a high impedance state, if @p->modes has the
* PARPORT_MODE_TRISTATE bit set.
*/
static void parport_ip32_data_reverse(struct parport *p)
{
__parport_ip32_frob_control(p, DCR_DIR, DCR_DIR);
}
/**
* parport_ip32_init_state - for core parport code
* @dev: pointer to &struct pardevice
* @s: pointer to &struct parport_state to initialize
*/
static void parport_ip32_init_state(struct pardevice *dev,
struct parport_state *s)
{
s->u.ip32.dcr = DCR_SELECT | DCR_nINIT;
s->u.ip32.ecr = ECR_MODE_PS2 | ECR_nERRINTR | ECR_SERVINTR;
}
/**
* parport_ip32_save_state - for core parport code
* @p: pointer to &struct parport
* @s: pointer to &struct parport_state to save state to
*/
static void parport_ip32_save_state(struct parport *p,
struct parport_state *s)
{
s->u.ip32.dcr = __parport_ip32_read_control(p);
s->u.ip32.ecr = parport_ip32_read_econtrol(p);
}
/**
* parport_ip32_restore_state - for core parport code
* @p: pointer to &struct parport
* @s: pointer to &struct parport_state to restore state from
*/
static void parport_ip32_restore_state(struct parport *p,
struct parport_state *s)
{
parport_ip32_set_mode(p, s->u.ip32.ecr & ECR_MODE_MASK);
parport_ip32_write_econtrol(p, s->u.ip32.ecr);
__parport_ip32_write_control(p, s->u.ip32.dcr);
}
/*--- EPP mode functions -----------------------------------------------*/
/**
* parport_ip32_clear_epp_timeout - clear Timeout bit in EPP mode
* @p: pointer to &struct parport
*
* Returns 1 if the Timeout bit is clear, and 0 otherwise.
*/
static unsigned int parport_ip32_clear_epp_timeout(struct parport *p)
{
struct parport_ip32_private * const priv = p->physport->private_data;
unsigned int cleared;
if (!(parport_ip32_read_status(p) & DSR_TIMEOUT))
cleared = 1;
else {
unsigned int r;
/* To clear timeout some chips require double read */
parport_ip32_read_status(p);
r = parport_ip32_read_status(p);
/* Some reset by writing 1 */
iowrite8(r | DSR_TIMEOUT, priv->regs.dsr);
/* Others by writing 0 */
iowrite8(r & ~DSR_TIMEOUT, priv->regs.dsr);
r = parport_ip32_read_status(p);
cleared = !(r & DSR_TIMEOUT);
}
pr_trace(p, "(): %s", cleared ? "cleared" : "failed");
return cleared;
}
/**
* parport_ip32_epp_read - generic EPP read function
* @eppreg: I/O register to read from
* @p: pointer to &struct parport
* @buf: buffer to store read data
* @len: length of buffer @buf
* @flags: may be PARPORT_EPP_FAST
*/
static size_t parport_ip32_epp_read(void __iomem *eppreg,
struct parport *p, void *buf,
size_t len, int flags)
{
struct parport_ip32_private * const priv = p->physport->private_data;
size_t got;
parport_ip32_set_mode(p, ECR_MODE_EPP);
parport_ip32_data_reverse(p);
parport_ip32_write_control(p, DCR_nINIT);
if ((flags & PARPORT_EPP_FAST) && (len > 1)) {
ioread8_rep(eppreg, buf, len);
if (ioread8(priv->regs.dsr) & DSR_TIMEOUT) {
parport_ip32_clear_epp_timeout(p);
return -EIO;
}
got = len;
} else {
u8 *bufp = buf;
for (got = 0; got < len; got++) {
*bufp++ = ioread8(eppreg);
if (ioread8(priv->regs.dsr) & DSR_TIMEOUT) {
parport_ip32_clear_epp_timeout(p);
break;
}
}
}
parport_ip32_data_forward(p);
parport_ip32_set_mode(p, ECR_MODE_PS2);
return got;
}
/**
* parport_ip32_epp_write - generic EPP write function
* @eppreg: I/O register to write to
* @p: pointer to &struct parport
* @buf: buffer of data to write
* @len: length of buffer @buf
* @flags: may be PARPORT_EPP_FAST
*/
static size_t parport_ip32_epp_write(void __iomem *eppreg,
struct parport *p, const void *buf,
size_t len, int flags)
{
struct parport_ip32_private * const priv = p->physport->private_data;
size_t written;
parport_ip32_set_mode(p, ECR_MODE_EPP);
parport_ip32_data_forward(p);
parport_ip32_write_control(p, DCR_nINIT);
if ((flags & PARPORT_EPP_FAST) && (len > 1)) {
iowrite8_rep(eppreg, buf, len);
if (ioread8(priv->regs.dsr) & DSR_TIMEOUT) {
parport_ip32_clear_epp_timeout(p);
return -EIO;