diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 19391d94e30..51eddcf2b79 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1218,6 +1218,8 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = {"zvl32768b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvl65536b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"ztso", ISA_SPEC_CLASS_DRAFT, 0, 1, 0 }, + {"zimop", ISA_SPEC_CLASS_DRAFT, 0, 1, 0}, + {"zcmop", ISA_SPEC_CLASS_DRAFT, 0, 1, 0}, {NULL, 0, 0, 0, 0} }; @@ -2383,6 +2385,10 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, return riscv_subset_supports (rps, "xtheadmempair"); case INSN_CLASS_XTHEADSYNC: return riscv_subset_supports (rps, "xtheadsync"); + case INSN_CLASS_ZIMOP: + return riscv_subset_supports (rps, "zimop"); + case INSN_CLASS_ZCMOP: + return riscv_subset_supports (rps, "zcmop"); default: rps->error_handler (_("internal: unreachable INSN_CLASS_*")); @@ -2541,6 +2547,10 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return "xtheadmempair"; case INSN_CLASS_XTHEADSYNC: return "xtheadsync"; + case INSN_CLASS_ZIMOP: + return _("zimop"); + case INSN_CLASS_ZCMOP: + return _("zcmop"); default: rps->error_handler (_("internal: unreachable INSN_CLASS_*")); diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 85d35c1efc9..b8610317eaf 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -501,6 +501,61 @@ #define MASK_XPERM4 0xfe00707f #define MATCH_XPERM8 0x28004033 #define MASK_XPERM8 0xfe00707f + +#define MATCH_MOP_R_0 0x81C04073 +#define MATCH_MOP_R_1 0x81D04073 +#define MATCH_MOP_R_2 0x81E04073 +#define MATCH_MOP_R_3 0x81F04073 +#define MATCH_MOP_R_4 0x85C04073 +#define MATCH_MOP_R_5 0x85D04073 +#define MATCH_MOP_R_6 0x85E04073 +#define MATCH_MOP_R_7 0x85F04073 +#define MATCH_MOP_R_8 0x89C04073 +#define MATCH_MOP_R_9 0x89D04073 +#define MATCH_MOP_R_10 0x89E04073 +#define MATCH_MOP_R_11 0x89F04073 +#define MATCH_MOP_R_12 0x8DC04073 +#define MATCH_MOP_R_13 0x8DD04073 +#define MATCH_MOP_R_14 0x8DE04073 +#define MATCH_MOP_R_15 0x8DF04073 +#define MATCH_MOP_R_16 0xC1C04073 +#define MATCH_MOP_R_17 0xC1D04073 +#define MATCH_MOP_R_18 0xC1E04073 +#define MATCH_MOP_R_19 0xC1F04073 +#define MATCH_MOP_R_20 0xC5C04073 +#define MATCH_MOP_R_21 0xC5D04073 +#define MATCH_MOP_R_22 0xC5E04073 +#define MATCH_MOP_R_23 0xC5F04073 +#define MATCH_MOP_R_24 0xC9C04073 +#define MATCH_MOP_R_25 0xC9D04073 +#define MATCH_MOP_R_26 0xC9E04073 +#define MATCH_MOP_R_27 0xC9F04073 +#define MATCH_MOP_R_28 0xCDC04073 +#define MATCH_MOP_R_29 0xCDD04073 +#define MATCH_MOP_R_30 0xCDE04073 +#define MATCH_MOP_R_31 0xCDF04073 +#define MASK_MOP_R 0xFFF0707F + +#define MATCH_MOP_RR_0 0x82004073 +#define MATCH_MOP_RR_1 0x86004073 +#define MATCH_MOP_RR_2 0x8A004073 +#define MATCH_MOP_RR_3 0x8E004073 +#define MATCH_MOP_RR_4 0xC2004073 +#define MATCH_MOP_RR_5 0xC6004073 +#define MATCH_MOP_RR_6 0xCA004073 +#define MATCH_MOP_RR_7 0xCE004073 +#define MASK_MOP_RR 0xFE00707F + +#define MATCH_C_MOP_0 0x6081 +#define MATCH_C_MOP_1 0x6181 +#define MATCH_C_MOP_2 0x6281 +#define MATCH_C_MOP_3 0x6381 +#define MATCH_C_MOP_4 0x6481 +#define MATCH_C_MOP_5 0x6581 +#define MATCH_C_MOP_6 0x6681 +#define MATCH_C_MOP_7 0x6781 +#define MASK_C_MOP 0xFFFF + #define MATCH_BCLRI 0x48001013 #define MASK_BCLRI 0xfc00707f #define MATCH_BSETI 0x28001013 diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index b4ae55249bb..1b2c0f05fbb 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -395,6 +395,8 @@ enum riscv_insn_class INSN_CLASS_ZBKB, INSN_CLASS_ZBKC, INSN_CLASS_ZBKX, + INSN_CLASS_ZIMOP, + INSN_CLASS_ZCMOP, INSN_CLASS_ZKND, INSN_CLASS_ZKNE, INSN_CLASS_ZKNH, diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index f67375f10a9..f60778712f6 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -1014,6 +1014,58 @@ const struct riscv_opcode riscv_opcodes[] = {"xperm4", 0, INSN_CLASS_ZBKX, "d,s,t", MATCH_XPERM4, MASK_XPERM4, match_opcode, 0 }, {"xperm8", 0, INSN_CLASS_ZBKX, "d,s,t", MATCH_XPERM8, MASK_XPERM8, match_opcode, 0 }, +/* Zimop instructions. */ +{"mop.r.0", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_0, MASK_MOP_R, match_opcode, 0}, +{"mop.r.1", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_1, MASK_MOP_R, match_opcode, 0}, +{"mop.r.2", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_2, MASK_MOP_R, match_opcode, 0}, +{"mop.r.3", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_3, MASK_MOP_R, match_opcode, 0}, +{"mop.r.4", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_4, MASK_MOP_R, match_opcode, 0}, +{"mop.r.5", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_5, MASK_MOP_R, match_opcode, 0}, +{"mop.r.6", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_6, MASK_MOP_R, match_opcode, 0}, +{"mop.r.7", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_7, MASK_MOP_R, match_opcode, 0}, +{"mop.r.8", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_8, MASK_MOP_R, match_opcode, 0}, +{"mop.r.9", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_9, MASK_MOP_R, match_opcode, 0}, +{"mop.r.10", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_10, MASK_MOP_R, match_opcode, 0}, +{"mop.r.11", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_11, MASK_MOP_R, match_opcode, 0}, +{"mop.r.12", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_12, MASK_MOP_R, match_opcode, 0}, +{"mop.r.13", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_13, MASK_MOP_R, match_opcode, 0}, +{"mop.r.14", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_14, MASK_MOP_R, match_opcode, 0}, +{"mop.r.15", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_15, MASK_MOP_R, match_opcode, 0}, +{"mop.r.16", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_16, MASK_MOP_R, match_opcode, 0}, +{"mop.r.17", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_17, MASK_MOP_R, match_opcode, 0}, +{"mop.r.18", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_18, MASK_MOP_R, match_opcode, 0}, +{"mop.r.19", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_19, MASK_MOP_R, match_opcode, 0}, +{"mop.r.20", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_20, MASK_MOP_R, match_opcode, 0}, +{"mop.r.21", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_21, MASK_MOP_R, match_opcode, 0}, +{"mop.r.22", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_22, MASK_MOP_R, match_opcode, 0}, +{"mop.r.23", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_23, MASK_MOP_R, match_opcode, 0}, +{"mop.r.24", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_24, MASK_MOP_R, match_opcode, 0}, +{"mop.r.25", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_25, MASK_MOP_R, match_opcode, 0}, +{"mop.r.26", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_26, MASK_MOP_R, match_opcode, 0}, +{"mop.r.27", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_27, MASK_MOP_R, match_opcode, 0}, +{"mop.r.28", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_28, MASK_MOP_R, match_opcode, 0}, +{"mop.r.29", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_29, MASK_MOP_R, match_opcode, 0}, +{"mop.r.30", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_30, MASK_MOP_R, match_opcode, 0}, +{"mop.r.31", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_31, MASK_MOP_R, match_opcode, 0}, + +{"mop.rr.0", 0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_0, MASK_MOP_RR, match_opcode, 0}, +{"mop.rr.1", 0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_1, MASK_MOP_RR, match_opcode, 0}, +{"mop.rr.2", 0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_2, MASK_MOP_RR, match_opcode, 0}, +{"mop.rr.3", 0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_3, MASK_MOP_RR, match_opcode, 0}, +{"mop.rr.4", 0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_4, MASK_MOP_RR, match_opcode, 0}, +{"mop.rr.5", 0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_5, MASK_MOP_RR, match_opcode, 0}, +{"mop.rr.6", 0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_6, MASK_MOP_RR, match_opcode, 0}, +{"mop.rr.7", 0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_7, MASK_MOP_RR, match_opcode, 0}, + +{"c.mop.0", 0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_0, MASK_C_MOP, match_opcode, 0}, +{"c.mop.1", 0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_1, MASK_C_MOP, match_opcode, 0}, +{"c.mop.2", 0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_2, MASK_C_MOP, match_opcode, 0}, +{"c.mop.3", 0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_3, MASK_C_MOP, match_opcode, 0}, +{"c.mop.4", 0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_4, MASK_C_MOP, match_opcode, 0}, +{"c.mop.5", 0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_5, MASK_C_MOP, match_opcode, 0}, +{"c.mop.6", 0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_6, MASK_C_MOP, match_opcode, 0}, +{"c.mop.7", 0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_7, MASK_C_MOP, match_opcode, 0}, + /* Zknd instructions. */ {"aes32dsi", 32, INSN_CLASS_ZKND, "d,s,t,y", MATCH_AES32DSI, MASK_AES32DSI, match_opcode, 0 }, {"aes32dsmi", 32, INSN_CLASS_ZKND, "d,s,t,y", MATCH_AES32DSMI, MASK_AES32DSMI, match_opcode, 0 },