diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index b7e067794ba..21fc99ef8c6 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1148,6 +1148,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"zhinx", "zhinxmin", check_implicit_always}, {"zhinxmin", "zfinx", check_implicit_always}, {"zfinx", "zicsr", check_implicit_always}, + {"zabha", "a", check_implicit_always}, {"zacas", "a", check_implicit_always}, {"zk", "zkn", check_implicit_always}, {"zk", "zkr", check_implicit_always}, @@ -1260,6 +1261,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = {"zihintntl", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zihintpause", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 }, {"zmmul", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zabha", ISA_SPEC_CLASS_DRAFT, 0, 9, 0 }, {"zacas", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zawrs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zfa", ISA_SPEC_CLASS_DRAFT, 0, 1, 0 }, @@ -2411,6 +2413,11 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, return riscv_subset_supports (rps, "zmmul"); case INSN_CLASS_A: return riscv_subset_supports (rps, "a"); + case INSN_CLASS_ZABHA: + return riscv_subset_supports (rps, "zabha"); + case INSN_CLASS_ZABHA_AND_ZACAS: + return (riscv_subset_supports (rps, "zabha") + && riscv_subset_supports (rps, "zacas")); case INSN_CLASS_ZACAS: return riscv_subset_supports (rps, "zacas"); case INSN_CLASS_ZAWRS: @@ -2623,6 +2630,16 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return _ ("m' or `zmmul"); case INSN_CLASS_A: return "a"; + case INSN_CLASS_ZABHA: + return "zabha"; + case INSN_CLASS_ZABHA_AND_ZACAS: + if (!riscv_subset_supports (rps, "zabha") + && !riscv_subset_supports (rps, "zacas")) + return _("zabha' and `zacas"); + else if (!riscv_subset_supports (rps, "zabha")) + return "zabha"; + else + return "zacas"; case INSN_CLASS_ZACAS: return "zacas"; case INSN_CLASS_ZAWRS: diff --git a/gas/testsuite/gas/riscv/zabha-zacas.d b/gas/testsuite/gas/riscv/zabha-zacas.d new file mode 100644 index 00000000000..ea3657a6093 --- /dev/null +++ b/gas/testsuite/gas/riscv/zabha-zacas.d @@ -0,0 +1,17 @@ +#as: -march=rv32i_zabha_zacas +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : +[ ]+[0-9a-f]+:[ ]+28c5852f[ ]+amocas\.b[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+2cc5852f[ ]+amocas\.b\.aq[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+2ac5852f[ ]+amocas\.b\.rl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+2ec5852f[ ]+amocas\.b\.aqrl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+28c5952f[ ]+amocas\.h[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+2cc5952f[ ]+amocas\.h\.aq[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+2ac5952f[ ]+amocas\.h\.rl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+2ec5952f[ ]+amocas\.h\.aqrl[ ]+a0,a2,\(a1\) diff --git a/gas/testsuite/gas/riscv/zabha-zacas.s b/gas/testsuite/gas/riscv/zabha-zacas.s new file mode 100644 index 00000000000..09aac3b9401 --- /dev/null +++ b/gas/testsuite/gas/riscv/zabha-zacas.s @@ -0,0 +1,9 @@ +target: + amocas.b a0, a2, (a1) + amocas.b.aq a0, a2, (a1) + amocas.b.rl a0, a2, (a1) + amocas.b.aqrl a0, a2, (a1) + amocas.h a0, a2, (a1) + amocas.h.aq a0, a2, (a1) + amocas.h.rl a0, a2, (a1) + amocas.h.aqrl a0, a2, (a1) diff --git a/gas/testsuite/gas/riscv/zabha.d b/gas/testsuite/gas/riscv/zabha.d new file mode 100644 index 00000000000..0cc39f9da82 --- /dev/null +++ b/gas/testsuite/gas/riscv/zabha.d @@ -0,0 +1,81 @@ +#as: -march=rv32i_zabha +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : +[ ]+[0-9a-f]+:[ ]+08c5852f[ ]+amoswap\.b[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+0cc5852f[ ]+amoswap\.b\.aq[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+0ac5852f[ ]+amoswap\.b\.rl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+0ec5852f[ ]+amoswap\.b\.aqrl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+00c5852f[ ]+amoadd\.b[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+04c5852f[ ]+amoadd\.b\.aq[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+02c5852f[ ]+amoadd\.b\.rl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+06c5852f[ ]+amoadd\.b\.aqrl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+20c5852f[ ]+amoxor\.b[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+24c5852f[ ]+amoxor\.b\.aq[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+22c5852f[ ]+amoxor\.b\.rl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+26c5852f[ ]+amoxor\.b\.aqrl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+60c5852f[ ]+amoand\.b[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+64c5852f[ ]+amoand\.b\.aq[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+62c5852f[ ]+amoand\.b\.rl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+66c5852f[ ]+amoand\.b\.aqrl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+40c5852f[ ]+amoor\.b[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+44c5852f[ ]+amoor\.b\.aq[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+42c5852f[ ]+amoor\.b\.rl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+46c5852f[ ]+amoor\.b\.aqrl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+80c5852f[ ]+amomin\.b[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+84c5852f[ ]+amomin\.b\.aq[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+82c5852f[ ]+amomin\.b\.rl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+86c5852f[ ]+amomin\.b\.aqrl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+a0c5852f[ ]+amomax\.b[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+a4c5852f[ ]+amomax\.b\.aq[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+a2c5852f[ ]+amomax\.b\.rl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+a6c5852f[ ]+amomax\.b\.aqrl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+c0c5852f[ ]+amominu\.b[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+c4c5852f[ ]+amominu\.b\.aq[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+c2c5852f[ ]+amominu\.b\.rl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+c6c5852f[ ]+amominu\.b\.aqrl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+e0c5852f[ ]+amomaxu\.b[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+e4c5852f[ ]+amomaxu\.b\.aq[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+e2c5852f[ ]+amomaxu\.b\.rl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+e6c5852f[ ]+amomaxu\.b\.aqrl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+08c5952f[ ]+amoswap\.h[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+0cc5952f[ ]+amoswap\.h\.aq[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+0ac5952f[ ]+amoswap\.h\.rl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+0ec5952f[ ]+amoswap\.h\.aqrl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+00c5952f[ ]+amoadd\.h[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+04c5952f[ ]+amoadd\.h\.aq[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+02c5952f[ ]+amoadd\.h\.rl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+06c5952f[ ]+amoadd\.h\.aqrl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+20c5952f[ ]+amoxor\.h[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+24c5952f[ ]+amoxor\.h\.aq[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+22c5952f[ ]+amoxor\.h\.rl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+26c5952f[ ]+amoxor\.h\.aqrl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+60c5952f[ ]+amoand\.h[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+64c5952f[ ]+amoand\.h\.aq[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+62c5952f[ ]+amoand\.h\.rl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+66c5952f[ ]+amoand\.h\.aqrl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+40c5952f[ ]+amoor\.h[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+44c5952f[ ]+amoor\.h\.aq[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+42c5952f[ ]+amoor\.h\.rl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+46c5952f[ ]+amoor\.h\.aqrl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+80c5952f[ ]+amomin\.h[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+84c5952f[ ]+amomin\.h\.aq[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+82c5952f[ ]+amomin\.h\.rl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+86c5952f[ ]+amomin\.h\.aqrl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+a0c5952f[ ]+amomax\.h[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+a4c5952f[ ]+amomax\.h\.aq[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+a2c5952f[ ]+amomax\.h\.rl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+a6c5952f[ ]+amomax\.h\.aqrl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+c0c5952f[ ]+amominu\.h[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+c4c5952f[ ]+amominu\.h\.aq[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+c2c5952f[ ]+amominu\.h\.rl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+c6c5952f[ ]+amominu\.h\.aqrl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+e0c5952f[ ]+amomaxu\.h[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+e4c5952f[ ]+amomaxu\.h\.aq[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+e2c5952f[ ]+amomaxu\.h\.rl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+e6c5952f[ ]+amomaxu\.h\.aqrl[ ]+a0,a2,\(a1\) diff --git a/gas/testsuite/gas/riscv/zabha.s b/gas/testsuite/gas/riscv/zabha.s new file mode 100644 index 00000000000..ab521119a75 --- /dev/null +++ b/gas/testsuite/gas/riscv/zabha.s @@ -0,0 +1,73 @@ +target: + amoswap.b a0, a2, (a1) + amoswap.b.aq a0, a2, (a1) + amoswap.b.rl a0, a2, (a1) + amoswap.b.aqrl a0, a2, (a1) + amoadd.b a0, a2, (a1) + amoadd.b.aq a0, a2, (a1) + amoadd.b.rl a0, a2, (a1) + amoadd.b.aqrl a0, a2, (a1) + amoxor.b a0, a2, (a1) + amoxor.b.aq a0, a2, (a1) + amoxor.b.rl a0, a2, (a1) + amoxor.b.aqrl a0, a2, (a1) + amoand.b a0, a2, (a1) + amoand.b.aq a0, a2, (a1) + amoand.b.rl a0, a2, (a1) + amoand.b.aqrl a0, a2, (a1) + amoor.b a0, a2, (a1) + amoor.b.aq a0, a2, (a1) + amoor.b.rl a0, a2, (a1) + amoor.b.aqrl a0, a2, (a1) + amomin.b a0, a2, (a1) + amomin.b.aq a0, a2, (a1) + amomin.b.rl a0, a2, (a1) + amomin.b.aqrl a0, a2, (a1) + amomax.b a0, a2, (a1) + amomax.b.aq a0, a2, (a1) + amomax.b.rl a0, a2, (a1) + amomax.b.aqrl a0, a2, (a1) + amominu.b a0, a2, (a1) + amominu.b.aq a0, a2, (a1) + amominu.b.rl a0, a2, (a1) + amominu.b.aqrl a0, a2, (a1) + amomaxu.b a0, a2, (a1) + amomaxu.b.aq a0, a2, (a1) + amomaxu.b.rl a0, a2, (a1) + amomaxu.b.aqrl a0, a2, (a1) + amoswap.h a0, a2, (a1) + amoswap.h.aq a0, a2, (a1) + amoswap.h.rl a0, a2, (a1) + amoswap.h.aqrl a0, a2, (a1) + amoadd.h a0, a2, (a1) + amoadd.h.aq a0, a2, (a1) + amoadd.h.rl a0, a2, (a1) + amoadd.h.aqrl a0, a2, (a1) + amoxor.h a0, a2, (a1) + amoxor.h.aq a0, a2, (a1) + amoxor.h.rl a0, a2, (a1) + amoxor.h.aqrl a0, a2, (a1) + amoand.h a0, a2, (a1) + amoand.h.aq a0, a2, (a1) + amoand.h.rl a0, a2, (a1) + amoand.h.aqrl a0, a2, (a1) + amoor.h a0, a2, (a1) + amoor.h.aq a0, a2, (a1) + amoor.h.rl a0, a2, (a1) + amoor.h.aqrl a0, a2, (a1) + amomin.h a0, a2, (a1) + amomin.h.aq a0, a2, (a1) + amomin.h.rl a0, a2, (a1) + amomin.h.aqrl a0, a2, (a1) + amomax.h a0, a2, (a1) + amomax.h.aq a0, a2, (a1) + amomax.h.rl a0, a2, (a1) + amomax.h.aqrl a0, a2, (a1) + amominu.h a0, a2, (a1) + amominu.h.aq a0, a2, (a1) + amominu.h.rl a0, a2, (a1) + amominu.h.aqrl a0, a2, (a1) + amomaxu.h a0, a2, (a1) + amomaxu.h.aq a0, a2, (a1) + amomaxu.h.rl a0, a2, (a1) + amomaxu.h.aqrl a0, a2, (a1) diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 8fb59e3db93..49786513a0a 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2315,6 +2315,47 @@ #define MASK_C_NTL_S1 0xffff #define MATCH_C_NTL_ALL 0x9016 #define MASK_C_NTL_ALL 0xffff +/* Zabha instructions. */ +#define MATCH_AMOADD_B 0x2f +#define MASK_AMOADD_B 0xf800707f +#define MATCH_AMOADD_H 0x102f +#define MASK_AMOADD_H 0xf800707f +#define MATCH_AMOAND_B 0x6000002f +#define MASK_AMOAND_B 0xf800707f +#define MATCH_AMOAND_H 0x6000102f +#define MASK_AMOAND_H 0xf800707f +#define MATCH_AMOMAX_B 0xa000002f +#define MASK_AMOMAX_B 0xf800707f +#define MATCH_AMOMAX_H 0xa000102f +#define MASK_AMOMAX_H 0xf800707f +#define MATCH_AMOMAXU_B 0xe000002f +#define MASK_AMOMAXU_B 0xf800707f +#define MATCH_AMOMAXU_H 0xe000102f +#define MASK_AMOMAXU_H 0xf800707f +#define MATCH_AMOMIN_B 0x8000002f +#define MASK_AMOMIN_B 0xf800707f +#define MATCH_AMOMIN_H 0x8000102f +#define MASK_AMOMIN_H 0xf800707f +#define MATCH_AMOMINU_B 0xc000002f +#define MASK_AMOMINU_B 0xf800707f +#define MATCH_AMOMINU_H 0xc000102f +#define MASK_AMOMINU_H 0xf800707f +#define MATCH_AMOOR_B 0x4000002f +#define MASK_AMOOR_B 0xf800707f +#define MATCH_AMOOR_H 0x4000102f +#define MASK_AMOOR_H 0xf800707f +#define MATCH_AMOSWAP_B 0x800002f +#define MASK_AMOSWAP_B 0xf800707f +#define MATCH_AMOSWAP_H 0x800102f +#define MASK_AMOSWAP_H 0xf800707f +#define MATCH_AMOXOR_B 0x2000002f +#define MASK_AMOXOR_B 0xf800707f +#define MATCH_AMOXOR_H 0x2000102f +#define MASK_AMOXOR_H 0xf800707f +#define MATCH_AMOCAS_B 0x2800002f +#define MASK_AMOCAS_B 0xf800707f +#define MATCH_AMOCAS_H 0x2800102f +#define MASK_AMOCAS_H 0xf800707f /* Zacas instructions. */ #define MATCH_AMOCAS_D 0x2800302f #define MASK_AMOCAS_D 0xf800707f @@ -3377,6 +3418,27 @@ DECLARE_INSN(c_ntl_p1, MATCH_C_NTL_P1, MASK_C_NTL_P1) DECLARE_INSN(c_ntl_pall, MATCH_C_NTL_PALL, MASK_C_NTL_PALL) DECLARE_INSN(c_ntl_s1, MATCH_C_NTL_S1, MASK_C_NTL_S1) DECLARE_INSN(c_ntl_all, MATCH_C_NTL_ALL, MASK_C_NTL_ALL) +/* Zabha instructions. */ +DECLARE_INSN(amoadd_b, MATCH_AMOADD_B, MASK_AMOADD_B) +DECLARE_INSN(amoadd_h, MATCH_AMOADD_H, MASK_AMOADD_H) +DECLARE_INSN(amoand_b, MATCH_AMOAND_B, MASK_AMOAND_B) +DECLARE_INSN(amoand_h, MATCH_AMOAND_H, MASK_AMOAND_H) +DECLARE_INSN(amomax_b, MATCH_AMOMAX_B, MASK_AMOMAX_B) +DECLARE_INSN(amomax_h, MATCH_AMOMAX_H, MASK_AMOMAX_H) +DECLARE_INSN(amomaxu_b, MATCH_AMOMAXU_B, MASK_AMOMAXU_B) +DECLARE_INSN(amomaxu_h, MATCH_AMOMAXU_H, MASK_AMOMAXU_H) +DECLARE_INSN(amomin_b, MATCH_AMOMIN_B, MASK_AMOMIN_B) +DECLARE_INSN(amomin_h, MATCH_AMOMIN_H, MASK_AMOMIN_H) +DECLARE_INSN(amominu_b, MATCH_AMOMINU_B, MASK_AMOMINU_B) +DECLARE_INSN(amominu_h, MATCH_AMOMINU_H, MASK_AMOMINU_H) +DECLARE_INSN(amoor_b, MATCH_AMOOR_B, MASK_AMOOR_B) +DECLARE_INSN(amoor_h, MATCH_AMOOR_H, MASK_AMOOR_H) +DECLARE_INSN(amoswap_b, MATCH_AMOSWAP_B, MASK_AMOSWAP_B) +DECLARE_INSN(amoswap_h, MATCH_AMOSWAP_H, MASK_AMOSWAP_H) +DECLARE_INSN(amoxor_b, MATCH_AMOXOR_B, MASK_AMOXOR_B) +DECLARE_INSN(amoxor_h, MATCH_AMOXOR_H, MASK_AMOXOR_H) +DECLARE_INSN(amocas_b, MATCH_AMOCAS_B, MASK_AMOCAS_B) +DECLARE_INSN(amocas_h, MATCH_AMOCAS_H, MASK_AMOCAS_H) /* Zacas instructions. */ DECLARE_INSN(amocas_d, MATCH_AMOCAS_D, MASK_AMOCAS_D) DECLARE_INSN(amocas_q, MATCH_AMOCAS_Q, MASK_AMOCAS_Q) diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index aefbfc7db81..f22f89bc38b 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -396,6 +396,8 @@ enum riscv_insn_class INSN_CLASS_ZIHINTNTL_AND_C, INSN_CLASS_ZIHINTPAUSE, INSN_CLASS_ZMMUL, + INSN_CLASS_ZABHA, + INSN_CLASS_ZABHA_AND_ZACAS, INSN_CLASS_ZACAS, INSN_CLASS_ZAWRS, INSN_CLASS_F_INX, diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 58087ca19ca..5955092d6f7 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -1000,6 +1000,88 @@ const struct riscv_opcode riscv_opcodes[] = {"czero.eqz", 0, INSN_CLASS_ZICOND, "d,s,t", MATCH_CZERO_EQZ, MASK_CZERO_EQZ, match_opcode, 0 }, {"czero.nez", 0, INSN_CLASS_ZICOND, "d,s,t", MATCH_CZERO_NEZ, MASK_CZERO_NEZ, match_opcode, 0 }, +/* Zabha instructions. */ +{"amoadd.b", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOADD_B, MASK_AMOADD_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amoswap.b", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOSWAP_B, MASK_AMOSWAP_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amoand.b", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOAND_B, MASK_AMOAND_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amoor.b", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOOR_B, MASK_AMOOR_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amoxor.b", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOXOR_B, MASK_AMOXOR_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amomax.b", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAX_B, MASK_AMOMAX_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amomaxu.b", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAXU_B, MASK_AMOMAXU_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amomin.b", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMIN_B, MASK_AMOMIN_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amominu.b", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMINU_B, MASK_AMOMINU_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amoadd.b.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOADD_B|MASK_AQ, MASK_AMOADD_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amoswap.b.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOSWAP_B|MASK_AQ, MASK_AMOSWAP_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amoand.b.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOAND_B|MASK_AQ, MASK_AMOAND_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amoor.b.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOOR_B|MASK_AQ, MASK_AMOOR_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amoxor.b.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOXOR_B|MASK_AQ, MASK_AMOXOR_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amomax.b.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAX_B|MASK_AQ, MASK_AMOMAX_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amomaxu.b.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAXU_B|MASK_AQ, MASK_AMOMAXU_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amomin.b.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMIN_B|MASK_AQ, MASK_AMOMIN_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amominu.b.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMINU_B|MASK_AQ, MASK_AMOMINU_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amoadd.b.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOADD_B|MASK_RL, MASK_AMOADD_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amoswap.b.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOSWAP_B|MASK_RL, MASK_AMOSWAP_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amoand.b.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOAND_B|MASK_RL, MASK_AMOAND_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amoor.b.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOOR_B|MASK_RL, MASK_AMOOR_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amoxor.b.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOXOR_B|MASK_RL, MASK_AMOXOR_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amomax.b.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAX_B|MASK_RL, MASK_AMOMAX_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amomaxu.b.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAXU_B|MASK_RL, MASK_AMOMAXU_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amomin.b.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMIN_B|MASK_RL, MASK_AMOMIN_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amominu.b.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMINU_B|MASK_RL, MASK_AMOMINU_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amoadd.b.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOADD_B|MASK_AQRL, MASK_AMOADD_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amoswap.b.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOSWAP_B|MASK_AQRL, MASK_AMOSWAP_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amoand.b.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOAND_B|MASK_AQRL, MASK_AMOAND_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amoor.b.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOOR_B|MASK_AQRL, MASK_AMOOR_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amoxor.b.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOXOR_B|MASK_AQRL, MASK_AMOXOR_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amomax.b.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAX_B|MASK_AQRL, MASK_AMOMAX_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amomaxu.b.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAXU_B|MASK_AQRL, MASK_AMOMAXU_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amomin.b.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMIN_B|MASK_AQRL, MASK_AMOMIN_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amominu.b.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMINU_B|MASK_AQRL, MASK_AMOMINU_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amoadd.h", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOADD_H, MASK_AMOADD_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amoswap.h", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOSWAP_H, MASK_AMOSWAP_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amoand.h", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOAND_H, MASK_AMOAND_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amoor.h", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOOR_H, MASK_AMOOR_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amoxor.h", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOXOR_H, MASK_AMOXOR_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amomax.h", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAX_H, MASK_AMOMAX_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amomaxu.h", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAXU_H, MASK_AMOMAXU_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amomin.h", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMIN_H, MASK_AMOMIN_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amominu.h", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMINU_H, MASK_AMOMINU_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amoadd.h.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOADD_H|MASK_AQ, MASK_AMOADD_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amoswap.h.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOSWAP_H|MASK_AQ, MASK_AMOSWAP_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amoand.h.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOAND_H|MASK_AQ, MASK_AMOAND_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amoor.h.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOOR_H|MASK_AQ, MASK_AMOOR_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amoxor.h.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOXOR_H|MASK_AQ, MASK_AMOXOR_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amomax.h.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAX_H|MASK_AQ, MASK_AMOMAX_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amomaxu.h.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAXU_H|MASK_AQ, MASK_AMOMAXU_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amomin.h.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMIN_H|MASK_AQ, MASK_AMOMIN_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amominu.h.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMINU_H|MASK_AQ, MASK_AMOMINU_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amoadd.h.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOADD_H|MASK_RL, MASK_AMOADD_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amoswap.h.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOSWAP_H|MASK_RL, MASK_AMOSWAP_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amoand.h.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOAND_H|MASK_RL, MASK_AMOAND_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amoor.h.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOOR_H|MASK_RL, MASK_AMOOR_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amoxor.h.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOXOR_H|MASK_RL, MASK_AMOXOR_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amomax.h.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAX_H|MASK_RL, MASK_AMOMAX_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amomaxu.h.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAXU_H|MASK_RL, MASK_AMOMAXU_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amomin.h.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMIN_H|MASK_RL, MASK_AMOMIN_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amominu.h.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMINU_H|MASK_RL, MASK_AMOMINU_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amoadd.h.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOADD_H|MASK_AQRL, MASK_AMOADD_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amoswap.h.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOSWAP_H|MASK_AQRL, MASK_AMOSWAP_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amoand.h.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOAND_H|MASK_AQRL, MASK_AMOAND_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amoor.h.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOOR_H|MASK_AQRL, MASK_AMOOR_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amoxor.h.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOXOR_H|MASK_AQRL, MASK_AMOXOR_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amomax.h.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAX_H|MASK_AQRL, MASK_AMOMAX_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amomaxu.h.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAXU_H|MASK_AQRL, MASK_AMOMAXU_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amomin.h.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMIN_H|MASK_AQRL, MASK_AMOMIN_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amominu.h.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMINU_H|MASK_AQRL, MASK_AMOMINU_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amocas.b", 0, INSN_CLASS_ZABHA_AND_ZACAS, "d,t,0(s)", MATCH_AMOCAS_B, MASK_AMOCAS_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amocas.h", 0, INSN_CLASS_ZABHA_AND_ZACAS, "d,t,0(s)", MATCH_AMOCAS_H, MASK_AMOCAS_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amocas.b.aq", 0, INSN_CLASS_ZABHA_AND_ZACAS, "d,t,0(s)", MATCH_AMOCAS_B|MASK_AQ, MASK_AMOCAS_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amocas.h.aq", 0, INSN_CLASS_ZABHA_AND_ZACAS, "d,t,0(s)", MATCH_AMOCAS_H|MASK_AQ, MASK_AMOCAS_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amocas.b.rl", 0, INSN_CLASS_ZABHA_AND_ZACAS, "d,t,0(s)", MATCH_AMOCAS_B|MASK_RL, MASK_AMOCAS_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amocas.h.rl", 0, INSN_CLASS_ZABHA_AND_ZACAS, "d,t,0(s)", MATCH_AMOCAS_H|MASK_RL, MASK_AMOCAS_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amocas.b.aqrl", 0, INSN_CLASS_ZABHA_AND_ZACAS, "d,t,0(s)", MATCH_AMOCAS_B|MASK_AQRL, MASK_AMOCAS_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amocas.h.aqrl", 0, INSN_CLASS_ZABHA_AND_ZACAS, "d,t,0(s)", MATCH_AMOCAS_H|MASK_AQRL, MASK_AMOCAS_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, + /* Zacas instructions. */ {"amocas.w", 0, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_W, MASK_AMOCAS_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, {"amocas.w.aq", 0, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_W|MASK_AQ, MASK_AMOCAS_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },