From df97f33dfbf5e7dae64d2a4dfb3aff25720f4b7c Mon Sep 17 00:00:00 2001
From: Tsukasa OI <research_trasio@irq.a4lg.com>
Date: Mon, 11 Jul 2022 16:41:07 +0900
Subject: [PATCH] RISC-V: Add comment to riscv_disassemble_insn

While other steps are annotated, extension test by instruction class was
not annotated or commented.

opcodes/ChangeLog:

	* riscv-dis.c (riscv_disassemble_insn) Add comment.
---
 opcodes/riscv-dis.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index f7cdf115b69..d68efee6ff2 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -755,7 +755,7 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info)
       /* Is this instruction restricted to a certain value of XLEN?  */
       if ((op->xlen_requirement != 0) && (op->xlen_requirement != xlen))
 	continue;
-
+      /* Is this instruction supported by the current architecture?  */
       if (!riscv_multi_subset_supports (&riscv_rps_dis, op->insn_class))
 	continue;