RISC-V: Support disassembling RV32E

This commit adds support for RV32E disassembling which turns x16-x31 into invalid16-invalid31 while disassembling. gas/ChangeLog: * testsuite/gas/riscv/e-ext-dis.s: New RV32E disassembler test. * testsuite/gas/riscv/e-ext-dis-rv32e.d: Likewise. * testsuite/gas/riscv/e-ext-dis-rv32i.d: Likewise. include/ChangeLog: * opcode/riscv.h: Add RVE register name definitions. opcodes/ChangeLog: * riscv-dis.c (init_riscv_dis_state_for_arch_and_options): Apply RVE register names when the E extension is enabled. * riscv-opc.c (riscv_gpr_names_rve_numeric): New. (riscv_gpr_names_rve_abi): New.
a4lg · Jul 13, 2022 · 82eaea0 · 82eaea0
1 parent 3d14647
commit 82eaea0
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Showing 6 changed files with 55 additions and 4 deletions.
diff --git a/gas/testsuite/gas/riscv/e-ext-dis-rv32e.d b/gas/testsuite/gas/riscv/e-ext-dis-rv32e.d
@@ -0,0 +1,11 @@
+#as: -march=rv32e
+#source: e-ext-dis.s
+#objdump: -dr -M numeric
+
+.*:[ 	]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+00f78793[ 	]+addi[ 	]+x15,x15,15
+[ 	]+[0-9a-f]+:[ 	]+01ff8f93[ 	]+addi[ 	]+invalid31,invalid31,31
diff --git a/gas/testsuite/gas/riscv/e-ext-dis-rv32i.d b/gas/testsuite/gas/riscv/e-ext-dis-rv32i.d
@@ -0,0 +1,11 @@
+#as: -march=rv32i
+#source: e-ext-dis.s
+#objdump: -dr -M numeric
+
+.*:[ 	]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+00f78793[ 	]+addi[ 	]+x15,x15,15
+[ 	]+[0-9a-f]+:[ 	]+01ff8f93[ 	]+addi[ 	]+x31,x31,31
diff --git a/gas/testsuite/gas/riscv/e-ext-dis.s b/gas/testsuite/gas/riscv/e-ext-dis.s
@@ -0,0 +1,4 @@
+target:
+	addi	x15, x15, 15
+	# addi	x31, x31, 31 (invalid on RV32E)
+	.insn	0x01ff8f93
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
@@ -519,6 +519,8 @@ enum riscv_seg_mstate
 
 extern const char * const riscv_gpr_names_numeric[NGPR];
 extern const char * const riscv_gpr_names_abi[NGPR];
+extern const char * const riscv_gpr_names_rve_numeric[NGPR];
+extern const char * const riscv_gpr_names_rve_abi[NGPR];
 extern const char * const riscv_fpr_names_numeric[NFPR];
 extern const char * const riscv_fpr_names_abi[NFPR];
 extern const char * const riscv_vecr_names_numeric[NVECR];

diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
@@ -86,6 +86,9 @@ init_riscv_dis_state_for_arch_and_options (void)
 {
   riscv_gpr_names = is_numeric ? riscv_gpr_names_numeric : riscv_gpr_names_abi;
   riscv_fpr_names = is_numeric ? riscv_fpr_names_numeric : riscv_fpr_names_abi;
+  if (riscv_subset_supports (&riscv_rps_dis, "e"))
+    riscv_gpr_names
+	= is_numeric ? riscv_gpr_names_rve_numeric : riscv_gpr_names_rve_abi;
   /* If arch has Zfinx extension, use GPR to disassemble.  */
   if (riscv_subset_supports (&riscv_rps_dis, "zfinx"))
     riscv_fpr_names = riscv_gpr_names;

diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
@@ -28,20 +28,40 @@
 
 const char * const riscv_gpr_names_numeric[NGPR] =
 {
-  "x0",   "x1",   "x2",   "x3",   "x4",   "x5",   "x6",   "x7",
-  "x8",   "x9",   "x10",  "x11",  "x12",  "x13",  "x14",  "x15",
+#define RISCV_GPR_NAMES_NUMERIC_LOWER \
+  "x0",   "x1",   "x2",   "x3",   "x4",   "x5",   "x6",   "x7", \
+  "x8",   "x9",   "x10",  "x11",  "x12",  "x13",  "x14",  "x15"
+  RISCV_GPR_NAMES_NUMERIC_LOWER,
   "x16",  "x17",  "x18",  "x19",  "x20",  "x21",  "x22",  "x23",
   "x24",  "x25",  "x26",  "x27",  "x28",  "x29",  "x30",  "x31"
 };
 
 const char * const riscv_gpr_names_abi[NGPR] =
 {
-  "zero", "ra",   "sp",   "gp",   "tp",   "t0",   "t1",   "t2",
-  "s0",   "s1",   "a0",   "a1",   "a2",   "a3",   "a4",   "a5",
+#define RISCV_GPR_NAMES_ABI_LOWER \
+  "zero", "ra",   "sp",   "gp",   "tp",   "t0",   "t1",   "t2", \
+  "s0",   "s1",   "a0",   "a1",   "a2",   "a3",   "a4",   "a5"
+  RISCV_GPR_NAMES_ABI_LOWER,
   "a6",   "a7",   "s2",   "s3",   "s4",   "s5",   "s6",   "s7",
   "s8",   "s9",   "s10",  "s11",  "t3",   "t4",   "t5",   "t6"
 };
 
+#define RISCV_GPR_NAMES_RVE_UPPER \
+  "invalid16", "invalid17", "invalid18", "invalid19", \
+  "invalid20", "invalid21", "invalid22", "invalid23", \
+  "invalid24", "invalid25", "invalid26", "invalid27", \
+  "invalid28", "invalid29", "invalid30", "invalid31"
+const char * const riscv_gpr_names_rve_numeric[NGPR] =
+{
+  RISCV_GPR_NAMES_NUMERIC_LOWER,
+  RISCV_GPR_NAMES_RVE_UPPER
+};
+const char * const riscv_gpr_names_rve_abi[NGPR] =
+{
+  RISCV_GPR_NAMES_ABI_LOWER,
+  RISCV_GPR_NAMES_RVE_UPPER
+};
+
 const char * const riscv_fpr_names_numeric[NFPR] =
 {
   "f0",   "f1",   "f2",   "f3",   "f4",   "f5",   "f6",   "f7",