diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index ee459872948..81aa7736710 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1185,6 +1185,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"smaia", "ssaia", check_implicit_always}, {"smstateen", "ssstateen", check_implicit_always}, {"smepmp", "zicsr", check_implicit_always}, + {"smrnmi", "zicsr", check_implicit_always}, {"ssaia", "zicsr", check_implicit_always}, {"sscofpmf", "zicsr", check_implicit_always}, {"ssstateen", "zicsr", check_implicit_always}, @@ -1329,6 +1330,7 @@ static struct riscv_supported_ext riscv_supported_std_s_ext[] = { {"smaia", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"smepmp", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"smrnmi", ISA_SPEC_CLASS_DRAFT, 0, 4, 0 }, {"smstateen", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"ssaia", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"sscofpmf", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, @@ -2525,6 +2527,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, case INSN_CLASS_ZCB_AND_ZMMUL: return (riscv_subset_supports (rps, "zcb") && riscv_subset_supports (rps, "zmmul")); + case INSN_CLASS_SMRNMI: + return riscv_subset_supports (rps, "smrnmi"); case INSN_CLASS_SVINVAL: return riscv_subset_supports (rps, "svinval"); case INSN_CLASS_H: @@ -2741,6 +2745,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return _("zcb' and `zbb"); case INSN_CLASS_ZCB_AND_ZMMUL: return _("zcb' and `zmmul', or `zcb' and `m"); + case INSN_CLASS_SMRNMI: + return "smrnmi"; case INSN_CLASS_SVINVAL: return "svinval"; case INSN_CLASS_H: diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index aaf8b9be64f..0547f236a4b 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -74,6 +74,7 @@ enum riscv_csr_class CSR_CLASS_H_32, /* hypervisor, rv32 only */ CSR_CLASS_SMAIA, /* Smaia */ CSR_CLASS_SMAIA_32, /* Smaia, rv32 only */ + CSR_CLASS_SMRNMI, /* Smrnmi only */ CSR_CLASS_SMSTATEEN, /* Smstateen only */ CSR_CLASS_SMSTATEEN_32, /* Smstateen RV32 only */ CSR_CLASS_SSAIA, /* Ssaia */ @@ -1052,6 +1053,9 @@ riscv_csr_address (const char *csr_name, case CSR_CLASS_SMAIA: extension = "smaia"; break; + case CSR_CLASS_SMRNMI: + extension = "smrnmi"; + break; case CSR_CLASS_SMSTATEEN_32: is_rv32_only = true; /* Fall through. */ diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.d b/gas/testsuite/gas/riscv/csr-dw-regnums.d index fd830666ab8..a87df625da9 100644 --- a/gas/testsuite/gas/riscv/csr-dw-regnums.d +++ b/gas/testsuite/gas/riscv/csr-dw-regnums.d @@ -324,6 +324,10 @@ Contents of the .* section: DW_CFA_offset_extended_sf: r4888 \(mvienh\) at cfa\+3168 DW_CFA_offset_extended_sf: r4889 \(mviph\) at cfa\+3172 DW_CFA_offset_extended_sf: r4948 \(miph\) at cfa\+3408 + DW_CFA_offset_extended_sf: r5952 \(mnscratch\) at cfa\+7424 + DW_CFA_offset_extended_sf: r5953 \(mnepc\) at cfa\+7428 + DW_CFA_offset_extended_sf: r5954 \(mncause\) at cfa\+7432 + DW_CFA_offset_extended_sf: r5956 \(mnstatus\) at cfa\+7440 DW_CFA_offset_extended_sf: r4876 \(mstateen0\) at cfa\+3120 DW_CFA_offset_extended_sf: r4877 \(mstateen1\) at cfa\+3124 DW_CFA_offset_extended_sf: r4878 \(mstateen2\) at cfa\+3128 diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.s b/gas/testsuite/gas/riscv/csr-dw-regnums.s index b8b0f790229..3ea3853a2cc 100644 --- a/gas/testsuite/gas/riscv/csr-dw-regnums.s +++ b/gas/testsuite/gas/riscv/csr-dw-regnums.s @@ -321,6 +321,11 @@ _start: .cfi_offset mvienh, 3168 .cfi_offset mviph, 3172 .cfi_offset miph, 3408 + # Smrnmi extension + .cfi_offset mnscratch, 7424 + .cfi_offset mnepc, 7428 + .cfi_offset mncause, 7432 + .cfi_offset mnstatus, 7440 # Smstateen extension .cfi_offset mstateen0, 3120 .cfi_offset mstateen1, 3124 diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.d b/gas/testsuite/gas/riscv/csr-version-1p10.d index ee41e1025cc..9c2bf4bc962 100644 --- a/gas/testsuite/gas/riscv/csr-version-1p10.d +++ b/gas/testsuite/gas/riscv/csr-version-1p10.d @@ -623,6 +623,14 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+31959073[ ]+csrw[ ]+mviph,a1 [ ]+[0-9a-f]+:[ ]+35402573[ ]+csrr[ ]+a0,miph [ ]+[0-9a-f]+:[ ]+35459073[ ]+csrw[ ]+miph,a1 +[ ]+[0-9a-f]+:[ ]+74002573[ ]+csrr[ ]+a0,mnscratch +[ ]+[0-9a-f]+:[ ]+74059073[ ]+csrw[ ]+mnscratch,a1 +[ ]+[0-9a-f]+:[ ]+74102573[ ]+csrr[ ]+a0,mnepc +[ ]+[0-9a-f]+:[ ]+74159073[ ]+csrw[ ]+mnepc,a1 +[ ]+[0-9a-f]+:[ ]+74202573[ ]+csrr[ ]+a0,mncause +[ ]+[0-9a-f]+:[ ]+74259073[ ]+csrw[ ]+mncause,a1 +[ ]+[0-9a-f]+:[ ]+74402573[ ]+csrr[ ]+a0,mnstatus +[ ]+[0-9a-f]+:[ ]+74459073[ ]+csrw[ ]+mnstatus,a1 [ ]+[0-9a-f]+:[ ]+30c02573[ ]+csrr[ ]+a0,mstateen0 [ ]+[0-9a-f]+:[ ]+30c59073[ ]+csrw[ ]+mstateen0,a1 [ ]+[0-9a-f]+:[ ]+30d02573[ ]+csrr[ ]+a0,mstateen1 diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.l b/gas/testsuite/gas/riscv/csr-version-1p10.l index 27bdc80c0d5..56891dd5f78 100644 --- a/gas/testsuite/gas/riscv/csr-version-1p10.l +++ b/gas/testsuite/gas/riscv/csr-version-1p10.l @@ -889,6 +889,22 @@ .*Info: macro .* .*Warning: invalid CSR `miph', needs `smaia' extension .*Info: macro .* +.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension +.*Info: macro .* +.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension +.*Info: macro .* +.*Warning: invalid CSR `mnepc', needs `smrnmi' extension +.*Info: macro .* +.*Warning: invalid CSR `mnepc', needs `smrnmi' extension +.*Info: macro .* +.*Warning: invalid CSR `mncause', needs `smrnmi' extension +.*Info: macro .* +.*Warning: invalid CSR `mncause', needs `smrnmi' extension +.*Info: macro .* +.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension +.*Info: macro .* +.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension +.*Info: macro .* .*Warning: invalid CSR `mstateen0', needs `smstateen' extension .*Info: macro .* .*Warning: invalid CSR `mstateen0', needs `smstateen' extension diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.d b/gas/testsuite/gas/riscv/csr-version-1p11.d index a83b1bf68f9..9783cb795e2 100644 --- a/gas/testsuite/gas/riscv/csr-version-1p11.d +++ b/gas/testsuite/gas/riscv/csr-version-1p11.d @@ -623,6 +623,14 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+31959073[ ]+csrw[ ]+mviph,a1 [ ]+[0-9a-f]+:[ ]+35402573[ ]+csrr[ ]+a0,miph [ ]+[0-9a-f]+:[ ]+35459073[ ]+csrw[ ]+miph,a1 +[ ]+[0-9a-f]+:[ ]+74002573[ ]+csrr[ ]+a0,mnscratch +[ ]+[0-9a-f]+:[ ]+74059073[ ]+csrw[ ]+mnscratch,a1 +[ ]+[0-9a-f]+:[ ]+74102573[ ]+csrr[ ]+a0,mnepc +[ ]+[0-9a-f]+:[ ]+74159073[ ]+csrw[ ]+mnepc,a1 +[ ]+[0-9a-f]+:[ ]+74202573[ ]+csrr[ ]+a0,mncause +[ ]+[0-9a-f]+:[ ]+74259073[ ]+csrw[ ]+mncause,a1 +[ ]+[0-9a-f]+:[ ]+74402573[ ]+csrr[ ]+a0,mnstatus +[ ]+[0-9a-f]+:[ ]+74459073[ ]+csrw[ ]+mnstatus,a1 [ ]+[0-9a-f]+:[ ]+30c02573[ ]+csrr[ ]+a0,mstateen0 [ ]+[0-9a-f]+:[ ]+30c59073[ ]+csrw[ ]+mstateen0,a1 [ ]+[0-9a-f]+:[ ]+30d02573[ ]+csrr[ ]+a0,mstateen1 diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.l b/gas/testsuite/gas/riscv/csr-version-1p11.l index ba497228d7f..d9d6f15cf69 100644 --- a/gas/testsuite/gas/riscv/csr-version-1p11.l +++ b/gas/testsuite/gas/riscv/csr-version-1p11.l @@ -885,6 +885,22 @@ .*Info: macro .* .*Warning: invalid CSR `miph', needs `smaia' extension .*Info: macro .* +.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension +.*Info: macro .* +.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension +.*Info: macro .* +.*Warning: invalid CSR `mnepc', needs `smrnmi' extension +.*Info: macro .* +.*Warning: invalid CSR `mnepc', needs `smrnmi' extension +.*Info: macro .* +.*Warning: invalid CSR `mncause', needs `smrnmi' extension +.*Info: macro .* +.*Warning: invalid CSR `mncause', needs `smrnmi' extension +.*Info: macro .* +.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension +.*Info: macro .* +.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension +.*Info: macro .* .*Warning: invalid CSR `mstateen0', needs `smstateen' extension .*Info: macro .* .*Warning: invalid CSR `mstateen0', needs `smstateen' extension diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.d b/gas/testsuite/gas/riscv/csr-version-1p12.d index 612aac28076..e39473062d5 100644 --- a/gas/testsuite/gas/riscv/csr-version-1p12.d +++ b/gas/testsuite/gas/riscv/csr-version-1p12.d @@ -623,6 +623,14 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+31959073[ ]+csrw[ ]+mviph,a1 [ ]+[0-9a-f]+:[ ]+35402573[ ]+csrr[ ]+a0,miph [ ]+[0-9a-f]+:[ ]+35459073[ ]+csrw[ ]+miph,a1 +[ ]+[0-9a-f]+:[ ]+74002573[ ]+csrr[ ]+a0,mnscratch +[ ]+[0-9a-f]+:[ ]+74059073[ ]+csrw[ ]+mnscratch,a1 +[ ]+[0-9a-f]+:[ ]+74102573[ ]+csrr[ ]+a0,mnepc +[ ]+[0-9a-f]+:[ ]+74159073[ ]+csrw[ ]+mnepc,a1 +[ ]+[0-9a-f]+:[ ]+74202573[ ]+csrr[ ]+a0,mncause +[ ]+[0-9a-f]+:[ ]+74259073[ ]+csrw[ ]+mncause,a1 +[ ]+[0-9a-f]+:[ ]+74402573[ ]+csrr[ ]+a0,mnstatus +[ ]+[0-9a-f]+:[ ]+74459073[ ]+csrw[ ]+mnstatus,a1 [ ]+[0-9a-f]+:[ ]+30c02573[ ]+csrr[ ]+a0,mstateen0 [ ]+[0-9a-f]+:[ ]+30c59073[ ]+csrw[ ]+mstateen0,a1 [ ]+[0-9a-f]+:[ ]+30d02573[ ]+csrr[ ]+a0,mstateen1 diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.l b/gas/testsuite/gas/riscv/csr-version-1p12.l index bdebea22334..b404e7d2eec 100644 --- a/gas/testsuite/gas/riscv/csr-version-1p12.l +++ b/gas/testsuite/gas/riscv/csr-version-1p12.l @@ -609,6 +609,22 @@ .*Info: macro .* .*Warning: invalid CSR `miph', needs `smaia' extension .*Info: macro .* +.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension +.*Info: macro .* +.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension +.*Info: macro .* +.*Warning: invalid CSR `mnepc', needs `smrnmi' extension +.*Info: macro .* +.*Warning: invalid CSR `mnepc', needs `smrnmi' extension +.*Info: macro .* +.*Warning: invalid CSR `mncause', needs `smrnmi' extension +.*Info: macro .* +.*Warning: invalid CSR `mncause', needs `smrnmi' extension +.*Info: macro .* +.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension +.*Info: macro .* +.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension +.*Info: macro .* .*Warning: invalid CSR `mstateen0', needs `smstateen' extension .*Info: macro .* .*Warning: invalid CSR `mstateen0', needs `smstateen' extension diff --git a/gas/testsuite/gas/riscv/csr-version-1p9p1.d b/gas/testsuite/gas/riscv/csr-version-1p9p1.d index 0fe849c269c..819292888aa 100644 --- a/gas/testsuite/gas/riscv/csr-version-1p9p1.d +++ b/gas/testsuite/gas/riscv/csr-version-1p9p1.d @@ -623,6 +623,14 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+31959073[ ]+csrw[ ]+mviph,a1 [ ]+[0-9a-f]+:[ ]+35402573[ ]+csrr[ ]+a0,miph [ ]+[0-9a-f]+:[ ]+35459073[ ]+csrw[ ]+miph,a1 +[ ]+[0-9a-f]+:[ ]+74002573[ ]+csrr[ ]+a0,mnscratch +[ ]+[0-9a-f]+:[ ]+74059073[ ]+csrw[ ]+mnscratch,a1 +[ ]+[0-9a-f]+:[ ]+74102573[ ]+csrr[ ]+a0,mnepc +[ ]+[0-9a-f]+:[ ]+74159073[ ]+csrw[ ]+mnepc,a1 +[ ]+[0-9a-f]+:[ ]+74202573[ ]+csrr[ ]+a0,mncause +[ ]+[0-9a-f]+:[ ]+74259073[ ]+csrw[ ]+mncause,a1 +[ ]+[0-9a-f]+:[ ]+74402573[ ]+csrr[ ]+a0,mnstatus +[ ]+[0-9a-f]+:[ ]+74459073[ ]+csrw[ ]+mnstatus,a1 [ ]+[0-9a-f]+:[ ]+30c02573[ ]+csrr[ ]+a0,mstateen0 [ ]+[0-9a-f]+:[ ]+30c59073[ ]+csrw[ ]+mstateen0,a1 [ ]+[0-9a-f]+:[ ]+30d02573[ ]+csrr[ ]+a0,mstateen1 diff --git a/gas/testsuite/gas/riscv/csr-version-1p9p1.l b/gas/testsuite/gas/riscv/csr-version-1p9p1.l index 49bd95954e2..a4092f51d26 100644 --- a/gas/testsuite/gas/riscv/csr-version-1p9p1.l +++ b/gas/testsuite/gas/riscv/csr-version-1p9p1.l @@ -989,6 +989,22 @@ .*Info: macro .* .*Warning: invalid CSR `miph', needs `smaia' extension .*Info: macro .* +.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension +.*Info: macro .* +.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension +.*Info: macro .* +.*Warning: invalid CSR `mnepc', needs `smrnmi' extension +.*Info: macro .* +.*Warning: invalid CSR `mnepc', needs `smrnmi' extension +.*Info: macro .* +.*Warning: invalid CSR `mncause', needs `smrnmi' extension +.*Info: macro .* +.*Warning: invalid CSR `mncause', needs `smrnmi' extension +.*Info: macro .* +.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension +.*Info: macro .* +.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension +.*Info: macro .* .*Warning: invalid CSR `mstateen0', needs `smstateen' extension .*Info: macro .* .*Warning: invalid CSR `mstateen0', needs `smstateen' extension diff --git a/gas/testsuite/gas/riscv/csr.s b/gas/testsuite/gas/riscv/csr.s index c7406ce34c2..3508c42f623 100644 --- a/gas/testsuite/gas/riscv/csr.s +++ b/gas/testsuite/gas/riscv/csr.s @@ -350,6 +350,12 @@ csr mviph csr miph + # Smrnmi extension + csr mnscratch + csr mnepc + csr mncause + csr mnstatus + # Smstateen/Ssstateen extensions csr mstateen0 csr mstateen1 diff --git a/gas/testsuite/gas/riscv/smrnmi-noarch.d b/gas/testsuite/gas/riscv/smrnmi-noarch.d new file mode 100644 index 00000000000..d28da973630 --- /dev/null +++ b/gas/testsuite/gas/riscv/smrnmi-noarch.d @@ -0,0 +1,3 @@ +#as: -march=rv32i +#source: smrnmi.s +#error_output: smrnmi-noarch.l diff --git a/gas/testsuite/gas/riscv/smrnmi-noarch.l b/gas/testsuite/gas/riscv/smrnmi-noarch.l new file mode 100644 index 00000000000..1ad5141c124 --- /dev/null +++ b/gas/testsuite/gas/riscv/smrnmi-noarch.l @@ -0,0 +1,2 @@ +.*: Assembler messages: +.*: Error: unrecognized opcode `mnret', extension `smrnmi' required diff --git a/gas/testsuite/gas/riscv/smrnmi.d b/gas/testsuite/gas/riscv/smrnmi.d new file mode 100644 index 00000000000..2b628e91a10 --- /dev/null +++ b/gas/testsuite/gas/riscv/smrnmi.d @@ -0,0 +1,10 @@ +#as: -march=rv32i_smrnmi +#source: smrnmi.s +#objdump: -d + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 : +[ ]+[0-9a-f]+:[ ]+70200073[ ]+mnret diff --git a/gas/testsuite/gas/riscv/smrnmi.s b/gas/testsuite/gas/riscv/smrnmi.s new file mode 100644 index 00000000000..f2008bd8704 --- /dev/null +++ b/gas/testsuite/gas/riscv/smrnmi.s @@ -0,0 +1,2 @@ +target: + mnret diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 53f5f200508..2f837346dc2 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2235,6 +2235,9 @@ #define MASK_C_NOT 0xfc7f #define MATCH_C_MUL 0x9c41 #define MASK_C_MUL 0xfc63 +/* Smrnmi instruction. */ +#define MATCH_MNRET 0x70200073 +#define MASK_MNRET 0xffffffff /* Svinval instruction. */ #define MATCH_SINVAL_VMA 0x16000073 #define MASK_SINVAL_VMA 0xfe007fff @@ -2863,6 +2866,11 @@ #define CSR_MVIENH 0x318 #define CSR_MVIPH 0x319 #define CSR_MIPH 0x354 +/* Smrnmi extension CSR addresses. */ +#define CSR_MNSCRATCH 0x740 +#define CSR_MNEPC 0x741 +#define CSR_MNCAUSE 0x742 +#define CSR_MNSTATUS 0x744 /* Smstateen extension */ #define CSR_MSTATEEN0 0x30c #define CSR_MSTATEEN1 0x30d @@ -3329,6 +3337,8 @@ DECLARE_INSN(hsv_b, MATCH_HSV_B, MASK_HSV_B) DECLARE_INSN(hsv_h, MATCH_HSV_H, MASK_HSV_H) DECLARE_INSN(hsv_w, MATCH_HSV_W, MASK_HSV_W) DECLARE_INSN(hsv_d, MATCH_HSV_D, MASK_HSV_D) +/* Smrnmi instructions. */ +DECLARE_INSN(mnret, MATCH_MNRET, MASK_MNRET) /* Zicbop instructions. */ DECLARE_INSN(prefetch_r, MATCH_PREFETCH_R, MASK_PREFETCH_R); DECLARE_INSN(prefetch_w, MATCH_PREFETCH_W, MASK_PREFETCH_W); @@ -3840,6 +3850,11 @@ DECLARE_CSR(mieh, CSR_MIEH, CSR_CLASS_SMAIA_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_ DECLARE_CSR(mvienh, CSR_MVIENH, CSR_CLASS_SMAIA_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) DECLARE_CSR(mviph, CSR_MVIPH, CSR_CLASS_SMAIA_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) DECLARE_CSR(miph, CSR_MIPH, CSR_CLASS_SMAIA_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +/* Smrnmi extension CSRs. */ +DECLARE_CSR(mnscratch, CSR_MNSCRATCH, CSR_CLASS_SMRNMI, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mnepc, CSR_MNEPC, CSR_CLASS_SMRNMI, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mncause, CSR_MNCAUSE, CSR_CLASS_SMRNMI, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mnstatus, CSR_MNSTATUS, CSR_CLASS_SMRNMI, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) /* Smstateen/Ssstateen extensions. */ DECLARE_CSR(mstateen0, CSR_MSTATEEN0, CSR_CLASS_SMSTATEEN, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) DECLARE_CSR(mstateen1, CSR_MSTATEEN1, CSR_CLASS_SMSTATEEN, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 808f3657303..4985f32c9fd 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -435,6 +435,7 @@ enum riscv_insn_class INSN_CLASS_ZCB_AND_ZBA, INSN_CLASS_ZCB_AND_ZBB, INSN_CLASS_ZCB_AND_ZMMUL, + INSN_CLASS_SMRNMI, INSN_CLASS_SVINVAL, INSN_CLASS_ZICBOM, INSN_CLASS_ZICBOP, diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 6a854736fec..6c168e6d97e 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -1999,6 +1999,9 @@ const struct riscv_opcode riscv_opcodes[] = {"sfence.vma", 0, INSN_CLASS_I, "s,t", MATCH_SFENCE_VMA, MASK_SFENCE_VMA, match_opcode, 0 }, {"wfi", 0, INSN_CLASS_I, "", MATCH_WFI, MASK_WFI, match_opcode, 0 }, +/* Smrnmi instructions. */ +{"mnret", 0, INSN_CLASS_SMRNMI, "", MATCH_MNRET, MASK_MNRET, match_opcode, 0 }, + /* Svinval instructions. */ {"sinval.vma", 0, INSN_CLASS_SVINVAL, "s,t", MATCH_SINVAL_VMA, MASK_SINVAL_VMA, match_opcode, 0 }, {"sfence.w.inval", 0, INSN_CLASS_SVINVAL, "", MATCH_SFENCE_W_INVAL, MASK_SFENCE_W_INVAL, match_opcode, 0 },