diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index c67d4167232..f795da19149 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -2338,6 +2338,10 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
     case INSN_CLASS_Q_OR_ZQINX:
       return (riscv_subset_supports (rps, "q")
 	      || riscv_subset_supports (rps, "zqinx"));
+    case INSN_CLASS_ZDINX:
+      return riscv_subset_supports (rps, "zdinx");
+    case INSN_CLASS_ZQINX:
+      return riscv_subset_supports (rps, "zqinx");
     case INSN_CLASS_ZFH_OR_ZHINX:
       return (riscv_subset_supports (rps, "zfh")
 	      || riscv_subset_supports (rps, "zhinx"));
@@ -2346,16 +2350,28 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
     case INSN_CLASS_ZFHMIN_OR_ZHINXMIN:
       return (riscv_subset_supports (rps, "zfhmin")
 	      || riscv_subset_supports (rps, "zhinxmin"));
-    case INSN_CLASS_ZFHMIN_AND_D:
+    case INSN_CLASS_ZFHMIN_AND_D_OR_X:
       return ((riscv_subset_supports (rps, "zfhmin")
 	       && riscv_subset_supports (rps, "d"))
 	      || (riscv_subset_supports (rps, "zhinxmin")
 		  && riscv_subset_supports (rps, "zdinx")));
-    case INSN_CLASS_ZFHMIN_AND_Q:
+    case INSN_CLASS_ZFHMIN_AND_Q_OR_X:
       return ((riscv_subset_supports (rps, "zfhmin")
 	       && riscv_subset_supports (rps, "q"))
 	      || (riscv_subset_supports (rps, "zhinxmin")
 		  && riscv_subset_supports (rps, "zqinx")));
+    case INSN_CLASS_ZFHMIN_AND_D:
+      return ((riscv_subset_supports (rps, "zfhmin")
+	       && riscv_subset_supports (rps, "d")));
+    case INSN_CLASS_ZFHMIN_AND_Q:
+      return ((riscv_subset_supports (rps, "zfhmin")
+	       && riscv_subset_supports (rps, "q")));
+    case INSN_CLASS_ZHINXMIN_AND_ZDINX:
+      return (riscv_subset_supports (rps, "zhinxmin")
+	      && riscv_subset_supports (rps, "zdinx"));
+    case INSN_CLASS_ZHINXMIN_AND_ZQINX:
+      return (riscv_subset_supports (rps, "zhinxmin")
+	      && riscv_subset_supports (rps, "zqinx"));
     case INSN_CLASS_ZBA:
       return riscv_subset_supports (rps, "zba");
     case INSN_CLASS_ZBB:
@@ -2485,13 +2501,17 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return _("d' or `zdinx");
     case INSN_CLASS_Q_OR_ZQINX:
       return _("q' or `zqinx");
+    case INSN_CLASS_ZDINX:
+      return "zdinx";
+    case INSN_CLASS_ZQINX:
+      return "zqinx";
     case INSN_CLASS_ZFH_OR_ZHINX:
       return _("zfh' or `zhinx");
     case INSN_CLASS_ZFHMIN:
       return "zfhmin";
     case INSN_CLASS_ZFHMIN_OR_ZHINXMIN:
       return _("zfhmin' or `zhinxmin");
-    case INSN_CLASS_ZFHMIN_AND_D:
+    case INSN_CLASS_ZFHMIN_AND_D_OR_X:
       if (riscv_subset_supports (rps, "zfhmin"))
 	return "d";
       else if (riscv_subset_supports (rps, "d"))
@@ -2502,7 +2522,7 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
 	return "zhinxmin";
       else
 	return _("zfhmin' and `d', or `zhinxmin' and `zdinx");
-    case INSN_CLASS_ZFHMIN_AND_Q:
+    case INSN_CLASS_ZFHMIN_AND_Q_OR_X:
       if (riscv_subset_supports (rps, "zfhmin"))
 	return "q";
       else if (riscv_subset_supports (rps, "q"))
@@ -2513,6 +2533,38 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
 	return "zhinxmin";
       else
 	return _("zfhmin' and `q', or `zhinxmin' and `zqinx");
+    case INSN_CLASS_ZFHMIN_AND_D:
+      if (!riscv_subset_supports (rps, "zfhmin")
+	  && !riscv_subset_supports (rps, "d"))
+	return _("zfhmin' and `d");
+      else if (!riscv_subset_supports (rps, "zfhmin"))
+	return "zfhmin";
+      else
+	return "d";
+    case INSN_CLASS_ZFHMIN_AND_Q:
+      if (!riscv_subset_supports (rps, "zfhmin")
+	  && !riscv_subset_supports (rps, "q"))
+	return _("zfhmin' and `q");
+      else if (!riscv_subset_supports (rps, "zfhmin"))
+	return "zfhmin";
+      else
+	return "q";
+    case INSN_CLASS_ZHINXMIN_AND_ZDINX:
+      if (!riscv_subset_supports (rps, "zhinxmin")
+	  && !riscv_subset_supports (rps, "zdinx"))
+	return _("zhinxmin' and `zdinx");
+      else if (!riscv_subset_supports (rps, "zhinxmin"))
+	return "zhinxmin";
+      else
+	return "zdinx";
+    case INSN_CLASS_ZHINXMIN_AND_ZQINX:
+      if (!riscv_subset_supports (rps, "zhinxmin")
+	  && !riscv_subset_supports (rps, "zqinx"))
+	return _("zhinxmin' and `zqinx");
+      else if (!riscv_subset_supports (rps, "zhinxmin"))
+	return "zhinxmin";
+      else
+	return "zqinx";
     case INSN_CLASS_ZBA:
       return "zba";
     case INSN_CLASS_ZBB:
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index f83b0ff3dad..8d464b64bc6 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -2420,6 +2420,22 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
 	      */
 	      switch (insn_class)
 		{
+		case INSN_CLASS_D:
+		case INSN_CLASS_ZDINX:
+		  insn_class = INSN_CLASS_D_OR_ZDINX;
+		  break;
+		case INSN_CLASS_Q:
+		case INSN_CLASS_ZQINX:
+		  insn_class = INSN_CLASS_Q_OR_ZQINX;
+		  break;
+		case INSN_CLASS_ZFHMIN_AND_D:
+		case INSN_CLASS_ZHINXMIN_AND_ZDINX:
+		  insn_class = INSN_CLASS_ZFHMIN_AND_D_OR_X;
+		  break;
+		case INSN_CLASS_ZFHMIN_AND_Q:
+		case INSN_CLASS_ZHINXMIN_AND_ZQINX:
+		  insn_class = INSN_CLASS_ZFHMIN_AND_Q_OR_X;
+		  break;
 		default:
 		  break;
 		}
diff --git a/gas/testsuite/gas/riscv/zdinx-32-regpair-dis.d b/gas/testsuite/gas/riscv/zdinx-32-regpair-dis.d
new file mode 100644
index 00000000000..dc5ccb1b342
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zdinx-32-regpair-dis.d
@@ -0,0 +1,10 @@
+#as: -march=rv32i_zdinx
+#objdump: -dr -Mnumeric
+
+.*:[ 	]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+02627153[ 	]+fadd.d[ 	]+x2,x4,x6
+[ 	]+[0-9a-f]+:[ 	]+0272f1d3[ 	]+fadd.d[ 	]+invalid3,invalid5,invalid7
diff --git a/gas/testsuite/gas/riscv/zdinx-32-regpair-dis.s b/gas/testsuite/gas/riscv/zdinx-32-regpair-dis.s
new file mode 100644
index 00000000000..5c28ca7cdc9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zdinx-32-regpair-dis.s
@@ -0,0 +1,5 @@
+target:
+	# fadd.d x2, x4, x6
+	.insn r	OP_FP, 0x7, 0x01, x2, x4, x6
+	# fadd.d x3, x5, x7 (invalid)
+	.insn r	OP_FP, 0x7, 0x01, x3, x5, x7
diff --git a/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.d b/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.d
new file mode 100644
index 00000000000..f4ef42e6bc3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.d
@@ -0,0 +1,2 @@
+#as: -march=rv32i_zdinx
+#error_output: zdinx-32-regpair-fail.l
diff --git a/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.l b/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.l
new file mode 100644
index 00000000000..ce4a8eaa42a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.l
@@ -0,0 +1,111 @@
+.*Assembler messages:
+.*Error: illegal operands `fadd\.d a1,a2,a4'
+.*Error: illegal operands `fadd\.d a1,a2,a4,rne'
+.*Error: illegal operands `fadd\.d a0,a1,a4'
+.*Error: illegal operands `fadd\.d a0,a1,a4,rne'
+.*Error: illegal operands `fadd\.d a0,a2,a1'
+.*Error: illegal operands `fadd\.d a0,a2,a1,rne'
+.*Error: illegal operands `fsub\.d a1,a2,a4'
+.*Error: illegal operands `fsub\.d a1,a2,a4,rne'
+.*Error: illegal operands `fsub\.d a0,a1,a4'
+.*Error: illegal operands `fsub\.d a0,a1,a4,rne'
+.*Error: illegal operands `fsub\.d a0,a2,a1'
+.*Error: illegal operands `fsub\.d a0,a2,a1,rne'
+.*Error: illegal operands `fmul\.d a1,a2,a4'
+.*Error: illegal operands `fmul\.d a1,a2,a4,rne'
+.*Error: illegal operands `fmul\.d a0,a1,a4'
+.*Error: illegal operands `fmul\.d a0,a1,a4,rne'
+.*Error: illegal operands `fmul\.d a0,a2,a1'
+.*Error: illegal operands `fmul\.d a0,a2,a1,rne'
+.*Error: illegal operands `fdiv\.d a1,a2,a4'
+.*Error: illegal operands `fdiv\.d a1,a2,a4,rne'
+.*Error: illegal operands `fdiv\.d a0,a1,a4'
+.*Error: illegal operands `fdiv\.d a0,a1,a4,rne'
+.*Error: illegal operands `fdiv\.d a0,a2,a1'
+.*Error: illegal operands `fdiv\.d a0,a2,a1,rne'
+.*Error: illegal operands `fsqrt\.d a1,a2'
+.*Error: illegal operands `fsqrt\.d a1,a2,rne'
+.*Error: illegal operands `fsqrt\.d a0,a1'
+.*Error: illegal operands `fsqrt\.d a0,a1,rne'
+.*Error: illegal operands `fmin\.d a1,a2,a4'
+.*Error: illegal operands `fmin\.d a0,a1,a4'
+.*Error: illegal operands `fmin\.d a0,a2,a1'
+.*Error: illegal operands `fmax\.d a1,a2,a4'
+.*Error: illegal operands `fmax\.d a0,a1,a4'
+.*Error: illegal operands `fmax\.d a0,a2,a1'
+.*Error: illegal operands `fmadd\.d a1,a2,a4,a6'
+.*Error: illegal operands `fmadd\.d a1,a2,a4,a6,rne'
+.*Error: illegal operands `fmadd\.d a0,a1,a4,a6'
+.*Error: illegal operands `fmadd\.d a0,a1,a4,a6,rne'
+.*Error: illegal operands `fmadd\.d a0,a2,a1,a6'
+.*Error: illegal operands `fmadd\.d a0,a2,a1,a6,rne'
+.*Error: illegal operands `fmadd\.d a0,a2,a4,a1'
+.*Error: illegal operands `fmadd\.d a0,a2,a4,a1,rne'
+.*Error: illegal operands `fnmadd\.d a1,a2,a4,a6'
+.*Error: illegal operands `fnmadd\.d a1,a2,a4,a6,rne'
+.*Error: illegal operands `fnmadd\.d a0,a1,a4,a6'
+.*Error: illegal operands `fnmadd\.d a0,a1,a4,a6,rne'
+.*Error: illegal operands `fnmadd\.d a0,a2,a1,a6'
+.*Error: illegal operands `fnmadd\.d a0,a2,a1,a6,rne'
+.*Error: illegal operands `fnmadd\.d a0,a2,a4,a1'
+.*Error: illegal operands `fnmadd\.d a0,a2,a4,a1,rne'
+.*Error: illegal operands `fmsub\.d a1,a2,a4,a6'
+.*Error: illegal operands `fmsub\.d a1,a2,a4,a6,rne'
+.*Error: illegal operands `fmsub\.d a0,a1,a4,a6'
+.*Error: illegal operands `fmsub\.d a0,a1,a4,a6,rne'
+.*Error: illegal operands `fmsub\.d a0,a2,a1,a6'
+.*Error: illegal operands `fmsub\.d a0,a2,a1,a6,rne'
+.*Error: illegal operands `fmsub\.d a0,a2,a4,a1'
+.*Error: illegal operands `fmsub\.d a0,a2,a4,a1,rne'
+.*Error: illegal operands `fnmsub\.d a1,a2,a4,a6'
+.*Error: illegal operands `fnmsub\.d a1,a2,a4,a6,rne'
+.*Error: illegal operands `fnmsub\.d a0,a1,a4,a6'
+.*Error: illegal operands `fnmsub\.d a0,a1,a4,a6,rne'
+.*Error: illegal operands `fnmsub\.d a0,a2,a1,a6'
+.*Error: illegal operands `fnmsub\.d a0,a2,a1,a6,rne'
+.*Error: illegal operands `fnmsub\.d a0,a2,a4,a1'
+.*Error: illegal operands `fnmsub\.d a0,a2,a4,a1,rne'
+.*Error: illegal operands `fsgnj\.d a1,a2,a4'
+.*Error: illegal operands `fsgnj\.d a0,a1,a4'
+.*Error: illegal operands `fsgnj\.d a0,a2,a1'
+.*Error: illegal operands `fsgnjn\.d a1,a2,a4'
+.*Error: illegal operands `fsgnjn\.d a0,a1,a4'
+.*Error: illegal operands `fsgnjn\.d a0,a2,a1'
+.*Error: illegal operands `fsgnjx\.d a1,a2,a4'
+.*Error: illegal operands `fsgnjx\.d a0,a1,a4'
+.*Error: illegal operands `fsgnjx\.d a0,a2,a1'
+.*Error: illegal operands `fmv\.d a1,a2'
+.*Error: illegal operands `fmv\.d a0,a1'
+.*Error: illegal operands `fneg\.d a1,a2'
+.*Error: illegal operands `fneg\.d a0,a1'
+.*Error: illegal operands `fabs\.d a1,a2'
+.*Error: illegal operands `fabs\.d a0,a1'
+.*Error: illegal operands `feq\.d a0,a1,a4'
+.*Error: illegal operands `feq\.d a0,a2,a1'
+.*Error: illegal operands `flt\.d a0,a1,a4'
+.*Error: illegal operands `flt\.d a0,a2,a1'
+.*Error: illegal operands `fle\.d a0,a1,a4'
+.*Error: illegal operands `fle\.d a0,a2,a1'
+.*Error: illegal operands `fgt\.d a0,a1,a4'
+.*Error: illegal operands `fgt\.d a0,a2,a1'
+.*Error: illegal operands `fge\.d a0,a1,a4'
+.*Error: illegal operands `fge\.d a0,a2,a1'
+.*Error: illegal operands `fclass\.d a0,a1'
+.*Error: illegal operands `fcvt\.w\.d a0,a1'
+.*Error: illegal operands `fcvt\.w\.d a0,a1,rne'
+.*Error: illegal operands `fcvt\.w\.d a3,a1'
+.*Error: illegal operands `fcvt\.w\.d a3,a1,rne'
+.*Error: illegal operands `fcvt\.wu\.d a0,a1'
+.*Error: illegal operands `fcvt\.wu\.d a0,a1,rne'
+.*Error: illegal operands `fcvt\.wu\.d a3,a1'
+.*Error: illegal operands `fcvt\.wu\.d a3,a1,rne'
+.*Error: illegal operands `fcvt\.d\.w a1,a2'
+.*Error: illegal operands `fcvt\.d\.w a1,a3'
+.*Error: illegal operands `fcvt\.d\.wu a1,a2'
+.*Error: illegal operands `fcvt\.d\.wu a1,a3'
+.*Error: illegal operands `fcvt\.s\.d a0,a1'
+.*Error: illegal operands `fcvt\.s\.d a0,a1,rne'
+.*Error: illegal operands `fcvt\.s\.d a3,a1'
+.*Error: illegal operands `fcvt\.s\.d a3,a1,rne'
+.*Error: illegal operands `fcvt\.d\.s a1,a2'
+.*Error: illegal operands `fcvt\.d\.s a1,a3'
diff --git a/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.s b/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.s
new file mode 100644
index 00000000000..2243d89a6d3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.s
@@ -0,0 +1,116 @@
+target:
+	fadd.d	a1, a2, a4
+	fadd.d	a1, a2, a4, rne
+	fadd.d	a0, a1, a4
+	fadd.d	a0, a1, a4, rne
+	fadd.d	a0, a2, a1
+	fadd.d	a0, a2, a1, rne
+	fsub.d	a1, a2, a4
+	fsub.d	a1, a2, a4, rne
+	fsub.d	a0, a1, a4
+	fsub.d	a0, a1, a4, rne
+	fsub.d	a0, a2, a1
+	fsub.d	a0, a2, a1, rne
+	fmul.d	a1, a2, a4
+	fmul.d	a1, a2, a4, rne
+	fmul.d	a0, a1, a4
+	fmul.d	a0, a1, a4, rne
+	fmul.d	a0, a2, a1
+	fmul.d	a0, a2, a1, rne
+	fdiv.d	a1, a2, a4
+	fdiv.d	a1, a2, a4, rne
+	fdiv.d	a0, a1, a4
+	fdiv.d	a0, a1, a4, rne
+	fdiv.d	a0, a2, a1
+	fdiv.d	a0, a2, a1, rne
+	fsqrt.d	a1, a2
+	fsqrt.d	a1, a2, rne
+	fsqrt.d	a0, a1
+	fsqrt.d	a0, a1, rne
+	fmin.d	a1, a2, a4
+	fmin.d	a0, a1, a4
+	fmin.d	a0, a2, a1
+	fmax.d	a1, a2, a4
+	fmax.d	a0, a1, a4
+	fmax.d	a0, a2, a1
+	fmadd.d	a1, a2, a4, a6
+	fmadd.d	a1, a2, a4, a6, rne
+	fmadd.d	a0, a1, a4, a6
+	fmadd.d	a0, a1, a4, a6, rne
+	fmadd.d	a0, a2, a1, a6
+	fmadd.d	a0, a2, a1, a6, rne
+	fmadd.d	a0, a2, a4, a1
+	fmadd.d	a0, a2, a4, a1, rne
+	fnmadd.d	a1, a2, a4, a6
+	fnmadd.d	a1, a2, a4, a6, rne
+	fnmadd.d	a0, a1, a4, a6
+	fnmadd.d	a0, a1, a4, a6, rne
+	fnmadd.d	a0, a2, a1, a6
+	fnmadd.d	a0, a2, a1, a6, rne
+	fnmadd.d	a0, a2, a4, a1
+	fnmadd.d	a0, a2, a4, a1, rne
+	fmsub.d	a1, a2, a4, a6
+	fmsub.d	a1, a2, a4, a6, rne
+	fmsub.d	a0, a1, a4, a6
+	fmsub.d	a0, a1, a4, a6, rne
+	fmsub.d	a0, a2, a1, a6
+	fmsub.d	a0, a2, a1, a6, rne
+	fmsub.d	a0, a2, a4, a1
+	fmsub.d	a0, a2, a4, a1, rne
+	fnmsub.d	a1, a2, a4, a6
+	fnmsub.d	a1, a2, a4, a6, rne
+	fnmsub.d	a0, a1, a4, a6
+	fnmsub.d	a0, a1, a4, a6, rne
+	fnmsub.d	a0, a2, a1, a6
+	fnmsub.d	a0, a2, a1, a6, rne
+	fnmsub.d	a0, a2, a4, a1
+	fnmsub.d	a0, a2, a4, a1, rne
+	fsgnj.d	a1, a2, a4
+	fsgnj.d	a0, a1, a4
+	fsgnj.d	a0, a2, a1
+	fsgnjn.d	a1, a2, a4
+	fsgnjn.d	a0, a1, a4
+	fsgnjn.d	a0, a2, a1
+	fsgnjx.d	a1, a2, a4
+	fsgnjx.d	a0, a1, a4
+	fsgnjx.d	a0, a2, a1
+	fmv.d	a1, a2
+	fmv.d	a0, a1
+	fneg.d	a1, a2
+	fneg.d	a0, a1
+	fabs.d	a1, a2
+	fabs.d	a0, a1
+	# Compare instructions: destination is a GPR
+	feq.d	a0, a1, a4
+	feq.d	a0, a2, a1
+	flt.d	a0, a1, a4
+	flt.d	a0, a2, a1
+	fle.d	a0, a1, a4
+	fle.d	a0, a2, a1
+	fgt.d	a0, a1, a4
+	fgt.d	a0, a2, a1
+	fge.d	a0, a1, a4
+	fge.d	a0, a2, a1
+	# fclass instruction: destination is a GPR
+	fclass.d	a0, a1
+	# fcvt instructions (float-int or int-float;
+	#                    integer operand register can be odd)
+	fcvt.w.d	a0, a1
+	fcvt.w.d	a0, a1, rne
+	fcvt.w.d	a3, a1
+	fcvt.w.d	a3, a1, rne
+	fcvt.wu.d	a0, a1
+	fcvt.wu.d	a0, a1, rne
+	fcvt.wu.d	a3, a1
+	fcvt.wu.d	a3, a1, rne
+	fcvt.d.w	a1, a2
+	fcvt.d.w	a1, a3
+	fcvt.d.wu	a1, a2
+	fcvt.d.wu	a1, a3
+	# fcvt instructions (float-float; FP32 operand can be odd)
+	fcvt.s.d	a0, a1
+	fcvt.s.d	a0, a1, rne
+	fcvt.s.d	a3, a1
+	fcvt.s.d	a3, a1, rne
+	fcvt.d.s	a1, a2
+	fcvt.d.s	a1, a3
diff --git a/gas/testsuite/gas/riscv/zdinx-32-regpair.d b/gas/testsuite/gas/riscv/zdinx-32-regpair.d
new file mode 100644
index 00000000000..ffbfa662854
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zdinx-32-regpair.d
@@ -0,0 +1,64 @@
+#as: -march=rv32i_zdinx
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+02e67553[ 	]+fadd.d[ 	]+a0,a2,a4
+[ 	]+[0-9a-f]+:[ 	]+02e60553[ 	]+fadd.d[ 	]+a0,a2,a4,rne
+[ 	]+[0-9a-f]+:[ 	]+0ae67553[ 	]+fsub.d[ 	]+a0,a2,a4
+[ 	]+[0-9a-f]+:[ 	]+0ae60553[ 	]+fsub.d[ 	]+a0,a2,a4,rne
+[ 	]+[0-9a-f]+:[ 	]+12e67553[ 	]+fmul.d[ 	]+a0,a2,a4
+[ 	]+[0-9a-f]+:[ 	]+12e60553[ 	]+fmul.d[ 	]+a0,a2,a4,rne
+[ 	]+[0-9a-f]+:[ 	]+1ae67553[ 	]+fdiv.d[ 	]+a0,a2,a4
+[ 	]+[0-9a-f]+:[ 	]+1ae60553[ 	]+fdiv.d[ 	]+a0,a2,a4,rne
+[ 	]+[0-9a-f]+:[ 	]+5a067553[ 	]+fsqrt.d[ 	]+a0,a2
+[ 	]+[0-9a-f]+:[ 	]+5a060553[ 	]+fsqrt.d[ 	]+a0,a2,rne
+[ 	]+[0-9a-f]+:[ 	]+2ae60553[ 	]+fmin.d[ 	]+a0,a2,a4
+[ 	]+[0-9a-f]+:[ 	]+2ae61553[ 	]+fmax.d[ 	]+a0,a2,a4
+[ 	]+[0-9a-f]+:[ 	]+82e67543[ 	]+fmadd.d[ 	]+a0,a2,a4,a6
+[ 	]+[0-9a-f]+:[ 	]+82e60543[ 	]+fmadd.d[ 	]+a0,a2,a4,a6,rne
+[ 	]+[0-9a-f]+:[ 	]+82e6754f[ 	]+fnmadd.d[ 	]+a0,a2,a4,a6
+[ 	]+[0-9a-f]+:[ 	]+82e6054f[ 	]+fnmadd.d[ 	]+a0,a2,a4,a6,rne
+[ 	]+[0-9a-f]+:[ 	]+82e67547[ 	]+fmsub.d[ 	]+a0,a2,a4,a6
+[ 	]+[0-9a-f]+:[ 	]+82e60547[ 	]+fmsub.d[ 	]+a0,a2,a4,a6,rne
+[ 	]+[0-9a-f]+:[ 	]+82e6754b[ 	]+fnmsub.d[ 	]+a0,a2,a4,a6
+[ 	]+[0-9a-f]+:[ 	]+82e6054b[ 	]+fnmsub.d[ 	]+a0,a2,a4,a6,rne
+[ 	]+[0-9a-f]+:[ 	]+22e60553[ 	]+fsgnj.d[ 	]+a0,a2,a4
+[ 	]+[0-9a-f]+:[ 	]+22e61553[ 	]+fsgnjn.d[ 	]+a0,a2,a4
+[ 	]+[0-9a-f]+:[ 	]+22e62553[ 	]+fsgnjx.d[ 	]+a0,a2,a4
+[ 	]+[0-9a-f]+:[ 	]+22c60553[ 	]+fmv.d[ 	]+a0,a2
+[ 	]+[0-9a-f]+:[ 	]+22c61553[ 	]+fneg.d[ 	]+a0,a2
+[ 	]+[0-9a-f]+:[ 	]+22c62553[ 	]+fabs.d[ 	]+a0,a2
+[ 	]+[0-9a-f]+:[ 	]+a2e62553[ 	]+feq.d[ 	]+a0,a2,a4
+[ 	]+[0-9a-f]+:[ 	]+a2e625d3[ 	]+feq.d[ 	]+a1,a2,a4
+[ 	]+[0-9a-f]+:[ 	]+a2e61553[ 	]+flt.d[ 	]+a0,a2,a4
+[ 	]+[0-9a-f]+:[ 	]+a2e615d3[ 	]+flt.d[ 	]+a1,a2,a4
+[ 	]+[0-9a-f]+:[ 	]+a2e60553[ 	]+fle.d[ 	]+a0,a2,a4
+[ 	]+[0-9a-f]+:[ 	]+a2e605d3[ 	]+fle.d[ 	]+a1,a2,a4
+[ 	]+[0-9a-f]+:[ 	]+a2c71553[ 	]+flt.d[ 	]+a0,a4,a2
+[ 	]+[0-9a-f]+:[ 	]+a2c715d3[ 	]+flt.d[ 	]+a1,a4,a2
+[ 	]+[0-9a-f]+:[ 	]+a2c70553[ 	]+fle.d[ 	]+a0,a4,a2
+[ 	]+[0-9a-f]+:[ 	]+a2c705d3[ 	]+fle.d[ 	]+a1,a4,a2
+[ 	]+[0-9a-f]+:[ 	]+e2061553[ 	]+fclass.d[ 	]+a0,a2
+[ 	]+[0-9a-f]+:[ 	]+e20615d3[ 	]+fclass.d[ 	]+a1,a2
+[ 	]+[0-9a-f]+:[ 	]+c2067553[ 	]+fcvt.w.d[ 	]+a0,a2
+[ 	]+[0-9a-f]+:[ 	]+c2060553[ 	]+fcvt.w.d[ 	]+a0,a2,rne
+[ 	]+[0-9a-f]+:[ 	]+c20675d3[ 	]+fcvt.w.d[ 	]+a1,a2
+[ 	]+[0-9a-f]+:[ 	]+c20605d3[ 	]+fcvt.w.d[ 	]+a1,a2,rne
+[ 	]+[0-9a-f]+:[ 	]+c2167553[ 	]+fcvt.wu.d[ 	]+a0,a2
+[ 	]+[0-9a-f]+:[ 	]+c2160553[ 	]+fcvt.wu.d[ 	]+a0,a2,rne
+[ 	]+[0-9a-f]+:[ 	]+c21675d3[ 	]+fcvt.wu.d[ 	]+a1,a2
+[ 	]+[0-9a-f]+:[ 	]+c21605d3[ 	]+fcvt.wu.d[ 	]+a1,a2,rne
+[ 	]+[0-9a-f]+:[ 	]+d2060553[ 	]+fcvt.d.w[ 	]+a0,a2
+[ 	]+[0-9a-f]+:[ 	]+d2058553[ 	]+fcvt.d.w[ 	]+a0,a1
+[ 	]+[0-9a-f]+:[ 	]+d2160553[ 	]+fcvt.d.wu[ 	]+a0,a2
+[ 	]+[0-9a-f]+:[ 	]+d2158553[ 	]+fcvt.d.wu[ 	]+a0,a1
+[ 	]+[0-9a-f]+:[ 	]+40167553[ 	]+fcvt.s.d[ 	]+a0,a2
+[ 	]+[0-9a-f]+:[ 	]+40160553[ 	]+fcvt.s.d[ 	]+a0,a2,rne
+[ 	]+[0-9a-f]+:[ 	]+401675d3[ 	]+fcvt.s.d[ 	]+a1,a2
+[ 	]+[0-9a-f]+:[ 	]+401605d3[ 	]+fcvt.s.d[ 	]+a1,a2,rne
+[ 	]+[0-9a-f]+:[ 	]+42060553[ 	]+fcvt.d.s[ 	]+a0,a2
+[ 	]+[0-9a-f]+:[ 	]+42058553[ 	]+fcvt.d.s[ 	]+a0,a1
diff --git a/gas/testsuite/gas/riscv/zdinx-32-regpair.s b/gas/testsuite/gas/riscv/zdinx-32-regpair.s
new file mode 100644
index 00000000000..cef479a976e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zdinx-32-regpair.s
@@ -0,0 +1,62 @@
+target:
+	fadd.d	a0, a2, a4
+	fadd.d	a0, a2, a4, rne
+	fsub.d	a0, a2, a4
+	fsub.d	a0, a2, a4, rne
+	fmul.d	a0, a2, a4
+	fmul.d	a0, a2, a4, rne
+	fdiv.d	a0, a2, a4
+	fdiv.d	a0, a2, a4, rne
+	fsqrt.d	a0, a2
+	fsqrt.d	a0, a2, rne
+	fmin.d	a0, a2, a4
+	fmax.d	a0, a2, a4
+	fmadd.d	a0, a2, a4, a6
+	fmadd.d	a0, a2, a4, a6, rne
+	fnmadd.d	a0, a2, a4, a6
+	fnmadd.d	a0, a2, a4, a6, rne
+	fmsub.d	a0, a2, a4, a6
+	fmsub.d	a0, a2, a4, a6, rne
+	fnmsub.d	a0, a2, a4, a6
+	fnmsub.d	a0, a2, a4, a6, rne
+	fsgnj.d	a0, a2, a4
+	fsgnjn.d	a0, a2, a4
+	fsgnjx.d	a0, a2, a4
+	fmv.d	a0, a2
+	fneg.d	a0, a2
+	fabs.d	a0, a2
+	# Compare instructions: destination is a GPR
+	feq.d	a0, a2, a4
+	feq.d	a1, a2, a4
+	flt.d	a0, a2, a4
+	flt.d	a1, a2, a4
+	fle.d	a0, a2, a4
+	fle.d	a1, a2, a4
+	fgt.d	a0, a2, a4
+	fgt.d	a1, a2, a4
+	fge.d	a0, a2, a4
+	fge.d	a1, a2, a4
+	# fclass instruction: destination is a GPR
+	fclass.d	a0, a2
+	fclass.d	a1, a2
+	# fcvt instructions (float-int or int-float;
+	#                    integer operand register can be odd)
+	fcvt.w.d	a0, a2
+	fcvt.w.d	a0, a2, rne
+	fcvt.w.d	a1, a2
+	fcvt.w.d	a1, a2, rne
+	fcvt.wu.d	a0, a2
+	fcvt.wu.d	a0, a2, rne
+	fcvt.wu.d	a1, a2
+	fcvt.wu.d	a1, a2, rne
+	fcvt.d.w	a0, a2
+	fcvt.d.w	a0, a1
+	fcvt.d.wu	a0, a2
+	fcvt.d.wu	a0, a1
+	# fcvt instructions (float-float; FP32 operand can be odd)
+	fcvt.s.d	a0, a2
+	fcvt.s.d	a0, a2, rne
+	fcvt.s.d	a1, a2
+	fcvt.s.d	a1, a2, rne
+	fcvt.d.s	a0, a2
+	fcvt.d.s	a0, a1
diff --git a/gas/testsuite/gas/riscv/zdinx-zhinxmin-32-regpair-fail.d b/gas/testsuite/gas/riscv/zdinx-zhinxmin-32-regpair-fail.d
new file mode 100644
index 00000000000..000308590f7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zdinx-zhinxmin-32-regpair-fail.d
@@ -0,0 +1,2 @@
+#as: -march=rv32i_zdinx_zhinxmin
+#error_output: zdinx-zhinxmin-32-regpair-fail.l
diff --git a/gas/testsuite/gas/riscv/zdinx-zhinxmin-32-regpair-fail.l b/gas/testsuite/gas/riscv/zdinx-zhinxmin-32-regpair-fail.l
new file mode 100644
index 00000000000..31d08406546
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zdinx-zhinxmin-32-regpair-fail.l
@@ -0,0 +1,7 @@
+.*Assembler messages:
+.*Error: illegal operands `fcvt\.h\.d a0,a3'
+.*Error: illegal operands `fcvt\.h\.d a1,a3'
+.*Error: illegal operands `fcvt\.h\.d a0,a3,rne'
+.*Error: illegal operands `fcvt\.h\.d a1,a3,rne'
+.*Error: illegal operands `fcvt\.d\.h a3,a0'
+.*Error: illegal operands `fcvt\.d\.h a3,a1'
diff --git a/gas/testsuite/gas/riscv/zdinx-zhinxmin-32-regpair-fail.s b/gas/testsuite/gas/riscv/zdinx-zhinxmin-32-regpair-fail.s
new file mode 100644
index 00000000000..eee52b98948
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zdinx-zhinxmin-32-regpair-fail.s
@@ -0,0 +1,8 @@
+target:
+	# fcvt instructions (float-float; FP16 operand can be odd)
+	fcvt.h.d	a0, a3
+	fcvt.h.d	a1, a3
+	fcvt.h.d	a0, a3, rne
+	fcvt.h.d	a1, a3, rne
+	fcvt.d.h	a3, a0
+	fcvt.d.h	a3, a1
diff --git a/gas/testsuite/gas/riscv/zdinx-zhinxmin-32-regpair.d b/gas/testsuite/gas/riscv/zdinx-zhinxmin-32-regpair.d
new file mode 100644
index 00000000000..2e9ae0ceed1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zdinx-zhinxmin-32-regpair.d
@@ -0,0 +1,14 @@
+#as: -march=rv32i_zdinx_zhinxmin
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+44167553[ 	]+fcvt.h.d[ 	]+a0,a2
+[ 	]+[0-9a-f]+:[ 	]+441675d3[ 	]+fcvt.h.d[ 	]+a1,a2
+[ 	]+[0-9a-f]+:[ 	]+44160553[ 	]+fcvt.h.d[ 	]+a0,a2,rne
+[ 	]+[0-9a-f]+:[ 	]+441605d3[ 	]+fcvt.h.d[ 	]+a1,a2,rne
+[ 	]+[0-9a-f]+:[ 	]+42250653[ 	]+fcvt.d.h[ 	]+a2,a0
+[ 	]+[0-9a-f]+:[ 	]+42258653[ 	]+fcvt.d.h[ 	]+a2,a1
diff --git a/gas/testsuite/gas/riscv/zdinx-zhinxmin-32-regpair.s b/gas/testsuite/gas/riscv/zdinx-zhinxmin-32-regpair.s
new file mode 100644
index 00000000000..c5fd42625fb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zdinx-zhinxmin-32-regpair.s
@@ -0,0 +1,8 @@
+target:
+	# fcvt instructions (float-float; FP32 operand can be odd)
+	fcvt.h.d	a0, a2
+	fcvt.h.d	a1, a2
+	fcvt.h.d	a0, a2, rne
+	fcvt.h.d	a1, a2, rne
+	fcvt.d.h	a2, a0
+	fcvt.d.h	a2, a1
diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair-dis.d b/gas/testsuite/gas/riscv/zqinx-32-regpair-dis.d
new file mode 100644
index 00000000000..3feecf45064
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zqinx-32-regpair-dis.d
@@ -0,0 +1,11 @@
+#as: -march=rv32i_zqinx
+#objdump: -dr -Mnumeric
+
+.*:[ 	]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+06c47253[ 	]+fadd.q[ 	]+x4,x8,x12
+[ 	]+[0-9a-f]+:[ 	]+06d4f2d3[ 	]+fadd.q[ 	]+invalid5,invalid9,invalid13
+[ 	]+[0-9a-f]+:[ 	]+06e57353[ 	]+fadd.q[ 	]+invalid6,invalid10,invalid14
diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair-dis.s b/gas/testsuite/gas/riscv/zqinx-32-regpair-dis.s
new file mode 100644
index 00000000000..c6ce9513175
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zqinx-32-regpair-dis.s
@@ -0,0 +1,7 @@
+target:
+	# fadd.q x4, x8, x12
+	.insn r	OP_FP, 0x7, 0x03, x4,  x8, x12
+	# fadd.q x5, x9, x13 (invalid)
+	.insn r	OP_FP, 0x7, 0x03, x5,  x9, x13
+	# fadd.q x6, x10, x14 (invalid)
+	.insn r	OP_FP, 0x7, 0x03, x6, x10, x14
diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.d b/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.d
new file mode 100644
index 00000000000..144868b5ab9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.d
@@ -0,0 +1,2 @@
+#as: -march=rv32i_zqinx
+#error_output: zqinx-32-regpair-fail.l
diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.l b/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.l
new file mode 100644
index 00000000000..61afcc84d79
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.l
@@ -0,0 +1,212 @@
+.*Assembler messages:
+.*Error: illegal operands `fadd\.q x5,x8,x12'
+.*Error: illegal operands `fadd\.q x5,x8,x12,rne'
+.*Error: illegal operands `fadd\.q x6,x8,x12'
+.*Error: illegal operands `fadd\.q x6,x8,x12,rne'
+.*Error: illegal operands `fadd\.q x4,x5,x12'
+.*Error: illegal operands `fadd\.q x4,x5,x12,rne'
+.*Error: illegal operands `fadd\.q x4,x6,x12'
+.*Error: illegal operands `fadd\.q x4,x6,x12,rne'
+.*Error: illegal operands `fadd\.q x4,x8,x5'
+.*Error: illegal operands `fadd\.q x4,x8,x5,rne'
+.*Error: illegal operands `fadd\.q x4,x8,x6'
+.*Error: illegal operands `fadd\.q x4,x8,x6,rne'
+.*Error: illegal operands `fsub\.q x5,x8,x12'
+.*Error: illegal operands `fsub\.q x5,x8,x12,rne'
+.*Error: illegal operands `fsub\.q x6,x8,x12'
+.*Error: illegal operands `fsub\.q x6,x8,x12,rne'
+.*Error: illegal operands `fsub\.q x4,x5,x12'
+.*Error: illegal operands `fsub\.q x4,x5,x12,rne'
+.*Error: illegal operands `fsub\.q x4,x6,x12'
+.*Error: illegal operands `fsub\.q x4,x6,x12,rne'
+.*Error: illegal operands `fsub\.q x4,x8,x5'
+.*Error: illegal operands `fsub\.q x4,x8,x5,rne'
+.*Error: illegal operands `fsub\.q x4,x8,x6'
+.*Error: illegal operands `fsub\.q x4,x8,x6,rne'
+.*Error: illegal operands `fmul\.q x5,x8,x12'
+.*Error: illegal operands `fmul\.q x5,x8,x12,rne'
+.*Error: illegal operands `fmul\.q x6,x8,x12'
+.*Error: illegal operands `fmul\.q x6,x8,x12,rne'
+.*Error: illegal operands `fmul\.q x4,x5,x12'
+.*Error: illegal operands `fmul\.q x4,x5,x12,rne'
+.*Error: illegal operands `fmul\.q x4,x6,x12'
+.*Error: illegal operands `fmul\.q x4,x6,x12,rne'
+.*Error: illegal operands `fmul\.q x4,x8,x5'
+.*Error: illegal operands `fmul\.q x4,x8,x5,rne'
+.*Error: illegal operands `fmul\.q x4,x8,x6'
+.*Error: illegal operands `fmul\.q x4,x8,x6,rne'
+.*Error: illegal operands `fdiv\.q x5,x8,x12'
+.*Error: illegal operands `fdiv\.q x5,x8,x12,rne'
+.*Error: illegal operands `fdiv\.q x6,x8,x12'
+.*Error: illegal operands `fdiv\.q x6,x8,x12,rne'
+.*Error: illegal operands `fdiv\.q x4,x5,x12'
+.*Error: illegal operands `fdiv\.q x4,x5,x12,rne'
+.*Error: illegal operands `fdiv\.q x4,x6,x12'
+.*Error: illegal operands `fdiv\.q x4,x6,x12,rne'
+.*Error: illegal operands `fdiv\.q x4,x8,x5'
+.*Error: illegal operands `fdiv\.q x4,x8,x5,rne'
+.*Error: illegal operands `fdiv\.q x4,x8,x6'
+.*Error: illegal operands `fdiv\.q x4,x8,x6,rne'
+.*Error: illegal operands `fsqrt\.q x5,x8'
+.*Error: illegal operands `fsqrt\.q x5,x8,rne'
+.*Error: illegal operands `fsqrt\.q x6,x8'
+.*Error: illegal operands `fsqrt\.q x6,x8,rne'
+.*Error: illegal operands `fsqrt\.q x4,x5'
+.*Error: illegal operands `fsqrt\.q x4,x5,rne'
+.*Error: illegal operands `fsqrt\.q x4,x6'
+.*Error: illegal operands `fsqrt\.q x4,x6,rne'
+.*Error: illegal operands `fmin\.q x5,x8,x12'
+.*Error: illegal operands `fmin\.q x6,x8,x12'
+.*Error: illegal operands `fmin\.q x4,x5,x12'
+.*Error: illegal operands `fmin\.q x4,x6,x12'
+.*Error: illegal operands `fmin\.q x4,x8,x5'
+.*Error: illegal operands `fmin\.q x4,x8,x6'
+.*Error: illegal operands `fmax\.q x5,x8,x12'
+.*Error: illegal operands `fmax\.q x6,x8,x12'
+.*Error: illegal operands `fmax\.q x4,x5,x12'
+.*Error: illegal operands `fmax\.q x4,x6,x12'
+.*Error: illegal operands `fmax\.q x4,x8,x5'
+.*Error: illegal operands `fmax\.q x4,x8,x6'
+.*Error: illegal operands `fmadd\.q x5,x8,x12,x16'
+.*Error: illegal operands `fmadd\.q x5,x8,x12,x16,rne'
+.*Error: illegal operands `fmadd\.q x6,x8,x12,x16'
+.*Error: illegal operands `fmadd\.q x6,x8,x12,x16,rne'
+.*Error: illegal operands `fmadd\.q x4,x5,x12,x16'
+.*Error: illegal operands `fmadd\.q x4,x5,x12,x16,rne'
+.*Error: illegal operands `fmadd\.q x4,x6,x12,x16'
+.*Error: illegal operands `fmadd\.q x4,x6,x12,x16,rne'
+.*Error: illegal operands `fmadd\.q x4,x8,x5,x16'
+.*Error: illegal operands `fmadd\.q x4,x8,x5,x16,rne'
+.*Error: illegal operands `fmadd\.q x4,x8,x6,x16'
+.*Error: illegal operands `fmadd\.q x4,x8,x6,x16,rne'
+.*Error: illegal operands `fmadd\.q x4,x8,x12,x5'
+.*Error: illegal operands `fmadd\.q x4,x8,x12,x5,rne'
+.*Error: illegal operands `fmadd\.q x4,x8,x12,x6'
+.*Error: illegal operands `fmadd\.q x4,x8,x12,x6,rne'
+.*Error: illegal operands `fnmadd\.q x5,x8,x12,x16'
+.*Error: illegal operands `fnmadd\.q x5,x8,x12,x16,rne'
+.*Error: illegal operands `fnmadd\.q x6,x8,x12,x16'
+.*Error: illegal operands `fnmadd\.q x6,x8,x12,x16,rne'
+.*Error: illegal operands `fnmadd\.q x4,x5,x12,x16'
+.*Error: illegal operands `fnmadd\.q x4,x5,x12,x16,rne'
+.*Error: illegal operands `fnmadd\.q x4,x6,x12,x16'
+.*Error: illegal operands `fnmadd\.q x4,x6,x12,x16,rne'
+.*Error: illegal operands `fnmadd\.q x4,x8,x5,x16'
+.*Error: illegal operands `fnmadd\.q x4,x8,x5,x16,rne'
+.*Error: illegal operands `fnmadd\.q x4,x8,x6,x16'
+.*Error: illegal operands `fnmadd\.q x4,x8,x6,x16,rne'
+.*Error: illegal operands `fnmadd\.q x4,x8,x12,x5'
+.*Error: illegal operands `fnmadd\.q x4,x8,x12,x5,rne'
+.*Error: illegal operands `fnmadd\.q x4,x8,x12,x6'
+.*Error: illegal operands `fnmadd\.q x4,x8,x12,x6,rne'
+.*Error: illegal operands `fmsub\.q x5,x8,x12,x16'
+.*Error: illegal operands `fmsub\.q x5,x8,x12,x16,rne'
+.*Error: illegal operands `fmsub\.q x6,x8,x12,x16'
+.*Error: illegal operands `fmsub\.q x6,x8,x12,x16,rne'
+.*Error: illegal operands `fmsub\.q x4,x5,x12,x16'
+.*Error: illegal operands `fmsub\.q x4,x5,x12,x16,rne'
+.*Error: illegal operands `fmsub\.q x4,x6,x12,x16'
+.*Error: illegal operands `fmsub\.q x4,x6,x12,x16,rne'
+.*Error: illegal operands `fmsub\.q x4,x8,x5,x16'
+.*Error: illegal operands `fmsub\.q x4,x8,x5,x16,rne'
+.*Error: illegal operands `fmsub\.q x4,x8,x6,x16'
+.*Error: illegal operands `fmsub\.q x4,x8,x6,x16,rne'
+.*Error: illegal operands `fmsub\.q x4,x8,x12,x5'
+.*Error: illegal operands `fmsub\.q x4,x8,x12,x5,rne'
+.*Error: illegal operands `fmsub\.q x4,x8,x12,x6'
+.*Error: illegal operands `fmsub\.q x4,x8,x12,x6,rne'
+.*Error: illegal operands `fnmsub\.q x5,x8,x12,x16'
+.*Error: illegal operands `fnmsub\.q x5,x8,x12,x16,rne'
+.*Error: illegal operands `fnmsub\.q x6,x8,x12,x16'
+.*Error: illegal operands `fnmsub\.q x6,x8,x12,x16,rne'
+.*Error: illegal operands `fnmsub\.q x4,x5,x12,x16'
+.*Error: illegal operands `fnmsub\.q x4,x5,x12,x16,rne'
+.*Error: illegal operands `fnmsub\.q x4,x6,x12,x16'
+.*Error: illegal operands `fnmsub\.q x4,x6,x12,x16,rne'
+.*Error: illegal operands `fnmsub\.q x4,x8,x5,x16'
+.*Error: illegal operands `fnmsub\.q x4,x8,x5,x16,rne'
+.*Error: illegal operands `fnmsub\.q x4,x8,x6,x16'
+.*Error: illegal operands `fnmsub\.q x4,x8,x6,x16,rne'
+.*Error: illegal operands `fnmsub\.q x4,x8,x12,x5'
+.*Error: illegal operands `fnmsub\.q x4,x8,x12,x5,rne'
+.*Error: illegal operands `fnmsub\.q x4,x8,x12,x6'
+.*Error: illegal operands `fnmsub\.q x4,x8,x12,x6,rne'
+.*Error: illegal operands `fsgnj\.q x5,x8,x12'
+.*Error: illegal operands `fsgnj\.q x6,x8,x12'
+.*Error: illegal operands `fsgnj\.q x4,x5,x12'
+.*Error: illegal operands `fsgnj\.q x4,x6,x12'
+.*Error: illegal operands `fsgnj\.q x4,x8,x5'
+.*Error: illegal operands `fsgnj\.q x4,x8,x6'
+.*Error: illegal operands `fsgnjn\.q x5,x8,x12'
+.*Error: illegal operands `fsgnjn\.q x6,x8,x12'
+.*Error: illegal operands `fsgnjn\.q x4,x5,x12'
+.*Error: illegal operands `fsgnjn\.q x4,x6,x12'
+.*Error: illegal operands `fsgnjn\.q x4,x8,x5'
+.*Error: illegal operands `fsgnjn\.q x4,x8,x6'
+.*Error: illegal operands `fsgnjx\.q x5,x8,x12'
+.*Error: illegal operands `fsgnjx\.q x6,x8,x12'
+.*Error: illegal operands `fsgnjx\.q x4,x5,x12'
+.*Error: illegal operands `fsgnjx\.q x4,x6,x12'
+.*Error: illegal operands `fsgnjx\.q x4,x8,x5'
+.*Error: illegal operands `fsgnjx\.q x4,x8,x6'
+.*Error: illegal operands `fmv\.q x5,x8'
+.*Error: illegal operands `fmv\.q x6,x8'
+.*Error: illegal operands `fmv\.q x4,x5'
+.*Error: illegal operands `fmv\.q x4,x6'
+.*Error: illegal operands `fneg\.q x5,x8'
+.*Error: illegal operands `fneg\.q x6,x8'
+.*Error: illegal operands `fneg\.q x4,x5'
+.*Error: illegal operands `fneg\.q x4,x6'
+.*Error: illegal operands `fabs\.q x5,x8'
+.*Error: illegal operands `fabs\.q x6,x8'
+.*Error: illegal operands `fabs\.q x4,x5'
+.*Error: illegal operands `fabs\.q x4,x6'
+.*Error: illegal operands `feq\.q x4,x5,x12'
+.*Error: illegal operands `feq\.q x4,x6,x12'
+.*Error: illegal operands `feq\.q x4,x8,x5'
+.*Error: illegal operands `feq\.q x4,x8,x6'
+.*Error: illegal operands `flt\.q x4,x5,x12'
+.*Error: illegal operands `flt\.q x4,x6,x12'
+.*Error: illegal operands `flt\.q x4,x8,x5'
+.*Error: illegal operands `flt\.q x4,x8,x6'
+.*Error: illegal operands `fle\.q x4,x5,x12'
+.*Error: illegal operands `fle\.q x4,x6,x12'
+.*Error: illegal operands `fle\.q x4,x8,x5'
+.*Error: illegal operands `fle\.q x4,x8,x6'
+.*Error: illegal operands `fgt\.q x4,x5,x12'
+.*Error: illegal operands `fgt\.q x4,x6,x12'
+.*Error: illegal operands `fgt\.q x4,x8,x5'
+.*Error: illegal operands `fgt\.q x4,x8,x6'
+.*Error: illegal operands `fge\.q x4,x5,x12'
+.*Error: illegal operands `fge\.q x4,x6,x12'
+.*Error: illegal operands `fge\.q x4,x8,x5'
+.*Error: illegal operands `fge\.q x4,x8,x6'
+.*Error: illegal operands `fclass\.q x4,x5'
+.*Error: illegal operands `fclass\.q x4,x6'
+.*Error: illegal operands `fcvt\.w\.q x4,x5'
+.*Error: illegal operands `fcvt\.w\.q x4,x5,rne'
+.*Error: illegal operands `fcvt\.w\.q x4,x6'
+.*Error: illegal operands `fcvt\.w\.q x4,x6,rne'
+.*Error: illegal operands `fcvt\.wu\.q x4,x5'
+.*Error: illegal operands `fcvt\.wu\.q x4,x5,rne'
+.*Error: illegal operands `fcvt\.wu\.q x4,x6'
+.*Error: illegal operands `fcvt\.wu\.q x4,x6,rne'
+.*Error: illegal operands `fcvt\.q\.w x5,x4'
+.*Error: illegal operands `fcvt\.q\.w x6,x4'
+.*Error: illegal operands `fcvt\.q\.wu x5,x4'
+.*Error: illegal operands `fcvt\.q\.wu x6,x4'
+.*Error: illegal operands `fcvt\.s\.q x4,x5'
+.*Error: illegal operands `fcvt\.s\.q x4,x5,rne'
+.*Error: illegal operands `fcvt\.s\.q x4,x6'
+.*Error: illegal operands `fcvt\.s\.q x4,x6,rne'
+.*Error: illegal operands `fcvt\.d\.q x4,x5'
+.*Error: illegal operands `fcvt\.d\.q x4,x5,rne'
+.*Error: illegal operands `fcvt\.d\.q x4,x6'
+.*Error: illegal operands `fcvt\.d\.q x4,x6,rne'
+.*Error: illegal operands `fcvt\.d\.q x5,x8'
+.*Error: illegal operands `fcvt\.d\.q x5,x8,rne'
+.*Error: illegal operands `fcvt\.q\.s x5,x4'
+.*Error: illegal operands `fcvt\.q\.s x6,x4'
+.*Error: illegal operands `fcvt\.q\.d x5,x4'
+.*Error: illegal operands `fcvt\.q\.d x6,x4'
+.*Error: illegal operands `fcvt\.q\.d x8,x5'
diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.s b/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.s
new file mode 100644
index 00000000000..9a1981f3bb3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.s
@@ -0,0 +1,218 @@
+target:
+	fadd.q	x5, x8, x12
+	fadd.q	x5, x8, x12, rne
+	fadd.q	x6, x8, x12
+	fadd.q	x6, x8, x12, rne
+	fadd.q	x4, x5, x12
+	fadd.q	x4, x5, x12, rne
+	fadd.q	x4, x6, x12
+	fadd.q	x4, x6, x12, rne
+	fadd.q	x4, x8, x5
+	fadd.q	x4, x8, x5, rne
+	fadd.q	x4, x8, x6
+	fadd.q	x4, x8, x6, rne
+	fsub.q	x5, x8, x12
+	fsub.q	x5, x8, x12, rne
+	fsub.q	x6, x8, x12
+	fsub.q	x6, x8, x12, rne
+	fsub.q	x4, x5, x12
+	fsub.q	x4, x5, x12, rne
+	fsub.q	x4, x6, x12
+	fsub.q	x4, x6, x12, rne
+	fsub.q	x4, x8, x5
+	fsub.q	x4, x8, x5, rne
+	fsub.q	x4, x8, x6
+	fsub.q	x4, x8, x6, rne
+	fmul.q	x5, x8, x12
+	fmul.q	x5, x8, x12, rne
+	fmul.q	x6, x8, x12
+	fmul.q	x6, x8, x12, rne
+	fmul.q	x4, x5, x12
+	fmul.q	x4, x5, x12, rne
+	fmul.q	x4, x6, x12
+	fmul.q	x4, x6, x12, rne
+	fmul.q	x4, x8, x5
+	fmul.q	x4, x8, x5, rne
+	fmul.q	x4, x8, x6
+	fmul.q	x4, x8, x6, rne
+	fdiv.q	x5, x8, x12
+	fdiv.q	x5, x8, x12, rne
+	fdiv.q	x6, x8, x12
+	fdiv.q	x6, x8, x12, rne
+	fdiv.q	x4, x5, x12
+	fdiv.q	x4, x5, x12, rne
+	fdiv.q	x4, x6, x12
+	fdiv.q	x4, x6, x12, rne
+	fdiv.q	x4, x8, x5
+	fdiv.q	x4, x8, x5, rne
+	fdiv.q	x4, x8, x6
+	fdiv.q	x4, x8, x6, rne
+	fsqrt.q	x5, x8
+	fsqrt.q	x5, x8, rne
+	fsqrt.q	x6, x8
+	fsqrt.q	x6, x8, rne
+	fsqrt.q	x4, x5
+	fsqrt.q	x4, x5, rne
+	fsqrt.q	x4, x6
+	fsqrt.q	x4, x6, rne
+	fmin.q	x5, x8, x12
+	fmin.q	x6, x8, x12
+	fmin.q	x4, x5, x12
+	fmin.q	x4, x6, x12
+	fmin.q	x4, x8, x5
+	fmin.q	x4, x8, x6
+	fmax.q	x5, x8, x12
+	fmax.q	x6, x8, x12
+	fmax.q	x4, x5, x12
+	fmax.q	x4, x6, x12
+	fmax.q	x4, x8, x5
+	fmax.q	x4, x8, x6
+	fmadd.q	x5, x8, x12, x16
+	fmadd.q	x5, x8, x12, x16, rne
+	fmadd.q	x6, x8, x12, x16
+	fmadd.q	x6, x8, x12, x16, rne
+	fmadd.q	x4, x5, x12, x16
+	fmadd.q	x4, x5, x12, x16, rne
+	fmadd.q	x4, x6, x12, x16
+	fmadd.q	x4, x6, x12, x16, rne
+	fmadd.q	x4, x8, x5, x16
+	fmadd.q	x4, x8, x5, x16, rne
+	fmadd.q	x4, x8, x6, x16
+	fmadd.q	x4, x8, x6, x16, rne
+	fmadd.q	x4, x8, x12, x5
+	fmadd.q	x4, x8, x12, x5, rne
+	fmadd.q	x4, x8, x12, x6
+	fmadd.q	x4, x8, x12, x6, rne
+	fnmadd.q	x5, x8, x12, x16
+	fnmadd.q	x5, x8, x12, x16, rne
+	fnmadd.q	x6, x8, x12, x16
+	fnmadd.q	x6, x8, x12, x16, rne
+	fnmadd.q	x4, x5, x12, x16
+	fnmadd.q	x4, x5, x12, x16, rne
+	fnmadd.q	x4, x6, x12, x16
+	fnmadd.q	x4, x6, x12, x16, rne
+	fnmadd.q	x4, x8, x5, x16
+	fnmadd.q	x4, x8, x5, x16, rne
+	fnmadd.q	x4, x8, x6, x16
+	fnmadd.q	x4, x8, x6, x16, rne
+	fnmadd.q	x4, x8, x12, x5
+	fnmadd.q	x4, x8, x12, x5, rne
+	fnmadd.q	x4, x8, x12, x6
+	fnmadd.q	x4, x8, x12, x6, rne
+	fmsub.q	x5, x8, x12, x16
+	fmsub.q	x5, x8, x12, x16, rne
+	fmsub.q	x6, x8, x12, x16
+	fmsub.q	x6, x8, x12, x16, rne
+	fmsub.q	x4, x5, x12, x16
+	fmsub.q	x4, x5, x12, x16, rne
+	fmsub.q	x4, x6, x12, x16
+	fmsub.q	x4, x6, x12, x16, rne
+	fmsub.q	x4, x8, x5, x16
+	fmsub.q	x4, x8, x5, x16, rne
+	fmsub.q	x4, x8, x6, x16
+	fmsub.q	x4, x8, x6, x16, rne
+	fmsub.q	x4, x8, x12, x5
+	fmsub.q	x4, x8, x12, x5, rne
+	fmsub.q	x4, x8, x12, x6
+	fmsub.q	x4, x8, x12, x6, rne
+	fnmsub.q	x5, x8, x12, x16
+	fnmsub.q	x5, x8, x12, x16, rne
+	fnmsub.q	x6, x8, x12, x16
+	fnmsub.q	x6, x8, x12, x16, rne
+	fnmsub.q	x4, x5, x12, x16
+	fnmsub.q	x4, x5, x12, x16, rne
+	fnmsub.q	x4, x6, x12, x16
+	fnmsub.q	x4, x6, x12, x16, rne
+	fnmsub.q	x4, x8, x5, x16
+	fnmsub.q	x4, x8, x5, x16, rne
+	fnmsub.q	x4, x8, x6, x16
+	fnmsub.q	x4, x8, x6, x16, rne
+	fnmsub.q	x4, x8, x12, x5
+	fnmsub.q	x4, x8, x12, x5, rne
+	fnmsub.q	x4, x8, x12, x6
+	fnmsub.q	x4, x8, x12, x6, rne
+	fsgnj.q	x5, x8, x12
+	fsgnj.q	x6, x8, x12
+	fsgnj.q	x4, x5, x12
+	fsgnj.q	x4, x6, x12
+	fsgnj.q	x4, x8, x5
+	fsgnj.q	x4, x8, x6
+	fsgnjn.q	x5, x8, x12
+	fsgnjn.q	x6, x8, x12
+	fsgnjn.q	x4, x5, x12
+	fsgnjn.q	x4, x6, x12
+	fsgnjn.q	x4, x8, x5
+	fsgnjn.q	x4, x8, x6
+	fsgnjx.q	x5, x8, x12
+	fsgnjx.q	x6, x8, x12
+	fsgnjx.q	x4, x5, x12
+	fsgnjx.q	x4, x6, x12
+	fsgnjx.q	x4, x8, x5
+	fsgnjx.q	x4, x8, x6
+	fmv.q	x5, x8
+	fmv.q	x6, x8
+	fmv.q	x4, x5
+	fmv.q	x4, x6
+	fneg.q	x5, x8
+	fneg.q	x6, x8
+	fneg.q	x4, x5
+	fneg.q	x4, x6
+	fabs.q	x5, x8
+	fabs.q	x6, x8
+	fabs.q	x4, x5
+	fabs.q	x4, x6
+	# Compare instructions: destination is a GPR
+	feq.q	x4, x5, x12
+	feq.q	x4, x6, x12
+	feq.q	x4, x8, x5
+	feq.q	x4, x8, x6
+	flt.q	x4, x5, x12
+	flt.q	x4, x6, x12
+	flt.q	x4, x8, x5
+	flt.q	x4, x8, x6
+	fle.q	x4, x5, x12
+	fle.q	x4, x6, x12
+	fle.q	x4, x8, x5
+	fle.q	x4, x8, x6
+	fgt.q	x4, x5, x12
+	fgt.q	x4, x6, x12
+	fgt.q	x4, x8, x5
+	fgt.q	x4, x8, x6
+	fge.q	x4, x5, x12
+	fge.q	x4, x6, x12
+	fge.q	x4, x8, x5
+	fge.q	x4, x8, x6
+	# fclass instruction: destination is a GPR
+	fclass.q	x4, x5
+	fclass.q	x4, x6
+	# fcvt instructions (float-int or int-float;
+	#                    integer operand register can be any)
+	fcvt.w.q	x4, x5
+	fcvt.w.q	x4, x5, rne
+	fcvt.w.q	x4, x6
+	fcvt.w.q	x4, x6, rne
+	fcvt.wu.q	x4, x5
+	fcvt.wu.q	x4, x5, rne
+	fcvt.wu.q	x4, x6
+	fcvt.wu.q	x4, x6, rne
+	fcvt.q.w	x5, x4
+	fcvt.q.w	x6, x4
+	fcvt.q.wu	x5, x4
+	fcvt.q.wu	x6, x4
+	# fcvt instructions (float-float; FP32 operand can be any,
+	#                    FP64 operand can be (x%4)==2)
+	fcvt.s.q	x4, x5
+	fcvt.s.q	x4, x5, rne
+	fcvt.s.q	x4, x6
+	fcvt.s.q	x4, x6, rne
+	fcvt.d.q	x4, x5
+	fcvt.d.q	x4, x5, rne
+	fcvt.d.q	x4, x6
+	fcvt.d.q	x4, x6, rne
+	fcvt.d.q	x5, x8
+	fcvt.d.q	x5, x8, rne
+	fcvt.q.s	x5, x4
+	fcvt.q.s	x6, x4
+	fcvt.q.d	x5, x4
+	fcvt.q.d	x6, x4
+	fcvt.q.d	x8, x5
diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair.d b/gas/testsuite/gas/riscv/zqinx-32-regpair.d
new file mode 100644
index 00000000000..3f2a3e5b832
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zqinx-32-regpair.d
@@ -0,0 +1,65 @@
+#as: -march=rv32i_zqinx
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+06c47253[ 	]+fadd.q[ 	]+tp,s0,a2
+[ 	]+[0-9a-f]+:[ 	]+0ec47253[ 	]+fsub.q[ 	]+tp,s0,a2
+[ 	]+[0-9a-f]+:[ 	]+16c47253[ 	]+fmul.q[ 	]+tp,s0,a2
+[ 	]+[0-9a-f]+:[ 	]+1ec47253[ 	]+fdiv.q[ 	]+tp,s0,a2
+[ 	]+[0-9a-f]+:[ 	]+5e047253[ 	]+fsqrt.q[ 	]+tp,s0
+[ 	]+[0-9a-f]+:[ 	]+2ec40253[ 	]+fmin.q[ 	]+tp,s0,a2
+[ 	]+[0-9a-f]+:[ 	]+2ec41253[ 	]+fmax.q[ 	]+tp,s0,a2
+[ 	]+[0-9a-f]+:[ 	]+86c47243[ 	]+fmadd.q[ 	]+tp,s0,a2,a6
+[ 	]+[0-9a-f]+:[ 	]+86c4724f[ 	]+fnmadd.q[ 	]+tp,s0,a2,a6
+[ 	]+[0-9a-f]+:[ 	]+86c47247[ 	]+fmsub.q[ 	]+tp,s0,a2,a6
+[ 	]+[0-9a-f]+:[ 	]+86c4724b[ 	]+fnmsub.q[ 	]+tp,s0,a2,a6
+[ 	]+[0-9a-f]+:[ 	]+26c40253[ 	]+fsgnj.q[ 	]+tp,s0,a2
+[ 	]+[0-9a-f]+:[ 	]+26c41253[ 	]+fsgnjn.q[ 	]+tp,s0,a2
+[ 	]+[0-9a-f]+:[ 	]+26c42253[ 	]+fsgnjx.q[ 	]+tp,s0,a2
+[ 	]+[0-9a-f]+:[ 	]+26840253[ 	]+fmv.q[ 	]+tp,s0
+[ 	]+[0-9a-f]+:[ 	]+26841253[ 	]+fneg.q[ 	]+tp,s0
+[ 	]+[0-9a-f]+:[ 	]+26842253[ 	]+fabs.q[ 	]+tp,s0
+[ 	]+[0-9a-f]+:[ 	]+a6c42253[ 	]+feq.q[ 	]+tp,s0,a2
+[ 	]+[0-9a-f]+:[ 	]+a6c422d3[ 	]+feq.q[ 	]+t0,s0,a2
+[ 	]+[0-9a-f]+:[ 	]+a6c42353[ 	]+feq.q[ 	]+t1,s0,a2
+[ 	]+[0-9a-f]+:[ 	]+a6c41253[ 	]+flt.q[ 	]+tp,s0,a2
+[ 	]+[0-9a-f]+:[ 	]+a6c412d3[ 	]+flt.q[ 	]+t0,s0,a2
+[ 	]+[0-9a-f]+:[ 	]+a6c41353[ 	]+flt.q[ 	]+t1,s0,a2
+[ 	]+[0-9a-f]+:[ 	]+a6c40253[ 	]+fle.q[ 	]+tp,s0,a2
+[ 	]+[0-9a-f]+:[ 	]+a6c402d3[ 	]+fle.q[ 	]+t0,s0,a2
+[ 	]+[0-9a-f]+:[ 	]+a6c40353[ 	]+fle.q[ 	]+t1,s0,a2
+[ 	]+[0-9a-f]+:[ 	]+a6861253[ 	]+flt.q[ 	]+tp,a2,s0
+[ 	]+[0-9a-f]+:[ 	]+a68612d3[ 	]+flt.q[ 	]+t0,a2,s0
+[ 	]+[0-9a-f]+:[ 	]+a6861353[ 	]+flt.q[ 	]+t1,a2,s0
+[ 	]+[0-9a-f]+:[ 	]+a6860253[ 	]+fle.q[ 	]+tp,a2,s0
+[ 	]+[0-9a-f]+:[ 	]+a68602d3[ 	]+fle.q[ 	]+t0,a2,s0
+[ 	]+[0-9a-f]+:[ 	]+a6860353[ 	]+fle.q[ 	]+t1,a2,s0
+[ 	]+[0-9a-f]+:[ 	]+e6041253[ 	]+fclass.q[ 	]+tp,s0
+[ 	]+[0-9a-f]+:[ 	]+e60412d3[ 	]+fclass.q[ 	]+t0,s0
+[ 	]+[0-9a-f]+:[ 	]+e6041353[ 	]+fclass.q[ 	]+t1,s0
+[ 	]+[0-9a-f]+:[ 	]+c6047253[ 	]+fcvt.w.q[ 	]+tp,s0
+[ 	]+[0-9a-f]+:[ 	]+c60472d3[ 	]+fcvt.w.q[ 	]+t0,s0
+[ 	]+[0-9a-f]+:[ 	]+c6047353[ 	]+fcvt.w.q[ 	]+t1,s0
+[ 	]+[0-9a-f]+:[ 	]+c6147253[ 	]+fcvt.wu.q[ 	]+tp,s0
+[ 	]+[0-9a-f]+:[ 	]+c61472d3[ 	]+fcvt.wu.q[ 	]+t0,s0
+[ 	]+[0-9a-f]+:[ 	]+c6147353[ 	]+fcvt.wu.q[ 	]+t1,s0
+[ 	]+[0-9a-f]+:[ 	]+d6020453[ 	]+fcvt.q.w[ 	]+s0,tp
+[ 	]+[0-9a-f]+:[ 	]+d6028453[ 	]+fcvt.q.w[ 	]+s0,t0
+[ 	]+[0-9a-f]+:[ 	]+d6030453[ 	]+fcvt.q.w[ 	]+s0,t1
+[ 	]+[0-9a-f]+:[ 	]+d6120453[ 	]+fcvt.q.wu[ 	]+s0,tp
+[ 	]+[0-9a-f]+:[ 	]+d6128453[ 	]+fcvt.q.wu[ 	]+s0,t0
+[ 	]+[0-9a-f]+:[ 	]+d6130453[ 	]+fcvt.q.wu[ 	]+s0,t1
+[ 	]+[0-9a-f]+:[ 	]+40347253[ 	]+fcvt.s.q[ 	]+tp,s0
+[ 	]+[0-9a-f]+:[ 	]+403472d3[ 	]+fcvt.s.q[ 	]+t0,s0
+[ 	]+[0-9a-f]+:[ 	]+40347353[ 	]+fcvt.s.q[ 	]+t1,s0
+[ 	]+[0-9a-f]+:[ 	]+42347253[ 	]+fcvt.d.q[ 	]+tp,s0
+[ 	]+[0-9a-f]+:[ 	]+42347353[ 	]+fcvt.d.q[ 	]+t1,s0
+[ 	]+[0-9a-f]+:[ 	]+46020453[ 	]+fcvt.q.s[ 	]+s0,tp
+[ 	]+[0-9a-f]+:[ 	]+46028453[ 	]+fcvt.q.s[ 	]+s0,t0
+[ 	]+[0-9a-f]+:[ 	]+46030453[ 	]+fcvt.q.s[ 	]+s0,t1
+[ 	]+[0-9a-f]+:[ 	]+46120453[ 	]+fcvt.q.d[ 	]+s0,tp
+[ 	]+[0-9a-f]+:[ 	]+46130453[ 	]+fcvt.q.d[ 	]+s0,t1
diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair.s b/gas/testsuite/gas/riscv/zqinx-32-regpair.s
new file mode 100644
index 00000000000..2f340767376
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zqinx-32-regpair.s
@@ -0,0 +1,64 @@
+target:
+	fadd.q	x4, x8, x12
+	fsub.q	x4, x8, x12
+	fmul.q	x4, x8, x12
+	fdiv.q	x4, x8, x12
+	fsqrt.q	x4, x8
+	fmin.q	x4, x8, x12
+	fmax.q	x4, x8, x12
+	fmadd.q	x4, x8, x12, x16
+	fnmadd.q	x4, x8, x12, x16
+	fmsub.q	x4, x8, x12, x16
+	fnmsub.q	x4, x8, x12, x16
+	fsgnj.q	x4, x8, x12
+	fsgnjn.q	x4, x8, x12
+	fsgnjx.q	x4, x8, x12
+	fmv.q	x4, x8
+	fneg.q	x4, x8
+	fabs.q	x4, x8
+	# Compare instructions: destination is a GPR
+	feq.q	x4, x8, x12
+	feq.q	x5, x8, x12
+	feq.q	x6, x8, x12
+	flt.q	x4, x8, x12
+	flt.q	x5, x8, x12
+	flt.q	x6, x8, x12
+	fle.q	x4, x8, x12
+	fle.q	x5, x8, x12
+	fle.q	x6, x8, x12
+	fgt.q	x4, x8, x12
+	fgt.q	x5, x8, x12
+	fgt.q	x6, x8, x12
+	fge.q	x4, x8, x12
+	fge.q	x5, x8, x12
+	fge.q	x6, x8, x12
+	# fclass instruction: destination is a GPR
+	fclass.q	x4, x8
+	fclass.q	x5, x8
+	fclass.q	x6, x8
+	# fcvt instructions (float-int or int-float;
+	#                    integer operand register can be any)
+	fcvt.w.q	x4, x8
+	fcvt.w.q	x5, x8
+	fcvt.w.q	x6, x8
+	fcvt.wu.q	x4, x8
+	fcvt.wu.q	x5, x8
+	fcvt.wu.q	x6, x8
+	fcvt.q.w	x8, x4
+	fcvt.q.w	x8, x5
+	fcvt.q.w	x8, x6
+	fcvt.q.wu	x8, x4
+	fcvt.q.wu	x8, x5
+	fcvt.q.wu	x8, x6
+	# fcvt instructions (float-float; FP32 operand can be any,
+	#                    FP64 operand can be (x%4)==2)
+	fcvt.s.q	x4, x8
+	fcvt.s.q	x5, x8
+	fcvt.s.q	x6, x8
+	fcvt.d.q	x4, x8
+	fcvt.d.q	x6, x8
+	fcvt.q.s	x8, x4
+	fcvt.q.s	x8, x5
+	fcvt.q.s	x8, x6
+	fcvt.q.d	x8, x4
+	fcvt.q.d	x8, x6
diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair-dis.d b/gas/testsuite/gas/riscv/zqinx-64-regpair-dis.d
new file mode 100644
index 00000000000..8ab2ea135cc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zqinx-64-regpair-dis.d
@@ -0,0 +1,10 @@
+#as: -march=rv64i_zqinx
+#objdump: -dr -Mnumeric
+
+.*:[ 	]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+06627153[ 	]+fadd.q[ 	]+x2,x4,x6
+[ 	]+[0-9a-f]+:[ 	]+0672f1d3[ 	]+fadd.q[ 	]+invalid3,invalid5,invalid7
diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair-dis.s b/gas/testsuite/gas/riscv/zqinx-64-regpair-dis.s
new file mode 100644
index 00000000000..619d0fa4fdb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zqinx-64-regpair-dis.s
@@ -0,0 +1,5 @@
+target:
+	# fadd.q x2, x4, x6
+	.insn r	OP_FP, 0x7, 0x03, x2, x4, x6
+	# fadd.q x3, x5, x7 (invalid)
+	.insn r	OP_FP, 0x7, 0x03, x3, x5, x7
diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.d b/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.d
new file mode 100644
index 00000000000..0b77281f72e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.d
@@ -0,0 +1,2 @@
+#as: -march=rv64i_zqinx
+#error_output: zqinx-64-regpair-fail.l
diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.l b/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.l
new file mode 100644
index 00000000000..5a48b7bd22f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.l
@@ -0,0 +1,133 @@
+.*Assembler messages:
+.*Error: illegal operands `fadd\.q a1,a2,a4'
+.*Error: illegal operands `fadd\.q a1,a2,a4,rne'
+.*Error: illegal operands `fadd\.q a0,a1,a4'
+.*Error: illegal operands `fadd\.q a0,a1,a4,rne'
+.*Error: illegal operands `fadd\.q a0,a2,a1'
+.*Error: illegal operands `fadd\.q a0,a2,a1,rne'
+.*Error: illegal operands `fsub\.q a1,a2,a4'
+.*Error: illegal operands `fsub\.q a1,a2,a4,rne'
+.*Error: illegal operands `fsub\.q a0,a1,a4'
+.*Error: illegal operands `fsub\.q a0,a1,a4,rne'
+.*Error: illegal operands `fsub\.q a0,a2,a1'
+.*Error: illegal operands `fsub\.q a0,a2,a1,rne'
+.*Error: illegal operands `fmul\.q a1,a2,a4'
+.*Error: illegal operands `fmul\.q a1,a2,a4,rne'
+.*Error: illegal operands `fmul\.q a0,a1,a4'
+.*Error: illegal operands `fmul\.q a0,a1,a4,rne'
+.*Error: illegal operands `fmul\.q a0,a2,a1'
+.*Error: illegal operands `fmul\.q a0,a2,a1,rne'
+.*Error: illegal operands `fdiv\.q a1,a2,a4'
+.*Error: illegal operands `fdiv\.q a1,a2,a4,rne'
+.*Error: illegal operands `fdiv\.q a0,a1,a4'
+.*Error: illegal operands `fdiv\.q a0,a1,a4,rne'
+.*Error: illegal operands `fdiv\.q a0,a2,a1'
+.*Error: illegal operands `fdiv\.q a0,a2,a1,rne'
+.*Error: illegal operands `fsqrt\.q a1,a2'
+.*Error: illegal operands `fsqrt\.q a1,a2,rne'
+.*Error: illegal operands `fsqrt\.q a0,a1'
+.*Error: illegal operands `fsqrt\.q a0,a1,rne'
+.*Error: illegal operands `fmin\.q a1,a2,a4'
+.*Error: illegal operands `fmin\.q a0,a1,a4'
+.*Error: illegal operands `fmin\.q a0,a2,a1'
+.*Error: illegal operands `fmax\.q a1,a2,a4'
+.*Error: illegal operands `fmax\.q a0,a1,a4'
+.*Error: illegal operands `fmax\.q a0,a2,a1'
+.*Error: illegal operands `fmadd\.q a1,a2,a4,a6'
+.*Error: illegal operands `fmadd\.q a1,a2,a4,a6,rne'
+.*Error: illegal operands `fmadd\.q a0,a1,a4,a6'
+.*Error: illegal operands `fmadd\.q a0,a1,a4,a6,rne'
+.*Error: illegal operands `fmadd\.q a0,a2,a1,a6'
+.*Error: illegal operands `fmadd\.q a0,a2,a1,a6,rne'
+.*Error: illegal operands `fmadd\.q a0,a2,a4,a1'
+.*Error: illegal operands `fmadd\.q a0,a2,a4,a1,rne'
+.*Error: illegal operands `fnmadd\.q a1,a2,a4,a6'
+.*Error: illegal operands `fnmadd\.q a1,a2,a4,a6,rne'
+.*Error: illegal operands `fnmadd\.q a0,a1,a4,a6'
+.*Error: illegal operands `fnmadd\.q a0,a1,a4,a6,rne'
+.*Error: illegal operands `fnmadd\.q a0,a2,a1,a6'
+.*Error: illegal operands `fnmadd\.q a0,a2,a1,a6,rne'
+.*Error: illegal operands `fnmadd\.q a0,a2,a4,a1'
+.*Error: illegal operands `fnmadd\.q a0,a2,a4,a1,rne'
+.*Error: illegal operands `fmsub\.q a1,a2,a4,a6'
+.*Error: illegal operands `fmsub\.q a1,a2,a4,a6,rne'
+.*Error: illegal operands `fmsub\.q a0,a1,a4,a6'
+.*Error: illegal operands `fmsub\.q a0,a1,a4,a6,rne'
+.*Error: illegal operands `fmsub\.q a0,a2,a1,a6'
+.*Error: illegal operands `fmsub\.q a0,a2,a1,a6,rne'
+.*Error: illegal operands `fmsub\.q a0,a2,a4,a1'
+.*Error: illegal operands `fmsub\.q a0,a2,a4,a1,rne'
+.*Error: illegal operands `fnmsub\.q a1,a2,a4,a6'
+.*Error: illegal operands `fnmsub\.q a1,a2,a4,a6,rne'
+.*Error: illegal operands `fnmsub\.q a0,a1,a4,a6'
+.*Error: illegal operands `fnmsub\.q a0,a1,a4,a6,rne'
+.*Error: illegal operands `fnmsub\.q a0,a2,a1,a6'
+.*Error: illegal operands `fnmsub\.q a0,a2,a1,a6,rne'
+.*Error: illegal operands `fnmsub\.q a0,a2,a4,a1'
+.*Error: illegal operands `fnmsub\.q a0,a2,a4,a1,rne'
+.*Error: illegal operands `fsgnj\.q a1,a2,a4'
+.*Error: illegal operands `fsgnj\.q a0,a1,a4'
+.*Error: illegal operands `fsgnj\.q a0,a2,a1'
+.*Error: illegal operands `fsgnjn\.q a1,a2,a4'
+.*Error: illegal operands `fsgnjn\.q a0,a1,a4'
+.*Error: illegal operands `fsgnjn\.q a0,a2,a1'
+.*Error: illegal operands `fsgnjx\.q a1,a2,a4'
+.*Error: illegal operands `fsgnjx\.q a0,a1,a4'
+.*Error: illegal operands `fsgnjx\.q a0,a2,a1'
+.*Error: illegal operands `fmv\.q a1,a2'
+.*Error: illegal operands `fmv\.q a0,a1'
+.*Error: illegal operands `fneg\.q a1,a2'
+.*Error: illegal operands `fneg\.q a0,a1'
+.*Error: illegal operands `fabs\.q a1,a2'
+.*Error: illegal operands `fabs\.q a0,a1'
+.*Error: illegal operands `feq\.q a0,a1,a4'
+.*Error: illegal operands `feq\.q a0,a2,a1'
+.*Error: illegal operands `flt\.q a0,a1,a4'
+.*Error: illegal operands `flt\.q a0,a2,a1'
+.*Error: illegal operands `fle\.q a0,a1,a4'
+.*Error: illegal operands `fle\.q a0,a2,a1'
+.*Error: illegal operands `fgt\.q a0,a1,a4'
+.*Error: illegal operands `fgt\.q a0,a2,a1'
+.*Error: illegal operands `fge\.q a0,a1,a4'
+.*Error: illegal operands `fge\.q a0,a2,a1'
+.*Error: illegal operands `fclass\.q a0,a1'
+.*Error: illegal operands `fcvt\.w\.q a0,a1'
+.*Error: illegal operands `fcvt\.w\.q a0,a1,rne'
+.*Error: illegal operands `fcvt\.w\.q a3,a1'
+.*Error: illegal operands `fcvt\.w\.q a3,a1,rne'
+.*Error: illegal operands `fcvt\.wu\.q a0,a1'
+.*Error: illegal operands `fcvt\.wu\.q a0,a1,rne'
+.*Error: illegal operands `fcvt\.wu\.q a3,a1'
+.*Error: illegal operands `fcvt\.wu\.q a3,a1,rne'
+.*Error: illegal operands `fcvt\.l\.q a0,a1'
+.*Error: illegal operands `fcvt\.l\.q a0,a1,rne'
+.*Error: illegal operands `fcvt\.l\.q a3,a1'
+.*Error: illegal operands `fcvt\.l\.q a3,a1,rne'
+.*Error: illegal operands `fcvt\.lu\.q a0,a1'
+.*Error: illegal operands `fcvt\.lu\.q a0,a1,rne'
+.*Error: illegal operands `fcvt\.lu\.q a3,a1'
+.*Error: illegal operands `fcvt\.lu\.q a3,a1,rne'
+.*Error: illegal operands `fcvt\.q\.w a1,a2'
+.*Error: illegal operands `fcvt\.q\.w a1,a3'
+.*Error: illegal operands `fcvt\.q\.wu a1,a2'
+.*Error: illegal operands `fcvt\.q\.wu a1,a3'
+.*Error: illegal operands `fcvt\.q\.l a1,a2'
+.*Error: illegal operands `fcvt\.q\.l a1,a2,rne'
+.*Error: illegal operands `fcvt\.q\.l a1,a3'
+.*Error: illegal operands `fcvt\.q\.l a1,a3,rne'
+.*Error: illegal operands `fcvt\.q\.lu a1,a2'
+.*Error: illegal operands `fcvt\.q\.lu a1,a2,rne'
+.*Error: illegal operands `fcvt\.q\.lu a1,a3'
+.*Error: illegal operands `fcvt\.q\.lu a1,a3,rne'
+.*Error: illegal operands `fcvt\.s\.q a0,a1'
+.*Error: illegal operands `fcvt\.s\.q a0,a1,rne'
+.*Error: illegal operands `fcvt\.s\.q a3,a1'
+.*Error: illegal operands `fcvt\.s\.q a3,a1,rne'
+.*Error: illegal operands `fcvt\.d\.q a0,a1'
+.*Error: illegal operands `fcvt\.d\.q a0,a1,rne'
+.*Error: illegal operands `fcvt\.d\.q a3,a1'
+.*Error: illegal operands `fcvt\.d\.q a3,a1,rne'
+.*Error: illegal operands `fcvt\.q\.s a1,a2'
+.*Error: illegal operands `fcvt\.q\.s a1,a3'
+.*Error: illegal operands `fcvt\.q\.d a1,a2'
+.*Error: illegal operands `fcvt\.q\.d a1,a3'
diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.s b/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.s
new file mode 100644
index 00000000000..36680e0c47a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.s
@@ -0,0 +1,138 @@
+target:
+	fadd.q	a1, a2, a4
+	fadd.q	a1, a2, a4, rne
+	fadd.q	a0, a1, a4
+	fadd.q	a0, a1, a4, rne
+	fadd.q	a0, a2, a1
+	fadd.q	a0, a2, a1, rne
+	fsub.q	a1, a2, a4
+	fsub.q	a1, a2, a4, rne
+	fsub.q	a0, a1, a4
+	fsub.q	a0, a1, a4, rne
+	fsub.q	a0, a2, a1
+	fsub.q	a0, a2, a1, rne
+	fmul.q	a1, a2, a4
+	fmul.q	a1, a2, a4, rne
+	fmul.q	a0, a1, a4
+	fmul.q	a0, a1, a4, rne
+	fmul.q	a0, a2, a1
+	fmul.q	a0, a2, a1, rne
+	fdiv.q	a1, a2, a4
+	fdiv.q	a1, a2, a4, rne
+	fdiv.q	a0, a1, a4
+	fdiv.q	a0, a1, a4, rne
+	fdiv.q	a0, a2, a1
+	fdiv.q	a0, a2, a1, rne
+	fsqrt.q	a1, a2
+	fsqrt.q	a1, a2, rne
+	fsqrt.q	a0, a1
+	fsqrt.q	a0, a1, rne
+	fmin.q	a1, a2, a4
+	fmin.q	a0, a1, a4
+	fmin.q	a0, a2, a1
+	fmax.q	a1, a2, a4
+	fmax.q	a0, a1, a4
+	fmax.q	a0, a2, a1
+	fmadd.q	a1, a2, a4, a6
+	fmadd.q	a1, a2, a4, a6, rne
+	fmadd.q	a0, a1, a4, a6
+	fmadd.q	a0, a1, a4, a6, rne
+	fmadd.q	a0, a2, a1, a6
+	fmadd.q	a0, a2, a1, a6, rne
+	fmadd.q	a0, a2, a4, a1
+	fmadd.q	a0, a2, a4, a1, rne
+	fnmadd.q	a1, a2, a4, a6
+	fnmadd.q	a1, a2, a4, a6, rne
+	fnmadd.q	a0, a1, a4, a6
+	fnmadd.q	a0, a1, a4, a6, rne
+	fnmadd.q	a0, a2, a1, a6
+	fnmadd.q	a0, a2, a1, a6, rne
+	fnmadd.q	a0, a2, a4, a1
+	fnmadd.q	a0, a2, a4, a1, rne
+	fmsub.q	a1, a2, a4, a6
+	fmsub.q	a1, a2, a4, a6, rne
+	fmsub.q	a0, a1, a4, a6
+	fmsub.q	a0, a1, a4, a6, rne
+	fmsub.q	a0, a2, a1, a6
+	fmsub.q	a0, a2, a1, a6, rne
+	fmsub.q	a0, a2, a4, a1
+	fmsub.q	a0, a2, a4, a1, rne
+	fnmsub.q	a1, a2, a4, a6
+	fnmsub.q	a1, a2, a4, a6, rne
+	fnmsub.q	a0, a1, a4, a6
+	fnmsub.q	a0, a1, a4, a6, rne
+	fnmsub.q	a0, a2, a1, a6
+	fnmsub.q	a0, a2, a1, a6, rne
+	fnmsub.q	a0, a2, a4, a1
+	fnmsub.q	a0, a2, a4, a1, rne
+	fsgnj.q	a1, a2, a4
+	fsgnj.q	a0, a1, a4
+	fsgnj.q	a0, a2, a1
+	fsgnjn.q	a1, a2, a4
+	fsgnjn.q	a0, a1, a4
+	fsgnjn.q	a0, a2, a1
+	fsgnjx.q	a1, a2, a4
+	fsgnjx.q	a0, a1, a4
+	fsgnjx.q	a0, a2, a1
+	fmv.q	a1, a2
+	fmv.q	a0, a1
+	fneg.q	a1, a2
+	fneg.q	a0, a1
+	fabs.q	a1, a2
+	fabs.q	a0, a1
+	# Compare instructions: destination is a GPR
+	feq.q	a0, a1, a4
+	feq.q	a0, a2, a1
+	flt.q	a0, a1, a4
+	flt.q	a0, a2, a1
+	fle.q	a0, a1, a4
+	fle.q	a0, a2, a1
+	fgt.q	a0, a1, a4
+	fgt.q	a0, a2, a1
+	fge.q	a0, a1, a4
+	fge.q	a0, a2, a1
+	# fclass instruction: destination is a GPR
+	fclass.q	a0, a1
+	# fcvt instructions (float-int or int-float;
+	#                    integer operand register can be odd)
+	fcvt.w.q	a0, a1
+	fcvt.w.q	a0, a1, rne
+	fcvt.w.q	a3, a1
+	fcvt.w.q	a3, a1, rne
+	fcvt.wu.q	a0, a1
+	fcvt.wu.q	a0, a1, rne
+	fcvt.wu.q	a3, a1
+	fcvt.wu.q	a3, a1, rne
+	fcvt.l.q	a0, a1
+	fcvt.l.q	a0, a1, rne
+	fcvt.l.q	a3, a1
+	fcvt.l.q	a3, a1, rne
+	fcvt.lu.q	a0, a1
+	fcvt.lu.q	a0, a1, rne
+	fcvt.lu.q	a3, a1
+	fcvt.lu.q	a3, a1, rne
+	fcvt.q.w	a1, a2
+	fcvt.q.w	a1, a3
+	fcvt.q.wu	a1, a2
+	fcvt.q.wu	a1, a3
+	fcvt.q.l	a1, a2
+	fcvt.q.l	a1, a2, rne
+	fcvt.q.l	a1, a3
+	fcvt.q.l	a1, a3, rne
+	fcvt.q.lu	a1, a2
+	fcvt.q.lu	a1, a2, rne
+	fcvt.q.lu	a1, a3
+	fcvt.q.lu	a1, a3, rne
+	# fcvt instructions (float-float; FP32/FP64 operand can be odd)
+	fcvt.s.q	a0, a1
+	fcvt.s.q	a0, a1, rne
+	fcvt.s.q	a3, a1
+	fcvt.s.q	a3, a1, rne
+	fcvt.d.q	a0, a1
+	fcvt.d.q	a0, a1, rne
+	fcvt.d.q	a3, a1
+	fcvt.d.q	a3, a1, rne
+	fcvt.q.s	a1, a2
+	fcvt.q.s	a1, a3
+	fcvt.q.d	a1, a2
+	fcvt.q.d	a1, a3
diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair.d b/gas/testsuite/gas/riscv/zqinx-64-regpair.d
new file mode 100644
index 00000000000..039f979148d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zqinx-64-regpair.d
@@ -0,0 +1,86 @@
+#as: -march=rv64i_zqinx
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+06e67553[ 	]+fadd.q[ 	]+a0,a2,a4
+[ 	]+[0-9a-f]+:[ 	]+06e60553[ 	]+fadd.q[ 	]+a0,a2,a4,rne
+[ 	]+[0-9a-f]+:[ 	]+0ee67553[ 	]+fsub.q[ 	]+a0,a2,a4
+[ 	]+[0-9a-f]+:[ 	]+0ee60553[ 	]+fsub.q[ 	]+a0,a2,a4,rne
+[ 	]+[0-9a-f]+:[ 	]+16e67553[ 	]+fmul.q[ 	]+a0,a2,a4
+[ 	]+[0-9a-f]+:[ 	]+16e60553[ 	]+fmul.q[ 	]+a0,a2,a4,rne
+[ 	]+[0-9a-f]+:[ 	]+1ee67553[ 	]+fdiv.q[ 	]+a0,a2,a4
+[ 	]+[0-9a-f]+:[ 	]+1ee60553[ 	]+fdiv.q[ 	]+a0,a2,a4,rne
+[ 	]+[0-9a-f]+:[ 	]+5e067553[ 	]+fsqrt.q[ 	]+a0,a2
+[ 	]+[0-9a-f]+:[ 	]+5e060553[ 	]+fsqrt.q[ 	]+a0,a2,rne
+[ 	]+[0-9a-f]+:[ 	]+2ee60553[ 	]+fmin.q[ 	]+a0,a2,a4
+[ 	]+[0-9a-f]+:[ 	]+2ee61553[ 	]+fmax.q[ 	]+a0,a2,a4
+[ 	]+[0-9a-f]+:[ 	]+86e67543[ 	]+fmadd.q[ 	]+a0,a2,a4,a6
+[ 	]+[0-9a-f]+:[ 	]+86e60543[ 	]+fmadd.q[ 	]+a0,a2,a4,a6,rne
+[ 	]+[0-9a-f]+:[ 	]+86e6754f[ 	]+fnmadd.q[ 	]+a0,a2,a4,a6
+[ 	]+[0-9a-f]+:[ 	]+86e6054f[ 	]+fnmadd.q[ 	]+a0,a2,a4,a6,rne
+[ 	]+[0-9a-f]+:[ 	]+86e67547[ 	]+fmsub.q[ 	]+a0,a2,a4,a6
+[ 	]+[0-9a-f]+:[ 	]+86e60547[ 	]+fmsub.q[ 	]+a0,a2,a4,a6,rne
+[ 	]+[0-9a-f]+:[ 	]+86e6754b[ 	]+fnmsub.q[ 	]+a0,a2,a4,a6
+[ 	]+[0-9a-f]+:[ 	]+86e6054b[ 	]+fnmsub.q[ 	]+a0,a2,a4,a6,rne
+[ 	]+[0-9a-f]+:[ 	]+26e60553[ 	]+fsgnj.q[ 	]+a0,a2,a4
+[ 	]+[0-9a-f]+:[ 	]+26e61553[ 	]+fsgnjn.q[ 	]+a0,a2,a4
+[ 	]+[0-9a-f]+:[ 	]+26e62553[ 	]+fsgnjx.q[ 	]+a0,a2,a4
+[ 	]+[0-9a-f]+:[ 	]+26c60553[ 	]+fmv.q[ 	]+a0,a2
+[ 	]+[0-9a-f]+:[ 	]+26c61553[ 	]+fneg.q[ 	]+a0,a2
+[ 	]+[0-9a-f]+:[ 	]+26c62553[ 	]+fabs.q[ 	]+a0,a2
+[ 	]+[0-9a-f]+:[ 	]+a6e62553[ 	]+feq.q[ 	]+a0,a2,a4
+[ 	]+[0-9a-f]+:[ 	]+a6e625d3[ 	]+feq.q[ 	]+a1,a2,a4
+[ 	]+[0-9a-f]+:[ 	]+a6e61553[ 	]+flt.q[ 	]+a0,a2,a4
+[ 	]+[0-9a-f]+:[ 	]+a6e615d3[ 	]+flt.q[ 	]+a1,a2,a4
+[ 	]+[0-9a-f]+:[ 	]+a6e60553[ 	]+fle.q[ 	]+a0,a2,a4
+[ 	]+[0-9a-f]+:[ 	]+a6e605d3[ 	]+fle.q[ 	]+a1,a2,a4
+[ 	]+[0-9a-f]+:[ 	]+a6c71553[ 	]+flt.q[ 	]+a0,a4,a2
+[ 	]+[0-9a-f]+:[ 	]+a6c715d3[ 	]+flt.q[ 	]+a1,a4,a2
+[ 	]+[0-9a-f]+:[ 	]+a6c70553[ 	]+fle.q[ 	]+a0,a4,a2
+[ 	]+[0-9a-f]+:[ 	]+a6c705d3[ 	]+fle.q[ 	]+a1,a4,a2
+[ 	]+[0-9a-f]+:[ 	]+e6061553[ 	]+fclass.q[ 	]+a0,a2
+[ 	]+[0-9a-f]+:[ 	]+e60615d3[ 	]+fclass.q[ 	]+a1,a2
+[ 	]+[0-9a-f]+:[ 	]+c6067553[ 	]+fcvt.w.q[ 	]+a0,a2
+[ 	]+[0-9a-f]+:[ 	]+c6060553[ 	]+fcvt.w.q[ 	]+a0,a2,rne
+[ 	]+[0-9a-f]+:[ 	]+c60675d3[ 	]+fcvt.w.q[ 	]+a1,a2
+[ 	]+[0-9a-f]+:[ 	]+c60605d3[ 	]+fcvt.w.q[ 	]+a1,a2,rne
+[ 	]+[0-9a-f]+:[ 	]+c6167553[ 	]+fcvt.wu.q[ 	]+a0,a2
+[ 	]+[0-9a-f]+:[ 	]+c6160553[ 	]+fcvt.wu.q[ 	]+a0,a2,rne
+[ 	]+[0-9a-f]+:[ 	]+c61675d3[ 	]+fcvt.wu.q[ 	]+a1,a2
+[ 	]+[0-9a-f]+:[ 	]+c61605d3[ 	]+fcvt.wu.q[ 	]+a1,a2,rne
+[ 	]+[0-9a-f]+:[ 	]+c6267553[ 	]+fcvt.l.q[ 	]+a0,a2
+[ 	]+[0-9a-f]+:[ 	]+c6260553[ 	]+fcvt.l.q[ 	]+a0,a2,rne
+[ 	]+[0-9a-f]+:[ 	]+c62675d3[ 	]+fcvt.l.q[ 	]+a1,a2
+[ 	]+[0-9a-f]+:[ 	]+c62605d3[ 	]+fcvt.l.q[ 	]+a1,a2,rne
+[ 	]+[0-9a-f]+:[ 	]+c6367553[ 	]+fcvt.lu.q[ 	]+a0,a2
+[ 	]+[0-9a-f]+:[ 	]+c6360553[ 	]+fcvt.lu.q[ 	]+a0,a2,rne
+[ 	]+[0-9a-f]+:[ 	]+c63675d3[ 	]+fcvt.lu.q[ 	]+a1,a2
+[ 	]+[0-9a-f]+:[ 	]+c63605d3[ 	]+fcvt.lu.q[ 	]+a1,a2,rne
+[ 	]+[0-9a-f]+:[ 	]+d6060553[ 	]+fcvt.q.w[ 	]+a0,a2
+[ 	]+[0-9a-f]+:[ 	]+d6058553[ 	]+fcvt.q.w[ 	]+a0,a1
+[ 	]+[0-9a-f]+:[ 	]+d6160553[ 	]+fcvt.q.wu[ 	]+a0,a2
+[ 	]+[0-9a-f]+:[ 	]+d6158553[ 	]+fcvt.q.wu[ 	]+a0,a1
+[ 	]+[0-9a-f]+:[ 	]+d6260553[ 	]+fcvt.q.l[ 	]+a0,a2
+[ 	]+[0-9a-f]+:[ 	]+d6267553[ 	]+fcvt.q.l[ 	]+a0,a2,dyn
+[ 	]+[0-9a-f]+:[ 	]+d6258553[ 	]+fcvt.q.l[ 	]+a0,a1
+[ 	]+[0-9a-f]+:[ 	]+d625f553[ 	]+fcvt.q.l[ 	]+a0,a1,dyn
+[ 	]+[0-9a-f]+:[ 	]+d6360553[ 	]+fcvt.q.lu[ 	]+a0,a2
+[ 	]+[0-9a-f]+:[ 	]+d6367553[ 	]+fcvt.q.lu[ 	]+a0,a2,dyn
+[ 	]+[0-9a-f]+:[ 	]+d6358553[ 	]+fcvt.q.lu[ 	]+a0,a1
+[ 	]+[0-9a-f]+:[ 	]+d635f553[ 	]+fcvt.q.lu[ 	]+a0,a1,dyn
+[ 	]+[0-9a-f]+:[ 	]+40367553[ 	]+fcvt.s.q[ 	]+a0,a2
+[ 	]+[0-9a-f]+:[ 	]+40360553[ 	]+fcvt.s.q[ 	]+a0,a2,rne
+[ 	]+[0-9a-f]+:[ 	]+403675d3[ 	]+fcvt.s.q[ 	]+a1,a2
+[ 	]+[0-9a-f]+:[ 	]+403605d3[ 	]+fcvt.s.q[ 	]+a1,a2,rne
+[ 	]+[0-9a-f]+:[ 	]+42367553[ 	]+fcvt.d.q[ 	]+a0,a2
+[ 	]+[0-9a-f]+:[ 	]+42360553[ 	]+fcvt.d.q[ 	]+a0,a2,rne
+[ 	]+[0-9a-f]+:[ 	]+423675d3[ 	]+fcvt.d.q[ 	]+a1,a2
+[ 	]+[0-9a-f]+:[ 	]+423605d3[ 	]+fcvt.d.q[ 	]+a1,a2,rne
+[ 	]+[0-9a-f]+:[ 	]+46060553[ 	]+fcvt.q.s[ 	]+a0,a2
+[ 	]+[0-9a-f]+:[ 	]+46058553[ 	]+fcvt.q.s[ 	]+a0,a1
+[ 	]+[0-9a-f]+:[ 	]+46160553[ 	]+fcvt.q.d[ 	]+a0,a2
+[ 	]+[0-9a-f]+:[ 	]+46158553[ 	]+fcvt.q.d[ 	]+a0,a1
diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair.s b/gas/testsuite/gas/riscv/zqinx-64-regpair.s
new file mode 100644
index 00000000000..abb6dbd9258
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zqinx-64-regpair.s
@@ -0,0 +1,84 @@
+target:
+	fadd.q	a0, a2, a4
+	fadd.q	a0, a2, a4, rne
+	fsub.q	a0, a2, a4
+	fsub.q	a0, a2, a4, rne
+	fmul.q	a0, a2, a4
+	fmul.q	a0, a2, a4, rne
+	fdiv.q	a0, a2, a4
+	fdiv.q	a0, a2, a4, rne
+	fsqrt.q	a0, a2
+	fsqrt.q	a0, a2, rne
+	fmin.q	a0, a2, a4
+	fmax.q	a0, a2, a4
+	fmadd.q	a0, a2, a4, a6
+	fmadd.q	a0, a2, a4, a6, rne
+	fnmadd.q	a0, a2, a4, a6
+	fnmadd.q	a0, a2, a4, a6, rne
+	fmsub.q	a0, a2, a4, a6
+	fmsub.q	a0, a2, a4, a6, rne
+	fnmsub.q	a0, a2, a4, a6
+	fnmsub.q	a0, a2, a4, a6, rne
+	fsgnj.q	a0, a2, a4
+	fsgnjn.q	a0, a2, a4
+	fsgnjx.q	a0, a2, a4
+	fmv.q	a0, a2
+	fneg.q	a0, a2
+	fabs.q	a0, a2
+	# Compare instructions: destination is a GPR
+	feq.q	a0, a2, a4
+	feq.q	a1, a2, a4
+	flt.q	a0, a2, a4
+	flt.q	a1, a2, a4
+	fle.q	a0, a2, a4
+	fle.q	a1, a2, a4
+	fgt.q	a0, a2, a4
+	fgt.q	a1, a2, a4
+	fge.q	a0, a2, a4
+	fge.q	a1, a2, a4
+	# fclass instruction: destination is a GPR
+	fclass.q	a0, a2
+	fclass.q	a1, a2
+	# fcvt instructions (float-int or int-float;
+	#                    integer operand register can be odd)
+	fcvt.w.q	a0, a2
+	fcvt.w.q	a0, a2, rne
+	fcvt.w.q	a1, a2
+	fcvt.w.q	a1, a2, rne
+	fcvt.wu.q	a0, a2
+	fcvt.wu.q	a0, a2, rne
+	fcvt.wu.q	a1, a2
+	fcvt.wu.q	a1, a2, rne
+	fcvt.l.q	a0, a2
+	fcvt.l.q	a0, a2, rne
+	fcvt.l.q	a1, a2
+	fcvt.l.q	a1, a2, rne
+	fcvt.lu.q	a0, a2
+	fcvt.lu.q	a0, a2, rne
+	fcvt.lu.q	a1, a2
+	fcvt.lu.q	a1, a2, rne
+	fcvt.q.w	a0, a2
+	fcvt.q.w	a0, a1
+	fcvt.q.wu	a0, a2
+	fcvt.q.wu	a0, a1
+	fcvt.q.l	a0, a2
+	fcvt.q.l	a0, a2, dyn
+	fcvt.q.l	a0, a1
+	fcvt.q.l	a0, a1, dyn
+	fcvt.q.lu	a0, a2
+	fcvt.q.lu	a0, a2, dyn
+	fcvt.q.lu	a0, a1
+	fcvt.q.lu	a0, a1, dyn
+	# fcvt instructions (float-float; FP32/FP64 operand can be odd)
+	fcvt.s.q	a0, a2
+	fcvt.s.q	a0, a2, rne
+	fcvt.s.q	a1, a2
+	fcvt.s.q	a1, a2, rne
+	fcvt.d.q	a0, a2
+	fcvt.d.q	a0, a2, rne
+	fcvt.d.q	a1, a2
+	fcvt.d.q	a1, a2, rne
+	fcvt.q.s	a0, a2
+	fcvt.q.s	a0, a1
+	fcvt.q.d	a0, a2
+	fcvt.q.d	a0, a1
diff --git a/gas/testsuite/gas/riscv/zqinx-zhinxmin-32-regpair-fail.d b/gas/testsuite/gas/riscv/zqinx-zhinxmin-32-regpair-fail.d
new file mode 100644
index 00000000000..5a4987ee3b6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zqinx-zhinxmin-32-regpair-fail.d
@@ -0,0 +1,2 @@
+#as: -march=rv32i_zqinx_zhinxmin
+#error_output: zqinx-zhinxmin-32-regpair-fail.l
diff --git a/gas/testsuite/gas/riscv/zqinx-zhinxmin-32-regpair-fail.l b/gas/testsuite/gas/riscv/zqinx-zhinxmin-32-regpair-fail.l
new file mode 100644
index 00000000000..3705943d1e9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zqinx-zhinxmin-32-regpair-fail.l
@@ -0,0 +1,19 @@
+.*Assembler messages:
+.*Error: illegal operands `fcvt\.h\.q x16,x13'
+.*Error: illegal operands `fcvt\.h\.q x17,x13'
+.*Error: illegal operands `fcvt\.h\.q x18,x13'
+.*Error: illegal operands `fcvt\.h\.q x16,x14'
+.*Error: illegal operands `fcvt\.h\.q x17,x14'
+.*Error: illegal operands `fcvt\.h\.q x18,x14'
+.*Error: illegal operands `fcvt\.h\.q x16,x13,rne'
+.*Error: illegal operands `fcvt\.h\.q x17,x13,rne'
+.*Error: illegal operands `fcvt\.h\.q x18,x13,rne'
+.*Error: illegal operands `fcvt\.h\.q x16,x14,rne'
+.*Error: illegal operands `fcvt\.h\.q x17,x14,rne'
+.*Error: illegal operands `fcvt\.h\.q x18,x14,rne'
+.*Error: illegal operands `fcvt\.q\.h x13,x16'
+.*Error: illegal operands `fcvt\.q\.h x13,x17'
+.*Error: illegal operands `fcvt\.q\.h x13,x18'
+.*Error: illegal operands `fcvt\.q\.h x14,x16'
+.*Error: illegal operands `fcvt\.q\.h x14,x17'
+.*Error: illegal operands `fcvt\.q\.h x14,x18'
diff --git a/gas/testsuite/gas/riscv/zqinx-zhinxmin-32-regpair-fail.s b/gas/testsuite/gas/riscv/zqinx-zhinxmin-32-regpair-fail.s
new file mode 100644
index 00000000000..a2025704238
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zqinx-zhinxmin-32-regpair-fail.s
@@ -0,0 +1,20 @@
+target:
+	# fcvt instructions (float-float; FP16 operand can be odd)
+	fcvt.h.q	x16, x13
+	fcvt.h.q	x17, x13
+	fcvt.h.q	x18, x13
+	fcvt.h.q	x16, x14
+	fcvt.h.q	x17, x14
+	fcvt.h.q	x18, x14
+	fcvt.h.q	x16, x13, rne
+	fcvt.h.q	x17, x13, rne
+	fcvt.h.q	x18, x13, rne
+	fcvt.h.q	x16, x14, rne
+	fcvt.h.q	x17, x14, rne
+	fcvt.h.q	x18, x14, rne
+	fcvt.q.h	x13, x16
+	fcvt.q.h	x13, x17
+	fcvt.q.h	x13, x18
+	fcvt.q.h	x14, x16
+	fcvt.q.h	x14, x17
+	fcvt.q.h	x14, x18
diff --git a/gas/testsuite/gas/riscv/zqinx-zhinxmin-32-regpair.d b/gas/testsuite/gas/riscv/zqinx-zhinxmin-32-regpair.d
new file mode 100644
index 00000000000..c54edd23e64
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zqinx-zhinxmin-32-regpair.d
@@ -0,0 +1,14 @@
+#as: -march=rv32i_zqinx_zhinxmin
+#objdump: -dr -M numeric
+
+.*:[ 	]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+44367853[ 	]+fcvt.h.q[ 	]+x16,x12
+[ 	]+[0-9a-f]+:[ 	]+443678d3[ 	]+fcvt.h.q[ 	]+x17,x12
+[ 	]+[0-9a-f]+:[ 	]+44360853[ 	]+fcvt.h.q[ 	]+x16,x12,rne
+[ 	]+[0-9a-f]+:[ 	]+443608d3[ 	]+fcvt.h.q[ 	]+x17,x12,rne
+[ 	]+[0-9a-f]+:[ 	]+46280653[ 	]+fcvt.q.h[ 	]+x12,x16
+[ 	]+[0-9a-f]+:[ 	]+46288653[ 	]+fcvt.q.h[ 	]+x12,x17
diff --git a/gas/testsuite/gas/riscv/zqinx-zhinxmin-32-regpair.s b/gas/testsuite/gas/riscv/zqinx-zhinxmin-32-regpair.s
new file mode 100644
index 00000000000..40c71391a18
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zqinx-zhinxmin-32-regpair.s
@@ -0,0 +1,8 @@
+target:
+	# fcvt instructions (float-float; FP32 operand can be odd)
+	fcvt.h.q	x16, x12
+	fcvt.h.q	x17, x12
+	fcvt.h.q	x16, x12, rne
+	fcvt.h.q	x17, x12, rne
+	fcvt.q.h	x12, x16
+	fcvt.q.h	x12, x17
diff --git a/gas/testsuite/gas/riscv/zqinx-zhinxmin-64-regpair-fail.d b/gas/testsuite/gas/riscv/zqinx-zhinxmin-64-regpair-fail.d
new file mode 100644
index 00000000000..be8cba133e6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zqinx-zhinxmin-64-regpair-fail.d
@@ -0,0 +1,2 @@
+#as: -march=rv64i_zqinx_zhinxmin
+#error_output: zqinx-zhinxmin-64-regpair-fail.l
diff --git a/gas/testsuite/gas/riscv/zqinx-zhinxmin-64-regpair-fail.l b/gas/testsuite/gas/riscv/zqinx-zhinxmin-64-regpair-fail.l
new file mode 100644
index 00000000000..3c2bc19d301
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zqinx-zhinxmin-64-regpair-fail.l
@@ -0,0 +1,7 @@
+.*Assembler messages:
+.*Error: illegal operands `fcvt\.h\.q x16,x13'
+.*Error: illegal operands `fcvt\.h\.q x17,x13'
+.*Error: illegal operands `fcvt\.h\.q x16,x13,rne'
+.*Error: illegal operands `fcvt\.h\.q x17,x13,rne'
+.*Error: illegal operands `fcvt\.q\.h x13,x16'
+.*Error: illegal operands `fcvt\.q\.h x13,x17'
diff --git a/gas/testsuite/gas/riscv/zqinx-zhinxmin-64-regpair-fail.s b/gas/testsuite/gas/riscv/zqinx-zhinxmin-64-regpair-fail.s
new file mode 100644
index 00000000000..75e32cb40cf
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zqinx-zhinxmin-64-regpair-fail.s
@@ -0,0 +1,8 @@
+target:
+	# fcvt instructions (float-float; FP16 operand can be odd)
+	fcvt.h.q	x16, x13
+	fcvt.h.q	x17, x13
+	fcvt.h.q	x16, x13, rne
+	fcvt.h.q	x17, x13, rne
+	fcvt.q.h	x13, x16
+	fcvt.q.h	x13, x17
diff --git a/gas/testsuite/gas/riscv/zqinx-zhinxmin-64-regpair.d b/gas/testsuite/gas/riscv/zqinx-zhinxmin-64-regpair.d
new file mode 100644
index 00000000000..a537ff123cd
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zqinx-zhinxmin-64-regpair.d
@@ -0,0 +1,14 @@
+#as: -march=rv64i_zqinx_zhinxmin
+#objdump: -dr -M numeric
+
+.*:[ 	]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+44377653[ 	]+fcvt.h.q[ 	]+x12,x14
+[ 	]+[0-9a-f]+:[ 	]+443776d3[ 	]+fcvt.h.q[ 	]+x13,x14
+[ 	]+[0-9a-f]+:[ 	]+44370653[ 	]+fcvt.h.q[ 	]+x12,x14,rne
+[ 	]+[0-9a-f]+:[ 	]+443706d3[ 	]+fcvt.h.q[ 	]+x13,x14,rne
+[ 	]+[0-9a-f]+:[ 	]+46260753[ 	]+fcvt.q.h[ 	]+x14,x12
+[ 	]+[0-9a-f]+:[ 	]+46268753[ 	]+fcvt.q.h[ 	]+x14,x13
diff --git a/gas/testsuite/gas/riscv/zqinx-zhinxmin-64-regpair.s b/gas/testsuite/gas/riscv/zqinx-zhinxmin-64-regpair.s
new file mode 100644
index 00000000000..edfb1cfcbdc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zqinx-zhinxmin-64-regpair.s
@@ -0,0 +1,8 @@
+target:
+	# fcvt instructions (float-float; FP32 operand can be odd)
+	fcvt.h.q	x12, x14
+	fcvt.h.q	x13, x14
+	fcvt.h.q	x12, x14, rne
+	fcvt.h.q	x13, x14, rne
+	fcvt.q.h	x14, x12
+	fcvt.q.h	x14, x13
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 3cfe132babe..88c9bdde306 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -387,13 +387,19 @@ enum riscv_insn_class
   INSN_CLASS_ZMMUL,
   INSN_CLASS_ZAWRS,
   INSN_CLASS_F_OR_ZFINX,
-  INSN_CLASS_D_OR_ZDINX,
-  INSN_CLASS_Q_OR_ZQINX,
+  INSN_CLASS_D_OR_ZDINX,  /* Diagnostics only.  */
+  INSN_CLASS_Q_OR_ZQINX,  /* Diagnostics only.  */
+  INSN_CLASS_ZDINX,
+  INSN_CLASS_ZQINX,
   INSN_CLASS_ZFH_OR_ZHINX,
   INSN_CLASS_ZFHMIN,
   INSN_CLASS_ZFHMIN_OR_ZHINXMIN,
+  INSN_CLASS_ZFHMIN_AND_D_OR_X,  /* Diagnostics only.  */
+  INSN_CLASS_ZFHMIN_AND_Q_OR_X,  /* Diagnostics only.  */
   INSN_CLASS_ZFHMIN_AND_D,
   INSN_CLASS_ZFHMIN_AND_Q,
+  INSN_CLASS_ZHINXMIN_AND_ZDINX,
+  INSN_CLASS_ZHINXMIN_AND_ZQINX,
   INSN_CLASS_ZBA,
   INSN_CLASS_ZBB,
   INSN_CLASS_ZBC,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 7e95f645c5c..f17c8573a93 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -601,267 +601,377 @@ const struct riscv_opcode riscv_opcodes[] =
 {"remw",      64, INSN_CLASS_M,     "d,s,t",     MATCH_REMW, MASK_REMW, match_opcode, 0 },
 {"remuw",     64, INSN_CLASS_M,     "d,s,t",     MATCH_REMUW, MASK_REMUW, match_opcode, 0 },
 
-/* Half-precision floating-point instruction subset.  */
-{"flh",        0, INSN_CLASS_ZFHMIN,   "D,o(s)",    MATCH_FLH, MASK_FLH, match_opcode, INSN_DREF|INSN_2_BYTE },
-{"flh",        0, INSN_CLASS_ZFHMIN,   "D,A,s",     0, (int) M_FLH, match_never, INSN_MACRO },
-{"fsh",        0, INSN_CLASS_ZFHMIN,   "T,q(s)",    MATCH_FSH, MASK_FSH, match_opcode, INSN_DREF|INSN_2_BYTE },
-{"fsh",        0, INSN_CLASS_ZFHMIN,   "T,A,s",     0, (int) M_FSH, match_never, INSN_MACRO },
-{"fmv.x.h",    0, INSN_CLASS_ZFHMIN,   "d,S",       MATCH_FMV_X_H, MASK_FMV_X_H, match_opcode, 0 },
-{"fmv.h.x",    0, INSN_CLASS_ZFHMIN,   "D,s",       MATCH_FMV_H_X, MASK_FMV_H_X, match_opcode, 0 },
-{"fmv.h",      0, INSN_CLASS_ZFH_OR_ZHINX,   "D,U",       MATCH_FSGNJ_H, MASK_FSGNJ_H, match_rs1_eq_rs2, INSN_ALIAS },
-{"fneg.h",     0, INSN_CLASS_ZFH_OR_ZHINX,   "D,U",       MATCH_FSGNJN_H, MASK_FSGNJN_H, match_rs1_eq_rs2, INSN_ALIAS },
-{"fabs.h",     0, INSN_CLASS_ZFH_OR_ZHINX,   "D,U",       MATCH_FSGNJX_H, MASK_FSGNJX_H, match_rs1_eq_rs2, INSN_ALIAS },
-{"fsgnj.h",    0, INSN_CLASS_ZFH_OR_ZHINX,   "D,S,T",     MATCH_FSGNJ_H, MASK_FSGNJ_H, match_opcode, 0 },
-{"fsgnjn.h",   0, INSN_CLASS_ZFH_OR_ZHINX,   "D,S,T",     MATCH_FSGNJN_H, MASK_FSGNJN_H, match_opcode, 0 },
-{"fsgnjx.h",   0, INSN_CLASS_ZFH_OR_ZHINX,   "D,S,T",     MATCH_FSGNJX_H, MASK_FSGNJX_H, match_opcode, 0 },
-{"fadd.h",     0, INSN_CLASS_ZFH_OR_ZHINX,   "D,S,T",     MATCH_FADD_H|MASK_RM, MASK_FADD_H|MASK_RM, match_opcode, 0 },
-{"fadd.h",     0, INSN_CLASS_ZFH_OR_ZHINX,   "D,S,T,m",   MATCH_FADD_H, MASK_FADD_H, match_opcode, 0 },
-{"fsub.h",     0, INSN_CLASS_ZFH_OR_ZHINX,   "D,S,T",     MATCH_FSUB_H|MASK_RM, MASK_FSUB_H|MASK_RM, match_opcode, 0 },
-{"fsub.h",     0, INSN_CLASS_ZFH_OR_ZHINX,   "D,S,T,m",   MATCH_FSUB_H, MASK_FSUB_H, match_opcode, 0 },
-{"fmul.h",     0, INSN_CLASS_ZFH_OR_ZHINX,   "D,S,T",     MATCH_FMUL_H|MASK_RM, MASK_FMUL_H|MASK_RM, match_opcode, 0 },
-{"fmul.h",     0, INSN_CLASS_ZFH_OR_ZHINX,   "D,S,T,m",   MATCH_FMUL_H, MASK_FMUL_H, match_opcode, 0 },
-{"fdiv.h",     0, INSN_CLASS_ZFH_OR_ZHINX,   "D,S,T",     MATCH_FDIV_H|MASK_RM, MASK_FDIV_H|MASK_RM, match_opcode, 0 },
-{"fdiv.h",     0, INSN_CLASS_ZFH_OR_ZHINX,   "D,S,T,m",   MATCH_FDIV_H, MASK_FDIV_H, match_opcode, 0 },
-{"fsqrt.h",    0, INSN_CLASS_ZFH_OR_ZHINX,   "D,S",       MATCH_FSQRT_H|MASK_RM, MASK_FSQRT_H|MASK_RM, match_opcode, 0 },
-{"fsqrt.h",    0, INSN_CLASS_ZFH_OR_ZHINX,   "D,S,m",     MATCH_FSQRT_H, MASK_FSQRT_H, match_opcode, 0 },
-{"fmin.h",     0, INSN_CLASS_ZFH_OR_ZHINX,   "D,S,T",     MATCH_FMIN_H, MASK_FMIN_H, match_opcode, 0 },
-{"fmax.h",     0, INSN_CLASS_ZFH_OR_ZHINX,   "D,S,T",     MATCH_FMAX_H, MASK_FMAX_H, match_opcode, 0 },
-{"fmadd.h",    0, INSN_CLASS_ZFH_OR_ZHINX,   "D,S,T,R",   MATCH_FMADD_H|MASK_RM, MASK_FMADD_H|MASK_RM, match_opcode, 0 },
-{"fmadd.h",    0, INSN_CLASS_ZFH_OR_ZHINX,   "D,S,T,R,m", MATCH_FMADD_H, MASK_FMADD_H, match_opcode, 0 },
-{"fnmadd.h",   0, INSN_CLASS_ZFH_OR_ZHINX,   "D,S,T,R",   MATCH_FNMADD_H|MASK_RM, MASK_FNMADD_H|MASK_RM, match_opcode, 0 },
-{"fnmadd.h",   0, INSN_CLASS_ZFH_OR_ZHINX,   "D,S,T,R,m", MATCH_FNMADD_H, MASK_FNMADD_H, match_opcode, 0 },
-{"fmsub.h",    0, INSN_CLASS_ZFH_OR_ZHINX,   "D,S,T,R",   MATCH_FMSUB_H|MASK_RM, MASK_FMSUB_H|MASK_RM, match_opcode, 0 },
-{"fmsub.h",    0, INSN_CLASS_ZFH_OR_ZHINX,   "D,S,T,R,m", MATCH_FMSUB_H, MASK_FMSUB_H, match_opcode, 0 },
-{"fnmsub.h",   0, INSN_CLASS_ZFH_OR_ZHINX,   "D,S,T,R",   MATCH_FNMSUB_H|MASK_RM, MASK_FNMSUB_H|MASK_RM, match_opcode, 0 },
-{"fnmsub.h",   0, INSN_CLASS_ZFH_OR_ZHINX,   "D,S,T,R,m", MATCH_FNMSUB_H, MASK_FNMSUB_H, match_opcode, 0 },
-{"fcvt.w.h",   0, INSN_CLASS_ZFH_OR_ZHINX,   "d,S",       MATCH_FCVT_W_H|MASK_RM, MASK_FCVT_W_H|MASK_RM, match_opcode, 0 },
-{"fcvt.w.h",   0, INSN_CLASS_ZFH_OR_ZHINX,   "d,S,m",     MATCH_FCVT_W_H, MASK_FCVT_W_H, match_opcode, 0 },
-{"fcvt.wu.h",  0, INSN_CLASS_ZFH_OR_ZHINX,   "d,S",       MATCH_FCVT_WU_H|MASK_RM, MASK_FCVT_WU_H|MASK_RM, match_opcode, 0 },
-{"fcvt.wu.h",  0, INSN_CLASS_ZFH_OR_ZHINX,   "d,S,m",     MATCH_FCVT_WU_H, MASK_FCVT_WU_H, match_opcode, 0 },
-{"fcvt.h.w",   0, INSN_CLASS_ZFH_OR_ZHINX,   "D,s",       MATCH_FCVT_H_W|MASK_RM, MASK_FCVT_H_W|MASK_RM, match_opcode, 0 },
-{"fcvt.h.w",   0, INSN_CLASS_ZFH_OR_ZHINX,   "D,s,m",     MATCH_FCVT_H_W, MASK_FCVT_H_W, match_opcode, 0 },
-{"fcvt.h.wu",  0, INSN_CLASS_ZFH_OR_ZHINX,   "D,s",       MATCH_FCVT_H_WU|MASK_RM, MASK_FCVT_H_WU|MASK_RM, match_opcode, 0 },
-{"fcvt.h.wu",  0, INSN_CLASS_ZFH_OR_ZHINX,   "D,s,m",     MATCH_FCVT_H_WU, MASK_FCVT_H_WU, match_opcode, 0 },
-{"fcvt.s.h",   0, INSN_CLASS_ZFHMIN_OR_ZHINXMIN, "D,S",     MATCH_FCVT_S_H, MASK_FCVT_S_H|MASK_RM, match_opcode, 0 },
-{"fcvt.d.h",   0, INSN_CLASS_ZFHMIN_AND_D,     "D,S",       MATCH_FCVT_D_H, MASK_FCVT_D_H|MASK_RM, match_opcode, 0 },
-{"fcvt.q.h",   0, INSN_CLASS_ZFHMIN_AND_Q,     "D,S",       MATCH_FCVT_Q_H, MASK_FCVT_Q_H|MASK_RM, match_opcode, 0 },
-{"fcvt.h.s",   0, INSN_CLASS_ZFHMIN_OR_ZHINXMIN, "D,S",     MATCH_FCVT_H_S|MASK_RM, MASK_FCVT_H_S|MASK_RM, match_opcode, 0 },
-{"fcvt.h.s",   0, INSN_CLASS_ZFHMIN_OR_ZHINXMIN, "D,S,m",   MATCH_FCVT_H_S, MASK_FCVT_H_S, match_opcode, 0 },
-{"fcvt.h.d",   0, INSN_CLASS_ZFHMIN_AND_D,     "D,S",       MATCH_FCVT_H_D|MASK_RM, MASK_FCVT_H_D|MASK_RM, match_opcode, 0 },
-{"fcvt.h.d",   0, INSN_CLASS_ZFHMIN_AND_D,     "D,S,m",     MATCH_FCVT_H_D, MASK_FCVT_H_D, match_opcode, 0 },
-{"fcvt.h.q",   0, INSN_CLASS_ZFHMIN_AND_Q,     "D,S",       MATCH_FCVT_H_Q|MASK_RM, MASK_FCVT_H_Q|MASK_RM, match_opcode, 0 },
-{"fcvt.h.q",   0, INSN_CLASS_ZFHMIN_AND_Q,     "D,S,m",     MATCH_FCVT_H_Q, MASK_FCVT_H_Q, match_opcode, 0 },
-{"fclass.h",   0, INSN_CLASS_ZFH_OR_ZHINX,   "d,S",       MATCH_FCLASS_H, MASK_FCLASS_H, match_opcode, 0 },
-{"feq.h",      0, INSN_CLASS_ZFH_OR_ZHINX,   "d,S,T",     MATCH_FEQ_H, MASK_FEQ_H, match_opcode, 0 },
-{"flt.h",      0, INSN_CLASS_ZFH_OR_ZHINX,   "d,S,T",     MATCH_FLT_H, MASK_FLT_H, match_opcode, 0 },
-{"fle.h",      0, INSN_CLASS_ZFH_OR_ZHINX,   "d,S,T",     MATCH_FLE_H, MASK_FLE_H, match_opcode, 0 },
-{"fgt.h",      0, INSN_CLASS_ZFH_OR_ZHINX,   "d,T,S",     MATCH_FLT_H, MASK_FLT_H, match_opcode, 0 },
-{"fge.h",      0, INSN_CLASS_ZFH_OR_ZHINX,   "d,T,S",     MATCH_FLE_H, MASK_FLE_H, match_opcode, 0 },
-{"fcvt.l.h",  64, INSN_CLASS_ZFH_OR_ZHINX,   "d,S",       MATCH_FCVT_L_H|MASK_RM, MASK_FCVT_L_H|MASK_RM, match_opcode, 0 },
-{"fcvt.l.h",  64, INSN_CLASS_ZFH_OR_ZHINX,   "d,S,m",     MATCH_FCVT_L_H, MASK_FCVT_L_H, match_opcode, 0 },
-{"fcvt.lu.h", 64, INSN_CLASS_ZFH_OR_ZHINX,   "d,S",       MATCH_FCVT_LU_H|MASK_RM, MASK_FCVT_LU_H|MASK_RM, match_opcode, 0 },
-{"fcvt.lu.h", 64, INSN_CLASS_ZFH_OR_ZHINX,   "d,S,m",     MATCH_FCVT_LU_H, MASK_FCVT_LU_H, match_opcode, 0 },
-{"fcvt.h.l",  64, INSN_CLASS_ZFH_OR_ZHINX,   "D,s",       MATCH_FCVT_H_L|MASK_RM, MASK_FCVT_H_L|MASK_RM, match_opcode, 0 },
-{"fcvt.h.l",  64, INSN_CLASS_ZFH_OR_ZHINX,   "D,s,m",     MATCH_FCVT_H_L, MASK_FCVT_H_L, match_opcode, 0 },
-{"fcvt.h.lu", 64, INSN_CLASS_ZFH_OR_ZHINX,   "D,s",       MATCH_FCVT_H_LU|MASK_RM, MASK_FCVT_H_LU|MASK_RM, match_opcode, 0 },
-{"fcvt.h.lu", 64, INSN_CLASS_ZFH_OR_ZHINX,   "D,s,m",     MATCH_FCVT_H_LU, MASK_FCVT_H_LU, match_opcode, 0 },
+/* Half-precision floating-point instruction subset.
+   [DQ]/Z[dq]inx-related instructions that share the name must have INSN_HAS_EXT_VARS flag.  */
+{"flh",        0, INSN_CLASS_ZFHMIN,             "D,o(s)",    MATCH_FLH, MASK_FLH, match_opcode, INSN_DREF|INSN_2_BYTE },
+{"flh",        0, INSN_CLASS_ZFHMIN,             "D,A,s",     0, (int) M_FLH, match_never, INSN_MACRO },
+{"fsh",        0, INSN_CLASS_ZFHMIN,             "T,q(s)",    MATCH_FSH, MASK_FSH, match_opcode, INSN_DREF|INSN_2_BYTE },
+{"fsh",        0, INSN_CLASS_ZFHMIN,             "T,A,s",     0, (int) M_FSH, match_never, INSN_MACRO },
+{"fmv.x.h",    0, INSN_CLASS_ZFHMIN,             "d,S",       MATCH_FMV_X_H, MASK_FMV_X_H, match_opcode, 0 },
+{"fmv.h.x",    0, INSN_CLASS_ZFHMIN,             "D,s",       MATCH_FMV_H_X, MASK_FMV_H_X, match_opcode, 0 },
+{"fmv.h",      0, INSN_CLASS_ZFH_OR_ZHINX,       "D,U",       MATCH_FSGNJ_H, MASK_FSGNJ_H, match_rs1_eq_rs2, INSN_ALIAS },
+{"fneg.h",     0, INSN_CLASS_ZFH_OR_ZHINX,       "D,U",       MATCH_FSGNJN_H, MASK_FSGNJN_H, match_rs1_eq_rs2, INSN_ALIAS },
+{"fabs.h",     0, INSN_CLASS_ZFH_OR_ZHINX,       "D,U",       MATCH_FSGNJX_H, MASK_FSGNJX_H, match_rs1_eq_rs2, INSN_ALIAS },
+{"fsgnj.h",    0, INSN_CLASS_ZFH_OR_ZHINX,       "D,S,T",     MATCH_FSGNJ_H, MASK_FSGNJ_H, match_opcode, 0 },
+{"fsgnjn.h",   0, INSN_CLASS_ZFH_OR_ZHINX,       "D,S,T",     MATCH_FSGNJN_H, MASK_FSGNJN_H, match_opcode, 0 },
+{"fsgnjx.h",   0, INSN_CLASS_ZFH_OR_ZHINX,       "D,S,T",     MATCH_FSGNJX_H, MASK_FSGNJX_H, match_opcode, 0 },
+{"fadd.h",     0, INSN_CLASS_ZFH_OR_ZHINX,       "D,S,T",     MATCH_FADD_H|MASK_RM, MASK_FADD_H|MASK_RM, match_opcode, 0 },
+{"fadd.h",     0, INSN_CLASS_ZFH_OR_ZHINX,       "D,S,T,m",   MATCH_FADD_H, MASK_FADD_H, match_opcode, 0 },
+{"fsub.h",     0, INSN_CLASS_ZFH_OR_ZHINX,       "D,S,T",     MATCH_FSUB_H|MASK_RM, MASK_FSUB_H|MASK_RM, match_opcode, 0 },
+{"fsub.h",     0, INSN_CLASS_ZFH_OR_ZHINX,       "D,S,T,m",   MATCH_FSUB_H, MASK_FSUB_H, match_opcode, 0 },
+{"fmul.h",     0, INSN_CLASS_ZFH_OR_ZHINX,       "D,S,T",     MATCH_FMUL_H|MASK_RM, MASK_FMUL_H|MASK_RM, match_opcode, 0 },
+{"fmul.h",     0, INSN_CLASS_ZFH_OR_ZHINX,       "D,S,T,m",   MATCH_FMUL_H, MASK_FMUL_H, match_opcode, 0 },
+{"fdiv.h",     0, INSN_CLASS_ZFH_OR_ZHINX,       "D,S,T",     MATCH_FDIV_H|MASK_RM, MASK_FDIV_H|MASK_RM, match_opcode, 0 },
+{"fdiv.h",     0, INSN_CLASS_ZFH_OR_ZHINX,       "D,S,T,m",   MATCH_FDIV_H, MASK_FDIV_H, match_opcode, 0 },
+{"fsqrt.h",    0, INSN_CLASS_ZFH_OR_ZHINX,       "D,S",       MATCH_FSQRT_H|MASK_RM, MASK_FSQRT_H|MASK_RM, match_opcode, 0 },
+{"fsqrt.h",    0, INSN_CLASS_ZFH_OR_ZHINX,       "D,S,m",     MATCH_FSQRT_H, MASK_FSQRT_H, match_opcode, 0 },
+{"fmin.h",     0, INSN_CLASS_ZFH_OR_ZHINX,       "D,S,T",     MATCH_FMIN_H, MASK_FMIN_H, match_opcode, 0 },
+{"fmax.h",     0, INSN_CLASS_ZFH_OR_ZHINX,       "D,S,T",     MATCH_FMAX_H, MASK_FMAX_H, match_opcode, 0 },
+{"fmadd.h",    0, INSN_CLASS_ZFH_OR_ZHINX,       "D,S,T,R",   MATCH_FMADD_H|MASK_RM, MASK_FMADD_H|MASK_RM, match_opcode, 0 },
+{"fmadd.h",    0, INSN_CLASS_ZFH_OR_ZHINX,       "D,S,T,R,m", MATCH_FMADD_H, MASK_FMADD_H, match_opcode, 0 },
+{"fnmadd.h",   0, INSN_CLASS_ZFH_OR_ZHINX,       "D,S,T,R",   MATCH_FNMADD_H|MASK_RM, MASK_FNMADD_H|MASK_RM, match_opcode, 0 },
+{"fnmadd.h",   0, INSN_CLASS_ZFH_OR_ZHINX,       "D,S,T,R,m", MATCH_FNMADD_H, MASK_FNMADD_H, match_opcode, 0 },
+{"fmsub.h",    0, INSN_CLASS_ZFH_OR_ZHINX,       "D,S,T,R",   MATCH_FMSUB_H|MASK_RM, MASK_FMSUB_H|MASK_RM, match_opcode, 0 },
+{"fmsub.h",    0, INSN_CLASS_ZFH_OR_ZHINX,       "D,S,T,R,m", MATCH_FMSUB_H, MASK_FMSUB_H, match_opcode, 0 },
+{"fnmsub.h",   0, INSN_CLASS_ZFH_OR_ZHINX,       "D,S,T,R",   MATCH_FNMSUB_H|MASK_RM, MASK_FNMSUB_H|MASK_RM, match_opcode, 0 },
+{"fnmsub.h",   0, INSN_CLASS_ZFH_OR_ZHINX,       "D,S,T,R,m", MATCH_FNMSUB_H, MASK_FNMSUB_H, match_opcode, 0 },
+{"fcvt.w.h",   0, INSN_CLASS_ZFH_OR_ZHINX,       "d,S",       MATCH_FCVT_W_H|MASK_RM, MASK_FCVT_W_H|MASK_RM, match_opcode, 0 },
+{"fcvt.w.h",   0, INSN_CLASS_ZFH_OR_ZHINX,       "d,S,m",     MATCH_FCVT_W_H, MASK_FCVT_W_H, match_opcode, 0 },
+{"fcvt.wu.h",  0, INSN_CLASS_ZFH_OR_ZHINX,       "d,S",       MATCH_FCVT_WU_H|MASK_RM, MASK_FCVT_WU_H|MASK_RM, match_opcode, 0 },
+{"fcvt.wu.h",  0, INSN_CLASS_ZFH_OR_ZHINX,       "d,S,m",     MATCH_FCVT_WU_H, MASK_FCVT_WU_H, match_opcode, 0 },
+{"fcvt.h.w",   0, INSN_CLASS_ZFH_OR_ZHINX,       "D,s",       MATCH_FCVT_H_W|MASK_RM, MASK_FCVT_H_W|MASK_RM, match_opcode, 0 },
+{"fcvt.h.w",   0, INSN_CLASS_ZFH_OR_ZHINX,       "D,s,m",     MATCH_FCVT_H_W, MASK_FCVT_H_W, match_opcode, 0 },
+{"fcvt.h.wu",  0, INSN_CLASS_ZFH_OR_ZHINX,       "D,s",       MATCH_FCVT_H_WU|MASK_RM, MASK_FCVT_H_WU|MASK_RM, match_opcode, 0 },
+{"fcvt.h.wu",  0, INSN_CLASS_ZFH_OR_ZHINX,       "D,s,m",     MATCH_FCVT_H_WU, MASK_FCVT_H_WU, match_opcode, 0 },
+{"fcvt.s.h",   0, INSN_CLASS_ZFHMIN_OR_ZHINXMIN, "D,S",       MATCH_FCVT_S_H, MASK_FCVT_S_H|MASK_RM, match_opcode, 0 },
+{"fcvt.d.h",   0, INSN_CLASS_ZFHMIN_AND_D,       "D,S",       MATCH_FCVT_D_H, MASK_FCVT_D_H|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.d.h",   0, INSN_CLASS_ZHINXMIN_AND_ZDINX, "l2d,l1s",   MATCH_FCVT_D_H, MASK_FCVT_D_H|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.q.h",   0, INSN_CLASS_ZFHMIN_AND_Q,       "D,S",       MATCH_FCVT_Q_H, MASK_FCVT_Q_H|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.q.h",   0, INSN_CLASS_ZHINXMIN_AND_ZQINX, "l4d,l1s",   MATCH_FCVT_Q_H, MASK_FCVT_Q_H|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.h.s",   0, INSN_CLASS_ZFHMIN_OR_ZHINXMIN, "D,S",       MATCH_FCVT_H_S|MASK_RM, MASK_FCVT_H_S|MASK_RM, match_opcode, 0 },
+{"fcvt.h.s",   0, INSN_CLASS_ZFHMIN_OR_ZHINXMIN, "D,S,m",     MATCH_FCVT_H_S, MASK_FCVT_H_S, match_opcode, 0 },
+{"fcvt.h.d",   0, INSN_CLASS_ZFHMIN_AND_D,       "D,S",       MATCH_FCVT_H_D|MASK_RM, MASK_FCVT_H_D|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.h.d",   0, INSN_CLASS_ZHINXMIN_AND_ZDINX, "l1d,l2s",   MATCH_FCVT_H_D|MASK_RM, MASK_FCVT_H_D|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.h.d",   0, INSN_CLASS_ZFHMIN_AND_D,       "D,S,m",     MATCH_FCVT_H_D, MASK_FCVT_H_D, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.h.d",   0, INSN_CLASS_ZHINXMIN_AND_ZDINX, "l1d,l2s,m", MATCH_FCVT_H_D, MASK_FCVT_H_D, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.h.q",   0, INSN_CLASS_ZFHMIN_AND_Q,       "D,S",       MATCH_FCVT_H_Q|MASK_RM, MASK_FCVT_H_Q|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.h.q",   0, INSN_CLASS_ZHINXMIN_AND_ZQINX, "l1d,l4s",   MATCH_FCVT_H_Q|MASK_RM, MASK_FCVT_H_Q|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.h.q",   0, INSN_CLASS_ZFHMIN_AND_Q,       "D,S,m",     MATCH_FCVT_H_Q, MASK_FCVT_H_Q, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.h.q",   0, INSN_CLASS_ZHINXMIN_AND_ZQINX, "l1d,l4s,m", MATCH_FCVT_H_Q, MASK_FCVT_H_Q, match_opcode, INSN_HAS_EXT_VARS },
+{"fclass.h",   0, INSN_CLASS_ZFH_OR_ZHINX,       "d,S",       MATCH_FCLASS_H, MASK_FCLASS_H, match_opcode, 0 },
+{"feq.h",      0, INSN_CLASS_ZFH_OR_ZHINX,       "d,S,T",     MATCH_FEQ_H, MASK_FEQ_H, match_opcode, 0 },
+{"flt.h",      0, INSN_CLASS_ZFH_OR_ZHINX,       "d,S,T",     MATCH_FLT_H, MASK_FLT_H, match_opcode, 0 },
+{"fle.h",      0, INSN_CLASS_ZFH_OR_ZHINX,       "d,S,T",     MATCH_FLE_H, MASK_FLE_H, match_opcode, 0 },
+{"fgt.h",      0, INSN_CLASS_ZFH_OR_ZHINX,       "d,T,S",     MATCH_FLT_H, MASK_FLT_H, match_opcode, 0 },
+{"fge.h",      0, INSN_CLASS_ZFH_OR_ZHINX,       "d,T,S",     MATCH_FLE_H, MASK_FLE_H, match_opcode, 0 },
+{"fcvt.l.h",  64, INSN_CLASS_ZFH_OR_ZHINX,       "d,S",       MATCH_FCVT_L_H|MASK_RM, MASK_FCVT_L_H|MASK_RM, match_opcode, 0 },
+{"fcvt.l.h",  64, INSN_CLASS_ZFH_OR_ZHINX,       "d,S,m",     MATCH_FCVT_L_H, MASK_FCVT_L_H, match_opcode, 0 },
+{"fcvt.lu.h", 64, INSN_CLASS_ZFH_OR_ZHINX,       "d,S",       MATCH_FCVT_LU_H|MASK_RM, MASK_FCVT_LU_H|MASK_RM, match_opcode, 0 },
+{"fcvt.lu.h", 64, INSN_CLASS_ZFH_OR_ZHINX,       "d,S,m",     MATCH_FCVT_LU_H, MASK_FCVT_LU_H, match_opcode, 0 },
+{"fcvt.h.l",  64, INSN_CLASS_ZFH_OR_ZHINX,       "D,s",       MATCH_FCVT_H_L|MASK_RM, MASK_FCVT_H_L|MASK_RM, match_opcode, 0 },
+{"fcvt.h.l",  64, INSN_CLASS_ZFH_OR_ZHINX,       "D,s,m",     MATCH_FCVT_H_L, MASK_FCVT_H_L, match_opcode, 0 },
+{"fcvt.h.lu", 64, INSN_CLASS_ZFH_OR_ZHINX,       "D,s",       MATCH_FCVT_H_LU|MASK_RM, MASK_FCVT_H_LU|MASK_RM, match_opcode, 0 },
+{"fcvt.h.lu", 64, INSN_CLASS_ZFH_OR_ZHINX,       "D,s,m",     MATCH_FCVT_H_LU, MASK_FCVT_H_LU, match_opcode, 0 },
 
 /* Single-precision floating-point instruction subset.  */
-{"frcsr",      0, INSN_CLASS_F_OR_ZFINX,   "d",         MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS },
-{"frsr",       0, INSN_CLASS_F_OR_ZFINX,   "d",         MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS },
-{"fscsr",      0, INSN_CLASS_F_OR_ZFINX,   "s",         MATCH_FSCSR, MASK_FSCSR|MASK_RD, match_opcode, INSN_ALIAS },
-{"fscsr",      0, INSN_CLASS_F_OR_ZFINX,   "d,s",       MATCH_FSCSR, MASK_FSCSR, match_opcode, INSN_ALIAS },
-{"fssr",       0, INSN_CLASS_F_OR_ZFINX,   "s",         MATCH_FSCSR, MASK_FSCSR|MASK_RD, match_opcode, INSN_ALIAS },
-{"fssr",       0, INSN_CLASS_F_OR_ZFINX,   "d,s",       MATCH_FSCSR, MASK_FSCSR, match_opcode, INSN_ALIAS },
-{"frrm",       0, INSN_CLASS_F_OR_ZFINX,   "d",         MATCH_FRRM, MASK_FRRM, match_opcode, INSN_ALIAS },
-{"fsrm",       0, INSN_CLASS_F_OR_ZFINX,   "s",         MATCH_FSRM, MASK_FSRM|MASK_RD, match_opcode, INSN_ALIAS },
-{"fsrm",       0, INSN_CLASS_F_OR_ZFINX,   "d,s",       MATCH_FSRM, MASK_FSRM, match_opcode, INSN_ALIAS },
-{"fsrmi",      0, INSN_CLASS_F_OR_ZFINX,   "d,Z",       MATCH_FSRMI, MASK_FSRMI, match_opcode, INSN_ALIAS },
-{"fsrmi",      0, INSN_CLASS_F_OR_ZFINX,   "Z",         MATCH_FSRMI, MASK_FSRMI|MASK_RD, match_opcode, INSN_ALIAS },
-{"frflags",    0, INSN_CLASS_F_OR_ZFINX,   "d",         MATCH_FRFLAGS, MASK_FRFLAGS, match_opcode, INSN_ALIAS },
-{"fsflags",    0, INSN_CLASS_F_OR_ZFINX,   "s",         MATCH_FSFLAGS, MASK_FSFLAGS|MASK_RD, match_opcode, INSN_ALIAS },
-{"fsflags",    0, INSN_CLASS_F_OR_ZFINX,   "d,s",       MATCH_FSFLAGS, MASK_FSFLAGS, match_opcode, INSN_ALIAS },
-{"fsflagsi",   0, INSN_CLASS_F_OR_ZFINX,   "d,Z",       MATCH_FSFLAGSI, MASK_FSFLAGSI, match_opcode, INSN_ALIAS },
-{"fsflagsi",   0, INSN_CLASS_F_OR_ZFINX,   "Z",         MATCH_FSFLAGSI, MASK_FSFLAGSI|MASK_RD, match_opcode, INSN_ALIAS },
-{"flw",       32, INSN_CLASS_F_AND_C, "D,Cm(Cc)",  MATCH_C_FLWSP, MASK_C_FLWSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE },
-{"flw",       32, INSN_CLASS_F_AND_C, "CD,Ck(Cs)", MATCH_C_FLW, MASK_C_FLW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE },
-{"flw",        0, INSN_CLASS_F,   "D,o(s)",    MATCH_FLW, MASK_FLW, match_opcode, INSN_DREF|INSN_4_BYTE },
-{"flw",        0, INSN_CLASS_F,   "D,A,s",     0, (int) M_FLW, match_never, INSN_MACRO },
-{"fsw",       32, INSN_CLASS_F_AND_C, "CT,CM(Cc)", MATCH_C_FSWSP, MASK_C_FSWSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE },
-{"fsw",       32, INSN_CLASS_F_AND_C, "CD,Ck(Cs)", MATCH_C_FSW, MASK_C_FSW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE },
-{"fsw",        0, INSN_CLASS_F,   "T,q(s)",    MATCH_FSW, MASK_FSW, match_opcode, INSN_DREF|INSN_4_BYTE },
-{"fsw",        0, INSN_CLASS_F,   "T,A,s",     0, (int) M_FSW, match_never, INSN_MACRO },
-{"fmv.x.w",    0, INSN_CLASS_F,   "d,S",       MATCH_FMV_X_S, MASK_FMV_X_S, match_opcode, 0 },
-{"fmv.w.x",    0, INSN_CLASS_F,   "D,s",       MATCH_FMV_S_X, MASK_FMV_S_X, match_opcode, 0 },
-{"fmv.x.s",    0, INSN_CLASS_F,   "d,S",       MATCH_FMV_X_S, MASK_FMV_X_S, match_opcode, 0 },
-{"fmv.s.x",    0, INSN_CLASS_F,   "D,s",       MATCH_FMV_S_X, MASK_FMV_S_X, match_opcode, 0 },
-{"fmv.s",      0, INSN_CLASS_F_OR_ZFINX,   "D,U",       MATCH_FSGNJ_S, MASK_FSGNJ_S, match_rs1_eq_rs2, INSN_ALIAS },
-{"fneg.s",     0, INSN_CLASS_F_OR_ZFINX,   "D,U",       MATCH_FSGNJN_S, MASK_FSGNJN_S, match_rs1_eq_rs2, INSN_ALIAS },
-{"fabs.s",     0, INSN_CLASS_F_OR_ZFINX,   "D,U",       MATCH_FSGNJX_S, MASK_FSGNJX_S, match_rs1_eq_rs2, INSN_ALIAS },
-{"fsgnj.s",    0, INSN_CLASS_F_OR_ZFINX,   "D,S,T",     MATCH_FSGNJ_S, MASK_FSGNJ_S, match_opcode, 0 },
-{"fsgnjn.s",   0, INSN_CLASS_F_OR_ZFINX,   "D,S,T",     MATCH_FSGNJN_S, MASK_FSGNJN_S, match_opcode, 0 },
-{"fsgnjx.s",   0, INSN_CLASS_F_OR_ZFINX,   "D,S,T",     MATCH_FSGNJX_S, MASK_FSGNJX_S, match_opcode, 0 },
-{"fadd.s",     0, INSN_CLASS_F_OR_ZFINX,   "D,S,T",     MATCH_FADD_S|MASK_RM, MASK_FADD_S|MASK_RM, match_opcode, 0 },
-{"fadd.s",     0, INSN_CLASS_F_OR_ZFINX,   "D,S,T,m",   MATCH_FADD_S, MASK_FADD_S, match_opcode, 0 },
-{"fsub.s",     0, INSN_CLASS_F_OR_ZFINX,   "D,S,T",     MATCH_FSUB_S|MASK_RM, MASK_FSUB_S|MASK_RM, match_opcode, 0 },
-{"fsub.s",     0, INSN_CLASS_F_OR_ZFINX,   "D,S,T,m",   MATCH_FSUB_S, MASK_FSUB_S, match_opcode, 0 },
-{"fmul.s",     0, INSN_CLASS_F_OR_ZFINX,   "D,S,T",     MATCH_FMUL_S|MASK_RM, MASK_FMUL_S|MASK_RM, match_opcode, 0 },
-{"fmul.s",     0, INSN_CLASS_F_OR_ZFINX,   "D,S,T,m",   MATCH_FMUL_S, MASK_FMUL_S, match_opcode, 0 },
-{"fdiv.s",     0, INSN_CLASS_F_OR_ZFINX,   "D,S,T",     MATCH_FDIV_S|MASK_RM, MASK_FDIV_S|MASK_RM, match_opcode, 0 },
-{"fdiv.s",     0, INSN_CLASS_F_OR_ZFINX,   "D,S,T,m",   MATCH_FDIV_S, MASK_FDIV_S, match_opcode, 0 },
-{"fsqrt.s",    0, INSN_CLASS_F_OR_ZFINX,   "D,S",       MATCH_FSQRT_S|MASK_RM, MASK_FSQRT_S|MASK_RM, match_opcode, 0 },
-{"fsqrt.s",    0, INSN_CLASS_F_OR_ZFINX,   "D,S,m",     MATCH_FSQRT_S, MASK_FSQRT_S, match_opcode, 0 },
-{"fmin.s",     0, INSN_CLASS_F_OR_ZFINX,   "D,S,T",     MATCH_FMIN_S, MASK_FMIN_S, match_opcode, 0 },
-{"fmax.s",     0, INSN_CLASS_F_OR_ZFINX,   "D,S,T",     MATCH_FMAX_S, MASK_FMAX_S, match_opcode, 0 },
-{"fmadd.s",    0, INSN_CLASS_F_OR_ZFINX,   "D,S,T,R",   MATCH_FMADD_S|MASK_RM, MASK_FMADD_S|MASK_RM, match_opcode, 0 },
-{"fmadd.s",    0, INSN_CLASS_F_OR_ZFINX,   "D,S,T,R,m", MATCH_FMADD_S, MASK_FMADD_S, match_opcode, 0 },
-{"fnmadd.s",   0, INSN_CLASS_F_OR_ZFINX,   "D,S,T,R",   MATCH_FNMADD_S|MASK_RM, MASK_FNMADD_S|MASK_RM, match_opcode, 0 },
-{"fnmadd.s",   0, INSN_CLASS_F_OR_ZFINX,   "D,S,T,R,m", MATCH_FNMADD_S, MASK_FNMADD_S, match_opcode, 0 },
-{"fmsub.s",    0, INSN_CLASS_F_OR_ZFINX,   "D,S,T,R",   MATCH_FMSUB_S|MASK_RM, MASK_FMSUB_S|MASK_RM, match_opcode, 0 },
-{"fmsub.s",    0, INSN_CLASS_F_OR_ZFINX,   "D,S,T,R,m", MATCH_FMSUB_S, MASK_FMSUB_S, match_opcode, 0 },
-{"fnmsub.s",   0, INSN_CLASS_F_OR_ZFINX,   "D,S,T,R",   MATCH_FNMSUB_S|MASK_RM, MASK_FNMSUB_S|MASK_RM, match_opcode, 0 },
-{"fnmsub.s",   0, INSN_CLASS_F_OR_ZFINX,   "D,S,T,R,m", MATCH_FNMSUB_S, MASK_FNMSUB_S, match_opcode, 0 },
-{"fcvt.w.s",   0, INSN_CLASS_F_OR_ZFINX,   "d,S",       MATCH_FCVT_W_S|MASK_RM, MASK_FCVT_W_S|MASK_RM, match_opcode, 0 },
-{"fcvt.w.s",   0, INSN_CLASS_F_OR_ZFINX,   "d,S,m",     MATCH_FCVT_W_S, MASK_FCVT_W_S, match_opcode, 0 },
-{"fcvt.wu.s",  0, INSN_CLASS_F_OR_ZFINX,   "d,S",       MATCH_FCVT_WU_S|MASK_RM, MASK_FCVT_WU_S|MASK_RM, match_opcode, 0 },
-{"fcvt.wu.s",  0, INSN_CLASS_F_OR_ZFINX,   "d,S,m",     MATCH_FCVT_WU_S, MASK_FCVT_WU_S, match_opcode, 0 },
-{"fcvt.s.w",   0, INSN_CLASS_F_OR_ZFINX,   "D,s",       MATCH_FCVT_S_W|MASK_RM, MASK_FCVT_S_W|MASK_RM, match_opcode, 0 },
-{"fcvt.s.w",   0, INSN_CLASS_F_OR_ZFINX,   "D,s,m",     MATCH_FCVT_S_W, MASK_FCVT_S_W, match_opcode, 0 },
-{"fcvt.s.wu",  0, INSN_CLASS_F_OR_ZFINX,   "D,s",       MATCH_FCVT_S_WU|MASK_RM, MASK_FCVT_S_WU|MASK_RM, match_opcode, 0 },
-{"fcvt.s.wu",  0, INSN_CLASS_F_OR_ZFINX,   "D,s,m",     MATCH_FCVT_S_WU, MASK_FCVT_S_WU, match_opcode, 0 },
-{"fclass.s",   0, INSN_CLASS_F_OR_ZFINX,   "d,S",       MATCH_FCLASS_S, MASK_FCLASS_S, match_opcode, 0 },
-{"feq.s",      0, INSN_CLASS_F_OR_ZFINX,   "d,S,T",     MATCH_FEQ_S, MASK_FEQ_S, match_opcode, 0 },
-{"flt.s",      0, INSN_CLASS_F_OR_ZFINX,   "d,S,T",     MATCH_FLT_S, MASK_FLT_S, match_opcode, 0 },
-{"fle.s",      0, INSN_CLASS_F_OR_ZFINX,   "d,S,T",     MATCH_FLE_S, MASK_FLE_S, match_opcode, 0 },
-{"fgt.s",      0, INSN_CLASS_F_OR_ZFINX,   "d,T,S",     MATCH_FLT_S, MASK_FLT_S, match_opcode, 0 },
-{"fge.s",      0, INSN_CLASS_F_OR_ZFINX,   "d,T,S",     MATCH_FLE_S, MASK_FLE_S, match_opcode, 0 },
-{"fcvt.l.s",  64, INSN_CLASS_F_OR_ZFINX,   "d,S",       MATCH_FCVT_L_S|MASK_RM, MASK_FCVT_L_S|MASK_RM, match_opcode, 0 },
-{"fcvt.l.s",  64, INSN_CLASS_F_OR_ZFINX,   "d,S,m",     MATCH_FCVT_L_S, MASK_FCVT_L_S, match_opcode, 0 },
-{"fcvt.lu.s", 64, INSN_CLASS_F_OR_ZFINX,   "d,S",       MATCH_FCVT_LU_S|MASK_RM, MASK_FCVT_LU_S|MASK_RM, match_opcode, 0 },
-{"fcvt.lu.s", 64, INSN_CLASS_F_OR_ZFINX,   "d,S,m",     MATCH_FCVT_LU_S, MASK_FCVT_LU_S, match_opcode, 0 },
-{"fcvt.s.l",  64, INSN_CLASS_F_OR_ZFINX,   "D,s",       MATCH_FCVT_S_L|MASK_RM, MASK_FCVT_S_L|MASK_RM, match_opcode, 0 },
-{"fcvt.s.l",  64, INSN_CLASS_F_OR_ZFINX,   "D,s,m",     MATCH_FCVT_S_L, MASK_FCVT_S_L, match_opcode, 0 },
-{"fcvt.s.lu", 64, INSN_CLASS_F_OR_ZFINX,   "D,s",       MATCH_FCVT_S_LU|MASK_RM, MASK_FCVT_S_LU|MASK_RM, match_opcode, 0 },
-{"fcvt.s.lu", 64, INSN_CLASS_F_OR_ZFINX,   "D,s,m",     MATCH_FCVT_S_LU, MASK_FCVT_S_LU, match_opcode, 0 },
-
-/* Double-precision floating-point instruction subset.  */
-{"fld",        0, INSN_CLASS_D_AND_C, "D,Cn(Cc)",  MATCH_C_FLDSP, MASK_C_FLDSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE },
-{"fld",        0, INSN_CLASS_D_AND_C, "CD,Cl(Cs)", MATCH_C_FLD, MASK_C_FLD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE },
-{"fld",        0, INSN_CLASS_D,   "D,o(s)",    MATCH_FLD, MASK_FLD, match_opcode, INSN_DREF|INSN_8_BYTE },
-{"fld",        0, INSN_CLASS_D,   "D,A,s",     0, (int) M_FLD, match_never, INSN_MACRO },
-{"fsd",        0, INSN_CLASS_D_AND_C, "CT,CN(Cc)", MATCH_C_FSDSP, MASK_C_FSDSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE },
-{"fsd",        0, INSN_CLASS_D_AND_C, "CD,Cl(Cs)", MATCH_C_FSD, MASK_C_FSD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE },
-{"fsd",        0, INSN_CLASS_D,   "T,q(s)",    MATCH_FSD, MASK_FSD, match_opcode, INSN_DREF|INSN_8_BYTE },
-{"fsd",        0, INSN_CLASS_D,   "T,A,s",     0, (int) M_FSD, match_never, INSN_MACRO },
-{"fmv.d",      0, INSN_CLASS_D_OR_ZDINX,   "D,U",       MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS },
-{"fneg.d",     0, INSN_CLASS_D_OR_ZDINX,   "D,U",       MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS },
-{"fabs.d",     0, INSN_CLASS_D_OR_ZDINX,   "D,U",       MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS },
-{"fsgnj.d",    0, INSN_CLASS_D_OR_ZDINX,   "D,S,T",     MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, 0 },
-{"fsgnjn.d",   0, INSN_CLASS_D_OR_ZDINX,   "D,S,T",     MATCH_FSGNJN_D, MASK_FSGNJN_D, match_opcode, 0 },
-{"fsgnjx.d",   0, INSN_CLASS_D_OR_ZDINX,   "D,S,T",     MATCH_FSGNJX_D, MASK_FSGNJX_D, match_opcode, 0 },
-{"fadd.d",     0, INSN_CLASS_D_OR_ZDINX,   "D,S,T",     MATCH_FADD_D|MASK_RM, MASK_FADD_D|MASK_RM, match_opcode, 0 },
-{"fadd.d",     0, INSN_CLASS_D_OR_ZDINX,   "D,S,T,m",   MATCH_FADD_D, MASK_FADD_D, match_opcode, 0 },
-{"fsub.d",     0, INSN_CLASS_D_OR_ZDINX,   "D,S,T",     MATCH_FSUB_D|MASK_RM, MASK_FSUB_D|MASK_RM, match_opcode, 0 },
-{"fsub.d",     0, INSN_CLASS_D_OR_ZDINX,   "D,S,T,m",   MATCH_FSUB_D, MASK_FSUB_D, match_opcode, 0 },
-{"fmul.d",     0, INSN_CLASS_D_OR_ZDINX,   "D,S,T",     MATCH_FMUL_D|MASK_RM, MASK_FMUL_D|MASK_RM, match_opcode, 0 },
-{"fmul.d",     0, INSN_CLASS_D_OR_ZDINX,   "D,S,T,m",   MATCH_FMUL_D, MASK_FMUL_D, match_opcode, 0 },
-{"fdiv.d",     0, INSN_CLASS_D_OR_ZDINX,   "D,S,T",     MATCH_FDIV_D|MASK_RM, MASK_FDIV_D|MASK_RM, match_opcode, 0 },
-{"fdiv.d",     0, INSN_CLASS_D_OR_ZDINX,   "D,S,T,m",   MATCH_FDIV_D, MASK_FDIV_D, match_opcode, 0 },
-{"fsqrt.d",    0, INSN_CLASS_D_OR_ZDINX,   "D,S",       MATCH_FSQRT_D|MASK_RM, MASK_FSQRT_D|MASK_RM, match_opcode, 0 },
-{"fsqrt.d",    0, INSN_CLASS_D_OR_ZDINX,   "D,S,m",     MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode, 0 },
-{"fmin.d",     0, INSN_CLASS_D_OR_ZDINX,   "D,S,T",     MATCH_FMIN_D, MASK_FMIN_D, match_opcode, 0 },
-{"fmax.d",     0, INSN_CLASS_D_OR_ZDINX,   "D,S,T",     MATCH_FMAX_D, MASK_FMAX_D, match_opcode, 0 },
-{"fmadd.d",    0, INSN_CLASS_D_OR_ZDINX,   "D,S,T,R",   MATCH_FMADD_D|MASK_RM, MASK_FMADD_D|MASK_RM, match_opcode, 0 },
-{"fmadd.d",    0, INSN_CLASS_D_OR_ZDINX,   "D,S,T,R,m", MATCH_FMADD_D, MASK_FMADD_D, match_opcode, 0 },
-{"fnmadd.d",   0, INSN_CLASS_D_OR_ZDINX,   "D,S,T,R",   MATCH_FNMADD_D|MASK_RM, MASK_FNMADD_D|MASK_RM, match_opcode, 0 },
-{"fnmadd.d",   0, INSN_CLASS_D_OR_ZDINX,   "D,S,T,R,m", MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode, 0 },
-{"fmsub.d",    0, INSN_CLASS_D_OR_ZDINX,   "D,S,T,R",   MATCH_FMSUB_D|MASK_RM, MASK_FMSUB_D|MASK_RM, match_opcode, 0 },
-{"fmsub.d",    0, INSN_CLASS_D_OR_ZDINX,   "D,S,T,R,m", MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode, 0 },
-{"fnmsub.d",   0, INSN_CLASS_D_OR_ZDINX,   "D,S,T,R",   MATCH_FNMSUB_D|MASK_RM, MASK_FNMSUB_D|MASK_RM, match_opcode, 0 },
-{"fnmsub.d",   0, INSN_CLASS_D_OR_ZDINX,   "D,S,T,R,m", MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode, 0 },
-{"fcvt.w.d",   0, INSN_CLASS_D_OR_ZDINX,   "d,S",       MATCH_FCVT_W_D|MASK_RM, MASK_FCVT_W_D|MASK_RM, match_opcode, 0 },
-{"fcvt.w.d",   0, INSN_CLASS_D_OR_ZDINX,   "d,S,m",     MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode, 0 },
-{"fcvt.wu.d",  0, INSN_CLASS_D_OR_ZDINX,   "d,S",       MATCH_FCVT_WU_D|MASK_RM, MASK_FCVT_WU_D|MASK_RM, match_opcode, 0 },
-{"fcvt.wu.d",  0, INSN_CLASS_D_OR_ZDINX,   "d,S,m",     MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode, 0 },
-{"fcvt.d.w",   0, INSN_CLASS_D_OR_ZDINX,   "D,s",       MATCH_FCVT_D_W, MASK_FCVT_D_W|MASK_RM, match_opcode, 0 },
-{"fcvt.d.wu",  0, INSN_CLASS_D_OR_ZDINX,   "D,s",       MATCH_FCVT_D_WU, MASK_FCVT_D_WU|MASK_RM, match_opcode, 0 },
-{"fcvt.d.s",   0, INSN_CLASS_D_OR_ZDINX,   "D,S",       MATCH_FCVT_D_S, MASK_FCVT_D_S|MASK_RM, match_opcode, 0 },
-{"fcvt.s.d",   0, INSN_CLASS_D_OR_ZDINX,   "D,S",       MATCH_FCVT_S_D|MASK_RM, MASK_FCVT_S_D|MASK_RM, match_opcode, 0 },
-{"fcvt.s.d",   0, INSN_CLASS_D_OR_ZDINX,   "D,S,m",     MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode, 0 },
-{"fclass.d",   0, INSN_CLASS_D_OR_ZDINX,   "d,S",       MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode, 0 },
-{"feq.d",      0, INSN_CLASS_D_OR_ZDINX,   "d,S,T",     MATCH_FEQ_D, MASK_FEQ_D, match_opcode, 0 },
-{"flt.d",      0, INSN_CLASS_D_OR_ZDINX,   "d,S,T",     MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 },
-{"fle.d",      0, INSN_CLASS_D_OR_ZDINX,   "d,S,T",     MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 },
-{"fgt.d",      0, INSN_CLASS_D_OR_ZDINX,   "d,T,S",     MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 },
-{"fge.d",      0, INSN_CLASS_D_OR_ZDINX,   "d,T,S",     MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 },
-{"fmv.x.d",   64, INSN_CLASS_D,   "d,S",       MATCH_FMV_X_D, MASK_FMV_X_D, match_opcode, 0 },
-{"fmv.d.x",   64, INSN_CLASS_D,   "D,s",       MATCH_FMV_D_X, MASK_FMV_D_X, match_opcode, 0 },
-{"fcvt.l.d",  64, INSN_CLASS_D_OR_ZDINX,   "d,S",       MATCH_FCVT_L_D|MASK_RM, MASK_FCVT_L_D|MASK_RM, match_opcode, 0 },
-{"fcvt.l.d",  64, INSN_CLASS_D_OR_ZDINX,   "d,S,m",     MATCH_FCVT_L_D, MASK_FCVT_L_D, match_opcode, 0 },
-{"fcvt.lu.d", 64, INSN_CLASS_D_OR_ZDINX,   "d,S",       MATCH_FCVT_LU_D|MASK_RM, MASK_FCVT_LU_D|MASK_RM, match_opcode, 0 },
-{"fcvt.lu.d", 64, INSN_CLASS_D_OR_ZDINX,   "d,S,m",     MATCH_FCVT_LU_D, MASK_FCVT_LU_D, match_opcode, 0 },
-{"fcvt.d.l",  64, INSN_CLASS_D_OR_ZDINX,   "D,s",       MATCH_FCVT_D_L|MASK_RM, MASK_FCVT_D_L|MASK_RM, match_opcode, 0 },
-{"fcvt.d.l",  64, INSN_CLASS_D_OR_ZDINX,   "D,s,m",     MATCH_FCVT_D_L, MASK_FCVT_D_L, match_opcode, 0 },
-{"fcvt.d.lu", 64, INSN_CLASS_D_OR_ZDINX,   "D,s",       MATCH_FCVT_D_LU|MASK_RM, MASK_FCVT_D_LU|MASK_RM, match_opcode, 0 },
-{"fcvt.d.lu", 64, INSN_CLASS_D_OR_ZDINX,   "D,s,m",     MATCH_FCVT_D_LU, MASK_FCVT_D_LU, match_opcode, 0 },
-
-/* Quad-precision floating-point instruction subset.  */
-{"flq",        0, INSN_CLASS_Q,   "D,o(s)",    MATCH_FLQ, MASK_FLQ, match_opcode, INSN_DREF|INSN_16_BYTE },
-{"flq",        0, INSN_CLASS_Q,   "D,A,s",     0, (int) M_FLQ, match_never, INSN_MACRO },
-{"fsq",        0, INSN_CLASS_Q,   "T,q(s)",    MATCH_FSQ, MASK_FSQ, match_opcode, INSN_DREF|INSN_16_BYTE },
-{"fsq",        0, INSN_CLASS_Q,   "T,A,s",     0, (int) M_FSQ, match_never, INSN_MACRO },
-{"fmv.q",      0, INSN_CLASS_Q_OR_ZQINX,   "D,U",       MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS },
-{"fneg.q",     0, INSN_CLASS_Q_OR_ZQINX,   "D,U",       MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2, INSN_ALIAS },
-{"fabs.q",     0, INSN_CLASS_Q_OR_ZQINX,   "D,U",       MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2, INSN_ALIAS },
-{"fsgnj.q",    0, INSN_CLASS_Q_OR_ZQINX,   "D,S,T",     MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode, 0 },
-{"fsgnjn.q",   0, INSN_CLASS_Q_OR_ZQINX,   "D,S,T",     MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_opcode, 0 },
-{"fsgnjx.q",   0, INSN_CLASS_Q_OR_ZQINX,   "D,S,T",     MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_opcode, 0 },
-{"fadd.q",     0, INSN_CLASS_Q_OR_ZQINX,   "D,S,T",     MATCH_FADD_Q|MASK_RM, MASK_FADD_Q|MASK_RM, match_opcode, 0 },
-{"fadd.q",     0, INSN_CLASS_Q_OR_ZQINX,   "D,S,T,m",   MATCH_FADD_Q, MASK_FADD_Q, match_opcode, 0 },
-{"fsub.q",     0, INSN_CLASS_Q_OR_ZQINX,   "D,S,T",     MATCH_FSUB_Q|MASK_RM, MASK_FSUB_Q|MASK_RM, match_opcode, 0 },
-{"fsub.q",     0, INSN_CLASS_Q_OR_ZQINX,   "D,S,T,m",   MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode, 0 },
-{"fmul.q",     0, INSN_CLASS_Q_OR_ZQINX,   "D,S,T",     MATCH_FMUL_Q|MASK_RM, MASK_FMUL_Q|MASK_RM, match_opcode, 0 },
-{"fmul.q",     0, INSN_CLASS_Q_OR_ZQINX,   "D,S,T,m",   MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode, 0 },
-{"fdiv.q",     0, INSN_CLASS_Q_OR_ZQINX,   "D,S,T",     MATCH_FDIV_Q|MASK_RM, MASK_FDIV_Q|MASK_RM, match_opcode, 0 },
-{"fdiv.q",     0, INSN_CLASS_Q_OR_ZQINX,   "D,S,T,m",   MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode, 0 },
-{"fsqrt.q",    0, INSN_CLASS_Q_OR_ZQINX,   "D,S",       MATCH_FSQRT_Q|MASK_RM, MASK_FSQRT_Q|MASK_RM, match_opcode, 0 },
-{"fsqrt.q",    0, INSN_CLASS_Q_OR_ZQINX,   "D,S,m",     MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode, 0 },
-{"fmin.q",     0, INSN_CLASS_Q_OR_ZQINX,   "D,S,T",     MATCH_FMIN_Q, MASK_FMIN_Q, match_opcode, 0 },
-{"fmax.q",     0, INSN_CLASS_Q_OR_ZQINX,   "D,S,T",     MATCH_FMAX_Q, MASK_FMAX_Q, match_opcode, 0 },
-{"fmadd.q",    0, INSN_CLASS_Q_OR_ZQINX,   "D,S,T,R",   MATCH_FMADD_Q|MASK_RM, MASK_FMADD_Q|MASK_RM, match_opcode, 0 },
-{"fmadd.q",    0, INSN_CLASS_Q_OR_ZQINX,   "D,S,T,R,m", MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode, 0 },
-{"fnmadd.q",   0, INSN_CLASS_Q_OR_ZQINX,   "D,S,T,R",   MATCH_FNMADD_Q|MASK_RM, MASK_FNMADD_Q|MASK_RM, match_opcode, 0 },
-{"fnmadd.q",   0, INSN_CLASS_Q_OR_ZQINX,   "D,S,T,R,m", MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode, 0 },
-{"fmsub.q",    0, INSN_CLASS_Q_OR_ZQINX,   "D,S,T,R",   MATCH_FMSUB_Q|MASK_RM, MASK_FMSUB_Q|MASK_RM, match_opcode, 0 },
-{"fmsub.q",    0, INSN_CLASS_Q_OR_ZQINX,   "D,S,T,R,m", MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode, 0 },
-{"fnmsub.q",   0, INSN_CLASS_Q_OR_ZQINX,   "D,S,T,R",   MATCH_FNMSUB_Q|MASK_RM, MASK_FNMSUB_Q|MASK_RM, match_opcode, 0 },
-{"fnmsub.q",   0, INSN_CLASS_Q_OR_ZQINX,   "D,S,T,R,m", MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode, 0 },
-{"fcvt.w.q",   0, INSN_CLASS_Q_OR_ZQINX,   "d,S",       MATCH_FCVT_W_Q|MASK_RM, MASK_FCVT_W_Q|MASK_RM, match_opcode, 0 },
-{"fcvt.w.q",   0, INSN_CLASS_Q_OR_ZQINX,   "d,S,m",     MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode, 0 },
-{"fcvt.wu.q",  0, INSN_CLASS_Q_OR_ZQINX,   "d,S",       MATCH_FCVT_WU_Q|MASK_RM, MASK_FCVT_WU_Q|MASK_RM, match_opcode, 0 },
-{"fcvt.wu.q",  0, INSN_CLASS_Q_OR_ZQINX,   "d,S,m",     MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode, 0 },
-{"fcvt.q.w",   0, INSN_CLASS_Q_OR_ZQINX,   "D,s",       MATCH_FCVT_Q_W, MASK_FCVT_Q_W|MASK_RM, match_opcode, 0 },
-{"fcvt.q.wu",  0, INSN_CLASS_Q_OR_ZQINX,   "D,s",       MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU|MASK_RM, match_opcode, 0 },
-{"fcvt.q.s",   0, INSN_CLASS_Q_OR_ZQINX,   "D,S",       MATCH_FCVT_Q_S, MASK_FCVT_Q_S|MASK_RM, match_opcode, 0 },
-{"fcvt.q.d",   0, INSN_CLASS_Q_OR_ZQINX,   "D,S",       MATCH_FCVT_Q_D, MASK_FCVT_Q_D|MASK_RM, match_opcode, 0 },
-{"fcvt.s.q",   0, INSN_CLASS_Q_OR_ZQINX,   "D,S",       MATCH_FCVT_S_Q|MASK_RM, MASK_FCVT_S_Q|MASK_RM, match_opcode, 0 },
-{"fcvt.s.q",   0, INSN_CLASS_Q_OR_ZQINX,   "D,S,m",     MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode, 0 },
-{"fcvt.d.q",   0, INSN_CLASS_Q_OR_ZQINX,   "D,S",       MATCH_FCVT_D_Q|MASK_RM, MASK_FCVT_D_Q|MASK_RM, match_opcode, 0 },
-{"fcvt.d.q",   0, INSN_CLASS_Q_OR_ZQINX,   "D,S,m",     MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode, 0 },
-{"fclass.q",   0, INSN_CLASS_Q_OR_ZQINX,   "d,S",       MATCH_FCLASS_Q, MASK_FCLASS_Q, match_opcode, 0 },
-{"feq.q",      0, INSN_CLASS_Q_OR_ZQINX,   "d,S,T",     MATCH_FEQ_Q, MASK_FEQ_Q, match_opcode, 0 },
-{"flt.q",      0, INSN_CLASS_Q_OR_ZQINX,   "d,S,T",     MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 },
-{"fle.q",      0, INSN_CLASS_Q_OR_ZQINX,   "d,S,T",     MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 },
-{"fgt.q",      0, INSN_CLASS_Q_OR_ZQINX,   "d,T,S",     MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 },
-{"fge.q",      0, INSN_CLASS_Q_OR_ZQINX,   "d,T,S",     MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 },
-{"fcvt.l.q",  64, INSN_CLASS_Q_OR_ZQINX,   "d,S",       MATCH_FCVT_L_Q|MASK_RM, MASK_FCVT_L_Q|MASK_RM, match_opcode, 0 },
-{"fcvt.l.q",  64, INSN_CLASS_Q_OR_ZQINX,   "d,S,m",     MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode, 0 },
-{"fcvt.lu.q", 64, INSN_CLASS_Q_OR_ZQINX,   "d,S",       MATCH_FCVT_LU_Q|MASK_RM, MASK_FCVT_LU_Q|MASK_RM, match_opcode, 0 },
-{"fcvt.lu.q", 64, INSN_CLASS_Q_OR_ZQINX,   "d,S,m",     MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode, 0 },
-{"fcvt.q.l",  64, INSN_CLASS_Q_OR_ZQINX,   "D,s",       MATCH_FCVT_Q_L, MASK_FCVT_Q_L|MASK_RM, match_opcode, 0 },
-{"fcvt.q.l",  64, INSN_CLASS_Q_OR_ZQINX,   "D,s,m",     MATCH_FCVT_Q_L, MASK_FCVT_Q_L, match_opcode, 0 },
-{"fcvt.q.lu", 64, INSN_CLASS_Q_OR_ZQINX,   "D,s",       MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU|MASK_RM, match_opcode, 0 },
-{"fcvt.q.lu", 64, INSN_CLASS_Q_OR_ZQINX,   "D,s,m",     MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU, match_opcode, 0 },
+{"frcsr",      0, INSN_CLASS_F_OR_ZFINX, "d",         MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS },
+{"frsr",       0, INSN_CLASS_F_OR_ZFINX, "d",         MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS },
+{"fscsr",      0, INSN_CLASS_F_OR_ZFINX, "s",         MATCH_FSCSR, MASK_FSCSR|MASK_RD, match_opcode, INSN_ALIAS },
+{"fscsr",      0, INSN_CLASS_F_OR_ZFINX, "d,s",       MATCH_FSCSR, MASK_FSCSR, match_opcode, INSN_ALIAS },
+{"fssr",       0, INSN_CLASS_F_OR_ZFINX, "s",         MATCH_FSCSR, MASK_FSCSR|MASK_RD, match_opcode, INSN_ALIAS },
+{"fssr",       0, INSN_CLASS_F_OR_ZFINX, "d,s",       MATCH_FSCSR, MASK_FSCSR, match_opcode, INSN_ALIAS },
+{"frrm",       0, INSN_CLASS_F_OR_ZFINX, "d",         MATCH_FRRM, MASK_FRRM, match_opcode, INSN_ALIAS },
+{"fsrm",       0, INSN_CLASS_F_OR_ZFINX, "s",         MATCH_FSRM, MASK_FSRM|MASK_RD, match_opcode, INSN_ALIAS },
+{"fsrm",       0, INSN_CLASS_F_OR_ZFINX, "d,s",       MATCH_FSRM, MASK_FSRM, match_opcode, INSN_ALIAS },
+{"fsrmi",      0, INSN_CLASS_F_OR_ZFINX, "d,Z",       MATCH_FSRMI, MASK_FSRMI, match_opcode, INSN_ALIAS },
+{"fsrmi",      0, INSN_CLASS_F_OR_ZFINX, "Z",         MATCH_FSRMI, MASK_FSRMI|MASK_RD, match_opcode, INSN_ALIAS },
+{"frflags",    0, INSN_CLASS_F_OR_ZFINX, "d",         MATCH_FRFLAGS, MASK_FRFLAGS, match_opcode, INSN_ALIAS },
+{"fsflags",    0, INSN_CLASS_F_OR_ZFINX, "s",         MATCH_FSFLAGS, MASK_FSFLAGS|MASK_RD, match_opcode, INSN_ALIAS },
+{"fsflags",    0, INSN_CLASS_F_OR_ZFINX, "d,s",       MATCH_FSFLAGS, MASK_FSFLAGS, match_opcode, INSN_ALIAS },
+{"fsflagsi",   0, INSN_CLASS_F_OR_ZFINX, "d,Z",       MATCH_FSFLAGSI, MASK_FSFLAGSI, match_opcode, INSN_ALIAS },
+{"fsflagsi",   0, INSN_CLASS_F_OR_ZFINX, "Z",         MATCH_FSFLAGSI, MASK_FSFLAGSI|MASK_RD, match_opcode, INSN_ALIAS },
+{"flw",       32, INSN_CLASS_F_AND_C,    "D,Cm(Cc)",  MATCH_C_FLWSP, MASK_C_FLWSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE },
+{"flw",       32, INSN_CLASS_F_AND_C,    "CD,Ck(Cs)", MATCH_C_FLW, MASK_C_FLW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE },
+{"flw",        0, INSN_CLASS_F,          "D,o(s)",    MATCH_FLW, MASK_FLW, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"flw",        0, INSN_CLASS_F,          "D,A,s",     0, (int) M_FLW, match_never, INSN_MACRO },
+{"fsw",       32, INSN_CLASS_F_AND_C,    "CT,CM(Cc)", MATCH_C_FSWSP, MASK_C_FSWSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE },
+{"fsw",       32, INSN_CLASS_F_AND_C,    "CD,Ck(Cs)", MATCH_C_FSW, MASK_C_FSW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE },
+{"fsw",        0, INSN_CLASS_F,          "T,q(s)",    MATCH_FSW, MASK_FSW, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"fsw",        0, INSN_CLASS_F,          "T,A,s",     0, (int) M_FSW, match_never, INSN_MACRO },
+{"fmv.x.w",    0, INSN_CLASS_F,          "d,S",       MATCH_FMV_X_S, MASK_FMV_X_S, match_opcode, 0 },
+{"fmv.w.x",    0, INSN_CLASS_F,          "D,s",       MATCH_FMV_S_X, MASK_FMV_S_X, match_opcode, 0 },
+{"fmv.x.s",    0, INSN_CLASS_F,          "d,S",       MATCH_FMV_X_S, MASK_FMV_X_S, match_opcode, 0 },
+{"fmv.s.x",    0, INSN_CLASS_F,          "D,s",       MATCH_FMV_S_X, MASK_FMV_S_X, match_opcode, 0 },
+{"fmv.s",      0, INSN_CLASS_F_OR_ZFINX, "D,U",       MATCH_FSGNJ_S, MASK_FSGNJ_S, match_rs1_eq_rs2, INSN_ALIAS },
+{"fneg.s",     0, INSN_CLASS_F_OR_ZFINX, "D,U",       MATCH_FSGNJN_S, MASK_FSGNJN_S, match_rs1_eq_rs2, INSN_ALIAS },
+{"fabs.s",     0, INSN_CLASS_F_OR_ZFINX, "D,U",       MATCH_FSGNJX_S, MASK_FSGNJX_S, match_rs1_eq_rs2, INSN_ALIAS },
+{"fsgnj.s",    0, INSN_CLASS_F_OR_ZFINX, "D,S,T",     MATCH_FSGNJ_S, MASK_FSGNJ_S, match_opcode, 0 },
+{"fsgnjn.s",   0, INSN_CLASS_F_OR_ZFINX, "D,S,T",     MATCH_FSGNJN_S, MASK_FSGNJN_S, match_opcode, 0 },
+{"fsgnjx.s",   0, INSN_CLASS_F_OR_ZFINX, "D,S,T",     MATCH_FSGNJX_S, MASK_FSGNJX_S, match_opcode, 0 },
+{"fadd.s",     0, INSN_CLASS_F_OR_ZFINX, "D,S,T",     MATCH_FADD_S|MASK_RM, MASK_FADD_S|MASK_RM, match_opcode, 0 },
+{"fadd.s",     0, INSN_CLASS_F_OR_ZFINX, "D,S,T,m",   MATCH_FADD_S, MASK_FADD_S, match_opcode, 0 },
+{"fsub.s",     0, INSN_CLASS_F_OR_ZFINX, "D,S,T",     MATCH_FSUB_S|MASK_RM, MASK_FSUB_S|MASK_RM, match_opcode, 0 },
+{"fsub.s",     0, INSN_CLASS_F_OR_ZFINX, "D,S,T,m",   MATCH_FSUB_S, MASK_FSUB_S, match_opcode, 0 },
+{"fmul.s",     0, INSN_CLASS_F_OR_ZFINX, "D,S,T",     MATCH_FMUL_S|MASK_RM, MASK_FMUL_S|MASK_RM, match_opcode, 0 },
+{"fmul.s",     0, INSN_CLASS_F_OR_ZFINX, "D,S,T,m",   MATCH_FMUL_S, MASK_FMUL_S, match_opcode, 0 },
+{"fdiv.s",     0, INSN_CLASS_F_OR_ZFINX, "D,S,T",     MATCH_FDIV_S|MASK_RM, MASK_FDIV_S|MASK_RM, match_opcode, 0 },
+{"fdiv.s",     0, INSN_CLASS_F_OR_ZFINX, "D,S,T,m",   MATCH_FDIV_S, MASK_FDIV_S, match_opcode, 0 },
+{"fsqrt.s",    0, INSN_CLASS_F_OR_ZFINX, "D,S",       MATCH_FSQRT_S|MASK_RM, MASK_FSQRT_S|MASK_RM, match_opcode, 0 },
+{"fsqrt.s",    0, INSN_CLASS_F_OR_ZFINX, "D,S,m",     MATCH_FSQRT_S, MASK_FSQRT_S, match_opcode, 0 },
+{"fmin.s",     0, INSN_CLASS_F_OR_ZFINX, "D,S,T",     MATCH_FMIN_S, MASK_FMIN_S, match_opcode, 0 },
+{"fmax.s",     0, INSN_CLASS_F_OR_ZFINX, "D,S,T",     MATCH_FMAX_S, MASK_FMAX_S, match_opcode, 0 },
+{"fmadd.s",    0, INSN_CLASS_F_OR_ZFINX, "D,S,T,R",   MATCH_FMADD_S|MASK_RM, MASK_FMADD_S|MASK_RM, match_opcode, 0 },
+{"fmadd.s",    0, INSN_CLASS_F_OR_ZFINX, "D,S,T,R,m", MATCH_FMADD_S, MASK_FMADD_S, match_opcode, 0 },
+{"fnmadd.s",   0, INSN_CLASS_F_OR_ZFINX, "D,S,T,R",   MATCH_FNMADD_S|MASK_RM, MASK_FNMADD_S|MASK_RM, match_opcode, 0 },
+{"fnmadd.s",   0, INSN_CLASS_F_OR_ZFINX, "D,S,T,R,m", MATCH_FNMADD_S, MASK_FNMADD_S, match_opcode, 0 },
+{"fmsub.s",    0, INSN_CLASS_F_OR_ZFINX, "D,S,T,R",   MATCH_FMSUB_S|MASK_RM, MASK_FMSUB_S|MASK_RM, match_opcode, 0 },
+{"fmsub.s",    0, INSN_CLASS_F_OR_ZFINX, "D,S,T,R,m", MATCH_FMSUB_S, MASK_FMSUB_S, match_opcode, 0 },
+{"fnmsub.s",   0, INSN_CLASS_F_OR_ZFINX, "D,S,T,R",   MATCH_FNMSUB_S|MASK_RM, MASK_FNMSUB_S|MASK_RM, match_opcode, 0 },
+{"fnmsub.s",   0, INSN_CLASS_F_OR_ZFINX, "D,S,T,R,m", MATCH_FNMSUB_S, MASK_FNMSUB_S, match_opcode, 0 },
+{"fcvt.w.s",   0, INSN_CLASS_F_OR_ZFINX, "d,S",       MATCH_FCVT_W_S|MASK_RM, MASK_FCVT_W_S|MASK_RM, match_opcode, 0 },
+{"fcvt.w.s",   0, INSN_CLASS_F_OR_ZFINX, "d,S,m",     MATCH_FCVT_W_S, MASK_FCVT_W_S, match_opcode, 0 },
+{"fcvt.wu.s",  0, INSN_CLASS_F_OR_ZFINX, "d,S",       MATCH_FCVT_WU_S|MASK_RM, MASK_FCVT_WU_S|MASK_RM, match_opcode, 0 },
+{"fcvt.wu.s",  0, INSN_CLASS_F_OR_ZFINX, "d,S,m",     MATCH_FCVT_WU_S, MASK_FCVT_WU_S, match_opcode, 0 },
+{"fcvt.s.w",   0, INSN_CLASS_F_OR_ZFINX, "D,s",       MATCH_FCVT_S_W|MASK_RM, MASK_FCVT_S_W|MASK_RM, match_opcode, 0 },
+{"fcvt.s.w",   0, INSN_CLASS_F_OR_ZFINX, "D,s,m",     MATCH_FCVT_S_W, MASK_FCVT_S_W, match_opcode, 0 },
+{"fcvt.s.wu",  0, INSN_CLASS_F_OR_ZFINX, "D,s",       MATCH_FCVT_S_WU|MASK_RM, MASK_FCVT_S_WU|MASK_RM, match_opcode, 0 },
+{"fcvt.s.wu",  0, INSN_CLASS_F_OR_ZFINX, "D,s,m",     MATCH_FCVT_S_WU, MASK_FCVT_S_WU, match_opcode, 0 },
+{"fclass.s",   0, INSN_CLASS_F_OR_ZFINX, "d,S",       MATCH_FCLASS_S, MASK_FCLASS_S, match_opcode, 0 },
+{"feq.s",      0, INSN_CLASS_F_OR_ZFINX, "d,S,T",     MATCH_FEQ_S, MASK_FEQ_S, match_opcode, 0 },
+{"flt.s",      0, INSN_CLASS_F_OR_ZFINX, "d,S,T",     MATCH_FLT_S, MASK_FLT_S, match_opcode, 0 },
+{"fle.s",      0, INSN_CLASS_F_OR_ZFINX, "d,S,T",     MATCH_FLE_S, MASK_FLE_S, match_opcode, 0 },
+{"fgt.s",      0, INSN_CLASS_F_OR_ZFINX, "d,T,S",     MATCH_FLT_S, MASK_FLT_S, match_opcode, 0 },
+{"fge.s",      0, INSN_CLASS_F_OR_ZFINX, "d,T,S",     MATCH_FLE_S, MASK_FLE_S, match_opcode, 0 },
+{"fcvt.l.s",  64, INSN_CLASS_F_OR_ZFINX, "d,S",       MATCH_FCVT_L_S|MASK_RM, MASK_FCVT_L_S|MASK_RM, match_opcode, 0 },
+{"fcvt.l.s",  64, INSN_CLASS_F_OR_ZFINX, "d,S,m",     MATCH_FCVT_L_S, MASK_FCVT_L_S, match_opcode, 0 },
+{"fcvt.lu.s", 64, INSN_CLASS_F_OR_ZFINX, "d,S",       MATCH_FCVT_LU_S|MASK_RM, MASK_FCVT_LU_S|MASK_RM, match_opcode, 0 },
+{"fcvt.lu.s", 64, INSN_CLASS_F_OR_ZFINX, "d,S,m",     MATCH_FCVT_LU_S, MASK_FCVT_LU_S, match_opcode, 0 },
+{"fcvt.s.l",  64, INSN_CLASS_F_OR_ZFINX, "D,s",       MATCH_FCVT_S_L|MASK_RM, MASK_FCVT_S_L|MASK_RM, match_opcode, 0 },
+{"fcvt.s.l",  64, INSN_CLASS_F_OR_ZFINX, "D,s,m",     MATCH_FCVT_S_L, MASK_FCVT_S_L, match_opcode, 0 },
+{"fcvt.s.lu", 64, INSN_CLASS_F_OR_ZFINX, "D,s",       MATCH_FCVT_S_LU|MASK_RM, MASK_FCVT_S_LU|MASK_RM, match_opcode, 0 },
+{"fcvt.s.lu", 64, INSN_CLASS_F_OR_ZFINX, "D,s,m",     MATCH_FCVT_S_LU, MASK_FCVT_S_LU, match_opcode, 0 },
+
+/* Double-precision floating-point instruction subset.
+   D/Zdinx instructions that share the name must have INSN_HAS_EXT_VARS flag.  */
+{"fld",        0, INSN_CLASS_D_AND_C, "D,Cn(Cc)",          MATCH_C_FLDSP, MASK_C_FLDSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE },
+{"fld",        0, INSN_CLASS_D_AND_C, "CD,Cl(Cs)",         MATCH_C_FLD, MASK_C_FLD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE },
+{"fld",        0, INSN_CLASS_D,       "D,o(s)",            MATCH_FLD, MASK_FLD, match_opcode, INSN_DREF|INSN_8_BYTE },
+{"fld",        0, INSN_CLASS_D,       "D,A,s",             0, (int) M_FLD, match_never, INSN_MACRO },
+{"fsd",        0, INSN_CLASS_D_AND_C, "CT,CN(Cc)",         MATCH_C_FSDSP, MASK_C_FSDSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE },
+{"fsd",        0, INSN_CLASS_D_AND_C, "CD,Cl(Cs)",         MATCH_C_FSD, MASK_C_FSD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE },
+{"fsd",        0, INSN_CLASS_D,       "T,q(s)",            MATCH_FSD, MASK_FSD, match_opcode, INSN_DREF|INSN_8_BYTE },
+{"fsd",        0, INSN_CLASS_D,       "T,A,s",             0, (int) M_FSD, match_never, INSN_MACRO },
+{"fmv.d",      0, INSN_CLASS_D,       "D,U",               MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS|INSN_HAS_EXT_VARS },
+{"fmv.d",      0, INSN_CLASS_ZDINX,   "l2d,l2u",           MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS|INSN_HAS_EXT_VARS },
+{"fneg.d",     0, INSN_CLASS_D,       "D,U",               MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS|INSN_HAS_EXT_VARS },
+{"fneg.d",     0, INSN_CLASS_ZDINX,   "l2d,l2u",           MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS|INSN_HAS_EXT_VARS },
+{"fabs.d",     0, INSN_CLASS_D,       "D,U",               MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS|INSN_HAS_EXT_VARS },
+{"fabs.d",     0, INSN_CLASS_ZDINX,   "l2d,l2u",           MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS|INSN_HAS_EXT_VARS },
+{"fsgnj.d",    0, INSN_CLASS_D,       "D,S,T",             MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, INSN_HAS_EXT_VARS },
+{"fsgnj.d",    0, INSN_CLASS_ZDINX,   "l2d,l2s,l2t",       MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, INSN_HAS_EXT_VARS },
+{"fsgnjn.d",   0, INSN_CLASS_D,       "D,S,T",             MATCH_FSGNJN_D, MASK_FSGNJN_D, match_opcode, INSN_HAS_EXT_VARS },
+{"fsgnjn.d",   0, INSN_CLASS_ZDINX,   "l2d,l2s,l2t",       MATCH_FSGNJN_D, MASK_FSGNJN_D, match_opcode, INSN_HAS_EXT_VARS },
+{"fsgnjx.d",   0, INSN_CLASS_D,       "D,S,T",             MATCH_FSGNJX_D, MASK_FSGNJX_D, match_opcode, INSN_HAS_EXT_VARS },
+{"fsgnjx.d",   0, INSN_CLASS_ZDINX,   "l2d,l2s,l2t",       MATCH_FSGNJX_D, MASK_FSGNJX_D, match_opcode, INSN_HAS_EXT_VARS },
+{"fadd.d",     0, INSN_CLASS_D,       "D,S,T",             MATCH_FADD_D|MASK_RM, MASK_FADD_D|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fadd.d",     0, INSN_CLASS_ZDINX,   "l2d,l2s,l2t",       MATCH_FADD_D|MASK_RM, MASK_FADD_D|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fadd.d",     0, INSN_CLASS_D,       "D,S,T,m",           MATCH_FADD_D, MASK_FADD_D, match_opcode, INSN_HAS_EXT_VARS },
+{"fadd.d",     0, INSN_CLASS_ZDINX,   "l2d,l2s,l2t,m",     MATCH_FADD_D, MASK_FADD_D, match_opcode, INSN_HAS_EXT_VARS },
+{"fsub.d",     0, INSN_CLASS_D,       "D,S,T",             MATCH_FSUB_D|MASK_RM, MASK_FSUB_D|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fsub.d",     0, INSN_CLASS_ZDINX,   "l2d,l2s,l2t",       MATCH_FSUB_D|MASK_RM, MASK_FSUB_D|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fsub.d",     0, INSN_CLASS_D,       "D,S,T,m",           MATCH_FSUB_D, MASK_FSUB_D, match_opcode, INSN_HAS_EXT_VARS },
+{"fsub.d",     0, INSN_CLASS_ZDINX,   "l2d,l2s,l2t,m",     MATCH_FSUB_D, MASK_FSUB_D, match_opcode, INSN_HAS_EXT_VARS },
+{"fmul.d",     0, INSN_CLASS_D,       "D,S,T",             MATCH_FMUL_D|MASK_RM, MASK_FMUL_D|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fmul.d",     0, INSN_CLASS_ZDINX,   "l2d,l2s,l2t",       MATCH_FMUL_D|MASK_RM, MASK_FMUL_D|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fmul.d",     0, INSN_CLASS_D,       "D,S,T,m",           MATCH_FMUL_D, MASK_FMUL_D, match_opcode, INSN_HAS_EXT_VARS },
+{"fmul.d",     0, INSN_CLASS_ZDINX,   "l2d,l2s,l2t,m",     MATCH_FMUL_D, MASK_FMUL_D, match_opcode, INSN_HAS_EXT_VARS },
+{"fdiv.d",     0, INSN_CLASS_D,       "D,S,T",             MATCH_FDIV_D|MASK_RM, MASK_FDIV_D|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fdiv.d",     0, INSN_CLASS_ZDINX,   "l2d,l2s,l2t",       MATCH_FDIV_D|MASK_RM, MASK_FDIV_D|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fdiv.d",     0, INSN_CLASS_D,       "D,S,T,m",           MATCH_FDIV_D, MASK_FDIV_D, match_opcode, INSN_HAS_EXT_VARS },
+{"fdiv.d",     0, INSN_CLASS_ZDINX,   "l2d,l2s,l2t,m",     MATCH_FDIV_D, MASK_FDIV_D, match_opcode, INSN_HAS_EXT_VARS },
+{"fsqrt.d",    0, INSN_CLASS_D,       "D,S",               MATCH_FSQRT_D|MASK_RM, MASK_FSQRT_D|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fsqrt.d",    0, INSN_CLASS_ZDINX,   "l2d,l2s",           MATCH_FSQRT_D|MASK_RM, MASK_FSQRT_D|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fsqrt.d",    0, INSN_CLASS_D,       "D,S,m",             MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode, INSN_HAS_EXT_VARS },
+{"fsqrt.d",    0, INSN_CLASS_ZDINX,   "l2d,l2s,m",         MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode, INSN_HAS_EXT_VARS },
+{"fmin.d",     0, INSN_CLASS_D,       "D,S,T",             MATCH_FMIN_D, MASK_FMIN_D, match_opcode, INSN_HAS_EXT_VARS },
+{"fmin.d",     0, INSN_CLASS_ZDINX,   "l2d,l2s,l2t",       MATCH_FMIN_D, MASK_FMIN_D, match_opcode, INSN_HAS_EXT_VARS },
+{"fmax.d",     0, INSN_CLASS_D,       "D,S,T",             MATCH_FMAX_D, MASK_FMAX_D, match_opcode, INSN_HAS_EXT_VARS },
+{"fmax.d",     0, INSN_CLASS_ZDINX,   "l2d,l2s,l2t",       MATCH_FMAX_D, MASK_FMAX_D, match_opcode, INSN_HAS_EXT_VARS },
+{"fmadd.d",    0, INSN_CLASS_D,       "D,S,T,R",           MATCH_FMADD_D|MASK_RM, MASK_FMADD_D|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fmadd.d",    0, INSN_CLASS_ZDINX,   "l2d,l2s,l2t,l2r",   MATCH_FMADD_D|MASK_RM, MASK_FMADD_D|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fmadd.d",    0, INSN_CLASS_D,       "D,S,T,R,m",         MATCH_FMADD_D, MASK_FMADD_D, match_opcode, INSN_HAS_EXT_VARS },
+{"fmadd.d",    0, INSN_CLASS_ZDINX,   "l2d,l2s,l2t,l2r,m", MATCH_FMADD_D, MASK_FMADD_D, match_opcode, INSN_HAS_EXT_VARS },
+{"fnmadd.d",   0, INSN_CLASS_D,       "D,S,T,R",           MATCH_FNMADD_D|MASK_RM, MASK_FNMADD_D|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fnmadd.d",   0, INSN_CLASS_ZDINX,   "l2d,l2s,l2t,l2r",   MATCH_FNMADD_D|MASK_RM, MASK_FNMADD_D|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fnmadd.d",   0, INSN_CLASS_D,       "D,S,T,R,m",         MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode, INSN_HAS_EXT_VARS },
+{"fnmadd.d",   0, INSN_CLASS_ZDINX,   "l2d,l2s,l2t,l2r,m", MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode, INSN_HAS_EXT_VARS },
+{"fmsub.d",    0, INSN_CLASS_D,       "D,S,T,R",           MATCH_FMSUB_D|MASK_RM, MASK_FMSUB_D|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fmsub.d",    0, INSN_CLASS_ZDINX,   "l2d,l2s,l2t,l2r",   MATCH_FMSUB_D|MASK_RM, MASK_FMSUB_D|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fmsub.d",    0, INSN_CLASS_D,       "D,S,T,R,m",         MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode, INSN_HAS_EXT_VARS },
+{"fmsub.d",    0, INSN_CLASS_ZDINX,   "l2d,l2s,l2t,l2r,m", MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode, INSN_HAS_EXT_VARS },
+{"fnmsub.d",   0, INSN_CLASS_D,       "D,S,T,R",           MATCH_FNMSUB_D|MASK_RM, MASK_FNMSUB_D|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fnmsub.d",   0, INSN_CLASS_ZDINX,   "l2d,l2s,l2t,l2r",   MATCH_FNMSUB_D|MASK_RM, MASK_FNMSUB_D|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fnmsub.d",   0, INSN_CLASS_D,       "D,S,T,R,m",         MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode, INSN_HAS_EXT_VARS },
+{"fnmsub.d",   0, INSN_CLASS_ZDINX,   "l2d,l2s,l2t,l2r,m", MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.w.d",   0, INSN_CLASS_D,       "d,S",               MATCH_FCVT_W_D|MASK_RM, MASK_FCVT_W_D|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.w.d",   0, INSN_CLASS_ZDINX,   "d,l2s",             MATCH_FCVT_W_D|MASK_RM, MASK_FCVT_W_D|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.w.d",   0, INSN_CLASS_D,       "d,S,m",             MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.w.d",   0, INSN_CLASS_ZDINX,   "d,l2s,m",           MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.wu.d",  0, INSN_CLASS_D,       "d,S",               MATCH_FCVT_WU_D|MASK_RM, MASK_FCVT_WU_D|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.wu.d",  0, INSN_CLASS_ZDINX,   "d,l2s",             MATCH_FCVT_WU_D|MASK_RM, MASK_FCVT_WU_D|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.wu.d",  0, INSN_CLASS_D,       "d,S,m",             MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.wu.d",  0, INSN_CLASS_ZDINX,   "d,l2s,m",           MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.d.w",   0, INSN_CLASS_D,       "D,s",               MATCH_FCVT_D_W, MASK_FCVT_D_W|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.d.w",   0, INSN_CLASS_ZDINX,   "l2d,s",             MATCH_FCVT_D_W, MASK_FCVT_D_W|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.d.wu",  0, INSN_CLASS_D,       "D,s",               MATCH_FCVT_D_WU, MASK_FCVT_D_WU|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.d.wu",  0, INSN_CLASS_ZDINX,   "l2d,s",             MATCH_FCVT_D_WU, MASK_FCVT_D_WU|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.d.s",   0, INSN_CLASS_D,       "D,S",               MATCH_FCVT_D_S, MASK_FCVT_D_S|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.d.s",   0, INSN_CLASS_ZDINX,   "l2d,l1s",           MATCH_FCVT_D_S, MASK_FCVT_D_S|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.s.d",   0, INSN_CLASS_D,       "D,S",               MATCH_FCVT_S_D|MASK_RM, MASK_FCVT_S_D|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.s.d",   0, INSN_CLASS_ZDINX,   "l1d,l2s",           MATCH_FCVT_S_D|MASK_RM, MASK_FCVT_S_D|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.s.d",   0, INSN_CLASS_D,       "D,S,m",             MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.s.d",   0, INSN_CLASS_ZDINX,   "l1d,l2s,m",         MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode, INSN_HAS_EXT_VARS },
+{"fclass.d",   0, INSN_CLASS_D,       "d,S",               MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode, INSN_HAS_EXT_VARS },
+{"fclass.d",   0, INSN_CLASS_ZDINX,   "d,l2s",             MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode, INSN_HAS_EXT_VARS },
+{"feq.d",      0, INSN_CLASS_D,       "d,S,T",             MATCH_FEQ_D, MASK_FEQ_D, match_opcode, INSN_HAS_EXT_VARS },
+{"feq.d",      0, INSN_CLASS_ZDINX,   "d,l2s,l2t",         MATCH_FEQ_D, MASK_FEQ_D, match_opcode, INSN_HAS_EXT_VARS },
+{"flt.d",      0, INSN_CLASS_D,       "d,S,T",             MATCH_FLT_D, MASK_FLT_D, match_opcode, INSN_HAS_EXT_VARS },
+{"flt.d",      0, INSN_CLASS_ZDINX,   "d,l2s,l2t",         MATCH_FLT_D, MASK_FLT_D, match_opcode, INSN_HAS_EXT_VARS },
+{"fle.d",      0, INSN_CLASS_D,       "d,S,T",             MATCH_FLE_D, MASK_FLE_D, match_opcode, INSN_HAS_EXT_VARS },
+{"fle.d",      0, INSN_CLASS_ZDINX,   "d,l2s,l2t",         MATCH_FLE_D, MASK_FLE_D, match_opcode, INSN_HAS_EXT_VARS },
+{"fgt.d",      0, INSN_CLASS_D,       "d,T,S",             MATCH_FLT_D, MASK_FLT_D, match_opcode, INSN_HAS_EXT_VARS },
+{"fgt.d",      0, INSN_CLASS_ZDINX,   "d,l2t,l2s",         MATCH_FLT_D, MASK_FLT_D, match_opcode, INSN_HAS_EXT_VARS },
+{"fge.d",      0, INSN_CLASS_D,       "d,T,S",             MATCH_FLE_D, MASK_FLE_D, match_opcode, INSN_HAS_EXT_VARS },
+{"fge.d",      0, INSN_CLASS_ZDINX,   "d,l2t,l2s",         MATCH_FLE_D, MASK_FLE_D, match_opcode, INSN_HAS_EXT_VARS },
+{"fmv.x.d",   64, INSN_CLASS_D,       "d,S",               MATCH_FMV_X_D, MASK_FMV_X_D, match_opcode, 0 },
+{"fmv.d.x",   64, INSN_CLASS_D,       "D,s",               MATCH_FMV_D_X, MASK_FMV_D_X, match_opcode, 0 },
+{"fcvt.l.d",  64, INSN_CLASS_D,       "d,S",               MATCH_FCVT_L_D|MASK_RM, MASK_FCVT_L_D|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.l.d",  64, INSN_CLASS_ZDINX,   "d,l2s",             MATCH_FCVT_L_D|MASK_RM, MASK_FCVT_L_D|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.l.d",  64, INSN_CLASS_D,       "d,S,m",             MATCH_FCVT_L_D, MASK_FCVT_L_D, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.l.d",  64, INSN_CLASS_ZDINX,   "d,l2s,m",           MATCH_FCVT_L_D, MASK_FCVT_L_D, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.lu.d", 64, INSN_CLASS_D,       "d,S",               MATCH_FCVT_LU_D|MASK_RM, MASK_FCVT_LU_D|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.lu.d", 64, INSN_CLASS_ZDINX,   "d,l2s",             MATCH_FCVT_LU_D|MASK_RM, MASK_FCVT_LU_D|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.lu.d", 64, INSN_CLASS_D,       "d,S,m",             MATCH_FCVT_LU_D, MASK_FCVT_LU_D, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.lu.d", 64, INSN_CLASS_ZDINX,   "d,l2s,m",           MATCH_FCVT_LU_D, MASK_FCVT_LU_D, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.d.l",  64, INSN_CLASS_D,       "D,s",               MATCH_FCVT_D_L|MASK_RM, MASK_FCVT_D_L|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.d.l",  64, INSN_CLASS_ZDINX,   "l2d,s",             MATCH_FCVT_D_L|MASK_RM, MASK_FCVT_D_L|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.d.l",  64, INSN_CLASS_D,       "D,s,m",             MATCH_FCVT_D_L, MASK_FCVT_D_L, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.d.l",  64, INSN_CLASS_ZDINX,   "l2d,s,m",           MATCH_FCVT_D_L, MASK_FCVT_D_L, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.d.lu", 64, INSN_CLASS_D,       "D,s",               MATCH_FCVT_D_LU|MASK_RM, MASK_FCVT_D_LU|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.d.lu", 64, INSN_CLASS_ZDINX,   "l2d,s",             MATCH_FCVT_D_LU|MASK_RM, MASK_FCVT_D_LU|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.d.lu", 64, INSN_CLASS_D,       "D,s,m",             MATCH_FCVT_D_LU, MASK_FCVT_D_LU, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.d.lu", 64, INSN_CLASS_ZDINX,   "l2d,s,m",           MATCH_FCVT_D_LU, MASK_FCVT_D_LU, match_opcode, INSN_HAS_EXT_VARS },
+
+/* Quad-precision floating-point instruction subset.
+   Q/Zqinx instructions that share the name must have INSN_HAS_EXT_VARS flag.  */
+{"flq",        0, INSN_CLASS_Q,     "D,o(s)",            MATCH_FLQ, MASK_FLQ, match_opcode, INSN_DREF|INSN_16_BYTE },
+{"flq",        0, INSN_CLASS_Q,     "D,A,s",             0, (int) M_FLQ, match_never, INSN_MACRO },
+{"fsq",        0, INSN_CLASS_Q,     "T,q(s)",            MATCH_FSQ, MASK_FSQ, match_opcode, INSN_DREF|INSN_16_BYTE },
+{"fsq",        0, INSN_CLASS_Q,     "T,A,s",             0, (int) M_FSQ, match_never, INSN_MACRO },
+{"fmv.q",      0, INSN_CLASS_Q,     "D,U",               MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS|INSN_HAS_EXT_VARS },
+{"fmv.q",      0, INSN_CLASS_ZQINX, "l4d,l4u",           MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS|INSN_HAS_EXT_VARS },
+{"fneg.q",     0, INSN_CLASS_Q,     "D,U",               MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2, INSN_ALIAS|INSN_HAS_EXT_VARS },
+{"fneg.q",     0, INSN_CLASS_ZQINX, "l4d,l4u",           MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2, INSN_ALIAS|INSN_HAS_EXT_VARS },
+{"fabs.q",     0, INSN_CLASS_Q,     "D,U",               MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2, INSN_ALIAS|INSN_HAS_EXT_VARS },
+{"fabs.q",     0, INSN_CLASS_ZQINX, "l4d,l4u",           MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2, INSN_ALIAS|INSN_HAS_EXT_VARS },
+{"fsgnj.q",    0, INSN_CLASS_Q,     "D,S,T",             MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode, INSN_HAS_EXT_VARS },
+{"fsgnj.q",    0, INSN_CLASS_ZQINX, "l4d,l4s,l4t",       MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode, INSN_HAS_EXT_VARS },
+{"fsgnjn.q",   0, INSN_CLASS_Q,     "D,S,T",             MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_opcode, INSN_HAS_EXT_VARS },
+{"fsgnjn.q",   0, INSN_CLASS_ZQINX, "l4d,l4s,l4t",       MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_opcode, INSN_HAS_EXT_VARS },
+{"fsgnjx.q",   0, INSN_CLASS_Q,     "D,S,T",             MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_opcode, INSN_HAS_EXT_VARS },
+{"fsgnjx.q",   0, INSN_CLASS_ZQINX, "l4d,l4s,l4t",       MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_opcode, INSN_HAS_EXT_VARS },
+{"fadd.q",     0, INSN_CLASS_Q,     "D,S,T",             MATCH_FADD_Q|MASK_RM, MASK_FADD_Q|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fadd.q",     0, INSN_CLASS_ZQINX, "l4d,l4s,l4t",       MATCH_FADD_Q|MASK_RM, MASK_FADD_Q|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fadd.q",     0, INSN_CLASS_Q,     "D,S,T,m",           MATCH_FADD_Q, MASK_FADD_Q, match_opcode, INSN_HAS_EXT_VARS },
+{"fadd.q",     0, INSN_CLASS_ZQINX, "l4d,l4s,l4t,m",     MATCH_FADD_Q, MASK_FADD_Q, match_opcode, INSN_HAS_EXT_VARS },
+{"fsub.q",     0, INSN_CLASS_Q,     "D,S,T",             MATCH_FSUB_Q|MASK_RM, MASK_FSUB_Q|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fsub.q",     0, INSN_CLASS_ZQINX, "l4d,l4s,l4t",       MATCH_FSUB_Q|MASK_RM, MASK_FSUB_Q|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fsub.q",     0, INSN_CLASS_Q,     "D,S,T,m",           MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode, INSN_HAS_EXT_VARS },
+{"fsub.q",     0, INSN_CLASS_ZQINX, "l4d,l4s,l4t,m",     MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode, INSN_HAS_EXT_VARS },
+{"fmul.q",     0, INSN_CLASS_Q,     "D,S,T",             MATCH_FMUL_Q|MASK_RM, MASK_FMUL_Q|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fmul.q",     0, INSN_CLASS_ZQINX, "l4d,l4s,l4t",       MATCH_FMUL_Q|MASK_RM, MASK_FMUL_Q|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fmul.q",     0, INSN_CLASS_Q,     "D,S,T,m",           MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode, INSN_HAS_EXT_VARS },
+{"fmul.q",     0, INSN_CLASS_ZQINX, "l4d,l4s,l4t,m",     MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode, INSN_HAS_EXT_VARS },
+{"fdiv.q",     0, INSN_CLASS_Q,     "D,S,T",             MATCH_FDIV_Q|MASK_RM, MASK_FDIV_Q|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fdiv.q",     0, INSN_CLASS_ZQINX, "l4d,l4s,l4t",       MATCH_FDIV_Q|MASK_RM, MASK_FDIV_Q|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fdiv.q",     0, INSN_CLASS_Q,     "D,S,T,m",           MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode, INSN_HAS_EXT_VARS },
+{"fdiv.q",     0, INSN_CLASS_ZQINX, "l4d,l4s,l4t,m",     MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode, INSN_HAS_EXT_VARS },
+{"fsqrt.q",    0, INSN_CLASS_Q,     "D,S",               MATCH_FSQRT_Q|MASK_RM, MASK_FSQRT_Q|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fsqrt.q",    0, INSN_CLASS_ZQINX, "l4d,l4s",           MATCH_FSQRT_Q|MASK_RM, MASK_FSQRT_Q|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fsqrt.q",    0, INSN_CLASS_Q,     "D,S,m",             MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode, INSN_HAS_EXT_VARS },
+{"fsqrt.q",    0, INSN_CLASS_ZQINX, "l4d,l4s,m",         MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode, INSN_HAS_EXT_VARS },
+{"fmin.q",     0, INSN_CLASS_Q,     "D,S,T",             MATCH_FMIN_Q, MASK_FMIN_Q, match_opcode, INSN_HAS_EXT_VARS },
+{"fmin.q",     0, INSN_CLASS_ZQINX, "l4d,l4s,l4t",       MATCH_FMIN_Q, MASK_FMIN_Q, match_opcode, INSN_HAS_EXT_VARS },
+{"fmax.q",     0, INSN_CLASS_Q,     "D,S,T",             MATCH_FMAX_Q, MASK_FMAX_Q, match_opcode, INSN_HAS_EXT_VARS },
+{"fmax.q",     0, INSN_CLASS_ZQINX, "l4d,l4s,l4t",       MATCH_FMAX_Q, MASK_FMAX_Q, match_opcode, INSN_HAS_EXT_VARS },
+{"fmadd.q",    0, INSN_CLASS_Q,     "D,S,T,R",           MATCH_FMADD_Q|MASK_RM, MASK_FMADD_Q|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fmadd.q",    0, INSN_CLASS_ZQINX, "l4d,l4s,l4t,l4r",   MATCH_FMADD_Q|MASK_RM, MASK_FMADD_Q|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fmadd.q",    0, INSN_CLASS_Q,     "D,S,T,R,m",         MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode, INSN_HAS_EXT_VARS },
+{"fmadd.q",    0, INSN_CLASS_ZQINX, "l4d,l4s,l4t,l4r,m", MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode, INSN_HAS_EXT_VARS },
+{"fnmadd.q",   0, INSN_CLASS_Q,     "D,S,T,R",           MATCH_FNMADD_Q|MASK_RM, MASK_FNMADD_Q|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fnmadd.q",   0, INSN_CLASS_ZQINX, "l4d,l4s,l4t,l4r",   MATCH_FNMADD_Q|MASK_RM, MASK_FNMADD_Q|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fnmadd.q",   0, INSN_CLASS_Q,     "D,S,T,R,m",         MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode, INSN_HAS_EXT_VARS },
+{"fnmadd.q",   0, INSN_CLASS_ZQINX, "l4d,l4s,l4t,l4r,m", MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode, INSN_HAS_EXT_VARS },
+{"fmsub.q",    0, INSN_CLASS_Q,     "D,S,T,R",           MATCH_FMSUB_Q|MASK_RM, MASK_FMSUB_Q|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fmsub.q",    0, INSN_CLASS_ZQINX, "l4d,l4s,l4t,l4r",   MATCH_FMSUB_Q|MASK_RM, MASK_FMSUB_Q|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fmsub.q",    0, INSN_CLASS_Q,     "D,S,T,R,m",         MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode, INSN_HAS_EXT_VARS },
+{"fmsub.q",    0, INSN_CLASS_ZQINX, "l4d,l4s,l4t,l4r,m", MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode, INSN_HAS_EXT_VARS },
+{"fnmsub.q",   0, INSN_CLASS_Q,     "D,S,T,R",           MATCH_FNMSUB_Q|MASK_RM, MASK_FNMSUB_Q|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fnmsub.q",   0, INSN_CLASS_ZQINX, "l4d,l4s,l4t,l4r",   MATCH_FNMSUB_Q|MASK_RM, MASK_FNMSUB_Q|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fnmsub.q",   0, INSN_CLASS_Q,     "D,S,T,R,m",         MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode, INSN_HAS_EXT_VARS },
+{"fnmsub.q",   0, INSN_CLASS_ZQINX, "l4d,l4s,l4t,l4r,m", MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.w.q",   0, INSN_CLASS_Q,     "d,S",               MATCH_FCVT_W_Q|MASK_RM, MASK_FCVT_W_Q|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.w.q",   0, INSN_CLASS_ZQINX, "d,l4s",             MATCH_FCVT_W_Q|MASK_RM, MASK_FCVT_W_Q|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.w.q",   0, INSN_CLASS_Q,     "d,S,m",             MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.w.q",   0, INSN_CLASS_ZQINX, "d,l4s,m",           MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.wu.q",  0, INSN_CLASS_Q,     "d,S",               MATCH_FCVT_WU_Q|MASK_RM, MASK_FCVT_WU_Q|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.wu.q",  0, INSN_CLASS_ZQINX, "d,l4s",             MATCH_FCVT_WU_Q|MASK_RM, MASK_FCVT_WU_Q|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.wu.q",  0, INSN_CLASS_Q,     "d,S,m",             MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.wu.q",  0, INSN_CLASS_ZQINX, "d,l4s,m",           MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.q.w",   0, INSN_CLASS_Q,     "D,s",               MATCH_FCVT_Q_W, MASK_FCVT_Q_W|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.q.w",   0, INSN_CLASS_ZQINX, "l4d,s",             MATCH_FCVT_Q_W, MASK_FCVT_Q_W|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.q.wu",  0, INSN_CLASS_Q,     "D,s",               MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.q.wu",  0, INSN_CLASS_ZQINX, "l4d,s",             MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.q.s",   0, INSN_CLASS_Q,     "D,S",               MATCH_FCVT_Q_S, MASK_FCVT_Q_S|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.q.s",   0, INSN_CLASS_ZQINX, "l4d,l1s",           MATCH_FCVT_Q_S, MASK_FCVT_Q_S|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.q.d",   0, INSN_CLASS_Q,     "D,S",               MATCH_FCVT_Q_D, MASK_FCVT_Q_D|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.q.d",   0, INSN_CLASS_ZQINX, "l4d,l2s",           MATCH_FCVT_Q_D, MASK_FCVT_Q_D|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.s.q",   0, INSN_CLASS_Q,     "D,S",               MATCH_FCVT_S_Q|MASK_RM, MASK_FCVT_S_Q|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.s.q",   0, INSN_CLASS_ZQINX, "l1d,l4s",           MATCH_FCVT_S_Q|MASK_RM, MASK_FCVT_S_Q|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.s.q",   0, INSN_CLASS_Q,     "D,S,m",             MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.s.q",   0, INSN_CLASS_ZQINX, "l1d,l4s,m",         MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.d.q",   0, INSN_CLASS_Q,     "D,S",               MATCH_FCVT_D_Q|MASK_RM, MASK_FCVT_D_Q|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.d.q",   0, INSN_CLASS_ZQINX, "l2d,l4s",           MATCH_FCVT_D_Q|MASK_RM, MASK_FCVT_D_Q|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.d.q",   0, INSN_CLASS_Q,     "D,S,m",             MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.d.q",   0, INSN_CLASS_ZQINX, "l2d,l4s,m",         MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode, INSN_HAS_EXT_VARS },
+{"fclass.q",   0, INSN_CLASS_Q,     "d,S",               MATCH_FCLASS_Q, MASK_FCLASS_Q, match_opcode, INSN_HAS_EXT_VARS },
+{"fclass.q",   0, INSN_CLASS_ZQINX, "d,l4s",             MATCH_FCLASS_Q, MASK_FCLASS_Q, match_opcode, INSN_HAS_EXT_VARS },
+{"feq.q",      0, INSN_CLASS_Q,     "d,S,T",             MATCH_FEQ_Q, MASK_FEQ_Q, match_opcode, INSN_HAS_EXT_VARS },
+{"feq.q",      0, INSN_CLASS_ZQINX, "d,l4s,l4t",         MATCH_FEQ_Q, MASK_FEQ_Q, match_opcode, INSN_HAS_EXT_VARS },
+{"flt.q",      0, INSN_CLASS_Q,     "d,S,T",             MATCH_FLT_Q, MASK_FLT_Q, match_opcode, INSN_HAS_EXT_VARS },
+{"flt.q",      0, INSN_CLASS_ZQINX, "d,l4s,l4t",         MATCH_FLT_Q, MASK_FLT_Q, match_opcode, INSN_HAS_EXT_VARS },
+{"fle.q",      0, INSN_CLASS_Q,     "d,S,T",             MATCH_FLE_Q, MASK_FLE_Q, match_opcode, INSN_HAS_EXT_VARS },
+{"fle.q",      0, INSN_CLASS_ZQINX, "d,l4s,l4t",         MATCH_FLE_Q, MASK_FLE_Q, match_opcode, INSN_HAS_EXT_VARS },
+{"fgt.q",      0, INSN_CLASS_Q,     "d,T,S",             MATCH_FLT_Q, MASK_FLT_Q, match_opcode, INSN_HAS_EXT_VARS },
+{"fgt.q",      0, INSN_CLASS_ZQINX, "d,l4t,l4s",         MATCH_FLT_Q, MASK_FLT_Q, match_opcode, INSN_HAS_EXT_VARS },
+{"fge.q",      0, INSN_CLASS_Q,     "d,T,S",             MATCH_FLE_Q, MASK_FLE_Q, match_opcode, INSN_HAS_EXT_VARS },
+{"fge.q",      0, INSN_CLASS_ZQINX, "d,l4t,l4s",         MATCH_FLE_Q, MASK_FLE_Q, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.l.q",  64, INSN_CLASS_Q,     "d,S",               MATCH_FCVT_L_Q|MASK_RM, MASK_FCVT_L_Q|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.l.q",  64, INSN_CLASS_ZQINX, "d,l4s",             MATCH_FCVT_L_Q|MASK_RM, MASK_FCVT_L_Q|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.l.q",  64, INSN_CLASS_Q,     "d,S,m",             MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.l.q",  64, INSN_CLASS_ZQINX, "d,l4s,m",           MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.lu.q", 64, INSN_CLASS_Q,     "d,S",               MATCH_FCVT_LU_Q|MASK_RM, MASK_FCVT_LU_Q|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.lu.q", 64, INSN_CLASS_ZQINX, "d,l4s",             MATCH_FCVT_LU_Q|MASK_RM, MASK_FCVT_LU_Q|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.lu.q", 64, INSN_CLASS_Q,     "d,S,m",             MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.lu.q", 64, INSN_CLASS_ZQINX, "d,l4s,m",           MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.q.l",  64, INSN_CLASS_Q,     "D,s",               MATCH_FCVT_Q_L, MASK_FCVT_Q_L|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.q.l",  64, INSN_CLASS_ZQINX, "l4d,s",             MATCH_FCVT_Q_L, MASK_FCVT_Q_L|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.q.l",  64, INSN_CLASS_Q,     "D,s,m",             MATCH_FCVT_Q_L, MASK_FCVT_Q_L, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.q.l",  64, INSN_CLASS_ZQINX, "l4d,s,m",           MATCH_FCVT_Q_L, MASK_FCVT_Q_L, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.q.lu", 64, INSN_CLASS_Q,     "D,s",               MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.q.lu", 64, INSN_CLASS_ZQINX, "l4d,s",             MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU|MASK_RM, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.q.lu", 64, INSN_CLASS_Q,     "D,s,m",             MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU, match_opcode, INSN_HAS_EXT_VARS },
+{"fcvt.q.lu", 64, INSN_CLASS_ZQINX, "l4d,s,m",           MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU, match_opcode, INSN_HAS_EXT_VARS },
 
 /* Compressed instructions.  */
 {"c.unimp",    0, INSN_CLASS_C,   "",          0, 0xffffU,  match_opcode, 0 },