UNRATIFIED RISC-V: Add 'Zfa' extension

[DO NOT MERGE]
Until 'Zfa' extension is frozen/ratified and final version number is
determined, this patch should not be merged upstream.  This commit uses
unratified version 0.1 as in the documentation (instead of possible 1.0
after ratification).

This commit adds the 'Zfa' extension (its instructions and new operand
type for FLI instructions).

This is based on:
<riscv/riscv-isa-manual@d74d99e>,
latest 'Zfa' change on the master branch of the RISC-V ISA Manual
as of this writing.

Note: the author is calling FLI instructions' RS1 encoded field as
"value".  It must be reviewed before the specification is frozen.

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_multi_subset_supports): Add instruction
	class support for 'Zfa' extension.
	(riscv_multi_subset_supports_ext): Likewise.
	(riscv_implicit_subsets): Add 'Zfa' -> 'F' dependency.

gas/ChangeLog:

	* testsuite/gas/riscv/zfa.s: New test.
	* testsuite/gas/riscv/zfa.d: Likewise.
	* testsuite/gas/riscv/zfa-32.s: New test.
	* testsuite/gas/riscv/zfa-32.d: Likewise.
	* testsuite/gas/riscv/zfa-64.s: New test.
	* testsuite/gas/riscv/zfa-64.d: Likewise.
	* testsuite/gas/riscv/zfa-fail.s: New failure test for 'Zfa'
	instructions.
	* testsuite/gas/riscv/zfa-fail.d: Likewise.
	* testsuite/gas/riscv/zfa-fail.l: Likewise.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_FLI_H, MASK_FLI_H, MATCH_FMINM_H,
	MASK_FMINM_H, MATCH_FMAXM_H, MASK_FMAXM_H, MATCH_FROUND_H,
	MASK_FROUND_H, MATCH_FROUNDNX_H, MASK_FROUNDNX_H, MATCH_FLTQ_H,
	MASK_FLTQ_H, MATCH_FLEQ_H, MASK_FLEQ_H, MATCH_FLI_S, MASK_FLI_S,
	MATCH_FMINM_S, MASK_FMINM_S, MATCH_FMAXM_S, MASK_FMAXM_S,
	MATCH_FROUND_S, MASK_FROUND_S, MATCH_FROUNDNX_S, MASK_FROUNDNX_S,
	MATCH_FLTQ_S, MASK_FLTQ_S, MATCH_FLEQ_S, MASK_FLEQ_S, MATCH_FLI_D,
	MASK_FLI_D, MATCH_FMINM_D, MASK_FMINM_D, MATCH_FMAXM_D,
	MASK_FMAXM_D, MATCH_FROUND_D, MASK_FROUND_D, MATCH_FROUNDNX_D,
	MASK_FROUNDNX_D, MATCH_FLTQ_D, MASK_FLTQ_D, MATCH_FLEQ_D,
	MASK_FLEQ_D, MATCH_FLI_Q, MASK_FLI_Q, MATCH_FMINM_Q, MASK_FMINM_Q,
	MATCH_FMAXM_Q, MASK_FMAXM_Q, MATCH_FROUND_Q, MASK_FROUND_Q,
	MATCH_FROUNDNX_Q, MASK_FROUNDNX_Q, MATCH_FLTQ_Q, MASK_FLTQ_Q,
	MATCH_FLEQ_Q, MASK_FLEQ_Q, MATCH_FCVTMOD_W_D, MASK_FCVTMOD_W_D,
	MATCH_FMVH_X_D, MASK_FMVH_X_D, MATCH_FMVH_X_Q, MASK_FMVH_X_Q,
	MATCH_FMVP_D_X, MASK_FMVP_D_X, MATCH_FMVP_Q_X,
	MASK_FMVP_Q_X): New.
	* opcode/riscv.h (enum riscv_insn_class): Add instruction
	classes for 'Zfa' extension.

opcodes/ChangeLog:

	* riscv-opc.c (riscv_opcodes): Add 'Zfa' instructions.

bfd/elfxx-riscv.c

@@ -1078,6 +1078,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"zvl256b", "zvl128b",	check_implicit_always},
   {"zvl128b", "zvl64b",		check_implicit_always},
   {"zvl64b", "zvl32b",		check_implicit_always},
+  {"zfa", "f",		check_implicit_always},
   {"d", "f",		check_implicit_always},
   {"zfh", "zfhmin",	check_implicit_always},
   {"zfhmin", "f",	check_implicit_always},
@@ -1175,6 +1176,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zihintpause",	ISA_SPEC_CLASS_DRAFT,		2, 0,  0 },
   {"zmmul",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zawrs",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zfa",		ISA_SPEC_CLASS_DRAFT,		0, 1,  0 },
   {"zfh",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zfhmin",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zfinx",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
@@ -2313,6 +2315,17 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
 	       && riscv_subset_supports (rps, "q"))
 	      || (riscv_subset_supports (rps, "zhinxmin")
 		  && riscv_subset_supports (rps, "zqinx")));
+    case INSN_CLASS_ZFA:
+      return riscv_subset_supports (rps, "zfa");
+    case INSN_CLASS_D_AND_ZFA:
+      return riscv_subset_supports (rps, "d")
+	     && riscv_subset_supports (rps, "zfa");
+    case INSN_CLASS_Q_AND_ZFA:
+      return riscv_subset_supports (rps, "q")
+	     && riscv_subset_supports (rps, "zfa");
+    case INSN_CLASS_ZFH_AND_ZFA:
+      return riscv_subset_supports (rps, "zfh")
+	     && riscv_subset_supports (rps, "zfa");
     case INSN_CLASS_ZBA:
       return riscv_subset_supports (rps, "zba");
     case INSN_CLASS_ZBB:
@@ -2479,6 +2492,32 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
 	return "zhinxmin";
       else
 	return _("zfhmin' and `q', or `zhinxmin' and `zqinx");
+    case INSN_CLASS_ZFA:
+      return "zfa";
+    case INSN_CLASS_D_AND_ZFA:
+      if (!riscv_subset_supports (rps, "d")
+	  && !riscv_subset_supports (rps, "zfa"))
+	return _("d' and `zfa");
+      else if (!riscv_subset_supports (rps, "d"))
+	return "d";
+      else
+	return "zfa";
+    case INSN_CLASS_Q_AND_ZFA:
+      if (!riscv_subset_supports (rps, "q")
+	  && !riscv_subset_supports (rps, "zfa"))
+	return _("q' and `zfa");
+      else if (!riscv_subset_supports (rps, "q"))
+	return "q";
+      else
+	return "zfa";
+    case INSN_CLASS_ZFH_AND_ZFA:
+      if (!riscv_subset_supports (rps, "zfh")
+	  && !riscv_subset_supports (rps, "zfa"))
+	return _("zfh' and `zfa");
+      else if (!riscv_subset_supports (rps, "zfh"))
+	return "zfh";
+      else
+	return "zfa";
     case INSN_CLASS_ZBA:
       return "zba";
     case INSN_CLASS_ZBB:

gas/config/tc-riscv.c

@@ -1399,6 +1399,14 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
 		  goto unknown_validate_operand;
 		}
 	      break;
+	    case 'f':
+	      switch (*++oparg)
+		{
+		case 'v': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break;
+		default:
+		  goto unknown_validate_operand;
+		}
+	      break;
 	    default:
 	      goto unknown_validate_operand;
 	    }
@@ -3458,6 +3466,34 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
 		      goto unknown_riscv_ip_operand;
 		    }
 		  break;
+		case 'f':
+		  switch (*++oparg)
+		    {
+		    case 'v':
+		      /* FLI.[HSDQ] value field for 'Zfa' extension.
+			 Either 0...29 or "min", "inf" or "nan".  */
+		      if (arg_lookup (&asarg, riscv_fli_value,
+				      ARRAY_SIZE (riscv_fli_value), &regno))
+			{
+			  INSERT_OPERAND (RS1, *ip, regno);
+			  continue;
+			}
+		      if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p)
+			  || imm_expr->X_op != O_constant)
+			break;
+		      if (imm_expr->X_add_number < 0
+			  || imm_expr->X_add_number > 29)
+			as_bad (_ ("improper fli value field (%ld), "
+				   "value must be 0...29 or min, inf or nan"),
+				(long) imm_expr->X_add_number);
+		      INSERT_OPERAND (RS1, *ip, imm_expr->X_add_number);
+		      imm_expr->X_op = O_absent;
+		      asarg = expr_parse_end;
+		      continue;
+		    default:
+		      goto unknown_riscv_ip_operand;
+		    }
+		  break;
 		default:
 		  goto unknown_riscv_ip_operand;
 		}

gas/testsuite/gas/riscv/zfa-32.d

@@ -0,0 +1,10 @@
+#as: -march=rv32id_zfa
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+e2108553[ 	]+fmvh\.x\.d[ 	]+a0,ft1
+[ 	]+[0-9a-f]+:[ 	]+b2b500d3[ 	]+fmvp\.d\.x[ 	]+ft1,a0,a1

gas/testsuite/gas/riscv/zfa-32.s

@@ -0,0 +1,3 @@
+target:
+	fmvh.x.d	a0, ft1
+	fmvp.d.x	ft1, a0, a1

gas/testsuite/gas/riscv/zfa-64.d

@@ -0,0 +1,10 @@
+#as: -march=rv64iq_zfa
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+e6108553[ 	]+fmvh\.x\.q[ 	]+a0,ft1
+[ 	]+[0-9a-f]+:[ 	]+b6b500d3[ 	]+fmvp\.q\.x[ 	]+ft1,a0,a1

gas/testsuite/gas/riscv/zfa-64.s

@@ -0,0 +1,3 @@
+target:
+	fmvh.x.q	a0, ft1
+	fmvp.q.x	ft1, a0, a1

gas/testsuite/gas/riscv/zfa-fail.d

@@ -0,0 +1,2 @@
+#as: -march=rv64iq_zfa_zfh
+#error_output: zfa-fail.l

gas/testsuite/gas/riscv/zfa-fail.l

@@ -0,0 +1,28 @@
+.*: Assembler messages:
+.*: Error: illegal operands `fcvtmod\.w\.d a0,ft1'
+.*: Error: illegal operands `fcvtmod\.w\.d a0,ft1,rne'
+.*: Error: illegal operands `fcvtmod\.w\.d a0,ft1,rdn'
+.*: Error: illegal operands `fcvtmod\.w\.d a0,ft1,rup'
+.*: Error: illegal operands `fcvtmod\.w\.d a0,ft1,rmm'
+.*: Error: illegal operands `fcvtmod\.w\.d a0,ft1,dyn'
+.*: Error: illegal operands `fcvtmod\.w\.d a0,ft1,invalid'
+.*: Error: improper fli value field \(-1\), value must be 0\.\.\.29 or min, inf or nan
+.*: Error: improper fli value field \(-1\), value must be 0\.\.\.29 or min, inf or nan
+.*: Error: improper fli value field \(-1\), value must be 0\.\.\.29 or min, inf or nan
+.*: Error: improper fli value field \(-1\), value must be 0\.\.\.29 or min, inf or nan
+.*: Error: improper fli value field \(-2\), value must be 0\.\.\.29 or min, inf or nan
+.*: Error: improper fli value field \(-2\), value must be 0\.\.\.29 or min, inf or nan
+.*: Error: improper fli value field \(-2\), value must be 0\.\.\.29 or min, inf or nan
+.*: Error: improper fli value field \(-2\), value must be 0\.\.\.29 or min, inf or nan
+.*: Error: improper fli value field \(30\), value must be 0\.\.\.29 or min, inf or nan
+.*: Error: improper fli value field \(30\), value must be 0\.\.\.29 or min, inf or nan
+.*: Error: improper fli value field \(30\), value must be 0\.\.\.29 or min, inf or nan
+.*: Error: improper fli value field \(30\), value must be 0\.\.\.29 or min, inf or nan
+.*: Error: improper fli value field \(32\), value must be 0\.\.\.29 or min, inf or nan
+.*: Error: improper fli value field \(32\), value must be 0\.\.\.29 or min, inf or nan
+.*: Error: improper fli value field \(32\), value must be 0\.\.\.29 or min, inf or nan
+.*: Error: improper fli value field \(32\), value must be 0\.\.\.29 or min, inf or nan
+.*: Error: illegal operands `fli\.h ft1,invalid'
+.*: Error: illegal operands `fli\.s ft1,invalid'
+.*: Error: illegal operands `fli\.d ft1,invalid'
+.*: Error: illegal operands `fli\.q ft1,invalid'

gas/testsuite/gas/riscv/zfa-fail.s

@@ -0,0 +1,36 @@
+target:
+	# fcvtmod.w.d: Requires explicit rounding mode.
+	fcvtmod.w.d	a0, ft1
+
+	# fcvtmod.w.d: Rounding mode other than rtz are reserved.
+	fcvtmod.w.d	a0, ft1, rne
+	fcvtmod.w.d	a0, ft1, rdn
+	fcvtmod.w.d	a0, ft1, rup
+	fcvtmod.w.d	a0, ft1, rmm
+	fcvtmod.w.d	a0, ft1, dyn
+	# fcvtmod.w.d: Invalid rounding mode is invalid.
+	fcvtmod.w.d	a0, ft1, invalid
+
+	# fli.[hsdq]: Invalid value field (numeric)
+	fli.h	ft1, -1
+	fli.s	ft1, -1
+	fli.d	ft1, -1
+	fli.q	ft1, -1
+	fli.h	ft1, -2
+	fli.s	ft1, -2
+	fli.d	ft1, -2
+	fli.q	ft1, -2
+	fli.h	ft1, 30
+	fli.s	ft1, 30
+	fli.d	ft1, 30
+	fli.q	ft1, 30
+	fli.h	ft1, 32
+	fli.s	ft1, 32
+	fli.d	ft1, 32
+	fli.q	ft1, 32
+
+	# fli.[hsdq]: Invalid value field (symbolic)
+	fli.h	ft1, invalid
+	fli.s	ft1, invalid
+	fli.d	ft1, invalid
+	fli.q	ft1, invalid

gas/testsuite/gas/riscv/zfa.d

@@ -0,0 +1,93 @@
+#as: -march=rv32iq_zfa_zfh
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+f41000d3[ 	]+fli\.h[ 		]+ft1,0
+[ 	]+[0-9a-f]+:[ 	]+f41080d3[ 	]+fli\.h[ 		]+ft1,min
+[ 	]+[0-9a-f]+:[ 	]+f41100d3[ 	]+fli\.h[ 		]+ft1,2
+[ 	]+[0-9a-f]+:[ 	]+f41d80d3[ 	]+fli\.h[ 		]+ft1,27
+[ 	]+[0-9a-f]+:[ 	]+f41e00d3[ 	]+fli\.h[ 		]+ft1,28
+[ 	]+[0-9a-f]+:[ 	]+f41e80d3[ 	]+fli\.h[ 		]+ft1,29
+[ 	]+[0-9a-f]+:[ 	]+f41080d3[ 	]+fli\.h[ 		]+ft1,min
+[ 	]+[0-9a-f]+:[ 	]+f41f00d3[ 	]+fli\.h[ 		]+ft1,inf
+[ 	]+[0-9a-f]+:[ 	]+f41f80d3[ 	]+fli\.h[ 		]+ft1,nan
+[ 	]+[0-9a-f]+:[ 	]+f01000d3[ 	]+fli\.s[ 		]+ft1,0
+[ 	]+[0-9a-f]+:[ 	]+f01080d3[ 	]+fli\.s[ 		]+ft1,min
+[ 	]+[0-9a-f]+:[ 	]+f01100d3[ 	]+fli\.s[ 		]+ft1,2
+[ 	]+[0-9a-f]+:[ 	]+f01d80d3[ 	]+fli\.s[ 		]+ft1,27
+[ 	]+[0-9a-f]+:[ 	]+f01e00d3[ 	]+fli\.s[ 		]+ft1,28
+[ 	]+[0-9a-f]+:[ 	]+f01e80d3[ 	]+fli\.s[ 		]+ft1,29
+[ 	]+[0-9a-f]+:[ 	]+f01080d3[ 	]+fli\.s[ 		]+ft1,min
+[ 	]+[0-9a-f]+:[ 	]+f01f00d3[ 	]+fli\.s[ 		]+ft1,inf
+[ 	]+[0-9a-f]+:[ 	]+f01f80d3[ 	]+fli\.s[ 		]+ft1,nan
+[ 	]+[0-9a-f]+:[ 	]+f21000d3[ 	]+fli\.d[ 		]+ft1,0
+[ 	]+[0-9a-f]+:[ 	]+f21080d3[ 	]+fli\.d[ 		]+ft1,min
+[ 	]+[0-9a-f]+:[ 	]+f21100d3[ 	]+fli\.d[ 		]+ft1,2
+[ 	]+[0-9a-f]+:[ 	]+f21d80d3[ 	]+fli\.d[ 		]+ft1,27
+[ 	]+[0-9a-f]+:[ 	]+f21e00d3[ 	]+fli\.d[ 		]+ft1,28
+[ 	]+[0-9a-f]+:[ 	]+f21e80d3[ 	]+fli\.d[ 		]+ft1,29
+[ 	]+[0-9a-f]+:[ 	]+f21080d3[ 	]+fli\.d[ 		]+ft1,min
+[ 	]+[0-9a-f]+:[ 	]+f21f00d3[ 	]+fli\.d[ 		]+ft1,inf
+[ 	]+[0-9a-f]+:[ 	]+f21f80d3[ 	]+fli\.d[ 		]+ft1,nan
+[ 	]+[0-9a-f]+:[ 	]+f61000d3[ 	]+fli\.q[ 		]+ft1,0
+[ 	]+[0-9a-f]+:[ 	]+f61080d3[ 	]+fli\.q[ 		]+ft1,min
+[ 	]+[0-9a-f]+:[ 	]+f61100d3[ 	]+fli\.q[ 		]+ft1,2
+[ 	]+[0-9a-f]+:[ 	]+f61d80d3[ 	]+fli\.q[ 		]+ft1,27
+[ 	]+[0-9a-f]+:[ 	]+f61e00d3[ 	]+fli\.q[ 		]+ft1,28
+[ 	]+[0-9a-f]+:[ 	]+f61e80d3[ 	]+fli\.q[ 		]+ft1,29
+[ 	]+[0-9a-f]+:[ 	]+f61080d3[ 	]+fli\.q[ 		]+ft1,min
+[ 	]+[0-9a-f]+:[ 	]+f61f00d3[ 	]+fli\.q[ 		]+ft1,inf
+[ 	]+[0-9a-f]+:[ 	]+f61f80d3[ 	]+fli\.q[ 		]+ft1,nan
+[ 	]+[0-9a-f]+:[ 	]+2c3100d3[ 	]+fmin\.h[ 		]+ft1,ft2,ft3
+[ 	]+[0-9a-f]+:[ 	]+2c3120d3[ 	]+fminm\.h[ 		]+ft1,ft2,ft3
+[ 	]+[0-9a-f]+:[ 	]+283100d3[ 	]+fmin\.s[ 		]+ft1,ft2,ft3
+[ 	]+[0-9a-f]+:[ 	]+283120d3[ 	]+fminm\.s[ 		]+ft1,ft2,ft3
+[ 	]+[0-9a-f]+:[ 	]+2a3100d3[ 	]+fmin\.d[ 		]+ft1,ft2,ft3
+[ 	]+[0-9a-f]+:[ 	]+2a3120d3[ 	]+fminm\.d[ 		]+ft1,ft2,ft3
+[ 	]+[0-9a-f]+:[ 	]+2e3100d3[ 	]+fmin\.q[ 		]+ft1,ft2,ft3
+[ 	]+[0-9a-f]+:[ 	]+2e3120d3[ 	]+fminm\.q[ 		]+ft1,ft2,ft3
+[ 	]+[0-9a-f]+:[ 	]+2c3110d3[ 	]+fmax\.h[ 		]+ft1,ft2,ft3
+[ 	]+[0-9a-f]+:[ 	]+2c3130d3[ 	]+fmaxm\.h[ 		]+ft1,ft2,ft3
+[ 	]+[0-9a-f]+:[ 	]+283110d3[ 	]+fmax\.s[ 		]+ft1,ft2,ft3
+[ 	]+[0-9a-f]+:[ 	]+283130d3[ 	]+fmaxm\.s[ 		]+ft1,ft2,ft3
+[ 	]+[0-9a-f]+:[ 	]+2a3110d3[ 	]+fmax\.d[ 		]+ft1,ft2,ft3
+[ 	]+[0-9a-f]+:[ 	]+2a3130d3[ 	]+fmaxm\.d[ 		]+ft1,ft2,ft3
+[ 	]+[0-9a-f]+:[ 	]+2e3110d3[ 	]+fmax\.q[ 		]+ft1,ft2,ft3
+[ 	]+[0-9a-f]+:[ 	]+2e3130d3[ 	]+fmaxm\.q[ 		]+ft1,ft2,ft3
+[ 	]+[0-9a-f]+:[ 	]+4445f553[ 	]+fround\.h[ 		]+fa0,fa1
+[ 	]+[0-9a-f]+:[ 	]+44459553[ 	]+fround\.h[ 		]+fa0,fa1,rtz
+[ 	]+[0-9a-f]+:[ 	]+4045f553[ 	]+fround\.s[ 		]+fa0,fa1
+[ 	]+[0-9a-f]+:[ 	]+40459553[ 	]+fround\.s[ 		]+fa0,fa1,rtz
+[ 	]+[0-9a-f]+:[ 	]+4245f553[ 	]+fround\.d[ 		]+fa0,fa1
+[ 	]+[0-9a-f]+:[ 	]+42459553[ 	]+fround\.d[ 		]+fa0,fa1,rtz
+[ 	]+[0-9a-f]+:[ 	]+4645f553[ 	]+fround\.q[ 		]+fa0,fa1
+[ 	]+[0-9a-f]+:[ 	]+46459553[ 	]+fround\.q[ 		]+fa0,fa1,rtz
+[ 	]+[0-9a-f]+:[ 	]+4455f553[ 	]+froundnx\.h[ 		]+fa0,fa1
+[ 	]+[0-9a-f]+:[ 	]+44559553[ 	]+froundnx\.h[ 		]+fa0,fa1,rtz
+[ 	]+[0-9a-f]+:[ 	]+4055f553[ 	]+froundnx\.s[ 		]+fa0,fa1
+[ 	]+[0-9a-f]+:[ 	]+40559553[ 	]+froundnx\.s[ 		]+fa0,fa1,rtz
+[ 	]+[0-9a-f]+:[ 	]+4255f553[ 	]+froundnx\.d[ 		]+fa0,fa1
+[ 	]+[0-9a-f]+:[ 	]+42559553[ 	]+froundnx\.d[ 		]+fa0,fa1,rtz
+[ 	]+[0-9a-f]+:[ 	]+4655f553[ 	]+froundnx\.q[ 		]+fa0,fa1
+[ 	]+[0-9a-f]+:[ 	]+46559553[ 	]+froundnx\.q[ 		]+fa0,fa1,rtz
+[ 	]+[0-9a-f]+:[ 	]+c2809553[ 	]+fcvtmod\.w\.d[ 	]+a0,ft1,rtz
+[ 	]+[0-9a-f]+:[ 	]+a4209553[ 	]+flt\.h[ 		]+a0,ft1,ft2
+[ 	]+[0-9a-f]+:[ 	]+a420d553[ 	]+fltq\.h[ 		]+a0,ft1,ft2
+[ 	]+[0-9a-f]+:[ 	]+a0209553[ 	]+flt\.s[ 		]+a0,ft1,ft2
+[ 	]+[0-9a-f]+:[ 	]+a020d553[ 	]+fltq\.s[ 		]+a0,ft1,ft2
+[ 	]+[0-9a-f]+:[ 	]+a2209553[ 	]+flt\.d[ 		]+a0,ft1,ft2
+[ 	]+[0-9a-f]+:[ 	]+a220d553[ 	]+fltq\.d[ 		]+a0,ft1,ft2
+[ 	]+[0-9a-f]+:[ 	]+a6209553[ 	]+flt\.q[ 		]+a0,ft1,ft2
+[ 	]+[0-9a-f]+:[ 	]+a620d553[ 	]+fltq\.q[ 		]+a0,ft1,ft2
+[ 	]+[0-9a-f]+:[ 	]+a4208553[ 	]+fle\.h[ 		]+a0,ft1,ft2
+[ 	]+[0-9a-f]+:[ 	]+a420c553[ 	]+fleq\.h[ 		]+a0,ft1,ft2
+[ 	]+[0-9a-f]+:[ 	]+a0208553[ 	]+fle\.s[ 		]+a0,ft1,ft2
+[ 	]+[0-9a-f]+:[ 	]+a020c553[ 	]+fleq\.s[ 		]+a0,ft1,ft2
+[ 	]+[0-9a-f]+:[ 	]+a2208553[ 	]+fle\.d[ 		]+a0,ft1,ft2
+[ 	]+[0-9a-f]+:[ 	]+a220c553[ 	]+fleq\.d[ 		]+a0,ft1,ft2
+[ 	]+[0-9a-f]+:[ 	]+a6208553[ 	]+fle\.q[ 		]+a0,ft1,ft2
+[ 	]+[0-9a-f]+:[ 	]+a620c553[ 	]+fleq\.q[ 		]+a0,ft1,ft2