From b9592093b54d6d0faa2e355d74f172bb857b791d Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 30 Aug 2023 15:28:05 +0200 Subject: [PATCH] Update examples to synth_lattice --- machxo2/examples/README.md | 6 +++--- machxo2/examples/demo-vhdl.sh | 2 +- machxo2/examples/demo.sh | 2 +- machxo2/examples/mitertest.sh | 8 ++++---- machxo2/examples/simple.sh | 4 ++-- machxo2/examples/simtest.sh | 6 +++--- 6 files changed, 14 insertions(+), 14 deletions(-) diff --git a/machxo2/examples/README.md b/machxo2/examples/README.md index 545afd2649..7d3d3470c9 100644 --- a/machxo2/examples/README.md +++ b/machxo2/examples/README.md @@ -73,7 +73,7 @@ few reasons: 2. To keep the `gold`/`gate` generation simpler, examples are currently assumed to _not_ instantiate MachXO2 simulation primitives directly (`FACADE_IO`, `FACADE_FF`, etc). - 3. `synth_machxo2` runs `deminout` on `inouts` when generating the `gate` + 3. `synth_lattice` runs `deminout` on `inouts` when generating the `gate` module. This is not handled yet when generating the `gold` module. ## Verilog Examples @@ -101,9 +101,9 @@ few reasons: Defaults to the `nextpnr-machxo2` binary at the root of the `nextpnr` source tree. This should be set, for instance, if doing an out-of-tree build of `nextpnr-machxo2`. -* `CELLS_SIM`- Set to the location of `machxo2/cells_sim.v` simulation models. +* `CELLS_SIM`- Set to the location of `lattice/cells_sim_xo2.v` simulation models. Defaults to whatever `yosys-config` associated with the above `YOSYS` binary - returns. You may want to set this to `/path/to/yosys/src/share/machxo2/cells_sim.v` + returns. You may want to set this to `/path/to/yosys/src/share/lattice/cells_sim_xo2.v` if doing development; `yosys-config` cannot find these "before-installation" simulation models. * `TRELLIS_DB`- Set to the location of the Project Trellis database to use. diff --git a/machxo2/examples/demo-vhdl.sh b/machxo2/examples/demo-vhdl.sh index 054b8585dd..1258344912 100644 --- a/machxo2/examples/demo-vhdl.sh +++ b/machxo2/examples/demo-vhdl.sh @@ -18,7 +18,7 @@ set -ex ${YOSYS:-yosys} -p "ghdl --std=08 prims.vhd ${1}.vhd -e; attrmap -tocase LOC - synth_machxo2 -json ${1}-vhdl.json" + synth_lattice -family xo2 -json ${1}-vhdl.json" ${NEXTPNR:-../../nextpnr-machxo2} --device LCMXO2-1200HC-4SG32C --json $1-vhdl.json --textcfg $1-vhdl.txt ecppack --compress $DB_ARG $1-vhdl.txt $1-vhdl.bit tinyproga -b $1-vhdl.bit diff --git a/machxo2/examples/demo.sh b/machxo2/examples/demo.sh index 8e8a49a6d0..d5c138720c 100644 --- a/machxo2/examples/demo.sh +++ b/machxo2/examples/demo.sh @@ -16,7 +16,7 @@ fi set -ex -${YOSYS:-yosys} -p "read_verilog $1.v; synth_machxo2 -json $1.json" +${YOSYS:-yosys} -p "read_verilog $1.v; synth_lattice -family xo2 -json $1.json" ${NEXTPNR:-../../nextpnr-machxo2} --device LCMXO2-1200HC-4SG32C --json $1.json --textcfg $1.txt ecppack --compress $DB_ARG $1.txt $1.bit tinyproga -b $1.bit diff --git a/machxo2/examples/mitertest.sh b/machxo2/examples/mitertest.sh index 161eaa8861..be01eae6de 100644 --- a/machxo2/examples/mitertest.sh +++ b/machxo2/examples/mitertest.sh @@ -44,7 +44,7 @@ do_sat() { rename top gold read_verilog ${2}${1}.v rename top gate - read_verilog +/machxo2/cells_sim.v + read_verilog +/lattice/cells_sim_xo2.v miter -equiv -make_assert -flatten gold gate ${2}${1}_miter hierarchy -top ${2}${1}_miter @@ -56,7 +56,7 @@ do_smt() { rename top gold read_verilog ${2}${1}.v rename top gate - read_verilog +/machxo2/cells_sim.v + read_verilog +/lattice/cells_sim_xo2.v miter -equiv -make_assert gold gate ${2}${1}_miter hierarchy -top ${2}${1}_miter; proc; @@ -72,9 +72,9 @@ do_smt() { set -ex ${YOSYS:-yosys} -p "read_verilog ${1}.v - synth_machxo2 -json ${1}.json" + synth_lattice -family xo2 -json ${1}.json" ${NEXTPNR:-../../nextpnr-machxo2} $NEXTPNR_MODE --device LCMXO2-1200HC-4SG32C --json ${1}.json --write ${2}${1}.json -${YOSYS:-yosys} -p "read_verilog -lib +/machxo2/cells_sim.v +${YOSYS:-yosys} -p "read_verilog -lib +/lattice/cells_sim_xo2.v read_json ${2}${1}.json clean -purge write_verilog -noattr -norename ${2}${1}.v" diff --git a/machxo2/examples/simple.sh b/machxo2/examples/simple.sh index 4037fa6f1c..540e7fd286 100644 --- a/machxo2/examples/simple.sh +++ b/machxo2/examples/simple.sh @@ -24,10 +24,10 @@ esac set -ex ${YOSYS:-yosys} -p "read_verilog ${1}.v - synth_machxo2 -json ${1}.json + synth_lattice -family xo2 -json ${1}.json show -format png -prefix ${1}" ${NEXTPNR:-../../nextpnr-machxo2} $NEXTPNR_MODE --device LCMXO2-1200HC-4SG32C --json ${1}.json --write ${2}${1}.json -${YOSYS:-yosys} -p "read_verilog -lib +/machxo2/cells_sim.v +${YOSYS:-yosys} -p "read_verilog -lib +/lattice/cells_sim_xo2.v read_json ${2}${1}.json clean -purge show -format png -prefix ${2}${1} diff --git a/machxo2/examples/simtest.sh b/machxo2/examples/simtest.sh index eb97719bdd..e50779798f 100644 --- a/machxo2/examples/simtest.sh +++ b/machxo2/examples/simtest.sh @@ -29,11 +29,11 @@ fi set -ex ${YOSYS:-yosys} -p "read_verilog ${1}.v - synth_machxo2 -json ${1}.json" + synth_lattice -family xo2 -json ${1}.json" ${NEXTPNR:-../../nextpnr-machxo2} $NEXTPNR_MODE --device LCMXO2-1200HC-4SG32C --json ${1}.json --write ${2}${1}.json -${YOSYS:-yosys} -p "read_verilog -lib +/machxo2/cells_sim.v +${YOSYS:-yosys} -p "read_verilog -lib +/lattice/cells_sim_xo2.v read_json ${2}${1}.json clean -purge write_verilog -noattr -norename ${2}${1}.v" -iverilog -o ${1}_simtest ${CELLS_SIM:-`${YOSYS:yosys}-config --datdir/machxo2/cells_sim.v`} ${1}_tb.v ${2}${1}.v +iverilog -o ${1}_simtest ${CELLS_SIM:-`${YOSYS:yosys}-config --datdir/lattice/cells_sim_xo2.v`} ${1}_tb.v ${2}${1}.v vvp -N ./${1}_simtest