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will support python interface? #344
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Hi @zjd1988 , So far, no plan to support python. Could you share more background why you interested with python interface? I can promote your information to the team. Thanks |
hi @sunshinemyson, thanks for your reply. |
@zjd1988 , Sorry that RV1109 is not actively supported from our side, even if you can overcome the conversion issue, their driver stack is not verified with TIM-VX. I would like to recommend VIM3/VIM3L dev-kit to you, they are active and verified by us. The vx-delegate is preferred for inference on board. Hope you can enjoy it. Thanks. |
@sunshinemyson I have implemented a simple python binding for timvx,verified with lenet example |
Great job, Thanks for sharing. Would you like merge it to tim-vx? |
@sunshinemyson I‘m not sure’whether the code quality is good enough to merge. You may check it out first. |
Hi @sunshinemyson, I have a simple question, weights tensor's data layout is NCHW or WHCN in lenet_asymu8_weights.h? |
Hi @sunshinemyson, Is it convenient to communication with wechat (xd-zjd) |
For convolution's kernel, data layout in memory is Oc,Ic,H,W, In VX, it descripted in shape as C_Array[W,H,Ic,Oc] - column major description. |
@sunshinemyson Does it necessarily mean all the data layout description in tim-vx is column major? Or have you documented this somewhere I missed out? |
Sorry for late. https://github.com/VeriSilicon/TIM-VX/blob/main/docs/Programming_Guide.md#memory-layout |
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