v0.26.0

• Fixed parse error on constant declarations with newlines, issue #59

v0.25.0

• Fixed issue #58 by making the VHDL parser handle more cases.

v0.24.0

• More graceful shutdown of ModelSim process under normal circumstances preventing the vish_stacktrace.vstf file from being created
• Fixed #56 by removing use of TCL 8.5 only list expand operator causing problems for older ModelSim with TCL 8.4
• .vp file ending recognized as verilog

v0.23.0

• Fixed dependency scanning bug. Issue #50. Space not accepted between entity and parenthesis of architecture name.

v0.22.0

• Adds --exit-0 flag to exit with code 0 even with failed tests but not when a fatal error occured

v0.21.0

• Adds support for parallel test execution
• Improves textual report

v0.20.0

• Adds dependency scanning support for configurations. Issue #46

v0.19.0

• Adds support for adding extra flags to vsim command.

v0.18.0

• Adds support for GHDL.

v0.17.0

• Adds support for disabling warnings from IEEE packages.