FIFO_ctr.vhd.bak

------------------------------------------------------------------------
--
--        Copyright (C) 2018
--        All rights reserved
--
--        filename: FIFO_ctr
--
--        created by Tyl at 2019-01-06 08:48:20
--        modified by Tyl at 
--
------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity FIFO_ctr is
	port(
		clk, rst: in std_logic;
		half_FIFO_used: in std_logic;
		RAMWFull: in std_logic;
		FIFOWen: out std_logic;
		FIFORen: out std_logic
	);
end FIFO_ctr;