PDB.pro

update=Sa 06 Apr 2019 04:02:54 CEST
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=
CopperLayerCount=2
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.15
MinViaDiameter=0.5
MinViaDrill=0.25
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.2
TrackWidth2=0.15
TrackWidth3=0.2
TrackWidth4=0.25
TrackWidth5=0.4
TrackWidth6=0.5
TrackWidth7=1
TrackWidth8=2
TrackWidth9=2.5
TrackWidth10=3
ViaDiameter1=0.5
ViaDrill1=0.25
ViaDiameter2=0.5
ViaDrill2=0.25
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
SilkLineWidth=0.25
SilkTextSizeV=1
SilkTextSizeH=1
SilkTextSizeThickness=0.25
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.2
CopperTextSizeV=1.5
CopperTextSizeH=1.5
CopperTextThickness=0.3
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.09999999999999999
CourtyardLineWidth=0.05
OthersLineWidth=0.15
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0
SolderMaskMinWidth=0.25
SolderPasteClearance=0
SolderPasteRatio=-0