mult62.a

; mult62.a
; based on Dr Jefyll, http://forum.6502.org/viewtopic.php?f=9&t=689&start=0#p19958
; - adjusted to use fixed zero page addresses
; - removed 'decrement to avoid clc' as this is slower on average
; - rearranged memory use to remove final memory copy and give LSB first order to result
; - removed temp zp storage bytes
; - unrolled the outer loop
; - unrolled the two inner loops once
;
; 16 bit x 16 bit unsigned multiply, 32 bit result
; Average cycles: 442.00
; 93 bytes

multiplicand    = $02   ; 2 bytes
multiplier      = $04   ; 2 bytes
result          = $04   ; 4 bytes   (note: shares memory with multiplier)

* = $0200

; 16 bit x 16 bit unsigned multiply, 32 bit result
;
; On Entry:
;   (multiplier, multiplier+1): two byte multiplier, four bytes needed for result
;   (multiplicand, multiplicand+1): two byte multiplicand
; On Exit:
;   (result, result+1, result+2, result+3): product
mult
    lda #0              ;
    sta result+2        ; 16 bits of zero in A, result+2
                        ;  Note:    First 8 shifts are  A -> result+2 -> result
                        ;           Final 8 shifts are  A -> result+2 -> result+1

    ; --- 1st byte ---
    ldy #4              ; count for inner loop
    lsr result

    ; inner loop (8 times)
inner_loop
    ; first time
    bcc +
    tax                 ; retain A
    lda result+2
    clc
    adc multiplicand
    sta result+2
    txa                 ; recall A
    adc multiplicand+1

+
    ror                 ; shift
    ror result+2
    ror result

    ; second time
    bcc +
    tax                 ; retain A
    lda result+2
    clc
    adc multiplicand
    sta result+2
    txa                 ; recall A
    adc multiplicand+1

+
    ror                 ; shift
    ror result+2
    ror result

    dey
    bne inner_loop      ; go back for 1 more shift?

    ; --- 2nd byte ---
    ldy #4              ; count for inner loop
    lsr result+1

    ; inner loop (8 times)
inner_loop2
    ; first time
    bcc +
    tax                 ; retain A
    lda result+2
    clc
    adc multiplicand
    sta result+2
    txa                 ; recall A
    adc multiplicand+1

+
    ror                 ; shift
    ror result+2
    ror result+1

    ; second time
    bcc +
    tax                 ; retain A
    lda result+2
    clc
    adc multiplicand
    sta result+2
    txa                 ; recall A
    adc multiplicand+1

+
    ror                 ; shift
    ror result+2
    ror result+1
    dey
    bne inner_loop2     ; go back for 1 more shift?

    sta result+3        ; ms byte of hi-word of result
    rts