mpl2: support snapping of macros with pins in multiple layers

[AcKoucher]

Resolve #5854.

Attempts to move the macro to different track-grid positions after snapping based on the first layer we find.
First all vertical layers with pins, then all horizontal layers with pins.
The goal is to search for a location that results in the largest number of layers with pins in the same direction to have those pins correctly aligned with the grid.

[github-actions]

clang-tidy made some suggestions

[github-actions]

clang-tidy review says "All clean, LGTM! 👍"

[github-actions]

clang-tidy review says "All clean, LGTM! 👍"

[github-actions]

clang-tidy review says "All clean, LGTM! 👍"

[github-actions]

clang-tidy review says "All clean, LGTM! 👍"

[github-actions]

clang-tidy review says "All clean, LGTM! 👍"

[github-actions]

clang-tidy review says "All clean, LGTM! 👍"

[github-actions]

clang-tidy made some suggestions

[github-actions]

clang-tidy review says "All clean, LGTM! 👍"

[oharboe]

Took it for a quick spin on The-OpenROAD-Project/OpenROAD-flow-scripts#2412:

make DESIGN_CONFIG=designs/asap7/mock-array/config.mk

Results in error:

[INFO PPL-0007] Random pin placement.
[WARNING PPL-0106] At least 2 pins in position (42633, 43200), layer M3, port io_ins_down[61].
[ERROR PPL-0107] Invalid pin placement.
Error: io_placement_util.tcl, 11 PPL-0107

[AcKoucher]

@oharboe I believe this is not related to the macro placement. Do you see macros with pins out of track after mpl?

[oharboe]

@oharboe I believe this is not related to the macro placement. Do you see macros with pins out of track after mpl?

I don't know how to check that...

[AcKoucher]

You can set the tracks visibility in the layout display and then find the pins in the layers you want.

Without the changes here, the pins in some layers were not properly aligned with the grid.
With the changes here we have something like this:

Some pins of ces_0_0

So you shouldn't have the DRCs problems anymore.

[oharboe]

Never gets far enough... This might be another manifestation of a problem that I raised with @maliberty ?

Standalone testcase io_placement_problem.tar.gz

$ make DESIGN_CONFIG=designs/asap7/mock-array/config.mk 
Running io_placement_random.tcl, stage 2_2_floorplan_io
[INFO ORD-0030] Using 16 thread(s).
[INFO PPL-0048] Restrict pins [ io_ins_up[0] io_ins_up[10] io_ins_up[11] io_ins_up[12] io_ins_up[13] ... ] to region 0.00u-43.20u at the BOTTOM edge.
[INFO PPL-0048] Restrict pins [ io_ins_left[0] io_ins_left[10] io_ins_left[11] io_ins_left[12] io_ins_left[13] ... ] to region 0.00u-43.20u at the RIGHT edge.
[INFO PPL-0048] Restrict pins [ io_lsbOuts_0 io_lsbOuts_1 io_lsbOuts_2 io_lsbOuts_3 io_lsbOuts_4 ... ] to region 0.00u-43.20u at the RIGHT edge.
[INFO PPL-0048] Restrict pins [ clock ] to region 0.00u-43.20u at the TOP edge.
place_pins -hor_layers M2 M4 -ver_layers M3 M5 -random
Found 0 macro blocks.
Using 2 tracks default min distance between IO pins.
[INFO PPL-0007] Random pin placement.
[WARNING PPL-0106] At least 2 pins in position (42633, 43200), layer M3, port io_ins_down[61].
[ERROR PPL-0107] Invalid pin placement.
Error: io_placement_util.tcl, 11 PPL-0107
Command exited with non-zero status 1
Elapsed time: 0:01.09[h:]min:sec. CPU time: user 1.04 sys 0.05 (100%). Peak memory: 217100KB.
make[2]: *** [Makefile:651: do-2_2_floorplan_io] Error 1
make[1]: *** [Makefile:649: results/asap7/mock-array_Element/base/2_2_floorplan_io.odb] Error 2
make: *** [Makefile:351: results/asap7/mock-array_Element/base/Element.lib] Error 2
$ ls results/asap7/mock-array_Element/base/
1_1_yosys.v  1_synth.rtlil  1_synth.sdc  1_synth.v  2_1_floorplan.odb  2_floorplan.sdc  clock_period.txt  keep_hierarchy.tcl  mem.json

[eder-matheus]

@oharboe @AcKoucher The PPL error was fixed last week, but your branch is not updated with the latest master branch. You should not see the PPL issue once you merge the latest master in this PR.

[oharboe]

@oharboe @AcKoucher The PPL error was fixed last week, but your branch is not updated with the latest master branch. You should not see the PPL issue once you merge the latest master in this PR.

Indeed.

[oharboe]

The-OpenROAD-Project/OpenROAD-flow-scripts#2412 seems to work fine with this PR+master of OpenROAD. 👍

[maliberty]

secure CI?

[maliberty]

@eder-matheus you still have requested change status

[AcKoucher]

Running secure-CI

[AcKoucher]

@eder-matheus @maliberty

Public CI showed some failures:

nangate45 bp_be
      [ERROR DRT-0416] Term w_mask_in[0] contains offgrid pin shape. Pin shape ( 1070263 1136310 ) ( 1070403 1136450 ) is not a multiple of the manufacturing grid 10.

nangate45 bp_fe
      [ERROR GRT-0119] Routing congestion too high. Check the congestion heatmap in the GUI and load ./reports/nangate45/bp_fe/base/congestion.rpt in the DRC viewer.

nangate45 bp_multi
      [ERROR DRT-0416] Term w_mask_in[0] contains offgrid pin shape. Pin shape ( 1872632 45150 ) ( 1872772 45290 ) is not a multiple of the manufacturing grid 10.

nangate45 tinyRocket
      [ERROR DRT-0416] Term w_mask_in[0] contains offgrid pin shape. Pin shape ( 142613 829430 ) ( 142753 829570 ) is not a multiple of the manufacturing grid 10.

These were because for macros that don't have pins to be aligned with the track in a certain direction, we were not aligning with the manufacturing grid.

I pushed a change to ensure that, even we don't need to align with the tracks, we'll still align with the manufacturing grid.

I'll re-run CI.

[github-actions]

clang-tidy review says "All clean, LGTM! 👍"

[AcKoucher]

Secure-CI is fine.