external registers - implementation of ack signals

[arnonsha]

My design has many external registers. It is also sensitive to area (gate count)

According to documentation the read and write ack signals should be:

assign hwif_out.MYFIELD.rd_ack  = hwif_in.MYFIELD.req && !hwif_in.MYFIELD.req_is_wr;
assign hwif_out.MYFIELD.wr_ack  = hwif_in.MYFIELD.req &&  hwif_in.MYFIELD.req_is_wr;

However in practice we can completely omit the AND gates with the request signal if we don't care about the rd_ack and wr_ack signals going back to the cpu interface (for example if we know that the transaction will complete is a single cycle). In this case the ack signals can be set as follows:

assign hwif_out.MYFIELD.rd_ack  = hwif_in.MYFIELD.req;
assign hwif_out.MYFIELD.wr_ack  = hwif_in.MYFIELD.req;

rationale:
The rd_ack signal is used as a selector for the register file's read mux (readback_array). During read transactions it is still set correctly, while in write transactions I don't care about the read mux (logically speaking. Power consumption however will be somewhat higher since the read mux changes also during write).

Does that sounds reasonable ?

thanks

[amykyta3]

It really depends on the CPU interface protocol you are using.
In your example, you would technically be issuing a read and write ack for every transaction which is semantically incorrect.

For simple interfaces like APB, I'm pretty sure it would still work fine. But for protocols like AXI4-Lite, you risk putting the state machine out of sync and potentially issuing an unexpected response on the wrong channel.

Given the current implementation, I would not recommend this shortcut.

[arnonsha]

Thanks for the detailed answer.
I was writing the above under the context of APB and AHB (using the generic cpu interface). I agree this wouldn't work with AXI.