VHDL Package Compatibilty

[eddlestar]

Different take than the VHDL request - I'm instantiating the SV output in a VHDL design. If I take the SV package and make a VHDL equivalent (records that match the structs), I'm able to keep the SV code mostly unchanged.

Request:

1. __ is unsupported in VHDL names, so package names like global_csr__VER_SEMANTIC_REG_SEL__in_t are illegal in VHDL. Would it be possible to generate names that don't have double underscore?
2. next is a VHDL reserved keyword, would it be possible to use a different name (next_, next_value, etc.)
3. More of a reach request would be to generate a VHDL package automatically.

Thanks - love this tool :)

[amykyta3]

Nice. I didn't realize tools even allowed casting structs/records across language boundaries. Glad to hear this area has improved in EDA tools. I'd be happy to figure out solutions to get this to work, even if it is a "VHDL compatibility mode"

What synthesis tool are you using? I'd like to understand how the tool defines the rules for this from the VHDL side of things. Standardization of VHDL/Verilog boundaries is pretty ad-hoc and varies wildly between tools.
I assume you are manually creating an equivalent record declaration in VHDL? Does the type name need to match exactly or are the cross-language rules permissive enough to allow differing type names as long as the struct/record members are equivalent?

I was not aware of the double-underscore limitation in VHDL. That seems like quite an absurd limitation, but I see now that the formal grammar of the language actually specifies this. Weird.

Regarding the thing.next struct member, have you tried using the extended identifier syntax that VHDL allows? You can escape controlled keywords via: thing.\next\. I believe you can do the same for the double-underscores.

Auto-generating a VHDL package wouldn't be too hard. I'd just like to pin down the above things a bit better and understand how this boundary is handled in tools.
I'll experiment with it a bit in Questa/Vivado

[RasmusGOlsen]

I tried out casting between SystemVerilog structs and VHDL records.

In Vivado you can cast packed and unpacked structs to records, but Quartus will not.

-- file: pkg.vhd
library ieee;
use ieee.std_logic_1164.all;

package pkg is

    type reg_t is record
        a: std_logic;
        b: std_logic;
    end record reg_t;

end package pkg;

// file: pkg.sv
package pkg;

    typedef struct packed {
        logic a;
        logic b;
    } reg_t;

endpackage: pkg

-- file: top.vhd
library ieee;
use ieee.std_logic_1164.all;

library work;
use work.pkg.reg_t;

entity top is
    port(
        clk_i: in  std_logic;
        a_i:   in  std_logic;
        b_i:   in  std_logic;
        a_o:   out std_logic;
        b_o:   out std_logic
    );
end top;


architecture rtl of top is

    component sub
        port(
            clk_i : in  std_logic;
            a_i   : in  std_logic;
            b_i   : in  std_logic;
            regs_o: out reg_t
        );
    end component sub;

    signal regs: reg_t;

begin

    i_sub: sub
        port map(
            clk_i  => clk_i,
            a_i    => a_i,
            b_i    => b_i,
            regs_o => regs
        );

    p_ff : process(clk_i)
    begin
        if rising_edge(clk_i) then
            a_o <= regs.a;
            b_o <= regs.b;
        end if;
    end process;

end rtl;

// file: sub.sv
module sub
    import pkg::reg_t;
(
    input  logic      clk_i,
    input  logic      a_i,
    input  logic      b_i,
    output reg_t      regs_o
);

    reg_t regs;

    always_ff @( posedge clk_i ) begin
        regs.a <= a_i;
        regs.b <= b_i;
    end

    assign regs_o = regs;

endmodule: sub