nbit_syncCount_parLoad.vhd.bak

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: Devashish Bishnoi 
-- 
-- Create Date:    14:21:44 11/16/2016 
-- Design Name: 
-- Module Name:    nbit_syncCount_parLoad - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity nbit_syncCount_parLoad is
	Generic (n : positive := 4);
	Port ( D_inputs : in  STD_LOGIC_VECTOR (n-1 downto 0);
           load : in  STD_LOGIC;
           count_enable : in  STD_LOGIC;
           CLK : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           Q_outputs : inout  STD_LOGIC_VECTOR (n-1 downto 0);
	   ripple_carry_out : out std_logic;
	   leds : out std_logic_vector (6 downto 0)
	); -- 7 bit decoded output
end nbit_syncCount_parLoad;

architecture Behavioral of nbit_syncCount_parLoad is
	
component nbit_incrementor
	generic ( n : positive := 4);
   Port ( InA : in  STD_LOGIC_VECTOR (n-1 downto 0);
           C_in : in  STD_LOGIC;
           Sum : out  STD_LOGIC_VECTOR (n-1 downto 0);
           C_out : out  STD_LOGIC);
end component;
	
component nbitReg is
	 generic(n : positive := 4);
    Port ( 
           D_inputs : in  STD_LOGIC_vector (n-1 downto 0);
			  CLK : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           preset : in  STD_LOGIC;
           Q_outputs : inout  STD_LOGIC_vector (n-1 downto 0);
           Q_bar_outputs : inout  STD_LOGIC_vector (n-1 downto 0));
end component;
	
component nbitTwoInputMux_VHDL is 
	generic (n: positive := 4);
    Port ( InA : in  STD_LOGIC_VECTOR (n-1 downto 0);
           InB : in  STD_LOGIC_VECTOR (n-1 downto 0);
           Control : in  STD_LOGIC;
           Output : out  STD_LOGIC_VECTOR (n-1 downto 0));
end component;

component bcd7seg is
port (
      CLK : in std_logic;
        bcd : in std_logic_vector(3 downto 0);  --BCD input
        leds : out std_logic_vector(6 downto 0)  -- 7 bit decoded output.
    );
end component;
--SIGNALS

signal inctomux : std_logic_vector (n-1 downto 0);
signal muxtoreg: std_logic_vector (n-1 downto 0);
--signal leds: std_logic_vector (6 downto 0);
begin

inc: nbit_incrementor generic map (n) port map (Q_outputs, count_enable, inctomux);
mux: nbitTwoInputMux_VHDL generic map (n) port map (inctomux, D_inputs, load, muxtoreg ); 
reg: nbitReg generic map (n) port map (muxtoreg, CLK, reset, '0', Q_outputs); 
seg: bcd7seg port map (CLK, Q_outputs, leds);

end Behavioral;