Fix esp32 clock definitions #2456
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SmingHub#2455 changed the timer2 timebase so it no longer corresponds with the microsecond system clock used for OsTimer.
ccount value accurately reflects selected CPU frequency
Systick is a down-counter
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This PR fixes an issue with `HostTests` which hangs consistently when testing Timer1 (used by HardwareTimer) on the Esp8266. The problem occurs whilst checking each timer for consistency against system time. This happens because the test code doesn't set a callback interrupt routine. It is only a problem on the Esp8266 because the callback routine is set directly on the interrupt vector. Other architectures use indirection and so do nothing if the callback isn't set. NB. Doing this with the Esp8266 would increase interrupt latency which would affect PWM timing, etc. Normal code uses the `HardwareTimer` class which contains logic to ensure this doesn't happen during setup. Timer1 has only a 23-bit counter so fails test with /16 divisor as it wraps at around 1.7s (test duration is 2 seconds). Fixed by restricting duration to timer maximum (less 1ms). Elapsed tick calculation check also improved by first checking whether timer is an UP or DOWN counter, and using timer maximum tick value to handle wraps correctly. This PR also reduces the number of test loops on the Host (from 2000 to 50). Note: Bug was introduced in #2456. Timer1 needed to be correctly configured (but inactive) to produce correct result for Esp32.
slaff
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Jan 19, 2024
This PR fixes an issue with `HostTests` which hangs consistently when testing Timer1 (used by HardwareTimer) on the Esp8266. The problem occurs whilst checking each timer for consistency against system time. This happens because the test code doesn't set a callback interrupt routine. It is only a problem on the Esp8266 because the callback routine is set directly on the interrupt vector. Other architectures use indirection and so do nothing if the callback isn't set. NB. Doing this with the Esp8266 would increase interrupt latency which would affect PWM timing, etc. Normal code uses the `HardwareTimer` class which contains logic to ensure this doesn't happen during setup. Timer1 has only a 23-bit counter so fails test with /16 divisor as it wraps at around 1.7s (test duration is 2 seconds). Fixed by restricting duration to timer maximum (less 1ms). Elapsed tick calculation check also improved by first checking whether timer is an UP or DOWN counter, and using timer maximum tick value to handle wraps correctly. This PR also reduces the number of test loops on the Host (from 2000 to 50). Note: Bug was introduced in #2456. Timer1 needed to be correctly configured (but inactive) to produce correct result for Esp32.
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#2455 changed the timer2 timebase so it no longer corresponds with the microsecond system clock used for OsTimer.
Added check in HostTests to catch this.
Also improve Host CPU clock emulation to accurately reflect selected frequency.
Also fix rp2040 esp_get_ccount return value, now passes tests.