From 1e61e1139c43fca15c3aebc431b10b9a216781fa Mon Sep 17 00:00:00 2001 From: srningap Date: Mon, 28 Aug 2023 15:52:39 +0530 Subject: [PATCH 1/7] enables both the buttons for 917SoC 2.0 boards --- .../BRD4325x/support/hal/rsi_hal_mcu_m4.c | 60 ++++++++++++++----- .../support/hal/rsi_hal_mcu_platform_init.c | 47 +++++++++++++++ 2 files changed, 93 insertions(+), 14 deletions(-) diff --git a/matter/si91x/siwx917/BRD4325x/support/hal/rsi_hal_mcu_m4.c b/matter/si91x/siwx917/BRD4325x/support/hal/rsi_hal_mcu_m4.c index 5cf849a50a..108e5514ff 100644 --- a/matter/si91x/siwx917/BRD4325x/support/hal/rsi_hal_mcu_m4.c +++ b/matter/si91x/siwx917/BRD4325x/support/hal/rsi_hal_mcu_m4.c @@ -22,8 +22,21 @@ #include "rsi_power_save.h" #endif -uint8_t btn0 = 1; -uint8_t btn1 = 1; +#define BTN_RELEASED 0 +#define BTN_PRESSED 1 + +#ifdef SI917_RADIO_BOARD_V2 +#define PIN_INT 7 +#ifndef M4_GPIO_PORT +#define M4_GPIO_PORT 0 +#endif +#ifndef M4_GPIO_PIN +#define M4_GPIO_PIN (11U) +#endif +#endif // SI917_RADIO_BOARD_V2 + +uint8_t gpio0 = 1; +uint8_t gpio2 = 1; void sl_button_on_change(uint8_t btn, uint8_t btnAction); @@ -59,6 +72,17 @@ void rsi_assertion(uint16_t assertion_val, const char *string) { } } +#if SI917_RADIO_BOARD_V2 +void IRQ059_Handler(void) { + // TODO: Replace with rsi_delay once that is fixed + for (int i = 0; i < 10000; i++) + __asm__("nop;"); + + RSI_EGPIO_IntClr(EGPIO, PIN_INT, INTERRUPT_STATUS_CLR); + RSI_EGPIO_GetPin(EGPIO, M4_GPIO_PORT, M4_GPIO_PIN) ? sl_button_on_change(1, BTN_RELEASED) : sl_button_on_change(1, BTN_PRESSED); +} +#endif // SI917_RADIO_BOARD_V2 + void IRQ021_Handler(void) { // TODO: Replace with rsi_delay once that is fixed for (int i = 0; i < 10000; i++) @@ -67,22 +91,30 @@ void IRQ021_Handler(void) { RSI_NPSSGPIO_ClrIntr(NPSS_GPIO_0_INTR); RSI_NPSSGPIO_ClrIntr(NPSS_GPIO_2_INTR); // if the btn is not pressed setting the state to 1 - if (RSI_NPSSGPIO_GetPin(NPSS_GPIO_2) && (!btn1)) { - btn1 = 1; - sl_button_on_change(1, 0); + if (RSI_NPSSGPIO_GetPin(NPSS_GPIO_2) && (!gpio2)) { + gpio2 = 1; +#ifdef SI917_RADIO_BOARD_V2 + sl_button_on_change(0, BTN_RELEASED); +#else + sl_button_on_change(1, BTN_RELEASED); +#endif //SI917_RADIO_BOARD_V2 } // geting the state of the gpio 2 pin and checking if the btn is already // pressed or not - if (!RSI_NPSSGPIO_GetPin(NPSS_GPIO_2) && btn1) { - btn1 = 0; - sl_button_on_change(1, 1); + if (!RSI_NPSSGPIO_GetPin(NPSS_GPIO_2) && gpio2) { + gpio2 = 0; +#ifdef SI917_RADIO_BOARD_V2 + sl_button_on_change(0, BTN_PRESSED); +#else + sl_button_on_change(1, BTN_PRESSED); +#endif // SI917_RADIO_BOARD_V2 } - if (RSI_NPSSGPIO_GetPin(NPSS_GPIO_0) && (!btn0)) { - btn0 = 1; - sl_button_on_change(0, 0); + if (RSI_NPSSGPIO_GetPin(NPSS_GPIO_0) && (!gpio0)) { + gpio0 = 1; + sl_button_on_change(0, BTN_RELEASED); } - if (!RSI_NPSSGPIO_GetPin(NPSS_GPIO_0) && btn0) { - btn0 = 0; - sl_button_on_change(0, 1); + if (!RSI_NPSSGPIO_GetPin(NPSS_GPIO_0) && gpio0) { + gpio0 = 0; + sl_button_on_change(0, BTN_PRESSED); } } diff --git a/matter/si91x/siwx917/BRD4325x/support/hal/rsi_hal_mcu_platform_init.c b/matter/si91x/siwx917/BRD4325x/support/hal/rsi_hal_mcu_platform_init.c index eeede73def..ad25308f7d 100644 --- a/matter/si91x/siwx917/BRD4325x/support/hal/rsi_hal_mcu_platform_init.c +++ b/matter/si91x/siwx917/BRD4325x/support/hal/rsi_hal_mcu_platform_init.c @@ -45,6 +45,16 @@ #define MISC_CONFIG_MISC_CTRL1 *(volatile uint32_t *)(0x46008000 + 0x44) #define MISC_QUASI_SYNC_MODE *(volatile uint32_t *)(0x46008000 + 0x84) + +/* for B0 2.0 board */ +#ifdef SI917_RADIO_BOARD_V2 +#include "rsi_rom_egpio.h" + +#define M4_GPIO_PORT 0 +#define M4_GPIO_PIN (11U) +#define PININT_NVIC_NAME EGPIO_PIN_7_IRQn +#define PIN_INT 7 +#endif /** * @fn void soc_pll_config() * @brief This function to configure clock for SiWx917 SoC (80MHz) @@ -138,6 +148,43 @@ void RSI_Wakeupsw_config(void) { NVIC_SetPriority(NPSS_TO_MCU_GPIO_INTR_IRQn, 7); } +// For B0 2.0 board BTN1 +#ifdef SI917_RADIO_BOARD_V2 +void RSI_Wakeupsw_config_gpio11(void) { + uint8_t pad_sel = 1; + + /*Enable clock for EGPIO module*/ + RSI_CLK_PeripheralClkEnable(M4CLK, EGPIO_CLK, ENABLE_STATIC_CLK); + + /*PAD selection*/ + for (pad_sel = 1; pad_sel < 34; pad_sel++) { + if (pad_sel != 9) { + RSI_EGPIO_PadSelectionEnable(pad_sel); + } + } + + RSI_EGPIO_SetDir(EGPIO, M4_GPIO_PORT, M4_GPIO_PIN, 1); + /*REN enable */ + RSI_EGPIO_PadReceiverEnable(M4_GPIO_PIN); + + /*Configure default GPIO mode(0) */ + RSI_EGPIO_SetPinMux(EGPIO, M4_GPIO_PORT, M4_GPIO_PIN, EGPIO_PIN_MUX_MODE0); + + /*Selects the pin interrupt for the GPIO*/ + RSI_EGPIO_PinIntSel(EGPIO, PIN_INT, M4_GPIO_PORT, M4_GPIO_PIN); + RSI_EGPIO_SetIntRiseEdgeEnable(EGPIO, PIN_INT); + RSI_EGPIO_SetIntFallEdgeEnable(EGPIO, PIN_INT); + + /*Unmask the interrupt*/ + RSI_EGPIO_IntUnMask(EGPIO, PIN_INT); + + /*NVIC enable */ + NVIC_EnableIRQ(PININT_NVIC_NAME); + NVIC_SetPriority(PININT_NVIC_NAME, 7); + RSI_EGPIO_IntUnMask(EGPIO, PIN_INT); +} +#endif // SI917_RADIO_BOARD_V2 + void RSI_Wakeupsw_config_gpio0(void) { /*Configure the NPSS GPIO mode to wake up */ RSI_NPSSGPIO_SetPinMux(NPSS_GPIO_0, NPSSGPIO_PIN_MUX_MODE2); From 2bacf2fabb1b3e592c30d0bf90df195a955565e9 Mon Sep 17 00:00:00 2001 From: "Restyled.io" Date: Mon, 28 Aug 2023 17:16:04 +0000 Subject: [PATCH 2/7] Restyled by clang-format --- .../BRD4325x/support/hal/rsi_hal_mcu_m4.c | 6 ++- .../support/hal/rsi_hal_mcu_platform_init.c | 47 +++++++++---------- 2 files changed, 27 insertions(+), 26 deletions(-) diff --git a/matter/si91x/siwx917/BRD4325x/support/hal/rsi_hal_mcu_m4.c b/matter/si91x/siwx917/BRD4325x/support/hal/rsi_hal_mcu_m4.c index 108e5514ff..229504c5f6 100644 --- a/matter/si91x/siwx917/BRD4325x/support/hal/rsi_hal_mcu_m4.c +++ b/matter/si91x/siwx917/BRD4325x/support/hal/rsi_hal_mcu_m4.c @@ -79,7 +79,9 @@ void IRQ059_Handler(void) { __asm__("nop;"); RSI_EGPIO_IntClr(EGPIO, PIN_INT, INTERRUPT_STATUS_CLR); - RSI_EGPIO_GetPin(EGPIO, M4_GPIO_PORT, M4_GPIO_PIN) ? sl_button_on_change(1, BTN_RELEASED) : sl_button_on_change(1, BTN_PRESSED); + RSI_EGPIO_GetPin(EGPIO, M4_GPIO_PORT, M4_GPIO_PIN) + ? sl_button_on_change(1, BTN_RELEASED) + : sl_button_on_change(1, BTN_PRESSED); } #endif // SI917_RADIO_BOARD_V2 @@ -97,7 +99,7 @@ void IRQ021_Handler(void) { sl_button_on_change(0, BTN_RELEASED); #else sl_button_on_change(1, BTN_RELEASED); -#endif //SI917_RADIO_BOARD_V2 +#endif // SI917_RADIO_BOARD_V2 } // geting the state of the gpio 2 pin and checking if the btn is already // pressed or not diff --git a/matter/si91x/siwx917/BRD4325x/support/hal/rsi_hal_mcu_platform_init.c b/matter/si91x/siwx917/BRD4325x/support/hal/rsi_hal_mcu_platform_init.c index ad25308f7d..497ce296da 100644 --- a/matter/si91x/siwx917/BRD4325x/support/hal/rsi_hal_mcu_platform_init.c +++ b/matter/si91x/siwx917/BRD4325x/support/hal/rsi_hal_mcu_platform_init.c @@ -45,7 +45,6 @@ #define MISC_CONFIG_MISC_CTRL1 *(volatile uint32_t *)(0x46008000 + 0x44) #define MISC_QUASI_SYNC_MODE *(volatile uint32_t *)(0x46008000 + 0x84) - /* for B0 2.0 board */ #ifdef SI917_RADIO_BOARD_V2 #include "rsi_rom_egpio.h" @@ -151,37 +150,37 @@ void RSI_Wakeupsw_config(void) { // For B0 2.0 board BTN1 #ifdef SI917_RADIO_BOARD_V2 void RSI_Wakeupsw_config_gpio11(void) { - uint8_t pad_sel = 1; + uint8_t pad_sel = 1; - /*Enable clock for EGPIO module*/ - RSI_CLK_PeripheralClkEnable(M4CLK, EGPIO_CLK, ENABLE_STATIC_CLK); + /*Enable clock for EGPIO module*/ + RSI_CLK_PeripheralClkEnable(M4CLK, EGPIO_CLK, ENABLE_STATIC_CLK); - /*PAD selection*/ - for (pad_sel = 1; pad_sel < 34; pad_sel++) { - if (pad_sel != 9) { - RSI_EGPIO_PadSelectionEnable(pad_sel); - } + /*PAD selection*/ + for (pad_sel = 1; pad_sel < 34; pad_sel++) { + if (pad_sel != 9) { + RSI_EGPIO_PadSelectionEnable(pad_sel); } + } - RSI_EGPIO_SetDir(EGPIO, M4_GPIO_PORT, M4_GPIO_PIN, 1); - /*REN enable */ - RSI_EGPIO_PadReceiverEnable(M4_GPIO_PIN); + RSI_EGPIO_SetDir(EGPIO, M4_GPIO_PORT, M4_GPIO_PIN, 1); + /*REN enable */ + RSI_EGPIO_PadReceiverEnable(M4_GPIO_PIN); - /*Configure default GPIO mode(0) */ - RSI_EGPIO_SetPinMux(EGPIO, M4_GPIO_PORT, M4_GPIO_PIN, EGPIO_PIN_MUX_MODE0); + /*Configure default GPIO mode(0) */ + RSI_EGPIO_SetPinMux(EGPIO, M4_GPIO_PORT, M4_GPIO_PIN, EGPIO_PIN_MUX_MODE0); - /*Selects the pin interrupt for the GPIO*/ - RSI_EGPIO_PinIntSel(EGPIO, PIN_INT, M4_GPIO_PORT, M4_GPIO_PIN); - RSI_EGPIO_SetIntRiseEdgeEnable(EGPIO, PIN_INT); - RSI_EGPIO_SetIntFallEdgeEnable(EGPIO, PIN_INT); + /*Selects the pin interrupt for the GPIO*/ + RSI_EGPIO_PinIntSel(EGPIO, PIN_INT, M4_GPIO_PORT, M4_GPIO_PIN); + RSI_EGPIO_SetIntRiseEdgeEnable(EGPIO, PIN_INT); + RSI_EGPIO_SetIntFallEdgeEnable(EGPIO, PIN_INT); - /*Unmask the interrupt*/ - RSI_EGPIO_IntUnMask(EGPIO, PIN_INT); + /*Unmask the interrupt*/ + RSI_EGPIO_IntUnMask(EGPIO, PIN_INT); - /*NVIC enable */ - NVIC_EnableIRQ(PININT_NVIC_NAME); - NVIC_SetPriority(PININT_NVIC_NAME, 7); - RSI_EGPIO_IntUnMask(EGPIO, PIN_INT); + /*NVIC enable */ + NVIC_EnableIRQ(PININT_NVIC_NAME); + NVIC_SetPriority(PININT_NVIC_NAME, 7); + RSI_EGPIO_IntUnMask(EGPIO, PIN_INT); } #endif // SI917_RADIO_BOARD_V2 From 395d9dc8823cd1155fde455b7b6a2c124a100e6e Mon Sep 17 00:00:00 2001 From: srningap Date: Tue, 29 Aug 2023 12:57:23 +0530 Subject: [PATCH 3/7] Updated pad selection for GPIO11 --- .../BRD4325x/support/hal/rsi_hal_mcu_platform_init.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/matter/si91x/siwx917/BRD4325x/support/hal/rsi_hal_mcu_platform_init.c b/matter/si91x/siwx917/BRD4325x/support/hal/rsi_hal_mcu_platform_init.c index 497ce296da..6168a2de60 100644 --- a/matter/si91x/siwx917/BRD4325x/support/hal/rsi_hal_mcu_platform_init.c +++ b/matter/si91x/siwx917/BRD4325x/support/hal/rsi_hal_mcu_platform_init.c @@ -150,17 +150,13 @@ void RSI_Wakeupsw_config(void) { // For B0 2.0 board BTN1 #ifdef SI917_RADIO_BOARD_V2 void RSI_Wakeupsw_config_gpio11(void) { - uint8_t pad_sel = 1; + uint8_t pad_select = 6; /*Enable clock for EGPIO module*/ RSI_CLK_PeripheralClkEnable(M4CLK, EGPIO_CLK, ENABLE_STATIC_CLK); /*PAD selection*/ - for (pad_sel = 1; pad_sel < 34; pad_sel++) { - if (pad_sel != 9) { - RSI_EGPIO_PadSelectionEnable(pad_sel); - } - } + RSI_EGPIO_PadSelectionEnable(pad_select); RSI_EGPIO_SetDir(EGPIO, M4_GPIO_PORT, M4_GPIO_PIN, 1); /*REN enable */ From 0e16dcc7b9c04f192a712044945f36fba29ed244 Mon Sep 17 00:00:00 2001 From: srningap Date: Mon, 4 Sep 2023 17:41:45 +0530 Subject: [PATCH 4/7] Added BRD4338A folder for 2.0 common flash board --- .../BRD4325x/support/hal/rsi_hal_mcu_m4.c | 62 +-- .../support/hal/rsi_hal_mcu_platform_init.c | 42 -- .../siwx917/BRD4338A/autogen/RTE_Components.h | 32 ++ .../BRD4338A/autogen/sl_component_catalog.h | 39 ++ .../BRD4338A/autogen/sl_event_handler.c | 43 ++ .../BRD4338A/autogen/sl_event_handler.h | 11 + .../BRD4338A/config/emlib_core_debug_config.h | 46 ++ .../BRD4338A/support/hal/rsi_hal_mcu_m4.c | 102 ++++ .../support/hal/rsi_hal_mcu_platform_init.c | 206 +++++++ .../BRD4338A/support/hal/rsi_hal_mcu_timer.c | 216 ++++++++ .../BRD4338A/support/inc/system_si917.h | 168 ++++++ .../support/src/startup_common_RS1xxxx.c | 514 ++++++++++++++++++ 12 files changed, 1391 insertions(+), 90 deletions(-) create mode 100644 matter/si91x/siwx917/BRD4338A/autogen/RTE_Components.h create mode 100644 matter/si91x/siwx917/BRD4338A/autogen/sl_component_catalog.h create mode 100644 matter/si91x/siwx917/BRD4338A/autogen/sl_event_handler.c create mode 100644 matter/si91x/siwx917/BRD4338A/autogen/sl_event_handler.h create mode 100644 matter/si91x/siwx917/BRD4338A/config/emlib_core_debug_config.h create mode 100644 matter/si91x/siwx917/BRD4338A/support/hal/rsi_hal_mcu_m4.c create mode 100644 matter/si91x/siwx917/BRD4338A/support/hal/rsi_hal_mcu_platform_init.c create mode 100644 matter/si91x/siwx917/BRD4338A/support/hal/rsi_hal_mcu_timer.c create mode 100644 matter/si91x/siwx917/BRD4338A/support/inc/system_si917.h create mode 100644 matter/si91x/siwx917/BRD4338A/support/src/startup_common_RS1xxxx.c diff --git a/matter/si91x/siwx917/BRD4325x/support/hal/rsi_hal_mcu_m4.c b/matter/si91x/siwx917/BRD4325x/support/hal/rsi_hal_mcu_m4.c index 229504c5f6..5cf849a50a 100644 --- a/matter/si91x/siwx917/BRD4325x/support/hal/rsi_hal_mcu_m4.c +++ b/matter/si91x/siwx917/BRD4325x/support/hal/rsi_hal_mcu_m4.c @@ -22,21 +22,8 @@ #include "rsi_power_save.h" #endif -#define BTN_RELEASED 0 -#define BTN_PRESSED 1 - -#ifdef SI917_RADIO_BOARD_V2 -#define PIN_INT 7 -#ifndef M4_GPIO_PORT -#define M4_GPIO_PORT 0 -#endif -#ifndef M4_GPIO_PIN -#define M4_GPIO_PIN (11U) -#endif -#endif // SI917_RADIO_BOARD_V2 - -uint8_t gpio0 = 1; -uint8_t gpio2 = 1; +uint8_t btn0 = 1; +uint8_t btn1 = 1; void sl_button_on_change(uint8_t btn, uint8_t btnAction); @@ -72,19 +59,6 @@ void rsi_assertion(uint16_t assertion_val, const char *string) { } } -#if SI917_RADIO_BOARD_V2 -void IRQ059_Handler(void) { - // TODO: Replace with rsi_delay once that is fixed - for (int i = 0; i < 10000; i++) - __asm__("nop;"); - - RSI_EGPIO_IntClr(EGPIO, PIN_INT, INTERRUPT_STATUS_CLR); - RSI_EGPIO_GetPin(EGPIO, M4_GPIO_PORT, M4_GPIO_PIN) - ? sl_button_on_change(1, BTN_RELEASED) - : sl_button_on_change(1, BTN_PRESSED); -} -#endif // SI917_RADIO_BOARD_V2 - void IRQ021_Handler(void) { // TODO: Replace with rsi_delay once that is fixed for (int i = 0; i < 10000; i++) @@ -93,30 +67,22 @@ void IRQ021_Handler(void) { RSI_NPSSGPIO_ClrIntr(NPSS_GPIO_0_INTR); RSI_NPSSGPIO_ClrIntr(NPSS_GPIO_2_INTR); // if the btn is not pressed setting the state to 1 - if (RSI_NPSSGPIO_GetPin(NPSS_GPIO_2) && (!gpio2)) { - gpio2 = 1; -#ifdef SI917_RADIO_BOARD_V2 - sl_button_on_change(0, BTN_RELEASED); -#else - sl_button_on_change(1, BTN_RELEASED); -#endif // SI917_RADIO_BOARD_V2 + if (RSI_NPSSGPIO_GetPin(NPSS_GPIO_2) && (!btn1)) { + btn1 = 1; + sl_button_on_change(1, 0); } // geting the state of the gpio 2 pin and checking if the btn is already // pressed or not - if (!RSI_NPSSGPIO_GetPin(NPSS_GPIO_2) && gpio2) { - gpio2 = 0; -#ifdef SI917_RADIO_BOARD_V2 - sl_button_on_change(0, BTN_PRESSED); -#else - sl_button_on_change(1, BTN_PRESSED); -#endif // SI917_RADIO_BOARD_V2 + if (!RSI_NPSSGPIO_GetPin(NPSS_GPIO_2) && btn1) { + btn1 = 0; + sl_button_on_change(1, 1); } - if (RSI_NPSSGPIO_GetPin(NPSS_GPIO_0) && (!gpio0)) { - gpio0 = 1; - sl_button_on_change(0, BTN_RELEASED); + if (RSI_NPSSGPIO_GetPin(NPSS_GPIO_0) && (!btn0)) { + btn0 = 1; + sl_button_on_change(0, 0); } - if (!RSI_NPSSGPIO_GetPin(NPSS_GPIO_0) && gpio0) { - gpio0 = 0; - sl_button_on_change(0, BTN_PRESSED); + if (!RSI_NPSSGPIO_GetPin(NPSS_GPIO_0) && btn0) { + btn0 = 0; + sl_button_on_change(0, 1); } } diff --git a/matter/si91x/siwx917/BRD4325x/support/hal/rsi_hal_mcu_platform_init.c b/matter/si91x/siwx917/BRD4325x/support/hal/rsi_hal_mcu_platform_init.c index 6168a2de60..eeede73def 100644 --- a/matter/si91x/siwx917/BRD4325x/support/hal/rsi_hal_mcu_platform_init.c +++ b/matter/si91x/siwx917/BRD4325x/support/hal/rsi_hal_mcu_platform_init.c @@ -45,15 +45,6 @@ #define MISC_CONFIG_MISC_CTRL1 *(volatile uint32_t *)(0x46008000 + 0x44) #define MISC_QUASI_SYNC_MODE *(volatile uint32_t *)(0x46008000 + 0x84) -/* for B0 2.0 board */ -#ifdef SI917_RADIO_BOARD_V2 -#include "rsi_rom_egpio.h" - -#define M4_GPIO_PORT 0 -#define M4_GPIO_PIN (11U) -#define PININT_NVIC_NAME EGPIO_PIN_7_IRQn -#define PIN_INT 7 -#endif /** * @fn void soc_pll_config() * @brief This function to configure clock for SiWx917 SoC (80MHz) @@ -147,39 +138,6 @@ void RSI_Wakeupsw_config(void) { NVIC_SetPriority(NPSS_TO_MCU_GPIO_INTR_IRQn, 7); } -// For B0 2.0 board BTN1 -#ifdef SI917_RADIO_BOARD_V2 -void RSI_Wakeupsw_config_gpio11(void) { - uint8_t pad_select = 6; - - /*Enable clock for EGPIO module*/ - RSI_CLK_PeripheralClkEnable(M4CLK, EGPIO_CLK, ENABLE_STATIC_CLK); - - /*PAD selection*/ - RSI_EGPIO_PadSelectionEnable(pad_select); - - RSI_EGPIO_SetDir(EGPIO, M4_GPIO_PORT, M4_GPIO_PIN, 1); - /*REN enable */ - RSI_EGPIO_PadReceiverEnable(M4_GPIO_PIN); - - /*Configure default GPIO mode(0) */ - RSI_EGPIO_SetPinMux(EGPIO, M4_GPIO_PORT, M4_GPIO_PIN, EGPIO_PIN_MUX_MODE0); - - /*Selects the pin interrupt for the GPIO*/ - RSI_EGPIO_PinIntSel(EGPIO, PIN_INT, M4_GPIO_PORT, M4_GPIO_PIN); - RSI_EGPIO_SetIntRiseEdgeEnable(EGPIO, PIN_INT); - RSI_EGPIO_SetIntFallEdgeEnable(EGPIO, PIN_INT); - - /*Unmask the interrupt*/ - RSI_EGPIO_IntUnMask(EGPIO, PIN_INT); - - /*NVIC enable */ - NVIC_EnableIRQ(PININT_NVIC_NAME); - NVIC_SetPriority(PININT_NVIC_NAME, 7); - RSI_EGPIO_IntUnMask(EGPIO, PIN_INT); -} -#endif // SI917_RADIO_BOARD_V2 - void RSI_Wakeupsw_config_gpio0(void) { /*Configure the NPSS GPIO mode to wake up */ RSI_NPSSGPIO_SetPinMux(NPSS_GPIO_0, NPSSGPIO_PIN_MUX_MODE2); diff --git a/matter/si91x/siwx917/BRD4338A/autogen/RTE_Components.h b/matter/si91x/siwx917/BRD4338A/autogen/RTE_Components.h new file mode 100644 index 0000000000..f4ff113e8f --- /dev/null +++ b/matter/si91x/siwx917/BRD4338A/autogen/RTE_Components.h @@ -0,0 +1,32 @@ +// This file is autogenerated by Simplicity Configuration Tools. +// The contents of this file will be replaced in their entirety upon regeneration. +// +// Source template file: RTE_Components.h.jinja + + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + +/* standard device header from emlib */ +#define CMSIS_device_header "em_device.h" + +/* components are auto-generated here */ + +#define RTE_RTOS_FreeRTOS_CORE + +#define RTE_RTOS_FreeRTOS_CONFIG_RTOS2 + +#define RTE_RTOS_FreeRTOS_COROUTINE + +#define RTE_RTOS_FreeRTOS_EVENTGROUPS + +#define RTE_RTOS_FreeRTOS_TIMERS + + +#endif /* RTE_COMPONENTS_H */ + +/* This file is autogenerated by Simplicity Configuration Tools. */ +/* The contents of this file will be replaced in their entirety upon regeneration. */ +/* */ +/* Source template file: RTE_Components.h.jinja */ + diff --git a/matter/si91x/siwx917/BRD4338A/autogen/sl_component_catalog.h b/matter/si91x/siwx917/BRD4338A/autogen/sl_component_catalog.h new file mode 100644 index 0000000000..e782eccb43 --- /dev/null +++ b/matter/si91x/siwx917/BRD4338A/autogen/sl_component_catalog.h @@ -0,0 +1,39 @@ +#ifndef SL_COMPONENT_CATALOG_H +#define SL_COMPONENT_CATALOG_H + +// APIs present in project +#define SL_CATALOG_MATTER_ACCESS_CONTROL_PRESENT +#define SL_CATALOG_MATTER_ADMINISTRATOR_COMMISSIONING_PRESENT +#define SL_CATALOG_MATTER_BASIC_PRESENT +#define SL_CATALOG_MATTER_COLOR_CONTROL_PRESENT +#define SL_CATALOG_MATTER_DESCRIPTOR_PRESENT +#define SL_CATALOG_MATTER_DIAGNOSTIC_LOGS_PRESENT +#define SL_CATALOG_MATTER_ETHERNET_NETWORK_DIAGNOSTICS_PRESENT +#define SL_CATALOG_MATTER_FIXED_LABEL_PRESENT +#define SL_CATALOG_MATTER_GENERAL_COMMISSIONING_PRESENT +#define SL_CATALOG_MATTER_GENERAL_DIAGNOSTICS_PRESENT +#define SL_CATALOG_MATTER_GROUP_KEY_MGMT_PRESENT +#define SL_CATALOG_MATTER_GROUPS_PRESENT +#define SL_CATALOG_MATTER_IDENTIFY_PRESENT +#define SL_CATALOG_MATTER_LEVEL_CONTROL_PRESENT +#define SL_CATALOG_MATTER_LOCALIZATION_CONFIGURATION_PRESENT +#define SL_CATALOG_MATTER_NETWORK_COMMISSIONING_PRESENT +#define SL_CATALOG_MATTER_OCCUPANCY_SENSOR_PRESENT +#define SL_CATALOG_MATTER_ON_OFF_PRESENT +#define SL_CATALOG_MATTER_OPERATIONAL_CREDENTIALS_PRESENT +#define SL_CATALOG_MATTER_OTA_REQUESTOR_PRESENT +#define SL_CATALOG_MATTER_SOFTWARE_DIAGNOSTICS_PRESENT +#define SL_CATALOG_MATTER_SWITCH_PRESENT +#define SL_CATALOG_MATTER_THREAD_NETWORK_DIAGNOSTICS_PRESENT +#define SL_CATALOG_MATTER_TIME_FORMAT_LOCALIZATION_PRESENT +#define SL_CATALOG_MATTER_USER_LABEL_PRESENT +#define SL_CATALOG_MATTER_BLE_PRESENT +#define SL_CATALOG_MATTER_WIFI_NETWORK_DIAGNOSTICS_PRESENT +#define SL_CATALOG_CMSIS_OS_COMMON_PRESENT +#define SL_CATALOG_DEVICE_INIT_NVIC_PRESENT +#define SL_CATALOG_EMLIB_CORE_PRESENT +#define SL_CATALOG_EMLIB_CORE_DEBUG_CONFIG_PRESENT +#define SL_CATALOG_FREERTOS_KERNEL_PRESENT +#define SL_CATALOG_KERNEL_PRESENT + +#endif // SL_COMPONENT_CATALOG_H diff --git a/matter/si91x/siwx917/BRD4338A/autogen/sl_event_handler.c b/matter/si91x/siwx917/BRD4338A/autogen/sl_event_handler.c new file mode 100644 index 0000000000..4f7f400898 --- /dev/null +++ b/matter/si91x/siwx917/BRD4338A/autogen/sl_event_handler.c @@ -0,0 +1,43 @@ +#include "sl_event_handler.h" + +#include "rsi_chip.h" +#include "rsi_nvic_priorities_config.h" +#include "sl_device_init_nvic.h" +#include "sli_siwx917_soc.h" +#include "rsi_board.h" +#include "rsi_wisemcu_hardware_setup.h" +#include "cmsis_os2.h" + +void sl_platform_init(void) +{ + SystemCoreClockUpdate(); + sl_si91x_device_init_nvic(); + sl_device_init_nvic(); + sli_si91x_platform_init(); + RSI_Board_Init(); + sl_si91x_hardware_setup(); + osKernelInitialize(); +} + +void sl_kernel_start(void) +{ + osKernelStart(); +} + +void sl_driver_init(void) +{ +} + +void sl_service_init(void) +{ + DEBUGINIT(); +} + +void sl_stack_init(void) +{ +} + +void sl_internal_app_init(void) +{ +} + diff --git a/matter/si91x/siwx917/BRD4338A/autogen/sl_event_handler.h b/matter/si91x/siwx917/BRD4338A/autogen/sl_event_handler.h new file mode 100644 index 0000000000..e12b2e3cde --- /dev/null +++ b/matter/si91x/siwx917/BRD4338A/autogen/sl_event_handler.h @@ -0,0 +1,11 @@ +#ifndef SL_EVENT_HANDLER_H +#define SL_EVENT_HANDLER_H + +void sl_platform_init(void); +void sl_kernel_start(void); +void sl_driver_init(void); +void sl_service_init(void); +void sl_stack_init(void); +void sl_internal_app_init(void); + +#endif // SL_EVENT_HANDLER_H diff --git a/matter/si91x/siwx917/BRD4338A/config/emlib_core_debug_config.h b/matter/si91x/siwx917/BRD4338A/config/emlib_core_debug_config.h new file mode 100644 index 0000000000..8316d3fc67 --- /dev/null +++ b/matter/si91x/siwx917/BRD4338A/config/emlib_core_debug_config.h @@ -0,0 +1,46 @@ +/***************************************************************************//** + * @file + * @brief emlib_core Configuration + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_CORE_DEBUG_CONFIG_H +#define EM_CORE_DEBUG_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Core Configuration + +// Enables measuring of interrupt disable time for debugging purposes. +// Default: 0 +// If Enabled, either cycle_counter or systemview component must be added to project. +#define SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING 0 + +// + +// <<< end of configuration section >>> +#endif // EM_CORE_CONFIG_H diff --git a/matter/si91x/siwx917/BRD4338A/support/hal/rsi_hal_mcu_m4.c b/matter/si91x/siwx917/BRD4338A/support/hal/rsi_hal_mcu_m4.c new file mode 100644 index 0000000000..6e4b5e760a --- /dev/null +++ b/matter/si91x/siwx917/BRD4338A/support/hal/rsi_hal_mcu_m4.c @@ -0,0 +1,102 @@ +/* + * + * Copyright (c) 2022 Project CHIP Authors + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "rsi_board.h" +#include "rsi_chip.h" +#include "rsi_m4.h" +#ifdef COMMON_FLASH_EN +#include "rsi_power_save.h" +#endif + +#define BTN_RELEASED 0 +#define BTN_PRESSED 1 + +#define PIN_INT 7 +#ifndef M4_GPIO_PORT +#define M4_GPIO_PORT 0 +#endif +#ifndef M4_GPIO_PIN +#define M4_GPIO_PIN (11U) +#endif + +uint8_t gpio0 = 1; +uint8_t btn0 = 1; + +void sl_button_on_change(uint8_t btn, uint8_t btnAction); + +uint32_t NVIC_GetIRQEnable(IRQn_Type IRQn) { + return ((NVIC->ICER[((uint32_t)(IRQn) >> 5)] & (1 << ((uint32_t)(IRQn)&0x1F))) + ? 1 + : 0); +} + +void rsi_assertion(uint16_t assertion_val, const char *string) { + uint16_t i; + if (assertion_val == 0) { + for (i = 0; i < strlen(string); i++) { +#ifdef DEBUG_UART +#ifdef DEBUG_ASSERTION + Board_UARTPutChar(string[i]); +#endif +#endif + } + + return; + } else { + for (i = 0; i < strlen(string); i++) { +#ifdef DEBUG_UART +#ifdef DEBUG_ASSERTION + Board_UARTPutChar(string[i]); +#endif +#endif + } + + while (1) + ; + } +} + +void IRQ059_Handler(void) { + // TODO: Replace with rsi_delay once that is fixed + for (int i = 0; i < 10000; i++) + __asm__("nop;"); + + RSI_EGPIO_IntClr(EGPIO, PIN_INT, INTERRUPT_STATUS_CLR); + RSI_EGPIO_GetPin(EGPIO, M4_GPIO_PORT, M4_GPIO_PIN) + ? sl_button_on_change(1, BTN_RELEASED) + : sl_button_on_change(1, BTN_PRESSED); +} + +void IRQ021_Handler(void) { + // TODO: Replace with rsi_delay once that is fixed + for (int i = 0; i < 10000; i++) + __asm__("nop;"); + /* clear NPSS GPIO interrupt*/ + RSI_NPSSGPIO_ClrIntr(NPSS_GPIO_0_INTR); + RSI_NPSSGPIO_ClrIntr(NPSS_GPIO_2_INTR); + // if the btn is not pressed setting the state to 1 + if (RSI_NPSSGPIO_GetPin(NPSS_GPIO_2) && (!btn0)) { + btn0 = 1; + sl_button_on_change(0, BTN_RELEASED); + } + // geting the state of the gpio 2 pin and checking if the btn is already + // pressed or not + if (!RSI_NPSSGPIO_GetPin(NPSS_GPIO_2) && btn0) { + btn0 = 0; + sl_button_on_change(0, BTN_PRESSED); + } +} diff --git a/matter/si91x/siwx917/BRD4338A/support/hal/rsi_hal_mcu_platform_init.c b/matter/si91x/siwx917/BRD4338A/support/hal/rsi_hal_mcu_platform_init.c new file mode 100644 index 0000000000..daa6af0638 --- /dev/null +++ b/matter/si91x/siwx917/BRD4338A/support/hal/rsi_hal_mcu_platform_init.c @@ -0,0 +1,206 @@ +/* + * + * Copyright (c) 2022 Project CHIP Authors + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + * Includes + */ +#include "rsi_board.h" +#include "rsi_pll.h" +#include "rsi_rom_clks.h" +#include "silabs_utils.h" +#include "sli_siwx917_soc.h" +#include "rsi_rom_egpio.h" + +#define SOC_PLL_REF_FREQUENCY 32000000 /* PLL input REFERENCE clock 32MHZ */ + +// Note: Change this macro to required PLL frequency in hertz +#define PS4_SOC_FREQ 180000000 /* PLL out clock 180MHz */ +#define SWITCH_QSPI_TO_SOC_PLL +#define ICACHE_DISABLE +#define DEBUG_DISABLE + +/* QSPI clock config params */ +#define INTF_PLL_500_CTRL_VALUE 0xD900 +#define INTF_PLL_CLK 80000000 /* PLL out clock 80 MHz */ + +#define PMU_GOOD_TIME 31 /*Duration in us*/ +#define XTAL_GOOD_TIME 31 /*Duration in us*/ + +/*Pre-fetch and regestring */ +#define ICACHE2_ADDR_TRANSLATE_1_REG *(volatile uint32_t *)(0x20280000 + 0x24) +#define MISC_CFG_SRAM_REDUNDANCY_CTRL *(volatile uint32_t *)(0x46008000 + 0x18) +#define MISC_CONFIG_MISC_CTRL1 *(volatile uint32_t *)(0x46008000 + 0x44) +#define MISC_QUASI_SYNC_MODE *(volatile uint32_t *)(0x46008000 + 0x84) + +/* BTN1 defines */ +#define M4_GPIO_PORT 0 +#define M4_GPIO_PIN (11U) +#define PININT_NVIC_NAME EGPIO_PIN_7_IRQn +#define PIN_INT 7 + +/** + * @fn void soc_pll_config() + * @brief This function to configure clock for SiWx917 SoC (80MHz) + * Configure the PLL frequency and Switch M4 clock to PLL clock + * for speed operations + * + * @param[in] none + * @param[out] none + * @return int + * @section description + * configure clock for SiWx917 SoC + * + */ +int soc_pll_config(void) { + int32_t status = RSI_OK; + + RSI_CLK_SocPllLockConfig(1, 1, 7); + + RSI_CLK_SocPllRefClkConfig(2); + + RSI_CLK_M4SocClkConfig(M4CLK, M4_ULPREFCLK, 0); + + /*Enable fre-fetch and register if SOC-PLL frequency is more than or equal to + * 120M*/ +#if (PS4_SOC_FREQ >= 120000000) + ICACHE2_ADDR_TRANSLATE_1_REG = BIT(21); + MISC_CFG_SRAM_REDUNDANCY_CTRL = BIT(4); + MISC_CONFIG_MISC_CTRL1 |= BIT(4); +#if !(defined WISE_AOC_4) + MISC_QUASI_SYNC_MODE |= BIT(6); + MISC_QUASI_SYNC_MODE |= (BIT(6) | BIT(7)); +#endif /* !WISE_AOC_4 */ +#endif /* (PS4_SOC_FREQ > 120000000) */ + + RSI_CLK_SetSocPllFreq(M4CLK, PS4_SOC_FREQ, SOC_PLL_REF_FREQUENCY); + + RSI_CLK_M4SocClkConfig(M4CLK, M4_SOCPLLCLK, 0); + +#ifdef SWITCH_QSPI_TO_SOC_PLL + /* program intf pll to 160Mhz */ + SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG9) = INTF_PLL_500_CTRL_VALUE; + status = RSI_CLK_SetIntfPllFreq(M4CLK, INTF_PLL_CLK, SOC_PLL_REF_FREQUENCY); + if (status != RSI_OK) { + SILABS_LOG("Failed to Config Interface PLL Clock, status:%d", status); + } else { + SILABS_LOG("Configured Interface PLL Clock to %d", INTF_PLL_CLK); + } + + RSI_CLK_QspiClkConfig(M4CLK, QSPI_INTFPLLCLK, 0, 0, 1); +#endif /* SWITCH_QSPI_TO_SOC_PLL */ + + return 0; +} + +/*==============================================*/ +/** + * @fn void RSI_Wakeupsw_config() + * @brief This function Initializes the platform + * @param[in] none + * @param[out] none + * @return none + * @section description + * This function initializes the platform + * + */ +void RSI_Wakeupsw_config(void) { + /*Enable the REN*/ + RSI_NPSSGPIO_InputBufferEn(NPSS_GPIO_2, 1); + + /*Configure the NPSS GPIO mode to wake up */ + RSI_NPSSGPIO_SetPinMux(NPSS_GPIO_2, NPSSGPIO_PIN_MUX_MODE2); + + /*Configure the NPSS GPIO direction to input */ + RSI_NPSSGPIO_SetDir(NPSS_GPIO_2, NPSS_GPIO_DIR_OUTPUT); + + /* Enables fall edge interrupt detection for UULP_VBAT_GPIO_0 */ + RSI_NPSSGPIO_SetIntFallEdgeEnable(NPSS_GPIO_2_INTR); + + /* Un mask the NPSS GPIO interrupt*/ + RSI_NPSSGPIO_IntrUnMask(NPSS_GPIO_2_INTR); + + /*Select wake up sources */ + RSI_PS_SetWkpSources(GPIO_BASED_WAKEUP); + + /* clear NPSS GPIO interrupt*/ + RSI_NPSSGPIO_ClrIntr(NPSS_GPIO_2_INTR); + + /*Enable the NPSS GPIO interrupt slot*/ + NVIC_EnableIRQ(NPSS_TO_MCU_GPIO_INTR_IRQn); + + NVIC_SetPriority(NPSS_TO_MCU_GPIO_INTR_IRQn, 7); +} + +void RSI_Wakeupsw_config_gpio11(void) { + uint8_t pad_select = 6; + + /*Enable clock for EGPIO module*/ + RSI_CLK_PeripheralClkEnable(M4CLK, EGPIO_CLK, ENABLE_STATIC_CLK); + + /*PAD selection*/ + RSI_EGPIO_PadSelectionEnable(pad_select); + + RSI_EGPIO_SetDir(EGPIO, M4_GPIO_PORT, M4_GPIO_PIN, 1); + /*REN enable */ + RSI_EGPIO_PadReceiverEnable(M4_GPIO_PIN); + + /*Configure default GPIO mode(0) */ + RSI_EGPIO_SetPinMux(EGPIO, M4_GPIO_PORT, M4_GPIO_PIN, EGPIO_PIN_MUX_MODE0); + + /*Selects the pin interrupt for the GPIO*/ + RSI_EGPIO_PinIntSel(EGPIO, PIN_INT, M4_GPIO_PORT, M4_GPIO_PIN); + RSI_EGPIO_SetIntRiseEdgeEnable(EGPIO, PIN_INT); + RSI_EGPIO_SetIntFallEdgeEnable(EGPIO, PIN_INT); + + /*Unmask the interrupt*/ + RSI_EGPIO_IntUnMask(EGPIO, PIN_INT); + + /*NVIC enable */ + NVIC_EnableIRQ(PININT_NVIC_NAME); + NVIC_SetPriority(PININT_NVIC_NAME, 7); + RSI_EGPIO_IntUnMask(EGPIO, PIN_INT); +} + +/*==============================================*/ +/** + * @fn void rsi_hal_board_init() + * @brief This function Initializes the platform + * @param[in] none + * @param[out] none + * @return none + * @section description + * This function initializes the platform + * + */ +void rsi_hal_board_init(void) { + SystemCoreClockUpdate(); + + // initialize the LED pins + RSI_Board_Init(); + + /* configure clock for SiWx917 SoC */ + soc_pll_config(); + +#ifdef COMMON_FLASH_EN + /* Before TA going to power save mode ,set m4ss_ref_clk_mux_ctrl + ,tass_ref_clk_mux_ctrl, AON domain power supply controls form TA to M4 */ + RSI_Set_Cntrls_To_M4(); +#endif +#ifdef DEBUG_UART + DEBUGINIT(); +#endif +} diff --git a/matter/si91x/siwx917/BRD4338A/support/hal/rsi_hal_mcu_timer.c b/matter/si91x/siwx917/BRD4338A/support/hal/rsi_hal_mcu_timer.c new file mode 100644 index 0000000000..9db8c6562c --- /dev/null +++ b/matter/si91x/siwx917/BRD4338A/support/hal/rsi_hal_mcu_timer.c @@ -0,0 +1,216 @@ +/* + * + * Copyright (c) 2022 Project CHIP Authors + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + * Includes + */ + +#include "rsi_driver.h" +#ifdef RSI_WITH_OS +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "stack_macros.h" +#include "task.h" +#include "timers.h" + +#if defined(SysTick) +#undef SysTick_Handler +/* FreeRTOS SysTick interrupt handler prototype */ +extern void SysTick_Handler(void); +/* FreeRTOS tick timer interrupt handler prototype */ +extern void xPortSysTickHandler(void); +#endif /* SysTick */ +#endif + +static volatile uint32_t _dwTickCount; // systick cout variable + +/*===================================================*/ +/** + * @fn int32_t rsi_timer_start(uint8_t timer_no, uint8_t mode,uint8_t + * type,uint32_t duration,void (* rsi_timer_expiry_handler)()) + * @brief Starts and configures timer + * @param[in] timer_node, timer node to be configured. + * @param[in] mode , mode of the timer + * 0 - Micro seconds mode + * 1 - Milli seconds mode + * @param[in] type, type of the timer + * 0 - single shot type + * 1 - periodic type + * @param[in] duration, timer duration + * @param[in] rsi_timer_expiry_handler() ,call back function to handle timer + * interrupt + * @param[out] none + * @return 0 - success + * !0 - Failure + * @description This HAL API should contain the code to initialize the timer + * and start the timer + * + */ + +int32_t rsi_timer_start(uint8_t timer_node, uint8_t mode, uint8_t type, + uint32_t duration, + void (*rsi_timer_expiry_handler)(void)) { + + //! Initialise the timer + + //! register the call back + + //! Start timer + + return 0; +} + +/*===================================================*/ +/** + * @fn int32_t rsi_timer_stop(uint8_t timer_no) + * @brief Stops timer + * @param[in] timer_node, timer node to stop + * @param[out] none + * @return 0 - success + * !0 - Failure + * @description This HAL API should contain the code to stop the timer + * + */ + +int32_t rsi_timer_stop(uint8_t timer_node) { + + //! Stop the timer + + return 0; +} + +/*===================================================*/ +/** + * @fn uint32_t rsi_timer_read(uint8_t timer_node) + * @brief read timer + * @param[in] timer_node, timer node to read + * @param[out] none + * @return timer value + * @description This HAL API should contain API to read the timer + * + */ + +uint32_t rsi_timer_read(uint8_t timer_node) { + + volatile uint32_t timer_val = 0; + + //! read the timer and return timer value + + return timer_val; +} + +/*===================================================*/ +/** + * @fn void rsi_delay_us(uint32_t delay) + * @brief create delay in micro seconds + * @param[in] delay_us, timer delay in micro seconds + * @param[out] none + * @return none + * @description This HAL API should contain the code to create delay in micro + * seconds + * + */ +void rsi_delay_us(uint32_t delay_us) { + + //! call the API for delay in micro seconds + + return; +} + +/*===================================================*/ +/** + * @fn void rsi_delay_ms(uint32_t delay) + * @brief create delay in micro seconds + * @param[in] delay, timer delay in micro seconds + * @param[out] none + * @return none + * @description This HAL API should contain the code to create delay in micro + * seconds + * + */ +void rsi_delay_ms1(uint32_t delay_ms) { + + //! call the API for delay in milli seconds + + return; +} + +/*===================================================*/ +/** + * @fn void SysTick_Handler(void); + * @brief systick cout variable + * @param[in] none + * @param[out] none + * @return none + * @description This HAL API is systick cout variable + * + */ + +void SysTick_Handler(void) { + _dwTickCount++; +#ifdef RSI_WITH_OS + if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) { + xPortSysTickHandler(); + } +#endif +} +/*===================================================*/ +/** + * @fn uint32_t GetTickCount( void ) + * @brief gets the tick count from systic ISR + * @param[in] delay, timer delay in micro seconds + * @param[out] none + * @return Returns the systick current tick count + * @description This HAL API gets the tick count from systic ISR + * + */ + +uint32_t GetTickCount(void) { + return _dwTickCount; // gets the tick count from systic ISR +} + +/*===================================================*/ +/** + * @fn void rsi_delay_ms(uint32_t delay) + * @brief create delay in milli seconds + * @param[in] delay, timer delay in milli seconds + * @param[out] none + * @return none + * @description This HAL API should contain the code to create delay in milli + * seconds + * + */ + +void rsi_delay_ms(uint32_t delay_ms) { + uint64_t waitTime = rsi_hal_gettickcount() + delay_ms; + + while (waitTime > rsi_hal_gettickcount()) { + // we busy wait + } +} + +/*===================================================*/ +/** + * @fn uint32_t rsi_hal_gettickcount() + * @brief provides a tick value in milliseconds + * @return tick value + * @description This HAL API should contain the code to read the timer tick + * count value in milliseconds + * + */ + +uint32_t rsi_hal_gettickcount(void) { return GetTickCount(); } diff --git a/matter/si91x/siwx917/BRD4338A/support/inc/system_si917.h b/matter/si91x/siwx917/BRD4338A/support/inc/system_si917.h new file mode 100644 index 0000000000..d373eb283a --- /dev/null +++ b/matter/si91x/siwx917/BRD4338A/support/inc/system_si917.h @@ -0,0 +1,168 @@ +/* + * + * Copyright (c) 2022 Project CHIP Authors + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +// system header +#include "si91x_device.h" +// Processor spefic haeders +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include + +// CMSIS GCC header +#include "cmsis_gcc.h" + +/******************************************************************************* + * @addtogroup Parts + * @{ + ******************************************************************************/ +/******************************************************************************* + * @addtogroup EFR32 EFR32 + * @{ + ******************************************************************************/ + +/******************************************************************************* + ****************************** TYPEDEFS *********************************** + ******************************************************************************/ + +/* Interrupt vectortable entry */ +typedef union { + void (*VECTOR_TABLE_Type)(void); + void *topOfStack; +} tVectorEntry; + +/******************************************************************************* + ************************** GLOBAL VARIABLES ******************************* + ******************************************************************************/ +//#ifndef CCP_SI917_BRINGUP +extern uint32_t SystemCoreClock; /**< System Clock Frequency (Core Clock) */ +//#endif /* CCP_SI917_BRINGUP */ +extern uint32_t SystemHfrcoFreq; /**< System HFRCO frequency */ + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +void Reset_Handler(void); /**< Reset Handler */ +void NMI_Handler(void); /**< NMI Handler */ +void HardFault_Handler(void); /**< Hard Fault Handler */ +void MemManage_Handler(void); /**< MPU Fault Handler */ +void BusFault_Handler(void); /**< Bus Fault Handler */ +void UsageFault_Handler(void); /**< Usage Fault Handler */ +void SVC_Handler(void); /**< SVCall Handler */ +void DebugMon_Handler(void); /**< Debug Monitor Handler */ +void PendSV_Handler(void); /**< PendSV Handler */ +void SysTick_Handler(void); /**< SysTick Handler */ + +void EMU_IRQHandler(void); /**< EMU IRQ Handler */ +void FRC_PRI_IRQHandler(void); /**< FRC_PRI IRQ Handler */ +void WDOG0_IRQHandler(void); /**< WDOG0 IRQ Handler */ +void WDOG1_IRQHandler(void); /**< WDOG1 IRQ Handler */ +void FRC_IRQHandler(void); /**< FRC IRQ Handler */ +void MODEM_IRQHandler(void); /**< MODEM IRQ Handler */ +void RAC_SEQ_IRQHandler(void); /**< RAC_SEQ IRQ Handler */ +void RAC_RSM_IRQHandler(void); /**< RAC_RSM IRQ Handler */ +void BUFC_IRQHandler(void); /**< BUFC IRQ Handler */ +void LDMA_IRQHandler(void); /**< LDMA IRQ Handler */ +void GPIO_EVEN_IRQHandler(void); /**< GPIO_EVEN IRQ Handler */ +void TIMER0_IRQHandler(void); /**< TIMER0 IRQ Handler */ +void USART0_RX_IRQHandler(void); /**< USART0_RX IRQ Handler */ +void USART0_TX_IRQHandler(void); /**< USART0_TX IRQ Handler */ +void ACMP0_IRQHandler(void); /**< ACMP0 IRQ Handler */ +void ADC0_IRQHandler(void); /**< ADC0 IRQ Handler */ +void IDAC0_IRQHandler(void); /**< IDAC0 IRQ Handler */ +void I2C0_IRQHandler(void); /**< I2C0 IRQ Handler */ +void GPIO_ODD_IRQHandler(void); /**< GPIO_ODD IRQ Handler */ +void TIMER1_IRQHandler(void); /**< TIMER1 IRQ Handler */ +void USART1_RX_IRQHandler(void); /**< USART1_RX IRQ Handler */ +void USART1_TX_IRQHandler(void); /**< USART1_TX IRQ Handler */ +void LEUART0_IRQHandler(void); /**< LEUART0 IRQ Handler */ +void PCNT0_IRQHandler(void); /**< PCNT0 IRQ Handler */ +void CMU_IRQHandler(void); /**< CMU IRQ Handler */ +void MSC_IRQHandler(void); /**< MSC IRQ Handler */ +void CRYPTO0_IRQHandler(void); /**< CRYPTO IRQ Handler */ +void LETIMER0_IRQHandler(void); /**< LETIMER0 IRQ Handler */ +void AGC_IRQHandler(void); /**< AGC IRQ Handler */ +void PROTIMER_IRQHandler(void); /**< PROTIMER IRQ Handler */ +void RTCC_IRQHandler(void); /**< RTCC IRQ Handler */ +void SYNTH_IRQHandler(void); /**< SYNTH IRQ Handler */ +void CRYOTIMER_IRQHandler(void); /**< CRYOTIMER IRQ Handler */ +void RFSENSE_IRQHandler(void); /**< RFSENSE IRQ Handler */ +void FPUEH_IRQHandler(void); /**< FPUEH IRQ Handler */ +void SMU_IRQHandler(void); /**< SMU IRQ Handler */ +void WTIMER0_IRQHandler(void); /**< WTIMER0 IRQ Handler */ +void WTIMER1_IRQHandler(void); /**< WTIMER1 IRQ Handler */ +void PCNT1_IRQHandler(void); /**< PCNT1 IRQ Handler */ +void PCNT2_IRQHandler(void); /**< PCNT2 IRQ Handler */ +void USART2_RX_IRQHandler(void); /**< USART2_RX IRQ Handler */ +void USART2_TX_IRQHandler(void); /**< USART2_TX IRQ Handler */ +void I2C1_IRQHandler(void); /**< I2C1 IRQ Handler */ +void USART3_RX_IRQHandler(void); /**< USART3_RX IRQ Handler */ +void USART3_TX_IRQHandler(void); /**< USART3_TX IRQ Handler */ +void VDAC0_IRQHandler(void); /**< VDAC0 IRQ Handler */ +void CSEN_IRQHandler(void); /**< CSEN IRQ Handler */ +void LESENSE_IRQHandler(void); /**< LESENSE IRQ Handler */ +void CRYPTO1_IRQHandler(void); /**< CRYPTO1 IRQ Handler */ +void TRNG0_IRQHandler(void); /**< TRNG0 IRQ Handler */ +void SYSCFG_IRQHandler(void); /**< SYSCFG IRQ Handler */ + +uint32_t SystemCoreClockGet(void); + +/******************************************************************************* + * @brief + * Update CMSIS SystemCoreClock variable. + * + * @details + * CMSIS defines a global variable SystemCoreClock + *that shall hold the core frequency in Hz. If the + *core frequency is dynamically changed, the variable + *must be kept updated in order to be CMSIS compliant. + * + * Notice that only if changing the core clock + *frequency through the EFR CMU API, this variable + *will be kept updated. This function is only provided + * for CMSIS compliance and if a user modifies the + *the core clock outside the CMU API. + ******************************************************************************/ +#ifndef CCP_SI917_BRINGUP +static __INLINE void SystemCoreClockUpdate(void) { (void)SystemCoreClockGet(); } +#endif /* CCP_SI917_BRINGUP */ + +uint32_t SystemMaxCoreClockGet(void); + +void SystemInit(void); +uint32_t SystemHFClockGet(void); + +uint32_t SystemHFXOClockGet(void); +void SystemHFXOClockSet(uint32_t freq); + +uint32_t SystemLFRCOClockGet(void); +uint32_t SystemULFRCOClockGet(void); + +uint32_t SystemLFXOClockGet(void); +void SystemLFXOClockSet(uint32_t freq); + +/** @} End of group */ +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif diff --git a/matter/si91x/siwx917/BRD4338A/support/src/startup_common_RS1xxxx.c b/matter/si91x/siwx917/BRD4338A/support/src/startup_common_RS1xxxx.c new file mode 100644 index 0000000000..f05122df80 --- /dev/null +++ b/matter/si91x/siwx917/BRD4338A/support/src/startup_common_RS1xxxx.c @@ -0,0 +1,514 @@ +/** + ****************************************************************************** + * @file startup_si91x.c + * @author Coocox + * @version V1.0 + * @date 03/16/2013 + * @brief Cortex M4 Devices Startup code. + * This module performs: + * - Set the initial SP + * - Set the vector table entries with the exceptions ISR address + * - Initialize data and bss + * - Call the application's entry point. + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ******************************************************************************* + */ +// System headers +#include "si91x_device.h" +#include "system_si91x.h" +// Processor specific headers +#include "core_cm4.h" +#include "rsi_ps_ram_func.h" +/*----------Stack Symbols-----------------------------------------------*/ +extern uint32_t __StackTop; +extern uint32_t __co_stackTop; + +/*----------Macro definition--------------------------------------------------*/ +#define WEAK __attribute__((weak)) + +/*----------Declaration of the default fault handlers-------------------------*/ +#ifndef __START +extern void _start(void) + __attribute__((noreturn)); /* Pre Main (C library entry point) */ +#else +extern int __START(void) __attribute__((noreturn)); /* main entry point */ +#endif + +/* System exception vector handler */ +__attribute__((used)) void WEAK Reset_Handler(void); +void WEAK NMI_Handler(void); +void WEAK HardFault_Handler(void); +void WEAK MemManage_Handler(void); +void WEAK BusFault_Handler(void); +void WEAK UsageFault_Handler(void); +void WEAK SVC_Handler(void); +void WEAK DebugMon_Handler(void); +void WEAK PendSV_Handler(void); +void WEAK SysTick_Handler(void); + +/*Boot up functions*/ +void RSI_Default_Reset_Handler(void); +void RSI_Default_WakeUp_Handler(void); +void RSI_PS_RestoreCpuContext(void); + +void WEAK IRQ000_Handler(void); /*!< ULP Processor Interrupt 0 */ +void WEAK IRQ001_Handler(void); /*!< ULP Processor Interrupt 1 */ +void WEAK IRQ002_Handler(void); /*!< ULP Processor Interrupt 2 */ +void WEAK IRQ003_Handler(void); /*!< ULP Processor Interrupt 3 */ +void WEAK IRQ004_Handler(void); /*!< ULP Processor Interrupt 4 */ +void WEAK IRQ005_Handler(void); /*!< ULP Processor Interrupt 5 */ +void WEAK IRQ006_Handler(void); /*!< ULP Processor Interrupt 6 */ +void WEAK IRQ007_Handler(void); /*!< ULP Processor Interrupt 7 */ +void WEAK IRQ008_Handler(void); /*!< ULP Processor Interrupt 8 */ +void WEAK IRQ009_Handler(void); /*!< ULP Processor Interrupt 9 */ +void WEAK IRQ010_Handler(void); /*!< ULP Processor Interrupt 10 */ +void WEAK IRQ011_Handler(void); /*!< ULP Processor Interrupt 11 */ +void WEAK IRQ012_Handler(void); /*!< ULP Processor Interrupt 12 */ +void WEAK IRQ013_Handler(void); /*!< ULP Processor Interrupt 13 */ +void WEAK IRQ014_Handler(void); /*!< ULP Processor Interrupt 14 */ +void WEAK IRQ015_Handler(void); /*!< ULP Processor Interrupt 15 */ +void WEAK IRQ016_Handler(void); /*!< ULP Processor Interrupt 15 */ +void WEAK IRQ017_Handler(void); /*!< ULP Processor Interrupt 17 */ +void WEAK IRQ018_Handler(void); /*!< ULP Processor Interrupt 18 */ +void WEAK IRQ019_Handler(void); /*!< ULP Processor Interrupt 19 */ +void WEAK IRQ020_Handler(void); +/*!< Sleep Sensor Interrupts 0 */ /*WDT*/ +void WEAK IRQ021_Handler(void); /*!< Sleep Sensor Interrupts 1 */ +void WEAK IRQ022_Handler(void); /*!< Sleep Sensor Interrupts 2 */ +void WEAK IRQ023_Handler(void); /*!< Sleep Sensor Interrupts 3 */ +void WEAK IRQ024_Handler(void); /*!< Sleep Sensor Interrupts 4 */ +void WEAK IRQ025_Handler(void); /*!< Sleep Sensor Interrupts 5 */ +void WEAK IRQ026_Handler(void); /*!< Sleep Sensor Interrupts 6 */ +void WEAK IRQ027_Handler(void); /*!< Sleep Sensor Interrupts 7 */ +void WEAK IRQ028_Handler(void); +/*!< Sleep Sensor Interrupts 8 */ /*Alarm*/ +void WEAK IRQ029_Handler(void); +/*!< Sleep Sensor Interrupts 9 */ /*Msec and sec interrupt */ +void WEAK IRQ030_Handler(void); /*!< Reserved */ +void WEAK IRQ031_Handler(void); /*!< M4SS DMA interrupt */ +void WEAK IRQ032_Handler(void); /*!< Reserved */ +void WEAK IRQ033_Handler(void); /*!< M4SS DMA interrupt */ +void WEAK IRQ034_Handler(void); /*!< M4SS SCT interrupt */ +void WEAK HIF1_IRQHandler(void); /*!< HIF Interrupt 1 */ +void WEAK HIF2_IRQHandler(void); /*!< HIF Interrupt 2 */ +void WEAK IRQ037_Handler(void); /*!< SIO Interrupt */ +void WEAK IRQ038_Handler(void); /*!< USART 1 Interrupt */ +void WEAK IRQ039_Handler(void); /*!< Reserved */ +void WEAK IRQ040_Handler(void); /*!< Reserved */ +void WEAK IRQ041_Handler(void); /*!< Reserved */ +void WEAK IRQ042_Handler(void); /*!< I2C Interrupt */ +void WEAK IRQ043_Handler(void); /*!< Reserved */ +void WEAK IRQ044_Handler(void); /*!< SSI Slave Interrupt */ +void WEAK IRQ045_Handler(void); /*!< Reserved */ +void WEAK IRQ046_Handler(void); /*!< GSPI Master 1 Interrupt */ +void WEAK IRQ047_Handler(void); /*!< Reserved */ +void WEAK IRQ048_Handler(void); /*!< MCPWM Interrupt */ +void WEAK IRQ049_Handler(void); /*!< QEI Interrupt */ +void WEAK IRQ050_Handler(void); /*!< GPIO Group Interrupt 0 */ +void WEAK IRQ051_Handler(void); /*!< GPIO Group Interrupt 1 */ +void WEAK IRQ052_Handler(void); /*!< GPIO Pin Interrupt 0 */ +void WEAK IRQ053_Handler(void); /*!< GPIO Pin Interrupt 1 */ +void WEAK IRQ054_Handler(void); /*!< GPIO Pin Interrupt 2 */ +void WEAK IRQ055_Handler(void); /*!< GPIO Pin Interrupt 3 */ +void WEAK IRQ056_Handler(void); /*!< GPIO Pin Interrupt 4 */ +void WEAK IRQ057_Handler(void); /*!< GPIO Pin Interrupt 5 */ +void WEAK IRQ058_Handler(void); /*!< GPIO Pin Interrupt 6 */ +void WEAK IRQ059_Handler(void); /*!< GPIO Pin Interrupt 7 */ +void WEAK IRQ060_Handler(void); /*!< QSPI Interrupt */ +void WEAK IRQ061_Handler(void); /*!< I2C 2 Interrupt */ +void WEAK IRQ062_Handler(void); /*!< Ethernet Interrupt */ +void WEAK IRQ063_Handler(void); /*!< Reserved */ +void WEAK IRQ064_Handler(void); /*!< I2S master Interrupt */ +void WEAK IRQ065_Handler(void); /*!< Reserved */ +void WEAK IRQ066_Handler(void); /*!< Can 1 Interrupt */ +void WEAK IRQ067_Handler(void); /*!< Reserved */ +void WEAK IRQ068_Handler(void); /*!< SDMEM Interrupt */ +void WEAK IRQ069_Handler(void); /*!< PLL clock ind Interrupt */ +void WEAK IRQ070_Handler(void); /*!< Reserved */ +void WEAK IRQ071_Handler(void); /*!< CCI system Interrupt Out */ +void WEAK IRQ072_Handler(void); /*!< FPU exception */ +void WEAK IRQ073_Handler(void); /*!< USB INTR */ +void WEAK IRQ074_Handler(void); /*!< TASS_P2P_INTR */ +void WEAK IRQ075_Handler(void); /*!< WLAN Band1 intr0 */ +void WEAK IRQ076_Handler(void); /*!< WLAN Band1 intr1 */ +void WEAK IRQ077_Handler(void); /*!< Reserved */ +void WEAK IRQ078_Handler(void); /*!< Reserved */ +void WEAK IRQ079_Handler(void); /*!< BT intr */ +void WEAK IRQ080_Handler(void); /*!< ZB intr */ +void WEAK IRQ081_Handler(void); /*!< Reserved */ +void WEAK IRQ082_Handler(void); /*!< Modem disabled mode trigger intr */ +void WEAK IRQ083_Handler(void); /*!< gpio intr */ +void WEAK IRQ084_Handler(void); /*!< uart intr */ +void WEAK IRQ085_Handler(void); /*!< watch dog level intr */ +void WEAK IRQ086_Handler(void); /*!< ULP Sleep sensor interrupt */ +void WEAK IRQ087_Handler(void); /*!< ECDH intr */ +void WEAK IRQ088_Handler(void); /*!< DH intr */ +void WEAK IRQ089_Handler(void); /*!< QSPI intr */ +void WEAK IRQ090_Handler(void); /*!< ULP processor interrupt TASS */ +void WEAK IRQ091_Handler(void); /*!< Sys Tick Timer */ +void WEAK IRQ092_Handler(void); /*!< Real Timer interrupt */ +void WEAK IRQ093_Handler(void); /*!< PLL lock interrupt */ +void WEAK IRQ094_Handler(void); /*!< Reserved */ +void WEAK IRQ095_Handler(void); /*!< UART2 Interrupt */ +void WEAK IRQ096_Handler(void); /*!< I2S Interrupt */ +void WEAK IRQ097_Handler(void); /*!< I2C Interrupt */ +void WEAK IRQ098_Handler(void); /*!< RESERVED */ + +/*----------Symbols defined in linker script----------------------------------*/ +extern unsigned long _sidata; /*!< Start address for the initialization + values of the .data section. */ +extern unsigned long _sdata; /*!< Start address for the .data section */ +extern unsigned long _edata; /*!< End address for the .data section */ +extern unsigned long _sbss; /*!< Start address for the .bss section */ +extern unsigned long _ebss; /*!< End address for the .bss section */ +extern void _eram; /*!< End address for ram */ +extern uint32_t __etext; +extern unsigned long __StackTop; + +/*----------Function prototypes-----------------------------------------------*/ +extern int main(void); /*!< The entry point for the application */ +void Default_Reset_Handler(void); /*!< Default reset handler */ +static void Default_Handler(void); /*!< Default exception handler */ +/** + *@brief The minimal vector table for a Cortex M4. Note that the proper + *constructs must be placed on this to ensure that it ends up at physical + *address 0x00000000. + */ +__attribute__((used, + section(".isr_vector"))) void (*const g_pfnVectors[])(void) = { + /*----------------------------------Core + Exceptions---------------------------------- */ + + (void *)&__StackTop, /*!< The initial stack pointer (0x00) */ + (void *)0x300001, /*!< Reset Handler */ + NMI_Handler, /*!< NMI Handler */ + HardFault_Handler, /*!< Hard Fault Handler */ + MemManage_Handler, /*!< MPU Fault Handler */ + BusFault_Handler, /*!< Bus Fault Handler */ + UsageFault_Handler, /*!< Usage Fault Handler */ + 0, /*!< Reserved */ + 0, /*!< Reserved */ + 0, /*!< Reserved */ + 0, /*!< Reserved */ + SVC_Handler, /*!< SVCall Handler */ + DebugMon_Handler, /*!< Debug Monitor Handler */ + 0, /*!< Reserved */ + PendSV_Handler, /*!< PendSV Handler */ + SysTick_Handler, /*!< SysTick Handler */ + + IRQ000_Handler, // 0: VAD interrupt + IRQ001_Handler, // 1: ULP Processor Interrupt1 + IRQ002_Handler, // 2: ULP Processor Interrupt2 + IRQ003_Handler, // 3: ULP Processor Interrupt3 + IRQ004_Handler, // 4: ULP Processor Interrupt4 + IRQ005_Handler, // 5: ULP Processor Interrupt5 + IRQ006_Handler, // 6: ULP Processor Interrupt6 + IRQ007_Handler, // 7: ULP Processor Interrupt7 + IRQ008_Handler, // 8: ULP Processor Interrupt8 + IRQ009_Handler, // 9: ULP Processor Interrupt8 + IRQ010_Handler, // 10: ULP Processor Interrupt8 + IRQ011_Handler, // 11: ULP Processor Interrupt8 + IRQ012_Handler, // 12: ULP Processor Interrupt8 + IRQ013_Handler, // 13: ULP Processor Interrupt8 + IRQ014_Handler, // 14: ULP Processor Interrupt8 + IRQ015_Handler, // 15: ULP Processor Interrupt8 + IRQ016_Handler, // 16: ULP Processor Interrupt8 + IRQ017_Handler, // 17: ULP Processor Interrupt8 + IRQ018_Handler, // 18: ULP Processor Interrupt8 + IRQ019_Handler, // 19: ULP Processor Interrupt8 + IRQ020_Handler, // 20: Sleep Sensor Interrupts 0 + IRQ021_Handler, // 21: Sleep Sensor Interrupts 1 + IRQ022_Handler, // 22: Sleep Sensor Interrupts 2 + IRQ023_Handler, // 23: Sleep Sensor Interrupts 3 + IRQ024_Handler, // 24: Sleep Sensor Interrupts 4 + IRQ025_Handler, // 25: Sleep Sensor Interrupts 5 + IRQ026_Handler, // 26: Sleep Sensor Interrupts 6 + IRQ027_Handler, // 27: Sleep Sensor Interrupts 7 + IRQ028_Handler, // 28: Sleep Sensor Interrupts 8 + IRQ029_Handler, // 29: Sleep Sensor Interrupts 9 + (void *)&__co_stackTop, // 30: Reserved + IRQ031_Handler, // 31: RPDMA interrupt + RSI_Default_Reset_Handler, // 32: Reserved + IRQ033_Handler, // 33: UDMA interrupt + IRQ034_Handler, // 34: SCT interrupt + HIF1_IRQHandler, // 35: HIF Interrupt1 + HIF2_IRQHandler, // 36: HIF Interrupt2 + IRQ037_Handler, // 37: SIO Interrupt + IRQ038_Handler, // 38: USART 1 Interrupt + IRQ039_Handler, // 39: USART 2 Interrupt + RSI_PS_RestoreCpuContext, // 40: USART 3 Interrupt + IRQ041_Handler, // 41: GPIO WAKEUP INTERRUPT + IRQ042_Handler, // 42: I2C Interrupt + (void *)0x10AD10AD, // 43: Reserved + IRQ044_Handler, // 44: SSI Slave Interrupt + 0, // 45: Reserved + IRQ046_Handler, // 46: GSPI Master 1 Interrupt + IRQ047_Handler, // 47: Reserved + IRQ048_Handler, // 48: MCPWM Interrupt + IRQ049_Handler, // 49: QEI Interrupt + IRQ050_Handler, // 50: GPIO Group Interrupt 0 + IRQ051_Handler, // 51: GPIO Group Interrupt 1 + IRQ052_Handler, // 52: GPIO Pin Interrupt 0 + IRQ053_Handler, // 53: GPIO Pin Interrupt 1 + IRQ054_Handler, // 54: GPIO Pin Interrupt 2 + IRQ055_Handler, // 55: GPIO Pin Interrupt 3 + IRQ056_Handler, // 56: GPIO Pin Interrupt 4 + IRQ057_Handler, // 57: GPIO Pin Interrupt 5 + IRQ058_Handler, // 58: GPIO Pin Interrupt 6 + IRQ059_Handler, // 59: GPIO Pin Interrupt 7 + IRQ060_Handler, // 60: QSPI Interrupt + IRQ061_Handler, // 61: I2C 2 Interrupt + IRQ062_Handler, // 62: Ethernet Interrupt + IRQ063_Handler, // 63: Reserved + IRQ064_Handler, // 64: I2S master Interrupt + 0, // 65: Reserved + IRQ066_Handler, // 66: Can 1 Interrupt + 0, // 67: Reserved + IRQ068_Handler, // 68: SDMEM Interrupt + IRQ069_Handler, // 69: PLL clock ind Interrupt + 0, // 70: Reserved + IRQ071_Handler, // 71: CCI system Interrupt Out + IRQ072_Handler, // 72: FPU exception + IRQ073_Handler, // 73: USB INTR + IRQ074_Handler, // 74: TASS_P2P_INTR + IRQ075_Handler, // 75: WLAN Band1 intr0(TA) + IRQ076_Handler, // 76: WLAN Band1 intr1(TA) + 0, // 77: Reserved(TA) + 0, // 78: Reserved(TA) + IRQ079_Handler, // 79: BT intr(TA) + IRQ080_Handler, // 80: ZB intr(TA) + 0, // 81: Reserved(TA) + IRQ082_Handler, // 82: Modem disabled mode trigger intr(TA) + IRQ083_Handler, // 83: gpio intr(TA) + IRQ084_Handler, // 84: uart intr(TA) + IRQ085_Handler, // 85: watch dog level intr(TA) + IRQ086_Handler, // 86: ULP Sleep sensor interrupt(TA) + IRQ087_Handler, // 87: ECDH intr(TA) + IRQ088_Handler, // 88: DH intr(TA) + IRQ089_Handler, // 89: QSPI intr(TA) + IRQ090_Handler, // 90: ULP processor interrupt TASS(TA) + IRQ091_Handler, // 91: Sys Tick Timer(TA) + IRQ092_Handler, // 92: Real Timer interrupt(TA) + IRQ093_Handler, // 93: PLL lock interrupt(TA) + 0, // 94: Reserved(TA) + IRQ095_Handler, // 95: UART2 Interrupt(TA) + 0, // 96: Reserved(TA) + IRQ097_Handler, // 97: I2C Interrupt(TA) +}; + +/** + * @brief This is the code that gets never called, Dummy handler + * @param None + * @retval None + */ +void Default_Reset_Handler(void) { + /*Generic Default reset handler for CM4 */ + while (1) + ; +} + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + */ +volatile unsigned long *pulSrc, *pulDest; + +#ifdef M4_PS2_STATE +__attribute__((section(".reset_handler"))) +#endif +#ifdef EXECUTION_FROM_RAM +__attribute__((section(".ramVector"))) char RAM_VECTOR[sizeof(g_pfnVectors)]; +__attribute__ ((section(".reset_handler"))) +#endif + +void Copy_Table() +{ + uint32_t *pSrc, *pDest; + extern uint32_t __etext; + extern uint32_t __data_start__; + extern uint32_t __data_end__; + pSrc = &__etext; + pDest = &__data_start__; + + for (; pDest < &__data_end__;) { + *pDest++ = *pSrc++; + } +} + +void Zero_Table() { + uint32_t *pDest; + extern uint32_t __bss_start__; + extern uint32_t __bss_end__; + pDest = &__bss_start__; + + for (; pDest < &__bss_end__;) { + *pDest++ = 0UL; + } +} + +void RSI_Default_Reset_Handler(void) { + +#ifdef BOOTLOADER_ENABLE + SystemInit2(); +#endif /* BOOTLOADER_ENABLE */ + +#if defined(__GNUC__) && defined(__START) + Copy_Table(); + Zero_Table(); + __START(); +#else +#if 0 // senthil_ccp + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +#else + Copy_Table(); + Zero_Table(); + +#ifdef EXECUTION_FROM_RAM + // copying the vector table from flash to ram + memcpy(RAM_VECTOR, (uint32_t *)SCB->VTOR, sizeof(g_pfnVectors)); + // assing the ram vector address to VTOR register + SCB->VTOR = (uint32_t)RAM_VECTOR; +#endif + +#ifndef __NO_SYSTEM_INIT + SystemInit(); /* CMSIS System Initialization */ +#endif + _start(); +#endif +#endif /* __GNUC__ */ +} + +/** + *@brief Provide weak aliases for each Exception handler to the Default_Handler. + * As they are weak aliases, any function with the same name will override + * this definition. + */ +#pragma weak Reset_Handler = Default_Reset_Handler +#pragma weak NMI_Handler = Default_Handler +#pragma weak HardFault_Handler = Default_Handler +#pragma weak MemManage_Handler = Default_Handler +#pragma weak BusFault_Handler = Default_Handler +#pragma weak UsageFault_Handler = Default_Handler +#pragma weak SVC_Handler = Default_Handler +#pragma weak DebugMon_Handler = Default_Handler +#pragma weak PendSV_Handler = Default_Handler +#pragma weak SysTick_Handler = Default_Handler +/*----------------------------------external + * interrupts------------------------------ */ +#pragma weak IRQ000_Handler = Default_Handler +#pragma weak IRQ001_Handler = Default_Handler +#pragma weak IRQ002_Handler = Default_Handler +#pragma weak IRQ003_Handler = Default_Handler +#pragma weak IRQ004_Handler = Default_Handler +#pragma weak IRQ005_Handler = Default_Handler +#pragma weak IRQ006_Handler = Default_Handler +#pragma weak IRQ007_Handler = Default_Handler +#pragma weak IRQ008_Handler = Default_Handler +#pragma weak IRQ009_Handler = Default_Handler +#pragma weak IRQ010_Handler = Default_Handler +#pragma weak IRQ011_Handler = Default_Handler +#pragma weak IRQ012_Handler = Default_Handler +#pragma weak IRQ013_Handler = Default_Handler +#pragma weak IRQ014_Handler = Default_Handler +#pragma weak IRQ015_Handler = Default_Handler +#pragma weak IRQ016_Handler = Default_Handler +#pragma weak IRQ017_Handler = Default_Handler +#pragma weak IRQ018_Handler = Default_Handler +#pragma weak IRQ019_Handler = Default_Handler +#pragma weak IRQ020_Handler = Default_Handler +#pragma weak IRQ021_Handler = Default_Handler +#pragma weak IRQ022_Handler = Default_Handler +#pragma weak IRQ023_Handler = Default_Handler +#pragma weak IRQ024_Handler = Default_Handler +#pragma weak IRQ025_Handler = Default_Handler +#pragma weak IRQ026_Handler = Default_Handler +#pragma weak IRQ027_Handler = Default_Handler +#pragma weak IRQ028_Handler = Default_Handler +#pragma weak IRQ029_Handler = Default_Handler +#pragma weak IRQ030_Handler = Default_Handler +#pragma weak IRQ031_Handler = Default_Handler +#pragma weak IRQ032_Handler = Default_Handler +#pragma weak IRQ033_Handler = Default_Handler +#pragma weak IRQ034_Handler = Default_Handler +#pragma weak HIF1_IRQHandler = Default_Handler +#pragma weak HIF2_IRQHandler = Default_Handler +#pragma weak IRQ037_Handler = Default_Handler +#pragma weak IRQ038_Handler = Default_Handler +#pragma weak IRQ039_Handler = Default_Handler +#pragma weak IRQ040_Handler = Default_Handler +#pragma weak IRQ041_Handler = Default_Handler +#pragma weak IRQ042_Handler = Default_Handler +#pragma weak IRQ043_Handler = Default_Handler +#pragma weak IRQ044_Handler = Default_Handler +#pragma weak IRQ045_Handler = Default_Handler +#pragma weak IRQ046_Handler = Default_Handler +#pragma weak IRQ047_Handler = Default_Handler +#pragma weak IRQ048_Handler = Default_Handler +#pragma weak IRQ049_Handler = Default_Handler +#pragma weak IRQ050_Handler = Default_Handler +#pragma weak IRQ051_Handler = Default_Handler +#pragma weak IRQ052_Handler = Default_Handler +#pragma weak IRQ053_Handler = Default_Handler +#pragma weak IRQ054_Handler = Default_Handler +#pragma weak IRQ055_Handler = Default_Handler +#pragma weak IRQ056_Handler = Default_Handler +#pragma weak IRQ057_Handler = Default_Handler +#pragma weak IRQ058_Handler = Default_Handler +#pragma weak IRQ059_Handler = Default_Handler +#pragma weak IRQ060_Handler = Default_Handler +#pragma weak IRQ061_Handler = Default_Handler +#pragma weak IRQ062_Handler = Default_Handler +#pragma weak IRQ063_Handler = Default_Handler +#pragma weak IRQ064_Handler = Default_Handler +#pragma weak IRQ065_Handler = Default_Handler +#pragma weak IRQ066_Handler = Default_Handler +#pragma weak IRQ067_Handler = Default_Handler +#pragma weak IRQ068_Handler = Default_Handler +#pragma weak IRQ069_Handler = Default_Handler +#pragma weak IRQ070_Handler = Default_Handler +#pragma weak IRQ071_Handler = Default_Handler +#pragma weak IRQ072_Handler = Default_Handler +#pragma weak IRQ073_Handler = Default_Handler +#pragma weak IRQ074_Handler = Default_Handler +#pragma weak IRQ075_Handler = Default_Handler +#pragma weak IRQ076_Handler = Default_Handler +#pragma weak IRQ077_Handler = Default_Handler +#pragma weak IRQ078_Handler = Default_Handler +#pragma weak IRQ079_Handler = Default_Handler +#pragma weak IRQ080_Handler = Default_Handler +#pragma weak IRQ081_Handler = Default_Handler +#pragma weak IRQ082_Handler = Default_Handler +#pragma weak IRQ083_Handler = Default_Handler +#pragma weak IRQ084_Handler = Default_Handler +#pragma weak IRQ085_Handler = Default_Handler +#pragma weak IRQ086_Handler = Default_Handler +#pragma weak IRQ087_Handler = Default_Handler +#pragma weak IRQ088_Handler = Default_Handler +#pragma weak IRQ089_Handler = Default_Handler +#pragma weak IRQ090_Handler = Default_Handler +#pragma weak IRQ091_Handler = Default_Handler +#pragma weak IRQ092_Handler = Default_Handler +#pragma weak IRQ093_Handler = Default_Handler +#pragma weak IRQ094_Handler = Default_Handler +#pragma weak IRQ095_Handler = Default_Handler +#pragma weak IRQ096_Handler = Default_Handler +#pragma weak IRQ097_Handler = Default_Handler +#pragma weak IRQ098_Handler = Default_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, + * preserving the system state for examination by a debugger. + * @param None + * @retval None + */ +static void Default_Handler(void) { + /* Go into an infinite loop. */ + while (1) { + } +} + +/*********************** (C) COPYRIGHT 2009 Coocox ************END OF FILE*****/ From d256f67581090b7402d77464bdf8d58a90c683bb Mon Sep 17 00:00:00 2001 From: srningap Date: Mon, 4 Sep 2023 18:22:35 +0530 Subject: [PATCH 5/7] removed redundant code --- matter/si91x/siwx917/BRD4338A/support/hal/rsi_hal_mcu_m4.c | 1 - 1 file changed, 1 deletion(-) diff --git a/matter/si91x/siwx917/BRD4338A/support/hal/rsi_hal_mcu_m4.c b/matter/si91x/siwx917/BRD4338A/support/hal/rsi_hal_mcu_m4.c index 6e4b5e760a..f9a7957ca0 100644 --- a/matter/si91x/siwx917/BRD4338A/support/hal/rsi_hal_mcu_m4.c +++ b/matter/si91x/siwx917/BRD4338A/support/hal/rsi_hal_mcu_m4.c @@ -86,7 +86,6 @@ void IRQ021_Handler(void) { for (int i = 0; i < 10000; i++) __asm__("nop;"); /* clear NPSS GPIO interrupt*/ - RSI_NPSSGPIO_ClrIntr(NPSS_GPIO_0_INTR); RSI_NPSSGPIO_ClrIntr(NPSS_GPIO_2_INTR); // if the btn is not pressed setting the state to 1 if (RSI_NPSSGPIO_GetPin(NPSS_GPIO_2) && (!btn0)) { From bdf0f769d897aec8ac04fbc330cb616923cb0df0 Mon Sep 17 00:00:00 2001 From: srningap Date: Tue, 5 Sep 2023 16:27:10 +0530 Subject: [PATCH 6/7] restyled --- .../siwx917/BRD4338A/autogen/RTE_Components.h | 8 +++-- .../BRD4338A/autogen/sl_event_handler.c | 32 ++++++------------- .../BRD4338A/config/emlib_core_debug_config.h | 11 ++++--- .../support/hal/rsi_hal_mcu_platform_init.c | 2 +- 4 files changed, 22 insertions(+), 31 deletions(-) diff --git a/matter/si91x/siwx917/BRD4338A/autogen/RTE_Components.h b/matter/si91x/siwx917/BRD4338A/autogen/RTE_Components.h index f4ff113e8f..fa2e6ed411 100644 --- a/matter/si91x/siwx917/BRD4338A/autogen/RTE_Components.h +++ b/matter/si91x/siwx917/BRD4338A/autogen/RTE_Components.h @@ -1,5 +1,6 @@ // This file is autogenerated by Simplicity Configuration Tools. -// The contents of this file will be replaced in their entirety upon regeneration. +// The contents of this file will be replaced in their entirety upon +// regeneration. // // Source template file: RTE_Components.h.jinja @@ -8,7 +9,7 @@ #define RTE_COMPONENTS_H /* standard device header from emlib */ -#define CMSIS_device_header "em_device.h" +#define CMSIS_device_header "em_device.h" /* components are auto-generated here */ @@ -26,7 +27,8 @@ #endif /* RTE_COMPONENTS_H */ /* This file is autogenerated by Simplicity Configuration Tools. */ -/* The contents of this file will be replaced in their entirety upon regeneration. */ +/* The contents of this file will be replaced in their entirety upon + * regeneration. */ /* */ /* Source template file: RTE_Components.h.jinja */ diff --git a/matter/si91x/siwx917/BRD4338A/autogen/sl_event_handler.c b/matter/si91x/siwx917/BRD4338A/autogen/sl_event_handler.c index 4f7f400898..67f242e2ac 100644 --- a/matter/si91x/siwx917/BRD4338A/autogen/sl_event_handler.c +++ b/matter/si91x/siwx917/BRD4338A/autogen/sl_event_handler.c @@ -1,15 +1,14 @@ #include "sl_event_handler.h" +#include "cmsis_os2.h" +#include "rsi_board.h" #include "rsi_chip.h" #include "rsi_nvic_priorities_config.h" +#include "rsi_wisemcu_hardware_setup.h" #include "sl_device_init_nvic.h" #include "sli_siwx917_soc.h" -#include "rsi_board.h" -#include "rsi_wisemcu_hardware_setup.h" -#include "cmsis_os2.h" -void sl_platform_init(void) -{ +void sl_platform_init(void) { SystemCoreClockUpdate(); sl_si91x_device_init_nvic(); sl_device_init_nvic(); @@ -19,25 +18,12 @@ void sl_platform_init(void) osKernelInitialize(); } -void sl_kernel_start(void) -{ - osKernelStart(); -} - -void sl_driver_init(void) -{ -} +void sl_kernel_start(void) { osKernelStart(); } -void sl_service_init(void) -{ - DEBUGINIT(); -} +void sl_driver_init(void) {} -void sl_stack_init(void) -{ -} +void sl_service_init(void) { DEBUGINIT(); } -void sl_internal_app_init(void) -{ -} +void sl_stack_init(void) {} +void sl_internal_app_init(void) {} diff --git a/matter/si91x/siwx917/BRD4338A/config/emlib_core_debug_config.h b/matter/si91x/siwx917/BRD4338A/config/emlib_core_debug_config.h index 8316d3fc67..0641552551 100644 --- a/matter/si91x/siwx917/BRD4338A/config/emlib_core_debug_config.h +++ b/matter/si91x/siwx917/BRD4338A/config/emlib_core_debug_config.h @@ -1,4 +1,5 @@ -/***************************************************************************//** +/***************************************************************************/ +/** * @file * @brief emlib_core Configuration ******************************************************************************* @@ -35,10 +36,12 @@ // Core Configuration -// Enables measuring of interrupt disable time for debugging purposes. +// Enables measuring of +// interrupt disable time for debugging purposes. // Default: 0 -// If Enabled, either cycle_counter or systemview component must be added to project. -#define SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING 0 +// If Enabled, +// either cycle_counter or systemview component must be added to project. +#define SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING 0 // diff --git a/matter/si91x/siwx917/BRD4338A/support/hal/rsi_hal_mcu_platform_init.c b/matter/si91x/siwx917/BRD4338A/support/hal/rsi_hal_mcu_platform_init.c index daa6af0638..5fe31e3e69 100644 --- a/matter/si91x/siwx917/BRD4338A/support/hal/rsi_hal_mcu_platform_init.c +++ b/matter/si91x/siwx917/BRD4338A/support/hal/rsi_hal_mcu_platform_init.c @@ -21,9 +21,9 @@ #include "rsi_board.h" #include "rsi_pll.h" #include "rsi_rom_clks.h" +#include "rsi_rom_egpio.h" #include "silabs_utils.h" #include "sli_siwx917_soc.h" -#include "rsi_rom_egpio.h" #define SOC_PLL_REF_FREQUENCY 32000000 /* PLL input REFERENCE clock 32MHZ */ From bffc5687f29bbd933d826323a49ac5922efb0a1d Mon Sep 17 00:00:00 2001 From: srningap Date: Tue, 5 Sep 2023 16:39:59 +0530 Subject: [PATCH 7/7] restyled --- matter/si91x/siwx917/BRD4338A/autogen/RTE_Components.h | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/matter/si91x/siwx917/BRD4338A/autogen/RTE_Components.h b/matter/si91x/siwx917/BRD4338A/autogen/RTE_Components.h index fa2e6ed411..9e2cbfebbb 100644 --- a/matter/si91x/siwx917/BRD4338A/autogen/RTE_Components.h +++ b/matter/si91x/siwx917/BRD4338A/autogen/RTE_Components.h @@ -1,10 +1,9 @@ // This file is autogenerated by Simplicity Configuration Tools. // The contents of this file will be replaced in their entirety upon // regeneration. -// +// // Source template file: RTE_Components.h.jinja - #ifndef RTE_COMPONENTS_H #define RTE_COMPONENTS_H @@ -23,7 +22,6 @@ #define RTE_RTOS_FreeRTOS_TIMERS - #endif /* RTE_COMPONENTS_H */ /* This file is autogenerated by Simplicity Configuration Tools. */ @@ -31,4 +29,3 @@ * regeneration. */ /* */ /* Source template file: RTE_Components.h.jinja */ -