CSA_Block.vhd

library ieee; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_unsigned.all;

-- Carry Select Adder block that is made up of a 2-to-1 NBIT mux that selects one 
-- sum between the two generated by the correspondent RCAs using the carry in signal as the 
-- selection signal
entity CSA_Block is
	generic(NBIT: integer);
	port(	A: in std_logic_vector(NBIT-1 downto 0);
			B: in std_logic_vector(NBIT-1 downto 0);
			Cin: in std_logic;
			S: out std_logic_vector(NBIT-1 downto 0));
end CSA_Block;

architecture structural of CSA_Block is
	-- signals that represent the outputs of the two different RCAs
	signal SUM_Cin0, SUM_Cin1: std_logic_vector(NBIT-1 downto 0);
	
	component RCA
	generic (NBIT: integer);
	Port(	A:	In	std_logic_vector(NBIT-1 downto 0);
			B:	In	std_logic_vector(NBIT-1 downto 0);
			Ci: In std_logic;
			S:	Out std_logic_vector(NBIT-1 downto 0);
			Co: Out std_logic);
	end component;

	component MUX21_GENERIC
  	Generic (NBIT: integer);
	Port( A:	In	std_logic_vector(NBIT-1 downto 0) ; -- A and B are the 2 inputs
			B:	In	std_logic_vector(NBIT-1 downto 0);
			SEL:	In	std_logic;					 -- SEL is the selection signal
			Y:	Out	std_logic_vector(NBIT-1 downto 0)); -- Y is the output
	end component;
	
	begin
		-- the first RCA generates the sum summing the two inputs with a C_in = '0'
		-- while the second does the same thing but with C_in = '1'.
		-- Thei outputs are the inputs of the mux that selects one of them according to the actual C_in
		RCA_0: RCA generic map(NBIT => NBIT)
				    port map(A => A, B => B, Ci => '0', S => SUM_Cin0);
					
		RCA_1: RCA generic map(NBIT => NBIT)
				    port map(A => A, B => B, Ci => '1', S => SUM_Cin1);
					
		MUX: MUX21_GENERIC generic map(NBIT => NBIT)
				    port map(A => SUM_Cin1, B => SUM_Cin0, SEL => Cin, Y => S);
					
end structural;