cpufeatures: add XGETBV checks

[newpavlov]

According to the Intel manual, when detecting features like AVX and AVX2 we should first check availability of the XGETBV instruction and then check that OS supports XMM and YMM registers.

[gabrielesvelto]

The link in the first comment is dead but the document has been archived fortunately. We're hitting a crash in Firefox because of this, see bug 1838108.

The full detection sequence for AVX from the Intel manual is the following:

1. Detect CPUID.1:ECX.OSXSAVE[bit 27] = 1 (XGETBV enabled for application use).
2. Issue XGETBV and verify that XFEATURE_ENABLED_MASK[2:1] = ‘11b’ (XMM state and YMM state are enabled by OS).
3. detect CPUID.1:ECX.AVX[bit 28] = 1 (AVX instructions supported).

From what I can tell what the crate is missing at the moment is step 2.

[tarcieri]

It seems like we can use core::arch::x86_64::_xgetbv.

Something like this? (after detecting XGETBV is enabled)

let xcr0 = unsafe { core::arch::x86_64::_xgetbv(0) };

// XMM state and YMM state are enabled by OS
(xcr0 & 6) == 6

[gabrielesvelto]

Yes, that would do the trick.

[newpavlov]

What about target features dependent on XMM and ZMM registers?

[tarcieri]

@newpavlov I guess that'd be all of the AVX-512 instructions? (and wouldn't it be XMM, YMM, and ZMM?)

[newpavlov]

I mean, shouldn't we technically check OS support for XMM registers when we use SSE instructions? Same for ZMM registers which are indeed used by AVX-512 instructions. After a cursory search I couldn't find information about them.

[tarcieri]

That seems like the safest option, although I'm curious what the Intel manual says

[ericlagergren]

I mean, shouldn't we technically check OS support for XMM registers when we use SSE instructions? Same for ZMM registers which are indeed used by AVX-512 instructions. After a cursory search I couldn't find information about them.

I /believe/ you only need to check OSXSAVE for VEX-prefixed instructions.