Cycle accurate simulator for a 5 staged pipelined RISC-V CPU.
- Pick any testcase and its binary from Testcases folder (or u can make your own testcase)
- Output binary destination of binary is in Assembler/Output/Output.bin
- Result generated from Evaluation af binary generated by Assembler is placed in Assembler/Result/Assembler_Evaluation.txt
- Logs Generated from simulator are placed in logs/logfile.log
- Place your assembly language code in Input/Input.txt and its corresponding binary text file in Input/binary.txt
- Now to run, Open terminal in this repository directory and type command 'make' (Please note that this run approach will work only in case of linux environment)
- Tada!!! Results from Assembler and its Cycle accurate Simulator are ready to view
Some outputs -
