| Page name | QA | Status | Test | Description/Comment |
|---|---|---|---|---|
| DECODE_DGA.v | Verilog created | Top module of the DGA | ||
| DECODE_DGA_COMM.v | Verilog created | Decode Internal Databus Commands | ||
| DECODE_DGA_IDBS.v | Verilog created | Decode Internal Databus SOURCE (IDBS). Generates ENABLE signals for the chips to be read or written | ||
| DECODE_DGA_PFIFC.v | Verilog created | FIFO controller. Replaced by FIFO_8BIT.v | ||
| DECODE_DGA_PFIFC_DELAY.v | Verilog created | FIFO delay. Replaced by FIFO_8BIT.v | ||
| DECODE_DGA_PFIFD.v | Verilog created | FIFO data. Replaced by FIFO_8BIT.v | ||
| DECODE_DGA_POW.v | Verilog created | POWER detection | ||
| F091.v | Verilog created | NEC F091 - H,L LEVEL GENERATOR | ||
| F103.v | Verilog created | NEC F103 - Inverter x3 signal drive | ||
| F571.v | Verilog created | NEC F571 - 2 TO 1 MULTIPLEXER | ||
| F595.v | Verilog created | ** NEED TO ADD TEST ** | NEC F595 - R/S Latch with Gated input | |
| F617.v | Verilog created | ** NEED TO ADD TEST ** | NEC F617 - D Flip-Flop with RB, SB | |
| F714.v | Verilog created | ** NEED TO ADD TEST ** | NEC F714 - T Flip-Flop with R, S | |
| F924.v | Verilog created | ** NEED TO ADD TEST ** | NEC F924 - 4-BIT D-TYPE FLIP-FLOP |