-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathrv_csr.cpp
248 lines (214 loc) · 11.2 KB
/
rv_csr.cpp
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
// Generated by: MakeCSR.py3
// Copyright (C) 2022, Ron K. Irvine. All rights reserved.
// Date: 2022-01-13 21:25:09
// Currently allocated RISC-V machine-level CSR addresses
// ======================================================
#include <stdlib.h>
#include <stdint.h>
#include <stdio.h>
typedef struct {
uint16_t csr;
const char* access;
const char* name;
const char* desc;
} csr_t;
csr_t csr_table[] {
// Unprivileged and User-Level CSRs
// 00 00 XXXX 0x000-0x0FF Standard read/write
// 01 00 XXXX 0x400-0x4FF Standard read/write
// 10 00 XXXX 0x800-0x8FF Custom read/write
// 11 00 0XXX 0xC00-0xC7F Standard read-only
// 11 00 10XX 0xC80-0xCBF Standard read-only
// 11 00 11XX 0xCC0-0xCFF Custom read-only
// Supervisor-Level CSRs
// 00 01 XXXX 0x100-0x1FF Standard read/write
// 01 01 0XXX 0x500-0x57F Standard read/write
// 01 01 10XX 0x580-0x5BF Standard read/write
// 01 01 11XX 0x5C0-0x5FF Custom read/write
// 10 01 0XXX 0x900-0x97F Standard read/write
// 10 01 10XX 0x980-0x9BF Standard read/write
// 10 01 11XX 0x9C0-0x9FF Custom read/write
// 11 01 0XXX 0xD00-0xD7F Standard read-only
// 11 01 10XX 0xD80-0xDBF Standard read-only
// 11 01 11XX 0xDC0-0xDFF Custom read-only
// Hypervisor and VS CSRs
// 00 10 XXXX 0x200-0x2FF Standard read/write
// 01 10 0XXX 0x600-0x67F Standard read/write
// 01 10 10XX 0x680-0x6BF Standard read/write
// 01 10 11XX 0x6C0-0x6FF Custom read/write
// 10 10 0XXX 0xA00-0xA7F Standard read/write
// 10 10 10XX 0xA80-0xABF Standard read/write
// 10 10 11XX 0xAC0-0xAFF Custom read/write
// 11 10 0XXX 0xE00-0xE7F Standard read-only
// 11 10 10XX 0xE80-0xEBF Standard read-only
// 11 10 11XX 0xEC0-0xEFF Custom read-only
// Machine-Level CSRs
// 00 11 XXXX 0x300-0x3FF Standard read/write
// 01 11 0XXX 0x700-0x77F Standard read/write
// 01 11 100X 0x780-0x79F Standard read/write
// 01 11 1010 0x7A0-0x7AF Standard read/write debug CSRs
// 01 11 1011 0x7B0-0x7BF Debug-mode-only CSRs
// 01 11 11XX 0x7C0-0x7FF Custom read/write
// 10 11 0XXX 0xB00-0xB7F Standard read/write
// 10 11 10XX 0xB80-0xBBF Standard read/write
// 10 11 11XX 0xBC0-0xBFF Custom read/write
// 11 11 0XXX 0xF00-0xF7F Standard read-only
// 11 11 10XX 0xF80-0xFBF Standard read-only
// 11 11 11XX 0xFC0-0xFFF Custom read-only
// Currently allocated RISC-V machine-level CSR addresses.
// =======================================================
// Number Privilege Name Description
// ---------------------------------
// Unprivileged Floating-Point CSRs
{ 0x001, "URW", "fflags", "Floating-Point Accrued Exceptions" },
{ 0x002, "URW", "frm", "Floating-Point Dynamic Rounding Mode" },
{ 0x003, "URW", "fcsr", "Floating-Point Control and Status Register (frm + fflags)" },
// Unprivileged Counter/Timers
{ 0xC00, "URO", "cycle", "Cycle counter for RDCYCLE instruction" },
{ 0xC01, "URO", "time", "Timer for RDTIME instruction" },
{ 0xC02, "URO", "instret", "Instructions-retired counter for RDINSTRET instruction" },
{ 0xC03, "URO", "hpmcounter3", "Performance-monitoring counter" },
{ 0xC04, "URO", "hpmcounter4", "Performance-monitoring counter" },
// ...
{ 0xC1F, "URO", "hpmcounter31", "Performance-monitoring counter" },
{ 0xC80, "URO", "cycleh", "Upper 32 bits of cycle, RV32 only" },
{ 0xC81, "URO", "timeh", "Upper 32 bits of time, RV32 only" },
{ 0xC82, "URO", "instreth", "Upper 32 bits of instret, RV32 only" },
{ 0xC83, "URO", "hpmcounter3h", "Upper 32 bits of hpmcounter3, RV32 only" },
{ 0xC84, "URO", "hpmcounter4h", "Upper 32 bits of hpmcounter4, RV32 only" },
// ...
{ 0xC9F, "URO", "hpmcounter31h", "Upper 32 bits of hpmcounter31, RV32 only" },
// Supervisor Trap Setup
{ 0x100, "SRW", "sstatus", "Supervisor status register" },
{ 0x104, "SRW", "sie", "Supervisor interrupt-enable register" },
{ 0x105, "SRW", "stvec", "Supervisor trap handler base address" },
{ 0x106, "SRW", "scounteren", "Supervisor counter enable" },
// Supervisor Configuration
{ 0x10A, "SRW", "senvcfg", "Supervisor environment configuration register" },
// Supervisor Trap Handling
{ 0x140, "SRW", "sscratch", "Scratch register for supervisor trap handlers" },
{ 0x141, "SRW", "sepc", "Supervisor exception program counter" },
{ 0x142, "SRW", "scause", "Supervisor trap cause" },
{ 0x143, "SRW", "stval", "Supervisor bad address or instruction" },
{ 0x144, "SRW", "sip", "Supervisor interrupt pending" },
// Supervisor Protection and Translation
{ 0x180, "SRW", "satp", "Supervisor address translation and protection" },
// Debug/Trace Registers
{ 0x5A8, "SRW", "scontext", "Supervisor-mode context register" },
// Hypervisor Trap Setup
{ 0x600, "HRW", "hstatus", "Hypervisor status register" },
{ 0x602, "HRW", "hedeleg", "Hypervisor exception delegation register" },
{ 0x603, "HRW", "hideleg", "Hypervisor interrupt delegation register" },
{ 0x604, "HRW", "hie", "Hypervisor interrupt-enable register" },
{ 0x606, "HRW", "hcounteren", "Hypervisor counter enable" },
{ 0x607, "HRW", "hgeie", "Hypervisor guest external interrupt-enable register" },
// Hypervisor Trap Handling
{ 0x643, "HRW", "htval", "Hypervisor bad guest physical address" },
{ 0x644, "HRW", "hip", "Hypervisor interrupt pending" },
{ 0x645, "HRW", "hvip", "Hypervisor virtual interrupt pending" },
{ 0x64A, "HRW", "htinst", "Hypervisor trap instruction (transformed)" },
{ 0xE12, "HRO", "hgeip", "Hypervisor guest external interrupt pending" },
// Hypervisor Configuration
{ 0x60A, "HRW", "henvcfg", "Hypervisor environment configuration register" },
{ 0x61A, "HRW", "henvcfgh", "Additional hypervisor env. conf. register, RV32 only" },
// Hypervisor Protection and Translation
{ 0x680, "HRW", "hgatp", "Hypervisor guest address translation and protection" },
// Debug/Trace Registers
{ 0x6A8, "HRW", "hcontext", "Hypervisor-mode context register" },
// Hypervisor Counter/Timer Virtualization Registers
{ 0x605, "HRW", "htimedelta", "Delta for VS/VU-mode timer" },
{ 0x615, "HRW", "htimedeltah", "Upper 32 bits of htimedelta, HSXLEN=32 only" },
// Virtual Supervisor Registers
{ 0x200, "HRW", "vsstatus", "Virtual supervisor status register" },
{ 0x204, "HRW", "vsie", "Virtual supervisor interrupt-enable register" },
{ 0x205, "HRW", "vstvec", "Virtual supervisor trap handler base address" },
{ 0x240, "HRW", "vsscratch", "Virtual supervisor scratch register" },
{ 0x241, "HRW", "vsepc", "Virtual supervisor exception program counter" },
{ 0x242, "HRW", "vscause", "Virtual supervisor trap cause" },
{ 0x243, "HRW", "vstval", "Virtual supervisor bad address or instruction" },
{ 0x244, "HRW", "vsip", "Virtual supervisor interrupt pending" },
{ 0x280, "HRW", "vsatp", "Virtual supervisor address translation and protection" },
// Machine Information Registers
{ 0xF11, "MRO", "mvendorid", "Vendor ID" },
{ 0xF12, "MRO", "marchid", "Architecture ID" },
{ 0xF13, "MRO", "mimpid", "Implementation ID" },
{ 0xF14, "MRO", "mhartid", "Hardware thread ID" },
{ 0xF15, "MRO", "mconfigptr", "Pointer to configuration data structure" },
// Machine Trap Setup
{ 0x300, "MRW", "mstatus", "Machine status register" },
{ 0x301, "MRW", "misa", "ISA and extensions" },
{ 0x302, "MRW", "medeleg", "Machine exception delegation register" },
{ 0x303, "MRW", "mideleg", "Machine interrupt delegation register" },
{ 0x304, "MRW", "mie", "Machine interrupt-enable register" },
{ 0x305, "MRW", "mtvec", "Machine trap-handler base address" },
{ 0x306, "MRW", "mcounteren", "Machine counter enable" },
{ 0x310, "MRW", "mstatush", "Additional machine status register, RV32 only" },
// Machine Trap Handling
{ 0x340, "MRW", "mscratch", "Scratch register for machine trap handlers" },
{ 0x341, "MRW", "mepc", "Machine exception program counter" },
{ 0x342, "MRW", "mcause", "Machine trap cause" },
{ 0x343, "MRW", "mtval", "Machine bad address or instruction" },
{ 0x344, "MRW", "mip", "Machine interrupt pending" },
{ 0x34A, "MRW", "mtinst", "Machine trap instruction (transformed)" },
{ 0x34B, "MRW", "mtval2", "Machine bad guest physical address" },
// Machine Configuration
{ 0x30A, "MRW", "menvcfg", "Machine environment configuration register" },
{ 0x31A, "MRW", "menvcfgh", "Additional machine env. conf. register, RV32 only" },
{ 0x747, "MRW", "mseccfg", "Machine security configuration register" },
{ 0x757, "MRW", "mseccfgh", "Additional machine security conf. register, RV32 only" },
// Machine Memory Protection
{ 0x3A0, "MRW", "pmpcfg0", "Physical memory protection configuration" },
{ 0x3A1, "MRW", "pmpcfg1", "Physical memory protection configuration, RV32 only" },
{ 0x3A2, "MRW", "pmpcfg2", "Physical memory protection configuration" },
{ 0x3A3, "MRW", "pmpcfg3", "Physical memory protection configuration, RV32 only" },
// ...
{ 0x3AE, "MRW", "pmpcfg14", "Physical memory protection configuration" },
{ 0x3AF, "MRW", "pmpcfg15", "Physical memory protection configuration, RV32 only" },
{ 0x3B0, "MRW", "pmpaddr0", "Physical memory protection address register" },
{ 0x3B1, "MRW", "pmpaddr1", "Physical memory protection address register" },
// ...
{ 0x3EF, "MRW", "pmpaddr63", "Physical memory protection address register" },
// Machine Counter/Timers
{ 0xB00, "MRW", "mcycle", "Machine cycle counter" },
{ 0xB02, "MRW", "minstret", "Machine instructions-retired counter" },
{ 0xB03, "MRW", "mhpmcounter3", "Machine performance-monitoring counter" },
{ 0xB04, "MRW", "mhpmcounter4", "Machine performance-monitoring counter" },
// ...
{ 0xB1F, "MRW", "mhpmcounter31", "Machine performance-monitoring counter" },
{ 0xB80, "MRW", "mcycleh", "Upper 32 bits of mcycle, RV32 only" },
{ 0xB82, "MRW", "minstreth", "Upper 32 bits of minstret, RV32 only" },
{ 0xB83, "MRW", "mhpmcounter3h", "Upper 32 bits of mhpmcounter3, RV32 only" },
{ 0xB84, "MRW", "mhpmcounter4h", "Upper 32 bits of mhpmcounter4, RV32 only" },
// ...
{ 0xB9F, "MRW", "mhpmcounter31h", "Upper 32 bits of mhpmcounter31, RV32 only" },
// Machine Counter Setup
{ 0x320, "MRW", "mcountinhibit", "Machine counter-inhibit register" },
{ 0x323, "MRW", "mhpmevent3", "Machine performance-monitoring event selector" },
{ 0x324, "MRW", "mhpmevent4", "Machine performance-monitoring event selector" },
// ...
{ 0x33F, "MRW", "mhpmevent31", "Machine performance-monitoring event selector" },
// Debug/Trace Registers (shared with Debug Mode)
{ 0x7A0, "MRW", "tselect", "Debug/Trace trigger register select" },
{ 0x7A1, "MRW", "tdata1", "First Debug/Trace trigger data register" },
{ 0x7A2, "MRW", "tdata2", "Second Debug/Trace trigger data register" },
{ 0x7A3, "MRW", "tdata3", "Third Debug/Trace trigger data register" },
{ 0x7A8, "MRW", "mcontext", "Machine-mode context register" },
// Debug Mode Registers
{ 0x7B0, "DRW", "dcsr", "Debug control and status register" },
{ 0x7B1, "DRW", "dpc", "Debug PC" },
{ 0x7B2, "DRW", "dscratch0", "Debug scratch register 0" },
{ 0x7B3, "DRW", "dscratch1", "Debug scratch register 1" },
// Unprivileged Custom read-only
{ 0xCC0, "URO", "rand", "Random Number, 32 bit" },
{ 0x000, NULL, NULL, NULL }
};
const char* csr_name(int csr) {
for(csr_t* cp=csr_table; cp->name != NULL; ++cp) {
if(cp->csr == csr) {
return cp->name;
}
}
static char buf[16];
sprintf(buf, "0x%03x", csr);
return buf;
}