From 4f945c524077982fde0f067747a3a47e0a009eac Mon Sep 17 00:00:00 2001 From: RipleyTom Date: Fri, 23 Nov 2018 16:15:34 +0100 Subject: [PATCH] More bpm changes #2 --- rpcs3/Emu/Cell/PPUInterpreter.cpp | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/rpcs3/Emu/Cell/PPUInterpreter.cpp b/rpcs3/Emu/Cell/PPUInterpreter.cpp index 01e3acf54de5..aa2e07811730 100644 --- a/rpcs3/Emu/Cell/PPUInterpreter.cpp +++ b/rpcs3/Emu/Cell/PPUInterpreter.cpp @@ -3621,6 +3621,13 @@ bool ppu_interpreter::STWUX(ppu_thread& ppu, ppu_opcode_t op) { const u64 addr = ppu.gpr[op.ra] + ppu.gpr[op.rb]; vm::write32(vm::cast(addr, HERE), (u32)ppu.gpr[op.rs]); + + if (g_breakpoint_handler->HasBreakpoint(addr, breakpoint_type::bp_mwrite)) + { + LOG_SUCCESS(GENERAL, "BPMW: STWUX breakpoint writing 0x%x at 0x%x", (u32)ppu.gpr[op.rs], addr); + ppubreak(ppu); + } + ppu.gpr[op.ra] = addr; return true; } @@ -4497,6 +4504,13 @@ bool ppu_interpreter::STWU(ppu_thread& ppu, ppu_opcode_t op) { const u64 addr = ppu.gpr[op.ra] + op.simm16; vm::write32(vm::cast(addr, HERE), (u32)ppu.gpr[op.rs]); + + if (g_breakpoint_handler->HasBreakpoint(addr, breakpoint_type::bp_mwrite)) + { + LOG_SUCCESS(GENERAL, "BPMW: STWU breakpoint writing 0x%x at 0x%x", (u32)ppu.gpr[op.rs], addr); + ppubreak(ppu); + } + ppu.gpr[op.ra] = addr; return true; }