Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

cpu/msp430fxyz: Fixed input sanitizing in GPIO_PIN #9367

Merged
merged 1 commit into from
Jun 26, 2018

Conversation

maribu
Copy link
Member

@maribu maribu commented Jun 17, 2018

In cpu/msp430fxyz/include/periph_cpu.h the type gpio_t is defined as:

typedef uint16_t gpio_t;

The old version of the macro is:

#define GPIO_PIN(x, y)      ((gpio_t)(((x & 0xff) << 8) | (1 << (y & 0xff))))

Both x and y are sanitized by using bit-wise and. But the y sanitizing is not correct:
1 can be shifted at most 15 times to the left in an uint16_t. But the upper 8 bits are determined by the port x, so only the lower 8 bit should be determined by y. Thus, the correct bitmask is 0x07 to sanitize y.

Update: My original patch and statement was strictly wrong. It should be fixed now.

@maribu
Copy link
Member Author

maribu commented Jun 17, 2018

@haukepetersen: As you are the author of cpu/msp430fxyz/include/periph_cpu.h, could you review this one-liner PR?

@maribu
Copy link
Member Author

maribu commented Jun 25, 2018

Sadly this issue is blocking another pull request, which I'm really interested to get it merged. Maybe @cladmi also has a an msp430 bases board and is able to review and test this one-line PR?

@PeterKietzmann PeterKietzmann self-assigned this Jun 26, 2018
@PeterKietzmann PeterKietzmann added Type: bug The issue reports a bug / The PR fixes a bug (including spelling errors) Platform: MSP Platform: This PR/issue effects MSP-based platforms Area: drivers Area: Device drivers labels Jun 26, 2018
@PeterKietzmann
Copy link
Member

@maribu I can give it a look this evening. Can you add a short description how to test this PR in order to see that it fixes the bug?

@maribu
Copy link
Member Author

maribu commented Jun 26, 2018

@PeterKietzmann: Thank you very much. The bug is that the compilation with specific invalid values for x and/or y in GPIO_PIN(x, y) fails. In this PR a test application for the SHT10/SHT11/SHT15 driver is compiled by Murdock against all platforms. If a board does not specify on which pins the SHT1x is connected, the default configuration is used - which happens to be invalid on msp430fxyz based boards. Of course, it does not make much sense to compile the test application and the driver for a board not having such a sensor. But as the GPIO_PIN macro does perform sanitizing of the input already, it should do that imho correctly.

So, I already know that this PR fixes the compilation Bug. I only don't know if it has any regressions, as I don't have the correct hardware to test. So basically, does the GPIO_PIN() still allow to access all pins on all ports? (I would just test the pin with the highest and lowest number on each port and three randomly chosen pins with an LED to reduce the testing effort. If there is a bug in the new sanitizing, it should affect pins with high port or pin numbers. Maybe using the SAUL interface to GPIO controlled LEDs and the saul CLI is an easy way for testing?)

@PeterKietzmann
Copy link
Member

@maribu I'm fine with the y operation but I don't understand how 0x0f & x "clears all but the lower 8 bits". Can you investigate on that? It shouldn't hurt though as the MCU has max. 8 pins per port anyway. I ran some tests on the Z1 board but unfortunately the driver doesn't seem to work for all port/pins, neither on master nor with your PR. If we agree on the x sanitation this general" bug shouldn't block your PR.

@maribu
Copy link
Member Author

maribu commented Jun 26, 2018

You're totally right about the x sanitizing. I guess I should stop creating pull requests after long days at work. I feel quite a bit ashamed now of me writing such bullshit. I fixed both the PR description and the PR

@PeterKietzmann
Copy link
Member

@maribu no worries, we all know that.

@PeterKietzmann PeterKietzmann added the CI: ready for build If set, CI server will compile all applications for all available boards for the labeled PR label Jun 26, 2018
Copy link
Member

@PeterKietzmann PeterKietzmann left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

ACK. I wasn't able to completely test this PR as the driver seems (partly) broken. However, the change (i) is correct by the description and (ii) does not break the Z1/MSP430 GPIO pins that work on current master. Furthermore, this PR blocks progress in other PRs so I decide for merging it know.

@PeterKietzmann PeterKietzmann merged commit 7f8caf8 into RIOT-OS:master Jun 26, 2018
@maribu maribu deleted the mps430fxyz branch June 27, 2018 06:56
@cladmi cladmi added this to the Release 2018.07 milestone Jul 10, 2018
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
Area: drivers Area: Device drivers CI: ready for build If set, CI server will compile all applications for all available boards for the labeled PR Platform: MSP Platform: This PR/issue effects MSP-based platforms Type: bug The issue reports a bug / The PR fixes a bug (including spelling errors)
Projects
None yet
Development

Successfully merging this pull request may close these issues.

3 participants