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stm32/periph/uart: extra byte transmitted on first transmission #8045
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Here is a hexdump from the serial console:
That first 0xff is not supposed to be there. On the pyserial it also displays as |
I can roughly confirm this. Out of my head I think I remember seing this on some STM boards, but not all of them. So if I am right, this is effecting only some stm32 family members, though I can't say which ones. Just happen to have a
(pressing the reset button a couple of times...) |
On paper, line 61 of the /* set TX pin high to avoid garbage during further initialization */
gpio_set(uart_config[uart].tx_pin); should prevent the @bergzand could you maybe play with that line a little bit and see if you can prevent that garbage byte from being send somehow? |
This issue has been automatically marked as stale because it has not had recent activity. It will be closed if no further activity occurs. If you want me to ignore this issue, please mark it with the "State: don't stale" label. Thank you for your contributions. |
In This is related to #12380 and #12612 Based on the nature of the cause, I'd guess that slower boards are more susceptible to showing this bug. |
@bergzand or perhaps @haukepetersen could you test #14417 and see if it resolves this issue? Using a board with a slower MCU might help to reproduce it. If not, speeding up the baud rate should help reproduce it too. Actually yeah just speed up the baud rate as much as possible. That should do the trick. |
I used the following patch: diff --git a/cpu/stm32/periph/uart.c b/cpu/stm32/periph/uart.c
index 5cba9470ec..0815009e3e 100644
--- a/cpu/stm32/periph/uart.c
+++ b/cpu/stm32/periph/uart.c
@@ -160,6 +160,9 @@ static inline void uart_disable_clock(uart_t uart)
int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg)
{
+ gpio_t signal_pin = GPIO_PIN(PORT_D, 2);
+ gpio_init(signal_pin, GPIO_OUT);
+ gpio_clear(signal_pin);
assert(uart < UART_NUMOF);
/* save ISR context */
@@ -221,6 +224,7 @@ int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg)
}
#endif
+ gpio_set(signal_pin);
return UART_OK;
} And connected a logic analyzer to the UART port and to PD2 (label Above, you can see some noise on TXD while Same data, zoomed in. Even more zoom. |
So, it is possible to set the GPIO after the periph clock is enabled but before the pin is configured. There is still some flickering that my logic analyzer picks up, but the integrated programmer/debugger/UART-adapter of Nucleo-F446Re will ignore it. I guess that is good enough. |
The fix is actually different than described above. Please refer to the PR description of #14426 for a description of the cause of the issue and how I suggest to fix it. |
Fixed by #14426. |
After testing the slipdev driver on a nucleo-f446, it appeared to me as if an extra 0xFF byte is transmitted by the UART driver. As somewhat described in #8041 (comment), this can be explicitly triggered with slipdev by having the node transmit a frame. An initial 0xff byte should appear as first byte (and by doing so crash the tunslip6 application).
More a suspicion than a confirmed bug, it would help if somebody can reproduce this (or refute this bug), I still have to test if this 0xff byte is also added to the UART interface of the shell.
Oh and close and ignore this issue if it is caused by the low on reset nature of the hardware and the active-low of UART.
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