From 159405e5d13f33e504bf6274ee0f3223dc058791 Mon Sep 17 00:00:00 2001 From: Marian Buschsieweke Date: Mon, 28 Nov 2022 14:05:52 +0100 Subject: [PATCH 1/2] cpu/qn909x/periph_timer: make clangd happy The linter was unhappy that `unsinged long` and `uint32_t` were used inconsistency (in the `timer_init()` declaration, implementation, as well as in the `DEBUG()` format specifiers). (cherry picked from commit c95028655d823ec932523127704cd5001fe38a13) --- cpu/qn908x/periph/timer.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/cpu/qn908x/periph/timer.c b/cpu/qn908x/periph/timer.c index 586090e623c1..9004842adbee 100644 --- a/cpu/qn908x/periph/timer.c +++ b/cpu/qn908x/periph/timer.c @@ -66,9 +66,9 @@ static const clock_ip_name_t ctimers_clocks[FSL_FEATURE_SOC_CTIMER_COUNT] = #error "ERROR in board timer configuration: too many timers defined" #endif -int timer_init(tim_t tim, unsigned long freq, timer_cb_t cb, void *arg) +int timer_init(tim_t tim, uint32_t freq, timer_cb_t cb, void *arg) { - DEBUG("timer_init(%u, %lu)\n", tim, freq); + DEBUG("timer_init(%u, %" PRIu32 ")\n", tim, freq); if (tim >= TIMER_NUMOF) { return -1; } @@ -84,7 +84,7 @@ int timer_init(tim_t tim, unsigned long freq, timer_cb_t cb, void *arg) uint32_t core_freq = CLOCK_GetFreq(kCLOCK_ApbClk); uint32_t prescale = (core_freq + freq / 2) / freq - 1; if (prescale == (uint32_t)(-1)) { - DEBUG("timer_init: Frequency %lu is too fast for core_freq=%lu", + DEBUG("timer_init: Frequency %" PRIu32 " is too fast for core_freq=%" PRIu32, freq, core_freq); return -1; } From f0572a5214106991d33775095828d571bb47e26a Mon Sep 17 00:00:00 2001 From: Marian Buschsieweke Date: Mon, 28 Nov 2022 16:36:34 +0100 Subject: [PATCH 2/2] cpu/qn908x: use bitarithm_test_and_clear() & fix cb Previously, the callback was incorrectly passed a channel of zero as argument regardless of the channel that triggered the IRQ. This fixes the issue and also uses `bitarithm_test_and_clear()` to only iterate over the channels that actually have an IRQ flag set, rather than all channels. (cherry picked from commit 0d853561801a47c5eda97ad17c7219fb7c05da23) --- cpu/qn908x/periph/timer.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/cpu/qn908x/periph/timer.c b/cpu/qn908x/periph/timer.c index 9004842adbee..f80faa584dce 100644 --- a/cpu/qn908x/periph/timer.c +++ b/cpu/qn908x/periph/timer.c @@ -25,10 +25,11 @@ #include -#include "cpu.h" +#include "bitarithm.h" #include "board.h" -#include "periph_conf.h" +#include "cpu.h" #include "periph/timer.h" +#include "periph_conf.h" #include "vendor/drivers/fsl_clock.h" @@ -144,14 +145,15 @@ static inline void isr_ctimer_n(CTIMER_Type *dev, uint32_t ctimer_num) { DEBUG("isr_ctimer_%" PRIu32 " flags=0x%" PRIx32 "\n", ctimer_num, dev->IR); - for (uint32_t i = 0; i < TIMER_CHANNELS; i++) { - if (dev->IR & (1u << i)) { - /* Note: setting the bit to 1 in the flag register will clear the - * bit. */ - dev->IR = 1u << i; - dev->MCR &= ~(CTIMER_MCR_MR0I_MASK << (i * 3)); - isr_ctx[ctimer_num].cb(isr_ctx[ctimer_num].arg, 0); - } + unsigned state = dev->IR & ((1 << TIMER_CHANNELS) - 1); + while (state) { + uint8_t channel; + state = bitarithm_test_and_clear(state, &channel); + /* Note: setting the bit to 1 in the flag register will clear the + * bit. */ + dev->IR = 1u << channel; + dev->MCR &= ~(CTIMER_MCR_MR0I_MASK << (channel * 3)); + isr_ctx[ctimer_num].cb(isr_ctx[ctimer_num].arg, channel); } cortexm_isr_end(); }