diff --git a/boards/esp32s2-lilygo-ttgo-t8/Kconfig b/boards/esp32s2-lilygo-ttgo-t8/Kconfig new file mode 100644 index 0000000000000..e732c8eb549ef --- /dev/null +++ b/boards/esp32s2-lilygo-ttgo-t8/Kconfig @@ -0,0 +1,61 @@ +# Copyright (c) 2020 HAW Hamburg +# 2022 Gunar Schorcht +# +# This file is subject to the terms and conditions of the GNU Lesser +# General Public License v2.1. See the file LICENSE in the top level +# directory for more details. + +config BOARD + default "esp32s2-lilygo-ttgo-t8" if BOARD_ESP32S2_LILYGO_TTGO_T8 + +config BOARD_ESP32S2_LILYGO_TTGO_T8 + bool + default y + select BOARD_COMMON_ESP32S2 + select CPU_MODEL_ESP32S2 + select HAS_ARDUINO + select HAS_ESP_RTC_TIMER_32K if ESP32S2_LILYGO_TTGO_T8_32K_XTAL + select HAS_ESP_SPI_RAM + select HAS_HIGHLEVEL_STDIO if ESP32S2_LILYGO_TTGO_T8_USB + select HAS_PERIPH_ADC + select HAS_PERIPH_DAC + select HAS_PERIPH_I2C + select HAS_PERIPH_PWM + select HAS_PERIPH_SPI + select HAS_PERIPH_USBDEV + select HAS_SDCARD_SPI + select HAS_TINYUSB_DEVICE + select HAVE_MTD_SDCARD_DEFAULT + select HAVE_ST7735 + select MODULE_FATFS_VFS if MODULE_VFS_DEFAULT + select MODULE_USBUS_CDC_ACM if MODULE_USBUS + +menu "LILYGO TTGO T8 ESP32-S2 Board configurations" + depends on BOARD_ESP32S2_LILYGO_TTGO_T8 + + config ESP32S2_LILYGO_TTGO_T8_USB + bool "USB interface is used instead of USB-to-UART bridge" + help + The USB D-/D+ signals are connected via DIP switches either to the + USB-to-UART bridge (default) or to GPIO19/GPIO20 of the ESP32-S2. + To use the USB interface of the ESP32-S2, the USB D-/D+ signals + must be connected to GPIO19 and GPIO20 and this option has to be + enabled. + + config ESP32S2_LILYGO_TTGO_T8_32K_XTAL + bool "32.768 kHz crystal is used" + default y + help + GPIO15 and GPIO16 of the ESP32-S2 are connected via DIP switches + either with the on-board 32.768 kHz crystal (default) or the + according pins at the extension headers. If the pins at the + extension headers are used instead, disable this option. + +endmenu + +choice STDIO_IMPLEMENTATION + default MODULE_STDIO_CDC_ACM if MODULE_USBUS + default MODULE_STDIO_TINYUSB_CDC_ACM if MODULE_TINYUSB_DEVICE +endchoice + +source "$(RIOTBOARD)/common/esp32s2/Kconfig" diff --git a/boards/esp32s2-lilygo-ttgo-t8/Makefile b/boards/esp32s2-lilygo-ttgo-t8/Makefile new file mode 100644 index 0000000000000..c71e835d772ac --- /dev/null +++ b/boards/esp32s2-lilygo-ttgo-t8/Makefile @@ -0,0 +1,5 @@ +MODULE = board + +DIRS = $(RIOTBOARD)/common/esp32s2 + +include $(RIOTBASE)/Makefile.base diff --git a/boards/esp32s2-lilygo-ttgo-t8/Makefile.dep b/boards/esp32s2-lilygo-ttgo-t8/Makefile.dep new file mode 100644 index 0000000000000..10a0153c1d8da --- /dev/null +++ b/boards/esp32s2-lilygo-ttgo-t8/Makefile.dep @@ -0,0 +1,19 @@ +ifneq (,$(filter esp32s2-lilygo-ttgo-t8-usb,$(USEMODULE))) + include $(RIOTBOARD)/common/makefiles/stdio_cdc_acm.dep.mk +endif + +ifneq (,$(filter mtd,$(USEMODULE))) + USEMODULE += mtd_sdcard_default +endif + +# default to using fatfs on SD card +ifneq (,$(filter vfs_default,$(USEMODULE))) + USEMODULE += fatfs_vfs + USEMODULE += mtd +endif + +ifneq (,$(filter disp_dev,$(USEMODULE))) + USEMODULE += st7735 +endif + +include $(RIOTBOARD)/common/esp32s2/Makefile.dep diff --git a/boards/esp32s2-lilygo-ttgo-t8/Makefile.features b/boards/esp32s2-lilygo-ttgo-t8/Makefile.features new file mode 100644 index 0000000000000..2a9342802bbbf --- /dev/null +++ b/boards/esp32s2-lilygo-ttgo-t8/Makefile.features @@ -0,0 +1,24 @@ +# the board uses a ESP32-S2 with external 4MB QSPI Flash and external 8MB QSPI PSRAM +CPU_MODEL = esp32s2 +FEATURES_PROVIDED += esp_spi_ram + +# common board and CPU features +include $(RIOTBOARD)/common/esp32s2/Makefile.features + +# peripherals provided by the board +FEATURES_PROVIDED += periph_adc +FEATURES_PROVIDED += periph_dac +FEATURES_PROVIDED += periph_i2c +FEATURES_PROVIDED += periph_pwm +FEATURES_PROVIDED += periph_spi +FEATURES_PROVIDED += periph_usbdev + +# other features provided by the board +FEATURES_PROVIDED += arduino +FEATURES_PROVIDED += esp_rtc_timer_32k +FEATURES_PROVIDED += sdcard_spi +FEATURES_PROVIDED += tinyusb_device + +ifneq (,$(filter esp32s2-lilygo-ttgo-t8-usb,$(USEMODULE))) + FEATURES_PROVIDED += highlevel_stdio +endif diff --git a/boards/esp32s2-lilygo-ttgo-t8/Makefile.include b/boards/esp32s2-lilygo-ttgo-t8/Makefile.include new file mode 100644 index 0000000000000..9d387f68030bd --- /dev/null +++ b/boards/esp32s2-lilygo-ttgo-t8/Makefile.include @@ -0,0 +1,7 @@ +PSEUDOMODULES += esp32s2-lilygo-ttgo-t8-usb + +ifneq (,$(filter esp32s2-lilygo-ttgo-t8-usb,$(USEMODULE))) + PORT_LINUX ?= /dev/ttyACM0 +endif + +include $(RIOTBOARD)/common/esp32s2/Makefile.include diff --git a/boards/esp32s2-lilygo-ttgo-t8/board.c b/boards/esp32s2-lilygo-ttgo-t8/board.c new file mode 100644 index 0000000000000..f14f38beaed06 --- /dev/null +++ b/boards/esp32s2-lilygo-ttgo-t8/board.c @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2023 Gunar Schorcht + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup boards_esp32s2_lilygo_ttgo_t8 + * @{ + * + * @file + * @brief Board initialization for the LILYGO TTGO T8 ESP32-S2 board + * + * @author Gunar Schorcht + */ + +#include "board.h" +#include "periph/gpio.h" + +void board_init(void) +{ + if (IS_USED(MODULE_ST7735)) { + gpio_init(BACKLIGHT_PIN, GPIO_OUT); + } +} diff --git a/boards/esp32s2-lilygo-ttgo-t8/doc.txt b/boards/esp32s2-lilygo-ttgo-t8/doc.txt new file mode 100644 index 0000000000000..341913e6e34e1 --- /dev/null +++ b/boards/esp32s2-lilygo-ttgo-t8/doc.txt @@ -0,0 +1,179 @@ +/* + * Copyright (C) 2022 Gunar Schorcht + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @defgroup boards_esp32s2_lilygo_ttgo_t8 LILYGO TTGO T8 ESP32-S2 Board + * @ingroup boards_esp32s2 + * @brief Support for LILYGO TTGO T8 ESP32-S2 Board + * @author Gunar Schorcht + +\section esp32s2_lilygo_ttgo_t8 LILYGO TTGO T8 ESP32-S2 + +## Table of Contents {#esp32s2_lilygo_ttgo_t8_toc} + +1. [Overview](#esp32s2_lilygo_ttgo_t8_overview) +2. [Hardware](#esp32s2_lilygo_ttgo_t8_hardware) + 1. [MCU](#esp32s2_lilygo_ttgo_t8_mcu) + 2. [Board Configuration](#esp32s2_lilygo_ttgo_t8_board_configuration) + 3. [Board Pinout](#esp32s2_lilygo_ttgo_t8_pinout) +3. [Flashing the Device](#esp32s2_lilygo_ttgo_t8_flashing) + +## Overview {#esp32s2_lilygo_ttgo_t8_overview} + +The Espressif LILYGO TTGO T8 ESP32-S2 is a ESP32-S2 board with an OLED Display +(not yet supported) and a TF Card slot. + +\image html https://ae01.alicdn.com/kf/H8062f551fe7b4233809294d4a5b1d45d1.jpg "LILYGO TTGO T8 ESP32-S2" width=600px + +The board has following main features: + +Feature | Support +:--------------------|:------- +ESP32-S2 SoC | yes +4 MB Flash | yes +8 MB QSPI RAM | yes +SD Card slot | yes +32.768KHz Crystal | yes +OLED display ST77789 | no + +[Back to table of contents](#esp32s2_lilygo_ttgo_t8_toc) + +## Hardware {#esp32s2_lilygo_ttgo_t8_hardware} + +This section describes + +- the [MCU](#esp32s2_lilygo_ttgo_t8_mcu), +- the default [board configuration](#esp32s2_lilygo_ttgo_t8_board_configuration), +- [optional hardware configurations](#esp32s2_lilygo_ttgo_t8_optional_hardware), +- the [board pinout](#esp32s2_lilygo_ttgo_t8_pinout). + +[Back to table of contents](#esp32s2_lilygo_ttgo_t8_toc) + +### MCU {#esp32s2_lilygo_ttgo_t8_mcu} + +Most features of the board are provided by the ESP32-S2 SoC. For detailed +information about the ESP32-S2 SoC variant (family) and ESP32x SoCs, +see section \ref esp32_mcu_esp32 "ESP32 SoC Series". + +[Back to table of contents](#esp32s2_lilygo_ttgo_t8_toc) + +### Board Configuration {#esp32s2_lilygo_ttgo_t8_board_configuration} + +The LILYGO TTGO T8 ESP32-S2 board uses the `SPI_DEV(0)` (FSPI) for the +OLED Display. The GPIOs of `SPI_DEV(0)` are therefore not broken out. +SPI_DEV(1) is used for the SD Card slot. These GPIOs are broken out and +can also be used by other devices. + +The LILYGO TTGO T8 ESP32-S2 has a USB-to-UART bridge on board. The USB D-/D+ +signals of the USB-C connector are connected via DIP switches either to this +USB-to-UART bridge (default) or to GPIO19/GPIO20 of the ESP32-S2. To use the +USB-OTG interface of the ESP32-S2, the USB D-/D+ signals must be connected to +GPIO19 and GPIO20, see section \ref esp32s2_lilygo_ttgo_t8_pinout "Pinout". +If the USB-to-UART bridge is used, module `stdio_cdc_acm` or module +`stdio_tinyusb_cdc_acm` can be enabled to use the USB interface also for the +console. + +The LILYGO TTGO T8 ESP32-S2 has a 32.768 kHz crystal on the board, which is +connected to GPIO15 and GPIO16 via DIP switches (default). The crystal can +be switched off via the DIP switches so that GPIO15 and GPIO16 become available +at the headers, see section \ref esp32s2_lilygo_ttgo_t8_pinout "Pinout". + +The following table shows the default board configuration, which is sorted +according to the defined functionality of GPIOs. This configuration can be +overridden by \ref esp32_application_specific_configurations +"application-specific configurations". + +
+Function | GPIOs | Remarks | Configuration +:---------------|:-------|:--------|:---------------------------------- +BUTTON0 | GPIO0 | | | +ADC_LINE(n) | GPIO1 ... GPIO9 | | \ref esp32_adc_channels "ADC Channels" +DAC_LINE(n) | GPIO17, GPIO18 | | \ref esp32_dac_channels "DAC Channels" +GPIO38 | GPIO38 | OLED RESET (not broken out) | | +I2C_DEV(0) SCL | GPIO7 | | \ref esp32_i2c_interfaces "I2C Interfaces" +I2C_DEV(0) SDA | GPIO8 | | \ref esp32_i2c_interfaces "I2C Interfaces" +PWM_DEV(0) | GPIO39, GPIO40, GPIO41, GPIO42 | - | \ref esp32_pwm_channels "PWM Channels" +PWM_DEV(1) | GPIO15, GPIO16 | if module `esp_rtc_timer_32k` is not used | \ref esp32_pwm_channels "PWM Channels" +SPI_DEV(0) CLK | GPIO36 | OLED CLK (not broken out) | | +SPI_DEV(0) MISO | GPIO37 | OLED MISO (not broken out) | | +SPI_DEV(0) MOSI | GPIO35 | OLED MOSI (not broken out) | | +SPI_DEV(0) CS0 | GPIO34 | OLED CS0 (not broken out) | | +SPI_DEV(1) CLK | GPIO12 | SD Card CLK | \ref esp32_spi_interfaces "SPI Interfaces" +SPI_DEV(1) MISO | GPIO37 | SD Card MISO | \ref esp32_spi_interfaces "SPI Interfaces" +SPI_DEV(1) MOSI | GPIO35 | SD Card MOSI | \ref esp32_spi_interfaces "SPI Interfaces" +SPI_DEV(1) CS0 | GPIO34 | SD Card CS | \ref esp32_spi_interfaces "SPI Interfaces" +UART_DEV(0) TxD | GPIO43 | Console | \ref esp32_uart_interfaces "UART interfaces" +UART_DEV(0) RxD | GPIO44 | Console | \ref esp32_uart_interfaces "UART interfaces" +USB D- | GPIO19 | if USB-to-UART bridge is not used | | +USB D+ | GPIO20 | if USB-to-UART bridge is not used | | +
+\n + +For detailed information about the peripheral configurations of ESP32-S2 +boards, see section \ref esp32_peripherals "Common Peripherals". + +[Back to table of contents](#esp32s2_lilygo_ttgo_t8_toc) + +### Board Pinout {#esp32s2_lilygo_ttgo_t8_pinout} + +The following figure shows the pinout as configured by the board +definition. + +@image html https://ae01.alicdn.com/kf/H4a77f8684c144384a165d7a89476c602q.jpg "LILYGO TTGO T8 ESP32-S2 Pinout" width=900px + +The corresponding board schematics can be found [here] +(https://github.com/Xinyuan-LilyGO/LilyGo-T-Display-S2/raw/master/schematic/ESP32_S2-Display.pdf) + +[Back to table of contents](#esp32s2_lilygo_ttgo_t8_toc) + +## Flashing the Device {#esp32s2_lilygo_ttgo_t8_flashing} + +Flashing RIOT is quite easy. The board has an USB-C connector which is either +connected to the USB-to-UART bridge (default) with a built-in reset/boot/flash +logic or to the USB signals of the ESP32-S2 SoC. The flash method depends on +the configuration of the DIP switches, +see section \ref esp32s2_lilygo_ttgo_t8_pinout "Pinout". + +### USB-C connector is connected to the USB-to-UART bridge (default) + +Just connect the board to your host computer and type using the programming +port: +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +BOARD=esp32s2-liligo-ttgo-t8 make flash ... +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +For detailed information about ESP32-S2 as well as configuring and compiling +RIOT for ESP32-S2 boards, see \ref esp32_riot. + +### USB-C connector is connected to the USB signals of the ESP32-S2 SoC + +In this configuration the integrated USB-to-JTAG bridge can be used to flash +the board. The USB-to-JTAG bridge is automatically activated in the download +mode of the bootloader, provided that the eFuses `JTAG_SEL_ENABLE` and +`DIS_USB_JTAG` are not burned (see also section +\ref esp32_jtag_interface_esp32s2 "JTAG Interface" strapping pin GPIO3). + +For this purpose, connect the board to your host computer and enter the +following command using the programming port: + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +USEMODULE=esp32s2-lilygo-ttgo-t8-usb BOARD=esp32s2-liligo-ttgo-t8 make flash ... +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +If RIOT is already on the device, it should automatically reset the device +and enter the bootloader download mode. If + +- RIOT is not already on the device or +- automatic reset does not work or +- the device is stuck in some other mode, + +the download mode has to be forced before by pressing the Reset (RST) button +while holding the BOOT (BOT) button. + +[Back to table of contents](#esp32s2_lilygo_ttgo_t8_toc) + */ diff --git a/boards/esp32s2-lilygo-ttgo-t8/include/arduino_board.h b/boards/esp32s2-lilygo-ttgo-t8/include/arduino_board.h new file mode 100644 index 0000000000000..0fcca86b5f79a --- /dev/null +++ b/boards/esp32s2-lilygo-ttgo-t8/include/arduino_board.h @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2022 Gunar Schorcht + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup boards_esp32s2_lilygo_ttgo_t8 + * @{ + * + * @file + * @brief Board specific configuration for the Arduino API + * + * @author Gunar Schorcht + */ + +#ifndef ARDUINO_BOARD_H +#define ARDUINO_BOARD_H + +#include "arduino_board_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief The on-board LED is not available + */ +#define ARDUINO_LED (0) + +#ifdef __cplusplus +} +#endif + +#endif /* ARDUINO_BOARD_H */ +/** @} */ diff --git a/boards/esp32s2-lilygo-ttgo-t8/include/arduino_pinmap.h b/boards/esp32s2-lilygo-ttgo-t8/include/arduino_pinmap.h new file mode 100644 index 0000000000000..f1624c5689b92 --- /dev/null +++ b/boards/esp32s2-lilygo-ttgo-t8/include/arduino_pinmap.h @@ -0,0 +1,63 @@ +/* + * Copyright (C) 2022 Gunar Schorcht + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup boards_esp32s2_lilygo_ttgo_t8 + * @{ + * + * @file + * @brief Mapping from MCU pins to Arduino pins + * + * @author Gunar Schorcht + */ + +#ifndef ARDUINO_PINMAP_H +#define ARDUINO_PINMAP_H + +#include "periph/gpio.h" +#include "periph/adc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @name Mapping of MCU pins to Arduino pins + * @{ + */ +#define ARDUINO_PIN_0 GPIO44 /**< Arduino Uno pin 0 (RxD) */ +#define ARDUINO_PIN_1 GPIO43 /**< Arduino Uno pin 1 (TxD) */ +#define ARDUINO_PIN_2 GPIO21 /**< Arduino Uno pin 2 */ +#define ARDUINO_PIN_3 GPIO39 /**< Arduino Uno pin 3 (PWM) */ +#define ARDUINO_PIN_4 GPIO21 /**< Arduino Uno pin 4 */ +#define ARDUINO_PIN_5 GPIO40 /**< Arduino Uno pin 5 (PWM) */ +#define ARDUINO_PIN_6 GPIO41 /**< Arduino Uno pin 6 (PWM) */ +#define ARDUINO_PIN_7 GPIO17 /**< Arduino Uno pin 7 */ +#define ARDUINO_PIN_8 GPIO18 /**< Arduino Uno pin 8 */ +#define ARDUINO_PIN_9 GPIO42 /**< Arduino Uno pin 9 (PWM) */ + +#define ARDUINO_PIN_10 GPIO38 /**< Arduino Uno pin 10 (CS0 / PWM) */ +#define ARDUINO_PIN_11 GPIO35 /**< Arduino Uno pin 11 (MOSI / PWM) */ +#define ARDUINO_PIN_12 GPIO37 /**< Arduino Uno pin 12 (MISO) */ +#define ARDUINO_PIN_13 GPIO36 /**< Arduino Uno pin 13 (SCK) */ + +#define ARDUINO_PIN_A0 GPIO1 /**< Arduino Uno pin A0 */ +#define ARDUINO_PIN_A1 GPIO2 /**< Arduino Uno pin A1 */ +#define ARDUINO_PIN_A2 GPIO4 /**< Arduino Uno pin A2 */ +#define ARDUINO_PIN_A3 GPIO5 /**< Arduino Uno pin A3 */ + +#define ARDUINO_PIN_A4 GPIO7 /**< Arduino Uno pin A4 (SDA) */ +#define ARDUINO_PIN_A5 GPIO8 /**< Arduino Uno pin A5 (SCL) */ +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* ARDUINO_PINMAP_H */ +/** @} */ diff --git a/boards/esp32s2-lilygo-ttgo-t8/include/board.h b/boards/esp32s2-lilygo-ttgo-t8/include/board.h new file mode 100644 index 0000000000000..86d7fdc331373 --- /dev/null +++ b/boards/esp32s2-lilygo-ttgo-t8/include/board.h @@ -0,0 +1,125 @@ +/* + * Copyright (C) 2022 Gunar Schorcht + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup boards_esp32s2_lilygo_ttgo_t8 + * @brief Board definitions for the LILYGO TTGO T8 ESP32-S2 board + * @{ + * + * The board definitions in this file are valid for the LILYGO TTGO T8 ESP32-S2 + * board. + * + * @note + * Most definitions can be overridden by an + * \ref esp32_application_specific_configurations + * "application-specific board configuration" if necessary. + * + * @file + * @author Gunar Schorcht + */ + +#ifndef BOARD_H +#define BOARD_H + +#include + +/** + * @name Button pin definitions + * @{ + */ + +/** + * @brief Default button GPIO pin definition + * + * LILYGO TTGO T8 ESP32-S2 boards have a BOOT button connected to GPIO0, which + * can be used as button during normal operation. Since the GPIO9 pin is pulled up, + * the button signal is inverted, i.e., pressing the button will give a + * low signal. + */ +#define BTN0_PIN GPIO0 + +/** + * @brief Default button GPIO mode definition + * + * Since the GPIO of the button is pulled up with an external resistor, the + * mode for the GPIO pin has to be GPIO_IN. + */ +#define BTN0_MODE GPIO_IN_PU + +/** + * @brief Default interrupt flank definition for the button GPIO + */ +#ifndef BTN0_INT_FLANK +#define BTN0_INT_FLANK GPIO_FALLING +#endif + +/** + * @brief Definition for compatibility with previous versions + */ +#define BUTTON0_PIN BTN0_PIN + +/** @} */ + +/** + * @name SD-Card interface configuration + * + * SD-Card interface uses SPI_DEV(1) on this board. + * @{ + */ +#if (MODULE_SDCARD_SPI) || DOXYGEN +#define SDCARD_SPI_PARAM_SPI SPI_DEV(1) +#define SDCARD_SPI_PARAM_CS SPI1_CS0 +#define SDCARD_SPI_PARAM_CLK SPI1_SCK +#define SDCARD_SPI_PARAM_MOSI SPI1_MOSI +#define SDCARD_SPI_PARAM_MISO SPI1_MISO +#define SDCARD_SPI_PARAM_POWER GPIO_UNDEF +#endif +/** @} */ + +/** + * @name OLED display configuration + * + * OLED display uses SPI_DEV(0) on this board. + * @{ + */ +#if defined(MODULE_ST7735) +#define ST7735_PARAM_SPI SPI_DEV(1) /**< SPI device */ +#define ST7735_PARAM_SPI_CLK SPI_CLK_5MHZ /**< SPI clock frequency */ +#define ST7735_PARAM_SPI_MODE SPI_MODE_0 /**< SPI mode */ +#define ST7735_PARAM_CS GPIO34 /**< Chip Select pin */ +#define ST7735_PARAM_DCX GPIO37 /**< DCX pin */ +#define ST7735_PARAM_RST GPIO38 /**< Reset pin */ +#define ST7735_PARAM_RGB 1 /**< RGB mode enable */ +#define ST7735_PARAM_INVERTED 0 /**< Inverted mode enable */ +#define ST7735_PARAM_NUM_LINES 135U /**< Number of lines */ +#define ST7735_PARAM_RGB_CHANNELS 240U /**< Number of columns */ +#endif +/** @} */ + +/** + * @name Backlight control + * @{ + */ +#define BACKLIGHT_PIN GPIO33 /**< Backlight pin */ +#define BACKLIGHT_ON gpio_set(BACKLIGHT_PIN) /**< Turn backlight on */ +#define BACKLIGHT_OFF gpio_clear(BACKLIGHT_PIN) /**< Turn backlight off */ +/** @} */ + +/* include common board definitions as last step */ +#include "board_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} /* end extern "C" */ +#endif + +#endif /* BOARD_H */ +/** @} */ diff --git a/boards/esp32s2-lilygo-ttgo-t8/include/gpio_params.h b/boards/esp32s2-lilygo-ttgo-t8/include/gpio_params.h new file mode 100644 index 0000000000000..62e5170999430 --- /dev/null +++ b/boards/esp32s2-lilygo-ttgo-t8/include/gpio_params.h @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2018 Gunar Schorcht + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +#ifndef GPIO_PARAMS_H +#define GPIO_PARAMS_H + +/** + * @ingroup boards_esp32s2_lilygo_ttgo_t8 + * @brief Board specific configuration of direct mapped GPIOs + * @file + * @author Gunar Schorcht + * @{ + */ + +#include "board.h" +#include "saul/periph.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief LED and Button configuration + */ +static const saul_gpio_params_t saul_gpio_params[] = +{ + { + .name = "BOOT", + .pin = BTN0_PIN, + .mode = BTN0_MODE, + .flags = SAUL_GPIO_INVERTED + }, +}; + +#ifdef __cplusplus +} +#endif + +#endif /* GPIO_PARAMS_H */ +/** @} */ diff --git a/boards/esp32s2-lilygo-ttgo-t8/include/periph_conf.h b/boards/esp32s2-lilygo-ttgo-t8/include/periph_conf.h new file mode 100644 index 0000000000000..ca0343abcc64c --- /dev/null +++ b/boards/esp32s2-lilygo-ttgo-t8/include/periph_conf.h @@ -0,0 +1,199 @@ +/* + * Copyright (C) 2022 Gunar Schorcht + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup boards_esp32s2_lilygo_ttgo_t8 + * @brief Peripheral configurations for the LILYGO TTGO T8 ESP32-S2 board + * @{ + * + * The peripheral configurations in this file can be used for the + * LILYGO TTGO T8 ESP32-S2 board. + * + * For detailed information about the peripheral configuration for ESP32-S2 + * boards, see section \ref esp32_peripherals "Common Peripherals". + * + * @note + * Most definitions can be overridden by an + * \ref esp32_application_specific_configurations + * "application-specific board configuration" if necessary. + * + * @file + * @author Gunar Schorcht + */ + +#ifndef PERIPH_CONF_H +#define PERIPH_CONF_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @name ADC and DAC channel configuration + * @{ + */ +/** + * @brief Declaration of GPIOs that can be used as ADC channels + * + * All ADC pins of ADC1 that are broken out are declared as ADC channels except + * GPIO3 which is a strapping pin. GPIO7 and GPIO8 are also used by `I2C_DEV(0)` + * if enabled. GPIO9 is not broken out and used to measure V_BAT. + * + * @note As long as the GPIOs listed in ADC_GPIOS are not initialized as ADC + * channels with the `adc_init` function, they can be used for other + * purposes. + */ +#ifndef ADC_GPIOS +#define ADC_GPIOS { GPIO1, GPIO2, GPIO4, GPIO5, GPIO6, GPIO7, GPIO8, GPIO9 } +#endif + +/** + * @brief Declaration of GPIOs that can be used as DAC channels + * + * @note As long as the GPIOs listed in DAC_GPIOS are not initialized as DAC + * channels with the `dac_init` function, they can be used for other + * purposes. + */ +#ifndef DAC_GPIOS +#define DAC_GPIOS { GPIO17, GPIO18 } +#endif +/** @} */ + +/** + * @name I2C configuration + * + * Only one I2C interface I2C_DEV(0) is defined. + * + * The GPIOs listed in the configuration are only initialized as I2C signals + * when module `periph_i2c` is used. Otherwise they are not allocated and + * can be used for other purposes. + * + * @{ + */ +#ifndef I2C0_SPEED +#define I2C0_SPEED I2C_SPEED_FAST /**< I2C bus speed of I2C_DEV(0) */ +#endif +#ifndef I2C0_SCL +#define I2C0_SCL GPIO7 /**< SCL signal of I2C_DEV(0) */ +#endif +#ifndef I2C0_SDA +#define I2C0_SDA GPIO8 /**< SDA signal of I2C_DEV(0) */ +#endif +/** @} */ + +/** + * @name PWM channel configuration + * + * Two PWM devices are configured. These devices + * contain all GPIOs that are not defined as I2C, SPI or UART for this board. + * Generally, all outputs pins could be used as PWM channels. + * + * @note As long as the according PWM device is not initialized with + * the `pwm_init`, the GPIOs declared for this device can be used + * for other purposes. + * + * @{ + */ + +/** + * @brief Declaration of the channels for device PWM_DEV(0), + * at maximum PWM_CHANNEL_NUM_DEV_MAX. + */ +#ifndef PWM0_GPIOS +#define PWM0_GPIOS { GPIO39, GPIO40, GPIO41, GPIO42 } +#endif + +/** + * @brief Declaration of the channels for device PWM_DEV(1), + * at maximum PWM_CHANNEL_NUM_DEV_MAX. + * + * These PWM channels cannot be used if an external 32 kHz crystal is + * connected to the board at GPIO15 and GPIO16 (configured by the DIP switches). + */ +#ifndef MODULE_ESP_RTC_TIMER_32K +#ifndef PWM1_GPIOS +#define PWM1_GPIOS { GPIO15, GPIO16 } +#endif +#endif + +/** @} */ + +/** + * @name SPI configuration + * + * SPI_DEV(0) is used for the Display. The GPIOs are not broken out.
+ * SPI_DEV(1) is used for the SD Card slot. The GPIOs are broken out and can + * also be used by other devices. + * + * @note The GPIOs listed in the configuration are first initialized as SPI + * signals when the corresponding SPI interface is used for the first time + * by either calling the `spi_init_cs` function or the `spi_acquire` + * function. That is, they are not allocated as SPI signals before and can + * be used for other purposes as long as the SPI interface is not used. + * @{ + */ + +#ifndef SPI0_CTRL +#define SPI0_CTRL FSPI /**< FSPI (SPI Controller 2) is used as SPI_DEV(0) */ +#endif +#ifndef SPI0_SCK +#define SPI0_SCK GPIO36 /**< FSPICLK used as signal `OLED_CLK` */ +#endif +#ifndef SPI0_MISO +#define SPI0_MISO GPIO37 /**< FSPIQ used as Display signal `OLED_MISO` */ +#endif +#ifndef SPI0_MOSI +#define SPI0_MOSI GPIO35 /**< FSPID used as Display signal `OLED_MOSI` */ +#endif +#ifndef SPI0_CS0 +#define SPI0_CS0 GPIO34 /**< FSPICS0 used as Display signal `OLED_CS` */ +#endif + +#ifndef SPI1_CTRL +#define SPI1_CTRL HSPI /**< HSPI (SPI Controller 3) is used as SPI_DEV(1) */ +#endif +#ifndef SPI1_SCK +#define SPI1_SCK GPIO12 /**< SPI SCK */ +#endif +#ifndef SPI1_MISO +#define SPI1_MISO GPIO13 /**< SPI MISO */ +#endif +#ifndef SPI1_MOSI +#define SPI1_MOSI GPIO11 /**< SPI MOSI */ +#endif +#ifndef SPI1_CS0 +#define SPI1_CS0 GPIO10 /**< SPI CS0 used for Display */ +#endif +/** @} */ + +/** + * @name UART configuration + * + * ESP32-S2 provides 2 UART interfaces at maximum: + * + * UART_DEV(0) uses fixed standard configuration.
+ * UART_DEV(1) is not used.
+ * + * @{ + */ +#define UART0_TXD GPIO43 /**< direct I/O pin for UART_DEV(0) TxD, can't be changed */ +#define UART0_RXD GPIO44 /**< direct I/O pin for UART_DEV(0) RxD, can't be changed */ + +/** @} */ + +#ifdef __cplusplus +} /* end extern "C" */ +#endif + +/* include common peripheral definitions as last step */ +#include "periph_conf_common.h" + +#endif /* PERIPH_CONF_H */ +/** @} */ diff --git a/cpu/esp32/doc.txt b/cpu/esp32/doc.txt index 5654cb4115505..6c92a80f73901 100644 --- a/cpu/esp32/doc.txt +++ b/cpu/esp32/doc.txt @@ -858,7 +858,7 @@ as DAC channels with the #dac_init function, they can be used for other purposes. DACs are currently only supported for the \ref esp32_dac_channels_esp32 -"ESP32 SoC" variant. +"ESP32 SoC" and the \ref esp32_dac_channels_esp32s2 "ESP32-S2 SoC" variant. [Back to table of contents](#esp32_toc) @@ -1561,8 +1561,8 @@ Furthermore, the following configuration parameters have to be defined: Parameter | Default | Description :-------------------|:--------------------------|:------------ -#ESP_WIFI_SSID | "RIOT_AP" | SSID of the AP to be used. -#ESP_WIFI_PASS | - | Passphrase used for the AP as clear text (max. 64 chars). +#WIFI_SSID | "RIOT_AP" | SSID of the AP to be used. +#WIFI_PASS | - | Passphrase used for the AP as clear text (max. 64 chars). #ESP_WIFI_STACKSIZE | #THREAD_STACKSIZE_DEFAULT | Stack size used for the WiFi netdev driver thread.
@@ -1573,14 +1573,14 @@ line, for example: ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ USEMODULE=esp_wifi \ -CFLAGS='-DESP_WIFI_SSID=\"MySSID\" -DESP_WIFI_PASS=\"MyPassphrase\"' \ +CFLAGS='-DWIFI_SSID=\"MySSID\" -DWIFI_PASS=\"MyPassphrase\"' \ make -C examples/gnrc_networking BOARD=... ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @note - Module `esp_wifi` is not enabled automatically when module `netdev_default` is used. -- Leave 'ESP_WIFI_PASS' undefined to connect to an open WiFi access point. +- Leave 'WIFI_PASS' undefined to connect to an open WiFi access point. - The Wifi network interface (module `esp_wifi`) and the [ESP-NOW network interface](#esp32_esp_now_network_interface) (module `esp_now`) can be used simultaneously, for example, to realize a border router for @@ -1612,16 +1612,16 @@ following configuration parameters have to be defined: Parameter | Default | Description :-------------------|:----------|:------------ -#ESP_WIFI_SSID | "RIOT_AP" | SSID of the AP to be used. -ESP_WIFI_EAP_ID | none | Optional anonymous identity used in phase 1 (outer) EAP authentication.[1] -ESP_WIFI_EAP_USER | none | User name used in phase 2 (inner) EAP authentication. -ESP_WIFI_EAP_PASS | none | Password used in phase 2 (inner) EAP authentication. +#WIFI_SSID | "RIOT_AP" | SSID of the AP to be used. +WIFI_EAP_ID | none | Optional anonymous identity used in phase 1 (outer) EAP authentication.[1] +WIFI_EAP_USER | none | User name used in phase 2 (inner) EAP authentication. +WIFI_EAP_PASS | none | Password used in phase 2 (inner) EAP authentication. #ESP_WIFI_STACKSIZE | #THREAD_STACKSIZE_DEFAULT | Stack size used for the WiFi netdev driver thread.
-[1] If the optional anonymous identy `ESP_WIFI_EAP_ID` is not defined, the user -name `ESP_WIFI_EAP_USER` defined for phase 2 (inner) EAP authentication is used +[1] If the optional anonymous identy `WIFI_EAP_ID` is not defined, the user +name `WIFI_EAP_USER` defined for phase 2 (inner) EAP authentication is used as identity in phase 1. These configuration parameter definitions, as well as enabling the `esp_wifi` @@ -1630,7 +1630,7 @@ line, for example: ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ USEMODULE=esp_wifi_enterprise \ -CFLAGS='-DESP_WIFI_SSID=\"MySSID\" -DESP_WIFI_EAP_ID=\"anonymous\" -DESP_WIFI_EAP_USER=\"MyUserName\" -DESP_WIFI_EAP_PASS=\"MyPassphrase\"' \ +CFLAGS='-DWIFI_SSID=\"MySSID\" -DWIFI_EAP_ID=\"anonymous\" -DWIFI_EAP_USER=\"MyUserName\" -DWIFI_EAP_PASS=\"MyPassphrase\"' \ make -C examples/gnrc_networking BOARD=... ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -1660,8 +1660,8 @@ The following parameters can be configured: Parameter | Default | Description :-------------------------|:--------------------------|:------------- -#ESP_WIFI_SSID | "RIOT_AP" | Static SSID definition for the SoftAP -#ESP_WIFI_PASS | none | The password for the WiFi SoftAP network interface.[1] +#WIFI_SSID | "RIOT_AP" | Static SSID definition for the SoftAP +#WIFI_PASS | none | The password for the WiFi SoftAP network interface.[1] #ESP_WIFI_SSID_DYNAMIC | 0 | Defines whether dynamic SSID is used for the SoftAP [2]. #ESP_WIFI_SSID_HIDDEN | 0 | Defines whether the SoftAP SSID should be hidden. #ESP_WIFI_MAX_CONN | 4 | The maximum number of connections for the SoftAP. @@ -1673,7 +1673,7 @@ Parameter | Default | Description [1] If no password is provided, the interface will be "open", otherwise it uses WPA2-PSK authentication mode.
[2] If `#ESP_WIFI_SSID_DYNAMIC` is set to 1, a dynamic SSID is generated for the - SoftAP by extending the defined SSID (`ESP_WIFI_SSID`) with the MAC address + SoftAP by extending the defined SSID (`WIFI_SSID`) with the MAC address of the SoftAP interface used, e.g.: `RIOT_AP_aabbccddeeff` These configuration parameter definitions, as well as enabling the `esp_wifi_ap` @@ -1682,7 +1682,7 @@ line, for example: ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ USEMODULE=esp_wifi_ap \ -CFLAGS='-DESP_WIFI_SSID=\"MySSID\" -DESP_WIFI_PASS=\"MyPassphrase\" -DESP_WIFI_MAX_CONN=1' \ +CFLAGS='-DWIFI_SSID=\"MySSID\" -DWIFI_PASS=\"MyPassphrase\" -DESP_WIFI_MAX_CONN=1' \ make -C examples/gnrc_networking BOARD=... ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/cpu/esp32/doc_esp32s2.txt b/cpu/esp32/doc_esp32s2.txt index 7f874b7714e03..0a0d480ad6702 100644 --- a/cpu/esp32/doc_esp32s2.txt +++ b/cpu/esp32/doc_esp32s2.txt @@ -91,8 +91,8 @@ GPIO13 | In/Out | X | X | X | - | - GPIO14 | In/Out | X | X | X | - | - GPIO15 | In/Out | X | X | X | XTAL_32K_P | External 32k crystal GPIO16 | In/Out | X | X | X | XTAL_32K_N | External 32k crystal -GPIO17 | In/Out | X | X | X | - | - -GPIO18 | In/Out | X | X | X | - | - +GPIO17 | In/Out | X | X | X | DAC1 | - +GPIO18 | In/Out | X | X | X | DAC2 | - GPIO19 | In/Out | X | X | X | USB D- | USB 2.0 OTG / USB-JTAG bridge GPIO20 | In/Out | X | X | X | USB D+ | USB 2.0 OTG / USB-JTAG bridge GPIO21 | In/Out | - | X | X | - | - @@ -174,6 +174,10 @@ total: that is at GPIO11 ... GPIO20. - GPIO3 is a strapping pin und shouldn't be used as ADC channel +## DAC Channels {#esp32_dac_channels_esp32s2} + +ESP32 SoC supports 2 DAC lines at GPIO17 and GPIO18. + ## I2C Interfaces {#esp32_i2c_interfaces_esp32s2} ESP32-S2 has two built-in I2C interfaces. diff --git a/cpu/esp8266/doc.txt b/cpu/esp8266/doc.txt index e451fa6d2335a..2c084e2175e48 100644 --- a/cpu/esp8266/doc.txt +++ b/cpu/esp8266/doc.txt @@ -717,8 +717,8 @@ Furthermore, the following configuration parameters have to be defined: Parameter | Default | Description :-------------------|:--------------------------|:------------ -#ESP_WIFI_SSID | "RIOT_AP" | SSID of the AP to be used. -#ESP_WIFI_PASS | - | Passphrase used for the AP as clear text (max. 64 chars). +#WIFI_SSID | "RIOT_AP" | SSID of the AP to be used. +#WIFI_PASS | - | Passphrase used for the AP as clear text (max. 64 chars). #ESP_WIFI_STACKSIZE | #THREAD_STACKSIZE_DEFAULT |Stack size used for the WiFi netdev driver thread. @@ -729,14 +729,14 @@ line, e.g.: ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ USEMODULE=esp_wifi \ -CFLAGS='-DESP_WIFI_SSID=\"MySSID\" -DESP_WIFI_PASS=\"MyPassphrase\"' \ +CFLAGS='-DWIFI_SSID=\"MySSID\" -DWIFI_PASS=\"MyPassphrase\"' \ make -C examples/gnrc_networking BOARD=... ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @note - Module `esp_wifi` is not enabled automatically when module `netdev_default` is used. -- Leave `ESP_WIFI_PASS` undefined to connect to an open WiFi access point. +- Leave `WIFI_PASS` undefined to connect to an open WiFi access point. - The Wifi network interface (module `esp_wifi`) and the [ESP-NOW network interface](#esp8266_esp_now_network_interface) (module `esp_now`) can be used simultaneously, for example, to realize a @@ -758,8 +758,8 @@ The following parameters can be configured: Parameter | Default | Description :-------------------------|:--------------------------|:------------- -#ESP_WIFI_SSID | "RIOT_AP" | Static SSID definition for the SoftAP -#ESP_WIFI_PASS | none | The password for the WiFi SoftAP network interface.[1] +#WIFI_SSID | "RIOT_AP" | Static SSID definition for the SoftAP +#WIFI_PASS | none | The password for the WiFi SoftAP network interface.[1] #ESP_WIFI_SSID_DYNAMIC | 0 | Defines whether dynamic SSID is used for the SoftAP [2]. #ESP_WIFI_SSID_HIDDEN | 0 | Defines whether the SoftAP SSID should be hidden. #ESP_WIFI_MAX_CONN | 4 | The maximum number of connections for the SoftAP. @@ -771,7 +771,7 @@ Parameter | Default | Description [1] If no password is provided, the interface will be "open", otherwise it uses WPA2-PSK authentication mode.
[2] If #ESP_WIFI_SSID_DYNAMIC is set to 1, a dynamic SSID is generated for the - SoftAP by extending the defined SSID (`ESP_WIFI_SSID`) with the MAC address + SoftAP by extending the defined SSID (`WIFI_SSID`) with the MAC address of the SoftAP interface used, e.g.: `RIOT_AP_aabbccddeeff` These configuration parameter definitions, as well as enabling the `esp_wifi_ap` @@ -780,7 +780,7 @@ line, for example: ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ USEMODULE=esp_wifi_ap \ -CFLAGS='-DESP_WIFI_SSID=\"MySSID\" -DESP_WIFI_PASS=\"MyPassphrase\" -DESP_WIFI_MAX_CONN=1' \ +CFLAGS='-DWIFI_SSID=\"MySSID\" -DWIFI_PASS=\"MyPassphrase\" -DESP_WIFI_MAX_CONN=1' \ make -C examples/gnrc_networking BOARD=... ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/cpu/esp_common/esp-wifi/doc.txt b/cpu/esp_common/esp-wifi/doc.txt index 670698cfb5099..16eba4936d4fb 100644 --- a/cpu/esp_common/esp-wifi/doc.txt +++ b/cpu/esp_common/esp-wifi/doc.txt @@ -38,8 +38,8 @@ Furthermore, the following configuration parameters have to be defined: Parameter | Default | Description :------------------|:--------------------------|:------------ -ESP_WIFI_SSID | "RIOT_AP" | SSID of the AP to be used. -ESP_WIFI_PASS | - | Passphrase used for the AP as clear text (max. 64 chars). +WIFI_SSID | "RIOT_AP" | SSID of the AP to be used. +WIFI_PASS | - | Passphrase used for the AP as clear text (max. 64 chars). ESP_WIFI_STACKSIZE | #THREAD_STACKSIZE_DEFAULT | Stack size used for the WiFi netdev driver thread. @@ -50,14 +50,14 @@ line, for example: ``` USEMODULE=esp_wifi \ -CFLAGS='-DESP_WIFI_SSID=\"MySSID\" -DESP_WIFI_PASS=\"MyPassphrase\"' \ +CFLAGS='-DWIFI_SSID=\"MySSID\" -DWIFI_PASS=\"MyPassphrase\"' \ make -C examples/gnrc_networking BOARD=... ``` @note - Module `esp_wifi` is not enabled automatically when module `netdev_default` is used. -- Leave 'ESP_WIFI_PASS' undefined to connect to an open WiFi access point. +- Leave 'WIFI_PASS' undefined to connect to an open WiFi access point. - The Wifi network interface (module `esp_wifi`) and the ESP-NOW network interface (module `esp_now`) can be used simultaneously, for example, to realize a border router for @@ -87,10 +87,10 @@ following configuration parameters have to be defined: Parameter | Default | Description :------------------|:----------|:------------ -ESP_WIFI_SSID | "RIOT_AP" | SSID of the AP to be used. -ESP_WIFI_EAP_ID | none | Optional anonymous identity used in phase 1 (outer) EAP authentication. If it is not defined, the user name defined for phase 2 (inner) EAP authentication is used as idendity in phase 1. -ESP_WIFI_EAP_USER | none | User name used in phase 2 (inner) EAP authentication. -ESP_WIFI_EAP_PASS | none | Password used in phase 2 (inner) EAP authentication. +WIFI_SSID | "RIOT_AP" | SSID of the AP to be used. +WIFI_EAP_ID | none | Optional anonymous identity used in phase 1 (outer) EAP authentication. If it is not defined, the user name defined for phase 2 (inner) EAP authentication is used as idendity in phase 1. +WIFI_EAP_USER | none | User name used in phase 2 (inner) EAP authentication. +WIFI_EAP_PASS | none | Password used in phase 2 (inner) EAP authentication. ESP_WIFI_STACKSIZE | #THREAD_STACKSIZE_DEFAULT | Stack size used for the WiFi netdev driver thread. @@ -101,7 +101,7 @@ line, for example: ``` USEMODULE=esp_wifi_enterprise \ -CFLAGS='-DESP_WIFI_SSID=\"MySSID\" -DESP_WIFI_EAP_ID=\"anonymous\" -DESP_WIFI_EAP_USER=\"MyUserName\" -DESP_WIFI_EAP_PASS=\"MyPassphrase\"' \ +CFLAGS='-DWIFI_SSID=\"MySSID\" -DWIFI_EAP_ID=\"anonymous\" -DWIFI_EAP_USER=\"MyUserName\" -DWIFI_EAP_PASS=\"MyPassphrase\"' \ make -C examples/gnrc_networking BOARD=... ``` diff --git a/cpu/esp_common/esp-wifi/esp_wifi_netdev.c b/cpu/esp_common/esp-wifi/esp_wifi_netdev.c index f496e2d83afc3..c32a828390a5a 100644 --- a/cpu/esp_common/esp-wifi/esp_wifi_netdev.c +++ b/cpu/esp_common/esp-wifi/esp_wifi_netdev.c @@ -797,9 +797,9 @@ static const netdev_driver_t _esp_wifi_driver = */ static wifi_config_t wifi_config_sta = { .sta = { - .ssid = ESP_WIFI_SSID, -#if !defined(MODULE_ESP_WIFI_ENTERPRISE) && defined(ESP_WIFI_PASS) - .password = ESP_WIFI_PASS, + .ssid = WIFI_SSID, +#if !defined(MODULE_ESP_WIFI_ENTERPRISE) && defined(WIFI_PASS) + .password = WIFI_PASS, #endif .channel = 0, .scan_method = WIFI_ALL_CHANNEL_SCAN, @@ -830,12 +830,12 @@ static wifi_config_t wifi_config_sta = { */ static wifi_config_t wifi_config_ap = { .ap = { -#ifdef ESP_WIFI_SSID - .ssid = ESP_WIFI_SSID, - .ssid_len = ARRAY_SIZE(ESP_WIFI_SSID) - 1, +#ifdef WIFI_SSID + .ssid = WIFI_SSID, + .ssid_len = sizeof(WIFI_SSID) - 1, #endif -#ifdef ESP_WIFI_PASS - .password = ESP_WIFI_PASS, +#ifdef WIFI_PASS + .password = WIFI_PASS, .authmode = WIFI_AUTH_WPA2_PSK, #else .authmode = WIFI_AUTH_OPEN, @@ -923,7 +923,7 @@ void esp_wifi_setup (esp_wifi_netdev_t* dev) uint8_t mac[ETHERNET_ADDR_LEN]; esp_wifi_get_mac(ESP_MAC_WIFI_SOFTAP, mac); sprintf((char*)wifi_config_ap.ap.ssid, "%s_%02x%02x%02x%02x%02x%02x", - ESP_WIFI_SSID, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); + WIFI_SSID, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); wifi_config_ap.ap.ssid_len = strlen((char*)wifi_config_ap.ap.ssid); #endif /* IS_ACTIVE(ESP_WIFI_SSID_DYNAMIC) */ /* set the SoftAP configuration */ @@ -947,20 +947,32 @@ void esp_wifi_setup (esp_wifi_netdev_t* dev) #if defined(MODULE_ESP_WIFI_ENTERPRISE) && !defined(MODULE_ESP_WIFI_AP) -#ifdef ESP_WIFI_EAP_ID - esp_wifi_sta_wpa2_ent_set_identity((const unsigned char *)ESP_WIFI_EAP_ID, - strlen(ESP_WIFI_EAP_ID)); -#endif /* ESP_WIFI_EAP_ID */ -#if defined(ESP_WIFI_EAP_USER) && defined(ESP_WIFI_EAP_PASS) +#if !defined(WIFI_EAP_ID) && defined(ESP_WIFI_EAP_ID) +#define WIFI_EAP_ID ESP_WIFI_EAP_ID +#endif + +#if !defined(WIFI_EAP_USER) && defined(ESP_WIFI_EAP_USER) +#define WIFI_EAP_USER ESP_WIFI_EAP_USER +#endif + +#if !defined(WIFI_EAP_PASS) && defined(ESP_WIFI_EAP_PASS) +#define WIFI_EAP_PASS ESP_WIFI_EAP_PASS +#endif + +#ifdef WIFI_EAP_ID + esp_wifi_sta_wpa2_ent_set_identity((const unsigned char *)WIFI_EAP_ID, + strlen(WIFI_EAP_ID)); +#endif /* WIFI_EAP_ID */ +#if defined(WIFI_EAP_USER) && defined(WIFI_EAP_PASS) ESP_WIFI_DEBUG("eap_user=%s eap_pass=%s\n", - ESP_WIFI_EAP_USER, ESP_WIFI_EAP_PASS); - esp_wifi_sta_wpa2_ent_set_username((const unsigned char *)ESP_WIFI_EAP_USER, - strlen(ESP_WIFI_EAP_USER)); - esp_wifi_sta_wpa2_ent_set_password((const unsigned char *)ESP_WIFI_EAP_PASS, - strlen(ESP_WIFI_EAP_PASS)); -#else /* defined(ESP_WIFI_EAP_USER) && defined(ESP_WIFI_EAP_PASS) */ -#error "ESP_WIFI_EAP_USER and ESP_WIFI_EAP_PASS have to be defined for EAP phase 2 authentication" -#endif /* defined(ESP_WIFI_EAP_USER) && defined(ESP_WIFI_EAP_PASS) */ + WIFI_EAP_USER, WIFI_EAP_PASS); + esp_wifi_sta_wpa2_ent_set_username((const unsigned char *)WIFI_EAP_USER, + strlen(WIFI_EAP_USER)); + esp_wifi_sta_wpa2_ent_set_password((const unsigned char *)WIFI_EAP_PASS, + strlen(WIFI_EAP_PASS)); +#else /* defined(WIFI_EAP_USER) && defined(WIFI_EAP_PASS) */ +#error "WIFI_EAP_USER and WIFI_EAP_PASS have to be defined for EAP phase 2 authentication" +#endif /* defined(WIFI_EAP_USER) && defined(WIFI_EAP_PASS) */ esp_wifi_sta_wpa2_ent_enable(); #endif /* defined(MODULE_ESP_WIFI_ENTERPRISE) && !defined(MODULE_ESP_WIFI_AP) */ diff --git a/cpu/esp_common/esp-wifi/esp_wifi_params.h b/cpu/esp_common/esp-wifi/esp_wifi_params.h index 60c30ac1b9260..a9d862b255f17 100644 --- a/cpu/esp_common/esp-wifi/esp_wifi_params.h +++ b/cpu/esp_common/esp-wifi/esp_wifi_params.h @@ -44,15 +44,23 @@ /** * @brief SSID of the AP to be used. */ -#ifndef ESP_WIFI_SSID -#define ESP_WIFI_SSID "RIOT_AP" +#ifndef WIFI_SSID +#ifdef ESP_WIFI_SSID +#define WIFI_SSID ESP_WIFI_SSID +#else +#define WIFI_SSID "RIOT_AP" +#endif #endif /** * @brief Passphrase used for the AP as clear text (max. 64 chars). */ #ifdef DOXYGEN -#define ESP_WIFI_PASS "ThisistheRIOTporttoESP" +#define WIFI_PASS "ThisistheRIOTporttoESP" +#endif + +#if !defined(WIFI_PASS) && defined(ESP_WIFI_PASS) +#define WIFI_PASS ESP_WIFI_PASS #endif #if defined(MODULE_ESP_WIFI_AP) || defined(DOXYGEN) @@ -61,7 +69,7 @@ * @brief Use dynamic SSID for the SoftAP * * If set to 1, the SSID for the SoftAP is generated dynamically by extending - * the defined SSID (`ESP_WIFI_SSID`) with the MAC address of the SoftAP + * the defined SSID (`WIFI_SSID`) with the MAC address of the SoftAP * interface used, e.g.: `RIOT_AP_aabbccddeeff` */ #ifndef ESP_WIFI_SSID_DYNAMIC diff --git a/cpu/gd32v/Kconfig b/cpu/gd32v/Kconfig index 6bdde87cc361a..e732c6eb85b0e 100644 --- a/cpu/gd32v/Kconfig +++ b/cpu/gd32v/Kconfig @@ -30,6 +30,7 @@ config CPU_FAM_GD32V select MODULE_PERIPH_CLIC if TEST_KCONFIG select MODULE_PERIPH_WDT if MODULE_PERIPH_PM && HAS_PERIPH_WDT + select MODULE_ZTIMER_USEC if MODULE_PERIPH_I2C select PACKAGE_NMSIS_SDK menu "GD32V configuration" diff --git a/cpu/gd32v/Makefile.dep b/cpu/gd32v/Makefile.dep index 578c9c82d2213..21499ed6185cf 100644 --- a/cpu/gd32v/Makefile.dep +++ b/cpu/gd32v/Makefile.dep @@ -7,4 +7,8 @@ ifneq (,$(filter periph_pm,$(USEMODULE))) FEATURES_REQUIRED += periph_wdt endif +ifneq (,$(filter periph_i2c,$(USEMODULE))) + USEMODULE += ztimer_usec +endif + include $(RIOTCPU)/riscv_common/Makefile.dep diff --git a/cpu/gd32v/include/periph_cpu.h b/cpu/gd32v/include/periph_cpu.h index 84aceead84521..9051edb42d482 100644 --- a/cpu/gd32v/include/periph_cpu.h +++ b/cpu/gd32v/include/periph_cpu.h @@ -397,7 +397,7 @@ typedef struct { gpio_t scl_pin; /**< scl pin number */ gpio_t sda_pin; /**< sda pin number */ uint32_t rcu_mask; /**< bit in clock enable register */ - uint8_t irqn; /**< I2C event interrupt number */ + IRQn_Type irqn; /**< I2C event interrupt number */ } i2c_conf_t; /** diff --git a/cpu/gd32v/periph/i2c.c b/cpu/gd32v/periph/i2c.c index dc98f92f3a19f..9917f225fc535 100644 --- a/cpu/gd32v/periph/i2c.c +++ b/cpu/gd32v/periph/i2c.c @@ -1,9 +1,5 @@ /* - * Copyright (C) 2017 Kaspar Schleiser - * 2014 FU Berlin - * 2018 Inria - * 2018 HAW Hamburg - * 2023 Gunar Schorcht + * Copyright (C) 2023 Gunar Schorcht * * This file is subject to the terms and conditions of the GNU Lesser * General Public License v2.1. See the file LICENSE in the top level @@ -16,21 +12,8 @@ * @{ * * @file - * @brief Low-level I2C driver implementation + * @brief Low-level I2C driver implementation for GD32VF103 * - * This driver is a modified copy of the I2C driver for the STM32F1 family. - * - * @note This implementation only implements the 7-bit addressing polling mode. - * - * @author Peter Kietzmann - * @author Hauke Petersen - * @author Thomas Eichinger - * @author Kaspar Schleiser - * @author Toon Stegen - * @author Vincent Dupont - * @author Víctor Ariño - * @author Alexandre Abadie - * @author Kevin Weiss * @author Gunar Schorcht * * @} @@ -43,49 +26,80 @@ #include "cpu.h" #include "irq.h" #include "mutex.h" +#ifdef MODULE_PM_LAYERED #include "pm_layered.h" +#endif #include "panic.h" #include "periph/i2c.h" #include "periph/gpio.h" #include "periph_conf.h" +#include "ztimer.h" -/* Some DEBUG statements may cause delays that alter i2c functionality */ -#define ENABLE_DEBUG 0 +#define ENABLE_DEBUG 0 #include "debug.h" -#define TICK_TIMEOUT (0xFFFF) +#define I2C_TIMEOUT_CYCLES 1000 /* clock cycles */ +#define I2C_IRQ_PRIO (1) -#define I2C_IRQ_PRIO (1) -#define I2C_FLAG_READ (I2C_READ) -#define I2C_FLAG_WRITE (0) +#define I2C_ERROR_FLAGS_USED (I2C_STAT0_AERR_Msk | I2C_STAT0_LOSTARB_Msk | \ + I2C_STAT0_BERR_Msk) +#define I2C_ERROR_FLAGS_OTHER (I2C_STAT0_OUERR_Msk | I2C_STAT0_PECERR_Msk | \ + I2C_STAT0_SMBTO_Msk | I2C_STAT0_SMBALT_Msk) +#define I2C_ERROR_FLAGS (I2C_ERROR_FLAGS_USED | I2C_ERROR_FLAGS_OTHER) -#define ERROR_FLAGS (I2C_STAT0_AERR_Msk | I2C_STAT0_LOSTARB_Msk | I2C_STAT0_BERR_Msk) +#define I2C_INT_EV_ERR_FLAGS (I2C_CTL1_EVIE_Msk | I2C_CTL1_ERRIE_Msk) +#define I2C_INT_ALL_FLAGS (I2C_CTL1_BUFIE_Msk | I2C_INT_EV_ERR_FLAGS) /* static function definitions */ static void _init(i2c_t dev); static void _init_pins(i2c_t dev); static void _init_clk(I2C_Type *i2c, uint32_t speed); static void _deinit_pins(i2c_t dev); - -static int _start(I2C_Type *dev, uint8_t address_byte, uint8_t flags, - size_t length); -static int _stop(I2C_Type *dev); - -static int _is_sr1_mask_set(I2C_Type *i2c, uint32_t mask, uint8_t flags); -static inline int _wait_for_bus(I2C_Type *i2c); - -/** - * @brief Array holding one pre-initialized mutex for each I2C device - */ -static mutex_t locks[I2C_NUMOF]; +static int _wait_for_bus(i2c_t dev); +static void _wait_for_irq(i2c_t dev); +static void _irq_handler(unsigned irqn); + +typedef enum { + I2C_OK, + I2C_START_SENT, + I2C_ADDR_SENT, + I2C_ADDR10_SENT, + I2C_BT_COMPLETE, + I2C_TXB_EMPTY, + I2C_RXB_NOT_EMPTY, + I2C_RXB_NOT_EMPTY_BT_COMPLETE, + I2C_TIMEOUT, + I2C_ACK_ERR, + I2C_ARB_LOST, + I2C_BUS_ERROR, + I2C_OTHER_ERROR, +} _i2c_state_t; + +typedef struct { + mutex_t dev_lock; + mutex_t irq_lock; + _i2c_state_t state; + void (*isr)(unsigned irqn); +} _i2c_dev_t; + +_i2c_dev_t _i2c_dev[] = { + { + .dev_lock = MUTEX_INIT, + .irq_lock = MUTEX_INIT_LOCKED, + .state = I2C_OK, + }, + { + .dev_lock = MUTEX_INIT, + .irq_lock = MUTEX_INIT_LOCKED, + .state = I2C_OK, + }, +}; void i2c_init(i2c_t dev) { assert(dev < I2C_NUMOF); - mutex_init(&locks[dev]); - assert(i2c_config[dev].dev != NULL); /* Configure pins in idle state as open drain outputs to keep the bus lines @@ -94,9 +108,16 @@ void i2c_init(i2c_t dev) periph_clk_en(APB1, i2c_config[dev].rcu_mask); + /* enable set event interrupt handler and enable the event interrupt */ + clic_set_handler(i2c_config[dev].irqn, _irq_handler); + clic_enable_interrupt(i2c_config[dev].irqn, CPU_DEFAULT_IRQ_PRIO); + /* enable set error interrupt handler and enable the error interrupt */ + clic_set_handler(i2c_config[dev].irqn + 1, _irq_handler); + clic_enable_interrupt(i2c_config[dev].irqn + 1, CPU_DEFAULT_IRQ_PRIO); + _init(dev); - periph_clk_dis(APB1, i2c_config[dev].rcu_mask); + _i2c_dev[dev].state = I2C_OK; } static void _init_pins(i2c_t dev) @@ -121,11 +142,8 @@ static void _init_clk(I2C_Type *i2c, uint32_t speed) i2c->CTL1 = (CLOCK_APB1 / MHZ(1)) | I2C_CTL1_ERRIE_Msk; i2c->CKCFG = CLOCK_APB1 / (2 * speed); i2c->RT = (CLOCK_APB1 / 1000000) + 1; - /* configure device */ - i2c->SADDR0 |= (1 << 14); /* datasheet: bit 14 should be kept 1 */ - i2c->SADDR0 &= ~I2C_SADDR0_ADDFORMAT_Msk; /* make sure we are in 7-bit address mode */ /* Clear flags */ - i2c->STAT0 &= ~ERROR_FLAGS; + i2c->STAT0 &= ~I2C_ERROR_FLAGS; /* enable device */ i2c->CTL0 |= I2C_CTL0_I2CEN_Msk; } @@ -155,7 +173,8 @@ void i2c_acquire(i2c_t dev) { assert(dev < I2C_NUMOF); - mutex_lock(&locks[dev]); + /* lock the device */ + mutex_lock(&_i2c_dev[dev].dev_lock); /* block DEEP_SLEEP mode */ pm_block(GD32V_PM_DEEPSLEEP); @@ -174,9 +193,9 @@ void i2c_release(i2c_t dev) assert(dev < I2C_NUMOF); /* disable device */ - i2c_config[dev].dev->CTL0 &= ~(I2C_CTL0_I2CEN_Msk); + i2c_config[dev].dev->CTL0 &= ~I2C_CTL0_I2CEN_Msk; - _wait_for_bus(i2c_config[dev].dev); + _wait_for_bus(dev); /* Disabling the clock switches off the I2C controller, which results in * LOW bus lines. To avoid that the used GPIOs then draw some milliamps @@ -189,18 +208,210 @@ void i2c_release(i2c_t dev) /* unblock DEEP_SLEEP mode */ pm_unblock(GD32V_PM_DEEPSLEEP); - mutex_unlock(&locks[dev]); + /* unlock the device */ + mutex_unlock(&_i2c_dev[dev].dev_lock); +} + +static int _i2c_start_cmd(i2c_t dev) +{ + DEBUG("START cmd, dev=%d\n", dev); + + I2C_Type *i2c = i2c_config[dev].dev; + + /* clear error flags */ + i2c->STAT0 &= ~I2C_ERROR_FLAGS; + + /* send start condition and wait for interrupt */ + i2c->CTL0 |= I2C_CTL0_START_Msk; + _wait_for_irq(dev); + + switch (_i2c_dev[dev].state) { + case I2C_START_SENT: + return 0; + case I2C_ARB_LOST: + return -EAGAIN; + case I2C_TIMEOUT: + return -ETIMEDOUT; + default: + /* on other errors */ + return -EINVAL; + } } -int i2c_read_bytes(i2c_t dev, uint16_t address, void *data, size_t length, +static int _i2c_stop_cmd(i2c_t dev) +{ + DEBUG("STOP cmd, dev=%d\n", dev); + + I2C_Type *i2c = i2c_config[dev].dev; + + /* clear error flags */ + i2c->STAT0 &= ~I2C_ERROR_FLAGS; + + /* send start condition */ + i2c->CTL0 |= I2C_CTL0_STOP_Msk; + + return 0; +} + +static int _i2c_stop_cmd_and_wait(i2c_t dev) +{ + _i2c_stop_cmd(dev); + return _wait_for_bus(dev); +} + +static int _i2c_addr_cmd(i2c_t dev, uint8_t *addr, uint8_t size) +{ + if (size == 1) { + DEBUG("ADDR cmd, dev=%d, addr=%02x\n", dev, addr[0]); + } + else{ + DEBUG("ADDR cmd, dev=%d, addr=%02x%02x\n", dev, addr[0], addr[1]); + } + + I2C_Type *i2c = i2c_config[dev].dev; + + /* clear error flags */ + i2c->STAT0 &= ~I2C_ERROR_FLAGS; + + /* read STAT0 followed by writing the first address byte to the + * DATA register to clear SBSEND and then wait for interrupt */ + i2c->STAT0; + i2c->DATA = addr[0]; + _wait_for_irq(dev); + + if ((_i2c_dev[dev].state == I2C_ADDR10_SENT)) { + /* first byte is sent and indicates a 10 bit address */ + assert(size == 2); + /* read STAT0 followed by writing the second byte of the 10-bit + * address to the DATA register to clear ADD10SEND and then wait for + * interrupt */ + i2c->STAT0; + i2c->DATA = addr[1]; + _wait_for_irq(dev); + } + + switch (_i2c_dev[dev].state) { + case I2C_ADDR_SENT: + /* Since the ADDSEND flag is needed to control the ACK bit while + * receiving bytes, it is intentionally not cleared here, but must + * be explicitly cleared in `i2c_read_bytes` and `i2c_read_bytes */ + return 0; + case I2C_ARB_LOST: + return -EAGAIN; + case I2C_TIMEOUT: + return -ETIMEDOUT; + case I2C_ACK_ERR: + return -ENXIO; + default: + /* on other errors */ + return -EINVAL; + } +} + +int _i2c_write_cmd(i2c_t dev, uint8_t data) +{ + DEBUG("WRITE cmd, dev=%d\n", dev); + + I2C_Type *i2c = i2c_config[dev].dev; + + /* clear error flags */ + i2c->STAT0 &= ~I2C_ERROR_FLAGS; + + /* send data byte and wait for BTC interrupt */ + i2c->DATA = data; + _wait_for_irq(dev); + + switch (_i2c_dev[dev].state) { + case I2C_BT_COMPLETE: + /* read STAT0 followed by reading DATA to clear the BTC flag */ + i2c->STAT0; + i2c->DATA; + return 0; + case I2C_ARB_LOST: + return -EAGAIN; + case I2C_TIMEOUT: + return -ETIMEDOUT; + case I2C_ACK_ERR: + return -EIO; + default: + /* on other errors */ + return -EINVAL; + } +} + +int _i2c_read_cmd(i2c_t dev, uint8_t *data) +{ + DEBUG("READ cmd, dev=%d\n", dev); + + I2C_Type *i2c = i2c_config[dev].dev; + + /* clear error flags */ + i2c->STAT0 &= ~I2C_ERROR_FLAGS; + + if (i2c->STAT0 & (I2C_STAT0_RBNE_Msk || I2C_STAT0_BTC_Msk)) { + _i2c_dev[dev].state = I2C_RXB_NOT_EMPTY; + } + else { + /* buffer interrupts have to be enabled for read */ + i2c_config[dev].dev->CTL1 |= I2C_CTL1_BUFIE_Msk; + + /* wait for interrupt */ + _wait_for_irq(dev); + } + + switch (_i2c_dev[dev].state) { + case I2C_RXB_NOT_EMPTY_BT_COMPLETE: + case I2C_RXB_NOT_EMPTY: + /* RBNE is cleared by reding STAT0 followed by reading the data register */ + i2c->STAT0; + *data = i2c->DATA; + return 0; + case I2C_ARB_LOST: + return -EAGAIN; + case I2C_TIMEOUT: + return -ETIMEDOUT; + default: + /* on other errors */ + return -EINVAL; + } +} + +static int _i2c_wait_rbne_btc(i2c_t dev) +{ + DEBUG("WAIT RNBE+BTC cmd, dev=%d\n", dev); + + I2C_Type *i2c = i2c_config[dev].dev; + + /* clear error flags */ + i2c->STAT0 &= ~I2C_ERROR_FLAGS; + + _wait_for_irq(dev); + + switch (_i2c_dev[dev].state) { + case I2C_RXB_NOT_EMPTY_BT_COMPLETE: + return 0; + case I2C_ARB_LOST: + return -EAGAIN; + case I2C_TIMEOUT: + return -ETIMEDOUT; + default: + /* on other errors */ + return -EINVAL; + } +} + +int i2c_read_bytes(i2c_t dev, uint16_t addr, void *data, size_t length, uint8_t flags) { assert(dev < I2C_NUMOF); + assert(data); + assert(length); + + DEBUG("i2c_read_bytes, dev=%d len=%d flags=%02x\n", dev, length, flags); I2C_Type *i2c = i2c_config[dev].dev; - DEBUG("[i2c] read_bytes: Starting\n"); - /* Repeated start of read operations is not supported. This is exactly the + /* Repeated START of read operations is not supported. This is exactly the * case if the previous transfer was a read operation (I2C_STAT1_TR == 0) * and was not terminated by a STOP condition (I2C_STAT1_I2CBSY == 1) and * the START condition is to be used (I2C_NOSTART == 0). @@ -210,206 +421,333 @@ int i2c_read_bytes(i2c_t dev, uint16_t address, void *data, size_t length, return -EOPNOTSUPP; } - int ret = _start(i2c, (address << 1) | I2C_FLAG_READ, flags, length); - if (ret < 0) { - if (ret == -ETIMEDOUT) { - _init(dev); + int res; + + _i2c_dev[dev].state = I2C_OK; + + /* set the ACK bit */ + i2c->CTL0 |= I2C_CTL0_ACKEN_Msk; + /* clear the POAP bit to indicate that ACK bit controls the current byte */ + i2c->CTL0 &= ~I2C_CTL0_POAP_Msk; + + if (!(flags & I2C_NOSTOP)) { + /* Since the I2C controller allows to receive up to two bytes before + * the application has to react, receiving a single byte, two bytes + * or more than two bytes needs a different handling for correct + * reception if the reception is not to be continued (I2C_NOSTOP + * is not set) */ + if (length == 1) { + /* If a single byte is to be received clear the ACK bit before + * any byte is received and keep the POAP bit cleared to indicate + * that the ACK bit controls the ACK of the currecnt byte. */ + i2c->CTL0 &= ~I2C_CTL0_ACKEN_Msk; + } + else if (length == 2) { + /* If exactly 2 bytes are to be received, keep the ACK bit set but + * also set the POAP bit to indicate that the ACK bit controls the + * next byte that is received in shift register. The ACK bit is then + * cleared after the ADDSEND flag is cleared and thus the reception + * of first byte has already been started. Thus an ACK is generated + * for the first byte and a NACK for the second byte. */ + i2c->CTL0 |= I2C_CTL0_POAP_Msk; } - return ret; + /* In all other cases the ACK flag is kept set while the POAP flag + * is kept cleared, so that the ACK bit always controls the byte + * currently to be received in the shift register. To clear the ACK bit + * before the last byte is received in the shift register, reading of + * bytes from the DATA register is stopped when there are 3 bytes left + * to receive until the BTC flag is set. The BTC flag then indicates + * that the DATA register then contains the third last byte and the + * shift register the second last byte. The ACK flag is then cleared + * before reading of the bytes from the DATA register continues. */ } - for (size_t i = 0; i < length; i++) { - if (i + 1 == length && !(flags & I2C_NOSTOP)) { - /* If data is already in the buffer we must clear before sending - * a stop. If I2C_NOSTOP was called up to two extra bytes may be - * clocked out on the line however they get ignored in the firmware.*/ - if ((i2c->STAT0 & I2C_STAT0_RBNE_Msk) && (length == 1)) { - ((uint8_t*)data)[i] = i2c->DATA; - return _stop(i2c); - } - /* STOP must also be sent before final read */ - ret = _stop(i2c); - if (ret < 0) { - return ret; - } + /* if I2C_NOSTART is not set, send START condition and ADDR */ + if (!(flags & I2C_NOSTART)) { + res = _i2c_start_cmd(dev); + if (res != 0) { + _i2c_stop_cmd_and_wait(dev); + return res; + } + + /* address handling */ + if (flags & I2C_ADDR10) { + /* prepare 10 bit address bytes */ + uint8_t addr10[2]; + addr10[0] = 0xf0 | (addr & 0x0300) >> 7 | I2C_READ; + addr10[1] = addr & 0xff; + /* send ADDR without read flag */ + res = _i2c_addr_cmd(dev, addr10, 2); } - /* Wait for reception to complete */ - ret = _is_sr1_mask_set(i2c, I2C_STAT0_RBNE_Msk, flags); - if (ret < 0) { - return ret; + else { + /* send ADDR without read flag */ + uint8_t addr7 = addr << 1 | I2C_READ; + res = _i2c_addr_cmd(dev, &addr7, 1); + } + if (res != 0) { + _i2c_stop_cmd_and_wait(dev); + return res; } - ((uint8_t*)data)[i] = i2c->DATA; - } - DEBUG("[i2c] read_bytes: Finished reading bytes\n"); - if (flags & I2C_NOSTOP) { - return 0; } - return _wait_for_bus(i2c); -} -int i2c_write_bytes(i2c_t dev, uint16_t address, const void *data, - size_t length, uint8_t flags) -{ - assert(dev < I2C_NUMOF); + /* read STAT0 followed by reading STAT1 to clear the ADDSEND flag */ + i2c->STAT0; + i2c->STAT1; - int ret; + /* read data */ + uint8_t *buffer = (uint8_t*)data; - I2C_Type *i2c = i2c_config[dev].dev; - assert(i2c != NULL); - DEBUG("[i2c] write_bytes: Starting\n"); - /* Length is 0 in start since we don't need to preset the stop bit */ - ret = _start(i2c, (address << 1) | I2C_FLAG_WRITE, flags, 0); - if (ret < 0) { - if (ret == -ETIMEDOUT) { - _init(dev); - } - return ret; - } - - /* Send out data bytes */ for (size_t i = 0; i < length; i++) { - DEBUG("[i2c] write_bytes: Waiting for TX reg to be free\n"); - ret = _is_sr1_mask_set(i2c, I2C_STAT0_TBE_Msk, flags); - if (ret < 0) { - return ret; + if (!(flags & I2C_NOSTOP)) { + /* if the reception is not to be continued (I2C_NOSTOP is not set) */ + if (i == 0 && (length == 2)) { + /* The shift register already receives the first byte after + * the ADDSEND flag has been cleared. Since the POAP bit is + * set in the case that exactly two bytes are to be received, + * the change of the ACK bit during the reception of a byte + * does not affect the generated ACK of the byte currently + * received, but of the byte to be received next. Since the + * ACK bit and the POAP bit were set in this case, an ACK + * is generated for the first byte. Clearing the ACK bit here + * then generates a NACK for the next (last) byte. */ + i2c->CTL0 &= ~I2C_CTL0_ACKEN_Msk; + } + else if (i == (length - 3)) { + /* To clear the ACK flag before the last byte is received + * in the shift register, reading of bytes from the DATA + * register is stopped when there are 3 bytes left to + * receive until the BTC flag is set. The BTC flag is then + * set when the third last received byte is in DATA register + * and the second last byte is in shift register. */ + res = _i2c_wait_rbne_btc(dev); + if (res != 0) { + _i2c_stop_cmd_and_wait(dev); + return res; + } + /* The ACK flag is then cleared before reading of the bytes + * from the DATA register continues to generate an NACK + * for the last byte. */ + i2c->CTL0 &= ~I2C_CTL0_ACKEN_Msk; + } } - DEBUG("[i2c] write_bytes: TX is free so send byte\n"); - i2c->DATA = ((uint8_t*)data)[i]; - } - /* Wait for tx reg to be empty so other calls will no interfere */ - ret = _is_sr1_mask_set(i2c, I2C_STAT0_TBE_Msk, flags); - if (ret < 0) { - return ret; - } - if (flags & I2C_NOSTOP) { - return 0; - } - else { - /* End transmission */ - DEBUG("[i2c] write_bytes: Ending transmission\n"); - ret = _stop(i2c); - if (ret < 0) { - return ret; + res = _i2c_read_cmd(dev, buffer + i); + if (res != 0) { + _i2c_stop_cmd_and_wait(dev); + return res; } - DEBUG("[i2c] write_bytes: STOP condition was send out\n"); } - return _wait_for_bus(i2c); + if (!(flags & I2C_NOSTOP)) { + /* If the transfer is not to be continued (I2C_NOSTOP is not set), set + * the STOP bit and wait a short time until the I2CBSY bit is cleared. */ + return _i2c_stop_cmd_and_wait(dev); + } + + return 0; } -static int _start(I2C_Type *i2c, uint8_t address_byte, uint8_t flags, - size_t length) +int i2c_write_bytes(i2c_t dev, uint16_t addr, const void *data, + size_t length, uint8_t flags) { - assert(i2c != NULL); + assert(dev < I2C_NUMOF); + assert(data); + assert(length); - if ((flags & I2C_ADDR10) || - (!(i2c->STAT1 & I2C_STAT1_I2CBSY_Msk) && (flags & I2C_NOSTART))) { - return -EOPNOTSUPP; - } + DEBUG("i2c_write_bytes, dev=%d len=%d flags=%02x\n", dev, length, flags); - /* Clear flags */ - i2c->STAT0 &= ~ERROR_FLAGS; + int res; + _i2c_dev[dev].state = I2C_OK; + + /* if I2C_NOSTART is not set, send START condition and ADDR */ if (!(flags & I2C_NOSTART)) { - DEBUG("[i2c] start: Generate start condition\n"); - /* Generate start condition */ - i2c->CTL0 |= I2C_CTL0_START_Msk | I2C_CTL0_ACKEN_Msk; - - /* Wait for SB flag to be set */ - int ret = _is_sr1_mask_set(i2c, I2C_STAT0_SBSEND_Msk, flags & ~I2C_NOSTOP); - if (ret < 0) { - return ret; + res = _i2c_start_cmd(dev); + if (res != 0) { + _i2c_stop_cmd_and_wait(dev); + return res; } - DEBUG("[i2c] start: Start condition generated\n"); - DEBUG("[i2c] start: Generating address\n"); - /* Send address and read/write flag */ - if ((i2c->STAT0 & I2C_STAT0_SBSEND_Msk)) { - i2c->DATA = (address_byte); + /* address handling */ + if (flags & I2C_ADDR10) { + /* prepare 10 bit address bytes */ + uint8_t addr10[2]; + addr10[0] = 0xf0 | (addr & 0x0300) >> 7; + addr10[1] = addr & 0xff; + /* send ADDR without read flag */ + res = _i2c_addr_cmd(dev, addr10, 2); } - if (!(flags & I2C_NOSTOP) && length == 1) { - i2c->CTL0 &= ~(I2C_CTL0_ACKEN_Msk); + else { + /* send ADDR without read flag */ + uint8_t addr7 = addr << 1; + res = _i2c_addr_cmd(dev, &addr7, 1); } - /* Wait for ADDR flag to be set */ - ret = _is_sr1_mask_set(i2c, I2C_STAT0_ADDSEND_Msk, flags & ~I2C_NOSTOP); - if (ret == -EIO){ - /* Since NACK happened during start it means no device connected */ - return -ENXIO; + if (res != 0) { + _i2c_stop_cmd_and_wait(dev); + return res; } + } + + /* read STAT0 followed by reading STAT1 to clear the ADDSEND flag */ + i2c_config[dev].dev->STAT0; + i2c_config[dev].dev->STAT1; - /* Wait until I2C_STAT0_ADDSEND is cleared. To clear I2C_STAT0_ADDSEND - * it is necessary to read STAT0 followed by reading STAT1 */ - while ((i2c->STAT0 & I2C_STAT0_ADDSEND_Msk) && i2c->STAT1) { } + /* send data */ + uint8_t *buffer = (uint8_t*)data; - if (!(flags & I2C_NOSTOP) && length == 1) { - /* Stop must also be sent before final read */ - i2c->CTL0 |= (I2C_CTL0_STOP_Msk); + for (size_t i = 0; i < length; i++) { + res = _i2c_write_cmd(dev, buffer[i]); + if (res != 0) { + _i2c_stop_cmd_and_wait(dev); + return res; } - DEBUG("[i2c] start: Address generated\n"); - return ret; } + + if (!(flags & I2C_NOSTOP)) { + /* If the transfer is not to be continued (I2C_NOSTOP is not set), set + * the STOP bit and wait a short time until the I2CBSY bit is cleared. */ + return _i2c_stop_cmd_and_wait(dev); + } + return 0; } -static int _is_sr1_mask_set(I2C_Type *i2c, uint32_t mask, uint8_t flags) +void _i2c_transfer_timeout(void *arg) { - DEBUG("[i2c] _is_sr1_mask_set: waiting to set %04X\n", (uint16_t)mask); - uint16_t tick = TICK_TIMEOUT; - while (tick--) { - uint32_t sr1 = i2c->STAT0; - if (sr1 & I2C_STAT0_AERR_Msk) { - DEBUG("[i2c] is_sr1_mask_set: NACK received\n"); - i2c->STAT0 &= ~ERROR_FLAGS; - if (!(flags & I2C_NOSTOP)) { - _stop(i2c); - } - return -EIO; - } - if ((sr1 & I2C_STAT0_LOSTARB_Msk) || (sr1 & I2C_STAT0_BERR_Msk)) { - DEBUG("[i2c] is_sr1_mask_set: arb lost or bus ERROR_FLAGS\n"); - i2c->STAT0 &= ~ERROR_FLAGS; - _stop(i2c); - return -EAGAIN; - } - if (sr1 & mask) { - i2c->STAT0 &= ~ERROR_FLAGS; - return 0; - } + i2c_t dev = (i2c_t)(uintptr_t)arg; + + /* set result to timeout */ + _i2c_dev[dev].state = I2C_TIMEOUT; + + /* wake up the thread that is waiting for the results */ + mutex_unlock(&_i2c_dev[dev].irq_lock); +} + +static void _wait_for_irq(i2c_t dev) +{ +#if defined(MODULE_ZTIMER_USEC) + ztimer_t timer = { .callback = _i2c_transfer_timeout, + .arg = (void *)dev }; + uint32_t timeout = ((I2C_TIMEOUT_CYCLES * MHZ(1)) / i2c_config[dev].speed) + 1; + ztimer_set(ZTIMER_USEC, &timer, timeout); +#elif defined(MODULE_ZTIMER_MSEC) + ztimer_t timer = { .callback = _i2c_transfer_timeout, + .arg = (void *)dev }; + uint32_t timeout = ((I2C_TIMEOUT_CYCLES * KHZ(1)) / i2c_config[dev].speed) + 1; + ztimer_set(ZTIMER_MSEC, &timer, timeout); +#else +#warning "I2C timeout handling requires to use ztimer_msec or ztimer_usec" +#endif + + /* enable only event and error interrupts, buffer interrupts are only used in read */ + i2c_config[dev].dev->CTL1 |= I2C_INT_EV_ERR_FLAGS; + + /* wait for buffer, event or error interrupt */ + mutex_lock(&_i2c_dev[dev].irq_lock); + +#if defined(MODULE_ZTIMER_USEC) + ztimer_remove(ZTIMER_USEC, &timer); +#elif defined(MODULE_ZTIMER_MSEC) + ztimer_remove(ZTIMER_MSEC, &timer); +#endif + + if (_i2c_dev[dev].state == I2C_TIMEOUT) { + DEBUG("error: timeout, dev=%d\n", dev); } - /* - * If timeout occurs this means a problem that must be handled on a higher - * level. A SWRST is recommended by the datasheet. - */ - i2c->STAT0 &= ~ERROR_FLAGS; - _stop(i2c); - return -ETIMEDOUT; } -static int _stop(I2C_Type *i2c) +#define TICK_TIMEOUT 0x00000fffUL + +static inline int _wait_for_bus(i2c_t dev) { - /* send STOP condition */ - DEBUG("[i2c] stop: Generate stop condition\n"); - i2c->CTL0 &= ~(I2C_CTL0_ACKEN_Msk); - i2c->CTL0 |= I2C_CTL0_STOP_Msk; uint16_t tick = TICK_TIMEOUT; - while ((i2c->CTL0 & I2C_CTL0_STOP_Msk) && tick--) {} + /* short busy waiting for the bus becoming free (I2CBSY is cleared) */ + while ((i2c_config[dev].dev->STAT1 & I2C_STAT1_I2CBSY_Msk) && tick--) {} if (!tick) { + DEBUG("error: timeout, dev=%d\n", dev); return -ETIMEDOUT; } - DEBUG("[i2c] stop: Stop condition succeeded\n"); - if (_wait_for_bus(i2c) < 0) { - return -ETIMEDOUT; - } - DEBUG("[i2c] stop: Bus is free\n"); return 0; } -static inline int _wait_for_bus(I2C_Type *i2c) +static void _irq_handler(unsigned irqn) { - uint16_t tick = TICK_TIMEOUT; - while ((i2c->STAT1 & I2C_STAT1_I2CBSY_Msk) && tick--) {} - if (!tick) { - return -ETIMEDOUT; + static_assert(I2C0_ER_IRQn == I2C0_EV_IRQn + 1); + static_assert(I2C1_ER_IRQn == I2C1_EV_IRQn + 1); + + i2c_t dev = ((irqn == i2c_config[0].irqn) || + (irqn == (i2c_config[0].irqn + 1))) ? I2C_DEV(0) : I2C_DEV(1); + + assert(dev < I2C_NUMOF); + + I2C_Type *i2c = i2c_config[dev].dev; + + assert(i2c != NULL); + + unsigned state = i2c->STAT0; + + /* disable buffer, event and error interrupts */ + i2c->CTL1 &= ~(I2C_INT_ALL_FLAGS); + + DEBUG("STAT0: %08x, dev=%d\n", state, dev); + + if (state & I2C_ERROR_FLAGS) { + /* any error happened */ + if (state & I2C_ERROR_FLAGS_USED) { + if (state & I2C_STAT0_LOSTARB_Msk) { + DEBUG("error: arbitration lost, dev=%d\n", dev); + _i2c_dev[dev].state = I2C_ARB_LOST; + } + else if (state & I2C_STAT0_AERR_Msk) { + DEBUG("error: ACK error, dev=%d\n", dev); + _i2c_dev[dev].state = I2C_ACK_ERR; + } + else if (state & I2C_STAT0_BERR_Msk) { + DEBUG("error: bus error, dev=%d\n", dev); + _i2c_dev[dev].state = I2C_BUS_ERROR; + } + } + if (state & I2C_ERROR_FLAGS_OTHER) { + /* PEC calculation and SMBus are not used, + * according errors are simply handled as other errors */ + DEBUG("error: other error, dev=%d\n", dev); + _i2c_dev[dev].state = I2C_OTHER_ERROR; + } + /* clear interrupt flags for errors */ + i2c->CTL1 &= ~(I2C_ERROR_FLAGS); } - return 0; + else if (state & I2C_STAT0_SBSEND_Msk) { + DEBUG("START sent, dev=%d\n", dev); + _i2c_dev[dev].state = I2C_START_SENT; + } + else if (state & I2C_STAT0_ADDSEND_Msk) { + DEBUG("ADDR sent, dev=%d\n", dev); + _i2c_dev[dev].state = I2C_ADDR_SENT; + } + else if (state & I2C_STAT0_ADD10SEND_Msk) { + DEBUG("ADDR10 first byte sent, dev=%d\n", dev); + _i2c_dev[dev].state = I2C_ADDR10_SENT; + } + else if (state & I2C_STAT0_RBNE_Msk) { + if (state & I2C_STAT0_BTC_Msk) { + DEBUG("RX buffer not empty + BT completed, dev=%d\n", dev); + _i2c_dev[dev].state = I2C_RXB_NOT_EMPTY_BT_COMPLETE; + } + else { + DEBUG("RX buffer not empty, dev=%d\n", dev); + _i2c_dev[dev].state = I2C_RXB_NOT_EMPTY; + } + } + else if (state & I2C_STAT0_BTC_Msk) { + DEBUG("BT completed, dev=%d\n", dev); + _i2c_dev[dev].state = I2C_BT_COMPLETE; + } + else if (state & I2C_STAT0_TBE_Msk) { + DEBUG("TX buffer empty, dev=%d\n", dev); + _i2c_dev[dev].state = I2C_TXB_EMPTY; + } + else { + _i2c_dev[dev].state = I2C_OK; + } + + mutex_unlock(&_i2c_dev[dev].irq_lock); } diff --git a/examples/gnrc_border_router/Makefile.wifi.conf b/examples/gnrc_border_router/Makefile.wifi.conf index 5d34ef71a68df..617c8258c7746 100644 --- a/examples/gnrc_border_router/Makefile.wifi.conf +++ b/examples/gnrc_border_router/Makefile.wifi.conf @@ -1,2 +1,2 @@ -CFLAGS += -DESP_WIFI_SSID=\"$(WIFI_SSID)\" -CFLAGS += -DESP_WIFI_PASS=\"$(WIFI_PASS)\" +CFLAGS += -DWIFI_SSID=\"$(WIFI_SSID)\" +CFLAGS += -DWIFI_PASS=\"$(WIFI_PASS)\" diff --git a/examples/paho-mqtt/Makefile b/examples/paho-mqtt/Makefile index fe47ad90fb5e4..1fddbd237504f 100644 --- a/examples/paho-mqtt/Makefile +++ b/examples/paho-mqtt/Makefile @@ -60,6 +60,6 @@ USEMODULE += ztimer_msec include $(RIOTBASE)/Makefile.include ifneq (,$(filter arch_esp,$(FEATURES_USED))) - CFLAGS += -DESP_WIFI_SSID=\"$(WIFI_SSID)\" - CFLAGS += -DESP_WIFI_PASS=\"$(WIFI_PASS)\" + CFLAGS += -DWIFI_SSID=\"$(WIFI_SSID)\" + CFLAGS += -DWIFI_PASS=\"$(WIFI_PASS)\" endif diff --git a/sys/fmt/fmt.c b/sys/fmt/fmt.c index c1d6386550436..d66e266990f6c 100644 --- a/sys/fmt/fmt.c +++ b/sys/fmt/fmt.c @@ -471,14 +471,13 @@ uint32_t scn_u32_dec(const char *str, size_t n) uint32_t res = 0; while (n--) { - char c = *str++; - if (!fmt_is_digit(c)) { + unsigned c = *str++; + unsigned d = c - (unsigned)'0'; + if ( !( '0'<= c && c <= '9') ) { break; } - else { - res *= 10; - res += (c - '0'); - } + res *= 10U; + res += d; } return res; } @@ -488,21 +487,23 @@ uint32_t scn_u32_hex(const char *str, size_t n) uint32_t res = 0; while (n--) { - char c = *str++; - if (!fmt_is_digit(c)) { - if (fmt_is_upper(c)) { - c = _to_lower(c); - } - if (c == '\0' || c > 'f') { - break; - } - res <<= 4; - res |= c - 'a' + 0xa; + unsigned c = *str++; + unsigned d; + if (('0'<= c) && (c <= '9')){ + d = c - (unsigned)'0'; + } + else if (('A' <= c) && (c <= 'F')) { + d = c - (unsigned)'A' + 0xaU; + } + else if (('a' <= c) && (c <= 'f')) { + d = c - (unsigned)'a' + 0xaU; } else { - res <<= 4; - res |= c - '0'; + break; } + res <<= 4U; + res |= d; + } return res; } diff --git a/tests/external_board_dirs/esp-ci-boards/esp32-ci/Makefile.include b/tests/external_board_dirs/esp-ci-boards/esp32-ci/Makefile.include index b4fdf5447b310..7095c81c02fc5 100644 --- a/tests/external_board_dirs/esp-ci-boards/esp32-ci/Makefile.include +++ b/tests/external_board_dirs/esp-ci-boards/esp32-ci/Makefile.include @@ -2,9 +2,9 @@ # to also include the main board header INCLUDES += $(addprefix -I,$(wildcard $(RIOTBOARD)/esp32-wrover-kit/include)) -# ESP_WIFI_EAP_USER and ESP_WIFI_EAP_PASS have to be defined to compile the +# WIFI_EAP_USER and WIFI_EAP_PASS have to be defined to compile the # optional module esp_wifi_enterprise in CI -CFLAGS += -DESP_WIFI_EAP_USER=\"riot@riot-os.org\" -CFLAGS += -DESP_WIFI_EAP_PASS=\"riot\" +CFLAGS += -DWIFI_EAP_USER=\"riot@riot-os.org\" +CFLAGS += -DWIFI_EAP_PASS=\"riot\" include $(RIOTBOARD)/esp32-wrover-kit/Makefile.include diff --git a/tests/external_board_dirs/esp-ci-boards/esp32c3-ci/Makefile.include b/tests/external_board_dirs/esp-ci-boards/esp32c3-ci/Makefile.include index c36113cd4af91..6405cc20dcdbc 100644 --- a/tests/external_board_dirs/esp-ci-boards/esp32c3-ci/Makefile.include +++ b/tests/external_board_dirs/esp-ci-boards/esp32c3-ci/Makefile.include @@ -2,9 +2,9 @@ # to also include the main board header INCLUDES += $(addprefix -I,$(wildcard $(RIOTBOARD)/esp32c3-devkit/include)) -# ESP_WIFI_EAP_USER and ESP_WIFI_EAP_PASS have to be defined to compile the +# WIFI_EAP_USER and WIFI_EAP_PASS have to be defined to compile the # optional module esp_wifi_enterprise in CI -CFLAGS += -DESP_WIFI_EAP_USER=\"riot@riot-os.org\" -CFLAGS += -DESP_WIFI_EAP_PASS=\"riot\" +CFLAGS += -DWIFI_EAP_USER=\"riot@riot-os.org\" +CFLAGS += -DWIFI_EAP_PASS=\"riot\" include $(RIOTBOARD)/esp32c3-devkit/Makefile.include diff --git a/tests/external_board_dirs/esp-ci-boards/esp32s2-ci/Makefile.include b/tests/external_board_dirs/esp-ci-boards/esp32s2-ci/Makefile.include index 8ef626680aa31..07302d83821c4 100644 --- a/tests/external_board_dirs/esp-ci-boards/esp32s2-ci/Makefile.include +++ b/tests/external_board_dirs/esp-ci-boards/esp32s2-ci/Makefile.include @@ -2,9 +2,9 @@ # to also include the main board header INCLUDES += $(addprefix -I,$(wildcard $(RIOTBOARD)/esp32s2-devkit/include)) -# ESP_WIFI_EAP_USER and ESP_WIFI_EAP_PASS have to be defined to compile the +# WIFI_EAP_USER and WIFI_EAP_PASS have to be defined to compile the # optional module esp_wifi_enterprise in CI -CFLAGS += -DESP_WIFI_EAP_USER=\"riot@riot-os.org\" -CFLAGS += -DESP_WIFI_EAP_PASS=\"riot\" +CFLAGS += -DWIFI_EAP_USER=\"riot@riot-os.org\" +CFLAGS += -DWIFI_EAP_PASS=\"riot\" include $(RIOTBOARD)/esp32s2-devkit/Makefile.include diff --git a/tests/external_board_dirs/esp-ci-boards/esp32s3-ci/Makefile.include b/tests/external_board_dirs/esp-ci-boards/esp32s3-ci/Makefile.include index 78a8c61812629..857c21f03ba2e 100644 --- a/tests/external_board_dirs/esp-ci-boards/esp32s3-ci/Makefile.include +++ b/tests/external_board_dirs/esp-ci-boards/esp32s3-ci/Makefile.include @@ -2,9 +2,9 @@ # to also include the main board header INCLUDES += $(addprefix -I,$(wildcard $(RIOTBOARD)/esp32s3-devkit/include)) -# ESP_WIFI_EAP_USER and ESP_WIFI_EAP_PASS have to be defined to compile the +# WIFI_EAP_USER and WIFI_EAP_PASS have to be defined to compile the # optional module esp_wifi_enterprise in CI -CFLAGS += -DESP_WIFI_EAP_USER=\"riot@riot-os.org\" -CFLAGS += -DESP_WIFI_EAP_PASS=\"riot\" +CFLAGS += -DWIFI_EAP_USER=\"riot@riot-os.org\" +CFLAGS += -DWIFI_EAP_PASS=\"riot\" include $(RIOTBOARD)/esp32s3-devkit/Makefile.include diff --git a/tests/malloc/main.c b/tests/malloc/main.c index e4ffac5e6271b..9728efa30d57f 100644 --- a/tests/malloc/main.c +++ b/tests/malloc/main.c @@ -59,7 +59,7 @@ static uint32_t fill_memory(struct node *head) total = 0; while (head && (head->ptr = malloc(CHUNK_SIZE)) && total < MAX_MEM) { - printf("Allocated %"PRIu32" Bytes at 0x%p, total %"PRIu32"\n", + printf("Allocated %"PRIu32" Bytes at %p, total %"PRIu32"\n", (uint32_t)CHUNK_SIZE, head->ptr, total += CHUNK_SIZE); memset(head->ptr, '@', CHUNK_SIZE); head = head->next = malloc(sizeof(struct node)); @@ -88,7 +88,7 @@ static void free_memory(struct node *head) total -= CHUNK_SIZE; freed++; } - printf("Free %"PRIu32" Bytes at 0x%p, total %"PRIu32"\n", + printf("Free %"PRIu32" Bytes at %p, total %"PRIu32"\n", (uint32_t)CHUNK_SIZE, head->ptr, total); free(head->ptr); } diff --git a/tests/nimble_esp_wifi_coexist/README.md b/tests/nimble_esp_wifi_coexist/README.md index 883b9c3a48a92..c947ef06c8944 100644 --- a/tests/nimble_esp_wifi_coexist/README.md +++ b/tests/nimble_esp_wifi_coexist/README.md @@ -8,7 +8,7 @@ ESP32x WiFi interface simultaneously. Comile and flash the application with command ``` -CFLAGS='-DESP_WIFI_SSID=\"myssid\" -DESP_WIFI_PASS=\"mypass\"' +CFLAGS='-DWIFI_SSID=\"myssid\" -DWIFI_PASS=\"mypass\"' BOARD=esp32-wroom-32 make -C tests/nimble_esp_wifi_coexist flash term ``` Once the test application is flashed and the WiFi connection is established,