From 28aed3cb9765f9e9214fe5b6b72d8d82b377a7cd Mon Sep 17 00:00:00 2001 From: MrKevinWeiss Date: Wed, 26 Oct 2022 11:55:43 +0200 Subject: [PATCH] cpu/stm32/kconfig: rework clock tree This splits up the clock configs. It allows CPU_FAM based file sourcing and also common CPU_FAMs. The dependancies are also included in wildcards would be used for the CPU_FAM macro. This should be much more readable. This also takes into account the HSE speeds in order to match the make/header resolution. Some hidden symbols were added to make sorting many CPU_SERIES dependencies easier. --- cpu/stm32/Kconfig | 20 +- cpu/stm32/kconfigs/Kconfig.clk | 427 +----------------- cpu/stm32/kconfigs/f0/Kconfig.clk | 8 + cpu/stm32/kconfigs/f0/Kconfig.lines | 2 + cpu/stm32/kconfigs/f0f1f3/Kconfig.clk | 31 ++ .../kconfigs/f0f1f3g0g4l0l1l4wbwl/Kconfig.clk | 89 ++++ cpu/stm32/kconfigs/f1/Kconfig.clk | 8 + cpu/stm32/kconfigs/f2/Kconfig.clk | 22 + cpu/stm32/kconfigs/f2f4f7mp1/Kconfig.clk | 54 +++ cpu/stm32/kconfigs/f3/Kconfig.clk | 8 + cpu/stm32/kconfigs/f3/Kconfig.lines | 13 + cpu/stm32/kconfigs/f4/Kconfig.clk | 43 ++ cpu/stm32/kconfigs/f4/Kconfig.lines | 9 + cpu/stm32/kconfigs/f7/Kconfig | 1 + cpu/stm32/kconfigs/f7/Kconfig.clk | 24 + cpu/stm32/kconfigs/g0/Kconfig.clk | 63 +++ cpu/stm32/kconfigs/g0wxmp1/Kconfig.clk | 18 + cpu/stm32/kconfigs/g4/Kconfig.clk | 23 + cpu/stm32/kconfigs/g4l4l5/Kconfig.clk | 35 ++ cpu/stm32/kconfigs/l0/Kconfig.clk | 8 + cpu/stm32/kconfigs/l0l1/Kconfig.clk | 112 +++++ cpu/stm32/kconfigs/l1/Kconfig.clk | 8 + cpu/stm32/kconfigs/l4/Kconfig.clk | 25 + cpu/stm32/kconfigs/l4l5wx/Kconfig.clk | 94 ++++ cpu/stm32/kconfigs/l5/Kconfig.clk | 24 + cpu/stm32/kconfigs/mp1/Kconfig.clk | 24 + cpu/stm32/kconfigs/u5/Kconfig.clk | 6 + cpu/stm32/kconfigs/wb/Kconfig.clk | 25 + cpu/stm32/kconfigs/wl/Kconfig.clk | 25 + 29 files changed, 822 insertions(+), 427 deletions(-) create mode 100644 cpu/stm32/kconfigs/f0/Kconfig.clk create mode 100644 cpu/stm32/kconfigs/f0f1f3/Kconfig.clk create mode 100644 cpu/stm32/kconfigs/f0f1f3g0g4l0l1l4wbwl/Kconfig.clk create mode 100644 cpu/stm32/kconfigs/f1/Kconfig.clk create mode 100644 cpu/stm32/kconfigs/f2/Kconfig.clk create mode 100644 cpu/stm32/kconfigs/f2f4f7mp1/Kconfig.clk create mode 100644 cpu/stm32/kconfigs/f3/Kconfig.clk create mode 100644 cpu/stm32/kconfigs/f4/Kconfig.clk create mode 100644 cpu/stm32/kconfigs/f7/Kconfig.clk create mode 100644 cpu/stm32/kconfigs/g0/Kconfig.clk create mode 100644 cpu/stm32/kconfigs/g0wxmp1/Kconfig.clk create mode 100644 cpu/stm32/kconfigs/g4/Kconfig.clk create mode 100644 cpu/stm32/kconfigs/g4l4l5/Kconfig.clk create mode 100644 cpu/stm32/kconfigs/l0/Kconfig.clk create mode 100644 cpu/stm32/kconfigs/l0l1/Kconfig.clk create mode 100644 cpu/stm32/kconfigs/l1/Kconfig.clk create mode 100644 cpu/stm32/kconfigs/l4/Kconfig.clk create mode 100644 cpu/stm32/kconfigs/l4l5wx/Kconfig.clk create mode 100644 cpu/stm32/kconfigs/l5/Kconfig.clk create mode 100644 cpu/stm32/kconfigs/mp1/Kconfig.clk create mode 100644 cpu/stm32/kconfigs/u5/Kconfig.clk create mode 100644 cpu/stm32/kconfigs/wb/Kconfig.clk create mode 100644 cpu/stm32/kconfigs/wl/Kconfig.clk diff --git a/cpu/stm32/Kconfig b/cpu/stm32/Kconfig index 8cbd0378b016..07a920dc459a 100644 --- a/cpu/stm32/Kconfig +++ b/cpu/stm32/Kconfig @@ -19,6 +19,8 @@ config CPU_STM32 # This CPU requires periph_rtc when periph_rtc_mem select MODULE_PERIPH_RTC if MODULE_PERIPH_RTC_MEM && HAS_PERIPH_RTC +menu "STM32 configuration" + # Common CPU symbol config CPU default "stm32" if CPU_STM32 @@ -39,10 +41,18 @@ config MODULE_BOOTLOADER_STM32 depends on HAS_BOOTLOADER_STM32 depends on TEST_KCONFIG -orsource "kconfigs/Kconfig.clk" -orsource "kconfigs/*/Kconfig" -orsource "kconfigs/*/Kconfig.lines" -orsource "kconfigs/*/Kconfig.models" + +menu "STM32 clock configuration" + depends on CPU_STM32 + +rsource "kconfigs/Kconfig.clk" +rsource "kconfigs/$(CPU_FAM)/Kconfig.clk" + +endmenu + +rsource "kconfigs/$(CPU_FAM)/Kconfig" +rsource "kconfigs/$(CPU_FAM)/Kconfig.lines" +rsource "kconfigs/$(CPU_FAM)/Kconfig.models" choice prompt "ReaDout Protection level" @@ -72,4 +82,6 @@ rsource "vectors/Kconfig" endif # TEST_KCONFIG +endmenu + source "$(RIOTCPU)/cortexm_common/Kconfig" diff --git a/cpu/stm32/kconfigs/Kconfig.clk b/cpu/stm32/kconfigs/Kconfig.clk index 18554d36bc21..1a898ef00bfd 100644 --- a/cpu/stm32/kconfigs/Kconfig.clk +++ b/cpu/stm32/kconfigs/Kconfig.clk @@ -10,8 +10,6 @@ config CLOCK_HAS_NO_MCO_PRE help Indicates that the CPU has no MCO prescaler -menu "STM32 clock configuration" - depends on CPU_STM32 choice bool "Clock source selection" @@ -20,10 +18,6 @@ default USE_CLOCK_PLL config USE_CLOCK_PLL bool "PLL" -config USE_CLOCK_MSI - bool "Use direct multi-speed frequency internal oscillator (MSI)" - depends on CPU_FAM_L0 || CPU_FAM_L1 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL - config USE_CLOCK_HSE bool "Direct High frequency external oscillator (HSE)" depends on BOARD_HAS_HSE @@ -33,345 +27,16 @@ config USE_CLOCK_HSI endchoice -if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL -choice -bool "Source clock for PLL" if USE_CLOCK_PLL -default CLOCK_PLL_SRC_HSE if BOARD_HAS_HSE -default CLOCK_PLL_SRC_MSI - -config CLOCK_PLL_SRC_MSI - bool "Use MSI source clock" - -config CLOCK_PLL_SRC_HSE - bool "Use HSE source clock" +config CLOCK_HSE + int depends on BOARD_HAS_HSE - -config CLOCK_PLL_SRC_HSI - bool "Use HSI16 source clock" -endchoice - -endif # CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL + default 24000000 if CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L0 || CPU_FAM_L1 || CPU_FAM_MP1 + default 8000000 config CUSTOM_PLL_PARAMS bool "Configure PLL parameters" depends on USE_CLOCK_PLL -if CPU_FAM_F2 || CPU_FAM_F4 || CPU_FAM_F7 || CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_MP1 -config CLOCK_PLL_M - int "M: PLLIN division factor" if CUSTOM_PLL_PARAMS - default 4 if CPU_FAM_F2 || CPU_FAM_F4 || CPU_FAM_F7 - default 1 if CPU_FAM_G0 - default 6 if CPU_FAM_G4 && BOARD_HAS_HSE - default 4 if CPU_FAM_G4 - default 6 if (CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL) && CLOCK_PLL_SRC_MSI - default 4 if (CPU_FAM_WB || CPU_FAM_WL) && CLOCK_PLL_SRC_HSE - default 2 if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL || CPU_FAM_MP1 - range 1 8 if CPU_FAM_G0 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL - range 1 16 if CPU_FAM_G4 - -config CLOCK_PLL_N - int "N: PLLIN multiply factor" if CUSTOM_PLL_PARAMS - default 120 if BOARD_HAS_HSE && CPU_FAM_F2 - default 60 if CPU_FAM_F2 - default 168 if CPU_FAM_F4 && CLOCK_MAX_84MHZ && BOARD_HAS_HSE - default 84 if CPU_FAM_F4 && CLOCK_MAX_84MHZ - default 96 if CPU_FAM_F4 && CLOCK_MAX_100MHZ && BOARD_HAS_HSE && (MODULE_PERIPH_USBDEV_CLK || USEMODULE_PERIPH_USBDEV_CLK) - default 48 if CPU_FAM_F4 && CLOCK_MAX_100MHZ && (MODULE_PERIPH_USBDEV_CLK || USEMODULE_PERIPH_USBDEV_CLK) - default 100 if CPU_FAM_F4 && CLOCK_MAX_100MHZ && BOARD_HAS_HSE - default 50 if CPU_FAM_F4 && CLOCK_MAX_100MHZ - default 168 if CPU_FAM_F4 && CLOCK_MAX_180MHZ && BOARD_HAS_HSE && (MODULE_PERIPH_USBDEV_CLK || USEMODULE_PERIPH_USBDEV_CLK) - default 84 if CPU_FAM_F4 && CLOCK_MAX_180MHZ && (MODULE_PERIPH_USBDEV_CLK || USEMODULE_PERIPH_USBDEV_CLK) - default 180 if CPU_FAM_F4 && CLOCK_MAX_180MHZ && BOARD_HAS_HSE - default 90 if CPU_FAM_F4 && CLOCK_MAX_180MHZ - default 216 if CPU_FAM_F7 && BOARD_HAS_HSE - default 108 if CPU_FAM_F7 - default 12 if CPU_FAM_WL - default 16 if CPU_FAM_WB - default 30 if CPU_LINE_STM32L4A6XX || CPU_LINE_STM32L4P5XX || CPU_LINE_STM32L4Q5XX || CPU_LINE_STM32L4R5XX || CPU_LINE_STM32L4R7XX || CPU_LINE_STM32L4R9XX || CPU_LINE_STM32L4S5XX || CPU_LINE_STM32L4S7XX || CPU_LINE_STM32L4S9XX - default 27 if CPU_FAM_L5 - default 20 if CPU_FAM_G0 || CPU_FAM_L4 - default 85 if CPU_FAM_G4 - default 52 if CPU_FAM_MP1 && BOARD_HAS_HSE - default 78 if CPU_FAM_MP1 - range 8 86 if CPU_FAM_G0 || CPU_FAM_L4 || CPU_FAM_L5 - range 50 432 if CPU_FAM_F2 || CPU_FAM_F4 || CPU_FAM_F7 - range 8 127 if CPU_FAM_G4 - range 6 127 if CPU_FAM_WB || CPU_FAM_WL - range 4 512 if CPU_FAM_MP1 - -if CPU_FAM_F2 || CPU_FAM_F4 || CPU_FAM_F7 || CPU_FAM_MP1 -choice -bool "Main PLL division factor (PLLP) for main system clock" if CUSTOM_PLL_PARAMS -default PLL_P_DIV_4 if CPU_FAM_F4 && CLOCK_MAX_84MHZ -default PLL_P_DIV_2 - -config PLL_P_DIV_2 - bool "Divide by 2" - -config PLL_P_DIV_4 - bool "Divide by 4" - -config PLL_P_DIV_6 - bool "Divide by 6" - -config PLL_P_DIV_8 - bool "Divide by 8" - -endchoice - -config CLOCK_PLL_P - int - default 3 if CPU_FAM_MP1 - default 2 if PLL_P_DIV_2 - default 4 if PLL_P_DIV_4 - default 6 if PLL_P_DIV_6 - default 8 if PLL_P_DIV_8 - -config CLOCK_PLL_Q - int "Main PLL division factor (PLLQ) for USB OTG FS, and SDIO clocks" if CUSTOM_PLL_PARAMS - default 5 if CPU_FAM_F2 - default 7 if CPU_FAM_F4 && CLOCK_MAX_84MHZ - default 4 if CPU_FAM_F4 && CLOCK_MAX_100MHZ - default 7 if CPU_FAM_F4 && CLOCK_MAX_180MHZ && (MODULE_PERIPH_USBDEV_CLK || USEMODULE_PERIPH_USBDEV_CLK) - default 9 if CPU_FAM_F7 - default 13 if CPU_FAM_MP1 - default 8 - range 2 15 -endif # CPU_FAM_F2 || CPU_FAM_F4 || CPU_FAM_F7 || CPU_FAM_MP1 - -if CPU_FAM_G0 || CPU_FAM_WB || CPU_FAM_WL || CPU_FAM_MP1 -config CLOCK_PLL_R - int "Q: VCO division factor" if CUSTOM_PLL_PARAMS - default 2 if CPU_FAM_WB || CPU_FAM_WL - default 3 if CPU_FAM_MP1 - default 6 if BOARD_HAS_HSE - default 5 - range 2 8 -endif # CPU_FAM_G0 || CPU_FAM_WB || CPU_FAM_WL || CPU_FAM_MP1 - -if CPU_FAM_G4 || CPU_FAM_L4 || CPU_FAM_L5 -choice -bool "R: Main PLL division factor for PLL 'R' clock (system clock)" if CUSTOM_PLL_PARAMS -default PLL_R_DIV_2 - -config PLL_R_DIV_2 - bool "Divide by 2" - -config PLL_R_DIV_4 - bool "Divide by 4" - -config PLL_R_DIV_6 - bool "Divide by 6" - -config PLL_R_DIV_8 - bool "Divide by 8" - -endchoice - -config CLOCK_PLL_R - int - default 2 if PLL_R_DIV_2 - default 4 if PLL_R_DIV_4 - default 6 if PLL_R_DIV_6 - default 8 if PLL_R_DIV_8 -endif # CPU_FAM_G4 || CPU_FAM_L4 || CPU_FAM_L5 - -endif # CPU_FAM_F2 || CPU_FAM_F4 || CPU_FAM_F7 || CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL || CPU_FAM_MP1 - -if CPU_FAM_F0 || CPU_FAM_F1 || CPU_FAM_F3 -config CLOCK_PLL_PREDIV - int "PLLIN division factor" if CUSTOM_PLL_PARAMS && !CPU_LINE_STM32F031X6 && !CPU_LINE_STM32F042X6 && !CPU_LINE_STM32F303X8 - default 2 if CPU_LINE_STM32F031X6 || CPU_LINE_STM32F042X6 || CPU_LINE_STM32F303X8 || CPU_LINE_STM32F303XC - default 1 - range 1 16 - -config CLOCK_PLL_MUL - int "PLLIN multiply factor" if CUSTOM_PLL_PARAMS - default 16 if CPU_LINE_STM32F303X8 - default 12 if CPU_LINE_STM32F031X6 || CPU_LINE_STM32F042X6 - default 9 if CPU_FAM_F1 || CPU_FAM_F3 - default 6 if CPU_FAM_F0 - range 2 16 -endif # CPU_FAM_F0 || CPU_FAM_F1 || CPU_FAM_F3 - -if CPU_FAM_L0 || CPU_FAM_L1 -config CLOCK_PLL_DIV - int "Main PLL division factor" if CUSTOM_PLL_PARAMS - default 2 - range 2 4 - -choice -bool "Main PLL multiply factor" if CUSTOM_PLL_PARAMS -default PLL_MUL_4 - -config PLL_MUL_3 - bool "Multiply by 3" - -config PLL_MUL_4 - bool "Multiply by 4" - -config PLL_MUL_6 - bool "Multiply by 6" - -config PLL_MUL_8 - bool "Multiply by 8" - -config PLL_MUL_12 - bool "Multiply by 12" - -config PLL_MUL_16 - bool "Multiply by 16" - -config PLL_MUL_24 - bool "Multiply by 24" - -config PLL_MUL_32 - bool "Multiply by 32" - -config PLL_MUL_48 - bool "Multiply by 48" - -endchoice - -config CLOCK_PLL_MUL - int - default 3 if PLL_MUL_3 - default 4 if PLL_MUL_4 - default 6 if PLL_MUL_6 - default 8 if PLL_MUL_8 - default 12 if PLL_MUL_12 - default 16 if PLL_MUL_16 - default 24 if PLL_MUL_24 - default 32 if PLL_MUL_32 - default 48 if PLL_MUL_48 -endif # CPU_FAM_L0 || CPU_FAM_L1 - -if CPU_FAM_G0 -choice -bool "HSISYS division factor" if USE_CLOCK_HSI -default CLOCK_HSISYS_DIV_1 - -config CLOCK_HSISYS_DIV_1 - bool "Divide HSISYS by 1" - -config CLOCK_HSISYS_DIV_2 - bool "Divide HSISYS by 2" - -config CLOCK_HSISYS_DIV_4 - bool "Divide HSISYS by 4" - -config CLOCK_HSISYS_DIV_8 - bool "Divide HSISYS by 8" - -config CLOCK_HSISYS_DIV_16 - bool "Divide HSISYS by 16" - -config CLOCK_HSISYS_DIV_32 - bool "Divide HSISYS by 32" - -config CLOCK_HSISYS_DIV_64 - bool "Divide HSISYS by 64" - -config CLOCK_HSISYS_DIV_128 - bool "Divide HSISYS by 128" - -endchoice - -config CLOCK_HSISYS_DIV - int - default 1 if CLOCK_HSISYS_DIV_1 - default 2 if CLOCK_HSISYS_DIV_2 - default 4 if CLOCK_HSISYS_DIV_4 - default 8 if CLOCK_HSISYS_DIV_8 - default 16 if CLOCK_HSISYS_DIV_16 - default 32 if CLOCK_HSISYS_DIV_32 - default 64 if CLOCK_HSISYS_DIV_64 - default 128 if CLOCK_HSISYS_DIV_128 -endif # CPU_FAM_G0 - -if CPU_FAM_L0 || CPU_FAM_L1 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL -choice -bool "Desired MSI clock frequency" if USE_CLOCK_MSI || (USE_CLOCK_PLL && CLOCK_PLL_SRC_MSI) -default CLOCK_MSI_48MHZ if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL -default CLOCK_MSI_4MHZ - -config CLOCK_MSI_65KHZ - bool "65.536kHz" if CPU_FAM_L0 || CPU_FAM_L1 - -config CLOCK_MSI_100KHZ - bool "100kHz" if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL - -config CLOCK_MSI_130KHZ - bool "131.072kHz" if CPU_FAM_L0 || CPU_FAM_L1 - -config CLOCK_MSI_200KHZ - bool "200kHz" if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL - -config CLOCK_MSI_260KHZ - bool "262.144kHz" if CPU_FAM_L0 || CPU_FAM_L1 - -config CLOCK_MSI_400KHZ - bool "400kHz" if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL - -config CLOCK_MSI_520KHZ - bool "524.288kHz" if CPU_FAM_L0 || CPU_FAM_L1 - -config CLOCK_MSI_800KHZ - bool "800kHz" if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL - -config CLOCK_MSI_1MHZ - bool - prompt "1MHz" - -config CLOCK_MSI_2MHZ - bool - prompt "2MHz" - -config CLOCK_MSI_4MHZ - bool - prompt "4MHz" - -config CLOCK_MSI_8MHZ - bool "8MHz" if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL - -config CLOCK_MSI_16MHZ - bool "16MHz" if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL - -config CLOCK_MSI_24MHZ - bool "24MHz" if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL - -config CLOCK_MSI_32MHZ - bool "32MHz" if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL - -config CLOCK_MSI_48MHZ - bool "48MHz" if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL - -endchoice - -config CLOCK_MSI - int - default 65536 if CLOCK_MSI_65KHZ - default 131072 if CLOCK_MSI_130KHZ - default 262144 if CLOCK_MSI_260KHZ - default 524288 if CLOCK_MSI_520KHZ - default 100000 if CLOCK_MSI_100KHZ - default 200000 if CLOCK_MSI_200KHZ - default 400000 if CLOCK_MSI_400KHZ - default 800000 if CLOCK_MSI_800KHZ - default 1000000 if CLOCK_MSI_1MHZ && (CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL) - default 1048000 if CLOCK_MSI_1MHZ && (CPU_FAM_L0 || CPU_FAM_L1) - default 2000000 if CLOCK_MSI_2MHZ && (CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL) - default 2097000 if CLOCK_MSI_2MHZ && (CPU_FAM_L0 || CPU_FAM_L1) - default 4000000 if CLOCK_MSI_4MHZ && (CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL) - default 4194000 if CLOCK_MSI_4MHZ && (CPU_FAM_L0 || CPU_FAM_L1) - default 8000000 if CLOCK_MSI_8MHZ - default 16000000 if CLOCK_MSI_16MHZ - default 24000000 if CLOCK_MSI_24MHZ - default 32000000 if CLOCK_MSI_32MHZ - default 48000000 if CLOCK_MSI_48MHZ - -endif # CPU_FAM_L0 || CPU_FAM_L1 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL - choice bool "APB1 prescaler (division factor of HCLK to produce PCLK1)" default CLOCK_APB1_DIV_4 if CPU_FAM_F2 || (CPU_FAM_F4 && CLOCK_MAX_180MHZ) || CPU_FAM_F7 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_U5 || CPU_FAM_WB || CPU_FAM_WL @@ -433,87 +98,3 @@ config CLOCK_APB2_DIV default 4 if CLOCK_APB2_DIV_4 default 8 if CLOCK_APB2_DIV_8 default 16 if CLOCK_APB2_DIV_16 - -if CPU_FAM_F0 || CPU_FAM_F1 || CPU_FAM_F3 || CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L0 || CPU_FAM_L1 || CPU_FAM_L4 || CPU_FAM_WB || CPU_FAM_WL -config CLOCK_ENABLE_MCO - bool "Enable MCU Clock Output (MCO) on PA8" - -choice -bool "MCO source" -depends on CLOCK_ENABLE_MCO -default CLOCK_MCO_USE_PLLCLK - -config CLOCK_MCO_USE_PLLCLK - bool "Use PLLCLK as MCO source" - -config CLOCK_MCO_USE_HSE - bool "Use HSE as MCO source" - -config CLOCK_MCO_USE_HSI - bool "Use HSI as MCO source" - -config CLOCK_MCO_USE_LSE - bool "Use LSE as MCO source" - depends on CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L0 || CPU_FAM_L1 || CPU_FAM_L4 || CPU_FAM_WB || CPU_FAM_WL - -config CLOCK_MCO_USE_LSI - bool "Use LSI as MCO source" - depends on CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L0 || CPU_FAM_L1 || CPU_FAM_L4 || CPU_FAM_WB || CPU_FAM_WL - -config CLOCK_MCO_USE_MSI - bool "Use MSI as MCO source" - depends on CPU_FAM_L0 || CPU_FAM_L1 || CPU_FAM_L4 || CPU_FAM_WB || CPU_FAM_WL - -config CLOCK_MCO_USE_SYSCLK - bool "Use SYSCLK as MCO source" - -endchoice - -choice -bool "MCO prescaler" -depends on !CLOCK_HAS_NO_MCO_PRE && CLOCK_ENABLE_MCO -default CLOCK_MCO_PRE_1 - -config CLOCK_MCO_PRE_1 - bool "Divide MCO by 1" - -config CLOCK_MCO_PRE_2 - bool "Divide MCO by 2" - -config CLOCK_MCO_PRE_4 - bool "Divide MCO by 4" - -config CLOCK_MCO_PRE_8 - bool "Divide MCO by 8" - -config CLOCK_MCO_PRE_16 - bool "Divide MCO by 16" - -config CLOCK_MCO_PRE_32 - bool "Divide MCO by 32" - depends on !CPU_FAM_G4 && !CPU_FAM_L0 && !CPU_FAM_L1 && !CPU_FAM_L4 && !CPU_FAM_WB && !CPU_FAM_WL - -config CLOCK_MCO_PRE_64 - bool "Divide MCO by 64" - depends on !CPU_FAM_G4 && !CPU_FAM_L0 && !CPU_FAM_L1 && !CPU_FAM_L4 && !CPU_FAM_WB && !CPU_FAM_WL - -config CLOCK_MCO_PRE_128 - bool "Divide MCO by 128" - depends on !CPU_FAM_G4 && !CPU_FAM_L0 && !CPU_FAM_L1 && !CPU_FAM_L4 && !CPU_FAM_WB && !CPU_FAM_WL - -endchoice - -config CLOCK_MCO_PRE - int - default 2 if CLOCK_MCO_PRE_2 - default 4 if CLOCK_MCO_PRE_4 - default 8 if CLOCK_MCO_PRE_8 - default 16 if CLOCK_MCO_PRE_16 - default 32 if CLOCK_MCO_PRE_32 - default 64 if CLOCK_MCO_PRE_64 - default 128 if CLOCK_MCO_PRE_128 - default 1 - -endif # CPU_FAM_F0 || CPU_FAM_F1 || CPU_FAM_F3 || CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L0 || CPU_FAM_L1 || CPU_FAM_L4 || CPU_FAM_WB || CPU_FAM_WL - -endmenu diff --git a/cpu/stm32/kconfigs/f0/Kconfig.clk b/cpu/stm32/kconfigs/f0/Kconfig.clk new file mode 100644 index 000000000000..d4c08b1aa6f8 --- /dev/null +++ b/cpu/stm32/kconfigs/f0/Kconfig.clk @@ -0,0 +1,8 @@ +# Copyright (c) 2022 HAW Hamburg +# +# This file is subject to the terms and conditions of the GNU Lesser +# General Public License v2.1. See the file LICENSE in the top level +# directory for more details. +# + +rsource '../f0f1f3/Kconfig.clk' diff --git a/cpu/stm32/kconfigs/f0/Kconfig.lines b/cpu/stm32/kconfigs/f0/Kconfig.lines index e52ba029c1a7..28226e48813e 100644 --- a/cpu/stm32/kconfigs/f0/Kconfig.lines +++ b/cpu/stm32/kconfigs/f0/Kconfig.lines @@ -28,6 +28,7 @@ config CPU_LINE_STM32F031X6 select CPU_FAM_F0 select HAS_PERIPH_RTC_MEM select HAS_PERIPH_VBAT + select HAVE_CLOCK_PLL_PREDIV_HARDWIRED_2 config CPU_LINE_STM32F038XX bool @@ -40,6 +41,7 @@ config CPU_LINE_STM32F042X6 select CPU_FAM_F0 select HAS_PERIPH_RTC_MEM select HAS_PERIPH_VBAT + select HAVE_CLOCK_PLL_PREDIV_HARDWIRED_2 config CPU_LINE_STM32F048XX bool diff --git a/cpu/stm32/kconfigs/f0f1f3/Kconfig.clk b/cpu/stm32/kconfigs/f0f1f3/Kconfig.clk new file mode 100644 index 000000000000..21ef7de8b9a8 --- /dev/null +++ b/cpu/stm32/kconfigs/f0f1f3/Kconfig.clk @@ -0,0 +1,31 @@ +# Copyright (c) 2022 HAW Hamburg +# +# This file is subject to the terms and conditions of the GNU Lesser +# General Public License v2.1. See the file LICENSE in the top level +# directory for more details. +# + +if CPU_FAM_F0 || CPU_FAM_F1 || CPU_FAM_F3 + +config CLOCK_PLL_PREDIV + int "PLLIN division factor" if CUSTOM_PLL_PARAMS && !HAVE_CLOCK_PLL_PREDIV_HARDWIRED_2 + default 2 if HAVE_CLOCK_PLL_PREDIV_HARDWIRED_2 || CLOCK_HSE = 16000000 + default 1 + range 1 16 + +config CLOCK_PLL_MUL + int "PLLIN multiply factor" if CUSTOM_PLL_PARAMS + default 12 if CPU_FAM_F0 && HAVE_CLOCK_PLL_PREDIV_HARDWIRED_2 + default 6 if CPU_FAM_F0 + default 16 if CPU_FAM_F3 && HAVE_CLOCK_PLL_PREDIV_HARDWIRED_2 + default 9 if CPU_FAM_F1 || CPU_FAM_F3 + + range 2 16 + +config HAVE_CLOCK_PLL_PREDIV_HARDWIRED_2 + bool + help + Indicated that this CPU Line has the prediv hardwired to 2, making it + unable to change. + +endif # CPU_FAM_F0 || CPU_FAM_F1 || CPU_FAM_F3 diff --git a/cpu/stm32/kconfigs/f0f1f3g0g4l0l1l4wbwl/Kconfig.clk b/cpu/stm32/kconfigs/f0f1f3g0g4l0l1l4wbwl/Kconfig.clk new file mode 100644 index 000000000000..b08de4271971 --- /dev/null +++ b/cpu/stm32/kconfigs/f0f1f3g0g4l0l1l4wbwl/Kconfig.clk @@ -0,0 +1,89 @@ +# Copyright (c) 2022 HAW Hamburg +# +# This file is subject to the terms and conditions of the GNU Lesser +# General Public License v2.1. See the file LICENSE in the top level +# directory for more details. +# + +if CPU_FAM_F0 || CPU_FAM_F1 || CPU_FAM_F3 || CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L0 || CPU_FAM_L4 || CPU_FAM_WB || CPU_FAM_WL + +config CLOCK_ENABLE_MCO + bool "Enable MCU Clock Output (MCO) on PA8" + +choice +bool "MCO source" +depends on CLOCK_ENABLE_MCO +default CLOCK_MCO_USE_PLLCLK + +config CLOCK_MCO_USE_PLLCLK + bool "Use PLLCLK as MCO source" + +config CLOCK_MCO_USE_HSE + bool "Use HSE as MCO source" + +config CLOCK_MCO_USE_HSI + bool "Use HSI as MCO source" + +config CLOCK_MCO_USE_LSE + bool "Use LSE as MCO source" + depends on CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L0 || CPU_FAM_L1 || CPU_FAM_L4 || CPU_FAM_WB || CPU_FAM_WL + +config CLOCK_MCO_USE_LSI + bool "Use LSI as MCO source" + depends on CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L0 || CPU_FAM_L1 || CPU_FAM_L4 || CPU_FAM_WB || CPU_FAM_WL + +config CLOCK_MCO_USE_MSI + bool "Use MSI as MCO source" + depends on CPU_FAM_L0 || CPU_FAM_L1 || CPU_FAM_L4 || CPU_FAM_WB || CPU_FAM_WL + +config CLOCK_MCO_USE_SYSCLK + bool "Use SYSCLK as MCO source" + +endchoice + +choice +bool "MCO prescaler" +depends on !CLOCK_HAS_NO_MCO_PRE && CLOCK_ENABLE_MCO +default CLOCK_MCO_PRE_1 + +config CLOCK_MCO_PRE_1 + bool "Divide MCO by 1" + +config CLOCK_MCO_PRE_2 + bool "Divide MCO by 2" + +config CLOCK_MCO_PRE_4 + bool "Divide MCO by 4" + +config CLOCK_MCO_PRE_8 + bool "Divide MCO by 8" + +config CLOCK_MCO_PRE_16 + bool "Divide MCO by 16" + +config CLOCK_MCO_PRE_32 + bool "Divide MCO by 32" + depends on CPU_FAM_F0 || CPU_FAM_F1 || CPU_FAM_F3 || CPU_FAM_G0 + +config CLOCK_MCO_PRE_64 + bool "Divide MCO by 64" + depends on CPU_FAM_F0 || CPU_FAM_F1 || CPU_FAM_F3 || CPU_FAM_G0 + +config CLOCK_MCO_PRE_128 + bool "Divide MCO by 128" + depends on CPU_FAM_F0 || CPU_FAM_F1 || CPU_FAM_F3 || CPU_FAM_G0 + +endchoice + +config CLOCK_MCO_PRE + int + default 2 if CLOCK_MCO_PRE_2 + default 4 if CLOCK_MCO_PRE_4 + default 8 if CLOCK_MCO_PRE_8 + default 16 if CLOCK_MCO_PRE_16 + default 32 if CLOCK_MCO_PRE_32 + default 64 if CLOCK_MCO_PRE_64 + default 128 if CLOCK_MCO_PRE_128 + default 1 + +endif # CPU_FAM_F0 || CPU_FAM_F1 || CPU_FAM_F3 || CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L0 || CPU_FAM_L4 || CPU_FAM_WB || CPU_FAM_WL diff --git a/cpu/stm32/kconfigs/f1/Kconfig.clk b/cpu/stm32/kconfigs/f1/Kconfig.clk new file mode 100644 index 000000000000..d4c08b1aa6f8 --- /dev/null +++ b/cpu/stm32/kconfigs/f1/Kconfig.clk @@ -0,0 +1,8 @@ +# Copyright (c) 2022 HAW Hamburg +# +# This file is subject to the terms and conditions of the GNU Lesser +# General Public License v2.1. See the file LICENSE in the top level +# directory for more details. +# + +rsource '../f0f1f3/Kconfig.clk' diff --git a/cpu/stm32/kconfigs/f2/Kconfig.clk b/cpu/stm32/kconfigs/f2/Kconfig.clk new file mode 100644 index 000000000000..bea4721017ef --- /dev/null +++ b/cpu/stm32/kconfigs/f2/Kconfig.clk @@ -0,0 +1,22 @@ +# Copyright (c) 2022 HAW Hamburg +# +# This file is subject to the terms and conditions of the GNU Lesser +# General Public License v2.1. See the file LICENSE in the top level +# directory for more details. +# + +rsource '../f2f4f7mp1/Kconfig.clk' + +if CPU_FAM_F2 + +config CLOCK_PLL_M + int "M: PLLIN division factor" if CUSTOM_PLL_PARAMS + default 4 + +config CLOCK_PLL_N + int "N: PLLIN multiply factor" if CUSTOM_PLL_PARAMS + default 120 if CLOCK_HSE = 8000000 + default 60 + range 50 432 + +endif # CPU_FAM_F2 diff --git a/cpu/stm32/kconfigs/f2f4f7mp1/Kconfig.clk b/cpu/stm32/kconfigs/f2f4f7mp1/Kconfig.clk new file mode 100644 index 000000000000..5900f0247eb4 --- /dev/null +++ b/cpu/stm32/kconfigs/f2f4f7mp1/Kconfig.clk @@ -0,0 +1,54 @@ +# Copyright (c) 2022 HAW Hamburg +# +# This file is subject to the terms and conditions of the GNU Lesser +# General Public License v2.1. See the file LICENSE in the top level +# directory for more details. +# + +if CPU_FAM_F2 || CPU_FAM_F4 || CPU_FAM_F7 || CPU_FAM_MP1 + +choice +bool "Main PLL division factor (PLLP) for main system clock" if CUSTOM_PLL_PARAMS +default PLL_P_DIV_4 if CPU_FAM_F4 && CLOCK_MAX_84MHZ +default PLL_P_DIV_2 + +config PLL_P_DIV_2 + bool "Divide by 2" + +config PLL_P_DIV_4 + bool "Divide by 4" + +config PLL_P_DIV_6 + bool "Divide by 6" + +config PLL_P_DIV_8 + bool "Divide by 8" + +endchoice + +config CLOCK_PLL_P + int + default 3 if CPU_FAM_MP1 + default 2 if PLL_P_DIV_2 + default 4 if PLL_P_DIV_4 + default 6 if PLL_P_DIV_6 + default 8 if PLL_P_DIV_8 + +config CLOCK_PLL_Q + int "Main PLL division factor (PLLQ) for USB OTG FS, and SDIO clocks" if CUSTOM_PLL_PARAMS + default 5 if CPU_FAM_F2 + default 7 if CPU_FAM_F4 && CLOCK_MAX_84MHZ + default 4 if CPU_FAM_F4 && CLOCK_MAX_100MHZ + default 7 if CPU_FAM_F4 && CLOCK_MAX_180MHZ && (MODULE_PERIPH_USBDEV_CLK || USEMODULE_PERIPH_USBDEV_CLK) && !HAVE_CLOCK_ALT_48MHZ + default 9 if CPU_FAM_F7 + default 13 if CPU_FAM_MP1 + default 8 + range 2 15 + +config HAVE_CLOCK_ALT_48MHZ + bool + help + Indicates this CPU has an alternate clock source that can be used to + provide 48 MHz for the USB peripheral. + +endif # CPU_FAM_F2 || CPU_FAM_F4 || CPU_FAM_F7 || CPU_FAM_MP1 diff --git a/cpu/stm32/kconfigs/f3/Kconfig.clk b/cpu/stm32/kconfigs/f3/Kconfig.clk new file mode 100644 index 000000000000..d4c08b1aa6f8 --- /dev/null +++ b/cpu/stm32/kconfigs/f3/Kconfig.clk @@ -0,0 +1,8 @@ +# Copyright (c) 2022 HAW Hamburg +# +# This file is subject to the terms and conditions of the GNU Lesser +# General Public License v2.1. See the file LICENSE in the top level +# directory for more details. +# + +rsource '../f0f1f3/Kconfig.clk' diff --git a/cpu/stm32/kconfigs/f3/Kconfig.lines b/cpu/stm32/kconfigs/f3/Kconfig.lines index 8a07aaf22fdb..f964c3a9777a 100644 --- a/cpu/stm32/kconfigs/f3/Kconfig.lines +++ b/cpu/stm32/kconfigs/f3/Kconfig.lines @@ -27,15 +27,27 @@ config CPU_LINE_STM32F302XE bool select CPU_FAM_F3 +config CPU_LINE_STM32F303X6 + bool + select CPU_FAM_F3 + select HAVE_CLOCK_PLL_PREDIV_HARDWIRED_2 + config CPU_LINE_STM32F303X8 bool select CPU_FAM_F3 + select HAVE_CLOCK_PLL_PREDIV_HARDWIRED_2 + +config CPU_LINE_STM32F303XB + bool + select CPU_FAM_F3 + select HAVE_CLOCK_PLL_PREDIV_HARDWIRED_2 config CPU_LINE_STM32F303XC bool select CPU_FAM_F3 select HAS_CORTEXM_MPU select CLOCK_HAS_NO_MCO_PRE + select HAVE_CLOCK_PLL_PREDIV_HARDWIRED_2 config CPU_LINE_STM32F303XE bool @@ -49,6 +61,7 @@ config CPU_LINE_STM32F318XX config CPU_LINE_STM32F328XX bool select CPU_FAM_F3 + select HAVE_CLOCK_PLL_PREDIV_HARDWIRED_2 config CPU_LINE_STM32F334X8 bool diff --git a/cpu/stm32/kconfigs/f4/Kconfig.clk b/cpu/stm32/kconfigs/f4/Kconfig.clk new file mode 100644 index 000000000000..88f7037dafda --- /dev/null +++ b/cpu/stm32/kconfigs/f4/Kconfig.clk @@ -0,0 +1,43 @@ +# Copyright (c) 2022 HAW Hamburg +# +# This file is subject to the terms and conditions of the GNU Lesser +# General Public License v2.1. See the file LICENSE in the top level +# directory for more details. +# + +rsource '../f2f4f7mp1/Kconfig.clk' + +if CPU_FAM_F4 + +config CLOCK_PLL_M + int "M: PLLIN division factor" if CUSTOM_PLL_PARAMS + default 25 if CLOCK_MAX_84MHZ && CLOCK_HSE = 25000000 + default 25 if CLOCK_MAX_100MHZ && CLOCK_HSE = 25000000 + default 12 if CLOCK_MAX_180MHZ && CLOCK_HSE = 16000000 + default 12 if CLOCK_MAX_180MHZ && CLOCK_HSE = 12000000 + default 4 + +config CLOCK_PLL_N + int "N: PLLIN multiply factor" if CUSTOM_PLL_PARAMS + default 168 if CLOCK_MAX_84MHZ && CLOCK_HSE = 8000000 + default 336 if CLOCK_MAX_84MHZ && CLOCK_HSE = 25000000 + default 84 if CLOCK_MAX_84MHZ + + default 96 if CLOCK_MAX_100MHZ && CLOCK_HSE = 8000000 && (MODULE_PERIPH_USBDEV_CLK || USEMODULE_PERIPH_USBDEV_CLK) && !HAVE_CLOCK_ALT_48MHZ + default 100 if CLOCK_MAX_100MHZ && CLOCK_HSE = 8000000 + default 192 if CLOCK_MAX_100MHZ && CLOCK_HSE = 25000000 && (MODULE_PERIPH_USBDEV_CLK || USEMODULE_PERIPH_USBDEV_CLK) && !HAVE_CLOCK_ALT_48MHZ + default 200 if CLOCK_MAX_100MHZ && CLOCK_HSE = 25000000 + default 48 if CLOCK_MAX_100MHZ && (MODULE_PERIPH_USBDEV_CLK || USEMODULE_PERIPH_USBDEV_CLK) + default 50 if CLOCK_MAX_100MHZ + + default 168 if CLOCK_MAX_180MHZ && CLOCK_HSE = 8000000 && (MODULE_PERIPH_USBDEV_CLK || USEMODULE_PERIPH_USBDEV_CLK) && !HAVE_CLOCK_ALT_48MHZ + default 180 if CLOCK_MAX_180MHZ && CLOCK_HSE = 8000000 + default 336 if CLOCK_MAX_180MHZ && CLOCK_HSE = 12000000 && (MODULE_PERIPH_USBDEV_CLK || USEMODULE_PERIPH_USBDEV_CLK) && !HAVE_CLOCK_ALT_48MHZ + default 360 if CLOCK_MAX_180MHZ && CLOCK_HSE = 12000000 + default 336 if CLOCK_MAX_180MHZ && CLOCK_HSE = 16000000 && (MODULE_PERIPH_USBDEV_CLK || USEMODULE_PERIPH_USBDEV_CLK) && !HAVE_CLOCK_ALT_48MHZ + default 360 if CLOCK_MAX_180MHZ && CLOCK_HSE = 16000000 + default 84 if CLOCK_MAX_180MHZ && (MODULE_PERIPH_USBDEV_CLK || USEMODULE_PERIPH_USBDEV_CLK) && !HAVE_CLOCK_ALT_48MHZ + default 90 if CLOCK_MAX_180MHZ + range 50 432 + +endif # CPU_FAM_F4 diff --git a/cpu/stm32/kconfigs/f4/Kconfig.lines b/cpu/stm32/kconfigs/f4/Kconfig.lines index 21938fec4d7c..40491548da83 100644 --- a/cpu/stm32/kconfigs/f4/Kconfig.lines +++ b/cpu/stm32/kconfigs/f4/Kconfig.lines @@ -59,28 +59,33 @@ config CPU_LINE_STM32F412CX bool select CPU_FAM_F4 select CLOCK_MAX_100MHZ + select HAVE_CLOCK_ALT_48MHZ config CPU_LINE_STM32F412RX bool select CPU_FAM_F4 select CLOCK_MAX_100MHZ + select HAVE_CLOCK_ALT_48MHZ config CPU_LINE_STM32F412VX bool select CPU_FAM_F4 select CLOCK_MAX_100MHZ + select HAVE_CLOCK_ALT_48MHZ config CPU_LINE_STM32F412ZX bool select CPU_FAM_F4 select HAS_PERIPH_HWRNG select CLOCK_MAX_100MHZ + select HAVE_CLOCK_ALT_48MHZ config CPU_LINE_STM32F413XX bool select CPU_FAM_F4 select HAS_PERIPH_HWRNG select CLOCK_MAX_100MHZ + select HAVE_CLOCK_ALT_48MHZ config CPU_LINE_STM32F415XX bool @@ -99,6 +104,7 @@ config CPU_LINE_STM32F423XX bool select CPU_FAM_F4 select CLOCK_MAX_100MHZ + select HAVE_CLOCK_ALT_48MHZ config CPU_LINE_STM32F427XX bool @@ -132,6 +138,7 @@ config CPU_LINE_STM32F446XX select CPU_FAM_F4 select HAS_BACKUP_RAM select CLOCK_MAX_180MHZ + select HAVE_CLOCK_ALT_48MHZ config CPU_LINE_STM32F469XX bool @@ -139,9 +146,11 @@ config CPU_LINE_STM32F469XX select HAS_BACKUP_RAM select HAS_PERIPH_HWRNG select CLOCK_MAX_180MHZ + select HAVE_CLOCK_ALT_48MHZ config CPU_LINE_STM32F479XX bool select CPU_FAM_F4 select HAS_BACKUP_RAM select CLOCK_MAX_180MHZ + select HAVE_CLOCK_ALT_48MHZ diff --git a/cpu/stm32/kconfigs/f7/Kconfig b/cpu/stm32/kconfigs/f7/Kconfig index 79bfb37d6af2..8b07ec2ecae4 100644 --- a/cpu/stm32/kconfigs/f7/Kconfig +++ b/cpu/stm32/kconfigs/f7/Kconfig @@ -22,6 +22,7 @@ config CPU_FAM_F7 select HAS_PERIPH_VBAT select HAS_PERIPH_WDT select HAS_BOOTLOADER_STM32 + select HAVE_CLOCK_ALT_48MHZ config CPU_FAM default "f7" if CPU_FAM_F7 diff --git a/cpu/stm32/kconfigs/f7/Kconfig.clk b/cpu/stm32/kconfigs/f7/Kconfig.clk new file mode 100644 index 000000000000..25a8096abeb0 --- /dev/null +++ b/cpu/stm32/kconfigs/f7/Kconfig.clk @@ -0,0 +1,24 @@ +# Copyright (c) 2022 HAW Hamburg +# +# This file is subject to the terms and conditions of the GNU Lesser +# General Public License v2.1. See the file LICENSE in the top level +# directory for more details. +# + +rsource '../f2f4f7mp1/Kconfig.clk' + +if CPU_FAM_F7 + +config CLOCK_PLL_M + int "M: PLLIN division factor" if CUSTOM_PLL_PARAMS + default 25 if CLOCK_HSE = 25000000 + default 4 + +config CLOCK_PLL_N + int "N: PLLIN multiply factor" if CUSTOM_PLL_PARAMS + default 216 if CLOCK_HSE = 8000000 + default 432 if CLOCK_HSE = 25000000 + default 108 + range 50 432 + +endif # CPU_FAM_F7 diff --git a/cpu/stm32/kconfigs/g0/Kconfig.clk b/cpu/stm32/kconfigs/g0/Kconfig.clk new file mode 100644 index 000000000000..6a304bedce65 --- /dev/null +++ b/cpu/stm32/kconfigs/g0/Kconfig.clk @@ -0,0 +1,63 @@ +# Copyright (c) 2022 HAW Hamburg +# +# This file is subject to the terms and conditions of the GNU Lesser +# General Public License v2.1. See the file LICENSE in the top level +# directory for more details. +# + +rsource '../g0wxmp1/Kconfig.clk' + +if CPU_FAM_G0 + +config CLOCK_PLL_M + int "M: PLLIN division factor" if CUSTOM_PLL_PARAMS + default 1 + range 1 8 + +config CLOCK_PLL_N + int "N: PLLIN multiply factor" if CUSTOM_PLL_PARAMS + default 20 + range 8 86 + +choice +bool "HSISYS division factor" if USE_CLOCK_HSI +default CLOCK_HSISYS_DIV_1 + +config CLOCK_HSISYS_DIV_1 + bool "Divide HSISYS by 1" + +config CLOCK_HSISYS_DIV_2 + bool "Divide HSISYS by 2" + +config CLOCK_HSISYS_DIV_4 + bool "Divide HSISYS by 4" + +config CLOCK_HSISYS_DIV_8 + bool "Divide HSISYS by 8" + +config CLOCK_HSISYS_DIV_16 + bool "Divide HSISYS by 16" + +config CLOCK_HSISYS_DIV_32 + bool "Divide HSISYS by 32" + +config CLOCK_HSISYS_DIV_64 + bool "Divide HSISYS by 64" + +config CLOCK_HSISYS_DIV_128 + bool "Divide HSISYS by 128" + +endchoice + +config CLOCK_HSISYS_DIV + int + default 1 if CLOCK_HSISYS_DIV_1 + default 2 if CLOCK_HSISYS_DIV_2 + default 4 if CLOCK_HSISYS_DIV_4 + default 8 if CLOCK_HSISYS_DIV_8 + default 16 if CLOCK_HSISYS_DIV_16 + default 32 if CLOCK_HSISYS_DIV_32 + default 64 if CLOCK_HSISYS_DIV_64 + default 128 if CLOCK_HSISYS_DIV_128 + +endif # CPU_FAM_G0 diff --git a/cpu/stm32/kconfigs/g0wxmp1/Kconfig.clk b/cpu/stm32/kconfigs/g0wxmp1/Kconfig.clk new file mode 100644 index 000000000000..b0092c6156b4 --- /dev/null +++ b/cpu/stm32/kconfigs/g0wxmp1/Kconfig.clk @@ -0,0 +1,18 @@ +# Copyright (c) 2022 HAW Hamburg +# +# This file is subject to the terms and conditions of the GNU Lesser +# General Public License v2.1. See the file LICENSE in the top level +# directory for more details. +# + +if CPU_FAM_G0 || CPU_FAM_WB || CPU_FAM_WL || CPU_FAM_MP1 + +config CLOCK_PLL_R + int "Q: VCO division factor" if CUSTOM_PLL_PARAMS + default 2 if CPU_FAM_WB || CPU_FAM_WL + default 3 if CPU_FAM_MP1 + default 6 if BOARD_HAS_HSE + default 5 + range 2 8 + +endif # CPU_FAM_G0 || CPU_FAM_WB || CPU_FAM_WL || CPU_FAM_MP1 diff --git a/cpu/stm32/kconfigs/g4/Kconfig.clk b/cpu/stm32/kconfigs/g4/Kconfig.clk new file mode 100644 index 000000000000..5253a6518e51 --- /dev/null +++ b/cpu/stm32/kconfigs/g4/Kconfig.clk @@ -0,0 +1,23 @@ +# Copyright (c) 2022 HAW Hamburg +# +# This file is subject to the terms and conditions of the GNU Lesser +# General Public License v2.1. See the file LICENSE in the top level +# directory for more details. +# + +rsource '../g4l4l5/Kconfig.clk' + +if CPU_FAM_G4 + +config CLOCK_PLL_M + int "M: PLLIN division factor" if CUSTOM_PLL_PARAMS + default 6 if BOARD_HAS_HSE + default 4 + range 1 16 + +config CLOCK_PLL_N + int "N: PLLIN multiply factor" if CUSTOM_PLL_PARAMS + default 85 + range 8 127 + +endif # CPU_FAM_G4 diff --git a/cpu/stm32/kconfigs/g4l4l5/Kconfig.clk b/cpu/stm32/kconfigs/g4l4l5/Kconfig.clk new file mode 100644 index 000000000000..313c4284fae4 --- /dev/null +++ b/cpu/stm32/kconfigs/g4l4l5/Kconfig.clk @@ -0,0 +1,35 @@ +# Copyright (c) 2022 HAW Hamburg +# +# This file is subject to the terms and conditions of the GNU Lesser +# General Public License v2.1. See the file LICENSE in the top level +# directory for more details. +# + +if CPU_FAM_G4 || CPU_FAM_L4 || CPU_FAM_L5 + +choice +bool "R: Main PLL division factor for PLL 'R' clock (system clock)" if CUSTOM_PLL_PARAMS +default PLL_R_DIV_2 + +config PLL_R_DIV_2 + bool "Divide by 2" + +config PLL_R_DIV_4 + bool "Divide by 4" + +config PLL_R_DIV_6 + bool "Divide by 6" + +config PLL_R_DIV_8 + bool "Divide by 8" + +endchoice + +config CLOCK_PLL_R + int + default 2 if PLL_R_DIV_2 + default 4 if PLL_R_DIV_4 + default 6 if PLL_R_DIV_6 + default 8 if PLL_R_DIV_8 + +endif # CPU_FAM_G4 || CPU_FAM_L4 || CPU_FAM_L5 diff --git a/cpu/stm32/kconfigs/l0/Kconfig.clk b/cpu/stm32/kconfigs/l0/Kconfig.clk new file mode 100644 index 000000000000..cab42844c3c5 --- /dev/null +++ b/cpu/stm32/kconfigs/l0/Kconfig.clk @@ -0,0 +1,8 @@ +# Copyright (c) 2022 HAW Hamburg +# +# This file is subject to the terms and conditions of the GNU Lesser +# General Public License v2.1. See the file LICENSE in the top level +# directory for more details. +# + +rsource '../l0l1/Kconfig.clk' diff --git a/cpu/stm32/kconfigs/l0l1/Kconfig.clk b/cpu/stm32/kconfigs/l0l1/Kconfig.clk new file mode 100644 index 000000000000..eb4bd7d3e106 --- /dev/null +++ b/cpu/stm32/kconfigs/l0l1/Kconfig.clk @@ -0,0 +1,112 @@ +# Copyright (c) 2022 HAW Hamburg +# +# This file is subject to the terms and conditions of the GNU Lesser +# General Public License v2.1. See the file LICENSE in the top level +# directory for more details. +# + +if CPU_FAM_L0 || CPU_FAM_L1 + +config CLOCK_PLL_DIV + int "Main PLL division factor" if CUSTOM_PLL_PARAMS + default 2 + range 2 4 + +choice +bool "Main PLL multiply factor" if CUSTOM_PLL_PARAMS +default PLL_MUL_4 + +config PLL_MUL_3 + bool "Multiply by 3" + +config PLL_MUL_4 + bool "Multiply by 4" + +config PLL_MUL_6 + bool "Multiply by 6" + +config PLL_MUL_8 + bool "Multiply by 8" + +config PLL_MUL_12 + bool "Multiply by 12" + +config PLL_MUL_16 + bool "Multiply by 16" + +config PLL_MUL_24 + bool "Multiply by 24" + +config PLL_MUL_32 + bool "Multiply by 32" + +config PLL_MUL_48 + bool "Multiply by 48" + +endchoice + +config CLOCK_PLL_MUL + int + default 3 if PLL_MUL_3 + default 4 if PLL_MUL_4 + default 6 if PLL_MUL_6 + default 8 if PLL_MUL_8 + default 12 if PLL_MUL_12 + default 16 if PLL_MUL_16 + default 24 if PLL_MUL_24 + default 32 if PLL_MUL_32 + default 48 if PLL_MUL_48 + +config USE_CLOCK_MSI + bool "Use direct multi-speed frequency internal oscillator (MSI)" + +choice +bool "Desired MSI clock frequency" if USE_CLOCK_MSI || (USE_CLOCK_PLL && CLOCK_PLL_SRC_MSI) +default CLOCK_MSI_4MHZ + +config CLOCK_MSI_65KHZ + bool "65.536kHz" + +config CLOCK_MSI_130KHZ + bool "131.072kHz" + +config CLOCK_MSI_260KHZ + bool "262.144kHz" + +config CLOCK_MSI_520KHZ + bool "524.288kHz" + +config CLOCK_MSI_1MHZ + bool + prompt "1MHz" + +config CLOCK_MSI_2MHZ + bool + prompt "2MHz" + +config CLOCK_MSI_4MHZ + bool + prompt "4MHz" + +endchoice + +config CLOCK_MSI + int + default 65536 if CLOCK_MSI_65KHZ + default 131072 if CLOCK_MSI_130KHZ + default 262144 if CLOCK_MSI_260KHZ + default 524288 if CLOCK_MSI_520KHZ + default 100000 if CLOCK_MSI_100KHZ + default 200000 if CLOCK_MSI_200KHZ + default 400000 if CLOCK_MSI_400KHZ + default 800000 if CLOCK_MSI_800KHZ + default 1048000 if CLOCK_MSI_1MHZ + default 2097000 if CLOCK_MSI_2MHZ + default 4194000 if CLOCK_MSI_4MHZ + default 8000000 if CLOCK_MSI_8MHZ + default 16000000 if CLOCK_MSI_16MHZ + default 24000000 if CLOCK_MSI_24MHZ + default 32000000 if CLOCK_MSI_32MHZ + default 48000000 if CLOCK_MSI_48MHZ + +endif # CPU_FAM_L0 || CPU_FAM_L1 diff --git a/cpu/stm32/kconfigs/l1/Kconfig.clk b/cpu/stm32/kconfigs/l1/Kconfig.clk new file mode 100644 index 000000000000..cab42844c3c5 --- /dev/null +++ b/cpu/stm32/kconfigs/l1/Kconfig.clk @@ -0,0 +1,8 @@ +# Copyright (c) 2022 HAW Hamburg +# +# This file is subject to the terms and conditions of the GNU Lesser +# General Public License v2.1. See the file LICENSE in the top level +# directory for more details. +# + +rsource '../l0l1/Kconfig.clk' diff --git a/cpu/stm32/kconfigs/l4/Kconfig.clk b/cpu/stm32/kconfigs/l4/Kconfig.clk new file mode 100644 index 000000000000..263f0baaae46 --- /dev/null +++ b/cpu/stm32/kconfigs/l4/Kconfig.clk @@ -0,0 +1,25 @@ +# Copyright (c) 2022 HAW Hamburg +# +# This file is subject to the terms and conditions of the GNU Lesser +# General Public License v2.1. See the file LICENSE in the top level +# directory for more details. +# + +rsource '../g4l4l5/Kconfig.clk' +rsource '../l4l5wx/Kconfig.clk' + +if CPU_FAM_L4 + +config CLOCK_PLL_M + int "M: PLLIN division factor" if CUSTOM_PLL_PARAMS + default 6 if CLOCK_PLL_SRC_MSI + default 2 + range 1 8 + +config CLOCK_PLL_N + int "N: PLLIN multiply factor" if CUSTOM_PLL_PARAMS + default 30 if CPU_LINE_STM32L4A6XX || CPU_LINE_STM32L4P5XX || CPU_LINE_STM32L4Q5XX || CPU_LINE_STM32L4R5XX || CPU_LINE_STM32L4R7XX || CPU_LINE_STM32L4R9XX || CPU_LINE_STM32L4S5XX || CPU_LINE_STM32L4S7XX || CPU_LINE_STM32L4S9XX + default 20 + range 8 86 + +endif # CPU_FAM_L4 diff --git a/cpu/stm32/kconfigs/l4l5wx/Kconfig.clk b/cpu/stm32/kconfigs/l4l5wx/Kconfig.clk new file mode 100644 index 000000000000..2d76c04c576f --- /dev/null +++ b/cpu/stm32/kconfigs/l4l5wx/Kconfig.clk @@ -0,0 +1,94 @@ +# Copyright (c) 2022 HAW Hamburg +# +# This file is subject to the terms and conditions of the GNU Lesser +# General Public License v2.1. See the file LICENSE in the top level +# directory for more details. +# + +if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL + +config USE_CLOCK_MSI + bool "Use direct multi-speed frequency internal oscillator (MSI)" + +choice +bool "Desired MSI clock frequency" if USE_CLOCK_MSI || (USE_CLOCK_PLL && CLOCK_PLL_SRC_MSI) +default CLOCK_MSI_48MHZ + +config CLOCK_MSI_100KHZ + bool "100kHz" + +config CLOCK_MSI_200KHZ + bool "200kHz" + +config CLOCK_MSI_400KHZ + bool "400kHz" + +config CLOCK_MSI_800KHZ + bool "800kHz" + +config CLOCK_MSI_1MHZ + bool + prompt "1MHz" + +config CLOCK_MSI_2MHZ + bool + prompt "2MHz" + +config CLOCK_MSI_4MHZ + bool + prompt "4MHz" + +config CLOCK_MSI_8MHZ + bool "8MHz" + +config CLOCK_MSI_16MHZ + bool "16MHz" + +config CLOCK_MSI_24MHZ + bool "24MHz" + +config CLOCK_MSI_32MHZ + bool "32MHz" + +config CLOCK_MSI_48MHZ + bool "48MHz" + +endchoice + +config CLOCK_MSI + int + default 65536 if CLOCK_MSI_65KHZ + default 131072 if CLOCK_MSI_130KHZ + default 262144 if CLOCK_MSI_260KHZ + default 524288 if CLOCK_MSI_520KHZ + default 100000 if CLOCK_MSI_100KHZ + default 200000 if CLOCK_MSI_200KHZ + default 400000 if CLOCK_MSI_400KHZ + default 800000 if CLOCK_MSI_800KHZ + default 1000000 if CLOCK_MSI_1MHZ + default 2000000 if CLOCK_MSI_2MHZ + default 4000000 if CLOCK_MSI_4MHZ + default 8000000 if CLOCK_MSI_8MHZ + default 16000000 if CLOCK_MSI_16MHZ + default 24000000 if CLOCK_MSI_24MHZ + default 32000000 if CLOCK_MSI_32MHZ + default 48000000 if CLOCK_MSI_48MHZ + + +choice +bool "Source clock for PLL" if USE_CLOCK_PLL +default CLOCK_PLL_SRC_HSE if BOARD_HAS_HSE +default CLOCK_PLL_SRC_MSI + +config CLOCK_PLL_SRC_MSI + bool "Use MSI source clock" + +config CLOCK_PLL_SRC_HSE + bool "Use HSE source clock" + depends on BOARD_HAS_HSE + +config CLOCK_PLL_SRC_HSI + bool "Use HSI16 source clock" +endchoice + +endif # CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL diff --git a/cpu/stm32/kconfigs/l5/Kconfig.clk b/cpu/stm32/kconfigs/l5/Kconfig.clk new file mode 100644 index 000000000000..d7777cdf326c --- /dev/null +++ b/cpu/stm32/kconfigs/l5/Kconfig.clk @@ -0,0 +1,24 @@ +# Copyright (c) 2022 HAW Hamburg +# +# This file is subject to the terms and conditions of the GNU Lesser +# General Public License v2.1. See the file LICENSE in the top level +# directory for more details. +# + +rsource '../g4l4l5/Kconfig.clk' +rsource '../l4l5wx/Kconfig.clk' + +if CPU_FAM_L5 + +config CLOCK_PLL_M + int "M: PLLIN division factor" if CUSTOM_PLL_PARAMS + default 6 if CLOCK_PLL_SRC_MSI + default 2 + range 1 8 + +config CLOCK_PLL_N + int "N: PLLIN multiply factor" if CUSTOM_PLL_PARAMS + default 27 if CPU_FAM_L5 + range 8 86 + +endif # CPU_FAM_L5 diff --git a/cpu/stm32/kconfigs/mp1/Kconfig.clk b/cpu/stm32/kconfigs/mp1/Kconfig.clk new file mode 100644 index 000000000000..ec5c3bf9bc45 --- /dev/null +++ b/cpu/stm32/kconfigs/mp1/Kconfig.clk @@ -0,0 +1,24 @@ +# Copyright (c) 2022 HAW Hamburg +# +# This file is subject to the terms and conditions of the GNU Lesser +# General Public License v2.1. See the file LICENSE in the top level +# directory for more details. +# + +rsource '../f2f4f7mp1/Kconfig.clk' +rsource '../g0wxmp1/Kconfig.clk' + +if CPU_FAM_MP1 + +config CLOCK_PLL_M + int "M: PLLIN division factor" if CUSTOM_PLL_PARAMS + default 2 + range 1 64 + +config CLOCK_PLL_N + int "N: PLLIN multiply factor" if CUSTOM_PLL_PARAMS + default 52 if BOARD_HAS_HSE + default 78 + range 4 512 + +endif # CPU_FAM_MP1 diff --git a/cpu/stm32/kconfigs/u5/Kconfig.clk b/cpu/stm32/kconfigs/u5/Kconfig.clk new file mode 100644 index 000000000000..7062ae4ea72a --- /dev/null +++ b/cpu/stm32/kconfigs/u5/Kconfig.clk @@ -0,0 +1,6 @@ +# Copyright (c) 2022 HAW Hamburg +# +# This file is subject to the terms and conditions of the GNU Lesser +# General Public License v2.1. See the file LICENSE in the top level +# directory for more details. +# diff --git a/cpu/stm32/kconfigs/wb/Kconfig.clk b/cpu/stm32/kconfigs/wb/Kconfig.clk new file mode 100644 index 000000000000..943c70f3908d --- /dev/null +++ b/cpu/stm32/kconfigs/wb/Kconfig.clk @@ -0,0 +1,25 @@ +# Copyright (c) 2022 HAW Hamburg +# +# This file is subject to the terms and conditions of the GNU Lesser +# General Public License v2.1. See the file LICENSE in the top level +# directory for more details. +# + +rsource '../l4l5wx/Kconfig.clk' +rsource '../g0wxmp1/Kconfig.clk' + +if CPU_FAM_WB + +config CLOCK_PLL_M + int "M: PLLIN division factor" if CUSTOM_PLL_PARAMS + default 6 if CLOCK_PLL_SRC_MSI + default 4 if CLOCK_PLL_SRC_HSE + default 2 + range 1 8 + +config CLOCK_PLL_N + int "N: PLLIN multiply factor" if CUSTOM_PLL_PARAMS + default 16 + range 6 127 + +endif # CPU_FAM_WB diff --git a/cpu/stm32/kconfigs/wl/Kconfig.clk b/cpu/stm32/kconfigs/wl/Kconfig.clk new file mode 100644 index 000000000000..881c890dfb94 --- /dev/null +++ b/cpu/stm32/kconfigs/wl/Kconfig.clk @@ -0,0 +1,25 @@ +# Copyright (c) 2022 HAW Hamburg +# +# This file is subject to the terms and conditions of the GNU Lesser +# General Public License v2.1. See the file LICENSE in the top level +# directory for more details. +# + +rsource '../l4l5wx/Kconfig.clk' +rsource '../g0wxmp1/Kconfig.clk' + +if CPU_FAM_WL + +config CLOCK_PLL_M + int "M: PLLIN division factor" if CUSTOM_PLL_PARAMS + default 6 if CLOCK_PLL_SRC_MSI + default 4 if CLOCK_PLL_SRC_HSE + default 2 + range 1 8 + +config CLOCK_PLL_N + int "N: PLLIN multiply factor" if CUSTOM_PLL_PARAMS + default 12 + range 6 127 + +endif # CPU_FAM_WL