diff --git a/qiskit/transpiler/passes/layout/sabre_layout.py b/qiskit/transpiler/passes/layout/sabre_layout.py
index 8c2e273e02b7..750e17c1520e 100644
--- a/qiskit/transpiler/passes/layout/sabre_layout.py
+++ b/qiskit/transpiler/passes/layout/sabre_layout.py
@@ -76,36 +76,6 @@ def run(self, dag):
         Raises:
             TranspilerError: if dag wider than self.coupling_map
         """
-        def _layout_and_route_passmanager(initial_layout):
-            """Return a passmanager for a full layout and routing.
-
-            We use a factory to remove potential statefulness of passes.
-            """
-            layout_and_route = [SetLayout(initial_layout),
-                                FullAncillaAllocation(self.coupling_map),
-                                EnlargeWithAncilla(),
-                                ApplyLayout(),
-                                self.routing_pass]
-            pm = PassManager(layout_and_route)
-            return pm
-
-        def _compose_layouts(initial_layout, pass_final_layout, qregs):
-            """Return the real final_layout resulting from the composition
-            of an initial_layout with the final_layout reported by a pass.
-
-            The routing passes internally start with a trivial layout, as the
-            layout gets applied to the circuit prior to running them. So the
-            "final_layout" they report must be amended to account for the actual
-            initial_layout that was selected.
-            """
-            trivial_layout = Layout.generate_trivial_layout(*qregs)
-            pass_final_layout = Layout({trivial_layout[v.index]: p
-                                        for v, p in pass_final_layout.get_virtual_bits().items()})
-            qubit_map = Layout.combine_into_edge_map(initial_layout, trivial_layout)
-            final_layout = {v: pass_final_layout[qubit_map[v]]
-                            for v, _ in initial_layout.get_virtual_bits().items()}
-            return Layout(final_layout)
-
         if len(dag.qubits) > self.coupling_map.size():
             raise TranspilerError('More virtual qubits exist than physical.')
 
@@ -127,14 +97,14 @@ def _compose_layouts(initial_layout, pass_final_layout, qregs):
         circ = dag_to_circuit(dag)
         for i in range(self.max_iterations):
             for _ in ('forward', 'backward'):
-                pm = _layout_and_route_passmanager(initial_layout)
+                pm = self._layout_and_route_passmanager(initial_layout)
                 new_circ = pm.run(circ)
 
                 # Update initial layout and reverse the unmapped circuit.
                 pass_final_layout = pm.property_set['final_layout']
-                final_layout = _compose_layouts(initial_layout,
-                                                pass_final_layout,
-                                                circ.qregs)
+                final_layout = self._compose_layouts(initial_layout,
+                                                     pass_final_layout,
+                                                     circ.qregs)
                 initial_layout = final_layout
                 circ = circ.reverse_ops()
 
@@ -145,3 +115,33 @@ def _compose_layouts(initial_layout, pass_final_layout, qregs):
             logger.info(initial_layout)
 
         self.property_set['layout'] = initial_layout
+
+    def _layout_and_route_passmanager(self, initial_layout):
+        """Return a passmanager for a full layout and routing.
+
+        We use a factory to remove potential statefulness of passes.
+        """
+        layout_and_route = [SetLayout(initial_layout),
+                            FullAncillaAllocation(self.coupling_map),
+                            EnlargeWithAncilla(),
+                            ApplyLayout(),
+                            self.routing_pass]
+        pm = PassManager(layout_and_route)
+        return pm
+
+    def _compose_layouts(self, initial_layout, pass_final_layout, qregs):
+        """Return the real final_layout resulting from the composition
+        of an initial_layout with the final_layout reported by a pass.
+
+        The routing passes internally start with a trivial layout, as the
+        layout gets applied to the circuit prior to running them. So the
+        "final_layout" they report must be amended to account for the actual
+        initial_layout that was selected.
+        """
+        trivial_layout = Layout.generate_trivial_layout(*qregs)
+        pass_final_layout = Layout({trivial_layout[v.index]: p
+                                    for v, p in pass_final_layout.get_virtual_bits().items()})
+        qubit_map = Layout.combine_into_edge_map(initial_layout, trivial_layout)
+        final_layout = {v: pass_final_layout[qubit_map[v]]
+                        for v, _ in initial_layout.get_virtual_bits().items()}
+        return Layout(final_layout)
diff --git a/test/python/transpiler/test_coupling.py b/test/python/transpiler/test_coupling.py
index cebe322e8c14..178a9b1fb425 100644
--- a/test/python/transpiler/test_coupling.py
+++ b/test/python/transpiler/test_coupling.py
@@ -132,15 +132,6 @@ def test_make_symmetric(self):
 
         self.assertEqual(set(edges), set([(0, 1), (0, 2), (2, 0), (1, 0)]))
 
-    def test_neighbors(self):
-        coupling_list = [[0, 1], [0, 2], [2, 0]]
-        coupling = CouplingMap(coupling_list)
-
-        physical_qubits = coupling.physical_qubits
-        self.assertEqual(set(coupling.neighbors(physical_qubits[0])), set([1, 2]))
-        self.assertEqual(set(coupling.neighbors(physical_qubits[1])), set([]))
-        self.assertEqual(set(coupling.neighbors(physical_qubits[2])), set([0]))
-
     def test_full_factory(self):
         coupling = CouplingMap.from_full(4)
         edges = coupling.get_edges()