diff --git a/docs/tutorials/FlowTutorial.md b/docs/tutorials/FlowTutorial.md index 9b274da873..a9059e18c6 100644 --- a/docs/tutorials/FlowTutorial.md +++ b/docs/tutorials/FlowTutorial.md @@ -408,8 +408,13 @@ The log structure is as follows: View design area and its core utilization: -``` +```shell make gui_final +``` + +In the `Tcl Commands` section: + +```tcl report_design_area ``` @@ -453,6 +458,8 @@ hierarchy refer to the OpenROAD [GUI](https://openroad.readthedocs.io/en/latest/ Use the report command to view individual power components i.e. sequential, combinational, macro and power consumed by I/O pads. +In the `Tcl Commands` section: + ```tcl report_power ``` @@ -699,6 +706,11 @@ fixed DRC violation in the design: ```shell openroad -gui +``` + +In the `Tcl Commands` section: + +```tcl source drc_fix.tcl ``` @@ -718,7 +730,7 @@ to view Tcl Commands available. In OpenROAD GUI, at the bottom, `TCL commands` executable space is available to run the commands. For example -View `design area`: +View `design area` in the `Tcl Commands` section of the GUI: ```tcl report_design_area @@ -817,7 +829,7 @@ The `gcd` design synthesis results for area and speed optimizations are shown be |-----------------------|--------------------------------------|--------------------------------------| | `Number of wires` | 224 | 224 | | `Number of wire bits` | 270 | 270 | -| `Number of cells` | 234 | 234 | +| `Number of cells` | 234 | 234 | | `Chip area` | 2083.248000 | 2083.248000 | | `Final Design Area` | Design area 4295 u^2 6% utilization. | Design area 4074 u^2 6% utilization. | @@ -1085,6 +1097,11 @@ To check this in OpenROAD tool root directory: ```shell cd ../tools/OpenROAD/src/ifp/test/ openroad +``` + +In the `Tcl Commands` section: + +```tcl source tiecells.tcl ``` @@ -1095,7 +1112,7 @@ AND2_X1 u2 (.A1(r1q), .A2(1'b0), .ZN(u2z0)); AND2_X1 u3 (.A1(u1z), .A2(1'b1), .ZN(u2z1)); ``` With following `insert_tiecells` command: -``` +```tcl insert_tiecells LOGIC0_X1/Z -prefix "TIE_ZERO_" insert_tiecells LOGIC1_X1/Z ``` @@ -1152,7 +1169,7 @@ Read the resulting macro placement with a complete core view: ##### Macro Placement With Halo Spacing Explore macro placement with halo spacing, refer to the example -[here]((https://github.com/The-OpenROAD-Project/OpenROAD/tree/master/src/mpl/test/). +[here](https://github.com/The-OpenROAD-Project/OpenROAD/tree/master/src/mpl/test/). Launch GUI by running the following command(s) in the terminal in OpenROAD tool root directory: ```shell @@ -1208,7 +1225,7 @@ Change `CORE_UTILIZATION` and `PLACE_DENSITY` for the `ibex` design View `ibex` design `config.mk` [here](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/master/flow/designs/sky130hd/ibex/config.mk). -``` +```tcl export CORE_UTILIZATION = 40 export PLACE_DENSITY_LB_ADDON = 0.1 ``` @@ -1324,6 +1341,7 @@ corners. Refer to the built-in example [here](https://github.com/The-OpenROAD-Project/OpenROAD/blob/master/test/gcd_sky130hd_fast_slow.tcl). Run the following commands in the terminal: + ```shell cd ../../test/ openroad @@ -1332,12 +1350,15 @@ source gcd_sky130hd_fast_slow.tcl The resulting `worst slack`, `TNS`: -``` +```tcl report_worst_slack -min -digits 3 -worst slack 0.321 report_worst_slack -max -digits 3 -worst slack -16.005 report_tns -digits 3 +``` + +``` +worst slack 0.321 +worst slack -16.005 tns -529.496 ``` @@ -1431,7 +1452,7 @@ Reduce the clock frequency by increasing the clock period to `0.9` and re-run `repair_timing` to fix the setup violation warnings. Such timing violations are automatically fixed by the `resizer` `post CTS` and `global routing.` -```yvl +```tcl create_clock -period 0.9 clk repair_timing -setup ``` @@ -1701,7 +1722,7 @@ Refer to the built-in examples [here](https://github.com/The-OpenROAD-Project/Op Run these Tcl commands in the terminal in OpenROAD tool root directory: -``` +```shell cd ../tools/OpenROAD/src/cts/test/ openroad source post_cts_opt.tcl @@ -1765,7 +1786,7 @@ Filler cells removed with `remove_fillers` command. ### Global Routing The global router analyzes available routing resources and automatically -allocates them to avoid any  H/V  overflow violations for optimal routing.  +allocates them to avoid any H/V overflow violations for optimal routing. It generates a congestion report for GCells showing total resources, demand, utilization, location and the H/V violation status. If there are no violations reported then the design can proceed to detail routing. @@ -1937,22 +1958,32 @@ design rules while obeying DRC constraints. It is driven by a json configuration file. Command used as follows: + ```tcl density_fill -rules [-area ] ``` + If -area is not specified, the core area will be used. To run metal fill post route, run the following: + ```shell cd flow/tutorials/scripts/metal_fill openroad -gui +``` + +In the `Tcl Commands` section: + +```tcl source "helpers.tcl" read_db ./5_route.odb ``` + Layout before adding metal fill is as follows: ![Detail Routing](./images/sky130_gcd_route.webp) To add metal fill, run the command: + ```tcl density_fill -rules ../../../platforms/sky130hd/fill.json ``` @@ -1980,7 +2011,8 @@ cd ../tools/OpenROAD/src/rcx/test/ openroad ``` -To run parasitics for gcd design: +Run parasitics in the `Tcl Commands` section: + ```tcl source 45_gcd.tcl ``` @@ -2064,6 +2096,7 @@ In the GUI, you can go under `Heat Maps` and mark the You can create a text file with the congestion information of the GCells for further investigation on the GUI. To do that, add the `-congestion_report_file file_name` to the `global_route` command, as shown below: + ```tcl global_route -guide_file out.guide -congestion_report_file congest.rpt ``` diff --git a/docs/user/FlowVariables.md b/docs/user/FlowVariables.md index a042ccc3d2..5d84f396df 100644 --- a/docs/user/FlowVariables.md +++ b/docs/user/FlowVariables.md @@ -49,117 +49,146 @@ configuration file. # Automatically generated tables from flow/scripts/variables.yaml ## Variables in alphabetic order -| Variable | Description | Default | -| --- | --- | --- | -| ABC_AREA| Strategies for Yosys ABC synthesis: Area/Speed. Default ABC_SPEED.| | -| ABC_CLOCK_PERIOD_IN_PS| Clock period to be used by STA during synthesis. Default value read from `constraint.sdc`.| | -| ABC_DRIVER_CELL| Default driver cell used during ABC synthesis.| | -| ABC_LOAD_IN_FF| During synthesis set_load value used.| | -| ADDER_MAP_FILE| List of adders treated as a black box by Yosys.| | -| ADDITIONAL_FILES| Additional files to be added to `make issue` archive.| | -| ADDITIONAL_GDS| Hardened macro GDS files listed here.| | -| ADDITIONAL_LEFS| Hardened macro LEF view files listed here. The LEF information of the macros is immutable and used throughout all stages. Stored in the .odb file.| | -| ADDITIONAL_LIBS| Hardened macro library files listed here. The library information is immutable and used throughout all stages. Not stored in the .odb file.| | -| BLOCKS| Blocks used as hard macros in a hierarchical flow. Do note that you have to specify block-specific inputs file in the directory mentioned by Makefile.| | -| CAP_MARGIN| Specifies a capacitance margin when fixing max capacitance violations. This option allows you to overfix.| | -| CDL_FILES| Insert additional Circuit Description Language (`.cdl`) netlist files.| | -| CELL_PAD_IN_SITES_DETAIL_PLACEMENT| Cell padding on both sides in site widths to ease routability in detail placement.| | -| CELL_PAD_IN_SITES_GLOBAL_PLACEMENT| Cell padding on both sides in site widths to ease routability during global placement.| | -| CLKGATE_MAP_FILE| List of cells for gating clock treated as a black box by Yosys.| | -| CORE_AREA| The core area specified as a list of lower-left and upper-right corners in microns (X1 Y1 X2 Y2).| | -| CORE_ASPECT_RATIO| The core aspect ratio (height / width). This value is ignored if `CORE_UTILIZATION` is undefined.| | -| CORE_MARGIN| The margin between the core area and die area, in multiples of SITE heights. The margin is applied to each side. This variable is ignored if `CORE_UTILIZATION` is undefined.| | -| CORE_UTILIZATION| The core utilization percentage (0-100).| | -| CORNER| PVT corner library selection. Only available for ASAP7 and GF180 PDK.| | -| CTS_ARGS| Override `clock_tree_synthesis` arguments.| | -| CTS_BUF_DISTANCE| Distance (in microns) between buffers.| | -| CTS_CLUSTER_DIAMETER| Maximum diameter (in microns) of sink cluster. Default 20.| | -| CTS_CLUSTER_SIZE| Maximum number of sinks per cluster. Default 50.| | -| CTS_SNAPSHOT| Creates ODB/SDC files prior to clock net and setup/hold repair.| | -| DESIGN_NAME| The name of the top-level module of the design.| | -| DESIGN_NICKNAME| DESIGN_NICKNAME just changes the directory name that ORFS outputs to be DESIGN_NICKNAME instead of DESIGN_NAME in case DESIGN_NAME is unwieldy or conflicts with a different design.| | -| DETAILED_METRICS| If set, then calls report_metrics prior to repair operations in the CTS and global route stages| 0 | -| DETAILED_ROUTE_ARGS| Add additional arguments for debugging purposes during detail route.| | -| DETAILED_ROUTE_END_ITERATION| Maximum number of iterations, default 64.| | -| DFF_LIB_FILES| Technology mapping liberty files for flip-flops.| | -| DIE_AREA| The die area specified as a list of lower-left and upper-right corners in microns (X1 Y1 X2 Y2).| | -| DONT_USE_CELLS| Dont use cells eases pin access in detailed routing.| | -| DONT_USE_LIBS| Set liberty files as `dont_use`.| | -| DPO_MAX_DISPLACEMENT| Specifies how far an instance can be moved when optimizing.| | -| ENABLE_DPO| Enable detail placement with improve_placement feature.| | -| EQUIVALENCE_CHECK| Enable running equivalence checks to verify logical correctness of repair_timing.| 0 | -| FASTROUTE_TCL| Specifies a Tcl script with commands to run before FastRoute.| | -| FILL_CELLS| Fill cells are used to fill empty sites. If not set or empty, fill cell insertion is skipped.| | -| FILL_CONFIG| JSON rule file for metal fill during chip finishing.| | -| FLOORPLAN_DEF| Use the DEF file to initialize floorplan.| | -| GDS_FILES| Path to platform GDS files.| | -| GENERATE_ARTIFACTS_ON_FAILURE| For instance Bazel needs artifacts (.odb and .rpt files) on a failure to allow the user to save hours on re-running the failed step locally, but when working with a Makefile flow, it is more natural to fail the step and leave the user to manually inspect the logs and artifacts directly via the file system. Set to 1 to change the behavior to generate artifacts upon failure to e.g. do a global route. The exit code will still be non-zero on all other failures that aren't covered by the "useful to inspect the artifacts on failure" use-case. Example: just like detailed routing, a global route that fails with congestion, is not a build failure(as in exit code non-zero), it is a successful(as in zero exit code) global route that produce reports detailing the problem. Detailed route will not proceed, if there is global routing congestion This allows build systems, such as bazel, to create artifacts for global and detailed route, even if the operation had problems, without having know about the semantics between global and detailed route. Considering that global and detailed route can run for a long time and use a lot of memory, this allows inspecting results on a laptop for a build that ran on a server.| 0 | -| GLOBAL_PLACEMENT_ARGS| Use additional tuning parameters during global placement other than default args defined in global_place.tcl.| | -| GND_NETS_VOLTAGES| Used for IR Drop calculation.| | -| GPL_ROUTABILITY_DRIVEN| Specifies whether the placer should use routability driven placement.| | -| GPL_TIMING_DRIVEN| Specifies whether the placer should use timing driven placement.| | -| GUI_TIMING| Load timing information when opening GUI. For large designs, this can be quite time consuming. Useful to disable when investigating non-timing aspects like floorplan, placement, routing, etc.| | -| HOLD_SLACK_MARGIN| Specifies a time margin for the slack when fixing hold violations. This option allows you to overfix.| | -| IO_PLACER_H| The metal layer on which to place the I/O pins horizontally (top and bottom of the die).| | -| IO_PLACER_V| The metal layer on which to place the I/O pins vertically (sides of the die).| | -| IR_DROP_LAYER| Default metal layer to report IR drop.| | -| KLAYOUT_TECH_FILE| A mapping from LEF/DEF to GDS using the KLayout tool.| | -| LATCH_MAP_FILE| List of latches treated as a black box by Yosys.| | -| LIB_FILES| A Liberty file of the standard cell library with PVT characterization, input and output characteristics, timing and power definitions for each cell.| | -| MACRO_BLOCKAGE_HALO| Blockage width overridden from default calculation.| | -| MACRO_EXTENSION| Sets the number of GCells added to the blockages boundaries from macros.| | -| MACRO_HALO_X| Set macro halo for x-direction. Only available for ASAP7 PDK.| | -| MACRO_HALO_Y| Set macro halo for y-direction. Only available for ASAP7 PDK.| | -| MACRO_PLACEMENT| Specifies the path of a file on how to place certain macros manually using read_macro_placement.| | -| MACRO_PLACEMENT_TCL| Specifies the path of a TCL file on how to place certain macros manually.| | -| MACRO_PLACE_CHANNEL| Horizontal/vertical channel width between macros (microns). Used by automatic macro placement when RTLMP_FLOW is disabled. Imagine channel=10 and halo=5. Then macros must be 10 apart but standard cells must be 5 away from a macro.| | -| MACRO_PLACE_HALO| Horizontal/vertical halo around macros (microns). Used by automatic macro placement.| | -| MACRO_WRAPPERS| The wrapper file that replaces existing macros with their wrapped version.| | -| MAKE_TRACKS| Tcl file that defines add routing tracks to a floorplan.| | -| MAX_ROUTING_LAYER| The highest metal layer name to be used in routing.| | -| MAX_UNGROUP_SIZE| For hierarchical synthesis, we ungroup modules of size given by this variable.| | -| MIN_BUF_CELL_AND_PORTS| Used to insert a buffer cell to pass through wires. Used in synthesis.| | -| MIN_ROUTING_LAYER| The lowest metal layer name to be used in routing.| | -| PDN_TCL| File path which has a set of power grid policies used by pdn to be applied to the design, such as layers to use, stripe width and spacing to generate the actual metal straps.| | -| PLACE_DENSITY| The desired placement density of cells. It reflects how spread the cells would be on the core area. 1.0 = closely dense. 0.0 = widely spread.| | -| PLACE_DENSITY_LB_ADDON| Check the lower boundary of the PLACE_DENSITY and add PLACE_DENSITY_LB_ADDON if it exists.| | -| PLACE_SITE| Placement site for core cells defined in the technology LEF file.| | -| PLATFORM| Specifies process design kit or technology node to be used.| | -| POST_CTS_TCL| Specifies a Tcl script with commands to run after CTS is completed.| | -| PRESERVE_CELLS| Mark modules to keep from getting removed in flattening.| | -| PROCESS| Technology node or process in use.| | -| PWR_NETS_VOLTAGES| Used for IR Drop calculation.| | -| RCX_RULES| RC Extraction rules file path.| | -| RECOVER_POWER| Specifies how many percent of paths with positive slacks can be slowed for power savings [0-100].| 0 | -| REMOVE_CELLS_FOR_EQY| String patterns directly passed to write_verilog -remove_cells <> for equivalence checks.| | -| REPAIR_PDN_VIA_LAYER| Remove power grid vias which generate DRC violations after detailed routing.| | -| RESYNTH_AREA_RECOVER| Enable re-synthesis for area reclaim.| | -| RESYNTH_TIMING_RECOVER| Enable re-synthesis for timing optimization.| | -| ROUTING_LAYER_ADJUSTMENT| Default routing layer adjustment| 0.5 | -| RTLMP_FLOW| 1 to enable the Hierarchical RTLMP flow, default empty.| | -| SC_LEF| Path to technology standard cell LEF file.| | -| SDC_FILE| The path to design constraint (SDC) file.| | -| SEAL_GDS| Seal macro to place around the design.| | -| SETUP_SLACK_MARGIN| Specifies a time margin for the slack when fixing setup violations.| | -| SET_RC_TCL| Metal & Via RC definition file path.| | -| SKIP_CTS_REPAIR_TIMING| Skipping CTS repair, which can take a long time, can be useful in architectural exploration or when getting CI up and running.| | -| SKIP_GATE_CLONING| Do not use gate cloning transform to fix timing violations (default: use gate cloning).| | -| SKIP_INCREMENTAL_REPAIR| | 0 | -| SKIP_PIN_SWAP| Do not use pin swapping as a transform to fix timing violations (default: use pin swapping).| | -| SKIP_REPORT_METRICS| If set to 1, then metrics, report_metrics does nothing. Useful to speed up builds.| | -| SLEW_MARGIN| Specifies a slew margin when fixing max slew violations. This option allows you to overfix.| | -| SYNTH_ARGS| Optional synthesis variables for yosys.| | -| SYNTH_HIERARCHICAL| Enable to Synthesis hierarchically, otherwise considered flat synthesis.| | -| TAPCELL_TCL| Path to Endcap and Welltie cells file.| | -| TAP_CELL_NAME| Name of the cell to use in tap cell insertion.| | -| TECH_LEF| A technology LEF file of the PDK that includes all relevant information regarding metal layers, vias, and spacing requirements.| | -| TIEHI_CELL_AND_PORT| Tie high cells used in Yosys synthesis to replace a logical 1 in the Netlist.| | -| TIELO_CELL_AND_PORT| Tie low cells used in Yosys synthesis to replace a logical 0 in the Netlist.| | -| TNS_END_PERCENT| Default TNS_END_PERCENT value for post CTS timing repair. Try fixing all violating endpoints by default (reduce to 5% for runtime). Specifies how many percent of violating paths to fix [0-100]. Worst path will always be fixed.| 100 | -| USE_FILL| Whether to perform metal density filling. Default 0 (=off).| | -| VERILOG_FILES| The path to the design Verilog files or JSON files providing a description of modules (check `yosys -h write_json` for more details).| | -| VERILOG_INCLUDE_DIRS| Specifies the include directories for the Verilog input files.| | -| VERILOG_TOP_PARAMS| Apply toplevel params (if exist).| | + +| Variable | Description | Default | Deprecated | +| --- | --- | --- | --- | +| ABC_AREA| Strategies for Yosys ABC synthesis: Area/Speed. Default ABC_SPEED.| 0| | +| ABC_CLOCK_PERIOD_IN_PS| Clock period to be used by STA during synthesis. Default value read from `constraint.sdc`.| | | +| ABC_DRIVER_CELL| Default driver cell used during ABC synthesis.| | | +| ABC_LOAD_IN_FF| During synthesis set_load value used.| | | +| ABSTRACT_SOURCE| Which .odb file to use to create abstract| | | +| ADDER_MAP_FILE| List of adders treated as a black box by Yosys.| | | +| ADDITIONAL_FILES| Additional files to be added to `make issue` archive.| | | +| ADDITIONAL_GDS| Hardened macro GDS files listed here.| | | +| ADDITIONAL_LEFS| Hardened macro LEF view files listed here. The LEF information of the macros is immutable and used throughout all stages. Stored in the .odb file.| | | +| ADDITIONAL_LIBS| Hardened macro library files listed here. The library information is immutable and used throughout all stages. Not stored in the .odb file.| | | +| BLOCKS| Blocks used as hard macros in a hierarchical flow. Do note that you have to specify block-specific inputs file in the directory mentioned by Makefile.| | | +| CAP_MARGIN| Specifies a capacitance margin when fixing max capacitance violations. This option allows you to overfix.| | | +| CDL_FILES| Insert additional Circuit Description Language (`.cdl`) netlist files.| | | +| CELL_PAD_IN_SITES_DETAIL_PLACEMENT| Cell padding on both sides in site widths to ease routability in detail placement.| 0| | +| CELL_PAD_IN_SITES_GLOBAL_PLACEMENT| Cell padding on both sides in site widths to ease routability during global placement.| 0| | +| CLKGATE_MAP_FILE| List of cells for gating clock treated as a black box by Yosys.| | | +| CORE_AREA| The core area specified as a list of lower-left and upper-right corners in microns (X1 Y1 X2 Y2).| | | +| CORE_ASPECT_RATIO| The core aspect ratio (height / width). This value is ignored if `CORE_UTILIZATION` is undefined.| | | +| CORE_MARGIN| The margin between the core area and die area, specified in microns. Allowed values are either one value for all margins or a set of four values, one for each margin. The order of the four values are: `{bottom top left right}`. This variable is ignored if `CORE_UTILIZATION` is undefined.| | | +| CORE_UTILIZATION| The core utilization percentage (0-100).| | | +| CORNER| PVT corner library selection. Only available for ASAP7 and GF180 PDKs.| | | +| CTS_ARGS| Override `clock_tree_synthesis` arguments.| | | +| CTS_BUF_DISTANCE| Distance (in microns) between buffers.| | | +| CTS_CLUSTER_DIAMETER| Maximum diameter (in microns) of sink cluster.| 20| | +| CTS_CLUSTER_SIZE| Maximum number of sinks per cluster.| 50| | +| CTS_SNAPSHOT| Creates ODB/SDC files prior to clock net and setup/hold repair.| | | +| DESIGN_NAME| The name of the top-level module of the design.| | | +| DESIGN_NICKNAME| DESIGN_NICKNAME just changes the directory name that ORFS outputs to be DESIGN_NICKNAME instead of DESIGN_NAME in case DESIGN_NAME is unwieldy or conflicts with a different design.| | | +| DETAILED_METRICS| If set, then calls report_metrics prior to repair operations in the CTS and global route stages| 0| | +| DETAILED_ROUTE_ARGS| Add additional arguments for debugging purposes during detail route.| | | +| DETAILED_ROUTE_END_ITERATION| Maximum number of iterations.| 64| | +| DFF_LIB_FILES| Technology mapping liberty files for flip-flops.| | | +| DIE_AREA| The die area specified as a list of lower-left and upper-right corners in microns (X1 Y1 X2 Y2).| | | +| DONT_USE_CELLS| Dont use cells eases pin access in detailed routing.| | | +| DONT_USE_LIBS| Set liberty files as `dont_use`.| | | +| DPO_MAX_DISPLACEMENT| Specifies how far an instance can be moved when optimizing.| 5 1| | +| ENABLE_DPO| Enable detail placement with improve_placement feature.| 1| | +| EQUIVALENCE_CHECK| Enable running equivalence checks to verify logical correctness of repair_timing.| 0| | +| FASTROUTE_TCL| Specifies a Tcl script with commands to run before FastRoute.| | | +| FILL_CELLS| Fill cells are used to fill empty sites. If not set or empty, fill cell insertion is skipped.| | | +| FILL_CONFIG| JSON rule file for metal fill during chip finishing.| | | +| FLOORPLAN_DEF| Use the DEF file to initialize floorplan.| | | +| GDS_FILES| Path to platform GDS files.| | | +| GENERATE_ARTIFACTS_ON_FAILURE| For instance Bazel needs artifacts (.odb and .rpt files) on a failure to allow the user to save hours on re-running the failed step locally, but when working with a Makefile flow, it is more natural to fail the step and leave the user to manually inspect the logs and artifacts directly via the file system. Set to 1 to change the behavior to generate artifacts upon failure to e.g. do a global route. The exit code will still be non-zero on all other failures that aren't covered by the "useful to inspect the artifacts on failure" use-case. Example: just like detailed routing, a global route that fails with congestion, is not a build failure(as in exit code non-zero), it is a successful(as in zero exit code) global route that produce reports detailing the problem. Detailed route will not proceed, if there is global routing congestion This allows build systems, such as bazel, to create artifacts for global and detailed route, even if the operation had problems, without having know about the semantics between global and detailed route. Considering that global and detailed route can run for a long time and use a lot of memory, this allows inspecting results on a laptop for a build that ran on a server.| 0| | +| GLOBAL_PLACEMENT_ARGS| Use additional tuning parameters during global placement other than default args defined in global_place.tcl.| | | +| GLOBAL_ROUTE_ARGS| Replaces default arguments for global route.| -congestion_iterations 30 -congestion_report_iter_step 5 -verbose| | +| GND_NETS_VOLTAGES| Used for IR Drop calculation.| | | +| GPL_ROUTABILITY_DRIVEN| Specifies whether the placer should use routability driven placement.| 1| | +| GPL_TIMING_DRIVEN| Specifies whether the placer should use timing driven placement.| 1| | +| GUI_TIMING| Load timing information when opening GUI. For large designs, this can be quite time consuming. Useful to disable when investigating non-timing aspects like floorplan, placement, routing, etc.| 1| | +| HOLD_SLACK_MARGIN| Specifies a time margin for the slack when fixing hold violations. This option allows you to overfix or underfix(negative value, terminate retiming before 0 or positive slack). Use min of HOLD_SLACK_MARGIN and 0(default hold slack margin) in floorplan. This avoids overrepair in floorplan for hold by default, but allows skipping hold repair using a negative HOLD_SLACK_MARGIN. Exiting timing repair early is useful in exploration where the .sdc has a fixed clock period at designs target clock period and where HOLD/SETUP_SLACK_MARGIN is used to avoid overrepair(extremely long running times) when exploring different parameter settings.| 0| | +| IO_CONSTRAINTS| File path to the IO constraints .tcl file.| | | +| IO_PLACER_H| The metal layer on which to place the I/O pins horizontally (top and bottom of the die).| | | +| IO_PLACER_V| The metal layer on which to place the I/O pins vertically (sides of the die).| | | +| IR_DROP_LAYER| Default metal layer to report IR drop.| | | +| KLAYOUT_TECH_FILE| A mapping from LEF/DEF to GDS using the KLayout tool.| | | +| LATCH_MAP_FILE| List of latches treated as a black box by Yosys.| | | +| LIB_FILES| A Liberty file of the standard cell library with PVT characterization, input and output characteristics, timing and power definitions for each cell.| | | +| MACRO_BLOCKAGE_HALO| Blockage width overridden from default calculation.| | | +| MACRO_EXTENSION| Sets the number of GCells added to the blockages boundaries from macros.| | | +| MACRO_HALO_X| Set macro halo for x-direction. Only available for ASAP7 PDK.| | | +| MACRO_HALO_Y| Set macro halo for y-direction. Only available for ASAP7 PDK.| | | +| MACRO_PLACEMENT| Specifies the path of a file on how to place certain macros manually using read_macro_placement.| | | +| MACRO_PLACEMENT_TCL| Specifies the path of a TCL file on how to place certain macros manually.| | | +| MACRO_PLACE_CHANNEL| Horizontal/vertical channel width between macros (microns). Used by automatic macro placement. Imagine channel=10 and halo=5. Then macros must be 10 apart but standard cells must be 5 away from a macro.| | | +| MACRO_PLACE_HALO| Horizontal/vertical halo around macros (microns). Used by automatic macro placement.| | | +| MACRO_WRAPPERS| The wrapper file that replaces existing macros with their wrapped version.| | | +| MAKE_TRACKS| Tcl file that defines add routing tracks to a floorplan.| | | +| MATCH_CELL_FOOTPRINT| Enforce sizing operations to only swap cells that have the same layout boundary.| 0| | +| MAX_ROUTING_LAYER| The highest metal layer name to be used in routing.| | | +| MAX_UNGROUP_SIZE| For hierarchical synthesis, we ungroup modules of larger area than given by this variable. The default value is > 0 platform specific.| | | +| MIN_BUF_CELL_AND_PORTS| Used to insert a buffer cell to pass through wires. Used in synthesis.| | | +| MIN_ROUTING_LAYER| The lowest metal layer name to be used in routing.| | | +| PDN_TCL| File path which has a set of power grid policies used by pdn to be applied to the design, such as layers to use, stripe width and spacing to generate the actual metal straps.| | | +| PLACE_DENSITY| The desired placement density of cells. It reflects how spread the cells would be on the core area. 1.0 = closely dense. 0.0 = widely spread.| | | +| PLACE_DENSITY_LB_ADDON| Check the lower boundary of the PLACE_DENSITY and add PLACE_DENSITY_LB_ADDON if it exists.| | | +| PLACE_PINS_ARGS| Arguments to place_pins| | | +| PLACE_SITE| Placement site for core cells defined in the technology LEF file.| | | +| PLATFORM| Specifies process design kit or technology node to be used.| | | +| POST_CTS_TCL| Specifies a Tcl script with commands to run after CTS is completed.| | | +| PRESERVE_CELLS| Mark modules to keep from getting removed in flattening.| | | +| PROCESS| Technology node or process in use.| | | +| PWR_NETS_VOLTAGES| Used for IR Drop calculation.| | | +| RCX_RULES| RC Extraction rules file path.| | | +| RECOVER_POWER| Specifies how many percent of paths with positive slacks can be slowed for power savings [0-100].| 0| | +| REMOVE_ABC_BUFFERS| Remove abc buffers from the netlist. If timing repair in floorplanning is taking too long, use a SETUP_HOLD_MARGIN to terminate timing repair early instead of using REMOVE_ABC_BUFFERS or set SKIP_LAST_GAST=1.| | yes| +| REMOVE_CELLS_FOR_EQY| String patterns directly passed to write_verilog -remove_cells <> for equivalence checks.| | | +| REPAIR_PDN_VIA_LAYER| Remove power grid vias which generate DRC violations after detailed routing.| | | +| REPORT_CLOCK_SKEW| Report clock skew as part of reporting metrics, starting at CTS, before which there is no clock skew. This metric can be quite time-consuming, so it can be useful to disable.| 1| | +| RESYNTH_AREA_RECOVER| Enable re-synthesis for area reclaim.| 0| | +| RESYNTH_TIMING_RECOVER| Enable re-synthesis for timing optimization.| 0| | +| ROUTING_LAYER_ADJUSTMENT| Default routing layer adjustment| 0.5| | +| RTLMP_AREA_WT| Weight for the area of the current floorplan.| 0.1| | +| RTLMP_ARGS| Overrides all other RTL macro placer arguments.| | | +| RTLMP_BOUNDARY_WT| Weight for the boundary or how far the hard macro clusters are from boundaries.| 50.0| | +| RTLMP_DEAD_SPACE| Specifies the target dead space percentage, which influences the utilization of a cluster.| 0.05| | +| RTLMP_FENCE_LX| Defines the lower left X coordinate for the global fence bounding box in microns.| 0.0| | +| RTLMP_FENCE_LY| Defines the lower left Y coordinate for the global fence bounding box in microns.| 0.0| | +| RTLMP_FENCE_UX| Defines the upper right X coordinate for the global fence bounding box in microns.| 100000000.0| | +| RTLMP_FENCE_UY| Defines the upper right Y coordinate for the global fence bounding box in microns.| 100000000.0| | +| RTLMP_MAX_INST| Maximum number of standard cells in a cluster. If unset, rtl_macro_placer will calculate a value based on the design attributes.| | | +| RTLMP_MAX_LEVEL| Maximum depth of the physical hierarchy tree.| 2| | +| RTLMP_MAX_MACRO| Maximum number of macros in a cluster. If unset, rtl_macro_placer will calculate a value based on the design attributes.| | | +| RTLMP_MIN_AR| Specifies the minimum aspect ratio (height/width).| 0.33| | +| RTLMP_MIN_INST| Minimum number of standard cells in a cluster. If unset, rtl_macro_placer will calculate a value based on the design attributes.| | | +| RTLMP_MIN_MACRO| Minimum number of macros in a cluster. If unset, rtl_macro_placer will calculate a value based on the design attributes.| | | +| RTLMP_NOTCH_WT| Weight for the notch, or the existence of dead space that cannot be used for placement and routing.| 10.0| | +| RTLMP_OUTLINE_WT| Weight for violating the fixed outline constraint, meaning that all clusters should be placed within the shape of their parent cluster.| 100.0| | +| RTLMP_RPT_DIR| Path to the directory where reports are saved.| | | +| RTLMP_SIGNATURE_NET_THRESHOLD| Minimum number of connections between two clusters to be identified as connected.| 50| | +| RTLMP_WIRELENGTH_WT| Weight for half-perimiter wirelength.| 100.0| | +| SC_LEF| Path to technology standard cell LEF file.| | | +| SDC_FILE| The path to design constraint (SDC) file.| | | +| SDC_GUT| Load design and remove all internal logic before doing synthesis. This is useful when creating a mock .lef abstract that has a smaller area than the amount of logic would allow. bazel-orfs uses this to mock SRAMs, for instance.| | | +| SEAL_GDS| Seal macro to place around the design.| | | +| SETUP_SLACK_MARGIN| Specifies a time margin for the slack when fixing setup violations. This option allows you to overfix or underfix(negative value, terminate retiming before 0 or positive slack).| 0| | +| SET_RC_TCL| Metal & Via RC definition file path.| | | +| SKIP_CTS_REPAIR_TIMING| Skipping CTS repair, which can take a long time, can be useful in architectural exploration or when getting CI up and running.| | | +| SKIP_GATE_CLONING| Do not use gate cloning transform to fix timing violations (default: use gate cloning).| | | +| SKIP_INCREMENTAL_REPAIR| Skip incremental repair in global route.| 0| | +| SKIP_LAST_GASP| Do not use last gasp optimization to fix timing violations (default: use gate last gasp).| | | +| SKIP_PIN_SWAP| Do not use pin swapping as a transform to fix timing violations (default: use pin swapping).| | | +| SKIP_REPORT_METRICS| If set to 1, then metrics, report_metrics does nothing. Useful to speed up builds.| | | +| SLEW_MARGIN| Specifies a slew margin when fixing max slew violations. This option allows you to overfix.| | | +| SYNTH_ARGS| Optional synthesis variables for yosys.| -flatten| | +| SYNTH_GUT| Load design and remove all internal logic before doing synthesis. This is useful when creating a mock .lef abstract that has a smaller area than the amount of logic would allow. bazel-orfs uses this to mock SRAMs, for instance.| | | +| SYNTH_HIERARCHICAL| Enable to Synthesis hierarchically, otherwise considered flat synthesis.| 0| | +| TAPCELL_TCL| Path to Endcap and Welltie cells file.| | | +| TAP_CELL_NAME| Name of the cell to use in tap cell insertion.| | | +| TECH_LEF| A technology LEF file of the PDK that includes all relevant information regarding metal layers, vias, and spacing requirements.| | | +| TIEHI_CELL_AND_PORT| Tie high cells used in Yosys synthesis to replace a logical 1 in the Netlist.| | | +| TIELO_CELL_AND_PORT| Tie low cells used in Yosys synthesis to replace a logical 0 in the Netlist.| | | +| TNS_END_PERCENT| Default TNS_END_PERCENT value for post CTS timing repair. Try fixing all violating endpoints by default (reduce to 5% for runtime). Specifies how many percent of violating paths to fix [0-100]. Worst path will always be fixed.| 100| | +| USE_FILL| Whether to perform metal density filling.| 0| | +| VERILOG_FILES| The path to the design Verilog files or JSON files providing a description of modules (check `yosys -h write_json` for more details).| | | +| VERILOG_INCLUDE_DIRS| Specifies the include directories for the Verilog input files.| | | +| VERILOG_TOP_PARAMS| Apply toplevel params (if exist).| | | ## synth variables - [ABC_AREA](#ABC_AREA) @@ -167,13 +196,15 @@ configuration file. - [ABC_DRIVER_CELL](#ABC_DRIVER_CELL) - [ABC_LOAD_IN_FF](#ABC_LOAD_IN_FF) - [ADDER_MAP_FILE](#ADDER_MAP_FILE) -- [ADDITIONAL_FILES](#ADDITIONAL_FILES) - [CLKGATE_MAP_FILE](#CLKGATE_MAP_FILE) - [LATCH_MAP_FILE](#LATCH_MAP_FILE) - [MAX_UNGROUP_SIZE](#MAX_UNGROUP_SIZE) - [MIN_BUF_CELL_AND_PORTS](#MIN_BUF_CELL_AND_PORTS) - [RESYNTH_AREA_RECOVER](#RESYNTH_AREA_RECOVER) - [RESYNTH_TIMING_RECOVER](#RESYNTH_TIMING_RECOVER) +- [SDC_FILE](#SDC_FILE) +- [SDC_GUT](#SDC_GUT) +- [SYNTH_GUT](#SYNTH_GUT) - [SYNTH_HIERARCHICAL](#SYNTH_HIERARCHICAL) - [TIEHI_CELL_AND_PORT](#TIEHI_CELL_AND_PORT) - [TIELO_CELL_AND_PORT](#TIELO_CELL_AND_PORT) @@ -183,7 +214,6 @@ configuration file. ## floorplan variables -- [ADDITIONAL_FILES](#ADDITIONAL_FILES) - [CELL_PAD_IN_SITES_GLOBAL_PLACEMENT](#CELL_PAD_IN_SITES_GLOBAL_PLACEMENT) - [CORE_AREA](#CORE_AREA) - [CORE_ASPECT_RATIO](#CORE_ASPECT_RATIO) @@ -191,6 +221,8 @@ configuration file. - [CORE_UTILIZATION](#CORE_UTILIZATION) - [DIE_AREA](#DIE_AREA) - [FLOORPLAN_DEF](#FLOORPLAN_DEF) +- [HOLD_SLACK_MARGIN](#HOLD_SLACK_MARGIN) +- [IO_CONSTRAINTS](#IO_CONSTRAINTS) - [IO_PLACER_H](#IO_PLACER_H) - [IO_PLACER_V](#IO_PLACER_V) - [MACRO_BLOCKAGE_HALO](#MACRO_BLOCKAGE_HALO) @@ -202,32 +234,61 @@ configuration file. - [MACRO_PLACE_HALO](#MACRO_PLACE_HALO) - [MACRO_WRAPPERS](#MACRO_WRAPPERS) - [MAKE_TRACKS](#MAKE_TRACKS) +- [MATCH_CELL_FOOTPRINT](#MATCH_CELL_FOOTPRINT) - [PDN_TCL](#PDN_TCL) - [PLACE_DENSITY](#PLACE_DENSITY) +- [PLACE_PINS_ARGS](#PLACE_PINS_ARGS) - [PLACE_SITE](#PLACE_SITE) -- [RTLMP_FLOW](#RTLMP_FLOW) +- [REMOVE_ABC_BUFFERS](#REMOVE_ABC_BUFFERS) +- [RTLMP_AREA_WT](#RTLMP_AREA_WT) +- [RTLMP_ARGS](#RTLMP_ARGS) +- [RTLMP_BOUNDARY_WT](#RTLMP_BOUNDARY_WT) +- [RTLMP_DEAD_SPACE](#RTLMP_DEAD_SPACE) +- [RTLMP_FENCE_LX](#RTLMP_FENCE_LX) +- [RTLMP_FENCE_LY](#RTLMP_FENCE_LY) +- [RTLMP_FENCE_UX](#RTLMP_FENCE_UX) +- [RTLMP_FENCE_UY](#RTLMP_FENCE_UY) +- [RTLMP_MAX_INST](#RTLMP_MAX_INST) +- [RTLMP_MAX_LEVEL](#RTLMP_MAX_LEVEL) +- [RTLMP_MAX_MACRO](#RTLMP_MAX_MACRO) +- [RTLMP_MIN_AR](#RTLMP_MIN_AR) +- [RTLMP_MIN_INST](#RTLMP_MIN_INST) +- [RTLMP_MIN_MACRO](#RTLMP_MIN_MACRO) +- [RTLMP_NOTCH_WT](#RTLMP_NOTCH_WT) +- [RTLMP_OUTLINE_WT](#RTLMP_OUTLINE_WT) +- [RTLMP_RPT_DIR](#RTLMP_RPT_DIR) +- [RTLMP_SIGNATURE_NET_THRESHOLD](#RTLMP_SIGNATURE_NET_THRESHOLD) +- [RTLMP_WIRELENGTH_WT](#RTLMP_WIRELENGTH_WT) +- [SETUP_SLACK_MARGIN](#SETUP_SLACK_MARGIN) +- [SKIP_GATE_CLONING](#SKIP_GATE_CLONING) +- [SKIP_LAST_GASP](#SKIP_LAST_GASP) +- [SKIP_PIN_SWAP](#SKIP_PIN_SWAP) +- [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS) - [TAPCELL_TCL](#TAPCELL_TCL) - [TNS_END_PERCENT](#TNS_END_PERCENT) ## place variables -- [ADDITIONAL_FILES](#ADDITIONAL_FILES) - [CELL_PAD_IN_SITES_DETAIL_PLACEMENT](#CELL_PAD_IN_SITES_DETAIL_PLACEMENT) - [CELL_PAD_IN_SITES_GLOBAL_PLACEMENT](#CELL_PAD_IN_SITES_GLOBAL_PLACEMENT) +- [FLOORPLAN_DEF](#FLOORPLAN_DEF) - [GPL_ROUTABILITY_DRIVEN](#GPL_ROUTABILITY_DRIVEN) - [GPL_TIMING_DRIVEN](#GPL_TIMING_DRIVEN) +- [IO_CONSTRAINTS](#IO_CONSTRAINTS) - [IO_PLACER_H](#IO_PLACER_H) - [IO_PLACER_V](#IO_PLACER_V) +- [MATCH_CELL_FOOTPRINT](#MATCH_CELL_FOOTPRINT) - [MAX_ROUTING_LAYER](#MAX_ROUTING_LAYER) - [MIN_ROUTING_LAYER](#MIN_ROUTING_LAYER) - [PLACE_DENSITY](#PLACE_DENSITY) +- [PLACE_PINS_ARGS](#PLACE_PINS_ARGS) - [ROUTING_LAYER_ADJUSTMENT](#ROUTING_LAYER_ADJUSTMENT) +- [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS) - [TIEHI_CELL_AND_PORT](#TIEHI_CELL_AND_PORT) - [TIELO_CELL_AND_PORT](#TIELO_CELL_AND_PORT) ## cts variables -- [ADDITIONAL_FILES](#ADDITIONAL_FILES) - [CELL_PAD_IN_SITES_DETAIL_PLACEMENT](#CELL_PAD_IN_SITES_DETAIL_PLACEMENT) - [CTS_ARGS](#CTS_ARGS) - [CTS_BUF_DISTANCE](#CTS_BUF_DISTANCE) @@ -236,42 +297,71 @@ configuration file. - [CTS_SNAPSHOT](#CTS_SNAPSHOT) - [DETAILED_METRICS](#DETAILED_METRICS) - [EQUIVALENCE_CHECK](#EQUIVALENCE_CHECK) +- [HOLD_SLACK_MARGIN](#HOLD_SLACK_MARGIN) +- [MATCH_CELL_FOOTPRINT](#MATCH_CELL_FOOTPRINT) - [POST_CTS_TCL](#POST_CTS_TCL) - [REMOVE_CELLS_FOR_EQY](#REMOVE_CELLS_FOR_EQY) +- [REPORT_CLOCK_SKEW](#REPORT_CLOCK_SKEW) +- [SETUP_SLACK_MARGIN](#SETUP_SLACK_MARGIN) - [SKIP_CTS_REPAIR_TIMING](#SKIP_CTS_REPAIR_TIMING) +- [SKIP_GATE_CLONING](#SKIP_GATE_CLONING) +- [SKIP_LAST_GASP](#SKIP_LAST_GASP) +- [SKIP_PIN_SWAP](#SKIP_PIN_SWAP) +- [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS) - [TNS_END_PERCENT](#TNS_END_PERCENT) ## grt variables -- [ADDITIONAL_FILES](#ADDITIONAL_FILES) - [CELL_PAD_IN_SITES_DETAIL_PLACEMENT](#CELL_PAD_IN_SITES_DETAIL_PLACEMENT) - [DETAILED_METRICS](#DETAILED_METRICS) +- [GLOBAL_ROUTE_ARGS](#GLOBAL_ROUTE_ARGS) +- [HOLD_SLACK_MARGIN](#HOLD_SLACK_MARGIN) - [MAX_ROUTING_LAYER](#MAX_ROUTING_LAYER) - [MIN_ROUTING_LAYER](#MIN_ROUTING_LAYER) +- [REPORT_CLOCK_SKEW](#REPORT_CLOCK_SKEW) - [ROUTING_LAYER_ADJUSTMENT](#ROUTING_LAYER_ADJUSTMENT) +- [SETUP_SLACK_MARGIN](#SETUP_SLACK_MARGIN) +- [SKIP_GATE_CLONING](#SKIP_GATE_CLONING) +- [SKIP_INCREMENTAL_REPAIR](#SKIP_INCREMENTAL_REPAIR) +- [SKIP_LAST_GASP](#SKIP_LAST_GASP) +- [SKIP_PIN_SWAP](#SKIP_PIN_SWAP) +- [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS) - [TNS_END_PERCENT](#TNS_END_PERCENT) ## route variables -- [ADDITIONAL_FILES](#ADDITIONAL_FILES) - [DETAILED_ROUTE_ARGS](#DETAILED_ROUTE_ARGS) - [DETAILED_ROUTE_END_ITERATION](#DETAILED_ROUTE_END_ITERATION) +- [FILL_CELLS](#FILL_CELLS) +- [MATCH_CELL_FOOTPRINT](#MATCH_CELL_FOOTPRINT) - [MAX_ROUTING_LAYER](#MAX_ROUTING_LAYER) - [MIN_ROUTING_LAYER](#MIN_ROUTING_LAYER) +- [REPORT_CLOCK_SKEW](#REPORT_CLOCK_SKEW) - [ROUTING_LAYER_ADJUSTMENT](#ROUTING_LAYER_ADJUSTMENT) +- [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS) ## final variables -- [ADDITIONAL_FILES](#ADDITIONAL_FILES) +- [ADDITIONAL_GDS](#ADDITIONAL_GDS) +- [GND_NETS_VOLTAGES](#GND_NETS_VOLTAGES) +- [MAX_ROUTING_LAYER](#MAX_ROUTING_LAYER) +- [MIN_ROUTING_LAYER](#MIN_ROUTING_LAYER) +- [PWR_NETS_VOLTAGES](#PWR_NETS_VOLTAGES) +- [REPORT_CLOCK_SKEW](#REPORT_CLOCK_SKEW) - [ROUTING_LAYER_ADJUSTMENT](#ROUTING_LAYER_ADJUSTMENT) +- [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS) + +## generate_abstract variables + +- [ABSTRACT_SOURCE](#ABSTRACT_SOURCE) ## All stages variables -- [ADDITIONAL_FILES](#ADDITIONAL_FILES) + ## Uncategorized variables -- [ADDITIONAL_GDS](#ADDITIONAL_GDS) +- [ADDITIONAL_FILES](#ADDITIONAL_FILES) - [ADDITIONAL_LEFS](#ADDITIONAL_LEFS) - [ADDITIONAL_LIBS](#ADDITIONAL_LIBS) - [BLOCKS](#BLOCKS) @@ -286,14 +376,11 @@ configuration file. - [DPO_MAX_DISPLACEMENT](#DPO_MAX_DISPLACEMENT) - [ENABLE_DPO](#ENABLE_DPO) - [FASTROUTE_TCL](#FASTROUTE_TCL) -- [FILL_CELLS](#FILL_CELLS) - [FILL_CONFIG](#FILL_CONFIG) - [GDS_FILES](#GDS_FILES) - [GENERATE_ARTIFACTS_ON_FAILURE](#GENERATE_ARTIFACTS_ON_FAILURE) - [GLOBAL_PLACEMENT_ARGS](#GLOBAL_PLACEMENT_ARGS) -- [GND_NETS_VOLTAGES](#GND_NETS_VOLTAGES) - [GUI_TIMING](#GUI_TIMING) -- [HOLD_SLACK_MARGIN](#HOLD_SLACK_MARGIN) - [IR_DROP_LAYER](#IR_DROP_LAYER) - [KLAYOUT_TECH_FILE](#KLAYOUT_TECH_FILE) - [LIB_FILES](#LIB_FILES) @@ -302,19 +389,12 @@ configuration file. - [PLATFORM](#PLATFORM) - [PRESERVE_CELLS](#PRESERVE_CELLS) - [PROCESS](#PROCESS) -- [PWR_NETS_VOLTAGES](#PWR_NETS_VOLTAGES) - [RCX_RULES](#RCX_RULES) - [RECOVER_POWER](#RECOVER_POWER) - [REPAIR_PDN_VIA_LAYER](#REPAIR_PDN_VIA_LAYER) - [SC_LEF](#SC_LEF) -- [SDC_FILE](#SDC_FILE) - [SEAL_GDS](#SEAL_GDS) -- [SETUP_SLACK_MARGIN](#SETUP_SLACK_MARGIN) - [SET_RC_TCL](#SET_RC_TCL) -- [SKIP_GATE_CLONING](#SKIP_GATE_CLONING) -- [SKIP_INCREMENTAL_REPAIR](#SKIP_INCREMENTAL_REPAIR) -- [SKIP_PIN_SWAP](#SKIP_PIN_SWAP) -- [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS) - [SLEW_MARGIN](#SLEW_MARGIN) - [SYNTH_ARGS](#SYNTH_ARGS) - [TAP_CELL_NAME](#TAP_CELL_NAME) diff --git a/docs/user/InstructionsForAutoTuner.md b/docs/user/InstructionsForAutoTuner.md index 5eba85b8e3..7b43950e05 100644 --- a/docs/user/InstructionsForAutoTuner.md +++ b/docs/user/InstructionsForAutoTuner.md @@ -23,17 +23,17 @@ User-defined coefficient values (`coeff_perform`, `coeff_power`, `coeff_area`) o ## Setting up AutoTuner -We have provided two convenience scripts, `./install.sh` and `./setup.sh` +We have provided two convenience scripts, `./installer.sh` and `./setup.sh` that works in Python3.8 for installation and configuration of AutoTuner, as shown below: ```{note} -Make sure you run the following commands in `./tools/AutoTuner/src/autotuner`. +Make sure you run the following commands in the ORFS root directory. ``` ```shell # Install prerequisites -./tools/AutoTuner/install.sh +./tools/AutoTuner/installer.sh # Start virtual environment ./tools/AutoTuner/setup.sh @@ -104,14 +104,15 @@ For Global Routing parameters that are set on `fastroute.tcl` you can use: ### General Information -The `distributed.py` script uses Ray's job scheduling and management to +The `distributed.py` script located in `./tools/AutoTuner/src/autotuner` uses [Ray's](https://docs.ray.io/en/latest/index.html) job scheduling and management to fully utilize available hardware resources from a single server -configuration, on-premies or over the cloud with multiple CPUs. -The two modes of operation: `sweep`, where every possible parameter -combination in the search space is tested; and `tune`, where we use -Ray's Tune feature to intelligently search the space and optimize -hyperparameters using one of the algorithms listed above. The `sweep` -mode is useful when we want to isolate or test a single or very few +configuration, on-premise or over the cloud with multiple CPUs. + +The two modes of operation: +- `sweep`, where every possible parameter combination in the search space is tested +- `tune`, where we use Ray's Tune feature to intelligently search the space and optimize hyperparameters using one of the algorithms listed above. + +The `sweep` mode is useful when we want to isolate or test a single or very few parameters. On the other hand, `tune` is more suitable for finding the best combination of a complex and large number of flow parameters. Both modes rely on user-specified search space that is @@ -120,7 +121,7 @@ though some features may not be available for sweeping. ```{note} The order of the parameters matter. Arguments `--design`, `--platform` and -`--config` are always required and should precede . +`--config` are always required and should precede *mode*. ``` #### Tune only @@ -153,35 +154,44 @@ GCP Setup Tutorial coming soon. ### List of input arguments -| Argument | Description | -|-------------------------------|-------------------------------------------------------------------------------------------------------| -| `--design` | Name of the design for Autotuning. | -| `--platform` | Name of the platform for Autotuning. | -| `--config` | Configuration file that sets which knobs to use for Autotuning. | -| `--experiment` | Experiment name. This parameter is used to prefix the FLOW_VARIANT and to set the Ray log destination.| -| `--resume` | Resume previous run. | -| `--git_clean` | Clean binaries and build files. **WARNING**: may lose previous data. | -| `--git_clone` | Force new git clone. **WARNING**: may lose previous data. | -| `--git_clone_args` | Additional git clone arguments. | -| `--git_latest` | Use latest version of OpenROAD app. | -| `--git_or_branch` | OpenROAD app branch to use. | -| `--git_orfs_branch` | OpenROAD-flow-scripts branch to use. | -| `--git_url` | OpenROAD-flow-scripts repo URL to use. | -| `--build_args` | Additional arguments given to ./build_openroad.sh | -| `--algorithm` | Search algorithm to use for Autotuning. | -| `--eval` | Evalaute function to use with search algorithm. \ | -| `--samples` | Number of samples for tuning. | -| `--iterations` | Number of iterations for tuning. | -| `--resources_per_trial` | Number of CPUs to request for each tuning job. | -| `--reference` | Reference file for use with PPAImprov. | -| `--perturbation` | Perturbation interval for PopulationBasedTraining | -| `--seed` | Random seed. | -| `--jobs` | Max number of concurrent jobs. | -| `--openroad_threads` | Max number of threads usable. | -| `--server` | The address of Ray server to connect. | -| `--port` | The port of Ray server to connect. | -| `-v` or `--verbose` | Verbosity Level. [0: Only ray status, 1: print stderr, 2: print stdout on top of what is in level 0 and 1. ] | -| | | +| Argument | Description | Default | +|-------------------------------|-------------------------------------------------------------------------------------------------------|---------| +| `--design` | Name of the design for Autotuning. || +| `--platform` | Name of the platform for Autotuning. || +| `--config` | Configuration file that sets which knobs to use for Autotuning. || +| `--experiment` | Experiment name. This parameter is used to prefix the FLOW_VARIANT and to set the Ray log destination.| test | +| `--git_clean` | Clean binaries and build files. **WARNING**: may lose previous data. || +| `--git_clone` | Force new git clone. **WARNING**: may lose previous data. || +| `--git_clone_args` | Additional git clone arguments. || +| `--git_latest` | Use latest version of OpenROAD app. || +| `--git_or_branch` | OpenROAD app branch to use. || +| `--git_orfs_branch` | OpenROAD-flow-scripts branch to use. || +| `--git_url` | OpenROAD-flow-scripts repo URL to use. | [ORFS GitHub repo](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts) | +| `--build_args` | Additional arguments given to ./build_openroad.sh || +| `--samples` | Number of samples for tuning. | 10 | +| `--jobs` | Max number of concurrent jobs. | # of CPUs / 2 | +| `--openroad_threads` | Max number of threads usable. | 16 | +| `--server` | The address of Ray server to connect. || +| `--port` | The port of Ray server to connect. | 10001 | +| `--timeout` | Time limit (in hours) for each trial run. | No limit | +| `-v` or `--verbose` | Verbosity Level. [0: Only ray status, 1: print stderr, 2: print stdout on top of what is in level 0 and 1. ] | 0 | +| | || + +#### Input arguments specific to tune mode +The following input arguments are applicable for tune mode only. + +| Argument | Description | Default | +|-------------------------------|-------------------------------------------------------------------------------------------------------|---------| +| `--algorithm` | Search algorithm to use for Autotuning. | hyperopt | +| `--eval` | Evaluate function to use with search algorithm. || +| `--iterations` | Number of iterations for tuning. | 1 | +| `--resources_per_trial` | Number of CPUs to request for each tuning job. | 1 | +| `--reference` | Reference file for use with PPAImprov. || +| `--perturbation` | Perturbation interval for PopulationBasedTraining | 25 | +| `--seed` | Random seed. | 42 | +| `--resume` | Resume previous run. || +| | || + ### GUI Basically, progress is displayed at the terminal where you run, and when all runs are finished, the results are displayed. diff --git a/flow/BUILD.bazel b/flow/BUILD.bazel index 95e97751e3..ed9b9dbc73 100644 --- a/flow/BUILD.bazel +++ b/flow/BUILD.bazel @@ -70,7 +70,6 @@ orfs_flow( "SDC_FILE": "$(location :constraints-swerv)", }, "floorplan": SWERV_ALL | { - "RTLMP_FLOW": "1", "RTLMP_MAX_INST": "30000", "RTLMP_MIN_INST": "5000", "RTLMP_MAX_MACRO": "30", @@ -144,7 +143,6 @@ MOCK_ARRAY_FLOORPLAN_PLACE = { "CORE_AREA": "2.16 2.16 356.40000000000003 386.64000000000004", "MACRO_PLACE_HALO": "0 2.16", "RTLMP_BOUNDARY_WT": "0", - "RTLMP_FLOW": "1", "PDN_TCL": "$(PLATFORM_DIR)/openRoad/pdn/BLOCKS_grid_strategy.tcl", "MACRO_HALO_X": "0.5", "MACRO_HALO_Y": "0.5", diff --git a/flow/Makefile b/flow/Makefile index 23befe9d75..f184dbf28d 100644 --- a/flow/Makefile +++ b/flow/Makefile @@ -160,8 +160,6 @@ export UTILS_DIR ?= $(FLOW_HOME)/util export SCRIPTS_DIR ?= $(FLOW_HOME)/scripts export TEST_DIR ?= $(FLOW_HOME)/test -$(foreach line,$(shell $(SCRIPTS_DIR)/defaults.py),$(eval export $(line))) - PUBLIC=nangate45 sky130hd sky130hs asap7 ihp-sg13g2 gf180 ifneq ($(wildcard $(PLATFORM_HOME)/$(PLATFORM)),) @@ -176,38 +174,22 @@ endif include $(PLATFORM_DIR)/config.mk +# __SPACE__ is a workaround for whitespace hell in "foreach"; there +# is no way to escape space in defaults.py and get "foreach" to work. +$(foreach line,$(shell $(SCRIPTS_DIR)/defaults.py),$(eval export $(subst __SPACE__, ,$(line)))) + # Enables hierarchical yosys -export SYNTH_HIERARCHICAL ?= 0 -export SYNTH_STOP_MODULE_SCRIPT = $(RESULTS_DIR)/keep_hierarchy.tcl -export HIER_REPORT_SCRIPT = $(SCRIPTS_DIR)/synth_hier_report.tcl +export SYNTH_STATS = $(RESULTS_DIR)/synth_stats.txt +export SYNTH_STATS_SCRIPT = $(SCRIPTS_DIR)/synth_stats.tcl +# If the design, nor $(PLATFORM_DIR)/config.mk provided a default, provide one here export MAX_UNGROUP_SIZE ?= 0 -# Enables Re-synthesis for area reclaim -export RESYNTH_AREA_RECOVER ?= 0 -export RESYNTH_TIMING_RECOVER ?= 0 -export ABC_AREA ?= 0 - -# User adjustable synthesis arguments -export SYNTH_ARGS ?= -flatten # Not normally adjusted by user export SYNTH_OPERATIONS_ARGS ?= -extra-map $(FLOW_HOME)/platforms/common/lcu_kogge_stone.v export SYNTH_FULL_ARGS ?= $(SYNTH_ARGS) $(SYNTH_OPERATIONS_ARGS) -# Global setting for Floorplan -export PLACE_PINS_ARGS - export FLOW_VARIANT ?= base -export GPL_TIMING_DRIVEN ?= 1 -export GPL_ROUTABILITY_DRIVEN ?= 1 - -# Cell padding in SITE widths to ease rout-ability. Applied to both sides -export CELL_PAD_IN_SITES_GLOBAL_PLACEMENT ?= 0 -export CELL_PAD_IN_SITES_DETAIL_PLACEMENT ?= 0 - -export ENABLE_DPO ?= 1 -export DPO_MAX_DISPLACEMENT ?= 5 1 - # Setup working directories export DESIGN_NICKNAME ?= $(DESIGN_NAME) @@ -233,7 +215,6 @@ ifneq ($(BLOCKS),) endif endif -export RTLMP_FLOW ?= 1 export RTLMP_RPT_DIR ?= $(OBJECTS_DIR)/rtlmp export RTLMP_RPT_FILE ?= partition.txt export RTLMP_BLOCKAGE_FILE ?= $(OBJECTS_DIR)/rtlmp/partition.txt.blockage @@ -456,10 +437,13 @@ synth-report: synth .PHONY: do-synth-report do-synth-report: - ($(TIME_CMD) $(OPENROAD_CMD) $(SCRIPTS_DIR)/synth_metrics.tcl) 2>&1 | tee $(LOG_DIR)/1_1_yosys_metrics.log + ($(TIME_CMD) $(OPENROAD_CMD) $(SCRIPTS_DIR)/synth_metrics.tcl) 2>&1 | tee $(abspath $(LOG_DIR)/1_1_yosys_metrics.log) .PHONY: memory memory: + if [ -f $(RESULTS_DIR)/mem_hierarchical.json ]; then \ + python3 $(SCRIPTS_DIR)/mem_dump.py $(RESULTS_DIR)/mem_hierarchical.json; \ + fi python3 $(SCRIPTS_DIR)/mem_dump.py $(RESULTS_DIR)/mem.json # ============================================================================== @@ -471,11 +455,11 @@ memory: export SYNTH_SCRIPT ?= $(SCRIPTS_DIR)/synth.tcl export SYNTH_MEMORY_MAX_BITS ?= 4096 -.PHONY: do-yosys-keep-hierarchy -do-yosys-keep-hierarchy: +.PHONY: do-yosys-stats +do-yosys-stats: mkdir -p $(RESULTS_DIR) $(LOG_DIR) $(REPORTS_DIR) (export VERILOG_FILES=$(RESULTS_DIR)/1_synth.rtlil; \ - $(TIME_CMD) $(YOSYS_EXE) $(YOSYS_FLAGS) -c $(HIER_REPORT_SCRIPT)) 2>&1 | tee $(abspath $(LOG_DIR)/1_1_yosys_hier_report.log) + $(TIME_CMD) $(YOSYS_EXE) $(YOSYS_FLAGS) -c $(SYNTH_STATS_SCRIPT)) 2>&1 | tee $(abspath $(LOG_DIR)/1_1_yosys_stats.log) export SDC_FILE_CLOCK_PERIOD = $(RESULTS_DIR)/clock_period.txt @@ -503,7 +487,7 @@ $(RESULTS_DIR)/1_synth.rtlil: $(YOSYS_DEPENDENCIES) $(UNSET_AND_MAKE) do-yosys-canonicalize $(RESULTS_DIR)/1_1_yosys.v: $(RESULTS_DIR)/1_synth.rtlil - $(UNSET_AND_MAKE) do-yosys-keep-hierarchy do-yosys + $(UNSET_AND_MAKE) do-yosys-stats do-yosys .PHONY: do-synth do-synth: @@ -515,10 +499,10 @@ $(RESULTS_DIR)/1_synth.v: $(RESULTS_DIR)/1_1_yosys.v .PHONY: clean_synth clean_synth: - rm -f $(RESULTS_DIR)/1_* $(RESULTS_DIR)/mem.json + rm -f $(RESULTS_DIR)/1_* $(RESULTS_DIR)/mem*.json rm -f $(REPORTS_DIR)/synth_* rm -f $(LOG_DIR)/1_* - rm -f $(SYNTH_STOP_MODULE_SCRIPT) + rm -f $(SYNTH_STATS) rm -f $(SDC_FILE_CLOCK_PERIOD) rm -rf _tmp_yosys-abc-* @@ -569,7 +553,7 @@ define OPEN_GUI open_$(1): $(2)=$(RESULTS_DIR)/$(1) $(OPENROAD_NO_EXIT_CMD) $(SCRIPTS_DIR)/open.tcl gui_$(1): - $$(UNSET_AND_MAKE) GUI_SHOW=1 open_$(1) + $(2)=$(RESULTS_DIR)/$(1) GUI_SHOW=1 $(OPENROAD_GUI_CMD) -minimize $(SCRIPTS_DIR)/open.tcl endef # Separate dependency checking and doing a step. This can @@ -642,31 +626,31 @@ endef #------------------------------------------------------------------------------- $(eval $(call do-step,2_1_floorplan,$(RESULTS_DIR)/1_synth.v $(RESULTS_DIR)/1_synth.sdc $(TECH_LEF) $(SC_LEF) $(ADDITIONAL_LEFS) $(FOOTPRINT) $(SIG_MAP_FILE) $(FOOTPRINT_TCL),floorplan)) +# STEP 2: Random IO placement +#------------------------------------------------------------------------------- $(eval $(call do-step,2_2_floorplan_io,$(RESULTS_DIR)/2_1_floorplan.odb $(IO_CONSTRAINTS),io_placement_random)) -# STEP 3: Timing Driven Mixed Sized Placement -#------------------------------------------------------------------------------- -$(eval $(call do-step,2_3_floorplan_tdms,$(RESULTS_DIR)/2_2_floorplan_io.odb $(RESULTS_DIR)/1_synth.v $(RESULTS_DIR)/1_synth.sdc $(LIB_FILES),tdms_place)) +$(eval $(call do-copy,2_floorplan,2_1_floorplan.sdc,,.sdc)) -# STEP 4: Macro Placement +# STEP 3: Macro Placement #------------------------------------------------------------------------------- -$(eval $(call do-step,2_4_floorplan_macro,$(RESULTS_DIR)/2_3_floorplan_tdms.odb $(RESULTS_DIR)/1_synth.v $(RESULTS_DIR)/1_synth.sdc $(MACRO_PLACEMENT) $(MACRO_PLACEMENT_TCL),macro_place)) +$(eval $(call do-step,2_3_floorplan_macro,$(RESULTS_DIR)/2_2_floorplan_io.odb $(RESULTS_DIR)/1_synth.v $(RESULTS_DIR)/1_synth.sdc $(MACRO_PLACEMENT) $(MACRO_PLACEMENT_TCL),macro_place)) -# STEP 5: Tapcell and Welltie insertion +# STEP 4: Tapcell and Welltie insertion #------------------------------------------------------------------------------- -$(eval $(call do-step,2_5_floorplan_tapcell,$(RESULTS_DIR)/2_4_floorplan_macro.odb $(TAPCELL_TCL),tapcell)) +$(eval $(call do-step,2_4_floorplan_tapcell,$(RESULTS_DIR)/2_3_floorplan_macro.odb $(TAPCELL_TCL),tapcell)) -# STEP 6: PDN generation +# STEP 5: PDN generation #------------------------------------------------------------------------------- -$(eval $(call do-step,2_6_floorplan_pdn,$(RESULTS_DIR)/2_5_floorplan_tapcell.odb $(PDN_TCL),pdn)) +$(eval $(call do-step,2_5_floorplan_pdn,$(RESULTS_DIR)/2_4_floorplan_tapcell.odb $(PDN_TCL),pdn)) -$(eval $(call do-copy,2_floorplan,2_6_floorplan_pdn.odb,)) +$(eval $(call do-copy,2_floorplan,2_5_floorplan_pdn.odb,)) $(RESULTS_DIR)/2_floorplan.sdc: $(RESULTS_DIR)/2_1_floorplan.odb .PHONY: do-floorplan do-floorplan: - $(UNSET_AND_MAKE) do-2_1_floorplan do-2_2_floorplan_io do-2_3_floorplan_tdms do-2_4_floorplan_macro do-2_5_floorplan_tapcell do-2_6_floorplan_pdn do-2_floorplan + $(UNSET_AND_MAKE) do-2_1_floorplan do-2_2_floorplan_io do-2_3_floorplan_macro do-2_4_floorplan_tapcell do-2_5_floorplan_pdn do-2_floorplan do-2_floorplan.sdc .PHONY: clean_floorplan clean_floorplan: @@ -876,7 +860,7 @@ generate_abstract: $(RESULTS_DIR)/6_final.gds $(RESULTS_DIR)/6_final.def $(RESU .PHONY: do-generate_abstract do-generate_abstract: mkdir -p $(LOG_DIR) $(REPORTS_DIR) - ($(TIME_CMD) $(OPENROAD_CMD) $(SCRIPTS_DIR)/generate_abstract.tcl -metrics $(LOG_DIR)/generate_abstract.json) 2>&1 | tee $(LOG_DIR)/generate_abstract.log + ($(TIME_CMD) $(OPENROAD_CMD) $(SCRIPTS_DIR)/generate_abstract.tcl -metrics $(LOG_DIR)/generate_abstract.json) 2>&1 | tee $(abspath $(LOG_DIR)/generate_abstract.log) .PHONY: clean_abstract clean_abstract: @@ -894,7 +878,7 @@ $(WRAPPED_GDSOAS): $(OBJECTS_DIR)/klayout_wrap.lyt $(WRAPPED_LEFS) -rd out_file=$@ \ -rd tech_file=$(OBJECTS_DIR)/klayout_wrap.lyt \ -rd layer_map=$(GDS_LAYER_MAP) \ - -r $(UTILS_DIR)/def2stream.py) 2>&1 | tee $(LOG_DIR)/6_merge_$(basename $(notdir $@)).log + -r $(UTILS_DIR)/def2stream.py) 2>&1 | tee $(abspath $(LOG_DIR)/6_merge_$(basename $(notdir $@)).log) # Merge GDS using Klayout #------------------------------------------------------------------------------- @@ -912,7 +896,7 @@ do-gds-merged: -rd out_file=$(GDS_MERGED_FILE) \ -rd tech_file=$(OBJECTS_DIR)/klayout.lyt \ -rd layer_map=$(GDS_LAYER_MAP) \ - -r $(UTILS_DIR)/def2stream.py) 2>&1 | tee $(LOG_DIR)/6_1_merge.log + -r $(UTILS_DIR)/def2stream.py) 2>&1 | tee $(abspath $(LOG_DIR)/6_1_merge.log) $(RESULTS_DIR)/6_final.v: $(LOG_DIR)/6_report.log @@ -932,7 +916,7 @@ ifneq ($(KLAYOUT_DRC_FILE),) $(call KLAYOUT_FOUND) ($(TIME_CMD) $(KLAYOUT_CMD) -zz -rd in_gds="$<" \ -rd report_file=$(abspath $@) \ - -r $(KLAYOUT_DRC_FILE)) 2>&1 | tee $(LOG_DIR)/6_drc.log + -r $(KLAYOUT_DRC_FILE)) 2>&1 | tee $(abspath $(LOG_DIR)/6_drc.log) # Hacky way of getting DRV count (don't error on no matches) grep -c "" $@ > $(REPORTS_DIR)/6_drc_count.rpt || [[ $$? == 1 ]] else @@ -940,7 +924,7 @@ else endif $(RESULTS_DIR)/6_final.cdl: $(RESULTS_DIR)/6_final.v - ($(TIME_CMD) $(OPENROAD_CMD) $(SCRIPTS_DIR)/cdl.tcl) 2>&1 | tee $(LOG_DIR)/6_cdl.log + ($(TIME_CMD) $(OPENROAD_CMD) $(SCRIPTS_DIR)/cdl.tcl) 2>&1 | tee $(abspath $(LOG_DIR)/6_cdl.log) $(OBJECTS_DIR)/6_final_concat.cdl: $(RESULTS_DIR)/6_final.cdl $(CDL_FILE) cat $^ > $@ @@ -954,7 +938,7 @@ ifneq ($(KLAYOUT_LVS_FILE),) ($(TIME_CMD) $(KLAYOUT_CMD) -b -rd in_gds="$<" \ -rd cdl_file=$(abspath $(OBJECTS_DIR)/6_final_concat.cdl) \ -rd report_file=$(abspath $@) \ - -r $(KLAYOUT_LVS_FILE)) 2>&1 | tee $(LOG_DIR)/6_lvs.log + -r $(KLAYOUT_LVS_FILE)) 2>&1 | tee $(abspath $(LOG_DIR)/6_lvs.log) else echo "LVS not supported on this platform" > $@ endif diff --git a/flow/designs/asap7/aes-block/config.mk b/flow/designs/asap7/aes-block/config.mk index d13c524ee9..79520f6b4c 100644 --- a/flow/designs/asap7/aes-block/config.mk +++ b/flow/designs/asap7/aes-block/config.mk @@ -3,8 +3,8 @@ export PLATFORM = asap7 export DESIGN_NAME = aes_cipher_top export DESIGN_NICKNAME = aes-block -export VERILOG_FILES = $(sort $(wildcard ./designs/src/aes/*.v)) -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/aes/*.v)) +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export ABC_AREA = 1 diff --git a/flow/designs/asap7/aes-mbff/config.mk b/flow/designs/asap7/aes-mbff/config.mk index d1a31fe77d..ac7f0f1aa8 100644 --- a/flow/designs/asap7/aes-mbff/config.mk +++ b/flow/designs/asap7/aes-mbff/config.mk @@ -3,8 +3,8 @@ export PLATFORM = asap7 export DESIGN_NAME = aes_cipher_top export DESIGN_NICKNAME = aes-mbff -export VERILOG_FILES = $(sort $(wildcard ./designs/src/aes/*.v)) -export SDC_FILE = ./designs/$(PLATFORM)/aes/constraint.sdc +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/aes/*.v)) +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/aes/constraint.sdc export ABC_AREA = 1 diff --git a/flow/designs/asap7/aes/config.mk b/flow/designs/asap7/aes/config.mk index 05cd01aeee..fa660b726e 100644 --- a/flow/designs/asap7/aes/config.mk +++ b/flow/designs/asap7/aes/config.mk @@ -3,8 +3,8 @@ export PLATFORM = asap7 export DESIGN_NAME = aes_cipher_top export DESIGN_NICKNAME = aes -export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v)) -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export ABC_AREA = 1 diff --git a/flow/designs/asap7/aes_lvt/config.mk b/flow/designs/asap7/aes_lvt/config.mk index 1ae7270e25..e3d1779d9b 100644 --- a/flow/designs/asap7/aes_lvt/config.mk +++ b/flow/designs/asap7/aes_lvt/config.mk @@ -3,8 +3,8 @@ export PLATFORM = asap7 export DESIGN_NAME = aes_cipher_top export DESIGN_NICKNAME = aes_lvt -export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v)) -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export ABC_AREA = 1 diff --git a/flow/designs/asap7/ethmac/config.mk b/flow/designs/asap7/ethmac/config.mk index 00efe3335c..fad9fb1cca 100644 --- a/flow/designs/asap7/ethmac/config.mk +++ b/flow/designs/asap7/ethmac/config.mk @@ -2,8 +2,8 @@ export PLATFORM = asap7 export DESIGN_NAME = ethmac -export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v)) -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export ABC_AREA = 1 export CORE_UTILIZATION = 40 diff --git a/flow/designs/asap7/ethmac_lvt/config.mk b/flow/designs/asap7/ethmac_lvt/config.mk index 0135606146..21dc689e75 100644 --- a/flow/designs/asap7/ethmac_lvt/config.mk +++ b/flow/designs/asap7/ethmac_lvt/config.mk @@ -3,8 +3,8 @@ export PLATFORM = asap7 export DESIGN_NAME = ethmac export DESIGN_NICKNAME = ethmac_lvt -export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v)) -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export ABC_AREA = 1 export CORE_UTILIZATION = 40 diff --git a/flow/designs/asap7/gcd/config.mk b/flow/designs/asap7/gcd/config.mk index 699ddae5b7..35d247211a 100644 --- a/flow/designs/asap7/gcd/config.mk +++ b/flow/designs/asap7/gcd/config.mk @@ -2,8 +2,8 @@ export PLATFORM = asap7 export DESIGN_NAME = gcd -export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NAME)/*.v)) -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NAME)/*.v)) +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc export DIE_AREA = 0 0 16.2 16.2 export CORE_AREA = 1.08 1.08 15.12 15.12 diff --git a/flow/designs/asap7/ibex/config.mk b/flow/designs/asap7/ibex/config.mk index 53e54ba599..b49ef0dac7 100644 --- a/flow/designs/asap7/ibex/config.mk +++ b/flow/designs/asap7/ibex/config.mk @@ -3,8 +3,8 @@ export PLATFORM = asap7 export DESIGN_NICKNAME = ibex export DESIGN_NAME = ibex_core -export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v)) -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export CORE_UTILIZATION = 40 export CORE_ASPECT_RATIO = 1 diff --git a/flow/designs/asap7/jpeg/config.mk b/flow/designs/asap7/jpeg/config.mk index d23d475a8c..f00ea0e782 100644 --- a/flow/designs/asap7/jpeg/config.mk +++ b/flow/designs/asap7/jpeg/config.mk @@ -3,9 +3,9 @@ export PLATFORM = asap7 export DESIGN_NAME = jpeg_encoder export DESIGN_NICKNAME = jpeg -export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v)) -export VERILOG_INCLUDE_DIRS = ./designs/src/$(DESIGN_NICKNAME)/include -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/jpeg_encoder15_7nm.sdc +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) +export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/include +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/jpeg_encoder15_7nm.sdc export ABC_AREA = 1 export CORE_UTILIZATION = 30 diff --git a/flow/designs/asap7/jpeg_lvt/config.mk b/flow/designs/asap7/jpeg_lvt/config.mk index 2e5369ae4d..975596c3a4 100644 --- a/flow/designs/asap7/jpeg_lvt/config.mk +++ b/flow/designs/asap7/jpeg_lvt/config.mk @@ -3,9 +3,9 @@ export PLATFORM = asap7 export DESIGN_NAME = jpeg_encoder export DESIGN_NICKNAME = jpeg_lvt -export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v)) -export VERILOG_INCLUDE_DIRS = ./designs/src/$(DESIGN_NICKNAME)/include -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/jpeg_encoder15_7nm.sdc +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) +export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/include +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/jpeg_encoder15_7nm.sdc export ABC_AREA = 1 export ADDITIONAL_LIBS = $(LIB_DIR)/asap7sc7p5t_AO_LVT_FF_nldm_211120.lib.gz \ diff --git a/flow/designs/asap7/mock-array/Element/config.mk b/flow/designs/asap7/mock-array/Element/config.mk index 7965743b6a..4f4f4c3830 100644 --- a/flow/designs/asap7/mock-array/Element/config.mk +++ b/flow/designs/asap7/mock-array/Element/config.mk @@ -27,7 +27,7 @@ export IO_CONSTRAINTS = designs/asap7/mock-array/Element/io.tcl export PDN_TCL = $(FLOW_HOME)/platforms/asap7/openRoad/pdn/BLOCK_grid_strategy.tcl # Detailed routing should be easy, limit iterations -export DETAILED_ROUTE_END_ITERATION = 6 +export DETAILED_ROUTE_END_ITERATION ?= 6 export MIN_ROUTING_LAYER = M2 # M5 is the top PDN layer, so don't exceed that. diff --git a/flow/designs/asap7/mock-array/config.mk b/flow/designs/asap7/mock-array/config.mk index 7bff8603d9..52aa1de51e 100644 --- a/flow/designs/asap7/mock-array/config.mk +++ b/flow/designs/asap7/mock-array/config.mk @@ -32,7 +32,7 @@ export BLOCKS ?= Element ifneq ($(BLOCKS),) export GDS_ALLOW_EMPTY = Element ifneq ($(RTLMP_FLOW), 1) - export MACRO_PLACEMENT_TCL = ./designs/asap7/mock-array/macro-placement.tcl + export MACRO_PLACEMENT_TCL = $(DESIGN_HOME)/asap7/mock-array/macro-placement.tcl endif export PDN_TCL = $(PLATFORM_DIR)/openRoad/pdn/BLOCKS_grid_strategy.tcl endif @@ -44,33 +44,28 @@ export IO_CONSTRAINTS = designs/asap7/mock-array/io.tcl verilog: export MOCK_ARRAY_ROWS=$(word 1, $(MOCK_ARRAY_TABLE)) ; \ export MOCK_ARRAY_COLS=$(word 2, $(MOCK_ARRAY_TABLE)) ; \ - ./designs/asap7/mock-array/verilog.sh + $(DESIGN_HOME)/asap7/mock-array/verilog.sh .PHONY: simulate simulate: export MOCK_ARRAY_ROWS=$(word 1, $(MOCK_ARRAY_TABLE)) ; \ export MOCK_ARRAY_COLS=$(word 2, $(MOCK_ARRAY_TABLE)) ; \ - ./designs/asap7/mock-array/simulate.sh + $(DESIGN_HOME)/asap7/mock-array/simulate.sh .PHONY: power power: $(OPENSTA_EXE) -no_init -exit designs/asap7/mock-array/power.tcl # Routing by abutment should be easy, limit iterations -export DETAILED_ROUTE_END_ITERATION = 6 +export DETAILED_ROUTE_END_ITERATION ?= 6 export MAX_ROUTING_LAYER = M9 export ROUTING_LAYER_ADJUSTMENT = 0.45 -# works with 28 or more iterations as of writing, so give it a few more. -export GLOBAL_ROUTE_ARGS=-congestion_iterations 40 -verbose - # ensure we have some rows, so we don't get a bad clock skew. export MACRO_HALO_X = 0.5 export MACRO_HALO_Y = 0.5 -export CTS_BUF_DISTANCE = 60 - export ADDITIONAL_FILES = designs/src/mock-array/util.tcl export IO_PLACER_V = M5 M7 diff --git a/flow/designs/asap7/mock-array/macro-placement.tcl b/flow/designs/asap7/mock-array/macro-placement.tcl index aed383e579..18bd768798 100644 --- a/flow/designs/asap7/mock-array/macro-placement.tcl +++ b/flow/designs/asap7/mock-array/macro-placement.tcl @@ -1,27 +1,25 @@ -# fish out values from single source of truth: config.py -set vals [regexp -all -inline {\S+} [exec sh -c {cd designs/asap7/mock-array && python3 -c "import config;print(f'{config.rows} {config.cols} {config.pitch_x} {config.pitch_y} {config.array_offset_x} {config.array_offset_y} {config.placement_grid_x} {config.placement_grid_y}')"}]] -lassign $vals rows cols pitch_x pitch_y array_offset_x array_offset_y placement_grid_x placement_grid_y +# Define the variables x and y for the offset set block [ord::get_db_block] -set units [$block getDefUnits] +set core [$block getCoreArea] -for {set row 0} {$row < $rows} {incr row} { - for {set col 0} {$col < $cols} {incr col} { - set inst [$block findInst [format "ces_%d_%d" $row $col]] +set element [lindex [find_macros] 0] +set bbox [$element getBBox] - set x [expr round((($array_offset_x + (($placement_grid_x * $pitch_x) * $col)) * $units))] - set y [expr round((($array_offset_y + (($placement_grid_y * $pitch_y) * $row)) * $units))] +# Calculate the x and y pitch +set x_pitch [$bbox getDX] +set y_pitch [expr [$bbox getDY] + 4/[ord::dbu_to_microns 1]] - # belt and suspenders check... ASAP7 macro placement must be aligned to 0.048um - if {$x % 48 != 0} { - error "x=$x is not divisible by 48" - } - if {$y % 48 != 0} { - error "y=$y is not divisible by 48" - } +# Define the base location +set x_offset [expr [$core xMin] + ([$core dx] - (7 * $x_pitch) - [$bbox getDX])/2] +set y_offset [expr [$core yMin] + ([$core dy] - (7 * $y_pitch) - [$bbox getDY])/2] - $inst setOrient R0 - $inst setOrigin $x $y - $inst setPlacementStatus FIRM - } +# Loop through the 8x8 array, add the offset, and invoke place_macro +for {set i 0} {$i < 8} {incr i} { + for {set j 0} {$j < 8} {incr j} { + set macro_name [format "ces_%d_%d" $i $j] + set x_location [expr {$j * $x_pitch + $x_offset}] + set y_location [expr {$i * $y_pitch + $y_offset}] + place_macro -macro_name $macro_name -location [list [expr [ord::dbu_to_microns 1] * $x_location] [expr [ord::dbu_to_microns 1] * $y_location]] -orientation R0 + } } diff --git a/flow/designs/asap7/mock-cpu/config.mk b/flow/designs/asap7/mock-cpu/config.mk index f486f52e96..2eb0c35ac2 100644 --- a/flow/designs/asap7/mock-cpu/config.mk +++ b/flow/designs/asap7/mock-cpu/config.mk @@ -3,8 +3,8 @@ export PLATFORM = asap7 export DESIGN_NAME = mock_cpu export DESIGN_NICKNAME = mock-cpu -export VERILOG_FILES = $(wildcard ./designs/src/fifo/*.v) -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(wildcard $(DESIGN_HOME)/src/fifo/*.v) +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export CORE_UTILIZATION = 40 export CORE_ASPECT_RATIO = 1 diff --git a/flow/designs/asap7/riscv32i-mock-sram/fakeram7_256x32/config.mk b/flow/designs/asap7/riscv32i-mock-sram/fakeram7_256x32/config.mk index b4c53955fb..a029c68794 100644 --- a/flow/designs/asap7/riscv32i-mock-sram/fakeram7_256x32/config.mk +++ b/flow/designs/asap7/riscv32i-mock-sram/fakeram7_256x32/config.mk @@ -2,8 +2,8 @@ export DESIGN_NICKNAME = riscv32i-mock-sram_fakeram7_256x32 export DESIGN_NAME = fakeram7_256x32 export PLATFORM = asap7 -export VERILOG_FILES = ./designs/asap7/riscv32i-mock-sram/fakeram7_256x32/*.v -export SDC_FILE = ./designs/$(PLATFORM)/riscv32i-mock-sram/fakeram7_256x32/constraints.sdc +export VERILOG_FILES = $(DESIGN_HOME)/asap7/riscv32i-mock-sram/fakeram7_256x32/*.v +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/riscv32i-mock-sram/fakeram7_256x32/constraints.sdc export CORE_UTILIZATION = 50 export CORE_ASPECT_RATIO = 8 diff --git a/flow/designs/asap7/riscv32i/config.mk b/flow/designs/asap7/riscv32i/config.mk index fe7eb0779e..d129acb64e 100644 --- a/flow/designs/asap7/riscv32i/config.mk +++ b/flow/designs/asap7/riscv32i/config.mk @@ -2,7 +2,7 @@ export DESIGN_NICKNAME ?= riscv32i export DESIGN_NAME = riscv_top export PLATFORM = asap7 -export SYNTH_HIERARCHICAL = 1 +export SYNTH_HIERARCHICAL ?= 1 export RTLMP_MIN_INST = 1000 export RTLMP_MAX_INST = 3500 @@ -11,8 +11,8 @@ export RTLMP_MAX_MACRO = 5 export MAX_UNGROUP_SIZE ?= 1000 -export VERILOG_FILES = $(sort $(wildcard ./designs/src/riscv32i/*.v)) -export SDC_FILE = ./designs/$(PLATFORM)/riscv32i/constraint.sdc +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/riscv32i/*.v)) +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/riscv32i/constraint.sdc ifeq ($(BLOCKS),) export ADDITIONAL_LEFS = ./platforms/$(PLATFORM)/lef/fakeram7_256x32.lef diff --git a/flow/designs/asap7/swerv_wrapper/config.mk b/flow/designs/asap7/swerv_wrapper/config.mk index 80fa22d9c7..2a42119d6d 100644 --- a/flow/designs/asap7/swerv_wrapper/config.mk +++ b/flow/designs/asap7/swerv_wrapper/config.mk @@ -10,12 +10,12 @@ export RTLMP_MIN_MACRO = 4 export LIB_MODEL = CCS -export VERILOG_FILES = ./designs/src/swerv/swerv_wrapper.sv2v.v \ - ./designs/$(PLATFORM)/swerv_wrapper/macros.v -export SDC_FILE = ./designs/$(PLATFORM)/swerv_wrapper/constraint.sdc +export VERILOG_FILES = $(DESIGN_HOME)/src/swerv/swerv_wrapper.sv2v.v \ + $(DESIGN_HOME)/$(PLATFORM)/swerv_wrapper/macros.v +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/swerv_wrapper/constraint.sdc -export ADDITIONAL_LEFS = $(sort $(wildcard ./designs/$(PLATFORM)/swerv_wrapper/lef/*.lef)) -export ADDITIONAL_LIBS = $(sort $(wildcard ./designs/$(PLATFORM)/swerv_wrapper/lib/*.lib)) +export ADDITIONAL_LEFS = $(sort $(wildcard $(DESIGN_HOME)/$(PLATFORM)/swerv_wrapper/lef/*.lef)) +export ADDITIONAL_LIBS = $(sort $(wildcard $(DESIGN_HOME)/$(PLATFORM)/swerv_wrapper/lib/*.lib)) export DIE_AREA = 0 0 550 600 export CORE_AREA = 5 5 545 595 diff --git a/flow/designs/asap7/uart/config.mk b/flow/designs/asap7/uart/config.mk index 5f00ce2e2d..6d980d3f7d 100644 --- a/flow/designs/asap7/uart/config.mk +++ b/flow/designs/asap7/uart/config.mk @@ -3,8 +3,8 @@ export CORNER = TC export DESIGN_NAME = uart -export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v)) -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) 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"1fF", "run__flow__platform__current_units": "1uA", @@ -299,13 +362,13 @@ "run__flow__platform__time_units": "1ps", "run__flow__platform__voltage_units": "1v", "run__flow__platform_commit": "N/A", - "run__flow__scripts_commit": "dcb6ca0773163b3ff4f04a9a88c8df5f2a1860f4", - "run__flow__uuid": "9affa055-c5c1-49a7-8701-e13304ecea25", + "run__flow__scripts_commit": "ec7293db19147fc6f53f724975d2e7f587635c34", + "run__flow__uuid": "e49a753b-ce89-4f4f-9b98-17fc48d4a0c8", "run__flow__variant": "base", - "synth__cpu__total": 16.82, + "synth__cpu__total": 16.17, "synth__design__instance__area__stdcell": 3245.792252, "synth__design__instance__count__stdcell": 14430.0, - "synth__mem__peak": 423636.0, - "synth__runtime__total": "0:17.63", - "total_time": "0:03:23.510000" + "synth__mem__peak": 424192.0, + "synth__runtime__total": "0:17.08", + "total_time": "0:03:22.370000" } \ No newline at end of file diff --git a/flow/designs/gf12/aes/rules-base.json b/flow/designs/gf12/aes/rules-base.json index 3f0f364820..8203b3070d 100644 --- a/flow/designs/gf12/aes/rules-base.json +++ b/flow/designs/gf12/aes/rules-base.json @@ -8,7 +8,7 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 4526, + "value": 5357, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { @@ -52,7 +52,7 @@ "compare": ">=" }, "finish__design__instance__area": { - "value": 4590, + "value": 5428, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { diff --git a/flow/designs/gf12/ariane/config.mk b/flow/designs/gf12/ariane/config.mk index 22a38dcdf4..bc3ef63e47 100644 --- a/flow/designs/gf12/ariane/config.mk +++ b/flow/designs/gf12/ariane/config.mk @@ -5,11 +5,11 @@ export SYNTH_HIERARCHICAL = 1 export MAX_UNGROUP_SIZE ?= 10000 # -export VERILOG_FILES = ./designs/src/$(DESIGN_NAME)/ariane.sv2v.v \ - ./designs/$(PLATFORM)/$(DESIGN_NAME)/macros.v +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/ariane.sv2v.v \ + $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/macros.v -#export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NAME)/constraint_hier.sdc +#export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint_hier.sdc export WRAP_LEFS = $(PLATFORM_DIR)/lef/gf12lp_1rf_lg8_w64_byte.lef @@ -27,7 +27,7 @@ export PLACE_PINS_ARGS = -exclude left:0-150 -exclude left:450-600 -exclude righ export MACRO_PLACE_HALO = 7 7 export MACRO_PLACE_CHANNEL = 14 14 -export MACRO_WRAPPERS = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/wrappers.tcl +export MACRO_WRAPPERS = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/wrappers.tcl ifeq ($(USE_FILL),1) export DESIGN_TYPE = CELL diff --git a/flow/designs/gf12/ariane/metadata-base-ok.json b/flow/designs/gf12/ariane/metadata-base-ok.json index 5d62edce46..96024f1555 100644 --- a/flow/designs/gf12/ariane/metadata-base-ok.json +++ b/flow/designs/gf12/ariane/metadata-base-ok.json @@ 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"placeopt__timing__drv__max_slew": 0, + "placeopt__timing__drv__max_slew_limit": 9.86865e-05, + "placeopt__timing__drv__setup_violation_count": 3867, + "placeopt__timing__setup__tns": -1983520.0, + "placeopt__timing__setup__ws": -871.665, "run__flow__design": "ariane", - "run__flow__generate_date": "2024-09-19 15:55", + "run__flow__generate_date": "2024-11-23 01:01", "run__flow__metrics_version": "Metrics_2.1.2", "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-15759-g9136ba699", + "run__flow__openroad_version": "v2.0-17258-gc1904e24e", "run__flow__platform": "gf12", "run__flow__platform__capacitance_units": "1fF", "run__flow__platform__current_units": "1uA", @@ -322,13 +450,13 @@ "run__flow__platform__time_units": "1ps", "run__flow__platform__voltage_units": "1v", "run__flow__platform_commit": "N/A", - "run__flow__scripts_commit": "dcb6ca0773163b3ff4f04a9a88c8df5f2a1860f4", - "run__flow__uuid": "612fb3df-19c2-4148-8f66-648a5e10f04d", + "run__flow__scripts_commit": "ec7293db19147fc6f53f724975d2e7f587635c34", + "run__flow__uuid": "5445e416-51e4-434c-97c6-325a0960c5f6", "run__flow__variant": "base", - "synth__cpu__total": 710.92, - "synth__design__instance__area__stdcell": 170188.427926, - "synth__design__instance__count__stdcell": 181070.0, - "synth__mem__peak": 1079180.0, - "synth__runtime__total": "11:55.69", - "total_time": "1:24:56.450000" + "synth__cpu__total": 663.58, + "synth__design__instance__area__stdcell": 170170.864322, + "synth__design__instance__count__stdcell": 180817.0, + "synth__mem__peak": 785800.0, + "synth__runtime__total": "11:07.94", + "total_time": "2:04:32.270000" } \ No newline at end of file diff --git a/flow/designs/gf12/ariane/rules-base.json b/flow/designs/gf12/ariane/rules-base.json index aa480a84a4..ae13348b97 100644 --- a/flow/designs/gf12/ariane/rules-base.json +++ b/flow/designs/gf12/ariane/rules-base.json @@ -48,7 +48,7 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -211.15, + "value": -446.42, "compare": ">=" }, "finish__design__instance__area": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -14.7, + "value": -29.8, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/gf12/ariane133/config.mk b/flow/designs/gf12/ariane133/config.mk index 51dc5f6dc9..fb084b725a 100644 --- a/flow/designs/gf12/ariane133/config.mk +++ b/flow/designs/gf12/ariane133/config.mk @@ -9,7 +9,7 @@ export MAX_UNGROUP_SIZE ?= 10000 export VERILOG_FILES = $(PLATFORM_DIR)/ariane133/ariane.v -export SDC_FILE = ./designs/$(PLATFORM)/ariane133/ariane.sdc +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/ariane133/ariane.sdc export WRAP_LEFS = $(PLATFORM_DIR)/lef/gf12_1rw_256x16.lef export WRAP_LIBS = $(PLATFORM_DIR)/lib/gf12_1rw_256x16_ffpg_sigcmin_0p88v_0p88v_m40c.lib diff --git a/flow/designs/gf12/bp_single/config.mk b/flow/designs/gf12/bp_single/config.mk index f10c8732bf..8a9a24d646 100644 --- a/flow/designs/gf12/bp_single/config.mk +++ b/flow/designs/gf12/bp_single/config.mk @@ -61,7 +61,7 @@ export MACRO_PLACEMENT = $(PLATFORM_DIR)/bp/auto_fence2_bp_single.macro_placment export MACRO_BLOCKAGE_HALO = 25 export PDN_TCL = $(PLATFORM_DIR)/cfg/pdn_grid_strategy_13m_9T.top.tcl -export FASTROUTE_TCL = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/fastroute.tcl +export FASTROUTE_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/fastroute.tcl ifeq ($(USE_FILL),1) export DESIGN_TYPE = CHIP diff --git a/flow/designs/gf12/ca53/metadata-base-ok.json b/flow/designs/gf12/ca53/metadata-base-ok.json index 918604721c..dcb7094abb 100644 --- a/flow/designs/gf12/ca53/metadata-base-ok.json +++ b/flow/designs/gf12/ca53/metadata-base-ok.json @@ -3,206 +3,191 @@ "constraints__clocks__details": [ "clk: 2000.0000" ], - "cts__clock__skew__hold": 582.746, - "cts__clock__skew__setup": 460.489, - "cts__cpu__total": 2629.16, + "cts__clock__skew__hold": 687.931, + "cts__clock__skew__setup": 525.727, + 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"placeopt__timing__drv__hold_violation_count": 0, "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.00191589, + "placeopt__timing__drv__max_cap_limit": 0.034224, "placeopt__timing__drv__max_fanout": 0, "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 23, - "placeopt__timing__drv__max_slew_limit": -0.182281, + "placeopt__timing__drv__max_slew": 13, + "placeopt__timing__drv__max_slew_limit": -0.250829, "placeopt__timing__drv__setup_violation_count": 0, "placeopt__timing__setup__tns": 0, - "placeopt__timing__setup__ws": 292.142, + "placeopt__timing__setup__ws": 101.446, "run__flow__design": "ca53_cpu", - "run__flow__generate_date": "2024-10-22 07:36", + "run__flow__generate_date": "2024-09-19 21:22", "run__flow__metrics_version": "Metrics_2.1.2", "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-16686-gb522e2fe5", + "run__flow__openroad_version": "v2.0-15759-g9136ba699", "run__flow__platform": "gf12", "run__flow__platform__capacitance_units": "1fF", "run__flow__platform__current_units": "1uA", @@ -354,13 +336,13 @@ "run__flow__platform__time_units": "1ps", "run__flow__platform__voltage_units": "1v", "run__flow__platform_commit": "N/A", - "run__flow__scripts_commit": "not a git repo", - "run__flow__uuid": "c0e11029-195f-444f-b662-aeaef2168e64", + "run__flow__scripts_commit": "dcb6ca0773163b3ff4f04a9a88c8df5f2a1860f4", + "run__flow__uuid": "abe50750-2458-4eac-b250-80786df6d0d6", "run__flow__variant": "base", - "synth__cpu__total": 0.06, + "synth__cpu__total": 0.0, "synth__design__instance__area__stdcell": "ERR", "synth__design__instance__count__stdcell": "ERR", - "synth__mem__peak": 12544.0, - "synth__runtime__total": "0:00.35", - "total_time": "4:13:17.470000" + "synth__mem__peak": 12800.0, + "synth__runtime__total": "0:00.25", + "total_time": "5:00:33.180000" } \ No newline at end of file diff --git a/flow/designs/gf12/ca53/rules-base.json b/flow/designs/gf12/ca53/rules-base.json index 7475c50912..6f1e37e918 100644 --- a/flow/designs/gf12/ca53/rules-base.json +++ b/flow/designs/gf12/ca53/rules-base.json @@ -56,7 +56,7 @@ "compare": "<=" }, "finish__timing__drv__hold_violation_count": { - "value": 9718, + "value": 4971, "compare": "<=" }, "finish__timing__wns_percent_delay": { diff --git a/flow/designs/gf12/coyote/config.mk b/flow/designs/gf12/coyote/config.mk index 5a754be25b..db5c537c5c 100644 --- a/flow/designs/gf12/coyote/config.mk +++ b/flow/designs/gf12/coyote/config.mk @@ -2,10 +2,10 @@ export DESIGN_NICKNAME = coyote export DESIGN_NAME = bsg_rocket_node_client_rocc export PLATFORM = gf12 -export VERILOG_FILES = ./designs/src/$(DESIGN_NICKNAME)/coyote.sv2v.v \ - ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/macros.v +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/coyote.sv2v.v \ + $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/macros.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export ABC_AREA = 1 export WRAP_LEFS = $(PLATFORM_DIR)/lef/gf12_1rf_lg6_w80_bit.lef \ @@ -25,7 +25,7 @@ export ADDITIONAL_GDS = $(PLATFORM_DIR)/gds/gf12_1rf_lg6_w80_bit.gds2 \ export PLACE_DENSITY = 0.35 -export MACRO_WRAPPERS = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/wrappers.tcl +export MACRO_WRAPPERS = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/wrappers.tcl export DIE_AREA = 0 0 752 752 export CORE_AREA = 2 2 750 750 diff --git a/flow/designs/gf12/gcd/config.mk b/flow/designs/gf12/gcd/config.mk index f35f197557..470e63993d 100644 --- a/flow/designs/gf12/gcd/config.mk +++ b/flow/designs/gf12/gcd/config.mk @@ -2,8 +2,8 @@ export DESIGN_NICKNAME = gcd_$(TRACK_OPTION)_$(TECH_OPTION) export DESIGN_NAME = gcd export PLATFORM = gf12 -export VERILOG_FILES = ./designs/src/$(DESIGN_NAME)/gcd.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/gcd.v +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc # These values must be multiples of placement site export DIE_AREA = 0 0 99.96 100.128 diff --git a/flow/designs/gf12/ibex/config.mk b/flow/designs/gf12/ibex/config.mk index 54be100405..c94bfc69e1 100644 --- a/flow/designs/gf12/ibex/config.mk +++ b/flow/designs/gf12/ibex/config.mk @@ -3,47 +3,47 @@ export DESIGN_NAME = ibex_core export PLATFORM = gf12 -export VERILOG_FILES = ./designs/src/$(DESIGN_NICKNAME)/ibex_alu.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_branch_predict.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_compressed_decoder.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_controller.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_core.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_counter.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_cs_registers.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_csr.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_decoder.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_dummy_instr.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_ex_block.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_fetch_fifo.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_icache.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_id_stage.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_if_stage.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_load_store_unit.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_multdiv_fast.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_multdiv_slow.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_pmp.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_prefetch_buffer.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_register_file_ff.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_register_file_fpga.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_register_file_latch.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_wb_stage.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_badbit_ram_1p.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_clock_gating.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_generic_clock_gating.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_generic_ram_1p.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_lfsr.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_ram_1p.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_28_22_dec.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_28_22_enc.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_39_32_dec.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_39_32_enc.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_72_64_dec.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_72_64_enc.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_xilinx_clock_gating.v - - - -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_alu.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_branch_predict.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_compressed_decoder.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_controller.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_core.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_counter.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_cs_registers.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_csr.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_decoder.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_dummy_instr.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_ex_block.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_fetch_fifo.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_icache.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_id_stage.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_if_stage.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_load_store_unit.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_fast.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_slow.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_pmp.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_prefetch_buffer.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_ff.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_fpga.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_latch.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_wb_stage.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_badbit_ram_1p.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_clock_gating.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_generic_clock_gating.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_generic_ram_1p.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_lfsr.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_ram_1p.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_28_22_dec.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_28_22_enc.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_39_32_dec.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_39_32_enc.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_72_64_dec.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_72_64_enc.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_xilinx_clock_gating.v + + + +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export CORE_UTILIZATION = 40 export CORE_ASPECT_RATIO = 1 diff --git a/flow/designs/gf12/jpeg/config.mk b/flow/designs/gf12/jpeg/config.mk index df448a8a43..3a817b948a 100644 --- a/flow/designs/gf12/jpeg/config.mk +++ b/flow/designs/gf12/jpeg/config.mk @@ -2,10 +2,10 @@ export DESIGN_NICKNAME = jpeg export DESIGN_NAME = jpeg_encoder export PLATFORM = gf12 -export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v)) -export VERILOG_INCLUDE_DIRS = ./designs/src/$(DESIGN_NICKNAME)/include +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) +export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/include -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export ABC_AREA = 1 export CORE_UTILIZATION = 40 diff --git a/flow/designs/gf12/swerv_wrapper/config.mk b/flow/designs/gf12/swerv_wrapper/config.mk index 6ebac68cbc..56b208a44d 100644 --- a/flow/designs/gf12/swerv_wrapper/config.mk +++ b/flow/designs/gf12/swerv_wrapper/config.mk @@ -10,9 +10,9 @@ export RTLMP_MIN_INST = 5000 export RTLMP_MAX_MACRO = 12 export RTLMP_MIN_MACRO = 4 -export VERILOG_FILES = ./designs/src/swerv/swerv_wrapper.sv2v.v \ - ./designs/$(PLATFORM)/$(DESIGN_NAME)/macros.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc +export VERILOG_FILES = $(DESIGN_HOME)/src/swerv/swerv_wrapper.sv2v.v \ + $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/macros.v +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc export WRAP_LEFS = $(PLATFORM_DIR)/lef/gf12_1rf_lg11_w40_all.lef \ $(PLATFORM_DIR)/lef/gf12_1rf_lg6_w22_all.lef \ @@ -32,7 +32,7 @@ export CORE_AREA = 2 2 608 498 export PLACE_PINS_ARGS = -exclude left:* -exclude right:* -exclude top:* -exclude bottom:0-10 -exclude bottom:400-700 export PLACE_DENSITY_LB_ADDON = 0.05 -export MACRO_WRAPPERS = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/wrappers.tcl +export MACRO_WRAPPERS = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/wrappers.tcl # export MACRO_PLACE_HALO = 7 7 export MACRO_PLACE_CHANNEL = 14 14 diff --git a/flow/designs/gf12/swerv_wrapper/metadata-base-ok.json b/flow/designs/gf12/swerv_wrapper/metadata-base-ok.json index 19a654344a..6496b7ded9 100644 --- a/flow/designs/gf12/swerv_wrapper/metadata-base-ok.json +++ b/flow/designs/gf12/swerv_wrapper/metadata-base-ok.json @@ -4,314 +4,292 @@ "core_clock: 1500.0000", "jtag_clock: 1500.0000" ], - "cts__clock__skew__hold": 323.499, - "cts__clock__skew__setup": 295.284, - "cts__cpu__total": 1069.32, + "cts__clock__skew__hold": 352.327, + "cts__clock__skew__setup": 327.443, + "cts__cpu__total": 1263.09, "cts__design__core__area": 300176, "cts__design__die__area": 305000, - "cts__design__instance__area": 160446, + "cts__design__instance__area": 160592, "cts__design__instance__area__macros": 107153, - "cts__design__instance__area__stdcell": 53292.8, - "cts__design__instance__count": 121570, - "cts__design__instance__count__hold_buffer": 12729, + "cts__design__instance__area__stdcell": 53438.8, + "cts__design__instance__count": 122002, + "cts__design__instance__count__hold_buffer": 12645, "cts__design__instance__count__macros": 28, - "cts__design__instance__count__setup_buffer": 32, - "cts__design__instance__count__stdcell": 121542, - "cts__design__instance__displacement__max": 3.456, - "cts__design__instance__displacement__mean": 0.073, - "cts__design__instance__displacement__total": 8936.74, - "cts__design__instance__utilization": 0.534506, - "cts__design__instance__utilization__stdcell": 0.276096, + "cts__design__instance__count__setup_buffer": 25, + "cts__design__instance__count__stdcell": 121974, + "cts__design__instance__displacement__max": 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"v2.0-15759-g9136ba699", "run__flow__platform": "gf12", "run__flow__platform__capacitance_units": "1fF", "run__flow__platform__current_units": "1uA", @@ -321,13 +299,13 @@ "run__flow__platform__time_units": "1ps", "run__flow__platform__voltage_units": "1v", "run__flow__platform_commit": "N/A", - "run__flow__scripts_commit": "not a git repo", - "run__flow__uuid": "b8f03b92-3079-441c-b6ee-90600ac39cfc", + "run__flow__scripts_commit": "dcb6ca0773163b3ff4f04a9a88c8df5f2a1860f4", + "run__flow__uuid": "0f83e524-7073-4d84-affb-6fc980c8fd03", "run__flow__variant": "base", - "synth__cpu__total": 345.76, - "synth__design__instance__area__stdcell": 136810.82701, - "synth__design__instance__count__stdcell": 94783.0, - "synth__mem__peak": 1262064.0, - "synth__runtime__total": "5:49.24", - "total_time": "0:44:39.710000" + "synth__cpu__total": 365.41, + "synth__design__instance__area__stdcell": 136814.601002, + "synth__design__instance__count__stdcell": 95238.0, + "synth__mem__peak": 1238052.0, + "synth__runtime__total": "6:08.40", + "total_time": "0:51:49.570000" } \ No newline at end of file diff --git a/flow/designs/gf12/swerv_wrapper/rules-base.json b/flow/designs/gf12/swerv_wrapper/rules-base.json index 828a641b10..ee782b1b4c 100644 --- a/flow/designs/gf12/swerv_wrapper/rules-base.json +++ b/flow/designs/gf12/swerv_wrapper/rules-base.json @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 2129575, + "value": 2132201, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -60,7 +60,7 @@ "compare": "<=" }, "finish__timing__drv__hold_violation_count": { - "value": 3946, + "value": 660, "compare": "<=" }, "finish__timing__wns_percent_delay": { diff --git a/flow/designs/gf12/tinyRocket/config.mk b/flow/designs/gf12/tinyRocket/config.mk index 673bfe72b0..98eeb8da2e 100644 --- a/flow/designs/gf12/tinyRocket/config.mk +++ b/flow/designs/gf12/tinyRocket/config.mk @@ -5,14 +5,14 @@ export PLATFORM = gf12 export SYNTH_HIERARCHICAL = 1 export MAX_UNGROUP_SIZE ?= 1000 -export VERILOG_FILES = ./designs/src/$(DESIGN_NICKNAME)/AsyncResetReg.v \ - ./designs/src/$(DESIGN_NICKNAME)/ClockDivider2.v \ - ./designs/src/$(DESIGN_NICKNAME)/ClockDivider3.v \ - ./designs/src/$(DESIGN_NICKNAME)/plusarg_reader.v \ - ./designs/src/$(DESIGN_NICKNAME)/freechips.rocketchip.system.TinyConfig.v \ - ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/macros.v +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/AsyncResetReg.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ClockDivider2.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ClockDivider3.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/plusarg_reader.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/freechips.rocketchip.system.TinyConfig.v \ + $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/macros.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export WRAP_LEFS = $(PLATFORM_DIR)/lef/gf12_1rf_lg6_w32_all.lef \ $(PLATFORM_DIR)/lef/gf12_1rf_lg6_w32_byte.lef @@ -31,7 +31,7 @@ export CORE_AREA = 19.992 20.16 380.016 380.16 export PLACE_DENSITY = 0.20 -export MACRO_WRAPPERS = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/wrappers.tcl +export MACRO_WRAPPERS = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/wrappers.tcl ifeq ($(USE_FILL),1) export DESIGN_TYPE = CELL diff --git a/flow/designs/gf180/aes-hybrid/config.mk b/flow/designs/gf180/aes-hybrid/config.mk index 2113b1a32f..7da1e35827 100644 --- a/flow/designs/gf180/aes-hybrid/config.mk +++ b/flow/designs/gf180/aes-hybrid/config.mk @@ -3,7 +3,7 @@ export DESIGN_NAME = aes_cipher_top export PLATFORM = gf180 # See the README -export SC_LEF = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/adjusted-gf180mcu_5LM_1TM_9K_9t_sc.lef +export SC_LEF = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/adjusted-gf180mcu_5LM_1TM_9K_9t_sc.lef export BC_ADDITIONAL_LIB_FILES = gf180mcu_fd_sc_mcu7t$(POWER_OPTION)__ff_n40C_5v50.lib.gz @@ -11,7 +11,7 @@ export WC_ADDITIONAL_LIB_FILES = gf180mcu_fd_sc_mcu7t$(POWER_OPTION)__ss_125C_4v export TC_ADDITIONAL_LIB_FILES = gf180mcu_fd_sc_mcu7t$(POWER_OPTION)__tt_025C_5v00.lib.gz -export ADDITIONAL_LEFS = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/hybrid_sites.lef \ +export ADDITIONAL_LEFS = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/hybrid_sites.lef \ $(PLATFORM_DIR)/lef/gf180mcu_5LM_1TM_9K_7t_sc.lef export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/$($(CORNER)_ADDITIONAL_LIB_FILES) #export ADDITIONAL_GDS = $(wildcard $(PLATFORM_DIR)/gds/7t/*.gds) @@ -20,8 +20,8 @@ export GDS_ALLOW_EMPTY = gf180mcu_fd_sc_mcu7t5v0__.* export PLACE_SITE = sc9sc7 -export VERILOG_FILES = $(sort $(wildcard ./designs/src/aes/*.v)) -export SDC_FILE = ./designs/$(PLATFORM)/aes/constraint.sdc +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/aes/*.v)) +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/aes/constraint.sdc export ABC_AREA = 1 export CORE_UTILIZATION = 30 diff --git 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"value": 1849747, + "value": 1826404, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,11 +44,11 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 22, + "value": 15, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -1.39, + "value": -1.38, "compare": ">=" }, "finish__design__instance__area": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -41.15, + "value": -40.85, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/gf180/aes/config.mk b/flow/designs/gf180/aes/config.mk index c11063120d..74abc9da2d 100644 --- a/flow/designs/gf180/aes/config.mk +++ b/flow/designs/gf180/aes/config.mk @@ -2,8 +2,8 @@ export DESIGN_NICKNAME = aes export DESIGN_NAME = aes_cipher_top export PLATFORM = gf180 -export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v)) -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(sort 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"v2.0-16239-ge23ebb9f9", + "run__flow__openroad_version": "v2.0-17258-gc1904e24e", "run__flow__platform": "gf180", "run__flow__platform__capacitance_units": "1pF", "run__flow__platform__current_units": "1mA", @@ -308,12 +369,12 @@ "run__flow__platform__voltage_units": "1v", "run__flow__platform_commit": "N/A", "run__flow__scripts_commit": "not a git repo", - "run__flow__uuid": "2b701c1b-2d5c-4769-b843-a5e5fb2300d1", + "run__flow__uuid": "a78ebf22-7935-47ac-abf1-a44215ba4824", "run__flow__variant": "base", - "synth__cpu__total": 24.76, + "synth__cpu__total": 22.15, "synth__design__instance__area__stdcell": 542978.9568, "synth__design__instance__count__stdcell": 16498.0, - "synth__mem__peak": 336652.0, - "synth__runtime__total": "0:25.28", - "total_time": "0:13:51.270000" + "synth__mem__peak": 336656.0, + "synth__runtime__total": "0:22.63", + "total_time": "0:10:51.170000" } \ No newline at end of file diff --git a/flow/designs/gf180/aes/rules-base.json b/flow/designs/gf180/aes/rules-base.json index dab9770552..64ef15f9d3 100644 --- a/flow/designs/gf180/aes/rules-base.json +++ b/flow/designs/gf180/aes/rules-base.json @@ -28,7 +28,7 @@ "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 1, + "value": 16, "compare": "<=" }, "detailedroute__route__wirelength": { @@ -44,11 +44,11 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 3, + "value": 14, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -1.23, + "value": -1.17, "compare": ">=" }, "finish__design__instance__area": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -37.66, + "value": -36.86, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/gf180/ibex/config.mk b/flow/designs/gf180/ibex/config.mk index 0954f47fc0..ebeeadf520 100644 --- a/flow/designs/gf180/ibex/config.mk +++ b/flow/designs/gf180/ibex/config.mk @@ -2,45 +2,45 @@ export DESIGN_NICKNAME = ibex export DESIGN_NAME = ibex_core export PLATFORM = gf180 -export VERILOG_FILES = ./designs/src/$(DESIGN_NICKNAME)/ibex_alu.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_branch_predict.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_compressed_decoder.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_controller.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_core.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_counter.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_cs_registers.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_csr.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_decoder.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_dummy_instr.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_ex_block.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_fetch_fifo.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_icache.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_id_stage.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_if_stage.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_load_store_unit.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_multdiv_fast.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_multdiv_slow.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_pmp.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_prefetch_buffer.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_register_file_ff.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_register_file_fpga.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_register_file_latch.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_wb_stage.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_badbit_ram_1p.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_clock_gating.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_generic_clock_gating.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_generic_ram_1p.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_lfsr.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_ram_1p.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_28_22_dec.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_28_22_enc.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_39_32_dec.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_39_32_enc.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_72_64_dec.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_72_64_enc.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_xilinx_clock_gating.v +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_alu.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_branch_predict.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_compressed_decoder.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_controller.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_core.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_counter.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_cs_registers.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_csr.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_decoder.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_dummy_instr.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_ex_block.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_fetch_fifo.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_icache.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_id_stage.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_if_stage.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_load_store_unit.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_fast.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_slow.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_pmp.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_prefetch_buffer.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_ff.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_fpga.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_latch.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_wb_stage.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_badbit_ram_1p.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_clock_gating.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_generic_clock_gating.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_generic_ram_1p.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_lfsr.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_ram_1p.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_28_22_dec.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_28_22_enc.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_39_32_dec.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_39_32_enc.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_72_64_dec.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_72_64_enc.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_xilinx_clock_gating.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export CORE_UTILIZATION = 45 export PLACE_DENSITY_LB_ADDON = 0.1 diff --git a/flow/designs/gf180/ibex/metadata-base-ok.json b/flow/designs/gf180/ibex/metadata-base-ok.json index 48990f1db9..8e453fcc04 100644 --- a/flow/designs/gf180/ibex/metadata-base-ok.json +++ b/flow/designs/gf180/ibex/metadata-base-ok.json @@ -3,55 +3,67 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- "cts__power__internal__total": 2.13421, - "cts__power__leakage__total": 4.88739e-06, - "cts__power__switching__total": 1.45043, - "cts__power__total": 3.58465, - "cts__route__wirelength__estimated": 1265720.0, - "cts__runtime__total": "17:17.65", + "cts__mem__peak": 705168.0, + "cts__power__internal__total": 2.14073, + "cts__power__leakage__total": 4.84017e-06, + "cts__power__switching__total": 1.4658, + "cts__power__total": 3.60654, + "cts__route__wirelength__estimated": 1277920.0, + "cts__runtime__total": "11:15.42", "cts__timing__drv__hold_violation_count": 0, "cts__timing__drv__max_cap": 0, "cts__timing__drv__max_cap_limit": 0.435791, "cts__timing__drv__max_fanout": 0, "cts__timing__drv__max_fanout_limit": 0, "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew_limit": 0.289091, - "cts__timing__drv__setup_violation_count": 868, - "cts__timing__setup__tns": -814.352, - "cts__timing__setup__ws": -1.74975, + "cts__timing__drv__max_slew_limit": 0.288878, + "cts__timing__drv__setup_violation_count": 622, + "cts__timing__setup__tns": -206.947, + "cts__timing__setup__ws": -1.17232, "design__io__hpwl": 129760044, "design__violations": 0, - "detailedplace__cpu__total": 25.83, + "detailedplace__cpu__total": 18.26, "detailedplace__design__core__area": 1436150.0, "detailedplace__design__die__area": 1450880.0, "detailedplace__design__instance__area": 746559, + "detailedplace__design__instance__area__cover": 0, "detailedplace__design__instance__area__macros": 0, + "detailedplace__design__instance__area__padcells": 0, "detailedplace__design__instance__area__stdcell": 746559, "detailedplace__design__instance__count": 15889, + "detailedplace__design__instance__count__cover": 0, "detailedplace__design__instance__count__macros": 0, + "detailedplace__design__instance__count__padcells": 0, "detailedplace__design__instance__count__stdcell": 15889, "detailedplace__design__instance__displacement__max": 44.8, "detailedplace__design__instance__displacement__mean": 4.9875, @@ -59,16 +71,20 @@ "detailedplace__design__instance__utilization": 0.519834, "detailedplace__design__instance__utilization__stdcell": 0.519834, "detailedplace__design__io": 264, + "detailedplace__design__rows": 237, + "detailedplace__design__rows:GF018hv5v_green_sc9": 237, + "detailedplace__design__sites": 508839, + "detailedplace__design__sites:GF018hv5v_green_sc9": 508839, "detailedplace__design__violations": 0, "detailedplace__flow__errors__count": 0, "detailedplace__flow__warnings__count": 0, - "detailedplace__mem__peak": 309196.0, + "detailedplace__mem__peak": 305084.0, "detailedplace__power__internal__total": 1.74593, "detailedplace__power__leakage__total": 4.49012e-06, "detailedplace__power__switching__total": 1.2454, "detailedplace__power__total": 2.99133, "detailedplace__route__wirelength__estimated": 1195600.0, - "detailedplace__runtime__total": "0:26.03", + "detailedplace__runtime__total": "0:18.43", "detailedplace__timing__drv__hold_violation_count": 0, "detailedplace__timing__drv__max_cap": 0, "detailedplace__timing__drv__max_cap_limit": 0.42805, @@ -81,209 +97,251 @@ "detailedplace__timing__setup__ws": -1.74542, "detailedroute__antenna__violating__nets": 0, "detailedroute__antenna__violating__pins": 0, - "detailedroute__antenna_diodes_count": 8, + "detailedroute__antenna_diodes_count": 2, "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 20, + "detailedroute__flow__warnings__count": 16, "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 29, - "detailedroute__route__drc_errors__iter:2": 6, - "detailedroute__route__drc_errors__iter:3": 6, + "detailedroute__route__drc_errors__iter:1": 42, + "detailedroute__route__drc_errors__iter:2": 12, + "detailedroute__route__drc_errors__iter:3": 1, "detailedroute__route__drc_errors__iter:4": 0, - "detailedroute__route__drc_errors__iter:5": 9, - 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"placeopt__design__sites:GF018hv5v_green_sc9": 508839, "placeopt__flow__errors__count": 0, "placeopt__flow__warnings__count": 1, - "placeopt__mem__peak": 545576.0, + "placeopt__mem__peak": 542780.0, "placeopt__power__internal__total": 1.74671, "placeopt__power__leakage__total": 4.49012e-06, "placeopt__power__switching__total": 1.23635, "placeopt__power__total": 2.98306, - "placeopt__runtime__total": "0:26.77", + "placeopt__runtime__total": "0:19.16", "placeopt__timing__drv__floating__nets": 0, "placeopt__timing__drv__floating__pins": 1, "placeopt__timing__drv__hold_violation_count": 0, @@ -297,10 +355,10 @@ "placeopt__timing__setup__tns": -657.364, "placeopt__timing__setup__ws": -1.6933, "run__flow__design": "ibex", - "run__flow__generate_date": "2024-10-03 21:26", + "run__flow__generate_date": "2024-11-22 14:06", "run__flow__metrics_version": "Metrics_2.1.2", "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-16239-ge23ebb9f9", + "run__flow__openroad_version": "v2.0-17198-g8396d0866", "run__flow__platform": "gf180", "run__flow__platform__capacitance_units": "1pF", "run__flow__platform__current_units": "1mA", @@ -311,12 +369,12 @@ "run__flow__platform__voltage_units": "1v", "run__flow__platform_commit": "N/A", "run__flow__scripts_commit": "not a git repo", - "run__flow__uuid": "0cd7c440-939a-4d73-a117-23c67f225923", + "run__flow__uuid": "d617959e-3147-4a62-9467-180c3cdeff80", "run__flow__variant": "base", - "synth__cpu__total": 86.07, + "synth__cpu__total": 59.31, "synth__design__instance__area__stdcell": 650732.544, "synth__design__instance__count__stdcell": 13731.0, - "synth__mem__peak": 233056.0, - "synth__runtime__total": "1:26.42", - "total_time": "0:38:53.280000" + "synth__mem__peak": 157424.0, + "synth__runtime__total": "0:59.60", + "total_time": "0:24:06.690000" } \ No newline at end of file diff --git a/flow/designs/gf180/ibex/rules-base.json b/flow/designs/gf180/ibex/rules-base.json index 3acfaf2b5e..7a4ee74ee7 100644 --- a/flow/designs/gf180/ibex/rules-base.json +++ b/flow/designs/gf180/ibex/rules-base.json @@ -28,7 +28,7 @@ "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 12, + "value": 18, "compare": "<=" }, "detailedroute__route__wirelength": { @@ -44,11 +44,11 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 9, + "value": 5, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -2.28, + "value": -1.91, "compare": ">=" }, "finish__design__instance__area": { @@ -56,7 +56,7 @@ "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 1082, + "value": 794, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -31.88, + "value": -28.08, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/gf180/jpeg/config.mk b/flow/designs/gf180/jpeg/config.mk index f3d6be3acd..edce7ef623 100644 --- a/flow/designs/gf180/jpeg/config.mk +++ b/flow/designs/gf180/jpeg/config.mk @@ -2,9 +2,9 @@ export DESIGN_NICKNAME = jpeg export DESIGN_NAME = jpeg_encoder export PLATFORM = gf180 -export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v)) -export VERILOG_INCLUDE_DIRS = ./designs/src/$(DESIGN_NICKNAME)/include -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) +export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/include +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export CORE_UTILIZATION = 45 export PLACE_DENSITY_LB_ADDON = 0.20 diff --git a/flow/designs/gf180/riscv32i/config.mk b/flow/designs/gf180/riscv32i/config.mk index 5ebdc8f5be..7fd7df9230 100644 --- a/flow/designs/gf180/riscv32i/config.mk +++ b/flow/designs/gf180/riscv32i/config.mk @@ -2,8 +2,8 @@ export DESIGN_NICKNAME = riscv32i export DESIGN_NAME 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"run__flow__openroad_version": "v2.0-16507-gd0e17f1a2", + "run__flow__openroad_version": "v2.0-17258-gc1904e24e", "run__flow__platform": "gf180", "run__flow__platform__capacitance_units": "1pF", "run__flow__platform__current_units": "1mA", @@ -309,12 +369,12 @@ "run__flow__platform__voltage_units": "1v", "run__flow__platform_commit": "N/A", "run__flow__scripts_commit": "not a git repo", - "run__flow__uuid": "7aa9f3e3-49f4-49a0-91ae-ffcabb1f3048", + "run__flow__uuid": "f62a6bc1-95d6-4dc4-bb27-a1f79a759f69", "run__flow__variant": "base", - "synth__cpu__total": 33.56, + "synth__cpu__total": 33.31, "synth__design__instance__area__stdcell": 309456.4032, "synth__design__instance__count__stdcell": 6256.0, "synth__mem__peak": 82176.0, - "synth__runtime__total": "0:33.81", - "total_time": "0:06:40.070000" + "synth__runtime__total": "0:33.52", + "total_time": "0:07:13.620000" } \ No newline at end of file diff --git a/flow/designs/gf180/riscv32i/rules-base.json b/flow/designs/gf180/riscv32i/rules-base.json index 0c70fb92fd..b7ab511eb7 100644 --- a/flow/designs/gf180/riscv32i/rules-base.json +++ b/flow/designs/gf180/riscv32i/rules-base.json @@ -28,7 +28,7 @@ "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 2, + "value": 5, "compare": "<=" }, "detailedroute__route__wirelength": { diff --git a/flow/designs/gf180/uart-blocks/config.mk b/flow/designs/gf180/uart-blocks/config.mk index 033e53d088..70ba7881f3 100644 --- a/flow/designs/gf180/uart-blocks/config.mk +++ b/flow/designs/gf180/uart-blocks/config.mk @@ -3,8 +3,8 @@ export PLATFORM = gf180 export DESIGN_NAME = uart export DESIGN_NICKNAME = uart-blocks -export VERILOG_FILES = ./designs/src/uart-no-param/*.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(DESIGN_HOME)/src/uart-no-param/*.v +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export SYNTH_HIERARCHICAL = 1 export BLOCKS = uart_rx @@ -17,9 +17,9 @@ export PLACE_PINS_ARGS = -exclude bottom:* -exclude top:* -exclude right:* export MACRO_PLACE_HALO = 20 20 export MACRO_PLACE_CHANNEL = 20 20 -export PDN_TCL = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/BLOCKS_grid_strategy.tcl +export PDN_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/BLOCKS_grid_strategy.tcl export PLACE_DENSITY = 0.60 -export TAPCELL_TCL ?= ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/tapcell.tcl +export TAPCELL_TCL ?= $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/tapcell.tcl export MACRO_HALO_X = 14 export MACRO_HALO_Y = 14 diff --git a/flow/designs/gf180/uart-blocks/metadata-base-ok.json b/flow/designs/gf180/uart-blocks/metadata-base-ok.json index c81aaacd8d..6bb1cf42ac 100644 --- a/flow/designs/gf180/uart-blocks/metadata-base-ok.json +++ b/flow/designs/gf180/uart-blocks/metadata-base-ok.json @@ -3,299 +3,358 @@ "constraints__clocks__details": [ "clk: 6.0000" ], - "cts__clock__skew__hold": 0.0023147, - "cts__clock__skew__setup": 0.0023147, - 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git repo", - "run__flow__uuid": "08239734-9e09-48e7-a2ad-ecc404022164", + "run__flow__uuid": "604ca928-0867-43b3-8504-ea4a991e8b79", "run__flow__variant": "base", - "synth__cpu__total": 2.51, - "synth__design__instance__area__stdcell": 54754.4314, + "synth__cpu__total": 2.57, + "synth__design__instance__area__stdcell": 54754.4774, "synth__design__instance__count__stdcell": 249.0, - "synth__mem__peak": 67072.0, - "synth__runtime__total": "0:02.66", - "total_time": "0:00:37.510000" + "synth__mem__peak": 66560.0, + "synth__runtime__total": "0:02.71", + "total_time": "0:00:36.870000" } \ No newline at end of file diff --git a/flow/designs/gf180/uart-blocks/rules-base.json b/flow/designs/gf180/uart-blocks/rules-base.json index df7eb920d2..d16e164302 100644 --- a/flow/designs/gf180/uart-blocks/rules-base.json +++ b/flow/designs/gf180/uart-blocks/rules-base.json @@ -28,7 +28,7 @@ "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 10, + "value": 14, "compare": "<=" }, "detailedroute__route__wirelength": { diff --git a/flow/designs/gf180/uart-blocks/uart_rx/config.mk b/flow/designs/gf180/uart-blocks/uart_rx/config.mk index 688159feff..28d3e1aaf4 100644 --- a/flow/designs/gf180/uart-blocks/uart_rx/config.mk +++ b/flow/designs/gf180/uart-blocks/uart_rx/config.mk @@ -3,15 +3,15 @@ export PLATFORM = gf180 export DESIGN_NAME = uart_rx export DESIGN_NICKNAME = uart-blocks_uart_rx -export VERILOG_FILES = ./designs/src/uart-no-param/*.v -export SDC_FILE = ./designs/$(PLATFORM)/uart-blocks/uart_rx/constraint.sdc +export VERILOG_FILES = $(DESIGN_HOME)/src/uart-no-param/*.v +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/uart-blocks/uart_rx/constraint.sdc export CORE_UTILIZATION = 30 export CORE_ASPECT_RATIO = 1 export CORE_MARGIN = 2 export PLACE_DENSITY = 0.60 -export PDN_TCL = ./designs/$(PLATFORM)/uart-blocks/BLOCKS_grid_strategy.tcl +export PDN_TCL = $(DESIGN_HOME)/$(PLATFORM)/uart-blocks/BLOCKS_grid_strategy.tcl export PLACE_PINS_ARGS = -exclude bottom:* -exclude top:* -exclude right:* diff --git a/flow/designs/gf55/aes/config.mk b/flow/designs/gf55/aes/config.mk index 2ba971e3fd..51640fcc8d 100644 --- a/flow/designs/gf55/aes/config.mk +++ b/flow/designs/gf55/aes/config.mk @@ -5,7 +5,7 @@ export DESIGN_NICKNAME = aes export DESIGN_NAME = aes_cipher_top export PLATFORM = gf55 -export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v)) +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) export SDC_FILE = $(DESIGN_DIR)/constraint.sdc export ABC_AREA = 1 diff --git a/flow/designs/ihp-sg13g2/aes/config.mk b/flow/designs/ihp-sg13g2/aes/config.mk index c72e089d8d..5acb53d84d 100644 --- a/flow/designs/ihp-sg13g2/aes/config.mk +++ b/flow/designs/ihp-sg13g2/aes/config.mk @@ -2,8 +2,8 @@ export DESIGN_NICKNAME = aes export DESIGN_NAME = aes_cipher_top export PLATFORM = ihp-sg13g2 -export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v)) -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export CORE_UTILIZATION = 20 export CORE_ASPECT_RATIO = 1 diff --git a/flow/designs/ihp-sg13g2/gcd/config.mk b/flow/designs/ihp-sg13g2/gcd/config.mk index a6d9895c17..7fceb006ae 100644 --- a/flow/designs/ihp-sg13g2/gcd/config.mk +++ b/flow/designs/ihp-sg13g2/gcd/config.mk @@ -1,8 +1,8 @@ export DESIGN_NAME = gcd export PLATFORM = ihp-sg13g2 -export VERILOG_FILES = ./designs/src/$(DESIGN_NICKNAME)/gcd.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/gcd.v +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export USE_FILL = 1 diff --git a/flow/designs/ihp-sg13g2/ibex/config.mk b/flow/designs/ihp-sg13g2/ibex/config.mk index ed352f6283..8565d7e0b5 100644 --- a/flow/designs/ihp-sg13g2/ibex/config.mk +++ b/flow/designs/ihp-sg13g2/ibex/config.mk @@ -2,45 +2,45 @@ export DESIGN_NICKNAME = ibex export DESIGN_NAME = ibex_core export PLATFORM = ihp-sg13g2 -export VERILOG_FILES = ./designs/src/$(DESIGN_NICKNAME)/ibex_alu.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_branch_predict.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_compressed_decoder.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_controller.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_core.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_counter.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_cs_registers.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_csr.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_decoder.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_dummy_instr.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_ex_block.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_fetch_fifo.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_icache.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_id_stage.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_if_stage.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_load_store_unit.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_multdiv_fast.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_multdiv_slow.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_pmp.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_prefetch_buffer.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_register_file_ff.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_register_file_fpga.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_register_file_latch.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_wb_stage.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_badbit_ram_1p.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_clock_gating.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_generic_clock_gating.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_generic_ram_1p.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_lfsr.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_ram_1p.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_28_22_dec.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_28_22_enc.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_39_32_dec.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_39_32_enc.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_72_64_dec.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_72_64_enc.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_xilinx_clock_gating.v +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_alu.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_branch_predict.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_compressed_decoder.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_controller.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_core.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_counter.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_cs_registers.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_csr.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_decoder.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_dummy_instr.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_ex_block.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_fetch_fifo.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_icache.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_id_stage.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_if_stage.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_load_store_unit.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_fast.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_slow.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_pmp.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_prefetch_buffer.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_ff.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_fpga.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_latch.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_wb_stage.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_badbit_ram_1p.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_clock_gating.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_generic_clock_gating.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_generic_ram_1p.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_lfsr.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_ram_1p.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_28_22_dec.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_28_22_enc.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_39_32_dec.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_39_32_enc.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_72_64_dec.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_72_64_enc.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_xilinx_clock_gating.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc # Adders degrade ibex setup repair export ADDER_MAP_FILE := diff --git a/flow/designs/ihp-sg13g2/jpeg/config.mk b/flow/designs/ihp-sg13g2/jpeg/config.mk index e9a0fd1083..79fe5ed4a4 100644 --- a/flow/designs/ihp-sg13g2/jpeg/config.mk +++ b/flow/designs/ihp-sg13g2/jpeg/config.mk @@ -2,9 +2,9 @@ export DESIGN_NICKNAME = jpeg export DESIGN_NAME = jpeg_encoder export PLATFORM = ihp-sg13g2 -export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v)) -export VERILOG_INCLUDE_DIRS = ./designs/src/$(DESIGN_NICKNAME)/include -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) +export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/include +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export CORE_UTILIZATION = 55 export PLACE_DENSITY_LB_ADDON = 0.20 diff --git a/flow/designs/ihp-sg13g2/riscv32i/config.mk b/flow/designs/ihp-sg13g2/riscv32i/config.mk index 47593d42ff..43bbc9f064 100644 --- a/flow/designs/ihp-sg13g2/riscv32i/config.mk +++ b/flow/designs/ihp-sg13g2/riscv32i/config.mk @@ -2,8 +2,8 @@ export DESIGN_NICKNAME = riscv32i export DESIGN_NAME = riscv export PLATFORM = ihp-sg13g2 -export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v)) -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export USE_FILL 1 diff --git a/flow/designs/ihp-sg13g2/riscv32i/metadata-base-ok.json b/flow/designs/ihp-sg13g2/riscv32i/metadata-base-ok.json index 2ee3018c6d..567c675914 100644 --- a/flow/designs/ihp-sg13g2/riscv32i/metadata-base-ok.json +++ b/flow/designs/ihp-sg13g2/riscv32i/metadata-base-ok.json @@ -3,164 +3,174 @@ "constraints__clocks__details": [ "clk: 10.0000" ], - "cts__clock__skew__hold": 0.167414, - "cts__clock__skew__setup": 0.167414, - "cts__cpu__total": 23.18, + "cts__clock__skew__hold": 0.204393, + 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"v2.0-16787-gcd519bb5e", "run__flow__platform": "ihp-sg13g2", "run__flow__platform__capacitance_units": "1pF", "run__flow__platform__current_units": "1uA", @@ -316,14 +343,14 @@ "run__flow__platform__resistance_units": "1kohm", "run__flow__platform__time_units": "1ns", "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "53863581bcebf441b313abb65c15059fd79752b8", - "run__flow__scripts_commit": "53863581bcebf441b313abb65c15059fd79752b8", - "run__flow__uuid": "b4b7ea9a-c028-4d9b-a9f9-83e5b3895c64", + "run__flow__platform_commit": "N/A", + "run__flow__scripts_commit": "not a git repo", + "run__flow__uuid": "974b9e27-10ad-4879-ac78-536379f03117", "run__flow__variant": "base", - "synth__cpu__total": 22.19, + "synth__cpu__total": 35.13, "synth__design__instance__area__stdcell": 137047.3398, "synth__design__instance__count__stdcell": 8570.0, - "synth__mem__peak": 66520.0, - "synth__runtime__total": "0:22.33", - "total_time": "0:15:07.100000" + "synth__mem__peak": 60160.0, + "synth__runtime__total": "0:35.31", + "total_time": "0:05:03.220000" } \ No newline at end of file diff --git a/flow/designs/ihp-sg13g2/riscv32i/rules-base.json b/flow/designs/ihp-sg13g2/riscv32i/rules-base.json index eebe2c8db0..bad6e72d88 100644 --- a/flow/designs/ihp-sg13g2/riscv32i/rules-base.json +++ b/flow/designs/ihp-sg13g2/riscv32i/rules-base.json @@ -27,8 +27,12 @@ "value": 504, "compare": "<=" }, + "globalroute__antenna_diodes_count": { + "value": 779, + "compare": "<=" + }, "detailedroute__route__wirelength": { - "value": 820447, + "value": 819634, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -36,7 +40,7 @@ "compare": "<=" }, "detailedroute__antenna__violating__nets": { - "value": 30, + "value": 46, "compare": "<=" }, "finish__timing__setup__ws": { diff --git a/flow/designs/ihp-sg13g2/spi/config.mk b/flow/designs/ihp-sg13g2/spi/config.mk index 995e7e0a47..d791fbec23 100644 --- a/flow/designs/ihp-sg13g2/spi/config.mk +++ b/flow/designs/ihp-sg13g2/spi/config.mk @@ -1,8 +1,8 @@ export DESIGN_NAME = spi export PLATFORM = ihp-sg13g2 -export VERILOG_FILES = ./designs/src/$(DESIGN_NICKNAME)/spi.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/spi.v +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export USE_FILL = 1 diff --git a/flow/designs/intel16/gcd/config.mk b/flow/designs/intel16/gcd/config.mk index bb23ac570f..6d857dfbd6 100644 --- a/flow/designs/intel16/gcd/config.mk +++ b/flow/designs/intel16/gcd/config.mk @@ -1,8 +1,8 @@ export DESIGN_NAME = gcd export PLATFORM = intel16 -export VERILOG_FILES = ./designs/src/$(DESIGN_NAME)/gcd.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/gcd.v +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc export ABC_AREA = 1 # Adders degrade GCD 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"run__flow__platform__current_units": "1mA", @@ -305,13 +301,13 @@ "run__flow__platform__time_units": "1ps", "run__flow__platform__voltage_units": "1v", "run__flow__platform_commit": "N/A", - "run__flow__scripts_commit": "dcb6ca0773163b3ff4f04a9a88c8df5f2a1860f4", - "run__flow__uuid": "d8cce0f8-6782-4ca4-88de-ad3118b7ef5a", + "run__flow__scripts_commit": "667e920003c11365066311f2823f79ea4f1ef964", + "run__flow__uuid": "62300412-3533-4a1b-ab7b-4580152bdf90", "run__flow__variant": "base", - "synth__cpu__total": 2.34, + "synth__cpu__total": 2.26, "synth__design__instance__area__stdcell": 166.27032, "synth__design__instance__count__stdcell": 431.0, - "synth__mem__peak": 95488.0, - "synth__runtime__total": "0:06.86", - "total_time": "0:01:00.290000" + "synth__mem__peak": 96000.0, + "synth__runtime__total": "0:05.36", + "total_time": "0:00:56.150000" } \ No newline at end of file diff --git a/flow/designs/intel16/gcd/rules-base.json b/flow/designs/intel16/gcd/rules-base.json index e42eaf2840..1fdd7a9d40 100644 --- a/flow/designs/intel16/gcd/rules-base.json +++ b/flow/designs/intel16/gcd/rules-base.json @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 2564, + "value": 3020, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -52,7 +52,7 @@ "compare": ">=" }, "finish__design__instance__area": { - "value": 273, + "value": 360, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { diff --git a/flow/designs/intel22/jpeg/config.mk b/flow/designs/intel22/jpeg/config.mk index 3ca6ed0df8..246f63bb3f 100644 --- a/flow/designs/intel22/jpeg/config.mk +++ b/flow/designs/intel22/jpeg/config.mk @@ -6,7 +6,7 @@ export DESIGN_NAME = jpeg_encoder export PLATFORM = intel22 export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) -export VERILOG_INCLUDE_DIRS = ./designs/src/$(DESIGN_NICKNAME)/include +export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/include export SDC_FILE = $(DESIGN_DIR)/constraint.sdc export CORE_UTILIZATION = 30 diff --git a/flow/designs/nangate45/aes/config.mk b/flow/designs/nangate45/aes/config.mk index a797e9ff36..f653445292 100644 --- a/flow/designs/nangate45/aes/config.mk +++ b/flow/designs/nangate45/aes/config.mk @@ -2,10 +2,10 @@ export DESIGN_NICKNAME = aes export DESIGN_NAME = aes_cipher_top export PLATFORM = nangate45 -export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v)) -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc -export FLOORPLAN_DEF = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/aes_ng45_fp.def +export FLOORPLAN_DEF = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/aes_ng45_fp.def export PLACE_DENSITY_LB_ADDON = 0.20 export TNS_END_PERCENT = 100 diff --git a/flow/designs/nangate45/ariane133/config.mk b/flow/designs/nangate45/ariane133/config.mk index d440d5f4f2..6790881b88 100644 --- a/flow/designs/nangate45/ariane133/config.mk +++ b/flow/designs/nangate45/ariane133/config.mk @@ -10,10 +10,10 @@ export RTLMP_MIN_INST = 5000 export RTLMP_MAX_MACRO = 16 export RTLMP_MIN_MACRO = 4 -export VERILOG_FILES = ./designs/src/$(DESIGN_NICKNAME)/ariane.sv2v.v \ - ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/macros.v +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ariane.sv2v.v \ + $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/macros.v -export SDC_FILE = ./designs/$(PLATFORM)/ariane133/ariane.sdc +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/ariane133/ariane.sdc export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/fakeram45_256x16.lef export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/fakeram45_256x16.lib diff --git a/flow/designs/nangate45/ariane136/config.mk b/flow/designs/nangate45/ariane136/config.mk index 6fdc44d170..2a72f8effb 100644 --- a/flow/designs/nangate45/ariane136/config.mk +++ b/flow/designs/nangate45/ariane136/config.mk @@ -11,10 +11,10 @@ export RTLMP_MAX_MACRO = 16 export RTLMP_MIN_MACRO = 4 export RTLMP_SIGNATURE_NET_THRESHOLD = 30 -export VERILOG_FILES = ./designs/src/$(DESIGN_NICKNAME)/ariane.sv2v.v \ - ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/macros.v +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ariane.sv2v.v \ + $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/macros.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/fakeram45_256x16.lef @@ -28,3 +28,4 @@ export PLACE_PINS_ARGS = -exclude left:0-500 -exclude left:1000-1500: -exclude r export MACRO_PLACE_HALO = 10 10 export MACRO_PLACE_CHANNEL = 20 20 export TNS_END_PERCENT = 100 +export PLACE_DENSITY = 0.35 diff --git a/flow/designs/nangate45/ariane136/metadata-base-ok.json b/flow/designs/nangate45/ariane136/metadata-base-ok.json index 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"placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 2, - "placeopt__timing__drv__max_slew_limit": -0.248842, + "placeopt__timing__drv__max_slew": 0, + "placeopt__timing__drv__max_slew_limit": 0.353682, "placeopt__timing__drv__setup_violation_count": 0, "placeopt__timing__setup__tns": 0, - "placeopt__timing__setup__ws": 1.12611, + "placeopt__timing__setup__ws": 1.10919, "run__flow__design": "ariane136", - "run__flow__generate_date": "2024-10-22 10:42", + "run__flow__generate_date": "2024-11-26 16:46", "run__flow__metrics_version": "Metrics_2.1.2", "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-16688-g86a2cb529", + "run__flow__openroad_version": "v2.0-17322-g75f345819", "run__flow__platform": "nangate45", "run__flow__platform__capacitance_units": "1fF", "run__flow__platform__current_units": "1mA", @@ -318,14 +377,14 @@ "run__flow__platform__resistance_units": "1kohm", "run__flow__platform__time_units": "1ns", "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "N/A", - "run__flow__scripts_commit": "not a git repo", - "run__flow__uuid": "32bd9e0f-99a2-45a8-9eaa-12f6fa782317", + "run__flow__platform_commit": "16627131686649bdc0c8ea3bda72c7bdc1544928", + "run__flow__scripts_commit": "16627131686649bdc0c8ea3bda72c7bdc1544928", + "run__flow__uuid": "b407c0e5-fa3b-4ec3-9a5c-898ef6e3b110", "run__flow__variant": "base", - "synth__cpu__total": 920.11, - "synth__design__instance__area__stdcell": 745383.072, - "synth__design__instance__count__stdcell": 171230.0, - "synth__mem__peak": 1070080.0, - "synth__runtime__total": "15:25.22", - "total_time": "2:45:39.730000" + "synth__cpu__total": 860.17, + "synth__design__instance__area__stdcell": 745785.53, + "synth__design__instance__count__stdcell": 171502.0, + "synth__mem__peak": 786004.0, + "synth__runtime__total": "14:24.54", + "total_time": "2:18:42.510000" } \ No newline at end of file diff --git a/flow/designs/nangate45/ariane136/rules-base.json b/flow/designs/nangate45/ariane136/rules-base.json index c4403390a0..2835091759 100644 --- a/flow/designs/nangate45/ariane136/rules-base.json +++ b/flow/designs/nangate45/ariane136/rules-base.json @@ -60,7 +60,7 @@ "compare": "<=" }, "finish__timing__drv__hold_violation_count": { - "value": 1369, + "value": 259, "compare": "<=" }, "finish__timing__wns_percent_delay": { diff --git a/flow/designs/nangate45/black_parrot/config.mk b/flow/designs/nangate45/black_parrot/config.mk index be943c4c9d..16e60bd058 100644 --- a/flow/designs/nangate45/black_parrot/config.mk +++ b/flow/designs/nangate45/black_parrot/config.mk @@ -10,12 +10,12 @@ export RTLMP_MIN_INST = 5000 export RTLMP_MAX_MACRO = 12 export RTLMP_MIN_MACRO = 4 -export VERILOG_FILES = ./designs/src/$(DESIGN_NAME)/pickled.v \ - ./designs/$(PLATFORM)/$(DESIGN_NAME)/macros.v +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/pickled.v \ + $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/macros.v export ABC_AREA = 1 -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/fakeram45_512x64.lef \ $(PLATFORM_DIR)/lef/fakeram45_256x95.lef \ diff --git a/flow/designs/nangate45/black_parrot/metadata-base-ok.json b/flow/designs/nangate45/black_parrot/metadata-base-ok.json index 1f1675c53c..2ae3d9724f 100644 --- a/flow/designs/nangate45/black_parrot/metadata-base-ok.json +++ b/flow/designs/nangate45/black_parrot/metadata-base-ok.json @@ -3,173 +3,174 @@ "constraints__clocks__details": [ "CLK: 6.0000" ], - "cts__clock__skew__hold": 0.116723, - "cts__clock__skew__setup": 0.116723, - "cts__cpu__total": 339.25, + "cts__clock__skew__hold": 0.10935, + "cts__clock__skew__setup": 0.10935, + "cts__cpu__total": 279.41, "cts__design__core__area": 1699760.0, "cts__design__die__area": 1755000.0, - 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"placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.378785, + "placeopt__timing__drv__max_slew_limit": 0.379057, "placeopt__timing__drv__setup_violation_count": 1, - "placeopt__timing__setup__tns": -0.739802, - "placeopt__timing__setup__ws": -0.739802, + "placeopt__timing__setup__tns": -0.733073, + "placeopt__timing__setup__ws": -0.733073, "run__flow__design": "bp", - "run__flow__generate_date": "2024-10-22 09:14", + "run__flow__generate_date": "2024-08-24 22:19", "run__flow__metrics_version": "Metrics_2.1.2", "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-16688-g86a2cb529", + "run__flow__openroad_version": "v2.0-15311-g42ba30d73", "run__flow__platform": "nangate45", "run__flow__platform__capacitance_units": "1fF", "run__flow__platform__current_units": "1mA", @@ -326,14 +323,14 @@ "run__flow__platform__resistance_units": "1kohm", "run__flow__platform__time_units": "1ns", "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "N/A", - "run__flow__scripts_commit": "not a git repo", - "run__flow__uuid": "c361e755-aea5-4b9e-b8ab-68af917b731a", + "run__flow__platform_commit": "20576ce92a18c95900f45bbf8aff4385defe5527", + "run__flow__scripts_commit": "20576ce92a18c95900f45bbf8aff4385defe5527", + "run__flow__uuid": "bdcea526-879b-4fbf-a6be-69719910d012", "run__flow__variant": "base", - "synth__cpu__total": 418.06, + "synth__cpu__total": 359.91, "synth__design__instance__area__stdcell": 763869.274, "synth__design__instance__count__stdcell": 306819.0, - "synth__mem__peak": 809344.0, - "synth__runtime__total": "7:02.88", - "total_time": "1:19:15.120000" + "synth__mem__peak": 812780.0, + "synth__runtime__total": "6:03.99", + "total_time": "1:23:50.270000" } \ No newline at end of file diff --git a/flow/designs/nangate45/black_parrot/rules-base.json b/flow/designs/nangate45/black_parrot/rules-base.json index 9594b32e5b..da8cb9c170 100644 --- a/flow/designs/nangate45/black_parrot/rules-base.json +++ b/flow/designs/nangate45/black_parrot/rules-base.json @@ -27,10 +27,6 @@ "value": 30123, "compare": "<=" }, - "globalroute__antenna_diodes_count": { - "value": 0, - "compare": "<=" - }, "detailedroute__route__wirelength": { "value": 9419931, "compare": "<=" @@ -43,12 +39,8 @@ "value": 0, "compare": "<=" }, - "detailedroute__antenna_diodes_count": { - "value": 5, - "compare": "<=" - }, "finish__timing__setup__ws": { - "value": -7896.73, + "value": -0.88, "compare": ">=" }, "finish__design__instance__area": { @@ -64,7 +56,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -129.89, + "value": -19.62, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/nangate45/bp_be_top/config.mk b/flow/designs/nangate45/bp_be_top/config.mk index 08f2628621..6d21176d60 100644 --- a/flow/designs/nangate45/bp_be_top/config.mk +++ b/flow/designs/nangate45/bp_be_top/config.mk @@ -10,9 +10,9 @@ export RTLMP_MIN_INST = 5000 export RTLMP_MAX_MACRO = 12 export RTLMP_MIN_MACRO = 4 -export VERILOG_FILES = ./designs/src/$(DESIGN_NAME)/pickled.v \ - ./designs/$(PLATFORM)/$(DESIGN_NAME)/macros.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/pickled.v \ + $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/macros.v +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/fakeram45_512x64.lef \ $(PLATFORM_DIR)/lef/fakeram45_64x15.lef \ diff --git a/flow/designs/nangate45/bp_be_top/metadata-base-ok.json b/flow/designs/nangate45/bp_be_top/metadata-base-ok.json index bf34cdcc7e..518b1b7c86 100644 --- a/flow/designs/nangate45/bp_be_top/metadata-base-ok.json +++ b/flow/designs/nangate45/bp_be_top/metadata-base-ok.json @@ -5,7 +5,7 @@ ], "cts__clock__skew__hold": 0.124765, "cts__clock__skew__setup": 0.124765, - "cts__cpu__total": 364.99, + "cts__cpu__total": 361.09, "cts__design__core__area": 528365, "cts__design__die__area": 560000, "cts__design__instance__area": 267430, @@ -31,7 +31,7 @@ "cts__power__switching__total": 0.0344243, "cts__power__total": 0.137984, "cts__route__wirelength__estimated": 2528980.0, - "cts__runtime__total": "6:05.84", + "cts__runtime__total": "6:01.87", "cts__timing__drv__hold_violation_count": 0, "cts__timing__drv__max_cap": 0, "cts__timing__drv__max_cap_limit": 0.00193814, @@ -44,7 +44,7 @@ "cts__timing__setup__ws": -0.268139, "design__io__hpwl": 2277424288, "design__violations": 0, - "detailedplace__cpu__total": 75.5, + "detailedplace__cpu__total": 71.4, "detailedplace__design__core__area": 528365, "detailedplace__design__die__area": 560000, "detailedplace__design__instance__area": 264037, @@ -62,13 +62,13 @@ "detailedplace__design__violations": 0, "detailedplace__flow__errors__count": 0, "detailedplace__flow__warnings__count": 0, - "detailedplace__mem__peak": 651924.0, + "detailedplace__mem__peak": 651688.0, "detailedplace__power__internal__total": 0.0863632, "detailedplace__power__leakage__total": 0.00973354, "detailedplace__power__switching__total": 0.0258172, "detailedplace__power__total": 0.121914, "detailedplace__route__wirelength__estimated": 2517150.0, - "detailedplace__runtime__total": "1:16.02", + "detailedplace__runtime__total": "1:11.92", "detailedplace__timing__drv__hold_violation_count": 0, "detailedplace__timing__drv__max_cap": 0, "detailedplace__timing__drv__max_cap_limit": 0.00155115, @@ -85,41 +85,43 @@ "detailedroute__flow__errors__count": 0, "detailedroute__flow__warnings__count": 1, "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 23241, - "detailedroute__route__drc_errors__iter:10": 415, - "detailedroute__route__drc_errors__iter:11": 165, - "detailedroute__route__drc_errors__iter:12": 18, - "detailedroute__route__drc_errors__iter:13": 0, - "detailedroute__route__drc_errors__iter:2": 4866, - "detailedroute__route__drc_errors__iter:3": 3113, - "detailedroute__route__drc_errors__iter:4": 1001, - "detailedroute__route__drc_errors__iter:5": 748, - "detailedroute__route__drc_errors__iter:6": 641, - "detailedroute__route__drc_errors__iter:7": 591, - "detailedroute__route__drc_errors__iter:8": 562, - "detailedroute__route__drc_errors__iter:9": 512, + "detailedroute__route__drc_errors__iter:1": 22768, + "detailedroute__route__drc_errors__iter:10": 424, + "detailedroute__route__drc_errors__iter:11": 185, + "detailedroute__route__drc_errors__iter:12": 24, + "detailedroute__route__drc_errors__iter:13": 1, + "detailedroute__route__drc_errors__iter:14": 0, + "detailedroute__route__drc_errors__iter:2": 4718, + "detailedroute__route__drc_errors__iter:3": 3266, + "detailedroute__route__drc_errors__iter:4": 1137, + "detailedroute__route__drc_errors__iter:5": 844, + "detailedroute__route__drc_errors__iter:6": 732, + "detailedroute__route__drc_errors__iter:7": 639, + "detailedroute__route__drc_errors__iter:8": 602, + "detailedroute__route__drc_errors__iter:9": 515, "detailedroute__route__net": 68477, "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 547861, + "detailedroute__route__vias": 547685, "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 547861, - "detailedroute__route__wirelength": 3085456, - "detailedroute__route__wirelength__iter:1": 3099329, - "detailedroute__route__wirelength__iter:10": 3085460, - "detailedroute__route__wirelength__iter:11": 3085469, - "detailedroute__route__wirelength__iter:12": 3085474, - "detailedroute__route__wirelength__iter:13": 3085456, - "detailedroute__route__wirelength__iter:2": 3087240, - "detailedroute__route__wirelength__iter:3": 3084044, - "detailedroute__route__wirelength__iter:4": 3084850, - "detailedroute__route__wirelength__iter:5": 3085027, - "detailedroute__route__wirelength__iter:6": 3085175, - "detailedroute__route__wirelength__iter:7": 3085256, - "detailedroute__route__wirelength__iter:8": 3085278, - "detailedroute__route__wirelength__iter:9": 3085376, - "finish__clock__skew__hold": 0.499121, - "finish__clock__skew__setup": 0.499121, - "finish__cpu__total": 187.57, + "detailedroute__route__vias__singlecut": 547685, + "detailedroute__route__wirelength": 3084898, + "detailedroute__route__wirelength__iter:1": 3096871, + "detailedroute__route__wirelength__iter:10": 3084662, + "detailedroute__route__wirelength__iter:11": 3084812, + "detailedroute__route__wirelength__iter:12": 3084913, + "detailedroute__route__wirelength__iter:13": 3084913, + "detailedroute__route__wirelength__iter:14": 3084898, + "detailedroute__route__wirelength__iter:2": 3086422, + "detailedroute__route__wirelength__iter:3": 3083525, + "detailedroute__route__wirelength__iter:4": 3084199, + "detailedroute__route__wirelength__iter:5": 3084517, + "detailedroute__route__wirelength__iter:6": 3084626, + "detailedroute__route__wirelength__iter:7": 3084600, + "detailedroute__route__wirelength__iter:8": 3084592, + "detailedroute__route__wirelength__iter:9": 3084606, + "finish__clock__skew__hold": 0.513013, + "finish__clock__skew__setup": 0.513013, + "finish__cpu__total": 176.3, "finish__design__core__area": 528365, "finish__design__die__area": 560000, "finish__design__instance__area": 269035, @@ -142,35 +144,35 @@ "finish__design__instance__utilization": 0.509184, "finish__design__instance__utilization__stdcell": 0.325398, "finish__design__io": 3029, - "finish__design_powergrid__drop__average__net:VDD__corner:default": 1.08972, - "finish__design_powergrid__drop__average__net:VSS__corner:default": 0.010291, - "finish__design_powergrid__drop__worst__net:VDD__corner:default": 0.0217044, - "finish__design_powergrid__drop__worst__net:VSS__corner:default": 0.0253029, - "finish__design_powergrid__voltage__worst__net:VDD__corner:default": 1.0783, - "finish__design_powergrid__voltage__worst__net:VSS__corner:default": 0.0253029, + "finish__design_powergrid__drop__average__net:VDD__corner:default": 1.08798, + "finish__design_powergrid__drop__average__net:VSS__corner:default": 0.0118994, + "finish__design_powergrid__drop__worst__net:VDD__corner:default": 0.0232615, + "finish__design_powergrid__drop__worst__net:VSS__corner:default": 0.0274227, + "finish__design_powergrid__voltage__worst__net:VDD__corner:default": 1.07674, + "finish__design_powergrid__voltage__worst__net:VSS__corner:default": 0.0274227, "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 164416, - "finish__mem__peak": 1380012.0, - "finish__power__internal__total": 0.0942175, + "finish__flow__warnings__count": 1, + "finish__mem__peak": 1566548.0, + "finish__power__internal__total": 0.0944396, "finish__power__leakage__total": 0.0098665, - "finish__power__switching__total": 0.0273215, - "finish__power__total": 0.131406, - "finish__runtime__total": "3:09.59", - "finish__timing__drv__hold_violation_count": 1085, - "finish__timing__drv__max_cap": 25, - "finish__timing__drv__max_cap_limit": -0.671071, + "finish__power__switching__total": 0.04166, + "finish__power__total": 0.145966, + "finish__runtime__total": "2:58.31", + "finish__timing__drv__hold_violation_count": 540, + "finish__timing__drv__max_cap": 206, + "finish__timing__drv__max_cap_limit": -0.784523, "finish__timing__drv__max_fanout": 0, "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 6, - "finish__timing__drv__max_slew_limit": -468.076, - "finish__timing__drv__setup_violation_count": 358, - "finish__timing__setup__tns": -134933, - "finish__timing__setup__ws": -592.166, - "finish__timing__wns_percent_delay": -99.477286, - "finish_merge__cpu__total": 9.13, - "finish_merge__mem__peak": 928012.0, - "finish_merge__runtime__total": "0:09.88", - "floorplan__cpu__total": 35.06, + "finish__timing__drv__max_slew": 16, + "finish__timing__drv__max_slew_limit": -0.606029, + "finish__timing__drv__setup_violation_count": 130, + "finish__timing__setup__tns": -89.279, + "finish__timing__setup__ws": -0.863575, + "finish__timing__wns_percent_delay": -30.157843, + "finish_merge__cpu__total": 7.96, + "finish_merge__mem__peak": 928180.0, + "finish_merge__runtime__total": "0:08.61", + "floorplan__cpu__total": 31.09, "floorplan__design__core__area": 528365, "floorplan__design__die__area": 560000, "floorplan__design__instance__area": 236465, @@ -186,32 +188,32 @@ "floorplan__design__io": 3029, "floorplan__flow__errors__count": 0, "floorplan__flow__warnings__count": 1, - "floorplan__mem__peak": 353124.0, + "floorplan__mem__peak": 353348.0, "floorplan__power__internal__total": 0.0776664, "floorplan__power__leakage__total": 0.00862544, "floorplan__power__switching__total": 0.00839269, "floorplan__power__total": 0.0946846, - "floorplan__runtime__total": "0:35.50", + "floorplan__runtime__total": "0:31.28", "floorplan__timing__setup__tns": 0, "floorplan__timing__setup__ws": 0.02525, - "floorplan_io__cpu__total": 1.07, - "floorplan_io__mem__peak": 216116.0, - "floorplan_io__runtime__total": "0:01.23", - "floorplan_macro__cpu__total": 225.53, - "floorplan_macro__mem__peak": 357080.0, - "floorplan_macro__runtime__total": "0:19.89", - "floorplan_pdn__cpu__total": 2.74, - "floorplan_pdn__mem__peak": 256748.0, - "floorplan_pdn__runtime__total": "0:02.95", - "floorplan_tap__cpu__total": 1.03, - "floorplan_tap__mem__peak": 187900.0, - "floorplan_tap__runtime__total": "0:01.15", - "floorplan_tdms__cpu__total": 0.16, - "floorplan_tdms__mem__peak": 100020.0, - "floorplan_tdms__runtime__total": "0:00.28", + "floorplan_io__cpu__total": 1.05, + "floorplan_io__mem__peak": 216368.0, + "floorplan_io__runtime__total": "0:01.22", + "floorplan_macro__cpu__total": 221.36, + "floorplan_macro__mem__peak": 356936.0, + "floorplan_macro__runtime__total": "0:18.89", + "floorplan_pdn__cpu__total": 2.57, + "floorplan_pdn__mem__peak": 256552.0, + "floorplan_pdn__runtime__total": "0:02.73", + "floorplan_tap__cpu__total": 1.04, + "floorplan_tap__mem__peak": 188104.0, + "floorplan_tap__runtime__total": "0:01.17", + "floorplan_tdms__cpu__total": 0.17, + "floorplan_tdms__mem__peak": 99644.0, + "floorplan_tdms__runtime__total": "0:00.25", "flow__errors__count": 0, "flow__warnings__count": 0, - "globalplace__cpu__total": 1705.21, + "globalplace__cpu__total": 1676.78, "globalplace__design__core__area": 528365, "globalplace__design__die__area": 560000, "globalplace__design__instance__area": 237397, @@ -225,26 +227,26 @@ "globalplace__design__io": 3029, "globalplace__flow__errors__count": 0, "globalplace__flow__warnings__count": 0, - "globalplace__mem__peak": 935752.0, + "globalplace__mem__peak": 935336.0, "globalplace__power__internal__total": 0.0781424, "globalplace__power__leakage__total": 0.00862544, "globalplace__power__switching__total": 0.0193044, "globalplace__power__total": 0.106072, - "globalplace__runtime__total": "5:41.62", + "globalplace__runtime__total": "5:30.33", "globalplace__timing__setup__tns": -903.949, "globalplace__timing__setup__ws": -1.27604, - "globalplace_io__cpu__total": 2.07, - "globalplace_io__mem__peak": 229032.0, - "globalplace_io__runtime__total": "0:02.27", - "globalplace_skip_io__cpu__total": 611.33, - "globalplace_skip_io__mem__peak": 348304.0, - "globalplace_skip_io__runtime__total": "0:28.29", + "globalplace_io__cpu__total": 1.71, + "globalplace_io__mem__peak": 228312.0, + "globalplace_io__runtime__total": "0:01.88", + "globalplace_skip_io__cpu__total": 601.2, + "globalplace_skip_io__mem__peak": 347312.0, + "globalplace_skip_io__runtime__total": "0:25.44", "globalroute__antenna__violating__nets": 0, "globalroute__antenna__violating__pins": 0, "globalroute__antenna_diodes_count": 0, "globalroute__clock__skew__hold": 0.425906, "globalroute__clock__skew__setup": 0.425906, - "globalroute__cpu__total": 1010.55, + "globalroute__cpu__total": 964.66, "globalroute__design__core__area": 528365, "globalroute__design__die__area": 560000, "globalroute__design__instance__area": 269035, @@ -264,13 +266,13 @@ "globalroute__design__violations": 0, "globalroute__flow__errors__count": 0, "globalroute__flow__warnings__count": 2, - "globalroute__mem__peak": 1708672.0, + "globalroute__mem__peak": 1706368.0, "globalroute__power__internal__total": 0.0942858, "globalroute__power__leakage__total": 0.0098665, "globalroute__power__switching__total": 0.0377993, "globalroute__power__total": 0.141952, "globalroute__route__wirelength__estimated": 2550000.0, - "globalroute__runtime__total": "15:41.41", + "globalroute__runtime__total": "14:59.38", "globalroute__timing__clock__slack": -0.682, "globalroute__timing__drv__hold_violation_count": 21, "globalroute__timing__drv__max_cap": 110, @@ -282,7 +284,7 @@ "globalroute__timing__drv__setup_violation_count": 111, "globalroute__timing__setup__tns": -68.4425, "globalroute__timing__setup__ws": -0.681791, - "placeopt__cpu__total": 73.23, + "placeopt__cpu__total": 69.89, "placeopt__design__core__area": 528365, "placeopt__design__die__area": 560000, "placeopt__design__instance__area": 264037, @@ -296,12 +298,12 @@ "placeopt__design__io": 3029, "placeopt__flow__errors__count": 0, "placeopt__flow__warnings__count": 0, - "placeopt__mem__peak": 533484.0, + "placeopt__mem__peak": 533100.0, "placeopt__power__internal__total": 0.0863651, "placeopt__power__leakage__total": 0.00973354, "placeopt__power__switching__total": 0.0259016, "placeopt__power__total": 0.122, - "placeopt__runtime__total": "1:13.73", + "placeopt__runtime__total": "1:10.42", "placeopt__timing__drv__floating__nets": 0, "placeopt__timing__drv__floating__pins": 0, "placeopt__timing__drv__hold_violation_count": 0, @@ -315,10 +317,10 @@ "placeopt__timing__setup__tns": -9.54989, "placeopt__timing__setup__ws": -0.167034, "run__flow__design": "bp_be", - "run__flow__generate_date": "2024-10-22 08:13", + "run__flow__generate_date": "2024-10-15 22:51", "run__flow__metrics_version": "Metrics_2.1.2", "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-16688-g86a2cb529", + "run__flow__openroad_version": "v2.0-16535-g199588e84", "run__flow__platform": "nangate45", "run__flow__platform__capacitance_units": "1fF", "run__flow__platform__current_units": "1mA", @@ -329,12 +331,12 @@ "run__flow__platform__voltage_units": "1v", "run__flow__platform_commit": "N/A", "run__flow__scripts_commit": "not a git repo", - "run__flow__uuid": "79658110-5c29-45b5-9a61-0fc307a6777b", + "run__flow__uuid": "a767acaf-69f2-477d-868f-54dced30b74f", "run__flow__variant": "base", - "synth__cpu__total": 146.59, + "synth__cpu__total": 123.65, "synth__design__instance__area__stdcell": 236465.222, "synth__design__instance__count__stdcell": 51393.0, - "synth__mem__peak": 214608.0, - "synth__runtime__total": "2:27.50", - "total_time": "0:37:17.150000" + "synth__mem__peak": 212008.0, + "synth__runtime__total": "2:04.51", + "total_time": "0:35:28.210000" } \ No newline at end of file diff --git a/flow/designs/nangate45/bp_be_top/rules-base.json b/flow/designs/nangate45/bp_be_top/rules-base.json index 6aba8daa41..786ae3b754 100644 --- a/flow/designs/nangate45/bp_be_top/rules-base.json +++ b/flow/designs/nangate45/bp_be_top/rules-base.json @@ -48,7 +48,7 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -592.29, + "value": -0.99, "compare": ">=" }, "finish__design__instance__area": { @@ -60,11 +60,11 @@ "compare": "<=" }, "finish__timing__drv__hold_violation_count": { - "value": 1456, + "value": 775, "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -129.37, + "value": -46.18, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/nangate45/bp_fe_top/config.mk b/flow/designs/nangate45/bp_fe_top/config.mk index 8a5b3a516c..aa6cc60fe8 100644 --- a/flow/designs/nangate45/bp_fe_top/config.mk +++ b/flow/designs/nangate45/bp_fe_top/config.mk @@ -10,9 +10,9 @@ export RTLMP_MIN_INST = 5000 export RTLMP_MAX_MACRO = 12 export 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"placeopt__timing__setup__ws": -0.163713, + "placeopt__timing__drv__max_slew_limit": 0.395534, + "placeopt__timing__drv__setup_violation_count": 42, + "placeopt__timing__setup__tns": -1.81031, + "placeopt__timing__setup__ws": -0.124353, "run__flow__design": "bp_fe", - "run__flow__generate_date": "2024-10-02 09:02", + "run__flow__generate_date": "2024-11-27 01:17", "run__flow__metrics_version": "Metrics_2.1.2", "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-16219-g56c3c86ba", + "run__flow__openroad_version": "v2.0-17353-g10a5df25b", "run__flow__platform": "nangate45", "run__flow__platform__capacitance_units": "1fF", "run__flow__platform__current_units": "1mA", @@ -320,12 +389,12 @@ "run__flow__platform__voltage_units": "1v", "run__flow__platform_commit": "N/A", "run__flow__scripts_commit": "not a git repo", - "run__flow__uuid": "0de528d1-948f-41d1-978f-0d3d9763db53", + "run__flow__uuid": "1e5c415d-d16c-4631-8f18-24a8ed5b3d7a", "run__flow__variant": "base", - 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"finish__timing__wns_percent_delay": { diff --git a/flow/designs/nangate45/bp_multi_top/config.mk b/flow/designs/nangate45/bp_multi_top/config.mk index 59c9975a36..71ce929ee1 100644 --- a/flow/designs/nangate45/bp_multi_top/config.mk +++ b/flow/designs/nangate45/bp_multi_top/config.mk @@ -10,9 +10,9 @@ export RTLMP_MIN_INST = 5000 export RTLMP_MAX_MACRO = 12 export RTLMP_MIN_MACRO = 4 -export VERILOG_FILES = ./designs/src/$(DESIGN_NAME)/pickled.v \ - ./designs/$(PLATFORM)/$(DESIGN_NAME)/macros.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/pickled.v \ + $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/macros.v +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc export ABC_AREA = 1 export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/fakeram45_512x64.lef \ diff --git a/flow/designs/nangate45/bp_multi_top/metadata-base-ok.json b/flow/designs/nangate45/bp_multi_top/metadata-base-ok.json index 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"bp_multi", - "run__flow__generate_date": "2024-10-22 08:21", + "run__flow__generate_date": "2024-09-26 21:20", "run__flow__metrics_version": "Metrics_2.1.2", "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-16688-g86a2cb529", + "run__flow__openroad_version": "v2.0-15807-g036379d64", "run__flow__platform": "nangate45", "run__flow__platform__capacitance_units": "1fF", "run__flow__platform__current_units": "1mA", @@ -322,14 +314,14 @@ "run__flow__platform__resistance_units": "1kohm", "run__flow__platform__time_units": "1ns", "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "N/A", - "run__flow__scripts_commit": "not a git repo", - "run__flow__uuid": "ca9f6ce9-5204-4097-88b5-4844de448226", - "run__flow__variant": "base", - "synth__cpu__total": 235.98, + "run__flow__platform_commit": "d505a82b2c409ec7bd0449ee0cb737219c4c8f2b", + "run__flow__scripts_commit": "d505a82b2c409ec7bd0449ee0cb737219c4c8f2b", + "run__flow__uuid": "ae3654ab-272b-4138-b6ed-db38a72a220b", + "run__flow__variant": "odb_0925", + "synth__cpu__total": 220.65, "synth__design__instance__area__stdcell": 550926.128, "synth__design__instance__count__stdcell": 152650.0, - "synth__mem__peak": 500852.0, - "synth__runtime__total": "3:58.98", - "total_time": "0:41:50.780000" + "synth__mem__peak": 497232.0, + "synth__runtime__total": "4:21.51", + "total_time": "0:40:02.770000" } \ No newline at end of file diff --git a/flow/designs/nangate45/bp_multi_top/rules-base.json b/flow/designs/nangate45/bp_multi_top/rules-base.json index c54eae34fb..4aa4273f85 100644 --- a/flow/designs/nangate45/bp_multi_top/rules-base.json +++ b/flow/designs/nangate45/bp_multi_top/rules-base.json @@ -48,7 +48,7 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -591.5, + "value": -2.16, "compare": ">=" }, "finish__design__instance__area": { @@ -60,11 +60,11 @@ "compare": "<=" }, "finish__timing__drv__hold_violation_count": { - "value": 482, + "value": 100, "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -128.92, + "value": -41.94, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/nangate45/bp_quad/config.mk b/flow/designs/nangate45/bp_quad/config.mk index f55ffdd96f..4064f9bb17 100644 --- a/flow/designs/nangate45/bp_quad/config.mk +++ b/flow/designs/nangate45/bp_quad/config.mk @@ -10,10 +10,10 @@ export SYNTH_HIERARCHICAL = 1 #export RTLMP_MAX_MACRO = 16 #export RTLMP_MIN_MACRO = 4 -export VERILOG_FILES = ./designs/src/$(DESIGN_NICKNAME)/bsg_chip_block.sv2v.v \ - ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/macros.v +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/bsg_chip_block.sv2v.v \ + $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/macros.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/bsg_chip.sdc +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/bsg_chip.sdc export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/fakeram45_256x48.lef \ $(PLATFORM_DIR)/lef/fakeram45_32x32.lef \ diff --git a/flow/designs/nangate45/dynamic_node/config.mk b/flow/designs/nangate45/dynamic_node/config.mk index ac7805eea3..33365ed46c 100644 --- a/flow/designs/nangate45/dynamic_node/config.mk +++ b/flow/designs/nangate45/dynamic_node/config.mk @@ -2,8 +2,8 @@ export DESIGN_NICKNAME = dynamic_node export DESIGN_NAME = dynamic_node_top_wrap export PLATFORM = nangate45 -export VERILOG_FILES = ./designs/src/$(DESIGN_NICKNAME)/dynamic_node.pickle.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/dynamic_node.pickle.v +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export CORE_UTILIZATION = 40 diff --git a/flow/designs/nangate45/gcd/config.mk b/flow/designs/nangate45/gcd/config.mk index 536991d4d2..1b61b78af4 100644 --- a/flow/designs/nangate45/gcd/config.mk +++ b/flow/designs/nangate45/gcd/config.mk @@ -1,8 +1,8 @@ export DESIGN_NAME = gcd export PLATFORM = nangate45 -export VERILOG_FILES = ./designs/src/$(DESIGN_NAME)/gcd.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/gcd.v +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc export ABC_AREA = 1 # Adders degrade GCD diff --git a/flow/designs/nangate45/ibex/config.mk b/flow/designs/nangate45/ibex/config.mk index 4b4db1cfd5..8d6843f00e 100644 --- a/flow/designs/nangate45/ibex/config.mk +++ b/flow/designs/nangate45/ibex/config.mk @@ -4,48 +4,48 @@ export PLATFORM = nangate45 -export VERILOG_FILES = ./designs/src/$(DESIGN_NICKNAME)/ibex_alu.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_branch_predict.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_compressed_decoder.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_controller.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_core.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_counter.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_cs_registers.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_csr.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_decoder.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_dummy_instr.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_ex_block.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_fetch_fifo.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_icache.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_id_stage.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_if_stage.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_load_store_unit.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_multdiv_fast.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_multdiv_slow.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_pmp.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_prefetch_buffer.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_register_file_ff.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_register_file_fpga.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_register_file_latch.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_wb_stage.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_badbit_ram_1p.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_clock_gating.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_generic_clock_gating.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_generic_ram_1p.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_lfsr.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_ram_1p.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_28_22_dec.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_28_22_enc.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_39_32_dec.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_39_32_enc.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_72_64_dec.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_72_64_enc.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_xilinx_clock_gating.v - - - - -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_alu.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_branch_predict.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_compressed_decoder.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_controller.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_core.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_counter.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_cs_registers.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_csr.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_decoder.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_dummy_instr.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_ex_block.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_fetch_fifo.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_icache.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_id_stage.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_if_stage.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_load_store_unit.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_fast.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_slow.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_pmp.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_prefetch_buffer.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_ff.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_fpga.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_latch.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_wb_stage.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_badbit_ram_1p.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_clock_gating.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_generic_clock_gating.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_generic_ram_1p.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_lfsr.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_ram_1p.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_28_22_dec.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_28_22_enc.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_39_32_dec.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_39_32_enc.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_72_64_dec.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_72_64_enc.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_xilinx_clock_gating.v + + + + +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export CORE_UTILIZATION ?= 50 export PLACE_DENSITY_LB_ADDON = 0.20 diff --git a/flow/designs/nangate45/jpeg/config.mk b/flow/designs/nangate45/jpeg/config.mk index 55a99dd60d..ff8578ccd2 100644 --- a/flow/designs/nangate45/jpeg/config.mk +++ b/flow/designs/nangate45/jpeg/config.mk @@ -2,9 +2,9 @@ export DESIGN_NICKNAME = jpeg export DESIGN_NAME = jpeg_encoder export PLATFORM = nangate45 -export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v)) -export VERILOG_INCLUDE_DIRS = ./designs/src/$(DESIGN_NICKNAME)/include -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) +export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/include +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export ABC_AREA = 1 export CORE_UTILIZATION ?= 45 diff --git a/flow/designs/nangate45/jpeg/metadata-base-ok.json b/flow/designs/nangate45/jpeg/metadata-base-ok.json index 926e389b91..a92c915177 100644 --- a/flow/designs/nangate45/jpeg/metadata-base-ok.json +++ b/flow/designs/nangate45/jpeg/metadata-base-ok.json @@ -3,295 +3,366 @@ "constraints__clocks__details": [ "clk: 1.4000" ], - "cts__clock__skew__hold": 0.0293147, - "cts__clock__skew__setup": 0.0293147, - "cts__cpu__total": 509.97, + "cts__clock__skew__hold": 0.0252455, + "cts__clock__skew__setup": 0.0252455, + "cts__cpu__total": 624.64, "cts__design__core__area": 232329, "cts__design__die__area": 234866, - "cts__design__instance__area": 112994, + "cts__design__instance__area": 113934, + "cts__design__instance__area__cover": 0, "cts__design__instance__area__macros": 0, - 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"placeopt__timing__drv__max_fanout_limit": 0, "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.371872, - "placeopt__timing__drv__setup_violation_count": 556, - "placeopt__timing__setup__tns": -114.023, - "placeopt__timing__setup__ws": -0.454664, + "placeopt__timing__drv__max_slew_limit": 0.375408, + "placeopt__timing__drv__setup_violation_count": 553, + "placeopt__timing__setup__tns": -115.891, + "placeopt__timing__setup__ws": -0.4537, "run__flow__design": "jpeg", - "run__flow__generate_date": "2024-09-27 18:14", + "run__flow__generate_date": "2024-11-22 23:13", "run__flow__metrics_version": "Metrics_2.1.2", "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-16089-gd06039e7d", + "run__flow__openroad_version": "v2.0-17258-gc1904e24e", "run__flow__platform": "nangate45", "run__flow__platform__capacitance_units": "1fF", "run__flow__platform__current_units": "1mA", @@ -302,12 +373,12 @@ "run__flow__platform__voltage_units": "1v", "run__flow__platform_commit": "N/A", "run__flow__scripts_commit": "not a git repo", - "run__flow__uuid": "deb18144-61ea-47cd-b37f-28e67631c442", + "run__flow__uuid": "d6242a6c-8db3-468e-92d3-9357c1ef8dbf", "run__flow__variant": "base", - "synth__cpu__total": 123.49, + "synth__cpu__total": 131.13, "synth__design__instance__area__stdcell": 104819.96, "synth__design__instance__count__stdcell": 66988.0, - "synth__mem__peak": 726864.0, - "synth__runtime__total": "2:04.93", - "total_time": "0:26:30.130000" + "synth__mem__peak": 614604.0, + "synth__runtime__total": "2:12.69", + "total_time": "0:31:51.570000" } \ No newline at end of file diff --git a/flow/designs/nangate45/jpeg/rules-base.json b/flow/designs/nangate45/jpeg/rules-base.json index fbf378d2a6..233d1dadfd 100644 --- a/flow/designs/nangate45/jpeg/rules-base.json +++ b/flow/designs/nangate45/jpeg/rules-base.json @@ -48,7 +48,7 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.36, + "value": -0.44, "compare": ">=" }, "finish__design__instance__area": { diff --git a/flow/designs/nangate45/mempool_group/config.mk b/flow/designs/nangate45/mempool_group/config.mk index 4859cff4e6..50d4c1ee76 100644 --- a/flow/designs/nangate45/mempool_group/config.mk +++ b/flow/designs/nangate45/mempool_group/config.mk @@ -4,10 +4,10 @@ export PLATFORM = nangate45 export SYNTH_HIERARCHICAL = 1 -export TEMP_DESIGN_DIR = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME) -export VERILOG_FILES = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/$(DESIGN_NAME).v +export TEMP_DESIGN_DIR = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME) +export VERILOG_FILES = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/$(DESIGN_NAME).v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/$(DESIGN_NAME).sdc +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/$(DESIGN_NAME).sdc export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/fakeram45_256x32.lef \ $(PLATFORM_DIR)/lef/fakeram45_64x64.lef \ diff --git a/flow/designs/nangate45/swerv/config.mk b/flow/designs/nangate45/swerv/config.mk index 93210cf09f..6625aced49 100644 --- a/flow/designs/nangate45/swerv/config.mk +++ b/flow/designs/nangate45/swerv/config.mk @@ -1,8 +1,8 @@ export DESIGN_NAME = swerv export PLATFORM = nangate45 -export VERILOG_FILES = ./designs/src/$(DESIGN_NAME)/swerv_wrapper.sv2v.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/swerv_wrapper.sv2v.v +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc export CORE_UTILIZATION = 40 export CORE_ASPECT_RATIO = 1 diff --git a/flow/designs/nangate45/swerv/metadata-base-ok.json b/flow/designs/nangate45/swerv/metadata-base-ok.json index 9b99d556e1..1748668370 100644 --- a/flow/designs/nangate45/swerv/metadata-base-ok.json +++ b/flow/designs/nangate45/swerv/metadata-base-ok.json @@ -3,297 +3,366 @@ "constraints__clocks__details": [ "core_clock: 2.0000" ], - "cts__clock__skew__hold": 0.118838, - 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"run__flow__openroad_version": "v2.0-17258-gc1904e24e", "run__flow__platform": "nangate45", "run__flow__platform__capacitance_units": "1fF", "run__flow__platform__current_units": "1mA", @@ -304,12 +373,12 @@ "run__flow__platform__voltage_units": "1v", "run__flow__platform_commit": "N/A", "run__flow__scripts_commit": "not a git repo", - "run__flow__uuid": "ca29e368-be3b-42f9-8528-8b550a484ae9", + "run__flow__uuid": "2c6f4364-17a6-43b3-a32d-f532c87a0799", "run__flow__variant": "base", - "synth__cpu__total": 568.17, + "synth__cpu__total": 631.56, "synth__design__instance__area__stdcell": 155952.874, "synth__design__instance__count__stdcell": 88287.0, - "synth__mem__peak": 1559504.0, - "synth__runtime__total": "9:30.55", - "total_time": "1:02:32.320000" + "synth__mem__peak": 1229088.0, + "synth__runtime__total": "10:34.17", + "total_time": "1:07:01.330000" } \ No newline at end of file diff --git a/flow/designs/nangate45/swerv/rules-base.json b/flow/designs/nangate45/swerv/rules-base.json index f42b75e257..f947405e48 100644 --- a/flow/designs/nangate45/swerv/rules-base.json +++ b/flow/designs/nangate45/swerv/rules-base.json @@ -48,7 +48,7 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.37, + "value": -0.49, "compare": ">=" }, "finish__design__instance__area": { diff --git a/flow/designs/nangate45/swerv_wrapper/config.mk b/flow/designs/nangate45/swerv_wrapper/config.mk index d464f44273..0f868c0e54 100644 --- a/flow/designs/nangate45/swerv_wrapper/config.mk +++ b/flow/designs/nangate45/swerv_wrapper/config.mk @@ -9,9 +9,9 @@ export RTLMP_MIN_INST = 5000 export RTLMP_MAX_MACRO = 12 export RTLMP_MIN_MACRO = 4 -export VERILOG_FILES = ./designs/src/swerv/swerv_wrapper.sv2v.v \ - ./designs/$(PLATFORM)/swerv/macros.v -export SDC_FILE = ./designs/$(PLATFORM)/swerv_wrapper/constraint.sdc +export VERILOG_FILES = $(DESIGN_HOME)/src/swerv/swerv_wrapper.sv2v.v \ + $(DESIGN_HOME)/$(PLATFORM)/swerv/macros.v +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/swerv_wrapper/constraint.sdc export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/fakeram45_2048x39.lef \ $(PLATFORM_DIR)/lef/fakeram45_256x34.lef \ @@ -28,8 +28,8 @@ export PLACE_PINS_ARGS = -exclude left:* -exclude right:* -exclude top:* -exclud export MACRO_PLACE_HALO = 10 10 export MACRO_PLACE_CHANNEL = 20 20 -export PLACE_DENSITY_LB_ADDON = 0.10 +export PLACE_DENSITY_LB_ADDON = 0.25 export TNS_END_PERCENT = 100 -export FASTROUTE_TCL = ./designs/$(PLATFORM)/$(DESIGN_NAME)/fastroute.tcl +export FASTROUTE_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/fastroute.tcl diff --git a/flow/designs/nangate45/swerv_wrapper/metadata-base-ok.json b/flow/designs/nangate45/swerv_wrapper/metadata-base-ok.json index 9f8e10e2ab..43f1b79189 100644 --- a/flow/designs/nangate45/swerv_wrapper/metadata-base-ok.json +++ b/flow/designs/nangate45/swerv_wrapper/metadata-base-ok.json @@ -3,328 +3,315 @@ "constraints__clocks__details": [ "core_clock: 2.0000" ], - "cts__clock__skew__hold": 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"placeopt__timing__drv__max_fanout": 0, "placeopt__timing__drv__max_fanout_limit": 0, "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.306307, - "placeopt__timing__drv__setup_violation_count": 1388, - "placeopt__timing__setup__tns": -885.823, - "placeopt__timing__setup__ws": -0.889743, + "placeopt__timing__drv__max_slew_limit": 0.348147, + "placeopt__timing__drv__setup_violation_count": 1364, + "placeopt__timing__setup__tns": -827.018, + "placeopt__timing__setup__ws": -0.920516, "run__flow__design": "swerv_wrapper", - "run__flow__generate_date": "2024-10-22 09:17", + "run__flow__generate_date": "2024-09-27 20:26", "run__flow__metrics_version": "Metrics_2.1.2", "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-16688-g86a2cb529", + "run__flow__openroad_version": "v2.0-16089-gd06039e7d", "run__flow__platform": "nangate45", "run__flow__platform__capacitance_units": "1fF", "run__flow__platform__current_units": "1mA", @@ -335,12 +322,12 @@ "run__flow__platform__voltage_units": "1v", "run__flow__platform_commit": "N/A", "run__flow__scripts_commit": "not a git repo", - "run__flow__uuid": "d8403866-b2b2-45ce-bc54-7c1d97e8cef2", + "run__flow__uuid": "6fac9442-fc01-4b30-ba0c-7900b3282062", "run__flow__variant": "base", - "synth__cpu__total": 512.75, - "synth__design__instance__area__stdcell": 642482.568, - "synth__design__instance__count__stdcell": 98107.0, - "synth__mem__peak": 700148.0, - "synth__runtime__total": "8:35.81", - "total_time": "1:21:49.720000" + "synth__cpu__total": 519.96, + "synth__design__instance__area__stdcell": 642344.514, + "synth__design__instance__count__stdcell": 98157.0, + "synth__mem__peak": 696440.0, + "synth__runtime__total": "8:43.05", + "total_time": "2:00:28.930000" } \ No newline at end of file diff --git a/flow/designs/nangate45/swerv_wrapper/rules-base.json b/flow/designs/nangate45/swerv_wrapper/rules-base.json index 64de9ed0b9..76cc3754de 100644 --- a/flow/designs/nangate45/swerv_wrapper/rules-base.json +++ b/flow/designs/nangate45/swerv_wrapper/rules-base.json @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 4994889, + "value": 7081024, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -48,7 +48,7 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -5.88, + "value": -0.79, "compare": ">=" }, "finish__design__instance__area": { @@ -60,11 +60,11 @@ "compare": "<=" }, "finish__timing__drv__hold_violation_count": { - "value": 589, + "value": 1119, "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -94.0, + "value": -35.9, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/nangate45/tinyRocket/config.mk b/flow/designs/nangate45/tinyRocket/config.mk index 3ba4266214..d06262dd95 100644 --- a/flow/designs/nangate45/tinyRocket/config.mk +++ b/flow/designs/nangate45/tinyRocket/config.mk @@ -5,17 +5,17 @@ export PLATFORM = nangate45 export SYNTH_HIERARCHICAL = 1 export MAX_UNGROUP_SIZE ?= 5000 -export VERILOG_FILES = ./designs/src/$(DESIGN_NICKNAME)/AsyncResetReg.v \ - ./designs/src/$(DESIGN_NICKNAME)/ClockDivider2.v \ - ./designs/src/$(DESIGN_NICKNAME)/ClockDivider3.v \ - ./designs/src/$(DESIGN_NICKNAME)/plusarg_reader.v \ - ./designs/src/$(DESIGN_NICKNAME)/freechips.rocketchip.system.TinyConfig.v \ - ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/freechips.rocketchip.system.TinyConfig.v +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/AsyncResetReg.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ClockDivider2.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ClockDivider3.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/plusarg_reader.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/freechips.rocketchip.system.TinyConfig.v \ + $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/freechips.rocketchip.system.TinyConfig.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc -export ADDITIONAL_LEFS = $(sort $(wildcard ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/*.lef)) -export ADDITIONAL_LIBS = $(sort $(wildcard ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/*.lib)) +export ADDITIONAL_LEFS = $(sort $(wildcard $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/*.lef)) +export ADDITIONAL_LIBS = $(sort $(wildcard $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/*.lib)) # These values must be multiples of placement site diff --git a/flow/designs/sky130hd/aes/config.mk b/flow/designs/sky130hd/aes/config.mk index 7195ef15bd..a7fdf67708 100644 --- a/flow/designs/sky130hd/aes/config.mk +++ b/flow/designs/sky130hd/aes/config.mk @@ -2,8 +2,8 @@ export DESIGN_NICKNAME = aes export DESIGN_NAME = aes_cipher_top export PLATFORM = sky130hd -export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v)) -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export PLACE_PINS_ARGS = -min_distance 4 -min_distance_in_tracks @@ -14,7 +14,7 @@ export CORE_MARGIN = 2 export PLACE_DENSITY = 0.6 export TNS_END_PERCENT = 100 -export FASTROUTE_TCL = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/fastroute.tcl +export FASTROUTE_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/fastroute.tcl export REMOVE_ABC_BUFFERS = 1 diff --git a/flow/designs/sky130hd/chameleon/config.mk b/flow/designs/sky130hd/chameleon/config.mk index 375321a149..be2a73d697 100644 --- a/flow/designs/sky130hd/chameleon/config.mk +++ b/flow/designs/sky130hd/chameleon/config.mk @@ -2,37 +2,37 @@ export DESIGN_NICKNAME = chameleon export DESIGN_NAME = soc_core export PLATFORM = sky130hd -export VERILOG_FILES_BLACKBOX = ./designs/src/$(DESIGN_NICKNAME)/ibex/*.v \ - ./designs/src/$(DESIGN_NICKNAME)/IPs/DFFRAM_4K.v \ - ./designs/src/$(DESIGN_NICKNAME)/AHB_sys_0/APB_sys_0/*.v \ - ./designs/src/$(DESIGN_NICKNAME)/IPs/DMC_32x16HC.v - -export VERILOG_FILES = ./designs/src/$(DESIGN_NICKNAME)/acc/AHB_SPM.v \ - ./designs/src/$(DESIGN_NICKNAME)/IPs/AHBSRAM.v \ - ./designs/src/$(DESIGN_NICKNAME)/IPs/DFFRAMBB.v \ - ./designs/src/$(DESIGN_NICKNAME)/IPs/GPIO.v \ - ./designs/src/$(DESIGN_NICKNAME)/IPs/APB_I2C.v \ - ./designs/src/$(DESIGN_NICKNAME)/IPs/APB_SPI.v \ - ./designs/src/$(DESIGN_NICKNAME)/IPs/APB_UART.v \ - ./designs/src/$(DESIGN_NICKNAME)/IPs/i2c_master.v \ - ./designs/src/$(DESIGN_NICKNAME)/IPs/PWM32.v \ - ./designs/src/$(DESIGN_NICKNAME)/IPs/RAM_3Kx32.v \ - ./designs/src/$(DESIGN_NICKNAME)/IPs/QSPI_XIP_CTRL.v \ - ./designs/src/$(DESIGN_NICKNAME)/IPs/spi_master.v \ - ./designs/src/$(DESIGN_NICKNAME)/IPs/TIMER32.v \ - ./designs/src/$(DESIGN_NICKNAME)/IPs/WDT32.v \ - ./designs/src/$(DESIGN_NICKNAME)/AHB_sys_0/*.v \ - ./designs/src/$(DESIGN_NICKNAME)/soc_core.v \ +export VERILOG_FILES_BLACKBOX = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex/*.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/IPs/DFFRAM_4K.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/AHB_sys_0/APB_sys_0/*.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/IPs/DMC_32x16HC.v + +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/acc/AHB_SPM.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/IPs/AHBSRAM.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/IPs/DFFRAMBB.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/IPs/GPIO.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/IPs/APB_I2C.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/IPs/APB_SPI.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/IPs/APB_UART.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/IPs/i2c_master.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/IPs/PWM32.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/IPs/RAM_3Kx32.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/IPs/QSPI_XIP_CTRL.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/IPs/spi_master.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/IPs/TIMER32.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/IPs/WDT32.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/AHB_sys_0/*.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/soc_core.v \ $(VERILOG_FILES_BLACKBOX) export ABC_AREA = 1 -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export DIE_AREA = 0 0 2920 3520 export CORE_AREA = 20 20 2900 3500 -export chameleon_DIR = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME) +export chameleon_DIR = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME) export ADDITIONAL_GDS = $(chameleon_DIR)/gds/apb_sys_0.gds.gz \ $(chameleon_DIR)/gds/DMC_32x16HC.gds.gz \ diff --git a/flow/designs/sky130hd/chameleon/metadata-base-ok.json b/flow/designs/sky130hd/chameleon/metadata-base-ok.json index 5ea92f0087..5b54d071c7 100644 --- a/flow/designs/sky130hd/chameleon/metadata-base-ok.json +++ b/flow/designs/sky130hd/chameleon/metadata-base-ok.json @@ -3,360 +3,370 @@ "constraints__clocks__details": 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"placeopt__timing__drv__max_fanout_limit": 0, "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.103813, + "placeopt__timing__drv__max_slew_limit": 0.0719374, "placeopt__timing__drv__setup_violation_count": 0, "placeopt__timing__setup__tns": 0, - "placeopt__timing__setup__ws": 1.38853, + "placeopt__timing__setup__ws": 0.511819, "run__flow__design": "chameleon", - "run__flow__generate_date": "2024-10-15 22:17", + "run__flow__generate_date": "2024-11-27 00:38", "run__flow__metrics_version": "Metrics_2.1.2", "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-16535-g199588e84", + "run__flow__openroad_version": "v2.0-17353-g10a5df25b", "run__flow__platform": "sky130hd", "run__flow__platform__capacitance_units": "1pF", "run__flow__platform__current_units": "1mA", @@ -367,12 +377,12 @@ "run__flow__platform__voltage_units": "1v", "run__flow__platform_commit": "N/A", "run__flow__scripts_commit": "not a git repo", - "run__flow__uuid": "715cf9a5-1ae4-4ed3-8e4f-9ab97a8042fd", + "run__flow__uuid": "cc9194ef-3040-4eca-b6ac-9732fc8925c4", "run__flow__variant": "base", - "synth__cpu__total": 4.62, + "synth__cpu__total": 4.54, "synth__design__instance__area__stdcell": 23875.3984, "synth__design__instance__count__stdcell": 2766.0, - "synth__mem__peak": 55552.0, - "synth__runtime__total": "0:04.76", - "total_time": "0:07:04.760000" + "synth__mem__peak": 55296.0, + "synth__runtime__total": "0:04.67", + "total_time": "0:05:48.530000" } \ No newline at end of file diff --git a/flow/designs/sky130hd/chameleon/rules-base.json b/flow/designs/sky130hd/chameleon/rules-base.json index a26c3b7540..0d2b4ffe85 100644 --- a/flow/designs/sky130hd/chameleon/rules-base.json +++ b/flow/designs/sky130hd/chameleon/rules-base.json @@ -8,7 +8,7 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 6536749, + "value": 6535013, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 923401, + "value": 843488, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,7 +44,7 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 54, + "value": 64, "compare": "<=" }, "finish__timing__setup__ws": { @@ -52,7 +52,7 @@ "compare": ">=" }, "finish__design__instance__area": { - "value": 6541223, + "value": 6539601, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { diff --git a/flow/designs/sky130hd/chameleon_hier/DFFRAM_4K/config.mk b/flow/designs/sky130hd/chameleon_hier/DFFRAM_4K/config.mk index 19c59dfd34..7a3fe7c767 100644 --- a/flow/designs/sky130hd/chameleon_hier/DFFRAM_4K/config.mk +++ b/flow/designs/sky130hd/chameleon_hier/DFFRAM_4K/config.mk @@ -1,10 +1,10 @@ export TOP_NICKNAME = chameleon_hier -export TOP_DIR = ./designs/$(PLATFORM)/${TOP_NICKNAME} +export TOP_DIR = $(DESIGN_HOME)/$(PLATFORM)/${TOP_NICKNAME} export DESIGN_NAME = DFFRAM_4K export DESIGN_NICKNAME = ${TOP_NICKNAME}_${DESIGN_NAME} export PLATFORM = sky130hd -export RTL_DIR = ./designs/src/${TOP_NICKNAME}/rtl +export RTL_DIR = $(DESIGN_HOME)/src/${TOP_NICKNAME}/rtl export VERILOG_FILES = \ ${RTL_DIR}/IPs/DFFRAM_4K.v \ diff --git a/flow/designs/sky130hd/chameleon_hier/DMC_32x16HC/config.mk b/flow/designs/sky130hd/chameleon_hier/DMC_32x16HC/config.mk index e29494e4ac..c63c632188 100644 --- a/flow/designs/sky130hd/chameleon_hier/DMC_32x16HC/config.mk +++ b/flow/designs/sky130hd/chameleon_hier/DMC_32x16HC/config.mk @@ -1,10 +1,10 @@ export TOP_NICKNAME = chameleon_hier -export TOP_DIR = ./designs/$(PLATFORM)/${TOP_NICKNAME} +export TOP_DIR = $(DESIGN_HOME)/$(PLATFORM)/${TOP_NICKNAME} export DESIGN_NAME = DMC_32x16HC export DESIGN_NICKNAME = ${TOP_NICKNAME}_${DESIGN_NAME} export PLATFORM = sky130hd -export RTL_DIR = ./designs/src/${TOP_NICKNAME}/rtl +export RTL_DIR = $(DESIGN_HOME)/src/${TOP_NICKNAME}/rtl export VERILOG_FILES = \ ${RTL_DIR}/IPs/DFFRAMBB.v \ diff --git a/flow/designs/sky130hd/chameleon_hier/apb_sys_0/config.mk b/flow/designs/sky130hd/chameleon_hier/apb_sys_0/config.mk index 31a2cfd9e1..9ad85c0488 100644 --- a/flow/designs/sky130hd/chameleon_hier/apb_sys_0/config.mk +++ b/flow/designs/sky130hd/chameleon_hier/apb_sys_0/config.mk @@ -1,10 +1,10 @@ export TOP_NICKNAME = chameleon_hier -export TOP_DIR = ./designs/$(PLATFORM)/${TOP_NICKNAME} +export TOP_DIR = $(DESIGN_HOME)/$(PLATFORM)/${TOP_NICKNAME} export DESIGN_NAME = apb_sys_0 export DESIGN_NICKNAME = ${TOP_NICKNAME}_${DESIGN_NAME} export PLATFORM = sky130hd -export RTL_DIR = ./designs/src/${TOP_NICKNAME}/rtl +export RTL_DIR = $(DESIGN_HOME)/src/${TOP_NICKNAME}/rtl export VERILOG_FILES = \ ${RTL_DIR}/AHB_sys_0/APB_sys_0/*\ diff --git a/flow/designs/sky130hd/chameleon_hier/config.mk b/flow/designs/sky130hd/chameleon_hier/config.mk index ceb86b845a..cd63d0fa5b 100644 --- a/flow/designs/sky130hd/chameleon_hier/config.mk +++ b/flow/designs/sky130hd/chameleon_hier/config.mk @@ -9,10 +9,10 @@ export IO_DIR = ./platforms/sky130io export VERILOG_FILES_BLACKBOX = \ - ./designs/src/$(DESIGN_NICKNAME)/rtl/ibex/*.v \ - ./designs/src/$(DESIGN_NICKNAME)/rtl/IPs/DFFRAM_4K.v \ - ./designs/src/$(DESIGN_NICKNAME)/rtl/AHB_sys_0/APB_sys_0/*.v \ - ./designs/src/$(DESIGN_NICKNAME)/rtl/IPs/DMC_32x16HC.v + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/ibex/*.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/IPs/DFFRAM_4K.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/AHB_sys_0/APB_sys_0/*.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/IPs/DMC_32x16HC.v export BLOCKS = \ DFFRAM_4K \ @@ -22,22 +22,22 @@ export BLOCKS = \ export VERILOG_FILES = \ - ./designs/src/$(DESIGN_NICKNAME)/rtl/acc/AHB_SPM.v \ - ./designs/src/$(DESIGN_NICKNAME)/rtl/IPs/AHBSRAM.v \ - ./designs/src/$(DESIGN_NICKNAME)/rtl/IPs/DFFRAMBB.v \ - ./designs/src/$(DESIGN_NICKNAME)/rtl/IPs/GPIO.v \ - ./designs/src/$(DESIGN_NICKNAME)/rtl/IPs/APB_I2C.v \ - ./designs/src/$(DESIGN_NICKNAME)/rtl/IPs/APB_SPI.v \ - ./designs/src/$(DESIGN_NICKNAME)/rtl/IPs/APB_UART.v \ - ./designs/src/$(DESIGN_NICKNAME)/rtl/IPs/i2c_master.v \ - ./designs/src/$(DESIGN_NICKNAME)/rtl/IPs/PWM32.v \ - ./designs/src/$(DESIGN_NICKNAME)/rtl/IPs/RAM_3Kx32.v \ - ./designs/src/$(DESIGN_NICKNAME)/rtl/IPs/QSPI_XIP_CTRL.v \ - ./designs/src/$(DESIGN_NICKNAME)/rtl/IPs/spi_master.v \ - ./designs/src/$(DESIGN_NICKNAME)/rtl/IPs/TIMER32.v \ - ./designs/src/$(DESIGN_NICKNAME)/rtl/IPs/WDT32.v \ - ./designs/src/$(DESIGN_NICKNAME)/rtl/AHB_sys_0/*.v \ - ./designs/src/$(DESIGN_NICKNAME)/rtl/soc_core.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/acc/AHB_SPM.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/IPs/AHBSRAM.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/IPs/DFFRAMBB.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/IPs/GPIO.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/IPs/APB_I2C.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/IPs/APB_SPI.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/IPs/APB_UART.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/IPs/i2c_master.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/IPs/PWM32.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/IPs/RAM_3Kx32.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/IPs/QSPI_XIP_CTRL.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/IPs/spi_master.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/IPs/TIMER32.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/IPs/WDT32.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/AHB_sys_0/*.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/soc_core.v \ $(VERILOG_FILES_BLACKBOX) export ENABLE_DPO = 0 @@ -45,7 +45,7 @@ export MACRO_PLACE_CHANNEL = 160 160 export MACRO_PLACE_HALO = 160 160 export DIE_AREA = 0.0 0.0 6800 6800 export CORE_AREA = 200 200 6600 6600 -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export MIN_ROUTING_LAYER = met1 export MAX_ROUTING_LAYER = met5 diff --git a/flow/designs/sky130hd/chameleon_hier/ibex_wrapper/config.mk b/flow/designs/sky130hd/chameleon_hier/ibex_wrapper/config.mk index 44a26e5ceb..5a8995057d 100644 --- a/flow/designs/sky130hd/chameleon_hier/ibex_wrapper/config.mk +++ b/flow/designs/sky130hd/chameleon_hier/ibex_wrapper/config.mk @@ -1,10 +1,10 @@ export TOP_NICKNAME = chameleon_hier -export TOP_DIR = ./designs/$(PLATFORM)/${TOP_NICKNAME} +export TOP_DIR = $(DESIGN_HOME)/$(PLATFORM)/${TOP_NICKNAME} export DESIGN_NAME = ibex_wrapper export DESIGN_NICKNAME = ${TOP_NICKNAME}_${DESIGN_NAME} export PLATFORM = sky130hd -export RTL_DIR = ./designs/src/${TOP_NICKNAME}/rtl +export RTL_DIR = $(DESIGN_HOME)/src/${TOP_NICKNAME}/rtl export VERILOG_FILES = \ ${RTL_DIR}/ibex/ibex_core.v\ diff --git a/flow/designs/sky130hd/coyote_tc/config.mk b/flow/designs/sky130hd/coyote_tc/config.mk index 82b6d20da2..c7ff070a28 100644 --- a/flow/designs/sky130hd/coyote_tc/config.mk +++ b/flow/designs/sky130hd/coyote_tc/config.mk @@ -12,15 +12,15 @@ export SKY130_IO_VERSION ?= v0.2.0 export OPENRAMS_DIR = ./platforms/sky130ram export IO_DIR = ./platforms/sky130io -export VERILOG_FILES = ./designs/$(PLATFORM)/coyote_tc/ios.v \ - ./designs/$(PLATFORM)/coyote_tc/macros.v \ - ./designs/src/coyote_tc/coyote_tc.v \ - ./designs/src/coyote/coyote.sv2v.v \ +export VERILOG_FILES = $(DESIGN_HOME)/$(PLATFORM)/coyote_tc/ios.v \ + $(DESIGN_HOME)/$(PLATFORM)/coyote_tc/macros.v \ + $(DESIGN_HOME)/src/coyote_tc/coyote_tc.v \ + $(DESIGN_HOME)/src/coyote/coyote.sv2v.v \ $(IO_DIR)/verilog/sky130_io.blackbox.v -export SDC_FILE = ./designs/$(PLATFORM)/coyote_tc/constraint.sdc +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/coyote_tc/constraint.sdc -export FOOTPRINT_TCL = ./designs/$(PLATFORM)/coyote_tc/pad.tcl +export FOOTPRINT_TCL = $(DESIGN_HOME)/$(PLATFORM)/coyote_tc/pad.tcl export ADDITIONAL_LIBS = $(OPENRAMS_DIR)/sky130_sram_1rw1r_80x64_8/sky130_sram_1rw1r_80x64_8_TT_1p8V_25C.lib \ $(OPENRAMS_DIR)/sky130_sram_1rw1r_128x256_8/sky130_sram_1rw1r_128x256_8_TT_1p8V_25C.lib \ @@ -61,7 +61,7 @@ export DIE_AREA = 0.0 0.0 5200 4609.14 export CORE_AREA = 250 250 4950 4349.14 # Use custom power grid with core rings offset from the pads -export PDN_TCL = ./designs/$(PLATFORM)/coyote_tc/pdn.tcl +export PDN_TCL = $(DESIGN_HOME)/$(PLATFORM)/coyote_tc/pdn.tcl # Point to the RC file export SETRC_FILE = $(PLATFORM_DIR)/setRC.tcl diff --git a/flow/designs/sky130hd/gcd/config.mk b/flow/designs/sky130hd/gcd/config.mk index 1d7248feb4..9b725dcf0b 100644 --- a/flow/designs/sky130hd/gcd/config.mk +++ b/flow/designs/sky130hd/gcd/config.mk @@ -1,8 +1,8 @@ export DESIGN_NAME = gcd export PLATFORM = sky130hd -export VERILOG_FILES = ./designs/src/$(DESIGN_NICKNAME)/gcd.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/gcd.v +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc # Adders degrade GCD export ADDER_MAP_FILE := diff --git a/flow/designs/sky130hd/ibex/config.mk b/flow/designs/sky130hd/ibex/config.mk index 91c302a9f6..1173a088a0 100644 --- a/flow/designs/sky130hd/ibex/config.mk +++ b/flow/designs/sky130hd/ibex/config.mk @@ -2,45 +2,45 @@ export DESIGN_NICKNAME = ibex export DESIGN_NAME = ibex_core export PLATFORM = sky130hd -export VERILOG_FILES = ./designs/src/$(DESIGN_NICKNAME)/ibex_alu.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_branch_predict.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_compressed_decoder.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_controller.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_core.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_counter.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_cs_registers.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_csr.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_decoder.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_dummy_instr.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_ex_block.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_fetch_fifo.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_icache.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_id_stage.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_if_stage.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_load_store_unit.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_multdiv_fast.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_multdiv_slow.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_pmp.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_prefetch_buffer.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_register_file_ff.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_register_file_fpga.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_register_file_latch.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_wb_stage.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_badbit_ram_1p.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_clock_gating.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_generic_clock_gating.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_generic_ram_1p.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_lfsr.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_ram_1p.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_28_22_dec.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_28_22_enc.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_39_32_dec.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_39_32_enc.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_72_64_dec.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_72_64_enc.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_xilinx_clock_gating.v +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_alu.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_branch_predict.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_compressed_decoder.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_controller.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_core.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_counter.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_cs_registers.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_csr.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_decoder.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_dummy_instr.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_ex_block.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_fetch_fifo.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_icache.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_id_stage.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_if_stage.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_load_store_unit.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_fast.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_slow.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_pmp.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_prefetch_buffer.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_ff.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_fpga.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_latch.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_wb_stage.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_badbit_ram_1p.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_clock_gating.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_generic_clock_gating.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_generic_ram_1p.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_lfsr.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_ram_1p.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_28_22_dec.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_28_22_enc.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_39_32_dec.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_39_32_enc.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_72_64_dec.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_72_64_enc.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_xilinx_clock_gating.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc # Adders degrade ibex setup repair export ADDER_MAP_FILE := @@ -49,6 +49,6 @@ export CORE_UTILIZATION = 45 export PLACE_DENSITY_LB_ADDON = 0.2 export TNS_END_PERCENT = 100 -export FASTROUTE_TCL = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/fastroute.tcl +export FASTROUTE_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/fastroute.tcl export REMOVE_ABC_BUFFERS = 1 diff --git a/flow/designs/sky130hd/ibex/fastroute.tcl b/flow/designs/sky130hd/ibex/fastroute.tcl index f4b95b5ae0..80a2ca181e 100644 --- a/flow/designs/sky130hd/ibex/fastroute.tcl +++ b/flow/designs/sky130hd/ibex/fastroute.tcl @@ -1,4 +1,4 @@ -set_global_routing_layer_adjustment $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) 0.35 +set_global_routing_layer_adjustment $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) 0.3 set_routing_layers -clock $::env(MIN_CLK_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) set_routing_layers -signal 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"449eea39-70ee-4444-90ad-98f712df634f", + "run__flow__platform_commit": "c1c473e880e726d110a25b5f1e208dfcb31681a0", + "run__flow__scripts_commit": "c1c473e880e726d110a25b5f1e208dfcb31681a0", + "run__flow__uuid": "f96e61b7-9835-4d9c-b921-60dc6133cff9", "run__flow__variant": "base", - "synth__cpu__total": 121.12, - "synth__design__instance__area__stdcell": 136601.0112, - "synth__design__instance__count__stdcell": 16274.0, - "synth__mem__peak": 229876.0, - "synth__runtime__total": "2:01.52", - "total_time": "0:35:51.910000" + "synth__cpu__total": 40.62, + "synth__design__instance__area__stdcell": 136437.104, + "synth__design__instance__count__stdcell": 15954.0, + "synth__mem__peak": 157400.0, + "synth__runtime__total": "0:40.76", + "total_time": "0:07:24.610000" } \ No newline at end of file diff --git a/flow/designs/sky130hd/ibex/rules-base.json b/flow/designs/sky130hd/ibex/rules-base.json index 496b9a8741..634420abe0 100644 --- a/flow/designs/sky130hd/ibex/rules-base.json +++ b/flow/designs/sky130hd/ibex/rules-base.json @@ -28,11 +28,11 @@ "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 302, + "value": 130, "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 897255, + "value": 865853, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,7 +44,7 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 74, + "value": 38, "compare": "<=" }, "finish__timing__setup__ws": { diff --git a/flow/designs/sky130hd/jpeg/config.mk b/flow/designs/sky130hd/jpeg/config.mk index 7857e38ad7..dced6f2bca 100644 --- a/flow/designs/sky130hd/jpeg/config.mk +++ b/flow/designs/sky130hd/jpeg/config.mk @@ -2,14 +2,14 @@ export DESIGN_NICKNAME = jpeg export DESIGN_NAME = jpeg_encoder export PLATFORM = sky130hd -export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v)) -export VERILOG_INCLUDE_DIRS = ./designs/src/$(DESIGN_NICKNAME)/include -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) +export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/include +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export CORE_UTILIZATION = 50 export PLACE_DENSITY_LB_ADDON = 0.15 export TNS_END_PERCENT = 100 -export FASTROUTE_TCL = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/fastroute.tcl +export FASTROUTE_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/fastroute.tcl export REMOVE_ABC_BUFFERS = 1 diff --git a/flow/designs/sky130hd/jpeg/metadata-base-ok.json b/flow/designs/sky130hd/jpeg/metadata-base-ok.json index d4faae393e..19e0e7c67a 100644 --- a/flow/designs/sky130hd/jpeg/metadata-base-ok.json +++ b/flow/designs/sky130hd/jpeg/metadata-base-ok.json @@ -5,7 +5,7 @@ ], "cts__clock__skew__hold": 0.109872, "cts__clock__skew__setup": 0.109872, - "cts__cpu__total": 51.1, + "cts__cpu__total": 58.28, "cts__design__core__area": 965699, "cts__design__die__area": 972827, "cts__design__instance__area": 540354, @@ -22,16 +22,20 @@ "cts__design__instance__utilization": 0.559548, "cts__design__instance__utilization__stdcell": 0.559548, "cts__design__io": 47, + "cts__design__rows": 361, + "cts__design__rows:unithd": 361, + "cts__design__sites": 771818, + "cts__design__sites:unithd": 771818, "cts__design__violations": 0, "cts__flow__errors__count": 0, "cts__flow__warnings__count": 0, - "cts__mem__peak": 991392.0, + "cts__mem__peak": 1061660.0, "cts__power__internal__total": 0.377681, "cts__power__leakage__total": 2.48599e-07, "cts__power__switching__total": 0.436043, "cts__power__total": 0.813723, "cts__route__wirelength__estimated": 1199090.0, - "cts__runtime__total": "0:51.90", + "cts__runtime__total": "0:59.17", "cts__timing__drv__hold_violation_count": 0, "cts__timing__drv__max_cap": 0, "cts__timing__drv__max_cap_limit": 0.01612, @@ -44,7 +48,7 @@ "cts__timing__setup__ws": 0.00157652, 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"detailedplace__power__total": 0.778519, "detailedplace__route__wirelength__estimated": 1196140.0, - "detailedplace__runtime__total": "1:06.09", + "detailedplace__runtime__total": "1:14.02", "detailedplace__timing__drv__hold_violation_count": 0, "detailedplace__timing__drv__max_cap": 0, "detailedplace__timing__drv__max_cap_limit": 0.0137956, @@ -81,81 +89,94 @@ "detailedplace__timing__setup__ws": 0.0190648, "detailedroute__antenna__violating__nets": 0, "detailedroute__antenna__violating__pins": 0, - "detailedroute__antenna_diodes_count": 30, + "detailedroute__antenna_diodes_count": 49, "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 55, + "detailedroute__flow__warnings__count": 145, "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 25291, - "detailedroute__route__drc_errors__iter:10": 6, + "detailedroute__route__drc_errors__iter:1": 216, + "detailedroute__route__drc_errors__iter:10": 1, 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"finish__timing__drv__max_fanout_limit": 0, "finish__timing__drv__max_slew": 0, - "finish__timing__drv__max_slew_limit": 0.0428902, + "finish__timing__drv__max_slew_limit": 0.0207335, "finish__timing__drv__setup_violation_count": 0, "finish__timing__setup__tns": 0, - "finish__timing__setup__ws": 0.274012, - "finish__timing__wns_percent_delay": 3.145015, - "finish_merge__cpu__total": 6.69, - "finish_merge__mem__peak": 850232.0, - "finish_merge__runtime__total": "0:07.24", - "floorplan__cpu__total": 29.43, + "finish__timing__setup__ws": 0.282058, + "finish__timing__wns_percent_delay": 3.241076, + "finish_merge__cpu__total": 7.49, + "finish_merge__mem__peak": 838560.0, + "finish_merge__runtime__total": "0:08.08", + "floorplan__cpu__total": 32.17, "floorplan__design__core__area": 965699, "floorplan__design__die__area": 972827, "floorplan__design__instance__area": 477036, @@ -167,34 +188,38 @@ "floorplan__design__instance__utilization": 0.49398, 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"flow__errors__count": 0, "flow__warnings__count": 0, - "globalplace__cpu__total": 1992.25, + "globalplace__cpu__total": 991.68, "globalplace__design__core__area": 965699, "globalplace__design__die__area": 972827, "globalplace__design__instance__area": 493159, @@ -206,28 +231,32 @@ "globalplace__design__instance__utilization": 0.510676, "globalplace__design__instance__utilization__stdcell": 0.510676, "globalplace__design__io": 47, + "globalplace__design__rows": 361, + "globalplace__design__rows:unithd": 361, + "globalplace__design__sites": 771818, + "globalplace__design__sites:unithd": 771818, "globalplace__flow__errors__count": 0, "globalplace__flow__warnings__count": 0, - "globalplace__mem__peak": 1186720.0, + "globalplace__mem__peak": 1193172.0, "globalplace__power__internal__total": 0.339259, "globalplace__power__leakage__total": 2.33901e-07, "globalplace__power__switching__total": 0.38014, "globalplace__power__total": 0.7194, - "globalplace__runtime__total": "4:21.09", + "globalplace__runtime__total": "4:10.88", "globalplace__timing__setup__tns": -209917, "globalplace__timing__setup__ws": -253.556, - "globalplace_io__cpu__total": 0.81, - "globalplace_io__mem__peak": 235292.0, - "globalplace_io__runtime__total": "0:01.07", - "globalplace_skip_io__cpu__total": 829.72, - "globalplace_skip_io__mem__peak": 310260.0, - "globalplace_skip_io__runtime__total": "0:31.05", + "globalplace_io__cpu__total": 1.11, + "globalplace_io__mem__peak": 240784.0, + "globalplace_io__runtime__total": "0:01.30", + "globalplace_skip_io__cpu__total": 553.81, + "globalplace_skip_io__mem__peak": 316276.0, + "globalplace_skip_io__runtime__total": "0:23.23", "globalroute__antenna__violating__nets": 0, "globalroute__antenna__violating__pins": 0, "globalroute__antenna_diodes_count": 234, "globalroute__clock__skew__hold": 0.120395, "globalroute__clock__skew__setup": 0.120395, - "globalroute__cpu__total": 485.51, + "globalroute__cpu__total": 507.25, "globalroute__design__core__area": 965699, "globalroute__design__die__area": 972827, "globalroute__design__instance__area": 541252, @@ -244,16 +273,20 @@ "globalroute__design__instance__utilization": 0.560477, "globalroute__design__instance__utilization__stdcell": 0.560477, "globalroute__design__io": 47, + "globalroute__design__rows": 361, + "globalroute__design__rows:unithd": 361, + "globalroute__design__sites": 771818, + "globalroute__design__sites:unithd": 771818, "globalroute__design__violations": 0, "globalroute__flow__errors__count": 0, "globalroute__flow__warnings__count": 0, - "globalroute__mem__peak": 1433476.0, + "globalroute__mem__peak": 1505652.0, "globalroute__power__internal__total": 0.389931, "globalroute__power__leakage__total": 2.48807e-07, "globalroute__power__switching__total": 0.510344, "globalroute__power__total": 0.900275, "globalroute__route__wirelength__estimated": 1200890.0, - "globalroute__runtime__total": "1:39.21", + "globalroute__runtime__total": "1:53.00", "globalroute__timing__clock__slack": 0.029, "globalroute__timing__drv__hold_violation_count": 0, "globalroute__timing__drv__max_cap": 0, @@ -265,7 +298,7 @@ "globalroute__timing__drv__setup_violation_count": 0, "globalroute__timing__setup__tns": 0, "globalroute__timing__setup__ws": 0.0293445, - "placeopt__cpu__total": 52.53, + "placeopt__cpu__total": 60.02, "placeopt__design__core__area": 965699, "placeopt__design__die__area": 972827, "placeopt__design__instance__area": 521888, @@ -277,14 +310,18 @@ "placeopt__design__instance__utilization": 0.540425, "placeopt__design__instance__utilization__stdcell": 0.540425, "placeopt__design__io": 47, + "placeopt__design__rows": 361, + "placeopt__design__rows:unithd": 361, + "placeopt__design__sites": 771818, + "placeopt__design__sites:unithd": 771818, "placeopt__flow__errors__count": 0, "placeopt__flow__warnings__count": 0, - "placeopt__mem__peak": 871692.0, + "placeopt__mem__peak": 863228.0, "placeopt__power__internal__total": 0.361801, "placeopt__power__leakage__total": 2.39495e-07, "placeopt__power__switching__total": 0.413409, "placeopt__power__total": 0.77521, - "placeopt__runtime__total": "0:53.37", + "placeopt__runtime__total": "1:00.95", "placeopt__timing__drv__floating__nets": 0, "placeopt__timing__drv__floating__pins": 0, "placeopt__timing__drv__hold_violation_count": 0, @@ -298,10 +335,10 @@ "placeopt__timing__setup__tns": -0.168848, "placeopt__timing__setup__ws": -0.091422, "run__flow__design": "jpeg", - "run__flow__generate_date": "2024-09-28 19:52", + "run__flow__generate_date": "2024-10-28 13:59", "run__flow__metrics_version": "Metrics_2.1.2", "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-16113-g7b5c8faf7", + "run__flow__openroad_version": "v2.0-16787-gcd519bb5e", "run__flow__platform": "sky130hd", "run__flow__platform__capacitance_units": "1pF", "run__flow__platform__current_units": "1mA", @@ -312,12 +349,12 @@ "run__flow__platform__voltage_units": "1v", "run__flow__platform_commit": "N/A", "run__flow__scripts_commit": "not a git repo", - "run__flow__uuid": "4aa0a06a-8e72-4ebb-8191-74f4dc223a99", + "run__flow__uuid": "f61d2ab1-8ce1-4193-8a9d-39ba48c6566c", "run__flow__variant": "base", - "synth__cpu__total": 131.12, + "synth__cpu__total": 146.62, "synth__design__instance__area__stdcell": 484442.1184, "synth__design__instance__count__stdcell": 53182.0, - "synth__mem__peak": 740628.0, - "synth__runtime__total": "2:12.41", - "total_time": "0:13:44.610000" + "synth__mem__peak": 740116.0, + "synth__runtime__total": "2:28.12", + "total_time": "0:14:44.990000" } \ No newline at end of file diff --git a/flow/designs/sky130hd/jpeg/rules-base.json b/flow/designs/sky130hd/jpeg/rules-base.json index c028adb8d2..359f00156d 100644 --- a/flow/designs/sky130hd/jpeg/rules-base.json +++ b/flow/designs/sky130hd/jpeg/rules-base.json @@ -44,11 +44,11 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 34, + "value": 56, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.12, + "value": -0.11, "compare": ">=" }, "finish__design__instance__area": { diff --git a/flow/designs/sky130hd/microwatt/config.mk b/flow/designs/sky130hd/microwatt/config.mk index 07bdd1cf10..c38676da4e 100644 --- a/flow/designs/sky130hd/microwatt/config.mk +++ b/flow/designs/sky130hd/microwatt/config.mk @@ -2,18 +2,18 @@ export DESIGN_NICKNAME = microwatt export DESIGN_NAME = microwatt export PLATFORM = sky130hd -export VERILOG_FILES_BLACKBOX = ./designs/src/$(DESIGN_NICKNAME)/IPs/*.v -export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v \ +export VERILOG_FILES_BLACKBOX = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/IPs/*.v +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v \ $(VERILOG_FILES_BLACKBOX))) -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export DIE_AREA = 0 0 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"placeopt__timing__setup__tns": -339.136, - "placeopt__timing__setup__ws": -2.25461, + "placeopt__timing__drv__max_slew_limit": 0.00224583, + "placeopt__timing__drv__setup_violation_count": 335, + "placeopt__timing__setup__tns": -740.676, + "placeopt__timing__setup__ws": -3.96828, "run__flow__design": "microwatt", - "run__flow__generate_date": "2024-10-22 10:16", + "run__flow__generate_date": "2024-11-27 03:33", "run__flow__metrics_version": "Metrics_2.1.2", "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-16688-g86a2cb529", + "run__flow__openroad_version": "v2.0-17353-g10a5df25b", "run__flow__platform": "sky130hd", "run__flow__platform__capacitance_units": "1pF", "run__flow__platform__current_units": "1mA", @@ -364,12 +406,12 @@ "run__flow__platform__voltage_units": "1v", "run__flow__platform_commit": "N/A", "run__flow__scripts_commit": "not a git repo", - "run__flow__uuid": "54cbe702-cb21-41f5-9250-f50aa471cb1e", + "run__flow__uuid": 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"detailedplace__design__violations": { @@ -20,19 +20,19 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 16685, + "value": 16681, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 16685, + "value": 16681, "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 7292, + "value": 8485, "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 9705104, + "value": 10332428, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -40,15 +40,15 @@ "compare": "<=" }, "detailedroute__antenna__violating__nets": { - "value": 0, + "value": 3, "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 922, + "value": 1213, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -2.03, + "value": -4.77, "compare": ">=" }, "finish__design__instance__area": { @@ -56,15 +56,15 @@ "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 8343, + "value": 8341, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { - "value": 315, + "value": 122, "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -17.97, + "value": -21.69, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/sky130hd/riscv32i/config.mk b/flow/designs/sky130hd/riscv32i/config.mk index 78dfa704a2..523df1d1c1 100644 --- a/flow/designs/sky130hd/riscv32i/config.mk +++ b/flow/designs/sky130hd/riscv32i/config.mk @@ -2,8 +2,8 @@ export DESIGN_NICKNAME = riscv32i export DESIGN_NAME = riscv export PLATFORM = sky130hd -export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v)) -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export CORE_UTILIZATION = 45 export PLACE_DENSITY_LB_ADDON = 0.2 diff --git a/flow/designs/sky130hd_fakestack/aes/config.mk b/flow/designs/sky130hd_fakestack/aes/config.mk index 5e7513f4d8..e4c679faf2 100644 --- a/flow/designs/sky130hd_fakestack/aes/config.mk +++ b/flow/designs/sky130hd_fakestack/aes/config.mk @@ -2,8 +2,8 @@ export DESIGN_NICKNAME = aes export DESIGN_NAME = aes_cipher_top export PLATFORM = sky130hd_fakestack -export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v)) -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export CORE_UTILIZATION = 20 export CORE_ASPECT_RATIO = 1 diff --git a/flow/designs/sky130hd_fakestack/ariane136/config.mk b/flow/designs/sky130hd_fakestack/ariane136/config.mk index 8d76ad6dd0..8ab5d099ac 100644 --- a/flow/designs/sky130hd_fakestack/ariane136/config.mk +++ b/flow/designs/sky130hd_fakestack/ariane136/config.mk @@ -5,10 +5,10 @@ export PLATFORM = sky130hd_fakestack export SYNTH_HIERARCHICAL = 1 export MAX_UNGROUP_SIZE = 10000 -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc -export VERILOG_FILES = ./designs/src/$(DESIGN_NICKNAME)/ariane.sv2v.v \ - ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/macros.v +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ariane.sv2v.v \ + $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/macros.v export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/fakeram130_256x16.lef export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/fakeram130_256x16.lib diff --git a/flow/designs/sky130hd_fakestack/gcd/config.mk b/flow/designs/sky130hd_fakestack/gcd/config.mk index 53acdea671..4ebdfbc698 100644 --- a/flow/designs/sky130hd_fakestack/gcd/config.mk +++ b/flow/designs/sky130hd_fakestack/gcd/config.mk @@ -1,8 +1,8 @@ export DESIGN_NAME = gcd export PLATFORM = sky130hd_fakestack -export VERILOG_FILES = ./designs/src/$(DESIGN_NICKNAME)/gcd.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/gcd.v +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc # Adders degrade GCD export ADDER_MAP_FILE := diff --git a/flow/designs/sky130hs/aes/config.mk b/flow/designs/sky130hs/aes/config.mk index 1ae8e2c5b2..78dd2e33a6 100644 --- a/flow/designs/sky130hs/aes/config.mk +++ b/flow/designs/sky130hs/aes/config.mk @@ -2,8 +2,8 @@ export DESIGN_NICKNAME = aes export DESIGN_NAME = aes_cipher_top export PLATFORM = sky130hs -export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v)) -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export CORE_UTILIZATION = 40 export CORE_ASPECT_RATIO = 1 diff --git a/flow/designs/sky130hs/coyote_tc/config.mk b/flow/designs/sky130hs/coyote_tc/config.mk index 6d48cf0a33..bb141adccf 100644 --- a/flow/designs/sky130hs/coyote_tc/config.mk +++ b/flow/designs/sky130hs/coyote_tc/config.mk @@ -10,17 +10,17 @@ export SKY130_IO_VERSION ?= v0.2.0 export OPENRAMS_DIR = ./platforms/sky130ram export IO_DIR = ./platforms/sky130io -export VERILOG_FILES = ./designs/src/coyote_tc/coyote_tc.v \ - ./designs/src/coyote/coyote.sv2v.v \ - ./designs/$(PLATFORM)/coyote_tc/ios.v \ - ./designs/$(PLATFORM)/coyote_tc/macros.v \ +export VERILOG_FILES = $(DESIGN_HOME)/src/coyote_tc/coyote_tc.v \ + $(DESIGN_HOME)/src/coyote/coyote.sv2v.v \ + $(DESIGN_HOME)/$(PLATFORM)/coyote_tc/ios.v \ + $(DESIGN_HOME)/$(PLATFORM)/coyote_tc/macros.v \ $(IO_DIR)/verilog/sky130_io.blackbox.v -export SDC_FILE = ./designs/$(PLATFORM)/coyote_tc/constraint.sdc +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/coyote_tc/constraint.sdc export FOOTPRINT_LIBRARY = $(IO_DIR)/library.sky130_fd_io.tcl -export FOOTPRINT = ./designs/$(PLATFORM)/coyote_tc/coyote_tc.package.strategy -export SIG_MAP_FILE = ./designs/$(PLATFORM)/coyote_tc/coyote_tc.sigmap +export FOOTPRINT = $(DESIGN_HOME)/$(PLATFORM)/coyote_tc/coyote_tc.package.strategy +export SIG_MAP_FILE = $(DESIGN_HOME)/$(PLATFORM)/coyote_tc/coyote_tc.sigmap export ADDITIONAL_LIBS = $(OPENRAMS_DIR)/sky130_sram_1rw1r_80x64_8/sky130_sram_1rw1r_80x64_8_TT_1p8V_25C.lib \ $(OPENRAMS_DIR)/sky130_sram_1rw1r_128x256_8/sky130_sram_1rw1r_128x256_8_TT_1p8V_25C.lib \ @@ -64,10 +64,10 @@ export CORE_AREA = 210 210 4990 4389.14 export ABC_DRIVER_CELL = sky130_fd_sc_hs__buf_1 export ABC_LOAD_IN_FF = 3 -export POST_SYNTHESYS_RENAMING = ./designs/$(PLATFORM)/coyote_tc/post_synthesis_rename.tcl +export POST_SYNTHESYS_RENAMING = $(DESIGN_HOME)/$(PLATFORM)/coyote_tc/post_synthesis_rename.tcl # Use custom power grid with core rings offset from the pads -export PDN_CFG = ./designs/$(PLATFORM)/coyote_tc/pdn.cfg +export PDN_CFG = $(DESIGN_HOME)/$(PLATFORM)/coyote_tc/pdn.cfg # Point to the RC file export SETRC_FILE = $(PLATFORM_DIR)/setRC.tcl diff --git a/flow/designs/sky130hs/gcd/config.mk b/flow/designs/sky130hs/gcd/config.mk index b37de24845..8e0a87133b 100644 --- a/flow/designs/sky130hs/gcd/config.mk +++ b/flow/designs/sky130hs/gcd/config.mk @@ -1,8 +1,8 @@ export DESIGN_NAME = gcd export PLATFORM = sky130hs -export VERILOG_FILES = ./designs/src/$(DESIGN_NICKNAME)/gcd.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/gcd.v +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export ABC_AREA = 1 # Adders degrade GCD diff --git a/flow/designs/sky130hs/ibex/config.mk b/flow/designs/sky130hs/ibex/config.mk index b03d4a1f06..3235138721 100644 --- a/flow/designs/sky130hs/ibex/config.mk +++ b/flow/designs/sky130hs/ibex/config.mk @@ -2,44 +2,44 @@ export DESIGN_NICKNAME = ibex export DESIGN_NAME = ibex_core export PLATFORM = sky130hs -export VERILOG_FILES = ./designs/src/$(DESIGN_NICKNAME)/ibex_alu.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_branch_predict.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_compressed_decoder.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_controller.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_core.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_counter.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_cs_registers.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_csr.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_decoder.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_dummy_instr.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_ex_block.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_fetch_fifo.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_icache.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_id_stage.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_if_stage.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_load_store_unit.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_multdiv_fast.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_multdiv_slow.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_pmp.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_prefetch_buffer.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_register_file_ff.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_register_file_fpga.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_register_file_latch.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_wb_stage.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_badbit_ram_1p.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_clock_gating.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_generic_clock_gating.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_generic_ram_1p.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_lfsr.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_ram_1p.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_28_22_dec.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_28_22_enc.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_39_32_dec.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_39_32_enc.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_72_64_dec.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_72_64_enc.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_xilinx_clock_gating.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_alu.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_branch_predict.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_compressed_decoder.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_controller.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_core.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_counter.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_cs_registers.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_csr.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_decoder.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_dummy_instr.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_ex_block.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_fetch_fifo.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_icache.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_id_stage.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_if_stage.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_load_store_unit.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_fast.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_slow.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_pmp.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_prefetch_buffer.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_ff.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_fpga.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_latch.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_wb_stage.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_badbit_ram_1p.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_clock_gating.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_generic_clock_gating.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_generic_ram_1p.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_lfsr.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_ram_1p.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_28_22_dec.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_28_22_enc.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_39_32_dec.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_39_32_enc.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_72_64_dec.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_72_64_enc.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_xilinx_clock_gating.v +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export CORE_UTILIZATION = 45 export PLACE_DENSITY_LB_ADDON = 0.2 diff --git a/flow/designs/sky130hs/ibex/metadata-base-ok.json b/flow/designs/sky130hs/ibex/metadata-base-ok.json index b03caf8ba0..389b3dd079 100644 --- a/flow/designs/sky130hs/ibex/metadata-base-ok.json +++ b/flow/designs/sky130hs/ibex/metadata-base-ok.json @@ -3,301 +3,376 @@ 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0.0197833, "placeopt__timing__drv__setup_violation_count": 0, "placeopt__timing__setup__tns": 0, - "placeopt__timing__setup__ws": 2.14329, + "placeopt__timing__setup__ws": 2.28649, "run__flow__design": "ibex", - "run__flow__generate_date": "2024-09-28 19:54", + "run__flow__generate_date": "2024-11-22 13:56", "run__flow__metrics_version": "Metrics_2.1.2", "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-16113-g7b5c8faf7", + "run__flow__openroad_version": "v2.0-17198-g8396d0866", "run__flow__platform": "sky130hs", "run__flow__platform__capacitance_units": "1pF", "run__flow__platform__current_units": "1mA", @@ -308,12 +383,12 @@ "run__flow__platform__voltage_units": "1v", "run__flow__platform_commit": "N/A", "run__flow__scripts_commit": "not a git repo", - "run__flow__uuid": "0da8a432-5437-41c0-ba3a-bf6ea63e462b", + "run__flow__uuid": "b7e804fd-4507-4040-afd2-cccafa69f971", "run__flow__variant": "base", - "synth__cpu__total": 89.54, - "synth__design__instance__area__stdcell": 187556.256, - "synth__design__instance__count__stdcell": 14588.0, - "synth__mem__peak": 228472.0, - "synth__runtime__total": "1:30.05", - "total_time": "0:08:19.700000" + "synth__cpu__total": 62.73, + "synth__design__instance__area__stdcell": 190474.9344, + "synth__design__instance__count__stdcell": 13598.0, + "synth__mem__peak": 159808.0, + "synth__runtime__total": "1:03.09", + "total_time": "0:05:49.800000" } \ No newline at end of file diff --git a/flow/designs/sky130hs/ibex/rules-base.json b/flow/designs/sky130hs/ibex/rules-base.json index f0c1ebfcb4..a2e1eecf6c 100644 --- a/flow/designs/sky130hs/ibex/rules-base.json +++ b/flow/designs/sky130hs/ibex/rules-base.json @@ -12,7 +12,7 @@ "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 20686, + "value": 19965, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,19 +20,19 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 1799, + "value": 1736, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 1799, + "value": 1736, "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 20, + "value": 36, "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 800273, + "value": 787855, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,7 +44,7 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 15, + "value": 14, "compare": "<=" }, "finish__timing__setup__ws": { @@ -52,11 +52,11 @@ "compare": ">=" }, "finish__design__instance__area": { - "value": 285126, + "value": 280694, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 899, + "value": 868, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { diff --git a/flow/designs/sky130hs/jpeg/config.mk b/flow/designs/sky130hs/jpeg/config.mk index 8df8c90626..6e7b62953e 100644 --- a/flow/designs/sky130hs/jpeg/config.mk +++ b/flow/designs/sky130hs/jpeg/config.mk @@ -2,9 +2,9 @@ export DESIGN_NICKNAME = jpeg export DESIGN_NAME = jpeg_encoder export PLATFORM = sky130hs -export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v)) -export VERILOG_INCLUDE_DIRS = ./designs/src/$(DESIGN_NICKNAME)/include -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) +export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/include +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export ABC_AREA = 1 export CORE_UTILIZATION = 50 diff --git a/flow/designs/sky130hs/riscv32i/config.mk b/flow/designs/sky130hs/riscv32i/config.mk index 467d36af0d..1cf6ab1cf9 100644 --- a/flow/designs/sky130hs/riscv32i/config.mk +++ b/flow/designs/sky130hs/riscv32i/config.mk @@ -2,8 +2,8 @@ export DESIGN_NICKNAME = riscv32i export DESIGN_NAME = riscv export PLATFORM = sky130hs -export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v)) -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export CORE_UTILIZATION = 45 export PLACE_DENSITY_LB_ADDON = 0.2 @@ -11,6 +11,6 @@ export PLACE_DENSITY_LB_ADDON = 0.2 export PLACE_PINS_ARGS=-min_distance 6 -min_distance_in_tracks export TNS_END_PERCENT = 100 -export FASTROUTE_TCL = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/fastroute.tcl +export FASTROUTE_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/fastroute.tcl export REMOVE_ABC_BUFFERS = 1 diff --git a/flow/designs/src/mock-array/build.sbt b/flow/designs/src/mock-array/build.sbt index dfca81a771..6954dda226 100644 --- a/flow/designs/src/mock-array/build.sbt +++ b/flow/designs/src/mock-array/build.sbt @@ -3,7 +3,7 @@ import scala.io.Source organization := "edu.berkeley.cs" -scalaVersion := "2.13.10" +scalaVersion := "2.13.11" scalacOptions ++= Seq("-deprecation", "-feature", "-unchecked", "-language:reflectiveCalls") diff --git a/flow/designs/tsmc65lp/aes/config.mk b/flow/designs/tsmc65lp/aes/config.mk index 2c75469042..d8ed07c577 100644 --- a/flow/designs/tsmc65lp/aes/config.mk +++ b/flow/designs/tsmc65lp/aes/config.mk @@ -2,8 +2,8 @@ export DESIGN_NICKNAME = aes export DESIGN_NAME = aes_cipher_top export PLATFORM = tsmc65lp -export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v)) -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export ABC_AREA = 1 export CORE_UTILIZATION = 40 diff --git a/flow/designs/tsmc65lp/ariane/config.mk b/flow/designs/tsmc65lp/ariane/config.mk index 3e7c20984e..2d97789c52 100644 --- a/flow/designs/tsmc65lp/ariane/config.mk +++ b/flow/designs/tsmc65lp/ariane/config.mk @@ -3,10 +3,10 @@ export PLATFORM = tsmc65lp export SYNTH_HIERARCHICAL = 1 -export VERILOG_FILES = ./designs/src/$(DESIGN_NAME)/ariane.sv2v.v \ - ./designs/$(PLATFORM)/$(DESIGN_NAME)/macros.v +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/ariane.sv2v.v \ + $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/macros.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/tsmc65lp_1rf_lg8_w64_byte.lef export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/tsmc65lp_1rf_lg8_w64_byte_ss_1p08v_1p08v_125c.lib diff --git a/flow/designs/tsmc65lp/black_parrot/config.mk b/flow/designs/tsmc65lp/black_parrot/config.mk index 1f55e1f239..62c0998b62 100644 --- a/flow/designs/tsmc65lp/black_parrot/config.mk +++ b/flow/designs/tsmc65lp/black_parrot/config.mk @@ -10,9 +10,9 @@ export RTLMP_MIN_INST = 5000 export RTLMP_MAX_MACRO = 12 export RTLMP_MIN_MACRO = 4 -export VERILOG_FILES = ./designs/src/$(DESIGN_NAME)/pickled.v \ - ./designs/$(PLATFORM)/$(DESIGN_NAME)/macros.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/pickled.v \ + $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/macros.v +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/tsmc65lp_1rf_lg6_w16_bit.lef \ $(PLATFORM_DIR)/lef/tsmc65lp_1rf_lg6_w8_bit.lef \ diff --git a/flow/designs/tsmc65lp/bp_be_top/config.mk b/flow/designs/tsmc65lp/bp_be_top/config.mk index d3f4916616..937ffce750 100644 --- a/flow/designs/tsmc65lp/bp_be_top/config.mk +++ b/flow/designs/tsmc65lp/bp_be_top/config.mk @@ -4,9 +4,9 @@ export PLATFORM = tsmc65lp export SYNTH_HIERARCHICAL = 1 # -export VERILOG_FILES = ./designs/src/$(DESIGN_NAME)/pickled.v \ - ./designs/$(PLATFORM)/$(DESIGN_NAME)/macros.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/pickled.v \ + $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/macros.v +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/tsmc65lp_1rf_lg6_w16_bit.lef \ $(PLATFORM_DIR)/lef/tsmc65lp_1rf_lg6_w96_bit.lef \ diff --git a/flow/designs/tsmc65lp/bp_fe_top/config.mk b/flow/designs/tsmc65lp/bp_fe_top/config.mk index 0a62e5d519..5b5161a467 100644 --- a/flow/designs/tsmc65lp/bp_fe_top/config.mk +++ b/flow/designs/tsmc65lp/bp_fe_top/config.mk @@ -4,9 +4,9 @@ export PLATFORM = tsmc65lp export SYNTH_HIERARCHICAL = 1 -export VERILOG_FILES = ./designs/src/$(DESIGN_NAME)/pickled.v \ - ./designs/$(PLATFORM)/$(DESIGN_NAME)/macros.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/pickled.v \ + $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/macros.v +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/tsmc65lp_1rf_lg6_w8_bit.lef \ $(PLATFORM_DIR)/lef/tsmc65lp_1rf_lg6_w96_bit.lef \ diff --git a/flow/designs/tsmc65lp/bp_multi_top/config.mk b/flow/designs/tsmc65lp/bp_multi_top/config.mk index 475fded14c..9e4d4aebad 100644 --- a/flow/designs/tsmc65lp/bp_multi_top/config.mk +++ b/flow/designs/tsmc65lp/bp_multi_top/config.mk @@ -10,9 +10,9 @@ export RTLMP_MIN_INST = 5000 export RTLMP_MAX_MACRO = 12 export RTLMP_MIN_MACRO = 4 -export VERILOG_FILES = ./designs/src/$(DESIGN_NAME)/pickled.v \ - ./designs/$(PLATFORM)/$(DESIGN_NAME)/macros.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/pickled.v \ + $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/macros.v +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/tsmc65lp_1rf_lg6_w16_bit.lef \ $(PLATFORM_DIR)/lef/tsmc65lp_1rf_lg6_w8_bit.lef \ diff --git a/flow/designs/tsmc65lp/coyote/config.mk b/flow/designs/tsmc65lp/coyote/config.mk index 4f4b3379da..2d52982f86 100644 --- a/flow/designs/tsmc65lp/coyote/config.mk +++ b/flow/designs/tsmc65lp/coyote/config.mk @@ -11,10 +11,10 @@ export RTLMP_MIN_INST = 5000 export RTLMP_MAX_MACRO = 10 export RTLMP_MIN_MACRO = 5 -export VERILOG_FILES = ./designs/src/$(DESIGN_NICKNAME)/coyote.sv2v.v \ - ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/macros.v -#export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint_hier.sdc +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/coyote.sv2v.v \ + $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/macros.v +#export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint_hier.sdc export ABC_AREA = 1 export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/tsmc65lp_1rf_lg6_w80_bit.lef \ diff --git a/flow/designs/tsmc65lp/dynamic_node/config.mk b/flow/designs/tsmc65lp/dynamic_node/config.mk index cc715798a2..973945e928 100644 --- a/flow/designs/tsmc65lp/dynamic_node/config.mk +++ b/flow/designs/tsmc65lp/dynamic_node/config.mk @@ -2,8 +2,8 @@ export DESIGN_NICKNAME = dynamic_node export DESIGN_NAME = dynamic_node_top_wrap export PLATFORM = tsmc65lp -export VERILOG_FILES = ./designs/src/$(DESIGN_NICKNAME)/dynamic_node.pickle.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/dynamic_node.pickle.v +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc # These values must be multiples of placement site export DIE_AREA = 0 0 500 501.6 diff --git a/flow/designs/tsmc65lp/gcd/config.mk b/flow/designs/tsmc65lp/gcd/config.mk index edebb09326..aad84150d4 100644 --- a/flow/designs/tsmc65lp/gcd/config.mk +++ b/flow/designs/tsmc65lp/gcd/config.mk @@ -1,8 +1,8 @@ export DESIGN_NAME = gcd export PLATFORM = tsmc65lp -export VERILOG_FILES = ./designs/src/$(DESIGN_NAME)/gcd.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/gcd.v +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc export ABC_AREA = 1 # These values must be multiples of placement site diff --git a/flow/designs/tsmc65lp/ibex/config.mk b/flow/designs/tsmc65lp/ibex/config.mk index 5711d86239..16405a538a 100644 --- a/flow/designs/tsmc65lp/ibex/config.mk +++ b/flow/designs/tsmc65lp/ibex/config.mk @@ -2,47 +2,47 @@ export DESIGN_NICKNAME = ibex export DESIGN_NAME = ibex_core export PLATFORM = tsmc65lp -export VERILOG_FILES = ./designs/src/$(DESIGN_NICKNAME)/ibex_alu.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_branch_predict.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_compressed_decoder.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_controller.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_core.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_counter.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_cs_registers.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_csr.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_decoder.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_dummy_instr.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_ex_block.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_fetch_fifo.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_icache.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_id_stage.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_if_stage.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_load_store_unit.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_multdiv_fast.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_multdiv_slow.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_pmp.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_prefetch_buffer.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_register_file_ff.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_register_file_fpga.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_register_file_latch.v \ - ./designs/src/$(DESIGN_NICKNAME)/ibex_wb_stage.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_badbit_ram_1p.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_clock_gating.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_generic_clock_gating.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_generic_ram_1p.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_lfsr.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_ram_1p.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_28_22_dec.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_28_22_enc.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_39_32_dec.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_39_32_enc.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_72_64_dec.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_secded_72_64_enc.v \ - ./designs/src/$(DESIGN_NICKNAME)/prim_xilinx_clock_gating.v +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_alu.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_branch_predict.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_compressed_decoder.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_controller.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_core.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_counter.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_cs_registers.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_csr.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_decoder.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_dummy_instr.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_ex_block.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_fetch_fifo.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_icache.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_id_stage.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_if_stage.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_load_store_unit.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_fast.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_slow.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_pmp.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_prefetch_buffer.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_ff.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_fpga.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_latch.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_wb_stage.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_badbit_ram_1p.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_clock_gating.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_generic_clock_gating.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_generic_ram_1p.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_lfsr.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_ram_1p.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_28_22_dec.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_28_22_enc.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_39_32_dec.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_39_32_enc.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_72_64_dec.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_72_64_enc.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_xilinx_clock_gating.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export CORE_UTILIZATION = 40 export CORE_ASPECT_RATIO = 1 diff --git a/flow/designs/tsmc65lp/jpeg/config.mk b/flow/designs/tsmc65lp/jpeg/config.mk index 1aebb9fff4..65077f3e2f 100644 --- a/flow/designs/tsmc65lp/jpeg/config.mk +++ b/flow/designs/tsmc65lp/jpeg/config.mk @@ -2,9 +2,9 @@ export DESIGN_NICKNAME = jpeg export DESIGN_NAME = jpeg_encoder export PLATFORM = tsmc65lp -export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v)) -export VERILOG_INCLUDE_DIRS = ./designs/src/$(DESIGN_NICKNAME)/include -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) +export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/include +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export ABC_AREA = 1 export CORE_UTILIZATION = 40 diff --git a/flow/designs/tsmc65lp/swerv/config.mk b/flow/designs/tsmc65lp/swerv/config.mk index 7b5b8267be..52cd636c16 100644 --- a/flow/designs/tsmc65lp/swerv/config.mk +++ b/flow/designs/tsmc65lp/swerv/config.mk @@ -1,8 +1,8 @@ export DESIGN_NAME = swerv export PLATFORM = tsmc65lp -export VERILOG_FILES = ./designs/src/$(DESIGN_NAME)/swerv_wrapper.sv2v.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/swerv_wrapper.sv2v.v +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc # These values must be multiples of placement site export DIE_AREA = 0 0 1550 1341.6 diff --git a/flow/designs/tsmc65lp/swerv_wrapper/config.mk b/flow/designs/tsmc65lp/swerv_wrapper/config.mk index 5482d732fb..0b2ea6472b 100644 --- a/flow/designs/tsmc65lp/swerv_wrapper/config.mk +++ b/flow/designs/tsmc65lp/swerv_wrapper/config.mk @@ -9,9 +9,9 @@ export RTLMP_MIN_INST = 5000 export RTLMP_MAX_MACRO = 12 export RTLMP_MIN_MACRO = 4 -export VERILOG_FILES = ./designs/src/swerv/swerv_wrapper.sv2v.v \ - ./designs/$(PLATFORM)/$(DESIGN_NAME)/macros.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc +export VERILOG_FILES = $(DESIGN_HOME)/src/swerv/swerv_wrapper.sv2v.v \ + $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/macros.v +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/tsmc65lp_1rf_lg11_w40_all.lef \ $(PLATFORM_DIR)/lef/tsmc65lp_1rf_lg6_w22_all.lef \ diff --git a/flow/designs/tsmc65lp/tinyRocket/config.mk b/flow/designs/tsmc65lp/tinyRocket/config.mk index b42f5bc1b6..9d43e434da 100644 --- a/flow/designs/tsmc65lp/tinyRocket/config.mk +++ b/flow/designs/tsmc65lp/tinyRocket/config.mk @@ -5,14 +5,14 @@ export PLATFORM = tsmc65lp export SYNTH_HIERARCHICAL = 1 export MAX_UNGROUP_SIZE ?= 5000 -export VERILOG_FILES = ./designs/src/$(DESIGN_NICKNAME)/AsyncResetReg.v \ - ./designs/src/$(DESIGN_NICKNAME)/ClockDivider2.v \ - ./designs/src/$(DESIGN_NICKNAME)/ClockDivider3.v \ - ./designs/src/$(DESIGN_NICKNAME)/plusarg_reader.v \ - ./designs/src/$(DESIGN_NICKNAME)/freechips.rocketchip.system.TinyConfig.v \ - ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/macros.v +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/AsyncResetReg.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ClockDivider2.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ClockDivider3.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/plusarg_reader.v \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/freechips.rocketchip.system.TinyConfig.v \ + $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/macros.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/tsmc65lp_1rf_lg6_w32_byte.lef \ $(PLATFORM_DIR)/lef/tsmc65lp_1rf_lg6_w32_all.lef \ diff --git a/flow/designs/tsmc65lp/vanilla5/config.mk b/flow/designs/tsmc65lp/vanilla5/config.mk index be37f0b139..80122d2091 100644 --- a/flow/designs/tsmc65lp/vanilla5/config.mk +++ b/flow/designs/tsmc65lp/vanilla5/config.mk @@ -2,8 +2,8 @@ export DESIGN_NICKNAME = vanilla5 export DESIGN_NAME = bsg_manycore_tile export PLATFORM = tsmc65lp -export VERILOG_FILES = ./designs/src/$(DESIGN_NICKNAME)/bsg_manycore_tile.sv2v.v -export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/bsg_manycore_tile.sv2v.v +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/tsmc65lp_1rf_lg10_w32_all.lef \ $(PLATFORM_DIR)/lef/tsmc65lp_2rf_lg5_w32_all.lef \ diff --git a/flow/platforms/ihp-sg13g2/cdl/RM_IHPSG13_1P_1024x16_c2_bm_bist.cdl b/flow/platforms/ihp-sg13g2/cdl/RM_IHPSG13_1P_1024x16_c2_bm_bist.cdl new file mode 100644 index 0000000000..1f2dc467dd --- /dev/null +++ b/flow/platforms/ihp-sg13g2/cdl/RM_IHPSG13_1P_1024x16_c2_bm_bist.cdl @@ -0,0 +1,6391 @@ +* ------------------------------------------------------ +* +* Copyright 2024 IHP PDK Authors +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* https://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* +* Generated on Fri Jul 19 08:58:12 2024 +* +* ------------------------------------------------------ + +.SUBCKT RM_IHPSG13_1024x16_c2_1P_BITKIT_CORNER NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_CORNER VDD_CORE VSS +XI16 VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_1P_BITKIT_CORNER +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_LR LWL NW PW VDD VSS +MN1 VSS LWL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN0 VSS net9 VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_EDGE_LR A_WL<15> A_WL<14> A_WL<13> A_WL<12> ++ A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> ++ A_WL<2> A_WL<1> A_WL<0> VDD_CORE VSS +XI0<15> A_WL<15> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_LR +XI0<14> A_WL<14> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_LR +XI0<13> A_WL<13> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_LR +XI0<12> A_WL<12> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_LR +XI0<11> A_WL<11> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_LR +XI0<10> A_WL<10> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_LR +XI0<9> A_WL<9> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_LR +XI0<8> A_WL<8> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_LR +XI0<7> A_WL<7> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_LR +XI0<6> A_WL<6> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_LR +XI0<5> A_WL<5> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_LR +XI0<4> A_WL<4> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_LR +XI0<3> A_WL<3> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_LR +XI0<2> A_WL<2> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_LR +XI0<1> A_WL<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_LR +XI0<0> A_WL<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_LR +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL BLC_BOT BLC_TOP BLT_BOT BLT_TOP LWL NW PW ++ RWL VDD VSS +MN0 NC NT VSS PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN1 NT NC VSS PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN3 NC RWL BLC_TOP PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN2 BLT_BOT LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MP1 NT NC VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 NC NT VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +R1 BLC_BOT BLC_TOP lvsres w=2.6e-07 l=6e-07 +R0 BLT_BOT BLT_TOP lvsres w=2.6e-07 l=6e-07 +R2 RWL LWL lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_SRAM A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> ++ A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<15> ++ A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> ++ A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> ++ A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> ++ A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> VDD_CORE ++ VSS +XCELL<31> A_BLC_TOP<1> A_RBLC<15> A_BLT_TOP<1> A_RBLT<15> A_RWL<15> ++ VDD_CORE VSS A_XWL<15> VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL +XCELL<30> A_RBLC<14> A_RBLC<15> A_RBLT<14> A_RBLT<15> A_RWL<14> VDD_CORE ++ VSS A_XWL<14> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL +XCELL<29> A_RBLC<14> A_RBLC<13> A_RBLT<14> A_RBLT<13> A_RWL<13> VDD_CORE ++ VSS A_XWL<13> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL +XCELL<28> A_RBLC<12> A_RBLC<13> A_RBLT<12> A_RBLT<13> A_RWL<12> VDD_CORE ++ VSS A_XWL<12> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL +XCELL<27> A_RBLC<12> A_RBLC<11> A_RBLT<12> A_RBLT<11> A_RWL<11> VDD_CORE ++ VSS A_XWL<11> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL +XCELL<26> A_RBLC<10> A_RBLC<11> A_RBLT<10> A_RBLT<11> A_RWL<10> VDD_CORE ++ VSS A_XWL<10> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL +XCELL<25> A_RBLC<10> A_RBLC<9> A_RBLT<10> A_RBLT<9> A_RWL<9> VDD_CORE ++ VSS A_XWL<9> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL +XCELL<24> A_RBLC<8> A_RBLC<9> A_RBLT<8> A_RBLT<9> A_RWL<8> VDD_CORE ++ VSS A_XWL<8> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL +XCELL<23> A_RBLC<8> A_RBLC<7> A_RBLT<8> A_RBLT<7> A_RWL<7> VDD_CORE ++ VSS A_XWL<7> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL +XCELL<22> A_RBLC<6> A_RBLC<7> A_RBLT<6> A_RBLT<7> A_RWL<6> VDD_CORE ++ VSS A_XWL<6> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL +XCELL<21> A_RBLC<6> A_RBLC<5> A_RBLT<6> A_RBLT<5> A_RWL<5> VDD_CORE ++ VSS A_XWL<5> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL +XCELL<20> A_RBLC<4> A_RBLC<5> A_RBLT<4> A_RBLT<5> A_RWL<4> VDD_CORE ++ VSS A_XWL<4> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL +XCELL<19> A_RBLC<4> A_RBLC<3> A_RBLT<4> A_RBLT<3> A_RWL<3> VDD_CORE ++ VSS A_XWL<3> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL +XCELL<18> A_RBLC<2> A_RBLC<3> A_RBLT<2> A_RBLT<3> A_RWL<2> VDD_CORE ++ VSS A_XWL<2> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL +XCELL<17> A_RBLC<2> A_RBLC<1> A_RBLT<2> A_RBLT<1> A_RWL<1> VDD_CORE ++ VSS A_XWL<1> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL +XCELL<16> A_BLC_BOT<1> A_RBLC<1> A_BLT_BOT<1> A_RBLT<1> A_RWL<0> VDD_CORE ++ VSS A_XWL<0> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL +XCELL<15> A_BLC_TOP<0> A_LBLC<15> A_BLT_TOP<0> A_LBLT<15> A_LWL<15> ++ VDD_CORE VSS A_XWL<15> VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL +XCELL<14> A_LBLC<14> A_LBLC<15> A_LBLT<14> A_LBLT<15> A_LWL<14> VDD_CORE ++ VSS A_XWL<14> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL +XCELL<13> A_LBLC<14> A_LBLC<13> A_LBLT<14> A_LBLT<13> A_LWL<13> VDD_CORE ++ VSS A_XWL<13> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL +XCELL<12> A_LBLC<12> A_LBLC<13> A_LBLT<12> A_LBLT<13> A_LWL<12> VDD_CORE ++ VSS A_XWL<12> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL +XCELL<11> A_LBLC<12> A_LBLC<11> A_LBLT<12> A_LBLT<11> A_LWL<11> VDD_CORE ++ VSS A_XWL<11> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL +XCELL<10> A_LBLC<10> A_LBLC<11> A_LBLT<10> A_LBLT<11> A_LWL<10> VDD_CORE ++ VSS A_XWL<10> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL +XCELL<9> A_LBLC<10> A_LBLC<9> A_LBLT<10> A_LBLT<9> A_LWL<9> VDD_CORE ++ VSS A_XWL<9> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL +XCELL<8> A_LBLC<8> A_LBLC<9> A_LBLT<8> A_LBLT<9> A_LWL<8> VDD_CORE ++ VSS A_XWL<8> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL +XCELL<7> A_LBLC<8> A_LBLC<7> A_LBLT<8> A_LBLT<7> A_LWL<7> VDD_CORE ++ VSS A_XWL<7> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL +XCELL<6> A_LBLC<6> A_LBLC<7> A_LBLT<6> A_LBLT<7> A_LWL<6> VDD_CORE ++ VSS A_XWL<6> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL +XCELL<5> A_LBLC<6> A_LBLC<5> A_LBLT<6> A_LBLT<5> A_LWL<5> VDD_CORE ++ VSS A_XWL<5> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL +XCELL<4> A_LBLC<4> A_LBLC<5> A_LBLT<4> A_LBLT<5> A_LWL<4> VDD_CORE ++ VSS A_XWL<4> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL +XCELL<3> A_LBLC<4> A_LBLC<3> A_LBLT<4> A_LBLT<3> A_LWL<3> VDD_CORE ++ VSS A_XWL<3> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL +XCELL<2> A_LBLC<2> A_LBLC<3> A_LBLT<2> A_LBLT<3> A_LWL<2> VDD_CORE ++ VSS A_XWL<2> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL +XCELL<1> A_LBLC<2> A_LBLC<1> A_LBLT<2> A_LBLT<1> A_LWL<1> VDD_CORE ++ VSS A_XWL<1> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL +XCELL<0> A_BLC_BOT<0> A_LBLC<1> A_BLT_BOT<0> A_LBLT<1> A_LWL<0> VDD_CORE ++ VSS A_XWL<0> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_TB BLC BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_EDGE_TB A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ VDD_CORE VSS +XEDGE<1> A_BLC<1> A_BLT<1> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_TB +XEDGE<0> A_BLC<0> A_BLT<0> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_TB +.ENDS + +.SUBCKT RSC_IHPSG13_CBUFX4 A Z VDD VSS +MN0 net9 A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 Z net9 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MP0 net9 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP1 Z net9 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_COLDRV13X4 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX4 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_WLDRV16X4 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX4 +.ENDS +.SUBCKT RSC_IHPSG13_FILLCAP8 VDD VSS +MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=4.98u l=130.00n ng=6 nrd=0 ++ nrs=0 +MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=6.48u l=385.000n ng=4 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_LHPQX2 CP D Q VDD VSS +MN3 QIN CPN net14 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN2 net14 net10 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN5 net21 D VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN6 QIN CP net21 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net10 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 CPN CP VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 Q QIN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP2 QIN CP net16 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 CPN CP VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 Q QIN VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP3 net10 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net16 net10 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP6 QIN CPN net20 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP5 net20 D VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_NAND2X2 A B Z VDD VSS +MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z B net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net7 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX4 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX2 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_INVX2 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_NAND3X2 A B C Z VDD VSS +MP2 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z C VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN1 net12 B net16 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z C net12 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN2 net16 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_NOR3X2 A B C Z VDD VSS +MP0 net13 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z C net10 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP1 net10 B net13 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN1 Z B VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z C VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0 +MN2 Z A VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_FILLCAP4 VDD VSS +MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=2.49u l=130.00n ng=3 nrd=0 ++ nrs=0 +MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=3.24u l=385.000n ng=2 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_MET2RES A B +R0 B A lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_DEC04 ADDR<3> ADDR<2> ADDR<1> ADDR<0> CS ECLK_H_BOT ++ ECLK_H_TOP ECLK_L_BOT ECLK_L_TOP WL<15> WL<14> WL<13> WL<12> WL<11> WL<10> ++ WL<9> WL<8> WL<7> WL<6> WL<5> WL<4> WL<3> WL<2> WL<1> WL<0> VDD VSS +XLATCH<3> CS ADDR<3> PADR<3> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<2> CS ADDR<2> PADR<2> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<1> CS ADDR<1> PADR<1> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<0> CS ADDR<0> PADR<0> VDD VSS / RSC_IHPSG13_LHPQX2 +XI0<3> PADR<1> PADR<0> sel01<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<2> PADR<1> NADR<0> sel01<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<1> NADR<1> PADR<0> sel01<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<0> NADR<1> NADR<0> sel01<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI4 ECLK_L_BOT EN VDD VSS / RSC_IHPSG13_CINVX4 +XI5 ECLK_H_BOT ECLK_L_BOT VDD VSS / RSC_IHPSG13_CINVX2 +XI3<3> PADR<3> NADR<3> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> PADR<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> PADR<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> PADR<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI1<3> PADR<2> PADR<3> CS sel23<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<2> PADR<3> CS sel23<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<2> NADR<3> CS sel23<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<2> NADR<3> CS sel23<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI2<15> sel23<3> sel01<3> EN WL<15> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<14> sel23<3> sel01<2> EN WL<14> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<13> sel23<3> sel01<1> EN WL<13> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<12> sel23<3> sel01<0> EN WL<12> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<11> sel23<2> sel01<3> EN WL<11> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<10> sel23<2> sel01<2> EN WL<10> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<9> sel23<2> sel01<1> EN WL<9> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<8> sel23<2> sel01<0> EN WL<8> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<7> sel23<1> sel01<3> EN WL<7> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<6> sel23<1> sel01<2> EN WL<6> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<5> sel23<1> sel01<1> EN WL<5> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<4> sel23<1> sel01<0> EN WL<4> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<3> sel23<0> sel01<3> EN WL<3> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<2> sel23<0> sel01<2> EN WL<2> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<1> sel23<0> sel01<1> EN WL<1> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<0> sel23<0> sel01<0> EN WL<0> VDD VSS / RSC_IHPSG13_NOR3X2 +XCAPS4 VDD VSS / RSC_IHPSG13_FILLCAP4 +XI11 ECLK_L_BOT ECLK_L_TOP / RSC_IHPSG13_MET2RES +XR0 ECLK_H_BOT ECLK_H_TOP / RSC_IHPSG13_MET2RES +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_ROWDEC4 ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> ++ CS_I ECLK_I WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XSEL ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ECLK_H<1> ++ ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> ++ WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> ++ WL_O<0> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX8 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=2.82u l=130.00n ng=4 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_DFNQMX2IX1 BE BI CN D QI QIN VDD VSS +MN15 net026 BI VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN14 MXI_OUT BE net026 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net025 D VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 MXI_OUT BEN net025 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN10 QI CNN net21 VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 nrd=0 nrs=0 +MN11 net21 QI_MS VSS VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN7 net30 QI_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN6 QIN_MS CNN net30 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 QI_MS QIN_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN12 CNN CN VSS VSS sg13_lv_nmos m=1 w=495.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN9 net37 MXI_OUT VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN8 QIN_MS CN net37 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 QI CN net25 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN4 net25 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 QIN QI VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN13 BEN BE VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP15 MXI_OUT BEN net027 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP14 net027 BI VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP1 MXI_OUT BE net024 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 net024 D VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP13 BEN BE VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP6 QI_MS QIN_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP3 QI CNN net27 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MP2 net27 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP10 net36 MXI_OUT VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP11 QIN_MS CNN net36 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net32 QI_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP5 QIN_MS CN net32 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 QIN QI VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP12 CNN CN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP9 QI CN net19 VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 nrd=0 nrs=0 +MP8 net19 QI_MS VDD VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_ROWREG4 ACLK_N_I ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RSC_IHPSG13_CDLYX1 A Z VDD VSS +MN1 net010 net032 VSS VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 ++ nrd=0 nrs=0 +MN2 net032 A net014 VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 ++ nrs=0 +MN0 Z net032 net010 VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 ++ nrs=0 +MN3 net014 A VSS VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 ++ nrs=0 +MP1 Z net032 net07 VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 ++ nrs=0 +MP3 net011 A VDD VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 ++ nrs=0 +MP0 net07 net032 VDD VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 ++ nrd=0 nrs=0 +MP2 net032 A net011 VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CDLYX1_DUMMY A Z VDD VSS +MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=2.49u l=300.0n ng=3 nrd=0 ++ nrs=0 +MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=3.24u l=640.00n ng=2 nrd=0 ++ nrs=0 +R0 Z A lvsres w=2.6e-07 l=6e-07 +.ENDS + +.SUBCKT RSC_IHPSG13_MX2IX1 A0 A1 S ZN VDD VSS +MP4 SN S VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 nrs=0 +MP3 ZN SN net12 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 nrs=0 +MP2 net12 A1 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 ZN S net17 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 nrs=0 +MP0 net17 A0 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 SN S VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN3 net13 A1 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 ZN S net13 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net15 A0 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 ZN SN net15 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_DLY_MUX A SEL Z VDD VSS +XI11 net4 Z VDD VSS / RSC_IHPSG13_CINVX2 +XI8 A D<3> SEL net4 VDD VSS / RSC_IHPSG13_MX2IX1 +XI20<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1 +.ENDS +.SUBCKT RSC_IHPSG13_DFNQX2 CN D Q VDD VSS +MN0 Q QIN_SL VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN10 QIN_SL CNN net21 VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN11 net21 QI_MS VSS VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN7 net30 QI_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN6 QIN_MS CNN net30 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 QI_MS QIN_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN12 CNN CN VSS VSS sg13_lv_nmos m=1 w=495.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN9 net37 D VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN8 QIN_MS CN net37 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 QIN_SL CN net25 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net25 QI_SL VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN2 QI_SL QIN_SL VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP0 Q QIN_SL VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP6 QI_MS QIN_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP3 QIN_SL CNN net27 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 net27 QI_SL VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP10 net36 D VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP11 QIN_MS CNN net36 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net32 QI_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP5 QIN_MS CN net32 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 QI_SL QIN_SL VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP12 CNN CN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP9 QIN_SL CN net19 VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP8 net19 QI_MS VDD VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CNAND2X2 A B Z VDD VSS +MN0 Z B net6 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net6 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CGATEPX4 CP E Q VDD VSS +MN1 net08 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 net019 net08 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN3 QIN CP net019 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN6 Q net015 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 ++ nrs=0 +MN5 net015 net08 net018 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN8 QIN CPN net023 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN7 net023 E VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net018 CP VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 CPN CP VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP3 net08 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 QIN CPN net017 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net017 net08 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP0 CPN CP VDD VDD sg13_lv_pmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP8 QIN CP net024 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 net024 E VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net015 CP VDD VDD sg13_lv_pmos m=1 w=1.27u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP6 Q net015 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 ++ nrs=0 +MP5 net015 net08 VDD VDD sg13_lv_pmos m=1 w=1.27u l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CBUFX8 A Z VDD VSS +MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0 +MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=2.82u l=130.00n ng=4 nrd=0 nrs=0 +MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CDLYX2 A Z VDD VSS +MN2 net4 A net9 VSS sg13_lv_nmos m=1 w=320.00n l=200.0n ng=1 nrd=0 nrs=0 +MN0 Z net4 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net9 A VSS VSS sg13_lv_nmos m=1 w=320.00n l=200.0n ng=1 nrd=0 nrs=0 +MP2 net4 A net10 VDD sg13_lv_pmos m=1 w=1.2u l=200.0n ng=1 nrd=0 nrs=0 +MP1 net10 A VDD VDD sg13_lv_pmos m=1 w=1.2u l=200.0n ng=1 nrd=0 nrs=0 +MP0 Z net4 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_MX2X2 A0 A1 S Z VDD VSS +MP6 Z net010 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 SN S VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 nrs=0 +MP3 net010 SN net12 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 net12 A1 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net010 S net17 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 net17 A0 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN6 Z net010 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 SN S VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 nrs=0 +MN3 net13 A1 VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 net010 S net13 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net15 A0 VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 net010 SN net15 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_AND2X2 A B Z VDD VSS +MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_TIEL Z VDD VSS +MN0 Z net2 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 net2 net2 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_XOR2X2 A B Z VDD VSS +MP8 net012 B net7 VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 net011 net3 net012 VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP6 Z net012 VDD VDD sg13_lv_pmos m=1 w=1.535u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 net7 A VDD VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net011 net7 VDD VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP5 net3 B VDD VDD sg13_lv_pmos m=1 w=580.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN7 net012 B net011 VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN6 net7 net3 net012 VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 Z net012 VSS VSS sg13_lv_nmos m=1 w=775.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 net7 A VSS VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net3 B VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 net011 net7 VSS VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_OA12X1 A B C Z VDD VSS +MN2 net7 C VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 Z net17 VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net17 B net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN0 net17 A net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 net24 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP3 Z net17 VDD VDD sg13_lv_pmos m=1 w=905.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net17 B net24 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP2 net17 C VDD VDD sg13_lv_pmos m=1 w=905.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_CTRL ACLK_N BIST_CK_I BIST_CS_I BIST_EN BIST_RE_I ++ BIST_WE_I B_TIEL_O CK_I CS_I DCLK ECLK PULSE_H PULSE_L PULSE_O RCLK RE_I ++ ROW_CS WCLK WE_I VDD VSS +XI17 ck_regs we col_we VDD VSS / RSC_IHPSG13_DFNQX2 +XI16 ck_regs re col_re VDD VSS / RSC_IHPSG13_DFNQX2 +XI18 ck_regs cs net7 VDD VSS / RSC_IHPSG13_DFNQX2 +XI71 ACLK_N net012 PULSE_O VDD VSS / RSC_IHPSG13_DFNQX2 +XI77 col_we net9 net016 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI76 col_re net9 net018 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI15 ck_dly WEorREandCS aclk VDD VSS / RSC_IHPSG13_CGATEPX4 +XI14 ck WEandCS DCLK VDD VSS / RSC_IHPSG13_CGATEPX4 +XI60 net7 ROW_CS VDD VSS / RSC_IHPSG13_CBUFX8 +XI73 PULSE_O net012 VDD VSS / RSC_IHPSG13_CINVX2 +XI8 net9 net8 VDD VSS / RSC_IHPSG13_CINVX2 +XI64 ck ck_dly VDD VSS / RSC_IHPSG13_CDLYX2 +XI86 CS_I BIST_CS_I BIST_EN cs VDD VSS / RSC_IHPSG13_MX2X2 +XI87 CK_I BIST_CK_I BIST_EN ck VDD VSS / RSC_IHPSG13_MX2X2 +XI85 WE_I BIST_WE_I BIST_EN we VDD VSS / RSC_IHPSG13_MX2X2 +XI84 RE_I BIST_RE_I BIST_EN re VDD VSS / RSC_IHPSG13_MX2X2 +XI22 we cs WEandCS VDD VSS / RSC_IHPSG13_AND2X2 +XBM_TIEL B_TIEL_O VDD VSS / RSC_IHPSG13_TIEL +XI48 ck_dly ck_regs VDD VSS / RSC_IHPSG13_CINVX4 +XI81 net016 WCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI80 net018 RCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI78 net8 net020 VDD VSS / RSC_IHPSG13_CINVX4 +XI6 PULSE_L PULSE_H net9 VDD VSS / RSC_IHPSG13_XOR2X2 +XI79 net020 ECLK VDD VSS / RSC_IHPSG13_CINVX8 +XI63 aclk ACLK_N VDD VSS / RSC_IHPSG13_CINVX8 +XI21 re we cs WEorREandCS VDD VSS / RSC_IHPSG13_OA12X1 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_COLDEC2 ACLK_N ADDR<1> ADDR<0> ADDR_COL<1> ADDR_COL<0> ++ ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ADDR_DEC<2> ++ ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI14<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net6<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net6<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI1<3> PADR<1> PADR<0> addr_n<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<2> PADR<1> NADR<0> addr_n<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<1> NADR<1> PADR<0> addr_n<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<0> NADR<1> NADR<0> addr_n<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI16<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI17<3> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_TIEL +XI17<2> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_TIEL +XI17<1> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_TIEL +XI17<0> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RSC_IHPSG13_NOR2X2 A B Z VDD VSS +MP1 Z B net9 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 net9 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z B VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 Z A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX4_WN A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_BLDRV BLC BLC_SEL BLT BLT_SEL PRE_N SEL_P WR_ONE WR_ZERO ++ VDD VSS +XCDEC SEL_P WR_ZERO BLC_PMOS_DRIVE VDD VSS / RSC_IHPSG13_NAND2X2 +XTDEC SEL_P WR_ONE BLT_PMOS_DRIVE VDD VSS / RSC_IHPSG13_NAND2X2 +MTWN BLT BLT_NMOS_DRIVE VSS VSS sg13_lv_nmos m=1 w=4.82u l=130.00n ++ ng=2 nrd=0 nrs=0 +MCWN BLC BLC_NMOS_DRIVE VSS VSS sg13_lv_nmos m=1 w=4.82u l=130.00n ++ ng=2 nrd=0 nrs=0 +MCWP BLC BLC_PMOS_DRIVE VDD VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 ++ nrd=0 nrs=0 +MTWP BLT BLT_PMOS_DRIVE VDD VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 ++ nrd=0 nrs=0 +MTSP BLT_SEL SEL_N BLT VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 nrd=0 ++ nrs=0 +MTPR BLT PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ng=2 nrd=0 ++ nrs=0 +MCSP BLC_SEL SEL_N BLC VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 nrd=0 ++ nrs=0 +MCPR BLC PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ng=2 nrd=0 ++ nrs=0 +XI86 SEL_P SEL_N VDD VSS / RSC_IHPSG13_INVX2 +XTINV BLC_PMOS_DRIVE BLT_NMOS_DRIVE VDD VSS / RSC_IHPSG13_INVX2 +XCINV BLT_PMOS_DRIVE BLC_NMOS_DRIVE VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RSC_IHPSG13_TIEH Z VDD VSS +MN0 net2 net2 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 Z net2 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_MET3RES A B +R0 B A lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RSC_IHPSG13_DFPQD_MSAFFX2 CP DN DP QN QP VDD VSS +MN12 SN RN DIFFP VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN13 TAIL CP VSS VSS sg13_lv_nmos m=1 w=2.4u l=130.00n ng=2 nrd=0 nrs=0 +MN9 DIFFP DP TAIL VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN10 DIFFN DN TAIL VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN11 RN SN DIFFN VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN19 net33 SN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN20 QN QP net37 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN18 net37 RN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN17 QP QN net33 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP15 SN RN VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP16 RN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP14 DIFFP CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP12 RN SN VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP13 DIFFN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP11 SN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP19 QN QP VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +MP20 QP SN VDD VDD sg13_lv_pmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP18 QN RN VDD VDD sg13_lv_pmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP17 QP QN VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CBUFX2 A Z VDD VSS +MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=540.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=1.1u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_INVX4 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=1.96u l=130.00n ng=2 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_COLCTRL2 A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<3> A_BLC<2> A_BLC<1> ++ A_BLC<0> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_I80 A_WCLK_B_R A_RCLK_B_R net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I44 A_WCLK_B_R A_BM_N A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_ADDR_DEC<2> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_ADDR_DEC<1> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<0> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_R A_RCLK_B_L / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_R A_RCLK_L / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_R A_WCLK_B_L / RSC_IHPSG13_MET3RES +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_I78 A_RCLK_B_R A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_R VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_R A_RCLK_B_R VDD VSS / RSC_IHPSG13_CINVX2 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_COLDRV13_FILL4 VDD VSS +XI0<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_COLDRV13_FILL4C2 VDD VSS +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_1024x16_c2_1P_COLDEC4 ACLK_N ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<3> BIST_ADDR<2> ++ BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI15 ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI14 addr_int ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int net7<0> VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net7<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net7<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net7<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RSC_IHPSG13_AND2X4 A B Z VDD VSS +MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.96u l=130.00n ng=2 nrd=0 nrs=0 +MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_COLCTRL4 A_ADDR_COL A_ADDR_DEC<7> A_ADDR_DEC<6> ++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<15> A_BLC<14> ++ A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> ++ A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<15> A_BLT<14> ++ A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L ++ A_DCLK_B_R A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L ++ A_RCLK_R A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_I80 A_WCLK_B_L A_RCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DO_WRITE_P A_DI_N A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4 +XA_CAPS<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_N0 A_P0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL A_N0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_I81<1> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_BLTMUX<15> A_BLC<15> A_BLC_SEL A_BLT<15> A_BLT_SEL A_PRE_N A_SEL_P<15> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<14> A_BLC<14> A_BLC_SEL A_BLT<14> A_BLT_SEL A_PRE_N A_SEL_P<14> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<13> A_BLC<13> A_BLC_SEL A_BLT<13> A_BLT_SEL A_PRE_N A_SEL_P<13> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<12> A_BLC<12> A_BLC_SEL A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<12> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<11> A_BLC<11> A_BLC_SEL A_BLT<11> A_BLT_SEL A_PRE_N A_SEL_P<11> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<10> A_BLC<10> A_BLC_SEL A_BLT<10> A_BLT_SEL A_PRE_N A_SEL_P<10> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<9> A_BLC<9> A_BLC_SEL A_BLT<9> A_BLT_SEL A_PRE_N A_SEL_P<9> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<8> A_BLC<8> A_BLC_SEL A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<8> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_SEL_P<7> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_SEL_P<6> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_SEL_P<5> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<4> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_SEL_P<3> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_SEL_P<2> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_SEL_P<1> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<0> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net24 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_DEC3INV<15> net23<0> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<1> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<2> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<3> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<4> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<5> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<6> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<7> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<8> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<9> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<10> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<11> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<12> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<13> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<14> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<15> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I70<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_DEC3<15> A_P0 A_ADDR_DEC<7> net23<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<14> A_P0 A_ADDR_DEC<6> net23<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<13> A_P0 A_ADDR_DEC<5> net23<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<12> A_P0 A_ADDR_DEC<4> net23<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<11> A_P0 A_ADDR_DEC<3> net23<4> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<10> A_P0 A_ADDR_DEC<2> net23<5> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<9> A_P0 A_ADDR_DEC<1> net23<6> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<8> A_P0 A_ADDR_DEC<0> net23<7> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<7> A_N0 A_ADDR_DEC<7> net23<8> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<6> A_N0 A_ADDR_DEC<6> net23<9> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<5> A_N0 A_ADDR_DEC<5> net23<10> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<4> A_N0 A_ADDR_DEC<4> net23<11> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<3> A_N0 A_ADDR_DEC<3> net23<12> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<2> A_N0 A_ADDR_DEC<2> net23<13> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<1> A_N0 A_ADDR_DEC<1> net23<14> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<0> A_N0 A_ADDR_DEC<0> net23<15> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS + + +.SUBCKT RM_IHPSG13_1024x16_c2_1P_COLDEC3 ACLK_N ADDR<2> ADDR<1> ADDR<0> ADDR_COL<1> ++ ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ++ ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> ++ BIST_EN_I VDD VSS +XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net6<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net6<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net6<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_COLCTRL3 A_ADDR_DEC<7> A_ADDR_DEC<6> A_ADDR_DEC<5> ++ A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> A_ADDR_DEC<0> ++ A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> ++ A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> ++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R A_DCLK_L ++ A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R A_TIEH_O ++ A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_R A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_I70<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I44 A_BM_N A_WCLK_B_R A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_ADDR_DEC<7> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_ADDR_DEC<6> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_ADDR_DEC<5> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_ADDR_DEC<4> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_ADDR_DEC<2> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_ADDR_DEC<1> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<0> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I80 A_WCLK_B_R A_RCLK_B_R net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_CORNER VDD_CORE VSS +XI16 VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_1P_BITKIT_CORNER +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_LR A_WL B_WL NW PW VDD VSS +MN1 VSS A_WL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN0 VSS B_WL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_EDGE_LR A_WL<15> A_WL<14> A_WL<13> A_WL<12> ++ A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> ++ A_WL<2> A_WL<1> A_WL<0> B_WL<15> B_WL<14> B_WL<13> B_WL<12> B_WL<11> ++ B_WL<10> B_WL<9> B_WL<8> B_WL<7> B_WL<6> B_WL<5> B_WL<4> B_WL<3> B_WL<2> ++ B_WL<1> B_WL<0> VDD_CORE VSS +XI0<15> A_WL<15> B_WL<15> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_LR +XI0<14> A_WL<14> B_WL<14> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_LR +XI0<13> A_WL<13> B_WL<13> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_LR +XI0<12> A_WL<12> B_WL<12> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_LR +XI0<11> A_WL<11> B_WL<11> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_LR +XI0<10> A_WL<10> B_WL<10> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_LR +XI0<9> A_WL<9> B_WL<9> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_LR +XI0<8> A_WL<8> B_WL<8> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_LR +XI0<7> A_WL<7> B_WL<7> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_LR +XI0<6> A_WL<6> B_WL<6> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_LR +XI0<5> A_WL<5> B_WL<5> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_LR +XI0<4> A_WL<4> B_WL<4> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_LR +XI0<3> A_WL<3> B_WL<3> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_LR +XI0<2> A_WL<2> B_WL<2> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_LR +XI0<1> A_WL<1> B_WL<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_LR +XI0<0> A_WL<0> B_WL<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_LR +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL A_BLC_BOT A_BLC_TOP A_BLT_BOT A_BLT_TOP ++ A_LWL A_RWL B_BLC_BOT B_BLC_TOP B_BLT_BOT B_BLT_TOP B_LWL B_RWL NW PW VDD VSS +MN5 NC B_RWL B_BLC_BOT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN4 B_BLT_BOT B_LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN0 NC NT VSS PW sg13_lv_nmos m=1 w=600.0n l=130.00n ng=2 nrd=0 nrs=0 +MN1 NT NC VSS PW sg13_lv_nmos m=1 w=600.0n l=130.00n ng=2 nrd=0 nrs=0 +MN3 NC A_RWL A_BLC_TOP PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN2 A_BLT_TOP A_LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MP1 NT NC VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 NC NT VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +R5 B_RWL B_LWL lvsres w=2.6e-07 l=6e-07 +R4 B_BLC_BOT B_BLC_TOP lvsres w=2.6e-07 l=6e-07 +R3 B_BLT_BOT B_BLT_TOP lvsres w=2.6e-07 l=6e-07 +R1 A_BLC_BOT A_BLC_TOP lvsres w=2.6e-07 l=6e-07 +R0 A_BLT_BOT A_BLT_TOP lvsres w=2.6e-07 l=6e-07 +R2 A_RWL A_LWL lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_SRAM A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> ++ A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<15> ++ A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> ++ A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> ++ A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> ++ A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> B_BLC_BOT<1> ++ B_BLC_BOT<0> B_BLC_TOP<1> B_BLC_TOP<0> B_BLT_BOT<1> B_BLT_BOT<0> ++ B_BLT_TOP<1> B_BLT_TOP<0> B_LWL<15> B_LWL<14> B_LWL<13> B_LWL<12> B_LWL<11> ++ B_LWL<10> B_LWL<9> B_LWL<8> B_LWL<7> B_LWL<6> B_LWL<5> B_LWL<4> B_LWL<3> ++ B_LWL<2> B_LWL<1> B_LWL<0> B_RWL<15> B_RWL<14> B_RWL<13> B_RWL<12> B_RWL<11> ++ B_RWL<10> B_RWL<9> B_RWL<8> B_RWL<7> B_RWL<6> B_RWL<5> B_RWL<4> B_RWL<3> ++ B_RWL<2> B_RWL<1> B_RWL<0> VDD_CORE VSS +XCELL<31> A_BLC_TOP<1> A_RBLC<15> A_BLT_TOP<1> A_RBLT<15> A_XWL<15> A_RWL<15> ++ B_BLC_TOP<1> B_RBLC<15> B_BLT_TOP<1> B_RBLT<15> B_XWL<15> B_RWL<15> ++ VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL +XCELL<30> A_RBLC<14> A_RBLC<15> A_RBLT<14> A_RBLT<15> A_XWL<14> A_RWL<14> ++ B_RBLC<14> B_RBLC<15> B_RBLT<14> B_RBLT<15> B_XWL<14> B_RWL<14> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL +XCELL<29> A_RBLC<14> A_RBLC<13> A_RBLT<14> A_RBLT<13> A_XWL<13> A_RWL<13> ++ B_RBLC<14> B_RBLC<13> B_RBLT<14> B_RBLT<13> B_XWL<13> B_RWL<13> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL +XCELL<28> A_RBLC<12> A_RBLC<13> A_RBLT<12> A_RBLT<13> A_XWL<12> A_RWL<12> ++ B_RBLC<12> B_RBLC<13> B_RBLT<12> B_RBLT<13> B_XWL<12> B_RWL<12> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL +XCELL<27> A_RBLC<12> A_RBLC<11> A_RBLT<12> A_RBLT<11> A_XWL<11> A_RWL<11> ++ B_RBLC<12> B_RBLC<11> B_RBLT<12> B_RBLT<11> B_XWL<11> B_RWL<11> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL +XCELL<26> A_RBLC<10> A_RBLC<11> A_RBLT<10> A_RBLT<11> A_XWL<10> A_RWL<10> ++ B_RBLC<10> B_RBLC<11> B_RBLT<10> B_RBLT<11> B_XWL<10> B_RWL<10> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL +XCELL<25> A_RBLC<10> A_RBLC<9> A_RBLT<10> A_RBLT<9> A_XWL<9> A_RWL<9> ++ B_RBLC<10> B_RBLC<9> B_RBLT<10> B_RBLT<9> B_XWL<9> B_RWL<9> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL +XCELL<24> A_RBLC<8> A_RBLC<9> A_RBLT<8> A_RBLT<9> A_XWL<8> A_RWL<8> B_RBLC<8> ++ B_RBLC<9> B_RBLT<8> B_RBLT<9> B_XWL<8> B_RWL<8> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL +XCELL<23> A_RBLC<8> A_RBLC<7> A_RBLT<8> A_RBLT<7> A_XWL<7> A_RWL<7> B_RBLC<8> ++ B_RBLC<7> B_RBLT<8> B_RBLT<7> B_XWL<7> B_RWL<7> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL +XCELL<22> A_RBLC<6> A_RBLC<7> A_RBLT<6> A_RBLT<7> A_XWL<6> A_RWL<6> B_RBLC<6> ++ B_RBLC<7> B_RBLT<6> B_RBLT<7> B_XWL<6> B_RWL<6> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL +XCELL<21> A_RBLC<6> A_RBLC<5> A_RBLT<6> A_RBLT<5> A_XWL<5> A_RWL<5> B_RBLC<6> ++ B_RBLC<5> B_RBLT<6> B_RBLT<5> B_XWL<5> B_RWL<5> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL +XCELL<20> A_RBLC<4> A_RBLC<5> A_RBLT<4> A_RBLT<5> A_XWL<4> A_RWL<4> B_RBLC<4> ++ B_RBLC<5> B_RBLT<4> B_RBLT<5> B_XWL<4> B_RWL<4> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL +XCELL<19> A_RBLC<4> A_RBLC<3> A_RBLT<4> A_RBLT<3> A_XWL<3> A_RWL<3> B_RBLC<4> ++ B_RBLC<3> B_RBLT<4> B_RBLT<3> B_XWL<3> B_RWL<3> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL +XCELL<18> A_RBLC<2> A_RBLC<3> A_RBLT<2> A_RBLT<3> A_XWL<2> A_RWL<2> B_RBLC<2> ++ B_RBLC<3> B_RBLT<2> B_RBLT<3> B_XWL<2> B_RWL<2> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL +XCELL<17> A_RBLC<2> A_RBLC<1> A_RBLT<2> A_RBLT<1> A_XWL<1> A_RWL<1> B_RBLC<2> ++ B_RBLC<1> B_RBLT<2> B_RBLT<1> B_XWL<1> B_RWL<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL +XCELL<16> A_BLC_BOT<1> A_RBLC<1> A_BLT_BOT<1> A_RBLT<1> A_XWL<0> A_RWL<0> ++ B_BLC_BOT<1> B_RBLC<1> B_BLT_BOT<1> B_RBLT<1> B_XWL<0> B_RWL<0> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL +XCELL<15> A_BLC_TOP<0> A_LBLC<15> A_BLT_TOP<0> A_LBLT<15> A_LWL<15> A_XWL<15> ++ B_BLC_TOP<0> B_LBLC<15> B_BLT_TOP<0> B_LBLT<15> B_LWL<15> B_XWL<15> ++ VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL +XCELL<14> A_LBLC<14> A_LBLC<15> A_LBLT<14> A_LBLT<15> A_LWL<14> A_XWL<14> ++ B_LBLC<14> B_LBLC<15> B_LBLT<14> B_LBLT<15> B_LWL<14> B_XWL<14> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL +XCELL<13> A_LBLC<14> A_LBLC<13> A_LBLT<14> A_LBLT<13> A_LWL<13> A_XWL<13> ++ B_LBLC<14> B_LBLC<13> B_LBLT<14> B_LBLT<13> B_LWL<13> B_XWL<13> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL +XCELL<12> A_LBLC<12> A_LBLC<13> A_LBLT<12> A_LBLT<13> A_LWL<12> A_XWL<12> ++ B_LBLC<12> B_LBLC<13> B_LBLT<12> B_LBLT<13> B_LWL<12> B_XWL<12> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL +XCELL<11> A_LBLC<12> A_LBLC<11> A_LBLT<12> A_LBLT<11> A_LWL<11> A_XWL<11> ++ B_LBLC<12> B_LBLC<11> B_LBLT<12> B_LBLT<11> B_LWL<11> B_XWL<11> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL +XCELL<10> A_LBLC<10> A_LBLC<11> A_LBLT<10> A_LBLT<11> A_LWL<10> A_XWL<10> ++ B_LBLC<10> B_LBLC<11> B_LBLT<10> B_LBLT<11> B_LWL<10> B_XWL<10> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL +XCELL<9> A_LBLC<10> A_LBLC<9> A_LBLT<10> A_LBLT<9> A_LWL<9> A_XWL<9> ++ B_LBLC<10> B_LBLC<9> B_LBLT<10> B_LBLT<9> B_LWL<9> B_XWL<9> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL +XCELL<8> A_LBLC<8> A_LBLC<9> A_LBLT<8> A_LBLT<9> A_LWL<8> A_XWL<8> B_LBLC<8> ++ B_LBLC<9> B_LBLT<8> B_LBLT<9> B_LWL<8> B_XWL<8> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL +XCELL<7> A_LBLC<8> A_LBLC<7> A_LBLT<8> A_LBLT<7> A_LWL<7> A_XWL<7> B_LBLC<8> ++ B_LBLC<7> B_LBLT<8> B_LBLT<7> B_LWL<7> B_XWL<7> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL +XCELL<6> A_LBLC<6> A_LBLC<7> A_LBLT<6> A_LBLT<7> A_LWL<6> A_XWL<6> B_LBLC<6> ++ B_LBLC<7> B_LBLT<6> B_LBLT<7> B_LWL<6> B_XWL<6> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL +XCELL<5> A_LBLC<6> A_LBLC<5> A_LBLT<6> A_LBLT<5> A_LWL<5> A_XWL<5> B_LBLC<6> ++ B_LBLC<5> B_LBLT<6> B_LBLT<5> B_LWL<5> B_XWL<5> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL +XCELL<4> A_LBLC<4> A_LBLC<5> A_LBLT<4> A_LBLT<5> A_LWL<4> A_XWL<4> B_LBLC<4> ++ B_LBLC<5> B_LBLT<4> B_LBLT<5> B_LWL<4> B_XWL<4> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL +XCELL<3> A_LBLC<4> A_LBLC<3> A_LBLT<4> A_LBLT<3> A_LWL<3> A_XWL<3> B_LBLC<4> ++ B_LBLC<3> B_LBLT<4> B_LBLT<3> B_LWL<3> B_XWL<3> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL +XCELL<2> A_LBLC<2> A_LBLC<3> A_LBLT<2> A_LBLT<3> A_LWL<2> A_XWL<2> B_LBLC<2> ++ B_LBLC<3> B_LBLT<2> B_LBLT<3> B_LWL<2> B_XWL<2> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL +XCELL<1> A_LBLC<2> A_LBLC<1> A_LBLT<2> A_LBLT<1> A_LWL<1> A_XWL<1> B_LBLC<2> ++ B_LBLC<1> B_LBLT<2> B_LBLT<1> B_LWL<1> B_XWL<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL +XCELL<0> A_BLC_BOT<0> A_LBLC<1> A_BLT_BOT<0> A_LBLT<1> A_LWL<0> A_XWL<0> ++ B_BLC_BOT<0> B_LBLC<1> B_BLT_BOT<0> B_LBLT<1> B_LWL<0> B_XWL<0> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_TB A_BLC A_BLT B_BLC B_BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_EDGE_TB A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ B_BLC<1> B_BLC<0> B_BLT<1> B_BLT<0> VDD_CORE VSS +XEDGE<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_TB +XEDGE<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_TB +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_BITKIT_TAP A_BLC A_BLT B_BLC B_BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_TAP A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ B_BLC<1> B_BLC<0> B_BLT<1> B_BLT<0> VDD_CORE VSS +XIEDGEBP_COL1<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_TB +XIEDGEBP_COL1<0> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_TB +XIEDGEBP_COL2<1> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_TB +XIEDGEBP_COL2<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_TB +XITAP<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_TAP +XITAP<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_TAP +.ENDS + + +.SUBCKT RM_IHPSG13_1024x16_c2_1P_BITKIT_TAP_LR NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_TAP_LR VDD_CORE VSS +XCORNER<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_1P_BITKIT_CORNER +XCORNER<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_1P_BITKIT_CORNER +XTAP_BORDER VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_1P_BITKIT_TAP_LR +.ENDS + +.SUBCKT RSC_IHPSG13_CBUFX12 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=4.23u l=130.00n ng=6 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=9.72u l=130.00n ng=6 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_COLDRV13X12 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX12 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=9.72u l=130.00n ng=6 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_WLDRV16X12 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX12 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_DEC04 ADDR<3> ADDR<2> ADDR<1> ADDR<0> CS ECLK_H_BOT ++ ECLK_H_TOP ECLK_L_BOT ECLK_L_TOP WL<15> WL<14> WL<13> WL<12> WL<11> WL<10> ++ WL<9> WL<8> WL<7> WL<6> WL<5> WL<4> WL<3> WL<2> WL<1> WL<0> VDD VSS +XI0<3> PADR<1> PADR<0> sel01<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<2> PADR<1> NADR<0> sel01<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<1> NADR<1> PADR<0> sel01<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<0> NADR<1> NADR<0> sel01<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI4 ECLK_L_BOT EN VDD VSS / RSC_IHPSG13_CINVX4 +XI5 ECLK_H_BOT ECLK_L_BOT VDD VSS / RSC_IHPSG13_CINVX2 +XI3<3> PADR<3> NADR<3> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> PADR<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> PADR<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> PADR<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XR0 ECLK_H_BOT ECLK_H_TOP / RSC_IHPSG13_MET2RES +XI11 ECLK_L_BOT ECLK_L_TOP / RSC_IHPSG13_MET2RES +XI1<3> PADR<2> PADR<3> CS sel23<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<2> PADR<3> CS sel23<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<2> NADR<3> CS sel23<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<2> NADR<3> CS sel23<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI2<15> sel23<3> sel01<3> EN WL<15> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<14> sel23<3> sel01<2> EN WL<14> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<13> sel23<3> sel01<1> EN WL<13> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<12> sel23<3> sel01<0> EN WL<12> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<11> sel23<2> sel01<3> EN WL<11> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<10> sel23<2> sel01<2> EN WL<10> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<9> sel23<2> sel01<1> EN WL<9> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<8> sel23<2> sel01<0> EN WL<8> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<7> sel23<1> sel01<3> EN WL<7> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<6> sel23<1> sel01<2> EN WL<6> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<5> sel23<1> sel01<1> EN WL<5> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<4> sel23<1> sel01<0> EN WL<4> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<3> sel23<0> sel01<3> EN WL<3> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<2> sel23<0> sel01<2> EN WL<2> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<1> sel23<0> sel01<1> EN WL<1> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<0> sel23<0> sel01<0> EN WL<0> VDD VSS / RSC_IHPSG13_NOR3X2 +XCAPS4 VDD VSS / RSC_IHPSG13_FILLCAP4 +XLATCH<3> CS ADDR<3> PADR<3> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<2> CS ADDR<2> PADR<2> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<1> CS ADDR<1> PADR<1> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<0> CS ADDR<0> PADR<0> VDD VSS / RSC_IHPSG13_LHPQX2 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_DEC02 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC ADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI2<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI2<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_DEC01 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC NADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI2<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI2<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_DEC00 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC NADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV<1> ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +XADDRINV<0> ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_DEC03 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC ADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_ROWDEC9 ADDR_N_I<8> ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ++ ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ++ WL_O<511> WL_O<510> WL_O<509> WL_O<508> WL_O<507> WL_O<506> WL_O<505> ++ WL_O<504> WL_O<503> WL_O<502> WL_O<501> WL_O<500> WL_O<499> WL_O<498> ++ WL_O<497> WL_O<496> WL_O<495> WL_O<494> WL_O<493> WL_O<492> WL_O<491> ++ WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> WL_O<484> ++ WL_O<483> WL_O<482> WL_O<481> WL_O<480> WL_O<479> WL_O<478> WL_O<477> ++ WL_O<476> WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> ++ WL_O<469> WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> WL_O<463> ++ WL_O<462> WL_O<461> WL_O<460> WL_O<459> WL_O<458> WL_O<457> WL_O<456> ++ WL_O<455> WL_O<454> WL_O<453> WL_O<452> WL_O<451> WL_O<450> WL_O<449> ++ WL_O<448> WL_O<447> WL_O<446> WL_O<445> WL_O<444> WL_O<443> WL_O<442> ++ WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> WL_O<436> WL_O<435> ++ WL_O<434> WL_O<433> WL_O<432> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> WL_O<415> WL_O<414> ++ WL_O<413> WL_O<412> WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> ++ WL_O<406> WL_O<405> WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> ++ WL_O<399> WL_O<398> WL_O<397> WL_O<396> WL_O<395> WL_O<394> WL_O<393> ++ WL_O<392> WL_O<391> WL_O<390> WL_O<389> WL_O<388> WL_O<387> WL_O<386> ++ WL_O<385> WL_O<384> WL_O<383> WL_O<382> WL_O<381> WL_O<380> WL_O<379> ++ WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> WL_O<372> ++ WL_O<371> WL_O<370> WL_O<369> WL_O<368> WL_O<367> WL_O<366> WL_O<365> ++ WL_O<364> WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> ++ WL_O<357> WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> WL_O<351> ++ WL_O<350> WL_O<349> WL_O<348> WL_O<347> WL_O<346> WL_O<345> WL_O<344> ++ WL_O<343> WL_O<342> WL_O<341> WL_O<340> WL_O<339> WL_O<338> WL_O<337> ++ WL_O<336> WL_O<335> WL_O<334> WL_O<333> WL_O<332> WL_O<331> WL_O<330> ++ WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> WL_O<324> WL_O<323> ++ WL_O<322> WL_O<321> WL_O<320> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> WL_O<303> WL_O<302> ++ WL_O<301> WL_O<300> WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> ++ WL_O<294> WL_O<293> WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> ++ WL_O<287> WL_O<286> WL_O<285> WL_O<284> WL_O<283> WL_O<282> WL_O<281> ++ WL_O<280> WL_O<279> WL_O<278> WL_O<277> WL_O<276> WL_O<275> WL_O<274> ++ WL_O<273> WL_O<272> WL_O<271> WL_O<270> WL_O<269> WL_O<268> WL_O<267> ++ WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> WL_O<260> ++ WL_O<259> WL_O<258> WL_O<257> WL_O<256> WL_O<255> WL_O<254> WL_O<253> ++ WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> ++ WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> WL_O<239> ++ WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> WL_O<233> WL_O<232> ++ WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> WL_O<226> WL_O<225> ++ WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> WL_O<219> WL_O<218> ++ WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> WL_O<212> WL_O<211> ++ WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> WL_O<191> WL_O<190> ++ WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> ++ WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> ++ WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> WL_O<170> WL_O<169> ++ WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> WL_O<163> WL_O<162> ++ WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> WL_O<156> WL_O<155> ++ WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> WL_O<148> ++ WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> WL_O<142> WL_O<141> ++ WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> ++ WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> WL_O<127> ++ WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> ++ WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> ++ WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> ++ WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> ++ WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XSEL<31> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<31> ECLK_H<31> ++ ECLK_H<32> ECLK_B<31> ECLK_B<32> WL_O<511> WL_O<510> WL_O<509> WL_O<508> ++ WL_O<507> WL_O<506> WL_O<505> WL_O<504> WL_O<503> WL_O<502> WL_O<501> ++ WL_O<500> WL_O<499> WL_O<498> WL_O<497> WL_O<496> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<30> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<30> ECLK_H<30> ++ ECLK_H<31> ECLK_B<30> ECLK_B<31> WL_O<495> WL_O<494> WL_O<493> WL_O<492> ++ WL_O<491> WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> ++ WL_O<484> WL_O<483> WL_O<482> WL_O<481> WL_O<480> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<29> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<29> ECLK_H<29> ++ ECLK_H<30> ECLK_B<29> ECLK_B<30> WL_O<479> WL_O<478> WL_O<477> WL_O<476> ++ WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> WL_O<469> ++ WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<28> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<28> ECLK_H<28> ++ ECLK_H<29> ECLK_B<28> ECLK_B<29> WL_O<463> WL_O<462> WL_O<461> WL_O<460> ++ WL_O<459> WL_O<458> WL_O<457> WL_O<456> WL_O<455> WL_O<454> WL_O<453> ++ WL_O<452> WL_O<451> WL_O<450> WL_O<449> WL_O<448> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<27> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<27> ECLK_H<27> ++ ECLK_H<28> ECLK_B<27> ECLK_B<28> WL_O<447> WL_O<446> WL_O<445> WL_O<444> ++ WL_O<443> WL_O<442> WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> ++ WL_O<436> WL_O<435> WL_O<434> WL_O<433> WL_O<432> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<26> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<26> ECLK_H<26> ++ ECLK_H<27> ECLK_B<26> ECLK_B<27> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<25> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<25> ECLK_H<25> ++ ECLK_H<26> ECLK_B<25> ECLK_B<26> WL_O<415> WL_O<414> WL_O<413> WL_O<412> ++ WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> WL_O<406> WL_O<405> ++ WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<24> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<24> ECLK_H<24> ++ ECLK_H<25> ECLK_B<24> ECLK_B<25> WL_O<399> WL_O<398> WL_O<397> WL_O<396> ++ WL_O<395> WL_O<394> WL_O<393> WL_O<392> WL_O<391> WL_O<390> WL_O<389> ++ WL_O<388> WL_O<387> WL_O<386> WL_O<385> WL_O<384> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<23> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<23> ECLK_H<23> ++ ECLK_H<24> ECLK_B<23> ECLK_B<24> WL_O<383> WL_O<382> WL_O<381> WL_O<380> ++ WL_O<379> WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> ++ WL_O<372> WL_O<371> WL_O<370> WL_O<369> WL_O<368> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<22> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<22> ECLK_H<22> ++ ECLK_H<23> ECLK_B<22> ECLK_B<23> WL_O<367> WL_O<366> WL_O<365> WL_O<364> ++ WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> WL_O<357> ++ WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<21> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<21> ECLK_H<21> ++ ECLK_H<22> ECLK_B<21> ECLK_B<22> WL_O<351> WL_O<350> WL_O<349> WL_O<348> ++ WL_O<347> WL_O<346> WL_O<345> WL_O<344> WL_O<343> WL_O<342> WL_O<341> ++ WL_O<340> WL_O<339> WL_O<338> WL_O<337> WL_O<336> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<20> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<20> ECLK_H<20> ++ ECLK_H<21> ECLK_B<20> ECLK_B<21> WL_O<335> WL_O<334> WL_O<333> WL_O<332> ++ WL_O<331> WL_O<330> WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> ++ WL_O<324> WL_O<323> WL_O<322> WL_O<321> WL_O<320> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<19> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<19> ECLK_H<19> ++ ECLK_H<20> ECLK_B<19> ECLK_B<20> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<18> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<18> ECLK_H<18> ++ ECLK_H<19> ECLK_B<18> ECLK_B<19> WL_O<303> WL_O<302> WL_O<301> WL_O<300> ++ WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> WL_O<294> WL_O<293> ++ WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<17> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<17> ECLK_H<17> ++ ECLK_H<18> ECLK_B<17> ECLK_B<18> WL_O<287> WL_O<286> WL_O<285> WL_O<284> ++ WL_O<283> WL_O<282> WL_O<281> WL_O<280> WL_O<279> WL_O<278> WL_O<277> ++ WL_O<276> WL_O<275> WL_O<274> WL_O<273> WL_O<272> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<16> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<16> ECLK_H<16> ++ ECLK_H<17> ECLK_B<16> ECLK_B<17> WL_O<271> WL_O<270> WL_O<269> WL_O<268> ++ WL_O<267> WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> ++ WL_O<260> WL_O<259> WL_O<258> WL_O<257> WL_O<256> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04 +XDEC10<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<6> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC02 +XDEC10<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<2> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC02 +XDEC10<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<30> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC02 +XDEC10<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<26> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC02 +XDEC10<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<22> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC02 +XDEC10<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<18> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<14> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<10> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<6> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<2> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC02 +XDEC01<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC01 +XDEC01<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<5> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC01 +XDEC01<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<1> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC01 +XDEC01<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<29> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC01 +XDEC01<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<25> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC01 +XDEC01<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<21> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC01 +XDEC01<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<17> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<13> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<9> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<5> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<1> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC01 +XL2<258> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<257> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<256> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<255> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<254> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<253> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<252> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<251> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<250> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<249> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<248> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<247> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<246> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<245> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<244> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<243> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<242> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<241> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<240> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<239> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<238> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<237> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<236> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<235> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<234> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<233> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<232> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<231> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<230> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<229> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<228> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<227> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<226> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<225> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<224> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<223> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<222> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<221> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<220> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<219> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<218> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<217> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<216> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<215> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<214> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<213> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<212> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<211> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<210> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<209> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<208> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<207> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<206> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<205> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<204> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<203> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<202> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<201> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<200> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<199> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<198> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<197> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<196> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<195> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<194> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<193> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<192> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<191> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<190> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<189> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<188> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<187> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<186> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<185> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<184> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<183> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<182> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<181> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<180> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<179> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<178> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<177> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<176> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<175> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<174> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<173> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<172> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<171> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<170> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<169> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<168> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<167> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<166> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<165> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<164> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<163> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<162> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<161> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<160> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<159> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<158> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<157> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<156> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<155> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<154> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<153> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<152> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<151> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<150> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<149> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<148> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<147> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<146> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<145> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<144> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<143> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<142> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<141> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<140> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<139> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<138> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<137> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<136> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<135> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<134> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<133> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC00<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC00 +XDEC00<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<4> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC00 +XDEC00<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<0> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC00 +XDEC00<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<28> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC00 +XDEC00<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<24> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC00 +XDEC00<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<20> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC00 +XDEC00<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<16> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<12> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<8> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<4> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<0> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC00 +XDEC11<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<7> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC03 +XDEC11<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<3> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC03 +XDEC11<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<31> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC03 +XDEC11<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<27> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC03 +XDEC11<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<23> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC03 +XDEC11<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<19> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<15> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<11> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<7> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<3> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC03 +XI0 ADDR_N_I<9> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_ROWREG9 ACLK_N_I ADDR_I<8> ADDR_I<7> ADDR_I<6> ADDR_I<5> ++ ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<8> ADDR_N_O<7> ++ ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ++ ADDR_N_O<0> BIST_ADDR_I<8> BIST_ADDR_I<7> BIST_ADDR_I<6> BIST_ADDR_I<5> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XDFF<8> BIST_EN_I BIST_ADDR_I<8> ACLK_N_I ADDR_I<8> q_int<8> net04<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net04<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net04<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net04<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net04<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net04<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net04<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net04<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net04<8> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDRV<8> qn_int<8> ADDR_N_O<8> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XINV<8> q_int<8> qn_int<8> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +.ENDS + +.SUBCKT RM_IHPSG13_1024x16_c2_2P_DLY_MUX A SEL Z VDD VSS +XI11 net4 Z VDD VSS / RSC_IHPSG13_CINVX2 +XI8 A D<3> SEL net4 VDD VSS / RSC_IHPSG13_MX2IX1 +XI20<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_CTRL ACLK_N BIST_CK_I BIST_CS_I BIST_EN BIST_RE_I ++ BIST_WE_I B_TIEL_O CK_I CS_I DCLK ECLK PULSE_H PULSE_L PULSE_O RCLK RE_I ++ ROW_CS WCLK WE_I VDD VSS +XI17 ck_regs we col_we VDD VSS / RSC_IHPSG13_DFNQX2 +XI16 ck_regs re col_re VDD VSS / RSC_IHPSG13_DFNQX2 +XI18 ck_regs cs net7 VDD VSS / RSC_IHPSG13_DFNQX2 +XI71 ACLK_N net012 PULSE_O VDD VSS / RSC_IHPSG13_DFNQX2 +XI77 col_we net017 net016 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI76 col_re net017 net018 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI15 ck_dly WEorREandCS aclk VDD VSS / RSC_IHPSG13_CGATEPX4 +XI14 ck WEandCS DCLK VDD VSS / RSC_IHPSG13_CGATEPX4 +XI60 net7 ROW_CS VDD VSS / RSC_IHPSG13_CBUFX8 +XI73 PULSE_O net012 VDD VSS / RSC_IHPSG13_CINVX2 +XI8 net017 net8 VDD VSS / RSC_IHPSG13_CINVX2 +XCAPS4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XBM_TIEL B_TIEL_O VDD VSS / RSC_IHPSG13_TIEL +XI64 ck ck_dly VDD VSS / RSC_IHPSG13_CDLYX2 +XI86 CS_I BIST_CS_I BIST_EN cs VDD VSS / RSC_IHPSG13_MX2X2 +XI87 CK_I BIST_CK_I BIST_EN ck VDD VSS / RSC_IHPSG13_MX2X2 +XI85 WE_I BIST_WE_I BIST_EN we VDD VSS / RSC_IHPSG13_MX2X2 +XI84 RE_I BIST_RE_I BIST_EN re VDD VSS / RSC_IHPSG13_MX2X2 +XI48 ck_dly ck_regs VDD VSS / RSC_IHPSG13_CINVX4 +XI81 net016 WCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI80 net018 RCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI78 net8 net020 VDD VSS / RSC_IHPSG13_CINVX4 +XCAPS8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI6 PULSE_L PULSE_H net017 VDD VSS / RSC_IHPSG13_XOR2X2 +XI22 we cs WEandCS VDD VSS / RSC_IHPSG13_AND2X2 +XI79 net020 ECLK VDD VSS / RSC_IHPSG13_CINVX8 +XI63 aclk ACLK_N VDD VSS / RSC_IHPSG13_CINVX8 +XI21 re we cs WEorREandCS VDD VSS / RSC_IHPSG13_OA12X1 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_COLDEC5 ACLK_N ADDR<4> ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<4> BIST_ADDR<3> ++ BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<4> BIST_EN_I BIST_ADDR<4> ACLK_N ADDR<4> addr_int<1> net13<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int<0> net13<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net13<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net13<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net13<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI15<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI15<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI15<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> addr_int<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_CBUFX2 +XI13<0> addr_int<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XI14<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_BLDRV A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL ++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> ++ A_SEL_P<1> A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> ++ B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> ++ B_SEL_P<2> B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS +MA_CWN<3> A_BLC<3> A_BLC_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CWN<2> A_BLC<2> A_BLC_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CWN<1> A_BLC<1> A_BLC_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CWN<0> A_BLC<0> A_BLC_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<3> A_BLT<3> A_BLT_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<2> A_BLT<2> A_BLT_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<1> A_BLT<1> A_BLT_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<0> A_BLT<0> A_BLT_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<3> B_BLT<3> B_BLT_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<2> B_BLT<2> B_BLT_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<1> B_BLT<1> B_BLT_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<0> B_BLT<0> B_BLT_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<3> B_BLC<3> B_BLC_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<2> B_BLC<2> B_BLC_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<1> B_BLC<1> B_BLC_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<0> B_BLC<0> B_BLC_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CPR<3> A_BLC<3> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_CPR<2> A_BLC<2> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_CPR<1> A_BLC<1> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_CPR<0> A_BLC<0> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TWP<3> A_BLT<3> A_BLT_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TWP<2> A_BLT<2> A_BLT_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TWP<1> A_BLT<1> A_BLT_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TWP<0> A_BLT<0> A_BLT_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<3> A_BLC<3> A_BLC_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<2> A_BLC<2> A_BLC_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<1> A_BLC<1> A_BLC_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<0> A_BLC<0> A_BLC_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TPR<3> A_BLT<3> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TPR<2> A_BLT<2> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TPR<1> A_BLT<1> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TPR<0> A_BLT<0> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TSP<3> A_BLT_SEL A_SEL_N<3> A_BLT<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TSP<2> A_BLT_SEL A_SEL_N<2> A_BLT<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TSP<1> A_BLT_SEL A_SEL_N<1> A_BLT<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TSP<0> A_BLT_SEL A_SEL_N<0> A_BLT<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<3> A_BLC_SEL A_SEL_N<3> A_BLC<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<2> A_BLC_SEL A_SEL_N<2> A_BLC<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<1> A_BLC_SEL A_SEL_N<1> A_BLC<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<0> A_BLC_SEL A_SEL_N<0> A_BLC<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<3> B_BLC<3> B_BLC_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<2> B_BLC<2> B_BLC_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<1> B_BLC<1> B_BLC_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<0> B_BLC<0> B_BLC_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<3> B_BLT<3> B_BLT_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<2> B_BLT<2> B_BLT_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<1> B_BLT<1> B_BLT_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<0> B_BLT<0> B_BLT_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<3> B_BLT_SEL B_SEL_N<3> B_BLT<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<2> B_BLT_SEL B_SEL_N<2> B_BLT<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<1> B_BLT_SEL B_SEL_N<1> B_BLT<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<0> B_BLT_SEL B_SEL_N<0> B_BLT<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TPR<3> B_BLT<3> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_TPR<2> B_BLT<2> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_TPR<1> B_BLT<1> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_TPR<0> B_BLT<0> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CSP<3> B_BLC_SEL B_SEL_N<3> B_BLC<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CSP<2> B_BLC_SEL B_SEL_N<2> B_BLC<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CSP<1> B_BLC_SEL B_SEL_N<1> B_BLC<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CSP<0> B_BLC_SEL B_SEL_N<0> B_BLC<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CPR<3> B_BLC<3> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CPR<2> B_BLC<2> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CPR<1> B_BLC<1> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CPR<0> B_BLC<0> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +XA_SEL<3> A_SEL_P<3> A_SEL_N<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_SEL<2> A_SEL_P<2> A_SEL_N<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_SEL<1> A_SEL_P<1> A_SEL_N<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_SEL<0> A_SEL_P<0> A_SEL_N<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_CINV<3> A_BLT_PMOS_DRIVE<3> A_BLC_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_CINV<2> A_BLT_PMOS_DRIVE<2> A_BLC_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_CINV<1> A_BLT_PMOS_DRIVE<1> A_BLC_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_CINV<0> A_BLT_PMOS_DRIVE<0> A_BLC_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<3> A_BLC_PMOS_DRIVE<3> A_BLT_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<2> A_BLC_PMOS_DRIVE<2> A_BLT_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<1> A_BLC_PMOS_DRIVE<1> A_BLT_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<0> A_BLC_PMOS_DRIVE<0> A_BLT_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_SEL<3> B_SEL_P<3> B_SEL_N<3> VDD VSS / RSC_IHPSG13_INVX2 +XB_SEL<2> B_SEL_P<2> B_SEL_N<2> VDD VSS / RSC_IHPSG13_INVX2 +XB_SEL<1> B_SEL_P<1> B_SEL_N<1> VDD VSS / RSC_IHPSG13_INVX2 +XB_SEL<0> B_SEL_P<0> B_SEL_N<0> VDD VSS / RSC_IHPSG13_INVX2 +XB_TINV<3> B_BLC_PMOS_DRIVE<3> B_BLT_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_TINV<2> B_BLC_PMOS_DRIVE<2> B_BLT_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_TINV<1> B_BLC_PMOS_DRIVE<1> B_BLT_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_TINV<0> B_BLC_PMOS_DRIVE<0> B_BLT_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<3> B_BLT_PMOS_DRIVE<3> B_BLC_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<2> B_BLT_PMOS_DRIVE<2> B_BLC_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<1> B_BLT_PMOS_DRIVE<1> B_BLC_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<0> B_BLT_PMOS_DRIVE<0> B_BLC_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TDEC<3> A_SEL_P<3> A_WR_ONE A_BLT_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_TDEC<2> A_SEL_P<2> A_WR_ONE A_BLT_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_TDEC<1> A_SEL_P<1> A_WR_ONE A_BLT_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_TDEC<0> A_SEL_P<0> A_WR_ONE A_BLT_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<3> A_SEL_P<3> A_WR_ZERO A_BLC_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<2> A_SEL_P<2> A_WR_ZERO A_BLC_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<1> A_SEL_P<1> A_WR_ZERO A_BLC_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<0> A_SEL_P<0> A_WR_ZERO A_BLC_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<3> B_SEL_P<3> B_WR_ZERO B_BLC_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<2> B_SEL_P<2> B_WR_ZERO B_BLC_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<1> B_SEL_P<1> B_WR_ZERO B_BLC_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<0> B_SEL_P<0> B_WR_ZERO B_BLC_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<3> B_SEL_P<3> B_WR_ONE B_BLT_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<2> B_SEL_P<2> B_WR_ONE B_BLT_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<1> B_SEL_P<1> B_WR_ONE B_BLT_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<0> B_SEL_P<0> B_WR_ONE B_BLT_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +.ENDS +.SUBCKT RSC_IHPSG13_AND2X6 A B Z VDD VSS +MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=2.94u l=130.00n ng=3 nrd=0 nrs=0 +MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=4.86u l=130.00n ng=3 nrd=0 nrs=0 +MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_COLCTRL5 A_ADDR_COL<1> A_ADDR_COL<0> A_ADDR_DEC<7> ++ A_ADDR_DEC<6> A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<31> ++ A_BLC<30> A_BLC<29> A_BLC<28> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> ++ A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC<19> A_BLC<18> A_BLC<17> ++ A_BLC<16> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> ++ A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> ++ A_BLC<1> A_BLC<0> A_BLT<31> A_BLT<30> A_BLT<29> A_BLT<28> A_BLT<27> ++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT<23> A_BLT<22> A_BLT<21> A_BLT<20> ++ A_BLT<19> A_BLT<18> A_BLT<17> A_BLT<16> A_BLT<15> A_BLT<14> A_BLT<13> ++ A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> ++ A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_COL<1> B_ADDR_COL<0> ++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> ++ B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I ++ B_BIST_EN_I B_BLC<31> B_BLC<30> B_BLC<29> B_BLC<28> B_BLC<27> B_BLC<26> ++ B_BLC<25> B_BLC<24> B_BLC<23> B_BLC<22> B_BLC<21> B_BLC<20> B_BLC<19> ++ B_BLC<18> B_BLC<17> B_BLC<16> B_BLC<15> B_BLC<14> B_BLC<13> B_BLC<12> ++ B_BLC<11> B_BLC<10> B_BLC<9> B_BLC<8> B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> ++ B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<31> B_BLT<30> B_BLT<29> B_BLT<28> ++ B_BLT<27> B_BLT<26> B_BLT<25> B_BLT<24> B_BLT<23> B_BLT<22> B_BLT<21> ++ B_BLT<20> B_BLT<19> B_BLT<18> B_BLT<17> B_BLT<16> B_BLT<15> B_BLT<14> ++ B_BLT<13> B_BLT<12> B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT<7> B_BLT<6> ++ B_BLT<5> B_BLT<4> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L ++ B_DCLK_B_R B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L ++ B_RCLK_R B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS +XB_I80<1> B_WCLK_B_L B_RCLK_B_L B_W_nor_R<1> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XB_I80<0> B_WCLK_B_L B_RCLK_B_L B_W_nor_R<0> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I80<1> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<1> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I80<0> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<0> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XI_FILL4<16> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<15> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<14> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<13> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<12> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XB_INV<6> B_N1<1> B_P1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<5> B_N0<1> B_P0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<4> B_N0<0> B_P0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<3> B_ADDR_COL<1> B_N1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<2> B_ADDR_COL<1> B_N1<0> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<1> B_ADDR_COL<0> B_N0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<0> B_ADDR_COL<0> B_N0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<6> A_N1<1> A_P1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<5> A_N0<1> A_P0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<4> A_N0<0> A_P0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<3> A_ADDR_COL<1> A_N1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<2> A_ADDR_COL<1> A_N1<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_ADDR_COL<0> A_N0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL<0> A_N0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XB_I81<3> B_W_nor_R<1> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<2> B_W_nor_R<1> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<1> B_W_nor_R<0> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<0> B_W_nor_R<0> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<3> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<2> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<1> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XI_FILL8<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XAB_BLMUX<7> A_BLC<31> A_BLC<30> A_BLC<29> A_BLC<28> A_BLC_SEL A_BLT<31> ++ A_BLT<30> A_BLT<29> A_BLT<28> A_BLT_SEL A_PRE_N A_SEL_P<31> A_SEL_P<30> ++ A_SEL_P<29> A_SEL_P<28> A_WR_ONE A_WR_ZERO B_BLC<31> B_BLC<30> B_BLC<29> ++ B_BLC<28> B_BLC_SEL B_BLT<31> B_BLT<30> B_BLT<29> B_BLT<28> B_BLT_SEL ++ B_PRE_N B_SEL_P<31> B_SEL_P<30> B_SEL_P<29> B_SEL_P<28> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_1024x16_c2_2P_BLDRV +XAB_BLMUX<6> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> A_BLC_SEL A_BLT<27> ++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT_SEL A_PRE_N A_SEL_P<27> A_SEL_P<26> ++ A_SEL_P<25> A_SEL_P<24> A_WR_ONE A_WR_ZERO B_BLC<27> B_BLC<26> B_BLC<25> ++ B_BLC<24> B_BLC_SEL B_BLT<27> B_BLT<26> B_BLT<25> B_BLT<24> B_BLT_SEL ++ B_PRE_N B_SEL_P<27> B_SEL_P<26> B_SEL_P<25> B_SEL_P<24> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_1024x16_c2_2P_BLDRV +XAB_BLMUX<5> A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC_SEL A_BLT<23> ++ A_BLT<22> A_BLT<21> A_BLT<20> A_BLT_SEL A_PRE_N A_SEL_P<23> A_SEL_P<22> ++ A_SEL_P<21> A_SEL_P<20> A_WR_ONE A_WR_ZERO B_BLC<23> B_BLC<22> B_BLC<21> ++ B_BLC<20> B_BLC_SEL B_BLT<23> B_BLT<22> B_BLT<21> B_BLT<20> B_BLT_SEL ++ B_PRE_N B_SEL_P<23> B_SEL_P<22> B_SEL_P<21> B_SEL_P<20> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_1024x16_c2_2P_BLDRV +XAB_BLMUX<4> A_BLC<19> A_BLC<18> A_BLC<17> A_BLC<16> A_BLC_SEL A_BLT<19> ++ A_BLT<18> A_BLT<17> A_BLT<16> A_BLT_SEL A_PRE_N A_SEL_P<19> A_SEL_P<18> ++ A_SEL_P<17> A_SEL_P<16> A_WR_ONE A_WR_ZERO B_BLC<19> B_BLC<18> B_BLC<17> ++ B_BLC<16> B_BLC_SEL B_BLT<19> B_BLT<18> B_BLT<17> B_BLT<16> B_BLT_SEL ++ B_PRE_N B_SEL_P<19> B_SEL_P<18> B_SEL_P<17> B_SEL_P<16> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_1024x16_c2_2P_BLDRV +XAB_BLMUX<3> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC_SEL A_BLT<15> ++ A_BLT<14> A_BLT<13> A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<15> A_SEL_P<14> ++ A_SEL_P<13> A_SEL_P<12> A_WR_ONE A_WR_ZERO B_BLC<15> B_BLC<14> B_BLC<13> ++ B_BLC<12> B_BLC_SEL B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT_SEL ++ B_PRE_N B_SEL_P<15> B_SEL_P<14> B_SEL_P<13> B_SEL_P<12> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_1024x16_c2_2P_BLDRV +XAB_BLMUX<2> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC_SEL A_BLT<11> ++ A_BLT<10> A_BLT<9> A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<11> A_SEL_P<10> ++ A_SEL_P<9> A_SEL_P<8> A_WR_ONE A_WR_ZERO B_BLC<11> B_BLC<10> B_BLC<9> ++ B_BLC<8> B_BLC_SEL B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT_SEL B_PRE_N ++ B_SEL_P<11> B_SEL_P<10> B_SEL_P<9> B_SEL_P<8> B_WR_ONE B_WR_ZERO VDD ++ VSS / RM_IHPSG13_1024x16_c2_2P_BLDRV +XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<7> A_SEL_P<6> A_SEL_P<5> ++ A_SEL_P<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC_SEL ++ B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N B_SEL_P<7> B_SEL_P<6> ++ B_SEL_P<5> B_SEL_P<4> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_BLDRV +XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> A_SEL_P<1> ++ A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLC_SEL ++ B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> B_SEL_P<2> ++ B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_BLDRV +XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6 +XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<31> net041<0> B_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<30> net041<1> B_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<29> net041<2> B_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<28> net041<3> B_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<27> net041<4> B_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<26> net041<5> B_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<25> net041<6> B_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<24> net041<7> B_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<23> net041<8> B_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<22> net041<9> B_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<21> net041<10> B_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<20> net041<11> B_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<19> net041<12> B_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<18> net041<13> B_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<17> net041<14> B_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<16> net041<15> B_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<15> net041<16> B_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<14> net041<17> B_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<13> net041<18> B_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<12> net041<19> B_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<11> net041<20> B_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<10> net041<21> B_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<9> net041<22> B_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<8> net041<23> B_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<7> net041<24> B_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<6> net041<25> B_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<5> net041<26> B_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<4> net041<27> B_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<3> net041<28> B_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<2> net041<29> B_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<1> net041<30> B_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<0> net041<31> B_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<31> net23<0> A_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<30> net23<1> A_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<29> net23<2> A_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<28> net23<3> A_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<27> net23<4> A_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<26> net23<5> A_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<25> net23<6> A_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<24> net23<7> A_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<23> net23<8> A_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<22> net23<9> A_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<21> net23<10> A_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<20> net23<11> A_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<19> net23<12> A_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<18> net23<13> A_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<17> net23<14> A_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<16> net23<15> A_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<15> net23<16> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<17> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<18> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<19> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<20> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<21> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<22> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<23> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<24> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<25> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<26> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<27> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<28> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<29> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<30> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<31> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net042 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net043 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net21 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XB_DEC3<31> B_P1<1> B_P0<1> B_ADDR_DEC<7> net041<0> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<30> B_P1<1> B_P0<1> B_ADDR_DEC<6> net041<1> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<29> B_P1<1> B_P0<1> B_ADDR_DEC<5> net041<2> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<28> B_P1<1> B_P0<1> B_ADDR_DEC<4> net041<3> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<27> B_P1<1> B_P0<1> B_ADDR_DEC<3> net041<4> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<26> B_P1<1> B_P0<1> B_ADDR_DEC<2> net041<5> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<25> B_P1<1> B_P0<1> B_ADDR_DEC<1> net041<6> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<24> B_P1<1> B_P0<1> B_ADDR_DEC<0> net041<7> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<23> B_P1<1> B_N0<1> B_ADDR_DEC<7> net041<8> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<22> B_P1<1> B_N0<1> B_ADDR_DEC<6> net041<9> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<21> B_P1<1> B_N0<1> B_ADDR_DEC<5> net041<10> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<20> B_P1<1> B_N0<1> B_ADDR_DEC<4> net041<11> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<19> B_P1<1> B_N0<1> B_ADDR_DEC<3> net041<12> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<18> B_P1<1> B_N0<1> B_ADDR_DEC<2> net041<13> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<17> B_P1<1> B_N0<1> B_ADDR_DEC<1> net041<14> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<16> B_P1<1> B_N0<1> B_ADDR_DEC<0> net041<15> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<15> B_N1<0> B_P0<0> B_ADDR_DEC<7> net041<16> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<14> B_N1<0> B_P0<0> B_ADDR_DEC<6> net041<17> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<13> B_N1<0> B_P0<0> B_ADDR_DEC<5> net041<18> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<12> B_N1<0> B_P0<0> B_ADDR_DEC<4> net041<19> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<11> B_N1<0> B_P0<0> B_ADDR_DEC<3> net041<20> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<10> B_N1<0> B_P0<0> B_ADDR_DEC<2> net041<21> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<9> B_N1<0> B_P0<0> B_ADDR_DEC<1> net041<22> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<8> B_N1<0> B_P0<0> B_ADDR_DEC<0> net041<23> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<7> B_N1<0> B_N0<0> B_ADDR_DEC<7> net041<24> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<6> B_N1<0> B_N0<0> B_ADDR_DEC<6> net041<25> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<5> B_N1<0> B_N0<0> B_ADDR_DEC<5> net041<26> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<4> B_N1<0> B_N0<0> B_ADDR_DEC<4> net041<27> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<3> B_N1<0> B_N0<0> B_ADDR_DEC<3> net041<28> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<2> B_N1<0> B_N0<0> B_ADDR_DEC<2> net041<29> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<1> B_N1<0> B_N0<0> B_ADDR_DEC<1> net041<30> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<0> B_N1<0> B_N0<0> B_ADDR_DEC<0> net041<31> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<31> A_P1<1> A_P0<1> A_ADDR_DEC<7> net23<0> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<30> A_P1<1> A_P0<1> A_ADDR_DEC<6> net23<1> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<29> A_P1<1> A_P0<1> A_ADDR_DEC<5> net23<2> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<28> A_P1<1> A_P0<1> A_ADDR_DEC<4> net23<3> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<27> A_P1<1> A_P0<1> A_ADDR_DEC<3> net23<4> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<26> A_P1<1> A_P0<1> A_ADDR_DEC<2> net23<5> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<25> A_P1<1> A_P0<1> A_ADDR_DEC<1> net23<6> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<24> A_P1<1> A_P0<1> A_ADDR_DEC<0> net23<7> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<23> A_P1<1> A_N0<1> A_ADDR_DEC<7> net23<8> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<22> A_P1<1> A_N0<1> A_ADDR_DEC<6> net23<9> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<21> A_P1<1> A_N0<1> A_ADDR_DEC<5> net23<10> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<20> A_P1<1> A_N0<1> A_ADDR_DEC<4> net23<11> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<19> A_P1<1> A_N0<1> A_ADDR_DEC<3> net23<12> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<18> A_P1<1> A_N0<1> A_ADDR_DEC<2> net23<13> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<17> A_P1<1> A_N0<1> A_ADDR_DEC<1> net23<14> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<16> A_P1<1> A_N0<1> A_ADDR_DEC<0> net23<15> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<15> A_N1<0> A_P0<0> A_ADDR_DEC<7> net23<16> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<14> A_N1<0> A_P0<0> A_ADDR_DEC<6> net23<17> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<13> A_N1<0> A_P0<0> A_ADDR_DEC<5> net23<18> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<12> A_N1<0> A_P0<0> A_ADDR_DEC<4> net23<19> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<11> A_N1<0> A_P0<0> A_ADDR_DEC<3> net23<20> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<10> A_N1<0> A_P0<0> A_ADDR_DEC<2> net23<21> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<9> A_N1<0> A_P0<0> A_ADDR_DEC<1> net23<22> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<8> A_N1<0> A_P0<0> A_ADDR_DEC<0> net23<23> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<7> A_N1<0> A_N0<0> A_ADDR_DEC<7> net23<24> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<6> A_N1<0> A_N0<0> A_ADDR_DEC<6> net23<25> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<5> A_N1<0> A_N0<0> A_ADDR_DEC<5> net23<26> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<4> A_N1<0> A_N0<0> A_ADDR_DEC<4> net23<27> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<3> A_N1<0> A_N0<0> A_ADDR_DEC<3> net23<28> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<2> A_N1<0> A_N0<0> A_ADDR_DEC<2> net23<29> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<1> A_N1<0> A_N0<0> A_ADDR_DEC<1> net23<30> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<0> A_N1<0> A_N0<0> A_ADDR_DEC<0> net23<31> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_COLDRV13_FILL4 VDD VSS +XI0<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RSC_IHPSG13_CBUFX16 A Z VDD VSS +MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=2.115u l=130.00n ng=3 nrd=0 nrs=0 +MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=5.64u l=130.00n ng=8 nrd=0 nrs=0 +MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=13.000u l=130.00n ng=8 nrd=0 ++ nrs=0 +MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=4.89u l=130.00n ng=3 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_COLDRV13X16 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP8 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX16 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=12.96u l=130.00n ng=8 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_WLDRV16X16 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX16 +.ENDS + + +.SUBCKT RM_IHPSG13_1024x16_c2_2P_COLDRV13X4 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1 VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_WLDRV16X4 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX4 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_ROWDEC8 ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ++ ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<255> ++ WL_O<254> WL_O<253> WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> ++ WL_O<247> WL_O<246> WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> ++ WL_O<240> WL_O<239> WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> ++ WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> ++ WL_O<226> WL_O<225> WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> ++ WL_O<205> WL_O<204> WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> ++ WL_O<198> WL_O<197> WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> ++ WL_O<191> WL_O<190> WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> ++ WL_O<184> WL_O<183> WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> ++ WL_O<177> WL_O<176> WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> ++ WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> ++ WL_O<163> WL_O<162> WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> ++ WL_O<156> WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> ++ WL_O<149> WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> ++ WL_O<142> WL_O<141> WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> ++ WL_O<135> WL_O<134> WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> ++ WL_O<128> WL_O<127> WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> ++ WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> ++ WL_O<114> WL_O<113> WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> ++ WL_O<92> WL_O<91> WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> ++ WL_O<84> WL_O<83> WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> ++ WL_O<76> WL_O<75> WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> ++ WL_O<68> WL_O<67> WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> ++ WL_O<60> WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> ++ WL_O<52> WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> ++ WL_O<44> WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> ++ WL_O<36> WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> ++ WL_O<28> WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> ++ WL_O<20> WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> ++ WL_O<12> WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> ++ WL_O<3> WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC11<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<3> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<15> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<11> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC03 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04 +XDEC10<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<2> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<14> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<10> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC02 +XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC00<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<12> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<8> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC00 +XDEC01<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<13> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<9> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC01 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_ROWREG8 ACLK_N_I ADDR_I<7> ADDR_I<6> ADDR_I<5> ADDR_I<4> ++ ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<7> ADDR_N_O<6> ADDR_N_O<5> ++ ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<7> ++ BIST_ADDR_I<6> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> ++ BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI10 VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_COLDEC4 ACLK_N ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<3> BIST_ADDR<2> ++ BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int net12<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net12<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net12<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net12<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI14 addr_int ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI15 ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_COLCTRL4 A_ADDR_COL A_ADDR_DEC<7> A_ADDR_DEC<6> ++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<15> A_BLC<14> ++ A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> ++ A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<15> A_BLT<14> ++ A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L ++ A_DCLK_B_R A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L ++ A_RCLK_R A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_COL ++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> ++ B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I ++ B_BIST_EN_I B_BLC<15> B_BLC<14> B_BLC<13> B_BLC<12> B_BLC<11> B_BLC<10> ++ B_BLC<9> B_BLC<8> B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC<3> B_BLC<2> ++ B_BLC<1> B_BLC<0> B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT<11> ++ B_BLT<10> B_BLT<9> B_BLT<8> B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT<3> ++ B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L B_DCLK_B_R B_DCLK_L B_DCLK_R ++ B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L B_RCLK_R B_TIEH_O B_WCLK_B_L ++ B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS +XB_I80 B_RCLK_B_L B_WCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I80 A_RCLK_B_L A_WCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4 +XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4 +XI_FILL4<26> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<25> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<24> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<23> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<22> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<21> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<20> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<19> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<18> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<17> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<16> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<15> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<14> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<13> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<12> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<1> B_N0 B_P0 VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<0> B_ADDR_COL B_N0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_N0 A_P0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL A_N0 VDD VSS / RSC_IHPSG13_CINVX4 +XB_I81<1> net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<0> net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<1> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XAB_BLMUX<3> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC_SEL A_BLT<15> ++ A_BLT<14> A_BLT<13> A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<15> A_SEL_P<14> ++ A_SEL_P<13> A_SEL_P<12> A_WR_ONE A_WR_ZERO B_BLC<15> B_BLC<14> B_BLC<13> ++ B_BLC<12> B_BLC_SEL B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT_SEL ++ B_PRE_N B_SEL_P<15> B_SEL_P<14> B_SEL_P<13> B_SEL_P<12> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_1024x16_c2_2P_BLDRV +XAB_BLMUX<2> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC_SEL A_BLT<11> ++ A_BLT<10> A_BLT<9> A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<11> A_SEL_P<10> ++ A_SEL_P<9> A_SEL_P<8> A_WR_ONE A_WR_ZERO B_BLC<11> B_BLC<10> B_BLC<9> ++ B_BLC<8> B_BLC_SEL B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT_SEL B_PRE_N ++ B_SEL_P<11> B_SEL_P<10> B_SEL_P<9> B_SEL_P<8> B_WR_ONE B_WR_ZERO VDD ++ VSS / RM_IHPSG13_1024x16_c2_2P_BLDRV +XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<7> A_SEL_P<6> A_SEL_P<5> ++ A_SEL_P<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC_SEL ++ B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N B_SEL_P<7> B_SEL_P<6> ++ B_SEL_P<5> B_SEL_P<4> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_BLDRV +XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> A_SEL_P<1> ++ A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLC_SEL ++ B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> B_SEL_P<2> ++ B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_BLDRV +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net046 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net045 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net24 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_DEC3INV<15> net23<0> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<1> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<2> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<3> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<4> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<5> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<6> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<7> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<8> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<9> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<10> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<11> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<12> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<13> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<14> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<15> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<15> net044<0> B_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<14> net044<1> B_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<13> net044<2> B_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<12> net044<3> B_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<11> net044<4> B_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<10> net044<5> B_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<9> net044<6> B_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<8> net044<7> B_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<7> net044<8> B_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<6> net044<9> B_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<5> net044<10> B_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<4> net044<11> B_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<3> net044<12> B_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<2> net044<13> B_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<1> net044<14> B_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<0> net044<15> B_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XI_FILL8<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_DEC3<15> A_P0 A_ADDR_DEC<7> net23<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<14> A_P0 A_ADDR_DEC<6> net23<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<13> A_P0 A_ADDR_DEC<5> net23<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<12> A_P0 A_ADDR_DEC<4> net23<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<11> A_P0 A_ADDR_DEC<3> net23<4> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<10> A_P0 A_ADDR_DEC<2> net23<5> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<9> A_P0 A_ADDR_DEC<1> net23<6> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<8> A_P0 A_ADDR_DEC<0> net23<7> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<7> A_N0 A_ADDR_DEC<7> net23<8> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<6> A_N0 A_ADDR_DEC<6> net23<9> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<5> A_N0 A_ADDR_DEC<5> net23<10> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<4> A_N0 A_ADDR_DEC<4> net23<11> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<3> A_N0 A_ADDR_DEC<3> net23<12> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<2> A_N0 A_ADDR_DEC<2> net23<13> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<1> A_N0 A_ADDR_DEC<1> net23<14> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<0> A_N0 A_ADDR_DEC<0> net23<15> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<15> B_P0 B_ADDR_DEC<7> net044<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<14> B_P0 B_ADDR_DEC<6> net044<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<13> B_P0 B_ADDR_DEC<5> net044<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<12> B_P0 B_ADDR_DEC<4> net044<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<11> B_P0 B_ADDR_DEC<3> net044<4> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<10> B_P0 B_ADDR_DEC<2> net044<5> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<9> B_P0 B_ADDR_DEC<1> net044<6> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<8> B_P0 B_ADDR_DEC<0> net044<7> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<7> B_N0 B_ADDR_DEC<7> net044<8> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<6> B_N0 B_ADDR_DEC<6> net044<9> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<5> B_N0 B_ADDR_DEC<5> net044<10> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<4> B_N0 B_ADDR_DEC<4> net044<11> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<3> B_N0 B_ADDR_DEC<3> net044<12> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<2> B_N0 B_ADDR_DEC<2> net044<13> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<1> B_N0 B_ADDR_DEC<1> net044<14> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<0> B_N0 B_ADDR_DEC<0> net044<15> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS + + +.SUBCKT RM_IHPSG13_1024x16_c2_2P_ROWDEC5 ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ++ ADDR_N_I<0> CS_I ECLK_I WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC00 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC01 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0 ADDR_N_I<5> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_ROWREG5 ACLK_N_I ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ++ ADDR_I<0> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_1024x16_c2_2P_COLDEC3 ACLK_N ADDR<2> ADDR<1> ADDR<0> ADDR_COL<1> ++ ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ++ ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> ++ BIST_EN_I VDD VSS +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net13<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net13<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net13<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RSC_IHPSG13_DFPQD_MSAFFX2P CP DN DP QN QP VDD VSS +XI_AMP CP DN DP QN QP VDD VSS / RSC_IHPSG13_DFPQD_MSAFFX2 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_COLCTRL3 A_ADDR_DEC<7> A_ADDR_DEC<6> A_ADDR_DEC<5> ++ A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> A_ADDR_DEC<0> ++ A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> ++ A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> ++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R A_DCLK_L ++ A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R A_TIEH_O ++ A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_DEC<7> B_ADDR_DEC<6> ++ B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> ++ B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I B_BIST_EN_I B_BLC<7> B_BLC<6> B_BLC<5> ++ B_BLC<4> B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<7> B_BLT<6> B_BLT<5> ++ B_BLT<4> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L B_DCLK_B_R ++ B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L B_RCLK_R ++ B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net044 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net043 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2P +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2P +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_ADDR_DEC<7> A_ADDR_DEC<6> ++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> ++ B_BLC<4> B_BLC_SEL B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N ++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_1024x16_c2_2P_BLDRV +XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> ++ B_BLC<0> B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N ++ B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_1024x16_c2_2P_BLDRV +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I80 B_WCLK_B_L B_RCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2 +XB_I76 B_DO_WRITE_P B_DI_N B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XB_I75 B_DO_WRITE_P B_DI_R B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_I80 A_WCLK_B_L A_RCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XB_I81 net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_1024x16_c2_2P_ROWDEC6 ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ++ ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<63> WL_O<62> WL_O<61> WL_O<60> ++ WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> ++ WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> ++ WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> ++ WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> ++ WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> ++ WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> ++ WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> ++ WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC10 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<2> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC02 +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC00 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04 +XDEC11 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<3> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC03 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC01 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_ROWREG6 ACLK_N_I ADDR_I<5> ADDR_I<4> ADDR_I<3> ADDR_I<2> ++ ADDR_I<1> ADDR_I<0> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ++ ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_1024x16_c2_2P_COLDRV13X16 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XI1<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_WLDRV16X16 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX16 +.ENDS + + +.SUBCKT RM_IHPSG13_1024x16_c2_1P_DEC01 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XDEC NADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XI2 VDD VSS / RSC_IHPSG13_FILLCAP4 +XADDRINV ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_DEC00 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XDEC NADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV<1> ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +XADDRINV<0> ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI1 VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_ROWDEC5 ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ++ ADDR_N_I<0> CS_I ECLK_I WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC01 +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC00 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04 +XI0 ADDR_N_I<5> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_ROWREG5 ACLK_N_I ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ++ ADDR_I<0> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + + +.SUBCKT RM_IHPSG13_1024x16_c2_1P_COLDEC5 ACLK_N ADDR<4> ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<4> BIST_ADDR<3> ++ BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI13<1> addr_int<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_CBUFX2 +XI13<0> addr_int<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XDFF<4> BIST_EN_I BIST_ADDR<4> ACLK_N ADDR<4> addr_int<1> net7<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int<0> net7<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net7<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net7<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net7<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI15<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI15<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI15<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_COLCTRL5 A_ADDR_COL<1> A_ADDR_COL<0> A_ADDR_DEC<7> ++ A_ADDR_DEC<6> A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<31> ++ A_BLC<30> A_BLC<29> A_BLC<28> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> ++ A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC<19> A_BLC<18> A_BLC<17> ++ A_BLC<16> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> ++ A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> ++ A_BLC<1> A_BLC<0> A_BLT<31> A_BLT<30> A_BLT<29> A_BLT<28> A_BLT<27> ++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT<23> A_BLT<22> A_BLT<21> A_BLT<20> ++ A_BLT<19> A_BLT<18> A_BLT<17> A_BLT<16> A_BLT<15> A_BLT<14> A_BLT<13> ++ A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> ++ A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_I80<1> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<1> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I80<0> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<0> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XI80<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_INV<6> A_N1<1> A_P1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<5> A_N0<1> A_P0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<4> A_N0<0> A_P0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<3> A_ADDR_COL<1> A_N1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<2> A_ADDR_COL<1> A_N1<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_ADDR_COL<0> A_N0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL<0> A_N0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_I81<3> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<2> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<1> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_BLTMUX<31> A_BLC<31> A_BLC_SEL A_BLT<31> A_BLT_SEL A_PRE_N A_SEL_P<31> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<30> A_BLC<30> A_BLC_SEL A_BLT<30> A_BLT_SEL A_PRE_N A_SEL_P<30> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<29> A_BLC<29> A_BLC_SEL A_BLT<29> A_BLT_SEL A_PRE_N A_SEL_P<29> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<28> A_BLC<28> A_BLC_SEL A_BLT<28> A_BLT_SEL A_PRE_N A_SEL_P<28> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<27> A_BLC<27> A_BLC_SEL A_BLT<27> A_BLT_SEL A_PRE_N A_SEL_P<27> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<26> A_BLC<26> A_BLC_SEL A_BLT<26> A_BLT_SEL A_PRE_N A_SEL_P<26> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<25> A_BLC<25> A_BLC_SEL A_BLT<25> A_BLT_SEL A_PRE_N A_SEL_P<25> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<24> A_BLC<24> A_BLC_SEL A_BLT<24> A_BLT_SEL A_PRE_N A_SEL_P<24> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<23> A_BLC<23> A_BLC_SEL A_BLT<23> A_BLT_SEL A_PRE_N A_SEL_P<23> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<22> A_BLC<22> A_BLC_SEL A_BLT<22> A_BLT_SEL A_PRE_N A_SEL_P<22> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<21> A_BLC<21> A_BLC_SEL A_BLT<21> A_BLT_SEL A_PRE_N A_SEL_P<21> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<20> A_BLC<20> A_BLC_SEL A_BLT<20> A_BLT_SEL A_PRE_N A_SEL_P<20> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<19> A_BLC<19> A_BLC_SEL A_BLT<19> A_BLT_SEL A_PRE_N A_SEL_P<19> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<18> A_BLC<18> A_BLC_SEL A_BLT<18> A_BLT_SEL A_PRE_N A_SEL_P<18> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<17> A_BLC<17> A_BLC_SEL A_BLT<17> A_BLT_SEL A_PRE_N A_SEL_P<17> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<16> A_BLC<16> A_BLC_SEL A_BLT<16> A_BLT_SEL A_PRE_N A_SEL_P<16> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<15> A_BLC<15> A_BLC_SEL A_BLT<15> A_BLT_SEL A_PRE_N A_SEL_P<15> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<14> A_BLC<14> A_BLC_SEL A_BLT<14> A_BLT_SEL A_PRE_N A_SEL_P<14> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<13> A_BLC<13> A_BLC_SEL A_BLT<13> A_BLT_SEL A_PRE_N A_SEL_P<13> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<12> A_BLC<12> A_BLC_SEL A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<12> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<11> A_BLC<11> A_BLC_SEL A_BLT<11> A_BLT_SEL A_PRE_N A_SEL_P<11> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<10> A_BLC<10> A_BLC_SEL A_BLT<10> A_BLT_SEL A_PRE_N A_SEL_P<10> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<9> A_BLC<9> A_BLC_SEL A_BLT<9> A_BLT_SEL A_PRE_N A_SEL_P<9> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<8> A_BLC<8> A_BLC_SEL A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<8> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_SEL_P<7> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_SEL_P<6> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_SEL_P<5> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<4> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_SEL_P<3> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_SEL_P<2> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_SEL_P<1> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<0> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV +XA_CAPS<17> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<16> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<15> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<14> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<13> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<12> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<31> net23<0> A_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<30> net23<1> A_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<29> net23<2> A_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<28> net23<3> A_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<27> net23<4> A_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<26> net23<5> A_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<25> net23<6> A_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<24> net23<7> A_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<23> net23<8> A_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<22> net23<9> A_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<21> net23<10> A_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<20> net23<11> A_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<19> net23<12> A_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<18> net23<13> A_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<17> net23<14> A_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<16> net23<15> A_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<15> net23<16> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<17> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<18> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<19> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<20> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<21> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<22> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<23> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<24> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<25> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<26> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<27> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<28> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<29> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<30> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<31> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net21 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_DEC3<31> A_P1<1> A_P0<1> A_ADDR_DEC<7> net23<0> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<30> A_P1<1> A_P0<1> A_ADDR_DEC<6> net23<1> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<29> A_P1<1> A_P0<1> A_ADDR_DEC<5> net23<2> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<28> A_P1<1> A_P0<1> A_ADDR_DEC<4> net23<3> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<27> A_P1<1> A_P0<1> A_ADDR_DEC<3> net23<4> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<26> A_P1<1> A_P0<1> A_ADDR_DEC<2> net23<5> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<25> A_P1<1> A_P0<1> A_ADDR_DEC<1> net23<6> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<24> A_P1<1> A_P0<1> A_ADDR_DEC<0> net23<7> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<23> A_P1<1> A_N0<1> A_ADDR_DEC<7> net23<8> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<22> A_P1<1> A_N0<1> A_ADDR_DEC<6> net23<9> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<21> A_P1<1> A_N0<1> A_ADDR_DEC<5> net23<10> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<20> A_P1<1> A_N0<1> A_ADDR_DEC<4> net23<11> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<19> A_P1<1> A_N0<1> A_ADDR_DEC<3> net23<12> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<18> A_P1<1> A_N0<1> A_ADDR_DEC<2> net23<13> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<17> A_P1<1> A_N0<1> A_ADDR_DEC<1> net23<14> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<16> A_P1<1> A_N0<1> A_ADDR_DEC<0> net23<15> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<15> A_N1<0> A_P0<0> A_ADDR_DEC<7> net23<16> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<14> A_N1<0> A_P0<0> A_ADDR_DEC<6> net23<17> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<13> A_N1<0> A_P0<0> A_ADDR_DEC<5> net23<18> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<12> A_N1<0> A_P0<0> A_ADDR_DEC<4> net23<19> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<11> A_N1<0> A_P0<0> A_ADDR_DEC<3> net23<20> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<10> A_N1<0> A_P0<0> A_ADDR_DEC<2> net23<21> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<9> A_N1<0> A_P0<0> A_ADDR_DEC<1> net23<22> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<8> A_N1<0> A_P0<0> A_ADDR_DEC<0> net23<23> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<7> A_N1<0> A_N0<0> A_ADDR_DEC<7> net23<24> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<6> A_N1<0> A_N0<0> A_ADDR_DEC<6> net23<25> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<5> A_N1<0> A_N0<0> A_ADDR_DEC<5> net23<26> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<4> A_N1<0> A_N0<0> A_ADDR_DEC<4> net23<27> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<3> A_N1<0> A_N0<0> A_ADDR_DEC<3> net23<28> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<2> A_N1<0> A_N0<0> A_ADDR_DEC<2> net23<29> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<1> A_N1<0> A_N0<0> A_ADDR_DEC<1> net23<30> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<0> A_N1<0> A_N0<0> A_ADDR_DEC<0> net23<31> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS + +.SUBCKT RM_IHPSG13_1024x16_c2_1P_COLDRV13X12 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP8 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_WLDRV16X12 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX12 +.ENDS + + + +.SUBCKT RM_IHPSG13_1024x16_c2_2P_COLDRV13X8 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX8 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_WLDRV16X8 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX8 +.ENDS + + + +.SUBCKT RM_IHPSG13_1024x16_c2_2P_COLDEC2 ACLK_N ADDR<1> ADDR<0> ADDR_COL<1> ADDR_COL<0> ++ ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ADDR_DEC<2> ++ ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI16<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<3> PADR<0> PADR<1> addr_n<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<2> NADR<0> PADR<1> addr_n<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<1> PADR<0> NADR<1> addr_n<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<0> NADR<0> NADR<1> addr_n<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI17<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI17<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI14<3> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_TIEL +XI14<2> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_TIEL +XI14<1> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_TIEL +XI14<0> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_TIEL +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net12<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net12<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI15<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_COLCTRL2 A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<3> A_BLC<2> A_BLC<1> ++ A_BLC<0> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_DEC<3> B_ADDR_DEC<2> ++ B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I B_BIST_EN_I B_BLC<3> ++ B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I ++ B_DCLK_B_L B_DCLK_B_R B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R ++ B_RCLK_L B_RCLK_R B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD ++ VSS +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net046 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net045 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XB_CAPS VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS VDD VSS / RSC_IHPSG13_FILLCAP4 +XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XB_I80 B_RCLK_B_L B_WCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2 +XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I80 A_RCLK_B_L A_WCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XB_I44 B_WCLK_B_L B_BM_N B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I44 A_WCLK_B_L A_BM_N A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XB_I81 net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XAB_BLMUX A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> ++ B_BLC<0> B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N ++ B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_1024x16_c2_2P_BLDRV +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net039 net040 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I51 net039 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_COLDRV13_FILL4C2 VDD VSS +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_1024x16_c2_2P_ROWDEC7 ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ++ ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<127> WL_O<126> ++ WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> ++ WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> ++ WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> WL_O<105> ++ WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> WL_O<98> WL_O<97> ++ WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> WL_O<90> WL_O<89> ++ WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> WL_O<82> WL_O<81> ++ WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> WL_O<74> WL_O<73> ++ WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> WL_O<66> WL_O<65> ++ WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> WL_O<58> WL_O<57> ++ WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> WL_O<50> WL_O<49> ++ WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> WL_O<42> WL_O<41> ++ WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> WL_O<34> WL_O<33> ++ WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> WL_O<26> WL_O<25> ++ WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> WL_O<18> WL_O<17> ++ WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC03 +XDEC01<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC01 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC02 +XDEC00<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_1024x16_c2_2P_DEC00 +XI0 ADDR_N_I<7> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_ROWREG7 ACLK_N_I ADDR_I<6> ADDR_I<5> ADDR_I<4> ADDR_I<3> ++ ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<6> ++ BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> ++ BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<0> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_1024x16_c2_2P_ROWDEC4 ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> ++ CS_I ECLK_I WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XSEL ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ECLK_H<1> ++ ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> ++ WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> ++ WL_O<0> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_2P_ROWREG4 ACLK_N_I ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net7<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net7<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net7<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net7<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_1024x16_c2_1P_BITKIT_TAP BLC BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_TAP A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ VDD_CORE VSS +XITAP<1> A_BLC<1> A_BLT<1> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_1024x16_c2_1P_BITKIT_TAP +XITAP<0> A_BLC<0> A_BLT<0> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_1024x16_c2_1P_BITKIT_TAP +XIEDGEBP_COL1<1> BLC<1> BLT<1> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_TB +XIEDGEBP_COL1<0> BLC<1> BLT<1> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_TB +XIEDGEBP_COL2<1> BLC<0> BLT<0> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_TB +XIEDGEBP_COL2<0> BLC<0> BLT<0> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_TB +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_TAP_LR VDD_CORE VSS +XCORNER<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_1P_BITKIT_CORNER +XCORNER<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_1P_BITKIT_CORNER +XTAP_BORDER VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x16_c2_1P_BITKIT_TAP_LR +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_DEC03 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI0 VDD VSS / RSC_IHPSG13_FILLCAP4 +XDEC ADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_DEC02 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XDEC ADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XI2 VDD VSS / RSC_IHPSG13_FILLCAP4 +XADDRINV ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_ROWDEC8 ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ++ ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<255> ++ WL_O<254> WL_O<253> WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> ++ WL_O<247> WL_O<246> WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> ++ WL_O<240> WL_O<239> WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> ++ WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> ++ WL_O<226> WL_O<225> WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> ++ WL_O<205> WL_O<204> WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> ++ WL_O<198> WL_O<197> WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> ++ WL_O<191> WL_O<190> WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> ++ WL_O<184> WL_O<183> WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> ++ WL_O<177> WL_O<176> WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> ++ WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> ++ WL_O<163> WL_O<162> WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> ++ WL_O<156> WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> ++ WL_O<149> WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> ++ WL_O<142> WL_O<141> WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> ++ WL_O<135> WL_O<134> WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> ++ WL_O<128> WL_O<127> WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> ++ WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> ++ WL_O<114> WL_O<113> WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> ++ WL_O<92> WL_O<91> WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> ++ WL_O<84> WL_O<83> WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> ++ WL_O<76> WL_O<75> WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> ++ WL_O<68> WL_O<67> WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> ++ WL_O<60> WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> ++ WL_O<52> WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> ++ WL_O<44> WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> ++ WL_O<36> WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> ++ WL_O<28> WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> ++ WL_O<20> WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> ++ WL_O<12> WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> ++ WL_O<3> WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC11<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<3> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<15> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<11> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC03 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC10<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<2> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<14> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<10> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC02 +XDEC00<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<12> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<8> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC00 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04 +XDEC01<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<13> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<9> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC01 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_ROWREG8 ACLK_N_I ADDR_I<7> ADDR_I<6> ADDR_I<5> ADDR_I<4> ++ ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<7> ADDR_N_O<6> ADDR_N_O<5> ++ ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<7> ++ BIST_ADDR_I<6> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> ++ BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + +.SUBCKT RM_IHPSG13_1024x16_c2_1P_ROWDEC9 ADDR_N_I<8> ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ++ ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ++ WL_O<511> WL_O<510> WL_O<509> WL_O<508> WL_O<507> WL_O<506> WL_O<505> ++ WL_O<504> WL_O<503> WL_O<502> WL_O<501> WL_O<500> WL_O<499> WL_O<498> ++ WL_O<497> WL_O<496> WL_O<495> WL_O<494> WL_O<493> WL_O<492> WL_O<491> ++ WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> WL_O<484> ++ WL_O<483> WL_O<482> WL_O<481> WL_O<480> WL_O<479> WL_O<478> WL_O<477> ++ WL_O<476> WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> ++ WL_O<469> WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> WL_O<463> ++ WL_O<462> WL_O<461> WL_O<460> WL_O<459> WL_O<458> WL_O<457> WL_O<456> ++ WL_O<455> WL_O<454> WL_O<453> WL_O<452> WL_O<451> WL_O<450> WL_O<449> ++ WL_O<448> WL_O<447> WL_O<446> WL_O<445> WL_O<444> WL_O<443> WL_O<442> ++ WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> WL_O<436> WL_O<435> ++ WL_O<434> WL_O<433> WL_O<432> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> WL_O<415> WL_O<414> ++ WL_O<413> WL_O<412> WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> ++ WL_O<406> WL_O<405> WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> ++ WL_O<399> WL_O<398> WL_O<397> WL_O<396> WL_O<395> WL_O<394> WL_O<393> ++ WL_O<392> WL_O<391> WL_O<390> WL_O<389> WL_O<388> WL_O<387> WL_O<386> ++ WL_O<385> WL_O<384> WL_O<383> WL_O<382> WL_O<381> WL_O<380> WL_O<379> ++ WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> WL_O<372> ++ WL_O<371> WL_O<370> WL_O<369> WL_O<368> WL_O<367> WL_O<366> WL_O<365> ++ WL_O<364> WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> ++ WL_O<357> WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> WL_O<351> ++ WL_O<350> WL_O<349> WL_O<348> WL_O<347> WL_O<346> WL_O<345> WL_O<344> ++ WL_O<343> WL_O<342> WL_O<341> WL_O<340> WL_O<339> WL_O<338> WL_O<337> ++ WL_O<336> WL_O<335> WL_O<334> WL_O<333> WL_O<332> WL_O<331> WL_O<330> ++ WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> WL_O<324> WL_O<323> ++ WL_O<322> WL_O<321> WL_O<320> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> WL_O<303> WL_O<302> ++ WL_O<301> WL_O<300> WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> ++ WL_O<294> WL_O<293> WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> ++ WL_O<287> WL_O<286> WL_O<285> WL_O<284> WL_O<283> WL_O<282> WL_O<281> ++ WL_O<280> WL_O<279> WL_O<278> WL_O<277> WL_O<276> WL_O<275> WL_O<274> ++ WL_O<273> WL_O<272> WL_O<271> WL_O<270> WL_O<269> WL_O<268> WL_O<267> ++ WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> WL_O<260> ++ WL_O<259> WL_O<258> WL_O<257> WL_O<256> WL_O<255> WL_O<254> WL_O<253> ++ WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> ++ WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> WL_O<239> ++ WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> WL_O<233> WL_O<232> ++ WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> WL_O<226> WL_O<225> ++ WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> WL_O<219> WL_O<218> ++ WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> WL_O<212> WL_O<211> ++ WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> WL_O<191> WL_O<190> ++ WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> ++ WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> ++ WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> WL_O<170> WL_O<169> ++ WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> WL_O<163> WL_O<162> ++ WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> WL_O<156> WL_O<155> ++ WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> WL_O<148> ++ WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> WL_O<142> WL_O<141> ++ WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> ++ WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> WL_O<127> ++ WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> ++ WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> ++ WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> ++ WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> ++ WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XL2<172> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<171> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<170> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<169> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<168> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<167> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<166> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<165> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<164> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<163> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<162> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<161> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<160> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<159> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<158> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<157> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<156> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<155> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<154> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<153> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<152> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<151> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<150> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<149> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<148> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<147> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<146> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<145> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<144> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<143> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<142> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<141> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<140> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<139> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<138> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<137> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<136> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<135> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<134> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<133> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC11<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<7> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC03 +XDEC11<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<3> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC03 +XDEC11<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<31> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC03 +XDEC11<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<27> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC03 +XDEC11<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<23> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC03 +XDEC11<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<19> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<15> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<11> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<7> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<3> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC03 +XDEC00<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC00 +XDEC00<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<4> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC00 +XDEC00<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<0> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC00 +XDEC00<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<28> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC00 +XDEC00<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<24> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC00 +XDEC00<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<20> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC00 +XDEC00<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<16> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<12> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<8> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<4> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<0> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC00 +XSEL<31> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<31> ECLK_H<31> ++ ECLK_H<32> ECLK_B<31> ECLK_B<32> WL_O<511> WL_O<510> WL_O<509> WL_O<508> ++ WL_O<507> WL_O<506> WL_O<505> WL_O<504> WL_O<503> WL_O<502> WL_O<501> ++ WL_O<500> WL_O<499> WL_O<498> WL_O<497> WL_O<496> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<30> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<30> ECLK_H<30> ++ ECLK_H<31> ECLK_B<30> ECLK_B<31> WL_O<495> WL_O<494> WL_O<493> WL_O<492> ++ WL_O<491> WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> ++ WL_O<484> WL_O<483> WL_O<482> WL_O<481> WL_O<480> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<29> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<29> ECLK_H<29> ++ ECLK_H<30> ECLK_B<29> ECLK_B<30> WL_O<479> WL_O<478> WL_O<477> WL_O<476> ++ WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> WL_O<469> ++ WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<28> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<28> ECLK_H<28> ++ ECLK_H<29> ECLK_B<28> ECLK_B<29> WL_O<463> WL_O<462> WL_O<461> WL_O<460> ++ WL_O<459> WL_O<458> WL_O<457> WL_O<456> WL_O<455> WL_O<454> WL_O<453> ++ WL_O<452> WL_O<451> WL_O<450> WL_O<449> WL_O<448> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<27> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<27> ECLK_H<27> ++ ECLK_H<28> ECLK_B<27> ECLK_B<28> WL_O<447> WL_O<446> WL_O<445> WL_O<444> ++ WL_O<443> WL_O<442> WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> ++ WL_O<436> WL_O<435> WL_O<434> WL_O<433> WL_O<432> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<26> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<26> ECLK_H<26> ++ ECLK_H<27> ECLK_B<26> ECLK_B<27> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<25> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<25> ECLK_H<25> ++ ECLK_H<26> ECLK_B<25> ECLK_B<26> WL_O<415> WL_O<414> WL_O<413> WL_O<412> ++ WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> WL_O<406> WL_O<405> ++ WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<24> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<24> ECLK_H<24> ++ ECLK_H<25> ECLK_B<24> ECLK_B<25> WL_O<399> WL_O<398> WL_O<397> WL_O<396> ++ WL_O<395> WL_O<394> WL_O<393> WL_O<392> WL_O<391> WL_O<390> WL_O<389> ++ WL_O<388> WL_O<387> WL_O<386> WL_O<385> WL_O<384> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<23> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<23> ECLK_H<23> ++ ECLK_H<24> ECLK_B<23> ECLK_B<24> WL_O<383> WL_O<382> WL_O<381> WL_O<380> ++ WL_O<379> WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> ++ WL_O<372> WL_O<371> WL_O<370> WL_O<369> WL_O<368> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<22> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<22> ECLK_H<22> ++ ECLK_H<23> ECLK_B<22> ECLK_B<23> WL_O<367> WL_O<366> WL_O<365> WL_O<364> ++ WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> WL_O<357> ++ WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<21> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<21> ECLK_H<21> ++ ECLK_H<22> ECLK_B<21> ECLK_B<22> WL_O<351> WL_O<350> WL_O<349> WL_O<348> ++ WL_O<347> WL_O<346> WL_O<345> WL_O<344> WL_O<343> WL_O<342> WL_O<341> ++ WL_O<340> WL_O<339> WL_O<338> WL_O<337> WL_O<336> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<20> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<20> ECLK_H<20> ++ ECLK_H<21> ECLK_B<20> ECLK_B<21> WL_O<335> WL_O<334> WL_O<333> WL_O<332> ++ WL_O<331> WL_O<330> WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> ++ WL_O<324> WL_O<323> WL_O<322> WL_O<321> WL_O<320> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<19> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<19> ECLK_H<19> ++ ECLK_H<20> ECLK_B<19> ECLK_B<20> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<18> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<18> ECLK_H<18> ++ ECLK_H<19> ECLK_B<18> ECLK_B<19> WL_O<303> WL_O<302> WL_O<301> WL_O<300> ++ WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> WL_O<294> WL_O<293> ++ WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<17> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<17> ECLK_H<17> ++ ECLK_H<18> ECLK_B<17> ECLK_B<18> WL_O<287> WL_O<286> WL_O<285> WL_O<284> ++ WL_O<283> WL_O<282> WL_O<281> WL_O<280> WL_O<279> WL_O<278> WL_O<277> ++ WL_O<276> WL_O<275> WL_O<274> WL_O<273> WL_O<272> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<16> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<16> ECLK_H<16> ++ ECLK_H<17> ECLK_B<16> ECLK_B<17> WL_O<271> WL_O<270> WL_O<269> WL_O<268> ++ WL_O<267> WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> ++ WL_O<260> WL_O<259> WL_O<258> WL_O<257> WL_O<256> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04 +XDEC01<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC01 +XDEC01<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<5> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC01 +XDEC01<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<1> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC01 +XDEC01<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<29> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC01 +XDEC01<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<25> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC01 +XDEC01<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<21> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC01 +XDEC01<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<17> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<13> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<9> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<5> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<1> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC01 +XDEC10<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<6> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC02 +XDEC10<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<2> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC02 +XDEC10<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<30> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC02 +XDEC10<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<26> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC02 +XDEC10<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<22> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC02 +XDEC10<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<18> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<14> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<10> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<6> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<2> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC02 +XI0 ADDR_N_I<9> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_ROWREG9 ACLK_N_I ADDR_I<8> ADDR_I<7> ADDR_I<6> ADDR_I<5> ++ ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<8> ADDR_N_O<7> ++ ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ++ ADDR_N_O<0> BIST_ADDR_I<8> BIST_ADDR_I<7> BIST_ADDR_I<6> BIST_ADDR_I<5> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XINV<8> q_int<8> qn_int<8> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<8> qn_int<8> ADDR_N_O<8> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<8> BIST_EN_I BIST_ADDR_I<8> ACLK_N_I ADDR_I<8> q_int<8> net04<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net04<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net04<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net04<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net04<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net04<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net04<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net04<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net04<8> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +.ENDS + +.SUBCKT RM_IHPSG13_1024x16_c2_1P_ROWDEC7 ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ++ ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<127> WL_O<126> ++ WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> ++ WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> ++ WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> WL_O<105> ++ WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> WL_O<98> WL_O<97> ++ WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> WL_O<90> WL_O<89> ++ WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> WL_O<82> WL_O<81> ++ WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> WL_O<74> WL_O<73> ++ WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> WL_O<66> WL_O<65> ++ WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> WL_O<58> WL_O<57> ++ WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> WL_O<50> WL_O<49> ++ WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> WL_O<42> WL_O<41> ++ WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> WL_O<34> WL_O<33> ++ WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> WL_O<26> WL_O<25> ++ WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> WL_O<18> WL_O<17> ++ WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC03 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC02 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04 +XDEC00<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC00 +XDEC01<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC01 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0 ADDR_N_I<7> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_ROWREG7 ACLK_N_I ADDR_I<6> ADDR_I<5> ADDR_I<4> ADDR_I<3> ++ ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<6> ++ BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> ++ BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + +.SUBCKT RM_IHPSG13_1024x16_c2_1P_COLDRV13X8 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_WLDRV16X8 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX8 +.ENDS + + + +.SUBCKT RM_IHPSG13_1024x16_c2_1P_ROWDEC6 ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ++ ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<63> WL_O<62> WL_O<61> WL_O<60> ++ WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> ++ WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> ++ WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> ++ WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> ++ WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> ++ WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> ++ WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> ++ WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC11 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<3> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC03 +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC00 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC01 +XDEC10 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<2> VDD VSS / ++ RM_IHPSG13_1024x16_c2_1P_DEC02 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_1024x16_c2_1P_ROWREG6 ACLK_N_I ADDR_I<5> ADDR_I<4> ADDR_I<3> ADDR_I<2> ++ ADDR_I<1> ADDR_I<0> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ++ ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + + +.SUBCKT RM_IHPSG13_1024x16_c2_1P_COLUMN_pcell_0 A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<255> A_LWL<254> A_LWL<253> A_LWL<252> A_LWL<251> A_LWL<250> A_LWL<249> A_LWL<248> A_LWL<247> A_LWL<246> A_LWL<245> A_LWL<244> A_LWL<243> A_LWL<242> A_LWL<241> A_LWL<240> A_LWL<239> A_LWL<238> A_LWL<237> A_LWL<236> A_LWL<235> A_LWL<234> A_LWL<233> A_LWL<232> A_LWL<231> A_LWL<230> A_LWL<229> A_LWL<228> A_LWL<227> A_LWL<226> A_LWL<225> A_LWL<224> A_LWL<223> A_LWL<222> A_LWL<221> A_LWL<220> A_LWL<219> A_LWL<218> A_LWL<217> A_LWL<216> A_LWL<215> A_LWL<214> A_LWL<213> A_LWL<212> A_LWL<211> A_LWL<210> A_LWL<209> A_LWL<208> A_LWL<207> A_LWL<206> A_LWL<205> A_LWL<204> A_LWL<203> A_LWL<202> A_LWL<201> A_LWL<200> A_LWL<199> A_LWL<198> A_LWL<197> A_LWL<196> A_LWL<195> A_LWL<194> A_LWL<193> A_LWL<192> A_LWL<191> A_LWL<190> A_LWL<189> A_LWL<188> A_LWL<187> A_LWL<186> A_LWL<185> A_LWL<184> A_LWL<183> A_LWL<182> A_LWL<181> A_LWL<180> A_LWL<179> A_LWL<178> A_LWL<177> A_LWL<176> A_LWL<175> A_LWL<174> A_LWL<173> A_LWL<172> A_LWL<171> A_LWL<170> A_LWL<169> A_LWL<168> A_LWL<167> A_LWL<166> A_LWL<165> A_LWL<164> A_LWL<163> A_LWL<162> A_LWL<161> A_LWL<160> A_LWL<159> A_LWL<158> A_LWL<157> A_LWL<156> A_LWL<155> A_LWL<154> A_LWL<153> A_LWL<152> A_LWL<151> A_LWL<150> A_LWL<149> A_LWL<148> A_LWL<147> A_LWL<146> A_LWL<145> A_LWL<144> A_LWL<143> A_LWL<142> A_LWL<141> A_LWL<140> A_LWL<139> A_LWL<138> A_LWL<137> A_LWL<136> A_LWL<135> A_LWL<134> A_LWL<133> A_LWL<132> A_LWL<131> A_LWL<130> A_LWL<129> A_LWL<128> A_LWL<127> A_LWL<126> A_LWL<125> A_LWL<124> A_LWL<123> A_LWL<122> A_LWL<121> A_LWL<120> A_LWL<119> A_LWL<118> A_LWL<117> A_LWL<116> A_LWL<115> A_LWL<114> A_LWL<113> A_LWL<112> A_LWL<111> A_LWL<110> A_LWL<109> A_LWL<108> A_LWL<107> A_LWL<106> A_LWL<105> A_LWL<104> A_LWL<103> A_LWL<102> A_LWL<101> A_LWL<100> A_LWL<99> A_LWL<98> A_LWL<97> A_LWL<96> A_LWL<95> A_LWL<94> A_LWL<93> A_LWL<92> A_LWL<91> A_LWL<90> A_LWL<89> A_LWL<88> A_LWL<87> A_LWL<86> A_LWL<85> A_LWL<84> A_LWL<83> A_LWL<82> A_LWL<81> A_LWL<80> A_LWL<79> A_LWL<78> A_LWL<77> A_LWL<76> A_LWL<75> A_LWL<74> A_LWL<73> A_LWL<72> A_LWL<71> A_LWL<70> A_LWL<69> A_LWL<68> A_LWL<67> A_LWL<66> A_LWL<65> A_LWL<64> A_LWL<63> A_LWL<62> A_LWL<61> A_LWL<60> A_LWL<59> A_LWL<58> A_LWL<57> A_LWL<56> A_LWL<55> A_LWL<54> A_LWL<53> A_LWL<52> A_LWL<51> A_LWL<50> A_LWL<49> A_LWL<48> A_LWL<47> A_LWL<46> A_LWL<45> A_LWL<44> A_LWL<43> A_LWL<42> A_LWL<41> A_LWL<40> A_LWL<39> A_LWL<38> A_LWL<37> A_LWL<36> A_LWL<35> A_LWL<34> A_LWL<33> A_LWL<32> A_LWL<31> A_LWL<30> A_LWL<29> A_LWL<28> A_LWL<27> A_LWL<26> A_LWL<25> A_LWL<24> A_LWL<23> A_LWL<22> A_LWL<21> A_LWL<20> A_LWL<19> A_LWL<18> A_LWL<17> A_LWL<16> A_LWL<15> A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<255> A_RWL<254> A_RWL<253> A_RWL<252> A_RWL<251> A_RWL<250> A_RWL<249> A_RWL<248> A_RWL<247> A_RWL<246> A_RWL<245> A_RWL<244> A_RWL<243> A_RWL<242> A_RWL<241> A_RWL<240> A_RWL<239> A_RWL<238> A_RWL<237> A_RWL<236> A_RWL<235> A_RWL<234> A_RWL<233> A_RWL<232> A_RWL<231> A_RWL<230> A_RWL<229> A_RWL<228> A_RWL<227> A_RWL<226> A_RWL<225> A_RWL<224> A_RWL<223> A_RWL<222> A_RWL<221> A_RWL<220> A_RWL<219> A_RWL<218> A_RWL<217> A_RWL<216> A_RWL<215> A_RWL<214> A_RWL<213> A_RWL<212> A_RWL<211> A_RWL<210> A_RWL<209> A_RWL<208> A_RWL<207> A_RWL<206> A_RWL<205> A_RWL<204> A_RWL<203> A_RWL<202> A_RWL<201> A_RWL<200> A_RWL<199> A_RWL<198> A_RWL<197> A_RWL<196> A_RWL<195> A_RWL<194> A_RWL<193> A_RWL<192> A_RWL<191> A_RWL<190> A_RWL<189> A_RWL<188> A_RWL<187> A_RWL<186> A_RWL<185> A_RWL<184> A_RWL<183> A_RWL<182> A_RWL<181> A_RWL<180> A_RWL<179> A_RWL<178> A_RWL<177> A_RWL<176> A_RWL<175> A_RWL<174> A_RWL<173> A_RWL<172> A_RWL<171> A_RWL<170> A_RWL<169> A_RWL<168> A_RWL<167> A_RWL<166> A_RWL<165> A_RWL<164> A_RWL<163> A_RWL<162> A_RWL<161> A_RWL<160> A_RWL<159> A_RWL<158> A_RWL<157> A_RWL<156> A_RWL<155> A_RWL<154> A_RWL<153> A_RWL<152> A_RWL<151> A_RWL<150> A_RWL<149> A_RWL<148> A_RWL<147> A_RWL<146> A_RWL<145> A_RWL<144> A_RWL<143> A_RWL<142> A_RWL<141> A_RWL<140> A_RWL<139> A_RWL<138> A_RWL<137> A_RWL<136> A_RWL<135> A_RWL<134> A_RWL<133> A_RWL<132> A_RWL<131> A_RWL<130> A_RWL<129> A_RWL<128> A_RWL<127> A_RWL<126> A_RWL<125> A_RWL<124> A_RWL<123> A_RWL<122> A_RWL<121> A_RWL<120> A_RWL<119> A_RWL<118> A_RWL<117> A_RWL<116> A_RWL<115> A_RWL<114> A_RWL<113> A_RWL<112> A_RWL<111> A_RWL<110> A_RWL<109> A_RWL<108> A_RWL<107> A_RWL<106> A_RWL<105> A_RWL<104> A_RWL<103> A_RWL<102> A_RWL<101> A_RWL<100> A_RWL<99> A_RWL<98> A_RWL<97> A_RWL<96> A_RWL<95> A_RWL<94> A_RWL<93> A_RWL<92> A_RWL<91> A_RWL<90> A_RWL<89> A_RWL<88> A_RWL<87> A_RWL<86> A_RWL<85> A_RWL<84> A_RWL<83> A_RWL<82> A_RWL<81> A_RWL<80> A_RWL<79> A_RWL<78> A_RWL<77> A_RWL<76> A_RWL<75> A_RWL<74> A_RWL<73> A_RWL<72> A_RWL<71> A_RWL<70> A_RWL<69> A_RWL<68> A_RWL<67> A_RWL<66> A_RWL<65> A_RWL<64> A_RWL<63> A_RWL<62> A_RWL<61> A_RWL<60> A_RWL<59> A_RWL<58> A_RWL<57> A_RWL<56> A_RWL<55> A_RWL<54> A_RWL<53> A_RWL<52> A_RWL<51> A_RWL<50> A_RWL<49> A_RWL<48> A_RWL<47> A_RWL<46> A_RWL<45> A_RWL<44> A_RWL<43> A_RWL<42> A_RWL<41> A_RWL<40> A_RWL<39> A_RWL<38> A_RWL<37> A_RWL<36> A_RWL<35> A_RWL<34> A_RWL<33> A_RWL<32> A_RWL<31> A_RWL<30> A_RWL<29> A_RWL<28> A_RWL<27> A_RWL<26> A_RWL<25> A_RWL<24> A_RWL<23> A_RWL<22> A_RWL<21> A_RWL<20> A_RWL<19> A_RWL<18> A_RWL<17> A_RWL<16> A_RWL<15> A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> VDD_CORE VSS +XRAM<16> A_BLC<29> A_BLC<28> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT<29> A_BLT<28> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<255> A_LWL<254> A_LWL<253> A_LWL<252> A_LWL<251> A_LWL<250> A_LWL<249> A_LWL<248> A_LWL<247> A_LWL<246> A_LWL<245> A_LWL<244> A_LWL<243> A_LWL<242> A_LWL<241> A_LWL<240> A_RWL<255> A_RWL<254> A_RWL<253> A_RWL<252> A_RWL<251> A_RWL<250> A_RWL<249> A_RWL<248> A_RWL<247> A_RWL<246> A_RWL<245> A_RWL<244> A_RWL<243> A_RWL<242> A_RWL<241> A_RWL<240> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_SRAM +XRAM<15> A_BLC<27> A_BLC<26> A_BLC<29> A_BLC<28> A_BLT<27> A_BLT<26> A_BLT<29> A_BLT<28> A_LWL<239> A_LWL<238> A_LWL<237> A_LWL<236> A_LWL<235> A_LWL<234> A_LWL<233> A_LWL<232> A_LWL<231> A_LWL<230> A_LWL<229> A_LWL<228> A_LWL<227> A_LWL<226> A_LWL<225> A_LWL<224> A_RWL<239> A_RWL<238> A_RWL<237> A_RWL<236> A_RWL<235> A_RWL<234> A_RWL<233> A_RWL<232> A_RWL<231> A_RWL<230> A_RWL<229> A_RWL<228> A_RWL<227> A_RWL<226> A_RWL<225> A_RWL<224> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_SRAM +XRAM<14> A_BLC<25> A_BLC<24> A_BLC<27> A_BLC<26> A_BLT<25> A_BLT<24> A_BLT<27> A_BLT<26> A_LWL<223> A_LWL<222> A_LWL<221> A_LWL<220> A_LWL<219> A_LWL<218> A_LWL<217> A_LWL<216> A_LWL<215> A_LWL<214> A_LWL<213> A_LWL<212> A_LWL<211> A_LWL<210> A_LWL<209> A_LWL<208> A_RWL<223> A_RWL<222> A_RWL<221> A_RWL<220> A_RWL<219> A_RWL<218> A_RWL<217> A_RWL<216> A_RWL<215> A_RWL<214> A_RWL<213> A_RWL<212> A_RWL<211> A_RWL<210> A_RWL<209> A_RWL<208> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_SRAM +XRAM<13> A_BLC<23> A_BLC<22> A_BLC<25> A_BLC<24> A_BLT<23> A_BLT<22> A_BLT<25> A_BLT<24> A_LWL<207> A_LWL<206> A_LWL<205> A_LWL<204> A_LWL<203> A_LWL<202> A_LWL<201> A_LWL<200> A_LWL<199> A_LWL<198> A_LWL<197> A_LWL<196> A_LWL<195> A_LWL<194> A_LWL<193> A_LWL<192> A_RWL<207> A_RWL<206> A_RWL<205> A_RWL<204> A_RWL<203> A_RWL<202> A_RWL<201> A_RWL<200> A_RWL<199> A_RWL<198> A_RWL<197> A_RWL<196> A_RWL<195> A_RWL<194> A_RWL<193> A_RWL<192> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_SRAM +XRAM<12> A_BLC<21> A_BLC<20> A_BLC<23> A_BLC<22> A_BLT<21> A_BLT<20> A_BLT<23> A_BLT<22> A_LWL<191> A_LWL<190> A_LWL<189> A_LWL<188> A_LWL<187> A_LWL<186> A_LWL<185> A_LWL<184> A_LWL<183> A_LWL<182> A_LWL<181> A_LWL<180> A_LWL<179> A_LWL<178> A_LWL<177> A_LWL<176> A_RWL<191> A_RWL<190> A_RWL<189> A_RWL<188> A_RWL<187> A_RWL<186> A_RWL<185> A_RWL<184> A_RWL<183> A_RWL<182> A_RWL<181> A_RWL<180> A_RWL<179> A_RWL<178> A_RWL<177> A_RWL<176> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_SRAM +XRAM<11> A_BLC<19> A_BLC<18> A_BLC<21> A_BLC<20> A_BLT<19> A_BLT<18> A_BLT<21> A_BLT<20> A_LWL<175> A_LWL<174> A_LWL<173> A_LWL<172> A_LWL<171> A_LWL<170> A_LWL<169> A_LWL<168> A_LWL<167> A_LWL<166> A_LWL<165> A_LWL<164> A_LWL<163> A_LWL<162> A_LWL<161> A_LWL<160> A_RWL<175> A_RWL<174> A_RWL<173> A_RWL<172> A_RWL<171> A_RWL<170> A_RWL<169> A_RWL<168> A_RWL<167> A_RWL<166> A_RWL<165> A_RWL<164> A_RWL<163> A_RWL<162> A_RWL<161> A_RWL<160> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_SRAM +XRAM<10> A_BLC<17> A_BLC<16> A_BLC<19> A_BLC<18> A_BLT<17> A_BLT<16> A_BLT<19> A_BLT<18> A_LWL<159> A_LWL<158> A_LWL<157> A_LWL<156> A_LWL<155> A_LWL<154> A_LWL<153> A_LWL<152> A_LWL<151> A_LWL<150> A_LWL<149> A_LWL<148> A_LWL<147> A_LWL<146> A_LWL<145> A_LWL<144> A_RWL<159> A_RWL<158> A_RWL<157> A_RWL<156> A_RWL<155> A_RWL<154> A_RWL<153> A_RWL<152> A_RWL<151> A_RWL<150> A_RWL<149> A_RWL<148> A_RWL<147> A_RWL<146> A_RWL<145> A_RWL<144> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_SRAM +XRAM<9> A_BLC<15> A_BLC<14> A_BLC<17> A_BLC<16> A_BLT<15> A_BLT<14> A_BLT<17> A_BLT<16> A_LWL<143> A_LWL<142> A_LWL<141> A_LWL<140> A_LWL<139> A_LWL<138> A_LWL<137> A_LWL<136> A_LWL<135> A_LWL<134> A_LWL<133> A_LWL<132> A_LWL<131> A_LWL<130> A_LWL<129> A_LWL<128> A_RWL<143> A_RWL<142> A_RWL<141> A_RWL<140> A_RWL<139> A_RWL<138> A_RWL<137> A_RWL<136> A_RWL<135> A_RWL<134> A_RWL<133> A_RWL<132> A_RWL<131> A_RWL<130> A_RWL<129> A_RWL<128> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_SRAM +XRAM<8> A_BLC<13> A_BLC<12> A_BLC<15> A_BLC<14> A_BLT<13> A_BLT<12> A_BLT<15> A_BLT<14> A_LWL<127> A_LWL<126> A_LWL<125> A_LWL<124> A_LWL<123> A_LWL<122> A_LWL<121> A_LWL<120> A_LWL<119> A_LWL<118> A_LWL<117> A_LWL<116> A_LWL<115> A_LWL<114> A_LWL<113> A_LWL<112> A_RWL<127> A_RWL<126> A_RWL<125> A_RWL<124> A_RWL<123> A_RWL<122> A_RWL<121> A_RWL<120> A_RWL<119> A_RWL<118> A_RWL<117> A_RWL<116> A_RWL<115> A_RWL<114> A_RWL<113> A_RWL<112> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_SRAM +XRAM<7> A_BLC<11> A_BLC<10> A_BLC<13> A_BLC<12> A_BLT<11> A_BLT<10> A_BLT<13> A_BLT<12> A_LWL<111> A_LWL<110> A_LWL<109> A_LWL<108> A_LWL<107> A_LWL<106> A_LWL<105> A_LWL<104> A_LWL<103> A_LWL<102> A_LWL<101> A_LWL<100> A_LWL<99> A_LWL<98> A_LWL<97> A_LWL<96> A_RWL<111> A_RWL<110> A_RWL<109> A_RWL<108> A_RWL<107> A_RWL<106> A_RWL<105> A_RWL<104> A_RWL<103> A_RWL<102> A_RWL<101> A_RWL<100> A_RWL<99> A_RWL<98> A_RWL<97> A_RWL<96> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_SRAM +XRAM<6> A_BLC<9> A_BLC<8> A_BLC<11> A_BLC<10> A_BLT<9> A_BLT<8> A_BLT<11> A_BLT<10> A_LWL<95> A_LWL<94> A_LWL<93> A_LWL<92> A_LWL<91> A_LWL<90> A_LWL<89> A_LWL<88> A_LWL<87> A_LWL<86> A_LWL<85> A_LWL<84> A_LWL<83> A_LWL<82> A_LWL<81> A_LWL<80> A_RWL<95> A_RWL<94> A_RWL<93> A_RWL<92> A_RWL<91> A_RWL<90> A_RWL<89> A_RWL<88> A_RWL<87> A_RWL<86> A_RWL<85> A_RWL<84> A_RWL<83> A_RWL<82> A_RWL<81> A_RWL<80> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_SRAM +XRAM<5> A_BLC<7> A_BLC<6> A_BLC<9> A_BLC<8> A_BLT<7> A_BLT<6> A_BLT<9> A_BLT<8> A_LWL<79> A_LWL<78> A_LWL<77> A_LWL<76> A_LWL<75> A_LWL<74> A_LWL<73> A_LWL<72> A_LWL<71> A_LWL<70> A_LWL<69> A_LWL<68> A_LWL<67> A_LWL<66> A_LWL<65> A_LWL<64> A_RWL<79> A_RWL<78> A_RWL<77> A_RWL<76> A_RWL<75> A_RWL<74> A_RWL<73> A_RWL<72> A_RWL<71> A_RWL<70> A_RWL<69> A_RWL<68> A_RWL<67> A_RWL<66> A_RWL<65> A_RWL<64> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_SRAM +XRAM<4> A_BLC<5> A_BLC<4> A_BLC<7> A_BLC<6> A_BLT<5> A_BLT<4> A_BLT<7> A_BLT<6> A_LWL<63> A_LWL<62> A_LWL<61> A_LWL<60> A_LWL<59> A_LWL<58> A_LWL<57> A_LWL<56> A_LWL<55> A_LWL<54> A_LWL<53> A_LWL<52> A_LWL<51> A_LWL<50> A_LWL<49> A_LWL<48> A_RWL<63> A_RWL<62> A_RWL<61> A_RWL<60> A_RWL<59> A_RWL<58> A_RWL<57> A_RWL<56> A_RWL<55> A_RWL<54> A_RWL<53> A_RWL<52> A_RWL<51> A_RWL<50> A_RWL<49> A_RWL<48> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_SRAM +XRAM<3> A_BLC<3> A_BLC<2> A_BLC<5> A_BLC<4> A_BLT<3> A_BLT<2> A_BLT<5> A_BLT<4> A_LWL<47> A_LWL<46> A_LWL<45> A_LWL<44> A_LWL<43> A_LWL<42> A_LWL<41> A_LWL<40> A_LWL<39> A_LWL<38> A_LWL<37> A_LWL<36> A_LWL<35> A_LWL<34> A_LWL<33> A_LWL<32> A_RWL<47> A_RWL<46> A_RWL<45> A_RWL<44> A_RWL<43> A_RWL<42> A_RWL<41> A_RWL<40> A_RWL<39> A_RWL<38> A_RWL<37> A_RWL<36> A_RWL<35> A_RWL<34> A_RWL<33> A_RWL<32> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_SRAM +XRAM<2> A_BLC<1> A_BLC<0> A_BLC<3> A_BLC<2> A_BLT<1> A_BLT<0> A_BLT<3> A_BLT<2> A_LWL<31> A_LWL<30> A_LWL<29> A_LWL<28> A_LWL<27> A_LWL<26> A_LWL<25> A_LWL<24> A_LWL<23> A_LWL<22> A_LWL<21> A_LWL<20> A_LWL<19> A_LWL<18> A_LWL<17> A_LWL<16> A_RWL<31> A_RWL<30> A_RWL<29> A_RWL<28> A_RWL<27> A_RWL<26> A_RWL<25> A_RWL<24> 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A_WL<107> A_WL<106> A_WL<105> A_WL<104> A_WL<103> A_WL<102> A_WL<101> A_WL<100> A_WL<99> A_WL<98> A_WL<97> A_WL<96> A_WL<95> A_WL<94> A_WL<93> A_WL<92> A_WL<91> A_WL<90> A_WL<89> A_WL<88> A_WL<87> A_WL<86> A_WL<85> A_WL<84> A_WL<83> A_WL<82> A_WL<81> A_WL<80> A_WL<79> A_WL<78> A_WL<77> A_WL<76> A_WL<75> A_WL<74> A_WL<73> A_WL<72> A_WL<71> A_WL<70> A_WL<69> A_WL<68> A_WL<67> A_WL<66> A_WL<65> A_WL<64> A_WL<63> A_WL<62> A_WL<61> A_WL<60> A_WL<59> A_WL<58> A_WL<57> A_WL<56> A_WL<55> A_WL<54> A_WL<53> A_WL<52> A_WL<51> A_WL<50> A_WL<49> A_WL<48> A_WL<47> A_WL<46> A_WL<45> A_WL<44> A_WL<43> A_WL<42> A_WL<41> A_WL<40> A_WL<39> A_WL<38> A_WL<37> A_WL<36> A_WL<35> A_WL<34> A_WL<33> A_WL<32> A_WL<31> A_WL<30> A_WL<29> A_WL<28> A_WL<27> A_WL<26> A_WL<25> A_WL<24> A_WL<23> A_WL<22> A_WL<21> A_WL<20> A_WL<19> A_WL<18> A_WL<17> A_WL<16> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> VDD_CORE VSS +XCORNER<3> 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A_WL<138> A_WL<137> A_WL<136> A_WL<135> A_WL<134> A_WL<133> A_WL<132> A_WL<131> A_WL<130> A_WL<129> A_WL<128> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<7> A_WL<127> A_WL<126> A_WL<125> A_WL<124> A_WL<123> A_WL<122> A_WL<121> A_WL<120> A_WL<119> A_WL<118> A_WL<117> A_WL<116> A_WL<115> A_WL<114> A_WL<113> A_WL<112> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<6> A_WL<111> A_WL<110> A_WL<109> A_WL<108> A_WL<107> A_WL<106> A_WL<105> A_WL<104> A_WL<103> A_WL<102> A_WL<101> A_WL<100> A_WL<99> A_WL<98> A_WL<97> A_WL<96> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<5> A_WL<95> A_WL<94> A_WL<93> A_WL<92> A_WL<91> A_WL<90> A_WL<89> A_WL<88> A_WL<87> A_WL<86> A_WL<85> A_WL<84> A_WL<83> A_WL<82> A_WL<81> A_WL<80> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<4> A_WL<79> A_WL<78> A_WL<77> A_WL<76> A_WL<75> A_WL<74> A_WL<73> A_WL<72> A_WL<71> A_WL<70> A_WL<69> A_WL<68> A_WL<67> A_WL<66> A_WL<65> A_WL<64> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<3> A_WL<63> A_WL<62> A_WL<61> A_WL<60> A_WL<59> A_WL<58> A_WL<57> A_WL<56> A_WL<55> A_WL<54> A_WL<53> A_WL<52> A_WL<51> A_WL<50> A_WL<49> A_WL<48> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<2> A_WL<47> A_WL<46> A_WL<45> A_WL<44> A_WL<43> A_WL<42> A_WL<41> A_WL<40> A_WL<39> A_WL<38> A_WL<37> A_WL<36> A_WL<35> A_WL<34> A_WL<33> A_WL<32> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<1> A_WL<31> A_WL<30> A_WL<29> A_WL<28> A_WL<27> A_WL<26> A_WL<25> A_WL<24> A_WL<23> A_WL<22> A_WL<21> A_WL<20> A_WL<19> A_WL<18> A_WL<17> A_WL<16> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<0> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<15> A_IWL<4095> A_IWL<4094> A_IWL<4093> A_IWL<4092> A_IWL<4091> A_IWL<4090> A_IWL<4089> A_IWL<4088> A_IWL<4087> A_IWL<4086> A_IWL<4085> A_IWL<4084> A_IWL<4083> A_IWL<4082> A_IWL<4081> A_IWL<4080> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<14> A_IWL<4079> A_IWL<4078> A_IWL<4077> A_IWL<4076> A_IWL<4075> A_IWL<4074> A_IWL<4073> A_IWL<4072> A_IWL<4071> A_IWL<4070> A_IWL<4069> A_IWL<4068> A_IWL<4067> A_IWL<4066> A_IWL<4065> A_IWL<4064> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<13> A_IWL<4063> A_IWL<4062> A_IWL<4061> A_IWL<4060> A_IWL<4059> A_IWL<4058> A_IWL<4057> A_IWL<4056> A_IWL<4055> A_IWL<4054> A_IWL<4053> A_IWL<4052> A_IWL<4051> A_IWL<4050> A_IWL<4049> A_IWL<4048> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<12> A_IWL<4047> A_IWL<4046> A_IWL<4045> A_IWL<4044> A_IWL<4043> A_IWL<4042> A_IWL<4041> A_IWL<4040> A_IWL<4039> A_IWL<4038> A_IWL<4037> A_IWL<4036> A_IWL<4035> A_IWL<4034> A_IWL<4033> A_IWL<4032> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<11> A_IWL<4031> A_IWL<4030> A_IWL<4029> A_IWL<4028> A_IWL<4027> A_IWL<4026> A_IWL<4025> A_IWL<4024> A_IWL<4023> A_IWL<4022> A_IWL<4021> A_IWL<4020> A_IWL<4019> A_IWL<4018> A_IWL<4017> A_IWL<4016> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<10> A_IWL<4015> A_IWL<4014> A_IWL<4013> A_IWL<4012> A_IWL<4011> A_IWL<4010> A_IWL<4009> A_IWL<4008> A_IWL<4007> A_IWL<4006> A_IWL<4005> A_IWL<4004> A_IWL<4003> A_IWL<4002> A_IWL<4001> A_IWL<4000> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<9> A_IWL<3999> A_IWL<3998> A_IWL<3997> A_IWL<3996> A_IWL<3995> A_IWL<3994> A_IWL<3993> A_IWL<3992> A_IWL<3991> A_IWL<3990> A_IWL<3989> A_IWL<3988> A_IWL<3987> A_IWL<3986> A_IWL<3985> A_IWL<3984> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<8> A_IWL<3983> A_IWL<3982> A_IWL<3981> A_IWL<3980> A_IWL<3979> A_IWL<3978> A_IWL<3977> A_IWL<3976> A_IWL<3975> A_IWL<3974> A_IWL<3973> A_IWL<3972> A_IWL<3971> A_IWL<3970> A_IWL<3969> A_IWL<3968> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<7> A_IWL<3967> A_IWL<3966> A_IWL<3965> A_IWL<3964> A_IWL<3963> A_IWL<3962> A_IWL<3961> A_IWL<3960> A_IWL<3959> A_IWL<3958> A_IWL<3957> A_IWL<3956> A_IWL<3955> A_IWL<3954> A_IWL<3953> A_IWL<3952> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<6> A_IWL<3951> A_IWL<3950> A_IWL<3949> A_IWL<3948> A_IWL<3947> A_IWL<3946> A_IWL<3945> A_IWL<3944> A_IWL<3943> A_IWL<3942> A_IWL<3941> A_IWL<3940> A_IWL<3939> A_IWL<3938> A_IWL<3937> A_IWL<3936> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<5> A_IWL<3935> A_IWL<3934> A_IWL<3933> A_IWL<3932> A_IWL<3931> A_IWL<3930> A_IWL<3929> A_IWL<3928> A_IWL<3927> A_IWL<3926> A_IWL<3925> A_IWL<3924> A_IWL<3923> A_IWL<3922> A_IWL<3921> A_IWL<3920> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<4> A_IWL<3919> A_IWL<3918> A_IWL<3917> A_IWL<3916> A_IWL<3915> A_IWL<3914> A_IWL<3913> A_IWL<3912> A_IWL<3911> A_IWL<3910> A_IWL<3909> A_IWL<3908> A_IWL<3907> A_IWL<3906> A_IWL<3905> A_IWL<3904> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<3> A_IWL<3903> A_IWL<3902> A_IWL<3901> A_IWL<3900> A_IWL<3899> A_IWL<3898> A_IWL<3897> A_IWL<3896> A_IWL<3895> A_IWL<3894> A_IWL<3893> A_IWL<3892> A_IWL<3891> A_IWL<3890> A_IWL<3889> A_IWL<3888> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<2> A_IWL<3887> A_IWL<3886> A_IWL<3885> A_IWL<3884> A_IWL<3883> A_IWL<3882> A_IWL<3881> A_IWL<3880> A_IWL<3879> A_IWL<3878> A_IWL<3877> A_IWL<3876> A_IWL<3875> A_IWL<3874> A_IWL<3873> A_IWL<3872> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<1> A_IWL<3871> A_IWL<3870> A_IWL<3869> A_IWL<3868> A_IWL<3867> A_IWL<3866> A_IWL<3865> A_IWL<3864> A_IWL<3863> A_IWL<3862> A_IWL<3861> A_IWL<3860> A_IWL<3859> A_IWL<3858> A_IWL<3857> A_IWL<3856> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<0> A_IWL<3855> A_IWL<3854> A_IWL<3853> A_IWL<3852> A_IWL<3851> A_IWL<3850> A_IWL<3849> A_IWL<3848> A_IWL<3847> A_IWL<3846> A_IWL<3845> A_IWL<3844> A_IWL<3843> A_IWL<3842> A_IWL<3841> A_IWL<3840> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_EDGE_LR +XCOL<15> A_BLC<31> A_BLC<30> A_BLC_TOP<31> A_BLC_TOP<30> A_BLT<31> A_BLT<30> A_BLT_TOP<31> A_BLT_TOP<30> A_IWL<3839> A_IWL<3838> A_IWL<3837> A_IWL<3836> A_IWL<3835> A_IWL<3834> A_IWL<3833> A_IWL<3832> A_IWL<3831> A_IWL<3830> A_IWL<3829> A_IWL<3828> A_IWL<3827> A_IWL<3826> A_IWL<3825> A_IWL<3824> A_IWL<3823> A_IWL<3822> A_IWL<3821> A_IWL<3820> A_IWL<3819> A_IWL<3818> A_IWL<3817> A_IWL<3816> A_IWL<3815> A_IWL<3814> A_IWL<3813> A_IWL<3812> A_IWL<3811> A_IWL<3810> A_IWL<3809> A_IWL<3808> A_IWL<3807> A_IWL<3806> A_IWL<3805> A_IWL<3804> A_IWL<3803> A_IWL<3802> A_IWL<3801> A_IWL<3800> A_IWL<3799> A_IWL<3798> A_IWL<3797> A_IWL<3796> A_IWL<3795> A_IWL<3794> A_IWL<3793> A_IWL<3792> A_IWL<3791> A_IWL<3790> A_IWL<3789> A_IWL<3788> A_IWL<3787> A_IWL<3786> A_IWL<3785> A_IWL<3784> A_IWL<3783> A_IWL<3782> A_IWL<3781> A_IWL<3780> A_IWL<3779> A_IWL<3778> A_IWL<3777> A_IWL<3776> A_IWL<3775> A_IWL<3774> A_IWL<3773> A_IWL<3772> A_IWL<3771> A_IWL<3770> A_IWL<3769> A_IWL<3768> A_IWL<3767> A_IWL<3766> A_IWL<3765> A_IWL<3764> A_IWL<3763> A_IWL<3762> A_IWL<3761> A_IWL<3760> A_IWL<3759> A_IWL<3758> A_IWL<3757> A_IWL<3756> A_IWL<3755> A_IWL<3754> A_IWL<3753> A_IWL<3752> A_IWL<3751> A_IWL<3750> A_IWL<3749> A_IWL<3748> A_IWL<3747> A_IWL<3746> A_IWL<3745> A_IWL<3744> A_IWL<3743> A_IWL<3742> A_IWL<3741> A_IWL<3740> A_IWL<3739> A_IWL<3738> A_IWL<3737> A_IWL<3736> A_IWL<3735> A_IWL<3734> A_IWL<3733> A_IWL<3732> A_IWL<3731> A_IWL<3730> A_IWL<3729> A_IWL<3728> A_IWL<3727> A_IWL<3726> A_IWL<3725> A_IWL<3724> A_IWL<3723> A_IWL<3722> A_IWL<3721> A_IWL<3720> A_IWL<3719> A_IWL<3718> A_IWL<3717> A_IWL<3716> A_IWL<3715> A_IWL<3714> A_IWL<3713> A_IWL<3712> A_IWL<3711> A_IWL<3710> A_IWL<3709> A_IWL<3708> A_IWL<3707> A_IWL<3706> A_IWL<3705> A_IWL<3704> A_IWL<3703> A_IWL<3702> A_IWL<3701> A_IWL<3700> A_IWL<3699> A_IWL<3698> A_IWL<3697> A_IWL<3696> A_IWL<3695> A_IWL<3694> A_IWL<3693> A_IWL<3692> A_IWL<3691> A_IWL<3690> A_IWL<3689> A_IWL<3688> A_IWL<3687> A_IWL<3686> A_IWL<3685> A_IWL<3684> A_IWL<3683> A_IWL<3682> A_IWL<3681> A_IWL<3680> A_IWL<3679> A_IWL<3678> A_IWL<3677> A_IWL<3676> A_IWL<3675> A_IWL<3674> A_IWL<3673> A_IWL<3672> A_IWL<3671> A_IWL<3670> A_IWL<3669> A_IWL<3668> A_IWL<3667> A_IWL<3666> A_IWL<3665> A_IWL<3664> A_IWL<3663> A_IWL<3662> A_IWL<3661> A_IWL<3660> A_IWL<3659> A_IWL<3658> A_IWL<3657> A_IWL<3656> A_IWL<3655> A_IWL<3654> A_IWL<3653> A_IWL<3652> A_IWL<3651> A_IWL<3650> A_IWL<3649> A_IWL<3648> A_IWL<3647> A_IWL<3646> A_IWL<3645> A_IWL<3644> A_IWL<3643> A_IWL<3642> A_IWL<3641> A_IWL<3640> A_IWL<3639> A_IWL<3638> A_IWL<3637> A_IWL<3636> A_IWL<3635> A_IWL<3634> A_IWL<3633> A_IWL<3632> A_IWL<3631> A_IWL<3630> A_IWL<3629> A_IWL<3628> A_IWL<3627> A_IWL<3626> A_IWL<3625> A_IWL<3624> A_IWL<3623> A_IWL<3622> A_IWL<3621> A_IWL<3620> A_IWL<3619> A_IWL<3618> A_IWL<3617> A_IWL<3616> A_IWL<3615> A_IWL<3614> A_IWL<3613> A_IWL<3612> A_IWL<3611> A_IWL<3610> A_IWL<3609> A_IWL<3608> A_IWL<3607> A_IWL<3606> A_IWL<3605> A_IWL<3604> A_IWL<3603> A_IWL<3602> A_IWL<3601> A_IWL<3600> A_IWL<3599> A_IWL<3598> A_IWL<3597> A_IWL<3596> A_IWL<3595> A_IWL<3594> A_IWL<3593> A_IWL<3592> A_IWL<3591> A_IWL<3590> A_IWL<3589> A_IWL<3588> A_IWL<3587> A_IWL<3586> A_IWL<3585> A_IWL<3584> A_IWL<4095> A_IWL<4094> A_IWL<4093> A_IWL<4092> A_IWL<4091> A_IWL<4090> A_IWL<4089> A_IWL<4088> A_IWL<4087> A_IWL<4086> A_IWL<4085> A_IWL<4084> A_IWL<4083> A_IWL<4082> A_IWL<4081> A_IWL<4080> A_IWL<4079> A_IWL<4078> A_IWL<4077> A_IWL<4076> A_IWL<4075> A_IWL<4074> A_IWL<4073> A_IWL<4072> A_IWL<4071> A_IWL<4070> A_IWL<4069> A_IWL<4068> A_IWL<4067> A_IWL<4066> A_IWL<4065> A_IWL<4064> A_IWL<4063> A_IWL<4062> A_IWL<4061> A_IWL<4060> A_IWL<4059> A_IWL<4058> A_IWL<4057> A_IWL<4056> A_IWL<4055> A_IWL<4054> A_IWL<4053> A_IWL<4052> A_IWL<4051> A_IWL<4050> A_IWL<4049> A_IWL<4048> A_IWL<4047> A_IWL<4046> A_IWL<4045> A_IWL<4044> A_IWL<4043> A_IWL<4042> A_IWL<4041> A_IWL<4040> A_IWL<4039> A_IWL<4038> A_IWL<4037> A_IWL<4036> A_IWL<4035> A_IWL<4034> A_IWL<4033> A_IWL<4032> A_IWL<4031> A_IWL<4030> A_IWL<4029> A_IWL<4028> A_IWL<4027> A_IWL<4026> A_IWL<4025> A_IWL<4024> A_IWL<4023> A_IWL<4022> A_IWL<4021> A_IWL<4020> A_IWL<4019> A_IWL<4018> A_IWL<4017> A_IWL<4016> A_IWL<4015> A_IWL<4014> A_IWL<4013> A_IWL<4012> A_IWL<4011> A_IWL<4010> A_IWL<4009> A_IWL<4008> A_IWL<4007> A_IWL<4006> A_IWL<4005> A_IWL<4004> A_IWL<4003> A_IWL<4002> A_IWL<4001> A_IWL<4000> A_IWL<3999> A_IWL<3998> A_IWL<3997> A_IWL<3996> A_IWL<3995> A_IWL<3994> A_IWL<3993> A_IWL<3992> A_IWL<3991> A_IWL<3990> A_IWL<3989> A_IWL<3988> A_IWL<3987> A_IWL<3986> A_IWL<3985> A_IWL<3984> A_IWL<3983> A_IWL<3982> A_IWL<3981> A_IWL<3980> A_IWL<3979> A_IWL<3978> A_IWL<3977> A_IWL<3976> A_IWL<3975> A_IWL<3974> A_IWL<3973> A_IWL<3972> A_IWL<3971> A_IWL<3970> A_IWL<3969> A_IWL<3968> A_IWL<3967> A_IWL<3966> A_IWL<3965> A_IWL<3964> A_IWL<3963> A_IWL<3962> A_IWL<3961> A_IWL<3960> A_IWL<3959> A_IWL<3958> A_IWL<3957> A_IWL<3956> A_IWL<3955> A_IWL<3954> A_IWL<3953> A_IWL<3952> A_IWL<3951> A_IWL<3950> A_IWL<3949> A_IWL<3948> A_IWL<3947> A_IWL<3946> A_IWL<3945> A_IWL<3944> A_IWL<3943> A_IWL<3942> A_IWL<3941> A_IWL<3940> A_IWL<3939> A_IWL<3938> A_IWL<3937> A_IWL<3936> A_IWL<3935> A_IWL<3934> A_IWL<3933> A_IWL<3932> A_IWL<3931> A_IWL<3930> A_IWL<3929> A_IWL<3928> A_IWL<3927> A_IWL<3926> A_IWL<3925> A_IWL<3924> A_IWL<3923> A_IWL<3922> A_IWL<3921> A_IWL<3920> A_IWL<3919> A_IWL<3918> A_IWL<3917> A_IWL<3916> A_IWL<3915> A_IWL<3914> A_IWL<3913> A_IWL<3912> A_IWL<3911> A_IWL<3910> A_IWL<3909> A_IWL<3908> A_IWL<3907> A_IWL<3906> A_IWL<3905> A_IWL<3904> A_IWL<3903> A_IWL<3902> A_IWL<3901> A_IWL<3900> A_IWL<3899> A_IWL<3898> A_IWL<3897> A_IWL<3896> A_IWL<3895> A_IWL<3894> A_IWL<3893> A_IWL<3892> A_IWL<3891> A_IWL<3890> A_IWL<3889> A_IWL<3888> A_IWL<3887> A_IWL<3886> A_IWL<3885> A_IWL<3884> A_IWL<3883> A_IWL<3882> A_IWL<3881> A_IWL<3880> A_IWL<3879> A_IWL<3878> A_IWL<3877> A_IWL<3876> A_IWL<3875> A_IWL<3874> A_IWL<3873> A_IWL<3872> A_IWL<3871> A_IWL<3870> A_IWL<3869> A_IWL<3868> A_IWL<3867> A_IWL<3866> A_IWL<3865> A_IWL<3864> A_IWL<3863> A_IWL<3862> A_IWL<3861> A_IWL<3860> A_IWL<3859> A_IWL<3858> A_IWL<3857> A_IWL<3856> A_IWL<3855> A_IWL<3854> A_IWL<3853> A_IWL<3852> A_IWL<3851> A_IWL<3850> A_IWL<3849> A_IWL<3848> A_IWL<3847> A_IWL<3846> A_IWL<3845> A_IWL<3844> A_IWL<3843> A_IWL<3842> A_IWL<3841> A_IWL<3840> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_COLUMN_pcell_0 +XCOL<14> A_BLC<29> A_BLC<28> A_BLC_TOP<29> A_BLC_TOP<28> A_BLT<29> A_BLT<28> A_BLT_TOP<29> A_BLT_TOP<28> A_IWL<3583> A_IWL<3582> A_IWL<3581> A_IWL<3580> A_IWL<3579> A_IWL<3578> A_IWL<3577> A_IWL<3576> A_IWL<3575> A_IWL<3574> A_IWL<3573> A_IWL<3572> A_IWL<3571> A_IWL<3570> A_IWL<3569> A_IWL<3568> A_IWL<3567> A_IWL<3566> A_IWL<3565> A_IWL<3564> A_IWL<3563> A_IWL<3562> A_IWL<3561> A_IWL<3560> A_IWL<3559> A_IWL<3558> A_IWL<3557> A_IWL<3556> A_IWL<3555> A_IWL<3554> A_IWL<3553> A_IWL<3552> A_IWL<3551> A_IWL<3550> A_IWL<3549> A_IWL<3548> A_IWL<3547> A_IWL<3546> A_IWL<3545> A_IWL<3544> A_IWL<3543> A_IWL<3542> A_IWL<3541> A_IWL<3540> A_IWL<3539> A_IWL<3538> A_IWL<3537> A_IWL<3536> A_IWL<3535> A_IWL<3534> A_IWL<3533> A_IWL<3532> A_IWL<3531> A_IWL<3530> A_IWL<3529> A_IWL<3528> A_IWL<3527> A_IWL<3526> A_IWL<3525> A_IWL<3524> A_IWL<3523> A_IWL<3522> A_IWL<3521> A_IWL<3520> A_IWL<3519> A_IWL<3518> A_IWL<3517> A_IWL<3516> A_IWL<3515> A_IWL<3514> A_IWL<3513> A_IWL<3512> A_IWL<3511> A_IWL<3510> A_IWL<3509> A_IWL<3508> A_IWL<3507> A_IWL<3506> A_IWL<3505> A_IWL<3504> A_IWL<3503> A_IWL<3502> A_IWL<3501> A_IWL<3500> A_IWL<3499> A_IWL<3498> A_IWL<3497> A_IWL<3496> A_IWL<3495> A_IWL<3494> A_IWL<3493> A_IWL<3492> A_IWL<3491> A_IWL<3490> A_IWL<3489> A_IWL<3488> A_IWL<3487> A_IWL<3486> A_IWL<3485> A_IWL<3484> A_IWL<3483> A_IWL<3482> A_IWL<3481> A_IWL<3480> A_IWL<3479> A_IWL<3478> A_IWL<3477> A_IWL<3476> A_IWL<3475> A_IWL<3474> A_IWL<3473> A_IWL<3472> A_IWL<3471> A_IWL<3470> A_IWL<3469> A_IWL<3468> A_IWL<3467> A_IWL<3466> A_IWL<3465> A_IWL<3464> A_IWL<3463> A_IWL<3462> A_IWL<3461> A_IWL<3460> A_IWL<3459> A_IWL<3458> A_IWL<3457> A_IWL<3456> A_IWL<3455> A_IWL<3454> A_IWL<3453> A_IWL<3452> A_IWL<3451> A_IWL<3450> A_IWL<3449> A_IWL<3448> A_IWL<3447> A_IWL<3446> A_IWL<3445> A_IWL<3444> A_IWL<3443> A_IWL<3442> A_IWL<3441> A_IWL<3440> A_IWL<3439> A_IWL<3438> A_IWL<3437> A_IWL<3436> A_IWL<3435> A_IWL<3434> A_IWL<3433> A_IWL<3432> A_IWL<3431> A_IWL<3430> A_IWL<3429> A_IWL<3428> A_IWL<3427> A_IWL<3426> A_IWL<3425> A_IWL<3424> A_IWL<3423> A_IWL<3422> A_IWL<3421> A_IWL<3420> A_IWL<3419> A_IWL<3418> A_IWL<3417> A_IWL<3416> A_IWL<3415> A_IWL<3414> A_IWL<3413> A_IWL<3412> A_IWL<3411> A_IWL<3410> A_IWL<3409> A_IWL<3408> A_IWL<3407> A_IWL<3406> A_IWL<3405> A_IWL<3404> A_IWL<3403> A_IWL<3402> A_IWL<3401> A_IWL<3400> A_IWL<3399> A_IWL<3398> A_IWL<3397> A_IWL<3396> A_IWL<3395> A_IWL<3394> A_IWL<3393> A_IWL<3392> A_IWL<3391> A_IWL<3390> A_IWL<3389> A_IWL<3388> A_IWL<3387> A_IWL<3386> A_IWL<3385> A_IWL<3384> A_IWL<3383> A_IWL<3382> A_IWL<3381> A_IWL<3380> A_IWL<3379> A_IWL<3378> A_IWL<3377> A_IWL<3376> A_IWL<3375> A_IWL<3374> A_IWL<3373> A_IWL<3372> A_IWL<3371> A_IWL<3370> A_IWL<3369> A_IWL<3368> A_IWL<3367> A_IWL<3366> A_IWL<3365> A_IWL<3364> A_IWL<3363> A_IWL<3362> A_IWL<3361> A_IWL<3360> A_IWL<3359> A_IWL<3358> A_IWL<3357> A_IWL<3356> A_IWL<3355> A_IWL<3354> A_IWL<3353> A_IWL<3352> A_IWL<3351> A_IWL<3350> A_IWL<3349> A_IWL<3348> A_IWL<3347> A_IWL<3346> A_IWL<3345> A_IWL<3344> A_IWL<3343> A_IWL<3342> A_IWL<3341> A_IWL<3340> A_IWL<3339> A_IWL<3338> A_IWL<3337> A_IWL<3336> A_IWL<3335> A_IWL<3334> A_IWL<3333> A_IWL<3332> A_IWL<3331> A_IWL<3330> A_IWL<3329> A_IWL<3328> A_IWL<3839> A_IWL<3838> A_IWL<3837> A_IWL<3836> A_IWL<3835> A_IWL<3834> A_IWL<3833> A_IWL<3832> A_IWL<3831> A_IWL<3830> A_IWL<3829> A_IWL<3828> A_IWL<3827> A_IWL<3826> A_IWL<3825> A_IWL<3824> A_IWL<3823> A_IWL<3822> A_IWL<3821> A_IWL<3820> A_IWL<3819> A_IWL<3818> A_IWL<3817> A_IWL<3816> A_IWL<3815> A_IWL<3814> A_IWL<3813> A_IWL<3812> A_IWL<3811> A_IWL<3810> A_IWL<3809> A_IWL<3808> A_IWL<3807> A_IWL<3806> A_IWL<3805> A_IWL<3804> A_IWL<3803> A_IWL<3802> A_IWL<3801> A_IWL<3800> A_IWL<3799> A_IWL<3798> A_IWL<3797> A_IWL<3796> A_IWL<3795> A_IWL<3794> A_IWL<3793> A_IWL<3792> A_IWL<3791> A_IWL<3790> A_IWL<3789> A_IWL<3788> A_IWL<3787> A_IWL<3786> A_IWL<3785> A_IWL<3784> A_IWL<3783> A_IWL<3782> A_IWL<3781> A_IWL<3780> A_IWL<3779> A_IWL<3778> A_IWL<3777> A_IWL<3776> A_IWL<3775> A_IWL<3774> A_IWL<3773> A_IWL<3772> A_IWL<3771> A_IWL<3770> A_IWL<3769> A_IWL<3768> A_IWL<3767> A_IWL<3766> A_IWL<3765> A_IWL<3764> A_IWL<3763> A_IWL<3762> A_IWL<3761> A_IWL<3760> A_IWL<3759> A_IWL<3758> A_IWL<3757> A_IWL<3756> A_IWL<3755> A_IWL<3754> A_IWL<3753> A_IWL<3752> A_IWL<3751> A_IWL<3750> A_IWL<3749> A_IWL<3748> A_IWL<3747> A_IWL<3746> A_IWL<3745> A_IWL<3744> A_IWL<3743> A_IWL<3742> A_IWL<3741> A_IWL<3740> A_IWL<3739> A_IWL<3738> A_IWL<3737> A_IWL<3736> A_IWL<3735> A_IWL<3734> A_IWL<3733> A_IWL<3732> A_IWL<3731> A_IWL<3730> A_IWL<3729> A_IWL<3728> A_IWL<3727> A_IWL<3726> A_IWL<3725> A_IWL<3724> A_IWL<3723> A_IWL<3722> A_IWL<3721> A_IWL<3720> A_IWL<3719> A_IWL<3718> A_IWL<3717> A_IWL<3716> A_IWL<3715> A_IWL<3714> A_IWL<3713> A_IWL<3712> A_IWL<3711> A_IWL<3710> A_IWL<3709> A_IWL<3708> A_IWL<3707> A_IWL<3706> A_IWL<3705> A_IWL<3704> A_IWL<3703> A_IWL<3702> A_IWL<3701> A_IWL<3700> A_IWL<3699> A_IWL<3698> A_IWL<3697> A_IWL<3696> A_IWL<3695> A_IWL<3694> A_IWL<3693> A_IWL<3692> A_IWL<3691> A_IWL<3690> A_IWL<3689> A_IWL<3688> A_IWL<3687> A_IWL<3686> A_IWL<3685> A_IWL<3684> A_IWL<3683> A_IWL<3682> A_IWL<3681> A_IWL<3680> A_IWL<3679> A_IWL<3678> A_IWL<3677> A_IWL<3676> A_IWL<3675> A_IWL<3674> A_IWL<3673> A_IWL<3672> A_IWL<3671> A_IWL<3670> A_IWL<3669> A_IWL<3668> A_IWL<3667> A_IWL<3666> A_IWL<3665> A_IWL<3664> A_IWL<3663> A_IWL<3662> A_IWL<3661> A_IWL<3660> A_IWL<3659> A_IWL<3658> A_IWL<3657> A_IWL<3656> A_IWL<3655> A_IWL<3654> A_IWL<3653> A_IWL<3652> A_IWL<3651> A_IWL<3650> A_IWL<3649> A_IWL<3648> A_IWL<3647> A_IWL<3646> A_IWL<3645> A_IWL<3644> A_IWL<3643> A_IWL<3642> A_IWL<3641> A_IWL<3640> A_IWL<3639> A_IWL<3638> A_IWL<3637> A_IWL<3636> A_IWL<3635> A_IWL<3634> A_IWL<3633> A_IWL<3632> A_IWL<3631> A_IWL<3630> A_IWL<3629> A_IWL<3628> A_IWL<3627> A_IWL<3626> A_IWL<3625> A_IWL<3624> A_IWL<3623> A_IWL<3622> A_IWL<3621> A_IWL<3620> A_IWL<3619> A_IWL<3618> A_IWL<3617> A_IWL<3616> A_IWL<3615> A_IWL<3614> A_IWL<3613> A_IWL<3612> A_IWL<3611> A_IWL<3610> A_IWL<3609> A_IWL<3608> A_IWL<3607> A_IWL<3606> A_IWL<3605> A_IWL<3604> A_IWL<3603> A_IWL<3602> A_IWL<3601> A_IWL<3600> A_IWL<3599> A_IWL<3598> A_IWL<3597> A_IWL<3596> A_IWL<3595> A_IWL<3594> A_IWL<3593> A_IWL<3592> A_IWL<3591> A_IWL<3590> A_IWL<3589> A_IWL<3588> A_IWL<3587> A_IWL<3586> A_IWL<3585> A_IWL<3584> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_COLUMN_pcell_0 +XCOL<13> A_BLC<27> A_BLC<26> A_BLC_TOP<27> A_BLC_TOP<26> A_BLT<27> A_BLT<26> A_BLT_TOP<27> A_BLT_TOP<26> A_IWL<3327> A_IWL<3326> A_IWL<3325> A_IWL<3324> A_IWL<3323> A_IWL<3322> A_IWL<3321> A_IWL<3320> A_IWL<3319> A_IWL<3318> A_IWL<3317> A_IWL<3316> A_IWL<3315> A_IWL<3314> A_IWL<3313> A_IWL<3312> A_IWL<3311> A_IWL<3310> A_IWL<3309> A_IWL<3308> A_IWL<3307> A_IWL<3306> A_IWL<3305> A_IWL<3304> A_IWL<3303> A_IWL<3302> A_IWL<3301> A_IWL<3300> A_IWL<3299> A_IWL<3298> A_IWL<3297> A_IWL<3296> A_IWL<3295> A_IWL<3294> A_IWL<3293> A_IWL<3292> A_IWL<3291> A_IWL<3290> A_IWL<3289> A_IWL<3288> A_IWL<3287> A_IWL<3286> A_IWL<3285> A_IWL<3284> A_IWL<3283> A_IWL<3282> A_IWL<3281> A_IWL<3280> A_IWL<3279> A_IWL<3278> A_IWL<3277> A_IWL<3276> A_IWL<3275> A_IWL<3274> A_IWL<3273> A_IWL<3272> A_IWL<3271> A_IWL<3270> A_IWL<3269> A_IWL<3268> A_IWL<3267> A_IWL<3266> A_IWL<3265> A_IWL<3264> A_IWL<3263> A_IWL<3262> A_IWL<3261> A_IWL<3260> A_IWL<3259> A_IWL<3258> A_IWL<3257> A_IWL<3256> A_IWL<3255> A_IWL<3254> A_IWL<3253> A_IWL<3252> A_IWL<3251> A_IWL<3250> A_IWL<3249> A_IWL<3248> A_IWL<3247> A_IWL<3246> A_IWL<3245> A_IWL<3244> A_IWL<3243> A_IWL<3242> A_IWL<3241> A_IWL<3240> A_IWL<3239> A_IWL<3238> A_IWL<3237> A_IWL<3236> A_IWL<3235> A_IWL<3234> A_IWL<3233> A_IWL<3232> A_IWL<3231> A_IWL<3230> A_IWL<3229> A_IWL<3228> A_IWL<3227> A_IWL<3226> A_IWL<3225> A_IWL<3224> A_IWL<3223> A_IWL<3222> A_IWL<3221> A_IWL<3220> A_IWL<3219> A_IWL<3218> A_IWL<3217> A_IWL<3216> A_IWL<3215> A_IWL<3214> A_IWL<3213> A_IWL<3212> A_IWL<3211> A_IWL<3210> A_IWL<3209> A_IWL<3208> A_IWL<3207> A_IWL<3206> A_IWL<3205> A_IWL<3204> A_IWL<3203> A_IWL<3202> A_IWL<3201> A_IWL<3200> A_IWL<3199> A_IWL<3198> A_IWL<3197> A_IWL<3196> A_IWL<3195> A_IWL<3194> A_IWL<3193> A_IWL<3192> A_IWL<3191> A_IWL<3190> A_IWL<3189> A_IWL<3188> A_IWL<3187> A_IWL<3186> A_IWL<3185> A_IWL<3184> A_IWL<3183> A_IWL<3182> A_IWL<3181> A_IWL<3180> A_IWL<3179> A_IWL<3178> A_IWL<3177> A_IWL<3176> A_IWL<3175> A_IWL<3174> A_IWL<3173> A_IWL<3172> A_IWL<3171> A_IWL<3170> A_IWL<3169> A_IWL<3168> A_IWL<3167> A_IWL<3166> A_IWL<3165> A_IWL<3164> A_IWL<3163> A_IWL<3162> A_IWL<3161> A_IWL<3160> A_IWL<3159> A_IWL<3158> A_IWL<3157> A_IWL<3156> A_IWL<3155> A_IWL<3154> A_IWL<3153> A_IWL<3152> A_IWL<3151> A_IWL<3150> A_IWL<3149> A_IWL<3148> A_IWL<3147> A_IWL<3146> A_IWL<3145> A_IWL<3144> A_IWL<3143> A_IWL<3142> A_IWL<3141> A_IWL<3140> A_IWL<3139> A_IWL<3138> A_IWL<3137> A_IWL<3136> A_IWL<3135> A_IWL<3134> A_IWL<3133> A_IWL<3132> A_IWL<3131> A_IWL<3130> A_IWL<3129> A_IWL<3128> A_IWL<3127> A_IWL<3126> A_IWL<3125> A_IWL<3124> A_IWL<3123> A_IWL<3122> A_IWL<3121> A_IWL<3120> A_IWL<3119> A_IWL<3118> A_IWL<3117> A_IWL<3116> A_IWL<3115> A_IWL<3114> A_IWL<3113> A_IWL<3112> A_IWL<3111> A_IWL<3110> A_IWL<3109> A_IWL<3108> A_IWL<3107> A_IWL<3106> A_IWL<3105> A_IWL<3104> A_IWL<3103> A_IWL<3102> A_IWL<3101> A_IWL<3100> A_IWL<3099> A_IWL<3098> A_IWL<3097> A_IWL<3096> A_IWL<3095> A_IWL<3094> A_IWL<3093> A_IWL<3092> A_IWL<3091> A_IWL<3090> A_IWL<3089> A_IWL<3088> A_IWL<3087> A_IWL<3086> A_IWL<3085> A_IWL<3084> A_IWL<3083> A_IWL<3082> A_IWL<3081> A_IWL<3080> A_IWL<3079> A_IWL<3078> A_IWL<3077> A_IWL<3076> A_IWL<3075> A_IWL<3074> A_IWL<3073> A_IWL<3072> A_IWL<3583> A_IWL<3582> A_IWL<3581> A_IWL<3580> A_IWL<3579> A_IWL<3578> A_IWL<3577> A_IWL<3576> A_IWL<3575> A_IWL<3574> A_IWL<3573> A_IWL<3572> A_IWL<3571> A_IWL<3570> A_IWL<3569> A_IWL<3568> A_IWL<3567> A_IWL<3566> A_IWL<3565> A_IWL<3564> A_IWL<3563> A_IWL<3562> A_IWL<3561> A_IWL<3560> A_IWL<3559> A_IWL<3558> A_IWL<3557> A_IWL<3556> A_IWL<3555> A_IWL<3554> A_IWL<3553> A_IWL<3552> A_IWL<3551> A_IWL<3550> A_IWL<3549> A_IWL<3548> A_IWL<3547> A_IWL<3546> A_IWL<3545> A_IWL<3544> A_IWL<3543> A_IWL<3542> A_IWL<3541> A_IWL<3540> A_IWL<3539> A_IWL<3538> A_IWL<3537> A_IWL<3536> A_IWL<3535> A_IWL<3534> A_IWL<3533> A_IWL<3532> A_IWL<3531> A_IWL<3530> A_IWL<3529> A_IWL<3528> A_IWL<3527> A_IWL<3526> A_IWL<3525> A_IWL<3524> A_IWL<3523> A_IWL<3522> A_IWL<3521> A_IWL<3520> A_IWL<3519> A_IWL<3518> A_IWL<3517> A_IWL<3516> A_IWL<3515> A_IWL<3514> A_IWL<3513> A_IWL<3512> A_IWL<3511> A_IWL<3510> A_IWL<3509> A_IWL<3508> A_IWL<3507> A_IWL<3506> A_IWL<3505> A_IWL<3504> A_IWL<3503> A_IWL<3502> A_IWL<3501> A_IWL<3500> A_IWL<3499> A_IWL<3498> A_IWL<3497> A_IWL<3496> A_IWL<3495> A_IWL<3494> A_IWL<3493> A_IWL<3492> A_IWL<3491> A_IWL<3490> A_IWL<3489> A_IWL<3488> A_IWL<3487> A_IWL<3486> A_IWL<3485> A_IWL<3484> A_IWL<3483> A_IWL<3482> A_IWL<3481> A_IWL<3480> A_IWL<3479> A_IWL<3478> A_IWL<3477> A_IWL<3476> A_IWL<3475> A_IWL<3474> A_IWL<3473> A_IWL<3472> A_IWL<3471> A_IWL<3470> A_IWL<3469> A_IWL<3468> A_IWL<3467> A_IWL<3466> A_IWL<3465> A_IWL<3464> A_IWL<3463> A_IWL<3462> A_IWL<3461> A_IWL<3460> A_IWL<3459> A_IWL<3458> A_IWL<3457> A_IWL<3456> A_IWL<3455> A_IWL<3454> A_IWL<3453> A_IWL<3452> A_IWL<3451> A_IWL<3450> A_IWL<3449> A_IWL<3448> A_IWL<3447> A_IWL<3446> A_IWL<3445> A_IWL<3444> A_IWL<3443> A_IWL<3442> A_IWL<3441> A_IWL<3440> A_IWL<3439> A_IWL<3438> A_IWL<3437> A_IWL<3436> A_IWL<3435> A_IWL<3434> A_IWL<3433> A_IWL<3432> A_IWL<3431> A_IWL<3430> A_IWL<3429> A_IWL<3428> A_IWL<3427> A_IWL<3426> A_IWL<3425> A_IWL<3424> A_IWL<3423> A_IWL<3422> A_IWL<3421> A_IWL<3420> A_IWL<3419> A_IWL<3418> A_IWL<3417> A_IWL<3416> A_IWL<3415> A_IWL<3414> A_IWL<3413> A_IWL<3412> A_IWL<3411> A_IWL<3410> A_IWL<3409> A_IWL<3408> A_IWL<3407> A_IWL<3406> A_IWL<3405> A_IWL<3404> A_IWL<3403> A_IWL<3402> A_IWL<3401> A_IWL<3400> A_IWL<3399> A_IWL<3398> A_IWL<3397> A_IWL<3396> A_IWL<3395> A_IWL<3394> A_IWL<3393> A_IWL<3392> A_IWL<3391> A_IWL<3390> A_IWL<3389> A_IWL<3388> A_IWL<3387> A_IWL<3386> A_IWL<3385> A_IWL<3384> A_IWL<3383> A_IWL<3382> A_IWL<3381> A_IWL<3380> A_IWL<3379> A_IWL<3378> A_IWL<3377> A_IWL<3376> A_IWL<3375> A_IWL<3374> A_IWL<3373> A_IWL<3372> A_IWL<3371> A_IWL<3370> A_IWL<3369> A_IWL<3368> A_IWL<3367> A_IWL<3366> A_IWL<3365> A_IWL<3364> A_IWL<3363> A_IWL<3362> A_IWL<3361> A_IWL<3360> A_IWL<3359> A_IWL<3358> A_IWL<3357> A_IWL<3356> A_IWL<3355> A_IWL<3354> A_IWL<3353> A_IWL<3352> A_IWL<3351> A_IWL<3350> A_IWL<3349> A_IWL<3348> A_IWL<3347> A_IWL<3346> A_IWL<3345> A_IWL<3344> A_IWL<3343> A_IWL<3342> A_IWL<3341> A_IWL<3340> A_IWL<3339> A_IWL<3338> A_IWL<3337> A_IWL<3336> A_IWL<3335> A_IWL<3334> A_IWL<3333> A_IWL<3332> A_IWL<3331> A_IWL<3330> A_IWL<3329> A_IWL<3328> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_COLUMN_pcell_0 +XCOL<12> A_BLC<25> A_BLC<24> A_BLC_TOP<25> A_BLC_TOP<24> A_BLT<25> A_BLT<24> A_BLT_TOP<25> A_BLT_TOP<24> A_IWL<3071> A_IWL<3070> A_IWL<3069> A_IWL<3068> A_IWL<3067> A_IWL<3066> A_IWL<3065> A_IWL<3064> A_IWL<3063> A_IWL<3062> A_IWL<3061> A_IWL<3060> A_IWL<3059> A_IWL<3058> A_IWL<3057> A_IWL<3056> A_IWL<3055> A_IWL<3054> A_IWL<3053> A_IWL<3052> A_IWL<3051> A_IWL<3050> A_IWL<3049> A_IWL<3048> A_IWL<3047> A_IWL<3046> A_IWL<3045> A_IWL<3044> A_IWL<3043> A_IWL<3042> A_IWL<3041> A_IWL<3040> A_IWL<3039> A_IWL<3038> A_IWL<3037> A_IWL<3036> A_IWL<3035> A_IWL<3034> A_IWL<3033> A_IWL<3032> A_IWL<3031> A_IWL<3030> A_IWL<3029> A_IWL<3028> A_IWL<3027> A_IWL<3026> A_IWL<3025> A_IWL<3024> A_IWL<3023> A_IWL<3022> A_IWL<3021> A_IWL<3020> A_IWL<3019> A_IWL<3018> A_IWL<3017> A_IWL<3016> A_IWL<3015> A_IWL<3014> A_IWL<3013> A_IWL<3012> A_IWL<3011> A_IWL<3010> A_IWL<3009> A_IWL<3008> A_IWL<3007> A_IWL<3006> A_IWL<3005> A_IWL<3004> A_IWL<3003> A_IWL<3002> A_IWL<3001> A_IWL<3000> A_IWL<2999> A_IWL<2998> A_IWL<2997> A_IWL<2996> A_IWL<2995> A_IWL<2994> A_IWL<2993> A_IWL<2992> A_IWL<2991> A_IWL<2990> A_IWL<2989> A_IWL<2988> A_IWL<2987> A_IWL<2986> A_IWL<2985> A_IWL<2984> A_IWL<2983> A_IWL<2982> A_IWL<2981> A_IWL<2980> A_IWL<2979> A_IWL<2978> A_IWL<2977> A_IWL<2976> A_IWL<2975> A_IWL<2974> A_IWL<2973> A_IWL<2972> A_IWL<2971> A_IWL<2970> A_IWL<2969> A_IWL<2968> A_IWL<2967> A_IWL<2966> A_IWL<2965> A_IWL<2964> A_IWL<2963> A_IWL<2962> A_IWL<2961> A_IWL<2960> A_IWL<2959> A_IWL<2958> A_IWL<2957> A_IWL<2956> A_IWL<2955> A_IWL<2954> A_IWL<2953> A_IWL<2952> A_IWL<2951> A_IWL<2950> A_IWL<2949> A_IWL<2948> A_IWL<2947> A_IWL<2946> A_IWL<2945> A_IWL<2944> A_IWL<2943> A_IWL<2942> A_IWL<2941> A_IWL<2940> A_IWL<2939> A_IWL<2938> A_IWL<2937> A_IWL<2936> A_IWL<2935> A_IWL<2934> A_IWL<2933> A_IWL<2932> A_IWL<2931> A_IWL<2930> A_IWL<2929> A_IWL<2928> A_IWL<2927> A_IWL<2926> A_IWL<2925> A_IWL<2924> A_IWL<2923> A_IWL<2922> A_IWL<2921> A_IWL<2920> A_IWL<2919> A_IWL<2918> A_IWL<2917> A_IWL<2916> A_IWL<2915> A_IWL<2914> A_IWL<2913> A_IWL<2912> A_IWL<2911> A_IWL<2910> A_IWL<2909> A_IWL<2908> A_IWL<2907> A_IWL<2906> A_IWL<2905> A_IWL<2904> A_IWL<2903> A_IWL<2902> A_IWL<2901> A_IWL<2900> A_IWL<2899> A_IWL<2898> A_IWL<2897> A_IWL<2896> A_IWL<2895> A_IWL<2894> A_IWL<2893> A_IWL<2892> A_IWL<2891> A_IWL<2890> A_IWL<2889> A_IWL<2888> A_IWL<2887> A_IWL<2886> A_IWL<2885> A_IWL<2884> A_IWL<2883> A_IWL<2882> A_IWL<2881> A_IWL<2880> A_IWL<2879> A_IWL<2878> A_IWL<2877> A_IWL<2876> A_IWL<2875> A_IWL<2874> A_IWL<2873> A_IWL<2872> A_IWL<2871> A_IWL<2870> A_IWL<2869> A_IWL<2868> A_IWL<2867> A_IWL<2866> A_IWL<2865> A_IWL<2864> A_IWL<2863> A_IWL<2862> A_IWL<2861> A_IWL<2860> A_IWL<2859> A_IWL<2858> A_IWL<2857> A_IWL<2856> A_IWL<2855> A_IWL<2854> A_IWL<2853> A_IWL<2852> A_IWL<2851> A_IWL<2850> A_IWL<2849> A_IWL<2848> A_IWL<2847> A_IWL<2846> A_IWL<2845> A_IWL<2844> A_IWL<2843> A_IWL<2842> A_IWL<2841> A_IWL<2840> A_IWL<2839> A_IWL<2838> A_IWL<2837> A_IWL<2836> A_IWL<2835> A_IWL<2834> A_IWL<2833> A_IWL<2832> A_IWL<2831> A_IWL<2830> A_IWL<2829> A_IWL<2828> A_IWL<2827> A_IWL<2826> A_IWL<2825> A_IWL<2824> A_IWL<2823> A_IWL<2822> A_IWL<2821> A_IWL<2820> A_IWL<2819> A_IWL<2818> A_IWL<2817> A_IWL<2816> A_IWL<3327> A_IWL<3326> A_IWL<3325> A_IWL<3324> A_IWL<3323> A_IWL<3322> A_IWL<3321> A_IWL<3320> A_IWL<3319> A_IWL<3318> A_IWL<3317> A_IWL<3316> A_IWL<3315> A_IWL<3314> A_IWL<3313> A_IWL<3312> A_IWL<3311> A_IWL<3310> A_IWL<3309> A_IWL<3308> A_IWL<3307> A_IWL<3306> A_IWL<3305> A_IWL<3304> A_IWL<3303> A_IWL<3302> A_IWL<3301> A_IWL<3300> A_IWL<3299> A_IWL<3298> A_IWL<3297> A_IWL<3296> A_IWL<3295> A_IWL<3294> A_IWL<3293> A_IWL<3292> A_IWL<3291> A_IWL<3290> A_IWL<3289> A_IWL<3288> A_IWL<3287> A_IWL<3286> A_IWL<3285> A_IWL<3284> A_IWL<3283> A_IWL<3282> A_IWL<3281> A_IWL<3280> A_IWL<3279> A_IWL<3278> A_IWL<3277> A_IWL<3276> A_IWL<3275> A_IWL<3274> A_IWL<3273> A_IWL<3272> A_IWL<3271> A_IWL<3270> A_IWL<3269> A_IWL<3268> A_IWL<3267> A_IWL<3266> A_IWL<3265> A_IWL<3264> A_IWL<3263> A_IWL<3262> A_IWL<3261> A_IWL<3260> A_IWL<3259> A_IWL<3258> A_IWL<3257> A_IWL<3256> A_IWL<3255> A_IWL<3254> A_IWL<3253> A_IWL<3252> A_IWL<3251> A_IWL<3250> A_IWL<3249> A_IWL<3248> A_IWL<3247> A_IWL<3246> A_IWL<3245> A_IWL<3244> A_IWL<3243> A_IWL<3242> A_IWL<3241> A_IWL<3240> A_IWL<3239> A_IWL<3238> A_IWL<3237> A_IWL<3236> A_IWL<3235> A_IWL<3234> A_IWL<3233> A_IWL<3232> A_IWL<3231> A_IWL<3230> A_IWL<3229> A_IWL<3228> A_IWL<3227> A_IWL<3226> A_IWL<3225> A_IWL<3224> A_IWL<3223> A_IWL<3222> A_IWL<3221> A_IWL<3220> A_IWL<3219> A_IWL<3218> A_IWL<3217> A_IWL<3216> A_IWL<3215> A_IWL<3214> A_IWL<3213> A_IWL<3212> A_IWL<3211> A_IWL<3210> A_IWL<3209> A_IWL<3208> A_IWL<3207> A_IWL<3206> A_IWL<3205> A_IWL<3204> A_IWL<3203> A_IWL<3202> A_IWL<3201> A_IWL<3200> A_IWL<3199> A_IWL<3198> A_IWL<3197> A_IWL<3196> A_IWL<3195> A_IWL<3194> A_IWL<3193> A_IWL<3192> A_IWL<3191> A_IWL<3190> A_IWL<3189> A_IWL<3188> A_IWL<3187> A_IWL<3186> A_IWL<3185> A_IWL<3184> A_IWL<3183> A_IWL<3182> A_IWL<3181> A_IWL<3180> A_IWL<3179> A_IWL<3178> A_IWL<3177> A_IWL<3176> A_IWL<3175> A_IWL<3174> A_IWL<3173> A_IWL<3172> A_IWL<3171> A_IWL<3170> A_IWL<3169> A_IWL<3168> A_IWL<3167> A_IWL<3166> A_IWL<3165> A_IWL<3164> A_IWL<3163> A_IWL<3162> A_IWL<3161> A_IWL<3160> A_IWL<3159> A_IWL<3158> A_IWL<3157> A_IWL<3156> A_IWL<3155> A_IWL<3154> A_IWL<3153> A_IWL<3152> A_IWL<3151> A_IWL<3150> A_IWL<3149> A_IWL<3148> A_IWL<3147> A_IWL<3146> A_IWL<3145> A_IWL<3144> A_IWL<3143> A_IWL<3142> A_IWL<3141> A_IWL<3140> A_IWL<3139> A_IWL<3138> A_IWL<3137> A_IWL<3136> A_IWL<3135> A_IWL<3134> A_IWL<3133> A_IWL<3132> A_IWL<3131> A_IWL<3130> A_IWL<3129> A_IWL<3128> A_IWL<3127> A_IWL<3126> A_IWL<3125> A_IWL<3124> A_IWL<3123> A_IWL<3122> A_IWL<3121> A_IWL<3120> A_IWL<3119> A_IWL<3118> A_IWL<3117> A_IWL<3116> A_IWL<3115> A_IWL<3114> A_IWL<3113> A_IWL<3112> A_IWL<3111> A_IWL<3110> A_IWL<3109> A_IWL<3108> A_IWL<3107> A_IWL<3106> A_IWL<3105> A_IWL<3104> A_IWL<3103> A_IWL<3102> A_IWL<3101> A_IWL<3100> A_IWL<3099> A_IWL<3098> A_IWL<3097> A_IWL<3096> A_IWL<3095> A_IWL<3094> A_IWL<3093> A_IWL<3092> A_IWL<3091> A_IWL<3090> A_IWL<3089> A_IWL<3088> A_IWL<3087> A_IWL<3086> A_IWL<3085> A_IWL<3084> A_IWL<3083> A_IWL<3082> A_IWL<3081> A_IWL<3080> A_IWL<3079> A_IWL<3078> A_IWL<3077> A_IWL<3076> A_IWL<3075> A_IWL<3074> A_IWL<3073> A_IWL<3072> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_COLUMN_pcell_0 +XCOL<11> A_BLC<23> A_BLC<22> A_BLC_TOP<23> A_BLC_TOP<22> A_BLT<23> A_BLT<22> A_BLT_TOP<23> A_BLT_TOP<22> A_IWL<2815> A_IWL<2814> A_IWL<2813> A_IWL<2812> A_IWL<2811> A_IWL<2810> A_IWL<2809> A_IWL<2808> A_IWL<2807> A_IWL<2806> A_IWL<2805> A_IWL<2804> A_IWL<2803> A_IWL<2802> A_IWL<2801> A_IWL<2800> A_IWL<2799> A_IWL<2798> A_IWL<2797> A_IWL<2796> A_IWL<2795> A_IWL<2794> A_IWL<2793> A_IWL<2792> A_IWL<2791> A_IWL<2790> A_IWL<2789> A_IWL<2788> A_IWL<2787> A_IWL<2786> A_IWL<2785> A_IWL<2784> A_IWL<2783> A_IWL<2782> A_IWL<2781> A_IWL<2780> A_IWL<2779> A_IWL<2778> A_IWL<2777> A_IWL<2776> A_IWL<2775> A_IWL<2774> A_IWL<2773> A_IWL<2772> A_IWL<2771> A_IWL<2770> A_IWL<2769> A_IWL<2768> A_IWL<2767> A_IWL<2766> A_IWL<2765> A_IWL<2764> A_IWL<2763> A_IWL<2762> A_IWL<2761> A_IWL<2760> A_IWL<2759> A_IWL<2758> A_IWL<2757> A_IWL<2756> A_IWL<2755> A_IWL<2754> A_IWL<2753> A_IWL<2752> A_IWL<2751> A_IWL<2750> A_IWL<2749> A_IWL<2748> A_IWL<2747> A_IWL<2746> A_IWL<2745> A_IWL<2744> A_IWL<2743> A_IWL<2742> A_IWL<2741> A_IWL<2740> A_IWL<2739> A_IWL<2738> A_IWL<2737> A_IWL<2736> A_IWL<2735> A_IWL<2734> A_IWL<2733> A_IWL<2732> A_IWL<2731> A_IWL<2730> A_IWL<2729> A_IWL<2728> A_IWL<2727> A_IWL<2726> A_IWL<2725> A_IWL<2724> A_IWL<2723> A_IWL<2722> A_IWL<2721> A_IWL<2720> A_IWL<2719> A_IWL<2718> A_IWL<2717> A_IWL<2716> A_IWL<2715> A_IWL<2714> A_IWL<2713> A_IWL<2712> A_IWL<2711> A_IWL<2710> A_IWL<2709> A_IWL<2708> A_IWL<2707> A_IWL<2706> A_IWL<2705> A_IWL<2704> A_IWL<2703> A_IWL<2702> A_IWL<2701> A_IWL<2700> A_IWL<2699> A_IWL<2698> A_IWL<2697> A_IWL<2696> A_IWL<2695> A_IWL<2694> A_IWL<2693> A_IWL<2692> A_IWL<2691> A_IWL<2690> A_IWL<2689> A_IWL<2688> A_IWL<2687> A_IWL<2686> A_IWL<2685> A_IWL<2684> A_IWL<2683> A_IWL<2682> A_IWL<2681> A_IWL<2680> A_IWL<2679> A_IWL<2678> A_IWL<2677> A_IWL<2676> A_IWL<2675> A_IWL<2674> A_IWL<2673> A_IWL<2672> A_IWL<2671> A_IWL<2670> A_IWL<2669> A_IWL<2668> A_IWL<2667> A_IWL<2666> A_IWL<2665> A_IWL<2664> A_IWL<2663> A_IWL<2662> A_IWL<2661> A_IWL<2660> A_IWL<2659> A_IWL<2658> A_IWL<2657> A_IWL<2656> A_IWL<2655> A_IWL<2654> A_IWL<2653> A_IWL<2652> A_IWL<2651> A_IWL<2650> A_IWL<2649> A_IWL<2648> A_IWL<2647> A_IWL<2646> A_IWL<2645> A_IWL<2644> A_IWL<2643> A_IWL<2642> A_IWL<2641> A_IWL<2640> A_IWL<2639> A_IWL<2638> A_IWL<2637> A_IWL<2636> A_IWL<2635> A_IWL<2634> A_IWL<2633> A_IWL<2632> A_IWL<2631> A_IWL<2630> A_IWL<2629> A_IWL<2628> A_IWL<2627> A_IWL<2626> A_IWL<2625> A_IWL<2624> A_IWL<2623> A_IWL<2622> A_IWL<2621> A_IWL<2620> A_IWL<2619> A_IWL<2618> A_IWL<2617> A_IWL<2616> A_IWL<2615> A_IWL<2614> A_IWL<2613> A_IWL<2612> A_IWL<2611> A_IWL<2610> A_IWL<2609> A_IWL<2608> A_IWL<2607> A_IWL<2606> A_IWL<2605> A_IWL<2604> A_IWL<2603> A_IWL<2602> A_IWL<2601> A_IWL<2600> A_IWL<2599> A_IWL<2598> A_IWL<2597> A_IWL<2596> A_IWL<2595> A_IWL<2594> A_IWL<2593> A_IWL<2592> A_IWL<2591> A_IWL<2590> A_IWL<2589> A_IWL<2588> A_IWL<2587> A_IWL<2586> A_IWL<2585> A_IWL<2584> A_IWL<2583> A_IWL<2582> A_IWL<2581> A_IWL<2580> A_IWL<2579> A_IWL<2578> A_IWL<2577> A_IWL<2576> A_IWL<2575> A_IWL<2574> A_IWL<2573> A_IWL<2572> A_IWL<2571> A_IWL<2570> A_IWL<2569> A_IWL<2568> A_IWL<2567> A_IWL<2566> A_IWL<2565> A_IWL<2564> A_IWL<2563> A_IWL<2562> A_IWL<2561> A_IWL<2560> A_IWL<3071> A_IWL<3070> A_IWL<3069> A_IWL<3068> A_IWL<3067> A_IWL<3066> A_IWL<3065> A_IWL<3064> A_IWL<3063> A_IWL<3062> A_IWL<3061> A_IWL<3060> A_IWL<3059> A_IWL<3058> A_IWL<3057> A_IWL<3056> A_IWL<3055> A_IWL<3054> A_IWL<3053> A_IWL<3052> A_IWL<3051> A_IWL<3050> A_IWL<3049> A_IWL<3048> A_IWL<3047> A_IWL<3046> A_IWL<3045> A_IWL<3044> A_IWL<3043> A_IWL<3042> A_IWL<3041> A_IWL<3040> A_IWL<3039> A_IWL<3038> A_IWL<3037> A_IWL<3036> A_IWL<3035> A_IWL<3034> A_IWL<3033> A_IWL<3032> A_IWL<3031> A_IWL<3030> A_IWL<3029> A_IWL<3028> A_IWL<3027> A_IWL<3026> A_IWL<3025> A_IWL<3024> A_IWL<3023> A_IWL<3022> A_IWL<3021> A_IWL<3020> A_IWL<3019> A_IWL<3018> A_IWL<3017> A_IWL<3016> A_IWL<3015> A_IWL<3014> A_IWL<3013> A_IWL<3012> A_IWL<3011> A_IWL<3010> A_IWL<3009> A_IWL<3008> A_IWL<3007> A_IWL<3006> A_IWL<3005> A_IWL<3004> A_IWL<3003> A_IWL<3002> A_IWL<3001> A_IWL<3000> A_IWL<2999> A_IWL<2998> A_IWL<2997> A_IWL<2996> A_IWL<2995> A_IWL<2994> A_IWL<2993> A_IWL<2992> A_IWL<2991> A_IWL<2990> A_IWL<2989> A_IWL<2988> A_IWL<2987> A_IWL<2986> A_IWL<2985> A_IWL<2984> A_IWL<2983> A_IWL<2982> A_IWL<2981> A_IWL<2980> A_IWL<2979> A_IWL<2978> A_IWL<2977> A_IWL<2976> A_IWL<2975> A_IWL<2974> A_IWL<2973> A_IWL<2972> A_IWL<2971> A_IWL<2970> A_IWL<2969> A_IWL<2968> A_IWL<2967> A_IWL<2966> A_IWL<2965> A_IWL<2964> A_IWL<2963> A_IWL<2962> A_IWL<2961> A_IWL<2960> A_IWL<2959> A_IWL<2958> A_IWL<2957> A_IWL<2956> A_IWL<2955> A_IWL<2954> A_IWL<2953> A_IWL<2952> A_IWL<2951> A_IWL<2950> A_IWL<2949> A_IWL<2948> A_IWL<2947> A_IWL<2946> A_IWL<2945> A_IWL<2944> A_IWL<2943> A_IWL<2942> A_IWL<2941> A_IWL<2940> A_IWL<2939> A_IWL<2938> A_IWL<2937> A_IWL<2936> A_IWL<2935> A_IWL<2934> A_IWL<2933> A_IWL<2932> A_IWL<2931> A_IWL<2930> A_IWL<2929> A_IWL<2928> A_IWL<2927> A_IWL<2926> A_IWL<2925> A_IWL<2924> A_IWL<2923> A_IWL<2922> A_IWL<2921> A_IWL<2920> A_IWL<2919> A_IWL<2918> A_IWL<2917> A_IWL<2916> A_IWL<2915> A_IWL<2914> A_IWL<2913> A_IWL<2912> A_IWL<2911> A_IWL<2910> A_IWL<2909> A_IWL<2908> A_IWL<2907> A_IWL<2906> A_IWL<2905> A_IWL<2904> A_IWL<2903> A_IWL<2902> A_IWL<2901> A_IWL<2900> A_IWL<2899> A_IWL<2898> A_IWL<2897> A_IWL<2896> A_IWL<2895> A_IWL<2894> A_IWL<2893> A_IWL<2892> A_IWL<2891> A_IWL<2890> A_IWL<2889> A_IWL<2888> A_IWL<2887> A_IWL<2886> A_IWL<2885> A_IWL<2884> A_IWL<2883> A_IWL<2882> A_IWL<2881> A_IWL<2880> A_IWL<2879> A_IWL<2878> A_IWL<2877> A_IWL<2876> A_IWL<2875> A_IWL<2874> A_IWL<2873> A_IWL<2872> A_IWL<2871> A_IWL<2870> A_IWL<2869> A_IWL<2868> A_IWL<2867> A_IWL<2866> A_IWL<2865> A_IWL<2864> A_IWL<2863> A_IWL<2862> A_IWL<2861> A_IWL<2860> A_IWL<2859> A_IWL<2858> A_IWL<2857> A_IWL<2856> A_IWL<2855> A_IWL<2854> A_IWL<2853> A_IWL<2852> A_IWL<2851> A_IWL<2850> A_IWL<2849> A_IWL<2848> A_IWL<2847> A_IWL<2846> A_IWL<2845> A_IWL<2844> A_IWL<2843> A_IWL<2842> A_IWL<2841> A_IWL<2840> A_IWL<2839> A_IWL<2838> A_IWL<2837> A_IWL<2836> A_IWL<2835> A_IWL<2834> A_IWL<2833> A_IWL<2832> A_IWL<2831> A_IWL<2830> A_IWL<2829> A_IWL<2828> A_IWL<2827> A_IWL<2826> A_IWL<2825> A_IWL<2824> A_IWL<2823> A_IWL<2822> A_IWL<2821> A_IWL<2820> A_IWL<2819> A_IWL<2818> A_IWL<2817> A_IWL<2816> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_COLUMN_pcell_0 +XCOL<10> A_BLC<21> A_BLC<20> A_BLC_TOP<21> A_BLC_TOP<20> A_BLT<21> A_BLT<20> A_BLT_TOP<21> A_BLT_TOP<20> A_IWL<2559> A_IWL<2558> A_IWL<2557> A_IWL<2556> A_IWL<2555> A_IWL<2554> A_IWL<2553> A_IWL<2552> A_IWL<2551> A_IWL<2550> A_IWL<2549> A_IWL<2548> A_IWL<2547> A_IWL<2546> A_IWL<2545> A_IWL<2544> A_IWL<2543> A_IWL<2542> A_IWL<2541> A_IWL<2540> A_IWL<2539> A_IWL<2538> A_IWL<2537> A_IWL<2536> A_IWL<2535> A_IWL<2534> A_IWL<2533> A_IWL<2532> A_IWL<2531> A_IWL<2530> A_IWL<2529> A_IWL<2528> A_IWL<2527> A_IWL<2526> A_IWL<2525> A_IWL<2524> A_IWL<2523> A_IWL<2522> A_IWL<2521> A_IWL<2520> A_IWL<2519> A_IWL<2518> A_IWL<2517> A_IWL<2516> A_IWL<2515> A_IWL<2514> A_IWL<2513> A_IWL<2512> A_IWL<2511> A_IWL<2510> A_IWL<2509> A_IWL<2508> A_IWL<2507> A_IWL<2506> A_IWL<2505> A_IWL<2504> A_IWL<2503> A_IWL<2502> A_IWL<2501> A_IWL<2500> A_IWL<2499> A_IWL<2498> A_IWL<2497> A_IWL<2496> A_IWL<2495> A_IWL<2494> A_IWL<2493> A_IWL<2492> A_IWL<2491> A_IWL<2490> A_IWL<2489> A_IWL<2488> A_IWL<2487> A_IWL<2486> A_IWL<2485> A_IWL<2484> A_IWL<2483> A_IWL<2482> A_IWL<2481> A_IWL<2480> A_IWL<2479> A_IWL<2478> A_IWL<2477> A_IWL<2476> A_IWL<2475> A_IWL<2474> A_IWL<2473> A_IWL<2472> A_IWL<2471> A_IWL<2470> A_IWL<2469> A_IWL<2468> A_IWL<2467> A_IWL<2466> A_IWL<2465> A_IWL<2464> A_IWL<2463> A_IWL<2462> A_IWL<2461> A_IWL<2460> A_IWL<2459> A_IWL<2458> A_IWL<2457> A_IWL<2456> A_IWL<2455> A_IWL<2454> A_IWL<2453> A_IWL<2452> A_IWL<2451> A_IWL<2450> A_IWL<2449> A_IWL<2448> A_IWL<2447> A_IWL<2446> A_IWL<2445> A_IWL<2444> A_IWL<2443> A_IWL<2442> A_IWL<2441> A_IWL<2440> A_IWL<2439> A_IWL<2438> A_IWL<2437> A_IWL<2436> A_IWL<2435> A_IWL<2434> A_IWL<2433> A_IWL<2432> A_IWL<2431> A_IWL<2430> A_IWL<2429> A_IWL<2428> A_IWL<2427> A_IWL<2426> A_IWL<2425> A_IWL<2424> A_IWL<2423> A_IWL<2422> A_IWL<2421> A_IWL<2420> A_IWL<2419> A_IWL<2418> A_IWL<2417> A_IWL<2416> A_IWL<2415> A_IWL<2414> A_IWL<2413> A_IWL<2412> A_IWL<2411> A_IWL<2410> A_IWL<2409> A_IWL<2408> A_IWL<2407> A_IWL<2406> A_IWL<2405> A_IWL<2404> A_IWL<2403> A_IWL<2402> A_IWL<2401> A_IWL<2400> A_IWL<2399> A_IWL<2398> A_IWL<2397> A_IWL<2396> A_IWL<2395> A_IWL<2394> A_IWL<2393> A_IWL<2392> A_IWL<2391> A_IWL<2390> A_IWL<2389> A_IWL<2388> A_IWL<2387> A_IWL<2386> A_IWL<2385> A_IWL<2384> A_IWL<2383> A_IWL<2382> A_IWL<2381> A_IWL<2380> A_IWL<2379> A_IWL<2378> A_IWL<2377> A_IWL<2376> A_IWL<2375> A_IWL<2374> A_IWL<2373> A_IWL<2372> A_IWL<2371> A_IWL<2370> A_IWL<2369> A_IWL<2368> A_IWL<2367> A_IWL<2366> A_IWL<2365> A_IWL<2364> A_IWL<2363> A_IWL<2362> A_IWL<2361> A_IWL<2360> A_IWL<2359> A_IWL<2358> A_IWL<2357> A_IWL<2356> A_IWL<2355> A_IWL<2354> A_IWL<2353> A_IWL<2352> A_IWL<2351> A_IWL<2350> A_IWL<2349> A_IWL<2348> A_IWL<2347> A_IWL<2346> A_IWL<2345> A_IWL<2344> A_IWL<2343> A_IWL<2342> A_IWL<2341> A_IWL<2340> A_IWL<2339> A_IWL<2338> A_IWL<2337> A_IWL<2336> A_IWL<2335> A_IWL<2334> A_IWL<2333> A_IWL<2332> A_IWL<2331> A_IWL<2330> A_IWL<2329> A_IWL<2328> A_IWL<2327> A_IWL<2326> A_IWL<2325> A_IWL<2324> A_IWL<2323> A_IWL<2322> A_IWL<2321> A_IWL<2320> A_IWL<2319> A_IWL<2318> A_IWL<2317> A_IWL<2316> A_IWL<2315> A_IWL<2314> A_IWL<2313> A_IWL<2312> A_IWL<2311> A_IWL<2310> A_IWL<2309> A_IWL<2308> A_IWL<2307> A_IWL<2306> A_IWL<2305> A_IWL<2304> A_IWL<2815> A_IWL<2814> A_IWL<2813> A_IWL<2812> A_IWL<2811> A_IWL<2810> A_IWL<2809> A_IWL<2808> A_IWL<2807> A_IWL<2806> A_IWL<2805> A_IWL<2804> A_IWL<2803> A_IWL<2802> A_IWL<2801> A_IWL<2800> A_IWL<2799> A_IWL<2798> A_IWL<2797> A_IWL<2796> A_IWL<2795> A_IWL<2794> A_IWL<2793> A_IWL<2792> A_IWL<2791> A_IWL<2790> A_IWL<2789> A_IWL<2788> A_IWL<2787> A_IWL<2786> A_IWL<2785> A_IWL<2784> A_IWL<2783> A_IWL<2782> A_IWL<2781> A_IWL<2780> A_IWL<2779> A_IWL<2778> A_IWL<2777> A_IWL<2776> A_IWL<2775> A_IWL<2774> A_IWL<2773> A_IWL<2772> A_IWL<2771> A_IWL<2770> A_IWL<2769> A_IWL<2768> A_IWL<2767> A_IWL<2766> A_IWL<2765> A_IWL<2764> A_IWL<2763> A_IWL<2762> A_IWL<2761> A_IWL<2760> A_IWL<2759> A_IWL<2758> A_IWL<2757> A_IWL<2756> A_IWL<2755> A_IWL<2754> A_IWL<2753> A_IWL<2752> A_IWL<2751> A_IWL<2750> A_IWL<2749> A_IWL<2748> A_IWL<2747> A_IWL<2746> A_IWL<2745> A_IWL<2744> A_IWL<2743> A_IWL<2742> A_IWL<2741> A_IWL<2740> A_IWL<2739> A_IWL<2738> A_IWL<2737> A_IWL<2736> A_IWL<2735> A_IWL<2734> A_IWL<2733> A_IWL<2732> A_IWL<2731> A_IWL<2730> A_IWL<2729> A_IWL<2728> A_IWL<2727> A_IWL<2726> A_IWL<2725> A_IWL<2724> A_IWL<2723> A_IWL<2722> A_IWL<2721> A_IWL<2720> A_IWL<2719> A_IWL<2718> A_IWL<2717> A_IWL<2716> A_IWL<2715> A_IWL<2714> A_IWL<2713> A_IWL<2712> A_IWL<2711> A_IWL<2710> A_IWL<2709> A_IWL<2708> A_IWL<2707> A_IWL<2706> A_IWL<2705> A_IWL<2704> A_IWL<2703> A_IWL<2702> A_IWL<2701> A_IWL<2700> A_IWL<2699> A_IWL<2698> A_IWL<2697> A_IWL<2696> A_IWL<2695> A_IWL<2694> A_IWL<2693> A_IWL<2692> A_IWL<2691> A_IWL<2690> A_IWL<2689> A_IWL<2688> A_IWL<2687> A_IWL<2686> A_IWL<2685> A_IWL<2684> A_IWL<2683> A_IWL<2682> A_IWL<2681> A_IWL<2680> A_IWL<2679> A_IWL<2678> A_IWL<2677> A_IWL<2676> A_IWL<2675> A_IWL<2674> A_IWL<2673> A_IWL<2672> A_IWL<2671> A_IWL<2670> A_IWL<2669> A_IWL<2668> A_IWL<2667> A_IWL<2666> A_IWL<2665> A_IWL<2664> A_IWL<2663> A_IWL<2662> A_IWL<2661> A_IWL<2660> A_IWL<2659> A_IWL<2658> A_IWL<2657> A_IWL<2656> A_IWL<2655> A_IWL<2654> A_IWL<2653> A_IWL<2652> A_IWL<2651> A_IWL<2650> A_IWL<2649> A_IWL<2648> A_IWL<2647> A_IWL<2646> A_IWL<2645> A_IWL<2644> A_IWL<2643> A_IWL<2642> A_IWL<2641> A_IWL<2640> A_IWL<2639> A_IWL<2638> A_IWL<2637> A_IWL<2636> A_IWL<2635> A_IWL<2634> A_IWL<2633> A_IWL<2632> A_IWL<2631> A_IWL<2630> A_IWL<2629> A_IWL<2628> A_IWL<2627> A_IWL<2626> A_IWL<2625> A_IWL<2624> A_IWL<2623> A_IWL<2622> A_IWL<2621> A_IWL<2620> A_IWL<2619> A_IWL<2618> A_IWL<2617> A_IWL<2616> A_IWL<2615> A_IWL<2614> A_IWL<2613> A_IWL<2612> A_IWL<2611> A_IWL<2610> A_IWL<2609> A_IWL<2608> A_IWL<2607> A_IWL<2606> A_IWL<2605> A_IWL<2604> A_IWL<2603> A_IWL<2602> A_IWL<2601> A_IWL<2600> A_IWL<2599> A_IWL<2598> A_IWL<2597> A_IWL<2596> A_IWL<2595> A_IWL<2594> A_IWL<2593> A_IWL<2592> A_IWL<2591> A_IWL<2590> A_IWL<2589> A_IWL<2588> A_IWL<2587> A_IWL<2586> A_IWL<2585> A_IWL<2584> A_IWL<2583> A_IWL<2582> A_IWL<2581> A_IWL<2580> A_IWL<2579> A_IWL<2578> A_IWL<2577> A_IWL<2576> A_IWL<2575> A_IWL<2574> A_IWL<2573> A_IWL<2572> A_IWL<2571> A_IWL<2570> A_IWL<2569> A_IWL<2568> A_IWL<2567> A_IWL<2566> A_IWL<2565> A_IWL<2564> A_IWL<2563> A_IWL<2562> A_IWL<2561> A_IWL<2560> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_COLUMN_pcell_0 +XCOL<9> A_BLC<19> A_BLC<18> A_BLC_TOP<19> A_BLC_TOP<18> A_BLT<19> A_BLT<18> A_BLT_TOP<19> A_BLT_TOP<18> A_IWL<2303> A_IWL<2302> A_IWL<2301> A_IWL<2300> A_IWL<2299> A_IWL<2298> A_IWL<2297> A_IWL<2296> A_IWL<2295> A_IWL<2294> A_IWL<2293> A_IWL<2292> A_IWL<2291> A_IWL<2290> A_IWL<2289> A_IWL<2288> A_IWL<2287> A_IWL<2286> A_IWL<2285> A_IWL<2284> A_IWL<2283> A_IWL<2282> A_IWL<2281> A_IWL<2280> A_IWL<2279> A_IWL<2278> A_IWL<2277> A_IWL<2276> A_IWL<2275> A_IWL<2274> A_IWL<2273> A_IWL<2272> A_IWL<2271> A_IWL<2270> A_IWL<2269> A_IWL<2268> A_IWL<2267> A_IWL<2266> A_IWL<2265> A_IWL<2264> A_IWL<2263> A_IWL<2262> A_IWL<2261> A_IWL<2260> A_IWL<2259> A_IWL<2258> A_IWL<2257> A_IWL<2256> A_IWL<2255> A_IWL<2254> A_IWL<2253> A_IWL<2252> A_IWL<2251> A_IWL<2250> A_IWL<2249> A_IWL<2248> A_IWL<2247> A_IWL<2246> A_IWL<2245> A_IWL<2244> A_IWL<2243> A_IWL<2242> A_IWL<2241> A_IWL<2240> A_IWL<2239> A_IWL<2238> A_IWL<2237> A_IWL<2236> A_IWL<2235> A_IWL<2234> A_IWL<2233> A_IWL<2232> A_IWL<2231> A_IWL<2230> A_IWL<2229> A_IWL<2228> A_IWL<2227> A_IWL<2226> A_IWL<2225> A_IWL<2224> A_IWL<2223> A_IWL<2222> A_IWL<2221> A_IWL<2220> A_IWL<2219> A_IWL<2218> A_IWL<2217> A_IWL<2216> A_IWL<2215> A_IWL<2214> A_IWL<2213> A_IWL<2212> A_IWL<2211> A_IWL<2210> A_IWL<2209> A_IWL<2208> A_IWL<2207> A_IWL<2206> A_IWL<2205> A_IWL<2204> A_IWL<2203> A_IWL<2202> A_IWL<2201> A_IWL<2200> A_IWL<2199> A_IWL<2198> A_IWL<2197> A_IWL<2196> A_IWL<2195> A_IWL<2194> A_IWL<2193> A_IWL<2192> A_IWL<2191> A_IWL<2190> A_IWL<2189> A_IWL<2188> A_IWL<2187> A_IWL<2186> A_IWL<2185> A_IWL<2184> A_IWL<2183> A_IWL<2182> A_IWL<2181> A_IWL<2180> A_IWL<2179> A_IWL<2178> A_IWL<2177> A_IWL<2176> A_IWL<2175> A_IWL<2174> A_IWL<2173> A_IWL<2172> A_IWL<2171> A_IWL<2170> A_IWL<2169> A_IWL<2168> A_IWL<2167> A_IWL<2166> A_IWL<2165> A_IWL<2164> A_IWL<2163> A_IWL<2162> A_IWL<2161> A_IWL<2160> A_IWL<2159> A_IWL<2158> A_IWL<2157> A_IWL<2156> A_IWL<2155> A_IWL<2154> A_IWL<2153> A_IWL<2152> A_IWL<2151> A_IWL<2150> A_IWL<2149> A_IWL<2148> A_IWL<2147> A_IWL<2146> A_IWL<2145> A_IWL<2144> A_IWL<2143> A_IWL<2142> A_IWL<2141> A_IWL<2140> A_IWL<2139> A_IWL<2138> A_IWL<2137> A_IWL<2136> A_IWL<2135> A_IWL<2134> A_IWL<2133> A_IWL<2132> A_IWL<2131> A_IWL<2130> A_IWL<2129> A_IWL<2128> A_IWL<2127> A_IWL<2126> A_IWL<2125> A_IWL<2124> A_IWL<2123> A_IWL<2122> A_IWL<2121> A_IWL<2120> A_IWL<2119> A_IWL<2118> A_IWL<2117> A_IWL<2116> A_IWL<2115> A_IWL<2114> A_IWL<2113> A_IWL<2112> A_IWL<2111> A_IWL<2110> A_IWL<2109> A_IWL<2108> A_IWL<2107> A_IWL<2106> A_IWL<2105> A_IWL<2104> A_IWL<2103> A_IWL<2102> A_IWL<2101> A_IWL<2100> A_IWL<2099> A_IWL<2098> A_IWL<2097> A_IWL<2096> A_IWL<2095> A_IWL<2094> A_IWL<2093> A_IWL<2092> A_IWL<2091> A_IWL<2090> A_IWL<2089> A_IWL<2088> A_IWL<2087> A_IWL<2086> A_IWL<2085> A_IWL<2084> A_IWL<2083> A_IWL<2082> A_IWL<2081> A_IWL<2080> A_IWL<2079> A_IWL<2078> A_IWL<2077> A_IWL<2076> A_IWL<2075> A_IWL<2074> A_IWL<2073> A_IWL<2072> A_IWL<2071> A_IWL<2070> A_IWL<2069> A_IWL<2068> A_IWL<2067> A_IWL<2066> A_IWL<2065> A_IWL<2064> A_IWL<2063> A_IWL<2062> A_IWL<2061> A_IWL<2060> A_IWL<2059> A_IWL<2058> A_IWL<2057> A_IWL<2056> A_IWL<2055> A_IWL<2054> A_IWL<2053> A_IWL<2052> A_IWL<2051> A_IWL<2050> A_IWL<2049> A_IWL<2048> A_IWL<2559> A_IWL<2558> A_IWL<2557> A_IWL<2556> A_IWL<2555> A_IWL<2554> A_IWL<2553> A_IWL<2552> A_IWL<2551> A_IWL<2550> A_IWL<2549> A_IWL<2548> A_IWL<2547> A_IWL<2546> A_IWL<2545> A_IWL<2544> A_IWL<2543> A_IWL<2542> A_IWL<2541> A_IWL<2540> A_IWL<2539> A_IWL<2538> A_IWL<2537> A_IWL<2536> A_IWL<2535> A_IWL<2534> A_IWL<2533> A_IWL<2532> A_IWL<2531> A_IWL<2530> A_IWL<2529> A_IWL<2528> A_IWL<2527> A_IWL<2526> A_IWL<2525> A_IWL<2524> A_IWL<2523> A_IWL<2522> A_IWL<2521> A_IWL<2520> A_IWL<2519> A_IWL<2518> A_IWL<2517> A_IWL<2516> A_IWL<2515> A_IWL<2514> A_IWL<2513> A_IWL<2512> A_IWL<2511> A_IWL<2510> A_IWL<2509> A_IWL<2508> A_IWL<2507> A_IWL<2506> A_IWL<2505> A_IWL<2504> A_IWL<2503> A_IWL<2502> A_IWL<2501> A_IWL<2500> A_IWL<2499> A_IWL<2498> A_IWL<2497> A_IWL<2496> A_IWL<2495> A_IWL<2494> A_IWL<2493> A_IWL<2492> A_IWL<2491> A_IWL<2490> A_IWL<2489> A_IWL<2488> A_IWL<2487> A_IWL<2486> A_IWL<2485> A_IWL<2484> A_IWL<2483> A_IWL<2482> A_IWL<2481> A_IWL<2480> A_IWL<2479> A_IWL<2478> A_IWL<2477> A_IWL<2476> A_IWL<2475> A_IWL<2474> A_IWL<2473> A_IWL<2472> A_IWL<2471> A_IWL<2470> A_IWL<2469> A_IWL<2468> A_IWL<2467> A_IWL<2466> A_IWL<2465> A_IWL<2464> A_IWL<2463> A_IWL<2462> A_IWL<2461> A_IWL<2460> A_IWL<2459> A_IWL<2458> A_IWL<2457> A_IWL<2456> A_IWL<2455> A_IWL<2454> A_IWL<2453> A_IWL<2452> A_IWL<2451> A_IWL<2450> A_IWL<2449> A_IWL<2448> A_IWL<2447> A_IWL<2446> A_IWL<2445> A_IWL<2444> A_IWL<2443> A_IWL<2442> A_IWL<2441> A_IWL<2440> A_IWL<2439> A_IWL<2438> A_IWL<2437> A_IWL<2436> A_IWL<2435> A_IWL<2434> A_IWL<2433> A_IWL<2432> A_IWL<2431> A_IWL<2430> A_IWL<2429> A_IWL<2428> A_IWL<2427> A_IWL<2426> A_IWL<2425> A_IWL<2424> A_IWL<2423> A_IWL<2422> A_IWL<2421> A_IWL<2420> A_IWL<2419> A_IWL<2418> A_IWL<2417> A_IWL<2416> A_IWL<2415> A_IWL<2414> A_IWL<2413> A_IWL<2412> A_IWL<2411> A_IWL<2410> A_IWL<2409> A_IWL<2408> A_IWL<2407> A_IWL<2406> A_IWL<2405> A_IWL<2404> A_IWL<2403> A_IWL<2402> A_IWL<2401> A_IWL<2400> A_IWL<2399> A_IWL<2398> A_IWL<2397> A_IWL<2396> A_IWL<2395> A_IWL<2394> A_IWL<2393> A_IWL<2392> A_IWL<2391> A_IWL<2390> A_IWL<2389> A_IWL<2388> A_IWL<2387> A_IWL<2386> A_IWL<2385> A_IWL<2384> A_IWL<2383> A_IWL<2382> A_IWL<2381> A_IWL<2380> A_IWL<2379> A_IWL<2378> A_IWL<2377> A_IWL<2376> A_IWL<2375> A_IWL<2374> A_IWL<2373> A_IWL<2372> A_IWL<2371> A_IWL<2370> A_IWL<2369> A_IWL<2368> A_IWL<2367> A_IWL<2366> A_IWL<2365> A_IWL<2364> A_IWL<2363> A_IWL<2362> A_IWL<2361> A_IWL<2360> A_IWL<2359> A_IWL<2358> A_IWL<2357> A_IWL<2356> A_IWL<2355> A_IWL<2354> A_IWL<2353> A_IWL<2352> A_IWL<2351> A_IWL<2350> A_IWL<2349> A_IWL<2348> A_IWL<2347> A_IWL<2346> A_IWL<2345> A_IWL<2344> A_IWL<2343> A_IWL<2342> A_IWL<2341> A_IWL<2340> A_IWL<2339> A_IWL<2338> A_IWL<2337> A_IWL<2336> A_IWL<2335> A_IWL<2334> A_IWL<2333> A_IWL<2332> A_IWL<2331> A_IWL<2330> A_IWL<2329> A_IWL<2328> A_IWL<2327> A_IWL<2326> A_IWL<2325> A_IWL<2324> A_IWL<2323> A_IWL<2322> A_IWL<2321> A_IWL<2320> A_IWL<2319> A_IWL<2318> A_IWL<2317> A_IWL<2316> A_IWL<2315> A_IWL<2314> A_IWL<2313> A_IWL<2312> A_IWL<2311> A_IWL<2310> A_IWL<2309> A_IWL<2308> A_IWL<2307> A_IWL<2306> A_IWL<2305> A_IWL<2304> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_COLUMN_pcell_0 +XCOL<8> A_BLC<17> A_BLC<16> A_BLC_TOP<17> A_BLC_TOP<16> A_BLT<17> A_BLT<16> A_BLT_TOP<17> A_BLT_TOP<16> A_IWL<2047> A_IWL<2046> A_IWL<2045> A_IWL<2044> A_IWL<2043> A_IWL<2042> A_IWL<2041> A_IWL<2040> A_IWL<2039> A_IWL<2038> A_IWL<2037> A_IWL<2036> A_IWL<2035> A_IWL<2034> A_IWL<2033> A_IWL<2032> A_IWL<2031> A_IWL<2030> A_IWL<2029> A_IWL<2028> A_IWL<2027> A_IWL<2026> A_IWL<2025> A_IWL<2024> A_IWL<2023> A_IWL<2022> A_IWL<2021> A_IWL<2020> A_IWL<2019> A_IWL<2018> A_IWL<2017> A_IWL<2016> A_IWL<2015> A_IWL<2014> A_IWL<2013> A_IWL<2012> A_IWL<2011> A_IWL<2010> A_IWL<2009> A_IWL<2008> A_IWL<2007> A_IWL<2006> A_IWL<2005> A_IWL<2004> A_IWL<2003> A_IWL<2002> A_IWL<2001> A_IWL<2000> A_IWL<1999> A_IWL<1998> A_IWL<1997> A_IWL<1996> A_IWL<1995> A_IWL<1994> A_IWL<1993> A_IWL<1992> A_IWL<1991> A_IWL<1990> A_IWL<1989> A_IWL<1988> A_IWL<1987> A_IWL<1986> A_IWL<1985> A_IWL<1984> A_IWL<1983> A_IWL<1982> A_IWL<1981> A_IWL<1980> A_IWL<1979> A_IWL<1978> A_IWL<1977> A_IWL<1976> A_IWL<1975> A_IWL<1974> A_IWL<1973> A_IWL<1972> A_IWL<1971> A_IWL<1970> A_IWL<1969> A_IWL<1968> A_IWL<1967> A_IWL<1966> A_IWL<1965> A_IWL<1964> A_IWL<1963> A_IWL<1962> A_IWL<1961> A_IWL<1960> A_IWL<1959> A_IWL<1958> A_IWL<1957> A_IWL<1956> A_IWL<1955> A_IWL<1954> A_IWL<1953> A_IWL<1952> A_IWL<1951> A_IWL<1950> A_IWL<1949> A_IWL<1948> A_IWL<1947> A_IWL<1946> A_IWL<1945> A_IWL<1944> A_IWL<1943> A_IWL<1942> A_IWL<1941> A_IWL<1940> A_IWL<1939> A_IWL<1938> A_IWL<1937> A_IWL<1936> A_IWL<1935> A_IWL<1934> A_IWL<1933> A_IWL<1932> A_IWL<1931> A_IWL<1930> A_IWL<1929> A_IWL<1928> A_IWL<1927> A_IWL<1926> A_IWL<1925> A_IWL<1924> A_IWL<1923> A_IWL<1922> A_IWL<1921> A_IWL<1920> A_IWL<1919> A_IWL<1918> A_IWL<1917> A_IWL<1916> A_IWL<1915> A_IWL<1914> A_IWL<1913> A_IWL<1912> A_IWL<1911> A_IWL<1910> A_IWL<1909> A_IWL<1908> A_IWL<1907> A_IWL<1906> A_IWL<1905> A_IWL<1904> A_IWL<1903> A_IWL<1902> A_IWL<1901> A_IWL<1900> A_IWL<1899> A_IWL<1898> A_IWL<1897> A_IWL<1896> A_IWL<1895> A_IWL<1894> A_IWL<1893> A_IWL<1892> A_IWL<1891> A_IWL<1890> A_IWL<1889> A_IWL<1888> A_IWL<1887> A_IWL<1886> A_IWL<1885> A_IWL<1884> A_IWL<1883> A_IWL<1882> A_IWL<1881> A_IWL<1880> A_IWL<1879> A_IWL<1878> A_IWL<1877> A_IWL<1876> A_IWL<1875> A_IWL<1874> A_IWL<1873> A_IWL<1872> A_IWL<1871> A_IWL<1870> A_IWL<1869> A_IWL<1868> A_IWL<1867> A_IWL<1866> A_IWL<1865> A_IWL<1864> A_IWL<1863> A_IWL<1862> A_IWL<1861> A_IWL<1860> A_IWL<1859> A_IWL<1858> A_IWL<1857> A_IWL<1856> A_IWL<1855> A_IWL<1854> A_IWL<1853> A_IWL<1852> A_IWL<1851> A_IWL<1850> A_IWL<1849> A_IWL<1848> A_IWL<1847> A_IWL<1846> A_IWL<1845> A_IWL<1844> A_IWL<1843> A_IWL<1842> A_IWL<1841> A_IWL<1840> A_IWL<1839> A_IWL<1838> A_IWL<1837> A_IWL<1836> A_IWL<1835> A_IWL<1834> A_IWL<1833> A_IWL<1832> A_IWL<1831> A_IWL<1830> A_IWL<1829> A_IWL<1828> A_IWL<1827> A_IWL<1826> A_IWL<1825> A_IWL<1824> A_IWL<1823> A_IWL<1822> A_IWL<1821> A_IWL<1820> A_IWL<1819> A_IWL<1818> A_IWL<1817> A_IWL<1816> A_IWL<1815> A_IWL<1814> A_IWL<1813> A_IWL<1812> A_IWL<1811> A_IWL<1810> A_IWL<1809> A_IWL<1808> A_IWL<1807> A_IWL<1806> A_IWL<1805> A_IWL<1804> A_IWL<1803> A_IWL<1802> A_IWL<1801> A_IWL<1800> A_IWL<1799> A_IWL<1798> A_IWL<1797> A_IWL<1796> A_IWL<1795> A_IWL<1794> A_IWL<1793> A_IWL<1792> A_IWL<2303> A_IWL<2302> A_IWL<2301> A_IWL<2300> A_IWL<2299> A_IWL<2298> A_IWL<2297> A_IWL<2296> A_IWL<2295> A_IWL<2294> A_IWL<2293> A_IWL<2292> A_IWL<2291> A_IWL<2290> A_IWL<2289> A_IWL<2288> A_IWL<2287> A_IWL<2286> A_IWL<2285> A_IWL<2284> A_IWL<2283> A_IWL<2282> A_IWL<2281> A_IWL<2280> A_IWL<2279> A_IWL<2278> A_IWL<2277> A_IWL<2276> A_IWL<2275> A_IWL<2274> A_IWL<2273> A_IWL<2272> A_IWL<2271> A_IWL<2270> A_IWL<2269> A_IWL<2268> A_IWL<2267> A_IWL<2266> A_IWL<2265> A_IWL<2264> A_IWL<2263> A_IWL<2262> A_IWL<2261> A_IWL<2260> A_IWL<2259> A_IWL<2258> A_IWL<2257> A_IWL<2256> A_IWL<2255> A_IWL<2254> A_IWL<2253> A_IWL<2252> A_IWL<2251> A_IWL<2250> A_IWL<2249> A_IWL<2248> A_IWL<2247> A_IWL<2246> A_IWL<2245> A_IWL<2244> A_IWL<2243> A_IWL<2242> A_IWL<2241> A_IWL<2240> A_IWL<2239> A_IWL<2238> A_IWL<2237> A_IWL<2236> A_IWL<2235> A_IWL<2234> A_IWL<2233> A_IWL<2232> A_IWL<2231> A_IWL<2230> A_IWL<2229> A_IWL<2228> A_IWL<2227> A_IWL<2226> A_IWL<2225> A_IWL<2224> A_IWL<2223> A_IWL<2222> A_IWL<2221> A_IWL<2220> A_IWL<2219> A_IWL<2218> A_IWL<2217> A_IWL<2216> A_IWL<2215> A_IWL<2214> A_IWL<2213> A_IWL<2212> A_IWL<2211> A_IWL<2210> A_IWL<2209> A_IWL<2208> A_IWL<2207> A_IWL<2206> A_IWL<2205> A_IWL<2204> A_IWL<2203> A_IWL<2202> A_IWL<2201> A_IWL<2200> A_IWL<2199> A_IWL<2198> A_IWL<2197> A_IWL<2196> A_IWL<2195> A_IWL<2194> A_IWL<2193> A_IWL<2192> A_IWL<2191> A_IWL<2190> A_IWL<2189> A_IWL<2188> A_IWL<2187> A_IWL<2186> A_IWL<2185> A_IWL<2184> A_IWL<2183> A_IWL<2182> A_IWL<2181> A_IWL<2180> A_IWL<2179> A_IWL<2178> A_IWL<2177> A_IWL<2176> A_IWL<2175> A_IWL<2174> A_IWL<2173> A_IWL<2172> A_IWL<2171> A_IWL<2170> A_IWL<2169> A_IWL<2168> A_IWL<2167> A_IWL<2166> A_IWL<2165> A_IWL<2164> A_IWL<2163> A_IWL<2162> A_IWL<2161> A_IWL<2160> A_IWL<2159> A_IWL<2158> A_IWL<2157> A_IWL<2156> A_IWL<2155> A_IWL<2154> A_IWL<2153> A_IWL<2152> A_IWL<2151> A_IWL<2150> A_IWL<2149> A_IWL<2148> A_IWL<2147> A_IWL<2146> A_IWL<2145> A_IWL<2144> A_IWL<2143> A_IWL<2142> A_IWL<2141> A_IWL<2140> A_IWL<2139> A_IWL<2138> A_IWL<2137> A_IWL<2136> A_IWL<2135> A_IWL<2134> A_IWL<2133> A_IWL<2132> A_IWL<2131> A_IWL<2130> A_IWL<2129> A_IWL<2128> A_IWL<2127> A_IWL<2126> A_IWL<2125> A_IWL<2124> A_IWL<2123> A_IWL<2122> A_IWL<2121> A_IWL<2120> A_IWL<2119> A_IWL<2118> A_IWL<2117> A_IWL<2116> A_IWL<2115> A_IWL<2114> A_IWL<2113> A_IWL<2112> A_IWL<2111> A_IWL<2110> A_IWL<2109> A_IWL<2108> A_IWL<2107> A_IWL<2106> A_IWL<2105> A_IWL<2104> A_IWL<2103> A_IWL<2102> A_IWL<2101> A_IWL<2100> A_IWL<2099> A_IWL<2098> A_IWL<2097> A_IWL<2096> A_IWL<2095> A_IWL<2094> A_IWL<2093> A_IWL<2092> A_IWL<2091> A_IWL<2090> A_IWL<2089> A_IWL<2088> A_IWL<2087> A_IWL<2086> A_IWL<2085> A_IWL<2084> A_IWL<2083> A_IWL<2082> A_IWL<2081> A_IWL<2080> A_IWL<2079> A_IWL<2078> A_IWL<2077> A_IWL<2076> A_IWL<2075> A_IWL<2074> A_IWL<2073> A_IWL<2072> A_IWL<2071> A_IWL<2070> A_IWL<2069> A_IWL<2068> A_IWL<2067> A_IWL<2066> A_IWL<2065> A_IWL<2064> A_IWL<2063> A_IWL<2062> A_IWL<2061> A_IWL<2060> A_IWL<2059> A_IWL<2058> A_IWL<2057> A_IWL<2056> A_IWL<2055> A_IWL<2054> A_IWL<2053> A_IWL<2052> A_IWL<2051> A_IWL<2050> A_IWL<2049> A_IWL<2048> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_COLUMN_pcell_0 +XCOL<7> A_BLC<15> A_BLC<14> A_BLC_TOP<15> A_BLC_TOP<14> A_BLT<15> A_BLT<14> A_BLT_TOP<15> A_BLT_TOP<14> A_IWL<1791> A_IWL<1790> A_IWL<1789> A_IWL<1788> A_IWL<1787> A_IWL<1786> A_IWL<1785> A_IWL<1784> A_IWL<1783> A_IWL<1782> A_IWL<1781> A_IWL<1780> A_IWL<1779> A_IWL<1778> A_IWL<1777> A_IWL<1776> A_IWL<1775> A_IWL<1774> A_IWL<1773> A_IWL<1772> A_IWL<1771> A_IWL<1770> A_IWL<1769> A_IWL<1768> A_IWL<1767> A_IWL<1766> A_IWL<1765> A_IWL<1764> A_IWL<1763> A_IWL<1762> A_IWL<1761> A_IWL<1760> A_IWL<1759> A_IWL<1758> A_IWL<1757> A_IWL<1756> A_IWL<1755> A_IWL<1754> A_IWL<1753> A_IWL<1752> A_IWL<1751> A_IWL<1750> A_IWL<1749> A_IWL<1748> A_IWL<1747> A_IWL<1746> A_IWL<1745> A_IWL<1744> A_IWL<1743> A_IWL<1742> A_IWL<1741> A_IWL<1740> A_IWL<1739> A_IWL<1738> A_IWL<1737> A_IWL<1736> A_IWL<1735> A_IWL<1734> A_IWL<1733> A_IWL<1732> A_IWL<1731> A_IWL<1730> A_IWL<1729> A_IWL<1728> A_IWL<1727> A_IWL<1726> A_IWL<1725> A_IWL<1724> A_IWL<1723> A_IWL<1722> A_IWL<1721> A_IWL<1720> A_IWL<1719> A_IWL<1718> A_IWL<1717> A_IWL<1716> A_IWL<1715> A_IWL<1714> A_IWL<1713> A_IWL<1712> A_IWL<1711> A_IWL<1710> A_IWL<1709> A_IWL<1708> A_IWL<1707> A_IWL<1706> A_IWL<1705> A_IWL<1704> A_IWL<1703> A_IWL<1702> A_IWL<1701> A_IWL<1700> A_IWL<1699> A_IWL<1698> A_IWL<1697> A_IWL<1696> A_IWL<1695> A_IWL<1694> A_IWL<1693> A_IWL<1692> A_IWL<1691> A_IWL<1690> A_IWL<1689> A_IWL<1688> A_IWL<1687> A_IWL<1686> A_IWL<1685> A_IWL<1684> A_IWL<1683> A_IWL<1682> A_IWL<1681> A_IWL<1680> A_IWL<1679> A_IWL<1678> A_IWL<1677> A_IWL<1676> A_IWL<1675> A_IWL<1674> A_IWL<1673> A_IWL<1672> A_IWL<1671> A_IWL<1670> A_IWL<1669> A_IWL<1668> A_IWL<1667> A_IWL<1666> A_IWL<1665> A_IWL<1664> A_IWL<1663> A_IWL<1662> A_IWL<1661> A_IWL<1660> A_IWL<1659> A_IWL<1658> A_IWL<1657> A_IWL<1656> A_IWL<1655> A_IWL<1654> A_IWL<1653> A_IWL<1652> A_IWL<1651> A_IWL<1650> A_IWL<1649> A_IWL<1648> A_IWL<1647> A_IWL<1646> A_IWL<1645> A_IWL<1644> A_IWL<1643> A_IWL<1642> A_IWL<1641> A_IWL<1640> A_IWL<1639> A_IWL<1638> A_IWL<1637> A_IWL<1636> A_IWL<1635> A_IWL<1634> A_IWL<1633> A_IWL<1632> A_IWL<1631> A_IWL<1630> A_IWL<1629> A_IWL<1628> A_IWL<1627> A_IWL<1626> A_IWL<1625> A_IWL<1624> A_IWL<1623> A_IWL<1622> A_IWL<1621> A_IWL<1620> A_IWL<1619> A_IWL<1618> A_IWL<1617> A_IWL<1616> A_IWL<1615> A_IWL<1614> A_IWL<1613> A_IWL<1612> A_IWL<1611> A_IWL<1610> A_IWL<1609> A_IWL<1608> A_IWL<1607> A_IWL<1606> A_IWL<1605> A_IWL<1604> A_IWL<1603> A_IWL<1602> A_IWL<1601> A_IWL<1600> A_IWL<1599> A_IWL<1598> A_IWL<1597> A_IWL<1596> A_IWL<1595> A_IWL<1594> A_IWL<1593> A_IWL<1592> A_IWL<1591> A_IWL<1590> A_IWL<1589> A_IWL<1588> A_IWL<1587> A_IWL<1586> A_IWL<1585> A_IWL<1584> A_IWL<1583> A_IWL<1582> A_IWL<1581> A_IWL<1580> A_IWL<1579> A_IWL<1578> A_IWL<1577> A_IWL<1576> A_IWL<1575> A_IWL<1574> A_IWL<1573> A_IWL<1572> A_IWL<1571> A_IWL<1570> A_IWL<1569> A_IWL<1568> A_IWL<1567> A_IWL<1566> A_IWL<1565> A_IWL<1564> A_IWL<1563> A_IWL<1562> A_IWL<1561> A_IWL<1560> A_IWL<1559> A_IWL<1558> A_IWL<1557> A_IWL<1556> A_IWL<1555> A_IWL<1554> A_IWL<1553> A_IWL<1552> A_IWL<1551> A_IWL<1550> A_IWL<1549> A_IWL<1548> A_IWL<1547> A_IWL<1546> A_IWL<1545> A_IWL<1544> A_IWL<1543> A_IWL<1542> A_IWL<1541> A_IWL<1540> A_IWL<1539> A_IWL<1538> A_IWL<1537> A_IWL<1536> A_IWL<2047> A_IWL<2046> A_IWL<2045> A_IWL<2044> A_IWL<2043> A_IWL<2042> A_IWL<2041> A_IWL<2040> A_IWL<2039> A_IWL<2038> A_IWL<2037> A_IWL<2036> A_IWL<2035> A_IWL<2034> A_IWL<2033> A_IWL<2032> A_IWL<2031> A_IWL<2030> A_IWL<2029> A_IWL<2028> A_IWL<2027> A_IWL<2026> A_IWL<2025> A_IWL<2024> A_IWL<2023> A_IWL<2022> A_IWL<2021> A_IWL<2020> A_IWL<2019> A_IWL<2018> A_IWL<2017> A_IWL<2016> A_IWL<2015> A_IWL<2014> A_IWL<2013> A_IWL<2012> A_IWL<2011> A_IWL<2010> A_IWL<2009> A_IWL<2008> A_IWL<2007> A_IWL<2006> A_IWL<2005> A_IWL<2004> A_IWL<2003> A_IWL<2002> A_IWL<2001> A_IWL<2000> A_IWL<1999> A_IWL<1998> A_IWL<1997> A_IWL<1996> A_IWL<1995> A_IWL<1994> A_IWL<1993> A_IWL<1992> A_IWL<1991> A_IWL<1990> A_IWL<1989> A_IWL<1988> A_IWL<1987> A_IWL<1986> A_IWL<1985> A_IWL<1984> A_IWL<1983> A_IWL<1982> A_IWL<1981> A_IWL<1980> A_IWL<1979> A_IWL<1978> A_IWL<1977> A_IWL<1976> A_IWL<1975> A_IWL<1974> A_IWL<1973> A_IWL<1972> A_IWL<1971> A_IWL<1970> A_IWL<1969> A_IWL<1968> A_IWL<1967> A_IWL<1966> A_IWL<1965> A_IWL<1964> A_IWL<1963> A_IWL<1962> A_IWL<1961> A_IWL<1960> A_IWL<1959> A_IWL<1958> A_IWL<1957> A_IWL<1956> A_IWL<1955> A_IWL<1954> A_IWL<1953> A_IWL<1952> A_IWL<1951> A_IWL<1950> A_IWL<1949> A_IWL<1948> A_IWL<1947> A_IWL<1946> A_IWL<1945> A_IWL<1944> A_IWL<1943> A_IWL<1942> A_IWL<1941> A_IWL<1940> A_IWL<1939> A_IWL<1938> A_IWL<1937> A_IWL<1936> A_IWL<1935> A_IWL<1934> A_IWL<1933> A_IWL<1932> A_IWL<1931> A_IWL<1930> A_IWL<1929> A_IWL<1928> A_IWL<1927> A_IWL<1926> A_IWL<1925> A_IWL<1924> A_IWL<1923> A_IWL<1922> A_IWL<1921> A_IWL<1920> A_IWL<1919> A_IWL<1918> A_IWL<1917> A_IWL<1916> A_IWL<1915> A_IWL<1914> A_IWL<1913> A_IWL<1912> A_IWL<1911> A_IWL<1910> A_IWL<1909> A_IWL<1908> A_IWL<1907> A_IWL<1906> A_IWL<1905> A_IWL<1904> A_IWL<1903> A_IWL<1902> A_IWL<1901> A_IWL<1900> A_IWL<1899> A_IWL<1898> A_IWL<1897> A_IWL<1896> A_IWL<1895> A_IWL<1894> A_IWL<1893> A_IWL<1892> A_IWL<1891> A_IWL<1890> A_IWL<1889> A_IWL<1888> A_IWL<1887> A_IWL<1886> A_IWL<1885> A_IWL<1884> A_IWL<1883> A_IWL<1882> A_IWL<1881> A_IWL<1880> A_IWL<1879> A_IWL<1878> A_IWL<1877> A_IWL<1876> A_IWL<1875> A_IWL<1874> A_IWL<1873> A_IWL<1872> A_IWL<1871> A_IWL<1870> A_IWL<1869> A_IWL<1868> A_IWL<1867> A_IWL<1866> A_IWL<1865> A_IWL<1864> A_IWL<1863> A_IWL<1862> A_IWL<1861> A_IWL<1860> A_IWL<1859> A_IWL<1858> A_IWL<1857> A_IWL<1856> A_IWL<1855> A_IWL<1854> A_IWL<1853> A_IWL<1852> A_IWL<1851> A_IWL<1850> A_IWL<1849> A_IWL<1848> A_IWL<1847> A_IWL<1846> A_IWL<1845> A_IWL<1844> A_IWL<1843> A_IWL<1842> A_IWL<1841> A_IWL<1840> A_IWL<1839> A_IWL<1838> A_IWL<1837> A_IWL<1836> A_IWL<1835> A_IWL<1834> A_IWL<1833> A_IWL<1832> A_IWL<1831> A_IWL<1830> A_IWL<1829> A_IWL<1828> A_IWL<1827> A_IWL<1826> A_IWL<1825> A_IWL<1824> A_IWL<1823> A_IWL<1822> A_IWL<1821> A_IWL<1820> A_IWL<1819> A_IWL<1818> A_IWL<1817> A_IWL<1816> A_IWL<1815> A_IWL<1814> A_IWL<1813> A_IWL<1812> A_IWL<1811> A_IWL<1810> A_IWL<1809> A_IWL<1808> A_IWL<1807> A_IWL<1806> A_IWL<1805> A_IWL<1804> A_IWL<1803> A_IWL<1802> A_IWL<1801> A_IWL<1800> A_IWL<1799> A_IWL<1798> A_IWL<1797> A_IWL<1796> A_IWL<1795> A_IWL<1794> A_IWL<1793> A_IWL<1792> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_COLUMN_pcell_0 +XCOL<6> A_BLC<13> A_BLC<12> A_BLC_TOP<13> A_BLC_TOP<12> A_BLT<13> A_BLT<12> A_BLT_TOP<13> A_BLT_TOP<12> A_IWL<1535> A_IWL<1534> A_IWL<1533> A_IWL<1532> A_IWL<1531> A_IWL<1530> A_IWL<1529> A_IWL<1528> A_IWL<1527> A_IWL<1526> A_IWL<1525> A_IWL<1524> A_IWL<1523> A_IWL<1522> A_IWL<1521> A_IWL<1520> A_IWL<1519> A_IWL<1518> A_IWL<1517> A_IWL<1516> A_IWL<1515> A_IWL<1514> A_IWL<1513> A_IWL<1512> A_IWL<1511> A_IWL<1510> A_IWL<1509> A_IWL<1508> A_IWL<1507> A_IWL<1506> A_IWL<1505> A_IWL<1504> A_IWL<1503> A_IWL<1502> A_IWL<1501> A_IWL<1500> A_IWL<1499> A_IWL<1498> A_IWL<1497> A_IWL<1496> A_IWL<1495> A_IWL<1494> A_IWL<1493> A_IWL<1492> A_IWL<1491> A_IWL<1490> A_IWL<1489> A_IWL<1488> A_IWL<1487> A_IWL<1486> A_IWL<1485> A_IWL<1484> A_IWL<1483> A_IWL<1482> A_IWL<1481> A_IWL<1480> A_IWL<1479> A_IWL<1478> A_IWL<1477> A_IWL<1476> A_IWL<1475> A_IWL<1474> A_IWL<1473> A_IWL<1472> A_IWL<1471> A_IWL<1470> A_IWL<1469> A_IWL<1468> A_IWL<1467> A_IWL<1466> A_IWL<1465> A_IWL<1464> A_IWL<1463> A_IWL<1462> A_IWL<1461> A_IWL<1460> A_IWL<1459> A_IWL<1458> A_IWL<1457> A_IWL<1456> A_IWL<1455> A_IWL<1454> A_IWL<1453> A_IWL<1452> A_IWL<1451> A_IWL<1450> A_IWL<1449> A_IWL<1448> A_IWL<1447> A_IWL<1446> A_IWL<1445> A_IWL<1444> A_IWL<1443> A_IWL<1442> A_IWL<1441> A_IWL<1440> A_IWL<1439> A_IWL<1438> A_IWL<1437> A_IWL<1436> A_IWL<1435> A_IWL<1434> A_IWL<1433> A_IWL<1432> A_IWL<1431> A_IWL<1430> A_IWL<1429> A_IWL<1428> A_IWL<1427> A_IWL<1426> A_IWL<1425> A_IWL<1424> A_IWL<1423> A_IWL<1422> A_IWL<1421> A_IWL<1420> A_IWL<1419> A_IWL<1418> A_IWL<1417> A_IWL<1416> A_IWL<1415> A_IWL<1414> A_IWL<1413> A_IWL<1412> A_IWL<1411> A_IWL<1410> A_IWL<1409> A_IWL<1408> A_IWL<1407> A_IWL<1406> A_IWL<1405> A_IWL<1404> A_IWL<1403> A_IWL<1402> A_IWL<1401> A_IWL<1400> A_IWL<1399> A_IWL<1398> A_IWL<1397> A_IWL<1396> A_IWL<1395> A_IWL<1394> A_IWL<1393> A_IWL<1392> A_IWL<1391> A_IWL<1390> A_IWL<1389> A_IWL<1388> A_IWL<1387> A_IWL<1386> A_IWL<1385> A_IWL<1384> A_IWL<1383> A_IWL<1382> A_IWL<1381> A_IWL<1380> A_IWL<1379> A_IWL<1378> A_IWL<1377> A_IWL<1376> A_IWL<1375> A_IWL<1374> A_IWL<1373> A_IWL<1372> A_IWL<1371> A_IWL<1370> A_IWL<1369> A_IWL<1368> A_IWL<1367> A_IWL<1366> A_IWL<1365> A_IWL<1364> A_IWL<1363> A_IWL<1362> A_IWL<1361> A_IWL<1360> A_IWL<1359> A_IWL<1358> A_IWL<1357> A_IWL<1356> A_IWL<1355> A_IWL<1354> A_IWL<1353> A_IWL<1352> A_IWL<1351> A_IWL<1350> A_IWL<1349> A_IWL<1348> A_IWL<1347> A_IWL<1346> A_IWL<1345> A_IWL<1344> A_IWL<1343> A_IWL<1342> A_IWL<1341> A_IWL<1340> A_IWL<1339> A_IWL<1338> A_IWL<1337> A_IWL<1336> A_IWL<1335> A_IWL<1334> A_IWL<1333> A_IWL<1332> A_IWL<1331> A_IWL<1330> A_IWL<1329> A_IWL<1328> A_IWL<1327> A_IWL<1326> A_IWL<1325> A_IWL<1324> A_IWL<1323> A_IWL<1322> A_IWL<1321> A_IWL<1320> A_IWL<1319> A_IWL<1318> A_IWL<1317> A_IWL<1316> A_IWL<1315> A_IWL<1314> A_IWL<1313> A_IWL<1312> A_IWL<1311> A_IWL<1310> A_IWL<1309> A_IWL<1308> A_IWL<1307> A_IWL<1306> A_IWL<1305> A_IWL<1304> A_IWL<1303> A_IWL<1302> A_IWL<1301> A_IWL<1300> A_IWL<1299> A_IWL<1298> A_IWL<1297> A_IWL<1296> A_IWL<1295> A_IWL<1294> A_IWL<1293> A_IWL<1292> A_IWL<1291> A_IWL<1290> A_IWL<1289> A_IWL<1288> A_IWL<1287> A_IWL<1286> A_IWL<1285> A_IWL<1284> A_IWL<1283> A_IWL<1282> A_IWL<1281> A_IWL<1280> A_IWL<1791> A_IWL<1790> A_IWL<1789> A_IWL<1788> A_IWL<1787> A_IWL<1786> A_IWL<1785> A_IWL<1784> A_IWL<1783> A_IWL<1782> A_IWL<1781> A_IWL<1780> A_IWL<1779> A_IWL<1778> A_IWL<1777> A_IWL<1776> A_IWL<1775> A_IWL<1774> A_IWL<1773> A_IWL<1772> A_IWL<1771> A_IWL<1770> A_IWL<1769> A_IWL<1768> A_IWL<1767> A_IWL<1766> A_IWL<1765> A_IWL<1764> A_IWL<1763> A_IWL<1762> A_IWL<1761> A_IWL<1760> A_IWL<1759> A_IWL<1758> A_IWL<1757> A_IWL<1756> A_IWL<1755> A_IWL<1754> A_IWL<1753> A_IWL<1752> A_IWL<1751> A_IWL<1750> A_IWL<1749> A_IWL<1748> A_IWL<1747> A_IWL<1746> A_IWL<1745> A_IWL<1744> A_IWL<1743> A_IWL<1742> A_IWL<1741> A_IWL<1740> A_IWL<1739> A_IWL<1738> A_IWL<1737> A_IWL<1736> A_IWL<1735> A_IWL<1734> A_IWL<1733> A_IWL<1732> A_IWL<1731> A_IWL<1730> A_IWL<1729> A_IWL<1728> A_IWL<1727> A_IWL<1726> A_IWL<1725> A_IWL<1724> A_IWL<1723> A_IWL<1722> A_IWL<1721> A_IWL<1720> A_IWL<1719> A_IWL<1718> A_IWL<1717> A_IWL<1716> A_IWL<1715> A_IWL<1714> A_IWL<1713> A_IWL<1712> A_IWL<1711> A_IWL<1710> A_IWL<1709> A_IWL<1708> A_IWL<1707> A_IWL<1706> A_IWL<1705> A_IWL<1704> A_IWL<1703> A_IWL<1702> A_IWL<1701> A_IWL<1700> A_IWL<1699> A_IWL<1698> A_IWL<1697> A_IWL<1696> A_IWL<1695> A_IWL<1694> A_IWL<1693> A_IWL<1692> A_IWL<1691> A_IWL<1690> A_IWL<1689> A_IWL<1688> A_IWL<1687> A_IWL<1686> A_IWL<1685> A_IWL<1684> A_IWL<1683> A_IWL<1682> A_IWL<1681> A_IWL<1680> A_IWL<1679> A_IWL<1678> A_IWL<1677> A_IWL<1676> A_IWL<1675> A_IWL<1674> A_IWL<1673> A_IWL<1672> A_IWL<1671> A_IWL<1670> A_IWL<1669> A_IWL<1668> A_IWL<1667> A_IWL<1666> A_IWL<1665> A_IWL<1664> A_IWL<1663> A_IWL<1662> A_IWL<1661> A_IWL<1660> A_IWL<1659> A_IWL<1658> A_IWL<1657> A_IWL<1656> A_IWL<1655> A_IWL<1654> A_IWL<1653> A_IWL<1652> A_IWL<1651> A_IWL<1650> A_IWL<1649> A_IWL<1648> A_IWL<1647> A_IWL<1646> A_IWL<1645> A_IWL<1644> A_IWL<1643> A_IWL<1642> A_IWL<1641> A_IWL<1640> A_IWL<1639> A_IWL<1638> A_IWL<1637> A_IWL<1636> A_IWL<1635> A_IWL<1634> A_IWL<1633> A_IWL<1632> A_IWL<1631> A_IWL<1630> A_IWL<1629> A_IWL<1628> A_IWL<1627> A_IWL<1626> A_IWL<1625> A_IWL<1624> A_IWL<1623> A_IWL<1622> A_IWL<1621> A_IWL<1620> A_IWL<1619> A_IWL<1618> A_IWL<1617> A_IWL<1616> A_IWL<1615> A_IWL<1614> A_IWL<1613> A_IWL<1612> A_IWL<1611> A_IWL<1610> A_IWL<1609> A_IWL<1608> A_IWL<1607> A_IWL<1606> A_IWL<1605> A_IWL<1604> A_IWL<1603> A_IWL<1602> A_IWL<1601> A_IWL<1600> A_IWL<1599> A_IWL<1598> A_IWL<1597> A_IWL<1596> A_IWL<1595> A_IWL<1594> A_IWL<1593> A_IWL<1592> A_IWL<1591> A_IWL<1590> A_IWL<1589> A_IWL<1588> A_IWL<1587> A_IWL<1586> A_IWL<1585> A_IWL<1584> A_IWL<1583> A_IWL<1582> A_IWL<1581> A_IWL<1580> A_IWL<1579> A_IWL<1578> A_IWL<1577> A_IWL<1576> A_IWL<1575> A_IWL<1574> A_IWL<1573> A_IWL<1572> A_IWL<1571> A_IWL<1570> A_IWL<1569> A_IWL<1568> A_IWL<1567> A_IWL<1566> A_IWL<1565> A_IWL<1564> A_IWL<1563> A_IWL<1562> A_IWL<1561> A_IWL<1560> A_IWL<1559> A_IWL<1558> A_IWL<1557> A_IWL<1556> A_IWL<1555> A_IWL<1554> A_IWL<1553> A_IWL<1552> A_IWL<1551> A_IWL<1550> A_IWL<1549> A_IWL<1548> A_IWL<1547> A_IWL<1546> A_IWL<1545> A_IWL<1544> A_IWL<1543> A_IWL<1542> A_IWL<1541> A_IWL<1540> A_IWL<1539> A_IWL<1538> A_IWL<1537> A_IWL<1536> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_COLUMN_pcell_0 +XCOL<5> A_BLC<11> A_BLC<10> A_BLC_TOP<11> A_BLC_TOP<10> A_BLT<11> A_BLT<10> A_BLT_TOP<11> A_BLT_TOP<10> A_IWL<1279> A_IWL<1278> A_IWL<1277> A_IWL<1276> A_IWL<1275> A_IWL<1274> A_IWL<1273> A_IWL<1272> A_IWL<1271> A_IWL<1270> A_IWL<1269> A_IWL<1268> A_IWL<1267> A_IWL<1266> A_IWL<1265> A_IWL<1264> A_IWL<1263> A_IWL<1262> A_IWL<1261> A_IWL<1260> A_IWL<1259> A_IWL<1258> A_IWL<1257> A_IWL<1256> A_IWL<1255> A_IWL<1254> A_IWL<1253> A_IWL<1252> A_IWL<1251> A_IWL<1250> A_IWL<1249> A_IWL<1248> A_IWL<1247> A_IWL<1246> A_IWL<1245> A_IWL<1244> A_IWL<1243> A_IWL<1242> A_IWL<1241> A_IWL<1240> A_IWL<1239> A_IWL<1238> A_IWL<1237> A_IWL<1236> A_IWL<1235> A_IWL<1234> A_IWL<1233> A_IWL<1232> A_IWL<1231> A_IWL<1230> A_IWL<1229> A_IWL<1228> A_IWL<1227> A_IWL<1226> A_IWL<1225> A_IWL<1224> A_IWL<1223> A_IWL<1222> A_IWL<1221> A_IWL<1220> A_IWL<1219> A_IWL<1218> A_IWL<1217> A_IWL<1216> A_IWL<1215> A_IWL<1214> A_IWL<1213> A_IWL<1212> A_IWL<1211> A_IWL<1210> A_IWL<1209> A_IWL<1208> A_IWL<1207> A_IWL<1206> A_IWL<1205> A_IWL<1204> A_IWL<1203> A_IWL<1202> A_IWL<1201> A_IWL<1200> A_IWL<1199> A_IWL<1198> A_IWL<1197> A_IWL<1196> A_IWL<1195> A_IWL<1194> A_IWL<1193> A_IWL<1192> A_IWL<1191> A_IWL<1190> A_IWL<1189> A_IWL<1188> A_IWL<1187> A_IWL<1186> A_IWL<1185> A_IWL<1184> A_IWL<1183> A_IWL<1182> A_IWL<1181> A_IWL<1180> A_IWL<1179> A_IWL<1178> A_IWL<1177> A_IWL<1176> A_IWL<1175> A_IWL<1174> A_IWL<1173> A_IWL<1172> A_IWL<1171> A_IWL<1170> A_IWL<1169> A_IWL<1168> A_IWL<1167> A_IWL<1166> A_IWL<1165> A_IWL<1164> A_IWL<1163> A_IWL<1162> A_IWL<1161> A_IWL<1160> A_IWL<1159> A_IWL<1158> A_IWL<1157> A_IWL<1156> A_IWL<1155> A_IWL<1154> A_IWL<1153> A_IWL<1152> A_IWL<1151> A_IWL<1150> A_IWL<1149> A_IWL<1148> A_IWL<1147> A_IWL<1146> A_IWL<1145> A_IWL<1144> A_IWL<1143> A_IWL<1142> A_IWL<1141> A_IWL<1140> A_IWL<1139> A_IWL<1138> A_IWL<1137> A_IWL<1136> A_IWL<1135> A_IWL<1134> A_IWL<1133> A_IWL<1132> A_IWL<1131> A_IWL<1130> A_IWL<1129> A_IWL<1128> A_IWL<1127> A_IWL<1126> A_IWL<1125> A_IWL<1124> A_IWL<1123> A_IWL<1122> A_IWL<1121> A_IWL<1120> A_IWL<1119> A_IWL<1118> A_IWL<1117> A_IWL<1116> A_IWL<1115> A_IWL<1114> A_IWL<1113> A_IWL<1112> A_IWL<1111> A_IWL<1110> A_IWL<1109> A_IWL<1108> A_IWL<1107> A_IWL<1106> A_IWL<1105> A_IWL<1104> A_IWL<1103> A_IWL<1102> A_IWL<1101> A_IWL<1100> A_IWL<1099> A_IWL<1098> A_IWL<1097> A_IWL<1096> A_IWL<1095> A_IWL<1094> A_IWL<1093> A_IWL<1092> A_IWL<1091> A_IWL<1090> A_IWL<1089> A_IWL<1088> A_IWL<1087> A_IWL<1086> A_IWL<1085> A_IWL<1084> A_IWL<1083> A_IWL<1082> A_IWL<1081> A_IWL<1080> A_IWL<1079> A_IWL<1078> A_IWL<1077> A_IWL<1076> A_IWL<1075> A_IWL<1074> A_IWL<1073> A_IWL<1072> A_IWL<1071> A_IWL<1070> A_IWL<1069> A_IWL<1068> A_IWL<1067> A_IWL<1066> A_IWL<1065> A_IWL<1064> A_IWL<1063> A_IWL<1062> A_IWL<1061> A_IWL<1060> A_IWL<1059> A_IWL<1058> A_IWL<1057> A_IWL<1056> A_IWL<1055> A_IWL<1054> A_IWL<1053> A_IWL<1052> A_IWL<1051> A_IWL<1050> A_IWL<1049> A_IWL<1048> A_IWL<1047> A_IWL<1046> A_IWL<1045> A_IWL<1044> A_IWL<1043> A_IWL<1042> A_IWL<1041> A_IWL<1040> A_IWL<1039> A_IWL<1038> A_IWL<1037> A_IWL<1036> A_IWL<1035> A_IWL<1034> A_IWL<1033> A_IWL<1032> A_IWL<1031> A_IWL<1030> A_IWL<1029> A_IWL<1028> A_IWL<1027> A_IWL<1026> A_IWL<1025> A_IWL<1024> A_IWL<1535> A_IWL<1534> A_IWL<1533> A_IWL<1532> A_IWL<1531> A_IWL<1530> A_IWL<1529> A_IWL<1528> A_IWL<1527> A_IWL<1526> A_IWL<1525> A_IWL<1524> A_IWL<1523> A_IWL<1522> A_IWL<1521> A_IWL<1520> A_IWL<1519> A_IWL<1518> A_IWL<1517> A_IWL<1516> A_IWL<1515> A_IWL<1514> A_IWL<1513> A_IWL<1512> A_IWL<1511> A_IWL<1510> A_IWL<1509> A_IWL<1508> A_IWL<1507> A_IWL<1506> A_IWL<1505> A_IWL<1504> A_IWL<1503> A_IWL<1502> A_IWL<1501> A_IWL<1500> A_IWL<1499> A_IWL<1498> A_IWL<1497> A_IWL<1496> A_IWL<1495> A_IWL<1494> A_IWL<1493> A_IWL<1492> A_IWL<1491> A_IWL<1490> A_IWL<1489> A_IWL<1488> A_IWL<1487> A_IWL<1486> A_IWL<1485> A_IWL<1484> A_IWL<1483> A_IWL<1482> A_IWL<1481> A_IWL<1480> A_IWL<1479> A_IWL<1478> A_IWL<1477> A_IWL<1476> A_IWL<1475> A_IWL<1474> A_IWL<1473> A_IWL<1472> A_IWL<1471> A_IWL<1470> A_IWL<1469> A_IWL<1468> A_IWL<1467> A_IWL<1466> A_IWL<1465> A_IWL<1464> A_IWL<1463> A_IWL<1462> A_IWL<1461> A_IWL<1460> A_IWL<1459> A_IWL<1458> A_IWL<1457> A_IWL<1456> A_IWL<1455> A_IWL<1454> A_IWL<1453> A_IWL<1452> A_IWL<1451> A_IWL<1450> A_IWL<1449> A_IWL<1448> A_IWL<1447> A_IWL<1446> A_IWL<1445> A_IWL<1444> A_IWL<1443> A_IWL<1442> A_IWL<1441> A_IWL<1440> A_IWL<1439> A_IWL<1438> A_IWL<1437> A_IWL<1436> A_IWL<1435> A_IWL<1434> A_IWL<1433> A_IWL<1432> A_IWL<1431> A_IWL<1430> A_IWL<1429> A_IWL<1428> A_IWL<1427> A_IWL<1426> A_IWL<1425> A_IWL<1424> A_IWL<1423> A_IWL<1422> A_IWL<1421> A_IWL<1420> A_IWL<1419> A_IWL<1418> A_IWL<1417> A_IWL<1416> A_IWL<1415> A_IWL<1414> A_IWL<1413> A_IWL<1412> A_IWL<1411> A_IWL<1410> A_IWL<1409> A_IWL<1408> A_IWL<1407> A_IWL<1406> A_IWL<1405> A_IWL<1404> A_IWL<1403> A_IWL<1402> A_IWL<1401> A_IWL<1400> A_IWL<1399> A_IWL<1398> A_IWL<1397> A_IWL<1396> A_IWL<1395> A_IWL<1394> A_IWL<1393> A_IWL<1392> A_IWL<1391> A_IWL<1390> A_IWL<1389> A_IWL<1388> A_IWL<1387> A_IWL<1386> A_IWL<1385> A_IWL<1384> A_IWL<1383> A_IWL<1382> A_IWL<1381> A_IWL<1380> A_IWL<1379> A_IWL<1378> A_IWL<1377> A_IWL<1376> A_IWL<1375> A_IWL<1374> A_IWL<1373> A_IWL<1372> A_IWL<1371> A_IWL<1370> A_IWL<1369> A_IWL<1368> A_IWL<1367> A_IWL<1366> A_IWL<1365> A_IWL<1364> A_IWL<1363> A_IWL<1362> A_IWL<1361> A_IWL<1360> A_IWL<1359> A_IWL<1358> A_IWL<1357> A_IWL<1356> A_IWL<1355> A_IWL<1354> A_IWL<1353> A_IWL<1352> A_IWL<1351> A_IWL<1350> A_IWL<1349> A_IWL<1348> A_IWL<1347> A_IWL<1346> A_IWL<1345> A_IWL<1344> A_IWL<1343> A_IWL<1342> A_IWL<1341> A_IWL<1340> A_IWL<1339> A_IWL<1338> A_IWL<1337> A_IWL<1336> A_IWL<1335> A_IWL<1334> A_IWL<1333> A_IWL<1332> A_IWL<1331> A_IWL<1330> A_IWL<1329> A_IWL<1328> A_IWL<1327> A_IWL<1326> A_IWL<1325> A_IWL<1324> A_IWL<1323> A_IWL<1322> A_IWL<1321> A_IWL<1320> A_IWL<1319> A_IWL<1318> A_IWL<1317> A_IWL<1316> A_IWL<1315> A_IWL<1314> A_IWL<1313> A_IWL<1312> A_IWL<1311> A_IWL<1310> A_IWL<1309> A_IWL<1308> A_IWL<1307> A_IWL<1306> A_IWL<1305> A_IWL<1304> A_IWL<1303> A_IWL<1302> A_IWL<1301> A_IWL<1300> A_IWL<1299> A_IWL<1298> A_IWL<1297> A_IWL<1296> A_IWL<1295> A_IWL<1294> A_IWL<1293> A_IWL<1292> A_IWL<1291> A_IWL<1290> A_IWL<1289> A_IWL<1288> A_IWL<1287> A_IWL<1286> A_IWL<1285> A_IWL<1284> A_IWL<1283> A_IWL<1282> A_IWL<1281> A_IWL<1280> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_COLUMN_pcell_0 +XCOL<4> A_BLC<9> A_BLC<8> A_BLC_TOP<9> A_BLC_TOP<8> A_BLT<9> A_BLT<8> A_BLT_TOP<9> A_BLT_TOP<8> A_IWL<1023> A_IWL<1022> A_IWL<1021> A_IWL<1020> A_IWL<1019> A_IWL<1018> A_IWL<1017> A_IWL<1016> A_IWL<1015> A_IWL<1014> A_IWL<1013> A_IWL<1012> A_IWL<1011> A_IWL<1010> A_IWL<1009> A_IWL<1008> A_IWL<1007> A_IWL<1006> A_IWL<1005> A_IWL<1004> A_IWL<1003> A_IWL<1002> A_IWL<1001> A_IWL<1000> A_IWL<999> A_IWL<998> A_IWL<997> A_IWL<996> A_IWL<995> A_IWL<994> A_IWL<993> A_IWL<992> A_IWL<991> A_IWL<990> A_IWL<989> A_IWL<988> A_IWL<987> A_IWL<986> A_IWL<985> A_IWL<984> A_IWL<983> A_IWL<982> A_IWL<981> A_IWL<980> A_IWL<979> A_IWL<978> A_IWL<977> A_IWL<976> A_IWL<975> A_IWL<974> A_IWL<973> A_IWL<972> A_IWL<971> A_IWL<970> A_IWL<969> A_IWL<968> A_IWL<967> A_IWL<966> A_IWL<965> A_IWL<964> A_IWL<963> A_IWL<962> A_IWL<961> A_IWL<960> A_IWL<959> A_IWL<958> A_IWL<957> A_IWL<956> A_IWL<955> A_IWL<954> A_IWL<953> A_IWL<952> A_IWL<951> A_IWL<950> A_IWL<949> A_IWL<948> A_IWL<947> A_IWL<946> A_IWL<945> A_IWL<944> A_IWL<943> A_IWL<942> A_IWL<941> A_IWL<940> A_IWL<939> A_IWL<938> A_IWL<937> A_IWL<936> A_IWL<935> A_IWL<934> A_IWL<933> A_IWL<932> A_IWL<931> A_IWL<930> A_IWL<929> A_IWL<928> A_IWL<927> A_IWL<926> A_IWL<925> A_IWL<924> A_IWL<923> A_IWL<922> A_IWL<921> A_IWL<920> A_IWL<919> A_IWL<918> A_IWL<917> A_IWL<916> A_IWL<915> A_IWL<914> A_IWL<913> A_IWL<912> A_IWL<911> A_IWL<910> A_IWL<909> A_IWL<908> A_IWL<907> A_IWL<906> A_IWL<905> A_IWL<904> A_IWL<903> A_IWL<902> A_IWL<901> A_IWL<900> A_IWL<899> A_IWL<898> A_IWL<897> A_IWL<896> A_IWL<895> A_IWL<894> A_IWL<893> A_IWL<892> A_IWL<891> A_IWL<890> A_IWL<889> A_IWL<888> A_IWL<887> A_IWL<886> A_IWL<885> A_IWL<884> A_IWL<883> A_IWL<882> A_IWL<881> A_IWL<880> A_IWL<879> A_IWL<878> A_IWL<877> A_IWL<876> A_IWL<875> A_IWL<874> A_IWL<873> A_IWL<872> A_IWL<871> A_IWL<870> A_IWL<869> A_IWL<868> A_IWL<867> A_IWL<866> A_IWL<865> A_IWL<864> A_IWL<863> A_IWL<862> A_IWL<861> A_IWL<860> A_IWL<859> A_IWL<858> A_IWL<857> A_IWL<856> A_IWL<855> A_IWL<854> A_IWL<853> A_IWL<852> A_IWL<851> A_IWL<850> A_IWL<849> A_IWL<848> A_IWL<847> A_IWL<846> A_IWL<845> A_IWL<844> A_IWL<843> A_IWL<842> A_IWL<841> A_IWL<840> A_IWL<839> A_IWL<838> A_IWL<837> A_IWL<836> A_IWL<835> A_IWL<834> A_IWL<833> A_IWL<832> A_IWL<831> A_IWL<830> A_IWL<829> A_IWL<828> A_IWL<827> A_IWL<826> A_IWL<825> A_IWL<824> A_IWL<823> A_IWL<822> A_IWL<821> A_IWL<820> A_IWL<819> A_IWL<818> A_IWL<817> A_IWL<816> A_IWL<815> A_IWL<814> A_IWL<813> A_IWL<812> A_IWL<811> A_IWL<810> A_IWL<809> A_IWL<808> A_IWL<807> A_IWL<806> A_IWL<805> A_IWL<804> A_IWL<803> A_IWL<802> A_IWL<801> A_IWL<800> A_IWL<799> A_IWL<798> A_IWL<797> A_IWL<796> A_IWL<795> A_IWL<794> A_IWL<793> A_IWL<792> A_IWL<791> A_IWL<790> A_IWL<789> A_IWL<788> A_IWL<787> A_IWL<786> A_IWL<785> A_IWL<784> A_IWL<783> A_IWL<782> A_IWL<781> A_IWL<780> A_IWL<779> A_IWL<778> A_IWL<777> A_IWL<776> A_IWL<775> A_IWL<774> A_IWL<773> A_IWL<772> A_IWL<771> A_IWL<770> A_IWL<769> A_IWL<768> A_IWL<1279> A_IWL<1278> A_IWL<1277> A_IWL<1276> A_IWL<1275> A_IWL<1274> A_IWL<1273> A_IWL<1272> A_IWL<1271> A_IWL<1270> A_IWL<1269> A_IWL<1268> A_IWL<1267> A_IWL<1266> A_IWL<1265> A_IWL<1264> A_IWL<1263> A_IWL<1262> A_IWL<1261> A_IWL<1260> A_IWL<1259> A_IWL<1258> A_IWL<1257> A_IWL<1256> A_IWL<1255> A_IWL<1254> A_IWL<1253> A_IWL<1252> A_IWL<1251> A_IWL<1250> A_IWL<1249> A_IWL<1248> A_IWL<1247> A_IWL<1246> A_IWL<1245> A_IWL<1244> A_IWL<1243> A_IWL<1242> A_IWL<1241> A_IWL<1240> A_IWL<1239> A_IWL<1238> A_IWL<1237> A_IWL<1236> A_IWL<1235> A_IWL<1234> A_IWL<1233> A_IWL<1232> A_IWL<1231> A_IWL<1230> A_IWL<1229> A_IWL<1228> A_IWL<1227> A_IWL<1226> A_IWL<1225> A_IWL<1224> A_IWL<1223> A_IWL<1222> A_IWL<1221> A_IWL<1220> A_IWL<1219> A_IWL<1218> A_IWL<1217> A_IWL<1216> A_IWL<1215> A_IWL<1214> A_IWL<1213> A_IWL<1212> A_IWL<1211> A_IWL<1210> A_IWL<1209> A_IWL<1208> A_IWL<1207> A_IWL<1206> A_IWL<1205> A_IWL<1204> A_IWL<1203> A_IWL<1202> A_IWL<1201> A_IWL<1200> A_IWL<1199> A_IWL<1198> A_IWL<1197> A_IWL<1196> A_IWL<1195> A_IWL<1194> A_IWL<1193> A_IWL<1192> A_IWL<1191> A_IWL<1190> A_IWL<1189> A_IWL<1188> A_IWL<1187> A_IWL<1186> A_IWL<1185> A_IWL<1184> A_IWL<1183> A_IWL<1182> A_IWL<1181> A_IWL<1180> A_IWL<1179> A_IWL<1178> A_IWL<1177> A_IWL<1176> A_IWL<1175> A_IWL<1174> A_IWL<1173> A_IWL<1172> A_IWL<1171> A_IWL<1170> A_IWL<1169> A_IWL<1168> A_IWL<1167> A_IWL<1166> A_IWL<1165> A_IWL<1164> A_IWL<1163> A_IWL<1162> A_IWL<1161> A_IWL<1160> A_IWL<1159> A_IWL<1158> A_IWL<1157> A_IWL<1156> A_IWL<1155> A_IWL<1154> A_IWL<1153> A_IWL<1152> A_IWL<1151> A_IWL<1150> A_IWL<1149> A_IWL<1148> A_IWL<1147> A_IWL<1146> A_IWL<1145> A_IWL<1144> A_IWL<1143> A_IWL<1142> A_IWL<1141> A_IWL<1140> A_IWL<1139> A_IWL<1138> A_IWL<1137> A_IWL<1136> A_IWL<1135> A_IWL<1134> A_IWL<1133> A_IWL<1132> A_IWL<1131> A_IWL<1130> A_IWL<1129> A_IWL<1128> A_IWL<1127> A_IWL<1126> A_IWL<1125> A_IWL<1124> A_IWL<1123> A_IWL<1122> A_IWL<1121> A_IWL<1120> A_IWL<1119> A_IWL<1118> A_IWL<1117> A_IWL<1116> A_IWL<1115> A_IWL<1114> A_IWL<1113> A_IWL<1112> A_IWL<1111> A_IWL<1110> A_IWL<1109> A_IWL<1108> A_IWL<1107> A_IWL<1106> A_IWL<1105> A_IWL<1104> A_IWL<1103> A_IWL<1102> A_IWL<1101> A_IWL<1100> A_IWL<1099> A_IWL<1098> A_IWL<1097> A_IWL<1096> A_IWL<1095> A_IWL<1094> A_IWL<1093> A_IWL<1092> A_IWL<1091> A_IWL<1090> A_IWL<1089> A_IWL<1088> A_IWL<1087> A_IWL<1086> A_IWL<1085> A_IWL<1084> A_IWL<1083> A_IWL<1082> A_IWL<1081> A_IWL<1080> A_IWL<1079> A_IWL<1078> A_IWL<1077> A_IWL<1076> A_IWL<1075> A_IWL<1074> A_IWL<1073> A_IWL<1072> A_IWL<1071> A_IWL<1070> A_IWL<1069> A_IWL<1068> A_IWL<1067> A_IWL<1066> A_IWL<1065> A_IWL<1064> A_IWL<1063> A_IWL<1062> A_IWL<1061> A_IWL<1060> A_IWL<1059> A_IWL<1058> A_IWL<1057> A_IWL<1056> A_IWL<1055> A_IWL<1054> A_IWL<1053> A_IWL<1052> A_IWL<1051> A_IWL<1050> A_IWL<1049> A_IWL<1048> A_IWL<1047> A_IWL<1046> A_IWL<1045> A_IWL<1044> A_IWL<1043> A_IWL<1042> A_IWL<1041> A_IWL<1040> A_IWL<1039> A_IWL<1038> A_IWL<1037> A_IWL<1036> A_IWL<1035> A_IWL<1034> A_IWL<1033> A_IWL<1032> A_IWL<1031> A_IWL<1030> A_IWL<1029> A_IWL<1028> A_IWL<1027> A_IWL<1026> A_IWL<1025> A_IWL<1024> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_COLUMN_pcell_0 +XCOL<3> A_BLC<7> A_BLC<6> A_BLC_TOP<7> A_BLC_TOP<6> A_BLT<7> A_BLT<6> A_BLT_TOP<7> A_BLT_TOP<6> A_IWL<767> A_IWL<766> A_IWL<765> A_IWL<764> A_IWL<763> A_IWL<762> A_IWL<761> A_IWL<760> A_IWL<759> A_IWL<758> A_IWL<757> A_IWL<756> A_IWL<755> A_IWL<754> A_IWL<753> A_IWL<752> A_IWL<751> A_IWL<750> A_IWL<749> A_IWL<748> A_IWL<747> A_IWL<746> A_IWL<745> A_IWL<744> A_IWL<743> A_IWL<742> A_IWL<741> A_IWL<740> A_IWL<739> A_IWL<738> A_IWL<737> A_IWL<736> A_IWL<735> A_IWL<734> A_IWL<733> A_IWL<732> A_IWL<731> A_IWL<730> A_IWL<729> A_IWL<728> A_IWL<727> A_IWL<726> A_IWL<725> A_IWL<724> A_IWL<723> A_IWL<722> A_IWL<721> A_IWL<720> A_IWL<719> A_IWL<718> A_IWL<717> A_IWL<716> A_IWL<715> A_IWL<714> A_IWL<713> A_IWL<712> A_IWL<711> A_IWL<710> A_IWL<709> A_IWL<708> A_IWL<707> A_IWL<706> A_IWL<705> A_IWL<704> A_IWL<703> A_IWL<702> A_IWL<701> A_IWL<700> A_IWL<699> A_IWL<698> A_IWL<697> A_IWL<696> A_IWL<695> A_IWL<694> A_IWL<693> A_IWL<692> A_IWL<691> A_IWL<690> A_IWL<689> A_IWL<688> A_IWL<687> A_IWL<686> A_IWL<685> A_IWL<684> A_IWL<683> A_IWL<682> A_IWL<681> A_IWL<680> A_IWL<679> A_IWL<678> A_IWL<677> A_IWL<676> A_IWL<675> A_IWL<674> A_IWL<673> A_IWL<672> A_IWL<671> A_IWL<670> A_IWL<669> A_IWL<668> A_IWL<667> A_IWL<666> A_IWL<665> A_IWL<664> A_IWL<663> A_IWL<662> A_IWL<661> A_IWL<660> A_IWL<659> A_IWL<658> A_IWL<657> A_IWL<656> A_IWL<655> A_IWL<654> A_IWL<653> A_IWL<652> A_IWL<651> A_IWL<650> A_IWL<649> A_IWL<648> A_IWL<647> A_IWL<646> A_IWL<645> A_IWL<644> A_IWL<643> A_IWL<642> A_IWL<641> A_IWL<640> A_IWL<639> A_IWL<638> A_IWL<637> A_IWL<636> A_IWL<635> A_IWL<634> A_IWL<633> A_IWL<632> A_IWL<631> A_IWL<630> A_IWL<629> A_IWL<628> A_IWL<627> A_IWL<626> A_IWL<625> A_IWL<624> A_IWL<623> A_IWL<622> A_IWL<621> A_IWL<620> A_IWL<619> A_IWL<618> A_IWL<617> A_IWL<616> A_IWL<615> A_IWL<614> A_IWL<613> A_IWL<612> A_IWL<611> A_IWL<610> A_IWL<609> A_IWL<608> A_IWL<607> A_IWL<606> A_IWL<605> A_IWL<604> A_IWL<603> A_IWL<602> A_IWL<601> A_IWL<600> A_IWL<599> A_IWL<598> A_IWL<597> A_IWL<596> A_IWL<595> A_IWL<594> A_IWL<593> A_IWL<592> A_IWL<591> A_IWL<590> A_IWL<589> A_IWL<588> A_IWL<587> A_IWL<586> A_IWL<585> A_IWL<584> A_IWL<583> A_IWL<582> A_IWL<581> A_IWL<580> A_IWL<579> A_IWL<578> A_IWL<577> A_IWL<576> A_IWL<575> A_IWL<574> A_IWL<573> A_IWL<572> A_IWL<571> A_IWL<570> A_IWL<569> A_IWL<568> A_IWL<567> A_IWL<566> A_IWL<565> A_IWL<564> A_IWL<563> A_IWL<562> A_IWL<561> A_IWL<560> A_IWL<559> A_IWL<558> A_IWL<557> A_IWL<556> A_IWL<555> A_IWL<554> A_IWL<553> A_IWL<552> A_IWL<551> A_IWL<550> A_IWL<549> A_IWL<548> A_IWL<547> A_IWL<546> A_IWL<545> A_IWL<544> A_IWL<543> A_IWL<542> A_IWL<541> A_IWL<540> A_IWL<539> A_IWL<538> A_IWL<537> A_IWL<536> A_IWL<535> A_IWL<534> A_IWL<533> A_IWL<532> A_IWL<531> A_IWL<530> A_IWL<529> A_IWL<528> A_IWL<527> A_IWL<526> A_IWL<525> A_IWL<524> A_IWL<523> A_IWL<522> A_IWL<521> A_IWL<520> A_IWL<519> A_IWL<518> A_IWL<517> A_IWL<516> A_IWL<515> A_IWL<514> A_IWL<513> A_IWL<512> A_IWL<1023> A_IWL<1022> A_IWL<1021> A_IWL<1020> A_IWL<1019> A_IWL<1018> A_IWL<1017> A_IWL<1016> A_IWL<1015> A_IWL<1014> A_IWL<1013> A_IWL<1012> A_IWL<1011> A_IWL<1010> A_IWL<1009> A_IWL<1008> A_IWL<1007> A_IWL<1006> A_IWL<1005> A_IWL<1004> A_IWL<1003> A_IWL<1002> A_IWL<1001> A_IWL<1000> A_IWL<999> A_IWL<998> A_IWL<997> A_IWL<996> A_IWL<995> A_IWL<994> A_IWL<993> A_IWL<992> A_IWL<991> A_IWL<990> A_IWL<989> A_IWL<988> A_IWL<987> A_IWL<986> A_IWL<985> A_IWL<984> A_IWL<983> A_IWL<982> A_IWL<981> A_IWL<980> A_IWL<979> A_IWL<978> A_IWL<977> A_IWL<976> A_IWL<975> A_IWL<974> A_IWL<973> A_IWL<972> A_IWL<971> A_IWL<970> A_IWL<969> A_IWL<968> A_IWL<967> A_IWL<966> A_IWL<965> A_IWL<964> A_IWL<963> A_IWL<962> A_IWL<961> A_IWL<960> A_IWL<959> A_IWL<958> A_IWL<957> A_IWL<956> A_IWL<955> A_IWL<954> A_IWL<953> A_IWL<952> A_IWL<951> A_IWL<950> A_IWL<949> A_IWL<948> A_IWL<947> A_IWL<946> A_IWL<945> A_IWL<944> A_IWL<943> A_IWL<942> A_IWL<941> A_IWL<940> A_IWL<939> A_IWL<938> A_IWL<937> A_IWL<936> A_IWL<935> A_IWL<934> A_IWL<933> A_IWL<932> A_IWL<931> A_IWL<930> A_IWL<929> A_IWL<928> A_IWL<927> A_IWL<926> A_IWL<925> A_IWL<924> A_IWL<923> A_IWL<922> A_IWL<921> A_IWL<920> A_IWL<919> A_IWL<918> A_IWL<917> A_IWL<916> A_IWL<915> A_IWL<914> A_IWL<913> A_IWL<912> A_IWL<911> A_IWL<910> A_IWL<909> A_IWL<908> A_IWL<907> A_IWL<906> A_IWL<905> A_IWL<904> A_IWL<903> A_IWL<902> A_IWL<901> A_IWL<900> A_IWL<899> A_IWL<898> A_IWL<897> A_IWL<896> A_IWL<895> A_IWL<894> A_IWL<893> A_IWL<892> A_IWL<891> A_IWL<890> A_IWL<889> A_IWL<888> A_IWL<887> A_IWL<886> A_IWL<885> A_IWL<884> A_IWL<883> A_IWL<882> A_IWL<881> A_IWL<880> A_IWL<879> A_IWL<878> A_IWL<877> A_IWL<876> A_IWL<875> A_IWL<874> A_IWL<873> A_IWL<872> A_IWL<871> A_IWL<870> A_IWL<869> A_IWL<868> A_IWL<867> A_IWL<866> A_IWL<865> A_IWL<864> A_IWL<863> A_IWL<862> A_IWL<861> A_IWL<860> A_IWL<859> A_IWL<858> A_IWL<857> A_IWL<856> A_IWL<855> A_IWL<854> A_IWL<853> A_IWL<852> A_IWL<851> A_IWL<850> A_IWL<849> A_IWL<848> A_IWL<847> A_IWL<846> A_IWL<845> A_IWL<844> A_IWL<843> A_IWL<842> A_IWL<841> A_IWL<840> A_IWL<839> A_IWL<838> A_IWL<837> A_IWL<836> A_IWL<835> A_IWL<834> A_IWL<833> A_IWL<832> A_IWL<831> A_IWL<830> A_IWL<829> A_IWL<828> A_IWL<827> A_IWL<826> A_IWL<825> A_IWL<824> A_IWL<823> A_IWL<822> A_IWL<821> A_IWL<820> A_IWL<819> A_IWL<818> A_IWL<817> A_IWL<816> A_IWL<815> A_IWL<814> A_IWL<813> A_IWL<812> A_IWL<811> A_IWL<810> A_IWL<809> A_IWL<808> A_IWL<807> A_IWL<806> A_IWL<805> A_IWL<804> A_IWL<803> A_IWL<802> A_IWL<801> A_IWL<800> A_IWL<799> A_IWL<798> A_IWL<797> A_IWL<796> A_IWL<795> A_IWL<794> A_IWL<793> A_IWL<792> A_IWL<791> A_IWL<790> A_IWL<789> A_IWL<788> A_IWL<787> A_IWL<786> A_IWL<785> A_IWL<784> A_IWL<783> A_IWL<782> A_IWL<781> A_IWL<780> A_IWL<779> A_IWL<778> A_IWL<777> A_IWL<776> A_IWL<775> A_IWL<774> A_IWL<773> A_IWL<772> A_IWL<771> A_IWL<770> A_IWL<769> A_IWL<768> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_COLUMN_pcell_0 +XCOL<2> A_BLC<5> A_BLC<4> A_BLC_TOP<5> A_BLC_TOP<4> A_BLT<5> A_BLT<4> A_BLT_TOP<5> A_BLT_TOP<4> A_IWL<511> A_IWL<510> A_IWL<509> A_IWL<508> A_IWL<507> A_IWL<506> A_IWL<505> A_IWL<504> A_IWL<503> A_IWL<502> A_IWL<501> A_IWL<500> A_IWL<499> A_IWL<498> A_IWL<497> A_IWL<496> A_IWL<495> A_IWL<494> A_IWL<493> A_IWL<492> A_IWL<491> A_IWL<490> A_IWL<489> A_IWL<488> A_IWL<487> A_IWL<486> A_IWL<485> A_IWL<484> A_IWL<483> A_IWL<482> A_IWL<481> A_IWL<480> A_IWL<479> A_IWL<478> A_IWL<477> A_IWL<476> A_IWL<475> A_IWL<474> A_IWL<473> A_IWL<472> A_IWL<471> A_IWL<470> A_IWL<469> A_IWL<468> A_IWL<467> A_IWL<466> A_IWL<465> A_IWL<464> A_IWL<463> A_IWL<462> A_IWL<461> A_IWL<460> A_IWL<459> A_IWL<458> A_IWL<457> A_IWL<456> A_IWL<455> A_IWL<454> A_IWL<453> A_IWL<452> A_IWL<451> A_IWL<450> A_IWL<449> A_IWL<448> A_IWL<447> A_IWL<446> A_IWL<445> A_IWL<444> A_IWL<443> A_IWL<442> A_IWL<441> A_IWL<440> A_IWL<439> A_IWL<438> A_IWL<437> A_IWL<436> A_IWL<435> A_IWL<434> A_IWL<433> A_IWL<432> A_IWL<431> A_IWL<430> A_IWL<429> A_IWL<428> A_IWL<427> A_IWL<426> A_IWL<425> A_IWL<424> A_IWL<423> A_IWL<422> A_IWL<421> A_IWL<420> A_IWL<419> A_IWL<418> A_IWL<417> A_IWL<416> A_IWL<415> A_IWL<414> A_IWL<413> A_IWL<412> A_IWL<411> A_IWL<410> A_IWL<409> A_IWL<408> A_IWL<407> A_IWL<406> A_IWL<405> A_IWL<404> A_IWL<403> A_IWL<402> A_IWL<401> A_IWL<400> A_IWL<399> A_IWL<398> A_IWL<397> A_IWL<396> A_IWL<395> A_IWL<394> A_IWL<393> A_IWL<392> A_IWL<391> A_IWL<390> A_IWL<389> A_IWL<388> A_IWL<387> A_IWL<386> A_IWL<385> A_IWL<384> A_IWL<383> A_IWL<382> A_IWL<381> A_IWL<380> A_IWL<379> A_IWL<378> A_IWL<377> A_IWL<376> A_IWL<375> A_IWL<374> A_IWL<373> A_IWL<372> A_IWL<371> A_IWL<370> A_IWL<369> A_IWL<368> A_IWL<367> A_IWL<366> A_IWL<365> A_IWL<364> A_IWL<363> A_IWL<362> A_IWL<361> A_IWL<360> A_IWL<359> A_IWL<358> A_IWL<357> A_IWL<356> A_IWL<355> A_IWL<354> A_IWL<353> A_IWL<352> A_IWL<351> A_IWL<350> A_IWL<349> A_IWL<348> A_IWL<347> A_IWL<346> A_IWL<345> A_IWL<344> A_IWL<343> A_IWL<342> A_IWL<341> A_IWL<340> A_IWL<339> A_IWL<338> A_IWL<337> A_IWL<336> A_IWL<335> A_IWL<334> A_IWL<333> A_IWL<332> A_IWL<331> A_IWL<330> A_IWL<329> A_IWL<328> A_IWL<327> A_IWL<326> A_IWL<325> A_IWL<324> A_IWL<323> A_IWL<322> A_IWL<321> A_IWL<320> A_IWL<319> A_IWL<318> A_IWL<317> A_IWL<316> A_IWL<315> A_IWL<314> A_IWL<313> A_IWL<312> A_IWL<311> A_IWL<310> A_IWL<309> A_IWL<308> A_IWL<307> A_IWL<306> A_IWL<305> A_IWL<304> A_IWL<303> A_IWL<302> A_IWL<301> A_IWL<300> A_IWL<299> A_IWL<298> A_IWL<297> A_IWL<296> A_IWL<295> A_IWL<294> A_IWL<293> A_IWL<292> A_IWL<291> A_IWL<290> A_IWL<289> A_IWL<288> A_IWL<287> A_IWL<286> A_IWL<285> A_IWL<284> A_IWL<283> A_IWL<282> A_IWL<281> A_IWL<280> A_IWL<279> A_IWL<278> A_IWL<277> A_IWL<276> A_IWL<275> A_IWL<274> A_IWL<273> A_IWL<272> A_IWL<271> A_IWL<270> A_IWL<269> A_IWL<268> A_IWL<267> A_IWL<266> A_IWL<265> A_IWL<264> A_IWL<263> A_IWL<262> A_IWL<261> A_IWL<260> A_IWL<259> A_IWL<258> A_IWL<257> A_IWL<256> A_IWL<767> A_IWL<766> A_IWL<765> A_IWL<764> A_IWL<763> A_IWL<762> A_IWL<761> A_IWL<760> A_IWL<759> A_IWL<758> A_IWL<757> A_IWL<756> A_IWL<755> A_IWL<754> A_IWL<753> A_IWL<752> A_IWL<751> A_IWL<750> A_IWL<749> A_IWL<748> A_IWL<747> A_IWL<746> A_IWL<745> A_IWL<744> A_IWL<743> A_IWL<742> A_IWL<741> A_IWL<740> A_IWL<739> A_IWL<738> A_IWL<737> A_IWL<736> A_IWL<735> A_IWL<734> A_IWL<733> A_IWL<732> A_IWL<731> A_IWL<730> A_IWL<729> A_IWL<728> A_IWL<727> A_IWL<726> A_IWL<725> A_IWL<724> A_IWL<723> A_IWL<722> A_IWL<721> A_IWL<720> A_IWL<719> A_IWL<718> A_IWL<717> A_IWL<716> A_IWL<715> A_IWL<714> A_IWL<713> A_IWL<712> A_IWL<711> A_IWL<710> A_IWL<709> A_IWL<708> A_IWL<707> A_IWL<706> A_IWL<705> A_IWL<704> A_IWL<703> A_IWL<702> A_IWL<701> A_IWL<700> A_IWL<699> A_IWL<698> A_IWL<697> A_IWL<696> A_IWL<695> A_IWL<694> A_IWL<693> A_IWL<692> A_IWL<691> A_IWL<690> A_IWL<689> A_IWL<688> A_IWL<687> A_IWL<686> A_IWL<685> A_IWL<684> A_IWL<683> A_IWL<682> A_IWL<681> A_IWL<680> A_IWL<679> A_IWL<678> A_IWL<677> A_IWL<676> A_IWL<675> A_IWL<674> A_IWL<673> A_IWL<672> A_IWL<671> A_IWL<670> A_IWL<669> A_IWL<668> A_IWL<667> A_IWL<666> A_IWL<665> A_IWL<664> A_IWL<663> A_IWL<662> A_IWL<661> A_IWL<660> A_IWL<659> A_IWL<658> A_IWL<657> A_IWL<656> A_IWL<655> A_IWL<654> A_IWL<653> A_IWL<652> A_IWL<651> A_IWL<650> A_IWL<649> A_IWL<648> A_IWL<647> A_IWL<646> A_IWL<645> A_IWL<644> A_IWL<643> A_IWL<642> A_IWL<641> A_IWL<640> A_IWL<639> A_IWL<638> A_IWL<637> A_IWL<636> A_IWL<635> A_IWL<634> A_IWL<633> A_IWL<632> A_IWL<631> A_IWL<630> A_IWL<629> A_IWL<628> A_IWL<627> A_IWL<626> A_IWL<625> A_IWL<624> A_IWL<623> A_IWL<622> A_IWL<621> A_IWL<620> A_IWL<619> A_IWL<618> A_IWL<617> A_IWL<616> A_IWL<615> A_IWL<614> A_IWL<613> A_IWL<612> A_IWL<611> A_IWL<610> A_IWL<609> A_IWL<608> A_IWL<607> A_IWL<606> A_IWL<605> A_IWL<604> A_IWL<603> A_IWL<602> A_IWL<601> A_IWL<600> A_IWL<599> A_IWL<598> A_IWL<597> A_IWL<596> A_IWL<595> A_IWL<594> A_IWL<593> A_IWL<592> A_IWL<591> A_IWL<590> A_IWL<589> A_IWL<588> A_IWL<587> A_IWL<586> A_IWL<585> A_IWL<584> A_IWL<583> A_IWL<582> A_IWL<581> A_IWL<580> A_IWL<579> A_IWL<578> A_IWL<577> A_IWL<576> A_IWL<575> A_IWL<574> A_IWL<573> A_IWL<572> A_IWL<571> A_IWL<570> A_IWL<569> A_IWL<568> A_IWL<567> A_IWL<566> A_IWL<565> A_IWL<564> A_IWL<563> A_IWL<562> A_IWL<561> A_IWL<560> A_IWL<559> A_IWL<558> A_IWL<557> A_IWL<556> A_IWL<555> A_IWL<554> A_IWL<553> A_IWL<552> A_IWL<551> A_IWL<550> A_IWL<549> A_IWL<548> A_IWL<547> A_IWL<546> A_IWL<545> A_IWL<544> A_IWL<543> A_IWL<542> A_IWL<541> A_IWL<540> A_IWL<539> A_IWL<538> A_IWL<537> A_IWL<536> A_IWL<535> A_IWL<534> A_IWL<533> A_IWL<532> A_IWL<531> A_IWL<530> A_IWL<529> A_IWL<528> A_IWL<527> A_IWL<526> A_IWL<525> A_IWL<524> A_IWL<523> A_IWL<522> A_IWL<521> A_IWL<520> A_IWL<519> A_IWL<518> A_IWL<517> A_IWL<516> A_IWL<515> A_IWL<514> A_IWL<513> A_IWL<512> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_COLUMN_pcell_0 +XCOL<1> A_BLC<3> A_BLC<2> A_BLC_TOP<3> A_BLC_TOP<2> A_BLT<3> A_BLT<2> A_BLT_TOP<3> A_BLT_TOP<2> A_IWL<255> A_IWL<254> A_IWL<253> A_IWL<252> A_IWL<251> A_IWL<250> A_IWL<249> A_IWL<248> A_IWL<247> A_IWL<246> A_IWL<245> A_IWL<244> A_IWL<243> A_IWL<242> A_IWL<241> A_IWL<240> A_IWL<239> A_IWL<238> A_IWL<237> A_IWL<236> A_IWL<235> A_IWL<234> A_IWL<233> A_IWL<232> A_IWL<231> A_IWL<230> A_IWL<229> A_IWL<228> A_IWL<227> A_IWL<226> A_IWL<225> A_IWL<224> A_IWL<223> A_IWL<222> A_IWL<221> A_IWL<220> A_IWL<219> A_IWL<218> A_IWL<217> A_IWL<216> A_IWL<215> A_IWL<214> A_IWL<213> A_IWL<212> A_IWL<211> A_IWL<210> A_IWL<209> A_IWL<208> A_IWL<207> A_IWL<206> A_IWL<205> A_IWL<204> A_IWL<203> A_IWL<202> A_IWL<201> A_IWL<200> A_IWL<199> A_IWL<198> A_IWL<197> A_IWL<196> A_IWL<195> A_IWL<194> A_IWL<193> A_IWL<192> A_IWL<191> A_IWL<190> A_IWL<189> A_IWL<188> A_IWL<187> A_IWL<186> A_IWL<185> A_IWL<184> A_IWL<183> A_IWL<182> A_IWL<181> A_IWL<180> A_IWL<179> A_IWL<178> A_IWL<177> A_IWL<176> A_IWL<175> A_IWL<174> A_IWL<173> A_IWL<172> A_IWL<171> A_IWL<170> A_IWL<169> A_IWL<168> A_IWL<167> A_IWL<166> A_IWL<165> A_IWL<164> A_IWL<163> A_IWL<162> A_IWL<161> A_IWL<160> A_IWL<159> A_IWL<158> A_IWL<157> A_IWL<156> A_IWL<155> A_IWL<154> A_IWL<153> A_IWL<152> A_IWL<151> A_IWL<150> A_IWL<149> A_IWL<148> A_IWL<147> A_IWL<146> A_IWL<145> A_IWL<144> A_IWL<143> A_IWL<142> A_IWL<141> A_IWL<140> A_IWL<139> A_IWL<138> A_IWL<137> A_IWL<136> A_IWL<135> A_IWL<134> A_IWL<133> A_IWL<132> A_IWL<131> A_IWL<130> A_IWL<129> A_IWL<128> A_IWL<127> A_IWL<126> A_IWL<125> A_IWL<124> A_IWL<123> A_IWL<122> A_IWL<121> A_IWL<120> A_IWL<119> A_IWL<118> A_IWL<117> A_IWL<116> A_IWL<115> A_IWL<114> A_IWL<113> A_IWL<112> A_IWL<111> A_IWL<110> A_IWL<109> A_IWL<108> A_IWL<107> A_IWL<106> A_IWL<105> A_IWL<104> A_IWL<103> A_IWL<102> A_IWL<101> A_IWL<100> A_IWL<99> A_IWL<98> A_IWL<97> A_IWL<96> A_IWL<95> A_IWL<94> A_IWL<93> A_IWL<92> A_IWL<91> A_IWL<90> A_IWL<89> A_IWL<88> A_IWL<87> A_IWL<86> A_IWL<85> A_IWL<84> A_IWL<83> A_IWL<82> A_IWL<81> A_IWL<80> A_IWL<79> A_IWL<78> A_IWL<77> A_IWL<76> A_IWL<75> A_IWL<74> A_IWL<73> A_IWL<72> A_IWL<71> A_IWL<70> A_IWL<69> A_IWL<68> A_IWL<67> A_IWL<66> A_IWL<65> A_IWL<64> A_IWL<63> A_IWL<62> A_IWL<61> A_IWL<60> A_IWL<59> A_IWL<58> A_IWL<57> A_IWL<56> A_IWL<55> A_IWL<54> A_IWL<53> A_IWL<52> A_IWL<51> A_IWL<50> A_IWL<49> A_IWL<48> A_IWL<47> A_IWL<46> A_IWL<45> A_IWL<44> A_IWL<43> A_IWL<42> A_IWL<41> A_IWL<40> A_IWL<39> A_IWL<38> A_IWL<37> A_IWL<36> A_IWL<35> A_IWL<34> A_IWL<33> A_IWL<32> A_IWL<31> A_IWL<30> A_IWL<29> A_IWL<28> A_IWL<27> A_IWL<26> A_IWL<25> A_IWL<24> A_IWL<23> A_IWL<22> A_IWL<21> A_IWL<20> A_IWL<19> A_IWL<18> A_IWL<17> A_IWL<16> A_IWL<15> A_IWL<14> A_IWL<13> A_IWL<12> A_IWL<11> A_IWL<10> A_IWL<9> A_IWL<8> A_IWL<7> A_IWL<6> A_IWL<5> A_IWL<4> A_IWL<3> A_IWL<2> A_IWL<1> A_IWL<0> A_IWL<511> A_IWL<510> A_IWL<509> A_IWL<508> A_IWL<507> A_IWL<506> A_IWL<505> A_IWL<504> A_IWL<503> A_IWL<502> A_IWL<501> A_IWL<500> A_IWL<499> A_IWL<498> A_IWL<497> A_IWL<496> A_IWL<495> A_IWL<494> A_IWL<493> A_IWL<492> A_IWL<491> A_IWL<490> A_IWL<489> A_IWL<488> A_IWL<487> A_IWL<486> A_IWL<485> A_IWL<484> A_IWL<483> A_IWL<482> A_IWL<481> A_IWL<480> A_IWL<479> A_IWL<478> A_IWL<477> A_IWL<476> A_IWL<475> A_IWL<474> A_IWL<473> A_IWL<472> A_IWL<471> A_IWL<470> A_IWL<469> A_IWL<468> A_IWL<467> A_IWL<466> A_IWL<465> A_IWL<464> A_IWL<463> A_IWL<462> A_IWL<461> A_IWL<460> A_IWL<459> A_IWL<458> A_IWL<457> A_IWL<456> A_IWL<455> A_IWL<454> A_IWL<453> A_IWL<452> A_IWL<451> A_IWL<450> A_IWL<449> A_IWL<448> A_IWL<447> A_IWL<446> A_IWL<445> A_IWL<444> A_IWL<443> A_IWL<442> A_IWL<441> A_IWL<440> A_IWL<439> A_IWL<438> A_IWL<437> A_IWL<436> A_IWL<435> A_IWL<434> A_IWL<433> A_IWL<432> A_IWL<431> A_IWL<430> A_IWL<429> A_IWL<428> A_IWL<427> A_IWL<426> A_IWL<425> A_IWL<424> A_IWL<423> A_IWL<422> A_IWL<421> A_IWL<420> A_IWL<419> A_IWL<418> A_IWL<417> A_IWL<416> A_IWL<415> A_IWL<414> A_IWL<413> A_IWL<412> A_IWL<411> A_IWL<410> A_IWL<409> A_IWL<408> A_IWL<407> A_IWL<406> A_IWL<405> A_IWL<404> A_IWL<403> A_IWL<402> A_IWL<401> A_IWL<400> A_IWL<399> A_IWL<398> A_IWL<397> A_IWL<396> A_IWL<395> A_IWL<394> A_IWL<393> A_IWL<392> A_IWL<391> A_IWL<390> A_IWL<389> A_IWL<388> A_IWL<387> A_IWL<386> A_IWL<385> A_IWL<384> A_IWL<383> A_IWL<382> A_IWL<381> A_IWL<380> A_IWL<379> A_IWL<378> A_IWL<377> A_IWL<376> A_IWL<375> A_IWL<374> A_IWL<373> A_IWL<372> A_IWL<371> A_IWL<370> A_IWL<369> A_IWL<368> A_IWL<367> A_IWL<366> A_IWL<365> A_IWL<364> A_IWL<363> A_IWL<362> A_IWL<361> A_IWL<360> A_IWL<359> A_IWL<358> A_IWL<357> A_IWL<356> A_IWL<355> A_IWL<354> A_IWL<353> A_IWL<352> A_IWL<351> A_IWL<350> A_IWL<349> A_IWL<348> A_IWL<347> A_IWL<346> A_IWL<345> A_IWL<344> A_IWL<343> A_IWL<342> A_IWL<341> A_IWL<340> A_IWL<339> A_IWL<338> A_IWL<337> A_IWL<336> A_IWL<335> A_IWL<334> A_IWL<333> A_IWL<332> A_IWL<331> A_IWL<330> A_IWL<329> A_IWL<328> A_IWL<327> A_IWL<326> A_IWL<325> A_IWL<324> A_IWL<323> A_IWL<322> A_IWL<321> A_IWL<320> A_IWL<319> A_IWL<318> A_IWL<317> A_IWL<316> A_IWL<315> A_IWL<314> A_IWL<313> A_IWL<312> A_IWL<311> A_IWL<310> A_IWL<309> A_IWL<308> A_IWL<307> A_IWL<306> A_IWL<305> A_IWL<304> A_IWL<303> A_IWL<302> A_IWL<301> A_IWL<300> A_IWL<299> A_IWL<298> A_IWL<297> A_IWL<296> A_IWL<295> A_IWL<294> A_IWL<293> A_IWL<292> A_IWL<291> A_IWL<290> A_IWL<289> A_IWL<288> A_IWL<287> A_IWL<286> A_IWL<285> A_IWL<284> A_IWL<283> A_IWL<282> A_IWL<281> A_IWL<280> A_IWL<279> A_IWL<278> A_IWL<277> A_IWL<276> A_IWL<275> A_IWL<274> A_IWL<273> A_IWL<272> A_IWL<271> A_IWL<270> A_IWL<269> A_IWL<268> A_IWL<267> A_IWL<266> A_IWL<265> A_IWL<264> A_IWL<263> A_IWL<262> A_IWL<261> A_IWL<260> A_IWL<259> A_IWL<258> A_IWL<257> A_IWL<256> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_COLUMN_pcell_0 +XCOL<0> A_BLC<1> A_BLC<0> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT<1> A_BLT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_WL<255> A_WL<254> A_WL<253> A_WL<252> A_WL<251> A_WL<250> A_WL<249> A_WL<248> A_WL<247> A_WL<246> A_WL<245> A_WL<244> A_WL<243> A_WL<242> A_WL<241> A_WL<240> A_WL<239> A_WL<238> A_WL<237> A_WL<236> A_WL<235> A_WL<234> A_WL<233> A_WL<232> A_WL<231> A_WL<230> A_WL<229> A_WL<228> A_WL<227> A_WL<226> A_WL<225> A_WL<224> A_WL<223> A_WL<222> A_WL<221> A_WL<220> A_WL<219> A_WL<218> A_WL<217> A_WL<216> A_WL<215> A_WL<214> A_WL<213> A_WL<212> A_WL<211> A_WL<210> A_WL<209> A_WL<208> A_WL<207> A_WL<206> A_WL<205> A_WL<204> A_WL<203> A_WL<202> A_WL<201> A_WL<200> A_WL<199> A_WL<198> A_WL<197> A_WL<196> A_WL<195> A_WL<194> A_WL<193> A_WL<192> A_WL<191> A_WL<190> A_WL<189> A_WL<188> A_WL<187> A_WL<186> A_WL<185> A_WL<184> A_WL<183> A_WL<182> A_WL<181> A_WL<180> A_WL<179> A_WL<178> A_WL<177> A_WL<176> A_WL<175> A_WL<174> A_WL<173> A_WL<172> A_WL<171> A_WL<170> A_WL<169> A_WL<168> A_WL<167> A_WL<166> A_WL<165> A_WL<164> A_WL<163> A_WL<162> A_WL<161> A_WL<160> A_WL<159> A_WL<158> A_WL<157> A_WL<156> A_WL<155> A_WL<154> A_WL<153> A_WL<152> A_WL<151> A_WL<150> A_WL<149> A_WL<148> A_WL<147> A_WL<146> A_WL<145> A_WL<144> A_WL<143> A_WL<142> A_WL<141> A_WL<140> A_WL<139> A_WL<138> A_WL<137> A_WL<136> A_WL<135> A_WL<134> A_WL<133> A_WL<132> A_WL<131> A_WL<130> A_WL<129> A_WL<128> A_WL<127> A_WL<126> A_WL<125> A_WL<124> A_WL<123> A_WL<122> A_WL<121> A_WL<120> A_WL<119> A_WL<118> A_WL<117> A_WL<116> A_WL<115> A_WL<114> A_WL<113> A_WL<112> A_WL<111> A_WL<110> A_WL<109> A_WL<108> A_WL<107> A_WL<106> A_WL<105> A_WL<104> A_WL<103> A_WL<102> A_WL<101> A_WL<100> A_WL<99> A_WL<98> A_WL<97> A_WL<96> A_WL<95> A_WL<94> A_WL<93> A_WL<92> A_WL<91> A_WL<90> A_WL<89> A_WL<88> A_WL<87> A_WL<86> A_WL<85> A_WL<84> A_WL<83> A_WL<82> A_WL<81> A_WL<80> A_WL<79> A_WL<78> A_WL<77> A_WL<76> A_WL<75> A_WL<74> A_WL<73> A_WL<72> A_WL<71> A_WL<70> A_WL<69> A_WL<68> A_WL<67> A_WL<66> A_WL<65> A_WL<64> A_WL<63> A_WL<62> A_WL<61> A_WL<60> A_WL<59> A_WL<58> A_WL<57> A_WL<56> A_WL<55> A_WL<54> A_WL<53> A_WL<52> A_WL<51> A_WL<50> A_WL<49> A_WL<48> A_WL<47> A_WL<46> A_WL<45> A_WL<44> A_WL<43> A_WL<42> A_WL<41> A_WL<40> A_WL<39> A_WL<38> A_WL<37> A_WL<36> A_WL<35> A_WL<34> A_WL<33> A_WL<32> A_WL<31> A_WL<30> A_WL<29> A_WL<28> A_WL<27> A_WL<26> A_WL<25> A_WL<24> A_WL<23> A_WL<22> A_WL<21> A_WL<20> A_WL<19> A_WL<18> A_WL<17> A_WL<16> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> A_IWL<255> A_IWL<254> A_IWL<253> A_IWL<252> A_IWL<251> A_IWL<250> A_IWL<249> A_IWL<248> A_IWL<247> A_IWL<246> A_IWL<245> A_IWL<244> A_IWL<243> A_IWL<242> A_IWL<241> A_IWL<240> A_IWL<239> A_IWL<238> A_IWL<237> A_IWL<236> A_IWL<235> A_IWL<234> A_IWL<233> A_IWL<232> A_IWL<231> A_IWL<230> A_IWL<229> A_IWL<228> A_IWL<227> A_IWL<226> A_IWL<225> A_IWL<224> A_IWL<223> A_IWL<222> A_IWL<221> A_IWL<220> A_IWL<219> A_IWL<218> A_IWL<217> A_IWL<216> A_IWL<215> A_IWL<214> A_IWL<213> A_IWL<212> A_IWL<211> A_IWL<210> A_IWL<209> A_IWL<208> A_IWL<207> A_IWL<206> A_IWL<205> A_IWL<204> A_IWL<203> A_IWL<202> A_IWL<201> A_IWL<200> A_IWL<199> A_IWL<198> A_IWL<197> A_IWL<196> A_IWL<195> A_IWL<194> A_IWL<193> A_IWL<192> A_IWL<191> A_IWL<190> A_IWL<189> A_IWL<188> A_IWL<187> A_IWL<186> A_IWL<185> A_IWL<184> A_IWL<183> A_IWL<182> A_IWL<181> A_IWL<180> A_IWL<179> A_IWL<178> A_IWL<177> A_IWL<176> A_IWL<175> A_IWL<174> A_IWL<173> A_IWL<172> A_IWL<171> A_IWL<170> A_IWL<169> A_IWL<168> A_IWL<167> A_IWL<166> A_IWL<165> A_IWL<164> A_IWL<163> A_IWL<162> A_IWL<161> A_IWL<160> A_IWL<159> A_IWL<158> A_IWL<157> A_IWL<156> A_IWL<155> A_IWL<154> A_IWL<153> A_IWL<152> A_IWL<151> A_IWL<150> A_IWL<149> A_IWL<148> A_IWL<147> A_IWL<146> A_IWL<145> A_IWL<144> A_IWL<143> A_IWL<142> A_IWL<141> A_IWL<140> A_IWL<139> A_IWL<138> A_IWL<137> A_IWL<136> A_IWL<135> A_IWL<134> A_IWL<133> A_IWL<132> A_IWL<131> A_IWL<130> A_IWL<129> A_IWL<128> A_IWL<127> A_IWL<126> A_IWL<125> A_IWL<124> A_IWL<123> A_IWL<122> A_IWL<121> A_IWL<120> A_IWL<119> A_IWL<118> A_IWL<117> A_IWL<116> A_IWL<115> A_IWL<114> A_IWL<113> A_IWL<112> A_IWL<111> A_IWL<110> A_IWL<109> A_IWL<108> A_IWL<107> A_IWL<106> A_IWL<105> A_IWL<104> A_IWL<103> A_IWL<102> A_IWL<101> A_IWL<100> A_IWL<99> A_IWL<98> A_IWL<97> A_IWL<96> A_IWL<95> A_IWL<94> A_IWL<93> A_IWL<92> A_IWL<91> A_IWL<90> A_IWL<89> A_IWL<88> A_IWL<87> A_IWL<86> A_IWL<85> A_IWL<84> A_IWL<83> A_IWL<82> A_IWL<81> A_IWL<80> A_IWL<79> A_IWL<78> A_IWL<77> A_IWL<76> A_IWL<75> A_IWL<74> A_IWL<73> A_IWL<72> A_IWL<71> A_IWL<70> A_IWL<69> A_IWL<68> A_IWL<67> A_IWL<66> A_IWL<65> A_IWL<64> A_IWL<63> A_IWL<62> A_IWL<61> A_IWL<60> A_IWL<59> A_IWL<58> A_IWL<57> A_IWL<56> A_IWL<55> A_IWL<54> A_IWL<53> A_IWL<52> A_IWL<51> A_IWL<50> A_IWL<49> A_IWL<48> A_IWL<47> A_IWL<46> A_IWL<45> A_IWL<44> A_IWL<43> A_IWL<42> A_IWL<41> A_IWL<40> A_IWL<39> A_IWL<38> A_IWL<37> A_IWL<36> A_IWL<35> A_IWL<34> A_IWL<33> A_IWL<32> A_IWL<31> A_IWL<30> A_IWL<29> A_IWL<28> A_IWL<27> A_IWL<26> A_IWL<25> A_IWL<24> A_IWL<23> A_IWL<22> A_IWL<21> A_IWL<20> A_IWL<19> A_IWL<18> A_IWL<17> A_IWL<16> A_IWL<15> A_IWL<14> A_IWL<13> A_IWL<12> A_IWL<11> A_IWL<10> A_IWL<9> A_IWL<8> A_IWL<7> A_IWL<6> A_IWL<5> A_IWL<4> A_IWL<3> A_IWL<2> A_IWL<1> A_IWL<0> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_COLUMN_pcell_0 +.ENDS + + + + +.SUBCKT RM_IHPSG13_1024x16_c2_1P_DLY_pcell_2 A Z VDD VSS + XIDL<2> D<7> Z VDD VSS / RSC_IHPSG13_CDLYX1 + XIDL<1> D<6> D<7> VDD VSS / RSC_IHPSG13_CDLYX1 + XIDM<6> D<5> D<6> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<5> D<4> D<5> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<4> D<3> D<4> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY +.ENDS + + +.SUBCKT RM_IHPSG13_1024x16_c2_1P_DLY_pcell_3 A Z VDD VSS + XIDL<4> D<7> Z VDD VSS / RSC_IHPSG13_CDLYX1 + XIDL<3> D<6> D<7> VDD VSS / RSC_IHPSG13_CDLYX1 + XIDL<2> D<5> D<6> VDD VSS / RSC_IHPSG13_CDLYX1 + XIDL<1> D<4> D<5> VDD VSS / RSC_IHPSG13_CDLYX1 + XIDM<4> D<3> D<4> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY +.ENDS + + + +.SUBCKT RM_IHPSG13_1P_1024x16_c2_bm_bist A_ADDR<9> A_ADDR<8> A_ADDR<7> A_ADDR<6> A_ADDR<5> A_ADDR<4> A_ADDR<3> A_ADDR<2> A_ADDR<1> A_ADDR<0> A_BIST_ADDR<9> A_BIST_ADDR<8> A_BIST_ADDR<7> A_BIST_ADDR<6> A_BIST_ADDR<5> A_BIST_ADDR<4> A_BIST_ADDR<3> A_BIST_ADDR<2> A_BIST_ADDR<1> A_BIST_ADDR<0> A_BIST_BM<15> A_BIST_BM<14> A_BIST_BM<13> A_BIST_BM<12> A_BIST_BM<11> A_BIST_BM<10> A_BIST_BM<9> A_BIST_BM<8> A_BIST_BM<7> A_BIST_BM<6> A_BIST_BM<5> A_BIST_BM<4> A_BIST_BM<3> A_BIST_BM<2> A_BIST_BM<1> A_BIST_BM<0> A_BIST_CLK A_BIST_DIN<15> A_BIST_DIN<14> A_BIST_DIN<13> A_BIST_DIN<12> A_BIST_DIN<11> A_BIST_DIN<10> A_BIST_DIN<9> A_BIST_DIN<8> A_BIST_DIN<7> A_BIST_DIN<6> A_BIST_DIN<5> A_BIST_DIN<4> A_BIST_DIN<3> A_BIST_DIN<2> A_BIST_DIN<1> A_BIST_DIN<0> A_BIST_EN A_BIST_MEN A_BIST_REN A_BIST_WEN A_BM<15> A_BM<14> A_BM<13> A_BM<12> A_BM<11> A_BM<10> A_BM<9> A_BM<8> A_BM<7> A_BM<6> A_BM<5> A_BM<4> A_BM<3> A_BM<2> A_BM<1> A_BM<0> A_CLK A_DIN<15> A_DIN<14> A_DIN<13> A_DIN<12> A_DIN<11> A_DIN<10> A_DIN<9> A_DIN<8> A_DIN<7> A_DIN<6> A_DIN<5> A_DIN<4> A_DIN<3> A_DIN<2> A_DIN<1> A_DIN<0> A_DLY A_DOUT<15> A_DOUT<14> A_DOUT<13> A_DOUT<12> A_DOUT<11> A_DOUT<10> A_DOUT<9> A_DOUT<8> A_DOUT<7> A_DOUT<6> A_DOUT<5> A_DOUT<4> A_DOUT<3> A_DOUT<2> A_DOUT<1> A_DOUT<0> A_MEN A_REN A_WEN VDD! VDDARRAY! VSS! + + +XRAM<1> a_blc_r<31> a_blc_r<30> a_blc_r<29> a_blc_r<28> a_blc_r<27> a_blc_r<26> a_blc_r<25> a_blc_r<24> a_blc_r<23> a_blc_r<22> a_blc_r<21> a_blc_r<20> a_blc_r<19> a_blc_r<18> a_blc_r<17> a_blc_r<16> a_blc_r<15> a_blc_r<14> a_blc_r<13> a_blc_r<12> a_blc_r<11> a_blc_r<10> a_blc_r<9> a_blc_r<8> a_blc_r<7> a_blc_r<6> a_blc_r<5> a_blc_r<4> a_blc_r<3> a_blc_r<2> a_blc_r<1> a_blc_r<0> a_blt_r<31> a_blt_r<30> a_blt_r<29> a_blt_r<28> a_blt_r<27> a_blt_r<26> a_blt_r<25> a_blt_r<24> a_blt_r<23> a_blt_r<22> a_blt_r<21> a_blt_r<20> a_blt_r<19> a_blt_r<18> a_blt_r<17> a_blt_r<16> a_blt_r<15> a_blt_r<14> a_blt_r<13> a_blt_r<12> a_blt_r<11> a_blt_r<10> a_blt_r<9> a_blt_r<8> a_blt_r<7> a_blt_r<6> a_blt_r<5> a_blt_r<4> a_blt_r<3> a_blt_r<2> a_blt_r<1> a_blt_r<0> a_wl_r<255> a_wl_r<254> a_wl_r<253> a_wl_r<252> a_wl_r<251> a_wl_r<250> a_wl_r<249> a_wl_r<248> a_wl_r<247> a_wl_r<246> a_wl_r<245> a_wl_r<244> a_wl_r<243> a_wl_r<242> a_wl_r<241> a_wl_r<240> a_wl_r<239> a_wl_r<238> a_wl_r<237> a_wl_r<236> a_wl_r<235> a_wl_r<234> a_wl_r<233> a_wl_r<232> a_wl_r<231> a_wl_r<230> a_wl_r<229> a_wl_r<228> a_wl_r<227> a_wl_r<226> a_wl_r<225> a_wl_r<224> a_wl_r<223> a_wl_r<222> a_wl_r<221> a_wl_r<220> a_wl_r<219> a_wl_r<218> a_wl_r<217> a_wl_r<216> a_wl_r<215> a_wl_r<214> a_wl_r<213> a_wl_r<212> a_wl_r<211> a_wl_r<210> a_wl_r<209> a_wl_r<208> a_wl_r<207> a_wl_r<206> a_wl_r<205> a_wl_r<204> a_wl_r<203> a_wl_r<202> a_wl_r<201> a_wl_r<200> a_wl_r<199> a_wl_r<198> a_wl_r<197> a_wl_r<196> a_wl_r<195> a_wl_r<194> a_wl_r<193> a_wl_r<192> a_wl_r<191> a_wl_r<190> a_wl_r<189> a_wl_r<188> a_wl_r<187> a_wl_r<186> a_wl_r<185> a_wl_r<184> a_wl_r<183> a_wl_r<182> a_wl_r<181> a_wl_r<180> a_wl_r<179> a_wl_r<178> a_wl_r<177> a_wl_r<176> a_wl_r<175> a_wl_r<174> a_wl_r<173> a_wl_r<172> a_wl_r<171> a_wl_r<170> a_wl_r<169> a_wl_r<168> a_wl_r<167> a_wl_r<166> a_wl_r<165> a_wl_r<164> a_wl_r<163> a_wl_r<162> a_wl_r<161> a_wl_r<160> a_wl_r<159> a_wl_r<158> a_wl_r<157> a_wl_r<156> a_wl_r<155> a_wl_r<154> a_wl_r<153> a_wl_r<152> a_wl_r<151> a_wl_r<150> a_wl_r<149> a_wl_r<148> a_wl_r<147> a_wl_r<146> a_wl_r<145> a_wl_r<144> a_wl_r<143> a_wl_r<142> a_wl_r<141> a_wl_r<140> a_wl_r<139> a_wl_r<138> a_wl_r<137> a_wl_r<136> a_wl_r<135> a_wl_r<134> a_wl_r<133> a_wl_r<132> a_wl_r<131> a_wl_r<130> a_wl_r<129> a_wl_r<128> a_wl_r<127> a_wl_r<126> a_wl_r<125> a_wl_r<124> a_wl_r<123> a_wl_r<122> a_wl_r<121> a_wl_r<120> a_wl_r<119> a_wl_r<118> a_wl_r<117> a_wl_r<116> a_wl_r<115> a_wl_r<114> a_wl_r<113> a_wl_r<112> a_wl_r<111> a_wl_r<110> a_wl_r<109> a_wl_r<108> a_wl_r<107> a_wl_r<106> a_wl_r<105> a_wl_r<104> a_wl_r<103> a_wl_r<102> a_wl_r<101> a_wl_r<100> a_wl_r<99> a_wl_r<98> a_wl_r<97> a_wl_r<96> a_wl_r<95> a_wl_r<94> a_wl_r<93> a_wl_r<92> a_wl_r<91> a_wl_r<90> a_wl_r<89> a_wl_r<88> a_wl_r<87> a_wl_r<86> a_wl_r<85> a_wl_r<84> a_wl_r<83> a_wl_r<82> a_wl_r<81> a_wl_r<80> a_wl_r<79> a_wl_r<78> a_wl_r<77> a_wl_r<76> a_wl_r<75> a_wl_r<74> a_wl_r<73> a_wl_r<72> a_wl_r<71> a_wl_r<70> a_wl_r<69> a_wl_r<68> a_wl_r<67> a_wl_r<66> a_wl_r<65> a_wl_r<64> a_wl_r<63> a_wl_r<62> a_wl_r<61> a_wl_r<60> a_wl_r<59> a_wl_r<58> a_wl_r<57> a_wl_r<56> a_wl_r<55> a_wl_r<54> a_wl_r<53> a_wl_r<52> a_wl_r<51> a_wl_r<50> a_wl_r<49> a_wl_r<48> a_wl_r<47> a_wl_r<46> a_wl_r<45> a_wl_r<44> a_wl_r<43> a_wl_r<42> a_wl_r<41> a_wl_r<40> a_wl_r<39> a_wl_r<38> a_wl_r<37> a_wl_r<36> a_wl_r<35> a_wl_r<34> a_wl_r<33> a_wl_r<32> a_wl_r<31> a_wl_r<30> a_wl_r<29> a_wl_r<28> a_wl_r<27> a_wl_r<26> a_wl_r<25> a_wl_r<24> a_wl_r<23> a_wl_r<22> a_wl_r<21> a_wl_r<20> a_wl_r<19> a_wl_r<18> a_wl_r<17> a_wl_r<16> a_wl_r<15> a_wl_r<14> a_wl_r<13> a_wl_r<12> a_wl_r<11> a_wl_r<10> a_wl_r<9> a_wl_r<8> a_wl_r<7> a_wl_r<6> a_wl_r<5> a_wl_r<4> a_wl_r<3> a_wl_r<2> a_wl_r<1> a_wl_r<0> VDDARRAY! VSS! / RM_IHPSG13_1024x16_c2_1P_MATRIX_pcell_1 +XRAM<0> a_blc_l<31> a_blc_l<30> a_blc_l<29> a_blc_l<28> a_blc_l<27> a_blc_l<26> a_blc_l<25> a_blc_l<24> a_blc_l<23> a_blc_l<22> a_blc_l<21> a_blc_l<20> a_blc_l<19> a_blc_l<18> a_blc_l<17> a_blc_l<16> a_blc_l<15> a_blc_l<14> a_blc_l<13> a_blc_l<12> a_blc_l<11> a_blc_l<10> a_blc_l<9> a_blc_l<8> a_blc_l<7> a_blc_l<6> a_blc_l<5> a_blc_l<4> a_blc_l<3> a_blc_l<2> a_blc_l<1> a_blc_l<0> a_blt_l<31> a_blt_l<30> a_blt_l<29> a_blt_l<28> a_blt_l<27> a_blt_l<26> a_blt_l<25> a_blt_l<24> a_blt_l<23> a_blt_l<22> a_blt_l<21> a_blt_l<20> a_blt_l<19> a_blt_l<18> a_blt_l<17> a_blt_l<16> a_blt_l<15> a_blt_l<14> a_blt_l<13> a_blt_l<12> a_blt_l<11> a_blt_l<10> a_blt_l<9> a_blt_l<8> a_blt_l<7> a_blt_l<6> a_blt_l<5> a_blt_l<4> a_blt_l<3> a_blt_l<2> a_blt_l<1> a_blt_l<0> a_wl_l<255> a_wl_l<254> a_wl_l<253> a_wl_l<252> a_wl_l<251> a_wl_l<250> a_wl_l<249> a_wl_l<248> a_wl_l<247> a_wl_l<246> a_wl_l<245> a_wl_l<244> a_wl_l<243> a_wl_l<242> a_wl_l<241> a_wl_l<240> a_wl_l<239> a_wl_l<238> a_wl_l<237> a_wl_l<236> a_wl_l<235> a_wl_l<234> a_wl_l<233> a_wl_l<232> a_wl_l<231> a_wl_l<230> a_wl_l<229> a_wl_l<228> a_wl_l<227> a_wl_l<226> a_wl_l<225> a_wl_l<224> a_wl_l<223> a_wl_l<222> a_wl_l<221> a_wl_l<220> a_wl_l<219> a_wl_l<218> a_wl_l<217> a_wl_l<216> a_wl_l<215> a_wl_l<214> a_wl_l<213> a_wl_l<212> a_wl_l<211> a_wl_l<210> a_wl_l<209> a_wl_l<208> a_wl_l<207> a_wl_l<206> a_wl_l<205> a_wl_l<204> a_wl_l<203> a_wl_l<202> a_wl_l<201> a_wl_l<200> a_wl_l<199> a_wl_l<198> a_wl_l<197> a_wl_l<196> a_wl_l<195> a_wl_l<194> a_wl_l<193> a_wl_l<192> a_wl_l<191> a_wl_l<190> a_wl_l<189> a_wl_l<188> a_wl_l<187> a_wl_l<186> a_wl_l<185> a_wl_l<184> a_wl_l<183> a_wl_l<182> a_wl_l<181> a_wl_l<180> a_wl_l<179> a_wl_l<178> a_wl_l<177> a_wl_l<176> a_wl_l<175> a_wl_l<174> a_wl_l<173> a_wl_l<172> a_wl_l<171> a_wl_l<170> a_wl_l<169> a_wl_l<168> a_wl_l<167> a_wl_l<166> a_wl_l<165> a_wl_l<164> a_wl_l<163> a_wl_l<162> a_wl_l<161> a_wl_l<160> a_wl_l<159> a_wl_l<158> a_wl_l<157> a_wl_l<156> a_wl_l<155> a_wl_l<154> a_wl_l<153> a_wl_l<152> a_wl_l<151> a_wl_l<150> a_wl_l<149> a_wl_l<148> a_wl_l<147> a_wl_l<146> a_wl_l<145> a_wl_l<144> a_wl_l<143> a_wl_l<142> a_wl_l<141> a_wl_l<140> a_wl_l<139> a_wl_l<138> a_wl_l<137> a_wl_l<136> a_wl_l<135> a_wl_l<134> a_wl_l<133> a_wl_l<132> a_wl_l<131> a_wl_l<130> a_wl_l<129> a_wl_l<128> a_wl_l<127> a_wl_l<126> a_wl_l<125> a_wl_l<124> a_wl_l<123> a_wl_l<122> a_wl_l<121> a_wl_l<120> a_wl_l<119> a_wl_l<118> a_wl_l<117> a_wl_l<116> a_wl_l<115> a_wl_l<114> a_wl_l<113> a_wl_l<112> a_wl_l<111> a_wl_l<110> a_wl_l<109> a_wl_l<108> a_wl_l<107> a_wl_l<106> a_wl_l<105> a_wl_l<104> a_wl_l<103> a_wl_l<102> a_wl_l<101> a_wl_l<100> a_wl_l<99> a_wl_l<98> a_wl_l<97> a_wl_l<96> a_wl_l<95> a_wl_l<94> a_wl_l<93> a_wl_l<92> a_wl_l<91> a_wl_l<90> a_wl_l<89> a_wl_l<88> a_wl_l<87> a_wl_l<86> a_wl_l<85> a_wl_l<84> a_wl_l<83> a_wl_l<82> a_wl_l<81> a_wl_l<80> a_wl_l<79> a_wl_l<78> a_wl_l<77> a_wl_l<76> a_wl_l<75> a_wl_l<74> a_wl_l<73> a_wl_l<72> a_wl_l<71> a_wl_l<70> a_wl_l<69> a_wl_l<68> a_wl_l<67> a_wl_l<66> a_wl_l<65> a_wl_l<64> a_wl_l<63> a_wl_l<62> a_wl_l<61> a_wl_l<60> a_wl_l<59> a_wl_l<58> a_wl_l<57> a_wl_l<56> a_wl_l<55> a_wl_l<54> a_wl_l<53> a_wl_l<52> a_wl_l<51> a_wl_l<50> a_wl_l<49> a_wl_l<48> a_wl_l<47> a_wl_l<46> a_wl_l<45> a_wl_l<44> a_wl_l<43> a_wl_l<42> a_wl_l<41> a_wl_l<40> a_wl_l<39> a_wl_l<38> a_wl_l<37> a_wl_l<36> a_wl_l<35> a_wl_l<34> a_wl_l<33> a_wl_l<32> a_wl_l<31> a_wl_l<30> a_wl_l<29> a_wl_l<28> a_wl_l<27> a_wl_l<26> a_wl_l<25> a_wl_l<24> a_wl_l<23> a_wl_l<22> a_wl_l<21> a_wl_l<20> a_wl_l<19> a_wl_l<18> a_wl_l<17> a_wl_l<16> a_wl_l<15> a_wl_l<14> a_wl_l<13> a_wl_l<12> a_wl_l<11> a_wl_l<10> a_wl_l<9> a_wl_l<8> a_wl_l<7> a_wl_l<6> a_wl_l<5> a_wl_l<4> a_wl_l<3> a_wl_l<2> a_wl_l<1> a_wl_l<0> VDDARRAY! VSS! / RM_IHPSG13_1024x16_c2_1P_MATRIX_pcell_1 + + +XA_COLDRV<1> a_addr_col<1> a_addr_col<0> a_addr_col_r<1> a_addr_col_r<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> a_dclk a_dclk_p_r<0> a_rclk a_rclk_p_r<0> a_wclk a_wclk_p_r<0> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_COLDRV13X4 +XA_COLDRV<0> a_addr_col<1> a_addr_col<0> a_addr_col_l<1> a_addr_col_l<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> a_dclk a_dclk_p_l<0> a_rclk a_rclk_p_l<0> a_wclk a_wclk_p_l<0> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_COLDRV13X4 + + +XA_WLDRV<31> a_wi<255> a_wi<254> a_wi<253> a_wi<252> a_wi<251> a_wi<250> a_wi<249> a_wi<248> a_wi<247> a_wi<246> a_wi<245> a_wi<244> a_wi<243> a_wi<242> a_wi<241> a_wi<240> a_wl_r<255> a_wl_r<254> a_wl_r<253> a_wl_r<252> a_wl_r<251> a_wl_r<250> a_wl_r<249> a_wl_r<248> a_wl_r<247> a_wl_r<246> a_wl_r<245> a_wl_r<244> a_wl_r<243> a_wl_r<242> a_wl_r<241> a_wl_r<240> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_WLDRV16X4 +XA_WLDRV<30> a_wi<239> a_wi<238> a_wi<237> a_wi<236> a_wi<235> a_wi<234> a_wi<233> a_wi<232> a_wi<231> a_wi<230> a_wi<229> a_wi<228> a_wi<227> a_wi<226> a_wi<225> a_wi<224> a_wl_r<239> a_wl_r<238> a_wl_r<237> a_wl_r<236> a_wl_r<235> a_wl_r<234> a_wl_r<233> a_wl_r<232> a_wl_r<231> a_wl_r<230> a_wl_r<229> a_wl_r<228> a_wl_r<227> a_wl_r<226> a_wl_r<225> a_wl_r<224> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_WLDRV16X4 +XA_WLDRV<29> a_wi<223> a_wi<222> a_wi<221> a_wi<220> a_wi<219> a_wi<218> a_wi<217> a_wi<216> a_wi<215> a_wi<214> a_wi<213> a_wi<212> a_wi<211> a_wi<210> a_wi<209> a_wi<208> a_wl_r<223> a_wl_r<222> a_wl_r<221> a_wl_r<220> a_wl_r<219> a_wl_r<218> a_wl_r<217> a_wl_r<216> a_wl_r<215> a_wl_r<214> a_wl_r<213> a_wl_r<212> a_wl_r<211> a_wl_r<210> a_wl_r<209> a_wl_r<208> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_WLDRV16X4 +XA_WLDRV<28> a_wi<207> a_wi<206> a_wi<205> a_wi<204> a_wi<203> a_wi<202> a_wi<201> a_wi<200> a_wi<199> a_wi<198> a_wi<197> a_wi<196> a_wi<195> a_wi<194> a_wi<193> a_wi<192> a_wl_r<207> a_wl_r<206> a_wl_r<205> a_wl_r<204> a_wl_r<203> a_wl_r<202> a_wl_r<201> a_wl_r<200> a_wl_r<199> a_wl_r<198> a_wl_r<197> a_wl_r<196> a_wl_r<195> a_wl_r<194> a_wl_r<193> a_wl_r<192> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_WLDRV16X4 +XA_WLDRV<27> a_wi<191> a_wi<190> a_wi<189> a_wi<188> a_wi<187> a_wi<186> a_wi<185> a_wi<184> a_wi<183> a_wi<182> a_wi<181> a_wi<180> a_wi<179> a_wi<178> a_wi<177> a_wi<176> a_wl_r<191> a_wl_r<190> a_wl_r<189> a_wl_r<188> a_wl_r<187> a_wl_r<186> a_wl_r<185> a_wl_r<184> a_wl_r<183> a_wl_r<182> a_wl_r<181> a_wl_r<180> a_wl_r<179> a_wl_r<178> a_wl_r<177> a_wl_r<176> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_WLDRV16X4 +XA_WLDRV<26> a_wi<175> a_wi<174> a_wi<173> a_wi<172> a_wi<171> a_wi<170> a_wi<169> a_wi<168> a_wi<167> a_wi<166> a_wi<165> a_wi<164> a_wi<163> a_wi<162> a_wi<161> a_wi<160> a_wl_r<175> a_wl_r<174> a_wl_r<173> a_wl_r<172> a_wl_r<171> a_wl_r<170> a_wl_r<169> a_wl_r<168> a_wl_r<167> a_wl_r<166> a_wl_r<165> a_wl_r<164> a_wl_r<163> a_wl_r<162> a_wl_r<161> a_wl_r<160> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_WLDRV16X4 +XA_WLDRV<25> a_wi<159> a_wi<158> a_wi<157> a_wi<156> a_wi<155> a_wi<154> a_wi<153> a_wi<152> a_wi<151> a_wi<150> a_wi<149> a_wi<148> a_wi<147> a_wi<146> a_wi<145> a_wi<144> a_wl_r<159> a_wl_r<158> a_wl_r<157> a_wl_r<156> a_wl_r<155> a_wl_r<154> a_wl_r<153> a_wl_r<152> a_wl_r<151> a_wl_r<150> a_wl_r<149> a_wl_r<148> a_wl_r<147> a_wl_r<146> a_wl_r<145> a_wl_r<144> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_WLDRV16X4 +XA_WLDRV<24> a_wi<143> a_wi<142> a_wi<141> a_wi<140> a_wi<139> a_wi<138> a_wi<137> a_wi<136> a_wi<135> a_wi<134> a_wi<133> a_wi<132> a_wi<131> a_wi<130> a_wi<129> a_wi<128> a_wl_r<143> a_wl_r<142> a_wl_r<141> a_wl_r<140> a_wl_r<139> a_wl_r<138> a_wl_r<137> a_wl_r<136> a_wl_r<135> a_wl_r<134> a_wl_r<133> a_wl_r<132> a_wl_r<131> a_wl_r<130> a_wl_r<129> a_wl_r<128> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_WLDRV16X4 +XA_WLDRV<23> a_wi<127> a_wi<126> a_wi<125> a_wi<124> a_wi<123> a_wi<122> a_wi<121> a_wi<120> a_wi<119> a_wi<118> a_wi<117> a_wi<116> a_wi<115> a_wi<114> a_wi<113> a_wi<112> a_wl_r<127> a_wl_r<126> a_wl_r<125> a_wl_r<124> a_wl_r<123> a_wl_r<122> a_wl_r<121> a_wl_r<120> a_wl_r<119> a_wl_r<118> a_wl_r<117> a_wl_r<116> a_wl_r<115> a_wl_r<114> a_wl_r<113> a_wl_r<112> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_WLDRV16X4 +XA_WLDRV<22> a_wi<111> a_wi<110> a_wi<109> a_wi<108> a_wi<107> a_wi<106> a_wi<105> a_wi<104> a_wi<103> a_wi<102> a_wi<101> a_wi<100> a_wi<99> a_wi<98> a_wi<97> a_wi<96> a_wl_r<111> a_wl_r<110> a_wl_r<109> a_wl_r<108> a_wl_r<107> a_wl_r<106> a_wl_r<105> a_wl_r<104> a_wl_r<103> a_wl_r<102> a_wl_r<101> a_wl_r<100> a_wl_r<99> a_wl_r<98> a_wl_r<97> a_wl_r<96> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_WLDRV16X4 +XA_WLDRV<21> a_wi<95> a_wi<94> a_wi<93> a_wi<92> a_wi<91> a_wi<90> a_wi<89> a_wi<88> a_wi<87> a_wi<86> a_wi<85> a_wi<84> a_wi<83> a_wi<82> a_wi<81> a_wi<80> a_wl_r<95> a_wl_r<94> a_wl_r<93> a_wl_r<92> a_wl_r<91> a_wl_r<90> a_wl_r<89> a_wl_r<88> a_wl_r<87> a_wl_r<86> a_wl_r<85> a_wl_r<84> a_wl_r<83> a_wl_r<82> a_wl_r<81> a_wl_r<80> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_WLDRV16X4 +XA_WLDRV<20> a_wi<79> a_wi<78> a_wi<77> a_wi<76> a_wi<75> a_wi<74> a_wi<73> a_wi<72> a_wi<71> a_wi<70> a_wi<69> a_wi<68> a_wi<67> a_wi<66> a_wi<65> a_wi<64> a_wl_r<79> a_wl_r<78> a_wl_r<77> a_wl_r<76> a_wl_r<75> a_wl_r<74> a_wl_r<73> a_wl_r<72> a_wl_r<71> a_wl_r<70> a_wl_r<69> a_wl_r<68> a_wl_r<67> a_wl_r<66> a_wl_r<65> a_wl_r<64> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_WLDRV16X4 +XA_WLDRV<19> a_wi<63> a_wi<62> a_wi<61> a_wi<60> a_wi<59> a_wi<58> a_wi<57> a_wi<56> a_wi<55> a_wi<54> a_wi<53> a_wi<52> a_wi<51> a_wi<50> a_wi<49> a_wi<48> a_wl_r<63> a_wl_r<62> a_wl_r<61> a_wl_r<60> a_wl_r<59> a_wl_r<58> a_wl_r<57> a_wl_r<56> a_wl_r<55> a_wl_r<54> a_wl_r<53> a_wl_r<52> a_wl_r<51> a_wl_r<50> a_wl_r<49> a_wl_r<48> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_WLDRV16X4 +XA_WLDRV<18> a_wi<47> a_wi<46> a_wi<45> a_wi<44> a_wi<43> a_wi<42> a_wi<41> a_wi<40> a_wi<39> a_wi<38> a_wi<37> a_wi<36> a_wi<35> a_wi<34> a_wi<33> a_wi<32> a_wl_r<47> a_wl_r<46> a_wl_r<45> a_wl_r<44> a_wl_r<43> a_wl_r<42> a_wl_r<41> a_wl_r<40> a_wl_r<39> a_wl_r<38> a_wl_r<37> a_wl_r<36> a_wl_r<35> a_wl_r<34> a_wl_r<33> a_wl_r<32> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_WLDRV16X4 +XA_WLDRV<17> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wl_r<31> a_wl_r<30> a_wl_r<29> a_wl_r<28> a_wl_r<27> a_wl_r<26> a_wl_r<25> a_wl_r<24> a_wl_r<23> a_wl_r<22> a_wl_r<21> a_wl_r<20> a_wl_r<19> a_wl_r<18> a_wl_r<17> a_wl_r<16> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_WLDRV16X4 +XA_WLDRV<16> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> a_wl_r<15> a_wl_r<14> a_wl_r<13> a_wl_r<12> a_wl_r<11> a_wl_r<10> a_wl_r<9> a_wl_r<8> a_wl_r<7> a_wl_r<6> a_wl_r<5> a_wl_r<4> a_wl_r<3> a_wl_r<2> a_wl_r<1> a_wl_r<0> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_WLDRV16X4 +XA_WLDRV<15> a_wi<255> a_wi<254> a_wi<253> a_wi<252> a_wi<251> a_wi<250> a_wi<249> a_wi<248> a_wi<247> a_wi<246> a_wi<245> a_wi<244> a_wi<243> a_wi<242> a_wi<241> a_wi<240> a_wl_l<255> a_wl_l<254> a_wl_l<253> a_wl_l<252> a_wl_l<251> a_wl_l<250> a_wl_l<249> a_wl_l<248> a_wl_l<247> a_wl_l<246> a_wl_l<245> a_wl_l<244> a_wl_l<243> a_wl_l<242> a_wl_l<241> a_wl_l<240> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_WLDRV16X4 +XA_WLDRV<14> a_wi<239> a_wi<238> a_wi<237> a_wi<236> a_wi<235> a_wi<234> a_wi<233> a_wi<232> a_wi<231> a_wi<230> a_wi<229> a_wi<228> a_wi<227> a_wi<226> a_wi<225> a_wi<224> a_wl_l<239> a_wl_l<238> a_wl_l<237> a_wl_l<236> a_wl_l<235> a_wl_l<234> a_wl_l<233> a_wl_l<232> a_wl_l<231> a_wl_l<230> a_wl_l<229> a_wl_l<228> a_wl_l<227> a_wl_l<226> a_wl_l<225> a_wl_l<224> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_WLDRV16X4 +XA_WLDRV<13> a_wi<223> a_wi<222> a_wi<221> a_wi<220> a_wi<219> a_wi<218> a_wi<217> a_wi<216> a_wi<215> a_wi<214> a_wi<213> a_wi<212> a_wi<211> a_wi<210> a_wi<209> a_wi<208> a_wl_l<223> a_wl_l<222> a_wl_l<221> a_wl_l<220> a_wl_l<219> a_wl_l<218> a_wl_l<217> a_wl_l<216> a_wl_l<215> a_wl_l<214> a_wl_l<213> a_wl_l<212> a_wl_l<211> a_wl_l<210> a_wl_l<209> a_wl_l<208> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_WLDRV16X4 +XA_WLDRV<12> a_wi<207> a_wi<206> a_wi<205> a_wi<204> a_wi<203> a_wi<202> a_wi<201> a_wi<200> a_wi<199> a_wi<198> a_wi<197> a_wi<196> a_wi<195> a_wi<194> a_wi<193> a_wi<192> a_wl_l<207> a_wl_l<206> a_wl_l<205> a_wl_l<204> a_wl_l<203> a_wl_l<202> a_wl_l<201> a_wl_l<200> a_wl_l<199> a_wl_l<198> a_wl_l<197> a_wl_l<196> a_wl_l<195> a_wl_l<194> a_wl_l<193> a_wl_l<192> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_WLDRV16X4 +XA_WLDRV<11> a_wi<191> a_wi<190> a_wi<189> a_wi<188> a_wi<187> a_wi<186> a_wi<185> a_wi<184> a_wi<183> a_wi<182> a_wi<181> a_wi<180> a_wi<179> a_wi<178> a_wi<177> a_wi<176> a_wl_l<191> a_wl_l<190> a_wl_l<189> a_wl_l<188> a_wl_l<187> a_wl_l<186> a_wl_l<185> a_wl_l<184> a_wl_l<183> a_wl_l<182> a_wl_l<181> a_wl_l<180> a_wl_l<179> a_wl_l<178> a_wl_l<177> a_wl_l<176> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_WLDRV16X4 +XA_WLDRV<10> a_wi<175> a_wi<174> a_wi<173> a_wi<172> a_wi<171> a_wi<170> a_wi<169> a_wi<168> a_wi<167> a_wi<166> a_wi<165> a_wi<164> a_wi<163> a_wi<162> a_wi<161> a_wi<160> a_wl_l<175> a_wl_l<174> a_wl_l<173> a_wl_l<172> a_wl_l<171> a_wl_l<170> a_wl_l<169> a_wl_l<168> a_wl_l<167> a_wl_l<166> a_wl_l<165> a_wl_l<164> a_wl_l<163> a_wl_l<162> a_wl_l<161> a_wl_l<160> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_WLDRV16X4 +XA_WLDRV<9> a_wi<159> a_wi<158> a_wi<157> a_wi<156> a_wi<155> a_wi<154> a_wi<153> a_wi<152> a_wi<151> a_wi<150> a_wi<149> a_wi<148> a_wi<147> a_wi<146> a_wi<145> a_wi<144> a_wl_l<159> a_wl_l<158> a_wl_l<157> a_wl_l<156> a_wl_l<155> a_wl_l<154> a_wl_l<153> a_wl_l<152> a_wl_l<151> a_wl_l<150> a_wl_l<149> a_wl_l<148> a_wl_l<147> a_wl_l<146> a_wl_l<145> a_wl_l<144> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_WLDRV16X4 +XA_WLDRV<8> a_wi<143> a_wi<142> a_wi<141> a_wi<140> a_wi<139> a_wi<138> a_wi<137> a_wi<136> a_wi<135> a_wi<134> a_wi<133> a_wi<132> a_wi<131> a_wi<130> a_wi<129> a_wi<128> a_wl_l<143> a_wl_l<142> a_wl_l<141> a_wl_l<140> a_wl_l<139> a_wl_l<138> a_wl_l<137> a_wl_l<136> a_wl_l<135> a_wl_l<134> a_wl_l<133> a_wl_l<132> a_wl_l<131> a_wl_l<130> a_wl_l<129> a_wl_l<128> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_WLDRV16X4 +XA_WLDRV<7> a_wi<127> a_wi<126> a_wi<125> a_wi<124> a_wi<123> a_wi<122> a_wi<121> a_wi<120> a_wi<119> a_wi<118> a_wi<117> a_wi<116> a_wi<115> a_wi<114> a_wi<113> a_wi<112> a_wl_l<127> a_wl_l<126> a_wl_l<125> a_wl_l<124> a_wl_l<123> a_wl_l<122> a_wl_l<121> a_wl_l<120> a_wl_l<119> a_wl_l<118> a_wl_l<117> a_wl_l<116> a_wl_l<115> a_wl_l<114> a_wl_l<113> a_wl_l<112> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_WLDRV16X4 +XA_WLDRV<6> a_wi<111> a_wi<110> a_wi<109> a_wi<108> a_wi<107> a_wi<106> a_wi<105> a_wi<104> a_wi<103> a_wi<102> a_wi<101> a_wi<100> a_wi<99> a_wi<98> a_wi<97> a_wi<96> a_wl_l<111> a_wl_l<110> a_wl_l<109> a_wl_l<108> a_wl_l<107> a_wl_l<106> a_wl_l<105> a_wl_l<104> a_wl_l<103> a_wl_l<102> a_wl_l<101> a_wl_l<100> a_wl_l<99> a_wl_l<98> a_wl_l<97> a_wl_l<96> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_WLDRV16X4 +XA_WLDRV<5> a_wi<95> a_wi<94> a_wi<93> a_wi<92> a_wi<91> a_wi<90> a_wi<89> a_wi<88> a_wi<87> a_wi<86> a_wi<85> a_wi<84> a_wi<83> a_wi<82> a_wi<81> a_wi<80> a_wl_l<95> a_wl_l<94> a_wl_l<93> a_wl_l<92> a_wl_l<91> a_wl_l<90> a_wl_l<89> a_wl_l<88> a_wl_l<87> a_wl_l<86> a_wl_l<85> a_wl_l<84> a_wl_l<83> a_wl_l<82> a_wl_l<81> a_wl_l<80> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_WLDRV16X4 +XA_WLDRV<4> a_wi<79> a_wi<78> a_wi<77> a_wi<76> a_wi<75> a_wi<74> a_wi<73> a_wi<72> a_wi<71> a_wi<70> a_wi<69> a_wi<68> a_wi<67> a_wi<66> a_wi<65> a_wi<64> a_wl_l<79> a_wl_l<78> a_wl_l<77> a_wl_l<76> a_wl_l<75> a_wl_l<74> a_wl_l<73> a_wl_l<72> a_wl_l<71> a_wl_l<70> a_wl_l<69> a_wl_l<68> a_wl_l<67> a_wl_l<66> a_wl_l<65> a_wl_l<64> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_WLDRV16X4 +XA_WLDRV<3> a_wi<63> a_wi<62> a_wi<61> a_wi<60> a_wi<59> a_wi<58> a_wi<57> a_wi<56> a_wi<55> a_wi<54> a_wi<53> a_wi<52> a_wi<51> a_wi<50> a_wi<49> a_wi<48> a_wl_l<63> a_wl_l<62> a_wl_l<61> a_wl_l<60> a_wl_l<59> a_wl_l<58> a_wl_l<57> a_wl_l<56> a_wl_l<55> a_wl_l<54> a_wl_l<53> a_wl_l<52> a_wl_l<51> a_wl_l<50> a_wl_l<49> a_wl_l<48> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_WLDRV16X4 +XA_WLDRV<2> a_wi<47> a_wi<46> a_wi<45> a_wi<44> a_wi<43> a_wi<42> a_wi<41> a_wi<40> a_wi<39> a_wi<38> a_wi<37> a_wi<36> a_wi<35> a_wi<34> a_wi<33> a_wi<32> a_wl_l<47> a_wl_l<46> a_wl_l<45> a_wl_l<44> a_wl_l<43> a_wl_l<42> a_wl_l<41> a_wl_l<40> a_wl_l<39> a_wl_l<38> a_wl_l<37> a_wl_l<36> a_wl_l<35> a_wl_l<34> a_wl_l<33> a_wl_l<32> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_WLDRV16X4 +XA_WLDRV<1> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wl_l<31> a_wl_l<30> a_wl_l<29> a_wl_l<28> a_wl_l<27> a_wl_l<26> a_wl_l<25> a_wl_l<24> a_wl_l<23> a_wl_l<22> a_wl_l<21> a_wl_l<20> a_wl_l<19> a_wl_l<18> a_wl_l<17> a_wl_l<16> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_WLDRV16X4 +XA_WLDRV<0> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> a_wl_l<15> a_wl_l<14> a_wl_l<13> a_wl_l<12> a_wl_l<11> a_wl_l<10> a_wl_l<9> a_wl_l<8> a_wl_l<7> a_wl_l<6> a_wl_l<5> a_wl_l<4> a_wl_l<3> a_wl_l<2> a_wl_l<1> a_wl_l<0> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_WLDRV16X4 + + +XA_CTRL a_aclk_n A_BIST_CLK A_BIST_MEN A_BIST_EN A_BIST_REN A_BIST_WEN a_tiel A_CLK A_MEN a_dclk a_eclk a_pulse_h a_pulse_l a_pulse a_rclk A_REN a_cs a_wclk A_WEN VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_CTRL + + +XA_ROWDEC a_addr_row<7> a_addr_row<6> a_addr_row<5> a_addr_row<4> a_addr_row<3> a_addr_row<2> a_addr_row<1> a_addr_row<0> a_cs a_eclk a_wi<255> a_wi<254> a_wi<253> a_wi<252> a_wi<251> a_wi<250> a_wi<249> a_wi<248> a_wi<247> a_wi<246> a_wi<245> a_wi<244> a_wi<243> a_wi<242> a_wi<241> a_wi<240> a_wi<239> a_wi<238> a_wi<237> a_wi<236> a_wi<235> a_wi<234> a_wi<233> a_wi<232> a_wi<231> a_wi<230> a_wi<229> a_wi<228> a_wi<227> a_wi<226> a_wi<225> a_wi<224> a_wi<223> a_wi<222> a_wi<221> a_wi<220> a_wi<219> a_wi<218> a_wi<217> a_wi<216> a_wi<215> a_wi<214> a_wi<213> a_wi<212> a_wi<211> a_wi<210> a_wi<209> a_wi<208> a_wi<207> a_wi<206> a_wi<205> a_wi<204> a_wi<203> a_wi<202> a_wi<201> a_wi<200> a_wi<199> a_wi<198> a_wi<197> a_wi<196> a_wi<195> a_wi<194> a_wi<193> a_wi<192> a_wi<191> a_wi<190> a_wi<189> a_wi<188> a_wi<187> a_wi<186> a_wi<185> a_wi<184> a_wi<183> a_wi<182> a_wi<181> a_wi<180> a_wi<179> a_wi<178> a_wi<177> a_wi<176> a_wi<175> a_wi<174> a_wi<173> a_wi<172> a_wi<171> a_wi<170> a_wi<169> a_wi<168> a_wi<167> a_wi<166> a_wi<165> a_wi<164> a_wi<163> a_wi<162> a_wi<161> a_wi<160> a_wi<159> a_wi<158> a_wi<157> a_wi<156> a_wi<155> a_wi<154> a_wi<153> a_wi<152> a_wi<151> a_wi<150> a_wi<149> a_wi<148> a_wi<147> a_wi<146> a_wi<145> a_wi<144> a_wi<143> a_wi<142> a_wi<141> a_wi<140> a_wi<139> a_wi<138> a_wi<137> a_wi<136> a_wi<135> a_wi<134> a_wi<133> a_wi<132> a_wi<131> a_wi<130> a_wi<129> a_wi<128> a_wi<127> a_wi<126> a_wi<125> a_wi<124> a_wi<123> a_wi<122> a_wi<121> a_wi<120> a_wi<119> a_wi<118> a_wi<117> a_wi<116> a_wi<115> a_wi<114> a_wi<113> a_wi<112> a_wi<111> a_wi<110> a_wi<109> a_wi<108> a_wi<107> a_wi<106> a_wi<105> a_wi<104> a_wi<103> a_wi<102> a_wi<101> a_wi<100> a_wi<99> a_wi<98> a_wi<97> a_wi<96> a_wi<95> a_wi<94> a_wi<93> a_wi<92> a_wi<91> a_wi<90> a_wi<89> a_wi<88> a_wi<87> a_wi<86> a_wi<85> a_wi<84> a_wi<83> a_wi<82> a_wi<81> a_wi<80> a_wi<79> a_wi<78> a_wi<77> a_wi<76> a_wi<75> a_wi<74> a_wi<73> a_wi<72> a_wi<71> a_wi<70> a_wi<69> a_wi<68> a_wi<67> a_wi<66> a_wi<65> a_wi<64> a_wi<63> a_wi<62> a_wi<61> a_wi<60> a_wi<59> a_wi<58> a_wi<57> a_wi<56> a_wi<55> a_wi<54> a_wi<53> a_wi<52> a_wi<51> a_wi<50> a_wi<49> a_wi<48> a_wi<47> a_wi<46> a_wi<45> a_wi<44> a_wi<43> a_wi<42> a_wi<41> a_wi<40> a_wi<39> a_wi<38> a_wi<37> a_wi<36> a_wi<35> a_wi<34> a_wi<33> a_wi<32> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_ROWDEC8 +XA_ROWREG a_aclk_n A_ADDR<9> A_ADDR<8> A_ADDR<7> A_ADDR<6> A_ADDR<5> A_ADDR<4> A_ADDR<3> A_ADDR<2> a_addr_row<7> a_addr_row<6> a_addr_row<5> a_addr_row<4> a_addr_row<3> a_addr_row<2> a_addr_row<1> a_addr_row<0> A_BIST_ADDR<9> A_BIST_ADDR<8> A_BIST_ADDR<7> A_BIST_ADDR<6> A_BIST_ADDR<5> A_BIST_ADDR<4> A_BIST_ADDR<3> A_BIST_ADDR<2> A_BIST_EN VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_ROWREG8 +XA_COLDEC a_aclk_n A_ADDR<1> A_ADDR<0> a_addr_col<1> a_addr_col<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> A_BIST_ADDR<1> A_BIST_ADDR<0> A_BIST_EN VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_COLDEC2 + + +XA_DLYH a_pulse a_pulse_h VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_DLY_pcell_2 +XA_DLYL a_pulse_x a_pulse_l VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_DLY_pcell_3 +XA_DLYMUX a_pulse_h A_DLY a_pulse_x VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_DLY_MUX + +XCOLCTRL<15> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<15> A_BIST_DIN<15> A_BIST_EN a_blc_r<31> a_blc_r<30> a_blc_r<29> a_blc_r<28> a_blt_r<31> a_blt_r<30> a_blt_r<29> a_blt_r<28> A_BM<15> a_dclk_n_r<7> a_dclk_n_r<8> a_dclk_p_r<7> a_dclk_p_r<8> A_DOUT<15> A_DIN<15> a_rclk_n_r<7> a_rclk_n_r<8> a_rclk_p_r<7> a_rclk_p_r<8> a_tieh<15> a_wclk_n_r<7> a_wclk_n_r<8> a_wclk_p_r<7> a_wclk_p_r<8> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_COLCTRL2 +XCOLCTRL<14> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<14> A_BIST_DIN<14> A_BIST_EN a_blc_r<27> a_blc_r<26> a_blc_r<25> a_blc_r<24> a_blt_r<27> a_blt_r<26> a_blt_r<25> a_blt_r<24> A_BM<14> a_dclk_n_r<6> a_dclk_n_r<7> a_dclk_p_r<6> a_dclk_p_r<7> A_DOUT<14> A_DIN<14> a_rclk_n_r<6> a_rclk_n_r<7> a_rclk_p_r<6> a_rclk_p_r<7> a_tieh<14> a_wclk_n_r<6> a_wclk_n_r<7> a_wclk_p_r<6> a_wclk_p_r<7> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_COLCTRL2 +XCOLCTRL<13> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<13> A_BIST_DIN<13> A_BIST_EN a_blc_r<23> a_blc_r<22> a_blc_r<21> a_blc_r<20> a_blt_r<23> a_blt_r<22> a_blt_r<21> a_blt_r<20> A_BM<13> a_dclk_n_r<5> a_dclk_n_r<6> a_dclk_p_r<5> a_dclk_p_r<6> A_DOUT<13> A_DIN<13> a_rclk_n_r<5> a_rclk_n_r<6> a_rclk_p_r<5> a_rclk_p_r<6> a_tieh<13> a_wclk_n_r<5> a_wclk_n_r<6> a_wclk_p_r<5> a_wclk_p_r<6> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_COLCTRL2 +XCOLCTRL<12> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<12> A_BIST_DIN<12> A_BIST_EN a_blc_r<19> a_blc_r<18> a_blc_r<17> a_blc_r<16> a_blt_r<19> a_blt_r<18> a_blt_r<17> a_blt_r<16> A_BM<12> a_dclk_n_r<4> a_dclk_n_r<5> a_dclk_p_r<4> a_dclk_p_r<5> A_DOUT<12> A_DIN<12> a_rclk_n_r<4> a_rclk_n_r<5> a_rclk_p_r<4> a_rclk_p_r<5> a_tieh<12> a_wclk_n_r<4> a_wclk_n_r<5> a_wclk_p_r<4> a_wclk_p_r<5> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_COLCTRL2 +XCOLCTRL<11> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<11> A_BIST_DIN<11> A_BIST_EN a_blc_r<15> a_blc_r<14> a_blc_r<13> a_blc_r<12> a_blt_r<15> a_blt_r<14> a_blt_r<13> a_blt_r<12> A_BM<11> a_dclk_n_r<3> a_dclk_n_r<4> a_dclk_p_r<3> a_dclk_p_r<4> A_DOUT<11> A_DIN<11> a_rclk_n_r<3> a_rclk_n_r<4> a_rclk_p_r<3> a_rclk_p_r<4> a_tieh<11> a_wclk_n_r<3> a_wclk_n_r<4> a_wclk_p_r<3> a_wclk_p_r<4> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_COLCTRL2 +XCOLCTRL<10> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<10> A_BIST_DIN<10> A_BIST_EN a_blc_r<11> a_blc_r<10> a_blc_r<9> a_blc_r<8> a_blt_r<11> a_blt_r<10> a_blt_r<9> a_blt_r<8> A_BM<10> a_dclk_n_r<2> a_dclk_n_r<3> a_dclk_p_r<2> a_dclk_p_r<3> A_DOUT<10> A_DIN<10> a_rclk_n_r<2> a_rclk_n_r<3> a_rclk_p_r<2> a_rclk_p_r<3> a_tieh<10> a_wclk_n_r<2> a_wclk_n_r<3> a_wclk_p_r<2> a_wclk_p_r<3> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_COLCTRL2 +XCOLCTRL<9> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<9> A_BIST_DIN<9> A_BIST_EN a_blc_r<7> a_blc_r<6> a_blc_r<5> a_blc_r<4> a_blt_r<7> a_blt_r<6> a_blt_r<5> a_blt_r<4> A_BM<9> a_dclk_n_r<1> a_dclk_n_r<2> a_dclk_p_r<1> a_dclk_p_r<2> A_DOUT<9> A_DIN<9> a_rclk_n_r<1> a_rclk_n_r<2> a_rclk_p_r<1> a_rclk_p_r<2> a_tieh<9> a_wclk_n_r<1> a_wclk_n_r<2> a_wclk_p_r<1> a_wclk_p_r<2> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_COLCTRL2 +XCOLCTRL<8> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<8> A_BIST_DIN<8> A_BIST_EN a_blc_r<3> a_blc_r<2> a_blc_r<1> a_blc_r<0> a_blt_r<3> a_blt_r<2> a_blt_r<1> a_blt_r<0> A_BM<8> a_dclk_n_r<0> a_dclk_n_r<1> a_dclk_p_r<0> a_dclk_p_r<1> A_DOUT<8> A_DIN<8> a_rclk_n_r<0> a_rclk_n_r<1> a_rclk_p_r<0> a_rclk_p_r<1> a_tieh<8> a_wclk_n_r<0> a_wclk_n_r<1> a_wclk_p_r<0> a_wclk_p_r<1> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_COLCTRL2 +XCOLCTRL<7> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<0> A_BIST_DIN<0> A_BIST_EN a_blc_l<31> a_blc_l<30> a_blc_l<29> a_blc_l<28> a_blt_l<31> a_blt_l<30> a_blt_l<29> a_blt_l<28> A_BM<0> a_dclk_n_l<7> a_dclk_n_l<8> a_dclk_p_l<7> a_dclk_p_l<8> A_DOUT<0> A_DIN<0> a_rclk_n_l<7> a_rclk_n_l<8> a_rclk_p_l<7> a_rclk_p_l<8> a_tieh<0> a_wclk_n_l<7> a_wclk_n_l<8> a_wclk_p_l<7> a_wclk_p_l<8> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_COLCTRL2 +XCOLCTRL<6> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<1> A_BIST_DIN<1> A_BIST_EN a_blc_l<27> a_blc_l<26> a_blc_l<25> a_blc_l<24> a_blt_l<27> a_blt_l<26> a_blt_l<25> a_blt_l<24> A_BM<1> a_dclk_n_l<6> a_dclk_n_l<7> a_dclk_p_l<6> a_dclk_p_l<7> A_DOUT<1> A_DIN<1> a_rclk_n_l<6> a_rclk_n_l<7> a_rclk_p_l<6> a_rclk_p_l<7> a_tieh<1> a_wclk_n_l<6> a_wclk_n_l<7> a_wclk_p_l<6> a_wclk_p_l<7> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_COLCTRL2 +XCOLCTRL<5> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<2> A_BIST_DIN<2> A_BIST_EN a_blc_l<23> a_blc_l<22> a_blc_l<21> a_blc_l<20> a_blt_l<23> a_blt_l<22> a_blt_l<21> a_blt_l<20> A_BM<2> a_dclk_n_l<5> a_dclk_n_l<6> a_dclk_p_l<5> a_dclk_p_l<6> A_DOUT<2> A_DIN<2> a_rclk_n_l<5> a_rclk_n_l<6> a_rclk_p_l<5> a_rclk_p_l<6> a_tieh<2> a_wclk_n_l<5> a_wclk_n_l<6> a_wclk_p_l<5> a_wclk_p_l<6> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_COLCTRL2 +XCOLCTRL<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<3> A_BIST_DIN<3> A_BIST_EN a_blc_l<19> a_blc_l<18> a_blc_l<17> a_blc_l<16> a_blt_l<19> a_blt_l<18> a_blt_l<17> a_blt_l<16> A_BM<3> a_dclk_n_l<4> a_dclk_n_l<5> a_dclk_p_l<4> a_dclk_p_l<5> A_DOUT<3> A_DIN<3> a_rclk_n_l<4> a_rclk_n_l<5> a_rclk_p_l<4> a_rclk_p_l<5> a_tieh<3> a_wclk_n_l<4> a_wclk_n_l<5> a_wclk_p_l<4> a_wclk_p_l<5> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_COLCTRL2 +XCOLCTRL<3> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<4> A_BIST_DIN<4> A_BIST_EN a_blc_l<15> a_blc_l<14> a_blc_l<13> a_blc_l<12> a_blt_l<15> a_blt_l<14> a_blt_l<13> a_blt_l<12> A_BM<4> a_dclk_n_l<3> a_dclk_n_l<4> a_dclk_p_l<3> a_dclk_p_l<4> A_DOUT<4> A_DIN<4> a_rclk_n_l<3> a_rclk_n_l<4> a_rclk_p_l<3> a_rclk_p_l<4> a_tieh<4> a_wclk_n_l<3> a_wclk_n_l<4> a_wclk_p_l<3> a_wclk_p_l<4> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_COLCTRL2 +XCOLCTRL<2> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<5> A_BIST_DIN<5> A_BIST_EN a_blc_l<11> a_blc_l<10> a_blc_l<9> a_blc_l<8> a_blt_l<11> a_blt_l<10> a_blt_l<9> a_blt_l<8> A_BM<5> a_dclk_n_l<2> a_dclk_n_l<3> a_dclk_p_l<2> a_dclk_p_l<3> A_DOUT<5> A_DIN<5> a_rclk_n_l<2> a_rclk_n_l<3> a_rclk_p_l<2> a_rclk_p_l<3> a_tieh<5> a_wclk_n_l<2> a_wclk_n_l<3> a_wclk_p_l<2> a_wclk_p_l<3> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_COLCTRL2 +XCOLCTRL<1> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<6> A_BIST_DIN<6> A_BIST_EN a_blc_l<7> a_blc_l<6> a_blc_l<5> a_blc_l<4> a_blt_l<7> a_blt_l<6> a_blt_l<5> a_blt_l<4> A_BM<6> a_dclk_n_l<1> a_dclk_n_l<2> a_dclk_p_l<1> a_dclk_p_l<2> A_DOUT<6> A_DIN<6> a_rclk_n_l<1> a_rclk_n_l<2> a_rclk_p_l<1> a_rclk_p_l<2> a_tieh<6> a_wclk_n_l<1> a_wclk_n_l<2> a_wclk_p_l<1> a_wclk_p_l<2> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_COLCTRL2 +XCOLCTRL<0> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<7> A_BIST_DIN<7> A_BIST_EN a_blc_l<3> a_blc_l<2> a_blc_l<1> a_blc_l<0> a_blt_l<3> a_blt_l<2> a_blt_l<1> a_blt_l<0> A_BM<7> a_dclk_n_l<0> a_dclk_n_l<1> a_dclk_p_l<0> a_dclk_p_l<1> A_DOUT<7> A_DIN<7> a_rclk_n_l<0> a_rclk_n_l<1> a_rclk_p_l<0> a_rclk_p_l<1> a_tieh<7> a_wclk_n_l<0> a_wclk_n_l<1> a_wclk_p_l<0> a_wclk_p_l<1> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_COLCTRL2 + + +XDRVFILL4<1> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_COLDRV13_FILL4 +XDRVFILL4<2> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_COLDRV13_FILL4 +XCOLFILL4<1> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_COLDRV13_FILL4C2 +XCOLFILL4<2> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_COLDRV13_FILL4C2 +XCOLFILL4<3> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_COLDRV13_FILL4C2 +XCOLFILL4<4> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_COLDRV13_FILL4C2 +XCOLFILL4<5> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_COLDRV13_FILL4C2 +XCOLFILL4<6> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_COLDRV13_FILL4C2 +.ENDS diff --git a/flow/platforms/ihp-sg13g2/cdl/RM_IHPSG13_1P_1024x8_c2_bm_bist.cdl b/flow/platforms/ihp-sg13g2/cdl/RM_IHPSG13_1P_1024x8_c2_bm_bist.cdl new file mode 100644 index 0000000000..97f559180a --- /dev/null +++ b/flow/platforms/ihp-sg13g2/cdl/RM_IHPSG13_1P_1024x8_c2_bm_bist.cdl @@ -0,0 +1,6375 @@ +* ------------------------------------------------------ +* +* Copyright 2024 IHP PDK Authors +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* https://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* +* Generated on Fri Jul 19 09:01:22 2024 +* +* ------------------------------------------------------ + +.SUBCKT RM_IHPSG13_1024x8_c2_1P_BITKIT_CORNER NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_CORNER VDD_CORE VSS +XI16 VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x8_c2_1P_BITKIT_CORNER +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_1P_BITKIT_EDGE_LR LWL NW PW VDD VSS +MN1 VSS LWL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN0 VSS net9 VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_LR A_WL<15> A_WL<14> A_WL<13> A_WL<12> ++ A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> ++ A_WL<2> A_WL<1> A_WL<0> VDD_CORE VSS +XI0<15> A_WL<15> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x8_c2_1P_BITKIT_EDGE_LR +XI0<14> A_WL<14> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x8_c2_1P_BITKIT_EDGE_LR +XI0<13> A_WL<13> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x8_c2_1P_BITKIT_EDGE_LR +XI0<12> A_WL<12> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x8_c2_1P_BITKIT_EDGE_LR +XI0<11> A_WL<11> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x8_c2_1P_BITKIT_EDGE_LR +XI0<10> A_WL<10> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x8_c2_1P_BITKIT_EDGE_LR +XI0<9> A_WL<9> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x8_c2_1P_BITKIT_EDGE_LR +XI0<8> A_WL<8> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x8_c2_1P_BITKIT_EDGE_LR +XI0<7> A_WL<7> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x8_c2_1P_BITKIT_EDGE_LR +XI0<6> A_WL<6> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x8_c2_1P_BITKIT_EDGE_LR +XI0<5> A_WL<5> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x8_c2_1P_BITKIT_EDGE_LR +XI0<4> A_WL<4> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x8_c2_1P_BITKIT_EDGE_LR +XI0<3> A_WL<3> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x8_c2_1P_BITKIT_EDGE_LR +XI0<2> A_WL<2> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x8_c2_1P_BITKIT_EDGE_LR +XI0<1> A_WL<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x8_c2_1P_BITKIT_EDGE_LR +XI0<0> A_WL<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x8_c2_1P_BITKIT_EDGE_LR +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_1P_BITKIT_CELL BLC_BOT BLC_TOP BLT_BOT BLT_TOP LWL NW PW ++ RWL VDD VSS +MN0 NC NT VSS PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN1 NT NC VSS PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN3 NC RWL BLC_TOP PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN2 BLT_BOT LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MP1 NT NC VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 NC NT VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +R1 BLC_BOT BLC_TOP lvsres w=2.6e-07 l=6e-07 +R0 BLT_BOT BLT_TOP lvsres w=2.6e-07 l=6e-07 +R2 RWL LWL lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_SRAM A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> ++ A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<15> ++ A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> ++ A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> ++ A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> ++ A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> VDD_CORE ++ VSS +XCELL<31> A_BLC_TOP<1> A_RBLC<15> A_BLT_TOP<1> A_RBLT<15> A_RWL<15> ++ VDD_CORE VSS A_XWL<15> VDD_CORE VSS / ++ RM_IHPSG13_1024x8_c2_1P_BITKIT_CELL +XCELL<30> A_RBLC<14> A_RBLC<15> A_RBLT<14> A_RBLT<15> A_RWL<14> VDD_CORE ++ VSS A_XWL<14> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_CELL +XCELL<29> A_RBLC<14> A_RBLC<13> A_RBLT<14> A_RBLT<13> A_RWL<13> VDD_CORE ++ VSS A_XWL<13> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_CELL +XCELL<28> A_RBLC<12> A_RBLC<13> A_RBLT<12> A_RBLT<13> A_RWL<12> VDD_CORE ++ VSS A_XWL<12> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_CELL +XCELL<27> A_RBLC<12> A_RBLC<11> A_RBLT<12> A_RBLT<11> A_RWL<11> VDD_CORE ++ VSS A_XWL<11> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_CELL +XCELL<26> A_RBLC<10> A_RBLC<11> A_RBLT<10> A_RBLT<11> A_RWL<10> VDD_CORE ++ VSS A_XWL<10> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_CELL +XCELL<25> A_RBLC<10> A_RBLC<9> A_RBLT<10> A_RBLT<9> A_RWL<9> VDD_CORE ++ VSS A_XWL<9> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_CELL +XCELL<24> A_RBLC<8> A_RBLC<9> A_RBLT<8> A_RBLT<9> A_RWL<8> VDD_CORE ++ VSS A_XWL<8> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_CELL +XCELL<23> A_RBLC<8> A_RBLC<7> A_RBLT<8> A_RBLT<7> A_RWL<7> VDD_CORE ++ VSS A_XWL<7> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_CELL +XCELL<22> A_RBLC<6> A_RBLC<7> A_RBLT<6> A_RBLT<7> A_RWL<6> VDD_CORE ++ VSS A_XWL<6> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_CELL +XCELL<21> A_RBLC<6> A_RBLC<5> A_RBLT<6> A_RBLT<5> A_RWL<5> VDD_CORE ++ VSS A_XWL<5> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_CELL +XCELL<20> A_RBLC<4> A_RBLC<5> A_RBLT<4> A_RBLT<5> A_RWL<4> VDD_CORE ++ VSS A_XWL<4> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_CELL +XCELL<19> A_RBLC<4> A_RBLC<3> A_RBLT<4> A_RBLT<3> A_RWL<3> VDD_CORE ++ VSS A_XWL<3> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_CELL +XCELL<18> A_RBLC<2> A_RBLC<3> A_RBLT<2> A_RBLT<3> A_RWL<2> VDD_CORE ++ VSS A_XWL<2> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_CELL +XCELL<17> A_RBLC<2> A_RBLC<1> A_RBLT<2> A_RBLT<1> A_RWL<1> VDD_CORE ++ VSS A_XWL<1> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_CELL +XCELL<16> A_BLC_BOT<1> A_RBLC<1> A_BLT_BOT<1> A_RBLT<1> A_RWL<0> VDD_CORE ++ VSS A_XWL<0> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_CELL +XCELL<15> A_BLC_TOP<0> A_LBLC<15> A_BLT_TOP<0> A_LBLT<15> A_LWL<15> ++ VDD_CORE VSS A_XWL<15> VDD_CORE VSS / ++ RM_IHPSG13_1024x8_c2_1P_BITKIT_CELL +XCELL<14> A_LBLC<14> A_LBLC<15> A_LBLT<14> A_LBLT<15> A_LWL<14> VDD_CORE ++ VSS A_XWL<14> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_CELL +XCELL<13> A_LBLC<14> A_LBLC<13> A_LBLT<14> A_LBLT<13> A_LWL<13> VDD_CORE ++ VSS A_XWL<13> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_CELL +XCELL<12> A_LBLC<12> A_LBLC<13> A_LBLT<12> A_LBLT<13> A_LWL<12> VDD_CORE ++ VSS A_XWL<12> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_CELL +XCELL<11> A_LBLC<12> A_LBLC<11> A_LBLT<12> A_LBLT<11> A_LWL<11> VDD_CORE ++ VSS A_XWL<11> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_CELL +XCELL<10> A_LBLC<10> A_LBLC<11> A_LBLT<10> A_LBLT<11> A_LWL<10> VDD_CORE ++ VSS A_XWL<10> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_CELL +XCELL<9> A_LBLC<10> A_LBLC<9> A_LBLT<10> A_LBLT<9> A_LWL<9> VDD_CORE ++ VSS A_XWL<9> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_CELL +XCELL<8> A_LBLC<8> A_LBLC<9> A_LBLT<8> A_LBLT<9> A_LWL<8> VDD_CORE ++ VSS A_XWL<8> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_CELL +XCELL<7> A_LBLC<8> A_LBLC<7> A_LBLT<8> A_LBLT<7> A_LWL<7> VDD_CORE ++ VSS A_XWL<7> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_CELL +XCELL<6> A_LBLC<6> A_LBLC<7> A_LBLT<6> A_LBLT<7> A_LWL<6> VDD_CORE ++ VSS A_XWL<6> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_CELL +XCELL<5> A_LBLC<6> A_LBLC<5> A_LBLT<6> A_LBLT<5> A_LWL<5> VDD_CORE ++ VSS A_XWL<5> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_CELL +XCELL<4> A_LBLC<4> A_LBLC<5> A_LBLT<4> A_LBLT<5> A_LWL<4> VDD_CORE ++ VSS A_XWL<4> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_CELL +XCELL<3> A_LBLC<4> A_LBLC<3> A_LBLT<4> A_LBLT<3> A_LWL<3> VDD_CORE ++ VSS A_XWL<3> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_CELL +XCELL<2> A_LBLC<2> A_LBLC<3> A_LBLT<2> A_LBLT<3> A_LWL<2> VDD_CORE ++ VSS A_XWL<2> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_CELL +XCELL<1> A_LBLC<2> A_LBLC<1> A_LBLT<2> A_LBLT<1> A_LWL<1> VDD_CORE ++ VSS A_XWL<1> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_CELL +XCELL<0> A_BLC_BOT<0> A_LBLC<1> A_BLT_BOT<0> A_LBLT<1> A_LWL<0> VDD_CORE ++ VSS A_XWL<0> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_CELL +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_1P_BITKIT_EDGE_TB BLC BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_TB A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ VDD_CORE VSS +XEDGE<1> A_BLC<1> A_BLT<1> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_1024x8_c2_1P_BITKIT_EDGE_TB +XEDGE<0> A_BLC<0> A_BLT<0> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_1024x8_c2_1P_BITKIT_EDGE_TB +.ENDS + +.SUBCKT RSC_IHPSG13_CBUFX4 A Z VDD VSS +MN0 net9 A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 Z net9 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MP0 net9 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP1 Z net9 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_1P_COLDRV13X4 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX4 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_1P_WLDRV16X4 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX4 +.ENDS +.SUBCKT RSC_IHPSG13_FILLCAP8 VDD VSS +MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=4.98u l=130.00n ng=6 nrd=0 ++ nrs=0 +MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=6.48u l=385.000n ng=4 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_LHPQX2 CP D Q VDD VSS +MN3 QIN CPN net14 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN2 net14 net10 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN5 net21 D VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN6 QIN CP net21 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net10 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 CPN CP VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 Q QIN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP2 QIN CP net16 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 CPN CP VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 Q QIN VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP3 net10 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net16 net10 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP6 QIN CPN net20 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP5 net20 D VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_NAND2X2 A B Z VDD VSS +MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z B net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net7 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX4 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX2 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_INVX2 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_NAND3X2 A B C Z VDD VSS +MP2 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z C VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN1 net12 B net16 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z C net12 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN2 net16 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_NOR3X2 A B C Z VDD VSS +MP0 net13 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z C net10 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP1 net10 B net13 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN1 Z B VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z C VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0 +MN2 Z A VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_FILLCAP4 VDD VSS +MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=2.49u l=130.00n ng=3 nrd=0 ++ nrs=0 +MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=3.24u l=385.000n ng=2 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_MET2RES A B +R0 B A lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_1P_DEC04 ADDR<3> ADDR<2> ADDR<1> ADDR<0> CS ECLK_H_BOT ++ ECLK_H_TOP ECLK_L_BOT ECLK_L_TOP WL<15> WL<14> WL<13> WL<12> WL<11> WL<10> ++ WL<9> WL<8> WL<7> WL<6> WL<5> WL<4> WL<3> WL<2> WL<1> WL<0> VDD VSS +XLATCH<3> CS ADDR<3> PADR<3> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<2> CS ADDR<2> PADR<2> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<1> CS ADDR<1> PADR<1> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<0> CS ADDR<0> PADR<0> VDD VSS / RSC_IHPSG13_LHPQX2 +XI0<3> PADR<1> PADR<0> sel01<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<2> PADR<1> NADR<0> sel01<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<1> NADR<1> PADR<0> sel01<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<0> NADR<1> NADR<0> sel01<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI4 ECLK_L_BOT EN VDD VSS / RSC_IHPSG13_CINVX4 +XI5 ECLK_H_BOT ECLK_L_BOT VDD VSS / RSC_IHPSG13_CINVX2 +XI3<3> PADR<3> NADR<3> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> PADR<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> PADR<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> PADR<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI1<3> PADR<2> PADR<3> CS sel23<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<2> PADR<3> CS sel23<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<2> NADR<3> CS sel23<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<2> NADR<3> CS sel23<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI2<15> sel23<3> sel01<3> EN WL<15> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<14> sel23<3> sel01<2> EN WL<14> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<13> sel23<3> sel01<1> EN WL<13> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<12> sel23<3> sel01<0> EN WL<12> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<11> sel23<2> sel01<3> EN WL<11> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<10> sel23<2> sel01<2> EN WL<10> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<9> sel23<2> sel01<1> EN WL<9> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<8> sel23<2> sel01<0> EN WL<8> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<7> sel23<1> sel01<3> EN WL<7> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<6> sel23<1> sel01<2> EN WL<6> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<5> sel23<1> sel01<1> EN WL<5> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<4> sel23<1> sel01<0> EN WL<4> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<3> sel23<0> sel01<3> EN WL<3> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<2> sel23<0> sel01<2> EN WL<2> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<1> sel23<0> sel01<1> EN WL<1> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<0> sel23<0> sel01<0> EN WL<0> VDD VSS / RSC_IHPSG13_NOR3X2 +XCAPS4 VDD VSS / RSC_IHPSG13_FILLCAP4 +XI11 ECLK_L_BOT ECLK_L_TOP / RSC_IHPSG13_MET2RES +XR0 ECLK_H_BOT ECLK_H_TOP / RSC_IHPSG13_MET2RES +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_1P_ROWDEC4 ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> ++ CS_I ECLK_I WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XSEL ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ECLK_H<1> ++ ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> ++ WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> ++ WL_O<0> VDD VSS / RM_IHPSG13_1024x8_c2_1P_DEC04 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX8 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=2.82u l=130.00n ng=4 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_DFNQMX2IX1 BE BI CN D QI QIN VDD VSS +MN15 net026 BI VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN14 MXI_OUT BE net026 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net025 D VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 MXI_OUT BEN net025 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN10 QI CNN net21 VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 nrd=0 nrs=0 +MN11 net21 QI_MS VSS VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN7 net30 QI_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN6 QIN_MS CNN net30 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 QI_MS QIN_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN12 CNN CN VSS VSS sg13_lv_nmos m=1 w=495.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN9 net37 MXI_OUT VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN8 QIN_MS CN net37 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 QI CN net25 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN4 net25 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 QIN QI VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN13 BEN BE VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP15 MXI_OUT BEN net027 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP14 net027 BI VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP1 MXI_OUT BE net024 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 net024 D VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP13 BEN BE VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP6 QI_MS QIN_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP3 QI CNN net27 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MP2 net27 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP10 net36 MXI_OUT VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP11 QIN_MS CNN net36 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net32 QI_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP5 QIN_MS CN net32 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 QIN QI VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP12 CNN CN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP9 QI CN net19 VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 nrd=0 nrs=0 +MP8 net19 QI_MS VDD VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_1P_ROWREG4 ACLK_N_I ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RSC_IHPSG13_CDLYX1 A Z VDD VSS +MN1 net010 net032 VSS VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 ++ nrd=0 nrs=0 +MN2 net032 A net014 VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 ++ nrs=0 +MN0 Z net032 net010 VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 ++ nrs=0 +MN3 net014 A VSS VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 ++ nrs=0 +MP1 Z net032 net07 VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 ++ nrs=0 +MP3 net011 A VDD VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 ++ nrs=0 +MP0 net07 net032 VDD VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 ++ nrd=0 nrs=0 +MP2 net032 A net011 VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CDLYX1_DUMMY A Z VDD VSS +MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=2.49u l=300.0n ng=3 nrd=0 ++ nrs=0 +MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=3.24u l=640.00n ng=2 nrd=0 ++ nrs=0 +R0 Z A lvsres w=2.6e-07 l=6e-07 +.ENDS + +.SUBCKT RSC_IHPSG13_MX2IX1 A0 A1 S ZN VDD VSS +MP4 SN S VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 nrs=0 +MP3 ZN SN net12 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 nrs=0 +MP2 net12 A1 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 ZN S net17 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 nrs=0 +MP0 net17 A0 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 SN S VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN3 net13 A1 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 ZN S net13 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net15 A0 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 ZN SN net15 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_1P_DLY_MUX A SEL Z VDD VSS +XI11 net4 Z VDD VSS / RSC_IHPSG13_CINVX2 +XI8 A D<3> SEL net4 VDD VSS / RSC_IHPSG13_MX2IX1 +XI20<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1 +.ENDS +.SUBCKT RSC_IHPSG13_DFNQX2 CN D Q VDD VSS +MN0 Q QIN_SL VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN10 QIN_SL CNN net21 VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN11 net21 QI_MS VSS VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN7 net30 QI_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN6 QIN_MS CNN net30 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 QI_MS QIN_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN12 CNN CN VSS VSS sg13_lv_nmos m=1 w=495.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN9 net37 D VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN8 QIN_MS CN net37 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 QIN_SL CN net25 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net25 QI_SL VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN2 QI_SL QIN_SL VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP0 Q QIN_SL VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP6 QI_MS QIN_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP3 QIN_SL CNN net27 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 net27 QI_SL VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP10 net36 D VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP11 QIN_MS CNN net36 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net32 QI_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP5 QIN_MS CN net32 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 QI_SL QIN_SL VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP12 CNN CN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP9 QIN_SL CN net19 VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP8 net19 QI_MS VDD VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CNAND2X2 A B Z VDD VSS +MN0 Z B net6 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net6 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CGATEPX4 CP E Q VDD VSS +MN1 net08 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 net019 net08 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN3 QIN CP net019 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN6 Q net015 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 ++ nrs=0 +MN5 net015 net08 net018 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN8 QIN CPN net023 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN7 net023 E VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net018 CP VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 CPN CP VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP3 net08 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 QIN CPN net017 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net017 net08 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP0 CPN CP VDD VDD sg13_lv_pmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP8 QIN CP net024 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 net024 E VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net015 CP VDD VDD sg13_lv_pmos m=1 w=1.27u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP6 Q net015 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 ++ nrs=0 +MP5 net015 net08 VDD VDD sg13_lv_pmos m=1 w=1.27u l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CBUFX8 A Z VDD VSS +MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0 +MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=2.82u l=130.00n ng=4 nrd=0 nrs=0 +MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CDLYX2 A Z VDD VSS +MN2 net4 A net9 VSS sg13_lv_nmos m=1 w=320.00n l=200.0n ng=1 nrd=0 nrs=0 +MN0 Z net4 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net9 A VSS VSS sg13_lv_nmos m=1 w=320.00n l=200.0n ng=1 nrd=0 nrs=0 +MP2 net4 A net10 VDD sg13_lv_pmos m=1 w=1.2u l=200.0n ng=1 nrd=0 nrs=0 +MP1 net10 A VDD VDD sg13_lv_pmos m=1 w=1.2u l=200.0n ng=1 nrd=0 nrs=0 +MP0 Z net4 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_MX2X2 A0 A1 S Z VDD VSS +MP6 Z net010 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 SN S VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 nrs=0 +MP3 net010 SN net12 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 net12 A1 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net010 S net17 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 net17 A0 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN6 Z net010 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 SN S VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 nrs=0 +MN3 net13 A1 VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 net010 S net13 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net15 A0 VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 net010 SN net15 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_AND2X2 A B Z VDD VSS +MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_TIEL Z VDD VSS +MN0 Z net2 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 net2 net2 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_XOR2X2 A B Z VDD VSS +MP8 net012 B net7 VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 net011 net3 net012 VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP6 Z net012 VDD VDD sg13_lv_pmos m=1 w=1.535u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 net7 A VDD VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net011 net7 VDD VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP5 net3 B VDD VDD sg13_lv_pmos m=1 w=580.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN7 net012 B net011 VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN6 net7 net3 net012 VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 Z net012 VSS VSS sg13_lv_nmos m=1 w=775.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 net7 A VSS VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net3 B VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 net011 net7 VSS VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_OA12X1 A B C Z VDD VSS +MN2 net7 C VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 Z net17 VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net17 B net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN0 net17 A net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 net24 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP3 Z net17 VDD VDD sg13_lv_pmos m=1 w=905.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net17 B net24 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP2 net17 C VDD VDD sg13_lv_pmos m=1 w=905.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_1P_CTRL ACLK_N BIST_CK_I BIST_CS_I BIST_EN BIST_RE_I ++ BIST_WE_I B_TIEL_O CK_I CS_I DCLK ECLK PULSE_H PULSE_L PULSE_O RCLK RE_I ++ ROW_CS WCLK WE_I VDD VSS +XI17 ck_regs we col_we VDD VSS / RSC_IHPSG13_DFNQX2 +XI16 ck_regs re col_re VDD VSS / RSC_IHPSG13_DFNQX2 +XI18 ck_regs cs net7 VDD VSS / RSC_IHPSG13_DFNQX2 +XI71 ACLK_N net012 PULSE_O VDD VSS / RSC_IHPSG13_DFNQX2 +XI77 col_we net9 net016 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI76 col_re net9 net018 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI15 ck_dly WEorREandCS aclk VDD VSS / RSC_IHPSG13_CGATEPX4 +XI14 ck WEandCS DCLK VDD VSS / RSC_IHPSG13_CGATEPX4 +XI60 net7 ROW_CS VDD VSS / RSC_IHPSG13_CBUFX8 +XI73 PULSE_O net012 VDD VSS / RSC_IHPSG13_CINVX2 +XI8 net9 net8 VDD VSS / RSC_IHPSG13_CINVX2 +XI64 ck ck_dly VDD VSS / RSC_IHPSG13_CDLYX2 +XI86 CS_I BIST_CS_I BIST_EN cs VDD VSS / RSC_IHPSG13_MX2X2 +XI87 CK_I BIST_CK_I BIST_EN ck VDD VSS / RSC_IHPSG13_MX2X2 +XI85 WE_I BIST_WE_I BIST_EN we VDD VSS / RSC_IHPSG13_MX2X2 +XI84 RE_I BIST_RE_I BIST_EN re VDD VSS / RSC_IHPSG13_MX2X2 +XI22 we cs WEandCS VDD VSS / RSC_IHPSG13_AND2X2 +XBM_TIEL B_TIEL_O VDD VSS / RSC_IHPSG13_TIEL +XI48 ck_dly ck_regs VDD VSS / RSC_IHPSG13_CINVX4 +XI81 net016 WCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI80 net018 RCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI78 net8 net020 VDD VSS / RSC_IHPSG13_CINVX4 +XI6 PULSE_L PULSE_H net9 VDD VSS / RSC_IHPSG13_XOR2X2 +XI79 net020 ECLK VDD VSS / RSC_IHPSG13_CINVX8 +XI63 aclk ACLK_N VDD VSS / RSC_IHPSG13_CINVX8 +XI21 re we cs WEorREandCS VDD VSS / RSC_IHPSG13_OA12X1 +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_1P_COLDEC2 ACLK_N ADDR<1> ADDR<0> ADDR_COL<1> ADDR_COL<0> ++ ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ADDR_DEC<2> ++ ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI14<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net6<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net6<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI1<3> PADR<1> PADR<0> addr_n<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<2> PADR<1> NADR<0> addr_n<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<1> NADR<1> PADR<0> addr_n<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<0> NADR<1> NADR<0> addr_n<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI16<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI17<3> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_TIEL +XI17<2> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_TIEL +XI17<1> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_TIEL +XI17<0> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RSC_IHPSG13_NOR2X2 A B Z VDD VSS +MP1 Z B net9 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 net9 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z B VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 Z A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX4_WN A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_1P_BLDRV BLC BLC_SEL BLT BLT_SEL PRE_N SEL_P WR_ONE WR_ZERO ++ VDD VSS +XCDEC SEL_P WR_ZERO BLC_PMOS_DRIVE VDD VSS / RSC_IHPSG13_NAND2X2 +XTDEC SEL_P WR_ONE BLT_PMOS_DRIVE VDD VSS / RSC_IHPSG13_NAND2X2 +MTWN BLT BLT_NMOS_DRIVE VSS VSS sg13_lv_nmos m=1 w=4.82u l=130.00n ++ ng=2 nrd=0 nrs=0 +MCWN BLC BLC_NMOS_DRIVE VSS VSS sg13_lv_nmos m=1 w=4.82u l=130.00n ++ ng=2 nrd=0 nrs=0 +MCWP BLC BLC_PMOS_DRIVE VDD VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 ++ nrd=0 nrs=0 +MTWP BLT BLT_PMOS_DRIVE VDD VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 ++ nrd=0 nrs=0 +MTSP BLT_SEL SEL_N BLT VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 nrd=0 ++ nrs=0 +MTPR BLT PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ng=2 nrd=0 ++ nrs=0 +MCSP BLC_SEL SEL_N BLC VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 nrd=0 ++ nrs=0 +MCPR BLC PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ng=2 nrd=0 ++ nrs=0 +XI86 SEL_P SEL_N VDD VSS / RSC_IHPSG13_INVX2 +XTINV BLC_PMOS_DRIVE BLT_NMOS_DRIVE VDD VSS / RSC_IHPSG13_INVX2 +XCINV BLT_PMOS_DRIVE BLC_NMOS_DRIVE VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RSC_IHPSG13_TIEH Z VDD VSS +MN0 net2 net2 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 Z net2 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_MET3RES A B +R0 B A lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RSC_IHPSG13_DFPQD_MSAFFX2 CP DN DP QN QP VDD VSS +MN12 SN RN DIFFP VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN13 TAIL CP VSS VSS sg13_lv_nmos m=1 w=2.4u l=130.00n ng=2 nrd=0 nrs=0 +MN9 DIFFP DP TAIL VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN10 DIFFN DN TAIL VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN11 RN SN DIFFN VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN19 net33 SN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN20 QN QP net37 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN18 net37 RN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN17 QP QN net33 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP15 SN RN VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP16 RN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP14 DIFFP CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP12 RN SN VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP13 DIFFN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP11 SN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP19 QN QP VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +MP20 QP SN VDD VDD sg13_lv_pmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP18 QN RN VDD VDD sg13_lv_pmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP17 QP QN VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CBUFX2 A Z VDD VSS +MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=540.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=1.1u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_INVX4 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=1.96u l=130.00n ng=2 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_1P_COLCTRL2 A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<3> A_BLC<2> A_BLC<1> ++ A_BLC<0> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_I80 A_WCLK_B_R A_RCLK_B_R net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I44 A_WCLK_B_R A_BM_N A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_ADDR_DEC<2> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_ADDR_DEC<1> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<0> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_R A_RCLK_B_L / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_R A_RCLK_L / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_R A_WCLK_B_L / RSC_IHPSG13_MET3RES +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_I78 A_RCLK_B_R A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_R VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_R A_RCLK_B_R VDD VSS / RSC_IHPSG13_CINVX2 +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_1P_COLDRV13_FILL4 VDD VSS +XI0<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_1P_COLDRV13_FILL4C2 VDD VSS +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_1024x8_c2_1P_COLDEC4 ACLK_N ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<3> BIST_ADDR<2> ++ BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI15 ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI14 addr_int ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int net7<0> VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net7<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net7<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net7<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RSC_IHPSG13_AND2X4 A B Z VDD VSS +MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.96u l=130.00n ng=2 nrd=0 nrs=0 +MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_1P_COLCTRL4 A_ADDR_COL A_ADDR_DEC<7> A_ADDR_DEC<6> ++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<15> A_BLC<14> ++ A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> ++ A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<15> A_BLT<14> ++ A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L ++ A_DCLK_B_R A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L ++ A_RCLK_R A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_I80 A_WCLK_B_L A_RCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DO_WRITE_P A_DI_N A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4 +XA_CAPS<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_N0 A_P0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL A_N0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_I81<1> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_BLTMUX<15> A_BLC<15> A_BLC_SEL A_BLT<15> A_BLT_SEL A_PRE_N A_SEL_P<15> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV +XA_BLTMUX<14> A_BLC<14> A_BLC_SEL A_BLT<14> A_BLT_SEL A_PRE_N A_SEL_P<14> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV +XA_BLTMUX<13> A_BLC<13> A_BLC_SEL A_BLT<13> A_BLT_SEL A_PRE_N A_SEL_P<13> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV +XA_BLTMUX<12> A_BLC<12> A_BLC_SEL A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<12> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV +XA_BLTMUX<11> A_BLC<11> A_BLC_SEL A_BLT<11> A_BLT_SEL A_PRE_N A_SEL_P<11> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV +XA_BLTMUX<10> A_BLC<10> A_BLC_SEL A_BLT<10> A_BLT_SEL A_PRE_N A_SEL_P<10> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV +XA_BLTMUX<9> A_BLC<9> A_BLC_SEL A_BLT<9> A_BLT_SEL A_PRE_N A_SEL_P<9> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV +XA_BLTMUX<8> A_BLC<8> A_BLC_SEL A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<8> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV +XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_SEL_P<7> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV +XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_SEL_P<6> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV +XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_SEL_P<5> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV +XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<4> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_SEL_P<3> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_SEL_P<2> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_SEL_P<1> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<0> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net24 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_DEC3INV<15> net23<0> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<1> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<2> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<3> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<4> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<5> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<6> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<7> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<8> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<9> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<10> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<11> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<12> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<13> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<14> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<15> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I70<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_DEC3<15> A_P0 A_ADDR_DEC<7> net23<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<14> A_P0 A_ADDR_DEC<6> net23<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<13> A_P0 A_ADDR_DEC<5> net23<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<12> A_P0 A_ADDR_DEC<4> net23<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<11> A_P0 A_ADDR_DEC<3> net23<4> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<10> A_P0 A_ADDR_DEC<2> net23<5> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<9> A_P0 A_ADDR_DEC<1> net23<6> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<8> A_P0 A_ADDR_DEC<0> net23<7> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<7> A_N0 A_ADDR_DEC<7> net23<8> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<6> A_N0 A_ADDR_DEC<6> net23<9> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<5> A_N0 A_ADDR_DEC<5> net23<10> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<4> A_N0 A_ADDR_DEC<4> net23<11> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<3> A_N0 A_ADDR_DEC<3> net23<12> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<2> A_N0 A_ADDR_DEC<2> net23<13> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<1> A_N0 A_ADDR_DEC<1> net23<14> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<0> A_N0 A_ADDR_DEC<0> net23<15> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS + + +.SUBCKT RM_IHPSG13_1024x8_c2_1P_COLDEC3 ACLK_N ADDR<2> ADDR<1> ADDR<0> ADDR_COL<1> ++ ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ++ ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> ++ BIST_EN_I VDD VSS +XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net6<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net6<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net6<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_1P_COLCTRL3 A_ADDR_DEC<7> A_ADDR_DEC<6> A_ADDR_DEC<5> ++ A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> A_ADDR_DEC<0> ++ A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> ++ A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> ++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R A_DCLK_L ++ A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R A_TIEH_O ++ A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_R A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_I70<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I44 A_BM_N A_WCLK_B_R A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_ADDR_DEC<7> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV +XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_ADDR_DEC<6> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV +XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_ADDR_DEC<5> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV +XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_ADDR_DEC<4> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_ADDR_DEC<2> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_ADDR_DEC<1> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<0> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I80 A_WCLK_B_R A_RCLK_B_R net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_1024x8_c2_2P_BITKIT_16x2_CORNER VDD_CORE VSS +XI16 VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x8_c2_1P_BITKIT_CORNER +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_2P_BITKIT_EDGE_LR A_WL B_WL NW PW VDD VSS +MN1 VSS A_WL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN0 VSS B_WL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_2P_BITKIT_16x2_EDGE_LR A_WL<15> A_WL<14> A_WL<13> A_WL<12> ++ A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> ++ A_WL<2> A_WL<1> A_WL<0> B_WL<15> B_WL<14> B_WL<13> B_WL<12> B_WL<11> ++ B_WL<10> B_WL<9> B_WL<8> B_WL<7> B_WL<6> B_WL<5> B_WL<4> B_WL<3> B_WL<2> ++ B_WL<1> B_WL<0> VDD_CORE VSS +XI0<15> A_WL<15> B_WL<15> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_1024x8_c2_2P_BITKIT_EDGE_LR +XI0<14> A_WL<14> B_WL<14> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_1024x8_c2_2P_BITKIT_EDGE_LR +XI0<13> A_WL<13> B_WL<13> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_1024x8_c2_2P_BITKIT_EDGE_LR +XI0<12> A_WL<12> B_WL<12> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_1024x8_c2_2P_BITKIT_EDGE_LR +XI0<11> A_WL<11> B_WL<11> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_1024x8_c2_2P_BITKIT_EDGE_LR +XI0<10> A_WL<10> B_WL<10> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_1024x8_c2_2P_BITKIT_EDGE_LR +XI0<9> A_WL<9> B_WL<9> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x8_c2_2P_BITKIT_EDGE_LR +XI0<8> A_WL<8> B_WL<8> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x8_c2_2P_BITKIT_EDGE_LR +XI0<7> A_WL<7> B_WL<7> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x8_c2_2P_BITKIT_EDGE_LR +XI0<6> A_WL<6> B_WL<6> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x8_c2_2P_BITKIT_EDGE_LR +XI0<5> A_WL<5> B_WL<5> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x8_c2_2P_BITKIT_EDGE_LR +XI0<4> A_WL<4> B_WL<4> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x8_c2_2P_BITKIT_EDGE_LR +XI0<3> A_WL<3> B_WL<3> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x8_c2_2P_BITKIT_EDGE_LR +XI0<2> A_WL<2> B_WL<2> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x8_c2_2P_BITKIT_EDGE_LR +XI0<1> A_WL<1> B_WL<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x8_c2_2P_BITKIT_EDGE_LR +XI0<0> A_WL<0> B_WL<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x8_c2_2P_BITKIT_EDGE_LR +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_2P_BITKIT_CELL A_BLC_BOT A_BLC_TOP A_BLT_BOT A_BLT_TOP ++ A_LWL A_RWL B_BLC_BOT B_BLC_TOP B_BLT_BOT B_BLT_TOP B_LWL B_RWL NW PW VDD VSS +MN5 NC B_RWL B_BLC_BOT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN4 B_BLT_BOT B_LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN0 NC NT VSS PW sg13_lv_nmos m=1 w=600.0n l=130.00n ng=2 nrd=0 nrs=0 +MN1 NT NC VSS PW sg13_lv_nmos m=1 w=600.0n l=130.00n ng=2 nrd=0 nrs=0 +MN3 NC A_RWL A_BLC_TOP PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN2 A_BLT_TOP A_LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MP1 NT NC VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 NC NT VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +R5 B_RWL B_LWL lvsres w=2.6e-07 l=6e-07 +R4 B_BLC_BOT B_BLC_TOP lvsres w=2.6e-07 l=6e-07 +R3 B_BLT_BOT B_BLT_TOP lvsres w=2.6e-07 l=6e-07 +R1 A_BLC_BOT A_BLC_TOP lvsres w=2.6e-07 l=6e-07 +R0 A_BLT_BOT A_BLT_TOP lvsres w=2.6e-07 l=6e-07 +R2 A_RWL A_LWL lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_2P_BITKIT_16x2_SRAM A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> ++ A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<15> ++ A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> ++ A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> ++ A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> ++ A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> B_BLC_BOT<1> ++ B_BLC_BOT<0> B_BLC_TOP<1> B_BLC_TOP<0> B_BLT_BOT<1> B_BLT_BOT<0> ++ B_BLT_TOP<1> B_BLT_TOP<0> B_LWL<15> B_LWL<14> B_LWL<13> B_LWL<12> B_LWL<11> ++ B_LWL<10> B_LWL<9> B_LWL<8> B_LWL<7> B_LWL<6> B_LWL<5> B_LWL<4> B_LWL<3> ++ B_LWL<2> B_LWL<1> B_LWL<0> B_RWL<15> B_RWL<14> B_RWL<13> B_RWL<12> B_RWL<11> ++ B_RWL<10> B_RWL<9> B_RWL<8> B_RWL<7> B_RWL<6> B_RWL<5> B_RWL<4> B_RWL<3> ++ B_RWL<2> B_RWL<1> B_RWL<0> VDD_CORE VSS +XCELL<31> A_BLC_TOP<1> A_RBLC<15> A_BLT_TOP<1> A_RBLT<15> A_XWL<15> A_RWL<15> ++ B_BLC_TOP<1> B_RBLC<15> B_BLT_TOP<1> B_RBLT<15> B_XWL<15> B_RWL<15> ++ VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x8_c2_2P_BITKIT_CELL +XCELL<30> A_RBLC<14> A_RBLC<15> A_RBLT<14> A_RBLT<15> A_XWL<14> A_RWL<14> ++ B_RBLC<14> B_RBLC<15> B_RBLT<14> B_RBLT<15> B_XWL<14> B_RWL<14> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_CELL +XCELL<29> A_RBLC<14> A_RBLC<13> A_RBLT<14> A_RBLT<13> A_XWL<13> A_RWL<13> ++ B_RBLC<14> B_RBLC<13> B_RBLT<14> B_RBLT<13> B_XWL<13> B_RWL<13> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_CELL +XCELL<28> A_RBLC<12> A_RBLC<13> A_RBLT<12> A_RBLT<13> A_XWL<12> A_RWL<12> ++ B_RBLC<12> B_RBLC<13> B_RBLT<12> B_RBLT<13> B_XWL<12> B_RWL<12> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_CELL +XCELL<27> A_RBLC<12> A_RBLC<11> A_RBLT<12> A_RBLT<11> A_XWL<11> A_RWL<11> ++ B_RBLC<12> B_RBLC<11> B_RBLT<12> B_RBLT<11> B_XWL<11> B_RWL<11> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_CELL +XCELL<26> A_RBLC<10> A_RBLC<11> A_RBLT<10> A_RBLT<11> A_XWL<10> A_RWL<10> ++ B_RBLC<10> B_RBLC<11> B_RBLT<10> B_RBLT<11> B_XWL<10> B_RWL<10> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_CELL +XCELL<25> A_RBLC<10> A_RBLC<9> A_RBLT<10> A_RBLT<9> A_XWL<9> A_RWL<9> ++ B_RBLC<10> B_RBLC<9> B_RBLT<10> B_RBLT<9> B_XWL<9> B_RWL<9> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_CELL +XCELL<24> A_RBLC<8> A_RBLC<9> A_RBLT<8> A_RBLT<9> A_XWL<8> A_RWL<8> B_RBLC<8> ++ B_RBLC<9> B_RBLT<8> B_RBLT<9> B_XWL<8> B_RWL<8> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_CELL +XCELL<23> A_RBLC<8> A_RBLC<7> A_RBLT<8> A_RBLT<7> A_XWL<7> A_RWL<7> B_RBLC<8> ++ B_RBLC<7> B_RBLT<8> B_RBLT<7> B_XWL<7> B_RWL<7> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_CELL +XCELL<22> A_RBLC<6> A_RBLC<7> A_RBLT<6> A_RBLT<7> A_XWL<6> A_RWL<6> B_RBLC<6> ++ B_RBLC<7> B_RBLT<6> B_RBLT<7> B_XWL<6> B_RWL<6> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_CELL +XCELL<21> A_RBLC<6> A_RBLC<5> A_RBLT<6> A_RBLT<5> A_XWL<5> A_RWL<5> B_RBLC<6> ++ B_RBLC<5> B_RBLT<6> B_RBLT<5> B_XWL<5> B_RWL<5> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_CELL +XCELL<20> A_RBLC<4> A_RBLC<5> A_RBLT<4> A_RBLT<5> A_XWL<4> A_RWL<4> B_RBLC<4> ++ B_RBLC<5> B_RBLT<4> B_RBLT<5> B_XWL<4> B_RWL<4> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_CELL +XCELL<19> A_RBLC<4> A_RBLC<3> A_RBLT<4> A_RBLT<3> A_XWL<3> A_RWL<3> B_RBLC<4> ++ B_RBLC<3> B_RBLT<4> B_RBLT<3> B_XWL<3> B_RWL<3> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_CELL +XCELL<18> A_RBLC<2> A_RBLC<3> A_RBLT<2> A_RBLT<3> A_XWL<2> A_RWL<2> B_RBLC<2> ++ B_RBLC<3> B_RBLT<2> B_RBLT<3> B_XWL<2> B_RWL<2> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_CELL +XCELL<17> A_RBLC<2> A_RBLC<1> A_RBLT<2> A_RBLT<1> A_XWL<1> A_RWL<1> B_RBLC<2> ++ B_RBLC<1> B_RBLT<2> B_RBLT<1> B_XWL<1> B_RWL<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_CELL +XCELL<16> A_BLC_BOT<1> A_RBLC<1> A_BLT_BOT<1> A_RBLT<1> A_XWL<0> A_RWL<0> ++ B_BLC_BOT<1> B_RBLC<1> B_BLT_BOT<1> B_RBLT<1> B_XWL<0> B_RWL<0> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_CELL +XCELL<15> A_BLC_TOP<0> A_LBLC<15> A_BLT_TOP<0> A_LBLT<15> A_LWL<15> A_XWL<15> ++ B_BLC_TOP<0> B_LBLC<15> B_BLT_TOP<0> B_LBLT<15> B_LWL<15> B_XWL<15> ++ VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x8_c2_2P_BITKIT_CELL +XCELL<14> A_LBLC<14> A_LBLC<15> A_LBLT<14> A_LBLT<15> A_LWL<14> A_XWL<14> ++ B_LBLC<14> B_LBLC<15> B_LBLT<14> B_LBLT<15> B_LWL<14> B_XWL<14> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_CELL +XCELL<13> A_LBLC<14> A_LBLC<13> A_LBLT<14> A_LBLT<13> A_LWL<13> A_XWL<13> ++ B_LBLC<14> B_LBLC<13> B_LBLT<14> B_LBLT<13> B_LWL<13> B_XWL<13> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_CELL +XCELL<12> A_LBLC<12> A_LBLC<13> A_LBLT<12> A_LBLT<13> A_LWL<12> A_XWL<12> ++ B_LBLC<12> B_LBLC<13> B_LBLT<12> B_LBLT<13> B_LWL<12> B_XWL<12> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_CELL +XCELL<11> A_LBLC<12> A_LBLC<11> A_LBLT<12> A_LBLT<11> A_LWL<11> A_XWL<11> ++ B_LBLC<12> B_LBLC<11> B_LBLT<12> B_LBLT<11> B_LWL<11> B_XWL<11> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_CELL +XCELL<10> A_LBLC<10> A_LBLC<11> A_LBLT<10> A_LBLT<11> A_LWL<10> A_XWL<10> ++ B_LBLC<10> B_LBLC<11> B_LBLT<10> B_LBLT<11> B_LWL<10> B_XWL<10> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_CELL +XCELL<9> A_LBLC<10> A_LBLC<9> A_LBLT<10> A_LBLT<9> A_LWL<9> A_XWL<9> ++ B_LBLC<10> B_LBLC<9> B_LBLT<10> B_LBLT<9> B_LWL<9> B_XWL<9> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_CELL +XCELL<8> A_LBLC<8> A_LBLC<9> A_LBLT<8> A_LBLT<9> A_LWL<8> A_XWL<8> B_LBLC<8> ++ B_LBLC<9> B_LBLT<8> B_LBLT<9> B_LWL<8> B_XWL<8> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_CELL +XCELL<7> A_LBLC<8> A_LBLC<7> A_LBLT<8> A_LBLT<7> A_LWL<7> A_XWL<7> B_LBLC<8> ++ B_LBLC<7> B_LBLT<8> B_LBLT<7> B_LWL<7> B_XWL<7> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_CELL +XCELL<6> A_LBLC<6> A_LBLC<7> A_LBLT<6> A_LBLT<7> A_LWL<6> A_XWL<6> B_LBLC<6> ++ B_LBLC<7> B_LBLT<6> B_LBLT<7> B_LWL<6> B_XWL<6> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_CELL +XCELL<5> A_LBLC<6> A_LBLC<5> A_LBLT<6> A_LBLT<5> A_LWL<5> A_XWL<5> B_LBLC<6> ++ B_LBLC<5> B_LBLT<6> B_LBLT<5> B_LWL<5> B_XWL<5> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_CELL +XCELL<4> A_LBLC<4> A_LBLC<5> A_LBLT<4> A_LBLT<5> A_LWL<4> A_XWL<4> B_LBLC<4> ++ B_LBLC<5> B_LBLT<4> B_LBLT<5> B_LWL<4> B_XWL<4> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_CELL +XCELL<3> A_LBLC<4> A_LBLC<3> A_LBLT<4> A_LBLT<3> A_LWL<3> A_XWL<3> B_LBLC<4> ++ B_LBLC<3> B_LBLT<4> B_LBLT<3> B_LWL<3> B_XWL<3> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_CELL +XCELL<2> A_LBLC<2> A_LBLC<3> A_LBLT<2> A_LBLT<3> A_LWL<2> A_XWL<2> B_LBLC<2> ++ B_LBLC<3> B_LBLT<2> B_LBLT<3> B_LWL<2> B_XWL<2> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_CELL +XCELL<1> A_LBLC<2> A_LBLC<1> A_LBLT<2> A_LBLT<1> A_LWL<1> A_XWL<1> B_LBLC<2> ++ B_LBLC<1> B_LBLT<2> B_LBLT<1> B_LWL<1> B_XWL<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_CELL +XCELL<0> A_BLC_BOT<0> A_LBLC<1> A_BLT_BOT<0> A_LBLT<1> A_LWL<0> A_XWL<0> ++ B_BLC_BOT<0> B_LBLC<1> B_BLT_BOT<0> B_LBLT<1> B_LWL<0> B_XWL<0> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_CELL +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_2P_BITKIT_EDGE_TB A_BLC A_BLT B_BLC B_BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_2P_BITKIT_16x2_EDGE_TB A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ B_BLC<1> B_BLC<0> B_BLT<1> B_BLT<0> VDD_CORE VSS +XEDGE<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_EDGE_TB +XEDGE<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_EDGE_TB +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_2P_BITKIT_TAP A_BLC A_BLT B_BLC B_BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_2P_BITKIT_16x2_TAP A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ B_BLC<1> B_BLC<0> B_BLT<1> B_BLT<0> VDD_CORE VSS +XIEDGEBP_COL1<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_EDGE_TB +XIEDGEBP_COL1<0> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_EDGE_TB +XIEDGEBP_COL2<1> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_EDGE_TB +XIEDGEBP_COL2<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_EDGE_TB +XITAP<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_TAP +XITAP<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_TAP +.ENDS + + +.SUBCKT RM_IHPSG13_1024x8_c2_1P_BITKIT_TAP_LR NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_2P_BITKIT_16x2_TAP_LR VDD_CORE VSS +XCORNER<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x8_c2_1P_BITKIT_CORNER +XCORNER<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x8_c2_1P_BITKIT_CORNER +XTAP_BORDER VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x8_c2_1P_BITKIT_TAP_LR +.ENDS + +.SUBCKT RSC_IHPSG13_CBUFX12 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=4.23u l=130.00n ng=6 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=9.72u l=130.00n ng=6 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_2P_COLDRV13X12 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX12 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=9.72u l=130.00n ng=6 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_2P_WLDRV16X12 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX12 +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_2P_DEC04 ADDR<3> ADDR<2> ADDR<1> ADDR<0> CS ECLK_H_BOT ++ ECLK_H_TOP ECLK_L_BOT ECLK_L_TOP WL<15> WL<14> WL<13> WL<12> WL<11> WL<10> ++ WL<9> WL<8> WL<7> WL<6> WL<5> WL<4> WL<3> WL<2> WL<1> WL<0> VDD VSS +XI0<3> PADR<1> PADR<0> sel01<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<2> PADR<1> NADR<0> sel01<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<1> NADR<1> PADR<0> sel01<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<0> NADR<1> NADR<0> sel01<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI4 ECLK_L_BOT EN VDD VSS / RSC_IHPSG13_CINVX4 +XI5 ECLK_H_BOT ECLK_L_BOT VDD VSS / RSC_IHPSG13_CINVX2 +XI3<3> PADR<3> NADR<3> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> PADR<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> PADR<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> PADR<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XR0 ECLK_H_BOT ECLK_H_TOP / RSC_IHPSG13_MET2RES +XI11 ECLK_L_BOT ECLK_L_TOP / RSC_IHPSG13_MET2RES +XI1<3> PADR<2> PADR<3> CS sel23<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<2> PADR<3> CS sel23<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<2> NADR<3> CS sel23<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<2> NADR<3> CS sel23<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI2<15> sel23<3> sel01<3> EN WL<15> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<14> sel23<3> sel01<2> EN WL<14> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<13> sel23<3> sel01<1> EN WL<13> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<12> sel23<3> sel01<0> EN WL<12> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<11> sel23<2> sel01<3> EN WL<11> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<10> sel23<2> sel01<2> EN WL<10> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<9> sel23<2> sel01<1> EN WL<9> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<8> sel23<2> sel01<0> EN WL<8> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<7> sel23<1> sel01<3> EN WL<7> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<6> sel23<1> sel01<2> EN WL<6> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<5> sel23<1> sel01<1> EN WL<5> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<4> sel23<1> sel01<0> EN WL<4> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<3> sel23<0> sel01<3> EN WL<3> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<2> sel23<0> sel01<2> EN WL<2> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<1> sel23<0> sel01<1> EN WL<1> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<0> sel23<0> sel01<0> EN WL<0> VDD VSS / RSC_IHPSG13_NOR3X2 +XCAPS4 VDD VSS / RSC_IHPSG13_FILLCAP4 +XLATCH<3> CS ADDR<3> PADR<3> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<2> CS ADDR<2> PADR<2> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<1> CS ADDR<1> PADR<1> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<0> CS ADDR<0> PADR<0> VDD VSS / RSC_IHPSG13_LHPQX2 +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_2P_DEC02 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC ADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI2<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI2<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_2P_DEC01 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC NADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI2<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI2<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_2P_DEC00 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC NADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV<1> ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +XADDRINV<0> ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_2P_DEC03 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC ADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_2P_ROWDEC9 ADDR_N_I<8> ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ++ ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ++ WL_O<511> WL_O<510> WL_O<509> WL_O<508> WL_O<507> WL_O<506> WL_O<505> ++ WL_O<504> WL_O<503> WL_O<502> WL_O<501> WL_O<500> WL_O<499> WL_O<498> ++ WL_O<497> WL_O<496> WL_O<495> WL_O<494> WL_O<493> WL_O<492> WL_O<491> ++ WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> WL_O<484> ++ WL_O<483> WL_O<482> WL_O<481> WL_O<480> WL_O<479> WL_O<478> WL_O<477> ++ WL_O<476> WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> ++ WL_O<469> WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> WL_O<463> ++ WL_O<462> WL_O<461> WL_O<460> WL_O<459> WL_O<458> WL_O<457> WL_O<456> ++ WL_O<455> WL_O<454> WL_O<453> WL_O<452> WL_O<451> WL_O<450> WL_O<449> ++ WL_O<448> WL_O<447> WL_O<446> WL_O<445> WL_O<444> WL_O<443> WL_O<442> ++ WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> WL_O<436> WL_O<435> ++ WL_O<434> WL_O<433> WL_O<432> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> WL_O<415> WL_O<414> ++ WL_O<413> WL_O<412> WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> ++ WL_O<406> WL_O<405> WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> ++ WL_O<399> WL_O<398> WL_O<397> WL_O<396> WL_O<395> WL_O<394> WL_O<393> ++ WL_O<392> WL_O<391> WL_O<390> WL_O<389> WL_O<388> WL_O<387> WL_O<386> ++ WL_O<385> WL_O<384> WL_O<383> WL_O<382> WL_O<381> WL_O<380> WL_O<379> ++ WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> WL_O<372> ++ WL_O<371> WL_O<370> WL_O<369> WL_O<368> WL_O<367> WL_O<366> WL_O<365> ++ WL_O<364> WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> ++ WL_O<357> WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> WL_O<351> ++ WL_O<350> WL_O<349> WL_O<348> WL_O<347> WL_O<346> WL_O<345> WL_O<344> ++ WL_O<343> WL_O<342> WL_O<341> WL_O<340> WL_O<339> WL_O<338> WL_O<337> ++ WL_O<336> WL_O<335> WL_O<334> WL_O<333> WL_O<332> WL_O<331> WL_O<330> ++ WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> WL_O<324> WL_O<323> ++ WL_O<322> WL_O<321> WL_O<320> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> WL_O<303> WL_O<302> ++ WL_O<301> WL_O<300> WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> ++ WL_O<294> WL_O<293> WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> ++ WL_O<287> WL_O<286> WL_O<285> WL_O<284> WL_O<283> WL_O<282> WL_O<281> ++ WL_O<280> WL_O<279> WL_O<278> WL_O<277> WL_O<276> WL_O<275> WL_O<274> ++ WL_O<273> WL_O<272> WL_O<271> WL_O<270> WL_O<269> WL_O<268> WL_O<267> ++ WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> WL_O<260> ++ WL_O<259> WL_O<258> WL_O<257> WL_O<256> WL_O<255> WL_O<254> WL_O<253> ++ WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> ++ WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> WL_O<239> ++ WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> WL_O<233> WL_O<232> ++ WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> WL_O<226> WL_O<225> ++ WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> WL_O<219> WL_O<218> ++ WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> WL_O<212> WL_O<211> ++ WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> WL_O<191> WL_O<190> ++ WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> ++ WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> ++ WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> WL_O<170> WL_O<169> ++ WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> WL_O<163> WL_O<162> ++ WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> WL_O<156> WL_O<155> ++ WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> WL_O<148> ++ WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> WL_O<142> WL_O<141> ++ WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> ++ WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> WL_O<127> ++ WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> ++ WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> ++ WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> ++ WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> ++ WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XSEL<31> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<31> ECLK_H<31> ++ ECLK_H<32> ECLK_B<31> ECLK_B<32> WL_O<511> WL_O<510> WL_O<509> WL_O<508> ++ WL_O<507> WL_O<506> WL_O<505> WL_O<504> WL_O<503> WL_O<502> WL_O<501> ++ WL_O<500> WL_O<499> WL_O<498> WL_O<497> WL_O<496> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC04 +XSEL<30> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<30> ECLK_H<30> ++ ECLK_H<31> ECLK_B<30> ECLK_B<31> WL_O<495> WL_O<494> WL_O<493> WL_O<492> ++ WL_O<491> WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> ++ WL_O<484> WL_O<483> WL_O<482> WL_O<481> WL_O<480> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC04 +XSEL<29> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<29> ECLK_H<29> ++ ECLK_H<30> ECLK_B<29> ECLK_B<30> WL_O<479> WL_O<478> WL_O<477> WL_O<476> ++ WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> WL_O<469> ++ WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC04 +XSEL<28> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<28> ECLK_H<28> ++ ECLK_H<29> ECLK_B<28> ECLK_B<29> WL_O<463> WL_O<462> WL_O<461> WL_O<460> ++ WL_O<459> WL_O<458> WL_O<457> WL_O<456> WL_O<455> WL_O<454> WL_O<453> ++ WL_O<452> WL_O<451> WL_O<450> WL_O<449> WL_O<448> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC04 +XSEL<27> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<27> ECLK_H<27> ++ ECLK_H<28> ECLK_B<27> ECLK_B<28> WL_O<447> WL_O<446> WL_O<445> WL_O<444> ++ WL_O<443> WL_O<442> WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> ++ WL_O<436> WL_O<435> WL_O<434> WL_O<433> WL_O<432> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC04 +XSEL<26> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<26> ECLK_H<26> ++ ECLK_H<27> ECLK_B<26> ECLK_B<27> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC04 +XSEL<25> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<25> ECLK_H<25> ++ ECLK_H<26> ECLK_B<25> ECLK_B<26> WL_O<415> WL_O<414> WL_O<413> WL_O<412> ++ WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> WL_O<406> WL_O<405> ++ WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC04 +XSEL<24> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<24> ECLK_H<24> ++ ECLK_H<25> ECLK_B<24> ECLK_B<25> WL_O<399> WL_O<398> WL_O<397> WL_O<396> ++ WL_O<395> WL_O<394> WL_O<393> WL_O<392> WL_O<391> WL_O<390> WL_O<389> ++ WL_O<388> WL_O<387> WL_O<386> WL_O<385> WL_O<384> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC04 +XSEL<23> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<23> ECLK_H<23> ++ ECLK_H<24> ECLK_B<23> ECLK_B<24> WL_O<383> WL_O<382> WL_O<381> WL_O<380> ++ WL_O<379> WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> ++ WL_O<372> WL_O<371> WL_O<370> WL_O<369> WL_O<368> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC04 +XSEL<22> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<22> ECLK_H<22> ++ ECLK_H<23> ECLK_B<22> ECLK_B<23> WL_O<367> WL_O<366> WL_O<365> WL_O<364> ++ WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> WL_O<357> ++ WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC04 +XSEL<21> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<21> ECLK_H<21> ++ ECLK_H<22> ECLK_B<21> ECLK_B<22> WL_O<351> WL_O<350> WL_O<349> WL_O<348> ++ WL_O<347> WL_O<346> WL_O<345> WL_O<344> WL_O<343> WL_O<342> WL_O<341> ++ WL_O<340> WL_O<339> WL_O<338> WL_O<337> WL_O<336> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC04 +XSEL<20> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<20> ECLK_H<20> ++ ECLK_H<21> ECLK_B<20> ECLK_B<21> WL_O<335> WL_O<334> WL_O<333> WL_O<332> ++ WL_O<331> WL_O<330> WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> ++ WL_O<324> WL_O<323> WL_O<322> WL_O<321> WL_O<320> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC04 +XSEL<19> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<19> ECLK_H<19> ++ ECLK_H<20> ECLK_B<19> ECLK_B<20> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC04 +XSEL<18> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<18> ECLK_H<18> ++ ECLK_H<19> ECLK_B<18> ECLK_B<19> WL_O<303> WL_O<302> WL_O<301> WL_O<300> ++ WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> WL_O<294> WL_O<293> ++ WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC04 +XSEL<17> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<17> ECLK_H<17> ++ ECLK_H<18> ECLK_B<17> ECLK_B<18> WL_O<287> WL_O<286> WL_O<285> WL_O<284> ++ WL_O<283> WL_O<282> WL_O<281> WL_O<280> WL_O<279> WL_O<278> WL_O<277> ++ WL_O<276> WL_O<275> WL_O<274> WL_O<273> WL_O<272> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC04 +XSEL<16> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<16> ECLK_H<16> ++ ECLK_H<17> ECLK_B<16> ECLK_B<17> WL_O<271> WL_O<270> WL_O<269> WL_O<268> ++ WL_O<267> WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> ++ WL_O<260> WL_O<259> WL_O<258> WL_O<257> WL_O<256> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC04 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_1024x8_c2_2P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_1024x8_c2_2P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_1024x8_c2_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_1024x8_c2_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_1024x8_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_1024x8_c2_2P_DEC04 +XDEC10<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<6> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC02 +XDEC10<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<2> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC02 +XDEC10<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<30> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC02 +XDEC10<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<26> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC02 +XDEC10<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<22> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC02 +XDEC10<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<18> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<14> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<10> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<6> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<2> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC02 +XDEC01<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC01 +XDEC01<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<5> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC01 +XDEC01<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<1> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC01 +XDEC01<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<29> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC01 +XDEC01<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<25> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC01 +XDEC01<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<21> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC01 +XDEC01<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<17> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<13> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<9> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<5> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<1> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC01 +XL2<258> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<257> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<256> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<255> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<254> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<253> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<252> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<251> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<250> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<249> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<248> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<247> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<246> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<245> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<244> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<243> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<242> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<241> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<240> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<239> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<238> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<237> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<236> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<235> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<234> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<233> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<232> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<231> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<230> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<229> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<228> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<227> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<226> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<225> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<224> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<223> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<222> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<221> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<220> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<219> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<218> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<217> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<216> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<215> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<214> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<213> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<212> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<211> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<210> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<209> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<208> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<207> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<206> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<205> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<204> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<203> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<202> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<201> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<200> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<199> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<198> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<197> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<196> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<195> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<194> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<193> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<192> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<191> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<190> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<189> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<188> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<187> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<186> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<185> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<184> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<183> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<182> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<181> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<180> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<179> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<178> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<177> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<176> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<175> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<174> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<173> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<172> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<171> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<170> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<169> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<168> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<167> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<166> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<165> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<164> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<163> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<162> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<161> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<160> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<159> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<158> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<157> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<156> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<155> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<154> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<153> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<152> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<151> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<150> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<149> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<148> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<147> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<146> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<145> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<144> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<143> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<142> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<141> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<140> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<139> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<138> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<137> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<136> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<135> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<134> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<133> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC00<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC00 +XDEC00<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<4> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC00 +XDEC00<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<0> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC00 +XDEC00<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<28> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC00 +XDEC00<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<24> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC00 +XDEC00<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<20> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC00 +XDEC00<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<16> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<12> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<8> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<4> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<0> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC00 +XDEC11<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<7> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC03 +XDEC11<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<3> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC03 +XDEC11<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<31> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC03 +XDEC11<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<27> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC03 +XDEC11<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<23> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC03 +XDEC11<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<19> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<15> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<11> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<7> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<3> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC03 +XI0 ADDR_N_I<9> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_2P_ROWREG9 ACLK_N_I ADDR_I<8> ADDR_I<7> ADDR_I<6> ADDR_I<5> ++ ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<8> ADDR_N_O<7> ++ ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ++ ADDR_N_O<0> BIST_ADDR_I<8> BIST_ADDR_I<7> BIST_ADDR_I<6> BIST_ADDR_I<5> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XDFF<8> BIST_EN_I BIST_ADDR_I<8> ACLK_N_I ADDR_I<8> q_int<8> net04<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net04<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net04<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net04<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net04<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net04<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net04<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net04<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net04<8> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDRV<8> qn_int<8> ADDR_N_O<8> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XINV<8> q_int<8> qn_int<8> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +.ENDS + +.SUBCKT RM_IHPSG13_1024x8_c2_2P_DLY_MUX A SEL Z VDD VSS +XI11 net4 Z VDD VSS / RSC_IHPSG13_CINVX2 +XI8 A D<3> SEL net4 VDD VSS / RSC_IHPSG13_MX2IX1 +XI20<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1 +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_2P_CTRL ACLK_N BIST_CK_I BIST_CS_I BIST_EN BIST_RE_I ++ BIST_WE_I B_TIEL_O CK_I CS_I DCLK ECLK PULSE_H PULSE_L PULSE_O RCLK RE_I ++ ROW_CS WCLK WE_I VDD VSS +XI17 ck_regs we col_we VDD VSS / RSC_IHPSG13_DFNQX2 +XI16 ck_regs re col_re VDD VSS / RSC_IHPSG13_DFNQX2 +XI18 ck_regs cs net7 VDD VSS / RSC_IHPSG13_DFNQX2 +XI71 ACLK_N net012 PULSE_O VDD VSS / RSC_IHPSG13_DFNQX2 +XI77 col_we net017 net016 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI76 col_re net017 net018 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI15 ck_dly WEorREandCS aclk VDD VSS / RSC_IHPSG13_CGATEPX4 +XI14 ck WEandCS DCLK VDD VSS / RSC_IHPSG13_CGATEPX4 +XI60 net7 ROW_CS VDD VSS / RSC_IHPSG13_CBUFX8 +XI73 PULSE_O net012 VDD VSS / RSC_IHPSG13_CINVX2 +XI8 net017 net8 VDD VSS / RSC_IHPSG13_CINVX2 +XCAPS4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XBM_TIEL B_TIEL_O VDD VSS / RSC_IHPSG13_TIEL +XI64 ck ck_dly VDD VSS / RSC_IHPSG13_CDLYX2 +XI86 CS_I BIST_CS_I BIST_EN cs VDD VSS / RSC_IHPSG13_MX2X2 +XI87 CK_I BIST_CK_I BIST_EN ck VDD VSS / RSC_IHPSG13_MX2X2 +XI85 WE_I BIST_WE_I BIST_EN we VDD VSS / RSC_IHPSG13_MX2X2 +XI84 RE_I BIST_RE_I BIST_EN re VDD VSS / RSC_IHPSG13_MX2X2 +XI48 ck_dly ck_regs VDD VSS / RSC_IHPSG13_CINVX4 +XI81 net016 WCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI80 net018 RCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI78 net8 net020 VDD VSS / RSC_IHPSG13_CINVX4 +XCAPS8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI6 PULSE_L PULSE_H net017 VDD VSS / RSC_IHPSG13_XOR2X2 +XI22 we cs WEandCS VDD VSS / RSC_IHPSG13_AND2X2 +XI79 net020 ECLK VDD VSS / RSC_IHPSG13_CINVX8 +XI63 aclk ACLK_N VDD VSS / RSC_IHPSG13_CINVX8 +XI21 re we cs WEorREandCS VDD VSS / RSC_IHPSG13_OA12X1 +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_2P_COLDEC5 ACLK_N ADDR<4> ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<4> BIST_ADDR<3> ++ BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<4> BIST_EN_I BIST_ADDR<4> ACLK_N ADDR<4> addr_int<1> net13<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int<0> net13<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net13<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net13<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net13<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI15<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI15<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI15<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> addr_int<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_CBUFX2 +XI13<0> addr_int<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XI14<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_2P_BLDRV A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL ++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> ++ A_SEL_P<1> A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> ++ B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> ++ B_SEL_P<2> B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS +MA_CWN<3> A_BLC<3> A_BLC_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CWN<2> A_BLC<2> A_BLC_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CWN<1> A_BLC<1> A_BLC_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CWN<0> A_BLC<0> A_BLC_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<3> A_BLT<3> A_BLT_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<2> A_BLT<2> A_BLT_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<1> A_BLT<1> A_BLT_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<0> A_BLT<0> A_BLT_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<3> B_BLT<3> B_BLT_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<2> B_BLT<2> B_BLT_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<1> B_BLT<1> B_BLT_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<0> B_BLT<0> B_BLT_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<3> B_BLC<3> B_BLC_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<2> B_BLC<2> B_BLC_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<1> B_BLC<1> B_BLC_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<0> B_BLC<0> B_BLC_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CPR<3> A_BLC<3> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_CPR<2> A_BLC<2> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_CPR<1> A_BLC<1> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_CPR<0> A_BLC<0> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TWP<3> A_BLT<3> A_BLT_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TWP<2> A_BLT<2> A_BLT_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TWP<1> A_BLT<1> A_BLT_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TWP<0> A_BLT<0> A_BLT_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<3> A_BLC<3> A_BLC_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<2> A_BLC<2> A_BLC_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<1> A_BLC<1> A_BLC_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<0> A_BLC<0> A_BLC_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TPR<3> A_BLT<3> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TPR<2> A_BLT<2> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TPR<1> A_BLT<1> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TPR<0> A_BLT<0> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TSP<3> A_BLT_SEL A_SEL_N<3> A_BLT<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TSP<2> A_BLT_SEL A_SEL_N<2> A_BLT<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TSP<1> A_BLT_SEL A_SEL_N<1> A_BLT<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TSP<0> A_BLT_SEL A_SEL_N<0> A_BLT<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<3> A_BLC_SEL A_SEL_N<3> A_BLC<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<2> A_BLC_SEL A_SEL_N<2> A_BLC<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<1> A_BLC_SEL A_SEL_N<1> A_BLC<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<0> A_BLC_SEL A_SEL_N<0> A_BLC<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<3> B_BLC<3> B_BLC_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<2> B_BLC<2> B_BLC_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<1> B_BLC<1> B_BLC_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<0> B_BLC<0> B_BLC_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<3> B_BLT<3> B_BLT_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<2> B_BLT<2> B_BLT_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<1> B_BLT<1> B_BLT_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<0> B_BLT<0> B_BLT_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<3> B_BLT_SEL B_SEL_N<3> B_BLT<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<2> B_BLT_SEL B_SEL_N<2> B_BLT<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<1> B_BLT_SEL B_SEL_N<1> B_BLT<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<0> B_BLT_SEL B_SEL_N<0> B_BLT<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TPR<3> B_BLT<3> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_TPR<2> B_BLT<2> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_TPR<1> B_BLT<1> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_TPR<0> B_BLT<0> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CSP<3> B_BLC_SEL B_SEL_N<3> B_BLC<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CSP<2> B_BLC_SEL B_SEL_N<2> B_BLC<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CSP<1> B_BLC_SEL B_SEL_N<1> B_BLC<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CSP<0> B_BLC_SEL B_SEL_N<0> B_BLC<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CPR<3> B_BLC<3> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CPR<2> B_BLC<2> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CPR<1> B_BLC<1> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CPR<0> B_BLC<0> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +XA_SEL<3> A_SEL_P<3> A_SEL_N<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_SEL<2> A_SEL_P<2> A_SEL_N<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_SEL<1> A_SEL_P<1> A_SEL_N<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_SEL<0> A_SEL_P<0> A_SEL_N<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_CINV<3> A_BLT_PMOS_DRIVE<3> A_BLC_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_CINV<2> A_BLT_PMOS_DRIVE<2> A_BLC_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_CINV<1> A_BLT_PMOS_DRIVE<1> A_BLC_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_CINV<0> A_BLT_PMOS_DRIVE<0> A_BLC_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<3> A_BLC_PMOS_DRIVE<3> A_BLT_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<2> A_BLC_PMOS_DRIVE<2> A_BLT_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<1> A_BLC_PMOS_DRIVE<1> A_BLT_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<0> A_BLC_PMOS_DRIVE<0> A_BLT_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_SEL<3> B_SEL_P<3> B_SEL_N<3> VDD VSS / RSC_IHPSG13_INVX2 +XB_SEL<2> B_SEL_P<2> B_SEL_N<2> VDD VSS / RSC_IHPSG13_INVX2 +XB_SEL<1> B_SEL_P<1> B_SEL_N<1> VDD VSS / RSC_IHPSG13_INVX2 +XB_SEL<0> B_SEL_P<0> B_SEL_N<0> VDD VSS / RSC_IHPSG13_INVX2 +XB_TINV<3> B_BLC_PMOS_DRIVE<3> B_BLT_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_TINV<2> B_BLC_PMOS_DRIVE<2> B_BLT_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_TINV<1> B_BLC_PMOS_DRIVE<1> B_BLT_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_TINV<0> B_BLC_PMOS_DRIVE<0> B_BLT_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<3> B_BLT_PMOS_DRIVE<3> B_BLC_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<2> B_BLT_PMOS_DRIVE<2> B_BLC_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<1> B_BLT_PMOS_DRIVE<1> B_BLC_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<0> B_BLT_PMOS_DRIVE<0> B_BLC_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TDEC<3> A_SEL_P<3> A_WR_ONE A_BLT_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_TDEC<2> A_SEL_P<2> A_WR_ONE A_BLT_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_TDEC<1> A_SEL_P<1> A_WR_ONE A_BLT_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_TDEC<0> A_SEL_P<0> A_WR_ONE A_BLT_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<3> A_SEL_P<3> A_WR_ZERO A_BLC_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<2> A_SEL_P<2> A_WR_ZERO A_BLC_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<1> A_SEL_P<1> A_WR_ZERO A_BLC_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<0> A_SEL_P<0> A_WR_ZERO A_BLC_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<3> B_SEL_P<3> B_WR_ZERO B_BLC_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<2> B_SEL_P<2> B_WR_ZERO B_BLC_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<1> B_SEL_P<1> B_WR_ZERO B_BLC_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<0> B_SEL_P<0> B_WR_ZERO B_BLC_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<3> B_SEL_P<3> B_WR_ONE B_BLT_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<2> B_SEL_P<2> B_WR_ONE B_BLT_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<1> B_SEL_P<1> B_WR_ONE B_BLT_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<0> B_SEL_P<0> B_WR_ONE B_BLT_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +.ENDS +.SUBCKT RSC_IHPSG13_AND2X6 A B Z VDD VSS +MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=2.94u l=130.00n ng=3 nrd=0 nrs=0 +MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=4.86u l=130.00n ng=3 nrd=0 nrs=0 +MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_2P_COLCTRL5 A_ADDR_COL<1> A_ADDR_COL<0> A_ADDR_DEC<7> ++ A_ADDR_DEC<6> A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<31> ++ A_BLC<30> A_BLC<29> A_BLC<28> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> ++ A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC<19> A_BLC<18> A_BLC<17> ++ A_BLC<16> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> ++ A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> ++ A_BLC<1> A_BLC<0> A_BLT<31> A_BLT<30> A_BLT<29> A_BLT<28> A_BLT<27> ++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT<23> A_BLT<22> A_BLT<21> A_BLT<20> ++ A_BLT<19> A_BLT<18> A_BLT<17> A_BLT<16> A_BLT<15> A_BLT<14> A_BLT<13> ++ A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> ++ A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_COL<1> B_ADDR_COL<0> ++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> ++ B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I ++ B_BIST_EN_I B_BLC<31> B_BLC<30> B_BLC<29> B_BLC<28> B_BLC<27> B_BLC<26> ++ B_BLC<25> B_BLC<24> B_BLC<23> B_BLC<22> B_BLC<21> B_BLC<20> B_BLC<19> ++ B_BLC<18> B_BLC<17> B_BLC<16> B_BLC<15> B_BLC<14> B_BLC<13> B_BLC<12> ++ B_BLC<11> B_BLC<10> B_BLC<9> B_BLC<8> B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> ++ B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<31> B_BLT<30> B_BLT<29> B_BLT<28> ++ B_BLT<27> B_BLT<26> B_BLT<25> B_BLT<24> B_BLT<23> B_BLT<22> B_BLT<21> ++ B_BLT<20> B_BLT<19> B_BLT<18> B_BLT<17> B_BLT<16> B_BLT<15> B_BLT<14> ++ B_BLT<13> B_BLT<12> B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT<7> B_BLT<6> ++ B_BLT<5> B_BLT<4> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L ++ B_DCLK_B_R B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L ++ B_RCLK_R B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS +XB_I80<1> B_WCLK_B_L B_RCLK_B_L B_W_nor_R<1> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XB_I80<0> B_WCLK_B_L B_RCLK_B_L B_W_nor_R<0> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I80<1> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<1> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I80<0> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<0> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XI_FILL4<16> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<15> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<14> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<13> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<12> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XB_INV<6> B_N1<1> B_P1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<5> B_N0<1> B_P0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<4> B_N0<0> B_P0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<3> B_ADDR_COL<1> B_N1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<2> B_ADDR_COL<1> B_N1<0> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<1> B_ADDR_COL<0> B_N0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<0> B_ADDR_COL<0> B_N0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<6> A_N1<1> A_P1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<5> A_N0<1> A_P0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<4> A_N0<0> A_P0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<3> A_ADDR_COL<1> A_N1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<2> A_ADDR_COL<1> A_N1<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_ADDR_COL<0> A_N0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL<0> A_N0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XB_I81<3> B_W_nor_R<1> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<2> B_W_nor_R<1> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<1> B_W_nor_R<0> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<0> B_W_nor_R<0> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<3> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<2> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<1> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XI_FILL8<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XAB_BLMUX<7> A_BLC<31> A_BLC<30> A_BLC<29> A_BLC<28> A_BLC_SEL A_BLT<31> ++ A_BLT<30> A_BLT<29> A_BLT<28> A_BLT_SEL A_PRE_N A_SEL_P<31> A_SEL_P<30> ++ A_SEL_P<29> A_SEL_P<28> A_WR_ONE A_WR_ZERO B_BLC<31> B_BLC<30> B_BLC<29> ++ B_BLC<28> B_BLC_SEL B_BLT<31> B_BLT<30> B_BLT<29> B_BLT<28> B_BLT_SEL ++ B_PRE_N B_SEL_P<31> B_SEL_P<30> B_SEL_P<29> B_SEL_P<28> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_1024x8_c2_2P_BLDRV +XAB_BLMUX<6> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> A_BLC_SEL A_BLT<27> ++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT_SEL A_PRE_N A_SEL_P<27> A_SEL_P<26> ++ A_SEL_P<25> A_SEL_P<24> A_WR_ONE A_WR_ZERO B_BLC<27> B_BLC<26> B_BLC<25> ++ B_BLC<24> B_BLC_SEL B_BLT<27> B_BLT<26> B_BLT<25> B_BLT<24> B_BLT_SEL ++ B_PRE_N B_SEL_P<27> B_SEL_P<26> B_SEL_P<25> B_SEL_P<24> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_1024x8_c2_2P_BLDRV +XAB_BLMUX<5> A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC_SEL A_BLT<23> ++ A_BLT<22> A_BLT<21> A_BLT<20> A_BLT_SEL A_PRE_N A_SEL_P<23> A_SEL_P<22> ++ A_SEL_P<21> A_SEL_P<20> A_WR_ONE A_WR_ZERO B_BLC<23> B_BLC<22> B_BLC<21> ++ B_BLC<20> B_BLC_SEL B_BLT<23> B_BLT<22> B_BLT<21> B_BLT<20> B_BLT_SEL ++ B_PRE_N B_SEL_P<23> B_SEL_P<22> B_SEL_P<21> B_SEL_P<20> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_1024x8_c2_2P_BLDRV +XAB_BLMUX<4> A_BLC<19> A_BLC<18> A_BLC<17> A_BLC<16> A_BLC_SEL A_BLT<19> ++ A_BLT<18> A_BLT<17> A_BLT<16> A_BLT_SEL A_PRE_N A_SEL_P<19> A_SEL_P<18> ++ A_SEL_P<17> A_SEL_P<16> A_WR_ONE A_WR_ZERO B_BLC<19> B_BLC<18> B_BLC<17> ++ B_BLC<16> B_BLC_SEL B_BLT<19> B_BLT<18> B_BLT<17> B_BLT<16> B_BLT_SEL ++ B_PRE_N B_SEL_P<19> B_SEL_P<18> B_SEL_P<17> B_SEL_P<16> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_1024x8_c2_2P_BLDRV +XAB_BLMUX<3> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC_SEL A_BLT<15> ++ A_BLT<14> A_BLT<13> A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<15> A_SEL_P<14> ++ A_SEL_P<13> A_SEL_P<12> A_WR_ONE A_WR_ZERO B_BLC<15> B_BLC<14> B_BLC<13> ++ B_BLC<12> B_BLC_SEL B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT_SEL ++ B_PRE_N B_SEL_P<15> B_SEL_P<14> B_SEL_P<13> B_SEL_P<12> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_1024x8_c2_2P_BLDRV +XAB_BLMUX<2> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC_SEL A_BLT<11> ++ A_BLT<10> A_BLT<9> A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<11> A_SEL_P<10> ++ A_SEL_P<9> A_SEL_P<8> A_WR_ONE A_WR_ZERO B_BLC<11> B_BLC<10> B_BLC<9> ++ B_BLC<8> B_BLC_SEL B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT_SEL B_PRE_N ++ B_SEL_P<11> B_SEL_P<10> B_SEL_P<9> B_SEL_P<8> B_WR_ONE B_WR_ZERO VDD ++ VSS / RM_IHPSG13_1024x8_c2_2P_BLDRV +XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<7> A_SEL_P<6> A_SEL_P<5> ++ A_SEL_P<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC_SEL ++ B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N B_SEL_P<7> B_SEL_P<6> ++ B_SEL_P<5> B_SEL_P<4> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_BLDRV +XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> A_SEL_P<1> ++ A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLC_SEL ++ B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> B_SEL_P<2> ++ B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_BLDRV +XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6 +XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<31> net041<0> B_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<30> net041<1> B_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<29> net041<2> B_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<28> net041<3> B_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<27> net041<4> B_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<26> net041<5> B_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<25> net041<6> B_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<24> net041<7> B_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<23> net041<8> B_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<22> net041<9> B_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<21> net041<10> B_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<20> net041<11> B_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<19> net041<12> B_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<18> net041<13> B_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<17> net041<14> B_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<16> net041<15> B_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<15> net041<16> B_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<14> net041<17> B_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<13> net041<18> B_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<12> net041<19> B_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<11> net041<20> B_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<10> net041<21> B_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<9> net041<22> B_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<8> net041<23> B_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<7> net041<24> B_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<6> net041<25> B_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<5> net041<26> B_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<4> net041<27> B_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<3> net041<28> B_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<2> net041<29> B_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<1> net041<30> B_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<0> net041<31> B_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<31> net23<0> A_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<30> net23<1> A_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<29> net23<2> A_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<28> net23<3> A_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<27> net23<4> A_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<26> net23<5> A_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<25> net23<6> A_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<24> net23<7> A_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<23> net23<8> A_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<22> net23<9> A_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<21> net23<10> A_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<20> net23<11> A_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<19> net23<12> A_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<18> net23<13> A_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<17> net23<14> A_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<16> net23<15> A_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<15> net23<16> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<17> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<18> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<19> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<20> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<21> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<22> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<23> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<24> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<25> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<26> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<27> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<28> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<29> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<30> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<31> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net042 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net043 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net21 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XB_DEC3<31> B_P1<1> B_P0<1> B_ADDR_DEC<7> net041<0> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<30> B_P1<1> B_P0<1> B_ADDR_DEC<6> net041<1> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<29> B_P1<1> B_P0<1> B_ADDR_DEC<5> net041<2> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<28> B_P1<1> B_P0<1> B_ADDR_DEC<4> net041<3> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<27> B_P1<1> B_P0<1> B_ADDR_DEC<3> net041<4> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<26> B_P1<1> B_P0<1> B_ADDR_DEC<2> net041<5> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<25> B_P1<1> B_P0<1> B_ADDR_DEC<1> net041<6> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<24> B_P1<1> B_P0<1> B_ADDR_DEC<0> net041<7> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<23> B_P1<1> B_N0<1> B_ADDR_DEC<7> net041<8> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<22> B_P1<1> B_N0<1> B_ADDR_DEC<6> net041<9> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<21> B_P1<1> B_N0<1> B_ADDR_DEC<5> net041<10> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<20> B_P1<1> B_N0<1> B_ADDR_DEC<4> net041<11> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<19> B_P1<1> B_N0<1> B_ADDR_DEC<3> net041<12> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<18> B_P1<1> B_N0<1> B_ADDR_DEC<2> net041<13> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<17> B_P1<1> B_N0<1> B_ADDR_DEC<1> net041<14> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<16> B_P1<1> B_N0<1> B_ADDR_DEC<0> net041<15> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<15> B_N1<0> B_P0<0> B_ADDR_DEC<7> net041<16> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<14> B_N1<0> B_P0<0> B_ADDR_DEC<6> net041<17> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<13> B_N1<0> B_P0<0> B_ADDR_DEC<5> net041<18> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<12> B_N1<0> B_P0<0> B_ADDR_DEC<4> net041<19> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<11> B_N1<0> B_P0<0> B_ADDR_DEC<3> net041<20> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<10> B_N1<0> B_P0<0> B_ADDR_DEC<2> net041<21> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<9> B_N1<0> B_P0<0> B_ADDR_DEC<1> net041<22> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<8> B_N1<0> B_P0<0> B_ADDR_DEC<0> net041<23> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<7> B_N1<0> B_N0<0> B_ADDR_DEC<7> net041<24> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<6> B_N1<0> B_N0<0> B_ADDR_DEC<6> net041<25> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<5> B_N1<0> B_N0<0> B_ADDR_DEC<5> net041<26> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<4> B_N1<0> B_N0<0> B_ADDR_DEC<4> net041<27> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<3> B_N1<0> B_N0<0> B_ADDR_DEC<3> net041<28> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<2> B_N1<0> B_N0<0> B_ADDR_DEC<2> net041<29> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<1> B_N1<0> B_N0<0> B_ADDR_DEC<1> net041<30> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<0> B_N1<0> B_N0<0> B_ADDR_DEC<0> net041<31> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<31> A_P1<1> A_P0<1> A_ADDR_DEC<7> net23<0> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<30> A_P1<1> A_P0<1> A_ADDR_DEC<6> net23<1> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<29> A_P1<1> A_P0<1> A_ADDR_DEC<5> net23<2> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<28> A_P1<1> A_P0<1> A_ADDR_DEC<4> net23<3> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<27> A_P1<1> A_P0<1> A_ADDR_DEC<3> net23<4> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<26> A_P1<1> A_P0<1> A_ADDR_DEC<2> net23<5> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<25> A_P1<1> A_P0<1> A_ADDR_DEC<1> net23<6> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<24> A_P1<1> A_P0<1> A_ADDR_DEC<0> net23<7> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<23> A_P1<1> A_N0<1> A_ADDR_DEC<7> net23<8> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<22> A_P1<1> A_N0<1> A_ADDR_DEC<6> net23<9> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<21> A_P1<1> A_N0<1> A_ADDR_DEC<5> net23<10> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<20> A_P1<1> A_N0<1> A_ADDR_DEC<4> net23<11> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<19> A_P1<1> A_N0<1> A_ADDR_DEC<3> net23<12> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<18> A_P1<1> A_N0<1> A_ADDR_DEC<2> net23<13> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<17> A_P1<1> A_N0<1> A_ADDR_DEC<1> net23<14> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<16> A_P1<1> A_N0<1> A_ADDR_DEC<0> net23<15> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<15> A_N1<0> A_P0<0> A_ADDR_DEC<7> net23<16> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<14> A_N1<0> A_P0<0> A_ADDR_DEC<6> net23<17> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<13> A_N1<0> A_P0<0> A_ADDR_DEC<5> net23<18> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<12> A_N1<0> A_P0<0> A_ADDR_DEC<4> net23<19> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<11> A_N1<0> A_P0<0> A_ADDR_DEC<3> net23<20> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<10> A_N1<0> A_P0<0> A_ADDR_DEC<2> net23<21> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<9> A_N1<0> A_P0<0> A_ADDR_DEC<1> net23<22> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<8> A_N1<0> A_P0<0> A_ADDR_DEC<0> net23<23> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<7> A_N1<0> A_N0<0> A_ADDR_DEC<7> net23<24> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<6> A_N1<0> A_N0<0> A_ADDR_DEC<6> net23<25> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<5> A_N1<0> A_N0<0> A_ADDR_DEC<5> net23<26> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<4> A_N1<0> A_N0<0> A_ADDR_DEC<4> net23<27> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<3> A_N1<0> A_N0<0> A_ADDR_DEC<3> net23<28> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<2> A_N1<0> A_N0<0> A_ADDR_DEC<2> net23<29> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<1> A_N1<0> A_N0<0> A_ADDR_DEC<1> net23<30> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<0> A_N1<0> A_N0<0> A_ADDR_DEC<0> net23<31> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_2P_COLDRV13_FILL4 VDD VSS +XI0<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RSC_IHPSG13_CBUFX16 A Z VDD VSS +MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=2.115u l=130.00n ng=3 nrd=0 nrs=0 +MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=5.64u l=130.00n ng=8 nrd=0 nrs=0 +MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=13.000u l=130.00n ng=8 nrd=0 ++ nrs=0 +MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=4.89u l=130.00n ng=3 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_1P_COLDRV13X16 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP8 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX16 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=12.96u l=130.00n ng=8 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_1P_WLDRV16X16 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX16 +.ENDS + + +.SUBCKT RM_IHPSG13_1024x8_c2_2P_COLDRV13X4 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1 VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_2P_WLDRV16X4 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX4 +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_2P_ROWDEC8 ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ++ ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<255> ++ WL_O<254> WL_O<253> WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> ++ WL_O<247> WL_O<246> WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> ++ WL_O<240> WL_O<239> WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> ++ WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> ++ WL_O<226> WL_O<225> WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> ++ WL_O<205> WL_O<204> WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> ++ WL_O<198> WL_O<197> WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> ++ WL_O<191> WL_O<190> WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> ++ WL_O<184> WL_O<183> WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> ++ WL_O<177> WL_O<176> WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> ++ WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> ++ WL_O<163> WL_O<162> WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> ++ WL_O<156> WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> ++ WL_O<149> WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> ++ WL_O<142> WL_O<141> WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> ++ WL_O<135> WL_O<134> WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> ++ WL_O<128> WL_O<127> WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> ++ WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> ++ WL_O<114> WL_O<113> WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> ++ WL_O<92> WL_O<91> WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> ++ WL_O<84> WL_O<83> WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> ++ WL_O<76> WL_O<75> WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> ++ WL_O<68> WL_O<67> WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> ++ WL_O<60> WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> ++ WL_O<52> WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> ++ WL_O<44> WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> ++ WL_O<36> WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> ++ WL_O<28> WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> ++ WL_O<20> WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> ++ WL_O<12> WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> ++ WL_O<3> WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC11<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<3> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<15> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<11> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC03 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_1024x8_c2_2P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_1024x8_c2_2P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_1024x8_c2_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_1024x8_c2_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_1024x8_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_1024x8_c2_2P_DEC04 +XDEC10<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<2> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<14> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<10> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC02 +XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC00<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<12> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<8> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC00 +XDEC01<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<13> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<9> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC01 +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_2P_ROWREG8 ACLK_N_I ADDR_I<7> ADDR_I<6> ADDR_I<5> ADDR_I<4> ++ ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<7> ADDR_N_O<6> ADDR_N_O<5> ++ ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<7> ++ BIST_ADDR_I<6> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> ++ BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI10 VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_2P_COLDEC4 ACLK_N ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<3> BIST_ADDR<2> ++ BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int net12<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net12<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net12<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net12<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI14 addr_int ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI15 ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_2P_COLCTRL4 A_ADDR_COL A_ADDR_DEC<7> A_ADDR_DEC<6> ++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<15> A_BLC<14> ++ A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> ++ A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<15> A_BLT<14> ++ A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L ++ A_DCLK_B_R A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L ++ A_RCLK_R A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_COL ++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> ++ B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I ++ B_BIST_EN_I B_BLC<15> B_BLC<14> B_BLC<13> B_BLC<12> B_BLC<11> B_BLC<10> ++ B_BLC<9> B_BLC<8> B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC<3> B_BLC<2> ++ B_BLC<1> B_BLC<0> B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT<11> ++ B_BLT<10> B_BLT<9> B_BLT<8> B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT<3> ++ B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L B_DCLK_B_R B_DCLK_L B_DCLK_R ++ B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L B_RCLK_R B_TIEH_O B_WCLK_B_L ++ B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS +XB_I80 B_RCLK_B_L B_WCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I80 A_RCLK_B_L A_WCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4 +XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4 +XI_FILL4<26> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<25> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<24> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<23> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<22> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<21> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<20> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<19> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<18> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<17> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<16> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<15> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<14> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<13> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<12> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<1> B_N0 B_P0 VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<0> B_ADDR_COL B_N0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_N0 A_P0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL A_N0 VDD VSS / RSC_IHPSG13_CINVX4 +XB_I81<1> net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<0> net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<1> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XAB_BLMUX<3> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC_SEL A_BLT<15> ++ A_BLT<14> A_BLT<13> A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<15> A_SEL_P<14> ++ A_SEL_P<13> A_SEL_P<12> A_WR_ONE A_WR_ZERO B_BLC<15> B_BLC<14> B_BLC<13> ++ B_BLC<12> B_BLC_SEL B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT_SEL ++ B_PRE_N B_SEL_P<15> B_SEL_P<14> B_SEL_P<13> B_SEL_P<12> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_1024x8_c2_2P_BLDRV +XAB_BLMUX<2> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC_SEL A_BLT<11> ++ A_BLT<10> A_BLT<9> A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<11> A_SEL_P<10> ++ A_SEL_P<9> A_SEL_P<8> A_WR_ONE A_WR_ZERO B_BLC<11> B_BLC<10> B_BLC<9> ++ B_BLC<8> B_BLC_SEL B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT_SEL B_PRE_N ++ B_SEL_P<11> B_SEL_P<10> B_SEL_P<9> B_SEL_P<8> B_WR_ONE B_WR_ZERO VDD ++ VSS / RM_IHPSG13_1024x8_c2_2P_BLDRV +XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<7> A_SEL_P<6> A_SEL_P<5> ++ A_SEL_P<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC_SEL ++ B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N B_SEL_P<7> B_SEL_P<6> ++ B_SEL_P<5> B_SEL_P<4> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_BLDRV +XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> A_SEL_P<1> ++ A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLC_SEL ++ B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> B_SEL_P<2> ++ B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_BLDRV +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net046 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net045 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net24 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_DEC3INV<15> net23<0> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<1> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<2> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<3> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<4> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<5> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<6> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<7> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<8> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<9> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<10> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<11> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<12> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<13> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<14> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<15> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<15> net044<0> B_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<14> net044<1> B_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<13> net044<2> B_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<12> net044<3> B_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<11> net044<4> B_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<10> net044<5> B_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<9> net044<6> B_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<8> net044<7> B_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<7> net044<8> B_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<6> net044<9> B_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<5> net044<10> B_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<4> net044<11> B_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<3> net044<12> B_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<2> net044<13> B_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<1> net044<14> B_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<0> net044<15> B_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XI_FILL8<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_DEC3<15> A_P0 A_ADDR_DEC<7> net23<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<14> A_P0 A_ADDR_DEC<6> net23<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<13> A_P0 A_ADDR_DEC<5> net23<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<12> A_P0 A_ADDR_DEC<4> net23<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<11> A_P0 A_ADDR_DEC<3> net23<4> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<10> A_P0 A_ADDR_DEC<2> net23<5> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<9> A_P0 A_ADDR_DEC<1> net23<6> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<8> A_P0 A_ADDR_DEC<0> net23<7> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<7> A_N0 A_ADDR_DEC<7> net23<8> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<6> A_N0 A_ADDR_DEC<6> net23<9> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<5> A_N0 A_ADDR_DEC<5> net23<10> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<4> A_N0 A_ADDR_DEC<4> net23<11> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<3> A_N0 A_ADDR_DEC<3> net23<12> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<2> A_N0 A_ADDR_DEC<2> net23<13> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<1> A_N0 A_ADDR_DEC<1> net23<14> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<0> A_N0 A_ADDR_DEC<0> net23<15> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<15> B_P0 B_ADDR_DEC<7> net044<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<14> B_P0 B_ADDR_DEC<6> net044<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<13> B_P0 B_ADDR_DEC<5> net044<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<12> B_P0 B_ADDR_DEC<4> net044<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<11> B_P0 B_ADDR_DEC<3> net044<4> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<10> B_P0 B_ADDR_DEC<2> net044<5> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<9> B_P0 B_ADDR_DEC<1> net044<6> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<8> B_P0 B_ADDR_DEC<0> net044<7> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<7> B_N0 B_ADDR_DEC<7> net044<8> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<6> B_N0 B_ADDR_DEC<6> net044<9> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<5> B_N0 B_ADDR_DEC<5> net044<10> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<4> B_N0 B_ADDR_DEC<4> net044<11> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<3> B_N0 B_ADDR_DEC<3> net044<12> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<2> B_N0 B_ADDR_DEC<2> net044<13> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<1> B_N0 B_ADDR_DEC<1> net044<14> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<0> B_N0 B_ADDR_DEC<0> net044<15> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS + + +.SUBCKT RM_IHPSG13_1024x8_c2_2P_ROWDEC5 ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ++ ADDR_N_I<0> CS_I ECLK_I WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC00 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_1024x8_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_1024x8_c2_2P_DEC04 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC01 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0 ADDR_N_I<5> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_2P_ROWREG5 ACLK_N_I ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ++ ADDR_I<0> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_1024x8_c2_2P_COLDEC3 ACLK_N ADDR<2> ADDR<1> ADDR<0> ADDR_COL<1> ++ ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ++ ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> ++ BIST_EN_I VDD VSS +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net13<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net13<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net13<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RSC_IHPSG13_DFPQD_MSAFFX2P CP DN DP QN QP VDD VSS +XI_AMP CP DN DP QN QP VDD VSS / RSC_IHPSG13_DFPQD_MSAFFX2 +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_2P_COLCTRL3 A_ADDR_DEC<7> A_ADDR_DEC<6> A_ADDR_DEC<5> ++ A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> A_ADDR_DEC<0> ++ A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> ++ A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> ++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R A_DCLK_L ++ A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R A_TIEH_O ++ A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_DEC<7> B_ADDR_DEC<6> ++ B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> ++ B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I B_BIST_EN_I B_BLC<7> B_BLC<6> B_BLC<5> ++ B_BLC<4> B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<7> B_BLT<6> B_BLT<5> ++ B_BLT<4> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L B_DCLK_B_R ++ B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L B_RCLK_R ++ B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net044 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net043 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2P +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2P +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_ADDR_DEC<7> A_ADDR_DEC<6> ++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> ++ B_BLC<4> B_BLC_SEL B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N ++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_1024x8_c2_2P_BLDRV +XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> ++ B_BLC<0> B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N ++ B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_1024x8_c2_2P_BLDRV +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I80 B_WCLK_B_L B_RCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2 +XB_I76 B_DO_WRITE_P B_DI_N B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XB_I75 B_DO_WRITE_P B_DI_R B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_I80 A_WCLK_B_L A_RCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XB_I81 net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_1024x8_c2_2P_ROWDEC6 ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ++ ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<63> WL_O<62> WL_O<61> WL_O<60> ++ WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> ++ WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> ++ WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> ++ WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> ++ WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> ++ WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> ++ WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> ++ WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC10 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<2> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC02 +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC00 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_1024x8_c2_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_1024x8_c2_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_1024x8_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_1024x8_c2_2P_DEC04 +XDEC11 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<3> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC03 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC01 +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_2P_ROWREG6 ACLK_N_I ADDR_I<5> ADDR_I<4> ADDR_I<3> ADDR_I<2> ++ ADDR_I<1> ADDR_I<0> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ++ ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_1024x8_c2_2P_COLDRV13X16 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XI1<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_2P_WLDRV16X16 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX16 +.ENDS + + +.SUBCKT RM_IHPSG13_1024x8_c2_1P_DEC01 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XDEC NADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XI2 VDD VSS / RSC_IHPSG13_FILLCAP4 +XADDRINV ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_1P_DEC00 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XDEC NADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV<1> ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +XADDRINV<0> ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI1 VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_1P_ROWDEC5 ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ++ ADDR_N_I<0> CS_I ECLK_I WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC01 +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC00 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_1024x8_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_1024x8_c2_1P_DEC04 +XI0 ADDR_N_I<5> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_1P_ROWREG5 ACLK_N_I ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ++ ADDR_I<0> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + + +.SUBCKT RM_IHPSG13_1024x8_c2_1P_COLDEC5 ACLK_N ADDR<4> ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<4> BIST_ADDR<3> ++ BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI13<1> addr_int<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_CBUFX2 +XI13<0> addr_int<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XDFF<4> BIST_EN_I BIST_ADDR<4> ACLK_N ADDR<4> addr_int<1> net7<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int<0> net7<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net7<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net7<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net7<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI15<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI15<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI15<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_1P_COLCTRL5 A_ADDR_COL<1> A_ADDR_COL<0> A_ADDR_DEC<7> ++ A_ADDR_DEC<6> A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<31> ++ A_BLC<30> A_BLC<29> A_BLC<28> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> ++ A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC<19> A_BLC<18> A_BLC<17> ++ A_BLC<16> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> ++ A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> ++ A_BLC<1> A_BLC<0> A_BLT<31> A_BLT<30> A_BLT<29> A_BLT<28> A_BLT<27> ++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT<23> A_BLT<22> A_BLT<21> A_BLT<20> ++ A_BLT<19> A_BLT<18> A_BLT<17> A_BLT<16> A_BLT<15> A_BLT<14> A_BLT<13> ++ A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> ++ A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_I80<1> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<1> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I80<0> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<0> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XI80<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_INV<6> A_N1<1> A_P1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<5> A_N0<1> A_P0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<4> A_N0<0> A_P0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<3> A_ADDR_COL<1> A_N1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<2> A_ADDR_COL<1> A_N1<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_ADDR_COL<0> A_N0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL<0> A_N0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_I81<3> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<2> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<1> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_BLTMUX<31> A_BLC<31> A_BLC_SEL A_BLT<31> A_BLT_SEL A_PRE_N A_SEL_P<31> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV +XA_BLTMUX<30> A_BLC<30> A_BLC_SEL A_BLT<30> A_BLT_SEL A_PRE_N A_SEL_P<30> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV +XA_BLTMUX<29> A_BLC<29> A_BLC_SEL A_BLT<29> A_BLT_SEL A_PRE_N A_SEL_P<29> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV +XA_BLTMUX<28> A_BLC<28> A_BLC_SEL A_BLT<28> A_BLT_SEL A_PRE_N A_SEL_P<28> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV +XA_BLTMUX<27> A_BLC<27> A_BLC_SEL A_BLT<27> A_BLT_SEL A_PRE_N A_SEL_P<27> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV +XA_BLTMUX<26> A_BLC<26> A_BLC_SEL A_BLT<26> A_BLT_SEL A_PRE_N A_SEL_P<26> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV +XA_BLTMUX<25> A_BLC<25> A_BLC_SEL A_BLT<25> A_BLT_SEL A_PRE_N A_SEL_P<25> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV +XA_BLTMUX<24> A_BLC<24> A_BLC_SEL A_BLT<24> A_BLT_SEL A_PRE_N A_SEL_P<24> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV +XA_BLTMUX<23> A_BLC<23> A_BLC_SEL A_BLT<23> A_BLT_SEL A_PRE_N A_SEL_P<23> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV +XA_BLTMUX<22> A_BLC<22> A_BLC_SEL A_BLT<22> A_BLT_SEL A_PRE_N A_SEL_P<22> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV +XA_BLTMUX<21> A_BLC<21> A_BLC_SEL A_BLT<21> A_BLT_SEL A_PRE_N A_SEL_P<21> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV +XA_BLTMUX<20> A_BLC<20> A_BLC_SEL A_BLT<20> A_BLT_SEL A_PRE_N A_SEL_P<20> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV +XA_BLTMUX<19> A_BLC<19> A_BLC_SEL A_BLT<19> A_BLT_SEL A_PRE_N A_SEL_P<19> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV +XA_BLTMUX<18> A_BLC<18> A_BLC_SEL A_BLT<18> A_BLT_SEL A_PRE_N A_SEL_P<18> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV +XA_BLTMUX<17> A_BLC<17> A_BLC_SEL A_BLT<17> A_BLT_SEL A_PRE_N A_SEL_P<17> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV +XA_BLTMUX<16> A_BLC<16> A_BLC_SEL A_BLT<16> A_BLT_SEL A_PRE_N A_SEL_P<16> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV +XA_BLTMUX<15> A_BLC<15> A_BLC_SEL A_BLT<15> A_BLT_SEL A_PRE_N A_SEL_P<15> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV +XA_BLTMUX<14> A_BLC<14> A_BLC_SEL A_BLT<14> A_BLT_SEL A_PRE_N A_SEL_P<14> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV +XA_BLTMUX<13> A_BLC<13> A_BLC_SEL A_BLT<13> A_BLT_SEL A_PRE_N A_SEL_P<13> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV +XA_BLTMUX<12> A_BLC<12> A_BLC_SEL A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<12> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV +XA_BLTMUX<11> A_BLC<11> A_BLC_SEL A_BLT<11> A_BLT_SEL A_PRE_N A_SEL_P<11> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV +XA_BLTMUX<10> A_BLC<10> A_BLC_SEL A_BLT<10> A_BLT_SEL A_PRE_N A_SEL_P<10> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV +XA_BLTMUX<9> A_BLC<9> A_BLC_SEL A_BLT<9> A_BLT_SEL A_PRE_N A_SEL_P<9> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV +XA_BLTMUX<8> A_BLC<8> A_BLC_SEL A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<8> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV +XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_SEL_P<7> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV +XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_SEL_P<6> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV +XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_SEL_P<5> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV +XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<4> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_SEL_P<3> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_SEL_P<2> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_SEL_P<1> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<0> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV +XA_CAPS<17> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<16> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<15> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<14> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<13> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<12> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<31> net23<0> A_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<30> net23<1> A_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<29> net23<2> A_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<28> net23<3> A_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<27> net23<4> A_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<26> net23<5> A_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<25> net23<6> A_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<24> net23<7> A_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<23> net23<8> A_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<22> net23<9> A_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<21> net23<10> A_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<20> net23<11> A_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<19> net23<12> A_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<18> net23<13> A_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<17> net23<14> A_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<16> net23<15> A_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<15> net23<16> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<17> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<18> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<19> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<20> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<21> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<22> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<23> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<24> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<25> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<26> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<27> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<28> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<29> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<30> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<31> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net21 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_DEC3<31> A_P1<1> A_P0<1> A_ADDR_DEC<7> net23<0> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<30> A_P1<1> A_P0<1> A_ADDR_DEC<6> net23<1> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<29> A_P1<1> A_P0<1> A_ADDR_DEC<5> net23<2> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<28> A_P1<1> A_P0<1> A_ADDR_DEC<4> net23<3> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<27> A_P1<1> A_P0<1> A_ADDR_DEC<3> net23<4> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<26> A_P1<1> A_P0<1> A_ADDR_DEC<2> net23<5> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<25> A_P1<1> A_P0<1> A_ADDR_DEC<1> net23<6> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<24> A_P1<1> A_P0<1> A_ADDR_DEC<0> net23<7> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<23> A_P1<1> A_N0<1> A_ADDR_DEC<7> net23<8> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<22> A_P1<1> A_N0<1> A_ADDR_DEC<6> net23<9> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<21> A_P1<1> A_N0<1> A_ADDR_DEC<5> net23<10> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<20> A_P1<1> A_N0<1> A_ADDR_DEC<4> net23<11> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<19> A_P1<1> A_N0<1> A_ADDR_DEC<3> net23<12> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<18> A_P1<1> A_N0<1> A_ADDR_DEC<2> net23<13> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<17> A_P1<1> A_N0<1> A_ADDR_DEC<1> net23<14> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<16> A_P1<1> A_N0<1> A_ADDR_DEC<0> net23<15> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<15> A_N1<0> A_P0<0> A_ADDR_DEC<7> net23<16> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<14> A_N1<0> A_P0<0> A_ADDR_DEC<6> net23<17> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<13> A_N1<0> A_P0<0> A_ADDR_DEC<5> net23<18> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<12> A_N1<0> A_P0<0> A_ADDR_DEC<4> net23<19> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<11> A_N1<0> A_P0<0> A_ADDR_DEC<3> net23<20> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<10> A_N1<0> A_P0<0> A_ADDR_DEC<2> net23<21> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<9> A_N1<0> A_P0<0> A_ADDR_DEC<1> net23<22> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<8> A_N1<0> A_P0<0> A_ADDR_DEC<0> net23<23> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<7> A_N1<0> A_N0<0> A_ADDR_DEC<7> net23<24> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<6> A_N1<0> A_N0<0> A_ADDR_DEC<6> net23<25> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<5> A_N1<0> A_N0<0> A_ADDR_DEC<5> net23<26> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<4> A_N1<0> A_N0<0> A_ADDR_DEC<4> net23<27> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<3> A_N1<0> A_N0<0> A_ADDR_DEC<3> net23<28> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<2> A_N1<0> A_N0<0> A_ADDR_DEC<2> net23<29> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<1> A_N1<0> A_N0<0> A_ADDR_DEC<1> net23<30> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<0> A_N1<0> A_N0<0> A_ADDR_DEC<0> net23<31> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS + +.SUBCKT RM_IHPSG13_1024x8_c2_1P_COLDRV13X12 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP8 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_1P_WLDRV16X12 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX12 +.ENDS + + + +.SUBCKT RM_IHPSG13_1024x8_c2_2P_COLDRV13X8 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX8 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_2P_WLDRV16X8 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX8 +.ENDS + + + +.SUBCKT RM_IHPSG13_1024x8_c2_2P_COLDEC2 ACLK_N ADDR<1> ADDR<0> ADDR_COL<1> ADDR_COL<0> ++ ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ADDR_DEC<2> ++ ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI16<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<3> PADR<0> PADR<1> addr_n<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<2> NADR<0> PADR<1> addr_n<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<1> PADR<0> NADR<1> addr_n<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<0> NADR<0> NADR<1> addr_n<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI17<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI17<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI14<3> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_TIEL +XI14<2> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_TIEL +XI14<1> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_TIEL +XI14<0> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_TIEL +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net12<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net12<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI15<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_2P_COLCTRL2 A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<3> A_BLC<2> A_BLC<1> ++ A_BLC<0> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_DEC<3> B_ADDR_DEC<2> ++ B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I B_BIST_EN_I B_BLC<3> ++ B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I ++ B_DCLK_B_L B_DCLK_B_R B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R ++ B_RCLK_L B_RCLK_R B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD ++ VSS +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net046 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net045 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XB_CAPS VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS VDD VSS / RSC_IHPSG13_FILLCAP4 +XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XB_I80 B_RCLK_B_L B_WCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2 +XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I80 A_RCLK_B_L A_WCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XB_I44 B_WCLK_B_L B_BM_N B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I44 A_WCLK_B_L A_BM_N A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XB_I81 net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XAB_BLMUX A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> ++ B_BLC<0> B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N ++ B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_1024x8_c2_2P_BLDRV +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net039 net040 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I51 net039 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_2P_COLDRV13_FILL4C2 VDD VSS +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_1024x8_c2_2P_ROWDEC7 ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ++ ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<127> WL_O<126> ++ WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> ++ WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> ++ WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> WL_O<105> ++ WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> WL_O<98> WL_O<97> ++ WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> WL_O<90> WL_O<89> ++ WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> WL_O<82> WL_O<81> ++ WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> WL_O<74> WL_O<73> ++ WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> WL_O<66> WL_O<65> ++ WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> WL_O<58> WL_O<57> ++ WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> WL_O<50> WL_O<49> ++ WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> WL_O<42> WL_O<41> ++ WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> WL_O<34> WL_O<33> ++ WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> WL_O<26> WL_O<25> ++ WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> WL_O<18> WL_O<17> ++ WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_1024x8_c2_2P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_1024x8_c2_2P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_1024x8_c2_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_1024x8_c2_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_1024x8_c2_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_1024x8_c2_2P_DEC04 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC03 +XDEC01<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC01 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC02 +XDEC00<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_1024x8_c2_2P_DEC00 +XI0 ADDR_N_I<7> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_2P_ROWREG7 ACLK_N_I ADDR_I<6> ADDR_I<5> ADDR_I<4> ADDR_I<3> ++ ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<6> ++ BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> ++ BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<0> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_1024x8_c2_2P_ROWDEC4 ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> ++ CS_I ECLK_I WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XSEL ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ECLK_H<1> ++ ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> ++ WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> ++ WL_O<0> VDD VSS / RM_IHPSG13_1024x8_c2_2P_DEC04 +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_2P_ROWREG4 ACLK_N_I ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net7<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net7<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net7<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net7<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_1024x8_c2_1P_BITKIT_TAP BLC BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_TAP A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ VDD_CORE VSS +XITAP<1> A_BLC<1> A_BLT<1> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_1024x8_c2_1P_BITKIT_TAP +XITAP<0> A_BLC<0> A_BLT<0> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_1024x8_c2_1P_BITKIT_TAP +XIEDGEBP_COL1<1> BLC<1> BLT<1> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_EDGE_TB +XIEDGEBP_COL1<0> BLC<1> BLT<1> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_EDGE_TB +XIEDGEBP_COL2<1> BLC<0> BLT<0> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_EDGE_TB +XIEDGEBP_COL2<0> BLC<0> BLT<0> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_EDGE_TB +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_TAP_LR VDD_CORE VSS +XCORNER<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x8_c2_1P_BITKIT_CORNER +XCORNER<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x8_c2_1P_BITKIT_CORNER +XTAP_BORDER VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_1024x8_c2_1P_BITKIT_TAP_LR +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_1P_DEC03 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI0 VDD VSS / RSC_IHPSG13_FILLCAP4 +XDEC ADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_1P_DEC02 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XDEC ADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XI2 VDD VSS / RSC_IHPSG13_FILLCAP4 +XADDRINV ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_1P_ROWDEC8 ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ++ ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<255> ++ WL_O<254> WL_O<253> WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> ++ WL_O<247> WL_O<246> WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> ++ WL_O<240> WL_O<239> WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> ++ WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> ++ WL_O<226> WL_O<225> WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> ++ WL_O<205> WL_O<204> WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> ++ WL_O<198> WL_O<197> WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> ++ WL_O<191> WL_O<190> WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> ++ WL_O<184> WL_O<183> WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> ++ WL_O<177> WL_O<176> WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> ++ WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> ++ WL_O<163> WL_O<162> WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> ++ WL_O<156> WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> ++ WL_O<149> WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> ++ WL_O<142> WL_O<141> WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> ++ WL_O<135> WL_O<134> WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> ++ WL_O<128> WL_O<127> WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> ++ WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> ++ WL_O<114> WL_O<113> WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> ++ WL_O<92> WL_O<91> WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> ++ WL_O<84> WL_O<83> WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> ++ WL_O<76> WL_O<75> WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> ++ WL_O<68> WL_O<67> WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> ++ WL_O<60> WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> ++ WL_O<52> WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> ++ WL_O<44> WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> ++ WL_O<36> WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> ++ WL_O<28> WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> ++ WL_O<20> WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> ++ WL_O<12> WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> ++ WL_O<3> WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC11<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<3> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<15> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<11> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC03 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC10<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<2> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<14> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<10> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC02 +XDEC00<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<12> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<8> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC00 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_1024x8_c2_1P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_1024x8_c2_1P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_1024x8_c2_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_1024x8_c2_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_1024x8_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_1024x8_c2_1P_DEC04 +XDEC01<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<13> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<9> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC01 +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_1P_ROWREG8 ACLK_N_I ADDR_I<7> ADDR_I<6> ADDR_I<5> ADDR_I<4> ++ ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<7> ADDR_N_O<6> ADDR_N_O<5> ++ ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<7> ++ BIST_ADDR_I<6> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> ++ BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + +.SUBCKT RM_IHPSG13_1024x8_c2_1P_ROWDEC9 ADDR_N_I<8> ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ++ ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ++ WL_O<511> WL_O<510> WL_O<509> WL_O<508> WL_O<507> WL_O<506> WL_O<505> ++ WL_O<504> WL_O<503> WL_O<502> WL_O<501> WL_O<500> WL_O<499> WL_O<498> ++ WL_O<497> WL_O<496> WL_O<495> WL_O<494> WL_O<493> WL_O<492> WL_O<491> ++ WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> WL_O<484> ++ WL_O<483> WL_O<482> WL_O<481> WL_O<480> WL_O<479> WL_O<478> WL_O<477> ++ WL_O<476> WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> ++ WL_O<469> WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> WL_O<463> ++ WL_O<462> WL_O<461> WL_O<460> WL_O<459> WL_O<458> WL_O<457> WL_O<456> ++ WL_O<455> WL_O<454> WL_O<453> WL_O<452> WL_O<451> WL_O<450> WL_O<449> ++ WL_O<448> WL_O<447> WL_O<446> WL_O<445> WL_O<444> WL_O<443> WL_O<442> ++ WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> WL_O<436> WL_O<435> ++ WL_O<434> WL_O<433> WL_O<432> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> WL_O<415> WL_O<414> ++ WL_O<413> WL_O<412> WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> ++ WL_O<406> WL_O<405> WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> ++ WL_O<399> WL_O<398> WL_O<397> WL_O<396> WL_O<395> WL_O<394> WL_O<393> ++ WL_O<392> WL_O<391> WL_O<390> WL_O<389> WL_O<388> WL_O<387> WL_O<386> ++ WL_O<385> WL_O<384> WL_O<383> WL_O<382> WL_O<381> WL_O<380> WL_O<379> ++ WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> WL_O<372> ++ WL_O<371> WL_O<370> WL_O<369> WL_O<368> WL_O<367> WL_O<366> WL_O<365> ++ WL_O<364> WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> ++ WL_O<357> WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> WL_O<351> ++ WL_O<350> WL_O<349> WL_O<348> WL_O<347> WL_O<346> WL_O<345> WL_O<344> ++ WL_O<343> WL_O<342> WL_O<341> WL_O<340> WL_O<339> WL_O<338> WL_O<337> ++ WL_O<336> WL_O<335> WL_O<334> WL_O<333> WL_O<332> WL_O<331> WL_O<330> ++ WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> WL_O<324> WL_O<323> ++ WL_O<322> WL_O<321> WL_O<320> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> WL_O<303> WL_O<302> ++ WL_O<301> WL_O<300> WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> ++ WL_O<294> WL_O<293> WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> ++ WL_O<287> WL_O<286> WL_O<285> WL_O<284> WL_O<283> WL_O<282> WL_O<281> ++ WL_O<280> WL_O<279> WL_O<278> WL_O<277> WL_O<276> WL_O<275> WL_O<274> ++ WL_O<273> WL_O<272> WL_O<271> WL_O<270> WL_O<269> WL_O<268> WL_O<267> ++ WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> WL_O<260> ++ WL_O<259> WL_O<258> WL_O<257> WL_O<256> WL_O<255> WL_O<254> WL_O<253> ++ WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> ++ WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> WL_O<239> ++ WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> WL_O<233> WL_O<232> ++ WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> WL_O<226> WL_O<225> ++ WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> WL_O<219> WL_O<218> ++ WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> WL_O<212> WL_O<211> ++ WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> WL_O<191> WL_O<190> ++ WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> ++ WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> ++ WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> WL_O<170> WL_O<169> ++ WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> WL_O<163> WL_O<162> ++ WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> WL_O<156> WL_O<155> ++ WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> WL_O<148> ++ WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> WL_O<142> WL_O<141> ++ WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> ++ WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> WL_O<127> ++ WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> ++ WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> ++ WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> ++ WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> ++ WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XL2<172> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<171> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<170> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<169> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<168> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<167> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<166> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<165> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<164> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<163> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<162> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<161> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<160> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<159> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<158> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<157> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<156> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<155> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<154> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<153> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<152> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<151> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<150> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<149> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<148> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<147> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<146> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<145> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<144> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<143> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<142> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<141> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<140> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<139> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<138> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<137> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<136> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<135> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<134> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<133> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC11<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<7> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC03 +XDEC11<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<3> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC03 +XDEC11<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<31> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC03 +XDEC11<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<27> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC03 +XDEC11<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<23> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC03 +XDEC11<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<19> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<15> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<11> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<7> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<3> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC03 +XDEC00<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC00 +XDEC00<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<4> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC00 +XDEC00<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<0> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC00 +XDEC00<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<28> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC00 +XDEC00<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<24> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC00 +XDEC00<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<20> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC00 +XDEC00<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<16> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<12> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<8> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<4> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<0> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC00 +XSEL<31> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<31> ECLK_H<31> ++ ECLK_H<32> ECLK_B<31> ECLK_B<32> WL_O<511> WL_O<510> WL_O<509> WL_O<508> ++ WL_O<507> WL_O<506> WL_O<505> WL_O<504> WL_O<503> WL_O<502> WL_O<501> ++ WL_O<500> WL_O<499> WL_O<498> WL_O<497> WL_O<496> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC04 +XSEL<30> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<30> ECLK_H<30> ++ ECLK_H<31> ECLK_B<30> ECLK_B<31> WL_O<495> WL_O<494> WL_O<493> WL_O<492> ++ WL_O<491> WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> ++ WL_O<484> WL_O<483> WL_O<482> WL_O<481> WL_O<480> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC04 +XSEL<29> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<29> ECLK_H<29> ++ ECLK_H<30> ECLK_B<29> ECLK_B<30> WL_O<479> WL_O<478> WL_O<477> WL_O<476> ++ WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> WL_O<469> ++ WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC04 +XSEL<28> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<28> ECLK_H<28> ++ ECLK_H<29> ECLK_B<28> ECLK_B<29> WL_O<463> WL_O<462> WL_O<461> WL_O<460> ++ WL_O<459> WL_O<458> WL_O<457> WL_O<456> WL_O<455> WL_O<454> WL_O<453> ++ WL_O<452> WL_O<451> WL_O<450> WL_O<449> WL_O<448> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC04 +XSEL<27> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<27> ECLK_H<27> ++ ECLK_H<28> ECLK_B<27> ECLK_B<28> WL_O<447> WL_O<446> WL_O<445> WL_O<444> ++ WL_O<443> WL_O<442> WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> ++ WL_O<436> WL_O<435> WL_O<434> WL_O<433> WL_O<432> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC04 +XSEL<26> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<26> ECLK_H<26> ++ ECLK_H<27> ECLK_B<26> ECLK_B<27> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC04 +XSEL<25> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<25> ECLK_H<25> ++ ECLK_H<26> ECLK_B<25> ECLK_B<26> WL_O<415> WL_O<414> WL_O<413> WL_O<412> ++ WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> WL_O<406> WL_O<405> ++ WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC04 +XSEL<24> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<24> ECLK_H<24> ++ ECLK_H<25> ECLK_B<24> ECLK_B<25> WL_O<399> WL_O<398> WL_O<397> WL_O<396> ++ WL_O<395> WL_O<394> WL_O<393> WL_O<392> WL_O<391> WL_O<390> WL_O<389> ++ WL_O<388> WL_O<387> WL_O<386> WL_O<385> WL_O<384> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC04 +XSEL<23> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<23> ECLK_H<23> ++ ECLK_H<24> ECLK_B<23> ECLK_B<24> WL_O<383> WL_O<382> WL_O<381> WL_O<380> ++ WL_O<379> WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> ++ WL_O<372> WL_O<371> WL_O<370> WL_O<369> WL_O<368> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC04 +XSEL<22> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<22> ECLK_H<22> ++ ECLK_H<23> ECLK_B<22> ECLK_B<23> WL_O<367> WL_O<366> WL_O<365> WL_O<364> ++ WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> WL_O<357> ++ WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC04 +XSEL<21> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<21> ECLK_H<21> ++ ECLK_H<22> ECLK_B<21> ECLK_B<22> WL_O<351> WL_O<350> WL_O<349> WL_O<348> ++ WL_O<347> WL_O<346> WL_O<345> WL_O<344> WL_O<343> WL_O<342> WL_O<341> ++ WL_O<340> WL_O<339> WL_O<338> WL_O<337> WL_O<336> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC04 +XSEL<20> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<20> ECLK_H<20> ++ ECLK_H<21> ECLK_B<20> ECLK_B<21> WL_O<335> WL_O<334> WL_O<333> WL_O<332> ++ WL_O<331> WL_O<330> WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> ++ WL_O<324> WL_O<323> WL_O<322> WL_O<321> WL_O<320> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC04 +XSEL<19> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<19> ECLK_H<19> ++ ECLK_H<20> ECLK_B<19> ECLK_B<20> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC04 +XSEL<18> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<18> ECLK_H<18> ++ ECLK_H<19> ECLK_B<18> ECLK_B<19> WL_O<303> WL_O<302> WL_O<301> WL_O<300> ++ WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> WL_O<294> WL_O<293> ++ WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC04 +XSEL<17> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<17> ECLK_H<17> ++ ECLK_H<18> ECLK_B<17> ECLK_B<18> WL_O<287> WL_O<286> WL_O<285> WL_O<284> ++ WL_O<283> WL_O<282> WL_O<281> WL_O<280> WL_O<279> WL_O<278> WL_O<277> ++ WL_O<276> WL_O<275> WL_O<274> WL_O<273> WL_O<272> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC04 +XSEL<16> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<16> ECLK_H<16> ++ ECLK_H<17> ECLK_B<16> ECLK_B<17> WL_O<271> WL_O<270> WL_O<269> WL_O<268> ++ WL_O<267> WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> ++ WL_O<260> WL_O<259> WL_O<258> WL_O<257> WL_O<256> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC04 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_1024x8_c2_1P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_1024x8_c2_1P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_1024x8_c2_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_1024x8_c2_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_1024x8_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_1024x8_c2_1P_DEC04 +XDEC01<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC01 +XDEC01<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<5> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC01 +XDEC01<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<1> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC01 +XDEC01<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<29> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC01 +XDEC01<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<25> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC01 +XDEC01<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<21> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC01 +XDEC01<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<17> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<13> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<9> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<5> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<1> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC01 +XDEC10<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<6> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC02 +XDEC10<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<2> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC02 +XDEC10<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<30> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC02 +XDEC10<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<26> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC02 +XDEC10<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<22> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC02 +XDEC10<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<18> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<14> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<10> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<6> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<2> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC02 +XI0 ADDR_N_I<9> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_1P_ROWREG9 ACLK_N_I ADDR_I<8> ADDR_I<7> ADDR_I<6> ADDR_I<5> ++ ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<8> ADDR_N_O<7> ++ ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ++ ADDR_N_O<0> BIST_ADDR_I<8> BIST_ADDR_I<7> BIST_ADDR_I<6> BIST_ADDR_I<5> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XINV<8> q_int<8> qn_int<8> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<8> qn_int<8> ADDR_N_O<8> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<8> BIST_EN_I BIST_ADDR_I<8> ACLK_N_I ADDR_I<8> q_int<8> net04<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net04<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net04<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net04<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net04<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net04<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net04<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net04<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net04<8> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +.ENDS + +.SUBCKT RM_IHPSG13_1024x8_c2_1P_ROWDEC7 ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ++ ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<127> WL_O<126> ++ WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> ++ WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> ++ WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> WL_O<105> ++ WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> WL_O<98> WL_O<97> ++ WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> WL_O<90> WL_O<89> ++ WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> WL_O<82> WL_O<81> ++ WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> WL_O<74> WL_O<73> ++ WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> WL_O<66> WL_O<65> ++ WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> WL_O<58> WL_O<57> ++ WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> WL_O<50> WL_O<49> ++ WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> WL_O<42> WL_O<41> ++ WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> WL_O<34> WL_O<33> ++ WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> WL_O<26> WL_O<25> ++ WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> WL_O<18> WL_O<17> ++ WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC03 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC02 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_1024x8_c2_1P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_1024x8_c2_1P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_1024x8_c2_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_1024x8_c2_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_1024x8_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_1024x8_c2_1P_DEC04 +XDEC00<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC00 +XDEC01<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC01 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0 ADDR_N_I<7> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_1P_ROWREG7 ACLK_N_I ADDR_I<6> ADDR_I<5> ADDR_I<4> ADDR_I<3> ++ ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<6> ++ BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> ++ BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + +.SUBCKT RM_IHPSG13_1024x8_c2_1P_COLDRV13X8 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_1P_WLDRV16X8 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX8 +.ENDS + + + +.SUBCKT RM_IHPSG13_1024x8_c2_1P_ROWDEC6 ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ++ ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<63> WL_O<62> WL_O<61> WL_O<60> ++ WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> ++ WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> ++ WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> ++ WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> ++ WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> ++ WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> ++ WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> ++ WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC11 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<3> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC03 +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC00 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC01 +XDEC10 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<2> VDD VSS / ++ RM_IHPSG13_1024x8_c2_1P_DEC02 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_1024x8_c2_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_1024x8_c2_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_1024x8_c2_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_1024x8_c2_1P_DEC04 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_1024x8_c2_1P_ROWREG6 ACLK_N_I ADDR_I<5> ADDR_I<4> ADDR_I<3> ADDR_I<2> ++ ADDR_I<1> ADDR_I<0> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ++ ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + + +.SUBCKT RM_IHPSG13_1024x8_c2_1P_COLUMN_pcell_0 A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<255> A_LWL<254> A_LWL<253> A_LWL<252> A_LWL<251> A_LWL<250> A_LWL<249> A_LWL<248> A_LWL<247> A_LWL<246> A_LWL<245> A_LWL<244> A_LWL<243> A_LWL<242> A_LWL<241> A_LWL<240> A_LWL<239> A_LWL<238> A_LWL<237> A_LWL<236> A_LWL<235> A_LWL<234> A_LWL<233> A_LWL<232> A_LWL<231> A_LWL<230> A_LWL<229> A_LWL<228> A_LWL<227> A_LWL<226> A_LWL<225> A_LWL<224> A_LWL<223> A_LWL<222> A_LWL<221> A_LWL<220> A_LWL<219> A_LWL<218> A_LWL<217> A_LWL<216> A_LWL<215> A_LWL<214> A_LWL<213> A_LWL<212> A_LWL<211> A_LWL<210> A_LWL<209> A_LWL<208> A_LWL<207> A_LWL<206> A_LWL<205> A_LWL<204> A_LWL<203> A_LWL<202> A_LWL<201> A_LWL<200> A_LWL<199> A_LWL<198> A_LWL<197> A_LWL<196> A_LWL<195> A_LWL<194> A_LWL<193> A_LWL<192> A_LWL<191> A_LWL<190> A_LWL<189> A_LWL<188> A_LWL<187> A_LWL<186> A_LWL<185> A_LWL<184> A_LWL<183> A_LWL<182> A_LWL<181> A_LWL<180> A_LWL<179> A_LWL<178> A_LWL<177> A_LWL<176> A_LWL<175> A_LWL<174> A_LWL<173> A_LWL<172> A_LWL<171> A_LWL<170> A_LWL<169> A_LWL<168> A_LWL<167> A_LWL<166> A_LWL<165> A_LWL<164> A_LWL<163> A_LWL<162> A_LWL<161> A_LWL<160> A_LWL<159> A_LWL<158> A_LWL<157> A_LWL<156> A_LWL<155> A_LWL<154> A_LWL<153> A_LWL<152> A_LWL<151> A_LWL<150> A_LWL<149> A_LWL<148> A_LWL<147> A_LWL<146> A_LWL<145> A_LWL<144> A_LWL<143> A_LWL<142> A_LWL<141> A_LWL<140> A_LWL<139> A_LWL<138> A_LWL<137> A_LWL<136> A_LWL<135> A_LWL<134> A_LWL<133> A_LWL<132> A_LWL<131> A_LWL<130> A_LWL<129> A_LWL<128> A_LWL<127> A_LWL<126> A_LWL<125> A_LWL<124> A_LWL<123> A_LWL<122> A_LWL<121> A_LWL<120> A_LWL<119> A_LWL<118> A_LWL<117> A_LWL<116> A_LWL<115> A_LWL<114> A_LWL<113> A_LWL<112> A_LWL<111> A_LWL<110> A_LWL<109> A_LWL<108> A_LWL<107> A_LWL<106> A_LWL<105> A_LWL<104> A_LWL<103> A_LWL<102> A_LWL<101> A_LWL<100> A_LWL<99> A_LWL<98> A_LWL<97> A_LWL<96> A_LWL<95> A_LWL<94> A_LWL<93> A_LWL<92> A_LWL<91> A_LWL<90> A_LWL<89> A_LWL<88> A_LWL<87> A_LWL<86> A_LWL<85> A_LWL<84> A_LWL<83> A_LWL<82> A_LWL<81> A_LWL<80> A_LWL<79> A_LWL<78> A_LWL<77> A_LWL<76> A_LWL<75> A_LWL<74> A_LWL<73> A_LWL<72> A_LWL<71> A_LWL<70> A_LWL<69> A_LWL<68> A_LWL<67> A_LWL<66> A_LWL<65> A_LWL<64> A_LWL<63> A_LWL<62> A_LWL<61> A_LWL<60> A_LWL<59> A_LWL<58> A_LWL<57> A_LWL<56> A_LWL<55> A_LWL<54> A_LWL<53> A_LWL<52> A_LWL<51> A_LWL<50> A_LWL<49> A_LWL<48> A_LWL<47> A_LWL<46> A_LWL<45> A_LWL<44> A_LWL<43> A_LWL<42> A_LWL<41> A_LWL<40> A_LWL<39> A_LWL<38> A_LWL<37> A_LWL<36> A_LWL<35> A_LWL<34> A_LWL<33> A_LWL<32> A_LWL<31> A_LWL<30> A_LWL<29> A_LWL<28> A_LWL<27> A_LWL<26> A_LWL<25> A_LWL<24> A_LWL<23> A_LWL<22> A_LWL<21> A_LWL<20> A_LWL<19> A_LWL<18> A_LWL<17> A_LWL<16> A_LWL<15> A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<255> A_RWL<254> A_RWL<253> A_RWL<252> A_RWL<251> A_RWL<250> A_RWL<249> A_RWL<248> A_RWL<247> A_RWL<246> A_RWL<245> A_RWL<244> A_RWL<243> A_RWL<242> A_RWL<241> A_RWL<240> A_RWL<239> A_RWL<238> A_RWL<237> A_RWL<236> A_RWL<235> A_RWL<234> A_RWL<233> A_RWL<232> A_RWL<231> A_RWL<230> A_RWL<229> A_RWL<228> A_RWL<227> A_RWL<226> A_RWL<225> A_RWL<224> A_RWL<223> A_RWL<222> A_RWL<221> A_RWL<220> A_RWL<219> A_RWL<218> A_RWL<217> A_RWL<216> A_RWL<215> A_RWL<214> A_RWL<213> A_RWL<212> A_RWL<211> A_RWL<210> A_RWL<209> A_RWL<208> A_RWL<207> A_RWL<206> A_RWL<205> A_RWL<204> A_RWL<203> A_RWL<202> A_RWL<201> A_RWL<200> A_RWL<199> A_RWL<198> A_RWL<197> A_RWL<196> A_RWL<195> A_RWL<194> A_RWL<193> A_RWL<192> A_RWL<191> A_RWL<190> A_RWL<189> A_RWL<188> A_RWL<187> A_RWL<186> A_RWL<185> A_RWL<184> A_RWL<183> A_RWL<182> A_RWL<181> A_RWL<180> A_RWL<179> A_RWL<178> A_RWL<177> A_RWL<176> A_RWL<175> A_RWL<174> A_RWL<173> A_RWL<172> A_RWL<171> A_RWL<170> A_RWL<169> A_RWL<168> A_RWL<167> A_RWL<166> A_RWL<165> A_RWL<164> A_RWL<163> A_RWL<162> A_RWL<161> A_RWL<160> A_RWL<159> A_RWL<158> A_RWL<157> A_RWL<156> A_RWL<155> A_RWL<154> A_RWL<153> A_RWL<152> A_RWL<151> A_RWL<150> A_RWL<149> A_RWL<148> A_RWL<147> A_RWL<146> A_RWL<145> A_RWL<144> A_RWL<143> A_RWL<142> A_RWL<141> A_RWL<140> A_RWL<139> A_RWL<138> A_RWL<137> A_RWL<136> A_RWL<135> A_RWL<134> A_RWL<133> A_RWL<132> A_RWL<131> A_RWL<130> A_RWL<129> A_RWL<128> A_RWL<127> A_RWL<126> A_RWL<125> A_RWL<124> A_RWL<123> A_RWL<122> A_RWL<121> A_RWL<120> A_RWL<119> A_RWL<118> A_RWL<117> A_RWL<116> A_RWL<115> A_RWL<114> A_RWL<113> A_RWL<112> A_RWL<111> A_RWL<110> A_RWL<109> A_RWL<108> A_RWL<107> A_RWL<106> A_RWL<105> A_RWL<104> A_RWL<103> A_RWL<102> A_RWL<101> A_RWL<100> A_RWL<99> A_RWL<98> A_RWL<97> A_RWL<96> A_RWL<95> A_RWL<94> A_RWL<93> A_RWL<92> A_RWL<91> A_RWL<90> A_RWL<89> A_RWL<88> A_RWL<87> A_RWL<86> A_RWL<85> A_RWL<84> A_RWL<83> A_RWL<82> A_RWL<81> A_RWL<80> A_RWL<79> A_RWL<78> A_RWL<77> A_RWL<76> A_RWL<75> A_RWL<74> A_RWL<73> A_RWL<72> A_RWL<71> A_RWL<70> A_RWL<69> A_RWL<68> A_RWL<67> A_RWL<66> A_RWL<65> A_RWL<64> A_RWL<63> A_RWL<62> A_RWL<61> A_RWL<60> A_RWL<59> A_RWL<58> A_RWL<57> A_RWL<56> A_RWL<55> A_RWL<54> A_RWL<53> A_RWL<52> A_RWL<51> A_RWL<50> A_RWL<49> A_RWL<48> A_RWL<47> A_RWL<46> A_RWL<45> A_RWL<44> A_RWL<43> A_RWL<42> A_RWL<41> A_RWL<40> A_RWL<39> A_RWL<38> A_RWL<37> A_RWL<36> A_RWL<35> A_RWL<34> A_RWL<33> A_RWL<32> A_RWL<31> A_RWL<30> A_RWL<29> A_RWL<28> A_RWL<27> A_RWL<26> A_RWL<25> A_RWL<24> A_RWL<23> A_RWL<22> A_RWL<21> A_RWL<20> A_RWL<19> A_RWL<18> A_RWL<17> A_RWL<16> A_RWL<15> A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> VDD_CORE VSS +XRAM<16> A_BLC<29> A_BLC<28> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT<29> A_BLT<28> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<255> A_LWL<254> A_LWL<253> A_LWL<252> A_LWL<251> A_LWL<250> A_LWL<249> A_LWL<248> A_LWL<247> A_LWL<246> A_LWL<245> A_LWL<244> A_LWL<243> A_LWL<242> A_LWL<241> A_LWL<240> A_RWL<255> A_RWL<254> A_RWL<253> A_RWL<252> A_RWL<251> A_RWL<250> A_RWL<249> A_RWL<248> A_RWL<247> A_RWL<246> A_RWL<245> A_RWL<244> A_RWL<243> A_RWL<242> A_RWL<241> A_RWL<240> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_SRAM +XRAM<15> A_BLC<27> A_BLC<26> A_BLC<29> A_BLC<28> A_BLT<27> A_BLT<26> A_BLT<29> A_BLT<28> A_LWL<239> A_LWL<238> A_LWL<237> A_LWL<236> A_LWL<235> A_LWL<234> A_LWL<233> A_LWL<232> A_LWL<231> A_LWL<230> A_LWL<229> A_LWL<228> A_LWL<227> A_LWL<226> A_LWL<225> A_LWL<224> A_RWL<239> A_RWL<238> A_RWL<237> A_RWL<236> A_RWL<235> A_RWL<234> A_RWL<233> A_RWL<232> A_RWL<231> A_RWL<230> A_RWL<229> A_RWL<228> A_RWL<227> A_RWL<226> A_RWL<225> A_RWL<224> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_SRAM +XRAM<14> A_BLC<25> A_BLC<24> A_BLC<27> A_BLC<26> A_BLT<25> A_BLT<24> A_BLT<27> A_BLT<26> A_LWL<223> A_LWL<222> A_LWL<221> A_LWL<220> A_LWL<219> A_LWL<218> A_LWL<217> A_LWL<216> A_LWL<215> A_LWL<214> A_LWL<213> A_LWL<212> A_LWL<211> A_LWL<210> A_LWL<209> A_LWL<208> A_RWL<223> A_RWL<222> A_RWL<221> A_RWL<220> A_RWL<219> A_RWL<218> A_RWL<217> A_RWL<216> A_RWL<215> A_RWL<214> A_RWL<213> A_RWL<212> A_RWL<211> A_RWL<210> A_RWL<209> A_RWL<208> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_SRAM +XRAM<13> A_BLC<23> A_BLC<22> A_BLC<25> A_BLC<24> A_BLT<23> A_BLT<22> A_BLT<25> A_BLT<24> A_LWL<207> A_LWL<206> A_LWL<205> A_LWL<204> A_LWL<203> A_LWL<202> A_LWL<201> A_LWL<200> A_LWL<199> A_LWL<198> A_LWL<197> A_LWL<196> A_LWL<195> A_LWL<194> A_LWL<193> A_LWL<192> A_RWL<207> A_RWL<206> A_RWL<205> A_RWL<204> A_RWL<203> A_RWL<202> A_RWL<201> A_RWL<200> A_RWL<199> A_RWL<198> A_RWL<197> A_RWL<196> A_RWL<195> A_RWL<194> A_RWL<193> A_RWL<192> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_SRAM +XRAM<12> A_BLC<21> A_BLC<20> A_BLC<23> A_BLC<22> A_BLT<21> A_BLT<20> A_BLT<23> A_BLT<22> A_LWL<191> A_LWL<190> A_LWL<189> A_LWL<188> A_LWL<187> A_LWL<186> A_LWL<185> A_LWL<184> A_LWL<183> A_LWL<182> A_LWL<181> A_LWL<180> A_LWL<179> A_LWL<178> A_LWL<177> A_LWL<176> A_RWL<191> A_RWL<190> A_RWL<189> A_RWL<188> A_RWL<187> A_RWL<186> A_RWL<185> A_RWL<184> A_RWL<183> A_RWL<182> A_RWL<181> A_RWL<180> A_RWL<179> A_RWL<178> A_RWL<177> A_RWL<176> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_SRAM +XRAM<11> A_BLC<19> A_BLC<18> A_BLC<21> A_BLC<20> A_BLT<19> A_BLT<18> A_BLT<21> A_BLT<20> A_LWL<175> A_LWL<174> A_LWL<173> A_LWL<172> A_LWL<171> A_LWL<170> A_LWL<169> A_LWL<168> A_LWL<167> A_LWL<166> A_LWL<165> A_LWL<164> A_LWL<163> A_LWL<162> A_LWL<161> A_LWL<160> A_RWL<175> A_RWL<174> A_RWL<173> A_RWL<172> A_RWL<171> A_RWL<170> A_RWL<169> A_RWL<168> A_RWL<167> A_RWL<166> A_RWL<165> A_RWL<164> A_RWL<163> A_RWL<162> A_RWL<161> A_RWL<160> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_SRAM +XRAM<10> A_BLC<17> A_BLC<16> A_BLC<19> A_BLC<18> A_BLT<17> A_BLT<16> A_BLT<19> A_BLT<18> A_LWL<159> A_LWL<158> A_LWL<157> A_LWL<156> A_LWL<155> A_LWL<154> A_LWL<153> A_LWL<152> A_LWL<151> A_LWL<150> A_LWL<149> A_LWL<148> A_LWL<147> A_LWL<146> A_LWL<145> A_LWL<144> A_RWL<159> A_RWL<158> A_RWL<157> A_RWL<156> A_RWL<155> A_RWL<154> A_RWL<153> A_RWL<152> A_RWL<151> A_RWL<150> A_RWL<149> A_RWL<148> A_RWL<147> A_RWL<146> A_RWL<145> A_RWL<144> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_SRAM +XRAM<9> A_BLC<15> A_BLC<14> A_BLC<17> A_BLC<16> A_BLT<15> A_BLT<14> A_BLT<17> A_BLT<16> A_LWL<143> A_LWL<142> A_LWL<141> A_LWL<140> A_LWL<139> A_LWL<138> A_LWL<137> A_LWL<136> A_LWL<135> A_LWL<134> A_LWL<133> A_LWL<132> A_LWL<131> A_LWL<130> A_LWL<129> A_LWL<128> A_RWL<143> A_RWL<142> A_RWL<141> A_RWL<140> A_RWL<139> A_RWL<138> A_RWL<137> A_RWL<136> A_RWL<135> A_RWL<134> A_RWL<133> A_RWL<132> A_RWL<131> A_RWL<130> A_RWL<129> A_RWL<128> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_SRAM +XRAM<8> A_BLC<13> A_BLC<12> A_BLC<15> A_BLC<14> A_BLT<13> A_BLT<12> A_BLT<15> A_BLT<14> A_LWL<127> A_LWL<126> A_LWL<125> A_LWL<124> A_LWL<123> A_LWL<122> A_LWL<121> A_LWL<120> A_LWL<119> A_LWL<118> A_LWL<117> A_LWL<116> A_LWL<115> A_LWL<114> A_LWL<113> A_LWL<112> A_RWL<127> A_RWL<126> A_RWL<125> A_RWL<124> A_RWL<123> A_RWL<122> A_RWL<121> A_RWL<120> A_RWL<119> A_RWL<118> A_RWL<117> A_RWL<116> A_RWL<115> A_RWL<114> A_RWL<113> A_RWL<112> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_SRAM +XRAM<7> A_BLC<11> A_BLC<10> A_BLC<13> A_BLC<12> A_BLT<11> A_BLT<10> A_BLT<13> A_BLT<12> A_LWL<111> A_LWL<110> A_LWL<109> A_LWL<108> A_LWL<107> A_LWL<106> A_LWL<105> A_LWL<104> A_LWL<103> A_LWL<102> A_LWL<101> A_LWL<100> A_LWL<99> A_LWL<98> A_LWL<97> A_LWL<96> A_RWL<111> A_RWL<110> A_RWL<109> A_RWL<108> A_RWL<107> A_RWL<106> A_RWL<105> A_RWL<104> A_RWL<103> A_RWL<102> A_RWL<101> A_RWL<100> A_RWL<99> A_RWL<98> A_RWL<97> A_RWL<96> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_SRAM +XRAM<6> A_BLC<9> A_BLC<8> A_BLC<11> A_BLC<10> A_BLT<9> A_BLT<8> A_BLT<11> A_BLT<10> A_LWL<95> A_LWL<94> A_LWL<93> A_LWL<92> A_LWL<91> A_LWL<90> A_LWL<89> A_LWL<88> A_LWL<87> A_LWL<86> A_LWL<85> A_LWL<84> A_LWL<83> A_LWL<82> A_LWL<81> A_LWL<80> A_RWL<95> A_RWL<94> A_RWL<93> A_RWL<92> A_RWL<91> A_RWL<90> A_RWL<89> A_RWL<88> A_RWL<87> A_RWL<86> A_RWL<85> A_RWL<84> A_RWL<83> A_RWL<82> A_RWL<81> A_RWL<80> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_SRAM +XRAM<5> A_BLC<7> A_BLC<6> A_BLC<9> A_BLC<8> A_BLT<7> A_BLT<6> A_BLT<9> A_BLT<8> A_LWL<79> A_LWL<78> A_LWL<77> A_LWL<76> A_LWL<75> A_LWL<74> A_LWL<73> A_LWL<72> A_LWL<71> A_LWL<70> A_LWL<69> A_LWL<68> A_LWL<67> A_LWL<66> A_LWL<65> A_LWL<64> A_RWL<79> A_RWL<78> A_RWL<77> A_RWL<76> A_RWL<75> A_RWL<74> A_RWL<73> A_RWL<72> A_RWL<71> A_RWL<70> A_RWL<69> A_RWL<68> A_RWL<67> A_RWL<66> A_RWL<65> A_RWL<64> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_SRAM +XRAM<4> A_BLC<5> A_BLC<4> A_BLC<7> A_BLC<6> A_BLT<5> A_BLT<4> A_BLT<7> A_BLT<6> A_LWL<63> A_LWL<62> A_LWL<61> A_LWL<60> A_LWL<59> A_LWL<58> A_LWL<57> A_LWL<56> A_LWL<55> A_LWL<54> A_LWL<53> A_LWL<52> A_LWL<51> A_LWL<50> A_LWL<49> A_LWL<48> A_RWL<63> A_RWL<62> A_RWL<61> A_RWL<60> A_RWL<59> A_RWL<58> A_RWL<57> A_RWL<56> A_RWL<55> A_RWL<54> A_RWL<53> A_RWL<52> A_RWL<51> A_RWL<50> A_RWL<49> A_RWL<48> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_SRAM +XRAM<3> A_BLC<3> A_BLC<2> A_BLC<5> A_BLC<4> A_BLT<3> A_BLT<2> A_BLT<5> A_BLT<4> A_LWL<47> A_LWL<46> A_LWL<45> A_LWL<44> A_LWL<43> A_LWL<42> A_LWL<41> A_LWL<40> A_LWL<39> A_LWL<38> A_LWL<37> A_LWL<36> A_LWL<35> A_LWL<34> A_LWL<33> A_LWL<32> A_RWL<47> A_RWL<46> A_RWL<45> A_RWL<44> A_RWL<43> A_RWL<42> A_RWL<41> A_RWL<40> A_RWL<39> A_RWL<38> A_RWL<37> A_RWL<36> A_RWL<35> A_RWL<34> A_RWL<33> A_RWL<32> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_SRAM +XRAM<2> A_BLC<1> A_BLC<0> A_BLC<3> A_BLC<2> A_BLT<1> A_BLT<0> A_BLT<3> A_BLT<2> A_LWL<31> A_LWL<30> A_LWL<29> A_LWL<28> A_LWL<27> A_LWL<26> A_LWL<25> A_LWL<24> A_LWL<23> A_LWL<22> A_LWL<21> A_LWL<20> A_LWL<19> A_LWL<18> A_LWL<17> A_LWL<16> A_RWL<31> A_RWL<30> A_RWL<29> A_RWL<28> A_RWL<27> A_RWL<26> A_RWL<25> A_RWL<24> A_RWL<23> A_RWL<22> A_RWL<21> A_RWL<20> A_RWL<19> A_RWL<18> A_RWL<17> A_RWL<16> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_SRAM +XRAM<1> A_BLC_BOT<1> A_BLC_BOT<0> A_BLC<1> A_BLC<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT<1> A_BLT<0> A_LWL<15> A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_SRAM +XEDGE<1> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT_TOP<1> A_BLT_TOP<0> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_TB +XEDGE<0> A_BLC_BOT<1> A_BLC_BOT<0> A_BLT_BOT<1> A_BLT_BOT<0> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_TB +.ENDS + + + + +.SUBCKT RM_IHPSG13_1024x8_c2_1P_MATRIX_pcell_1 A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<15> A_BLT<14> A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_WL<255> A_WL<254> A_WL<253> A_WL<252> A_WL<251> A_WL<250> A_WL<249> A_WL<248> A_WL<247> A_WL<246> A_WL<245> A_WL<244> A_WL<243> A_WL<242> A_WL<241> A_WL<240> A_WL<239> A_WL<238> A_WL<237> A_WL<236> A_WL<235> A_WL<234> A_WL<233> A_WL<232> A_WL<231> A_WL<230> A_WL<229> A_WL<228> A_WL<227> A_WL<226> A_WL<225> A_WL<224> A_WL<223> A_WL<222> A_WL<221> A_WL<220> A_WL<219> A_WL<218> A_WL<217> A_WL<216> A_WL<215> A_WL<214> A_WL<213> A_WL<212> A_WL<211> A_WL<210> A_WL<209> A_WL<208> A_WL<207> A_WL<206> A_WL<205> A_WL<204> A_WL<203> A_WL<202> A_WL<201> A_WL<200> A_WL<199> A_WL<198> A_WL<197> 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RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_CORNER +XCORNER<1> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_CORNER +XCORNER<0> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_CORNER +XRAMEDGE_L<15> A_WL<255> A_WL<254> A_WL<253> A_WL<252> A_WL<251> A_WL<250> A_WL<249> A_WL<248> A_WL<247> A_WL<246> A_WL<245> A_WL<244> A_WL<243> A_WL<242> A_WL<241> A_WL<240> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<14> A_WL<239> A_WL<238> A_WL<237> A_WL<236> A_WL<235> A_WL<234> A_WL<233> A_WL<232> A_WL<231> A_WL<230> A_WL<229> A_WL<228> A_WL<227> A_WL<226> A_WL<225> A_WL<224> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<13> A_WL<223> A_WL<222> A_WL<221> A_WL<220> A_WL<219> A_WL<218> A_WL<217> A_WL<216> A_WL<215> A_WL<214> A_WL<213> A_WL<212> A_WL<211> A_WL<210> A_WL<209> A_WL<208> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<12> A_WL<207> A_WL<206> A_WL<205> A_WL<204> A_WL<203> A_WL<202> A_WL<201> A_WL<200> A_WL<199> A_WL<198> A_WL<197> A_WL<196> A_WL<195> A_WL<194> A_WL<193> A_WL<192> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<11> A_WL<191> A_WL<190> A_WL<189> A_WL<188> A_WL<187> A_WL<186> A_WL<185> A_WL<184> A_WL<183> A_WL<182> A_WL<181> A_WL<180> A_WL<179> A_WL<178> A_WL<177> A_WL<176> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<10> A_WL<175> A_WL<174> A_WL<173> A_WL<172> A_WL<171> A_WL<170> A_WL<169> A_WL<168> A_WL<167> A_WL<166> A_WL<165> A_WL<164> A_WL<163> A_WL<162> A_WL<161> A_WL<160> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<9> A_WL<159> A_WL<158> A_WL<157> A_WL<156> A_WL<155> A_WL<154> A_WL<153> A_WL<152> A_WL<151> A_WL<150> A_WL<149> A_WL<148> A_WL<147> A_WL<146> A_WL<145> A_WL<144> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<8> A_WL<143> A_WL<142> A_WL<141> A_WL<140> A_WL<139> A_WL<138> A_WL<137> A_WL<136> A_WL<135> A_WL<134> A_WL<133> A_WL<132> A_WL<131> A_WL<130> A_WL<129> A_WL<128> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<7> A_WL<127> A_WL<126> A_WL<125> A_WL<124> A_WL<123> A_WL<122> A_WL<121> A_WL<120> A_WL<119> A_WL<118> A_WL<117> A_WL<116> A_WL<115> A_WL<114> A_WL<113> A_WL<112> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<6> A_WL<111> A_WL<110> A_WL<109> A_WL<108> A_WL<107> A_WL<106> A_WL<105> A_WL<104> A_WL<103> A_WL<102> A_WL<101> A_WL<100> A_WL<99> A_WL<98> A_WL<97> A_WL<96> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<5> A_WL<95> A_WL<94> A_WL<93> A_WL<92> A_WL<91> A_WL<90> A_WL<89> A_WL<88> A_WL<87> A_WL<86> A_WL<85> A_WL<84> A_WL<83> A_WL<82> A_WL<81> A_WL<80> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<4> A_WL<79> A_WL<78> A_WL<77> A_WL<76> A_WL<75> A_WL<74> A_WL<73> A_WL<72> A_WL<71> A_WL<70> A_WL<69> A_WL<68> A_WL<67> A_WL<66> A_WL<65> A_WL<64> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<3> A_WL<63> A_WL<62> A_WL<61> A_WL<60> A_WL<59> A_WL<58> A_WL<57> A_WL<56> A_WL<55> A_WL<54> A_WL<53> A_WL<52> A_WL<51> A_WL<50> A_WL<49> A_WL<48> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<2> A_WL<47> A_WL<46> A_WL<45> A_WL<44> A_WL<43> A_WL<42> A_WL<41> A_WL<40> A_WL<39> A_WL<38> A_WL<37> A_WL<36> A_WL<35> A_WL<34> A_WL<33> A_WL<32> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<1> A_WL<31> A_WL<30> A_WL<29> A_WL<28> A_WL<27> A_WL<26> A_WL<25> A_WL<24> A_WL<23> A_WL<22> A_WL<21> A_WL<20> A_WL<19> A_WL<18> A_WL<17> A_WL<16> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<0> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<15> A_IWL<2047> A_IWL<2046> A_IWL<2045> A_IWL<2044> A_IWL<2043> A_IWL<2042> A_IWL<2041> A_IWL<2040> A_IWL<2039> A_IWL<2038> A_IWL<2037> A_IWL<2036> A_IWL<2035> A_IWL<2034> A_IWL<2033> A_IWL<2032> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<14> A_IWL<2031> A_IWL<2030> A_IWL<2029> A_IWL<2028> A_IWL<2027> A_IWL<2026> A_IWL<2025> A_IWL<2024> A_IWL<2023> A_IWL<2022> A_IWL<2021> A_IWL<2020> A_IWL<2019> A_IWL<2018> A_IWL<2017> A_IWL<2016> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<13> A_IWL<2015> A_IWL<2014> A_IWL<2013> A_IWL<2012> A_IWL<2011> A_IWL<2010> A_IWL<2009> A_IWL<2008> A_IWL<2007> A_IWL<2006> A_IWL<2005> A_IWL<2004> A_IWL<2003> A_IWL<2002> A_IWL<2001> A_IWL<2000> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<12> A_IWL<1999> A_IWL<1998> A_IWL<1997> A_IWL<1996> A_IWL<1995> A_IWL<1994> A_IWL<1993> A_IWL<1992> A_IWL<1991> A_IWL<1990> A_IWL<1989> A_IWL<1988> A_IWL<1987> A_IWL<1986> A_IWL<1985> A_IWL<1984> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<11> A_IWL<1983> A_IWL<1982> A_IWL<1981> A_IWL<1980> A_IWL<1979> A_IWL<1978> A_IWL<1977> A_IWL<1976> A_IWL<1975> A_IWL<1974> A_IWL<1973> A_IWL<1972> A_IWL<1971> A_IWL<1970> A_IWL<1969> A_IWL<1968> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<10> A_IWL<1967> A_IWL<1966> A_IWL<1965> A_IWL<1964> A_IWL<1963> A_IWL<1962> A_IWL<1961> A_IWL<1960> A_IWL<1959> A_IWL<1958> A_IWL<1957> A_IWL<1956> A_IWL<1955> A_IWL<1954> A_IWL<1953> A_IWL<1952> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<9> A_IWL<1951> A_IWL<1950> A_IWL<1949> A_IWL<1948> A_IWL<1947> A_IWL<1946> A_IWL<1945> A_IWL<1944> A_IWL<1943> A_IWL<1942> A_IWL<1941> A_IWL<1940> A_IWL<1939> A_IWL<1938> A_IWL<1937> A_IWL<1936> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<8> A_IWL<1935> A_IWL<1934> A_IWL<1933> A_IWL<1932> A_IWL<1931> A_IWL<1930> A_IWL<1929> A_IWL<1928> A_IWL<1927> A_IWL<1926> A_IWL<1925> A_IWL<1924> A_IWL<1923> A_IWL<1922> A_IWL<1921> A_IWL<1920> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<7> A_IWL<1919> A_IWL<1918> A_IWL<1917> A_IWL<1916> A_IWL<1915> A_IWL<1914> A_IWL<1913> A_IWL<1912> A_IWL<1911> A_IWL<1910> A_IWL<1909> A_IWL<1908> A_IWL<1907> A_IWL<1906> A_IWL<1905> A_IWL<1904> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<6> A_IWL<1903> A_IWL<1902> A_IWL<1901> A_IWL<1900> A_IWL<1899> A_IWL<1898> A_IWL<1897> A_IWL<1896> A_IWL<1895> A_IWL<1894> A_IWL<1893> A_IWL<1892> A_IWL<1891> A_IWL<1890> A_IWL<1889> A_IWL<1888> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<5> A_IWL<1887> A_IWL<1886> A_IWL<1885> A_IWL<1884> A_IWL<1883> A_IWL<1882> A_IWL<1881> A_IWL<1880> A_IWL<1879> A_IWL<1878> A_IWL<1877> A_IWL<1876> A_IWL<1875> A_IWL<1874> A_IWL<1873> A_IWL<1872> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<4> A_IWL<1871> A_IWL<1870> A_IWL<1869> A_IWL<1868> A_IWL<1867> A_IWL<1866> A_IWL<1865> A_IWL<1864> A_IWL<1863> A_IWL<1862> A_IWL<1861> A_IWL<1860> A_IWL<1859> A_IWL<1858> A_IWL<1857> A_IWL<1856> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<3> A_IWL<1855> A_IWL<1854> A_IWL<1853> A_IWL<1852> A_IWL<1851> A_IWL<1850> A_IWL<1849> A_IWL<1848> A_IWL<1847> A_IWL<1846> A_IWL<1845> A_IWL<1844> A_IWL<1843> A_IWL<1842> A_IWL<1841> A_IWL<1840> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<2> A_IWL<1839> A_IWL<1838> A_IWL<1837> A_IWL<1836> A_IWL<1835> A_IWL<1834> A_IWL<1833> A_IWL<1832> A_IWL<1831> A_IWL<1830> A_IWL<1829> A_IWL<1828> A_IWL<1827> A_IWL<1826> A_IWL<1825> A_IWL<1824> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<1> A_IWL<1823> A_IWL<1822> A_IWL<1821> A_IWL<1820> A_IWL<1819> A_IWL<1818> A_IWL<1817> A_IWL<1816> A_IWL<1815> A_IWL<1814> A_IWL<1813> A_IWL<1812> A_IWL<1811> A_IWL<1810> A_IWL<1809> A_IWL<1808> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<0> A_IWL<1807> A_IWL<1806> A_IWL<1805> A_IWL<1804> A_IWL<1803> A_IWL<1802> A_IWL<1801> A_IWL<1800> A_IWL<1799> A_IWL<1798> A_IWL<1797> A_IWL<1796> A_IWL<1795> A_IWL<1794> A_IWL<1793> A_IWL<1792> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_LR +XCOL<7> A_BLC<15> A_BLC<14> A_BLC_TOP<15> A_BLC_TOP<14> A_BLT<15> A_BLT<14> A_BLT_TOP<15> A_BLT_TOP<14> A_IWL<1791> A_IWL<1790> A_IWL<1789> A_IWL<1788> A_IWL<1787> A_IWL<1786> A_IWL<1785> A_IWL<1784> A_IWL<1783> A_IWL<1782> A_IWL<1781> A_IWL<1780> A_IWL<1779> A_IWL<1778> A_IWL<1777> A_IWL<1776> A_IWL<1775> A_IWL<1774> A_IWL<1773> A_IWL<1772> A_IWL<1771> A_IWL<1770> A_IWL<1769> A_IWL<1768> A_IWL<1767> A_IWL<1766> A_IWL<1765> A_IWL<1764> A_IWL<1763> A_IWL<1762> A_IWL<1761> A_IWL<1760> A_IWL<1759> A_IWL<1758> A_IWL<1757> A_IWL<1756> A_IWL<1755> A_IWL<1754> A_IWL<1753> A_IWL<1752> A_IWL<1751> A_IWL<1750> A_IWL<1749> A_IWL<1748> A_IWL<1747> A_IWL<1746> A_IWL<1745> A_IWL<1744> A_IWL<1743> A_IWL<1742> A_IWL<1741> A_IWL<1740> A_IWL<1739> A_IWL<1738> A_IWL<1737> A_IWL<1736> A_IWL<1735> A_IWL<1734> A_IWL<1733> A_IWL<1732> A_IWL<1731> A_IWL<1730> A_IWL<1729> A_IWL<1728> A_IWL<1727> A_IWL<1726> A_IWL<1725> A_IWL<1724> A_IWL<1723> A_IWL<1722> A_IWL<1721> A_IWL<1720> A_IWL<1719> A_IWL<1718> A_IWL<1717> A_IWL<1716> A_IWL<1715> A_IWL<1714> A_IWL<1713> A_IWL<1712> A_IWL<1711> A_IWL<1710> A_IWL<1709> A_IWL<1708> A_IWL<1707> A_IWL<1706> A_IWL<1705> A_IWL<1704> A_IWL<1703> A_IWL<1702> A_IWL<1701> A_IWL<1700> A_IWL<1699> A_IWL<1698> A_IWL<1697> A_IWL<1696> A_IWL<1695> A_IWL<1694> A_IWL<1693> A_IWL<1692> A_IWL<1691> A_IWL<1690> A_IWL<1689> A_IWL<1688> A_IWL<1687> A_IWL<1686> A_IWL<1685> A_IWL<1684> A_IWL<1683> A_IWL<1682> A_IWL<1681> A_IWL<1680> A_IWL<1679> A_IWL<1678> A_IWL<1677> A_IWL<1676> A_IWL<1675> A_IWL<1674> A_IWL<1673> A_IWL<1672> A_IWL<1671> A_IWL<1670> A_IWL<1669> A_IWL<1668> A_IWL<1667> A_IWL<1666> A_IWL<1665> A_IWL<1664> A_IWL<1663> A_IWL<1662> A_IWL<1661> A_IWL<1660> A_IWL<1659> A_IWL<1658> A_IWL<1657> A_IWL<1656> A_IWL<1655> A_IWL<1654> A_IWL<1653> A_IWL<1652> A_IWL<1651> A_IWL<1650> A_IWL<1649> A_IWL<1648> A_IWL<1647> A_IWL<1646> A_IWL<1645> A_IWL<1644> A_IWL<1643> A_IWL<1642> A_IWL<1641> A_IWL<1640> A_IWL<1639> A_IWL<1638> A_IWL<1637> A_IWL<1636> A_IWL<1635> A_IWL<1634> A_IWL<1633> A_IWL<1632> A_IWL<1631> A_IWL<1630> A_IWL<1629> A_IWL<1628> A_IWL<1627> A_IWL<1626> A_IWL<1625> A_IWL<1624> A_IWL<1623> A_IWL<1622> A_IWL<1621> A_IWL<1620> A_IWL<1619> A_IWL<1618> A_IWL<1617> A_IWL<1616> A_IWL<1615> A_IWL<1614> A_IWL<1613> A_IWL<1612> A_IWL<1611> A_IWL<1610> A_IWL<1609> A_IWL<1608> A_IWL<1607> A_IWL<1606> A_IWL<1605> A_IWL<1604> A_IWL<1603> A_IWL<1602> A_IWL<1601> A_IWL<1600> A_IWL<1599> A_IWL<1598> A_IWL<1597> A_IWL<1596> A_IWL<1595> A_IWL<1594> A_IWL<1593> A_IWL<1592> A_IWL<1591> A_IWL<1590> A_IWL<1589> A_IWL<1588> A_IWL<1587> A_IWL<1586> A_IWL<1585> A_IWL<1584> A_IWL<1583> A_IWL<1582> A_IWL<1581> A_IWL<1580> A_IWL<1579> A_IWL<1578> A_IWL<1577> A_IWL<1576> A_IWL<1575> A_IWL<1574> A_IWL<1573> A_IWL<1572> A_IWL<1571> A_IWL<1570> A_IWL<1569> A_IWL<1568> A_IWL<1567> A_IWL<1566> A_IWL<1565> A_IWL<1564> A_IWL<1563> A_IWL<1562> A_IWL<1561> A_IWL<1560> A_IWL<1559> A_IWL<1558> A_IWL<1557> A_IWL<1556> A_IWL<1555> A_IWL<1554> A_IWL<1553> A_IWL<1552> A_IWL<1551> A_IWL<1550> A_IWL<1549> A_IWL<1548> A_IWL<1547> A_IWL<1546> A_IWL<1545> A_IWL<1544> A_IWL<1543> A_IWL<1542> A_IWL<1541> A_IWL<1540> A_IWL<1539> A_IWL<1538> A_IWL<1537> A_IWL<1536> A_IWL<2047> A_IWL<2046> A_IWL<2045> A_IWL<2044> A_IWL<2043> A_IWL<2042> A_IWL<2041> A_IWL<2040> A_IWL<2039> A_IWL<2038> A_IWL<2037> A_IWL<2036> A_IWL<2035> A_IWL<2034> A_IWL<2033> A_IWL<2032> A_IWL<2031> A_IWL<2030> A_IWL<2029> A_IWL<2028> A_IWL<2027> A_IWL<2026> A_IWL<2025> A_IWL<2024> A_IWL<2023> A_IWL<2022> A_IWL<2021> A_IWL<2020> A_IWL<2019> A_IWL<2018> A_IWL<2017> A_IWL<2016> A_IWL<2015> A_IWL<2014> A_IWL<2013> A_IWL<2012> A_IWL<2011> A_IWL<2010> A_IWL<2009> A_IWL<2008> A_IWL<2007> A_IWL<2006> A_IWL<2005> A_IWL<2004> A_IWL<2003> A_IWL<2002> A_IWL<2001> A_IWL<2000> A_IWL<1999> A_IWL<1998> A_IWL<1997> A_IWL<1996> A_IWL<1995> A_IWL<1994> A_IWL<1993> A_IWL<1992> A_IWL<1991> A_IWL<1990> A_IWL<1989> A_IWL<1988> A_IWL<1987> A_IWL<1986> A_IWL<1985> A_IWL<1984> A_IWL<1983> A_IWL<1982> A_IWL<1981> A_IWL<1980> A_IWL<1979> A_IWL<1978> A_IWL<1977> A_IWL<1976> A_IWL<1975> A_IWL<1974> A_IWL<1973> A_IWL<1972> A_IWL<1971> A_IWL<1970> A_IWL<1969> A_IWL<1968> A_IWL<1967> A_IWL<1966> A_IWL<1965> A_IWL<1964> A_IWL<1963> A_IWL<1962> A_IWL<1961> A_IWL<1960> A_IWL<1959> A_IWL<1958> A_IWL<1957> A_IWL<1956> A_IWL<1955> A_IWL<1954> A_IWL<1953> A_IWL<1952> A_IWL<1951> A_IWL<1950> A_IWL<1949> A_IWL<1948> A_IWL<1947> A_IWL<1946> A_IWL<1945> A_IWL<1944> A_IWL<1943> A_IWL<1942> A_IWL<1941> A_IWL<1940> A_IWL<1939> A_IWL<1938> A_IWL<1937> A_IWL<1936> A_IWL<1935> A_IWL<1934> A_IWL<1933> A_IWL<1932> A_IWL<1931> A_IWL<1930> A_IWL<1929> A_IWL<1928> A_IWL<1927> A_IWL<1926> A_IWL<1925> A_IWL<1924> A_IWL<1923> A_IWL<1922> A_IWL<1921> A_IWL<1920> A_IWL<1919> A_IWL<1918> A_IWL<1917> A_IWL<1916> A_IWL<1915> A_IWL<1914> A_IWL<1913> A_IWL<1912> A_IWL<1911> A_IWL<1910> A_IWL<1909> A_IWL<1908> A_IWL<1907> A_IWL<1906> A_IWL<1905> A_IWL<1904> A_IWL<1903> A_IWL<1902> A_IWL<1901> A_IWL<1900> A_IWL<1899> A_IWL<1898> A_IWL<1897> A_IWL<1896> A_IWL<1895> A_IWL<1894> A_IWL<1893> A_IWL<1892> A_IWL<1891> A_IWL<1890> A_IWL<1889> A_IWL<1888> A_IWL<1887> A_IWL<1886> A_IWL<1885> A_IWL<1884> A_IWL<1883> A_IWL<1882> A_IWL<1881> A_IWL<1880> A_IWL<1879> A_IWL<1878> A_IWL<1877> A_IWL<1876> A_IWL<1875> A_IWL<1874> A_IWL<1873> A_IWL<1872> A_IWL<1871> A_IWL<1870> A_IWL<1869> A_IWL<1868> A_IWL<1867> A_IWL<1866> A_IWL<1865> A_IWL<1864> A_IWL<1863> A_IWL<1862> A_IWL<1861> A_IWL<1860> A_IWL<1859> A_IWL<1858> A_IWL<1857> A_IWL<1856> A_IWL<1855> A_IWL<1854> A_IWL<1853> A_IWL<1852> A_IWL<1851> A_IWL<1850> A_IWL<1849> A_IWL<1848> A_IWL<1847> A_IWL<1846> A_IWL<1845> A_IWL<1844> A_IWL<1843> A_IWL<1842> A_IWL<1841> A_IWL<1840> A_IWL<1839> A_IWL<1838> A_IWL<1837> A_IWL<1836> A_IWL<1835> A_IWL<1834> A_IWL<1833> A_IWL<1832> A_IWL<1831> A_IWL<1830> A_IWL<1829> A_IWL<1828> A_IWL<1827> A_IWL<1826> A_IWL<1825> A_IWL<1824> A_IWL<1823> A_IWL<1822> A_IWL<1821> A_IWL<1820> A_IWL<1819> A_IWL<1818> A_IWL<1817> A_IWL<1816> A_IWL<1815> A_IWL<1814> A_IWL<1813> A_IWL<1812> A_IWL<1811> A_IWL<1810> A_IWL<1809> A_IWL<1808> A_IWL<1807> A_IWL<1806> A_IWL<1805> A_IWL<1804> A_IWL<1803> A_IWL<1802> A_IWL<1801> A_IWL<1800> A_IWL<1799> A_IWL<1798> A_IWL<1797> A_IWL<1796> A_IWL<1795> A_IWL<1794> A_IWL<1793> A_IWL<1792> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_COLUMN_pcell_0 +XCOL<6> A_BLC<13> A_BLC<12> A_BLC_TOP<13> A_BLC_TOP<12> A_BLT<13> A_BLT<12> A_BLT_TOP<13> A_BLT_TOP<12> A_IWL<1535> A_IWL<1534> A_IWL<1533> A_IWL<1532> A_IWL<1531> A_IWL<1530> A_IWL<1529> A_IWL<1528> A_IWL<1527> A_IWL<1526> A_IWL<1525> A_IWL<1524> A_IWL<1523> A_IWL<1522> A_IWL<1521> A_IWL<1520> A_IWL<1519> A_IWL<1518> A_IWL<1517> A_IWL<1516> A_IWL<1515> A_IWL<1514> A_IWL<1513> A_IWL<1512> A_IWL<1511> A_IWL<1510> A_IWL<1509> A_IWL<1508> A_IWL<1507> A_IWL<1506> A_IWL<1505> A_IWL<1504> A_IWL<1503> A_IWL<1502> A_IWL<1501> A_IWL<1500> A_IWL<1499> A_IWL<1498> A_IWL<1497> A_IWL<1496> A_IWL<1495> A_IWL<1494> A_IWL<1493> A_IWL<1492> A_IWL<1491> A_IWL<1490> A_IWL<1489> A_IWL<1488> A_IWL<1487> A_IWL<1486> A_IWL<1485> A_IWL<1484> A_IWL<1483> A_IWL<1482> A_IWL<1481> A_IWL<1480> A_IWL<1479> A_IWL<1478> A_IWL<1477> A_IWL<1476> A_IWL<1475> A_IWL<1474> A_IWL<1473> A_IWL<1472> A_IWL<1471> A_IWL<1470> A_IWL<1469> A_IWL<1468> A_IWL<1467> A_IWL<1466> A_IWL<1465> A_IWL<1464> A_IWL<1463> A_IWL<1462> A_IWL<1461> A_IWL<1460> A_IWL<1459> A_IWL<1458> A_IWL<1457> A_IWL<1456> A_IWL<1455> A_IWL<1454> A_IWL<1453> A_IWL<1452> A_IWL<1451> A_IWL<1450> A_IWL<1449> A_IWL<1448> A_IWL<1447> A_IWL<1446> A_IWL<1445> A_IWL<1444> A_IWL<1443> A_IWL<1442> A_IWL<1441> A_IWL<1440> A_IWL<1439> A_IWL<1438> A_IWL<1437> A_IWL<1436> A_IWL<1435> A_IWL<1434> A_IWL<1433> A_IWL<1432> A_IWL<1431> A_IWL<1430> A_IWL<1429> A_IWL<1428> A_IWL<1427> A_IWL<1426> A_IWL<1425> A_IWL<1424> A_IWL<1423> A_IWL<1422> A_IWL<1421> A_IWL<1420> A_IWL<1419> A_IWL<1418> A_IWL<1417> A_IWL<1416> A_IWL<1415> A_IWL<1414> A_IWL<1413> A_IWL<1412> A_IWL<1411> A_IWL<1410> A_IWL<1409> A_IWL<1408> A_IWL<1407> A_IWL<1406> A_IWL<1405> A_IWL<1404> A_IWL<1403> A_IWL<1402> A_IWL<1401> A_IWL<1400> A_IWL<1399> A_IWL<1398> A_IWL<1397> A_IWL<1396> A_IWL<1395> A_IWL<1394> A_IWL<1393> A_IWL<1392> A_IWL<1391> A_IWL<1390> A_IWL<1389> A_IWL<1388> A_IWL<1387> A_IWL<1386> A_IWL<1385> A_IWL<1384> A_IWL<1383> A_IWL<1382> A_IWL<1381> A_IWL<1380> A_IWL<1379> A_IWL<1378> A_IWL<1377> A_IWL<1376> A_IWL<1375> A_IWL<1374> A_IWL<1373> A_IWL<1372> A_IWL<1371> A_IWL<1370> A_IWL<1369> A_IWL<1368> A_IWL<1367> A_IWL<1366> A_IWL<1365> A_IWL<1364> A_IWL<1363> A_IWL<1362> A_IWL<1361> A_IWL<1360> A_IWL<1359> A_IWL<1358> A_IWL<1357> A_IWL<1356> A_IWL<1355> A_IWL<1354> A_IWL<1353> A_IWL<1352> A_IWL<1351> A_IWL<1350> A_IWL<1349> A_IWL<1348> A_IWL<1347> A_IWL<1346> A_IWL<1345> A_IWL<1344> A_IWL<1343> A_IWL<1342> A_IWL<1341> A_IWL<1340> A_IWL<1339> A_IWL<1338> A_IWL<1337> A_IWL<1336> A_IWL<1335> A_IWL<1334> A_IWL<1333> A_IWL<1332> A_IWL<1331> A_IWL<1330> A_IWL<1329> A_IWL<1328> A_IWL<1327> A_IWL<1326> A_IWL<1325> A_IWL<1324> A_IWL<1323> A_IWL<1322> A_IWL<1321> A_IWL<1320> A_IWL<1319> A_IWL<1318> A_IWL<1317> A_IWL<1316> A_IWL<1315> A_IWL<1314> A_IWL<1313> A_IWL<1312> A_IWL<1311> A_IWL<1310> A_IWL<1309> A_IWL<1308> A_IWL<1307> A_IWL<1306> A_IWL<1305> A_IWL<1304> A_IWL<1303> A_IWL<1302> A_IWL<1301> A_IWL<1300> A_IWL<1299> A_IWL<1298> A_IWL<1297> A_IWL<1296> A_IWL<1295> A_IWL<1294> A_IWL<1293> A_IWL<1292> A_IWL<1291> A_IWL<1290> A_IWL<1289> A_IWL<1288> A_IWL<1287> A_IWL<1286> A_IWL<1285> A_IWL<1284> A_IWL<1283> A_IWL<1282> A_IWL<1281> A_IWL<1280> A_IWL<1791> A_IWL<1790> A_IWL<1789> A_IWL<1788> A_IWL<1787> A_IWL<1786> A_IWL<1785> A_IWL<1784> A_IWL<1783> A_IWL<1782> A_IWL<1781> A_IWL<1780> A_IWL<1779> A_IWL<1778> A_IWL<1777> A_IWL<1776> A_IWL<1775> A_IWL<1774> A_IWL<1773> A_IWL<1772> A_IWL<1771> A_IWL<1770> A_IWL<1769> A_IWL<1768> A_IWL<1767> A_IWL<1766> A_IWL<1765> A_IWL<1764> A_IWL<1763> A_IWL<1762> A_IWL<1761> A_IWL<1760> A_IWL<1759> A_IWL<1758> A_IWL<1757> A_IWL<1756> A_IWL<1755> A_IWL<1754> A_IWL<1753> A_IWL<1752> A_IWL<1751> A_IWL<1750> A_IWL<1749> A_IWL<1748> A_IWL<1747> A_IWL<1746> A_IWL<1745> A_IWL<1744> A_IWL<1743> A_IWL<1742> A_IWL<1741> A_IWL<1740> A_IWL<1739> A_IWL<1738> A_IWL<1737> A_IWL<1736> A_IWL<1735> A_IWL<1734> A_IWL<1733> A_IWL<1732> A_IWL<1731> A_IWL<1730> A_IWL<1729> A_IWL<1728> A_IWL<1727> A_IWL<1726> A_IWL<1725> A_IWL<1724> A_IWL<1723> A_IWL<1722> A_IWL<1721> A_IWL<1720> A_IWL<1719> A_IWL<1718> A_IWL<1717> A_IWL<1716> A_IWL<1715> A_IWL<1714> A_IWL<1713> A_IWL<1712> A_IWL<1711> A_IWL<1710> A_IWL<1709> A_IWL<1708> A_IWL<1707> A_IWL<1706> A_IWL<1705> A_IWL<1704> A_IWL<1703> A_IWL<1702> A_IWL<1701> A_IWL<1700> A_IWL<1699> A_IWL<1698> A_IWL<1697> A_IWL<1696> A_IWL<1695> A_IWL<1694> A_IWL<1693> A_IWL<1692> A_IWL<1691> A_IWL<1690> A_IWL<1689> A_IWL<1688> A_IWL<1687> A_IWL<1686> A_IWL<1685> A_IWL<1684> A_IWL<1683> A_IWL<1682> A_IWL<1681> A_IWL<1680> A_IWL<1679> A_IWL<1678> A_IWL<1677> A_IWL<1676> A_IWL<1675> A_IWL<1674> A_IWL<1673> A_IWL<1672> A_IWL<1671> A_IWL<1670> A_IWL<1669> A_IWL<1668> A_IWL<1667> A_IWL<1666> A_IWL<1665> A_IWL<1664> A_IWL<1663> A_IWL<1662> A_IWL<1661> A_IWL<1660> A_IWL<1659> A_IWL<1658> A_IWL<1657> A_IWL<1656> A_IWL<1655> A_IWL<1654> A_IWL<1653> A_IWL<1652> A_IWL<1651> A_IWL<1650> A_IWL<1649> A_IWL<1648> A_IWL<1647> A_IWL<1646> A_IWL<1645> A_IWL<1644> A_IWL<1643> A_IWL<1642> A_IWL<1641> A_IWL<1640> A_IWL<1639> A_IWL<1638> A_IWL<1637> A_IWL<1636> A_IWL<1635> A_IWL<1634> A_IWL<1633> A_IWL<1632> A_IWL<1631> A_IWL<1630> A_IWL<1629> A_IWL<1628> A_IWL<1627> A_IWL<1626> A_IWL<1625> A_IWL<1624> A_IWL<1623> A_IWL<1622> A_IWL<1621> A_IWL<1620> A_IWL<1619> A_IWL<1618> A_IWL<1617> A_IWL<1616> A_IWL<1615> A_IWL<1614> A_IWL<1613> A_IWL<1612> A_IWL<1611> A_IWL<1610> A_IWL<1609> A_IWL<1608> A_IWL<1607> A_IWL<1606> A_IWL<1605> A_IWL<1604> A_IWL<1603> A_IWL<1602> A_IWL<1601> A_IWL<1600> A_IWL<1599> A_IWL<1598> A_IWL<1597> A_IWL<1596> A_IWL<1595> A_IWL<1594> A_IWL<1593> A_IWL<1592> A_IWL<1591> A_IWL<1590> A_IWL<1589> A_IWL<1588> A_IWL<1587> A_IWL<1586> A_IWL<1585> A_IWL<1584> A_IWL<1583> A_IWL<1582> A_IWL<1581> A_IWL<1580> A_IWL<1579> A_IWL<1578> A_IWL<1577> A_IWL<1576> A_IWL<1575> A_IWL<1574> A_IWL<1573> A_IWL<1572> A_IWL<1571> A_IWL<1570> A_IWL<1569> A_IWL<1568> A_IWL<1567> A_IWL<1566> A_IWL<1565> A_IWL<1564> A_IWL<1563> A_IWL<1562> A_IWL<1561> A_IWL<1560> A_IWL<1559> A_IWL<1558> A_IWL<1557> A_IWL<1556> A_IWL<1555> A_IWL<1554> A_IWL<1553> A_IWL<1552> A_IWL<1551> A_IWL<1550> A_IWL<1549> A_IWL<1548> A_IWL<1547> A_IWL<1546> A_IWL<1545> A_IWL<1544> A_IWL<1543> A_IWL<1542> A_IWL<1541> A_IWL<1540> A_IWL<1539> A_IWL<1538> A_IWL<1537> A_IWL<1536> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_COLUMN_pcell_0 +XCOL<5> A_BLC<11> A_BLC<10> A_BLC_TOP<11> A_BLC_TOP<10> A_BLT<11> A_BLT<10> A_BLT_TOP<11> A_BLT_TOP<10> A_IWL<1279> A_IWL<1278> A_IWL<1277> A_IWL<1276> A_IWL<1275> A_IWL<1274> A_IWL<1273> A_IWL<1272> A_IWL<1271> A_IWL<1270> A_IWL<1269> A_IWL<1268> A_IWL<1267> A_IWL<1266> A_IWL<1265> A_IWL<1264> A_IWL<1263> A_IWL<1262> A_IWL<1261> A_IWL<1260> A_IWL<1259> A_IWL<1258> A_IWL<1257> A_IWL<1256> A_IWL<1255> A_IWL<1254> A_IWL<1253> A_IWL<1252> A_IWL<1251> A_IWL<1250> A_IWL<1249> A_IWL<1248> A_IWL<1247> A_IWL<1246> A_IWL<1245> A_IWL<1244> A_IWL<1243> A_IWL<1242> A_IWL<1241> A_IWL<1240> A_IWL<1239> A_IWL<1238> A_IWL<1237> A_IWL<1236> A_IWL<1235> A_IWL<1234> A_IWL<1233> A_IWL<1232> A_IWL<1231> A_IWL<1230> A_IWL<1229> A_IWL<1228> A_IWL<1227> A_IWL<1226> A_IWL<1225> A_IWL<1224> A_IWL<1223> A_IWL<1222> A_IWL<1221> A_IWL<1220> A_IWL<1219> A_IWL<1218> A_IWL<1217> A_IWL<1216> A_IWL<1215> A_IWL<1214> A_IWL<1213> A_IWL<1212> A_IWL<1211> A_IWL<1210> A_IWL<1209> A_IWL<1208> A_IWL<1207> A_IWL<1206> A_IWL<1205> A_IWL<1204> A_IWL<1203> A_IWL<1202> A_IWL<1201> A_IWL<1200> A_IWL<1199> A_IWL<1198> A_IWL<1197> A_IWL<1196> A_IWL<1195> A_IWL<1194> A_IWL<1193> A_IWL<1192> A_IWL<1191> A_IWL<1190> A_IWL<1189> A_IWL<1188> A_IWL<1187> A_IWL<1186> A_IWL<1185> A_IWL<1184> A_IWL<1183> A_IWL<1182> A_IWL<1181> A_IWL<1180> A_IWL<1179> A_IWL<1178> A_IWL<1177> A_IWL<1176> A_IWL<1175> A_IWL<1174> A_IWL<1173> A_IWL<1172> A_IWL<1171> A_IWL<1170> A_IWL<1169> A_IWL<1168> A_IWL<1167> A_IWL<1166> A_IWL<1165> A_IWL<1164> A_IWL<1163> A_IWL<1162> A_IWL<1161> A_IWL<1160> A_IWL<1159> A_IWL<1158> A_IWL<1157> A_IWL<1156> A_IWL<1155> A_IWL<1154> A_IWL<1153> A_IWL<1152> A_IWL<1151> A_IWL<1150> A_IWL<1149> A_IWL<1148> A_IWL<1147> A_IWL<1146> A_IWL<1145> A_IWL<1144> A_IWL<1143> A_IWL<1142> A_IWL<1141> A_IWL<1140> A_IWL<1139> A_IWL<1138> A_IWL<1137> A_IWL<1136> A_IWL<1135> A_IWL<1134> A_IWL<1133> A_IWL<1132> A_IWL<1131> A_IWL<1130> A_IWL<1129> A_IWL<1128> A_IWL<1127> A_IWL<1126> A_IWL<1125> A_IWL<1124> A_IWL<1123> A_IWL<1122> A_IWL<1121> A_IWL<1120> A_IWL<1119> A_IWL<1118> A_IWL<1117> A_IWL<1116> A_IWL<1115> A_IWL<1114> A_IWL<1113> A_IWL<1112> A_IWL<1111> A_IWL<1110> A_IWL<1109> A_IWL<1108> A_IWL<1107> A_IWL<1106> A_IWL<1105> A_IWL<1104> A_IWL<1103> A_IWL<1102> A_IWL<1101> A_IWL<1100> A_IWL<1099> A_IWL<1098> A_IWL<1097> A_IWL<1096> A_IWL<1095> A_IWL<1094> A_IWL<1093> A_IWL<1092> A_IWL<1091> A_IWL<1090> A_IWL<1089> A_IWL<1088> A_IWL<1087> A_IWL<1086> A_IWL<1085> A_IWL<1084> A_IWL<1083> A_IWL<1082> A_IWL<1081> A_IWL<1080> A_IWL<1079> A_IWL<1078> A_IWL<1077> A_IWL<1076> A_IWL<1075> A_IWL<1074> A_IWL<1073> A_IWL<1072> A_IWL<1071> A_IWL<1070> A_IWL<1069> A_IWL<1068> A_IWL<1067> A_IWL<1066> A_IWL<1065> A_IWL<1064> A_IWL<1063> A_IWL<1062> A_IWL<1061> A_IWL<1060> A_IWL<1059> A_IWL<1058> A_IWL<1057> A_IWL<1056> A_IWL<1055> A_IWL<1054> A_IWL<1053> A_IWL<1052> A_IWL<1051> A_IWL<1050> A_IWL<1049> A_IWL<1048> A_IWL<1047> A_IWL<1046> A_IWL<1045> A_IWL<1044> A_IWL<1043> A_IWL<1042> A_IWL<1041> A_IWL<1040> A_IWL<1039> A_IWL<1038> A_IWL<1037> A_IWL<1036> A_IWL<1035> A_IWL<1034> A_IWL<1033> A_IWL<1032> A_IWL<1031> A_IWL<1030> A_IWL<1029> A_IWL<1028> A_IWL<1027> A_IWL<1026> A_IWL<1025> A_IWL<1024> A_IWL<1535> A_IWL<1534> A_IWL<1533> A_IWL<1532> A_IWL<1531> A_IWL<1530> A_IWL<1529> A_IWL<1528> A_IWL<1527> A_IWL<1526> A_IWL<1525> A_IWL<1524> A_IWL<1523> A_IWL<1522> A_IWL<1521> A_IWL<1520> A_IWL<1519> A_IWL<1518> A_IWL<1517> A_IWL<1516> A_IWL<1515> A_IWL<1514> A_IWL<1513> A_IWL<1512> A_IWL<1511> A_IWL<1510> A_IWL<1509> A_IWL<1508> A_IWL<1507> A_IWL<1506> A_IWL<1505> A_IWL<1504> A_IWL<1503> A_IWL<1502> A_IWL<1501> A_IWL<1500> A_IWL<1499> A_IWL<1498> A_IWL<1497> A_IWL<1496> A_IWL<1495> A_IWL<1494> A_IWL<1493> A_IWL<1492> A_IWL<1491> A_IWL<1490> A_IWL<1489> A_IWL<1488> A_IWL<1487> A_IWL<1486> A_IWL<1485> A_IWL<1484> A_IWL<1483> A_IWL<1482> A_IWL<1481> A_IWL<1480> A_IWL<1479> A_IWL<1478> A_IWL<1477> A_IWL<1476> A_IWL<1475> A_IWL<1474> A_IWL<1473> A_IWL<1472> A_IWL<1471> A_IWL<1470> A_IWL<1469> A_IWL<1468> A_IWL<1467> A_IWL<1466> A_IWL<1465> A_IWL<1464> A_IWL<1463> A_IWL<1462> A_IWL<1461> A_IWL<1460> A_IWL<1459> A_IWL<1458> A_IWL<1457> A_IWL<1456> A_IWL<1455> A_IWL<1454> A_IWL<1453> A_IWL<1452> A_IWL<1451> A_IWL<1450> A_IWL<1449> A_IWL<1448> A_IWL<1447> A_IWL<1446> A_IWL<1445> A_IWL<1444> A_IWL<1443> A_IWL<1442> A_IWL<1441> A_IWL<1440> A_IWL<1439> A_IWL<1438> A_IWL<1437> A_IWL<1436> A_IWL<1435> A_IWL<1434> A_IWL<1433> A_IWL<1432> A_IWL<1431> A_IWL<1430> A_IWL<1429> A_IWL<1428> A_IWL<1427> A_IWL<1426> A_IWL<1425> A_IWL<1424> A_IWL<1423> A_IWL<1422> A_IWL<1421> A_IWL<1420> A_IWL<1419> A_IWL<1418> A_IWL<1417> A_IWL<1416> A_IWL<1415> A_IWL<1414> A_IWL<1413> A_IWL<1412> A_IWL<1411> A_IWL<1410> A_IWL<1409> A_IWL<1408> A_IWL<1407> A_IWL<1406> A_IWL<1405> A_IWL<1404> A_IWL<1403> A_IWL<1402> A_IWL<1401> A_IWL<1400> A_IWL<1399> A_IWL<1398> A_IWL<1397> A_IWL<1396> A_IWL<1395> A_IWL<1394> A_IWL<1393> A_IWL<1392> A_IWL<1391> A_IWL<1390> A_IWL<1389> A_IWL<1388> A_IWL<1387> A_IWL<1386> A_IWL<1385> A_IWL<1384> A_IWL<1383> A_IWL<1382> A_IWL<1381> A_IWL<1380> A_IWL<1379> A_IWL<1378> A_IWL<1377> A_IWL<1376> A_IWL<1375> A_IWL<1374> A_IWL<1373> A_IWL<1372> A_IWL<1371> A_IWL<1370> A_IWL<1369> A_IWL<1368> A_IWL<1367> A_IWL<1366> A_IWL<1365> A_IWL<1364> A_IWL<1363> A_IWL<1362> A_IWL<1361> A_IWL<1360> A_IWL<1359> A_IWL<1358> A_IWL<1357> A_IWL<1356> A_IWL<1355> A_IWL<1354> A_IWL<1353> A_IWL<1352> A_IWL<1351> A_IWL<1350> A_IWL<1349> A_IWL<1348> A_IWL<1347> A_IWL<1346> A_IWL<1345> A_IWL<1344> A_IWL<1343> A_IWL<1342> A_IWL<1341> A_IWL<1340> A_IWL<1339> A_IWL<1338> A_IWL<1337> A_IWL<1336> A_IWL<1335> A_IWL<1334> A_IWL<1333> A_IWL<1332> A_IWL<1331> A_IWL<1330> A_IWL<1329> A_IWL<1328> A_IWL<1327> A_IWL<1326> A_IWL<1325> A_IWL<1324> A_IWL<1323> A_IWL<1322> A_IWL<1321> A_IWL<1320> A_IWL<1319> A_IWL<1318> A_IWL<1317> A_IWL<1316> A_IWL<1315> A_IWL<1314> A_IWL<1313> A_IWL<1312> A_IWL<1311> A_IWL<1310> A_IWL<1309> A_IWL<1308> A_IWL<1307> A_IWL<1306> A_IWL<1305> A_IWL<1304> A_IWL<1303> A_IWL<1302> A_IWL<1301> A_IWL<1300> A_IWL<1299> A_IWL<1298> A_IWL<1297> A_IWL<1296> A_IWL<1295> A_IWL<1294> A_IWL<1293> A_IWL<1292> A_IWL<1291> A_IWL<1290> A_IWL<1289> A_IWL<1288> A_IWL<1287> A_IWL<1286> A_IWL<1285> A_IWL<1284> A_IWL<1283> A_IWL<1282> A_IWL<1281> A_IWL<1280> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_COLUMN_pcell_0 +XCOL<4> A_BLC<9> A_BLC<8> A_BLC_TOP<9> A_BLC_TOP<8> A_BLT<9> A_BLT<8> A_BLT_TOP<9> A_BLT_TOP<8> A_IWL<1023> A_IWL<1022> A_IWL<1021> A_IWL<1020> A_IWL<1019> A_IWL<1018> A_IWL<1017> A_IWL<1016> A_IWL<1015> A_IWL<1014> A_IWL<1013> A_IWL<1012> A_IWL<1011> A_IWL<1010> A_IWL<1009> A_IWL<1008> A_IWL<1007> A_IWL<1006> A_IWL<1005> A_IWL<1004> A_IWL<1003> A_IWL<1002> A_IWL<1001> A_IWL<1000> A_IWL<999> A_IWL<998> A_IWL<997> A_IWL<996> A_IWL<995> A_IWL<994> A_IWL<993> A_IWL<992> A_IWL<991> A_IWL<990> A_IWL<989> A_IWL<988> A_IWL<987> A_IWL<986> A_IWL<985> A_IWL<984> A_IWL<983> A_IWL<982> A_IWL<981> A_IWL<980> A_IWL<979> A_IWL<978> A_IWL<977> A_IWL<976> A_IWL<975> A_IWL<974> A_IWL<973> A_IWL<972> A_IWL<971> A_IWL<970> A_IWL<969> A_IWL<968> A_IWL<967> A_IWL<966> A_IWL<965> A_IWL<964> A_IWL<963> A_IWL<962> A_IWL<961> A_IWL<960> A_IWL<959> A_IWL<958> A_IWL<957> A_IWL<956> A_IWL<955> A_IWL<954> A_IWL<953> A_IWL<952> A_IWL<951> A_IWL<950> A_IWL<949> A_IWL<948> A_IWL<947> A_IWL<946> A_IWL<945> A_IWL<944> A_IWL<943> A_IWL<942> A_IWL<941> A_IWL<940> A_IWL<939> A_IWL<938> A_IWL<937> A_IWL<936> A_IWL<935> A_IWL<934> A_IWL<933> A_IWL<932> A_IWL<931> A_IWL<930> A_IWL<929> A_IWL<928> A_IWL<927> A_IWL<926> A_IWL<925> A_IWL<924> A_IWL<923> A_IWL<922> A_IWL<921> A_IWL<920> A_IWL<919> A_IWL<918> A_IWL<917> A_IWL<916> A_IWL<915> A_IWL<914> A_IWL<913> A_IWL<912> A_IWL<911> A_IWL<910> A_IWL<909> A_IWL<908> A_IWL<907> A_IWL<906> A_IWL<905> A_IWL<904> A_IWL<903> A_IWL<902> A_IWL<901> A_IWL<900> A_IWL<899> A_IWL<898> A_IWL<897> A_IWL<896> A_IWL<895> A_IWL<894> A_IWL<893> A_IWL<892> A_IWL<891> A_IWL<890> A_IWL<889> A_IWL<888> A_IWL<887> A_IWL<886> A_IWL<885> A_IWL<884> A_IWL<883> A_IWL<882> A_IWL<881> A_IWL<880> A_IWL<879> A_IWL<878> A_IWL<877> A_IWL<876> A_IWL<875> A_IWL<874> A_IWL<873> A_IWL<872> A_IWL<871> A_IWL<870> A_IWL<869> A_IWL<868> A_IWL<867> A_IWL<866> A_IWL<865> A_IWL<864> A_IWL<863> A_IWL<862> A_IWL<861> A_IWL<860> A_IWL<859> A_IWL<858> A_IWL<857> A_IWL<856> A_IWL<855> A_IWL<854> A_IWL<853> A_IWL<852> A_IWL<851> A_IWL<850> A_IWL<849> A_IWL<848> A_IWL<847> A_IWL<846> A_IWL<845> A_IWL<844> A_IWL<843> A_IWL<842> A_IWL<841> A_IWL<840> A_IWL<839> A_IWL<838> A_IWL<837> A_IWL<836> A_IWL<835> A_IWL<834> A_IWL<833> A_IWL<832> A_IWL<831> A_IWL<830> A_IWL<829> A_IWL<828> A_IWL<827> A_IWL<826> A_IWL<825> A_IWL<824> A_IWL<823> A_IWL<822> A_IWL<821> A_IWL<820> A_IWL<819> A_IWL<818> A_IWL<817> A_IWL<816> A_IWL<815> A_IWL<814> A_IWL<813> A_IWL<812> A_IWL<811> A_IWL<810> A_IWL<809> A_IWL<808> A_IWL<807> A_IWL<806> A_IWL<805> A_IWL<804> A_IWL<803> A_IWL<802> A_IWL<801> A_IWL<800> A_IWL<799> A_IWL<798> A_IWL<797> A_IWL<796> A_IWL<795> A_IWL<794> A_IWL<793> A_IWL<792> A_IWL<791> A_IWL<790> A_IWL<789> A_IWL<788> A_IWL<787> A_IWL<786> A_IWL<785> A_IWL<784> A_IWL<783> A_IWL<782> A_IWL<781> A_IWL<780> A_IWL<779> A_IWL<778> A_IWL<777> A_IWL<776> A_IWL<775> A_IWL<774> A_IWL<773> A_IWL<772> A_IWL<771> A_IWL<770> A_IWL<769> A_IWL<768> A_IWL<1279> A_IWL<1278> A_IWL<1277> A_IWL<1276> A_IWL<1275> A_IWL<1274> A_IWL<1273> A_IWL<1272> A_IWL<1271> A_IWL<1270> A_IWL<1269> A_IWL<1268> A_IWL<1267> A_IWL<1266> A_IWL<1265> A_IWL<1264> A_IWL<1263> A_IWL<1262> A_IWL<1261> A_IWL<1260> A_IWL<1259> A_IWL<1258> A_IWL<1257> A_IWL<1256> A_IWL<1255> A_IWL<1254> A_IWL<1253> A_IWL<1252> A_IWL<1251> A_IWL<1250> A_IWL<1249> A_IWL<1248> A_IWL<1247> A_IWL<1246> A_IWL<1245> A_IWL<1244> A_IWL<1243> A_IWL<1242> A_IWL<1241> A_IWL<1240> A_IWL<1239> A_IWL<1238> A_IWL<1237> A_IWL<1236> A_IWL<1235> A_IWL<1234> A_IWL<1233> A_IWL<1232> A_IWL<1231> A_IWL<1230> A_IWL<1229> A_IWL<1228> A_IWL<1227> A_IWL<1226> A_IWL<1225> A_IWL<1224> A_IWL<1223> A_IWL<1222> A_IWL<1221> A_IWL<1220> A_IWL<1219> A_IWL<1218> A_IWL<1217> A_IWL<1216> A_IWL<1215> A_IWL<1214> A_IWL<1213> A_IWL<1212> A_IWL<1211> A_IWL<1210> A_IWL<1209> A_IWL<1208> A_IWL<1207> A_IWL<1206> A_IWL<1205> A_IWL<1204> A_IWL<1203> A_IWL<1202> A_IWL<1201> A_IWL<1200> A_IWL<1199> A_IWL<1198> A_IWL<1197> A_IWL<1196> A_IWL<1195> A_IWL<1194> A_IWL<1193> A_IWL<1192> A_IWL<1191> A_IWL<1190> A_IWL<1189> A_IWL<1188> A_IWL<1187> A_IWL<1186> A_IWL<1185> A_IWL<1184> A_IWL<1183> A_IWL<1182> A_IWL<1181> A_IWL<1180> A_IWL<1179> A_IWL<1178> A_IWL<1177> A_IWL<1176> A_IWL<1175> A_IWL<1174> A_IWL<1173> A_IWL<1172> A_IWL<1171> A_IWL<1170> A_IWL<1169> A_IWL<1168> A_IWL<1167> A_IWL<1166> A_IWL<1165> A_IWL<1164> A_IWL<1163> A_IWL<1162> A_IWL<1161> A_IWL<1160> A_IWL<1159> A_IWL<1158> A_IWL<1157> A_IWL<1156> A_IWL<1155> A_IWL<1154> A_IWL<1153> A_IWL<1152> A_IWL<1151> A_IWL<1150> A_IWL<1149> A_IWL<1148> A_IWL<1147> A_IWL<1146> A_IWL<1145> A_IWL<1144> A_IWL<1143> A_IWL<1142> A_IWL<1141> A_IWL<1140> A_IWL<1139> A_IWL<1138> A_IWL<1137> A_IWL<1136> A_IWL<1135> A_IWL<1134> A_IWL<1133> A_IWL<1132> A_IWL<1131> A_IWL<1130> A_IWL<1129> A_IWL<1128> A_IWL<1127> A_IWL<1126> A_IWL<1125> A_IWL<1124> A_IWL<1123> A_IWL<1122> A_IWL<1121> A_IWL<1120> A_IWL<1119> A_IWL<1118> A_IWL<1117> A_IWL<1116> A_IWL<1115> A_IWL<1114> A_IWL<1113> A_IWL<1112> A_IWL<1111> A_IWL<1110> A_IWL<1109> A_IWL<1108> A_IWL<1107> A_IWL<1106> A_IWL<1105> A_IWL<1104> A_IWL<1103> A_IWL<1102> A_IWL<1101> A_IWL<1100> A_IWL<1099> A_IWL<1098> A_IWL<1097> A_IWL<1096> A_IWL<1095> A_IWL<1094> A_IWL<1093> A_IWL<1092> A_IWL<1091> A_IWL<1090> A_IWL<1089> A_IWL<1088> A_IWL<1087> A_IWL<1086> A_IWL<1085> A_IWL<1084> A_IWL<1083> A_IWL<1082> A_IWL<1081> A_IWL<1080> A_IWL<1079> A_IWL<1078> A_IWL<1077> A_IWL<1076> A_IWL<1075> A_IWL<1074> A_IWL<1073> A_IWL<1072> A_IWL<1071> A_IWL<1070> A_IWL<1069> A_IWL<1068> A_IWL<1067> A_IWL<1066> A_IWL<1065> A_IWL<1064> A_IWL<1063> A_IWL<1062> A_IWL<1061> A_IWL<1060> A_IWL<1059> A_IWL<1058> A_IWL<1057> A_IWL<1056> A_IWL<1055> A_IWL<1054> A_IWL<1053> A_IWL<1052> A_IWL<1051> A_IWL<1050> A_IWL<1049> A_IWL<1048> A_IWL<1047> A_IWL<1046> A_IWL<1045> A_IWL<1044> A_IWL<1043> A_IWL<1042> A_IWL<1041> A_IWL<1040> A_IWL<1039> A_IWL<1038> A_IWL<1037> A_IWL<1036> A_IWL<1035> A_IWL<1034> A_IWL<1033> A_IWL<1032> A_IWL<1031> A_IWL<1030> A_IWL<1029> A_IWL<1028> A_IWL<1027> A_IWL<1026> A_IWL<1025> A_IWL<1024> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_COLUMN_pcell_0 +XCOL<3> A_BLC<7> A_BLC<6> A_BLC_TOP<7> A_BLC_TOP<6> A_BLT<7> A_BLT<6> A_BLT_TOP<7> A_BLT_TOP<6> A_IWL<767> A_IWL<766> A_IWL<765> A_IWL<764> A_IWL<763> A_IWL<762> A_IWL<761> A_IWL<760> A_IWL<759> A_IWL<758> A_IWL<757> A_IWL<756> A_IWL<755> A_IWL<754> A_IWL<753> A_IWL<752> A_IWL<751> A_IWL<750> A_IWL<749> A_IWL<748> A_IWL<747> A_IWL<746> A_IWL<745> A_IWL<744> A_IWL<743> A_IWL<742> A_IWL<741> A_IWL<740> A_IWL<739> A_IWL<738> A_IWL<737> A_IWL<736> A_IWL<735> A_IWL<734> A_IWL<733> A_IWL<732> A_IWL<731> A_IWL<730> A_IWL<729> A_IWL<728> A_IWL<727> A_IWL<726> A_IWL<725> A_IWL<724> A_IWL<723> A_IWL<722> A_IWL<721> A_IWL<720> A_IWL<719> A_IWL<718> A_IWL<717> A_IWL<716> A_IWL<715> A_IWL<714> A_IWL<713> A_IWL<712> A_IWL<711> A_IWL<710> A_IWL<709> A_IWL<708> A_IWL<707> A_IWL<706> A_IWL<705> A_IWL<704> A_IWL<703> A_IWL<702> A_IWL<701> A_IWL<700> A_IWL<699> A_IWL<698> A_IWL<697> A_IWL<696> A_IWL<695> A_IWL<694> A_IWL<693> A_IWL<692> A_IWL<691> A_IWL<690> A_IWL<689> A_IWL<688> A_IWL<687> A_IWL<686> A_IWL<685> A_IWL<684> A_IWL<683> A_IWL<682> A_IWL<681> A_IWL<680> A_IWL<679> A_IWL<678> A_IWL<677> A_IWL<676> A_IWL<675> A_IWL<674> A_IWL<673> A_IWL<672> A_IWL<671> A_IWL<670> A_IWL<669> A_IWL<668> A_IWL<667> A_IWL<666> A_IWL<665> A_IWL<664> A_IWL<663> A_IWL<662> A_IWL<661> A_IWL<660> A_IWL<659> A_IWL<658> A_IWL<657> A_IWL<656> A_IWL<655> A_IWL<654> A_IWL<653> A_IWL<652> A_IWL<651> A_IWL<650> A_IWL<649> A_IWL<648> A_IWL<647> A_IWL<646> A_IWL<645> A_IWL<644> A_IWL<643> A_IWL<642> A_IWL<641> A_IWL<640> A_IWL<639> A_IWL<638> A_IWL<637> A_IWL<636> A_IWL<635> A_IWL<634> A_IWL<633> A_IWL<632> A_IWL<631> A_IWL<630> A_IWL<629> A_IWL<628> A_IWL<627> A_IWL<626> A_IWL<625> A_IWL<624> A_IWL<623> A_IWL<622> A_IWL<621> A_IWL<620> A_IWL<619> A_IWL<618> A_IWL<617> A_IWL<616> A_IWL<615> A_IWL<614> A_IWL<613> A_IWL<612> A_IWL<611> A_IWL<610> A_IWL<609> A_IWL<608> A_IWL<607> A_IWL<606> A_IWL<605> A_IWL<604> A_IWL<603> A_IWL<602> A_IWL<601> A_IWL<600> A_IWL<599> A_IWL<598> A_IWL<597> A_IWL<596> A_IWL<595> A_IWL<594> A_IWL<593> A_IWL<592> A_IWL<591> A_IWL<590> A_IWL<589> A_IWL<588> A_IWL<587> A_IWL<586> A_IWL<585> A_IWL<584> A_IWL<583> A_IWL<582> A_IWL<581> A_IWL<580> A_IWL<579> A_IWL<578> A_IWL<577> A_IWL<576> A_IWL<575> A_IWL<574> A_IWL<573> A_IWL<572> A_IWL<571> A_IWL<570> A_IWL<569> A_IWL<568> A_IWL<567> A_IWL<566> A_IWL<565> A_IWL<564> A_IWL<563> A_IWL<562> A_IWL<561> A_IWL<560> A_IWL<559> A_IWL<558> A_IWL<557> A_IWL<556> A_IWL<555> A_IWL<554> A_IWL<553> A_IWL<552> A_IWL<551> A_IWL<550> A_IWL<549> A_IWL<548> A_IWL<547> A_IWL<546> A_IWL<545> A_IWL<544> A_IWL<543> A_IWL<542> A_IWL<541> A_IWL<540> A_IWL<539> A_IWL<538> A_IWL<537> A_IWL<536> A_IWL<535> A_IWL<534> A_IWL<533> A_IWL<532> A_IWL<531> A_IWL<530> A_IWL<529> A_IWL<528> A_IWL<527> A_IWL<526> A_IWL<525> A_IWL<524> A_IWL<523> A_IWL<522> A_IWL<521> A_IWL<520> A_IWL<519> A_IWL<518> A_IWL<517> A_IWL<516> A_IWL<515> A_IWL<514> A_IWL<513> A_IWL<512> A_IWL<1023> A_IWL<1022> A_IWL<1021> A_IWL<1020> A_IWL<1019> A_IWL<1018> A_IWL<1017> A_IWL<1016> A_IWL<1015> A_IWL<1014> A_IWL<1013> A_IWL<1012> A_IWL<1011> A_IWL<1010> A_IWL<1009> A_IWL<1008> A_IWL<1007> A_IWL<1006> A_IWL<1005> A_IWL<1004> A_IWL<1003> A_IWL<1002> A_IWL<1001> A_IWL<1000> A_IWL<999> A_IWL<998> A_IWL<997> A_IWL<996> A_IWL<995> A_IWL<994> A_IWL<993> A_IWL<992> A_IWL<991> A_IWL<990> A_IWL<989> A_IWL<988> A_IWL<987> A_IWL<986> A_IWL<985> A_IWL<984> A_IWL<983> A_IWL<982> A_IWL<981> A_IWL<980> A_IWL<979> A_IWL<978> A_IWL<977> A_IWL<976> A_IWL<975> A_IWL<974> A_IWL<973> A_IWL<972> A_IWL<971> A_IWL<970> A_IWL<969> A_IWL<968> A_IWL<967> A_IWL<966> A_IWL<965> A_IWL<964> A_IWL<963> A_IWL<962> A_IWL<961> A_IWL<960> A_IWL<959> A_IWL<958> A_IWL<957> A_IWL<956> A_IWL<955> A_IWL<954> A_IWL<953> A_IWL<952> A_IWL<951> A_IWL<950> A_IWL<949> A_IWL<948> A_IWL<947> A_IWL<946> A_IWL<945> A_IWL<944> A_IWL<943> A_IWL<942> A_IWL<941> A_IWL<940> A_IWL<939> A_IWL<938> A_IWL<937> A_IWL<936> A_IWL<935> A_IWL<934> A_IWL<933> A_IWL<932> A_IWL<931> A_IWL<930> A_IWL<929> A_IWL<928> A_IWL<927> A_IWL<926> A_IWL<925> A_IWL<924> A_IWL<923> A_IWL<922> A_IWL<921> A_IWL<920> A_IWL<919> A_IWL<918> A_IWL<917> A_IWL<916> A_IWL<915> A_IWL<914> A_IWL<913> A_IWL<912> A_IWL<911> A_IWL<910> A_IWL<909> A_IWL<908> A_IWL<907> A_IWL<906> A_IWL<905> A_IWL<904> A_IWL<903> A_IWL<902> A_IWL<901> A_IWL<900> A_IWL<899> A_IWL<898> A_IWL<897> A_IWL<896> A_IWL<895> A_IWL<894> A_IWL<893> A_IWL<892> A_IWL<891> A_IWL<890> A_IWL<889> A_IWL<888> A_IWL<887> A_IWL<886> A_IWL<885> A_IWL<884> A_IWL<883> A_IWL<882> A_IWL<881> A_IWL<880> A_IWL<879> A_IWL<878> A_IWL<877> A_IWL<876> A_IWL<875> A_IWL<874> A_IWL<873> A_IWL<872> A_IWL<871> A_IWL<870> A_IWL<869> A_IWL<868> A_IWL<867> A_IWL<866> A_IWL<865> A_IWL<864> A_IWL<863> A_IWL<862> A_IWL<861> A_IWL<860> A_IWL<859> A_IWL<858> A_IWL<857> A_IWL<856> A_IWL<855> A_IWL<854> A_IWL<853> A_IWL<852> A_IWL<851> A_IWL<850> A_IWL<849> A_IWL<848> A_IWL<847> A_IWL<846> A_IWL<845> A_IWL<844> A_IWL<843> A_IWL<842> A_IWL<841> A_IWL<840> A_IWL<839> A_IWL<838> A_IWL<837> A_IWL<836> A_IWL<835> A_IWL<834> A_IWL<833> A_IWL<832> A_IWL<831> A_IWL<830> A_IWL<829> A_IWL<828> A_IWL<827> A_IWL<826> A_IWL<825> A_IWL<824> A_IWL<823> A_IWL<822> A_IWL<821> A_IWL<820> A_IWL<819> A_IWL<818> A_IWL<817> A_IWL<816> A_IWL<815> A_IWL<814> A_IWL<813> A_IWL<812> A_IWL<811> A_IWL<810> A_IWL<809> A_IWL<808> A_IWL<807> A_IWL<806> A_IWL<805> A_IWL<804> A_IWL<803> A_IWL<802> A_IWL<801> A_IWL<800> A_IWL<799> A_IWL<798> A_IWL<797> A_IWL<796> A_IWL<795> A_IWL<794> A_IWL<793> A_IWL<792> A_IWL<791> A_IWL<790> A_IWL<789> A_IWL<788> A_IWL<787> A_IWL<786> A_IWL<785> A_IWL<784> A_IWL<783> A_IWL<782> A_IWL<781> A_IWL<780> A_IWL<779> A_IWL<778> A_IWL<777> A_IWL<776> A_IWL<775> A_IWL<774> A_IWL<773> A_IWL<772> A_IWL<771> A_IWL<770> A_IWL<769> A_IWL<768> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_COLUMN_pcell_0 +XCOL<2> A_BLC<5> A_BLC<4> A_BLC_TOP<5> A_BLC_TOP<4> A_BLT<5> A_BLT<4> A_BLT_TOP<5> A_BLT_TOP<4> A_IWL<511> A_IWL<510> A_IWL<509> A_IWL<508> A_IWL<507> A_IWL<506> A_IWL<505> A_IWL<504> A_IWL<503> A_IWL<502> A_IWL<501> A_IWL<500> A_IWL<499> A_IWL<498> A_IWL<497> A_IWL<496> A_IWL<495> A_IWL<494> A_IWL<493> A_IWL<492> A_IWL<491> A_IWL<490> A_IWL<489> A_IWL<488> A_IWL<487> A_IWL<486> A_IWL<485> A_IWL<484> A_IWL<483> A_IWL<482> A_IWL<481> A_IWL<480> A_IWL<479> A_IWL<478> A_IWL<477> A_IWL<476> A_IWL<475> A_IWL<474> A_IWL<473> A_IWL<472> A_IWL<471> A_IWL<470> A_IWL<469> A_IWL<468> A_IWL<467> A_IWL<466> A_IWL<465> A_IWL<464> A_IWL<463> A_IWL<462> A_IWL<461> A_IWL<460> A_IWL<459> A_IWL<458> A_IWL<457> A_IWL<456> A_IWL<455> A_IWL<454> A_IWL<453> A_IWL<452> A_IWL<451> A_IWL<450> A_IWL<449> A_IWL<448> A_IWL<447> A_IWL<446> A_IWL<445> A_IWL<444> A_IWL<443> A_IWL<442> A_IWL<441> A_IWL<440> A_IWL<439> A_IWL<438> A_IWL<437> A_IWL<436> A_IWL<435> A_IWL<434> A_IWL<433> A_IWL<432> A_IWL<431> A_IWL<430> A_IWL<429> A_IWL<428> A_IWL<427> A_IWL<426> A_IWL<425> A_IWL<424> A_IWL<423> A_IWL<422> A_IWL<421> A_IWL<420> A_IWL<419> A_IWL<418> A_IWL<417> A_IWL<416> A_IWL<415> A_IWL<414> A_IWL<413> A_IWL<412> A_IWL<411> A_IWL<410> A_IWL<409> A_IWL<408> A_IWL<407> A_IWL<406> A_IWL<405> A_IWL<404> A_IWL<403> A_IWL<402> A_IWL<401> A_IWL<400> A_IWL<399> A_IWL<398> A_IWL<397> A_IWL<396> A_IWL<395> A_IWL<394> A_IWL<393> A_IWL<392> A_IWL<391> A_IWL<390> A_IWL<389> A_IWL<388> A_IWL<387> A_IWL<386> A_IWL<385> A_IWL<384> A_IWL<383> A_IWL<382> A_IWL<381> A_IWL<380> A_IWL<379> A_IWL<378> A_IWL<377> A_IWL<376> A_IWL<375> A_IWL<374> A_IWL<373> A_IWL<372> A_IWL<371> A_IWL<370> A_IWL<369> A_IWL<368> A_IWL<367> A_IWL<366> A_IWL<365> A_IWL<364> A_IWL<363> A_IWL<362> A_IWL<361> A_IWL<360> A_IWL<359> A_IWL<358> A_IWL<357> A_IWL<356> A_IWL<355> A_IWL<354> A_IWL<353> A_IWL<352> A_IWL<351> A_IWL<350> A_IWL<349> A_IWL<348> A_IWL<347> A_IWL<346> A_IWL<345> A_IWL<344> A_IWL<343> A_IWL<342> A_IWL<341> A_IWL<340> A_IWL<339> A_IWL<338> A_IWL<337> A_IWL<336> A_IWL<335> A_IWL<334> A_IWL<333> A_IWL<332> A_IWL<331> A_IWL<330> A_IWL<329> A_IWL<328> A_IWL<327> A_IWL<326> A_IWL<325> A_IWL<324> A_IWL<323> A_IWL<322> A_IWL<321> A_IWL<320> A_IWL<319> A_IWL<318> A_IWL<317> A_IWL<316> A_IWL<315> A_IWL<314> A_IWL<313> A_IWL<312> A_IWL<311> A_IWL<310> A_IWL<309> A_IWL<308> A_IWL<307> A_IWL<306> A_IWL<305> A_IWL<304> A_IWL<303> A_IWL<302> A_IWL<301> A_IWL<300> A_IWL<299> A_IWL<298> A_IWL<297> A_IWL<296> A_IWL<295> A_IWL<294> A_IWL<293> A_IWL<292> A_IWL<291> A_IWL<290> A_IWL<289> A_IWL<288> A_IWL<287> A_IWL<286> A_IWL<285> A_IWL<284> A_IWL<283> A_IWL<282> A_IWL<281> A_IWL<280> A_IWL<279> A_IWL<278> A_IWL<277> A_IWL<276> A_IWL<275> A_IWL<274> A_IWL<273> A_IWL<272> A_IWL<271> A_IWL<270> A_IWL<269> A_IWL<268> A_IWL<267> A_IWL<266> A_IWL<265> A_IWL<264> A_IWL<263> A_IWL<262> A_IWL<261> A_IWL<260> A_IWL<259> A_IWL<258> A_IWL<257> A_IWL<256> A_IWL<767> A_IWL<766> A_IWL<765> A_IWL<764> A_IWL<763> A_IWL<762> A_IWL<761> A_IWL<760> A_IWL<759> A_IWL<758> A_IWL<757> A_IWL<756> A_IWL<755> A_IWL<754> A_IWL<753> A_IWL<752> A_IWL<751> A_IWL<750> A_IWL<749> A_IWL<748> A_IWL<747> A_IWL<746> A_IWL<745> A_IWL<744> A_IWL<743> A_IWL<742> A_IWL<741> A_IWL<740> A_IWL<739> A_IWL<738> A_IWL<737> A_IWL<736> A_IWL<735> A_IWL<734> A_IWL<733> A_IWL<732> A_IWL<731> A_IWL<730> A_IWL<729> A_IWL<728> A_IWL<727> A_IWL<726> A_IWL<725> A_IWL<724> A_IWL<723> A_IWL<722> A_IWL<721> A_IWL<720> A_IWL<719> A_IWL<718> A_IWL<717> A_IWL<716> A_IWL<715> A_IWL<714> A_IWL<713> A_IWL<712> A_IWL<711> A_IWL<710> A_IWL<709> A_IWL<708> A_IWL<707> A_IWL<706> A_IWL<705> A_IWL<704> A_IWL<703> A_IWL<702> A_IWL<701> A_IWL<700> A_IWL<699> A_IWL<698> A_IWL<697> A_IWL<696> A_IWL<695> A_IWL<694> A_IWL<693> A_IWL<692> A_IWL<691> A_IWL<690> A_IWL<689> A_IWL<688> A_IWL<687> A_IWL<686> A_IWL<685> A_IWL<684> A_IWL<683> A_IWL<682> A_IWL<681> A_IWL<680> A_IWL<679> A_IWL<678> A_IWL<677> A_IWL<676> A_IWL<675> A_IWL<674> A_IWL<673> A_IWL<672> A_IWL<671> A_IWL<670> A_IWL<669> A_IWL<668> A_IWL<667> A_IWL<666> A_IWL<665> A_IWL<664> A_IWL<663> A_IWL<662> A_IWL<661> A_IWL<660> A_IWL<659> A_IWL<658> A_IWL<657> A_IWL<656> A_IWL<655> A_IWL<654> A_IWL<653> A_IWL<652> A_IWL<651> A_IWL<650> A_IWL<649> A_IWL<648> A_IWL<647> A_IWL<646> A_IWL<645> A_IWL<644> A_IWL<643> A_IWL<642> A_IWL<641> A_IWL<640> A_IWL<639> A_IWL<638> A_IWL<637> A_IWL<636> A_IWL<635> A_IWL<634> A_IWL<633> A_IWL<632> A_IWL<631> A_IWL<630> A_IWL<629> A_IWL<628> A_IWL<627> A_IWL<626> A_IWL<625> A_IWL<624> A_IWL<623> A_IWL<622> A_IWL<621> A_IWL<620> A_IWL<619> A_IWL<618> A_IWL<617> A_IWL<616> A_IWL<615> A_IWL<614> A_IWL<613> A_IWL<612> A_IWL<611> A_IWL<610> A_IWL<609> A_IWL<608> A_IWL<607> A_IWL<606> A_IWL<605> A_IWL<604> A_IWL<603> A_IWL<602> A_IWL<601> A_IWL<600> A_IWL<599> A_IWL<598> A_IWL<597> A_IWL<596> A_IWL<595> A_IWL<594> A_IWL<593> A_IWL<592> A_IWL<591> A_IWL<590> A_IWL<589> A_IWL<588> A_IWL<587> A_IWL<586> A_IWL<585> A_IWL<584> A_IWL<583> A_IWL<582> A_IWL<581> A_IWL<580> A_IWL<579> A_IWL<578> A_IWL<577> A_IWL<576> A_IWL<575> A_IWL<574> A_IWL<573> A_IWL<572> A_IWL<571> A_IWL<570> A_IWL<569> A_IWL<568> A_IWL<567> A_IWL<566> A_IWL<565> A_IWL<564> A_IWL<563> A_IWL<562> A_IWL<561> A_IWL<560> A_IWL<559> A_IWL<558> A_IWL<557> A_IWL<556> A_IWL<555> A_IWL<554> A_IWL<553> A_IWL<552> A_IWL<551> A_IWL<550> A_IWL<549> A_IWL<548> A_IWL<547> A_IWL<546> A_IWL<545> A_IWL<544> A_IWL<543> A_IWL<542> A_IWL<541> A_IWL<540> A_IWL<539> A_IWL<538> A_IWL<537> A_IWL<536> A_IWL<535> A_IWL<534> A_IWL<533> A_IWL<532> A_IWL<531> A_IWL<530> A_IWL<529> A_IWL<528> A_IWL<527> A_IWL<526> A_IWL<525> A_IWL<524> A_IWL<523> A_IWL<522> A_IWL<521> A_IWL<520> A_IWL<519> A_IWL<518> A_IWL<517> A_IWL<516> A_IWL<515> A_IWL<514> A_IWL<513> A_IWL<512> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_COLUMN_pcell_0 +XCOL<1> A_BLC<3> A_BLC<2> A_BLC_TOP<3> A_BLC_TOP<2> A_BLT<3> A_BLT<2> A_BLT_TOP<3> A_BLT_TOP<2> A_IWL<255> A_IWL<254> A_IWL<253> A_IWL<252> A_IWL<251> A_IWL<250> A_IWL<249> A_IWL<248> A_IWL<247> A_IWL<246> A_IWL<245> A_IWL<244> A_IWL<243> A_IWL<242> A_IWL<241> A_IWL<240> A_IWL<239> A_IWL<238> A_IWL<237> A_IWL<236> A_IWL<235> A_IWL<234> A_IWL<233> A_IWL<232> A_IWL<231> A_IWL<230> A_IWL<229> A_IWL<228> A_IWL<227> A_IWL<226> A_IWL<225> A_IWL<224> A_IWL<223> A_IWL<222> A_IWL<221> A_IWL<220> A_IWL<219> A_IWL<218> A_IWL<217> A_IWL<216> A_IWL<215> A_IWL<214> A_IWL<213> A_IWL<212> A_IWL<211> A_IWL<210> A_IWL<209> A_IWL<208> A_IWL<207> A_IWL<206> A_IWL<205> A_IWL<204> A_IWL<203> A_IWL<202> A_IWL<201> A_IWL<200> A_IWL<199> A_IWL<198> A_IWL<197> A_IWL<196> A_IWL<195> A_IWL<194> A_IWL<193> A_IWL<192> A_IWL<191> A_IWL<190> A_IWL<189> A_IWL<188> A_IWL<187> A_IWL<186> A_IWL<185> A_IWL<184> A_IWL<183> A_IWL<182> A_IWL<181> A_IWL<180> A_IWL<179> A_IWL<178> A_IWL<177> A_IWL<176> A_IWL<175> A_IWL<174> A_IWL<173> A_IWL<172> A_IWL<171> A_IWL<170> A_IWL<169> A_IWL<168> A_IWL<167> A_IWL<166> A_IWL<165> A_IWL<164> A_IWL<163> A_IWL<162> A_IWL<161> A_IWL<160> A_IWL<159> A_IWL<158> A_IWL<157> A_IWL<156> A_IWL<155> A_IWL<154> A_IWL<153> A_IWL<152> A_IWL<151> A_IWL<150> A_IWL<149> A_IWL<148> A_IWL<147> A_IWL<146> A_IWL<145> A_IWL<144> A_IWL<143> A_IWL<142> A_IWL<141> A_IWL<140> A_IWL<139> A_IWL<138> A_IWL<137> A_IWL<136> A_IWL<135> A_IWL<134> A_IWL<133> A_IWL<132> A_IWL<131> A_IWL<130> A_IWL<129> A_IWL<128> A_IWL<127> A_IWL<126> A_IWL<125> A_IWL<124> A_IWL<123> A_IWL<122> A_IWL<121> A_IWL<120> A_IWL<119> A_IWL<118> A_IWL<117> A_IWL<116> A_IWL<115> A_IWL<114> A_IWL<113> A_IWL<112> A_IWL<111> A_IWL<110> A_IWL<109> A_IWL<108> A_IWL<107> A_IWL<106> A_IWL<105> A_IWL<104> A_IWL<103> A_IWL<102> A_IWL<101> A_IWL<100> A_IWL<99> A_IWL<98> A_IWL<97> A_IWL<96> A_IWL<95> A_IWL<94> A_IWL<93> A_IWL<92> A_IWL<91> A_IWL<90> A_IWL<89> A_IWL<88> A_IWL<87> A_IWL<86> A_IWL<85> A_IWL<84> A_IWL<83> A_IWL<82> A_IWL<81> A_IWL<80> A_IWL<79> A_IWL<78> A_IWL<77> A_IWL<76> A_IWL<75> A_IWL<74> A_IWL<73> A_IWL<72> A_IWL<71> A_IWL<70> A_IWL<69> A_IWL<68> A_IWL<67> A_IWL<66> A_IWL<65> A_IWL<64> A_IWL<63> A_IWL<62> A_IWL<61> A_IWL<60> A_IWL<59> A_IWL<58> A_IWL<57> A_IWL<56> A_IWL<55> A_IWL<54> A_IWL<53> A_IWL<52> A_IWL<51> A_IWL<50> A_IWL<49> A_IWL<48> A_IWL<47> A_IWL<46> A_IWL<45> A_IWL<44> A_IWL<43> A_IWL<42> A_IWL<41> A_IWL<40> A_IWL<39> A_IWL<38> A_IWL<37> A_IWL<36> A_IWL<35> A_IWL<34> A_IWL<33> A_IWL<32> A_IWL<31> A_IWL<30> A_IWL<29> A_IWL<28> A_IWL<27> A_IWL<26> A_IWL<25> A_IWL<24> A_IWL<23> A_IWL<22> A_IWL<21> A_IWL<20> A_IWL<19> A_IWL<18> A_IWL<17> A_IWL<16> A_IWL<15> A_IWL<14> A_IWL<13> A_IWL<12> A_IWL<11> A_IWL<10> A_IWL<9> A_IWL<8> A_IWL<7> A_IWL<6> A_IWL<5> A_IWL<4> A_IWL<3> A_IWL<2> A_IWL<1> A_IWL<0> A_IWL<511> A_IWL<510> A_IWL<509> A_IWL<508> A_IWL<507> A_IWL<506> A_IWL<505> A_IWL<504> A_IWL<503> A_IWL<502> A_IWL<501> A_IWL<500> A_IWL<499> A_IWL<498> A_IWL<497> A_IWL<496> A_IWL<495> A_IWL<494> A_IWL<493> A_IWL<492> A_IWL<491> A_IWL<490> A_IWL<489> A_IWL<488> A_IWL<487> A_IWL<486> A_IWL<485> A_IWL<484> A_IWL<483> A_IWL<482> A_IWL<481> A_IWL<480> A_IWL<479> A_IWL<478> A_IWL<477> A_IWL<476> A_IWL<475> A_IWL<474> A_IWL<473> A_IWL<472> A_IWL<471> A_IWL<470> A_IWL<469> A_IWL<468> A_IWL<467> A_IWL<466> A_IWL<465> A_IWL<464> A_IWL<463> A_IWL<462> A_IWL<461> A_IWL<460> A_IWL<459> A_IWL<458> A_IWL<457> A_IWL<456> A_IWL<455> A_IWL<454> A_IWL<453> A_IWL<452> A_IWL<451> A_IWL<450> A_IWL<449> A_IWL<448> A_IWL<447> A_IWL<446> A_IWL<445> A_IWL<444> A_IWL<443> A_IWL<442> A_IWL<441> A_IWL<440> A_IWL<439> A_IWL<438> A_IWL<437> A_IWL<436> A_IWL<435> A_IWL<434> A_IWL<433> A_IWL<432> A_IWL<431> A_IWL<430> A_IWL<429> A_IWL<428> A_IWL<427> A_IWL<426> A_IWL<425> A_IWL<424> A_IWL<423> A_IWL<422> A_IWL<421> A_IWL<420> A_IWL<419> A_IWL<418> A_IWL<417> A_IWL<416> A_IWL<415> A_IWL<414> A_IWL<413> A_IWL<412> A_IWL<411> A_IWL<410> A_IWL<409> A_IWL<408> A_IWL<407> A_IWL<406> A_IWL<405> A_IWL<404> A_IWL<403> A_IWL<402> A_IWL<401> A_IWL<400> A_IWL<399> A_IWL<398> A_IWL<397> A_IWL<396> A_IWL<395> A_IWL<394> A_IWL<393> A_IWL<392> A_IWL<391> A_IWL<390> A_IWL<389> A_IWL<388> A_IWL<387> A_IWL<386> A_IWL<385> A_IWL<384> A_IWL<383> A_IWL<382> A_IWL<381> A_IWL<380> A_IWL<379> A_IWL<378> A_IWL<377> A_IWL<376> A_IWL<375> A_IWL<374> A_IWL<373> A_IWL<372> A_IWL<371> A_IWL<370> A_IWL<369> A_IWL<368> A_IWL<367> A_IWL<366> A_IWL<365> A_IWL<364> A_IWL<363> A_IWL<362> A_IWL<361> A_IWL<360> A_IWL<359> A_IWL<358> A_IWL<357> A_IWL<356> A_IWL<355> A_IWL<354> A_IWL<353> A_IWL<352> A_IWL<351> A_IWL<350> A_IWL<349> A_IWL<348> A_IWL<347> A_IWL<346> A_IWL<345> A_IWL<344> A_IWL<343> A_IWL<342> A_IWL<341> A_IWL<340> A_IWL<339> A_IWL<338> A_IWL<337> A_IWL<336> A_IWL<335> A_IWL<334> A_IWL<333> A_IWL<332> A_IWL<331> A_IWL<330> A_IWL<329> A_IWL<328> A_IWL<327> A_IWL<326> A_IWL<325> A_IWL<324> A_IWL<323> A_IWL<322> A_IWL<321> A_IWL<320> A_IWL<319> A_IWL<318> A_IWL<317> A_IWL<316> A_IWL<315> A_IWL<314> A_IWL<313> A_IWL<312> A_IWL<311> A_IWL<310> A_IWL<309> A_IWL<308> A_IWL<307> A_IWL<306> A_IWL<305> A_IWL<304> A_IWL<303> A_IWL<302> A_IWL<301> A_IWL<300> A_IWL<299> A_IWL<298> A_IWL<297> A_IWL<296> A_IWL<295> A_IWL<294> A_IWL<293> A_IWL<292> A_IWL<291> A_IWL<290> A_IWL<289> A_IWL<288> A_IWL<287> A_IWL<286> A_IWL<285> A_IWL<284> A_IWL<283> A_IWL<282> A_IWL<281> A_IWL<280> A_IWL<279> A_IWL<278> A_IWL<277> A_IWL<276> A_IWL<275> A_IWL<274> A_IWL<273> A_IWL<272> A_IWL<271> A_IWL<270> A_IWL<269> A_IWL<268> A_IWL<267> A_IWL<266> A_IWL<265> A_IWL<264> A_IWL<263> A_IWL<262> A_IWL<261> A_IWL<260> A_IWL<259> A_IWL<258> A_IWL<257> A_IWL<256> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_COLUMN_pcell_0 +XCOL<0> A_BLC<1> A_BLC<0> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT<1> A_BLT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_WL<255> A_WL<254> A_WL<253> A_WL<252> A_WL<251> A_WL<250> A_WL<249> A_WL<248> A_WL<247> A_WL<246> A_WL<245> A_WL<244> A_WL<243> A_WL<242> A_WL<241> A_WL<240> A_WL<239> A_WL<238> A_WL<237> A_WL<236> A_WL<235> A_WL<234> A_WL<233> A_WL<232> A_WL<231> A_WL<230> A_WL<229> A_WL<228> A_WL<227> A_WL<226> A_WL<225> A_WL<224> A_WL<223> A_WL<222> A_WL<221> A_WL<220> A_WL<219> A_WL<218> A_WL<217> A_WL<216> A_WL<215> A_WL<214> A_WL<213> A_WL<212> A_WL<211> A_WL<210> A_WL<209> A_WL<208> A_WL<207> A_WL<206> A_WL<205> A_WL<204> A_WL<203> A_WL<202> A_WL<201> A_WL<200> A_WL<199> A_WL<198> A_WL<197> A_WL<196> A_WL<195> A_WL<194> A_WL<193> A_WL<192> A_WL<191> A_WL<190> A_WL<189> A_WL<188> A_WL<187> A_WL<186> A_WL<185> A_WL<184> A_WL<183> A_WL<182> A_WL<181> A_WL<180> A_WL<179> A_WL<178> A_WL<177> A_WL<176> A_WL<175> A_WL<174> A_WL<173> A_WL<172> A_WL<171> A_WL<170> A_WL<169> A_WL<168> A_WL<167> A_WL<166> A_WL<165> A_WL<164> A_WL<163> A_WL<162> A_WL<161> A_WL<160> A_WL<159> A_WL<158> A_WL<157> A_WL<156> A_WL<155> A_WL<154> A_WL<153> A_WL<152> A_WL<151> A_WL<150> A_WL<149> A_WL<148> A_WL<147> A_WL<146> A_WL<145> A_WL<144> A_WL<143> A_WL<142> A_WL<141> A_WL<140> A_WL<139> A_WL<138> A_WL<137> A_WL<136> A_WL<135> A_WL<134> A_WL<133> A_WL<132> A_WL<131> A_WL<130> A_WL<129> A_WL<128> A_WL<127> A_WL<126> A_WL<125> A_WL<124> A_WL<123> A_WL<122> A_WL<121> A_WL<120> A_WL<119> A_WL<118> A_WL<117> A_WL<116> A_WL<115> A_WL<114> A_WL<113> A_WL<112> A_WL<111> A_WL<110> A_WL<109> A_WL<108> A_WL<107> A_WL<106> A_WL<105> A_WL<104> A_WL<103> A_WL<102> A_WL<101> A_WL<100> A_WL<99> A_WL<98> A_WL<97> A_WL<96> A_WL<95> A_WL<94> A_WL<93> A_WL<92> A_WL<91> A_WL<90> A_WL<89> A_WL<88> A_WL<87> A_WL<86> A_WL<85> A_WL<84> A_WL<83> A_WL<82> A_WL<81> A_WL<80> A_WL<79> A_WL<78> A_WL<77> A_WL<76> A_WL<75> A_WL<74> A_WL<73> A_WL<72> A_WL<71> A_WL<70> A_WL<69> A_WL<68> A_WL<67> A_WL<66> A_WL<65> A_WL<64> A_WL<63> A_WL<62> A_WL<61> A_WL<60> A_WL<59> A_WL<58> A_WL<57> A_WL<56> A_WL<55> A_WL<54> A_WL<53> A_WL<52> A_WL<51> A_WL<50> A_WL<49> A_WL<48> A_WL<47> A_WL<46> A_WL<45> A_WL<44> A_WL<43> A_WL<42> A_WL<41> A_WL<40> A_WL<39> A_WL<38> A_WL<37> A_WL<36> A_WL<35> A_WL<34> A_WL<33> A_WL<32> A_WL<31> A_WL<30> A_WL<29> A_WL<28> A_WL<27> A_WL<26> A_WL<25> A_WL<24> A_WL<23> A_WL<22> A_WL<21> A_WL<20> A_WL<19> A_WL<18> A_WL<17> A_WL<16> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> A_IWL<255> A_IWL<254> A_IWL<253> A_IWL<252> A_IWL<251> A_IWL<250> A_IWL<249> A_IWL<248> A_IWL<247> A_IWL<246> A_IWL<245> A_IWL<244> A_IWL<243> A_IWL<242> A_IWL<241> A_IWL<240> A_IWL<239> A_IWL<238> A_IWL<237> A_IWL<236> A_IWL<235> A_IWL<234> A_IWL<233> A_IWL<232> A_IWL<231> A_IWL<230> A_IWL<229> A_IWL<228> A_IWL<227> A_IWL<226> A_IWL<225> A_IWL<224> A_IWL<223> A_IWL<222> A_IWL<221> A_IWL<220> A_IWL<219> A_IWL<218> A_IWL<217> A_IWL<216> A_IWL<215> A_IWL<214> A_IWL<213> A_IWL<212> A_IWL<211> A_IWL<210> A_IWL<209> A_IWL<208> A_IWL<207> A_IWL<206> A_IWL<205> A_IWL<204> A_IWL<203> A_IWL<202> A_IWL<201> A_IWL<200> A_IWL<199> A_IWL<198> A_IWL<197> A_IWL<196> A_IWL<195> A_IWL<194> A_IWL<193> A_IWL<192> A_IWL<191> A_IWL<190> A_IWL<189> A_IWL<188> A_IWL<187> A_IWL<186> A_IWL<185> A_IWL<184> A_IWL<183> A_IWL<182> A_IWL<181> A_IWL<180> A_IWL<179> A_IWL<178> A_IWL<177> A_IWL<176> A_IWL<175> A_IWL<174> A_IWL<173> A_IWL<172> A_IWL<171> A_IWL<170> A_IWL<169> A_IWL<168> A_IWL<167> A_IWL<166> A_IWL<165> A_IWL<164> A_IWL<163> A_IWL<162> A_IWL<161> A_IWL<160> A_IWL<159> A_IWL<158> A_IWL<157> A_IWL<156> A_IWL<155> A_IWL<154> A_IWL<153> A_IWL<152> A_IWL<151> A_IWL<150> A_IWL<149> A_IWL<148> A_IWL<147> A_IWL<146> A_IWL<145> A_IWL<144> A_IWL<143> A_IWL<142> A_IWL<141> A_IWL<140> A_IWL<139> A_IWL<138> A_IWL<137> A_IWL<136> A_IWL<135> A_IWL<134> A_IWL<133> A_IWL<132> A_IWL<131> A_IWL<130> A_IWL<129> A_IWL<128> A_IWL<127> A_IWL<126> A_IWL<125> A_IWL<124> A_IWL<123> A_IWL<122> A_IWL<121> A_IWL<120> A_IWL<119> A_IWL<118> A_IWL<117> A_IWL<116> A_IWL<115> A_IWL<114> A_IWL<113> A_IWL<112> A_IWL<111> A_IWL<110> A_IWL<109> A_IWL<108> A_IWL<107> A_IWL<106> A_IWL<105> A_IWL<104> A_IWL<103> A_IWL<102> A_IWL<101> A_IWL<100> A_IWL<99> A_IWL<98> A_IWL<97> A_IWL<96> A_IWL<95> A_IWL<94> A_IWL<93> A_IWL<92> A_IWL<91> A_IWL<90> A_IWL<89> A_IWL<88> A_IWL<87> A_IWL<86> A_IWL<85> A_IWL<84> A_IWL<83> A_IWL<82> A_IWL<81> A_IWL<80> A_IWL<79> A_IWL<78> A_IWL<77> A_IWL<76> A_IWL<75> A_IWL<74> A_IWL<73> A_IWL<72> A_IWL<71> A_IWL<70> A_IWL<69> A_IWL<68> A_IWL<67> A_IWL<66> A_IWL<65> A_IWL<64> A_IWL<63> A_IWL<62> A_IWL<61> A_IWL<60> A_IWL<59> A_IWL<58> A_IWL<57> A_IWL<56> A_IWL<55> A_IWL<54> A_IWL<53> A_IWL<52> A_IWL<51> A_IWL<50> A_IWL<49> A_IWL<48> A_IWL<47> A_IWL<46> A_IWL<45> A_IWL<44> A_IWL<43> A_IWL<42> A_IWL<41> A_IWL<40> A_IWL<39> A_IWL<38> A_IWL<37> A_IWL<36> A_IWL<35> A_IWL<34> A_IWL<33> A_IWL<32> A_IWL<31> A_IWL<30> A_IWL<29> A_IWL<28> A_IWL<27> A_IWL<26> A_IWL<25> A_IWL<24> A_IWL<23> A_IWL<22> A_IWL<21> A_IWL<20> A_IWL<19> A_IWL<18> A_IWL<17> A_IWL<16> A_IWL<15> A_IWL<14> A_IWL<13> A_IWL<12> A_IWL<11> A_IWL<10> A_IWL<9> A_IWL<8> A_IWL<7> A_IWL<6> A_IWL<5> A_IWL<4> A_IWL<3> A_IWL<2> A_IWL<1> A_IWL<0> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_COLUMN_pcell_0 +.ENDS + + + + +.SUBCKT RM_IHPSG13_1024x8_c2_1P_DLY_pcell_2 A Z VDD VSS + XIDL<2> D<7> Z VDD VSS / RSC_IHPSG13_CDLYX1 + XIDL<1> D<6> D<7> VDD VSS / RSC_IHPSG13_CDLYX1 + XIDM<6> D<5> D<6> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<5> D<4> D<5> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<4> D<3> D<4> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY +.ENDS + + +.SUBCKT RM_IHPSG13_1024x8_c2_1P_DLY_pcell_3 A Z VDD VSS + XIDL<4> D<7> Z VDD VSS / RSC_IHPSG13_CDLYX1 + XIDL<3> D<6> D<7> VDD VSS / RSC_IHPSG13_CDLYX1 + XIDL<2> D<5> D<6> VDD VSS / RSC_IHPSG13_CDLYX1 + XIDL<1> D<4> D<5> VDD VSS / RSC_IHPSG13_CDLYX1 + XIDM<4> D<3> D<4> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY +.ENDS + + + +.SUBCKT RM_IHPSG13_1P_1024x8_c2_bm_bist A_ADDR<9> A_ADDR<8> A_ADDR<7> A_ADDR<6> A_ADDR<5> A_ADDR<4> A_ADDR<3> A_ADDR<2> A_ADDR<1> A_ADDR<0> A_BIST_ADDR<9> A_BIST_ADDR<8> A_BIST_ADDR<7> A_BIST_ADDR<6> A_BIST_ADDR<5> A_BIST_ADDR<4> A_BIST_ADDR<3> A_BIST_ADDR<2> A_BIST_ADDR<1> A_BIST_ADDR<0> A_BIST_BM<7> A_BIST_BM<6> A_BIST_BM<5> A_BIST_BM<4> A_BIST_BM<3> A_BIST_BM<2> A_BIST_BM<1> A_BIST_BM<0> A_BIST_CLK A_BIST_DIN<7> A_BIST_DIN<6> A_BIST_DIN<5> A_BIST_DIN<4> A_BIST_DIN<3> A_BIST_DIN<2> A_BIST_DIN<1> A_BIST_DIN<0> A_BIST_EN A_BIST_MEN A_BIST_REN A_BIST_WEN A_BM<7> A_BM<6> A_BM<5> A_BM<4> A_BM<3> A_BM<2> A_BM<1> A_BM<0> A_CLK A_DIN<7> A_DIN<6> A_DIN<5> A_DIN<4> A_DIN<3> A_DIN<2> A_DIN<1> A_DIN<0> A_DLY A_DOUT<7> A_DOUT<6> A_DOUT<5> A_DOUT<4> A_DOUT<3> A_DOUT<2> A_DOUT<1> A_DOUT<0> A_MEN A_REN A_WEN VDD! VDDARRAY! VSS! + + +XRAM<1> a_blc_r<15> a_blc_r<14> a_blc_r<13> a_blc_r<12> a_blc_r<11> a_blc_r<10> a_blc_r<9> a_blc_r<8> a_blc_r<7> a_blc_r<6> a_blc_r<5> a_blc_r<4> a_blc_r<3> a_blc_r<2> a_blc_r<1> a_blc_r<0> a_blt_r<15> a_blt_r<14> a_blt_r<13> a_blt_r<12> a_blt_r<11> a_blt_r<10> a_blt_r<9> a_blt_r<8> a_blt_r<7> a_blt_r<6> a_blt_r<5> a_blt_r<4> a_blt_r<3> a_blt_r<2> a_blt_r<1> a_blt_r<0> a_wl_r<255> a_wl_r<254> a_wl_r<253> a_wl_r<252> a_wl_r<251> a_wl_r<250> a_wl_r<249> a_wl_r<248> a_wl_r<247> a_wl_r<246> a_wl_r<245> a_wl_r<244> a_wl_r<243> a_wl_r<242> a_wl_r<241> a_wl_r<240> a_wl_r<239> a_wl_r<238> a_wl_r<237> a_wl_r<236> a_wl_r<235> a_wl_r<234> a_wl_r<233> a_wl_r<232> a_wl_r<231> a_wl_r<230> a_wl_r<229> a_wl_r<228> a_wl_r<227> a_wl_r<226> a_wl_r<225> a_wl_r<224> a_wl_r<223> a_wl_r<222> a_wl_r<221> a_wl_r<220> a_wl_r<219> a_wl_r<218> a_wl_r<217> a_wl_r<216> a_wl_r<215> a_wl_r<214> a_wl_r<213> a_wl_r<212> a_wl_r<211> a_wl_r<210> a_wl_r<209> a_wl_r<208> a_wl_r<207> a_wl_r<206> a_wl_r<205> a_wl_r<204> a_wl_r<203> a_wl_r<202> a_wl_r<201> a_wl_r<200> a_wl_r<199> a_wl_r<198> a_wl_r<197> a_wl_r<196> a_wl_r<195> a_wl_r<194> a_wl_r<193> a_wl_r<192> a_wl_r<191> a_wl_r<190> a_wl_r<189> a_wl_r<188> a_wl_r<187> a_wl_r<186> a_wl_r<185> a_wl_r<184> a_wl_r<183> a_wl_r<182> a_wl_r<181> a_wl_r<180> a_wl_r<179> a_wl_r<178> a_wl_r<177> a_wl_r<176> a_wl_r<175> a_wl_r<174> a_wl_r<173> a_wl_r<172> a_wl_r<171> a_wl_r<170> a_wl_r<169> a_wl_r<168> a_wl_r<167> a_wl_r<166> a_wl_r<165> a_wl_r<164> a_wl_r<163> a_wl_r<162> a_wl_r<161> a_wl_r<160> a_wl_r<159> a_wl_r<158> a_wl_r<157> a_wl_r<156> a_wl_r<155> a_wl_r<154> a_wl_r<153> a_wl_r<152> a_wl_r<151> a_wl_r<150> a_wl_r<149> a_wl_r<148> a_wl_r<147> a_wl_r<146> a_wl_r<145> a_wl_r<144> a_wl_r<143> a_wl_r<142> a_wl_r<141> a_wl_r<140> a_wl_r<139> a_wl_r<138> a_wl_r<137> a_wl_r<136> a_wl_r<135> a_wl_r<134> a_wl_r<133> a_wl_r<132> a_wl_r<131> a_wl_r<130> a_wl_r<129> a_wl_r<128> a_wl_r<127> a_wl_r<126> a_wl_r<125> a_wl_r<124> a_wl_r<123> a_wl_r<122> a_wl_r<121> a_wl_r<120> a_wl_r<119> a_wl_r<118> a_wl_r<117> a_wl_r<116> a_wl_r<115> a_wl_r<114> a_wl_r<113> a_wl_r<112> a_wl_r<111> a_wl_r<110> a_wl_r<109> a_wl_r<108> a_wl_r<107> a_wl_r<106> a_wl_r<105> a_wl_r<104> a_wl_r<103> a_wl_r<102> a_wl_r<101> a_wl_r<100> a_wl_r<99> a_wl_r<98> a_wl_r<97> a_wl_r<96> a_wl_r<95> a_wl_r<94> a_wl_r<93> a_wl_r<92> a_wl_r<91> a_wl_r<90> a_wl_r<89> a_wl_r<88> a_wl_r<87> a_wl_r<86> a_wl_r<85> a_wl_r<84> a_wl_r<83> a_wl_r<82> a_wl_r<81> a_wl_r<80> a_wl_r<79> a_wl_r<78> a_wl_r<77> a_wl_r<76> a_wl_r<75> a_wl_r<74> a_wl_r<73> a_wl_r<72> a_wl_r<71> a_wl_r<70> a_wl_r<69> a_wl_r<68> a_wl_r<67> a_wl_r<66> a_wl_r<65> a_wl_r<64> a_wl_r<63> a_wl_r<62> a_wl_r<61> a_wl_r<60> a_wl_r<59> a_wl_r<58> a_wl_r<57> a_wl_r<56> a_wl_r<55> a_wl_r<54> a_wl_r<53> a_wl_r<52> a_wl_r<51> a_wl_r<50> a_wl_r<49> a_wl_r<48> a_wl_r<47> a_wl_r<46> a_wl_r<45> a_wl_r<44> a_wl_r<43> a_wl_r<42> a_wl_r<41> a_wl_r<40> a_wl_r<39> a_wl_r<38> a_wl_r<37> a_wl_r<36> a_wl_r<35> a_wl_r<34> a_wl_r<33> a_wl_r<32> a_wl_r<31> a_wl_r<30> a_wl_r<29> a_wl_r<28> a_wl_r<27> a_wl_r<26> a_wl_r<25> a_wl_r<24> a_wl_r<23> a_wl_r<22> a_wl_r<21> a_wl_r<20> a_wl_r<19> a_wl_r<18> a_wl_r<17> a_wl_r<16> a_wl_r<15> a_wl_r<14> a_wl_r<13> a_wl_r<12> a_wl_r<11> a_wl_r<10> a_wl_r<9> a_wl_r<8> a_wl_r<7> a_wl_r<6> a_wl_r<5> a_wl_r<4> a_wl_r<3> a_wl_r<2> a_wl_r<1> a_wl_r<0> VDDARRAY! VSS! / RM_IHPSG13_1024x8_c2_1P_MATRIX_pcell_1 +XRAM<0> a_blc_l<15> a_blc_l<14> a_blc_l<13> a_blc_l<12> a_blc_l<11> a_blc_l<10> a_blc_l<9> a_blc_l<8> a_blc_l<7> a_blc_l<6> a_blc_l<5> a_blc_l<4> a_blc_l<3> a_blc_l<2> a_blc_l<1> a_blc_l<0> a_blt_l<15> a_blt_l<14> a_blt_l<13> a_blt_l<12> a_blt_l<11> a_blt_l<10> a_blt_l<9> a_blt_l<8> a_blt_l<7> a_blt_l<6> a_blt_l<5> a_blt_l<4> a_blt_l<3> a_blt_l<2> a_blt_l<1> a_blt_l<0> a_wl_l<255> a_wl_l<254> a_wl_l<253> a_wl_l<252> a_wl_l<251> a_wl_l<250> a_wl_l<249> a_wl_l<248> a_wl_l<247> a_wl_l<246> a_wl_l<245> a_wl_l<244> a_wl_l<243> a_wl_l<242> a_wl_l<241> a_wl_l<240> a_wl_l<239> a_wl_l<238> a_wl_l<237> a_wl_l<236> a_wl_l<235> a_wl_l<234> a_wl_l<233> a_wl_l<232> a_wl_l<231> a_wl_l<230> a_wl_l<229> a_wl_l<228> a_wl_l<227> a_wl_l<226> a_wl_l<225> a_wl_l<224> a_wl_l<223> a_wl_l<222> a_wl_l<221> a_wl_l<220> a_wl_l<219> a_wl_l<218> a_wl_l<217> a_wl_l<216> a_wl_l<215> a_wl_l<214> a_wl_l<213> a_wl_l<212> a_wl_l<211> a_wl_l<210> a_wl_l<209> a_wl_l<208> a_wl_l<207> a_wl_l<206> a_wl_l<205> a_wl_l<204> a_wl_l<203> a_wl_l<202> a_wl_l<201> a_wl_l<200> a_wl_l<199> a_wl_l<198> a_wl_l<197> a_wl_l<196> a_wl_l<195> a_wl_l<194> a_wl_l<193> a_wl_l<192> a_wl_l<191> a_wl_l<190> a_wl_l<189> a_wl_l<188> a_wl_l<187> a_wl_l<186> a_wl_l<185> a_wl_l<184> a_wl_l<183> a_wl_l<182> a_wl_l<181> a_wl_l<180> a_wl_l<179> a_wl_l<178> a_wl_l<177> a_wl_l<176> a_wl_l<175> a_wl_l<174> a_wl_l<173> a_wl_l<172> a_wl_l<171> a_wl_l<170> a_wl_l<169> a_wl_l<168> a_wl_l<167> a_wl_l<166> a_wl_l<165> a_wl_l<164> a_wl_l<163> a_wl_l<162> a_wl_l<161> a_wl_l<160> a_wl_l<159> a_wl_l<158> a_wl_l<157> a_wl_l<156> a_wl_l<155> a_wl_l<154> a_wl_l<153> a_wl_l<152> a_wl_l<151> a_wl_l<150> a_wl_l<149> a_wl_l<148> a_wl_l<147> a_wl_l<146> a_wl_l<145> a_wl_l<144> a_wl_l<143> a_wl_l<142> a_wl_l<141> a_wl_l<140> a_wl_l<139> a_wl_l<138> a_wl_l<137> a_wl_l<136> a_wl_l<135> a_wl_l<134> a_wl_l<133> a_wl_l<132> a_wl_l<131> a_wl_l<130> a_wl_l<129> a_wl_l<128> a_wl_l<127> a_wl_l<126> a_wl_l<125> a_wl_l<124> a_wl_l<123> a_wl_l<122> a_wl_l<121> a_wl_l<120> a_wl_l<119> a_wl_l<118> a_wl_l<117> a_wl_l<116> a_wl_l<115> a_wl_l<114> a_wl_l<113> a_wl_l<112> a_wl_l<111> a_wl_l<110> a_wl_l<109> a_wl_l<108> a_wl_l<107> a_wl_l<106> a_wl_l<105> a_wl_l<104> a_wl_l<103> a_wl_l<102> a_wl_l<101> a_wl_l<100> a_wl_l<99> a_wl_l<98> a_wl_l<97> a_wl_l<96> a_wl_l<95> a_wl_l<94> a_wl_l<93> a_wl_l<92> a_wl_l<91> a_wl_l<90> a_wl_l<89> a_wl_l<88> a_wl_l<87> a_wl_l<86> a_wl_l<85> a_wl_l<84> a_wl_l<83> a_wl_l<82> a_wl_l<81> a_wl_l<80> a_wl_l<79> a_wl_l<78> a_wl_l<77> a_wl_l<76> a_wl_l<75> a_wl_l<74> a_wl_l<73> a_wl_l<72> a_wl_l<71> a_wl_l<70> a_wl_l<69> a_wl_l<68> a_wl_l<67> a_wl_l<66> a_wl_l<65> a_wl_l<64> a_wl_l<63> a_wl_l<62> a_wl_l<61> a_wl_l<60> a_wl_l<59> a_wl_l<58> a_wl_l<57> a_wl_l<56> a_wl_l<55> a_wl_l<54> a_wl_l<53> a_wl_l<52> a_wl_l<51> a_wl_l<50> a_wl_l<49> a_wl_l<48> a_wl_l<47> a_wl_l<46> a_wl_l<45> a_wl_l<44> a_wl_l<43> a_wl_l<42> a_wl_l<41> a_wl_l<40> a_wl_l<39> a_wl_l<38> a_wl_l<37> a_wl_l<36> a_wl_l<35> a_wl_l<34> a_wl_l<33> a_wl_l<32> a_wl_l<31> a_wl_l<30> a_wl_l<29> a_wl_l<28> a_wl_l<27> a_wl_l<26> a_wl_l<25> a_wl_l<24> a_wl_l<23> a_wl_l<22> a_wl_l<21> a_wl_l<20> a_wl_l<19> a_wl_l<18> a_wl_l<17> a_wl_l<16> a_wl_l<15> a_wl_l<14> a_wl_l<13> a_wl_l<12> a_wl_l<11> a_wl_l<10> a_wl_l<9> a_wl_l<8> a_wl_l<7> a_wl_l<6> a_wl_l<5> a_wl_l<4> a_wl_l<3> a_wl_l<2> a_wl_l<1> a_wl_l<0> VDDARRAY! VSS! / RM_IHPSG13_1024x8_c2_1P_MATRIX_pcell_1 + + +XA_COLDRV<1> a_addr_col<1> a_addr_col<0> a_addr_col_r<1> a_addr_col_r<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> a_dclk a_dclk_p_r<0> a_rclk a_rclk_p_r<0> a_wclk a_wclk_p_r<0> VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_COLDRV13X4 +XA_COLDRV<0> a_addr_col<1> a_addr_col<0> a_addr_col_l<1> a_addr_col_l<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> a_dclk a_dclk_p_l<0> a_rclk a_rclk_p_l<0> a_wclk a_wclk_p_l<0> VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_COLDRV13X4 + + +XA_WLDRV<31> a_wi<255> a_wi<254> a_wi<253> a_wi<252> a_wi<251> a_wi<250> a_wi<249> a_wi<248> a_wi<247> a_wi<246> a_wi<245> a_wi<244> a_wi<243> a_wi<242> a_wi<241> a_wi<240> a_wl_r<255> a_wl_r<254> a_wl_r<253> a_wl_r<252> a_wl_r<251> a_wl_r<250> a_wl_r<249> a_wl_r<248> a_wl_r<247> a_wl_r<246> a_wl_r<245> a_wl_r<244> a_wl_r<243> a_wl_r<242> a_wl_r<241> a_wl_r<240> VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_WLDRV16X4 +XA_WLDRV<30> a_wi<239> a_wi<238> a_wi<237> a_wi<236> a_wi<235> a_wi<234> a_wi<233> a_wi<232> a_wi<231> a_wi<230> a_wi<229> a_wi<228> a_wi<227> a_wi<226> a_wi<225> a_wi<224> a_wl_r<239> a_wl_r<238> a_wl_r<237> a_wl_r<236> a_wl_r<235> a_wl_r<234> a_wl_r<233> a_wl_r<232> a_wl_r<231> a_wl_r<230> a_wl_r<229> a_wl_r<228> a_wl_r<227> a_wl_r<226> a_wl_r<225> a_wl_r<224> VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_WLDRV16X4 +XA_WLDRV<29> a_wi<223> a_wi<222> a_wi<221> a_wi<220> a_wi<219> a_wi<218> a_wi<217> a_wi<216> a_wi<215> a_wi<214> a_wi<213> a_wi<212> a_wi<211> a_wi<210> a_wi<209> a_wi<208> a_wl_r<223> a_wl_r<222> a_wl_r<221> a_wl_r<220> a_wl_r<219> a_wl_r<218> a_wl_r<217> a_wl_r<216> a_wl_r<215> a_wl_r<214> a_wl_r<213> a_wl_r<212> a_wl_r<211> a_wl_r<210> a_wl_r<209> a_wl_r<208> VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_WLDRV16X4 +XA_WLDRV<28> a_wi<207> a_wi<206> a_wi<205> a_wi<204> a_wi<203> a_wi<202> a_wi<201> a_wi<200> a_wi<199> a_wi<198> a_wi<197> a_wi<196> a_wi<195> a_wi<194> a_wi<193> a_wi<192> a_wl_r<207> a_wl_r<206> a_wl_r<205> a_wl_r<204> a_wl_r<203> a_wl_r<202> a_wl_r<201> a_wl_r<200> a_wl_r<199> a_wl_r<198> a_wl_r<197> a_wl_r<196> a_wl_r<195> a_wl_r<194> a_wl_r<193> a_wl_r<192> VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_WLDRV16X4 +XA_WLDRV<27> a_wi<191> a_wi<190> a_wi<189> a_wi<188> a_wi<187> a_wi<186> a_wi<185> a_wi<184> a_wi<183> a_wi<182> a_wi<181> a_wi<180> a_wi<179> a_wi<178> a_wi<177> a_wi<176> a_wl_r<191> a_wl_r<190> a_wl_r<189> a_wl_r<188> a_wl_r<187> a_wl_r<186> a_wl_r<185> a_wl_r<184> a_wl_r<183> a_wl_r<182> a_wl_r<181> a_wl_r<180> a_wl_r<179> a_wl_r<178> a_wl_r<177> a_wl_r<176> VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_WLDRV16X4 +XA_WLDRV<26> a_wi<175> a_wi<174> a_wi<173> a_wi<172> a_wi<171> a_wi<170> a_wi<169> a_wi<168> a_wi<167> a_wi<166> a_wi<165> a_wi<164> a_wi<163> a_wi<162> a_wi<161> a_wi<160> a_wl_r<175> a_wl_r<174> a_wl_r<173> a_wl_r<172> a_wl_r<171> a_wl_r<170> a_wl_r<169> a_wl_r<168> a_wl_r<167> a_wl_r<166> a_wl_r<165> a_wl_r<164> a_wl_r<163> a_wl_r<162> a_wl_r<161> a_wl_r<160> VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_WLDRV16X4 +XA_WLDRV<25> a_wi<159> a_wi<158> a_wi<157> a_wi<156> a_wi<155> a_wi<154> a_wi<153> a_wi<152> a_wi<151> a_wi<150> a_wi<149> a_wi<148> a_wi<147> a_wi<146> a_wi<145> a_wi<144> a_wl_r<159> a_wl_r<158> a_wl_r<157> a_wl_r<156> a_wl_r<155> a_wl_r<154> a_wl_r<153> a_wl_r<152> a_wl_r<151> a_wl_r<150> a_wl_r<149> a_wl_r<148> a_wl_r<147> a_wl_r<146> a_wl_r<145> a_wl_r<144> VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_WLDRV16X4 +XA_WLDRV<24> a_wi<143> a_wi<142> a_wi<141> a_wi<140> a_wi<139> a_wi<138> a_wi<137> a_wi<136> a_wi<135> a_wi<134> a_wi<133> a_wi<132> a_wi<131> a_wi<130> a_wi<129> a_wi<128> a_wl_r<143> a_wl_r<142> a_wl_r<141> a_wl_r<140> a_wl_r<139> a_wl_r<138> a_wl_r<137> a_wl_r<136> a_wl_r<135> a_wl_r<134> a_wl_r<133> a_wl_r<132> a_wl_r<131> a_wl_r<130> a_wl_r<129> a_wl_r<128> VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_WLDRV16X4 +XA_WLDRV<23> a_wi<127> a_wi<126> a_wi<125> a_wi<124> a_wi<123> a_wi<122> a_wi<121> a_wi<120> a_wi<119> a_wi<118> a_wi<117> a_wi<116> a_wi<115> a_wi<114> a_wi<113> a_wi<112> a_wl_r<127> a_wl_r<126> a_wl_r<125> a_wl_r<124> a_wl_r<123> a_wl_r<122> a_wl_r<121> a_wl_r<120> a_wl_r<119> a_wl_r<118> a_wl_r<117> a_wl_r<116> a_wl_r<115> a_wl_r<114> a_wl_r<113> a_wl_r<112> VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_WLDRV16X4 +XA_WLDRV<22> a_wi<111> a_wi<110> a_wi<109> a_wi<108> a_wi<107> a_wi<106> a_wi<105> a_wi<104> a_wi<103> a_wi<102> a_wi<101> a_wi<100> a_wi<99> a_wi<98> a_wi<97> a_wi<96> a_wl_r<111> a_wl_r<110> a_wl_r<109> a_wl_r<108> a_wl_r<107> a_wl_r<106> a_wl_r<105> a_wl_r<104> a_wl_r<103> a_wl_r<102> a_wl_r<101> a_wl_r<100> a_wl_r<99> a_wl_r<98> a_wl_r<97> a_wl_r<96> VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_WLDRV16X4 +XA_WLDRV<21> a_wi<95> a_wi<94> a_wi<93> a_wi<92> a_wi<91> a_wi<90> a_wi<89> a_wi<88> a_wi<87> a_wi<86> a_wi<85> a_wi<84> a_wi<83> a_wi<82> a_wi<81> a_wi<80> a_wl_r<95> a_wl_r<94> a_wl_r<93> a_wl_r<92> a_wl_r<91> a_wl_r<90> a_wl_r<89> a_wl_r<88> a_wl_r<87> a_wl_r<86> a_wl_r<85> a_wl_r<84> a_wl_r<83> a_wl_r<82> a_wl_r<81> a_wl_r<80> VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_WLDRV16X4 +XA_WLDRV<20> a_wi<79> a_wi<78> a_wi<77> a_wi<76> a_wi<75> a_wi<74> a_wi<73> a_wi<72> a_wi<71> a_wi<70> a_wi<69> a_wi<68> a_wi<67> a_wi<66> a_wi<65> a_wi<64> a_wl_r<79> a_wl_r<78> a_wl_r<77> a_wl_r<76> a_wl_r<75> a_wl_r<74> a_wl_r<73> a_wl_r<72> a_wl_r<71> a_wl_r<70> a_wl_r<69> a_wl_r<68> a_wl_r<67> a_wl_r<66> a_wl_r<65> a_wl_r<64> VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_WLDRV16X4 +XA_WLDRV<19> a_wi<63> a_wi<62> a_wi<61> a_wi<60> a_wi<59> a_wi<58> a_wi<57> a_wi<56> a_wi<55> a_wi<54> a_wi<53> a_wi<52> a_wi<51> a_wi<50> a_wi<49> a_wi<48> a_wl_r<63> a_wl_r<62> a_wl_r<61> a_wl_r<60> a_wl_r<59> a_wl_r<58> a_wl_r<57> a_wl_r<56> a_wl_r<55> a_wl_r<54> a_wl_r<53> a_wl_r<52> a_wl_r<51> a_wl_r<50> a_wl_r<49> a_wl_r<48> VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_WLDRV16X4 +XA_WLDRV<18> a_wi<47> a_wi<46> a_wi<45> a_wi<44> a_wi<43> a_wi<42> a_wi<41> a_wi<40> a_wi<39> a_wi<38> a_wi<37> a_wi<36> a_wi<35> a_wi<34> a_wi<33> a_wi<32> a_wl_r<47> a_wl_r<46> a_wl_r<45> a_wl_r<44> a_wl_r<43> a_wl_r<42> a_wl_r<41> a_wl_r<40> a_wl_r<39> a_wl_r<38> a_wl_r<37> a_wl_r<36> a_wl_r<35> a_wl_r<34> a_wl_r<33> a_wl_r<32> VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_WLDRV16X4 +XA_WLDRV<17> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wl_r<31> a_wl_r<30> a_wl_r<29> a_wl_r<28> a_wl_r<27> a_wl_r<26> a_wl_r<25> a_wl_r<24> a_wl_r<23> a_wl_r<22> a_wl_r<21> a_wl_r<20> a_wl_r<19> a_wl_r<18> a_wl_r<17> a_wl_r<16> VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_WLDRV16X4 +XA_WLDRV<16> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> a_wl_r<15> a_wl_r<14> a_wl_r<13> a_wl_r<12> a_wl_r<11> a_wl_r<10> a_wl_r<9> a_wl_r<8> a_wl_r<7> a_wl_r<6> a_wl_r<5> a_wl_r<4> a_wl_r<3> a_wl_r<2> a_wl_r<1> a_wl_r<0> VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_WLDRV16X4 +XA_WLDRV<15> a_wi<255> a_wi<254> a_wi<253> a_wi<252> a_wi<251> a_wi<250> a_wi<249> a_wi<248> a_wi<247> a_wi<246> a_wi<245> a_wi<244> a_wi<243> a_wi<242> a_wi<241> a_wi<240> a_wl_l<255> a_wl_l<254> a_wl_l<253> a_wl_l<252> a_wl_l<251> a_wl_l<250> a_wl_l<249> a_wl_l<248> a_wl_l<247> a_wl_l<246> a_wl_l<245> a_wl_l<244> a_wl_l<243> a_wl_l<242> a_wl_l<241> a_wl_l<240> VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_WLDRV16X4 +XA_WLDRV<14> a_wi<239> a_wi<238> a_wi<237> a_wi<236> a_wi<235> a_wi<234> a_wi<233> a_wi<232> a_wi<231> a_wi<230> a_wi<229> a_wi<228> a_wi<227> a_wi<226> a_wi<225> a_wi<224> a_wl_l<239> a_wl_l<238> a_wl_l<237> a_wl_l<236> a_wl_l<235> a_wl_l<234> a_wl_l<233> a_wl_l<232> a_wl_l<231> a_wl_l<230> a_wl_l<229> a_wl_l<228> a_wl_l<227> a_wl_l<226> a_wl_l<225> a_wl_l<224> VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_WLDRV16X4 +XA_WLDRV<13> a_wi<223> a_wi<222> a_wi<221> a_wi<220> a_wi<219> a_wi<218> a_wi<217> a_wi<216> a_wi<215> a_wi<214> a_wi<213> a_wi<212> a_wi<211> a_wi<210> a_wi<209> a_wi<208> a_wl_l<223> a_wl_l<222> a_wl_l<221> a_wl_l<220> a_wl_l<219> a_wl_l<218> a_wl_l<217> a_wl_l<216> a_wl_l<215> a_wl_l<214> a_wl_l<213> a_wl_l<212> a_wl_l<211> a_wl_l<210> a_wl_l<209> a_wl_l<208> VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_WLDRV16X4 +XA_WLDRV<12> a_wi<207> a_wi<206> a_wi<205> a_wi<204> a_wi<203> a_wi<202> a_wi<201> a_wi<200> a_wi<199> a_wi<198> a_wi<197> a_wi<196> a_wi<195> a_wi<194> a_wi<193> a_wi<192> a_wl_l<207> a_wl_l<206> a_wl_l<205> a_wl_l<204> a_wl_l<203> a_wl_l<202> a_wl_l<201> a_wl_l<200> a_wl_l<199> a_wl_l<198> a_wl_l<197> a_wl_l<196> a_wl_l<195> a_wl_l<194> a_wl_l<193> a_wl_l<192> VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_WLDRV16X4 +XA_WLDRV<11> a_wi<191> a_wi<190> a_wi<189> a_wi<188> a_wi<187> a_wi<186> a_wi<185> a_wi<184> a_wi<183> a_wi<182> a_wi<181> a_wi<180> a_wi<179> a_wi<178> a_wi<177> a_wi<176> a_wl_l<191> a_wl_l<190> a_wl_l<189> a_wl_l<188> a_wl_l<187> a_wl_l<186> a_wl_l<185> a_wl_l<184> a_wl_l<183> a_wl_l<182> a_wl_l<181> a_wl_l<180> a_wl_l<179> a_wl_l<178> a_wl_l<177> a_wl_l<176> VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_WLDRV16X4 +XA_WLDRV<10> a_wi<175> a_wi<174> a_wi<173> a_wi<172> a_wi<171> a_wi<170> a_wi<169> a_wi<168> a_wi<167> a_wi<166> a_wi<165> a_wi<164> a_wi<163> a_wi<162> a_wi<161> a_wi<160> a_wl_l<175> a_wl_l<174> a_wl_l<173> a_wl_l<172> a_wl_l<171> a_wl_l<170> a_wl_l<169> a_wl_l<168> a_wl_l<167> a_wl_l<166> a_wl_l<165> a_wl_l<164> a_wl_l<163> a_wl_l<162> a_wl_l<161> a_wl_l<160> VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_WLDRV16X4 +XA_WLDRV<9> a_wi<159> a_wi<158> a_wi<157> a_wi<156> a_wi<155> a_wi<154> a_wi<153> a_wi<152> a_wi<151> a_wi<150> a_wi<149> a_wi<148> a_wi<147> a_wi<146> a_wi<145> a_wi<144> a_wl_l<159> a_wl_l<158> a_wl_l<157> a_wl_l<156> a_wl_l<155> a_wl_l<154> a_wl_l<153> a_wl_l<152> a_wl_l<151> a_wl_l<150> a_wl_l<149> a_wl_l<148> a_wl_l<147> a_wl_l<146> a_wl_l<145> a_wl_l<144> VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_WLDRV16X4 +XA_WLDRV<8> a_wi<143> a_wi<142> a_wi<141> a_wi<140> a_wi<139> a_wi<138> a_wi<137> a_wi<136> a_wi<135> a_wi<134> a_wi<133> a_wi<132> a_wi<131> a_wi<130> a_wi<129> a_wi<128> a_wl_l<143> a_wl_l<142> a_wl_l<141> a_wl_l<140> a_wl_l<139> a_wl_l<138> a_wl_l<137> a_wl_l<136> a_wl_l<135> a_wl_l<134> a_wl_l<133> a_wl_l<132> a_wl_l<131> a_wl_l<130> a_wl_l<129> a_wl_l<128> VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_WLDRV16X4 +XA_WLDRV<7> a_wi<127> a_wi<126> a_wi<125> a_wi<124> a_wi<123> a_wi<122> a_wi<121> a_wi<120> a_wi<119> a_wi<118> a_wi<117> a_wi<116> a_wi<115> a_wi<114> a_wi<113> a_wi<112> a_wl_l<127> a_wl_l<126> a_wl_l<125> a_wl_l<124> a_wl_l<123> a_wl_l<122> a_wl_l<121> a_wl_l<120> a_wl_l<119> a_wl_l<118> a_wl_l<117> a_wl_l<116> a_wl_l<115> a_wl_l<114> a_wl_l<113> a_wl_l<112> VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_WLDRV16X4 +XA_WLDRV<6> a_wi<111> a_wi<110> a_wi<109> a_wi<108> a_wi<107> a_wi<106> a_wi<105> a_wi<104> a_wi<103> a_wi<102> a_wi<101> a_wi<100> a_wi<99> a_wi<98> a_wi<97> a_wi<96> a_wl_l<111> a_wl_l<110> a_wl_l<109> a_wl_l<108> a_wl_l<107> a_wl_l<106> a_wl_l<105> a_wl_l<104> a_wl_l<103> a_wl_l<102> a_wl_l<101> a_wl_l<100> a_wl_l<99> a_wl_l<98> a_wl_l<97> a_wl_l<96> VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_WLDRV16X4 +XA_WLDRV<5> a_wi<95> a_wi<94> a_wi<93> a_wi<92> a_wi<91> a_wi<90> a_wi<89> a_wi<88> a_wi<87> a_wi<86> a_wi<85> a_wi<84> a_wi<83> a_wi<82> a_wi<81> a_wi<80> a_wl_l<95> a_wl_l<94> a_wl_l<93> a_wl_l<92> a_wl_l<91> a_wl_l<90> a_wl_l<89> a_wl_l<88> a_wl_l<87> a_wl_l<86> a_wl_l<85> a_wl_l<84> a_wl_l<83> a_wl_l<82> a_wl_l<81> a_wl_l<80> VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_WLDRV16X4 +XA_WLDRV<4> a_wi<79> a_wi<78> a_wi<77> a_wi<76> a_wi<75> a_wi<74> a_wi<73> a_wi<72> a_wi<71> a_wi<70> a_wi<69> a_wi<68> a_wi<67> a_wi<66> a_wi<65> a_wi<64> a_wl_l<79> a_wl_l<78> a_wl_l<77> a_wl_l<76> a_wl_l<75> a_wl_l<74> a_wl_l<73> a_wl_l<72> a_wl_l<71> a_wl_l<70> a_wl_l<69> a_wl_l<68> a_wl_l<67> a_wl_l<66> a_wl_l<65> a_wl_l<64> VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_WLDRV16X4 +XA_WLDRV<3> a_wi<63> a_wi<62> a_wi<61> a_wi<60> a_wi<59> a_wi<58> a_wi<57> a_wi<56> a_wi<55> a_wi<54> a_wi<53> a_wi<52> a_wi<51> a_wi<50> a_wi<49> a_wi<48> a_wl_l<63> a_wl_l<62> a_wl_l<61> a_wl_l<60> a_wl_l<59> a_wl_l<58> a_wl_l<57> a_wl_l<56> a_wl_l<55> a_wl_l<54> a_wl_l<53> a_wl_l<52> a_wl_l<51> a_wl_l<50> a_wl_l<49> a_wl_l<48> VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_WLDRV16X4 +XA_WLDRV<2> a_wi<47> a_wi<46> a_wi<45> a_wi<44> a_wi<43> a_wi<42> a_wi<41> a_wi<40> a_wi<39> a_wi<38> a_wi<37> a_wi<36> a_wi<35> a_wi<34> a_wi<33> a_wi<32> a_wl_l<47> a_wl_l<46> a_wl_l<45> a_wl_l<44> a_wl_l<43> a_wl_l<42> a_wl_l<41> a_wl_l<40> a_wl_l<39> a_wl_l<38> a_wl_l<37> a_wl_l<36> a_wl_l<35> a_wl_l<34> a_wl_l<33> a_wl_l<32> VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_WLDRV16X4 +XA_WLDRV<1> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wl_l<31> a_wl_l<30> a_wl_l<29> a_wl_l<28> a_wl_l<27> a_wl_l<26> a_wl_l<25> a_wl_l<24> a_wl_l<23> a_wl_l<22> a_wl_l<21> a_wl_l<20> a_wl_l<19> a_wl_l<18> a_wl_l<17> a_wl_l<16> VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_WLDRV16X4 +XA_WLDRV<0> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> a_wl_l<15> a_wl_l<14> a_wl_l<13> a_wl_l<12> a_wl_l<11> a_wl_l<10> a_wl_l<9> a_wl_l<8> a_wl_l<7> a_wl_l<6> a_wl_l<5> a_wl_l<4> a_wl_l<3> a_wl_l<2> a_wl_l<1> a_wl_l<0> VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_WLDRV16X4 + + +XA_CTRL a_aclk_n A_BIST_CLK A_BIST_MEN A_BIST_EN A_BIST_REN A_BIST_WEN a_tiel A_CLK A_MEN a_dclk a_eclk a_pulse_h a_pulse_l a_pulse a_rclk A_REN a_cs a_wclk A_WEN VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_CTRL + + +XA_ROWDEC a_addr_row<7> a_addr_row<6> a_addr_row<5> a_addr_row<4> a_addr_row<3> a_addr_row<2> a_addr_row<1> a_addr_row<0> a_cs a_eclk a_wi<255> a_wi<254> a_wi<253> a_wi<252> a_wi<251> a_wi<250> a_wi<249> a_wi<248> a_wi<247> a_wi<246> a_wi<245> a_wi<244> a_wi<243> a_wi<242> a_wi<241> a_wi<240> a_wi<239> a_wi<238> a_wi<237> a_wi<236> a_wi<235> a_wi<234> a_wi<233> a_wi<232> a_wi<231> a_wi<230> a_wi<229> a_wi<228> a_wi<227> a_wi<226> a_wi<225> a_wi<224> a_wi<223> a_wi<222> a_wi<221> a_wi<220> a_wi<219> a_wi<218> a_wi<217> a_wi<216> a_wi<215> a_wi<214> a_wi<213> a_wi<212> a_wi<211> a_wi<210> a_wi<209> a_wi<208> a_wi<207> a_wi<206> a_wi<205> a_wi<204> a_wi<203> a_wi<202> a_wi<201> a_wi<200> a_wi<199> a_wi<198> a_wi<197> a_wi<196> a_wi<195> a_wi<194> a_wi<193> a_wi<192> a_wi<191> a_wi<190> a_wi<189> a_wi<188> a_wi<187> a_wi<186> a_wi<185> a_wi<184> a_wi<183> a_wi<182> a_wi<181> a_wi<180> a_wi<179> a_wi<178> a_wi<177> a_wi<176> a_wi<175> a_wi<174> a_wi<173> a_wi<172> a_wi<171> a_wi<170> a_wi<169> a_wi<168> a_wi<167> a_wi<166> a_wi<165> a_wi<164> a_wi<163> a_wi<162> a_wi<161> a_wi<160> a_wi<159> a_wi<158> a_wi<157> a_wi<156> a_wi<155> a_wi<154> a_wi<153> a_wi<152> a_wi<151> a_wi<150> a_wi<149> a_wi<148> a_wi<147> a_wi<146> a_wi<145> a_wi<144> a_wi<143> a_wi<142> a_wi<141> a_wi<140> a_wi<139> a_wi<138> a_wi<137> a_wi<136> a_wi<135> a_wi<134> a_wi<133> a_wi<132> a_wi<131> a_wi<130> a_wi<129> a_wi<128> a_wi<127> a_wi<126> a_wi<125> a_wi<124> a_wi<123> a_wi<122> a_wi<121> a_wi<120> a_wi<119> a_wi<118> a_wi<117> a_wi<116> a_wi<115> a_wi<114> a_wi<113> a_wi<112> a_wi<111> a_wi<110> a_wi<109> a_wi<108> a_wi<107> a_wi<106> a_wi<105> a_wi<104> a_wi<103> a_wi<102> a_wi<101> a_wi<100> a_wi<99> a_wi<98> a_wi<97> a_wi<96> a_wi<95> a_wi<94> a_wi<93> a_wi<92> a_wi<91> a_wi<90> a_wi<89> a_wi<88> a_wi<87> a_wi<86> a_wi<85> a_wi<84> a_wi<83> a_wi<82> a_wi<81> a_wi<80> a_wi<79> a_wi<78> a_wi<77> a_wi<76> a_wi<75> a_wi<74> a_wi<73> a_wi<72> a_wi<71> a_wi<70> a_wi<69> a_wi<68> a_wi<67> a_wi<66> a_wi<65> a_wi<64> a_wi<63> a_wi<62> a_wi<61> a_wi<60> a_wi<59> a_wi<58> a_wi<57> a_wi<56> a_wi<55> a_wi<54> a_wi<53> a_wi<52> a_wi<51> a_wi<50> a_wi<49> a_wi<48> a_wi<47> a_wi<46> a_wi<45> a_wi<44> a_wi<43> a_wi<42> a_wi<41> a_wi<40> a_wi<39> a_wi<38> a_wi<37> a_wi<36> a_wi<35> a_wi<34> a_wi<33> a_wi<32> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_ROWDEC8 +XA_ROWREG a_aclk_n A_ADDR<9> A_ADDR<8> A_ADDR<7> A_ADDR<6> A_ADDR<5> A_ADDR<4> A_ADDR<3> A_ADDR<2> a_addr_row<7> a_addr_row<6> a_addr_row<5> a_addr_row<4> a_addr_row<3> a_addr_row<2> a_addr_row<1> a_addr_row<0> A_BIST_ADDR<9> A_BIST_ADDR<8> A_BIST_ADDR<7> A_BIST_ADDR<6> A_BIST_ADDR<5> A_BIST_ADDR<4> A_BIST_ADDR<3> A_BIST_ADDR<2> A_BIST_EN VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_ROWREG8 +XA_COLDEC a_aclk_n A_ADDR<1> A_ADDR<0> a_addr_col<1> a_addr_col<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> A_BIST_ADDR<1> A_BIST_ADDR<0> A_BIST_EN VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_COLDEC2 + + +XA_DLYH a_pulse a_pulse_h VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_DLY_pcell_2 +XA_DLYL a_pulse_x a_pulse_l VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_DLY_pcell_3 +XA_DLYMUX a_pulse_h A_DLY a_pulse_x VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_DLY_MUX + +XCOLCTRL<7> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<7> A_BIST_DIN<7> A_BIST_EN a_blc_r<15> a_blc_r<14> a_blc_r<13> a_blc_r<12> a_blt_r<15> a_blt_r<14> a_blt_r<13> a_blt_r<12> A_BM<7> a_dclk_n_r<3> a_dclk_n_r<4> a_dclk_p_r<3> a_dclk_p_r<4> A_DOUT<7> A_DIN<7> a_rclk_n_r<3> a_rclk_n_r<4> a_rclk_p_r<3> a_rclk_p_r<4> a_tieh<7> a_wclk_n_r<3> a_wclk_n_r<4> a_wclk_p_r<3> a_wclk_p_r<4> VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_COLCTRL2 +XCOLCTRL<6> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<6> A_BIST_DIN<6> A_BIST_EN a_blc_r<11> a_blc_r<10> a_blc_r<9> a_blc_r<8> a_blt_r<11> a_blt_r<10> a_blt_r<9> a_blt_r<8> A_BM<6> a_dclk_n_r<2> a_dclk_n_r<3> a_dclk_p_r<2> a_dclk_p_r<3> A_DOUT<6> A_DIN<6> a_rclk_n_r<2> a_rclk_n_r<3> a_rclk_p_r<2> a_rclk_p_r<3> a_tieh<6> a_wclk_n_r<2> a_wclk_n_r<3> a_wclk_p_r<2> a_wclk_p_r<3> VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_COLCTRL2 +XCOLCTRL<5> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<5> A_BIST_DIN<5> A_BIST_EN a_blc_r<7> a_blc_r<6> a_blc_r<5> a_blc_r<4> a_blt_r<7> a_blt_r<6> a_blt_r<5> a_blt_r<4> A_BM<5> a_dclk_n_r<1> a_dclk_n_r<2> a_dclk_p_r<1> a_dclk_p_r<2> A_DOUT<5> A_DIN<5> a_rclk_n_r<1> a_rclk_n_r<2> a_rclk_p_r<1> a_rclk_p_r<2> a_tieh<5> a_wclk_n_r<1> a_wclk_n_r<2> a_wclk_p_r<1> a_wclk_p_r<2> VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_COLCTRL2 +XCOLCTRL<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<4> A_BIST_DIN<4> A_BIST_EN a_blc_r<3> a_blc_r<2> a_blc_r<1> a_blc_r<0> a_blt_r<3> a_blt_r<2> a_blt_r<1> a_blt_r<0> A_BM<4> a_dclk_n_r<0> a_dclk_n_r<1> a_dclk_p_r<0> a_dclk_p_r<1> A_DOUT<4> A_DIN<4> a_rclk_n_r<0> a_rclk_n_r<1> a_rclk_p_r<0> a_rclk_p_r<1> a_tieh<4> a_wclk_n_r<0> a_wclk_n_r<1> a_wclk_p_r<0> a_wclk_p_r<1> VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_COLCTRL2 +XCOLCTRL<3> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<0> A_BIST_DIN<0> A_BIST_EN a_blc_l<15> a_blc_l<14> a_blc_l<13> a_blc_l<12> a_blt_l<15> a_blt_l<14> a_blt_l<13> a_blt_l<12> A_BM<0> a_dclk_n_l<3> a_dclk_n_l<4> a_dclk_p_l<3> a_dclk_p_l<4> A_DOUT<0> A_DIN<0> a_rclk_n_l<3> a_rclk_n_l<4> a_rclk_p_l<3> a_rclk_p_l<4> a_tieh<0> a_wclk_n_l<3> a_wclk_n_l<4> a_wclk_p_l<3> a_wclk_p_l<4> VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_COLCTRL2 +XCOLCTRL<2> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<1> A_BIST_DIN<1> A_BIST_EN a_blc_l<11> a_blc_l<10> a_blc_l<9> a_blc_l<8> a_blt_l<11> a_blt_l<10> a_blt_l<9> a_blt_l<8> A_BM<1> a_dclk_n_l<2> a_dclk_n_l<3> a_dclk_p_l<2> a_dclk_p_l<3> A_DOUT<1> A_DIN<1> a_rclk_n_l<2> a_rclk_n_l<3> a_rclk_p_l<2> a_rclk_p_l<3> a_tieh<1> a_wclk_n_l<2> a_wclk_n_l<3> a_wclk_p_l<2> a_wclk_p_l<3> VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_COLCTRL2 +XCOLCTRL<1> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<2> A_BIST_DIN<2> A_BIST_EN a_blc_l<7> a_blc_l<6> a_blc_l<5> a_blc_l<4> a_blt_l<7> a_blt_l<6> a_blt_l<5> a_blt_l<4> A_BM<2> a_dclk_n_l<1> a_dclk_n_l<2> a_dclk_p_l<1> a_dclk_p_l<2> A_DOUT<2> A_DIN<2> a_rclk_n_l<1> a_rclk_n_l<2> a_rclk_p_l<1> a_rclk_p_l<2> a_tieh<2> a_wclk_n_l<1> a_wclk_n_l<2> a_wclk_p_l<1> a_wclk_p_l<2> VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_COLCTRL2 +XCOLCTRL<0> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<3> A_BIST_DIN<3> A_BIST_EN a_blc_l<3> a_blc_l<2> a_blc_l<1> a_blc_l<0> a_blt_l<3> a_blt_l<2> a_blt_l<1> a_blt_l<0> A_BM<3> a_dclk_n_l<0> a_dclk_n_l<1> a_dclk_p_l<0> a_dclk_p_l<1> A_DOUT<3> A_DIN<3> a_rclk_n_l<0> a_rclk_n_l<1> a_rclk_p_l<0> a_rclk_p_l<1> a_tieh<3> a_wclk_n_l<0> a_wclk_n_l<1> a_wclk_p_l<0> a_wclk_p_l<1> VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_COLCTRL2 + + +XDRVFILL4<1> VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_COLDRV13_FILL4 +XDRVFILL4<2> VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_COLDRV13_FILL4 +XCOLFILL4<1> VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_COLDRV13_FILL4C2 +XCOLFILL4<2> VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_COLDRV13_FILL4C2 +XCOLFILL4<3> VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_COLDRV13_FILL4C2 +XCOLFILL4<4> VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_COLDRV13_FILL4C2 +XCOLFILL4<5> VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_COLDRV13_FILL4C2 +XCOLFILL4<6> VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_COLDRV13_FILL4C2 +.ENDS diff --git a/flow/platforms/ihp-sg13g2/cdl/RM_IHPSG13_1P_4096x16_c3_bm_bist.cdl b/flow/platforms/ihp-sg13g2/cdl/RM_IHPSG13_1P_4096x16_c3_bm_bist.cdl new file mode 100644 index 0000000000..5c3abf3d74 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/cdl/RM_IHPSG13_1P_4096x16_c3_bm_bist.cdl @@ -0,0 +1,6481 @@ +* ------------------------------------------------------ +* +* Copyright 2024 IHP PDK Authors +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* https://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* +* Generated on Fri Jul 12 17:37:44 2024 +* +* ------------------------------------------------------ + +.SUBCKT RM_IHPSG13_4096x16_c3_1P_BITKIT_CORNER NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_CORNER VDD_CORE VSS +XI16 VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x16_c3_1P_BITKIT_CORNER +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_1P_BITKIT_EDGE_LR LWL NW PW VDD VSS +MN1 VSS LWL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN0 VSS net9 VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR A_WL<15> A_WL<14> A_WL<13> A_WL<12> ++ A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> ++ A_WL<2> A_WL<1> A_WL<0> VDD_CORE VSS +XI0<15> A_WL<15> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x16_c3_1P_BITKIT_EDGE_LR +XI0<14> A_WL<14> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x16_c3_1P_BITKIT_EDGE_LR +XI0<13> A_WL<13> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x16_c3_1P_BITKIT_EDGE_LR +XI0<12> A_WL<12> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x16_c3_1P_BITKIT_EDGE_LR +XI0<11> A_WL<11> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x16_c3_1P_BITKIT_EDGE_LR +XI0<10> A_WL<10> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x16_c3_1P_BITKIT_EDGE_LR +XI0<9> A_WL<9> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x16_c3_1P_BITKIT_EDGE_LR +XI0<8> A_WL<8> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x16_c3_1P_BITKIT_EDGE_LR +XI0<7> A_WL<7> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x16_c3_1P_BITKIT_EDGE_LR +XI0<6> A_WL<6> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x16_c3_1P_BITKIT_EDGE_LR +XI0<5> A_WL<5> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x16_c3_1P_BITKIT_EDGE_LR +XI0<4> A_WL<4> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x16_c3_1P_BITKIT_EDGE_LR +XI0<3> A_WL<3> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x16_c3_1P_BITKIT_EDGE_LR +XI0<2> A_WL<2> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x16_c3_1P_BITKIT_EDGE_LR +XI0<1> A_WL<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x16_c3_1P_BITKIT_EDGE_LR +XI0<0> A_WL<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x16_c3_1P_BITKIT_EDGE_LR +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_1P_BITKIT_CELL BLC_BOT BLC_TOP BLT_BOT BLT_TOP LWL NW PW ++ RWL VDD VSS +MN0 NC NT VSS PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN1 NT NC VSS PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN3 NC RWL BLC_TOP PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN2 BLT_BOT LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MP1 NT NC VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 NC NT VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +R1 BLC_BOT BLC_TOP lvsres w=2.6e-07 l=6e-07 +R0 BLT_BOT BLT_TOP lvsres w=2.6e-07 l=6e-07 +R2 RWL LWL lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_SRAM A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> ++ A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<15> ++ A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> ++ A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> ++ A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> ++ A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> VDD_CORE ++ VSS +XCELL<31> A_BLC_TOP<1> A_RBLC<15> A_BLT_TOP<1> A_RBLT<15> A_RWL<15> ++ VDD_CORE VSS A_XWL<15> VDD_CORE VSS / ++ RM_IHPSG13_4096x16_c3_1P_BITKIT_CELL +XCELL<30> A_RBLC<14> A_RBLC<15> A_RBLT<14> A_RBLT<15> A_RWL<14> VDD_CORE ++ VSS A_XWL<14> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_CELL +XCELL<29> A_RBLC<14> A_RBLC<13> A_RBLT<14> A_RBLT<13> A_RWL<13> VDD_CORE ++ VSS A_XWL<13> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_CELL +XCELL<28> A_RBLC<12> A_RBLC<13> A_RBLT<12> A_RBLT<13> A_RWL<12> VDD_CORE ++ VSS A_XWL<12> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_CELL +XCELL<27> A_RBLC<12> A_RBLC<11> A_RBLT<12> A_RBLT<11> A_RWL<11> VDD_CORE ++ VSS A_XWL<11> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_CELL +XCELL<26> A_RBLC<10> A_RBLC<11> A_RBLT<10> A_RBLT<11> A_RWL<10> VDD_CORE ++ VSS A_XWL<10> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_CELL +XCELL<25> A_RBLC<10> A_RBLC<9> A_RBLT<10> A_RBLT<9> A_RWL<9> VDD_CORE ++ VSS A_XWL<9> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_CELL +XCELL<24> A_RBLC<8> A_RBLC<9> A_RBLT<8> A_RBLT<9> A_RWL<8> VDD_CORE ++ VSS A_XWL<8> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_CELL +XCELL<23> A_RBLC<8> A_RBLC<7> A_RBLT<8> A_RBLT<7> A_RWL<7> VDD_CORE ++ VSS A_XWL<7> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_CELL +XCELL<22> A_RBLC<6> A_RBLC<7> A_RBLT<6> A_RBLT<7> A_RWL<6> VDD_CORE ++ VSS A_XWL<6> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_CELL +XCELL<21> A_RBLC<6> A_RBLC<5> A_RBLT<6> A_RBLT<5> A_RWL<5> VDD_CORE ++ VSS A_XWL<5> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_CELL +XCELL<20> A_RBLC<4> A_RBLC<5> A_RBLT<4> A_RBLT<5> A_RWL<4> VDD_CORE ++ VSS A_XWL<4> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_CELL +XCELL<19> A_RBLC<4> A_RBLC<3> A_RBLT<4> A_RBLT<3> A_RWL<3> VDD_CORE ++ VSS A_XWL<3> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_CELL +XCELL<18> A_RBLC<2> A_RBLC<3> A_RBLT<2> A_RBLT<3> A_RWL<2> VDD_CORE ++ VSS A_XWL<2> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_CELL +XCELL<17> A_RBLC<2> A_RBLC<1> A_RBLT<2> A_RBLT<1> A_RWL<1> VDD_CORE ++ VSS A_XWL<1> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_CELL +XCELL<16> A_BLC_BOT<1> A_RBLC<1> A_BLT_BOT<1> A_RBLT<1> A_RWL<0> VDD_CORE ++ VSS A_XWL<0> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_CELL +XCELL<15> A_BLC_TOP<0> A_LBLC<15> A_BLT_TOP<0> A_LBLT<15> A_LWL<15> ++ VDD_CORE VSS A_XWL<15> VDD_CORE VSS / ++ RM_IHPSG13_4096x16_c3_1P_BITKIT_CELL +XCELL<14> A_LBLC<14> A_LBLC<15> A_LBLT<14> A_LBLT<15> A_LWL<14> VDD_CORE ++ VSS A_XWL<14> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_CELL +XCELL<13> A_LBLC<14> A_LBLC<13> A_LBLT<14> A_LBLT<13> A_LWL<13> VDD_CORE ++ VSS A_XWL<13> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_CELL +XCELL<12> A_LBLC<12> A_LBLC<13> A_LBLT<12> A_LBLT<13> A_LWL<12> VDD_CORE ++ VSS A_XWL<12> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_CELL +XCELL<11> A_LBLC<12> A_LBLC<11> A_LBLT<12> A_LBLT<11> A_LWL<11> VDD_CORE ++ VSS A_XWL<11> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_CELL +XCELL<10> A_LBLC<10> A_LBLC<11> A_LBLT<10> A_LBLT<11> A_LWL<10> VDD_CORE ++ VSS A_XWL<10> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_CELL +XCELL<9> A_LBLC<10> A_LBLC<9> A_LBLT<10> A_LBLT<9> A_LWL<9> VDD_CORE ++ VSS A_XWL<9> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_CELL +XCELL<8> A_LBLC<8> A_LBLC<9> A_LBLT<8> A_LBLT<9> A_LWL<8> VDD_CORE ++ VSS A_XWL<8> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_CELL +XCELL<7> A_LBLC<8> A_LBLC<7> A_LBLT<8> A_LBLT<7> A_LWL<7> VDD_CORE ++ VSS A_XWL<7> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_CELL +XCELL<6> A_LBLC<6> A_LBLC<7> A_LBLT<6> A_LBLT<7> A_LWL<6> VDD_CORE ++ VSS A_XWL<6> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_CELL +XCELL<5> A_LBLC<6> A_LBLC<5> A_LBLT<6> A_LBLT<5> A_LWL<5> VDD_CORE ++ VSS A_XWL<5> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_CELL +XCELL<4> A_LBLC<4> A_LBLC<5> A_LBLT<4> A_LBLT<5> A_LWL<4> VDD_CORE ++ VSS A_XWL<4> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_CELL +XCELL<3> A_LBLC<4> A_LBLC<3> A_LBLT<4> A_LBLT<3> A_LWL<3> VDD_CORE ++ VSS A_XWL<3> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_CELL +XCELL<2> A_LBLC<2> A_LBLC<3> A_LBLT<2> A_LBLT<3> A_LWL<2> VDD_CORE ++ VSS A_XWL<2> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_CELL +XCELL<1> A_LBLC<2> A_LBLC<1> A_LBLT<2> A_LBLT<1> A_LWL<1> VDD_CORE ++ VSS A_XWL<1> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_CELL +XCELL<0> A_BLC_BOT<0> A_LBLC<1> A_BLT_BOT<0> A_LBLT<1> A_LWL<0> VDD_CORE ++ VSS A_XWL<0> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_CELL +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_1P_BITKIT_EDGE_TB BLC BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_TB A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ VDD_CORE VSS +XEDGE<1> A_BLC<1> A_BLT<1> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_4096x16_c3_1P_BITKIT_EDGE_TB +XEDGE<0> A_BLC<0> A_BLT<0> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_4096x16_c3_1P_BITKIT_EDGE_TB +.ENDS + +.SUBCKT RSC_IHPSG13_CBUFX4 A Z VDD VSS +MN0 net9 A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 Z net9 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MP0 net9 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP1 Z net9 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_1P_COLDRV13X4 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX4 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_1P_WLDRV16X4 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX4 +.ENDS +.SUBCKT RSC_IHPSG13_FILLCAP8 VDD VSS +MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=4.98u l=130.00n ng=6 nrd=0 ++ nrs=0 +MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=6.48u l=385.000n ng=4 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_LHPQX2 CP D Q VDD VSS +MN3 QIN CPN net14 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN2 net14 net10 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN5 net21 D VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN6 QIN CP net21 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net10 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 CPN CP VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 Q QIN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP2 QIN CP net16 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 CPN CP VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 Q QIN VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP3 net10 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net16 net10 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP6 QIN CPN net20 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP5 net20 D VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_NAND2X2 A B Z VDD VSS +MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z B net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net7 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX4 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX2 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_INVX2 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_NAND3X2 A B C Z VDD VSS +MP2 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z C VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN1 net12 B net16 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z C net12 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN2 net16 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_NOR3X2 A B C Z VDD VSS +MP0 net13 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z C net10 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP1 net10 B net13 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN1 Z B VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z C VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0 +MN2 Z A VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_FILLCAP4 VDD VSS +MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=2.49u l=130.00n ng=3 nrd=0 ++ nrs=0 +MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=3.24u l=385.000n ng=2 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_MET2RES A B +R0 B A lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_1P_DEC04 ADDR<3> ADDR<2> ADDR<1> ADDR<0> CS ECLK_H_BOT ++ ECLK_H_TOP ECLK_L_BOT ECLK_L_TOP WL<15> WL<14> WL<13> WL<12> WL<11> WL<10> ++ WL<9> WL<8> WL<7> WL<6> WL<5> WL<4> WL<3> WL<2> WL<1> WL<0> VDD VSS +XLATCH<3> CS ADDR<3> PADR<3> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<2> CS ADDR<2> PADR<2> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<1> CS ADDR<1> PADR<1> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<0> CS ADDR<0> PADR<0> VDD VSS / RSC_IHPSG13_LHPQX2 +XI0<3> PADR<1> PADR<0> sel01<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<2> PADR<1> NADR<0> sel01<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<1> NADR<1> PADR<0> sel01<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<0> NADR<1> NADR<0> sel01<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI4 ECLK_L_BOT EN VDD VSS / RSC_IHPSG13_CINVX4 +XI5 ECLK_H_BOT ECLK_L_BOT VDD VSS / RSC_IHPSG13_CINVX2 +XI3<3> PADR<3> NADR<3> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> PADR<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> PADR<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> PADR<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI1<3> PADR<2> PADR<3> CS sel23<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<2> PADR<3> CS sel23<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<2> NADR<3> CS sel23<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<2> NADR<3> CS sel23<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI2<15> sel23<3> sel01<3> EN WL<15> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<14> sel23<3> sel01<2> EN WL<14> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<13> sel23<3> sel01<1> EN WL<13> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<12> sel23<3> sel01<0> EN WL<12> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<11> sel23<2> sel01<3> EN WL<11> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<10> sel23<2> sel01<2> EN WL<10> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<9> sel23<2> sel01<1> EN WL<9> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<8> sel23<2> sel01<0> EN WL<8> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<7> sel23<1> sel01<3> EN WL<7> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<6> sel23<1> sel01<2> EN WL<6> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<5> sel23<1> sel01<1> EN WL<5> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<4> sel23<1> sel01<0> EN WL<4> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<3> sel23<0> sel01<3> EN WL<3> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<2> sel23<0> sel01<2> EN WL<2> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<1> sel23<0> sel01<1> EN WL<1> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<0> sel23<0> sel01<0> EN WL<0> VDD VSS / RSC_IHPSG13_NOR3X2 +XCAPS4 VDD VSS / RSC_IHPSG13_FILLCAP4 +XI11 ECLK_L_BOT ECLK_L_TOP / RSC_IHPSG13_MET2RES +XR0 ECLK_H_BOT ECLK_H_TOP / RSC_IHPSG13_MET2RES +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_1P_ROWDEC4 ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> ++ CS_I ECLK_I WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XSEL ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ECLK_H<1> ++ ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> ++ WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> ++ WL_O<0> VDD VSS / RM_IHPSG13_4096x16_c3_1P_DEC04 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX8 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=2.82u l=130.00n ng=4 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_DFNQMX2IX1 BE BI CN D QI QIN VDD VSS +MN15 net026 BI VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN14 MXI_OUT BE net026 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net025 D VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 MXI_OUT BEN net025 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN10 QI CNN net21 VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 nrd=0 nrs=0 +MN11 net21 QI_MS VSS VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN7 net30 QI_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN6 QIN_MS CNN net30 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 QI_MS QIN_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN12 CNN CN VSS VSS sg13_lv_nmos m=1 w=495.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN9 net37 MXI_OUT VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN8 QIN_MS CN net37 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 QI CN net25 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN4 net25 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 QIN QI VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN13 BEN BE VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP15 MXI_OUT BEN net027 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP14 net027 BI VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP1 MXI_OUT BE net024 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 net024 D VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP13 BEN BE VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP6 QI_MS QIN_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP3 QI CNN net27 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MP2 net27 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP10 net36 MXI_OUT VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP11 QIN_MS CNN net36 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net32 QI_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP5 QIN_MS CN net32 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 QIN QI VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP12 CNN CN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP9 QI CN net19 VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 nrd=0 nrs=0 +MP8 net19 QI_MS VDD VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_1P_ROWREG4 ACLK_N_I ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RSC_IHPSG13_CDLYX1 A Z VDD VSS +MN1 net010 net032 VSS VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 ++ nrd=0 nrs=0 +MN2 net032 A net014 VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 ++ nrs=0 +MN0 Z net032 net010 VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 ++ nrs=0 +MN3 net014 A VSS VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 ++ nrs=0 +MP1 Z net032 net07 VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 ++ nrs=0 +MP3 net011 A VDD VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 ++ nrs=0 +MP0 net07 net032 VDD VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 ++ nrd=0 nrs=0 +MP2 net032 A net011 VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CDLYX1_DUMMY A Z VDD VSS +MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=2.49u l=300.0n ng=3 nrd=0 ++ nrs=0 +MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=3.24u l=640.00n ng=2 nrd=0 ++ nrs=0 +R0 Z A lvsres w=2.6e-07 l=6e-07 +.ENDS + +.SUBCKT RSC_IHPSG13_MX2IX1 A0 A1 S ZN VDD VSS +MP4 SN S VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 nrs=0 +MP3 ZN SN net12 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 nrs=0 +MP2 net12 A1 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 ZN S net17 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 nrs=0 +MP0 net17 A0 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 SN S VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN3 net13 A1 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 ZN S net13 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net15 A0 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 ZN SN net15 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_1P_DLY_MUX A SEL Z VDD VSS +XI11 net4 Z VDD VSS / RSC_IHPSG13_CINVX2 +XI8 A D<3> SEL net4 VDD VSS / RSC_IHPSG13_MX2IX1 +XI20<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1 +.ENDS +.SUBCKT RSC_IHPSG13_DFNQX2 CN D Q VDD VSS +MN0 Q QIN_SL VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN10 QIN_SL CNN net21 VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN11 net21 QI_MS VSS VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN7 net30 QI_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN6 QIN_MS CNN net30 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 QI_MS QIN_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN12 CNN CN VSS VSS sg13_lv_nmos m=1 w=495.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN9 net37 D VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN8 QIN_MS CN net37 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 QIN_SL CN net25 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net25 QI_SL VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN2 QI_SL QIN_SL VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP0 Q QIN_SL VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP6 QI_MS QIN_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP3 QIN_SL CNN net27 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 net27 QI_SL VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP10 net36 D VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP11 QIN_MS CNN net36 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net32 QI_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP5 QIN_MS CN net32 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 QI_SL QIN_SL VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP12 CNN CN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP9 QIN_SL CN net19 VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP8 net19 QI_MS VDD VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CNAND2X2 A B Z VDD VSS +MN0 Z B net6 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net6 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CGATEPX4 CP E Q VDD VSS +MN1 net08 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 net019 net08 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN3 QIN CP net019 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN6 Q net015 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 ++ nrs=0 +MN5 net015 net08 net018 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN8 QIN CPN net023 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN7 net023 E VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net018 CP VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 CPN CP VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP3 net08 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 QIN CPN net017 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net017 net08 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP0 CPN CP VDD VDD sg13_lv_pmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP8 QIN CP net024 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 net024 E VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net015 CP VDD VDD sg13_lv_pmos m=1 w=1.27u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP6 Q net015 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 ++ nrs=0 +MP5 net015 net08 VDD VDD sg13_lv_pmos m=1 w=1.27u l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CBUFX8 A Z VDD VSS +MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0 +MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=2.82u l=130.00n ng=4 nrd=0 nrs=0 +MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CDLYX2 A Z VDD VSS +MN2 net4 A net9 VSS sg13_lv_nmos m=1 w=320.00n l=200.0n ng=1 nrd=0 nrs=0 +MN0 Z net4 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net9 A VSS VSS sg13_lv_nmos m=1 w=320.00n l=200.0n ng=1 nrd=0 nrs=0 +MP2 net4 A net10 VDD sg13_lv_pmos m=1 w=1.2u l=200.0n ng=1 nrd=0 nrs=0 +MP1 net10 A VDD VDD sg13_lv_pmos m=1 w=1.2u l=200.0n ng=1 nrd=0 nrs=0 +MP0 Z net4 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_MX2X2 A0 A1 S Z VDD VSS +MP6 Z net010 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 SN S VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 nrs=0 +MP3 net010 SN net12 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 net12 A1 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net010 S net17 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 net17 A0 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN6 Z net010 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 SN S VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 nrs=0 +MN3 net13 A1 VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 net010 S net13 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net15 A0 VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 net010 SN net15 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_AND2X2 A B Z VDD VSS +MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_TIEL Z VDD VSS +MN0 Z net2 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 net2 net2 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_XOR2X2 A B Z VDD VSS +MP8 net012 B net7 VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 net011 net3 net012 VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP6 Z net012 VDD VDD sg13_lv_pmos m=1 w=1.535u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 net7 A VDD VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net011 net7 VDD VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP5 net3 B VDD VDD sg13_lv_pmos m=1 w=580.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN7 net012 B net011 VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN6 net7 net3 net012 VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 Z net012 VSS VSS sg13_lv_nmos m=1 w=775.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 net7 A VSS VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net3 B VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 net011 net7 VSS VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_OA12X1 A B C Z VDD VSS +MN2 net7 C VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 Z net17 VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net17 B net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN0 net17 A net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 net24 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP3 Z net17 VDD VDD sg13_lv_pmos m=1 w=905.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net17 B net24 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP2 net17 C VDD VDD sg13_lv_pmos m=1 w=905.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_1P_CTRL ACLK_N BIST_CK_I BIST_CS_I BIST_EN BIST_RE_I ++ BIST_WE_I B_TIEL_O CK_I CS_I DCLK ECLK PULSE_H PULSE_L PULSE_O RCLK RE_I ++ ROW_CS WCLK WE_I VDD VSS +XI17 ck_regs we col_we VDD VSS / RSC_IHPSG13_DFNQX2 +XI16 ck_regs re col_re VDD VSS / RSC_IHPSG13_DFNQX2 +XI18 ck_regs cs net7 VDD VSS / RSC_IHPSG13_DFNQX2 +XI71 ACLK_N net012 PULSE_O VDD VSS / RSC_IHPSG13_DFNQX2 +XI77 col_we net9 net016 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI76 col_re net9 net018 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI15 ck_dly WEorREandCS aclk VDD VSS / RSC_IHPSG13_CGATEPX4 +XI14 ck WEandCS DCLK VDD VSS / RSC_IHPSG13_CGATEPX4 +XI60 net7 ROW_CS VDD VSS / RSC_IHPSG13_CBUFX8 +XI73 PULSE_O net012 VDD VSS / RSC_IHPSG13_CINVX2 +XI8 net9 net8 VDD VSS / RSC_IHPSG13_CINVX2 +XI64 ck ck_dly VDD VSS / RSC_IHPSG13_CDLYX2 +XI86 CS_I BIST_CS_I BIST_EN cs VDD VSS / RSC_IHPSG13_MX2X2 +XI87 CK_I BIST_CK_I BIST_EN ck VDD VSS / RSC_IHPSG13_MX2X2 +XI85 WE_I BIST_WE_I BIST_EN we VDD VSS / RSC_IHPSG13_MX2X2 +XI84 RE_I BIST_RE_I BIST_EN re VDD VSS / RSC_IHPSG13_MX2X2 +XI22 we cs WEandCS VDD VSS / RSC_IHPSG13_AND2X2 +XBM_TIEL B_TIEL_O VDD VSS / RSC_IHPSG13_TIEL +XI48 ck_dly ck_regs VDD VSS / RSC_IHPSG13_CINVX4 +XI81 net016 WCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI80 net018 RCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI78 net8 net020 VDD VSS / RSC_IHPSG13_CINVX4 +XI6 PULSE_L PULSE_H net9 VDD VSS / RSC_IHPSG13_XOR2X2 +XI79 net020 ECLK VDD VSS / RSC_IHPSG13_CINVX8 +XI63 aclk ACLK_N VDD VSS / RSC_IHPSG13_CINVX8 +XI21 re we cs WEorREandCS VDD VSS / RSC_IHPSG13_OA12X1 +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_1P_COLDEC2 ACLK_N ADDR<1> ADDR<0> ADDR_COL<1> ADDR_COL<0> ++ ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ADDR_DEC<2> ++ ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI14<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net6<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net6<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI1<3> PADR<1> PADR<0> addr_n<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<2> PADR<1> NADR<0> addr_n<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<1> NADR<1> PADR<0> addr_n<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<0> NADR<1> NADR<0> addr_n<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI16<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI17<3> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_TIEL +XI17<2> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_TIEL +XI17<1> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_TIEL +XI17<0> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RSC_IHPSG13_NOR2X2 A B Z VDD VSS +MP1 Z B net9 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 net9 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z B VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 Z A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX4_WN A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_1P_BLDRV BLC BLC_SEL BLT BLT_SEL PRE_N SEL_P WR_ONE WR_ZERO ++ VDD VSS +XCDEC SEL_P WR_ZERO BLC_PMOS_DRIVE VDD VSS / RSC_IHPSG13_NAND2X2 +XTDEC SEL_P WR_ONE BLT_PMOS_DRIVE VDD VSS / RSC_IHPSG13_NAND2X2 +MTWN BLT BLT_NMOS_DRIVE VSS VSS sg13_lv_nmos m=1 w=4.82u l=130.00n ++ ng=2 nrd=0 nrs=0 +MCWN BLC BLC_NMOS_DRIVE VSS VSS sg13_lv_nmos m=1 w=4.82u l=130.00n ++ ng=2 nrd=0 nrs=0 +MCWP BLC BLC_PMOS_DRIVE VDD VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 ++ nrd=0 nrs=0 +MTWP BLT BLT_PMOS_DRIVE VDD VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 ++ nrd=0 nrs=0 +MTSP BLT_SEL SEL_N BLT VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 nrd=0 ++ nrs=0 +MTPR BLT PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ng=2 nrd=0 ++ nrs=0 +MCSP BLC_SEL SEL_N BLC VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 nrd=0 ++ nrs=0 +MCPR BLC PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ng=2 nrd=0 ++ nrs=0 +XI86 SEL_P SEL_N VDD VSS / RSC_IHPSG13_INVX2 +XTINV BLC_PMOS_DRIVE BLT_NMOS_DRIVE VDD VSS / RSC_IHPSG13_INVX2 +XCINV BLT_PMOS_DRIVE BLC_NMOS_DRIVE VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RSC_IHPSG13_TIEH Z VDD VSS +MN0 net2 net2 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 Z net2 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_MET3RES A B +R0 B A lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RSC_IHPSG13_DFPQD_MSAFFX2 CP DN DP QN QP VDD VSS +MN12 SN RN DIFFP VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN13 TAIL CP VSS VSS sg13_lv_nmos m=1 w=2.4u l=130.00n ng=2 nrd=0 nrs=0 +MN9 DIFFP DP TAIL VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN10 DIFFN DN TAIL VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN11 RN SN DIFFN VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN19 net33 SN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN20 QN QP net37 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN18 net37 RN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN17 QP QN net33 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP15 SN RN VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP16 RN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP14 DIFFP CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP12 RN SN VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP13 DIFFN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP11 SN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP19 QN QP VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +MP20 QP SN VDD VDD sg13_lv_pmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP18 QN RN VDD VDD sg13_lv_pmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP17 QP QN VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CBUFX2 A Z VDD VSS +MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=540.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=1.1u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_INVX4 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=1.96u l=130.00n ng=2 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_1P_COLCTRL2 A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<3> A_BLC<2> A_BLC<1> ++ A_BLC<0> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_I80 A_WCLK_B_R A_RCLK_B_R net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I44 A_WCLK_B_R A_BM_N A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_ADDR_DEC<2> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_ADDR_DEC<1> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<0> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_R A_RCLK_B_L / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_R A_RCLK_L / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_R A_WCLK_B_L / RSC_IHPSG13_MET3RES +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_I78 A_RCLK_B_R A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_R VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_R A_RCLK_B_R VDD VSS / RSC_IHPSG13_CINVX2 +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_1P_COLDRV13_FILL4 VDD VSS +XI0<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_1P_COLDRV13_FILL4C2 VDD VSS +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_4096x16_c3_1P_COLDEC4 ACLK_N ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<3> BIST_ADDR<2> ++ BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI15 ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI14 addr_int ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int net7<0> VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net7<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net7<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net7<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RSC_IHPSG13_AND2X4 A B Z VDD VSS +MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.96u l=130.00n ng=2 nrd=0 nrs=0 +MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_1P_COLCTRL4 A_ADDR_COL A_ADDR_DEC<7> A_ADDR_DEC<6> ++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<15> A_BLC<14> ++ A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> ++ A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<15> A_BLT<14> ++ A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L ++ A_DCLK_B_R A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L ++ A_RCLK_R A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_I80 A_WCLK_B_L A_RCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DO_WRITE_P A_DI_N A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4 +XA_CAPS<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_N0 A_P0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL A_N0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_I81<1> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_BLTMUX<15> A_BLC<15> A_BLC_SEL A_BLT<15> A_BLT_SEL A_PRE_N A_SEL_P<15> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV +XA_BLTMUX<14> A_BLC<14> A_BLC_SEL A_BLT<14> A_BLT_SEL A_PRE_N A_SEL_P<14> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV +XA_BLTMUX<13> A_BLC<13> A_BLC_SEL A_BLT<13> A_BLT_SEL A_PRE_N A_SEL_P<13> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV +XA_BLTMUX<12> A_BLC<12> A_BLC_SEL A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<12> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV +XA_BLTMUX<11> A_BLC<11> A_BLC_SEL A_BLT<11> A_BLT_SEL A_PRE_N A_SEL_P<11> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV +XA_BLTMUX<10> A_BLC<10> A_BLC_SEL A_BLT<10> A_BLT_SEL A_PRE_N A_SEL_P<10> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV +XA_BLTMUX<9> A_BLC<9> A_BLC_SEL A_BLT<9> A_BLT_SEL A_PRE_N A_SEL_P<9> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV +XA_BLTMUX<8> A_BLC<8> A_BLC_SEL A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<8> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV +XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_SEL_P<7> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV +XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_SEL_P<6> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV +XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_SEL_P<5> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV +XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<4> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_SEL_P<3> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_SEL_P<2> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_SEL_P<1> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<0> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net24 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_DEC3INV<15> net23<0> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<1> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<2> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<3> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<4> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<5> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<6> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<7> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<8> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<9> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<10> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<11> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<12> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<13> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<14> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<15> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I70<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_DEC3<15> A_P0 A_ADDR_DEC<7> net23<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<14> A_P0 A_ADDR_DEC<6> net23<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<13> A_P0 A_ADDR_DEC<5> net23<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<12> A_P0 A_ADDR_DEC<4> net23<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<11> A_P0 A_ADDR_DEC<3> net23<4> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<10> A_P0 A_ADDR_DEC<2> net23<5> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<9> A_P0 A_ADDR_DEC<1> net23<6> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<8> A_P0 A_ADDR_DEC<0> net23<7> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<7> A_N0 A_ADDR_DEC<7> net23<8> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<6> A_N0 A_ADDR_DEC<6> net23<9> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<5> A_N0 A_ADDR_DEC<5> net23<10> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<4> A_N0 A_ADDR_DEC<4> net23<11> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<3> A_N0 A_ADDR_DEC<3> net23<12> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<2> A_N0 A_ADDR_DEC<2> net23<13> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<1> A_N0 A_ADDR_DEC<1> net23<14> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<0> A_N0 A_ADDR_DEC<0> net23<15> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS + + +.SUBCKT RM_IHPSG13_4096x16_c3_1P_COLDEC3 ACLK_N ADDR<2> ADDR<1> ADDR<0> ADDR_COL<1> ++ ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ++ ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> ++ BIST_EN_I VDD VSS +XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net6<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net6<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net6<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_1P_COLCTRL3 A_ADDR_DEC<7> A_ADDR_DEC<6> A_ADDR_DEC<5> ++ A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> A_ADDR_DEC<0> ++ A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> ++ A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> ++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R A_DCLK_L ++ A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R A_TIEH_O ++ A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_R A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_I70<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I44 A_BM_N A_WCLK_B_R A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_ADDR_DEC<7> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV +XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_ADDR_DEC<6> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV +XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_ADDR_DEC<5> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV +XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_ADDR_DEC<4> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_ADDR_DEC<2> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_ADDR_DEC<1> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<0> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I80 A_WCLK_B_R A_RCLK_B_R net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_4096x16_c3_2P_BITKIT_16x2_CORNER VDD_CORE VSS +XI16 VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x16_c3_1P_BITKIT_CORNER +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_2P_BITKIT_EDGE_LR A_WL B_WL NW PW VDD VSS +MN1 VSS A_WL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN0 VSS B_WL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_2P_BITKIT_16x2_EDGE_LR A_WL<15> A_WL<14> A_WL<13> A_WL<12> ++ A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> ++ A_WL<2> A_WL<1> A_WL<0> B_WL<15> B_WL<14> B_WL<13> B_WL<12> B_WL<11> ++ B_WL<10> B_WL<9> B_WL<8> B_WL<7> B_WL<6> B_WL<5> B_WL<4> B_WL<3> B_WL<2> ++ B_WL<1> B_WL<0> VDD_CORE VSS +XI0<15> A_WL<15> B_WL<15> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_4096x16_c3_2P_BITKIT_EDGE_LR +XI0<14> A_WL<14> B_WL<14> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_4096x16_c3_2P_BITKIT_EDGE_LR +XI0<13> A_WL<13> B_WL<13> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_4096x16_c3_2P_BITKIT_EDGE_LR +XI0<12> A_WL<12> B_WL<12> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_4096x16_c3_2P_BITKIT_EDGE_LR +XI0<11> A_WL<11> B_WL<11> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_4096x16_c3_2P_BITKIT_EDGE_LR +XI0<10> A_WL<10> B_WL<10> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_4096x16_c3_2P_BITKIT_EDGE_LR +XI0<9> A_WL<9> B_WL<9> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x16_c3_2P_BITKIT_EDGE_LR +XI0<8> A_WL<8> B_WL<8> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x16_c3_2P_BITKIT_EDGE_LR +XI0<7> A_WL<7> B_WL<7> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x16_c3_2P_BITKIT_EDGE_LR +XI0<6> A_WL<6> B_WL<6> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x16_c3_2P_BITKIT_EDGE_LR +XI0<5> A_WL<5> B_WL<5> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x16_c3_2P_BITKIT_EDGE_LR +XI0<4> A_WL<4> B_WL<4> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x16_c3_2P_BITKIT_EDGE_LR +XI0<3> A_WL<3> B_WL<3> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x16_c3_2P_BITKIT_EDGE_LR +XI0<2> A_WL<2> B_WL<2> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x16_c3_2P_BITKIT_EDGE_LR +XI0<1> A_WL<1> B_WL<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x16_c3_2P_BITKIT_EDGE_LR +XI0<0> A_WL<0> B_WL<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x16_c3_2P_BITKIT_EDGE_LR +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_2P_BITKIT_CELL A_BLC_BOT A_BLC_TOP A_BLT_BOT A_BLT_TOP ++ A_LWL A_RWL B_BLC_BOT B_BLC_TOP B_BLT_BOT B_BLT_TOP B_LWL B_RWL NW PW VDD VSS +MN5 NC B_RWL B_BLC_BOT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN4 B_BLT_BOT B_LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN0 NC NT VSS PW sg13_lv_nmos m=1 w=600.0n l=130.00n ng=2 nrd=0 nrs=0 +MN1 NT NC VSS PW sg13_lv_nmos m=1 w=600.0n l=130.00n ng=2 nrd=0 nrs=0 +MN3 NC A_RWL A_BLC_TOP PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN2 A_BLT_TOP A_LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MP1 NT NC VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 NC NT VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +R5 B_RWL B_LWL lvsres w=2.6e-07 l=6e-07 +R4 B_BLC_BOT B_BLC_TOP lvsres w=2.6e-07 l=6e-07 +R3 B_BLT_BOT B_BLT_TOP lvsres w=2.6e-07 l=6e-07 +R1 A_BLC_BOT A_BLC_TOP lvsres w=2.6e-07 l=6e-07 +R0 A_BLT_BOT A_BLT_TOP lvsres w=2.6e-07 l=6e-07 +R2 A_RWL A_LWL lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_2P_BITKIT_16x2_SRAM A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> ++ A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<15> ++ A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> ++ A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> ++ A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> ++ A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> B_BLC_BOT<1> ++ B_BLC_BOT<0> B_BLC_TOP<1> B_BLC_TOP<0> B_BLT_BOT<1> B_BLT_BOT<0> ++ B_BLT_TOP<1> B_BLT_TOP<0> B_LWL<15> B_LWL<14> B_LWL<13> B_LWL<12> B_LWL<11> ++ B_LWL<10> B_LWL<9> B_LWL<8> B_LWL<7> B_LWL<6> B_LWL<5> B_LWL<4> B_LWL<3> ++ B_LWL<2> B_LWL<1> B_LWL<0> B_RWL<15> B_RWL<14> B_RWL<13> B_RWL<12> B_RWL<11> ++ B_RWL<10> B_RWL<9> B_RWL<8> B_RWL<7> B_RWL<6> B_RWL<5> B_RWL<4> B_RWL<3> ++ B_RWL<2> B_RWL<1> B_RWL<0> VDD_CORE VSS +XCELL<31> A_BLC_TOP<1> A_RBLC<15> A_BLT_TOP<1> A_RBLT<15> A_XWL<15> A_RWL<15> ++ B_BLC_TOP<1> B_RBLC<15> B_BLT_TOP<1> B_RBLT<15> B_XWL<15> B_RWL<15> ++ VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x16_c3_2P_BITKIT_CELL +XCELL<30> A_RBLC<14> A_RBLC<15> A_RBLT<14> A_RBLT<15> A_XWL<14> A_RWL<14> ++ B_RBLC<14> B_RBLC<15> B_RBLT<14> B_RBLT<15> B_XWL<14> B_RWL<14> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_CELL +XCELL<29> A_RBLC<14> A_RBLC<13> A_RBLT<14> A_RBLT<13> A_XWL<13> A_RWL<13> ++ B_RBLC<14> B_RBLC<13> B_RBLT<14> B_RBLT<13> B_XWL<13> B_RWL<13> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_CELL +XCELL<28> A_RBLC<12> A_RBLC<13> A_RBLT<12> A_RBLT<13> A_XWL<12> A_RWL<12> ++ B_RBLC<12> B_RBLC<13> B_RBLT<12> B_RBLT<13> B_XWL<12> B_RWL<12> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_CELL +XCELL<27> A_RBLC<12> A_RBLC<11> A_RBLT<12> A_RBLT<11> A_XWL<11> A_RWL<11> ++ B_RBLC<12> B_RBLC<11> B_RBLT<12> B_RBLT<11> B_XWL<11> B_RWL<11> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_CELL +XCELL<26> A_RBLC<10> A_RBLC<11> A_RBLT<10> A_RBLT<11> A_XWL<10> A_RWL<10> ++ B_RBLC<10> B_RBLC<11> B_RBLT<10> B_RBLT<11> B_XWL<10> B_RWL<10> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_CELL +XCELL<25> A_RBLC<10> A_RBLC<9> A_RBLT<10> A_RBLT<9> A_XWL<9> A_RWL<9> ++ B_RBLC<10> B_RBLC<9> B_RBLT<10> B_RBLT<9> B_XWL<9> B_RWL<9> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_CELL +XCELL<24> A_RBLC<8> A_RBLC<9> A_RBLT<8> A_RBLT<9> A_XWL<8> A_RWL<8> B_RBLC<8> ++ B_RBLC<9> B_RBLT<8> B_RBLT<9> B_XWL<8> B_RWL<8> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_CELL +XCELL<23> A_RBLC<8> A_RBLC<7> A_RBLT<8> A_RBLT<7> A_XWL<7> A_RWL<7> B_RBLC<8> ++ B_RBLC<7> B_RBLT<8> B_RBLT<7> B_XWL<7> B_RWL<7> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_CELL +XCELL<22> A_RBLC<6> A_RBLC<7> A_RBLT<6> A_RBLT<7> A_XWL<6> A_RWL<6> B_RBLC<6> ++ B_RBLC<7> B_RBLT<6> B_RBLT<7> B_XWL<6> B_RWL<6> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_CELL +XCELL<21> A_RBLC<6> A_RBLC<5> A_RBLT<6> A_RBLT<5> A_XWL<5> A_RWL<5> B_RBLC<6> ++ B_RBLC<5> B_RBLT<6> B_RBLT<5> B_XWL<5> B_RWL<5> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_CELL +XCELL<20> A_RBLC<4> A_RBLC<5> A_RBLT<4> A_RBLT<5> A_XWL<4> A_RWL<4> B_RBLC<4> ++ B_RBLC<5> B_RBLT<4> B_RBLT<5> B_XWL<4> B_RWL<4> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_CELL +XCELL<19> A_RBLC<4> A_RBLC<3> A_RBLT<4> A_RBLT<3> A_XWL<3> A_RWL<3> B_RBLC<4> ++ B_RBLC<3> B_RBLT<4> B_RBLT<3> B_XWL<3> B_RWL<3> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_CELL +XCELL<18> A_RBLC<2> A_RBLC<3> A_RBLT<2> A_RBLT<3> A_XWL<2> A_RWL<2> B_RBLC<2> ++ B_RBLC<3> B_RBLT<2> B_RBLT<3> B_XWL<2> B_RWL<2> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_CELL +XCELL<17> A_RBLC<2> A_RBLC<1> A_RBLT<2> A_RBLT<1> A_XWL<1> A_RWL<1> B_RBLC<2> ++ B_RBLC<1> B_RBLT<2> B_RBLT<1> B_XWL<1> B_RWL<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_CELL +XCELL<16> A_BLC_BOT<1> A_RBLC<1> A_BLT_BOT<1> A_RBLT<1> A_XWL<0> A_RWL<0> ++ B_BLC_BOT<1> B_RBLC<1> B_BLT_BOT<1> B_RBLT<1> B_XWL<0> B_RWL<0> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_CELL +XCELL<15> A_BLC_TOP<0> A_LBLC<15> A_BLT_TOP<0> A_LBLT<15> A_LWL<15> A_XWL<15> ++ B_BLC_TOP<0> B_LBLC<15> B_BLT_TOP<0> B_LBLT<15> B_LWL<15> B_XWL<15> ++ VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x16_c3_2P_BITKIT_CELL +XCELL<14> A_LBLC<14> A_LBLC<15> A_LBLT<14> A_LBLT<15> A_LWL<14> A_XWL<14> ++ B_LBLC<14> B_LBLC<15> B_LBLT<14> B_LBLT<15> B_LWL<14> B_XWL<14> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_CELL +XCELL<13> A_LBLC<14> A_LBLC<13> A_LBLT<14> A_LBLT<13> A_LWL<13> A_XWL<13> ++ B_LBLC<14> B_LBLC<13> B_LBLT<14> B_LBLT<13> B_LWL<13> B_XWL<13> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_CELL +XCELL<12> A_LBLC<12> A_LBLC<13> A_LBLT<12> A_LBLT<13> A_LWL<12> A_XWL<12> ++ B_LBLC<12> B_LBLC<13> B_LBLT<12> B_LBLT<13> B_LWL<12> B_XWL<12> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_CELL +XCELL<11> A_LBLC<12> A_LBLC<11> A_LBLT<12> A_LBLT<11> A_LWL<11> A_XWL<11> ++ B_LBLC<12> B_LBLC<11> B_LBLT<12> B_LBLT<11> B_LWL<11> B_XWL<11> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_CELL +XCELL<10> A_LBLC<10> A_LBLC<11> A_LBLT<10> A_LBLT<11> A_LWL<10> A_XWL<10> ++ B_LBLC<10> B_LBLC<11> B_LBLT<10> B_LBLT<11> B_LWL<10> B_XWL<10> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_CELL +XCELL<9> A_LBLC<10> A_LBLC<9> A_LBLT<10> A_LBLT<9> A_LWL<9> A_XWL<9> ++ B_LBLC<10> B_LBLC<9> B_LBLT<10> B_LBLT<9> B_LWL<9> B_XWL<9> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_CELL +XCELL<8> A_LBLC<8> A_LBLC<9> A_LBLT<8> A_LBLT<9> A_LWL<8> A_XWL<8> B_LBLC<8> ++ B_LBLC<9> B_LBLT<8> B_LBLT<9> B_LWL<8> B_XWL<8> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_CELL +XCELL<7> A_LBLC<8> A_LBLC<7> A_LBLT<8> A_LBLT<7> A_LWL<7> A_XWL<7> B_LBLC<8> ++ B_LBLC<7> B_LBLT<8> B_LBLT<7> B_LWL<7> B_XWL<7> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_CELL +XCELL<6> A_LBLC<6> A_LBLC<7> A_LBLT<6> A_LBLT<7> A_LWL<6> A_XWL<6> B_LBLC<6> ++ B_LBLC<7> B_LBLT<6> B_LBLT<7> B_LWL<6> B_XWL<6> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_CELL +XCELL<5> A_LBLC<6> A_LBLC<5> A_LBLT<6> A_LBLT<5> A_LWL<5> A_XWL<5> B_LBLC<6> ++ B_LBLC<5> B_LBLT<6> B_LBLT<5> B_LWL<5> B_XWL<5> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_CELL +XCELL<4> A_LBLC<4> A_LBLC<5> A_LBLT<4> A_LBLT<5> A_LWL<4> A_XWL<4> B_LBLC<4> ++ B_LBLC<5> B_LBLT<4> B_LBLT<5> B_LWL<4> B_XWL<4> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_CELL +XCELL<3> A_LBLC<4> A_LBLC<3> A_LBLT<4> A_LBLT<3> A_LWL<3> A_XWL<3> B_LBLC<4> ++ B_LBLC<3> B_LBLT<4> B_LBLT<3> B_LWL<3> B_XWL<3> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_CELL +XCELL<2> A_LBLC<2> A_LBLC<3> A_LBLT<2> A_LBLT<3> A_LWL<2> A_XWL<2> B_LBLC<2> ++ B_LBLC<3> B_LBLT<2> B_LBLT<3> B_LWL<2> B_XWL<2> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_CELL +XCELL<1> A_LBLC<2> A_LBLC<1> A_LBLT<2> A_LBLT<1> A_LWL<1> A_XWL<1> B_LBLC<2> ++ B_LBLC<1> B_LBLT<2> B_LBLT<1> B_LWL<1> B_XWL<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_CELL +XCELL<0> A_BLC_BOT<0> A_LBLC<1> A_BLT_BOT<0> A_LBLT<1> A_LWL<0> A_XWL<0> ++ B_BLC_BOT<0> B_LBLC<1> B_BLT_BOT<0> B_LBLT<1> B_LWL<0> B_XWL<0> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_CELL +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_2P_BITKIT_EDGE_TB A_BLC A_BLT B_BLC B_BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_2P_BITKIT_16x2_EDGE_TB A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ B_BLC<1> B_BLC<0> B_BLT<1> B_BLT<0> VDD_CORE VSS +XEDGE<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_EDGE_TB +XEDGE<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_EDGE_TB +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_2P_BITKIT_TAP A_BLC A_BLT B_BLC B_BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_2P_BITKIT_16x2_TAP A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ B_BLC<1> B_BLC<0> B_BLT<1> B_BLT<0> VDD_CORE VSS +XIEDGEBP_COL1<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_EDGE_TB +XIEDGEBP_COL1<0> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_EDGE_TB +XIEDGEBP_COL2<1> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_EDGE_TB +XIEDGEBP_COL2<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_EDGE_TB +XITAP<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_TAP +XITAP<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_TAP +.ENDS + + +.SUBCKT RM_IHPSG13_4096x16_c3_1P_BITKIT_TAP_LR NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_2P_BITKIT_16x2_TAP_LR VDD_CORE VSS +XCORNER<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x16_c3_1P_BITKIT_CORNER +XCORNER<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x16_c3_1P_BITKIT_CORNER +XTAP_BORDER VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x16_c3_1P_BITKIT_TAP_LR +.ENDS + +.SUBCKT RSC_IHPSG13_CBUFX12 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=4.23u l=130.00n ng=6 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=9.72u l=130.00n ng=6 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_2P_COLDRV13X12 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX12 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=9.72u l=130.00n ng=6 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_2P_WLDRV16X12 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX12 +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_2P_DEC04 ADDR<3> ADDR<2> ADDR<1> ADDR<0> CS ECLK_H_BOT ++ ECLK_H_TOP ECLK_L_BOT ECLK_L_TOP WL<15> WL<14> WL<13> WL<12> WL<11> WL<10> ++ WL<9> WL<8> WL<7> WL<6> WL<5> WL<4> WL<3> WL<2> WL<1> WL<0> VDD VSS +XI0<3> PADR<1> PADR<0> sel01<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<2> PADR<1> NADR<0> sel01<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<1> NADR<1> PADR<0> sel01<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<0> NADR<1> NADR<0> sel01<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI4 ECLK_L_BOT EN VDD VSS / RSC_IHPSG13_CINVX4 +XI5 ECLK_H_BOT ECLK_L_BOT VDD VSS / RSC_IHPSG13_CINVX2 +XI3<3> PADR<3> NADR<3> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> PADR<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> PADR<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> PADR<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XR0 ECLK_H_BOT ECLK_H_TOP / RSC_IHPSG13_MET2RES +XI11 ECLK_L_BOT ECLK_L_TOP / RSC_IHPSG13_MET2RES +XI1<3> PADR<2> PADR<3> CS sel23<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<2> PADR<3> CS sel23<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<2> NADR<3> CS sel23<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<2> NADR<3> CS sel23<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI2<15> sel23<3> sel01<3> EN WL<15> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<14> sel23<3> sel01<2> EN WL<14> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<13> sel23<3> sel01<1> EN WL<13> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<12> sel23<3> sel01<0> EN WL<12> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<11> sel23<2> sel01<3> EN WL<11> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<10> sel23<2> sel01<2> EN WL<10> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<9> sel23<2> sel01<1> EN WL<9> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<8> sel23<2> sel01<0> EN WL<8> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<7> sel23<1> sel01<3> EN WL<7> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<6> sel23<1> sel01<2> EN WL<6> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<5> sel23<1> sel01<1> EN WL<5> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<4> sel23<1> sel01<0> EN WL<4> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<3> sel23<0> sel01<3> EN WL<3> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<2> sel23<0> sel01<2> EN WL<2> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<1> sel23<0> sel01<1> EN WL<1> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<0> sel23<0> sel01<0> EN WL<0> VDD VSS / RSC_IHPSG13_NOR3X2 +XCAPS4 VDD VSS / RSC_IHPSG13_FILLCAP4 +XLATCH<3> CS ADDR<3> PADR<3> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<2> CS ADDR<2> PADR<2> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<1> CS ADDR<1> PADR<1> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<0> CS ADDR<0> PADR<0> VDD VSS / RSC_IHPSG13_LHPQX2 +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_2P_DEC02 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC ADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI2<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI2<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_2P_DEC01 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC NADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI2<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI2<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_2P_DEC00 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC NADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV<1> ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +XADDRINV<0> ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_2P_DEC03 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC ADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_2P_ROWDEC9 ADDR_N_I<8> ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ++ ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ++ WL_O<511> WL_O<510> WL_O<509> WL_O<508> WL_O<507> WL_O<506> WL_O<505> ++ WL_O<504> WL_O<503> WL_O<502> WL_O<501> WL_O<500> WL_O<499> WL_O<498> ++ WL_O<497> WL_O<496> WL_O<495> WL_O<494> WL_O<493> WL_O<492> WL_O<491> ++ WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> WL_O<484> ++ WL_O<483> WL_O<482> WL_O<481> WL_O<480> WL_O<479> WL_O<478> WL_O<477> ++ WL_O<476> WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> ++ WL_O<469> WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> WL_O<463> ++ WL_O<462> WL_O<461> WL_O<460> WL_O<459> WL_O<458> WL_O<457> WL_O<456> ++ WL_O<455> WL_O<454> WL_O<453> WL_O<452> WL_O<451> WL_O<450> WL_O<449> ++ WL_O<448> WL_O<447> WL_O<446> WL_O<445> WL_O<444> WL_O<443> WL_O<442> ++ WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> WL_O<436> WL_O<435> ++ WL_O<434> WL_O<433> WL_O<432> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> WL_O<415> WL_O<414> ++ WL_O<413> WL_O<412> WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> ++ WL_O<406> WL_O<405> WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> ++ WL_O<399> WL_O<398> WL_O<397> WL_O<396> WL_O<395> WL_O<394> WL_O<393> ++ WL_O<392> WL_O<391> WL_O<390> WL_O<389> WL_O<388> WL_O<387> WL_O<386> ++ WL_O<385> WL_O<384> WL_O<383> WL_O<382> WL_O<381> WL_O<380> WL_O<379> ++ WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> WL_O<372> ++ WL_O<371> WL_O<370> WL_O<369> WL_O<368> WL_O<367> WL_O<366> WL_O<365> ++ WL_O<364> WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> ++ WL_O<357> WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> WL_O<351> ++ WL_O<350> WL_O<349> WL_O<348> WL_O<347> WL_O<346> WL_O<345> WL_O<344> ++ WL_O<343> WL_O<342> WL_O<341> WL_O<340> WL_O<339> WL_O<338> WL_O<337> ++ WL_O<336> WL_O<335> WL_O<334> WL_O<333> WL_O<332> WL_O<331> WL_O<330> ++ WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> WL_O<324> WL_O<323> ++ WL_O<322> WL_O<321> WL_O<320> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> WL_O<303> WL_O<302> ++ WL_O<301> WL_O<300> WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> ++ WL_O<294> WL_O<293> WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> ++ WL_O<287> WL_O<286> WL_O<285> WL_O<284> WL_O<283> WL_O<282> WL_O<281> ++ WL_O<280> WL_O<279> WL_O<278> WL_O<277> WL_O<276> WL_O<275> WL_O<274> ++ WL_O<273> WL_O<272> WL_O<271> WL_O<270> WL_O<269> WL_O<268> WL_O<267> ++ WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> WL_O<260> ++ WL_O<259> WL_O<258> WL_O<257> WL_O<256> WL_O<255> WL_O<254> WL_O<253> ++ WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> ++ WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> WL_O<239> ++ WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> WL_O<233> WL_O<232> ++ WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> WL_O<226> WL_O<225> ++ WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> WL_O<219> WL_O<218> ++ WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> WL_O<212> WL_O<211> ++ WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> WL_O<191> WL_O<190> ++ WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> ++ WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> ++ WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> WL_O<170> WL_O<169> ++ WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> WL_O<163> WL_O<162> ++ WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> WL_O<156> WL_O<155> ++ WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> WL_O<148> ++ WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> WL_O<142> WL_O<141> ++ WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> ++ WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> WL_O<127> ++ WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> ++ WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> ++ WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> ++ WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> ++ WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XSEL<31> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<31> ECLK_H<31> ++ ECLK_H<32> ECLK_B<31> ECLK_B<32> WL_O<511> WL_O<510> WL_O<509> WL_O<508> ++ WL_O<507> WL_O<506> WL_O<505> WL_O<504> WL_O<503> WL_O<502> WL_O<501> ++ WL_O<500> WL_O<499> WL_O<498> WL_O<497> WL_O<496> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC04 +XSEL<30> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<30> ECLK_H<30> ++ ECLK_H<31> ECLK_B<30> ECLK_B<31> WL_O<495> WL_O<494> WL_O<493> WL_O<492> ++ WL_O<491> WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> ++ WL_O<484> WL_O<483> WL_O<482> WL_O<481> WL_O<480> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC04 +XSEL<29> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<29> ECLK_H<29> ++ ECLK_H<30> ECLK_B<29> ECLK_B<30> WL_O<479> WL_O<478> WL_O<477> WL_O<476> ++ WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> WL_O<469> ++ WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC04 +XSEL<28> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<28> ECLK_H<28> ++ ECLK_H<29> ECLK_B<28> ECLK_B<29> WL_O<463> WL_O<462> WL_O<461> WL_O<460> ++ WL_O<459> WL_O<458> WL_O<457> WL_O<456> WL_O<455> WL_O<454> WL_O<453> ++ WL_O<452> WL_O<451> WL_O<450> WL_O<449> WL_O<448> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC04 +XSEL<27> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<27> ECLK_H<27> ++ ECLK_H<28> ECLK_B<27> ECLK_B<28> WL_O<447> WL_O<446> WL_O<445> WL_O<444> ++ WL_O<443> WL_O<442> WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> ++ WL_O<436> WL_O<435> WL_O<434> WL_O<433> WL_O<432> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC04 +XSEL<26> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<26> ECLK_H<26> ++ ECLK_H<27> ECLK_B<26> ECLK_B<27> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC04 +XSEL<25> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<25> ECLK_H<25> ++ ECLK_H<26> ECLK_B<25> ECLK_B<26> WL_O<415> WL_O<414> WL_O<413> WL_O<412> ++ WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> WL_O<406> WL_O<405> ++ WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC04 +XSEL<24> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<24> ECLK_H<24> ++ ECLK_H<25> ECLK_B<24> ECLK_B<25> WL_O<399> WL_O<398> WL_O<397> WL_O<396> ++ WL_O<395> WL_O<394> WL_O<393> WL_O<392> WL_O<391> WL_O<390> WL_O<389> ++ WL_O<388> WL_O<387> WL_O<386> WL_O<385> WL_O<384> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC04 +XSEL<23> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<23> ECLK_H<23> ++ ECLK_H<24> ECLK_B<23> ECLK_B<24> WL_O<383> WL_O<382> WL_O<381> WL_O<380> ++ WL_O<379> WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> ++ WL_O<372> WL_O<371> WL_O<370> WL_O<369> WL_O<368> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC04 +XSEL<22> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<22> ECLK_H<22> ++ ECLK_H<23> ECLK_B<22> ECLK_B<23> WL_O<367> WL_O<366> WL_O<365> WL_O<364> ++ WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> WL_O<357> ++ WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC04 +XSEL<21> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<21> ECLK_H<21> ++ ECLK_H<22> ECLK_B<21> ECLK_B<22> WL_O<351> WL_O<350> WL_O<349> WL_O<348> ++ WL_O<347> WL_O<346> WL_O<345> WL_O<344> WL_O<343> WL_O<342> WL_O<341> ++ WL_O<340> WL_O<339> WL_O<338> WL_O<337> WL_O<336> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC04 +XSEL<20> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<20> ECLK_H<20> ++ ECLK_H<21> ECLK_B<20> ECLK_B<21> WL_O<335> WL_O<334> WL_O<333> WL_O<332> ++ WL_O<331> WL_O<330> WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> ++ WL_O<324> WL_O<323> WL_O<322> WL_O<321> WL_O<320> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC04 +XSEL<19> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<19> ECLK_H<19> ++ ECLK_H<20> ECLK_B<19> ECLK_B<20> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC04 +XSEL<18> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<18> ECLK_H<18> ++ ECLK_H<19> ECLK_B<18> ECLK_B<19> WL_O<303> WL_O<302> WL_O<301> WL_O<300> ++ WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> WL_O<294> WL_O<293> ++ WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC04 +XSEL<17> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<17> ECLK_H<17> ++ ECLK_H<18> ECLK_B<17> ECLK_B<18> WL_O<287> WL_O<286> WL_O<285> WL_O<284> ++ WL_O<283> WL_O<282> WL_O<281> WL_O<280> WL_O<279> WL_O<278> WL_O<277> ++ WL_O<276> WL_O<275> WL_O<274> WL_O<273> WL_O<272> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC04 +XSEL<16> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<16> ECLK_H<16> ++ ECLK_H<17> ECLK_B<16> ECLK_B<17> WL_O<271> WL_O<270> WL_O<269> WL_O<268> ++ WL_O<267> WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> ++ WL_O<260> WL_O<259> WL_O<258> WL_O<257> WL_O<256> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC04 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_4096x16_c3_2P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_4096x16_c3_2P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_4096x16_c3_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_4096x16_c3_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_4096x16_c3_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_4096x16_c3_2P_DEC04 +XDEC10<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<6> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC02 +XDEC10<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<2> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC02 +XDEC10<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<30> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC02 +XDEC10<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<26> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC02 +XDEC10<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<22> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC02 +XDEC10<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<18> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<14> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<10> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<6> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<2> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC02 +XDEC01<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC01 +XDEC01<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<5> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC01 +XDEC01<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<1> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC01 +XDEC01<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<29> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC01 +XDEC01<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<25> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC01 +XDEC01<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<21> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC01 +XDEC01<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<17> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<13> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<9> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<5> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<1> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC01 +XL2<258> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<257> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<256> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<255> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<254> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<253> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<252> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<251> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<250> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<249> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<248> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<247> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<246> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<245> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<244> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<243> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<242> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<241> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<240> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<239> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<238> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<237> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<236> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<235> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<234> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<233> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<232> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<231> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<230> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<229> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<228> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<227> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<226> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<225> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<224> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<223> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<222> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<221> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<220> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<219> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<218> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<217> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<216> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<215> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<214> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<213> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<212> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<211> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<210> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<209> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<208> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<207> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<206> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<205> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<204> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<203> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<202> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<201> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<200> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<199> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<198> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<197> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<196> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<195> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<194> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<193> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<192> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<191> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<190> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<189> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<188> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<187> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<186> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<185> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<184> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<183> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<182> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<181> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<180> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<179> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<178> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<177> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<176> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<175> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<174> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<173> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<172> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<171> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<170> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<169> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<168> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<167> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<166> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<165> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<164> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<163> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<162> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<161> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<160> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<159> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<158> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<157> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<156> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<155> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<154> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<153> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<152> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<151> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<150> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<149> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<148> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<147> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<146> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<145> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<144> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<143> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<142> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<141> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<140> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<139> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<138> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<137> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<136> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<135> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<134> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<133> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC00<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC00 +XDEC00<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<4> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC00 +XDEC00<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<0> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC00 +XDEC00<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<28> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC00 +XDEC00<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<24> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC00 +XDEC00<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<20> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC00 +XDEC00<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<16> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<12> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<8> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<4> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<0> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC00 +XDEC11<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<7> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC03 +XDEC11<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<3> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC03 +XDEC11<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<31> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC03 +XDEC11<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<27> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC03 +XDEC11<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<23> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC03 +XDEC11<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<19> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<15> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<11> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<7> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<3> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC03 +XI0 ADDR_N_I<9> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_2P_ROWREG9 ACLK_N_I ADDR_I<8> ADDR_I<7> ADDR_I<6> ADDR_I<5> ++ ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<8> ADDR_N_O<7> ++ ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ++ ADDR_N_O<0> BIST_ADDR_I<8> BIST_ADDR_I<7> BIST_ADDR_I<6> BIST_ADDR_I<5> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XDFF<8> BIST_EN_I BIST_ADDR_I<8> ACLK_N_I ADDR_I<8> q_int<8> net04<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net04<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net04<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net04<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net04<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net04<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net04<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net04<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net04<8> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDRV<8> qn_int<8> ADDR_N_O<8> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XINV<8> q_int<8> qn_int<8> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +.ENDS + +.SUBCKT RM_IHPSG13_4096x16_c3_2P_DLY_MUX A SEL Z VDD VSS +XI11 net4 Z VDD VSS / RSC_IHPSG13_CINVX2 +XI8 A D<3> SEL net4 VDD VSS / RSC_IHPSG13_MX2IX1 +XI20<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1 +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_2P_CTRL ACLK_N BIST_CK_I BIST_CS_I BIST_EN BIST_RE_I ++ BIST_WE_I B_TIEL_O CK_I CS_I DCLK ECLK PULSE_H PULSE_L PULSE_O RCLK RE_I ++ ROW_CS WCLK WE_I VDD VSS +XI17 ck_regs we col_we VDD VSS / RSC_IHPSG13_DFNQX2 +XI16 ck_regs re col_re VDD VSS / RSC_IHPSG13_DFNQX2 +XI18 ck_regs cs net7 VDD VSS / RSC_IHPSG13_DFNQX2 +XI71 ACLK_N net012 PULSE_O VDD VSS / RSC_IHPSG13_DFNQX2 +XI77 col_we net017 net016 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI76 col_re net017 net018 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI15 ck_dly WEorREandCS aclk VDD VSS / RSC_IHPSG13_CGATEPX4 +XI14 ck WEandCS DCLK VDD VSS / RSC_IHPSG13_CGATEPX4 +XI60 net7 ROW_CS VDD VSS / RSC_IHPSG13_CBUFX8 +XI73 PULSE_O net012 VDD VSS / RSC_IHPSG13_CINVX2 +XI8 net017 net8 VDD VSS / RSC_IHPSG13_CINVX2 +XCAPS4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XBM_TIEL B_TIEL_O VDD VSS / RSC_IHPSG13_TIEL +XI64 ck ck_dly VDD VSS / RSC_IHPSG13_CDLYX2 +XI86 CS_I BIST_CS_I BIST_EN cs VDD VSS / RSC_IHPSG13_MX2X2 +XI87 CK_I BIST_CK_I BIST_EN ck VDD VSS / RSC_IHPSG13_MX2X2 +XI85 WE_I BIST_WE_I BIST_EN we VDD VSS / RSC_IHPSG13_MX2X2 +XI84 RE_I BIST_RE_I BIST_EN re VDD VSS / RSC_IHPSG13_MX2X2 +XI48 ck_dly ck_regs VDD VSS / RSC_IHPSG13_CINVX4 +XI81 net016 WCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI80 net018 RCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI78 net8 net020 VDD VSS / RSC_IHPSG13_CINVX4 +XCAPS8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI6 PULSE_L PULSE_H net017 VDD VSS / RSC_IHPSG13_XOR2X2 +XI22 we cs WEandCS VDD VSS / RSC_IHPSG13_AND2X2 +XI79 net020 ECLK VDD VSS / RSC_IHPSG13_CINVX8 +XI63 aclk ACLK_N VDD VSS / RSC_IHPSG13_CINVX8 +XI21 re we cs WEorREandCS VDD VSS / RSC_IHPSG13_OA12X1 +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_2P_COLDEC5 ACLK_N ADDR<4> ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<4> BIST_ADDR<3> ++ BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<4> BIST_EN_I BIST_ADDR<4> ACLK_N ADDR<4> addr_int<1> net13<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int<0> net13<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net13<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net13<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net13<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI15<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI15<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI15<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> addr_int<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_CBUFX2 +XI13<0> addr_int<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XI14<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_2P_BLDRV A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL ++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> ++ A_SEL_P<1> A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> ++ B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> ++ B_SEL_P<2> B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS +MA_CWN<3> A_BLC<3> A_BLC_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CWN<2> A_BLC<2> A_BLC_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CWN<1> A_BLC<1> A_BLC_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CWN<0> A_BLC<0> A_BLC_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<3> A_BLT<3> A_BLT_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<2> A_BLT<2> A_BLT_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<1> A_BLT<1> A_BLT_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<0> A_BLT<0> A_BLT_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<3> B_BLT<3> B_BLT_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<2> B_BLT<2> B_BLT_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<1> B_BLT<1> B_BLT_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<0> B_BLT<0> B_BLT_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<3> B_BLC<3> B_BLC_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<2> B_BLC<2> B_BLC_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<1> B_BLC<1> B_BLC_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<0> B_BLC<0> B_BLC_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CPR<3> A_BLC<3> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_CPR<2> A_BLC<2> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_CPR<1> A_BLC<1> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_CPR<0> A_BLC<0> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TWP<3> A_BLT<3> A_BLT_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TWP<2> A_BLT<2> A_BLT_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TWP<1> A_BLT<1> A_BLT_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TWP<0> A_BLT<0> A_BLT_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<3> A_BLC<3> A_BLC_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<2> A_BLC<2> A_BLC_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<1> A_BLC<1> A_BLC_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<0> A_BLC<0> A_BLC_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TPR<3> A_BLT<3> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TPR<2> A_BLT<2> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TPR<1> A_BLT<1> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TPR<0> A_BLT<0> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TSP<3> A_BLT_SEL A_SEL_N<3> A_BLT<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TSP<2> A_BLT_SEL A_SEL_N<2> A_BLT<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TSP<1> A_BLT_SEL A_SEL_N<1> A_BLT<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TSP<0> A_BLT_SEL A_SEL_N<0> A_BLT<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<3> A_BLC_SEL A_SEL_N<3> A_BLC<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<2> A_BLC_SEL A_SEL_N<2> A_BLC<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<1> A_BLC_SEL A_SEL_N<1> A_BLC<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<0> A_BLC_SEL A_SEL_N<0> A_BLC<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<3> B_BLC<3> B_BLC_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<2> B_BLC<2> B_BLC_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<1> B_BLC<1> B_BLC_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<0> B_BLC<0> B_BLC_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<3> B_BLT<3> B_BLT_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<2> B_BLT<2> B_BLT_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<1> B_BLT<1> B_BLT_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<0> B_BLT<0> B_BLT_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<3> B_BLT_SEL B_SEL_N<3> B_BLT<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<2> B_BLT_SEL B_SEL_N<2> B_BLT<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<1> B_BLT_SEL B_SEL_N<1> B_BLT<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<0> B_BLT_SEL B_SEL_N<0> B_BLT<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TPR<3> B_BLT<3> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_TPR<2> B_BLT<2> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_TPR<1> B_BLT<1> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_TPR<0> B_BLT<0> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CSP<3> B_BLC_SEL B_SEL_N<3> B_BLC<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CSP<2> B_BLC_SEL B_SEL_N<2> B_BLC<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CSP<1> B_BLC_SEL B_SEL_N<1> B_BLC<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CSP<0> B_BLC_SEL B_SEL_N<0> B_BLC<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CPR<3> B_BLC<3> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CPR<2> B_BLC<2> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CPR<1> B_BLC<1> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CPR<0> B_BLC<0> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +XA_SEL<3> A_SEL_P<3> A_SEL_N<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_SEL<2> A_SEL_P<2> A_SEL_N<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_SEL<1> A_SEL_P<1> A_SEL_N<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_SEL<0> A_SEL_P<0> A_SEL_N<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_CINV<3> A_BLT_PMOS_DRIVE<3> A_BLC_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_CINV<2> A_BLT_PMOS_DRIVE<2> A_BLC_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_CINV<1> A_BLT_PMOS_DRIVE<1> A_BLC_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_CINV<0> A_BLT_PMOS_DRIVE<0> A_BLC_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<3> A_BLC_PMOS_DRIVE<3> A_BLT_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<2> A_BLC_PMOS_DRIVE<2> A_BLT_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<1> A_BLC_PMOS_DRIVE<1> A_BLT_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<0> A_BLC_PMOS_DRIVE<0> A_BLT_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_SEL<3> B_SEL_P<3> B_SEL_N<3> VDD VSS / RSC_IHPSG13_INVX2 +XB_SEL<2> B_SEL_P<2> B_SEL_N<2> VDD VSS / RSC_IHPSG13_INVX2 +XB_SEL<1> B_SEL_P<1> B_SEL_N<1> VDD VSS / RSC_IHPSG13_INVX2 +XB_SEL<0> B_SEL_P<0> B_SEL_N<0> VDD VSS / RSC_IHPSG13_INVX2 +XB_TINV<3> B_BLC_PMOS_DRIVE<3> B_BLT_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_TINV<2> B_BLC_PMOS_DRIVE<2> B_BLT_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_TINV<1> B_BLC_PMOS_DRIVE<1> B_BLT_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_TINV<0> B_BLC_PMOS_DRIVE<0> B_BLT_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<3> B_BLT_PMOS_DRIVE<3> B_BLC_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<2> B_BLT_PMOS_DRIVE<2> B_BLC_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<1> B_BLT_PMOS_DRIVE<1> B_BLC_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<0> B_BLT_PMOS_DRIVE<0> B_BLC_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TDEC<3> A_SEL_P<3> A_WR_ONE A_BLT_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_TDEC<2> A_SEL_P<2> A_WR_ONE A_BLT_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_TDEC<1> A_SEL_P<1> A_WR_ONE A_BLT_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_TDEC<0> A_SEL_P<0> A_WR_ONE A_BLT_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<3> A_SEL_P<3> A_WR_ZERO A_BLC_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<2> A_SEL_P<2> A_WR_ZERO A_BLC_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<1> A_SEL_P<1> A_WR_ZERO A_BLC_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<0> A_SEL_P<0> A_WR_ZERO A_BLC_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<3> B_SEL_P<3> B_WR_ZERO B_BLC_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<2> B_SEL_P<2> B_WR_ZERO B_BLC_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<1> B_SEL_P<1> B_WR_ZERO B_BLC_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<0> B_SEL_P<0> B_WR_ZERO B_BLC_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<3> B_SEL_P<3> B_WR_ONE B_BLT_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<2> B_SEL_P<2> B_WR_ONE B_BLT_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<1> B_SEL_P<1> B_WR_ONE B_BLT_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<0> B_SEL_P<0> B_WR_ONE B_BLT_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +.ENDS +.SUBCKT RSC_IHPSG13_AND2X6 A B Z VDD VSS +MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=2.94u l=130.00n ng=3 nrd=0 nrs=0 +MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=4.86u l=130.00n ng=3 nrd=0 nrs=0 +MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_2P_COLCTRL5 A_ADDR_COL<1> A_ADDR_COL<0> A_ADDR_DEC<7> ++ A_ADDR_DEC<6> A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<31> ++ A_BLC<30> A_BLC<29> A_BLC<28> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> ++ A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC<19> A_BLC<18> A_BLC<17> ++ A_BLC<16> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> ++ A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> ++ A_BLC<1> A_BLC<0> A_BLT<31> A_BLT<30> A_BLT<29> A_BLT<28> A_BLT<27> ++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT<23> A_BLT<22> A_BLT<21> A_BLT<20> ++ A_BLT<19> A_BLT<18> A_BLT<17> A_BLT<16> A_BLT<15> A_BLT<14> A_BLT<13> ++ A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> ++ A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_COL<1> B_ADDR_COL<0> ++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> ++ B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I ++ B_BIST_EN_I B_BLC<31> B_BLC<30> B_BLC<29> B_BLC<28> B_BLC<27> B_BLC<26> ++ B_BLC<25> B_BLC<24> B_BLC<23> B_BLC<22> B_BLC<21> B_BLC<20> B_BLC<19> ++ B_BLC<18> B_BLC<17> B_BLC<16> B_BLC<15> B_BLC<14> B_BLC<13> B_BLC<12> ++ B_BLC<11> B_BLC<10> B_BLC<9> B_BLC<8> B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> ++ B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<31> B_BLT<30> B_BLT<29> B_BLT<28> ++ B_BLT<27> B_BLT<26> B_BLT<25> B_BLT<24> B_BLT<23> B_BLT<22> B_BLT<21> ++ B_BLT<20> B_BLT<19> B_BLT<18> B_BLT<17> B_BLT<16> B_BLT<15> B_BLT<14> ++ B_BLT<13> B_BLT<12> B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT<7> B_BLT<6> ++ B_BLT<5> B_BLT<4> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L ++ B_DCLK_B_R B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L ++ B_RCLK_R B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS +XB_I80<1> B_WCLK_B_L B_RCLK_B_L B_W_nor_R<1> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XB_I80<0> B_WCLK_B_L B_RCLK_B_L B_W_nor_R<0> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I80<1> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<1> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I80<0> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<0> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XI_FILL4<16> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<15> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<14> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<13> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<12> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XB_INV<6> B_N1<1> B_P1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<5> B_N0<1> B_P0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<4> B_N0<0> B_P0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<3> B_ADDR_COL<1> B_N1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<2> B_ADDR_COL<1> B_N1<0> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<1> B_ADDR_COL<0> B_N0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<0> B_ADDR_COL<0> B_N0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<6> A_N1<1> A_P1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<5> A_N0<1> A_P0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<4> A_N0<0> A_P0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<3> A_ADDR_COL<1> A_N1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<2> A_ADDR_COL<1> A_N1<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_ADDR_COL<0> A_N0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL<0> A_N0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XB_I81<3> B_W_nor_R<1> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<2> B_W_nor_R<1> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<1> B_W_nor_R<0> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<0> B_W_nor_R<0> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<3> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<2> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<1> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XI_FILL8<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XAB_BLMUX<7> A_BLC<31> A_BLC<30> A_BLC<29> A_BLC<28> A_BLC_SEL A_BLT<31> ++ A_BLT<30> A_BLT<29> A_BLT<28> A_BLT_SEL A_PRE_N A_SEL_P<31> A_SEL_P<30> ++ A_SEL_P<29> A_SEL_P<28> A_WR_ONE A_WR_ZERO B_BLC<31> B_BLC<30> B_BLC<29> ++ B_BLC<28> B_BLC_SEL B_BLT<31> B_BLT<30> B_BLT<29> B_BLT<28> B_BLT_SEL ++ B_PRE_N B_SEL_P<31> B_SEL_P<30> B_SEL_P<29> B_SEL_P<28> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_4096x16_c3_2P_BLDRV +XAB_BLMUX<6> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> A_BLC_SEL A_BLT<27> ++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT_SEL A_PRE_N A_SEL_P<27> A_SEL_P<26> ++ A_SEL_P<25> A_SEL_P<24> A_WR_ONE A_WR_ZERO B_BLC<27> B_BLC<26> B_BLC<25> ++ B_BLC<24> B_BLC_SEL B_BLT<27> B_BLT<26> B_BLT<25> B_BLT<24> B_BLT_SEL ++ B_PRE_N B_SEL_P<27> B_SEL_P<26> B_SEL_P<25> B_SEL_P<24> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_4096x16_c3_2P_BLDRV +XAB_BLMUX<5> A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC_SEL A_BLT<23> ++ A_BLT<22> A_BLT<21> A_BLT<20> A_BLT_SEL A_PRE_N A_SEL_P<23> A_SEL_P<22> ++ A_SEL_P<21> A_SEL_P<20> A_WR_ONE A_WR_ZERO B_BLC<23> B_BLC<22> B_BLC<21> ++ B_BLC<20> B_BLC_SEL B_BLT<23> B_BLT<22> B_BLT<21> B_BLT<20> B_BLT_SEL ++ B_PRE_N B_SEL_P<23> B_SEL_P<22> B_SEL_P<21> B_SEL_P<20> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_4096x16_c3_2P_BLDRV +XAB_BLMUX<4> A_BLC<19> A_BLC<18> A_BLC<17> A_BLC<16> A_BLC_SEL A_BLT<19> ++ A_BLT<18> A_BLT<17> A_BLT<16> A_BLT_SEL A_PRE_N A_SEL_P<19> A_SEL_P<18> ++ A_SEL_P<17> A_SEL_P<16> A_WR_ONE A_WR_ZERO B_BLC<19> B_BLC<18> B_BLC<17> ++ B_BLC<16> B_BLC_SEL B_BLT<19> B_BLT<18> B_BLT<17> B_BLT<16> B_BLT_SEL ++ B_PRE_N B_SEL_P<19> B_SEL_P<18> B_SEL_P<17> B_SEL_P<16> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_4096x16_c3_2P_BLDRV +XAB_BLMUX<3> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC_SEL A_BLT<15> ++ A_BLT<14> A_BLT<13> A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<15> A_SEL_P<14> ++ A_SEL_P<13> A_SEL_P<12> A_WR_ONE A_WR_ZERO B_BLC<15> B_BLC<14> B_BLC<13> ++ B_BLC<12> B_BLC_SEL B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT_SEL ++ B_PRE_N B_SEL_P<15> B_SEL_P<14> B_SEL_P<13> B_SEL_P<12> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_4096x16_c3_2P_BLDRV +XAB_BLMUX<2> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC_SEL A_BLT<11> ++ A_BLT<10> A_BLT<9> A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<11> A_SEL_P<10> ++ A_SEL_P<9> A_SEL_P<8> A_WR_ONE A_WR_ZERO B_BLC<11> B_BLC<10> B_BLC<9> ++ B_BLC<8> B_BLC_SEL B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT_SEL B_PRE_N ++ B_SEL_P<11> B_SEL_P<10> B_SEL_P<9> B_SEL_P<8> B_WR_ONE B_WR_ZERO VDD ++ VSS / RM_IHPSG13_4096x16_c3_2P_BLDRV +XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<7> A_SEL_P<6> A_SEL_P<5> ++ A_SEL_P<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC_SEL ++ B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N B_SEL_P<7> B_SEL_P<6> ++ B_SEL_P<5> B_SEL_P<4> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_BLDRV +XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> A_SEL_P<1> ++ A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLC_SEL ++ B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> B_SEL_P<2> ++ B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_BLDRV +XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6 +XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<31> net041<0> B_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<30> net041<1> B_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<29> net041<2> B_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<28> net041<3> B_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<27> net041<4> B_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<26> net041<5> B_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<25> net041<6> B_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<24> net041<7> B_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<23> net041<8> B_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<22> net041<9> B_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<21> net041<10> B_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<20> net041<11> B_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<19> net041<12> B_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<18> net041<13> B_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<17> net041<14> B_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<16> net041<15> B_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<15> net041<16> B_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<14> net041<17> B_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<13> net041<18> B_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<12> net041<19> B_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<11> net041<20> B_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<10> net041<21> B_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<9> net041<22> B_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<8> net041<23> B_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<7> net041<24> B_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<6> net041<25> B_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<5> net041<26> B_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<4> net041<27> B_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<3> net041<28> B_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<2> net041<29> B_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<1> net041<30> B_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<0> net041<31> B_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<31> net23<0> A_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<30> net23<1> A_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<29> net23<2> A_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<28> net23<3> A_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<27> net23<4> A_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<26> net23<5> A_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<25> net23<6> A_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<24> net23<7> A_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<23> net23<8> A_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<22> net23<9> A_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<21> net23<10> A_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<20> net23<11> A_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<19> net23<12> A_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<18> net23<13> A_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<17> net23<14> A_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<16> net23<15> A_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<15> net23<16> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<17> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<18> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<19> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<20> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<21> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<22> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<23> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<24> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<25> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<26> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<27> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<28> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<29> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<30> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<31> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net042 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net043 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net21 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XB_DEC3<31> B_P1<1> B_P0<1> B_ADDR_DEC<7> net041<0> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<30> B_P1<1> B_P0<1> B_ADDR_DEC<6> net041<1> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<29> B_P1<1> B_P0<1> B_ADDR_DEC<5> net041<2> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<28> B_P1<1> B_P0<1> B_ADDR_DEC<4> net041<3> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<27> B_P1<1> B_P0<1> B_ADDR_DEC<3> net041<4> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<26> B_P1<1> B_P0<1> B_ADDR_DEC<2> net041<5> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<25> B_P1<1> B_P0<1> B_ADDR_DEC<1> net041<6> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<24> B_P1<1> B_P0<1> B_ADDR_DEC<0> net041<7> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<23> B_P1<1> B_N0<1> B_ADDR_DEC<7> net041<8> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<22> B_P1<1> B_N0<1> B_ADDR_DEC<6> net041<9> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<21> B_P1<1> B_N0<1> B_ADDR_DEC<5> net041<10> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<20> B_P1<1> B_N0<1> B_ADDR_DEC<4> net041<11> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<19> B_P1<1> B_N0<1> B_ADDR_DEC<3> net041<12> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<18> B_P1<1> B_N0<1> B_ADDR_DEC<2> net041<13> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<17> B_P1<1> B_N0<1> B_ADDR_DEC<1> net041<14> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<16> B_P1<1> B_N0<1> B_ADDR_DEC<0> net041<15> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<15> B_N1<0> B_P0<0> B_ADDR_DEC<7> net041<16> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<14> B_N1<0> B_P0<0> B_ADDR_DEC<6> net041<17> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<13> B_N1<0> B_P0<0> B_ADDR_DEC<5> net041<18> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<12> B_N1<0> B_P0<0> B_ADDR_DEC<4> net041<19> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<11> B_N1<0> B_P0<0> B_ADDR_DEC<3> net041<20> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<10> B_N1<0> B_P0<0> B_ADDR_DEC<2> net041<21> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<9> B_N1<0> B_P0<0> B_ADDR_DEC<1> net041<22> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<8> B_N1<0> B_P0<0> B_ADDR_DEC<0> net041<23> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<7> B_N1<0> B_N0<0> B_ADDR_DEC<7> net041<24> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<6> B_N1<0> B_N0<0> B_ADDR_DEC<6> net041<25> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<5> B_N1<0> B_N0<0> B_ADDR_DEC<5> net041<26> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<4> B_N1<0> B_N0<0> B_ADDR_DEC<4> net041<27> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<3> B_N1<0> B_N0<0> B_ADDR_DEC<3> net041<28> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<2> B_N1<0> B_N0<0> B_ADDR_DEC<2> net041<29> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<1> B_N1<0> B_N0<0> B_ADDR_DEC<1> net041<30> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<0> B_N1<0> B_N0<0> B_ADDR_DEC<0> net041<31> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<31> A_P1<1> A_P0<1> A_ADDR_DEC<7> net23<0> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<30> A_P1<1> A_P0<1> A_ADDR_DEC<6> net23<1> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<29> A_P1<1> A_P0<1> A_ADDR_DEC<5> net23<2> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<28> A_P1<1> A_P0<1> A_ADDR_DEC<4> net23<3> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<27> A_P1<1> A_P0<1> A_ADDR_DEC<3> net23<4> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<26> A_P1<1> A_P0<1> A_ADDR_DEC<2> net23<5> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<25> A_P1<1> A_P0<1> A_ADDR_DEC<1> net23<6> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<24> A_P1<1> A_P0<1> A_ADDR_DEC<0> net23<7> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<23> A_P1<1> A_N0<1> A_ADDR_DEC<7> net23<8> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<22> A_P1<1> A_N0<1> A_ADDR_DEC<6> net23<9> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<21> A_P1<1> A_N0<1> A_ADDR_DEC<5> net23<10> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<20> A_P1<1> A_N0<1> A_ADDR_DEC<4> net23<11> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<19> A_P1<1> A_N0<1> A_ADDR_DEC<3> net23<12> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<18> A_P1<1> A_N0<1> A_ADDR_DEC<2> net23<13> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<17> A_P1<1> A_N0<1> A_ADDR_DEC<1> net23<14> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<16> A_P1<1> A_N0<1> A_ADDR_DEC<0> net23<15> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<15> A_N1<0> A_P0<0> A_ADDR_DEC<7> net23<16> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<14> A_N1<0> A_P0<0> A_ADDR_DEC<6> net23<17> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<13> A_N1<0> A_P0<0> A_ADDR_DEC<5> net23<18> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<12> A_N1<0> A_P0<0> A_ADDR_DEC<4> net23<19> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<11> A_N1<0> A_P0<0> A_ADDR_DEC<3> net23<20> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<10> A_N1<0> A_P0<0> A_ADDR_DEC<2> net23<21> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<9> A_N1<0> A_P0<0> A_ADDR_DEC<1> net23<22> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<8> A_N1<0> A_P0<0> A_ADDR_DEC<0> net23<23> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<7> A_N1<0> A_N0<0> A_ADDR_DEC<7> net23<24> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<6> A_N1<0> A_N0<0> A_ADDR_DEC<6> net23<25> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<5> A_N1<0> A_N0<0> A_ADDR_DEC<5> net23<26> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<4> A_N1<0> A_N0<0> A_ADDR_DEC<4> net23<27> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<3> A_N1<0> A_N0<0> A_ADDR_DEC<3> net23<28> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<2> A_N1<0> A_N0<0> A_ADDR_DEC<2> net23<29> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<1> A_N1<0> A_N0<0> A_ADDR_DEC<1> net23<30> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<0> A_N1<0> A_N0<0> A_ADDR_DEC<0> net23<31> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_2P_COLDRV13_FILL4 VDD VSS +XI0<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RSC_IHPSG13_CBUFX16 A Z VDD VSS +MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=2.115u l=130.00n ng=3 nrd=0 nrs=0 +MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=5.64u l=130.00n ng=8 nrd=0 nrs=0 +MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=13.000u l=130.00n ng=8 nrd=0 ++ nrs=0 +MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=4.89u l=130.00n ng=3 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_1P_COLDRV13X16 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP8 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX16 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=12.96u l=130.00n ng=8 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_1P_WLDRV16X16 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX16 +.ENDS + + +.SUBCKT RM_IHPSG13_4096x16_c3_2P_COLDRV13X4 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1 VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_2P_WLDRV16X4 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX4 +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_2P_ROWDEC8 ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ++ ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<255> ++ WL_O<254> WL_O<253> WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> ++ WL_O<247> WL_O<246> WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> ++ WL_O<240> WL_O<239> WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> ++ WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> ++ WL_O<226> WL_O<225> WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> ++ WL_O<205> WL_O<204> WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> ++ WL_O<198> WL_O<197> WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> ++ WL_O<191> WL_O<190> WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> ++ WL_O<184> WL_O<183> WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> ++ WL_O<177> WL_O<176> WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> ++ WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> ++ WL_O<163> WL_O<162> WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> ++ WL_O<156> WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> ++ WL_O<149> WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> ++ WL_O<142> WL_O<141> WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> ++ WL_O<135> WL_O<134> WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> ++ WL_O<128> WL_O<127> WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> ++ WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> ++ WL_O<114> WL_O<113> WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> ++ WL_O<92> WL_O<91> WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> ++ WL_O<84> WL_O<83> WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> ++ WL_O<76> WL_O<75> WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> ++ WL_O<68> WL_O<67> WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> ++ WL_O<60> WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> ++ WL_O<52> WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> ++ WL_O<44> WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> ++ WL_O<36> WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> ++ WL_O<28> WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> ++ WL_O<20> WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> ++ WL_O<12> WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> ++ WL_O<3> WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC11<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<3> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<15> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<11> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC03 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_4096x16_c3_2P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_4096x16_c3_2P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_4096x16_c3_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_4096x16_c3_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_4096x16_c3_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_4096x16_c3_2P_DEC04 +XDEC10<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<2> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<14> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<10> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC02 +XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC00<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<12> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<8> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC00 +XDEC01<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<13> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<9> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC01 +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_2P_ROWREG8 ACLK_N_I ADDR_I<7> ADDR_I<6> ADDR_I<5> ADDR_I<4> ++ ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<7> ADDR_N_O<6> ADDR_N_O<5> ++ ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<7> ++ BIST_ADDR_I<6> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> ++ BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI10 VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_2P_COLDEC4 ACLK_N ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<3> BIST_ADDR<2> ++ BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int net12<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net12<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net12<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net12<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI14 addr_int ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI15 ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_2P_COLCTRL4 A_ADDR_COL A_ADDR_DEC<7> A_ADDR_DEC<6> ++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<15> A_BLC<14> ++ A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> ++ A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<15> A_BLT<14> ++ A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L ++ A_DCLK_B_R A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L ++ A_RCLK_R A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_COL ++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> ++ B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I ++ B_BIST_EN_I B_BLC<15> B_BLC<14> B_BLC<13> B_BLC<12> B_BLC<11> B_BLC<10> ++ B_BLC<9> B_BLC<8> B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC<3> B_BLC<2> ++ B_BLC<1> B_BLC<0> B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT<11> ++ B_BLT<10> B_BLT<9> B_BLT<8> B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT<3> ++ B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L B_DCLK_B_R B_DCLK_L B_DCLK_R ++ B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L B_RCLK_R B_TIEH_O B_WCLK_B_L ++ B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS +XB_I80 B_RCLK_B_L B_WCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I80 A_RCLK_B_L A_WCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4 +XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4 +XI_FILL4<26> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<25> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<24> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<23> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<22> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<21> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<20> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<19> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<18> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<17> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<16> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<15> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<14> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<13> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<12> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<1> B_N0 B_P0 VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<0> B_ADDR_COL B_N0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_N0 A_P0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL A_N0 VDD VSS / RSC_IHPSG13_CINVX4 +XB_I81<1> net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<0> net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<1> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XAB_BLMUX<3> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC_SEL A_BLT<15> ++ A_BLT<14> A_BLT<13> A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<15> A_SEL_P<14> ++ A_SEL_P<13> A_SEL_P<12> A_WR_ONE A_WR_ZERO B_BLC<15> B_BLC<14> B_BLC<13> ++ B_BLC<12> B_BLC_SEL B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT_SEL ++ B_PRE_N B_SEL_P<15> B_SEL_P<14> B_SEL_P<13> B_SEL_P<12> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_4096x16_c3_2P_BLDRV +XAB_BLMUX<2> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC_SEL A_BLT<11> ++ A_BLT<10> A_BLT<9> A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<11> A_SEL_P<10> ++ A_SEL_P<9> A_SEL_P<8> A_WR_ONE A_WR_ZERO B_BLC<11> B_BLC<10> B_BLC<9> ++ B_BLC<8> B_BLC_SEL B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT_SEL B_PRE_N ++ B_SEL_P<11> B_SEL_P<10> B_SEL_P<9> B_SEL_P<8> B_WR_ONE B_WR_ZERO VDD ++ VSS / RM_IHPSG13_4096x16_c3_2P_BLDRV +XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<7> A_SEL_P<6> A_SEL_P<5> ++ A_SEL_P<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC_SEL ++ B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N B_SEL_P<7> B_SEL_P<6> ++ B_SEL_P<5> B_SEL_P<4> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_BLDRV +XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> A_SEL_P<1> ++ A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLC_SEL ++ B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> B_SEL_P<2> ++ B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_BLDRV +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net046 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net045 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net24 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_DEC3INV<15> net23<0> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<1> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<2> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<3> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<4> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<5> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<6> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<7> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<8> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<9> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<10> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<11> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<12> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<13> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<14> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<15> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<15> net044<0> B_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<14> net044<1> B_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<13> net044<2> B_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<12> net044<3> B_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<11> net044<4> B_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<10> net044<5> B_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<9> net044<6> B_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<8> net044<7> B_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<7> net044<8> B_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<6> net044<9> B_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<5> net044<10> B_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<4> net044<11> B_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<3> net044<12> B_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<2> net044<13> B_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<1> net044<14> B_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<0> net044<15> B_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XI_FILL8<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_DEC3<15> A_P0 A_ADDR_DEC<7> net23<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<14> A_P0 A_ADDR_DEC<6> net23<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<13> A_P0 A_ADDR_DEC<5> net23<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<12> A_P0 A_ADDR_DEC<4> net23<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<11> A_P0 A_ADDR_DEC<3> net23<4> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<10> A_P0 A_ADDR_DEC<2> net23<5> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<9> A_P0 A_ADDR_DEC<1> net23<6> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<8> A_P0 A_ADDR_DEC<0> net23<7> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<7> A_N0 A_ADDR_DEC<7> net23<8> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<6> A_N0 A_ADDR_DEC<6> net23<9> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<5> A_N0 A_ADDR_DEC<5> net23<10> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<4> A_N0 A_ADDR_DEC<4> net23<11> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<3> A_N0 A_ADDR_DEC<3> net23<12> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<2> A_N0 A_ADDR_DEC<2> net23<13> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<1> A_N0 A_ADDR_DEC<1> net23<14> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<0> A_N0 A_ADDR_DEC<0> net23<15> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<15> B_P0 B_ADDR_DEC<7> net044<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<14> B_P0 B_ADDR_DEC<6> net044<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<13> B_P0 B_ADDR_DEC<5> net044<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<12> B_P0 B_ADDR_DEC<4> net044<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<11> B_P0 B_ADDR_DEC<3> net044<4> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<10> B_P0 B_ADDR_DEC<2> net044<5> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<9> B_P0 B_ADDR_DEC<1> net044<6> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<8> B_P0 B_ADDR_DEC<0> net044<7> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<7> B_N0 B_ADDR_DEC<7> net044<8> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<6> B_N0 B_ADDR_DEC<6> net044<9> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<5> B_N0 B_ADDR_DEC<5> net044<10> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<4> B_N0 B_ADDR_DEC<4> net044<11> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<3> B_N0 B_ADDR_DEC<3> net044<12> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<2> B_N0 B_ADDR_DEC<2> net044<13> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<1> B_N0 B_ADDR_DEC<1> net044<14> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<0> B_N0 B_ADDR_DEC<0> net044<15> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS + + +.SUBCKT RM_IHPSG13_4096x16_c3_2P_ROWDEC5 ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ++ ADDR_N_I<0> CS_I ECLK_I WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC00 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_4096x16_c3_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_4096x16_c3_2P_DEC04 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC01 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0 ADDR_N_I<5> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_2P_ROWREG5 ACLK_N_I ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ++ ADDR_I<0> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_4096x16_c3_2P_COLDEC3 ACLK_N ADDR<2> ADDR<1> ADDR<0> ADDR_COL<1> ++ ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ++ ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> ++ BIST_EN_I VDD VSS +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net13<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net13<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net13<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RSC_IHPSG13_DFPQD_MSAFFX2P CP DN DP QN QP VDD VSS +XI_AMP CP DN DP QN QP VDD VSS / RSC_IHPSG13_DFPQD_MSAFFX2 +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_2P_COLCTRL3 A_ADDR_DEC<7> A_ADDR_DEC<6> A_ADDR_DEC<5> ++ A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> A_ADDR_DEC<0> ++ A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> ++ A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> ++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R A_DCLK_L ++ A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R A_TIEH_O ++ A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_DEC<7> B_ADDR_DEC<6> ++ B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> ++ B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I B_BIST_EN_I B_BLC<7> B_BLC<6> B_BLC<5> ++ B_BLC<4> B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<7> B_BLT<6> B_BLT<5> ++ B_BLT<4> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L B_DCLK_B_R ++ B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L B_RCLK_R ++ B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net044 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net043 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2P +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2P +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_ADDR_DEC<7> A_ADDR_DEC<6> ++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> ++ B_BLC<4> B_BLC_SEL B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N ++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_4096x16_c3_2P_BLDRV +XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> ++ B_BLC<0> B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N ++ B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_4096x16_c3_2P_BLDRV +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I80 B_WCLK_B_L B_RCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2 +XB_I76 B_DO_WRITE_P B_DI_N B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XB_I75 B_DO_WRITE_P B_DI_R B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_I80 A_WCLK_B_L A_RCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XB_I81 net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_4096x16_c3_2P_ROWDEC6 ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ++ ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<63> WL_O<62> WL_O<61> WL_O<60> ++ WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> ++ WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> ++ WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> ++ WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> ++ WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> ++ WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> ++ WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> ++ WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC10 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<2> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC02 +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC00 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_4096x16_c3_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_4096x16_c3_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_4096x16_c3_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_4096x16_c3_2P_DEC04 +XDEC11 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<3> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC03 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC01 +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_2P_ROWREG6 ACLK_N_I ADDR_I<5> ADDR_I<4> ADDR_I<3> ADDR_I<2> ++ ADDR_I<1> ADDR_I<0> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ++ ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_4096x16_c3_2P_COLDRV13X16 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XI1<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_2P_WLDRV16X16 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX16 +.ENDS + + +.SUBCKT RM_IHPSG13_4096x16_c3_1P_DEC01 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XDEC NADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XI2 VDD VSS / RSC_IHPSG13_FILLCAP4 +XADDRINV ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_1P_DEC00 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XDEC NADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV<1> ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +XADDRINV<0> ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI1 VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_1P_ROWDEC5 ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ++ ADDR_N_I<0> CS_I ECLK_I WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC01 +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC00 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_4096x16_c3_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_4096x16_c3_1P_DEC04 +XI0 ADDR_N_I<5> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_1P_ROWREG5 ACLK_N_I ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ++ ADDR_I<0> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + + +.SUBCKT RM_IHPSG13_4096x16_c3_1P_COLDEC5 ACLK_N ADDR<4> ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<4> BIST_ADDR<3> ++ BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI13<1> addr_int<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_CBUFX2 +XI13<0> addr_int<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XDFF<4> BIST_EN_I BIST_ADDR<4> ACLK_N ADDR<4> addr_int<1> net7<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int<0> net7<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net7<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net7<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net7<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI15<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI15<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI15<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_1P_COLCTRL5 A_ADDR_COL<1> A_ADDR_COL<0> A_ADDR_DEC<7> ++ A_ADDR_DEC<6> A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<31> ++ A_BLC<30> A_BLC<29> A_BLC<28> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> ++ A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC<19> A_BLC<18> A_BLC<17> ++ A_BLC<16> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> ++ A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> ++ A_BLC<1> A_BLC<0> A_BLT<31> A_BLT<30> A_BLT<29> A_BLT<28> A_BLT<27> ++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT<23> A_BLT<22> A_BLT<21> A_BLT<20> ++ A_BLT<19> A_BLT<18> A_BLT<17> A_BLT<16> A_BLT<15> A_BLT<14> A_BLT<13> ++ A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> ++ A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_I80<1> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<1> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I80<0> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<0> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XI80<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_INV<6> A_N1<1> A_P1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<5> A_N0<1> A_P0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<4> A_N0<0> A_P0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<3> A_ADDR_COL<1> A_N1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<2> A_ADDR_COL<1> A_N1<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_ADDR_COL<0> A_N0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL<0> A_N0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_I81<3> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<2> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<1> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_BLTMUX<31> A_BLC<31> A_BLC_SEL A_BLT<31> A_BLT_SEL A_PRE_N A_SEL_P<31> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV +XA_BLTMUX<30> A_BLC<30> A_BLC_SEL A_BLT<30> A_BLT_SEL A_PRE_N A_SEL_P<30> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV +XA_BLTMUX<29> A_BLC<29> A_BLC_SEL A_BLT<29> A_BLT_SEL A_PRE_N A_SEL_P<29> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV +XA_BLTMUX<28> A_BLC<28> A_BLC_SEL A_BLT<28> A_BLT_SEL A_PRE_N A_SEL_P<28> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV +XA_BLTMUX<27> A_BLC<27> A_BLC_SEL A_BLT<27> A_BLT_SEL A_PRE_N A_SEL_P<27> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV +XA_BLTMUX<26> A_BLC<26> A_BLC_SEL A_BLT<26> A_BLT_SEL A_PRE_N A_SEL_P<26> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV +XA_BLTMUX<25> A_BLC<25> A_BLC_SEL A_BLT<25> A_BLT_SEL A_PRE_N A_SEL_P<25> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV +XA_BLTMUX<24> A_BLC<24> A_BLC_SEL A_BLT<24> A_BLT_SEL A_PRE_N A_SEL_P<24> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV +XA_BLTMUX<23> A_BLC<23> A_BLC_SEL A_BLT<23> A_BLT_SEL A_PRE_N A_SEL_P<23> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV +XA_BLTMUX<22> A_BLC<22> A_BLC_SEL A_BLT<22> A_BLT_SEL A_PRE_N A_SEL_P<22> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV +XA_BLTMUX<21> A_BLC<21> A_BLC_SEL A_BLT<21> A_BLT_SEL A_PRE_N A_SEL_P<21> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV +XA_BLTMUX<20> A_BLC<20> A_BLC_SEL A_BLT<20> A_BLT_SEL A_PRE_N A_SEL_P<20> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV +XA_BLTMUX<19> A_BLC<19> A_BLC_SEL A_BLT<19> A_BLT_SEL A_PRE_N A_SEL_P<19> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV +XA_BLTMUX<18> A_BLC<18> A_BLC_SEL A_BLT<18> A_BLT_SEL A_PRE_N A_SEL_P<18> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV +XA_BLTMUX<17> A_BLC<17> A_BLC_SEL A_BLT<17> A_BLT_SEL A_PRE_N A_SEL_P<17> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV +XA_BLTMUX<16> A_BLC<16> A_BLC_SEL A_BLT<16> A_BLT_SEL A_PRE_N A_SEL_P<16> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV +XA_BLTMUX<15> A_BLC<15> A_BLC_SEL A_BLT<15> A_BLT_SEL A_PRE_N A_SEL_P<15> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV +XA_BLTMUX<14> A_BLC<14> A_BLC_SEL A_BLT<14> A_BLT_SEL A_PRE_N A_SEL_P<14> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV +XA_BLTMUX<13> A_BLC<13> A_BLC_SEL A_BLT<13> A_BLT_SEL A_PRE_N A_SEL_P<13> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV +XA_BLTMUX<12> A_BLC<12> A_BLC_SEL A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<12> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV +XA_BLTMUX<11> A_BLC<11> A_BLC_SEL A_BLT<11> A_BLT_SEL A_PRE_N A_SEL_P<11> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV +XA_BLTMUX<10> A_BLC<10> A_BLC_SEL A_BLT<10> A_BLT_SEL A_PRE_N A_SEL_P<10> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV +XA_BLTMUX<9> A_BLC<9> A_BLC_SEL A_BLT<9> A_BLT_SEL A_PRE_N A_SEL_P<9> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV +XA_BLTMUX<8> A_BLC<8> A_BLC_SEL A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<8> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV +XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_SEL_P<7> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV +XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_SEL_P<6> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV +XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_SEL_P<5> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV +XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<4> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_SEL_P<3> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_SEL_P<2> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_SEL_P<1> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<0> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV +XA_CAPS<17> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<16> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<15> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<14> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<13> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<12> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<31> net23<0> A_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<30> net23<1> A_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<29> net23<2> A_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<28> net23<3> A_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<27> net23<4> A_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<26> net23<5> A_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<25> net23<6> A_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<24> net23<7> A_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<23> net23<8> A_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<22> net23<9> A_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<21> net23<10> A_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<20> net23<11> A_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<19> net23<12> A_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<18> net23<13> A_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<17> net23<14> A_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<16> net23<15> A_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<15> net23<16> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<17> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<18> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<19> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<20> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<21> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<22> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<23> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<24> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<25> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<26> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<27> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<28> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<29> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<30> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<31> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net21 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_DEC3<31> A_P1<1> A_P0<1> A_ADDR_DEC<7> net23<0> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<30> A_P1<1> A_P0<1> A_ADDR_DEC<6> net23<1> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<29> A_P1<1> A_P0<1> A_ADDR_DEC<5> net23<2> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<28> A_P1<1> A_P0<1> A_ADDR_DEC<4> net23<3> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<27> A_P1<1> A_P0<1> A_ADDR_DEC<3> net23<4> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<26> A_P1<1> A_P0<1> A_ADDR_DEC<2> net23<5> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<25> A_P1<1> A_P0<1> A_ADDR_DEC<1> net23<6> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<24> A_P1<1> A_P0<1> A_ADDR_DEC<0> net23<7> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<23> A_P1<1> A_N0<1> A_ADDR_DEC<7> net23<8> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<22> A_P1<1> A_N0<1> A_ADDR_DEC<6> net23<9> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<21> A_P1<1> A_N0<1> A_ADDR_DEC<5> net23<10> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<20> A_P1<1> A_N0<1> A_ADDR_DEC<4> net23<11> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<19> A_P1<1> A_N0<1> A_ADDR_DEC<3> net23<12> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<18> A_P1<1> A_N0<1> A_ADDR_DEC<2> net23<13> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<17> A_P1<1> A_N0<1> A_ADDR_DEC<1> net23<14> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<16> A_P1<1> A_N0<1> A_ADDR_DEC<0> net23<15> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<15> A_N1<0> A_P0<0> A_ADDR_DEC<7> net23<16> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<14> A_N1<0> A_P0<0> A_ADDR_DEC<6> net23<17> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<13> A_N1<0> A_P0<0> A_ADDR_DEC<5> net23<18> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<12> A_N1<0> A_P0<0> A_ADDR_DEC<4> net23<19> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<11> A_N1<0> A_P0<0> A_ADDR_DEC<3> net23<20> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<10> A_N1<0> A_P0<0> A_ADDR_DEC<2> net23<21> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<9> A_N1<0> A_P0<0> A_ADDR_DEC<1> net23<22> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<8> A_N1<0> A_P0<0> A_ADDR_DEC<0> net23<23> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<7> A_N1<0> A_N0<0> A_ADDR_DEC<7> net23<24> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<6> A_N1<0> A_N0<0> A_ADDR_DEC<6> net23<25> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<5> A_N1<0> A_N0<0> A_ADDR_DEC<5> net23<26> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<4> A_N1<0> A_N0<0> A_ADDR_DEC<4> net23<27> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<3> A_N1<0> A_N0<0> A_ADDR_DEC<3> net23<28> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<2> A_N1<0> A_N0<0> A_ADDR_DEC<2> net23<29> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<1> A_N1<0> A_N0<0> A_ADDR_DEC<1> net23<30> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<0> A_N1<0> A_N0<0> A_ADDR_DEC<0> net23<31> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS + +.SUBCKT RM_IHPSG13_4096x16_c3_1P_COLDRV13X12 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP8 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_1P_WLDRV16X12 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX12 +.ENDS + + + +.SUBCKT RM_IHPSG13_4096x16_c3_2P_COLDRV13X8 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX8 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_2P_WLDRV16X8 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX8 +.ENDS + + + +.SUBCKT RM_IHPSG13_4096x16_c3_2P_COLDEC2 ACLK_N ADDR<1> ADDR<0> ADDR_COL<1> ADDR_COL<0> ++ ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ADDR_DEC<2> ++ ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI16<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<3> PADR<0> PADR<1> addr_n<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<2> NADR<0> PADR<1> addr_n<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<1> PADR<0> NADR<1> addr_n<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<0> NADR<0> NADR<1> addr_n<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI17<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI17<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI14<3> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_TIEL +XI14<2> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_TIEL +XI14<1> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_TIEL +XI14<0> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_TIEL +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net12<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net12<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI15<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_2P_COLCTRL2 A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<3> A_BLC<2> A_BLC<1> ++ A_BLC<0> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_DEC<3> B_ADDR_DEC<2> ++ B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I B_BIST_EN_I B_BLC<3> ++ B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I ++ B_DCLK_B_L B_DCLK_B_R B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R ++ B_RCLK_L B_RCLK_R B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD ++ VSS +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net046 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net045 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XB_CAPS VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS VDD VSS / RSC_IHPSG13_FILLCAP4 +XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XB_I80 B_RCLK_B_L B_WCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2 +XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I80 A_RCLK_B_L A_WCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XB_I44 B_WCLK_B_L B_BM_N B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I44 A_WCLK_B_L A_BM_N A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XB_I81 net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XAB_BLMUX A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> ++ B_BLC<0> B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N ++ B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_4096x16_c3_2P_BLDRV +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net039 net040 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I51 net039 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_2P_COLDRV13_FILL4C2 VDD VSS +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_4096x16_c3_2P_ROWDEC7 ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ++ ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<127> WL_O<126> ++ WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> ++ WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> ++ WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> WL_O<105> ++ WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> WL_O<98> WL_O<97> ++ WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> WL_O<90> WL_O<89> ++ WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> WL_O<82> WL_O<81> ++ WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> WL_O<74> WL_O<73> ++ WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> WL_O<66> WL_O<65> ++ WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> WL_O<58> WL_O<57> ++ WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> WL_O<50> WL_O<49> ++ WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> WL_O<42> WL_O<41> ++ WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> WL_O<34> WL_O<33> ++ WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> WL_O<26> WL_O<25> ++ WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> WL_O<18> WL_O<17> ++ WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_4096x16_c3_2P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_4096x16_c3_2P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_4096x16_c3_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_4096x16_c3_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_4096x16_c3_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_4096x16_c3_2P_DEC04 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC03 +XDEC01<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC01 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC02 +XDEC00<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_4096x16_c3_2P_DEC00 +XI0 ADDR_N_I<7> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_2P_ROWREG7 ACLK_N_I ADDR_I<6> ADDR_I<5> ADDR_I<4> ADDR_I<3> ++ ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<6> ++ BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> ++ BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<0> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_4096x16_c3_2P_ROWDEC4 ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> ++ CS_I ECLK_I WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XSEL ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ECLK_H<1> ++ ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> ++ WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> ++ WL_O<0> VDD VSS / RM_IHPSG13_4096x16_c3_2P_DEC04 +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_2P_ROWREG4 ACLK_N_I ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net7<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net7<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net7<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net7<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_4096x16_c3_1P_BITKIT_TAP BLC BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_TAP A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ VDD_CORE VSS +XITAP<1> A_BLC<1> A_BLT<1> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_4096x16_c3_1P_BITKIT_TAP +XITAP<0> A_BLC<0> A_BLT<0> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_4096x16_c3_1P_BITKIT_TAP +XIEDGEBP_COL1<1> BLC<1> BLT<1> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_EDGE_TB +XIEDGEBP_COL1<0> BLC<1> BLT<1> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_EDGE_TB +XIEDGEBP_COL2<1> BLC<0> BLT<0> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_EDGE_TB +XIEDGEBP_COL2<0> BLC<0> BLT<0> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_EDGE_TB +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_TAP_LR VDD_CORE VSS +XCORNER<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x16_c3_1P_BITKIT_CORNER +XCORNER<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x16_c3_1P_BITKIT_CORNER +XTAP_BORDER VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x16_c3_1P_BITKIT_TAP_LR +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_1P_DEC03 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI0 VDD VSS / RSC_IHPSG13_FILLCAP4 +XDEC ADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_1P_DEC02 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XDEC ADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XI2 VDD VSS / RSC_IHPSG13_FILLCAP4 +XADDRINV ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_1P_ROWDEC8 ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ++ ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<255> ++ WL_O<254> WL_O<253> WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> ++ WL_O<247> WL_O<246> WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> ++ WL_O<240> WL_O<239> WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> ++ WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> ++ WL_O<226> WL_O<225> WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> ++ WL_O<205> WL_O<204> WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> ++ WL_O<198> WL_O<197> WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> ++ WL_O<191> WL_O<190> WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> ++ WL_O<184> WL_O<183> WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> ++ WL_O<177> WL_O<176> WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> ++ WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> ++ WL_O<163> WL_O<162> WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> ++ WL_O<156> WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> ++ WL_O<149> WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> ++ WL_O<142> WL_O<141> WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> ++ WL_O<135> WL_O<134> WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> ++ WL_O<128> WL_O<127> WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> ++ WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> ++ WL_O<114> WL_O<113> WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> ++ WL_O<92> WL_O<91> WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> ++ WL_O<84> WL_O<83> WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> ++ WL_O<76> WL_O<75> WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> ++ WL_O<68> WL_O<67> WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> ++ WL_O<60> WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> ++ WL_O<52> WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> ++ WL_O<44> WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> ++ WL_O<36> WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> ++ WL_O<28> WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> ++ WL_O<20> WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> ++ WL_O<12> WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> ++ WL_O<3> WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC11<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<3> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<15> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<11> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC03 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC10<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<2> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<14> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<10> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC02 +XDEC00<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<12> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<8> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC00 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_4096x16_c3_1P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_4096x16_c3_1P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_4096x16_c3_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_4096x16_c3_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_4096x16_c3_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_4096x16_c3_1P_DEC04 +XDEC01<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<13> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<9> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC01 +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_1P_ROWREG8 ACLK_N_I ADDR_I<7> ADDR_I<6> ADDR_I<5> ADDR_I<4> ++ ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<7> ADDR_N_O<6> ADDR_N_O<5> ++ ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<7> ++ BIST_ADDR_I<6> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> ++ BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + +.SUBCKT RM_IHPSG13_4096x16_c3_1P_ROWDEC9 ADDR_N_I<8> ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ++ ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ++ WL_O<511> WL_O<510> WL_O<509> WL_O<508> WL_O<507> WL_O<506> WL_O<505> ++ WL_O<504> WL_O<503> WL_O<502> WL_O<501> WL_O<500> WL_O<499> WL_O<498> ++ WL_O<497> WL_O<496> WL_O<495> WL_O<494> WL_O<493> WL_O<492> WL_O<491> ++ WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> WL_O<484> ++ WL_O<483> WL_O<482> WL_O<481> WL_O<480> WL_O<479> WL_O<478> WL_O<477> ++ WL_O<476> WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> ++ WL_O<469> WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> WL_O<463> ++ WL_O<462> WL_O<461> WL_O<460> WL_O<459> WL_O<458> WL_O<457> WL_O<456> ++ WL_O<455> WL_O<454> WL_O<453> WL_O<452> WL_O<451> WL_O<450> WL_O<449> ++ WL_O<448> WL_O<447> WL_O<446> WL_O<445> WL_O<444> WL_O<443> WL_O<442> ++ WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> WL_O<436> WL_O<435> ++ WL_O<434> WL_O<433> WL_O<432> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> WL_O<415> WL_O<414> ++ WL_O<413> WL_O<412> WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> ++ WL_O<406> WL_O<405> WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> ++ WL_O<399> WL_O<398> WL_O<397> WL_O<396> WL_O<395> WL_O<394> WL_O<393> ++ WL_O<392> WL_O<391> WL_O<390> WL_O<389> WL_O<388> WL_O<387> WL_O<386> ++ WL_O<385> WL_O<384> WL_O<383> WL_O<382> WL_O<381> WL_O<380> WL_O<379> ++ WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> WL_O<372> ++ WL_O<371> WL_O<370> WL_O<369> WL_O<368> WL_O<367> WL_O<366> WL_O<365> ++ WL_O<364> WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> ++ WL_O<357> WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> WL_O<351> ++ WL_O<350> WL_O<349> WL_O<348> WL_O<347> WL_O<346> WL_O<345> WL_O<344> ++ WL_O<343> WL_O<342> WL_O<341> WL_O<340> WL_O<339> WL_O<338> WL_O<337> ++ WL_O<336> WL_O<335> WL_O<334> WL_O<333> WL_O<332> WL_O<331> WL_O<330> ++ WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> WL_O<324> WL_O<323> ++ WL_O<322> WL_O<321> WL_O<320> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> WL_O<303> WL_O<302> ++ WL_O<301> WL_O<300> WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> ++ WL_O<294> WL_O<293> WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> ++ WL_O<287> WL_O<286> WL_O<285> WL_O<284> WL_O<283> WL_O<282> WL_O<281> ++ WL_O<280> WL_O<279> WL_O<278> WL_O<277> WL_O<276> WL_O<275> WL_O<274> ++ WL_O<273> WL_O<272> WL_O<271> WL_O<270> WL_O<269> WL_O<268> WL_O<267> ++ WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> WL_O<260> ++ WL_O<259> WL_O<258> WL_O<257> WL_O<256> WL_O<255> WL_O<254> WL_O<253> ++ WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> ++ WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> WL_O<239> ++ WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> WL_O<233> WL_O<232> ++ WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> WL_O<226> WL_O<225> ++ WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> WL_O<219> WL_O<218> ++ WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> WL_O<212> WL_O<211> ++ WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> WL_O<191> WL_O<190> ++ WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> ++ WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> ++ WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> WL_O<170> WL_O<169> ++ WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> WL_O<163> WL_O<162> ++ WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> WL_O<156> WL_O<155> ++ WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> WL_O<148> ++ WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> WL_O<142> WL_O<141> ++ WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> ++ WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> WL_O<127> ++ WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> ++ WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> ++ WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> ++ WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> ++ WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XL2<172> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<171> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<170> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<169> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<168> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<167> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<166> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<165> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<164> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<163> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<162> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<161> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<160> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<159> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<158> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<157> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<156> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<155> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<154> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<153> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<152> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<151> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<150> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<149> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<148> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<147> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<146> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<145> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<144> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<143> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<142> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<141> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<140> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<139> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<138> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<137> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<136> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<135> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<134> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<133> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC11<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<7> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC03 +XDEC11<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<3> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC03 +XDEC11<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<31> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC03 +XDEC11<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<27> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC03 +XDEC11<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<23> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC03 +XDEC11<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<19> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<15> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<11> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<7> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<3> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC03 +XDEC00<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC00 +XDEC00<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<4> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC00 +XDEC00<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<0> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC00 +XDEC00<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<28> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC00 +XDEC00<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<24> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC00 +XDEC00<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<20> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC00 +XDEC00<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<16> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<12> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<8> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<4> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<0> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC00 +XSEL<31> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<31> ECLK_H<31> ++ ECLK_H<32> ECLK_B<31> ECLK_B<32> WL_O<511> WL_O<510> WL_O<509> WL_O<508> ++ WL_O<507> WL_O<506> WL_O<505> WL_O<504> WL_O<503> WL_O<502> WL_O<501> ++ WL_O<500> WL_O<499> WL_O<498> WL_O<497> WL_O<496> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC04 +XSEL<30> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<30> ECLK_H<30> ++ ECLK_H<31> ECLK_B<30> ECLK_B<31> WL_O<495> WL_O<494> WL_O<493> WL_O<492> ++ WL_O<491> WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> ++ WL_O<484> WL_O<483> WL_O<482> WL_O<481> WL_O<480> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC04 +XSEL<29> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<29> ECLK_H<29> ++ ECLK_H<30> ECLK_B<29> ECLK_B<30> WL_O<479> WL_O<478> WL_O<477> WL_O<476> ++ WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> WL_O<469> ++ WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC04 +XSEL<28> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<28> ECLK_H<28> ++ ECLK_H<29> ECLK_B<28> ECLK_B<29> WL_O<463> WL_O<462> WL_O<461> WL_O<460> ++ WL_O<459> WL_O<458> WL_O<457> WL_O<456> WL_O<455> WL_O<454> WL_O<453> ++ WL_O<452> WL_O<451> WL_O<450> WL_O<449> WL_O<448> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC04 +XSEL<27> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<27> ECLK_H<27> ++ ECLK_H<28> ECLK_B<27> ECLK_B<28> WL_O<447> WL_O<446> WL_O<445> WL_O<444> ++ WL_O<443> WL_O<442> WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> ++ WL_O<436> WL_O<435> WL_O<434> WL_O<433> WL_O<432> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC04 +XSEL<26> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<26> ECLK_H<26> ++ ECLK_H<27> ECLK_B<26> ECLK_B<27> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC04 +XSEL<25> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<25> ECLK_H<25> ++ ECLK_H<26> ECLK_B<25> ECLK_B<26> WL_O<415> WL_O<414> WL_O<413> WL_O<412> ++ WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> WL_O<406> WL_O<405> ++ WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC04 +XSEL<24> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<24> ECLK_H<24> ++ ECLK_H<25> ECLK_B<24> ECLK_B<25> WL_O<399> WL_O<398> WL_O<397> WL_O<396> ++ WL_O<395> WL_O<394> WL_O<393> WL_O<392> WL_O<391> WL_O<390> WL_O<389> ++ WL_O<388> WL_O<387> WL_O<386> WL_O<385> WL_O<384> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC04 +XSEL<23> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<23> ECLK_H<23> ++ ECLK_H<24> ECLK_B<23> ECLK_B<24> WL_O<383> WL_O<382> WL_O<381> WL_O<380> ++ WL_O<379> WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> ++ WL_O<372> WL_O<371> WL_O<370> WL_O<369> WL_O<368> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC04 +XSEL<22> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<22> ECLK_H<22> ++ ECLK_H<23> ECLK_B<22> ECLK_B<23> WL_O<367> WL_O<366> WL_O<365> WL_O<364> ++ WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> WL_O<357> ++ WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC04 +XSEL<21> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<21> ECLK_H<21> ++ ECLK_H<22> ECLK_B<21> ECLK_B<22> WL_O<351> WL_O<350> WL_O<349> WL_O<348> ++ WL_O<347> WL_O<346> WL_O<345> WL_O<344> WL_O<343> WL_O<342> WL_O<341> ++ WL_O<340> WL_O<339> WL_O<338> WL_O<337> WL_O<336> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC04 +XSEL<20> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<20> ECLK_H<20> ++ ECLK_H<21> ECLK_B<20> ECLK_B<21> WL_O<335> WL_O<334> WL_O<333> WL_O<332> ++ WL_O<331> WL_O<330> WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> ++ WL_O<324> WL_O<323> WL_O<322> WL_O<321> WL_O<320> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC04 +XSEL<19> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<19> ECLK_H<19> ++ ECLK_H<20> ECLK_B<19> ECLK_B<20> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC04 +XSEL<18> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<18> ECLK_H<18> ++ ECLK_H<19> ECLK_B<18> ECLK_B<19> WL_O<303> WL_O<302> WL_O<301> WL_O<300> ++ WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> WL_O<294> WL_O<293> ++ WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC04 +XSEL<17> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<17> ECLK_H<17> ++ ECLK_H<18> ECLK_B<17> ECLK_B<18> WL_O<287> WL_O<286> WL_O<285> WL_O<284> ++ WL_O<283> WL_O<282> WL_O<281> WL_O<280> WL_O<279> WL_O<278> WL_O<277> ++ WL_O<276> WL_O<275> WL_O<274> WL_O<273> WL_O<272> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC04 +XSEL<16> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<16> ECLK_H<16> ++ ECLK_H<17> ECLK_B<16> ECLK_B<17> WL_O<271> WL_O<270> WL_O<269> WL_O<268> ++ WL_O<267> WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> ++ WL_O<260> WL_O<259> WL_O<258> WL_O<257> WL_O<256> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC04 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_4096x16_c3_1P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_4096x16_c3_1P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_4096x16_c3_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_4096x16_c3_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_4096x16_c3_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_4096x16_c3_1P_DEC04 +XDEC01<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC01 +XDEC01<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<5> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC01 +XDEC01<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<1> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC01 +XDEC01<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<29> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC01 +XDEC01<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<25> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC01 +XDEC01<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<21> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC01 +XDEC01<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<17> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<13> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<9> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<5> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<1> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC01 +XDEC10<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<6> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC02 +XDEC10<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<2> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC02 +XDEC10<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<30> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC02 +XDEC10<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<26> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC02 +XDEC10<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<22> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC02 +XDEC10<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<18> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<14> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<10> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<6> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<2> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC02 +XI0 ADDR_N_I<9> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_1P_ROWREG9 ACLK_N_I ADDR_I<8> ADDR_I<7> ADDR_I<6> ADDR_I<5> ++ ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<8> ADDR_N_O<7> ++ ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ++ ADDR_N_O<0> BIST_ADDR_I<8> BIST_ADDR_I<7> BIST_ADDR_I<6> BIST_ADDR_I<5> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XINV<8> q_int<8> qn_int<8> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<8> qn_int<8> ADDR_N_O<8> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<8> BIST_EN_I BIST_ADDR_I<8> ACLK_N_I ADDR_I<8> q_int<8> net04<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net04<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net04<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net04<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net04<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net04<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net04<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net04<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net04<8> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +.ENDS + +.SUBCKT RM_IHPSG13_4096x16_c3_1P_ROWDEC7 ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ++ ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<127> WL_O<126> ++ WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> ++ WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> ++ WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> WL_O<105> ++ WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> WL_O<98> WL_O<97> ++ WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> WL_O<90> WL_O<89> ++ WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> WL_O<82> WL_O<81> ++ WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> WL_O<74> WL_O<73> ++ WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> WL_O<66> WL_O<65> ++ WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> WL_O<58> WL_O<57> ++ WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> WL_O<50> WL_O<49> ++ WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> WL_O<42> WL_O<41> ++ WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> WL_O<34> WL_O<33> ++ WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> WL_O<26> WL_O<25> ++ WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> WL_O<18> WL_O<17> ++ WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC03 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC02 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_4096x16_c3_1P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_4096x16_c3_1P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_4096x16_c3_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_4096x16_c3_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_4096x16_c3_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_4096x16_c3_1P_DEC04 +XDEC00<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC00 +XDEC01<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC01 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0 ADDR_N_I<7> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_1P_ROWREG7 ACLK_N_I ADDR_I<6> ADDR_I<5> ADDR_I<4> ADDR_I<3> ++ ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<6> ++ BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> ++ BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + +.SUBCKT RM_IHPSG13_4096x16_c3_1P_COLDRV13X8 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_1P_WLDRV16X8 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX8 +.ENDS + + + +.SUBCKT RM_IHPSG13_4096x16_c3_1P_ROWDEC6 ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ++ ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<63> WL_O<62> WL_O<61> WL_O<60> ++ WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> ++ WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> ++ WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> ++ WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> ++ WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> ++ WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> ++ WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> ++ WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC11 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<3> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC03 +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC00 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC01 +XDEC10 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<2> VDD VSS / ++ RM_IHPSG13_4096x16_c3_1P_DEC02 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_4096x16_c3_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_4096x16_c3_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_4096x16_c3_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_4096x16_c3_1P_DEC04 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_4096x16_c3_1P_ROWREG6 ACLK_N_I ADDR_I<5> ADDR_I<4> ADDR_I<3> ADDR_I<2> ++ ADDR_I<1> ADDR_I<0> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ++ ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + + +.SUBCKT RM_IHPSG13_4096x16_c3_1P_COLUMN_pcell_0 A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<511> A_LWL<510> A_LWL<509> A_LWL<508> A_LWL<507> A_LWL<506> A_LWL<505> A_LWL<504> A_LWL<503> A_LWL<502> A_LWL<501> A_LWL<500> A_LWL<499> A_LWL<498> A_LWL<497> A_LWL<496> A_LWL<495> A_LWL<494> A_LWL<493> A_LWL<492> A_LWL<491> A_LWL<490> A_LWL<489> A_LWL<488> A_LWL<487> A_LWL<486> A_LWL<485> A_LWL<484> A_LWL<483> A_LWL<482> A_LWL<481> A_LWL<480> A_LWL<479> A_LWL<478> A_LWL<477> A_LWL<476> A_LWL<475> A_LWL<474> A_LWL<473> A_LWL<472> A_LWL<471> A_LWL<470> A_LWL<469> A_LWL<468> A_LWL<467> A_LWL<466> A_LWL<465> A_LWL<464> A_LWL<463> A_LWL<462> A_LWL<461> A_LWL<460> A_LWL<459> A_LWL<458> A_LWL<457> A_LWL<456> A_LWL<455> A_LWL<454> A_LWL<453> A_LWL<452> A_LWL<451> A_LWL<450> A_LWL<449> A_LWL<448> A_LWL<447> A_LWL<446> A_LWL<445> A_LWL<444> A_LWL<443> A_LWL<442> A_LWL<441> A_LWL<440> A_LWL<439> A_LWL<438> A_LWL<437> A_LWL<436> A_LWL<435> A_LWL<434> A_LWL<433> A_LWL<432> A_LWL<431> A_LWL<430> A_LWL<429> A_LWL<428> A_LWL<427> A_LWL<426> A_LWL<425> A_LWL<424> A_LWL<423> A_LWL<422> A_LWL<421> A_LWL<420> A_LWL<419> A_LWL<418> A_LWL<417> A_LWL<416> A_LWL<415> A_LWL<414> A_LWL<413> A_LWL<412> A_LWL<411> A_LWL<410> A_LWL<409> A_LWL<408> A_LWL<407> A_LWL<406> A_LWL<405> A_LWL<404> A_LWL<403> A_LWL<402> A_LWL<401> A_LWL<400> A_LWL<399> A_LWL<398> A_LWL<397> A_LWL<396> A_LWL<395> A_LWL<394> A_LWL<393> A_LWL<392> A_LWL<391> A_LWL<390> A_LWL<389> A_LWL<388> A_LWL<387> A_LWL<386> A_LWL<385> A_LWL<384> A_LWL<383> A_LWL<382> A_LWL<381> A_LWL<380> A_LWL<379> A_LWL<378> A_LWL<377> A_LWL<376> A_LWL<375> A_LWL<374> A_LWL<373> A_LWL<372> A_LWL<371> A_LWL<370> A_LWL<369> A_LWL<368> A_LWL<367> A_LWL<366> A_LWL<365> A_LWL<364> A_LWL<363> A_LWL<362> A_LWL<361> A_LWL<360> A_LWL<359> A_LWL<358> A_LWL<357> A_LWL<356> A_LWL<355> A_LWL<354> A_LWL<353> A_LWL<352> A_LWL<351> A_LWL<350> A_LWL<349> A_LWL<348> A_LWL<347> A_LWL<346> A_LWL<345> A_LWL<344> A_LWL<343> A_LWL<342> A_LWL<341> A_LWL<340> A_LWL<339> A_LWL<338> A_LWL<337> A_LWL<336> A_LWL<335> A_LWL<334> A_LWL<333> A_LWL<332> A_LWL<331> A_LWL<330> A_LWL<329> A_LWL<328> A_LWL<327> A_LWL<326> A_LWL<325> A_LWL<324> A_LWL<323> A_LWL<322> A_LWL<321> A_LWL<320> A_LWL<319> A_LWL<318> A_LWL<317> A_LWL<316> A_LWL<315> A_LWL<314> A_LWL<313> A_LWL<312> A_LWL<311> A_LWL<310> A_LWL<309> A_LWL<308> A_LWL<307> A_LWL<306> A_LWL<305> A_LWL<304> A_LWL<303> A_LWL<302> A_LWL<301> A_LWL<300> A_LWL<299> A_LWL<298> A_LWL<297> A_LWL<296> A_LWL<295> A_LWL<294> A_LWL<293> A_LWL<292> A_LWL<291> A_LWL<290> A_LWL<289> A_LWL<288> A_LWL<287> A_LWL<286> A_LWL<285> A_LWL<284> A_LWL<283> A_LWL<282> A_LWL<281> A_LWL<280> A_LWL<279> A_LWL<278> A_LWL<277> A_LWL<276> A_LWL<275> A_LWL<274> A_LWL<273> A_LWL<272> A_LWL<271> A_LWL<270> A_LWL<269> A_LWL<268> A_LWL<267> A_LWL<266> A_LWL<265> A_LWL<264> A_LWL<263> A_LWL<262> A_LWL<261> A_LWL<260> A_LWL<259> A_LWL<258> A_LWL<257> A_LWL<256> A_LWL<255> A_LWL<254> A_LWL<253> A_LWL<252> A_LWL<251> A_LWL<250> A_LWL<249> A_LWL<248> A_LWL<247> A_LWL<246> A_LWL<245> A_LWL<244> A_LWL<243> A_LWL<242> A_LWL<241> A_LWL<240> A_LWL<239> A_LWL<238> A_LWL<237> A_LWL<236> A_LWL<235> A_LWL<234> A_LWL<233> A_LWL<232> A_LWL<231> A_LWL<230> A_LWL<229> A_LWL<228> A_LWL<227> A_LWL<226> A_LWL<225> A_LWL<224> A_LWL<223> A_LWL<222> A_LWL<221> A_LWL<220> A_LWL<219> A_LWL<218> A_LWL<217> A_LWL<216> A_LWL<215> A_LWL<214> A_LWL<213> A_LWL<212> A_LWL<211> A_LWL<210> A_LWL<209> A_LWL<208> A_LWL<207> A_LWL<206> A_LWL<205> A_LWL<204> A_LWL<203> A_LWL<202> A_LWL<201> A_LWL<200> A_LWL<199> A_LWL<198> A_LWL<197> A_LWL<196> A_LWL<195> A_LWL<194> A_LWL<193> A_LWL<192> A_LWL<191> A_LWL<190> A_LWL<189> A_LWL<188> A_LWL<187> A_LWL<186> A_LWL<185> A_LWL<184> A_LWL<183> A_LWL<182> A_LWL<181> A_LWL<180> A_LWL<179> A_LWL<178> A_LWL<177> A_LWL<176> A_LWL<175> A_LWL<174> A_LWL<173> A_LWL<172> A_LWL<171> A_LWL<170> A_LWL<169> A_LWL<168> A_LWL<167> A_LWL<166> A_LWL<165> A_LWL<164> A_LWL<163> A_LWL<162> A_LWL<161> A_LWL<160> A_LWL<159> A_LWL<158> A_LWL<157> A_LWL<156> A_LWL<155> A_LWL<154> A_LWL<153> A_LWL<152> A_LWL<151> A_LWL<150> A_LWL<149> A_LWL<148> A_LWL<147> A_LWL<146> A_LWL<145> A_LWL<144> A_LWL<143> A_LWL<142> A_LWL<141> A_LWL<140> A_LWL<139> A_LWL<138> A_LWL<137> A_LWL<136> A_LWL<135> A_LWL<134> A_LWL<133> A_LWL<132> A_LWL<131> A_LWL<130> A_LWL<129> A_LWL<128> A_LWL<127> A_LWL<126> A_LWL<125> A_LWL<124> A_LWL<123> A_LWL<122> A_LWL<121> A_LWL<120> A_LWL<119> A_LWL<118> A_LWL<117> A_LWL<116> A_LWL<115> A_LWL<114> A_LWL<113> A_LWL<112> A_LWL<111> A_LWL<110> A_LWL<109> A_LWL<108> A_LWL<107> A_LWL<106> A_LWL<105> A_LWL<104> A_LWL<103> A_LWL<102> A_LWL<101> A_LWL<100> A_LWL<99> A_LWL<98> A_LWL<97> A_LWL<96> A_LWL<95> A_LWL<94> A_LWL<93> A_LWL<92> A_LWL<91> A_LWL<90> A_LWL<89> A_LWL<88> A_LWL<87> A_LWL<86> A_LWL<85> A_LWL<84> A_LWL<83> A_LWL<82> A_LWL<81> A_LWL<80> A_LWL<79> A_LWL<78> A_LWL<77> A_LWL<76> A_LWL<75> A_LWL<74> A_LWL<73> A_LWL<72> A_LWL<71> A_LWL<70> A_LWL<69> A_LWL<68> A_LWL<67> A_LWL<66> A_LWL<65> A_LWL<64> A_LWL<63> A_LWL<62> A_LWL<61> A_LWL<60> A_LWL<59> A_LWL<58> A_LWL<57> A_LWL<56> A_LWL<55> A_LWL<54> A_LWL<53> A_LWL<52> A_LWL<51> A_LWL<50> A_LWL<49> A_LWL<48> A_LWL<47> A_LWL<46> A_LWL<45> A_LWL<44> A_LWL<43> A_LWL<42> A_LWL<41> A_LWL<40> A_LWL<39> A_LWL<38> A_LWL<37> A_LWL<36> A_LWL<35> A_LWL<34> A_LWL<33> A_LWL<32> A_LWL<31> A_LWL<30> A_LWL<29> A_LWL<28> A_LWL<27> A_LWL<26> A_LWL<25> A_LWL<24> A_LWL<23> A_LWL<22> A_LWL<21> A_LWL<20> A_LWL<19> A_LWL<18> A_LWL<17> A_LWL<16> A_LWL<15> A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<511> A_RWL<510> A_RWL<509> A_RWL<508> A_RWL<507> A_RWL<506> A_RWL<505> A_RWL<504> A_RWL<503> A_RWL<502> A_RWL<501> A_RWL<500> A_RWL<499> A_RWL<498> A_RWL<497> A_RWL<496> A_RWL<495> A_RWL<494> A_RWL<493> A_RWL<492> A_RWL<491> A_RWL<490> A_RWL<489> A_RWL<488> A_RWL<487> A_RWL<486> A_RWL<485> A_RWL<484> A_RWL<483> A_RWL<482> A_RWL<481> A_RWL<480> A_RWL<479> A_RWL<478> A_RWL<477> A_RWL<476> A_RWL<475> A_RWL<474> A_RWL<473> A_RWL<472> A_RWL<471> A_RWL<470> A_RWL<469> A_RWL<468> A_RWL<467> A_RWL<466> A_RWL<465> A_RWL<464> A_RWL<463> A_RWL<462> A_RWL<461> A_RWL<460> A_RWL<459> A_RWL<458> A_RWL<457> A_RWL<456> A_RWL<455> A_RWL<454> A_RWL<453> A_RWL<452> A_RWL<451> A_RWL<450> A_RWL<449> A_RWL<448> A_RWL<447> A_RWL<446> A_RWL<445> A_RWL<444> A_RWL<443> A_RWL<442> A_RWL<441> A_RWL<440> A_RWL<439> A_RWL<438> A_RWL<437> A_RWL<436> A_RWL<435> A_RWL<434> A_RWL<433> A_RWL<432> A_RWL<431> A_RWL<430> A_RWL<429> A_RWL<428> A_RWL<427> A_RWL<426> A_RWL<425> A_RWL<424> A_RWL<423> A_RWL<422> A_RWL<421> A_RWL<420> A_RWL<419> A_RWL<418> A_RWL<417> A_RWL<416> A_RWL<415> A_RWL<414> A_RWL<413> A_RWL<412> A_RWL<411> A_RWL<410> A_RWL<409> A_RWL<408> A_RWL<407> A_RWL<406> A_RWL<405> A_RWL<404> A_RWL<403> A_RWL<402> A_RWL<401> A_RWL<400> A_RWL<399> A_RWL<398> A_RWL<397> A_RWL<396> A_RWL<395> A_RWL<394> A_RWL<393> A_RWL<392> A_RWL<391> A_RWL<390> A_RWL<389> A_RWL<388> A_RWL<387> A_RWL<386> A_RWL<385> A_RWL<384> A_RWL<383> A_RWL<382> A_RWL<381> A_RWL<380> A_RWL<379> A_RWL<378> A_RWL<377> A_RWL<376> A_RWL<375> A_RWL<374> A_RWL<373> A_RWL<372> A_RWL<371> A_RWL<370> A_RWL<369> A_RWL<368> A_RWL<367> A_RWL<366> A_RWL<365> A_RWL<364> A_RWL<363> A_RWL<362> A_RWL<361> A_RWL<360> A_RWL<359> A_RWL<358> A_RWL<357> A_RWL<356> A_RWL<355> A_RWL<354> A_RWL<353> A_RWL<352> A_RWL<351> A_RWL<350> A_RWL<349> A_RWL<348> A_RWL<347> A_RWL<346> A_RWL<345> A_RWL<344> A_RWL<343> A_RWL<342> A_RWL<341> A_RWL<340> A_RWL<339> A_RWL<338> A_RWL<337> A_RWL<336> A_RWL<335> A_RWL<334> A_RWL<333> A_RWL<332> A_RWL<331> A_RWL<330> A_RWL<329> A_RWL<328> A_RWL<327> A_RWL<326> A_RWL<325> A_RWL<324> A_RWL<323> A_RWL<322> A_RWL<321> A_RWL<320> A_RWL<319> A_RWL<318> A_RWL<317> A_RWL<316> A_RWL<315> A_RWL<314> A_RWL<313> A_RWL<312> A_RWL<311> A_RWL<310> A_RWL<309> A_RWL<308> A_RWL<307> A_RWL<306> A_RWL<305> A_RWL<304> A_RWL<303> A_RWL<302> A_RWL<301> A_RWL<300> A_RWL<299> A_RWL<298> A_RWL<297> A_RWL<296> A_RWL<295> A_RWL<294> A_RWL<293> A_RWL<292> A_RWL<291> A_RWL<290> A_RWL<289> A_RWL<288> A_RWL<287> A_RWL<286> A_RWL<285> A_RWL<284> A_RWL<283> A_RWL<282> A_RWL<281> A_RWL<280> A_RWL<279> A_RWL<278> A_RWL<277> A_RWL<276> A_RWL<275> A_RWL<274> A_RWL<273> A_RWL<272> A_RWL<271> A_RWL<270> A_RWL<269> A_RWL<268> A_RWL<267> A_RWL<266> A_RWL<265> A_RWL<264> A_RWL<263> A_RWL<262> A_RWL<261> A_RWL<260> A_RWL<259> A_RWL<258> A_RWL<257> A_RWL<256> A_RWL<255> A_RWL<254> A_RWL<253> A_RWL<252> A_RWL<251> A_RWL<250> A_RWL<249> A_RWL<248> A_RWL<247> A_RWL<246> A_RWL<245> A_RWL<244> A_RWL<243> A_RWL<242> A_RWL<241> A_RWL<240> A_RWL<239> A_RWL<238> A_RWL<237> A_RWL<236> A_RWL<235> A_RWL<234> A_RWL<233> A_RWL<232> A_RWL<231> A_RWL<230> A_RWL<229> A_RWL<228> A_RWL<227> A_RWL<226> A_RWL<225> A_RWL<224> A_RWL<223> A_RWL<222> A_RWL<221> A_RWL<220> A_RWL<219> A_RWL<218> A_RWL<217> A_RWL<216> A_RWL<215> A_RWL<214> A_RWL<213> A_RWL<212> A_RWL<211> A_RWL<210> A_RWL<209> A_RWL<208> A_RWL<207> A_RWL<206> A_RWL<205> A_RWL<204> A_RWL<203> A_RWL<202> A_RWL<201> A_RWL<200> A_RWL<199> A_RWL<198> A_RWL<197> A_RWL<196> A_RWL<195> A_RWL<194> A_RWL<193> A_RWL<192> A_RWL<191> A_RWL<190> A_RWL<189> A_RWL<188> A_RWL<187> A_RWL<186> A_RWL<185> A_RWL<184> A_RWL<183> A_RWL<182> A_RWL<181> A_RWL<180> A_RWL<179> A_RWL<178> A_RWL<177> A_RWL<176> A_RWL<175> A_RWL<174> A_RWL<173> A_RWL<172> A_RWL<171> A_RWL<170> A_RWL<169> A_RWL<168> A_RWL<167> A_RWL<166> A_RWL<165> A_RWL<164> A_RWL<163> A_RWL<162> A_RWL<161> A_RWL<160> A_RWL<159> A_RWL<158> A_RWL<157> A_RWL<156> A_RWL<155> A_RWL<154> A_RWL<153> A_RWL<152> A_RWL<151> A_RWL<150> A_RWL<149> A_RWL<148> A_RWL<147> A_RWL<146> A_RWL<145> A_RWL<144> A_RWL<143> A_RWL<142> A_RWL<141> A_RWL<140> A_RWL<139> A_RWL<138> A_RWL<137> A_RWL<136> A_RWL<135> A_RWL<134> A_RWL<133> A_RWL<132> A_RWL<131> A_RWL<130> A_RWL<129> A_RWL<128> A_RWL<127> A_RWL<126> A_RWL<125> A_RWL<124> A_RWL<123> A_RWL<122> A_RWL<121> A_RWL<120> A_RWL<119> A_RWL<118> A_RWL<117> A_RWL<116> A_RWL<115> A_RWL<114> A_RWL<113> A_RWL<112> A_RWL<111> A_RWL<110> A_RWL<109> A_RWL<108> A_RWL<107> A_RWL<106> A_RWL<105> A_RWL<104> A_RWL<103> A_RWL<102> A_RWL<101> A_RWL<100> A_RWL<99> A_RWL<98> A_RWL<97> A_RWL<96> A_RWL<95> A_RWL<94> A_RWL<93> A_RWL<92> A_RWL<91> A_RWL<90> A_RWL<89> A_RWL<88> A_RWL<87> A_RWL<86> A_RWL<85> A_RWL<84> A_RWL<83> A_RWL<82> A_RWL<81> A_RWL<80> A_RWL<79> A_RWL<78> A_RWL<77> A_RWL<76> A_RWL<75> A_RWL<74> A_RWL<73> A_RWL<72> A_RWL<71> A_RWL<70> A_RWL<69> A_RWL<68> A_RWL<67> A_RWL<66> A_RWL<65> A_RWL<64> A_RWL<63> A_RWL<62> A_RWL<61> A_RWL<60> A_RWL<59> A_RWL<58> A_RWL<57> A_RWL<56> A_RWL<55> A_RWL<54> A_RWL<53> A_RWL<52> A_RWL<51> A_RWL<50> A_RWL<49> A_RWL<48> A_RWL<47> A_RWL<46> A_RWL<45> A_RWL<44> A_RWL<43> A_RWL<42> A_RWL<41> A_RWL<40> A_RWL<39> A_RWL<38> A_RWL<37> A_RWL<36> A_RWL<35> A_RWL<34> A_RWL<33> A_RWL<32> A_RWL<31> A_RWL<30> A_RWL<29> A_RWL<28> A_RWL<27> A_RWL<26> A_RWL<25> A_RWL<24> A_RWL<23> A_RWL<22> A_RWL<21> A_RWL<20> A_RWL<19> A_RWL<18> A_RWL<17> A_RWL<16> A_RWL<15> A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> VDD_CORE VSS +XRAM<32> A_BLC<61> A_BLC<60> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT<61> A_BLT<60> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<511> A_LWL<510> A_LWL<509> A_LWL<508> A_LWL<507> A_LWL<506> A_LWL<505> A_LWL<504> A_LWL<503> A_LWL<502> A_LWL<501> A_LWL<500> A_LWL<499> A_LWL<498> A_LWL<497> A_LWL<496> A_RWL<511> A_RWL<510> A_RWL<509> A_RWL<508> A_RWL<507> A_RWL<506> A_RWL<505> A_RWL<504> A_RWL<503> A_RWL<502> A_RWL<501> A_RWL<500> A_RWL<499> A_RWL<498> A_RWL<497> A_RWL<496> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_SRAM +XRAM<31> A_BLC<59> A_BLC<58> A_BLC<61> A_BLC<60> A_BLT<59> A_BLT<58> A_BLT<61> A_BLT<60> A_LWL<495> A_LWL<494> A_LWL<493> A_LWL<492> A_LWL<491> A_LWL<490> A_LWL<489> A_LWL<488> A_LWL<487> A_LWL<486> A_LWL<485> A_LWL<484> A_LWL<483> A_LWL<482> A_LWL<481> A_LWL<480> A_RWL<495> A_RWL<494> A_RWL<493> A_RWL<492> A_RWL<491> A_RWL<490> A_RWL<489> A_RWL<488> A_RWL<487> A_RWL<486> A_RWL<485> A_RWL<484> A_RWL<483> A_RWL<482> A_RWL<481> A_RWL<480> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_SRAM +XRAM<30> A_BLC<57> A_BLC<56> A_BLC<59> A_BLC<58> A_BLT<57> A_BLT<56> A_BLT<59> A_BLT<58> A_LWL<479> A_LWL<478> A_LWL<477> A_LWL<476> A_LWL<475> A_LWL<474> A_LWL<473> A_LWL<472> A_LWL<471> A_LWL<470> A_LWL<469> A_LWL<468> A_LWL<467> A_LWL<466> A_LWL<465> A_LWL<464> A_RWL<479> A_RWL<478> A_RWL<477> A_RWL<476> A_RWL<475> A_RWL<474> A_RWL<473> A_RWL<472> A_RWL<471> A_RWL<470> A_RWL<469> A_RWL<468> A_RWL<467> A_RWL<466> A_RWL<465> A_RWL<464> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_SRAM +XRAM<29> A_BLC<55> A_BLC<54> A_BLC<57> A_BLC<56> A_BLT<55> A_BLT<54> A_BLT<57> A_BLT<56> A_LWL<463> A_LWL<462> A_LWL<461> A_LWL<460> A_LWL<459> A_LWL<458> A_LWL<457> A_LWL<456> A_LWL<455> A_LWL<454> A_LWL<453> A_LWL<452> A_LWL<451> A_LWL<450> A_LWL<449> A_LWL<448> A_RWL<463> A_RWL<462> A_RWL<461> A_RWL<460> A_RWL<459> A_RWL<458> A_RWL<457> A_RWL<456> A_RWL<455> A_RWL<454> A_RWL<453> A_RWL<452> A_RWL<451> A_RWL<450> A_RWL<449> A_RWL<448> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_SRAM +XRAM<28> A_BLC<53> A_BLC<52> A_BLC<55> A_BLC<54> A_BLT<53> A_BLT<52> A_BLT<55> A_BLT<54> A_LWL<447> A_LWL<446> A_LWL<445> A_LWL<444> A_LWL<443> A_LWL<442> A_LWL<441> A_LWL<440> A_LWL<439> A_LWL<438> A_LWL<437> A_LWL<436> A_LWL<435> A_LWL<434> A_LWL<433> A_LWL<432> A_RWL<447> A_RWL<446> A_RWL<445> A_RWL<444> A_RWL<443> A_RWL<442> A_RWL<441> A_RWL<440> A_RWL<439> A_RWL<438> A_RWL<437> A_RWL<436> A_RWL<435> A_RWL<434> A_RWL<433> A_RWL<432> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_SRAM +XRAM<27> A_BLC<51> A_BLC<50> A_BLC<53> A_BLC<52> A_BLT<51> A_BLT<50> A_BLT<53> A_BLT<52> A_LWL<431> A_LWL<430> A_LWL<429> A_LWL<428> A_LWL<427> A_LWL<426> A_LWL<425> A_LWL<424> A_LWL<423> A_LWL<422> A_LWL<421> A_LWL<420> A_LWL<419> A_LWL<418> A_LWL<417> A_LWL<416> A_RWL<431> A_RWL<430> A_RWL<429> A_RWL<428> A_RWL<427> A_RWL<426> A_RWL<425> A_RWL<424> A_RWL<423> A_RWL<422> A_RWL<421> A_RWL<420> A_RWL<419> A_RWL<418> A_RWL<417> A_RWL<416> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_SRAM +XRAM<26> A_BLC<49> A_BLC<48> A_BLC<51> A_BLC<50> A_BLT<49> A_BLT<48> A_BLT<51> A_BLT<50> A_LWL<415> A_LWL<414> A_LWL<413> A_LWL<412> A_LWL<411> A_LWL<410> A_LWL<409> A_LWL<408> A_LWL<407> A_LWL<406> A_LWL<405> A_LWL<404> A_LWL<403> A_LWL<402> A_LWL<401> A_LWL<400> A_RWL<415> A_RWL<414> A_RWL<413> A_RWL<412> A_RWL<411> A_RWL<410> A_RWL<409> A_RWL<408> A_RWL<407> A_RWL<406> A_RWL<405> A_RWL<404> A_RWL<403> A_RWL<402> A_RWL<401> A_RWL<400> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_SRAM +XRAM<25> A_BLC<47> A_BLC<46> A_BLC<49> A_BLC<48> A_BLT<47> A_BLT<46> A_BLT<49> A_BLT<48> A_LWL<399> A_LWL<398> A_LWL<397> A_LWL<396> A_LWL<395> A_LWL<394> A_LWL<393> A_LWL<392> A_LWL<391> A_LWL<390> A_LWL<389> A_LWL<388> A_LWL<387> A_LWL<386> A_LWL<385> A_LWL<384> A_RWL<399> A_RWL<398> A_RWL<397> A_RWL<396> A_RWL<395> A_RWL<394> A_RWL<393> A_RWL<392> A_RWL<391> A_RWL<390> A_RWL<389> A_RWL<388> A_RWL<387> A_RWL<386> A_RWL<385> A_RWL<384> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_SRAM +XRAM<24> A_BLC<45> A_BLC<44> A_BLC<47> A_BLC<46> A_BLT<45> A_BLT<44> A_BLT<47> A_BLT<46> A_LWL<383> A_LWL<382> A_LWL<381> A_LWL<380> A_LWL<379> A_LWL<378> A_LWL<377> A_LWL<376> A_LWL<375> A_LWL<374> A_LWL<373> A_LWL<372> A_LWL<371> A_LWL<370> A_LWL<369> A_LWL<368> A_RWL<383> A_RWL<382> A_RWL<381> A_RWL<380> A_RWL<379> A_RWL<378> A_RWL<377> A_RWL<376> A_RWL<375> A_RWL<374> A_RWL<373> A_RWL<372> A_RWL<371> A_RWL<370> A_RWL<369> A_RWL<368> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_SRAM +XRAM<23> A_BLC<43> A_BLC<42> A_BLC<45> A_BLC<44> A_BLT<43> A_BLT<42> A_BLT<45> A_BLT<44> A_LWL<367> A_LWL<366> A_LWL<365> A_LWL<364> A_LWL<363> A_LWL<362> A_LWL<361> A_LWL<360> A_LWL<359> A_LWL<358> A_LWL<357> A_LWL<356> A_LWL<355> A_LWL<354> A_LWL<353> A_LWL<352> A_RWL<367> A_RWL<366> A_RWL<365> A_RWL<364> A_RWL<363> A_RWL<362> A_RWL<361> A_RWL<360> A_RWL<359> A_RWL<358> A_RWL<357> A_RWL<356> A_RWL<355> A_RWL<354> A_RWL<353> A_RWL<352> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_SRAM +XRAM<22> A_BLC<41> A_BLC<40> A_BLC<43> A_BLC<42> A_BLT<41> A_BLT<40> A_BLT<43> A_BLT<42> A_LWL<351> A_LWL<350> A_LWL<349> A_LWL<348> A_LWL<347> A_LWL<346> A_LWL<345> A_LWL<344> A_LWL<343> A_LWL<342> A_LWL<341> A_LWL<340> A_LWL<339> A_LWL<338> A_LWL<337> A_LWL<336> A_RWL<351> A_RWL<350> A_RWL<349> A_RWL<348> A_RWL<347> A_RWL<346> A_RWL<345> A_RWL<344> A_RWL<343> A_RWL<342> A_RWL<341> A_RWL<340> A_RWL<339> A_RWL<338> A_RWL<337> A_RWL<336> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_SRAM +XRAM<21> A_BLC<39> A_BLC<38> A_BLC<41> A_BLC<40> A_BLT<39> A_BLT<38> A_BLT<41> A_BLT<40> A_LWL<335> A_LWL<334> A_LWL<333> A_LWL<332> A_LWL<331> A_LWL<330> A_LWL<329> A_LWL<328> A_LWL<327> A_LWL<326> A_LWL<325> A_LWL<324> A_LWL<323> A_LWL<322> A_LWL<321> A_LWL<320> A_RWL<335> A_RWL<334> A_RWL<333> A_RWL<332> A_RWL<331> A_RWL<330> A_RWL<329> A_RWL<328> A_RWL<327> A_RWL<326> A_RWL<325> A_RWL<324> A_RWL<323> A_RWL<322> A_RWL<321> A_RWL<320> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_SRAM +XRAM<20> A_BLC<37> A_BLC<36> A_BLC<39> A_BLC<38> A_BLT<37> A_BLT<36> A_BLT<39> A_BLT<38> A_LWL<319> A_LWL<318> A_LWL<317> A_LWL<316> A_LWL<315> A_LWL<314> A_LWL<313> A_LWL<312> A_LWL<311> A_LWL<310> A_LWL<309> A_LWL<308> A_LWL<307> A_LWL<306> A_LWL<305> A_LWL<304> A_RWL<319> A_RWL<318> A_RWL<317> A_RWL<316> A_RWL<315> A_RWL<314> A_RWL<313> A_RWL<312> A_RWL<311> A_RWL<310> A_RWL<309> A_RWL<308> A_RWL<307> A_RWL<306> A_RWL<305> A_RWL<304> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_SRAM +XRAM<19> A_BLC<35> A_BLC<34> A_BLC<37> A_BLC<36> A_BLT<35> A_BLT<34> A_BLT<37> A_BLT<36> A_LWL<303> A_LWL<302> A_LWL<301> A_LWL<300> A_LWL<299> A_LWL<298> A_LWL<297> A_LWL<296> A_LWL<295> A_LWL<294> A_LWL<293> A_LWL<292> A_LWL<291> A_LWL<290> A_LWL<289> A_LWL<288> A_RWL<303> A_RWL<302> A_RWL<301> A_RWL<300> A_RWL<299> A_RWL<298> A_RWL<297> A_RWL<296> A_RWL<295> A_RWL<294> A_RWL<293> A_RWL<292> A_RWL<291> A_RWL<290> A_RWL<289> A_RWL<288> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_SRAM +XRAM<18> A_BLC<33> A_BLC<32> A_BLC<35> A_BLC<34> A_BLT<33> A_BLT<32> A_BLT<35> A_BLT<34> A_LWL<287> A_LWL<286> A_LWL<285> A_LWL<284> A_LWL<283> A_LWL<282> A_LWL<281> A_LWL<280> A_LWL<279> A_LWL<278> A_LWL<277> A_LWL<276> A_LWL<275> A_LWL<274> A_LWL<273> A_LWL<272> A_RWL<287> A_RWL<286> A_RWL<285> A_RWL<284> A_RWL<283> A_RWL<282> A_RWL<281> A_RWL<280> A_RWL<279> A_RWL<278> A_RWL<277> A_RWL<276> A_RWL<275> A_RWL<274> A_RWL<273> A_RWL<272> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_SRAM +XRAM<17> A_BLC<31> A_BLC<30> A_BLC<33> A_BLC<32> A_BLT<31> A_BLT<30> A_BLT<33> A_BLT<32> A_LWL<271> A_LWL<270> A_LWL<269> A_LWL<268> A_LWL<267> A_LWL<266> A_LWL<265> A_LWL<264> A_LWL<263> A_LWL<262> A_LWL<261> A_LWL<260> A_LWL<259> A_LWL<258> A_LWL<257> A_LWL<256> A_RWL<271> A_RWL<270> A_RWL<269> A_RWL<268> A_RWL<267> A_RWL<266> A_RWL<265> A_RWL<264> A_RWL<263> A_RWL<262> A_RWL<261> A_RWL<260> A_RWL<259> A_RWL<258> A_RWL<257> A_RWL<256> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_SRAM +XRAM<16> A_BLC<29> A_BLC<28> A_BLC<31> A_BLC<30> A_BLT<29> A_BLT<28> A_BLT<31> A_BLT<30> A_LWL<255> A_LWL<254> A_LWL<253> A_LWL<252> A_LWL<251> A_LWL<250> A_LWL<249> A_LWL<248> A_LWL<247> A_LWL<246> A_LWL<245> A_LWL<244> A_LWL<243> A_LWL<242> A_LWL<241> A_LWL<240> A_RWL<255> A_RWL<254> A_RWL<253> A_RWL<252> A_RWL<251> A_RWL<250> A_RWL<249> A_RWL<248> A_RWL<247> A_RWL<246> A_RWL<245> A_RWL<244> A_RWL<243> A_RWL<242> A_RWL<241> A_RWL<240> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_SRAM +XRAM<15> A_BLC<27> A_BLC<26> A_BLC<29> A_BLC<28> A_BLT<27> A_BLT<26> A_BLT<29> A_BLT<28> A_LWL<239> A_LWL<238> A_LWL<237> A_LWL<236> A_LWL<235> A_LWL<234> A_LWL<233> A_LWL<232> A_LWL<231> A_LWL<230> A_LWL<229> A_LWL<228> A_LWL<227> A_LWL<226> A_LWL<225> A_LWL<224> A_RWL<239> A_RWL<238> A_RWL<237> A_RWL<236> A_RWL<235> A_RWL<234> A_RWL<233> A_RWL<232> A_RWL<231> A_RWL<230> A_RWL<229> A_RWL<228> A_RWL<227> A_RWL<226> A_RWL<225> A_RWL<224> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_SRAM +XRAM<14> A_BLC<25> A_BLC<24> A_BLC<27> A_BLC<26> A_BLT<25> A_BLT<24> A_BLT<27> A_BLT<26> A_LWL<223> A_LWL<222> A_LWL<221> A_LWL<220> A_LWL<219> A_LWL<218> A_LWL<217> A_LWL<216> A_LWL<215> A_LWL<214> A_LWL<213> A_LWL<212> A_LWL<211> A_LWL<210> A_LWL<209> A_LWL<208> A_RWL<223> A_RWL<222> A_RWL<221> A_RWL<220> A_RWL<219> A_RWL<218> A_RWL<217> A_RWL<216> A_RWL<215> A_RWL<214> A_RWL<213> A_RWL<212> A_RWL<211> A_RWL<210> A_RWL<209> A_RWL<208> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_SRAM +XRAM<13> A_BLC<23> A_BLC<22> A_BLC<25> A_BLC<24> A_BLT<23> A_BLT<22> A_BLT<25> A_BLT<24> A_LWL<207> A_LWL<206> A_LWL<205> A_LWL<204> A_LWL<203> A_LWL<202> A_LWL<201> A_LWL<200> A_LWL<199> A_LWL<198> A_LWL<197> A_LWL<196> A_LWL<195> A_LWL<194> A_LWL<193> A_LWL<192> A_RWL<207> A_RWL<206> A_RWL<205> A_RWL<204> A_RWL<203> A_RWL<202> A_RWL<201> A_RWL<200> A_RWL<199> A_RWL<198> A_RWL<197> A_RWL<196> A_RWL<195> A_RWL<194> A_RWL<193> A_RWL<192> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_SRAM +XRAM<12> A_BLC<21> A_BLC<20> A_BLC<23> A_BLC<22> A_BLT<21> A_BLT<20> A_BLT<23> A_BLT<22> A_LWL<191> A_LWL<190> A_LWL<189> A_LWL<188> A_LWL<187> A_LWL<186> A_LWL<185> A_LWL<184> A_LWL<183> A_LWL<182> A_LWL<181> A_LWL<180> A_LWL<179> A_LWL<178> A_LWL<177> A_LWL<176> A_RWL<191> A_RWL<190> A_RWL<189> A_RWL<188> A_RWL<187> A_RWL<186> A_RWL<185> A_RWL<184> A_RWL<183> A_RWL<182> A_RWL<181> A_RWL<180> A_RWL<179> A_RWL<178> A_RWL<177> A_RWL<176> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_SRAM +XRAM<11> A_BLC<19> A_BLC<18> A_BLC<21> A_BLC<20> A_BLT<19> A_BLT<18> A_BLT<21> A_BLT<20> A_LWL<175> A_LWL<174> A_LWL<173> A_LWL<172> A_LWL<171> A_LWL<170> A_LWL<169> A_LWL<168> A_LWL<167> A_LWL<166> A_LWL<165> A_LWL<164> A_LWL<163> A_LWL<162> A_LWL<161> A_LWL<160> A_RWL<175> A_RWL<174> A_RWL<173> A_RWL<172> A_RWL<171> A_RWL<170> A_RWL<169> A_RWL<168> A_RWL<167> A_RWL<166> A_RWL<165> A_RWL<164> A_RWL<163> A_RWL<162> A_RWL<161> A_RWL<160> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_SRAM +XRAM<10> A_BLC<17> A_BLC<16> A_BLC<19> A_BLC<18> A_BLT<17> A_BLT<16> A_BLT<19> A_BLT<18> A_LWL<159> A_LWL<158> A_LWL<157> A_LWL<156> A_LWL<155> A_LWL<154> A_LWL<153> A_LWL<152> A_LWL<151> A_LWL<150> A_LWL<149> A_LWL<148> A_LWL<147> A_LWL<146> A_LWL<145> A_LWL<144> A_RWL<159> A_RWL<158> A_RWL<157> A_RWL<156> A_RWL<155> A_RWL<154> A_RWL<153> A_RWL<152> A_RWL<151> A_RWL<150> A_RWL<149> A_RWL<148> A_RWL<147> A_RWL<146> A_RWL<145> A_RWL<144> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_SRAM +XRAM<9> A_BLC<15> A_BLC<14> A_BLC<17> A_BLC<16> A_BLT<15> A_BLT<14> A_BLT<17> A_BLT<16> A_LWL<143> A_LWL<142> A_LWL<141> A_LWL<140> A_LWL<139> A_LWL<138> A_LWL<137> A_LWL<136> A_LWL<135> A_LWL<134> A_LWL<133> A_LWL<132> A_LWL<131> A_LWL<130> A_LWL<129> A_LWL<128> A_RWL<143> A_RWL<142> A_RWL<141> A_RWL<140> A_RWL<139> A_RWL<138> A_RWL<137> A_RWL<136> A_RWL<135> A_RWL<134> A_RWL<133> A_RWL<132> A_RWL<131> A_RWL<130> A_RWL<129> A_RWL<128> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_SRAM +XRAM<8> A_BLC<13> A_BLC<12> A_BLC<15> A_BLC<14> A_BLT<13> A_BLT<12> A_BLT<15> A_BLT<14> A_LWL<127> A_LWL<126> A_LWL<125> A_LWL<124> A_LWL<123> A_LWL<122> A_LWL<121> A_LWL<120> A_LWL<119> A_LWL<118> A_LWL<117> A_LWL<116> A_LWL<115> A_LWL<114> A_LWL<113> A_LWL<112> A_RWL<127> A_RWL<126> A_RWL<125> A_RWL<124> A_RWL<123> A_RWL<122> A_RWL<121> A_RWL<120> A_RWL<119> A_RWL<118> A_RWL<117> A_RWL<116> A_RWL<115> A_RWL<114> A_RWL<113> A_RWL<112> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_SRAM +XRAM<7> A_BLC<11> A_BLC<10> A_BLC<13> A_BLC<12> A_BLT<11> A_BLT<10> A_BLT<13> A_BLT<12> A_LWL<111> A_LWL<110> A_LWL<109> A_LWL<108> A_LWL<107> A_LWL<106> A_LWL<105> A_LWL<104> A_LWL<103> A_LWL<102> A_LWL<101> A_LWL<100> A_LWL<99> A_LWL<98> A_LWL<97> A_LWL<96> A_RWL<111> A_RWL<110> A_RWL<109> A_RWL<108> A_RWL<107> A_RWL<106> A_RWL<105> A_RWL<104> A_RWL<103> A_RWL<102> A_RWL<101> A_RWL<100> A_RWL<99> A_RWL<98> A_RWL<97> A_RWL<96> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_SRAM +XRAM<6> A_BLC<9> A_BLC<8> A_BLC<11> A_BLC<10> A_BLT<9> A_BLT<8> A_BLT<11> A_BLT<10> A_LWL<95> A_LWL<94> A_LWL<93> A_LWL<92> A_LWL<91> A_LWL<90> A_LWL<89> A_LWL<88> A_LWL<87> A_LWL<86> A_LWL<85> A_LWL<84> A_LWL<83> A_LWL<82> A_LWL<81> A_LWL<80> A_RWL<95> A_RWL<94> A_RWL<93> A_RWL<92> A_RWL<91> A_RWL<90> A_RWL<89> A_RWL<88> A_RWL<87> A_RWL<86> A_RWL<85> A_RWL<84> A_RWL<83> A_RWL<82> A_RWL<81> A_RWL<80> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_SRAM +XRAM<5> A_BLC<7> A_BLC<6> A_BLC<9> A_BLC<8> A_BLT<7> A_BLT<6> A_BLT<9> A_BLT<8> A_LWL<79> A_LWL<78> A_LWL<77> A_LWL<76> A_LWL<75> A_LWL<74> A_LWL<73> A_LWL<72> A_LWL<71> A_LWL<70> A_LWL<69> A_LWL<68> A_LWL<67> A_LWL<66> A_LWL<65> A_LWL<64> A_RWL<79> A_RWL<78> A_RWL<77> A_RWL<76> A_RWL<75> A_RWL<74> A_RWL<73> A_RWL<72> A_RWL<71> A_RWL<70> A_RWL<69> A_RWL<68> A_RWL<67> A_RWL<66> A_RWL<65> A_RWL<64> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_SRAM +XRAM<4> A_BLC<5> A_BLC<4> A_BLC<7> A_BLC<6> A_BLT<5> A_BLT<4> A_BLT<7> A_BLT<6> A_LWL<63> A_LWL<62> A_LWL<61> A_LWL<60> A_LWL<59> A_LWL<58> A_LWL<57> A_LWL<56> A_LWL<55> A_LWL<54> A_LWL<53> A_LWL<52> A_LWL<51> A_LWL<50> A_LWL<49> A_LWL<48> A_RWL<63> A_RWL<62> A_RWL<61> A_RWL<60> A_RWL<59> A_RWL<58> A_RWL<57> A_RWL<56> A_RWL<55> A_RWL<54> A_RWL<53> A_RWL<52> A_RWL<51> A_RWL<50> A_RWL<49> A_RWL<48> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_SRAM +XRAM<3> A_BLC<3> A_BLC<2> A_BLC<5> A_BLC<4> A_BLT<3> A_BLT<2> A_BLT<5> A_BLT<4> A_LWL<47> A_LWL<46> A_LWL<45> A_LWL<44> A_LWL<43> A_LWL<42> A_LWL<41> A_LWL<40> A_LWL<39> A_LWL<38> A_LWL<37> A_LWL<36> A_LWL<35> A_LWL<34> A_LWL<33> A_LWL<32> A_RWL<47> A_RWL<46> A_RWL<45> A_RWL<44> A_RWL<43> A_RWL<42> A_RWL<41> A_RWL<40> A_RWL<39> A_RWL<38> A_RWL<37> A_RWL<36> A_RWL<35> A_RWL<34> A_RWL<33> A_RWL<32> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_SRAM +XRAM<2> A_BLC<1> A_BLC<0> A_BLC<3> A_BLC<2> A_BLT<1> A_BLT<0> A_BLT<3> A_BLT<2> A_LWL<31> A_LWL<30> A_LWL<29> A_LWL<28> A_LWL<27> A_LWL<26> A_LWL<25> A_LWL<24> A_LWL<23> A_LWL<22> A_LWL<21> A_LWL<20> A_LWL<19> A_LWL<18> A_LWL<17> A_LWL<16> A_RWL<31> A_RWL<30> A_RWL<29> A_RWL<28> A_RWL<27> A_RWL<26> A_RWL<25> A_RWL<24> A_RWL<23> A_RWL<22> A_RWL<21> A_RWL<20> A_RWL<19> A_RWL<18> A_RWL<17> A_RWL<16> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_SRAM +XRAM<1> A_BLC_BOT<1> A_BLC_BOT<0> A_BLC<1> A_BLC<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT<1> A_BLT<0> A_LWL<15> A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_SRAM +XEDGE<1> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT_TOP<1> A_BLT_TOP<0> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_TB +XEDGE<0> A_BLC_BOT<1> A_BLC_BOT<0> A_BLT_BOT<1> A_BLT_BOT<0> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_TB +.ENDS + + + + +.SUBCKT RM_IHPSG13_4096x16_c3_1P_MATRIX_pcell_1 A_BLC<63> A_BLC<62> A_BLC<61> A_BLC<60> A_BLC<59> A_BLC<58> A_BLC<57> A_BLC<56> A_BLC<55> A_BLC<54> A_BLC<53> A_BLC<52> A_BLC<51> A_BLC<50> A_BLC<49> A_BLC<48> A_BLC<47> A_BLC<46> A_BLC<45> A_BLC<44> A_BLC<43> A_BLC<42> A_BLC<41> A_BLC<40> A_BLC<39> A_BLC<38> A_BLC<37> A_BLC<36> A_BLC<35> A_BLC<34> A_BLC<33> A_BLC<32> A_BLC<31> A_BLC<30> A_BLC<29> A_BLC<28> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC<19> A_BLC<18> A_BLC<17> A_BLC<16> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<63> A_BLT<62> A_BLT<61> A_BLT<60> A_BLT<59> A_BLT<58> A_BLT<57> A_BLT<56> A_BLT<55> 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A_WL<165> A_WL<164> A_WL<163> A_WL<162> A_WL<161> A_WL<160> A_WL<159> A_WL<158> A_WL<157> A_WL<156> A_WL<155> A_WL<154> A_WL<153> A_WL<152> A_WL<151> A_WL<150> A_WL<149> A_WL<148> A_WL<147> A_WL<146> A_WL<145> A_WL<144> A_WL<143> A_WL<142> A_WL<141> A_WL<140> A_WL<139> A_WL<138> A_WL<137> A_WL<136> A_WL<135> A_WL<134> A_WL<133> A_WL<132> A_WL<131> A_WL<130> A_WL<129> A_WL<128> A_WL<127> A_WL<126> A_WL<125> A_WL<124> A_WL<123> A_WL<122> A_WL<121> A_WL<120> A_WL<119> A_WL<118> A_WL<117> A_WL<116> A_WL<115> A_WL<114> A_WL<113> A_WL<112> A_WL<111> A_WL<110> A_WL<109> A_WL<108> A_WL<107> A_WL<106> A_WL<105> A_WL<104> A_WL<103> A_WL<102> A_WL<101> A_WL<100> A_WL<99> A_WL<98> A_WL<97> A_WL<96> A_WL<95> A_WL<94> A_WL<93> A_WL<92> A_WL<91> A_WL<90> A_WL<89> A_WL<88> A_WL<87> A_WL<86> A_WL<85> A_WL<84> A_WL<83> A_WL<82> A_WL<81> A_WL<80> A_WL<79> A_WL<78> A_WL<77> A_WL<76> A_WL<75> A_WL<74> A_WL<73> A_WL<72> A_WL<71> A_WL<70> A_WL<69> A_WL<68> A_WL<67> A_WL<66> A_WL<65> A_WL<64> A_WL<63> A_WL<62> A_WL<61> A_WL<60> A_WL<59> A_WL<58> A_WL<57> A_WL<56> A_WL<55> A_WL<54> A_WL<53> A_WL<52> A_WL<51> A_WL<50> A_WL<49> A_WL<48> A_WL<47> A_WL<46> A_WL<45> A_WL<44> A_WL<43> A_WL<42> A_WL<41> A_WL<40> A_WL<39> A_WL<38> A_WL<37> A_WL<36> A_WL<35> A_WL<34> A_WL<33> A_WL<32> A_WL<31> A_WL<30> A_WL<29> A_WL<28> A_WL<27> A_WL<26> A_WL<25> A_WL<24> A_WL<23> A_WL<22> A_WL<21> A_WL<20> A_WL<19> A_WL<18> A_WL<17> A_WL<16> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> VDD_CORE VSS +XCORNER<3> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_CORNER +XCORNER<2> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_CORNER +XCORNER<1> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_CORNER +XCORNER<0> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_CORNER +XRAMEDGE_L<31> A_WL<511> A_WL<510> A_WL<509> A_WL<508> A_WL<507> A_WL<506> A_WL<505> A_WL<504> A_WL<503> A_WL<502> A_WL<501> A_WL<500> A_WL<499> A_WL<498> A_WL<497> A_WL<496> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<30> A_WL<495> A_WL<494> A_WL<493> A_WL<492> A_WL<491> A_WL<490> A_WL<489> A_WL<488> A_WL<487> A_WL<486> A_WL<485> A_WL<484> A_WL<483> A_WL<482> A_WL<481> A_WL<480> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<29> A_WL<479> A_WL<478> A_WL<477> A_WL<476> A_WL<475> A_WL<474> A_WL<473> A_WL<472> A_WL<471> A_WL<470> A_WL<469> A_WL<468> A_WL<467> A_WL<466> A_WL<465> A_WL<464> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<28> A_WL<463> A_WL<462> A_WL<461> A_WL<460> A_WL<459> A_WL<458> A_WL<457> A_WL<456> A_WL<455> A_WL<454> A_WL<453> A_WL<452> A_WL<451> A_WL<450> A_WL<449> A_WL<448> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<27> A_WL<447> A_WL<446> A_WL<445> A_WL<444> A_WL<443> A_WL<442> A_WL<441> A_WL<440> A_WL<439> A_WL<438> A_WL<437> A_WL<436> A_WL<435> A_WL<434> A_WL<433> A_WL<432> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<26> A_WL<431> A_WL<430> A_WL<429> A_WL<428> A_WL<427> A_WL<426> A_WL<425> A_WL<424> A_WL<423> A_WL<422> A_WL<421> A_WL<420> A_WL<419> A_WL<418> A_WL<417> A_WL<416> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<25> A_WL<415> A_WL<414> A_WL<413> A_WL<412> A_WL<411> A_WL<410> A_WL<409> A_WL<408> A_WL<407> A_WL<406> A_WL<405> A_WL<404> A_WL<403> A_WL<402> A_WL<401> A_WL<400> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<24> A_WL<399> A_WL<398> A_WL<397> A_WL<396> A_WL<395> A_WL<394> A_WL<393> A_WL<392> A_WL<391> A_WL<390> A_WL<389> A_WL<388> A_WL<387> A_WL<386> A_WL<385> A_WL<384> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<23> A_WL<383> A_WL<382> A_WL<381> A_WL<380> A_WL<379> A_WL<378> A_WL<377> A_WL<376> A_WL<375> A_WL<374> A_WL<373> A_WL<372> A_WL<371> A_WL<370> A_WL<369> A_WL<368> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<22> A_WL<367> A_WL<366> A_WL<365> A_WL<364> A_WL<363> A_WL<362> A_WL<361> A_WL<360> A_WL<359> A_WL<358> A_WL<357> A_WL<356> A_WL<355> A_WL<354> A_WL<353> A_WL<352> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<21> A_WL<351> A_WL<350> A_WL<349> A_WL<348> A_WL<347> A_WL<346> A_WL<345> A_WL<344> A_WL<343> A_WL<342> A_WL<341> A_WL<340> A_WL<339> A_WL<338> A_WL<337> A_WL<336> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<20> A_WL<335> A_WL<334> A_WL<333> A_WL<332> A_WL<331> A_WL<330> A_WL<329> A_WL<328> A_WL<327> A_WL<326> A_WL<325> A_WL<324> A_WL<323> A_WL<322> A_WL<321> A_WL<320> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<19> A_WL<319> A_WL<318> A_WL<317> A_WL<316> A_WL<315> A_WL<314> A_WL<313> A_WL<312> A_WL<311> A_WL<310> A_WL<309> A_WL<308> A_WL<307> A_WL<306> A_WL<305> A_WL<304> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<18> A_WL<303> A_WL<302> A_WL<301> A_WL<300> A_WL<299> A_WL<298> A_WL<297> A_WL<296> A_WL<295> A_WL<294> A_WL<293> A_WL<292> A_WL<291> A_WL<290> A_WL<289> A_WL<288> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<17> A_WL<287> A_WL<286> A_WL<285> A_WL<284> A_WL<283> A_WL<282> A_WL<281> A_WL<280> A_WL<279> A_WL<278> A_WL<277> A_WL<276> A_WL<275> A_WL<274> A_WL<273> A_WL<272> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<16> A_WL<271> A_WL<270> A_WL<269> A_WL<268> A_WL<267> A_WL<266> A_WL<265> A_WL<264> A_WL<263> A_WL<262> A_WL<261> A_WL<260> A_WL<259> A_WL<258> A_WL<257> A_WL<256> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<15> A_WL<255> A_WL<254> A_WL<253> A_WL<252> A_WL<251> A_WL<250> A_WL<249> A_WL<248> A_WL<247> A_WL<246> A_WL<245> A_WL<244> A_WL<243> A_WL<242> A_WL<241> A_WL<240> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<14> A_WL<239> A_WL<238> A_WL<237> A_WL<236> A_WL<235> A_WL<234> A_WL<233> A_WL<232> A_WL<231> A_WL<230> A_WL<229> A_WL<228> A_WL<227> A_WL<226> A_WL<225> A_WL<224> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<13> A_WL<223> A_WL<222> A_WL<221> A_WL<220> A_WL<219> A_WL<218> A_WL<217> A_WL<216> A_WL<215> A_WL<214> A_WL<213> A_WL<212> A_WL<211> A_WL<210> A_WL<209> A_WL<208> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<12> A_WL<207> A_WL<206> A_WL<205> A_WL<204> A_WL<203> A_WL<202> A_WL<201> A_WL<200> A_WL<199> A_WL<198> A_WL<197> A_WL<196> A_WL<195> A_WL<194> A_WL<193> A_WL<192> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<11> A_WL<191> A_WL<190> A_WL<189> A_WL<188> A_WL<187> A_WL<186> A_WL<185> A_WL<184> A_WL<183> A_WL<182> A_WL<181> A_WL<180> A_WL<179> A_WL<178> A_WL<177> A_WL<176> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<10> A_WL<175> A_WL<174> A_WL<173> A_WL<172> A_WL<171> A_WL<170> A_WL<169> A_WL<168> A_WL<167> A_WL<166> A_WL<165> A_WL<164> A_WL<163> A_WL<162> A_WL<161> A_WL<160> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<9> A_WL<159> A_WL<158> A_WL<157> A_WL<156> A_WL<155> A_WL<154> A_WL<153> A_WL<152> A_WL<151> A_WL<150> A_WL<149> A_WL<148> A_WL<147> A_WL<146> A_WL<145> A_WL<144> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<8> A_WL<143> A_WL<142> A_WL<141> A_WL<140> A_WL<139> A_WL<138> A_WL<137> A_WL<136> A_WL<135> A_WL<134> A_WL<133> A_WL<132> A_WL<131> A_WL<130> A_WL<129> A_WL<128> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<7> A_WL<127> A_WL<126> A_WL<125> A_WL<124> A_WL<123> A_WL<122> A_WL<121> A_WL<120> A_WL<119> A_WL<118> A_WL<117> A_WL<116> A_WL<115> A_WL<114> A_WL<113> A_WL<112> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<6> A_WL<111> A_WL<110> A_WL<109> A_WL<108> A_WL<107> A_WL<106> A_WL<105> A_WL<104> A_WL<103> A_WL<102> A_WL<101> A_WL<100> A_WL<99> A_WL<98> A_WL<97> A_WL<96> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<5> A_WL<95> A_WL<94> A_WL<93> A_WL<92> A_WL<91> A_WL<90> A_WL<89> A_WL<88> A_WL<87> A_WL<86> A_WL<85> A_WL<84> A_WL<83> A_WL<82> A_WL<81> A_WL<80> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<4> A_WL<79> A_WL<78> A_WL<77> A_WL<76> A_WL<75> A_WL<74> A_WL<73> A_WL<72> A_WL<71> A_WL<70> A_WL<69> A_WL<68> A_WL<67> A_WL<66> A_WL<65> A_WL<64> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<3> A_WL<63> A_WL<62> A_WL<61> A_WL<60> A_WL<59> A_WL<58> A_WL<57> A_WL<56> A_WL<55> A_WL<54> A_WL<53> A_WL<52> A_WL<51> A_WL<50> A_WL<49> A_WL<48> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<2> A_WL<47> A_WL<46> A_WL<45> A_WL<44> A_WL<43> A_WL<42> A_WL<41> A_WL<40> A_WL<39> A_WL<38> A_WL<37> A_WL<36> A_WL<35> A_WL<34> A_WL<33> A_WL<32> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<1> A_WL<31> A_WL<30> A_WL<29> A_WL<28> A_WL<27> A_WL<26> A_WL<25> A_WL<24> A_WL<23> A_WL<22> A_WL<21> A_WL<20> A_WL<19> A_WL<18> A_WL<17> A_WL<16> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<0> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<31> A_IWL<16383> A_IWL<16382> A_IWL<16381> A_IWL<16380> A_IWL<16379> A_IWL<16378> A_IWL<16377> A_IWL<16376> A_IWL<16375> A_IWL<16374> A_IWL<16373> A_IWL<16372> A_IWL<16371> A_IWL<16370> A_IWL<16369> A_IWL<16368> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<30> A_IWL<16367> A_IWL<16366> A_IWL<16365> A_IWL<16364> A_IWL<16363> A_IWL<16362> A_IWL<16361> A_IWL<16360> A_IWL<16359> A_IWL<16358> A_IWL<16357> A_IWL<16356> A_IWL<16355> A_IWL<16354> A_IWL<16353> A_IWL<16352> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<29> A_IWL<16351> A_IWL<16350> A_IWL<16349> A_IWL<16348> A_IWL<16347> A_IWL<16346> A_IWL<16345> A_IWL<16344> A_IWL<16343> A_IWL<16342> A_IWL<16341> A_IWL<16340> A_IWL<16339> A_IWL<16338> A_IWL<16337> A_IWL<16336> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<28> A_IWL<16335> A_IWL<16334> A_IWL<16333> A_IWL<16332> A_IWL<16331> A_IWL<16330> A_IWL<16329> A_IWL<16328> A_IWL<16327> A_IWL<16326> A_IWL<16325> A_IWL<16324> A_IWL<16323> A_IWL<16322> A_IWL<16321> A_IWL<16320> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<27> A_IWL<16319> A_IWL<16318> A_IWL<16317> A_IWL<16316> A_IWL<16315> A_IWL<16314> A_IWL<16313> A_IWL<16312> A_IWL<16311> A_IWL<16310> A_IWL<16309> A_IWL<16308> A_IWL<16307> A_IWL<16306> A_IWL<16305> A_IWL<16304> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<26> A_IWL<16303> A_IWL<16302> A_IWL<16301> A_IWL<16300> A_IWL<16299> A_IWL<16298> A_IWL<16297> A_IWL<16296> A_IWL<16295> A_IWL<16294> A_IWL<16293> A_IWL<16292> A_IWL<16291> A_IWL<16290> A_IWL<16289> A_IWL<16288> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<25> A_IWL<16287> A_IWL<16286> A_IWL<16285> A_IWL<16284> A_IWL<16283> A_IWL<16282> A_IWL<16281> A_IWL<16280> A_IWL<16279> A_IWL<16278> A_IWL<16277> A_IWL<16276> A_IWL<16275> A_IWL<16274> A_IWL<16273> A_IWL<16272> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<24> A_IWL<16271> A_IWL<16270> A_IWL<16269> A_IWL<16268> A_IWL<16267> A_IWL<16266> A_IWL<16265> A_IWL<16264> A_IWL<16263> A_IWL<16262> A_IWL<16261> A_IWL<16260> A_IWL<16259> A_IWL<16258> A_IWL<16257> A_IWL<16256> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<23> A_IWL<16255> A_IWL<16254> A_IWL<16253> A_IWL<16252> A_IWL<16251> A_IWL<16250> A_IWL<16249> A_IWL<16248> A_IWL<16247> A_IWL<16246> A_IWL<16245> A_IWL<16244> A_IWL<16243> A_IWL<16242> A_IWL<16241> A_IWL<16240> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<22> A_IWL<16239> A_IWL<16238> A_IWL<16237> A_IWL<16236> A_IWL<16235> A_IWL<16234> A_IWL<16233> A_IWL<16232> A_IWL<16231> A_IWL<16230> A_IWL<16229> A_IWL<16228> A_IWL<16227> A_IWL<16226> A_IWL<16225> A_IWL<16224> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<21> A_IWL<16223> A_IWL<16222> A_IWL<16221> A_IWL<16220> A_IWL<16219> A_IWL<16218> A_IWL<16217> A_IWL<16216> A_IWL<16215> A_IWL<16214> A_IWL<16213> A_IWL<16212> A_IWL<16211> A_IWL<16210> A_IWL<16209> A_IWL<16208> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<20> A_IWL<16207> A_IWL<16206> A_IWL<16205> A_IWL<16204> A_IWL<16203> A_IWL<16202> A_IWL<16201> A_IWL<16200> A_IWL<16199> A_IWL<16198> A_IWL<16197> A_IWL<16196> A_IWL<16195> A_IWL<16194> A_IWL<16193> A_IWL<16192> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<19> A_IWL<16191> A_IWL<16190> A_IWL<16189> A_IWL<16188> A_IWL<16187> A_IWL<16186> A_IWL<16185> A_IWL<16184> A_IWL<16183> A_IWL<16182> A_IWL<16181> A_IWL<16180> A_IWL<16179> A_IWL<16178> A_IWL<16177> A_IWL<16176> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<18> A_IWL<16175> A_IWL<16174> A_IWL<16173> A_IWL<16172> A_IWL<16171> A_IWL<16170> A_IWL<16169> A_IWL<16168> A_IWL<16167> A_IWL<16166> A_IWL<16165> A_IWL<16164> A_IWL<16163> A_IWL<16162> A_IWL<16161> A_IWL<16160> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<17> A_IWL<16159> A_IWL<16158> A_IWL<16157> A_IWL<16156> A_IWL<16155> A_IWL<16154> A_IWL<16153> A_IWL<16152> A_IWL<16151> A_IWL<16150> A_IWL<16149> A_IWL<16148> A_IWL<16147> A_IWL<16146> A_IWL<16145> A_IWL<16144> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<16> A_IWL<16143> A_IWL<16142> A_IWL<16141> A_IWL<16140> A_IWL<16139> A_IWL<16138> A_IWL<16137> A_IWL<16136> A_IWL<16135> A_IWL<16134> A_IWL<16133> A_IWL<16132> A_IWL<16131> A_IWL<16130> A_IWL<16129> A_IWL<16128> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<15> A_IWL<16127> A_IWL<16126> A_IWL<16125> A_IWL<16124> A_IWL<16123> A_IWL<16122> A_IWL<16121> A_IWL<16120> A_IWL<16119> A_IWL<16118> A_IWL<16117> A_IWL<16116> A_IWL<16115> A_IWL<16114> A_IWL<16113> A_IWL<16112> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<14> A_IWL<16111> A_IWL<16110> A_IWL<16109> A_IWL<16108> A_IWL<16107> A_IWL<16106> A_IWL<16105> A_IWL<16104> A_IWL<16103> A_IWL<16102> A_IWL<16101> A_IWL<16100> A_IWL<16099> A_IWL<16098> A_IWL<16097> A_IWL<16096> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<13> A_IWL<16095> A_IWL<16094> A_IWL<16093> A_IWL<16092> A_IWL<16091> A_IWL<16090> A_IWL<16089> A_IWL<16088> A_IWL<16087> A_IWL<16086> A_IWL<16085> A_IWL<16084> A_IWL<16083> A_IWL<16082> A_IWL<16081> A_IWL<16080> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<12> A_IWL<16079> A_IWL<16078> A_IWL<16077> A_IWL<16076> A_IWL<16075> A_IWL<16074> A_IWL<16073> A_IWL<16072> A_IWL<16071> A_IWL<16070> A_IWL<16069> A_IWL<16068> A_IWL<16067> A_IWL<16066> A_IWL<16065> A_IWL<16064> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<11> A_IWL<16063> A_IWL<16062> A_IWL<16061> A_IWL<16060> A_IWL<16059> A_IWL<16058> A_IWL<16057> A_IWL<16056> A_IWL<16055> A_IWL<16054> A_IWL<16053> A_IWL<16052> A_IWL<16051> A_IWL<16050> A_IWL<16049> A_IWL<16048> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<10> A_IWL<16047> A_IWL<16046> A_IWL<16045> A_IWL<16044> A_IWL<16043> A_IWL<16042> A_IWL<16041> A_IWL<16040> A_IWL<16039> A_IWL<16038> A_IWL<16037> A_IWL<16036> A_IWL<16035> A_IWL<16034> A_IWL<16033> A_IWL<16032> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<9> A_IWL<16031> A_IWL<16030> A_IWL<16029> A_IWL<16028> A_IWL<16027> A_IWL<16026> A_IWL<16025> A_IWL<16024> A_IWL<16023> A_IWL<16022> A_IWL<16021> A_IWL<16020> A_IWL<16019> A_IWL<16018> A_IWL<16017> A_IWL<16016> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<8> A_IWL<16015> A_IWL<16014> A_IWL<16013> A_IWL<16012> A_IWL<16011> A_IWL<16010> A_IWL<16009> A_IWL<16008> A_IWL<16007> A_IWL<16006> A_IWL<16005> A_IWL<16004> A_IWL<16003> A_IWL<16002> A_IWL<16001> A_IWL<16000> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<7> A_IWL<15999> A_IWL<15998> A_IWL<15997> A_IWL<15996> A_IWL<15995> A_IWL<15994> A_IWL<15993> A_IWL<15992> A_IWL<15991> A_IWL<15990> A_IWL<15989> A_IWL<15988> A_IWL<15987> A_IWL<15986> A_IWL<15985> A_IWL<15984> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<6> A_IWL<15983> A_IWL<15982> A_IWL<15981> A_IWL<15980> A_IWL<15979> A_IWL<15978> A_IWL<15977> A_IWL<15976> A_IWL<15975> A_IWL<15974> A_IWL<15973> A_IWL<15972> A_IWL<15971> A_IWL<15970> A_IWL<15969> A_IWL<15968> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<5> A_IWL<15967> A_IWL<15966> A_IWL<15965> A_IWL<15964> A_IWL<15963> A_IWL<15962> A_IWL<15961> A_IWL<15960> A_IWL<15959> A_IWL<15958> A_IWL<15957> A_IWL<15956> A_IWL<15955> A_IWL<15954> A_IWL<15953> A_IWL<15952> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<4> A_IWL<15951> A_IWL<15950> A_IWL<15949> A_IWL<15948> A_IWL<15947> A_IWL<15946> A_IWL<15945> A_IWL<15944> A_IWL<15943> A_IWL<15942> A_IWL<15941> A_IWL<15940> A_IWL<15939> A_IWL<15938> A_IWL<15937> A_IWL<15936> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<3> A_IWL<15935> A_IWL<15934> A_IWL<15933> A_IWL<15932> A_IWL<15931> A_IWL<15930> A_IWL<15929> A_IWL<15928> A_IWL<15927> A_IWL<15926> A_IWL<15925> A_IWL<15924> A_IWL<15923> A_IWL<15922> A_IWL<15921> A_IWL<15920> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<2> A_IWL<15919> A_IWL<15918> A_IWL<15917> A_IWL<15916> A_IWL<15915> A_IWL<15914> A_IWL<15913> A_IWL<15912> A_IWL<15911> A_IWL<15910> A_IWL<15909> A_IWL<15908> A_IWL<15907> A_IWL<15906> A_IWL<15905> A_IWL<15904> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<1> A_IWL<15903> A_IWL<15902> A_IWL<15901> A_IWL<15900> A_IWL<15899> A_IWL<15898> A_IWL<15897> A_IWL<15896> A_IWL<15895> A_IWL<15894> A_IWL<15893> A_IWL<15892> A_IWL<15891> A_IWL<15890> A_IWL<15889> A_IWL<15888> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<0> A_IWL<15887> A_IWL<15886> A_IWL<15885> A_IWL<15884> A_IWL<15883> A_IWL<15882> A_IWL<15881> A_IWL<15880> A_IWL<15879> A_IWL<15878> A_IWL<15877> A_IWL<15876> A_IWL<15875> A_IWL<15874> A_IWL<15873> A_IWL<15872> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR +XCOL<31> A_BLC<63> A_BLC<62> A_BLC_TOP<63> A_BLC_TOP<62> A_BLT<63> A_BLT<62> A_BLT_TOP<63> A_BLT_TOP<62> A_IWL<15871> A_IWL<15870> A_IWL<15869> A_IWL<15868> A_IWL<15867> A_IWL<15866> A_IWL<15865> A_IWL<15864> A_IWL<15863> A_IWL<15862> A_IWL<15861> A_IWL<15860> A_IWL<15859> A_IWL<15858> A_IWL<15857> A_IWL<15856> A_IWL<15855> A_IWL<15854> A_IWL<15853> A_IWL<15852> A_IWL<15851> A_IWL<15850> A_IWL<15849> A_IWL<15848> A_IWL<15847> A_IWL<15846> A_IWL<15845> A_IWL<15844> A_IWL<15843> A_IWL<15842> A_IWL<15841> A_IWL<15840> A_IWL<15839> A_IWL<15838> A_IWL<15837> A_IWL<15836> A_IWL<15835> A_IWL<15834> A_IWL<15833> A_IWL<15832> A_IWL<15831> A_IWL<15830> A_IWL<15829> A_IWL<15828> A_IWL<15827> A_IWL<15826> A_IWL<15825> A_IWL<15824> A_IWL<15823> A_IWL<15822> A_IWL<15821> A_IWL<15820> A_IWL<15819> A_IWL<15818> A_IWL<15817> A_IWL<15816> A_IWL<15815> A_IWL<15814> A_IWL<15813> A_IWL<15812> A_IWL<15811> A_IWL<15810> A_IWL<15809> A_IWL<15808> A_IWL<15807> A_IWL<15806> A_IWL<15805> A_IWL<15804> A_IWL<15803> A_IWL<15802> A_IWL<15801> A_IWL<15800> A_IWL<15799> A_IWL<15798> A_IWL<15797> A_IWL<15796> A_IWL<15795> A_IWL<15794> A_IWL<15793> A_IWL<15792> A_IWL<15791> A_IWL<15790> A_IWL<15789> A_IWL<15788> A_IWL<15787> A_IWL<15786> A_IWL<15785> A_IWL<15784> A_IWL<15783> A_IWL<15782> A_IWL<15781> A_IWL<15780> A_IWL<15779> A_IWL<15778> A_IWL<15777> A_IWL<15776> A_IWL<15775> A_IWL<15774> A_IWL<15773> A_IWL<15772> A_IWL<15771> A_IWL<15770> A_IWL<15769> A_IWL<15768> A_IWL<15767> A_IWL<15766> A_IWL<15765> A_IWL<15764> A_IWL<15763> A_IWL<15762> A_IWL<15761> A_IWL<15760> A_IWL<15759> A_IWL<15758> A_IWL<15757> A_IWL<15756> A_IWL<15755> A_IWL<15754> A_IWL<15753> A_IWL<15752> A_IWL<15751> A_IWL<15750> A_IWL<15749> A_IWL<15748> A_IWL<15747> A_IWL<15746> A_IWL<15745> A_IWL<15744> A_IWL<15743> A_IWL<15742> A_IWL<15741> A_IWL<15740> A_IWL<15739> A_IWL<15738> A_IWL<15737> A_IWL<15736> A_IWL<15735> A_IWL<15734> A_IWL<15733> A_IWL<15732> A_IWL<15731> A_IWL<15730> A_IWL<15729> A_IWL<15728> A_IWL<15727> A_IWL<15726> A_IWL<15725> A_IWL<15724> A_IWL<15723> A_IWL<15722> A_IWL<15721> A_IWL<15720> A_IWL<15719> A_IWL<15718> A_IWL<15717> A_IWL<15716> A_IWL<15715> A_IWL<15714> A_IWL<15713> A_IWL<15712> A_IWL<15711> A_IWL<15710> A_IWL<15709> A_IWL<15708> A_IWL<15707> A_IWL<15706> A_IWL<15705> A_IWL<15704> A_IWL<15703> A_IWL<15702> A_IWL<15701> A_IWL<15700> A_IWL<15699> A_IWL<15698> A_IWL<15697> A_IWL<15696> A_IWL<15695> A_IWL<15694> A_IWL<15693> A_IWL<15692> A_IWL<15691> A_IWL<15690> A_IWL<15689> A_IWL<15688> A_IWL<15687> A_IWL<15686> A_IWL<15685> A_IWL<15684> A_IWL<15683> A_IWL<15682> A_IWL<15681> A_IWL<15680> A_IWL<15679> A_IWL<15678> A_IWL<15677> A_IWL<15676> A_IWL<15675> A_IWL<15674> A_IWL<15673> A_IWL<15672> A_IWL<15671> A_IWL<15670> A_IWL<15669> A_IWL<15668> A_IWL<15667> A_IWL<15666> A_IWL<15665> A_IWL<15664> A_IWL<15663> A_IWL<15662> A_IWL<15661> A_IWL<15660> A_IWL<15659> A_IWL<15658> A_IWL<15657> A_IWL<15656> A_IWL<15655> A_IWL<15654> A_IWL<15653> A_IWL<15652> A_IWL<15651> A_IWL<15650> A_IWL<15649> A_IWL<15648> A_IWL<15647> A_IWL<15646> A_IWL<15645> A_IWL<15644> A_IWL<15643> A_IWL<15642> A_IWL<15641> A_IWL<15640> A_IWL<15639> A_IWL<15638> A_IWL<15637> A_IWL<15636> A_IWL<15635> A_IWL<15634> A_IWL<15633> A_IWL<15632> A_IWL<15631> A_IWL<15630> A_IWL<15629> A_IWL<15628> A_IWL<15627> A_IWL<15626> A_IWL<15625> A_IWL<15624> A_IWL<15623> A_IWL<15622> A_IWL<15621> A_IWL<15620> A_IWL<15619> A_IWL<15618> A_IWL<15617> A_IWL<15616> A_IWL<15615> A_IWL<15614> A_IWL<15613> A_IWL<15612> A_IWL<15611> A_IWL<15610> A_IWL<15609> A_IWL<15608> A_IWL<15607> A_IWL<15606> A_IWL<15605> A_IWL<15604> A_IWL<15603> A_IWL<15602> A_IWL<15601> A_IWL<15600> A_IWL<15599> A_IWL<15598> A_IWL<15597> A_IWL<15596> A_IWL<15595> A_IWL<15594> A_IWL<15593> A_IWL<15592> A_IWL<15591> A_IWL<15590> A_IWL<15589> A_IWL<15588> A_IWL<15587> A_IWL<15586> A_IWL<15585> A_IWL<15584> A_IWL<15583> A_IWL<15582> A_IWL<15581> A_IWL<15580> A_IWL<15579> A_IWL<15578> A_IWL<15577> A_IWL<15576> A_IWL<15575> A_IWL<15574> A_IWL<15573> A_IWL<15572> A_IWL<15571> A_IWL<15570> A_IWL<15569> A_IWL<15568> A_IWL<15567> A_IWL<15566> A_IWL<15565> A_IWL<15564> A_IWL<15563> A_IWL<15562> A_IWL<15561> A_IWL<15560> A_IWL<15559> A_IWL<15558> A_IWL<15557> A_IWL<15556> A_IWL<15555> A_IWL<15554> A_IWL<15553> A_IWL<15552> A_IWL<15551> A_IWL<15550> A_IWL<15549> A_IWL<15548> A_IWL<15547> A_IWL<15546> A_IWL<15545> A_IWL<15544> A_IWL<15543> A_IWL<15542> A_IWL<15541> A_IWL<15540> A_IWL<15539> A_IWL<15538> A_IWL<15537> A_IWL<15536> A_IWL<15535> A_IWL<15534> A_IWL<15533> A_IWL<15532> A_IWL<15531> A_IWL<15530> A_IWL<15529> A_IWL<15528> A_IWL<15527> A_IWL<15526> A_IWL<15525> A_IWL<15524> A_IWL<15523> A_IWL<15522> A_IWL<15521> A_IWL<15520> A_IWL<15519> A_IWL<15518> A_IWL<15517> A_IWL<15516> A_IWL<15515> A_IWL<15514> A_IWL<15513> A_IWL<15512> A_IWL<15511> A_IWL<15510> A_IWL<15509> A_IWL<15508> A_IWL<15507> A_IWL<15506> A_IWL<15505> A_IWL<15504> A_IWL<15503> A_IWL<15502> A_IWL<15501> A_IWL<15500> A_IWL<15499> A_IWL<15498> A_IWL<15497> A_IWL<15496> A_IWL<15495> A_IWL<15494> A_IWL<15493> A_IWL<15492> A_IWL<15491> A_IWL<15490> A_IWL<15489> A_IWL<15488> A_IWL<15487> A_IWL<15486> A_IWL<15485> A_IWL<15484> A_IWL<15483> A_IWL<15482> A_IWL<15481> A_IWL<15480> A_IWL<15479> A_IWL<15478> A_IWL<15477> A_IWL<15476> A_IWL<15475> A_IWL<15474> A_IWL<15473> A_IWL<15472> A_IWL<15471> A_IWL<15470> A_IWL<15469> A_IWL<15468> A_IWL<15467> A_IWL<15466> A_IWL<15465> A_IWL<15464> A_IWL<15463> A_IWL<15462> A_IWL<15461> A_IWL<15460> A_IWL<15459> A_IWL<15458> A_IWL<15457> A_IWL<15456> A_IWL<15455> A_IWL<15454> A_IWL<15453> A_IWL<15452> A_IWL<15451> A_IWL<15450> A_IWL<15449> A_IWL<15448> A_IWL<15447> A_IWL<15446> A_IWL<15445> A_IWL<15444> A_IWL<15443> A_IWL<15442> A_IWL<15441> A_IWL<15440> A_IWL<15439> A_IWL<15438> A_IWL<15437> A_IWL<15436> A_IWL<15435> A_IWL<15434> A_IWL<15433> A_IWL<15432> A_IWL<15431> A_IWL<15430> A_IWL<15429> A_IWL<15428> A_IWL<15427> A_IWL<15426> A_IWL<15425> A_IWL<15424> A_IWL<15423> A_IWL<15422> A_IWL<15421> A_IWL<15420> A_IWL<15419> A_IWL<15418> A_IWL<15417> A_IWL<15416> A_IWL<15415> A_IWL<15414> A_IWL<15413> A_IWL<15412> A_IWL<15411> A_IWL<15410> A_IWL<15409> A_IWL<15408> A_IWL<15407> A_IWL<15406> A_IWL<15405> A_IWL<15404> A_IWL<15403> A_IWL<15402> A_IWL<15401> A_IWL<15400> A_IWL<15399> A_IWL<15398> A_IWL<15397> A_IWL<15396> A_IWL<15395> A_IWL<15394> A_IWL<15393> A_IWL<15392> A_IWL<15391> A_IWL<15390> A_IWL<15389> A_IWL<15388> A_IWL<15387> A_IWL<15386> A_IWL<15385> A_IWL<15384> A_IWL<15383> A_IWL<15382> A_IWL<15381> A_IWL<15380> A_IWL<15379> A_IWL<15378> A_IWL<15377> A_IWL<15376> A_IWL<15375> A_IWL<15374> A_IWL<15373> A_IWL<15372> A_IWL<15371> A_IWL<15370> A_IWL<15369> A_IWL<15368> A_IWL<15367> A_IWL<15366> A_IWL<15365> A_IWL<15364> A_IWL<15363> A_IWL<15362> A_IWL<15361> A_IWL<15360> A_IWL<16383> A_IWL<16382> A_IWL<16381> A_IWL<16380> A_IWL<16379> A_IWL<16378> A_IWL<16377> A_IWL<16376> A_IWL<16375> A_IWL<16374> A_IWL<16373> A_IWL<16372> A_IWL<16371> A_IWL<16370> A_IWL<16369> A_IWL<16368> A_IWL<16367> A_IWL<16366> A_IWL<16365> A_IWL<16364> A_IWL<16363> A_IWL<16362> A_IWL<16361> A_IWL<16360> A_IWL<16359> A_IWL<16358> A_IWL<16357> A_IWL<16356> A_IWL<16355> A_IWL<16354> A_IWL<16353> A_IWL<16352> A_IWL<16351> A_IWL<16350> A_IWL<16349> A_IWL<16348> A_IWL<16347> A_IWL<16346> A_IWL<16345> A_IWL<16344> A_IWL<16343> A_IWL<16342> A_IWL<16341> A_IWL<16340> A_IWL<16339> A_IWL<16338> A_IWL<16337> A_IWL<16336> A_IWL<16335> A_IWL<16334> A_IWL<16333> A_IWL<16332> A_IWL<16331> A_IWL<16330> A_IWL<16329> A_IWL<16328> A_IWL<16327> A_IWL<16326> A_IWL<16325> A_IWL<16324> A_IWL<16323> A_IWL<16322> A_IWL<16321> A_IWL<16320> A_IWL<16319> A_IWL<16318> A_IWL<16317> A_IWL<16316> A_IWL<16315> A_IWL<16314> A_IWL<16313> A_IWL<16312> A_IWL<16311> A_IWL<16310> A_IWL<16309> A_IWL<16308> A_IWL<16307> A_IWL<16306> A_IWL<16305> A_IWL<16304> A_IWL<16303> A_IWL<16302> A_IWL<16301> A_IWL<16300> A_IWL<16299> A_IWL<16298> A_IWL<16297> A_IWL<16296> A_IWL<16295> A_IWL<16294> A_IWL<16293> A_IWL<16292> A_IWL<16291> A_IWL<16290> A_IWL<16289> A_IWL<16288> A_IWL<16287> A_IWL<16286> A_IWL<16285> A_IWL<16284> A_IWL<16283> A_IWL<16282> A_IWL<16281> A_IWL<16280> A_IWL<16279> A_IWL<16278> A_IWL<16277> A_IWL<16276> A_IWL<16275> A_IWL<16274> A_IWL<16273> A_IWL<16272> A_IWL<16271> A_IWL<16270> A_IWL<16269> A_IWL<16268> A_IWL<16267> A_IWL<16266> A_IWL<16265> A_IWL<16264> A_IWL<16263> A_IWL<16262> A_IWL<16261> A_IWL<16260> A_IWL<16259> A_IWL<16258> A_IWL<16257> A_IWL<16256> A_IWL<16255> A_IWL<16254> A_IWL<16253> A_IWL<16252> A_IWL<16251> A_IWL<16250> A_IWL<16249> A_IWL<16248> A_IWL<16247> A_IWL<16246> A_IWL<16245> A_IWL<16244> A_IWL<16243> A_IWL<16242> A_IWL<16241> A_IWL<16240> A_IWL<16239> A_IWL<16238> A_IWL<16237> A_IWL<16236> A_IWL<16235> A_IWL<16234> A_IWL<16233> A_IWL<16232> A_IWL<16231> A_IWL<16230> A_IWL<16229> A_IWL<16228> A_IWL<16227> A_IWL<16226> A_IWL<16225> A_IWL<16224> A_IWL<16223> A_IWL<16222> A_IWL<16221> A_IWL<16220> A_IWL<16219> A_IWL<16218> A_IWL<16217> A_IWL<16216> A_IWL<16215> A_IWL<16214> A_IWL<16213> A_IWL<16212> A_IWL<16211> A_IWL<16210> A_IWL<16209> A_IWL<16208> A_IWL<16207> A_IWL<16206> A_IWL<16205> A_IWL<16204> A_IWL<16203> A_IWL<16202> A_IWL<16201> A_IWL<16200> A_IWL<16199> A_IWL<16198> A_IWL<16197> A_IWL<16196> A_IWL<16195> A_IWL<16194> A_IWL<16193> A_IWL<16192> A_IWL<16191> A_IWL<16190> A_IWL<16189> A_IWL<16188> A_IWL<16187> A_IWL<16186> A_IWL<16185> A_IWL<16184> A_IWL<16183> A_IWL<16182> A_IWL<16181> A_IWL<16180> A_IWL<16179> A_IWL<16178> A_IWL<16177> A_IWL<16176> A_IWL<16175> A_IWL<16174> A_IWL<16173> A_IWL<16172> A_IWL<16171> A_IWL<16170> A_IWL<16169> A_IWL<16168> A_IWL<16167> A_IWL<16166> A_IWL<16165> A_IWL<16164> A_IWL<16163> A_IWL<16162> A_IWL<16161> A_IWL<16160> A_IWL<16159> A_IWL<16158> A_IWL<16157> A_IWL<16156> A_IWL<16155> A_IWL<16154> A_IWL<16153> A_IWL<16152> A_IWL<16151> A_IWL<16150> A_IWL<16149> A_IWL<16148> A_IWL<16147> A_IWL<16146> A_IWL<16145> A_IWL<16144> A_IWL<16143> A_IWL<16142> A_IWL<16141> A_IWL<16140> A_IWL<16139> A_IWL<16138> A_IWL<16137> A_IWL<16136> A_IWL<16135> A_IWL<16134> A_IWL<16133> A_IWL<16132> A_IWL<16131> A_IWL<16130> A_IWL<16129> A_IWL<16128> A_IWL<16127> A_IWL<16126> A_IWL<16125> A_IWL<16124> A_IWL<16123> A_IWL<16122> A_IWL<16121> A_IWL<16120> A_IWL<16119> A_IWL<16118> A_IWL<16117> A_IWL<16116> A_IWL<16115> A_IWL<16114> A_IWL<16113> A_IWL<16112> A_IWL<16111> A_IWL<16110> A_IWL<16109> A_IWL<16108> A_IWL<16107> A_IWL<16106> A_IWL<16105> A_IWL<16104> A_IWL<16103> A_IWL<16102> A_IWL<16101> A_IWL<16100> A_IWL<16099> A_IWL<16098> A_IWL<16097> A_IWL<16096> A_IWL<16095> A_IWL<16094> A_IWL<16093> A_IWL<16092> A_IWL<16091> A_IWL<16090> A_IWL<16089> A_IWL<16088> A_IWL<16087> A_IWL<16086> A_IWL<16085> A_IWL<16084> A_IWL<16083> A_IWL<16082> A_IWL<16081> A_IWL<16080> A_IWL<16079> A_IWL<16078> A_IWL<16077> A_IWL<16076> A_IWL<16075> A_IWL<16074> A_IWL<16073> A_IWL<16072> A_IWL<16071> A_IWL<16070> A_IWL<16069> A_IWL<16068> A_IWL<16067> A_IWL<16066> A_IWL<16065> A_IWL<16064> A_IWL<16063> A_IWL<16062> A_IWL<16061> A_IWL<16060> A_IWL<16059> A_IWL<16058> A_IWL<16057> A_IWL<16056> A_IWL<16055> A_IWL<16054> A_IWL<16053> A_IWL<16052> A_IWL<16051> A_IWL<16050> A_IWL<16049> A_IWL<16048> A_IWL<16047> A_IWL<16046> A_IWL<16045> A_IWL<16044> A_IWL<16043> A_IWL<16042> A_IWL<16041> A_IWL<16040> A_IWL<16039> A_IWL<16038> A_IWL<16037> A_IWL<16036> A_IWL<16035> A_IWL<16034> A_IWL<16033> A_IWL<16032> A_IWL<16031> A_IWL<16030> A_IWL<16029> A_IWL<16028> A_IWL<16027> A_IWL<16026> A_IWL<16025> A_IWL<16024> A_IWL<16023> A_IWL<16022> A_IWL<16021> A_IWL<16020> A_IWL<16019> A_IWL<16018> A_IWL<16017> A_IWL<16016> A_IWL<16015> A_IWL<16014> A_IWL<16013> A_IWL<16012> A_IWL<16011> A_IWL<16010> A_IWL<16009> A_IWL<16008> A_IWL<16007> A_IWL<16006> A_IWL<16005> A_IWL<16004> A_IWL<16003> A_IWL<16002> A_IWL<16001> A_IWL<16000> A_IWL<15999> A_IWL<15998> A_IWL<15997> A_IWL<15996> A_IWL<15995> A_IWL<15994> A_IWL<15993> A_IWL<15992> A_IWL<15991> A_IWL<15990> A_IWL<15989> A_IWL<15988> A_IWL<15987> A_IWL<15986> A_IWL<15985> A_IWL<15984> A_IWL<15983> A_IWL<15982> A_IWL<15981> A_IWL<15980> A_IWL<15979> A_IWL<15978> A_IWL<15977> A_IWL<15976> A_IWL<15975> A_IWL<15974> A_IWL<15973> A_IWL<15972> A_IWL<15971> A_IWL<15970> A_IWL<15969> A_IWL<15968> A_IWL<15967> A_IWL<15966> A_IWL<15965> A_IWL<15964> A_IWL<15963> A_IWL<15962> A_IWL<15961> A_IWL<15960> A_IWL<15959> A_IWL<15958> A_IWL<15957> A_IWL<15956> A_IWL<15955> A_IWL<15954> A_IWL<15953> A_IWL<15952> A_IWL<15951> A_IWL<15950> A_IWL<15949> A_IWL<15948> A_IWL<15947> A_IWL<15946> A_IWL<15945> A_IWL<15944> A_IWL<15943> A_IWL<15942> A_IWL<15941> A_IWL<15940> A_IWL<15939> A_IWL<15938> A_IWL<15937> A_IWL<15936> A_IWL<15935> A_IWL<15934> A_IWL<15933> A_IWL<15932> A_IWL<15931> A_IWL<15930> A_IWL<15929> A_IWL<15928> A_IWL<15927> A_IWL<15926> A_IWL<15925> A_IWL<15924> A_IWL<15923> A_IWL<15922> A_IWL<15921> A_IWL<15920> A_IWL<15919> A_IWL<15918> A_IWL<15917> A_IWL<15916> A_IWL<15915> A_IWL<15914> A_IWL<15913> A_IWL<15912> A_IWL<15911> A_IWL<15910> A_IWL<15909> A_IWL<15908> A_IWL<15907> A_IWL<15906> A_IWL<15905> A_IWL<15904> A_IWL<15903> A_IWL<15902> A_IWL<15901> A_IWL<15900> A_IWL<15899> A_IWL<15898> A_IWL<15897> A_IWL<15896> A_IWL<15895> A_IWL<15894> A_IWL<15893> A_IWL<15892> A_IWL<15891> A_IWL<15890> A_IWL<15889> A_IWL<15888> A_IWL<15887> A_IWL<15886> A_IWL<15885> A_IWL<15884> A_IWL<15883> A_IWL<15882> A_IWL<15881> A_IWL<15880> A_IWL<15879> A_IWL<15878> A_IWL<15877> A_IWL<15876> A_IWL<15875> A_IWL<15874> A_IWL<15873> A_IWL<15872> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_COLUMN_pcell_0 +XCOL<30> A_BLC<61> A_BLC<60> A_BLC_TOP<61> A_BLC_TOP<60> A_BLT<61> A_BLT<60> A_BLT_TOP<61> A_BLT_TOP<60> A_IWL<15359> A_IWL<15358> A_IWL<15357> A_IWL<15356> A_IWL<15355> A_IWL<15354> A_IWL<15353> A_IWL<15352> A_IWL<15351> A_IWL<15350> A_IWL<15349> A_IWL<15348> A_IWL<15347> A_IWL<15346> A_IWL<15345> A_IWL<15344> A_IWL<15343> A_IWL<15342> A_IWL<15341> A_IWL<15340> A_IWL<15339> A_IWL<15338> A_IWL<15337> A_IWL<15336> A_IWL<15335> A_IWL<15334> A_IWL<15333> A_IWL<15332> A_IWL<15331> A_IWL<15330> A_IWL<15329> A_IWL<15328> A_IWL<15327> A_IWL<15326> A_IWL<15325> A_IWL<15324> A_IWL<15323> A_IWL<15322> A_IWL<15321> A_IWL<15320> A_IWL<15319> A_IWL<15318> A_IWL<15317> A_IWL<15316> A_IWL<15315> A_IWL<15314> A_IWL<15313> A_IWL<15312> A_IWL<15311> A_IWL<15310> A_IWL<15309> A_IWL<15308> A_IWL<15307> A_IWL<15306> A_IWL<15305> A_IWL<15304> A_IWL<15303> A_IWL<15302> A_IWL<15301> A_IWL<15300> A_IWL<15299> A_IWL<15298> A_IWL<15297> A_IWL<15296> A_IWL<15295> A_IWL<15294> A_IWL<15293> A_IWL<15292> A_IWL<15291> A_IWL<15290> A_IWL<15289> A_IWL<15288> A_IWL<15287> A_IWL<15286> A_IWL<15285> A_IWL<15284> A_IWL<15283> A_IWL<15282> A_IWL<15281> A_IWL<15280> A_IWL<15279> A_IWL<15278> A_IWL<15277> A_IWL<15276> A_IWL<15275> A_IWL<15274> A_IWL<15273> A_IWL<15272> A_IWL<15271> A_IWL<15270> A_IWL<15269> A_IWL<15268> A_IWL<15267> A_IWL<15266> A_IWL<15265> A_IWL<15264> A_IWL<15263> A_IWL<15262> A_IWL<15261> A_IWL<15260> A_IWL<15259> A_IWL<15258> A_IWL<15257> A_IWL<15256> A_IWL<15255> A_IWL<15254> A_IWL<15253> A_IWL<15252> A_IWL<15251> A_IWL<15250> A_IWL<15249> A_IWL<15248> A_IWL<15247> A_IWL<15246> A_IWL<15245> A_IWL<15244> A_IWL<15243> A_IWL<15242> A_IWL<15241> A_IWL<15240> A_IWL<15239> A_IWL<15238> A_IWL<15237> A_IWL<15236> A_IWL<15235> A_IWL<15234> A_IWL<15233> A_IWL<15232> A_IWL<15231> A_IWL<15230> A_IWL<15229> A_IWL<15228> A_IWL<15227> A_IWL<15226> A_IWL<15225> A_IWL<15224> A_IWL<15223> A_IWL<15222> A_IWL<15221> A_IWL<15220> A_IWL<15219> A_IWL<15218> A_IWL<15217> A_IWL<15216> A_IWL<15215> A_IWL<15214> A_IWL<15213> A_IWL<15212> A_IWL<15211> A_IWL<15210> A_IWL<15209> A_IWL<15208> A_IWL<15207> A_IWL<15206> A_IWL<15205> A_IWL<15204> A_IWL<15203> A_IWL<15202> A_IWL<15201> A_IWL<15200> A_IWL<15199> A_IWL<15198> A_IWL<15197> A_IWL<15196> A_IWL<15195> A_IWL<15194> A_IWL<15193> A_IWL<15192> A_IWL<15191> A_IWL<15190> A_IWL<15189> A_IWL<15188> A_IWL<15187> A_IWL<15186> A_IWL<15185> A_IWL<15184> A_IWL<15183> A_IWL<15182> A_IWL<15181> A_IWL<15180> A_IWL<15179> A_IWL<15178> A_IWL<15177> A_IWL<15176> A_IWL<15175> A_IWL<15174> A_IWL<15173> A_IWL<15172> A_IWL<15171> A_IWL<15170> A_IWL<15169> A_IWL<15168> A_IWL<15167> A_IWL<15166> A_IWL<15165> A_IWL<15164> A_IWL<15163> A_IWL<15162> A_IWL<15161> A_IWL<15160> A_IWL<15159> A_IWL<15158> A_IWL<15157> A_IWL<15156> A_IWL<15155> A_IWL<15154> A_IWL<15153> A_IWL<15152> A_IWL<15151> A_IWL<15150> A_IWL<15149> A_IWL<15148> A_IWL<15147> A_IWL<15146> A_IWL<15145> A_IWL<15144> A_IWL<15143> A_IWL<15142> A_IWL<15141> A_IWL<15140> A_IWL<15139> A_IWL<15138> A_IWL<15137> A_IWL<15136> A_IWL<15135> A_IWL<15134> A_IWL<15133> A_IWL<15132> A_IWL<15131> A_IWL<15130> A_IWL<15129> A_IWL<15128> A_IWL<15127> A_IWL<15126> A_IWL<15125> A_IWL<15124> A_IWL<15123> A_IWL<15122> A_IWL<15121> A_IWL<15120> A_IWL<15119> A_IWL<15118> A_IWL<15117> A_IWL<15116> A_IWL<15115> A_IWL<15114> A_IWL<15113> A_IWL<15112> A_IWL<15111> A_IWL<15110> A_IWL<15109> A_IWL<15108> A_IWL<15107> A_IWL<15106> A_IWL<15105> A_IWL<15104> A_IWL<15103> A_IWL<15102> A_IWL<15101> A_IWL<15100> A_IWL<15099> A_IWL<15098> A_IWL<15097> A_IWL<15096> A_IWL<15095> A_IWL<15094> A_IWL<15093> A_IWL<15092> A_IWL<15091> A_IWL<15090> A_IWL<15089> A_IWL<15088> A_IWL<15087> A_IWL<15086> A_IWL<15085> A_IWL<15084> A_IWL<15083> A_IWL<15082> A_IWL<15081> A_IWL<15080> A_IWL<15079> A_IWL<15078> A_IWL<15077> A_IWL<15076> A_IWL<15075> A_IWL<15074> A_IWL<15073> A_IWL<15072> A_IWL<15071> A_IWL<15070> A_IWL<15069> A_IWL<15068> A_IWL<15067> A_IWL<15066> A_IWL<15065> A_IWL<15064> A_IWL<15063> A_IWL<15062> A_IWL<15061> A_IWL<15060> A_IWL<15059> A_IWL<15058> A_IWL<15057> A_IWL<15056> A_IWL<15055> A_IWL<15054> A_IWL<15053> A_IWL<15052> A_IWL<15051> A_IWL<15050> A_IWL<15049> A_IWL<15048> A_IWL<15047> A_IWL<15046> A_IWL<15045> A_IWL<15044> A_IWL<15043> A_IWL<15042> A_IWL<15041> A_IWL<15040> A_IWL<15039> A_IWL<15038> A_IWL<15037> A_IWL<15036> A_IWL<15035> A_IWL<15034> A_IWL<15033> A_IWL<15032> A_IWL<15031> A_IWL<15030> A_IWL<15029> A_IWL<15028> A_IWL<15027> A_IWL<15026> A_IWL<15025> A_IWL<15024> A_IWL<15023> A_IWL<15022> A_IWL<15021> A_IWL<15020> A_IWL<15019> A_IWL<15018> A_IWL<15017> A_IWL<15016> A_IWL<15015> A_IWL<15014> A_IWL<15013> A_IWL<15012> A_IWL<15011> A_IWL<15010> A_IWL<15009> A_IWL<15008> A_IWL<15007> A_IWL<15006> A_IWL<15005> A_IWL<15004> A_IWL<15003> A_IWL<15002> A_IWL<15001> A_IWL<15000> A_IWL<14999> A_IWL<14998> A_IWL<14997> A_IWL<14996> A_IWL<14995> A_IWL<14994> A_IWL<14993> A_IWL<14992> A_IWL<14991> A_IWL<14990> A_IWL<14989> A_IWL<14988> A_IWL<14987> A_IWL<14986> A_IWL<14985> A_IWL<14984> A_IWL<14983> A_IWL<14982> A_IWL<14981> A_IWL<14980> A_IWL<14979> A_IWL<14978> A_IWL<14977> A_IWL<14976> A_IWL<14975> A_IWL<14974> A_IWL<14973> A_IWL<14972> A_IWL<14971> A_IWL<14970> A_IWL<14969> A_IWL<14968> A_IWL<14967> A_IWL<14966> A_IWL<14965> A_IWL<14964> A_IWL<14963> A_IWL<14962> A_IWL<14961> A_IWL<14960> A_IWL<14959> A_IWL<14958> A_IWL<14957> A_IWL<14956> A_IWL<14955> A_IWL<14954> A_IWL<14953> A_IWL<14952> A_IWL<14951> A_IWL<14950> A_IWL<14949> A_IWL<14948> A_IWL<14947> A_IWL<14946> A_IWL<14945> A_IWL<14944> A_IWL<14943> A_IWL<14942> A_IWL<14941> A_IWL<14940> A_IWL<14939> A_IWL<14938> A_IWL<14937> A_IWL<14936> A_IWL<14935> A_IWL<14934> A_IWL<14933> A_IWL<14932> A_IWL<14931> A_IWL<14930> A_IWL<14929> A_IWL<14928> A_IWL<14927> A_IWL<14926> A_IWL<14925> A_IWL<14924> A_IWL<14923> A_IWL<14922> A_IWL<14921> A_IWL<14920> A_IWL<14919> A_IWL<14918> A_IWL<14917> A_IWL<14916> A_IWL<14915> A_IWL<14914> A_IWL<14913> A_IWL<14912> A_IWL<14911> A_IWL<14910> A_IWL<14909> A_IWL<14908> A_IWL<14907> A_IWL<14906> A_IWL<14905> A_IWL<14904> A_IWL<14903> A_IWL<14902> A_IWL<14901> A_IWL<14900> A_IWL<14899> A_IWL<14898> A_IWL<14897> A_IWL<14896> A_IWL<14895> A_IWL<14894> A_IWL<14893> A_IWL<14892> A_IWL<14891> A_IWL<14890> A_IWL<14889> A_IWL<14888> A_IWL<14887> A_IWL<14886> A_IWL<14885> A_IWL<14884> A_IWL<14883> A_IWL<14882> A_IWL<14881> A_IWL<14880> A_IWL<14879> A_IWL<14878> A_IWL<14877> A_IWL<14876> A_IWL<14875> A_IWL<14874> A_IWL<14873> A_IWL<14872> A_IWL<14871> A_IWL<14870> A_IWL<14869> A_IWL<14868> A_IWL<14867> A_IWL<14866> A_IWL<14865> A_IWL<14864> A_IWL<14863> A_IWL<14862> A_IWL<14861> A_IWL<14860> A_IWL<14859> A_IWL<14858> A_IWL<14857> A_IWL<14856> A_IWL<14855> A_IWL<14854> A_IWL<14853> A_IWL<14852> A_IWL<14851> A_IWL<14850> A_IWL<14849> A_IWL<14848> A_IWL<15871> A_IWL<15870> A_IWL<15869> A_IWL<15868> A_IWL<15867> A_IWL<15866> A_IWL<15865> A_IWL<15864> A_IWL<15863> A_IWL<15862> A_IWL<15861> A_IWL<15860> A_IWL<15859> A_IWL<15858> A_IWL<15857> A_IWL<15856> A_IWL<15855> A_IWL<15854> A_IWL<15853> A_IWL<15852> A_IWL<15851> A_IWL<15850> A_IWL<15849> A_IWL<15848> A_IWL<15847> A_IWL<15846> A_IWL<15845> A_IWL<15844> A_IWL<15843> A_IWL<15842> A_IWL<15841> A_IWL<15840> A_IWL<15839> A_IWL<15838> A_IWL<15837> A_IWL<15836> A_IWL<15835> A_IWL<15834> A_IWL<15833> A_IWL<15832> A_IWL<15831> A_IWL<15830> A_IWL<15829> A_IWL<15828> A_IWL<15827> A_IWL<15826> A_IWL<15825> A_IWL<15824> A_IWL<15823> A_IWL<15822> A_IWL<15821> A_IWL<15820> A_IWL<15819> A_IWL<15818> A_IWL<15817> A_IWL<15816> A_IWL<15815> A_IWL<15814> A_IWL<15813> A_IWL<15812> A_IWL<15811> A_IWL<15810> A_IWL<15809> A_IWL<15808> A_IWL<15807> A_IWL<15806> A_IWL<15805> A_IWL<15804> A_IWL<15803> A_IWL<15802> A_IWL<15801> A_IWL<15800> A_IWL<15799> A_IWL<15798> A_IWL<15797> A_IWL<15796> A_IWL<15795> A_IWL<15794> A_IWL<15793> A_IWL<15792> A_IWL<15791> A_IWL<15790> A_IWL<15789> A_IWL<15788> A_IWL<15787> A_IWL<15786> A_IWL<15785> A_IWL<15784> A_IWL<15783> A_IWL<15782> A_IWL<15781> A_IWL<15780> A_IWL<15779> A_IWL<15778> A_IWL<15777> A_IWL<15776> A_IWL<15775> A_IWL<15774> A_IWL<15773> A_IWL<15772> A_IWL<15771> A_IWL<15770> A_IWL<15769> A_IWL<15768> A_IWL<15767> A_IWL<15766> A_IWL<15765> A_IWL<15764> A_IWL<15763> A_IWL<15762> A_IWL<15761> A_IWL<15760> A_IWL<15759> A_IWL<15758> A_IWL<15757> A_IWL<15756> A_IWL<15755> A_IWL<15754> A_IWL<15753> A_IWL<15752> A_IWL<15751> A_IWL<15750> A_IWL<15749> A_IWL<15748> A_IWL<15747> A_IWL<15746> A_IWL<15745> A_IWL<15744> A_IWL<15743> A_IWL<15742> A_IWL<15741> A_IWL<15740> A_IWL<15739> A_IWL<15738> A_IWL<15737> A_IWL<15736> A_IWL<15735> A_IWL<15734> A_IWL<15733> A_IWL<15732> A_IWL<15731> A_IWL<15730> A_IWL<15729> A_IWL<15728> A_IWL<15727> A_IWL<15726> A_IWL<15725> A_IWL<15724> A_IWL<15723> A_IWL<15722> A_IWL<15721> A_IWL<15720> A_IWL<15719> A_IWL<15718> A_IWL<15717> A_IWL<15716> A_IWL<15715> A_IWL<15714> A_IWL<15713> A_IWL<15712> A_IWL<15711> A_IWL<15710> A_IWL<15709> A_IWL<15708> A_IWL<15707> A_IWL<15706> A_IWL<15705> A_IWL<15704> A_IWL<15703> A_IWL<15702> A_IWL<15701> A_IWL<15700> A_IWL<15699> A_IWL<15698> A_IWL<15697> A_IWL<15696> A_IWL<15695> A_IWL<15694> A_IWL<15693> A_IWL<15692> A_IWL<15691> A_IWL<15690> A_IWL<15689> A_IWL<15688> A_IWL<15687> A_IWL<15686> A_IWL<15685> A_IWL<15684> A_IWL<15683> A_IWL<15682> A_IWL<15681> A_IWL<15680> A_IWL<15679> A_IWL<15678> A_IWL<15677> A_IWL<15676> A_IWL<15675> A_IWL<15674> A_IWL<15673> A_IWL<15672> A_IWL<15671> A_IWL<15670> A_IWL<15669> A_IWL<15668> A_IWL<15667> A_IWL<15666> A_IWL<15665> A_IWL<15664> A_IWL<15663> A_IWL<15662> A_IWL<15661> A_IWL<15660> A_IWL<15659> A_IWL<15658> A_IWL<15657> A_IWL<15656> A_IWL<15655> A_IWL<15654> A_IWL<15653> A_IWL<15652> A_IWL<15651> A_IWL<15650> A_IWL<15649> A_IWL<15648> A_IWL<15647> A_IWL<15646> A_IWL<15645> A_IWL<15644> A_IWL<15643> A_IWL<15642> A_IWL<15641> A_IWL<15640> A_IWL<15639> A_IWL<15638> A_IWL<15637> A_IWL<15636> A_IWL<15635> A_IWL<15634> A_IWL<15633> A_IWL<15632> A_IWL<15631> A_IWL<15630> A_IWL<15629> A_IWL<15628> A_IWL<15627> A_IWL<15626> A_IWL<15625> A_IWL<15624> A_IWL<15623> A_IWL<15622> A_IWL<15621> A_IWL<15620> A_IWL<15619> A_IWL<15618> A_IWL<15617> A_IWL<15616> A_IWL<15615> A_IWL<15614> A_IWL<15613> A_IWL<15612> A_IWL<15611> A_IWL<15610> A_IWL<15609> A_IWL<15608> A_IWL<15607> A_IWL<15606> A_IWL<15605> A_IWL<15604> A_IWL<15603> A_IWL<15602> A_IWL<15601> A_IWL<15600> A_IWL<15599> A_IWL<15598> A_IWL<15597> A_IWL<15596> A_IWL<15595> A_IWL<15594> A_IWL<15593> A_IWL<15592> A_IWL<15591> A_IWL<15590> A_IWL<15589> A_IWL<15588> A_IWL<15587> A_IWL<15586> A_IWL<15585> A_IWL<15584> A_IWL<15583> A_IWL<15582> A_IWL<15581> A_IWL<15580> A_IWL<15579> A_IWL<15578> A_IWL<15577> A_IWL<15576> A_IWL<15575> A_IWL<15574> A_IWL<15573> A_IWL<15572> A_IWL<15571> A_IWL<15570> A_IWL<15569> A_IWL<15568> A_IWL<15567> A_IWL<15566> A_IWL<15565> A_IWL<15564> A_IWL<15563> A_IWL<15562> A_IWL<15561> A_IWL<15560> A_IWL<15559> A_IWL<15558> A_IWL<15557> A_IWL<15556> A_IWL<15555> A_IWL<15554> A_IWL<15553> A_IWL<15552> A_IWL<15551> A_IWL<15550> A_IWL<15549> A_IWL<15548> A_IWL<15547> A_IWL<15546> A_IWL<15545> A_IWL<15544> A_IWL<15543> A_IWL<15542> A_IWL<15541> A_IWL<15540> A_IWL<15539> A_IWL<15538> A_IWL<15537> A_IWL<15536> A_IWL<15535> A_IWL<15534> A_IWL<15533> A_IWL<15532> A_IWL<15531> A_IWL<15530> A_IWL<15529> A_IWL<15528> A_IWL<15527> A_IWL<15526> A_IWL<15525> A_IWL<15524> A_IWL<15523> A_IWL<15522> A_IWL<15521> A_IWL<15520> A_IWL<15519> A_IWL<15518> A_IWL<15517> A_IWL<15516> A_IWL<15515> A_IWL<15514> A_IWL<15513> A_IWL<15512> A_IWL<15511> A_IWL<15510> A_IWL<15509> A_IWL<15508> A_IWL<15507> A_IWL<15506> A_IWL<15505> A_IWL<15504> A_IWL<15503> A_IWL<15502> A_IWL<15501> A_IWL<15500> A_IWL<15499> A_IWL<15498> A_IWL<15497> A_IWL<15496> A_IWL<15495> A_IWL<15494> A_IWL<15493> A_IWL<15492> A_IWL<15491> A_IWL<15490> A_IWL<15489> A_IWL<15488> A_IWL<15487> A_IWL<15486> A_IWL<15485> A_IWL<15484> A_IWL<15483> A_IWL<15482> A_IWL<15481> A_IWL<15480> A_IWL<15479> A_IWL<15478> A_IWL<15477> A_IWL<15476> A_IWL<15475> A_IWL<15474> A_IWL<15473> A_IWL<15472> A_IWL<15471> A_IWL<15470> A_IWL<15469> A_IWL<15468> A_IWL<15467> A_IWL<15466> A_IWL<15465> A_IWL<15464> A_IWL<15463> A_IWL<15462> A_IWL<15461> A_IWL<15460> A_IWL<15459> A_IWL<15458> A_IWL<15457> A_IWL<15456> A_IWL<15455> A_IWL<15454> A_IWL<15453> A_IWL<15452> A_IWL<15451> A_IWL<15450> A_IWL<15449> A_IWL<15448> A_IWL<15447> A_IWL<15446> A_IWL<15445> A_IWL<15444> A_IWL<15443> A_IWL<15442> A_IWL<15441> A_IWL<15440> A_IWL<15439> A_IWL<15438> A_IWL<15437> A_IWL<15436> A_IWL<15435> A_IWL<15434> A_IWL<15433> A_IWL<15432> A_IWL<15431> A_IWL<15430> A_IWL<15429> A_IWL<15428> A_IWL<15427> A_IWL<15426> A_IWL<15425> A_IWL<15424> A_IWL<15423> A_IWL<15422> A_IWL<15421> A_IWL<15420> A_IWL<15419> A_IWL<15418> A_IWL<15417> A_IWL<15416> A_IWL<15415> A_IWL<15414> A_IWL<15413> A_IWL<15412> A_IWL<15411> A_IWL<15410> A_IWL<15409> A_IWL<15408> A_IWL<15407> A_IWL<15406> A_IWL<15405> A_IWL<15404> A_IWL<15403> A_IWL<15402> A_IWL<15401> A_IWL<15400> A_IWL<15399> A_IWL<15398> A_IWL<15397> A_IWL<15396> A_IWL<15395> A_IWL<15394> A_IWL<15393> A_IWL<15392> A_IWL<15391> A_IWL<15390> A_IWL<15389> A_IWL<15388> A_IWL<15387> A_IWL<15386> A_IWL<15385> A_IWL<15384> A_IWL<15383> A_IWL<15382> A_IWL<15381> A_IWL<15380> A_IWL<15379> A_IWL<15378> A_IWL<15377> A_IWL<15376> A_IWL<15375> A_IWL<15374> A_IWL<15373> A_IWL<15372> A_IWL<15371> A_IWL<15370> A_IWL<15369> A_IWL<15368> A_IWL<15367> A_IWL<15366> A_IWL<15365> A_IWL<15364> A_IWL<15363> A_IWL<15362> A_IWL<15361> A_IWL<15360> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_COLUMN_pcell_0 +XCOL<29> A_BLC<59> A_BLC<58> A_BLC_TOP<59> A_BLC_TOP<58> A_BLT<59> A_BLT<58> A_BLT_TOP<59> A_BLT_TOP<58> A_IWL<14847> A_IWL<14846> A_IWL<14845> A_IWL<14844> A_IWL<14843> A_IWL<14842> A_IWL<14841> A_IWL<14840> A_IWL<14839> A_IWL<14838> A_IWL<14837> A_IWL<14836> A_IWL<14835> A_IWL<14834> A_IWL<14833> A_IWL<14832> A_IWL<14831> A_IWL<14830> A_IWL<14829> A_IWL<14828> A_IWL<14827> A_IWL<14826> A_IWL<14825> A_IWL<14824> A_IWL<14823> A_IWL<14822> A_IWL<14821> A_IWL<14820> A_IWL<14819> A_IWL<14818> A_IWL<14817> A_IWL<14816> A_IWL<14815> A_IWL<14814> A_IWL<14813> A_IWL<14812> A_IWL<14811> A_IWL<14810> A_IWL<14809> A_IWL<14808> A_IWL<14807> A_IWL<14806> A_IWL<14805> A_IWL<14804> A_IWL<14803> A_IWL<14802> A_IWL<14801> A_IWL<14800> A_IWL<14799> A_IWL<14798> A_IWL<14797> A_IWL<14796> A_IWL<14795> A_IWL<14794> A_IWL<14793> A_IWL<14792> A_IWL<14791> A_IWL<14790> A_IWL<14789> A_IWL<14788> A_IWL<14787> A_IWL<14786> A_IWL<14785> A_IWL<14784> A_IWL<14783> A_IWL<14782> A_IWL<14781> A_IWL<14780> A_IWL<14779> A_IWL<14778> A_IWL<14777> A_IWL<14776> A_IWL<14775> A_IWL<14774> A_IWL<14773> A_IWL<14772> A_IWL<14771> A_IWL<14770> A_IWL<14769> A_IWL<14768> A_IWL<14767> A_IWL<14766> A_IWL<14765> A_IWL<14764> A_IWL<14763> A_IWL<14762> A_IWL<14761> A_IWL<14760> A_IWL<14759> A_IWL<14758> A_IWL<14757> A_IWL<14756> A_IWL<14755> A_IWL<14754> A_IWL<14753> A_IWL<14752> A_IWL<14751> A_IWL<14750> A_IWL<14749> A_IWL<14748> A_IWL<14747> A_IWL<14746> A_IWL<14745> A_IWL<14744> A_IWL<14743> A_IWL<14742> A_IWL<14741> A_IWL<14740> A_IWL<14739> A_IWL<14738> A_IWL<14737> A_IWL<14736> A_IWL<14735> A_IWL<14734> A_IWL<14733> A_IWL<14732> A_IWL<14731> A_IWL<14730> A_IWL<14729> A_IWL<14728> A_IWL<14727> A_IWL<14726> A_IWL<14725> A_IWL<14724> A_IWL<14723> A_IWL<14722> A_IWL<14721> A_IWL<14720> A_IWL<14719> A_IWL<14718> A_IWL<14717> A_IWL<14716> A_IWL<14715> A_IWL<14714> A_IWL<14713> A_IWL<14712> A_IWL<14711> A_IWL<14710> A_IWL<14709> A_IWL<14708> A_IWL<14707> A_IWL<14706> A_IWL<14705> A_IWL<14704> A_IWL<14703> A_IWL<14702> A_IWL<14701> A_IWL<14700> A_IWL<14699> A_IWL<14698> A_IWL<14697> A_IWL<14696> A_IWL<14695> A_IWL<14694> A_IWL<14693> A_IWL<14692> A_IWL<14691> A_IWL<14690> A_IWL<14689> A_IWL<14688> A_IWL<14687> A_IWL<14686> A_IWL<14685> A_IWL<14684> A_IWL<14683> A_IWL<14682> A_IWL<14681> A_IWL<14680> A_IWL<14679> A_IWL<14678> A_IWL<14677> A_IWL<14676> A_IWL<14675> A_IWL<14674> A_IWL<14673> A_IWL<14672> A_IWL<14671> A_IWL<14670> A_IWL<14669> A_IWL<14668> A_IWL<14667> A_IWL<14666> A_IWL<14665> A_IWL<14664> A_IWL<14663> A_IWL<14662> A_IWL<14661> A_IWL<14660> A_IWL<14659> A_IWL<14658> A_IWL<14657> A_IWL<14656> A_IWL<14655> A_IWL<14654> A_IWL<14653> A_IWL<14652> A_IWL<14651> A_IWL<14650> A_IWL<14649> A_IWL<14648> A_IWL<14647> A_IWL<14646> A_IWL<14645> A_IWL<14644> A_IWL<14643> A_IWL<14642> A_IWL<14641> A_IWL<14640> A_IWL<14639> A_IWL<14638> A_IWL<14637> A_IWL<14636> A_IWL<14635> A_IWL<14634> A_IWL<14633> A_IWL<14632> A_IWL<14631> A_IWL<14630> A_IWL<14629> A_IWL<14628> A_IWL<14627> A_IWL<14626> A_IWL<14625> A_IWL<14624> A_IWL<14623> A_IWL<14622> A_IWL<14621> A_IWL<14620> A_IWL<14619> A_IWL<14618> A_IWL<14617> A_IWL<14616> A_IWL<14615> A_IWL<14614> A_IWL<14613> A_IWL<14612> A_IWL<14611> A_IWL<14610> A_IWL<14609> A_IWL<14608> A_IWL<14607> A_IWL<14606> A_IWL<14605> A_IWL<14604> A_IWL<14603> A_IWL<14602> A_IWL<14601> A_IWL<14600> A_IWL<14599> A_IWL<14598> A_IWL<14597> A_IWL<14596> A_IWL<14595> A_IWL<14594> A_IWL<14593> A_IWL<14592> A_IWL<14591> A_IWL<14590> A_IWL<14589> A_IWL<14588> A_IWL<14587> A_IWL<14586> A_IWL<14585> A_IWL<14584> A_IWL<14583> A_IWL<14582> A_IWL<14581> A_IWL<14580> A_IWL<14579> A_IWL<14578> A_IWL<14577> A_IWL<14576> A_IWL<14575> A_IWL<14574> A_IWL<14573> A_IWL<14572> A_IWL<14571> A_IWL<14570> A_IWL<14569> A_IWL<14568> A_IWL<14567> A_IWL<14566> A_IWL<14565> A_IWL<14564> A_IWL<14563> A_IWL<14562> A_IWL<14561> A_IWL<14560> A_IWL<14559> A_IWL<14558> A_IWL<14557> A_IWL<14556> A_IWL<14555> A_IWL<14554> A_IWL<14553> A_IWL<14552> A_IWL<14551> A_IWL<14550> A_IWL<14549> A_IWL<14548> A_IWL<14547> A_IWL<14546> A_IWL<14545> A_IWL<14544> A_IWL<14543> A_IWL<14542> A_IWL<14541> A_IWL<14540> A_IWL<14539> A_IWL<14538> A_IWL<14537> A_IWL<14536> A_IWL<14535> A_IWL<14534> A_IWL<14533> A_IWL<14532> A_IWL<14531> A_IWL<14530> A_IWL<14529> A_IWL<14528> A_IWL<14527> A_IWL<14526> A_IWL<14525> A_IWL<14524> A_IWL<14523> A_IWL<14522> A_IWL<14521> A_IWL<14520> A_IWL<14519> A_IWL<14518> A_IWL<14517> A_IWL<14516> A_IWL<14515> A_IWL<14514> A_IWL<14513> A_IWL<14512> A_IWL<14511> A_IWL<14510> A_IWL<14509> A_IWL<14508> A_IWL<14507> A_IWL<14506> A_IWL<14505> A_IWL<14504> A_IWL<14503> A_IWL<14502> A_IWL<14501> A_IWL<14500> A_IWL<14499> A_IWL<14498> A_IWL<14497> A_IWL<14496> A_IWL<14495> A_IWL<14494> A_IWL<14493> A_IWL<14492> A_IWL<14491> A_IWL<14490> A_IWL<14489> A_IWL<14488> A_IWL<14487> A_IWL<14486> A_IWL<14485> A_IWL<14484> A_IWL<14483> A_IWL<14482> A_IWL<14481> A_IWL<14480> A_IWL<14479> A_IWL<14478> A_IWL<14477> A_IWL<14476> A_IWL<14475> A_IWL<14474> A_IWL<14473> A_IWL<14472> A_IWL<14471> A_IWL<14470> A_IWL<14469> A_IWL<14468> A_IWL<14467> A_IWL<14466> A_IWL<14465> A_IWL<14464> A_IWL<14463> A_IWL<14462> A_IWL<14461> A_IWL<14460> A_IWL<14459> A_IWL<14458> A_IWL<14457> A_IWL<14456> A_IWL<14455> A_IWL<14454> A_IWL<14453> A_IWL<14452> A_IWL<14451> A_IWL<14450> A_IWL<14449> A_IWL<14448> A_IWL<14447> A_IWL<14446> A_IWL<14445> A_IWL<14444> A_IWL<14443> A_IWL<14442> A_IWL<14441> A_IWL<14440> A_IWL<14439> A_IWL<14438> A_IWL<14437> A_IWL<14436> A_IWL<14435> A_IWL<14434> A_IWL<14433> A_IWL<14432> A_IWL<14431> A_IWL<14430> A_IWL<14429> A_IWL<14428> A_IWL<14427> A_IWL<14426> A_IWL<14425> A_IWL<14424> A_IWL<14423> A_IWL<14422> A_IWL<14421> A_IWL<14420> A_IWL<14419> A_IWL<14418> A_IWL<14417> A_IWL<14416> A_IWL<14415> A_IWL<14414> A_IWL<14413> A_IWL<14412> A_IWL<14411> A_IWL<14410> A_IWL<14409> A_IWL<14408> A_IWL<14407> A_IWL<14406> A_IWL<14405> A_IWL<14404> A_IWL<14403> A_IWL<14402> A_IWL<14401> A_IWL<14400> A_IWL<14399> A_IWL<14398> A_IWL<14397> A_IWL<14396> A_IWL<14395> A_IWL<14394> A_IWL<14393> A_IWL<14392> A_IWL<14391> A_IWL<14390> A_IWL<14389> A_IWL<14388> A_IWL<14387> A_IWL<14386> A_IWL<14385> A_IWL<14384> A_IWL<14383> A_IWL<14382> A_IWL<14381> A_IWL<14380> A_IWL<14379> A_IWL<14378> A_IWL<14377> A_IWL<14376> A_IWL<14375> A_IWL<14374> A_IWL<14373> A_IWL<14372> A_IWL<14371> A_IWL<14370> A_IWL<14369> A_IWL<14368> A_IWL<14367> A_IWL<14366> A_IWL<14365> A_IWL<14364> A_IWL<14363> A_IWL<14362> A_IWL<14361> A_IWL<14360> A_IWL<14359> A_IWL<14358> A_IWL<14357> A_IWL<14356> A_IWL<14355> A_IWL<14354> A_IWL<14353> A_IWL<14352> A_IWL<14351> A_IWL<14350> A_IWL<14349> A_IWL<14348> A_IWL<14347> A_IWL<14346> A_IWL<14345> A_IWL<14344> A_IWL<14343> A_IWL<14342> A_IWL<14341> A_IWL<14340> A_IWL<14339> A_IWL<14338> A_IWL<14337> A_IWL<14336> A_IWL<15359> A_IWL<15358> A_IWL<15357> A_IWL<15356> A_IWL<15355> A_IWL<15354> A_IWL<15353> A_IWL<15352> A_IWL<15351> A_IWL<15350> A_IWL<15349> A_IWL<15348> A_IWL<15347> A_IWL<15346> A_IWL<15345> A_IWL<15344> A_IWL<15343> A_IWL<15342> A_IWL<15341> A_IWL<15340> A_IWL<15339> A_IWL<15338> A_IWL<15337> A_IWL<15336> A_IWL<15335> A_IWL<15334> A_IWL<15333> A_IWL<15332> A_IWL<15331> A_IWL<15330> A_IWL<15329> A_IWL<15328> A_IWL<15327> A_IWL<15326> A_IWL<15325> A_IWL<15324> A_IWL<15323> A_IWL<15322> A_IWL<15321> A_IWL<15320> A_IWL<15319> A_IWL<15318> A_IWL<15317> A_IWL<15316> A_IWL<15315> A_IWL<15314> A_IWL<15313> A_IWL<15312> A_IWL<15311> A_IWL<15310> A_IWL<15309> A_IWL<15308> A_IWL<15307> A_IWL<15306> A_IWL<15305> A_IWL<15304> A_IWL<15303> A_IWL<15302> A_IWL<15301> A_IWL<15300> A_IWL<15299> A_IWL<15298> A_IWL<15297> A_IWL<15296> A_IWL<15295> A_IWL<15294> A_IWL<15293> A_IWL<15292> A_IWL<15291> A_IWL<15290> A_IWL<15289> A_IWL<15288> A_IWL<15287> A_IWL<15286> A_IWL<15285> A_IWL<15284> A_IWL<15283> A_IWL<15282> A_IWL<15281> A_IWL<15280> A_IWL<15279> A_IWL<15278> A_IWL<15277> A_IWL<15276> A_IWL<15275> A_IWL<15274> A_IWL<15273> A_IWL<15272> A_IWL<15271> A_IWL<15270> A_IWL<15269> A_IWL<15268> A_IWL<15267> A_IWL<15266> A_IWL<15265> A_IWL<15264> A_IWL<15263> A_IWL<15262> A_IWL<15261> A_IWL<15260> A_IWL<15259> A_IWL<15258> A_IWL<15257> A_IWL<15256> A_IWL<15255> A_IWL<15254> A_IWL<15253> A_IWL<15252> A_IWL<15251> A_IWL<15250> A_IWL<15249> A_IWL<15248> A_IWL<15247> A_IWL<15246> A_IWL<15245> A_IWL<15244> A_IWL<15243> A_IWL<15242> A_IWL<15241> A_IWL<15240> A_IWL<15239> A_IWL<15238> A_IWL<15237> A_IWL<15236> A_IWL<15235> A_IWL<15234> A_IWL<15233> A_IWL<15232> A_IWL<15231> A_IWL<15230> A_IWL<15229> A_IWL<15228> A_IWL<15227> A_IWL<15226> A_IWL<15225> A_IWL<15224> A_IWL<15223> A_IWL<15222> A_IWL<15221> A_IWL<15220> A_IWL<15219> A_IWL<15218> A_IWL<15217> A_IWL<15216> A_IWL<15215> A_IWL<15214> A_IWL<15213> A_IWL<15212> A_IWL<15211> A_IWL<15210> A_IWL<15209> A_IWL<15208> A_IWL<15207> A_IWL<15206> A_IWL<15205> A_IWL<15204> A_IWL<15203> A_IWL<15202> A_IWL<15201> A_IWL<15200> A_IWL<15199> A_IWL<15198> A_IWL<15197> A_IWL<15196> A_IWL<15195> A_IWL<15194> A_IWL<15193> A_IWL<15192> A_IWL<15191> A_IWL<15190> A_IWL<15189> A_IWL<15188> A_IWL<15187> A_IWL<15186> A_IWL<15185> A_IWL<15184> A_IWL<15183> A_IWL<15182> A_IWL<15181> A_IWL<15180> A_IWL<15179> A_IWL<15178> A_IWL<15177> A_IWL<15176> A_IWL<15175> A_IWL<15174> A_IWL<15173> A_IWL<15172> A_IWL<15171> A_IWL<15170> A_IWL<15169> A_IWL<15168> A_IWL<15167> A_IWL<15166> A_IWL<15165> A_IWL<15164> A_IWL<15163> A_IWL<15162> A_IWL<15161> A_IWL<15160> A_IWL<15159> A_IWL<15158> A_IWL<15157> A_IWL<15156> A_IWL<15155> A_IWL<15154> A_IWL<15153> A_IWL<15152> A_IWL<15151> A_IWL<15150> A_IWL<15149> A_IWL<15148> A_IWL<15147> A_IWL<15146> A_IWL<15145> A_IWL<15144> A_IWL<15143> A_IWL<15142> A_IWL<15141> A_IWL<15140> A_IWL<15139> A_IWL<15138> A_IWL<15137> A_IWL<15136> A_IWL<15135> A_IWL<15134> A_IWL<15133> A_IWL<15132> A_IWL<15131> A_IWL<15130> A_IWL<15129> A_IWL<15128> A_IWL<15127> A_IWL<15126> A_IWL<15125> A_IWL<15124> A_IWL<15123> A_IWL<15122> A_IWL<15121> A_IWL<15120> A_IWL<15119> A_IWL<15118> A_IWL<15117> A_IWL<15116> A_IWL<15115> A_IWL<15114> A_IWL<15113> A_IWL<15112> A_IWL<15111> A_IWL<15110> A_IWL<15109> A_IWL<15108> A_IWL<15107> A_IWL<15106> A_IWL<15105> A_IWL<15104> A_IWL<15103> A_IWL<15102> A_IWL<15101> A_IWL<15100> A_IWL<15099> A_IWL<15098> A_IWL<15097> A_IWL<15096> A_IWL<15095> A_IWL<15094> A_IWL<15093> A_IWL<15092> A_IWL<15091> A_IWL<15090> A_IWL<15089> A_IWL<15088> A_IWL<15087> A_IWL<15086> A_IWL<15085> A_IWL<15084> A_IWL<15083> A_IWL<15082> A_IWL<15081> A_IWL<15080> A_IWL<15079> A_IWL<15078> A_IWL<15077> A_IWL<15076> A_IWL<15075> A_IWL<15074> A_IWL<15073> A_IWL<15072> A_IWL<15071> A_IWL<15070> A_IWL<15069> A_IWL<15068> A_IWL<15067> A_IWL<15066> A_IWL<15065> A_IWL<15064> A_IWL<15063> A_IWL<15062> A_IWL<15061> A_IWL<15060> A_IWL<15059> A_IWL<15058> A_IWL<15057> A_IWL<15056> A_IWL<15055> A_IWL<15054> A_IWL<15053> A_IWL<15052> A_IWL<15051> A_IWL<15050> A_IWL<15049> A_IWL<15048> A_IWL<15047> A_IWL<15046> A_IWL<15045> A_IWL<15044> A_IWL<15043> A_IWL<15042> A_IWL<15041> A_IWL<15040> A_IWL<15039> A_IWL<15038> A_IWL<15037> A_IWL<15036> A_IWL<15035> A_IWL<15034> A_IWL<15033> A_IWL<15032> A_IWL<15031> A_IWL<15030> A_IWL<15029> A_IWL<15028> A_IWL<15027> A_IWL<15026> A_IWL<15025> A_IWL<15024> A_IWL<15023> A_IWL<15022> A_IWL<15021> A_IWL<15020> A_IWL<15019> A_IWL<15018> A_IWL<15017> A_IWL<15016> A_IWL<15015> A_IWL<15014> A_IWL<15013> A_IWL<15012> A_IWL<15011> A_IWL<15010> A_IWL<15009> A_IWL<15008> A_IWL<15007> A_IWL<15006> A_IWL<15005> A_IWL<15004> A_IWL<15003> A_IWL<15002> A_IWL<15001> A_IWL<15000> A_IWL<14999> A_IWL<14998> A_IWL<14997> A_IWL<14996> A_IWL<14995> A_IWL<14994> A_IWL<14993> A_IWL<14992> A_IWL<14991> A_IWL<14990> A_IWL<14989> A_IWL<14988> A_IWL<14987> A_IWL<14986> A_IWL<14985> A_IWL<14984> A_IWL<14983> A_IWL<14982> A_IWL<14981> A_IWL<14980> A_IWL<14979> A_IWL<14978> A_IWL<14977> A_IWL<14976> A_IWL<14975> A_IWL<14974> A_IWL<14973> A_IWL<14972> A_IWL<14971> A_IWL<14970> A_IWL<14969> A_IWL<14968> A_IWL<14967> A_IWL<14966> A_IWL<14965> A_IWL<14964> A_IWL<14963> A_IWL<14962> A_IWL<14961> A_IWL<14960> A_IWL<14959> A_IWL<14958> A_IWL<14957> A_IWL<14956> A_IWL<14955> A_IWL<14954> A_IWL<14953> A_IWL<14952> A_IWL<14951> A_IWL<14950> A_IWL<14949> A_IWL<14948> A_IWL<14947> A_IWL<14946> A_IWL<14945> A_IWL<14944> A_IWL<14943> A_IWL<14942> A_IWL<14941> A_IWL<14940> A_IWL<14939> A_IWL<14938> A_IWL<14937> A_IWL<14936> A_IWL<14935> A_IWL<14934> A_IWL<14933> A_IWL<14932> A_IWL<14931> A_IWL<14930> A_IWL<14929> A_IWL<14928> A_IWL<14927> A_IWL<14926> A_IWL<14925> A_IWL<14924> A_IWL<14923> A_IWL<14922> A_IWL<14921> A_IWL<14920> A_IWL<14919> A_IWL<14918> A_IWL<14917> A_IWL<14916> A_IWL<14915> A_IWL<14914> A_IWL<14913> A_IWL<14912> A_IWL<14911> A_IWL<14910> A_IWL<14909> A_IWL<14908> A_IWL<14907> A_IWL<14906> A_IWL<14905> A_IWL<14904> A_IWL<14903> A_IWL<14902> A_IWL<14901> A_IWL<14900> A_IWL<14899> A_IWL<14898> A_IWL<14897> A_IWL<14896> A_IWL<14895> A_IWL<14894> A_IWL<14893> A_IWL<14892> A_IWL<14891> A_IWL<14890> A_IWL<14889> A_IWL<14888> A_IWL<14887> A_IWL<14886> A_IWL<14885> A_IWL<14884> A_IWL<14883> A_IWL<14882> A_IWL<14881> A_IWL<14880> A_IWL<14879> A_IWL<14878> A_IWL<14877> A_IWL<14876> A_IWL<14875> A_IWL<14874> A_IWL<14873> A_IWL<14872> A_IWL<14871> A_IWL<14870> A_IWL<14869> A_IWL<14868> A_IWL<14867> A_IWL<14866> A_IWL<14865> A_IWL<14864> A_IWL<14863> A_IWL<14862> A_IWL<14861> A_IWL<14860> A_IWL<14859> A_IWL<14858> A_IWL<14857> A_IWL<14856> A_IWL<14855> A_IWL<14854> A_IWL<14853> A_IWL<14852> A_IWL<14851> A_IWL<14850> A_IWL<14849> A_IWL<14848> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_COLUMN_pcell_0 +XCOL<28> A_BLC<57> A_BLC<56> A_BLC_TOP<57> A_BLC_TOP<56> A_BLT<57> A_BLT<56> A_BLT_TOP<57> A_BLT_TOP<56> A_IWL<14335> A_IWL<14334> A_IWL<14333> A_IWL<14332> A_IWL<14331> A_IWL<14330> A_IWL<14329> A_IWL<14328> A_IWL<14327> A_IWL<14326> A_IWL<14325> A_IWL<14324> A_IWL<14323> A_IWL<14322> A_IWL<14321> A_IWL<14320> A_IWL<14319> A_IWL<14318> A_IWL<14317> A_IWL<14316> A_IWL<14315> A_IWL<14314> A_IWL<14313> A_IWL<14312> A_IWL<14311> A_IWL<14310> A_IWL<14309> A_IWL<14308> A_IWL<14307> A_IWL<14306> A_IWL<14305> A_IWL<14304> A_IWL<14303> A_IWL<14302> A_IWL<14301> A_IWL<14300> A_IWL<14299> A_IWL<14298> A_IWL<14297> A_IWL<14296> A_IWL<14295> A_IWL<14294> A_IWL<14293> A_IWL<14292> A_IWL<14291> A_IWL<14290> A_IWL<14289> A_IWL<14288> A_IWL<14287> A_IWL<14286> A_IWL<14285> A_IWL<14284> A_IWL<14283> A_IWL<14282> A_IWL<14281> A_IWL<14280> A_IWL<14279> A_IWL<14278> A_IWL<14277> A_IWL<14276> A_IWL<14275> A_IWL<14274> A_IWL<14273> A_IWL<14272> A_IWL<14271> A_IWL<14270> A_IWL<14269> A_IWL<14268> A_IWL<14267> A_IWL<14266> A_IWL<14265> A_IWL<14264> A_IWL<14263> A_IWL<14262> A_IWL<14261> A_IWL<14260> A_IWL<14259> A_IWL<14258> A_IWL<14257> A_IWL<14256> A_IWL<14255> A_IWL<14254> A_IWL<14253> A_IWL<14252> A_IWL<14251> A_IWL<14250> A_IWL<14249> A_IWL<14248> A_IWL<14247> A_IWL<14246> A_IWL<14245> A_IWL<14244> A_IWL<14243> A_IWL<14242> A_IWL<14241> A_IWL<14240> A_IWL<14239> A_IWL<14238> A_IWL<14237> A_IWL<14236> A_IWL<14235> A_IWL<14234> A_IWL<14233> A_IWL<14232> A_IWL<14231> A_IWL<14230> A_IWL<14229> A_IWL<14228> A_IWL<14227> A_IWL<14226> A_IWL<14225> A_IWL<14224> A_IWL<14223> A_IWL<14222> A_IWL<14221> A_IWL<14220> A_IWL<14219> A_IWL<14218> A_IWL<14217> A_IWL<14216> A_IWL<14215> A_IWL<14214> A_IWL<14213> A_IWL<14212> A_IWL<14211> A_IWL<14210> A_IWL<14209> A_IWL<14208> A_IWL<14207> A_IWL<14206> A_IWL<14205> A_IWL<14204> A_IWL<14203> A_IWL<14202> A_IWL<14201> A_IWL<14200> A_IWL<14199> A_IWL<14198> A_IWL<14197> A_IWL<14196> A_IWL<14195> A_IWL<14194> A_IWL<14193> A_IWL<14192> A_IWL<14191> A_IWL<14190> A_IWL<14189> A_IWL<14188> A_IWL<14187> A_IWL<14186> A_IWL<14185> A_IWL<14184> A_IWL<14183> A_IWL<14182> A_IWL<14181> A_IWL<14180> A_IWL<14179> A_IWL<14178> A_IWL<14177> A_IWL<14176> A_IWL<14175> A_IWL<14174> A_IWL<14173> A_IWL<14172> A_IWL<14171> A_IWL<14170> A_IWL<14169> A_IWL<14168> A_IWL<14167> A_IWL<14166> A_IWL<14165> A_IWL<14164> A_IWL<14163> A_IWL<14162> A_IWL<14161> A_IWL<14160> A_IWL<14159> A_IWL<14158> A_IWL<14157> A_IWL<14156> A_IWL<14155> A_IWL<14154> A_IWL<14153> A_IWL<14152> A_IWL<14151> A_IWL<14150> A_IWL<14149> A_IWL<14148> A_IWL<14147> A_IWL<14146> A_IWL<14145> A_IWL<14144> A_IWL<14143> A_IWL<14142> A_IWL<14141> A_IWL<14140> A_IWL<14139> A_IWL<14138> A_IWL<14137> A_IWL<14136> A_IWL<14135> A_IWL<14134> A_IWL<14133> A_IWL<14132> A_IWL<14131> A_IWL<14130> A_IWL<14129> A_IWL<14128> A_IWL<14127> A_IWL<14126> A_IWL<14125> A_IWL<14124> A_IWL<14123> A_IWL<14122> A_IWL<14121> A_IWL<14120> A_IWL<14119> A_IWL<14118> A_IWL<14117> A_IWL<14116> A_IWL<14115> A_IWL<14114> A_IWL<14113> A_IWL<14112> A_IWL<14111> A_IWL<14110> A_IWL<14109> A_IWL<14108> A_IWL<14107> A_IWL<14106> A_IWL<14105> A_IWL<14104> A_IWL<14103> A_IWL<14102> A_IWL<14101> A_IWL<14100> A_IWL<14099> A_IWL<14098> A_IWL<14097> A_IWL<14096> A_IWL<14095> A_IWL<14094> A_IWL<14093> A_IWL<14092> A_IWL<14091> A_IWL<14090> A_IWL<14089> A_IWL<14088> A_IWL<14087> A_IWL<14086> A_IWL<14085> A_IWL<14084> A_IWL<14083> A_IWL<14082> A_IWL<14081> A_IWL<14080> A_IWL<14079> A_IWL<14078> A_IWL<14077> A_IWL<14076> A_IWL<14075> A_IWL<14074> A_IWL<14073> A_IWL<14072> A_IWL<14071> A_IWL<14070> A_IWL<14069> A_IWL<14068> A_IWL<14067> A_IWL<14066> A_IWL<14065> A_IWL<14064> A_IWL<14063> A_IWL<14062> A_IWL<14061> A_IWL<14060> A_IWL<14059> A_IWL<14058> A_IWL<14057> A_IWL<14056> A_IWL<14055> A_IWL<14054> A_IWL<14053> A_IWL<14052> A_IWL<14051> A_IWL<14050> A_IWL<14049> A_IWL<14048> A_IWL<14047> A_IWL<14046> A_IWL<14045> A_IWL<14044> A_IWL<14043> A_IWL<14042> A_IWL<14041> A_IWL<14040> A_IWL<14039> A_IWL<14038> A_IWL<14037> A_IWL<14036> A_IWL<14035> A_IWL<14034> A_IWL<14033> A_IWL<14032> A_IWL<14031> A_IWL<14030> A_IWL<14029> A_IWL<14028> A_IWL<14027> A_IWL<14026> A_IWL<14025> A_IWL<14024> A_IWL<14023> A_IWL<14022> A_IWL<14021> A_IWL<14020> A_IWL<14019> A_IWL<14018> A_IWL<14017> A_IWL<14016> A_IWL<14015> A_IWL<14014> A_IWL<14013> A_IWL<14012> A_IWL<14011> A_IWL<14010> A_IWL<14009> A_IWL<14008> A_IWL<14007> A_IWL<14006> A_IWL<14005> A_IWL<14004> A_IWL<14003> A_IWL<14002> A_IWL<14001> A_IWL<14000> A_IWL<13999> A_IWL<13998> A_IWL<13997> A_IWL<13996> A_IWL<13995> A_IWL<13994> A_IWL<13993> A_IWL<13992> A_IWL<13991> A_IWL<13990> A_IWL<13989> A_IWL<13988> A_IWL<13987> A_IWL<13986> A_IWL<13985> A_IWL<13984> A_IWL<13983> A_IWL<13982> A_IWL<13981> A_IWL<13980> A_IWL<13979> A_IWL<13978> A_IWL<13977> A_IWL<13976> A_IWL<13975> A_IWL<13974> A_IWL<13973> A_IWL<13972> A_IWL<13971> A_IWL<13970> A_IWL<13969> A_IWL<13968> A_IWL<13967> A_IWL<13966> A_IWL<13965> A_IWL<13964> A_IWL<13963> A_IWL<13962> A_IWL<13961> A_IWL<13960> A_IWL<13959> A_IWL<13958> A_IWL<13957> A_IWL<13956> A_IWL<13955> A_IWL<13954> A_IWL<13953> A_IWL<13952> A_IWL<13951> A_IWL<13950> A_IWL<13949> A_IWL<13948> A_IWL<13947> A_IWL<13946> A_IWL<13945> A_IWL<13944> A_IWL<13943> A_IWL<13942> A_IWL<13941> A_IWL<13940> A_IWL<13939> A_IWL<13938> A_IWL<13937> A_IWL<13936> A_IWL<13935> A_IWL<13934> A_IWL<13933> A_IWL<13932> A_IWL<13931> A_IWL<13930> A_IWL<13929> A_IWL<13928> A_IWL<13927> A_IWL<13926> A_IWL<13925> A_IWL<13924> A_IWL<13923> A_IWL<13922> A_IWL<13921> A_IWL<13920> A_IWL<13919> A_IWL<13918> A_IWL<13917> A_IWL<13916> A_IWL<13915> A_IWL<13914> A_IWL<13913> A_IWL<13912> A_IWL<13911> A_IWL<13910> A_IWL<13909> A_IWL<13908> A_IWL<13907> A_IWL<13906> A_IWL<13905> A_IWL<13904> A_IWL<13903> A_IWL<13902> A_IWL<13901> A_IWL<13900> A_IWL<13899> A_IWL<13898> A_IWL<13897> A_IWL<13896> A_IWL<13895> A_IWL<13894> A_IWL<13893> A_IWL<13892> A_IWL<13891> A_IWL<13890> A_IWL<13889> A_IWL<13888> A_IWL<13887> A_IWL<13886> A_IWL<13885> A_IWL<13884> A_IWL<13883> A_IWL<13882> A_IWL<13881> A_IWL<13880> A_IWL<13879> A_IWL<13878> A_IWL<13877> A_IWL<13876> A_IWL<13875> A_IWL<13874> A_IWL<13873> A_IWL<13872> A_IWL<13871> A_IWL<13870> A_IWL<13869> A_IWL<13868> A_IWL<13867> A_IWL<13866> A_IWL<13865> A_IWL<13864> A_IWL<13863> A_IWL<13862> A_IWL<13861> A_IWL<13860> A_IWL<13859> A_IWL<13858> A_IWL<13857> A_IWL<13856> A_IWL<13855> A_IWL<13854> A_IWL<13853> A_IWL<13852> A_IWL<13851> A_IWL<13850> A_IWL<13849> A_IWL<13848> A_IWL<13847> A_IWL<13846> A_IWL<13845> A_IWL<13844> A_IWL<13843> A_IWL<13842> A_IWL<13841> A_IWL<13840> A_IWL<13839> A_IWL<13838> A_IWL<13837> A_IWL<13836> A_IWL<13835> A_IWL<13834> A_IWL<13833> A_IWL<13832> A_IWL<13831> A_IWL<13830> A_IWL<13829> A_IWL<13828> A_IWL<13827> A_IWL<13826> A_IWL<13825> A_IWL<13824> A_IWL<14847> A_IWL<14846> A_IWL<14845> A_IWL<14844> A_IWL<14843> A_IWL<14842> A_IWL<14841> A_IWL<14840> A_IWL<14839> A_IWL<14838> A_IWL<14837> A_IWL<14836> A_IWL<14835> A_IWL<14834> A_IWL<14833> A_IWL<14832> A_IWL<14831> A_IWL<14830> A_IWL<14829> A_IWL<14828> A_IWL<14827> A_IWL<14826> A_IWL<14825> A_IWL<14824> A_IWL<14823> A_IWL<14822> A_IWL<14821> A_IWL<14820> A_IWL<14819> A_IWL<14818> A_IWL<14817> A_IWL<14816> A_IWL<14815> A_IWL<14814> A_IWL<14813> A_IWL<14812> A_IWL<14811> A_IWL<14810> A_IWL<14809> A_IWL<14808> A_IWL<14807> A_IWL<14806> A_IWL<14805> A_IWL<14804> A_IWL<14803> A_IWL<14802> A_IWL<14801> A_IWL<14800> A_IWL<14799> A_IWL<14798> A_IWL<14797> A_IWL<14796> A_IWL<14795> A_IWL<14794> A_IWL<14793> A_IWL<14792> A_IWL<14791> A_IWL<14790> A_IWL<14789> A_IWL<14788> A_IWL<14787> A_IWL<14786> A_IWL<14785> A_IWL<14784> A_IWL<14783> A_IWL<14782> A_IWL<14781> A_IWL<14780> A_IWL<14779> A_IWL<14778> A_IWL<14777> A_IWL<14776> A_IWL<14775> A_IWL<14774> A_IWL<14773> A_IWL<14772> A_IWL<14771> A_IWL<14770> A_IWL<14769> A_IWL<14768> A_IWL<14767> A_IWL<14766> A_IWL<14765> A_IWL<14764> A_IWL<14763> A_IWL<14762> A_IWL<14761> A_IWL<14760> A_IWL<14759> A_IWL<14758> A_IWL<14757> A_IWL<14756> A_IWL<14755> A_IWL<14754> A_IWL<14753> A_IWL<14752> A_IWL<14751> A_IWL<14750> A_IWL<14749> A_IWL<14748> A_IWL<14747> A_IWL<14746> A_IWL<14745> A_IWL<14744> A_IWL<14743> A_IWL<14742> A_IWL<14741> A_IWL<14740> A_IWL<14739> A_IWL<14738> A_IWL<14737> A_IWL<14736> A_IWL<14735> A_IWL<14734> A_IWL<14733> A_IWL<14732> A_IWL<14731> A_IWL<14730> A_IWL<14729> A_IWL<14728> A_IWL<14727> A_IWL<14726> A_IWL<14725> A_IWL<14724> A_IWL<14723> A_IWL<14722> A_IWL<14721> A_IWL<14720> A_IWL<14719> A_IWL<14718> A_IWL<14717> A_IWL<14716> A_IWL<14715> A_IWL<14714> A_IWL<14713> A_IWL<14712> A_IWL<14711> A_IWL<14710> A_IWL<14709> A_IWL<14708> A_IWL<14707> A_IWL<14706> A_IWL<14705> A_IWL<14704> A_IWL<14703> A_IWL<14702> A_IWL<14701> A_IWL<14700> A_IWL<14699> A_IWL<14698> A_IWL<14697> A_IWL<14696> A_IWL<14695> A_IWL<14694> A_IWL<14693> A_IWL<14692> A_IWL<14691> A_IWL<14690> A_IWL<14689> A_IWL<14688> A_IWL<14687> A_IWL<14686> A_IWL<14685> A_IWL<14684> A_IWL<14683> A_IWL<14682> A_IWL<14681> A_IWL<14680> A_IWL<14679> A_IWL<14678> A_IWL<14677> A_IWL<14676> A_IWL<14675> A_IWL<14674> A_IWL<14673> A_IWL<14672> A_IWL<14671> A_IWL<14670> A_IWL<14669> A_IWL<14668> A_IWL<14667> A_IWL<14666> A_IWL<14665> A_IWL<14664> A_IWL<14663> A_IWL<14662> A_IWL<14661> A_IWL<14660> A_IWL<14659> A_IWL<14658> A_IWL<14657> A_IWL<14656> A_IWL<14655> A_IWL<14654> A_IWL<14653> A_IWL<14652> A_IWL<14651> A_IWL<14650> A_IWL<14649> A_IWL<14648> A_IWL<14647> A_IWL<14646> A_IWL<14645> A_IWL<14644> A_IWL<14643> A_IWL<14642> A_IWL<14641> A_IWL<14640> A_IWL<14639> A_IWL<14638> A_IWL<14637> A_IWL<14636> A_IWL<14635> A_IWL<14634> A_IWL<14633> A_IWL<14632> A_IWL<14631> A_IWL<14630> A_IWL<14629> A_IWL<14628> A_IWL<14627> A_IWL<14626> A_IWL<14625> A_IWL<14624> A_IWL<14623> A_IWL<14622> A_IWL<14621> A_IWL<14620> A_IWL<14619> A_IWL<14618> A_IWL<14617> A_IWL<14616> A_IWL<14615> A_IWL<14614> A_IWL<14613> A_IWL<14612> A_IWL<14611> A_IWL<14610> A_IWL<14609> A_IWL<14608> A_IWL<14607> A_IWL<14606> A_IWL<14605> A_IWL<14604> A_IWL<14603> A_IWL<14602> A_IWL<14601> A_IWL<14600> A_IWL<14599> A_IWL<14598> A_IWL<14597> A_IWL<14596> A_IWL<14595> A_IWL<14594> A_IWL<14593> A_IWL<14592> A_IWL<14591> A_IWL<14590> A_IWL<14589> A_IWL<14588> A_IWL<14587> A_IWL<14586> A_IWL<14585> A_IWL<14584> A_IWL<14583> A_IWL<14582> A_IWL<14581> A_IWL<14580> A_IWL<14579> A_IWL<14578> A_IWL<14577> A_IWL<14576> A_IWL<14575> A_IWL<14574> A_IWL<14573> A_IWL<14572> A_IWL<14571> A_IWL<14570> A_IWL<14569> A_IWL<14568> A_IWL<14567> A_IWL<14566> A_IWL<14565> A_IWL<14564> A_IWL<14563> A_IWL<14562> A_IWL<14561> A_IWL<14560> A_IWL<14559> A_IWL<14558> A_IWL<14557> A_IWL<14556> A_IWL<14555> A_IWL<14554> A_IWL<14553> A_IWL<14552> A_IWL<14551> A_IWL<14550> A_IWL<14549> A_IWL<14548> A_IWL<14547> A_IWL<14546> A_IWL<14545> A_IWL<14544> A_IWL<14543> A_IWL<14542> A_IWL<14541> A_IWL<14540> A_IWL<14539> A_IWL<14538> A_IWL<14537> A_IWL<14536> A_IWL<14535> A_IWL<14534> A_IWL<14533> A_IWL<14532> A_IWL<14531> A_IWL<14530> A_IWL<14529> A_IWL<14528> A_IWL<14527> A_IWL<14526> A_IWL<14525> A_IWL<14524> A_IWL<14523> A_IWL<14522> A_IWL<14521> A_IWL<14520> A_IWL<14519> A_IWL<14518> A_IWL<14517> A_IWL<14516> A_IWL<14515> A_IWL<14514> A_IWL<14513> A_IWL<14512> A_IWL<14511> A_IWL<14510> A_IWL<14509> A_IWL<14508> A_IWL<14507> A_IWL<14506> A_IWL<14505> A_IWL<14504> A_IWL<14503> A_IWL<14502> A_IWL<14501> A_IWL<14500> A_IWL<14499> A_IWL<14498> A_IWL<14497> A_IWL<14496> A_IWL<14495> A_IWL<14494> A_IWL<14493> A_IWL<14492> A_IWL<14491> A_IWL<14490> A_IWL<14489> A_IWL<14488> A_IWL<14487> A_IWL<14486> A_IWL<14485> A_IWL<14484> A_IWL<14483> A_IWL<14482> A_IWL<14481> A_IWL<14480> A_IWL<14479> A_IWL<14478> A_IWL<14477> A_IWL<14476> A_IWL<14475> A_IWL<14474> A_IWL<14473> A_IWL<14472> A_IWL<14471> A_IWL<14470> A_IWL<14469> A_IWL<14468> A_IWL<14467> A_IWL<14466> A_IWL<14465> A_IWL<14464> A_IWL<14463> A_IWL<14462> A_IWL<14461> A_IWL<14460> A_IWL<14459> A_IWL<14458> A_IWL<14457> A_IWL<14456> A_IWL<14455> A_IWL<14454> A_IWL<14453> A_IWL<14452> A_IWL<14451> A_IWL<14450> A_IWL<14449> A_IWL<14448> A_IWL<14447> A_IWL<14446> A_IWL<14445> A_IWL<14444> A_IWL<14443> A_IWL<14442> A_IWL<14441> A_IWL<14440> A_IWL<14439> A_IWL<14438> A_IWL<14437> A_IWL<14436> A_IWL<14435> A_IWL<14434> A_IWL<14433> A_IWL<14432> A_IWL<14431> A_IWL<14430> A_IWL<14429> A_IWL<14428> A_IWL<14427> A_IWL<14426> A_IWL<14425> A_IWL<14424> A_IWL<14423> A_IWL<14422> A_IWL<14421> A_IWL<14420> A_IWL<14419> A_IWL<14418> A_IWL<14417> A_IWL<14416> A_IWL<14415> A_IWL<14414> A_IWL<14413> A_IWL<14412> A_IWL<14411> A_IWL<14410> A_IWL<14409> A_IWL<14408> A_IWL<14407> A_IWL<14406> A_IWL<14405> A_IWL<14404> A_IWL<14403> A_IWL<14402> A_IWL<14401> A_IWL<14400> A_IWL<14399> A_IWL<14398> A_IWL<14397> A_IWL<14396> A_IWL<14395> A_IWL<14394> A_IWL<14393> A_IWL<14392> A_IWL<14391> A_IWL<14390> A_IWL<14389> A_IWL<14388> A_IWL<14387> A_IWL<14386> A_IWL<14385> A_IWL<14384> A_IWL<14383> A_IWL<14382> A_IWL<14381> A_IWL<14380> A_IWL<14379> A_IWL<14378> A_IWL<14377> A_IWL<14376> A_IWL<14375> A_IWL<14374> A_IWL<14373> A_IWL<14372> A_IWL<14371> A_IWL<14370> A_IWL<14369> A_IWL<14368> A_IWL<14367> A_IWL<14366> A_IWL<14365> A_IWL<14364> A_IWL<14363> A_IWL<14362> A_IWL<14361> A_IWL<14360> A_IWL<14359> A_IWL<14358> A_IWL<14357> A_IWL<14356> A_IWL<14355> A_IWL<14354> A_IWL<14353> A_IWL<14352> A_IWL<14351> A_IWL<14350> A_IWL<14349> A_IWL<14348> A_IWL<14347> A_IWL<14346> A_IWL<14345> A_IWL<14344> A_IWL<14343> A_IWL<14342> A_IWL<14341> A_IWL<14340> A_IWL<14339> A_IWL<14338> A_IWL<14337> A_IWL<14336> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_COLUMN_pcell_0 +XCOL<27> A_BLC<55> A_BLC<54> A_BLC_TOP<55> A_BLC_TOP<54> A_BLT<55> A_BLT<54> A_BLT_TOP<55> A_BLT_TOP<54> A_IWL<13823> A_IWL<13822> A_IWL<13821> A_IWL<13820> A_IWL<13819> A_IWL<13818> A_IWL<13817> A_IWL<13816> A_IWL<13815> A_IWL<13814> A_IWL<13813> A_IWL<13812> A_IWL<13811> A_IWL<13810> A_IWL<13809> A_IWL<13808> A_IWL<13807> A_IWL<13806> A_IWL<13805> A_IWL<13804> A_IWL<13803> A_IWL<13802> A_IWL<13801> A_IWL<13800> A_IWL<13799> A_IWL<13798> A_IWL<13797> A_IWL<13796> A_IWL<13795> A_IWL<13794> A_IWL<13793> A_IWL<13792> A_IWL<13791> A_IWL<13790> A_IWL<13789> A_IWL<13788> A_IWL<13787> A_IWL<13786> A_IWL<13785> A_IWL<13784> A_IWL<13783> A_IWL<13782> A_IWL<13781> A_IWL<13780> A_IWL<13779> A_IWL<13778> A_IWL<13777> A_IWL<13776> A_IWL<13775> A_IWL<13774> A_IWL<13773> A_IWL<13772> A_IWL<13771> A_IWL<13770> A_IWL<13769> A_IWL<13768> A_IWL<13767> A_IWL<13766> A_IWL<13765> A_IWL<13764> A_IWL<13763> A_IWL<13762> A_IWL<13761> A_IWL<13760> A_IWL<13759> A_IWL<13758> A_IWL<13757> A_IWL<13756> A_IWL<13755> A_IWL<13754> A_IWL<13753> A_IWL<13752> A_IWL<13751> A_IWL<13750> A_IWL<13749> A_IWL<13748> A_IWL<13747> A_IWL<13746> A_IWL<13745> A_IWL<13744> A_IWL<13743> A_IWL<13742> A_IWL<13741> A_IWL<13740> A_IWL<13739> A_IWL<13738> A_IWL<13737> A_IWL<13736> A_IWL<13735> A_IWL<13734> A_IWL<13733> A_IWL<13732> A_IWL<13731> A_IWL<13730> A_IWL<13729> A_IWL<13728> A_IWL<13727> A_IWL<13726> A_IWL<13725> A_IWL<13724> A_IWL<13723> A_IWL<13722> A_IWL<13721> A_IWL<13720> A_IWL<13719> A_IWL<13718> A_IWL<13717> A_IWL<13716> A_IWL<13715> A_IWL<13714> A_IWL<13713> A_IWL<13712> A_IWL<13711> A_IWL<13710> A_IWL<13709> A_IWL<13708> A_IWL<13707> A_IWL<13706> A_IWL<13705> A_IWL<13704> A_IWL<13703> A_IWL<13702> A_IWL<13701> A_IWL<13700> A_IWL<13699> A_IWL<13698> A_IWL<13697> A_IWL<13696> A_IWL<13695> A_IWL<13694> A_IWL<13693> A_IWL<13692> A_IWL<13691> A_IWL<13690> A_IWL<13689> A_IWL<13688> A_IWL<13687> A_IWL<13686> A_IWL<13685> A_IWL<13684> A_IWL<13683> A_IWL<13682> A_IWL<13681> A_IWL<13680> A_IWL<13679> A_IWL<13678> A_IWL<13677> A_IWL<13676> A_IWL<13675> A_IWL<13674> A_IWL<13673> A_IWL<13672> A_IWL<13671> A_IWL<13670> A_IWL<13669> A_IWL<13668> A_IWL<13667> A_IWL<13666> A_IWL<13665> A_IWL<13664> A_IWL<13663> A_IWL<13662> A_IWL<13661> A_IWL<13660> A_IWL<13659> A_IWL<13658> A_IWL<13657> A_IWL<13656> A_IWL<13655> A_IWL<13654> A_IWL<13653> A_IWL<13652> A_IWL<13651> A_IWL<13650> A_IWL<13649> A_IWL<13648> A_IWL<13647> A_IWL<13646> A_IWL<13645> A_IWL<13644> A_IWL<13643> A_IWL<13642> A_IWL<13641> A_IWL<13640> A_IWL<13639> A_IWL<13638> A_IWL<13637> A_IWL<13636> A_IWL<13635> A_IWL<13634> A_IWL<13633> A_IWL<13632> A_IWL<13631> A_IWL<13630> A_IWL<13629> A_IWL<13628> A_IWL<13627> A_IWL<13626> A_IWL<13625> A_IWL<13624> A_IWL<13623> A_IWL<13622> A_IWL<13621> A_IWL<13620> A_IWL<13619> A_IWL<13618> A_IWL<13617> A_IWL<13616> A_IWL<13615> A_IWL<13614> A_IWL<13613> A_IWL<13612> A_IWL<13611> A_IWL<13610> A_IWL<13609> A_IWL<13608> A_IWL<13607> A_IWL<13606> A_IWL<13605> A_IWL<13604> A_IWL<13603> A_IWL<13602> A_IWL<13601> A_IWL<13600> A_IWL<13599> A_IWL<13598> A_IWL<13597> A_IWL<13596> A_IWL<13595> A_IWL<13594> A_IWL<13593> A_IWL<13592> A_IWL<13591> A_IWL<13590> A_IWL<13589> A_IWL<13588> A_IWL<13587> A_IWL<13586> A_IWL<13585> A_IWL<13584> A_IWL<13583> A_IWL<13582> A_IWL<13581> A_IWL<13580> A_IWL<13579> A_IWL<13578> A_IWL<13577> A_IWL<13576> A_IWL<13575> A_IWL<13574> A_IWL<13573> A_IWL<13572> A_IWL<13571> A_IWL<13570> A_IWL<13569> A_IWL<13568> A_IWL<13567> A_IWL<13566> A_IWL<13565> A_IWL<13564> A_IWL<13563> A_IWL<13562> A_IWL<13561> A_IWL<13560> A_IWL<13559> A_IWL<13558> A_IWL<13557> A_IWL<13556> A_IWL<13555> A_IWL<13554> A_IWL<13553> A_IWL<13552> A_IWL<13551> A_IWL<13550> A_IWL<13549> A_IWL<13548> A_IWL<13547> A_IWL<13546> A_IWL<13545> A_IWL<13544> A_IWL<13543> A_IWL<13542> A_IWL<13541> A_IWL<13540> A_IWL<13539> A_IWL<13538> A_IWL<13537> A_IWL<13536> A_IWL<13535> A_IWL<13534> A_IWL<13533> A_IWL<13532> A_IWL<13531> A_IWL<13530> A_IWL<13529> A_IWL<13528> A_IWL<13527> A_IWL<13526> A_IWL<13525> A_IWL<13524> A_IWL<13523> A_IWL<13522> A_IWL<13521> A_IWL<13520> A_IWL<13519> A_IWL<13518> A_IWL<13517> A_IWL<13516> A_IWL<13515> A_IWL<13514> A_IWL<13513> A_IWL<13512> A_IWL<13511> A_IWL<13510> A_IWL<13509> A_IWL<13508> A_IWL<13507> A_IWL<13506> A_IWL<13505> A_IWL<13504> A_IWL<13503> A_IWL<13502> A_IWL<13501> A_IWL<13500> A_IWL<13499> A_IWL<13498> A_IWL<13497> A_IWL<13496> A_IWL<13495> A_IWL<13494> A_IWL<13493> A_IWL<13492> A_IWL<13491> A_IWL<13490> A_IWL<13489> A_IWL<13488> A_IWL<13487> A_IWL<13486> A_IWL<13485> A_IWL<13484> A_IWL<13483> A_IWL<13482> A_IWL<13481> A_IWL<13480> A_IWL<13479> A_IWL<13478> A_IWL<13477> A_IWL<13476> A_IWL<13475> A_IWL<13474> A_IWL<13473> A_IWL<13472> A_IWL<13471> A_IWL<13470> A_IWL<13469> A_IWL<13468> A_IWL<13467> A_IWL<13466> A_IWL<13465> A_IWL<13464> A_IWL<13463> A_IWL<13462> A_IWL<13461> A_IWL<13460> A_IWL<13459> A_IWL<13458> A_IWL<13457> A_IWL<13456> A_IWL<13455> A_IWL<13454> A_IWL<13453> A_IWL<13452> A_IWL<13451> A_IWL<13450> A_IWL<13449> A_IWL<13448> A_IWL<13447> A_IWL<13446> A_IWL<13445> A_IWL<13444> A_IWL<13443> A_IWL<13442> A_IWL<13441> A_IWL<13440> A_IWL<13439> A_IWL<13438> A_IWL<13437> A_IWL<13436> A_IWL<13435> A_IWL<13434> A_IWL<13433> A_IWL<13432> A_IWL<13431> A_IWL<13430> A_IWL<13429> A_IWL<13428> A_IWL<13427> A_IWL<13426> A_IWL<13425> A_IWL<13424> A_IWL<13423> A_IWL<13422> A_IWL<13421> A_IWL<13420> A_IWL<13419> A_IWL<13418> A_IWL<13417> A_IWL<13416> A_IWL<13415> A_IWL<13414> A_IWL<13413> A_IWL<13412> A_IWL<13411> A_IWL<13410> A_IWL<13409> A_IWL<13408> A_IWL<13407> A_IWL<13406> A_IWL<13405> A_IWL<13404> A_IWL<13403> A_IWL<13402> A_IWL<13401> A_IWL<13400> A_IWL<13399> A_IWL<13398> A_IWL<13397> A_IWL<13396> A_IWL<13395> A_IWL<13394> A_IWL<13393> A_IWL<13392> A_IWL<13391> A_IWL<13390> A_IWL<13389> A_IWL<13388> A_IWL<13387> A_IWL<13386> A_IWL<13385> A_IWL<13384> A_IWL<13383> A_IWL<13382> A_IWL<13381> A_IWL<13380> A_IWL<13379> A_IWL<13378> A_IWL<13377> A_IWL<13376> A_IWL<13375> A_IWL<13374> A_IWL<13373> A_IWL<13372> A_IWL<13371> A_IWL<13370> A_IWL<13369> A_IWL<13368> A_IWL<13367> A_IWL<13366> A_IWL<13365> A_IWL<13364> A_IWL<13363> A_IWL<13362> A_IWL<13361> A_IWL<13360> A_IWL<13359> A_IWL<13358> A_IWL<13357> A_IWL<13356> A_IWL<13355> A_IWL<13354> A_IWL<13353> A_IWL<13352> A_IWL<13351> A_IWL<13350> A_IWL<13349> A_IWL<13348> A_IWL<13347> A_IWL<13346> A_IWL<13345> A_IWL<13344> A_IWL<13343> A_IWL<13342> A_IWL<13341> A_IWL<13340> A_IWL<13339> A_IWL<13338> A_IWL<13337> A_IWL<13336> A_IWL<13335> A_IWL<13334> A_IWL<13333> A_IWL<13332> A_IWL<13331> A_IWL<13330> A_IWL<13329> A_IWL<13328> A_IWL<13327> A_IWL<13326> A_IWL<13325> A_IWL<13324> A_IWL<13323> A_IWL<13322> A_IWL<13321> A_IWL<13320> A_IWL<13319> A_IWL<13318> A_IWL<13317> A_IWL<13316> A_IWL<13315> A_IWL<13314> A_IWL<13313> A_IWL<13312> A_IWL<14335> A_IWL<14334> A_IWL<14333> A_IWL<14332> A_IWL<14331> A_IWL<14330> A_IWL<14329> A_IWL<14328> A_IWL<14327> A_IWL<14326> A_IWL<14325> A_IWL<14324> A_IWL<14323> A_IWL<14322> A_IWL<14321> A_IWL<14320> A_IWL<14319> A_IWL<14318> A_IWL<14317> A_IWL<14316> A_IWL<14315> A_IWL<14314> A_IWL<14313> A_IWL<14312> A_IWL<14311> A_IWL<14310> A_IWL<14309> A_IWL<14308> A_IWL<14307> A_IWL<14306> A_IWL<14305> A_IWL<14304> A_IWL<14303> A_IWL<14302> A_IWL<14301> A_IWL<14300> A_IWL<14299> A_IWL<14298> A_IWL<14297> A_IWL<14296> A_IWL<14295> A_IWL<14294> A_IWL<14293> A_IWL<14292> A_IWL<14291> A_IWL<14290> A_IWL<14289> A_IWL<14288> A_IWL<14287> A_IWL<14286> A_IWL<14285> A_IWL<14284> A_IWL<14283> A_IWL<14282> A_IWL<14281> A_IWL<14280> A_IWL<14279> A_IWL<14278> A_IWL<14277> A_IWL<14276> A_IWL<14275> A_IWL<14274> A_IWL<14273> A_IWL<14272> A_IWL<14271> A_IWL<14270> A_IWL<14269> A_IWL<14268> A_IWL<14267> A_IWL<14266> A_IWL<14265> A_IWL<14264> A_IWL<14263> A_IWL<14262> A_IWL<14261> A_IWL<14260> A_IWL<14259> A_IWL<14258> A_IWL<14257> A_IWL<14256> A_IWL<14255> A_IWL<14254> A_IWL<14253> A_IWL<14252> A_IWL<14251> A_IWL<14250> A_IWL<14249> A_IWL<14248> A_IWL<14247> A_IWL<14246> A_IWL<14245> A_IWL<14244> A_IWL<14243> A_IWL<14242> A_IWL<14241> A_IWL<14240> A_IWL<14239> A_IWL<14238> A_IWL<14237> A_IWL<14236> A_IWL<14235> A_IWL<14234> A_IWL<14233> A_IWL<14232> A_IWL<14231> A_IWL<14230> A_IWL<14229> A_IWL<14228> A_IWL<14227> A_IWL<14226> A_IWL<14225> A_IWL<14224> A_IWL<14223> A_IWL<14222> A_IWL<14221> A_IWL<14220> A_IWL<14219> A_IWL<14218> A_IWL<14217> A_IWL<14216> A_IWL<14215> A_IWL<14214> A_IWL<14213> A_IWL<14212> A_IWL<14211> A_IWL<14210> A_IWL<14209> A_IWL<14208> A_IWL<14207> A_IWL<14206> A_IWL<14205> A_IWL<14204> A_IWL<14203> A_IWL<14202> A_IWL<14201> A_IWL<14200> A_IWL<14199> A_IWL<14198> A_IWL<14197> A_IWL<14196> A_IWL<14195> A_IWL<14194> A_IWL<14193> A_IWL<14192> A_IWL<14191> A_IWL<14190> A_IWL<14189> A_IWL<14188> A_IWL<14187> A_IWL<14186> A_IWL<14185> A_IWL<14184> A_IWL<14183> A_IWL<14182> A_IWL<14181> A_IWL<14180> A_IWL<14179> A_IWL<14178> A_IWL<14177> A_IWL<14176> A_IWL<14175> A_IWL<14174> A_IWL<14173> A_IWL<14172> A_IWL<14171> A_IWL<14170> A_IWL<14169> A_IWL<14168> A_IWL<14167> A_IWL<14166> A_IWL<14165> A_IWL<14164> A_IWL<14163> A_IWL<14162> A_IWL<14161> A_IWL<14160> A_IWL<14159> A_IWL<14158> A_IWL<14157> A_IWL<14156> A_IWL<14155> A_IWL<14154> A_IWL<14153> A_IWL<14152> A_IWL<14151> A_IWL<14150> A_IWL<14149> A_IWL<14148> A_IWL<14147> A_IWL<14146> A_IWL<14145> A_IWL<14144> A_IWL<14143> A_IWL<14142> A_IWL<14141> A_IWL<14140> A_IWL<14139> A_IWL<14138> A_IWL<14137> A_IWL<14136> A_IWL<14135> A_IWL<14134> A_IWL<14133> A_IWL<14132> A_IWL<14131> A_IWL<14130> A_IWL<14129> A_IWL<14128> A_IWL<14127> A_IWL<14126> A_IWL<14125> A_IWL<14124> A_IWL<14123> A_IWL<14122> A_IWL<14121> A_IWL<14120> A_IWL<14119> A_IWL<14118> A_IWL<14117> A_IWL<14116> A_IWL<14115> A_IWL<14114> A_IWL<14113> A_IWL<14112> A_IWL<14111> A_IWL<14110> A_IWL<14109> A_IWL<14108> A_IWL<14107> A_IWL<14106> A_IWL<14105> A_IWL<14104> A_IWL<14103> A_IWL<14102> A_IWL<14101> A_IWL<14100> A_IWL<14099> A_IWL<14098> A_IWL<14097> A_IWL<14096> A_IWL<14095> A_IWL<14094> A_IWL<14093> A_IWL<14092> A_IWL<14091> A_IWL<14090> A_IWL<14089> A_IWL<14088> A_IWL<14087> A_IWL<14086> A_IWL<14085> A_IWL<14084> A_IWL<14083> A_IWL<14082> A_IWL<14081> A_IWL<14080> A_IWL<14079> A_IWL<14078> A_IWL<14077> A_IWL<14076> A_IWL<14075> A_IWL<14074> A_IWL<14073> A_IWL<14072> A_IWL<14071> A_IWL<14070> A_IWL<14069> A_IWL<14068> A_IWL<14067> A_IWL<14066> A_IWL<14065> A_IWL<14064> A_IWL<14063> A_IWL<14062> A_IWL<14061> A_IWL<14060> A_IWL<14059> A_IWL<14058> A_IWL<14057> A_IWL<14056> A_IWL<14055> A_IWL<14054> A_IWL<14053> A_IWL<14052> A_IWL<14051> A_IWL<14050> A_IWL<14049> A_IWL<14048> A_IWL<14047> A_IWL<14046> A_IWL<14045> A_IWL<14044> A_IWL<14043> A_IWL<14042> A_IWL<14041> A_IWL<14040> A_IWL<14039> A_IWL<14038> A_IWL<14037> A_IWL<14036> A_IWL<14035> A_IWL<14034> A_IWL<14033> A_IWL<14032> A_IWL<14031> A_IWL<14030> A_IWL<14029> A_IWL<14028> A_IWL<14027> A_IWL<14026> A_IWL<14025> A_IWL<14024> A_IWL<14023> A_IWL<14022> A_IWL<14021> A_IWL<14020> A_IWL<14019> A_IWL<14018> A_IWL<14017> A_IWL<14016> A_IWL<14015> A_IWL<14014> A_IWL<14013> A_IWL<14012> A_IWL<14011> A_IWL<14010> A_IWL<14009> A_IWL<14008> A_IWL<14007> A_IWL<14006> A_IWL<14005> A_IWL<14004> A_IWL<14003> A_IWL<14002> A_IWL<14001> A_IWL<14000> A_IWL<13999> A_IWL<13998> A_IWL<13997> A_IWL<13996> A_IWL<13995> A_IWL<13994> A_IWL<13993> A_IWL<13992> A_IWL<13991> A_IWL<13990> A_IWL<13989> A_IWL<13988> A_IWL<13987> A_IWL<13986> A_IWL<13985> A_IWL<13984> A_IWL<13983> A_IWL<13982> A_IWL<13981> A_IWL<13980> A_IWL<13979> A_IWL<13978> A_IWL<13977> A_IWL<13976> A_IWL<13975> A_IWL<13974> A_IWL<13973> A_IWL<13972> A_IWL<13971> A_IWL<13970> A_IWL<13969> A_IWL<13968> A_IWL<13967> A_IWL<13966> A_IWL<13965> A_IWL<13964> A_IWL<13963> A_IWL<13962> A_IWL<13961> A_IWL<13960> A_IWL<13959> A_IWL<13958> A_IWL<13957> A_IWL<13956> A_IWL<13955> A_IWL<13954> A_IWL<13953> A_IWL<13952> A_IWL<13951> A_IWL<13950> A_IWL<13949> A_IWL<13948> A_IWL<13947> A_IWL<13946> A_IWL<13945> A_IWL<13944> A_IWL<13943> A_IWL<13942> A_IWL<13941> A_IWL<13940> A_IWL<13939> A_IWL<13938> A_IWL<13937> A_IWL<13936> A_IWL<13935> A_IWL<13934> A_IWL<13933> A_IWL<13932> A_IWL<13931> A_IWL<13930> A_IWL<13929> A_IWL<13928> A_IWL<13927> A_IWL<13926> A_IWL<13925> A_IWL<13924> A_IWL<13923> A_IWL<13922> A_IWL<13921> A_IWL<13920> A_IWL<13919> A_IWL<13918> A_IWL<13917> A_IWL<13916> A_IWL<13915> A_IWL<13914> A_IWL<13913> A_IWL<13912> A_IWL<13911> A_IWL<13910> A_IWL<13909> A_IWL<13908> A_IWL<13907> A_IWL<13906> A_IWL<13905> A_IWL<13904> A_IWL<13903> A_IWL<13902> A_IWL<13901> A_IWL<13900> A_IWL<13899> A_IWL<13898> A_IWL<13897> A_IWL<13896> A_IWL<13895> A_IWL<13894> A_IWL<13893> A_IWL<13892> A_IWL<13891> A_IWL<13890> A_IWL<13889> A_IWL<13888> A_IWL<13887> A_IWL<13886> A_IWL<13885> A_IWL<13884> A_IWL<13883> A_IWL<13882> A_IWL<13881> A_IWL<13880> A_IWL<13879> A_IWL<13878> A_IWL<13877> A_IWL<13876> A_IWL<13875> A_IWL<13874> A_IWL<13873> A_IWL<13872> A_IWL<13871> A_IWL<13870> A_IWL<13869> A_IWL<13868> A_IWL<13867> A_IWL<13866> A_IWL<13865> A_IWL<13864> A_IWL<13863> A_IWL<13862> A_IWL<13861> A_IWL<13860> A_IWL<13859> A_IWL<13858> A_IWL<13857> A_IWL<13856> A_IWL<13855> A_IWL<13854> A_IWL<13853> A_IWL<13852> A_IWL<13851> A_IWL<13850> A_IWL<13849> A_IWL<13848> A_IWL<13847> A_IWL<13846> A_IWL<13845> A_IWL<13844> A_IWL<13843> A_IWL<13842> A_IWL<13841> A_IWL<13840> A_IWL<13839> A_IWL<13838> A_IWL<13837> A_IWL<13836> A_IWL<13835> A_IWL<13834> A_IWL<13833> A_IWL<13832> A_IWL<13831> A_IWL<13830> A_IWL<13829> A_IWL<13828> A_IWL<13827> A_IWL<13826> A_IWL<13825> A_IWL<13824> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_COLUMN_pcell_0 +XCOL<26> A_BLC<53> A_BLC<52> A_BLC_TOP<53> A_BLC_TOP<52> A_BLT<53> A_BLT<52> A_BLT_TOP<53> A_BLT_TOP<52> A_IWL<13311> A_IWL<13310> A_IWL<13309> A_IWL<13308> A_IWL<13307> A_IWL<13306> A_IWL<13305> A_IWL<13304> A_IWL<13303> A_IWL<13302> A_IWL<13301> A_IWL<13300> A_IWL<13299> A_IWL<13298> A_IWL<13297> A_IWL<13296> A_IWL<13295> A_IWL<13294> A_IWL<13293> A_IWL<13292> A_IWL<13291> A_IWL<13290> A_IWL<13289> A_IWL<13288> A_IWL<13287> A_IWL<13286> A_IWL<13285> A_IWL<13284> A_IWL<13283> A_IWL<13282> A_IWL<13281> A_IWL<13280> A_IWL<13279> A_IWL<13278> A_IWL<13277> A_IWL<13276> A_IWL<13275> A_IWL<13274> A_IWL<13273> A_IWL<13272> A_IWL<13271> A_IWL<13270> A_IWL<13269> A_IWL<13268> A_IWL<13267> A_IWL<13266> A_IWL<13265> A_IWL<13264> A_IWL<13263> A_IWL<13262> A_IWL<13261> A_IWL<13260> A_IWL<13259> A_IWL<13258> A_IWL<13257> A_IWL<13256> A_IWL<13255> A_IWL<13254> A_IWL<13253> A_IWL<13252> A_IWL<13251> A_IWL<13250> A_IWL<13249> A_IWL<13248> A_IWL<13247> A_IWL<13246> A_IWL<13245> A_IWL<13244> A_IWL<13243> A_IWL<13242> A_IWL<13241> A_IWL<13240> A_IWL<13239> A_IWL<13238> A_IWL<13237> A_IWL<13236> A_IWL<13235> A_IWL<13234> A_IWL<13233> A_IWL<13232> A_IWL<13231> A_IWL<13230> A_IWL<13229> A_IWL<13228> A_IWL<13227> A_IWL<13226> A_IWL<13225> A_IWL<13224> A_IWL<13223> A_IWL<13222> A_IWL<13221> A_IWL<13220> A_IWL<13219> A_IWL<13218> A_IWL<13217> A_IWL<13216> A_IWL<13215> A_IWL<13214> A_IWL<13213> A_IWL<13212> A_IWL<13211> A_IWL<13210> A_IWL<13209> A_IWL<13208> A_IWL<13207> A_IWL<13206> A_IWL<13205> A_IWL<13204> A_IWL<13203> A_IWL<13202> A_IWL<13201> A_IWL<13200> A_IWL<13199> A_IWL<13198> A_IWL<13197> A_IWL<13196> A_IWL<13195> A_IWL<13194> A_IWL<13193> A_IWL<13192> A_IWL<13191> A_IWL<13190> A_IWL<13189> A_IWL<13188> A_IWL<13187> A_IWL<13186> A_IWL<13185> A_IWL<13184> A_IWL<13183> A_IWL<13182> A_IWL<13181> A_IWL<13180> A_IWL<13179> A_IWL<13178> A_IWL<13177> A_IWL<13176> A_IWL<13175> A_IWL<13174> A_IWL<13173> A_IWL<13172> A_IWL<13171> A_IWL<13170> A_IWL<13169> A_IWL<13168> A_IWL<13167> A_IWL<13166> A_IWL<13165> A_IWL<13164> A_IWL<13163> A_IWL<13162> A_IWL<13161> A_IWL<13160> A_IWL<13159> A_IWL<13158> A_IWL<13157> A_IWL<13156> A_IWL<13155> A_IWL<13154> A_IWL<13153> A_IWL<13152> A_IWL<13151> A_IWL<13150> A_IWL<13149> A_IWL<13148> A_IWL<13147> A_IWL<13146> A_IWL<13145> A_IWL<13144> A_IWL<13143> A_IWL<13142> A_IWL<13141> A_IWL<13140> A_IWL<13139> A_IWL<13138> A_IWL<13137> A_IWL<13136> A_IWL<13135> A_IWL<13134> A_IWL<13133> A_IWL<13132> A_IWL<13131> A_IWL<13130> A_IWL<13129> A_IWL<13128> A_IWL<13127> A_IWL<13126> A_IWL<13125> A_IWL<13124> A_IWL<13123> A_IWL<13122> A_IWL<13121> A_IWL<13120> A_IWL<13119> A_IWL<13118> A_IWL<13117> A_IWL<13116> A_IWL<13115> A_IWL<13114> A_IWL<13113> A_IWL<13112> A_IWL<13111> A_IWL<13110> A_IWL<13109> A_IWL<13108> A_IWL<13107> A_IWL<13106> A_IWL<13105> A_IWL<13104> A_IWL<13103> A_IWL<13102> A_IWL<13101> A_IWL<13100> A_IWL<13099> A_IWL<13098> A_IWL<13097> A_IWL<13096> A_IWL<13095> A_IWL<13094> A_IWL<13093> A_IWL<13092> A_IWL<13091> A_IWL<13090> A_IWL<13089> A_IWL<13088> A_IWL<13087> A_IWL<13086> A_IWL<13085> A_IWL<13084> A_IWL<13083> A_IWL<13082> A_IWL<13081> A_IWL<13080> A_IWL<13079> A_IWL<13078> A_IWL<13077> A_IWL<13076> A_IWL<13075> A_IWL<13074> A_IWL<13073> A_IWL<13072> A_IWL<13071> A_IWL<13070> A_IWL<13069> A_IWL<13068> A_IWL<13067> A_IWL<13066> A_IWL<13065> A_IWL<13064> A_IWL<13063> A_IWL<13062> A_IWL<13061> A_IWL<13060> A_IWL<13059> A_IWL<13058> A_IWL<13057> A_IWL<13056> A_IWL<13055> A_IWL<13054> A_IWL<13053> A_IWL<13052> A_IWL<13051> A_IWL<13050> A_IWL<13049> A_IWL<13048> A_IWL<13047> A_IWL<13046> A_IWL<13045> A_IWL<13044> A_IWL<13043> A_IWL<13042> A_IWL<13041> A_IWL<13040> A_IWL<13039> A_IWL<13038> A_IWL<13037> A_IWL<13036> A_IWL<13035> A_IWL<13034> A_IWL<13033> A_IWL<13032> A_IWL<13031> A_IWL<13030> A_IWL<13029> A_IWL<13028> A_IWL<13027> A_IWL<13026> A_IWL<13025> A_IWL<13024> A_IWL<13023> A_IWL<13022> A_IWL<13021> A_IWL<13020> A_IWL<13019> A_IWL<13018> A_IWL<13017> A_IWL<13016> A_IWL<13015> A_IWL<13014> A_IWL<13013> A_IWL<13012> A_IWL<13011> A_IWL<13010> A_IWL<13009> A_IWL<13008> A_IWL<13007> A_IWL<13006> A_IWL<13005> A_IWL<13004> A_IWL<13003> A_IWL<13002> A_IWL<13001> A_IWL<13000> A_IWL<12999> A_IWL<12998> A_IWL<12997> A_IWL<12996> A_IWL<12995> A_IWL<12994> A_IWL<12993> A_IWL<12992> A_IWL<12991> A_IWL<12990> A_IWL<12989> A_IWL<12988> A_IWL<12987> A_IWL<12986> A_IWL<12985> A_IWL<12984> A_IWL<12983> A_IWL<12982> A_IWL<12981> A_IWL<12980> A_IWL<12979> A_IWL<12978> A_IWL<12977> A_IWL<12976> A_IWL<12975> A_IWL<12974> A_IWL<12973> A_IWL<12972> A_IWL<12971> A_IWL<12970> A_IWL<12969> A_IWL<12968> A_IWL<12967> A_IWL<12966> A_IWL<12965> A_IWL<12964> A_IWL<12963> A_IWL<12962> A_IWL<12961> A_IWL<12960> A_IWL<12959> A_IWL<12958> A_IWL<12957> A_IWL<12956> A_IWL<12955> A_IWL<12954> A_IWL<12953> A_IWL<12952> A_IWL<12951> A_IWL<12950> A_IWL<12949> A_IWL<12948> A_IWL<12947> A_IWL<12946> A_IWL<12945> A_IWL<12944> A_IWL<12943> A_IWL<12942> A_IWL<12941> A_IWL<12940> A_IWL<12939> A_IWL<12938> A_IWL<12937> A_IWL<12936> A_IWL<12935> A_IWL<12934> A_IWL<12933> A_IWL<12932> A_IWL<12931> A_IWL<12930> A_IWL<12929> A_IWL<12928> A_IWL<12927> A_IWL<12926> A_IWL<12925> A_IWL<12924> A_IWL<12923> A_IWL<12922> A_IWL<12921> A_IWL<12920> A_IWL<12919> A_IWL<12918> A_IWL<12917> A_IWL<12916> A_IWL<12915> A_IWL<12914> A_IWL<12913> A_IWL<12912> A_IWL<12911> A_IWL<12910> A_IWL<12909> A_IWL<12908> A_IWL<12907> A_IWL<12906> A_IWL<12905> A_IWL<12904> A_IWL<12903> A_IWL<12902> A_IWL<12901> A_IWL<12900> A_IWL<12899> A_IWL<12898> A_IWL<12897> A_IWL<12896> A_IWL<12895> A_IWL<12894> A_IWL<12893> A_IWL<12892> A_IWL<12891> A_IWL<12890> A_IWL<12889> A_IWL<12888> A_IWL<12887> A_IWL<12886> A_IWL<12885> A_IWL<12884> A_IWL<12883> A_IWL<12882> A_IWL<12881> A_IWL<12880> A_IWL<12879> A_IWL<12878> A_IWL<12877> A_IWL<12876> A_IWL<12875> A_IWL<12874> A_IWL<12873> A_IWL<12872> A_IWL<12871> A_IWL<12870> A_IWL<12869> A_IWL<12868> A_IWL<12867> A_IWL<12866> A_IWL<12865> A_IWL<12864> A_IWL<12863> A_IWL<12862> A_IWL<12861> A_IWL<12860> A_IWL<12859> A_IWL<12858> A_IWL<12857> A_IWL<12856> A_IWL<12855> A_IWL<12854> A_IWL<12853> A_IWL<12852> A_IWL<12851> A_IWL<12850> A_IWL<12849> A_IWL<12848> A_IWL<12847> A_IWL<12846> A_IWL<12845> A_IWL<12844> A_IWL<12843> A_IWL<12842> A_IWL<12841> A_IWL<12840> A_IWL<12839> A_IWL<12838> A_IWL<12837> A_IWL<12836> A_IWL<12835> A_IWL<12834> A_IWL<12833> A_IWL<12832> A_IWL<12831> A_IWL<12830> A_IWL<12829> A_IWL<12828> A_IWL<12827> A_IWL<12826> A_IWL<12825> A_IWL<12824> A_IWL<12823> A_IWL<12822> A_IWL<12821> A_IWL<12820> A_IWL<12819> A_IWL<12818> A_IWL<12817> A_IWL<12816> A_IWL<12815> A_IWL<12814> A_IWL<12813> A_IWL<12812> A_IWL<12811> A_IWL<12810> A_IWL<12809> A_IWL<12808> A_IWL<12807> A_IWL<12806> A_IWL<12805> A_IWL<12804> A_IWL<12803> A_IWL<12802> A_IWL<12801> A_IWL<12800> A_IWL<13823> A_IWL<13822> A_IWL<13821> A_IWL<13820> A_IWL<13819> A_IWL<13818> A_IWL<13817> A_IWL<13816> A_IWL<13815> A_IWL<13814> A_IWL<13813> A_IWL<13812> A_IWL<13811> A_IWL<13810> A_IWL<13809> A_IWL<13808> A_IWL<13807> A_IWL<13806> A_IWL<13805> A_IWL<13804> A_IWL<13803> A_IWL<13802> A_IWL<13801> A_IWL<13800> A_IWL<13799> A_IWL<13798> A_IWL<13797> A_IWL<13796> A_IWL<13795> A_IWL<13794> A_IWL<13793> A_IWL<13792> A_IWL<13791> A_IWL<13790> A_IWL<13789> A_IWL<13788> A_IWL<13787> A_IWL<13786> A_IWL<13785> A_IWL<13784> A_IWL<13783> A_IWL<13782> A_IWL<13781> A_IWL<13780> A_IWL<13779> A_IWL<13778> A_IWL<13777> A_IWL<13776> A_IWL<13775> A_IWL<13774> A_IWL<13773> A_IWL<13772> A_IWL<13771> A_IWL<13770> A_IWL<13769> A_IWL<13768> A_IWL<13767> A_IWL<13766> A_IWL<13765> A_IWL<13764> A_IWL<13763> A_IWL<13762> A_IWL<13761> A_IWL<13760> A_IWL<13759> A_IWL<13758> A_IWL<13757> A_IWL<13756> A_IWL<13755> A_IWL<13754> A_IWL<13753> A_IWL<13752> A_IWL<13751> A_IWL<13750> A_IWL<13749> A_IWL<13748> A_IWL<13747> A_IWL<13746> A_IWL<13745> A_IWL<13744> A_IWL<13743> A_IWL<13742> A_IWL<13741> A_IWL<13740> A_IWL<13739> A_IWL<13738> A_IWL<13737> A_IWL<13736> A_IWL<13735> A_IWL<13734> A_IWL<13733> A_IWL<13732> A_IWL<13731> A_IWL<13730> A_IWL<13729> A_IWL<13728> A_IWL<13727> A_IWL<13726> A_IWL<13725> A_IWL<13724> A_IWL<13723> A_IWL<13722> A_IWL<13721> A_IWL<13720> A_IWL<13719> A_IWL<13718> A_IWL<13717> A_IWL<13716> A_IWL<13715> A_IWL<13714> A_IWL<13713> A_IWL<13712> A_IWL<13711> A_IWL<13710> A_IWL<13709> A_IWL<13708> A_IWL<13707> A_IWL<13706> A_IWL<13705> A_IWL<13704> A_IWL<13703> A_IWL<13702> A_IWL<13701> A_IWL<13700> A_IWL<13699> A_IWL<13698> A_IWL<13697> A_IWL<13696> A_IWL<13695> A_IWL<13694> A_IWL<13693> A_IWL<13692> A_IWL<13691> A_IWL<13690> A_IWL<13689> A_IWL<13688> A_IWL<13687> A_IWL<13686> A_IWL<13685> A_IWL<13684> A_IWL<13683> A_IWL<13682> A_IWL<13681> A_IWL<13680> A_IWL<13679> A_IWL<13678> A_IWL<13677> A_IWL<13676> A_IWL<13675> A_IWL<13674> A_IWL<13673> A_IWL<13672> A_IWL<13671> A_IWL<13670> A_IWL<13669> A_IWL<13668> A_IWL<13667> A_IWL<13666> A_IWL<13665> A_IWL<13664> A_IWL<13663> A_IWL<13662> A_IWL<13661> A_IWL<13660> A_IWL<13659> A_IWL<13658> A_IWL<13657> A_IWL<13656> A_IWL<13655> A_IWL<13654> A_IWL<13653> A_IWL<13652> A_IWL<13651> A_IWL<13650> A_IWL<13649> A_IWL<13648> A_IWL<13647> A_IWL<13646> A_IWL<13645> A_IWL<13644> A_IWL<13643> A_IWL<13642> A_IWL<13641> A_IWL<13640> A_IWL<13639> A_IWL<13638> A_IWL<13637> A_IWL<13636> A_IWL<13635> A_IWL<13634> A_IWL<13633> A_IWL<13632> A_IWL<13631> A_IWL<13630> A_IWL<13629> A_IWL<13628> A_IWL<13627> A_IWL<13626> A_IWL<13625> A_IWL<13624> A_IWL<13623> A_IWL<13622> A_IWL<13621> A_IWL<13620> A_IWL<13619> A_IWL<13618> A_IWL<13617> A_IWL<13616> A_IWL<13615> A_IWL<13614> A_IWL<13613> A_IWL<13612> A_IWL<13611> A_IWL<13610> A_IWL<13609> A_IWL<13608> A_IWL<13607> A_IWL<13606> A_IWL<13605> A_IWL<13604> A_IWL<13603> A_IWL<13602> A_IWL<13601> A_IWL<13600> A_IWL<13599> A_IWL<13598> A_IWL<13597> A_IWL<13596> A_IWL<13595> A_IWL<13594> A_IWL<13593> A_IWL<13592> A_IWL<13591> A_IWL<13590> A_IWL<13589> A_IWL<13588> A_IWL<13587> A_IWL<13586> A_IWL<13585> A_IWL<13584> A_IWL<13583> A_IWL<13582> A_IWL<13581> A_IWL<13580> A_IWL<13579> A_IWL<13578> A_IWL<13577> A_IWL<13576> A_IWL<13575> A_IWL<13574> A_IWL<13573> A_IWL<13572> A_IWL<13571> A_IWL<13570> A_IWL<13569> A_IWL<13568> A_IWL<13567> A_IWL<13566> A_IWL<13565> A_IWL<13564> A_IWL<13563> A_IWL<13562> A_IWL<13561> A_IWL<13560> A_IWL<13559> A_IWL<13558> A_IWL<13557> A_IWL<13556> A_IWL<13555> A_IWL<13554> A_IWL<13553> A_IWL<13552> A_IWL<13551> A_IWL<13550> A_IWL<13549> A_IWL<13548> A_IWL<13547> A_IWL<13546> A_IWL<13545> A_IWL<13544> A_IWL<13543> A_IWL<13542> A_IWL<13541> A_IWL<13540> A_IWL<13539> A_IWL<13538> A_IWL<13537> A_IWL<13536> A_IWL<13535> A_IWL<13534> A_IWL<13533> A_IWL<13532> A_IWL<13531> A_IWL<13530> A_IWL<13529> A_IWL<13528> A_IWL<13527> A_IWL<13526> A_IWL<13525> A_IWL<13524> A_IWL<13523> A_IWL<13522> A_IWL<13521> A_IWL<13520> A_IWL<13519> A_IWL<13518> A_IWL<13517> A_IWL<13516> A_IWL<13515> A_IWL<13514> A_IWL<13513> A_IWL<13512> A_IWL<13511> A_IWL<13510> A_IWL<13509> A_IWL<13508> A_IWL<13507> A_IWL<13506> A_IWL<13505> A_IWL<13504> A_IWL<13503> A_IWL<13502> A_IWL<13501> A_IWL<13500> A_IWL<13499> A_IWL<13498> A_IWL<13497> A_IWL<13496> A_IWL<13495> A_IWL<13494> A_IWL<13493> A_IWL<13492> A_IWL<13491> A_IWL<13490> A_IWL<13489> A_IWL<13488> A_IWL<13487> A_IWL<13486> A_IWL<13485> A_IWL<13484> A_IWL<13483> A_IWL<13482> A_IWL<13481> A_IWL<13480> A_IWL<13479> A_IWL<13478> A_IWL<13477> A_IWL<13476> A_IWL<13475> A_IWL<13474> A_IWL<13473> A_IWL<13472> A_IWL<13471> A_IWL<13470> A_IWL<13469> A_IWL<13468> A_IWL<13467> A_IWL<13466> A_IWL<13465> A_IWL<13464> A_IWL<13463> A_IWL<13462> A_IWL<13461> A_IWL<13460> A_IWL<13459> A_IWL<13458> A_IWL<13457> A_IWL<13456> A_IWL<13455> A_IWL<13454> A_IWL<13453> A_IWL<13452> A_IWL<13451> A_IWL<13450> A_IWL<13449> A_IWL<13448> A_IWL<13447> A_IWL<13446> A_IWL<13445> A_IWL<13444> A_IWL<13443> A_IWL<13442> A_IWL<13441> A_IWL<13440> A_IWL<13439> A_IWL<13438> A_IWL<13437> A_IWL<13436> A_IWL<13435> A_IWL<13434> A_IWL<13433> A_IWL<13432> A_IWL<13431> A_IWL<13430> A_IWL<13429> A_IWL<13428> A_IWL<13427> A_IWL<13426> A_IWL<13425> A_IWL<13424> A_IWL<13423> A_IWL<13422> A_IWL<13421> A_IWL<13420> A_IWL<13419> A_IWL<13418> A_IWL<13417> A_IWL<13416> A_IWL<13415> A_IWL<13414> A_IWL<13413> A_IWL<13412> A_IWL<13411> A_IWL<13410> A_IWL<13409> A_IWL<13408> A_IWL<13407> A_IWL<13406> A_IWL<13405> A_IWL<13404> A_IWL<13403> A_IWL<13402> A_IWL<13401> A_IWL<13400> A_IWL<13399> A_IWL<13398> A_IWL<13397> A_IWL<13396> A_IWL<13395> A_IWL<13394> A_IWL<13393> A_IWL<13392> A_IWL<13391> A_IWL<13390> A_IWL<13389> A_IWL<13388> A_IWL<13387> A_IWL<13386> A_IWL<13385> A_IWL<13384> A_IWL<13383> A_IWL<13382> A_IWL<13381> A_IWL<13380> A_IWL<13379> A_IWL<13378> A_IWL<13377> A_IWL<13376> A_IWL<13375> A_IWL<13374> A_IWL<13373> A_IWL<13372> A_IWL<13371> A_IWL<13370> A_IWL<13369> A_IWL<13368> A_IWL<13367> A_IWL<13366> A_IWL<13365> A_IWL<13364> A_IWL<13363> A_IWL<13362> A_IWL<13361> A_IWL<13360> A_IWL<13359> A_IWL<13358> A_IWL<13357> A_IWL<13356> A_IWL<13355> A_IWL<13354> A_IWL<13353> A_IWL<13352> A_IWL<13351> A_IWL<13350> A_IWL<13349> A_IWL<13348> A_IWL<13347> A_IWL<13346> A_IWL<13345> A_IWL<13344> A_IWL<13343> A_IWL<13342> A_IWL<13341> A_IWL<13340> A_IWL<13339> A_IWL<13338> A_IWL<13337> A_IWL<13336> A_IWL<13335> A_IWL<13334> A_IWL<13333> A_IWL<13332> A_IWL<13331> A_IWL<13330> A_IWL<13329> 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A_IWL<12752> A_IWL<12751> A_IWL<12750> A_IWL<12749> A_IWL<12748> A_IWL<12747> A_IWL<12746> A_IWL<12745> A_IWL<12744> A_IWL<12743> A_IWL<12742> A_IWL<12741> A_IWL<12740> A_IWL<12739> A_IWL<12738> A_IWL<12737> A_IWL<12736> A_IWL<12735> A_IWL<12734> A_IWL<12733> A_IWL<12732> A_IWL<12731> A_IWL<12730> A_IWL<12729> A_IWL<12728> A_IWL<12727> A_IWL<12726> A_IWL<12725> A_IWL<12724> A_IWL<12723> A_IWL<12722> A_IWL<12721> A_IWL<12720> A_IWL<12719> A_IWL<12718> A_IWL<12717> A_IWL<12716> A_IWL<12715> A_IWL<12714> A_IWL<12713> A_IWL<12712> A_IWL<12711> A_IWL<12710> A_IWL<12709> A_IWL<12708> A_IWL<12707> A_IWL<12706> A_IWL<12705> A_IWL<12704> A_IWL<12703> A_IWL<12702> A_IWL<12701> A_IWL<12700> A_IWL<12699> A_IWL<12698> A_IWL<12697> A_IWL<12696> A_IWL<12695> A_IWL<12694> A_IWL<12693> A_IWL<12692> A_IWL<12691> A_IWL<12690> A_IWL<12689> A_IWL<12688> A_IWL<12687> A_IWL<12686> A_IWL<12685> A_IWL<12684> A_IWL<12683> A_IWL<12682> A_IWL<12681> A_IWL<12680> A_IWL<12679> A_IWL<12678> A_IWL<12677> A_IWL<12676> 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A_IWL<12598> A_IWL<12597> A_IWL<12596> A_IWL<12595> A_IWL<12594> A_IWL<12593> A_IWL<12592> A_IWL<12591> A_IWL<12590> A_IWL<12589> A_IWL<12588> A_IWL<12587> A_IWL<12586> A_IWL<12585> A_IWL<12584> A_IWL<12583> A_IWL<12582> A_IWL<12581> A_IWL<12580> A_IWL<12579> A_IWL<12578> A_IWL<12577> A_IWL<12576> A_IWL<12575> A_IWL<12574> A_IWL<12573> A_IWL<12572> A_IWL<12571> A_IWL<12570> A_IWL<12569> A_IWL<12568> A_IWL<12567> A_IWL<12566> A_IWL<12565> A_IWL<12564> A_IWL<12563> A_IWL<12562> A_IWL<12561> A_IWL<12560> A_IWL<12559> A_IWL<12558> A_IWL<12557> A_IWL<12556> A_IWL<12555> A_IWL<12554> A_IWL<12553> A_IWL<12552> A_IWL<12551> A_IWL<12550> A_IWL<12549> A_IWL<12548> A_IWL<12547> A_IWL<12546> A_IWL<12545> A_IWL<12544> A_IWL<12543> A_IWL<12542> A_IWL<12541> A_IWL<12540> A_IWL<12539> A_IWL<12538> A_IWL<12537> A_IWL<12536> A_IWL<12535> A_IWL<12534> A_IWL<12533> A_IWL<12532> A_IWL<12531> A_IWL<12530> A_IWL<12529> A_IWL<12528> A_IWL<12527> A_IWL<12526> A_IWL<12525> A_IWL<12524> A_IWL<12523> A_IWL<12522> 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A_IWL<12444> A_IWL<12443> A_IWL<12442> A_IWL<12441> A_IWL<12440> A_IWL<12439> A_IWL<12438> A_IWL<12437> A_IWL<12436> A_IWL<12435> A_IWL<12434> A_IWL<12433> A_IWL<12432> A_IWL<12431> A_IWL<12430> A_IWL<12429> A_IWL<12428> A_IWL<12427> A_IWL<12426> A_IWL<12425> A_IWL<12424> A_IWL<12423> A_IWL<12422> A_IWL<12421> A_IWL<12420> A_IWL<12419> A_IWL<12418> A_IWL<12417> A_IWL<12416> A_IWL<12415> A_IWL<12414> A_IWL<12413> A_IWL<12412> A_IWL<12411> A_IWL<12410> A_IWL<12409> A_IWL<12408> A_IWL<12407> A_IWL<12406> A_IWL<12405> A_IWL<12404> A_IWL<12403> A_IWL<12402> A_IWL<12401> A_IWL<12400> A_IWL<12399> A_IWL<12398> A_IWL<12397> A_IWL<12396> A_IWL<12395> A_IWL<12394> A_IWL<12393> A_IWL<12392> A_IWL<12391> A_IWL<12390> A_IWL<12389> A_IWL<12388> A_IWL<12387> A_IWL<12386> A_IWL<12385> A_IWL<12384> A_IWL<12383> A_IWL<12382> A_IWL<12381> A_IWL<12380> A_IWL<12379> A_IWL<12378> A_IWL<12377> A_IWL<12376> A_IWL<12375> A_IWL<12374> A_IWL<12373> A_IWL<12372> A_IWL<12371> A_IWL<12370> A_IWL<12369> A_IWL<12368> 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A_IWL<12929> A_IWL<12928> A_IWL<12927> A_IWL<12926> A_IWL<12925> A_IWL<12924> A_IWL<12923> A_IWL<12922> A_IWL<12921> A_IWL<12920> A_IWL<12919> A_IWL<12918> A_IWL<12917> A_IWL<12916> A_IWL<12915> A_IWL<12914> A_IWL<12913> A_IWL<12912> A_IWL<12911> A_IWL<12910> A_IWL<12909> A_IWL<12908> A_IWL<12907> A_IWL<12906> A_IWL<12905> A_IWL<12904> A_IWL<12903> A_IWL<12902> A_IWL<12901> A_IWL<12900> A_IWL<12899> A_IWL<12898> A_IWL<12897> A_IWL<12896> A_IWL<12895> A_IWL<12894> A_IWL<12893> A_IWL<12892> A_IWL<12891> A_IWL<12890> A_IWL<12889> A_IWL<12888> A_IWL<12887> A_IWL<12886> A_IWL<12885> A_IWL<12884> A_IWL<12883> A_IWL<12882> A_IWL<12881> A_IWL<12880> A_IWL<12879> A_IWL<12878> A_IWL<12877> A_IWL<12876> A_IWL<12875> A_IWL<12874> A_IWL<12873> A_IWL<12872> A_IWL<12871> A_IWL<12870> A_IWL<12869> A_IWL<12868> A_IWL<12867> A_IWL<12866> A_IWL<12865> A_IWL<12864> A_IWL<12863> A_IWL<12862> A_IWL<12861> A_IWL<12860> A_IWL<12859> A_IWL<12858> A_IWL<12857> A_IWL<12856> A_IWL<12855> A_IWL<12854> A_IWL<12853> A_IWL<12852> A_IWL<12851> A_IWL<12850> A_IWL<12849> A_IWL<12848> A_IWL<12847> A_IWL<12846> A_IWL<12845> A_IWL<12844> A_IWL<12843> A_IWL<12842> A_IWL<12841> A_IWL<12840> A_IWL<12839> A_IWL<12838> A_IWL<12837> A_IWL<12836> A_IWL<12835> A_IWL<12834> A_IWL<12833> A_IWL<12832> A_IWL<12831> A_IWL<12830> A_IWL<12829> A_IWL<12828> A_IWL<12827> A_IWL<12826> A_IWL<12825> A_IWL<12824> A_IWL<12823> A_IWL<12822> A_IWL<12821> A_IWL<12820> A_IWL<12819> A_IWL<12818> A_IWL<12817> A_IWL<12816> A_IWL<12815> A_IWL<12814> A_IWL<12813> A_IWL<12812> A_IWL<12811> A_IWL<12810> A_IWL<12809> A_IWL<12808> A_IWL<12807> A_IWL<12806> A_IWL<12805> A_IWL<12804> A_IWL<12803> A_IWL<12802> A_IWL<12801> A_IWL<12800> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_COLUMN_pcell_0 +XCOL<24> A_BLC<49> A_BLC<48> A_BLC_TOP<49> A_BLC_TOP<48> A_BLT<49> A_BLT<48> A_BLT_TOP<49> A_BLT_TOP<48> A_IWL<12287> A_IWL<12286> A_IWL<12285> A_IWL<12284> A_IWL<12283> A_IWL<12282> A_IWL<12281> A_IWL<12280> A_IWL<12279> A_IWL<12278> A_IWL<12277> A_IWL<12276> A_IWL<12275> A_IWL<12274> A_IWL<12273> A_IWL<12272> A_IWL<12271> A_IWL<12270> A_IWL<12269> A_IWL<12268> A_IWL<12267> A_IWL<12266> A_IWL<12265> A_IWL<12264> A_IWL<12263> A_IWL<12262> A_IWL<12261> A_IWL<12260> A_IWL<12259> A_IWL<12258> A_IWL<12257> A_IWL<12256> A_IWL<12255> A_IWL<12254> A_IWL<12253> A_IWL<12252> A_IWL<12251> A_IWL<12250> A_IWL<12249> A_IWL<12248> A_IWL<12247> A_IWL<12246> A_IWL<12245> A_IWL<12244> A_IWL<12243> A_IWL<12242> A_IWL<12241> A_IWL<12240> A_IWL<12239> A_IWL<12238> A_IWL<12237> A_IWL<12236> A_IWL<12235> A_IWL<12234> A_IWL<12233> A_IWL<12232> A_IWL<12231> A_IWL<12230> A_IWL<12229> A_IWL<12228> A_IWL<12227> A_IWL<12226> A_IWL<12225> A_IWL<12224> A_IWL<12223> A_IWL<12222> A_IWL<12221> A_IWL<12220> A_IWL<12219> A_IWL<12218> A_IWL<12217> A_IWL<12216> A_IWL<12215> A_IWL<12214> A_IWL<12213> A_IWL<12212> A_IWL<12211> A_IWL<12210> A_IWL<12209> A_IWL<12208> A_IWL<12207> A_IWL<12206> A_IWL<12205> A_IWL<12204> A_IWL<12203> A_IWL<12202> A_IWL<12201> A_IWL<12200> A_IWL<12199> A_IWL<12198> A_IWL<12197> A_IWL<12196> A_IWL<12195> A_IWL<12194> A_IWL<12193> A_IWL<12192> A_IWL<12191> A_IWL<12190> A_IWL<12189> A_IWL<12188> A_IWL<12187> A_IWL<12186> A_IWL<12185> A_IWL<12184> A_IWL<12183> A_IWL<12182> A_IWL<12181> A_IWL<12180> A_IWL<12179> A_IWL<12178> A_IWL<12177> A_IWL<12176> A_IWL<12175> A_IWL<12174> A_IWL<12173> A_IWL<12172> A_IWL<12171> A_IWL<12170> A_IWL<12169> A_IWL<12168> A_IWL<12167> A_IWL<12166> A_IWL<12165> A_IWL<12164> A_IWL<12163> A_IWL<12162> A_IWL<12161> A_IWL<12160> A_IWL<12159> A_IWL<12158> A_IWL<12157> A_IWL<12156> A_IWL<12155> A_IWL<12154> A_IWL<12153> A_IWL<12152> A_IWL<12151> A_IWL<12150> A_IWL<12149> A_IWL<12148> A_IWL<12147> A_IWL<12146> A_IWL<12145> A_IWL<12144> A_IWL<12143> A_IWL<12142> A_IWL<12141> A_IWL<12140> A_IWL<12139> A_IWL<12138> A_IWL<12137> A_IWL<12136> A_IWL<12135> A_IWL<12134> A_IWL<12133> A_IWL<12132> A_IWL<12131> A_IWL<12130> A_IWL<12129> A_IWL<12128> A_IWL<12127> A_IWL<12126> A_IWL<12125> A_IWL<12124> A_IWL<12123> A_IWL<12122> A_IWL<12121> A_IWL<12120> A_IWL<12119> A_IWL<12118> A_IWL<12117> A_IWL<12116> A_IWL<12115> A_IWL<12114> A_IWL<12113> A_IWL<12112> A_IWL<12111> A_IWL<12110> A_IWL<12109> A_IWL<12108> A_IWL<12107> A_IWL<12106> A_IWL<12105> A_IWL<12104> A_IWL<12103> A_IWL<12102> A_IWL<12101> A_IWL<12100> A_IWL<12099> A_IWL<12098> A_IWL<12097> A_IWL<12096> A_IWL<12095> A_IWL<12094> A_IWL<12093> A_IWL<12092> A_IWL<12091> A_IWL<12090> A_IWL<12089> A_IWL<12088> A_IWL<12087> A_IWL<12086> A_IWL<12085> A_IWL<12084> A_IWL<12083> A_IWL<12082> A_IWL<12081> A_IWL<12080> A_IWL<12079> A_IWL<12078> A_IWL<12077> A_IWL<12076> A_IWL<12075> A_IWL<12074> A_IWL<12073> A_IWL<12072> A_IWL<12071> A_IWL<12070> A_IWL<12069> A_IWL<12068> A_IWL<12067> A_IWL<12066> A_IWL<12065> A_IWL<12064> A_IWL<12063> A_IWL<12062> A_IWL<12061> A_IWL<12060> A_IWL<12059> A_IWL<12058> A_IWL<12057> A_IWL<12056> A_IWL<12055> A_IWL<12054> A_IWL<12053> A_IWL<12052> A_IWL<12051> A_IWL<12050> A_IWL<12049> A_IWL<12048> A_IWL<12047> A_IWL<12046> A_IWL<12045> A_IWL<12044> A_IWL<12043> A_IWL<12042> A_IWL<12041> A_IWL<12040> A_IWL<12039> A_IWL<12038> A_IWL<12037> A_IWL<12036> A_IWL<12035> A_IWL<12034> A_IWL<12033> A_IWL<12032> A_IWL<12031> A_IWL<12030> A_IWL<12029> A_IWL<12028> A_IWL<12027> A_IWL<12026> A_IWL<12025> A_IWL<12024> A_IWL<12023> A_IWL<12022> A_IWL<12021> A_IWL<12020> A_IWL<12019> A_IWL<12018> A_IWL<12017> A_IWL<12016> A_IWL<12015> A_IWL<12014> A_IWL<12013> A_IWL<12012> A_IWL<12011> A_IWL<12010> A_IWL<12009> A_IWL<12008> A_IWL<12007> A_IWL<12006> A_IWL<12005> A_IWL<12004> A_IWL<12003> A_IWL<12002> A_IWL<12001> A_IWL<12000> A_IWL<11999> A_IWL<11998> A_IWL<11997> A_IWL<11996> A_IWL<11995> A_IWL<11994> A_IWL<11993> A_IWL<11992> A_IWL<11991> A_IWL<11990> A_IWL<11989> A_IWL<11988> A_IWL<11987> A_IWL<11986> A_IWL<11985> A_IWL<11984> A_IWL<11983> A_IWL<11982> A_IWL<11981> A_IWL<11980> A_IWL<11979> A_IWL<11978> A_IWL<11977> A_IWL<11976> A_IWL<11975> A_IWL<11974> A_IWL<11973> A_IWL<11972> A_IWL<11971> A_IWL<11970> A_IWL<11969> A_IWL<11968> A_IWL<11967> A_IWL<11966> A_IWL<11965> A_IWL<11964> A_IWL<11963> A_IWL<11962> A_IWL<11961> A_IWL<11960> A_IWL<11959> A_IWL<11958> A_IWL<11957> A_IWL<11956> A_IWL<11955> A_IWL<11954> A_IWL<11953> A_IWL<11952> A_IWL<11951> A_IWL<11950> A_IWL<11949> A_IWL<11948> A_IWL<11947> A_IWL<11946> A_IWL<11945> A_IWL<11944> A_IWL<11943> A_IWL<11942> A_IWL<11941> A_IWL<11940> A_IWL<11939> A_IWL<11938> A_IWL<11937> A_IWL<11936> A_IWL<11935> A_IWL<11934> A_IWL<11933> A_IWL<11932> A_IWL<11931> A_IWL<11930> A_IWL<11929> A_IWL<11928> A_IWL<11927> A_IWL<11926> A_IWL<11925> A_IWL<11924> A_IWL<11923> A_IWL<11922> A_IWL<11921> A_IWL<11920> A_IWL<11919> A_IWL<11918> A_IWL<11917> A_IWL<11916> A_IWL<11915> A_IWL<11914> A_IWL<11913> A_IWL<11912> A_IWL<11911> A_IWL<11910> A_IWL<11909> A_IWL<11908> A_IWL<11907> A_IWL<11906> A_IWL<11905> A_IWL<11904> A_IWL<11903> A_IWL<11902> A_IWL<11901> A_IWL<11900> A_IWL<11899> A_IWL<11898> A_IWL<11897> A_IWL<11896> A_IWL<11895> A_IWL<11894> A_IWL<11893> A_IWL<11892> A_IWL<11891> A_IWL<11890> A_IWL<11889> A_IWL<11888> A_IWL<11887> A_IWL<11886> A_IWL<11885> A_IWL<11884> A_IWL<11883> A_IWL<11882> A_IWL<11881> A_IWL<11880> A_IWL<11879> A_IWL<11878> A_IWL<11877> A_IWL<11876> A_IWL<11875> A_IWL<11874> A_IWL<11873> A_IWL<11872> A_IWL<11871> A_IWL<11870> A_IWL<11869> A_IWL<11868> A_IWL<11867> A_IWL<11866> A_IWL<11865> A_IWL<11864> A_IWL<11863> A_IWL<11862> A_IWL<11861> A_IWL<11860> A_IWL<11859> A_IWL<11858> A_IWL<11857> A_IWL<11856> A_IWL<11855> A_IWL<11854> A_IWL<11853> A_IWL<11852> A_IWL<11851> A_IWL<11850> A_IWL<11849> A_IWL<11848> A_IWL<11847> A_IWL<11846> A_IWL<11845> A_IWL<11844> A_IWL<11843> A_IWL<11842> A_IWL<11841> A_IWL<11840> A_IWL<11839> A_IWL<11838> A_IWL<11837> A_IWL<11836> A_IWL<11835> A_IWL<11834> A_IWL<11833> A_IWL<11832> A_IWL<11831> A_IWL<11830> A_IWL<11829> A_IWL<11828> A_IWL<11827> A_IWL<11826> A_IWL<11825> A_IWL<11824> A_IWL<11823> A_IWL<11822> A_IWL<11821> A_IWL<11820> A_IWL<11819> A_IWL<11818> A_IWL<11817> A_IWL<11816> A_IWL<11815> A_IWL<11814> A_IWL<11813> A_IWL<11812> A_IWL<11811> A_IWL<11810> A_IWL<11809> A_IWL<11808> A_IWL<11807> A_IWL<11806> A_IWL<11805> A_IWL<11804> A_IWL<11803> A_IWL<11802> A_IWL<11801> A_IWL<11800> A_IWL<11799> A_IWL<11798> A_IWL<11797> A_IWL<11796> A_IWL<11795> A_IWL<11794> A_IWL<11793> A_IWL<11792> A_IWL<11791> A_IWL<11790> A_IWL<11789> A_IWL<11788> A_IWL<11787> A_IWL<11786> A_IWL<11785> A_IWL<11784> A_IWL<11783> A_IWL<11782> A_IWL<11781> A_IWL<11780> A_IWL<11779> A_IWL<11778> A_IWL<11777> A_IWL<11776> A_IWL<12799> A_IWL<12798> A_IWL<12797> A_IWL<12796> A_IWL<12795> A_IWL<12794> A_IWL<12793> A_IWL<12792> A_IWL<12791> A_IWL<12790> A_IWL<12789> A_IWL<12788> A_IWL<12787> A_IWL<12786> A_IWL<12785> A_IWL<12784> A_IWL<12783> A_IWL<12782> A_IWL<12781> A_IWL<12780> A_IWL<12779> A_IWL<12778> A_IWL<12777> A_IWL<12776> A_IWL<12775> A_IWL<12774> A_IWL<12773> A_IWL<12772> A_IWL<12771> A_IWL<12770> A_IWL<12769> A_IWL<12768> A_IWL<12767> A_IWL<12766> A_IWL<12765> A_IWL<12764> A_IWL<12763> A_IWL<12762> A_IWL<12761> A_IWL<12760> A_IWL<12759> A_IWL<12758> A_IWL<12757> A_IWL<12756> A_IWL<12755> A_IWL<12754> A_IWL<12753> A_IWL<12752> A_IWL<12751> A_IWL<12750> A_IWL<12749> A_IWL<12748> A_IWL<12747> A_IWL<12746> A_IWL<12745> A_IWL<12744> A_IWL<12743> A_IWL<12742> A_IWL<12741> A_IWL<12740> A_IWL<12739> A_IWL<12738> A_IWL<12737> A_IWL<12736> A_IWL<12735> A_IWL<12734> A_IWL<12733> A_IWL<12732> A_IWL<12731> A_IWL<12730> A_IWL<12729> A_IWL<12728> A_IWL<12727> A_IWL<12726> A_IWL<12725> A_IWL<12724> A_IWL<12723> A_IWL<12722> A_IWL<12721> A_IWL<12720> A_IWL<12719> A_IWL<12718> A_IWL<12717> A_IWL<12716> A_IWL<12715> A_IWL<12714> A_IWL<12713> A_IWL<12712> A_IWL<12711> A_IWL<12710> A_IWL<12709> A_IWL<12708> A_IWL<12707> A_IWL<12706> A_IWL<12705> A_IWL<12704> A_IWL<12703> A_IWL<12702> A_IWL<12701> A_IWL<12700> A_IWL<12699> A_IWL<12698> A_IWL<12697> A_IWL<12696> A_IWL<12695> A_IWL<12694> A_IWL<12693> A_IWL<12692> A_IWL<12691> A_IWL<12690> A_IWL<12689> A_IWL<12688> A_IWL<12687> A_IWL<12686> A_IWL<12685> A_IWL<12684> A_IWL<12683> A_IWL<12682> A_IWL<12681> A_IWL<12680> A_IWL<12679> A_IWL<12678> A_IWL<12677> A_IWL<12676> A_IWL<12675> A_IWL<12674> A_IWL<12673> A_IWL<12672> A_IWL<12671> A_IWL<12670> A_IWL<12669> A_IWL<12668> A_IWL<12667> A_IWL<12666> A_IWL<12665> A_IWL<12664> A_IWL<12663> A_IWL<12662> A_IWL<12661> A_IWL<12660> A_IWL<12659> A_IWL<12658> A_IWL<12657> A_IWL<12656> A_IWL<12655> A_IWL<12654> A_IWL<12653> A_IWL<12652> A_IWL<12651> A_IWL<12650> A_IWL<12649> A_IWL<12648> A_IWL<12647> A_IWL<12646> A_IWL<12645> A_IWL<12644> A_IWL<12643> A_IWL<12642> A_IWL<12641> A_IWL<12640> A_IWL<12639> A_IWL<12638> A_IWL<12637> A_IWL<12636> A_IWL<12635> A_IWL<12634> A_IWL<12633> A_IWL<12632> A_IWL<12631> A_IWL<12630> A_IWL<12629> A_IWL<12628> A_IWL<12627> A_IWL<12626> A_IWL<12625> A_IWL<12624> A_IWL<12623> A_IWL<12622> A_IWL<12621> A_IWL<12620> A_IWL<12619> A_IWL<12618> A_IWL<12617> A_IWL<12616> A_IWL<12615> A_IWL<12614> A_IWL<12613> A_IWL<12612> A_IWL<12611> A_IWL<12610> A_IWL<12609> A_IWL<12608> A_IWL<12607> A_IWL<12606> A_IWL<12605> A_IWL<12604> A_IWL<12603> A_IWL<12602> A_IWL<12601> A_IWL<12600> A_IWL<12599> A_IWL<12598> A_IWL<12597> A_IWL<12596> A_IWL<12595> A_IWL<12594> A_IWL<12593> A_IWL<12592> A_IWL<12591> A_IWL<12590> A_IWL<12589> A_IWL<12588> A_IWL<12587> A_IWL<12586> A_IWL<12585> A_IWL<12584> A_IWL<12583> A_IWL<12582> A_IWL<12581> A_IWL<12580> A_IWL<12579> A_IWL<12578> A_IWL<12577> A_IWL<12576> A_IWL<12575> A_IWL<12574> A_IWL<12573> A_IWL<12572> A_IWL<12571> A_IWL<12570> A_IWL<12569> A_IWL<12568> A_IWL<12567> A_IWL<12566> A_IWL<12565> A_IWL<12564> A_IWL<12563> A_IWL<12562> A_IWL<12561> A_IWL<12560> A_IWL<12559> A_IWL<12558> A_IWL<12557> A_IWL<12556> A_IWL<12555> A_IWL<12554> A_IWL<12553> A_IWL<12552> A_IWL<12551> A_IWL<12550> A_IWL<12549> A_IWL<12548> A_IWL<12547> A_IWL<12546> A_IWL<12545> A_IWL<12544> A_IWL<12543> A_IWL<12542> A_IWL<12541> A_IWL<12540> A_IWL<12539> A_IWL<12538> A_IWL<12537> A_IWL<12536> A_IWL<12535> A_IWL<12534> A_IWL<12533> A_IWL<12532> A_IWL<12531> A_IWL<12530> A_IWL<12529> A_IWL<12528> A_IWL<12527> A_IWL<12526> A_IWL<12525> A_IWL<12524> A_IWL<12523> A_IWL<12522> A_IWL<12521> A_IWL<12520> A_IWL<12519> A_IWL<12518> A_IWL<12517> A_IWL<12516> A_IWL<12515> A_IWL<12514> A_IWL<12513> A_IWL<12512> A_IWL<12511> A_IWL<12510> A_IWL<12509> A_IWL<12508> A_IWL<12507> A_IWL<12506> A_IWL<12505> A_IWL<12504> A_IWL<12503> A_IWL<12502> A_IWL<12501> A_IWL<12500> A_IWL<12499> A_IWL<12498> A_IWL<12497> A_IWL<12496> A_IWL<12495> A_IWL<12494> A_IWL<12493> A_IWL<12492> A_IWL<12491> A_IWL<12490> A_IWL<12489> A_IWL<12488> A_IWL<12487> A_IWL<12486> A_IWL<12485> A_IWL<12484> A_IWL<12483> A_IWL<12482> A_IWL<12481> A_IWL<12480> A_IWL<12479> A_IWL<12478> A_IWL<12477> A_IWL<12476> A_IWL<12475> A_IWL<12474> A_IWL<12473> A_IWL<12472> A_IWL<12471> A_IWL<12470> A_IWL<12469> A_IWL<12468> A_IWL<12467> A_IWL<12466> A_IWL<12465> A_IWL<12464> A_IWL<12463> A_IWL<12462> A_IWL<12461> A_IWL<12460> A_IWL<12459> A_IWL<12458> A_IWL<12457> A_IWL<12456> A_IWL<12455> A_IWL<12454> A_IWL<12453> A_IWL<12452> A_IWL<12451> A_IWL<12450> A_IWL<12449> A_IWL<12448> A_IWL<12447> A_IWL<12446> A_IWL<12445> A_IWL<12444> A_IWL<12443> A_IWL<12442> A_IWL<12441> A_IWL<12440> A_IWL<12439> A_IWL<12438> A_IWL<12437> A_IWL<12436> A_IWL<12435> A_IWL<12434> A_IWL<12433> A_IWL<12432> A_IWL<12431> A_IWL<12430> A_IWL<12429> A_IWL<12428> A_IWL<12427> A_IWL<12426> A_IWL<12425> A_IWL<12424> A_IWL<12423> A_IWL<12422> A_IWL<12421> A_IWL<12420> A_IWL<12419> A_IWL<12418> A_IWL<12417> A_IWL<12416> A_IWL<12415> A_IWL<12414> A_IWL<12413> A_IWL<12412> A_IWL<12411> A_IWL<12410> A_IWL<12409> A_IWL<12408> A_IWL<12407> A_IWL<12406> A_IWL<12405> A_IWL<12404> A_IWL<12403> A_IWL<12402> A_IWL<12401> A_IWL<12400> A_IWL<12399> A_IWL<12398> A_IWL<12397> A_IWL<12396> A_IWL<12395> A_IWL<12394> A_IWL<12393> A_IWL<12392> A_IWL<12391> A_IWL<12390> A_IWL<12389> A_IWL<12388> A_IWL<12387> A_IWL<12386> A_IWL<12385> A_IWL<12384> A_IWL<12383> A_IWL<12382> A_IWL<12381> A_IWL<12380> A_IWL<12379> A_IWL<12378> A_IWL<12377> A_IWL<12376> A_IWL<12375> A_IWL<12374> A_IWL<12373> A_IWL<12372> A_IWL<12371> A_IWL<12370> A_IWL<12369> A_IWL<12368> A_IWL<12367> A_IWL<12366> A_IWL<12365> A_IWL<12364> A_IWL<12363> A_IWL<12362> A_IWL<12361> A_IWL<12360> A_IWL<12359> A_IWL<12358> A_IWL<12357> A_IWL<12356> A_IWL<12355> A_IWL<12354> A_IWL<12353> A_IWL<12352> A_IWL<12351> A_IWL<12350> A_IWL<12349> A_IWL<12348> A_IWL<12347> A_IWL<12346> A_IWL<12345> A_IWL<12344> A_IWL<12343> A_IWL<12342> A_IWL<12341> A_IWL<12340> A_IWL<12339> A_IWL<12338> A_IWL<12337> A_IWL<12336> A_IWL<12335> A_IWL<12334> A_IWL<12333> A_IWL<12332> A_IWL<12331> A_IWL<12330> A_IWL<12329> A_IWL<12328> A_IWL<12327> A_IWL<12326> A_IWL<12325> A_IWL<12324> A_IWL<12323> A_IWL<12322> A_IWL<12321> A_IWL<12320> A_IWL<12319> A_IWL<12318> A_IWL<12317> A_IWL<12316> A_IWL<12315> A_IWL<12314> A_IWL<12313> A_IWL<12312> A_IWL<12311> A_IWL<12310> A_IWL<12309> A_IWL<12308> A_IWL<12307> A_IWL<12306> A_IWL<12305> A_IWL<12304> A_IWL<12303> A_IWL<12302> A_IWL<12301> A_IWL<12300> A_IWL<12299> A_IWL<12298> A_IWL<12297> A_IWL<12296> A_IWL<12295> A_IWL<12294> A_IWL<12293> A_IWL<12292> A_IWL<12291> A_IWL<12290> A_IWL<12289> A_IWL<12288> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_COLUMN_pcell_0 +XCOL<23> A_BLC<47> A_BLC<46> A_BLC_TOP<47> A_BLC_TOP<46> A_BLT<47> A_BLT<46> A_BLT_TOP<47> A_BLT_TOP<46> A_IWL<11775> A_IWL<11774> A_IWL<11773> A_IWL<11772> A_IWL<11771> A_IWL<11770> A_IWL<11769> A_IWL<11768> A_IWL<11767> A_IWL<11766> A_IWL<11765> A_IWL<11764> A_IWL<11763> A_IWL<11762> A_IWL<11761> A_IWL<11760> A_IWL<11759> A_IWL<11758> A_IWL<11757> A_IWL<11756> A_IWL<11755> A_IWL<11754> A_IWL<11753> A_IWL<11752> A_IWL<11751> A_IWL<11750> A_IWL<11749> A_IWL<11748> A_IWL<11747> A_IWL<11746> A_IWL<11745> A_IWL<11744> A_IWL<11743> A_IWL<11742> A_IWL<11741> A_IWL<11740> A_IWL<11739> A_IWL<11738> A_IWL<11737> A_IWL<11736> A_IWL<11735> A_IWL<11734> A_IWL<11733> A_IWL<11732> A_IWL<11731> A_IWL<11730> A_IWL<11729> A_IWL<11728> A_IWL<11727> A_IWL<11726> A_IWL<11725> A_IWL<11724> A_IWL<11723> A_IWL<11722> A_IWL<11721> A_IWL<11720> A_IWL<11719> A_IWL<11718> A_IWL<11717> A_IWL<11716> A_IWL<11715> A_IWL<11714> A_IWL<11713> A_IWL<11712> A_IWL<11711> A_IWL<11710> A_IWL<11709> A_IWL<11708> A_IWL<11707> A_IWL<11706> A_IWL<11705> A_IWL<11704> A_IWL<11703> A_IWL<11702> A_IWL<11701> A_IWL<11700> A_IWL<11699> A_IWL<11698> A_IWL<11697> A_IWL<11696> A_IWL<11695> A_IWL<11694> A_IWL<11693> A_IWL<11692> A_IWL<11691> A_IWL<11690> A_IWL<11689> A_IWL<11688> A_IWL<11687> A_IWL<11686> A_IWL<11685> A_IWL<11684> A_IWL<11683> A_IWL<11682> A_IWL<11681> A_IWL<11680> A_IWL<11679> A_IWL<11678> A_IWL<11677> A_IWL<11676> A_IWL<11675> A_IWL<11674> A_IWL<11673> A_IWL<11672> A_IWL<11671> A_IWL<11670> A_IWL<11669> A_IWL<11668> A_IWL<11667> A_IWL<11666> A_IWL<11665> A_IWL<11664> A_IWL<11663> A_IWL<11662> A_IWL<11661> A_IWL<11660> A_IWL<11659> A_IWL<11658> A_IWL<11657> A_IWL<11656> A_IWL<11655> A_IWL<11654> A_IWL<11653> A_IWL<11652> A_IWL<11651> A_IWL<11650> A_IWL<11649> A_IWL<11648> A_IWL<11647> A_IWL<11646> A_IWL<11645> A_IWL<11644> A_IWL<11643> A_IWL<11642> A_IWL<11641> A_IWL<11640> A_IWL<11639> A_IWL<11638> A_IWL<11637> A_IWL<11636> A_IWL<11635> A_IWL<11634> A_IWL<11633> A_IWL<11632> A_IWL<11631> A_IWL<11630> A_IWL<11629> A_IWL<11628> A_IWL<11627> A_IWL<11626> A_IWL<11625> A_IWL<11624> A_IWL<11623> A_IWL<11622> A_IWL<11621> A_IWL<11620> A_IWL<11619> A_IWL<11618> A_IWL<11617> A_IWL<11616> A_IWL<11615> A_IWL<11614> A_IWL<11613> A_IWL<11612> A_IWL<11611> A_IWL<11610> A_IWL<11609> A_IWL<11608> A_IWL<11607> A_IWL<11606> A_IWL<11605> A_IWL<11604> A_IWL<11603> A_IWL<11602> A_IWL<11601> A_IWL<11600> A_IWL<11599> A_IWL<11598> A_IWL<11597> A_IWL<11596> A_IWL<11595> A_IWL<11594> A_IWL<11593> A_IWL<11592> A_IWL<11591> A_IWL<11590> A_IWL<11589> A_IWL<11588> A_IWL<11587> A_IWL<11586> A_IWL<11585> A_IWL<11584> A_IWL<11583> A_IWL<11582> A_IWL<11581> A_IWL<11580> A_IWL<11579> A_IWL<11578> A_IWL<11577> A_IWL<11576> A_IWL<11575> A_IWL<11574> A_IWL<11573> A_IWL<11572> A_IWL<11571> A_IWL<11570> A_IWL<11569> A_IWL<11568> A_IWL<11567> A_IWL<11566> A_IWL<11565> A_IWL<11564> A_IWL<11563> A_IWL<11562> A_IWL<11561> A_IWL<11560> A_IWL<11559> A_IWL<11558> A_IWL<11557> A_IWL<11556> A_IWL<11555> A_IWL<11554> A_IWL<11553> A_IWL<11552> A_IWL<11551> A_IWL<11550> A_IWL<11549> A_IWL<11548> A_IWL<11547> A_IWL<11546> A_IWL<11545> A_IWL<11544> A_IWL<11543> A_IWL<11542> A_IWL<11541> A_IWL<11540> A_IWL<11539> A_IWL<11538> A_IWL<11537> A_IWL<11536> A_IWL<11535> A_IWL<11534> A_IWL<11533> A_IWL<11532> A_IWL<11531> A_IWL<11530> A_IWL<11529> A_IWL<11528> A_IWL<11527> A_IWL<11526> A_IWL<11525> A_IWL<11524> A_IWL<11523> A_IWL<11522> A_IWL<11521> A_IWL<11520> A_IWL<11519> A_IWL<11518> A_IWL<11517> A_IWL<11516> A_IWL<11515> A_IWL<11514> A_IWL<11513> A_IWL<11512> A_IWL<11511> A_IWL<11510> A_IWL<11509> A_IWL<11508> A_IWL<11507> A_IWL<11506> A_IWL<11505> A_IWL<11504> A_IWL<11503> A_IWL<11502> A_IWL<11501> A_IWL<11500> A_IWL<11499> A_IWL<11498> A_IWL<11497> A_IWL<11496> A_IWL<11495> A_IWL<11494> A_IWL<11493> A_IWL<11492> A_IWL<11491> A_IWL<11490> A_IWL<11489> A_IWL<11488> A_IWL<11487> A_IWL<11486> A_IWL<11485> A_IWL<11484> A_IWL<11483> A_IWL<11482> A_IWL<11481> A_IWL<11480> A_IWL<11479> A_IWL<11478> A_IWL<11477> A_IWL<11476> A_IWL<11475> A_IWL<11474> A_IWL<11473> A_IWL<11472> A_IWL<11471> A_IWL<11470> A_IWL<11469> A_IWL<11468> A_IWL<11467> A_IWL<11466> A_IWL<11465> A_IWL<11464> A_IWL<11463> A_IWL<11462> A_IWL<11461> A_IWL<11460> A_IWL<11459> A_IWL<11458> A_IWL<11457> A_IWL<11456> A_IWL<11455> A_IWL<11454> A_IWL<11453> A_IWL<11452> A_IWL<11451> A_IWL<11450> A_IWL<11449> A_IWL<11448> A_IWL<11447> A_IWL<11446> A_IWL<11445> A_IWL<11444> A_IWL<11443> A_IWL<11442> A_IWL<11441> A_IWL<11440> A_IWL<11439> A_IWL<11438> A_IWL<11437> A_IWL<11436> A_IWL<11435> A_IWL<11434> A_IWL<11433> A_IWL<11432> A_IWL<11431> A_IWL<11430> A_IWL<11429> A_IWL<11428> A_IWL<11427> A_IWL<11426> A_IWL<11425> A_IWL<11424> A_IWL<11423> A_IWL<11422> A_IWL<11421> A_IWL<11420> A_IWL<11419> A_IWL<11418> A_IWL<11417> A_IWL<11416> A_IWL<11415> A_IWL<11414> A_IWL<11413> A_IWL<11412> A_IWL<11411> A_IWL<11410> A_IWL<11409> A_IWL<11408> A_IWL<11407> A_IWL<11406> A_IWL<11405> A_IWL<11404> A_IWL<11403> A_IWL<11402> A_IWL<11401> A_IWL<11400> A_IWL<11399> A_IWL<11398> A_IWL<11397> A_IWL<11396> A_IWL<11395> A_IWL<11394> A_IWL<11393> A_IWL<11392> A_IWL<11391> A_IWL<11390> A_IWL<11389> A_IWL<11388> A_IWL<11387> A_IWL<11386> A_IWL<11385> A_IWL<11384> A_IWL<11383> A_IWL<11382> A_IWL<11381> A_IWL<11380> A_IWL<11379> A_IWL<11378> A_IWL<11377> A_IWL<11376> A_IWL<11375> A_IWL<11374> A_IWL<11373> A_IWL<11372> A_IWL<11371> A_IWL<11370> A_IWL<11369> A_IWL<11368> A_IWL<11367> A_IWL<11366> A_IWL<11365> A_IWL<11364> A_IWL<11363> A_IWL<11362> A_IWL<11361> A_IWL<11360> A_IWL<11359> A_IWL<11358> A_IWL<11357> A_IWL<11356> A_IWL<11355> A_IWL<11354> A_IWL<11353> A_IWL<11352> A_IWL<11351> A_IWL<11350> A_IWL<11349> A_IWL<11348> A_IWL<11347> A_IWL<11346> A_IWL<11345> A_IWL<11344> A_IWL<11343> A_IWL<11342> A_IWL<11341> A_IWL<11340> A_IWL<11339> A_IWL<11338> A_IWL<11337> A_IWL<11336> A_IWL<11335> A_IWL<11334> A_IWL<11333> A_IWL<11332> A_IWL<11331> A_IWL<11330> A_IWL<11329> A_IWL<11328> A_IWL<11327> A_IWL<11326> A_IWL<11325> A_IWL<11324> A_IWL<11323> A_IWL<11322> A_IWL<11321> A_IWL<11320> A_IWL<11319> A_IWL<11318> A_IWL<11317> A_IWL<11316> A_IWL<11315> A_IWL<11314> A_IWL<11313> A_IWL<11312> A_IWL<11311> A_IWL<11310> A_IWL<11309> A_IWL<11308> A_IWL<11307> A_IWL<11306> A_IWL<11305> A_IWL<11304> A_IWL<11303> A_IWL<11302> A_IWL<11301> A_IWL<11300> A_IWL<11299> A_IWL<11298> A_IWL<11297> A_IWL<11296> A_IWL<11295> A_IWL<11294> A_IWL<11293> A_IWL<11292> A_IWL<11291> A_IWL<11290> A_IWL<11289> A_IWL<11288> A_IWL<11287> A_IWL<11286> A_IWL<11285> A_IWL<11284> A_IWL<11283> A_IWL<11282> A_IWL<11281> A_IWL<11280> A_IWL<11279> A_IWL<11278> A_IWL<11277> A_IWL<11276> A_IWL<11275> A_IWL<11274> A_IWL<11273> A_IWL<11272> A_IWL<11271> A_IWL<11270> A_IWL<11269> A_IWL<11268> A_IWL<11267> A_IWL<11266> A_IWL<11265> A_IWL<11264> A_IWL<12287> A_IWL<12286> A_IWL<12285> A_IWL<12284> A_IWL<12283> A_IWL<12282> A_IWL<12281> A_IWL<12280> A_IWL<12279> A_IWL<12278> A_IWL<12277> A_IWL<12276> A_IWL<12275> A_IWL<12274> A_IWL<12273> A_IWL<12272> A_IWL<12271> A_IWL<12270> A_IWL<12269> A_IWL<12268> A_IWL<12267> A_IWL<12266> A_IWL<12265> A_IWL<12264> A_IWL<12263> A_IWL<12262> A_IWL<12261> A_IWL<12260> A_IWL<12259> A_IWL<12258> A_IWL<12257> A_IWL<12256> A_IWL<12255> A_IWL<12254> A_IWL<12253> A_IWL<12252> A_IWL<12251> A_IWL<12250> A_IWL<12249> A_IWL<12248> A_IWL<12247> A_IWL<12246> A_IWL<12245> A_IWL<12244> A_IWL<12243> A_IWL<12242> A_IWL<12241> A_IWL<12240> A_IWL<12239> A_IWL<12238> A_IWL<12237> A_IWL<12236> A_IWL<12235> A_IWL<12234> A_IWL<12233> A_IWL<12232> A_IWL<12231> A_IWL<12230> A_IWL<12229> A_IWL<12228> A_IWL<12227> A_IWL<12226> A_IWL<12225> A_IWL<12224> A_IWL<12223> A_IWL<12222> A_IWL<12221> A_IWL<12220> A_IWL<12219> A_IWL<12218> A_IWL<12217> A_IWL<12216> A_IWL<12215> A_IWL<12214> A_IWL<12213> A_IWL<12212> A_IWL<12211> A_IWL<12210> A_IWL<12209> A_IWL<12208> A_IWL<12207> A_IWL<12206> A_IWL<12205> A_IWL<12204> A_IWL<12203> A_IWL<12202> A_IWL<12201> A_IWL<12200> A_IWL<12199> A_IWL<12198> A_IWL<12197> A_IWL<12196> A_IWL<12195> A_IWL<12194> A_IWL<12193> A_IWL<12192> A_IWL<12191> A_IWL<12190> A_IWL<12189> A_IWL<12188> A_IWL<12187> A_IWL<12186> A_IWL<12185> A_IWL<12184> A_IWL<12183> A_IWL<12182> A_IWL<12181> A_IWL<12180> A_IWL<12179> A_IWL<12178> A_IWL<12177> A_IWL<12176> A_IWL<12175> A_IWL<12174> A_IWL<12173> A_IWL<12172> A_IWL<12171> A_IWL<12170> A_IWL<12169> A_IWL<12168> A_IWL<12167> A_IWL<12166> A_IWL<12165> A_IWL<12164> A_IWL<12163> A_IWL<12162> A_IWL<12161> A_IWL<12160> A_IWL<12159> A_IWL<12158> A_IWL<12157> A_IWL<12156> A_IWL<12155> A_IWL<12154> A_IWL<12153> A_IWL<12152> A_IWL<12151> A_IWL<12150> A_IWL<12149> A_IWL<12148> A_IWL<12147> A_IWL<12146> A_IWL<12145> A_IWL<12144> A_IWL<12143> A_IWL<12142> A_IWL<12141> A_IWL<12140> A_IWL<12139> A_IWL<12138> A_IWL<12137> A_IWL<12136> A_IWL<12135> A_IWL<12134> A_IWL<12133> A_IWL<12132> A_IWL<12131> A_IWL<12130> A_IWL<12129> A_IWL<12128> A_IWL<12127> A_IWL<12126> A_IWL<12125> A_IWL<12124> A_IWL<12123> A_IWL<12122> A_IWL<12121> A_IWL<12120> A_IWL<12119> A_IWL<12118> A_IWL<12117> A_IWL<12116> A_IWL<12115> A_IWL<12114> A_IWL<12113> A_IWL<12112> A_IWL<12111> A_IWL<12110> A_IWL<12109> A_IWL<12108> A_IWL<12107> A_IWL<12106> A_IWL<12105> A_IWL<12104> A_IWL<12103> A_IWL<12102> A_IWL<12101> A_IWL<12100> A_IWL<12099> A_IWL<12098> A_IWL<12097> A_IWL<12096> A_IWL<12095> A_IWL<12094> A_IWL<12093> A_IWL<12092> A_IWL<12091> A_IWL<12090> A_IWL<12089> A_IWL<12088> A_IWL<12087> A_IWL<12086> A_IWL<12085> A_IWL<12084> A_IWL<12083> A_IWL<12082> A_IWL<12081> A_IWL<12080> A_IWL<12079> A_IWL<12078> A_IWL<12077> A_IWL<12076> A_IWL<12075> A_IWL<12074> A_IWL<12073> A_IWL<12072> A_IWL<12071> A_IWL<12070> A_IWL<12069> A_IWL<12068> A_IWL<12067> A_IWL<12066> A_IWL<12065> A_IWL<12064> A_IWL<12063> A_IWL<12062> A_IWL<12061> A_IWL<12060> A_IWL<12059> A_IWL<12058> A_IWL<12057> A_IWL<12056> A_IWL<12055> A_IWL<12054> A_IWL<12053> A_IWL<12052> A_IWL<12051> A_IWL<12050> A_IWL<12049> A_IWL<12048> A_IWL<12047> A_IWL<12046> A_IWL<12045> A_IWL<12044> A_IWL<12043> A_IWL<12042> A_IWL<12041> A_IWL<12040> A_IWL<12039> A_IWL<12038> A_IWL<12037> A_IWL<12036> A_IWL<12035> A_IWL<12034> A_IWL<12033> A_IWL<12032> A_IWL<12031> A_IWL<12030> A_IWL<12029> A_IWL<12028> A_IWL<12027> A_IWL<12026> A_IWL<12025> A_IWL<12024> A_IWL<12023> A_IWL<12022> A_IWL<12021> A_IWL<12020> A_IWL<12019> A_IWL<12018> A_IWL<12017> A_IWL<12016> A_IWL<12015> A_IWL<12014> A_IWL<12013> A_IWL<12012> A_IWL<12011> A_IWL<12010> A_IWL<12009> A_IWL<12008> A_IWL<12007> A_IWL<12006> A_IWL<12005> A_IWL<12004> A_IWL<12003> A_IWL<12002> A_IWL<12001> A_IWL<12000> A_IWL<11999> A_IWL<11998> A_IWL<11997> A_IWL<11996> A_IWL<11995> A_IWL<11994> A_IWL<11993> A_IWL<11992> A_IWL<11991> A_IWL<11990> A_IWL<11989> A_IWL<11988> A_IWL<11987> A_IWL<11986> A_IWL<11985> A_IWL<11984> A_IWL<11983> A_IWL<11982> A_IWL<11981> A_IWL<11980> A_IWL<11979> A_IWL<11978> A_IWL<11977> A_IWL<11976> A_IWL<11975> A_IWL<11974> A_IWL<11973> A_IWL<11972> A_IWL<11971> A_IWL<11970> A_IWL<11969> A_IWL<11968> A_IWL<11967> A_IWL<11966> A_IWL<11965> A_IWL<11964> A_IWL<11963> A_IWL<11962> A_IWL<11961> A_IWL<11960> A_IWL<11959> A_IWL<11958> A_IWL<11957> A_IWL<11956> A_IWL<11955> A_IWL<11954> A_IWL<11953> A_IWL<11952> A_IWL<11951> A_IWL<11950> A_IWL<11949> A_IWL<11948> A_IWL<11947> A_IWL<11946> A_IWL<11945> A_IWL<11944> A_IWL<11943> A_IWL<11942> A_IWL<11941> A_IWL<11940> A_IWL<11939> A_IWL<11938> A_IWL<11937> A_IWL<11936> A_IWL<11935> A_IWL<11934> A_IWL<11933> A_IWL<11932> A_IWL<11931> A_IWL<11930> A_IWL<11929> A_IWL<11928> A_IWL<11927> A_IWL<11926> A_IWL<11925> A_IWL<11924> A_IWL<11923> A_IWL<11922> A_IWL<11921> A_IWL<11920> A_IWL<11919> A_IWL<11918> A_IWL<11917> A_IWL<11916> A_IWL<11915> A_IWL<11914> A_IWL<11913> A_IWL<11912> A_IWL<11911> A_IWL<11910> A_IWL<11909> A_IWL<11908> A_IWL<11907> A_IWL<11906> A_IWL<11905> A_IWL<11904> A_IWL<11903> A_IWL<11902> A_IWL<11901> A_IWL<11900> A_IWL<11899> A_IWL<11898> A_IWL<11897> A_IWL<11896> A_IWL<11895> A_IWL<11894> A_IWL<11893> A_IWL<11892> A_IWL<11891> A_IWL<11890> A_IWL<11889> A_IWL<11888> A_IWL<11887> A_IWL<11886> A_IWL<11885> A_IWL<11884> A_IWL<11883> A_IWL<11882> A_IWL<11881> A_IWL<11880> A_IWL<11879> A_IWL<11878> A_IWL<11877> A_IWL<11876> A_IWL<11875> A_IWL<11874> A_IWL<11873> A_IWL<11872> A_IWL<11871> A_IWL<11870> A_IWL<11869> A_IWL<11868> A_IWL<11867> A_IWL<11866> A_IWL<11865> A_IWL<11864> A_IWL<11863> A_IWL<11862> A_IWL<11861> A_IWL<11860> A_IWL<11859> A_IWL<11858> A_IWL<11857> A_IWL<11856> A_IWL<11855> A_IWL<11854> A_IWL<11853> A_IWL<11852> A_IWL<11851> A_IWL<11850> A_IWL<11849> A_IWL<11848> A_IWL<11847> A_IWL<11846> A_IWL<11845> A_IWL<11844> A_IWL<11843> A_IWL<11842> A_IWL<11841> A_IWL<11840> A_IWL<11839> A_IWL<11838> A_IWL<11837> A_IWL<11836> A_IWL<11835> A_IWL<11834> A_IWL<11833> A_IWL<11832> A_IWL<11831> A_IWL<11830> A_IWL<11829> A_IWL<11828> A_IWL<11827> A_IWL<11826> A_IWL<11825> A_IWL<11824> A_IWL<11823> A_IWL<11822> A_IWL<11821> A_IWL<11820> A_IWL<11819> A_IWL<11818> A_IWL<11817> A_IWL<11816> A_IWL<11815> A_IWL<11814> A_IWL<11813> A_IWL<11812> A_IWL<11811> A_IWL<11810> A_IWL<11809> A_IWL<11808> A_IWL<11807> A_IWL<11806> A_IWL<11805> A_IWL<11804> A_IWL<11803> A_IWL<11802> A_IWL<11801> A_IWL<11800> A_IWL<11799> A_IWL<11798> A_IWL<11797> A_IWL<11796> A_IWL<11795> A_IWL<11794> A_IWL<11793> A_IWL<11792> A_IWL<11791> A_IWL<11790> A_IWL<11789> A_IWL<11788> A_IWL<11787> A_IWL<11786> A_IWL<11785> A_IWL<11784> A_IWL<11783> A_IWL<11782> A_IWL<11781> A_IWL<11780> A_IWL<11779> A_IWL<11778> A_IWL<11777> A_IWL<11776> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_COLUMN_pcell_0 +XCOL<22> A_BLC<45> A_BLC<44> A_BLC_TOP<45> A_BLC_TOP<44> A_BLT<45> A_BLT<44> A_BLT_TOP<45> A_BLT_TOP<44> A_IWL<11263> A_IWL<11262> A_IWL<11261> A_IWL<11260> A_IWL<11259> A_IWL<11258> A_IWL<11257> A_IWL<11256> A_IWL<11255> A_IWL<11254> A_IWL<11253> A_IWL<11252> A_IWL<11251> A_IWL<11250> A_IWL<11249> A_IWL<11248> A_IWL<11247> A_IWL<11246> A_IWL<11245> A_IWL<11244> A_IWL<11243> A_IWL<11242> A_IWL<11241> A_IWL<11240> A_IWL<11239> A_IWL<11238> A_IWL<11237> A_IWL<11236> A_IWL<11235> A_IWL<11234> A_IWL<11233> A_IWL<11232> A_IWL<11231> A_IWL<11230> A_IWL<11229> A_IWL<11228> A_IWL<11227> A_IWL<11226> A_IWL<11225> A_IWL<11224> A_IWL<11223> A_IWL<11222> A_IWL<11221> A_IWL<11220> A_IWL<11219> A_IWL<11218> A_IWL<11217> A_IWL<11216> A_IWL<11215> A_IWL<11214> A_IWL<11213> A_IWL<11212> A_IWL<11211> A_IWL<11210> A_IWL<11209> A_IWL<11208> A_IWL<11207> A_IWL<11206> A_IWL<11205> A_IWL<11204> A_IWL<11203> A_IWL<11202> A_IWL<11201> A_IWL<11200> A_IWL<11199> A_IWL<11198> A_IWL<11197> A_IWL<11196> A_IWL<11195> A_IWL<11194> A_IWL<11193> A_IWL<11192> A_IWL<11191> A_IWL<11190> A_IWL<11189> A_IWL<11188> A_IWL<11187> A_IWL<11186> A_IWL<11185> A_IWL<11184> A_IWL<11183> A_IWL<11182> A_IWL<11181> A_IWL<11180> A_IWL<11179> A_IWL<11178> A_IWL<11177> A_IWL<11176> A_IWL<11175> A_IWL<11174> A_IWL<11173> A_IWL<11172> A_IWL<11171> A_IWL<11170> A_IWL<11169> A_IWL<11168> A_IWL<11167> A_IWL<11166> A_IWL<11165> A_IWL<11164> A_IWL<11163> A_IWL<11162> A_IWL<11161> A_IWL<11160> A_IWL<11159> A_IWL<11158> A_IWL<11157> A_IWL<11156> A_IWL<11155> A_IWL<11154> A_IWL<11153> A_IWL<11152> A_IWL<11151> A_IWL<11150> A_IWL<11149> A_IWL<11148> A_IWL<11147> A_IWL<11146> A_IWL<11145> A_IWL<11144> A_IWL<11143> A_IWL<11142> A_IWL<11141> A_IWL<11140> A_IWL<11139> A_IWL<11138> A_IWL<11137> A_IWL<11136> A_IWL<11135> A_IWL<11134> A_IWL<11133> A_IWL<11132> A_IWL<11131> A_IWL<11130> A_IWL<11129> A_IWL<11128> A_IWL<11127> A_IWL<11126> A_IWL<11125> A_IWL<11124> A_IWL<11123> A_IWL<11122> A_IWL<11121> A_IWL<11120> A_IWL<11119> A_IWL<11118> A_IWL<11117> A_IWL<11116> A_IWL<11115> A_IWL<11114> A_IWL<11113> A_IWL<11112> A_IWL<11111> A_IWL<11110> A_IWL<11109> A_IWL<11108> A_IWL<11107> A_IWL<11106> A_IWL<11105> A_IWL<11104> A_IWL<11103> A_IWL<11102> A_IWL<11101> A_IWL<11100> A_IWL<11099> A_IWL<11098> A_IWL<11097> A_IWL<11096> A_IWL<11095> A_IWL<11094> A_IWL<11093> A_IWL<11092> A_IWL<11091> A_IWL<11090> A_IWL<11089> A_IWL<11088> A_IWL<11087> A_IWL<11086> A_IWL<11085> A_IWL<11084> A_IWL<11083> A_IWL<11082> A_IWL<11081> A_IWL<11080> A_IWL<11079> A_IWL<11078> A_IWL<11077> A_IWL<11076> A_IWL<11075> A_IWL<11074> A_IWL<11073> A_IWL<11072> A_IWL<11071> A_IWL<11070> A_IWL<11069> A_IWL<11068> A_IWL<11067> A_IWL<11066> A_IWL<11065> A_IWL<11064> A_IWL<11063> A_IWL<11062> A_IWL<11061> A_IWL<11060> A_IWL<11059> A_IWL<11058> A_IWL<11057> A_IWL<11056> A_IWL<11055> A_IWL<11054> A_IWL<11053> A_IWL<11052> A_IWL<11051> A_IWL<11050> A_IWL<11049> A_IWL<11048> A_IWL<11047> A_IWL<11046> A_IWL<11045> A_IWL<11044> A_IWL<11043> A_IWL<11042> A_IWL<11041> A_IWL<11040> A_IWL<11039> A_IWL<11038> A_IWL<11037> A_IWL<11036> A_IWL<11035> A_IWL<11034> A_IWL<11033> A_IWL<11032> A_IWL<11031> A_IWL<11030> A_IWL<11029> A_IWL<11028> A_IWL<11027> A_IWL<11026> A_IWL<11025> A_IWL<11024> A_IWL<11023> A_IWL<11022> A_IWL<11021> A_IWL<11020> A_IWL<11019> A_IWL<11018> A_IWL<11017> A_IWL<11016> A_IWL<11015> A_IWL<11014> A_IWL<11013> A_IWL<11012> A_IWL<11011> A_IWL<11010> A_IWL<11009> A_IWL<11008> A_IWL<11007> A_IWL<11006> A_IWL<11005> A_IWL<11004> A_IWL<11003> A_IWL<11002> A_IWL<11001> A_IWL<11000> A_IWL<10999> A_IWL<10998> A_IWL<10997> A_IWL<10996> A_IWL<10995> A_IWL<10994> A_IWL<10993> A_IWL<10992> A_IWL<10991> A_IWL<10990> A_IWL<10989> A_IWL<10988> A_IWL<10987> A_IWL<10986> A_IWL<10985> A_IWL<10984> A_IWL<10983> A_IWL<10982> A_IWL<10981> A_IWL<10980> A_IWL<10979> A_IWL<10978> A_IWL<10977> A_IWL<10976> A_IWL<10975> A_IWL<10974> A_IWL<10973> A_IWL<10972> A_IWL<10971> A_IWL<10970> A_IWL<10969> A_IWL<10968> A_IWL<10967> A_IWL<10966> A_IWL<10965> A_IWL<10964> A_IWL<10963> A_IWL<10962> A_IWL<10961> A_IWL<10960> A_IWL<10959> A_IWL<10958> A_IWL<10957> A_IWL<10956> A_IWL<10955> A_IWL<10954> A_IWL<10953> A_IWL<10952> A_IWL<10951> A_IWL<10950> A_IWL<10949> A_IWL<10948> A_IWL<10947> A_IWL<10946> A_IWL<10945> A_IWL<10944> A_IWL<10943> A_IWL<10942> A_IWL<10941> A_IWL<10940> A_IWL<10939> A_IWL<10938> A_IWL<10937> A_IWL<10936> A_IWL<10935> A_IWL<10934> A_IWL<10933> A_IWL<10932> A_IWL<10931> A_IWL<10930> A_IWL<10929> A_IWL<10928> A_IWL<10927> A_IWL<10926> A_IWL<10925> A_IWL<10924> A_IWL<10923> A_IWL<10922> A_IWL<10921> A_IWL<10920> A_IWL<10919> A_IWL<10918> A_IWL<10917> A_IWL<10916> A_IWL<10915> A_IWL<10914> A_IWL<10913> A_IWL<10912> A_IWL<10911> A_IWL<10910> A_IWL<10909> A_IWL<10908> A_IWL<10907> A_IWL<10906> A_IWL<10905> A_IWL<10904> A_IWL<10903> A_IWL<10902> A_IWL<10901> A_IWL<10900> A_IWL<10899> A_IWL<10898> A_IWL<10897> A_IWL<10896> A_IWL<10895> A_IWL<10894> A_IWL<10893> A_IWL<10892> A_IWL<10891> A_IWL<10890> A_IWL<10889> A_IWL<10888> A_IWL<10887> A_IWL<10886> A_IWL<10885> A_IWL<10884> A_IWL<10883> A_IWL<10882> A_IWL<10881> A_IWL<10880> A_IWL<10879> A_IWL<10878> A_IWL<10877> A_IWL<10876> A_IWL<10875> A_IWL<10874> A_IWL<10873> A_IWL<10872> A_IWL<10871> A_IWL<10870> A_IWL<10869> A_IWL<10868> A_IWL<10867> A_IWL<10866> A_IWL<10865> A_IWL<10864> A_IWL<10863> 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A_IWL<11732> A_IWL<11731> A_IWL<11730> A_IWL<11729> A_IWL<11728> A_IWL<11727> A_IWL<11726> A_IWL<11725> A_IWL<11724> A_IWL<11723> A_IWL<11722> A_IWL<11721> A_IWL<11720> A_IWL<11719> A_IWL<11718> A_IWL<11717> A_IWL<11716> A_IWL<11715> A_IWL<11714> A_IWL<11713> A_IWL<11712> A_IWL<11711> A_IWL<11710> A_IWL<11709> A_IWL<11708> A_IWL<11707> A_IWL<11706> A_IWL<11705> A_IWL<11704> A_IWL<11703> A_IWL<11702> A_IWL<11701> A_IWL<11700> A_IWL<11699> A_IWL<11698> A_IWL<11697> A_IWL<11696> A_IWL<11695> A_IWL<11694> A_IWL<11693> A_IWL<11692> A_IWL<11691> A_IWL<11690> A_IWL<11689> A_IWL<11688> A_IWL<11687> A_IWL<11686> A_IWL<11685> A_IWL<11684> A_IWL<11683> A_IWL<11682> A_IWL<11681> A_IWL<11680> A_IWL<11679> A_IWL<11678> A_IWL<11677> A_IWL<11676> A_IWL<11675> A_IWL<11674> A_IWL<11673> A_IWL<11672> A_IWL<11671> A_IWL<11670> A_IWL<11669> A_IWL<11668> A_IWL<11667> A_IWL<11666> A_IWL<11665> A_IWL<11664> A_IWL<11663> A_IWL<11662> A_IWL<11661> A_IWL<11660> A_IWL<11659> A_IWL<11658> A_IWL<11657> A_IWL<11656> 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A_IWL<10617> A_IWL<10616> A_IWL<10615> A_IWL<10614> A_IWL<10613> A_IWL<10612> A_IWL<10611> A_IWL<10610> A_IWL<10609> A_IWL<10608> A_IWL<10607> A_IWL<10606> A_IWL<10605> A_IWL<10604> A_IWL<10603> A_IWL<10602> A_IWL<10601> A_IWL<10600> A_IWL<10599> A_IWL<10598> A_IWL<10597> A_IWL<10596> A_IWL<10595> A_IWL<10594> A_IWL<10593> A_IWL<10592> A_IWL<10591> A_IWL<10590> A_IWL<10589> A_IWL<10588> A_IWL<10587> A_IWL<10586> A_IWL<10585> A_IWL<10584> A_IWL<10583> A_IWL<10582> A_IWL<10581> A_IWL<10580> A_IWL<10579> A_IWL<10578> A_IWL<10577> A_IWL<10576> A_IWL<10575> A_IWL<10574> A_IWL<10573> A_IWL<10572> A_IWL<10571> A_IWL<10570> A_IWL<10569> A_IWL<10568> A_IWL<10567> A_IWL<10566> A_IWL<10565> A_IWL<10564> A_IWL<10563> A_IWL<10562> A_IWL<10561> A_IWL<10560> A_IWL<10559> A_IWL<10558> A_IWL<10557> A_IWL<10556> A_IWL<10555> A_IWL<10554> A_IWL<10553> A_IWL<10552> A_IWL<10551> A_IWL<10550> A_IWL<10549> A_IWL<10548> A_IWL<10547> A_IWL<10546> A_IWL<10545> A_IWL<10544> A_IWL<10543> A_IWL<10542> A_IWL<10541> A_IWL<10540> A_IWL<10539> A_IWL<10538> A_IWL<10537> A_IWL<10536> A_IWL<10535> A_IWL<10534> A_IWL<10533> A_IWL<10532> A_IWL<10531> A_IWL<10530> A_IWL<10529> A_IWL<10528> A_IWL<10527> A_IWL<10526> A_IWL<10525> A_IWL<10524> A_IWL<10523> A_IWL<10522> A_IWL<10521> A_IWL<10520> A_IWL<10519> A_IWL<10518> A_IWL<10517> A_IWL<10516> A_IWL<10515> A_IWL<10514> A_IWL<10513> A_IWL<10512> A_IWL<10511> A_IWL<10510> A_IWL<10509> A_IWL<10508> A_IWL<10507> A_IWL<10506> A_IWL<10505> A_IWL<10504> A_IWL<10503> A_IWL<10502> A_IWL<10501> A_IWL<10500> A_IWL<10499> A_IWL<10498> A_IWL<10497> A_IWL<10496> A_IWL<10495> A_IWL<10494> A_IWL<10493> A_IWL<10492> A_IWL<10491> A_IWL<10490> A_IWL<10489> A_IWL<10488> A_IWL<10487> A_IWL<10486> A_IWL<10485> A_IWL<10484> A_IWL<10483> A_IWL<10482> A_IWL<10481> A_IWL<10480> A_IWL<10479> A_IWL<10478> A_IWL<10477> A_IWL<10476> A_IWL<10475> A_IWL<10474> A_IWL<10473> A_IWL<10472> A_IWL<10471> A_IWL<10470> A_IWL<10469> A_IWL<10468> A_IWL<10467> A_IWL<10466> A_IWL<10465> A_IWL<10464> A_IWL<10463> A_IWL<10462> A_IWL<10461> A_IWL<10460> A_IWL<10459> A_IWL<10458> A_IWL<10457> A_IWL<10456> A_IWL<10455> A_IWL<10454> A_IWL<10453> A_IWL<10452> A_IWL<10451> A_IWL<10450> A_IWL<10449> A_IWL<10448> A_IWL<10447> A_IWL<10446> A_IWL<10445> A_IWL<10444> A_IWL<10443> A_IWL<10442> A_IWL<10441> A_IWL<10440> A_IWL<10439> A_IWL<10438> A_IWL<10437> A_IWL<10436> A_IWL<10435> A_IWL<10434> A_IWL<10433> A_IWL<10432> A_IWL<10431> A_IWL<10430> A_IWL<10429> A_IWL<10428> A_IWL<10427> A_IWL<10426> A_IWL<10425> A_IWL<10424> A_IWL<10423> A_IWL<10422> A_IWL<10421> A_IWL<10420> A_IWL<10419> A_IWL<10418> A_IWL<10417> A_IWL<10416> A_IWL<10415> A_IWL<10414> A_IWL<10413> A_IWL<10412> A_IWL<10411> A_IWL<10410> A_IWL<10409> A_IWL<10408> A_IWL<10407> A_IWL<10406> A_IWL<10405> A_IWL<10404> A_IWL<10403> A_IWL<10402> A_IWL<10401> A_IWL<10400> A_IWL<10399> A_IWL<10398> A_IWL<10397> A_IWL<10396> A_IWL<10395> A_IWL<10394> A_IWL<10393> A_IWL<10392> A_IWL<10391> A_IWL<10390> A_IWL<10389> A_IWL<10388> A_IWL<10387> A_IWL<10386> A_IWL<10385> A_IWL<10384> A_IWL<10383> A_IWL<10382> A_IWL<10381> A_IWL<10380> A_IWL<10379> A_IWL<10378> A_IWL<10377> A_IWL<10376> A_IWL<10375> A_IWL<10374> A_IWL<10373> A_IWL<10372> A_IWL<10371> A_IWL<10370> A_IWL<10369> A_IWL<10368> A_IWL<10367> A_IWL<10366> A_IWL<10365> A_IWL<10364> A_IWL<10363> A_IWL<10362> A_IWL<10361> A_IWL<10360> A_IWL<10359> A_IWL<10358> A_IWL<10357> A_IWL<10356> A_IWL<10355> A_IWL<10354> A_IWL<10353> A_IWL<10352> A_IWL<10351> A_IWL<10350> A_IWL<10349> A_IWL<10348> A_IWL<10347> A_IWL<10346> A_IWL<10345> A_IWL<10344> A_IWL<10343> A_IWL<10342> A_IWL<10341> A_IWL<10340> A_IWL<10339> A_IWL<10338> A_IWL<10337> A_IWL<10336> A_IWL<10335> A_IWL<10334> A_IWL<10333> A_IWL<10332> A_IWL<10331> A_IWL<10330> A_IWL<10329> A_IWL<10328> A_IWL<10327> A_IWL<10326> A_IWL<10325> A_IWL<10324> A_IWL<10323> A_IWL<10322> A_IWL<10321> A_IWL<10320> A_IWL<10319> A_IWL<10318> A_IWL<10317> A_IWL<10316> A_IWL<10315> A_IWL<10314> A_IWL<10313> A_IWL<10312> A_IWL<10311> A_IWL<10310> A_IWL<10309> A_IWL<10308> A_IWL<10307> A_IWL<10306> A_IWL<10305> A_IWL<10304> A_IWL<10303> A_IWL<10302> A_IWL<10301> A_IWL<10300> A_IWL<10299> A_IWL<10298> A_IWL<10297> A_IWL<10296> A_IWL<10295> A_IWL<10294> A_IWL<10293> A_IWL<10292> A_IWL<10291> A_IWL<10290> A_IWL<10289> A_IWL<10288> A_IWL<10287> A_IWL<10286> A_IWL<10285> A_IWL<10284> A_IWL<10283> A_IWL<10282> A_IWL<10281> A_IWL<10280> A_IWL<10279> A_IWL<10278> A_IWL<10277> A_IWL<10276> A_IWL<10275> A_IWL<10274> A_IWL<10273> A_IWL<10272> A_IWL<10271> A_IWL<10270> A_IWL<10269> A_IWL<10268> A_IWL<10267> A_IWL<10266> A_IWL<10265> A_IWL<10264> A_IWL<10263> A_IWL<10262> A_IWL<10261> A_IWL<10260> A_IWL<10259> A_IWL<10258> A_IWL<10257> A_IWL<10256> A_IWL<10255> A_IWL<10254> A_IWL<10253> A_IWL<10252> A_IWL<10251> A_IWL<10250> A_IWL<10249> A_IWL<10248> A_IWL<10247> A_IWL<10246> A_IWL<10245> A_IWL<10244> A_IWL<10243> A_IWL<10242> A_IWL<10241> A_IWL<10240> A_IWL<11263> A_IWL<11262> A_IWL<11261> A_IWL<11260> A_IWL<11259> A_IWL<11258> A_IWL<11257> A_IWL<11256> A_IWL<11255> A_IWL<11254> A_IWL<11253> A_IWL<11252> A_IWL<11251> A_IWL<11250> A_IWL<11249> A_IWL<11248> A_IWL<11247> A_IWL<11246> A_IWL<11245> A_IWL<11244> A_IWL<11243> A_IWL<11242> A_IWL<11241> A_IWL<11240> A_IWL<11239> A_IWL<11238> A_IWL<11237> A_IWL<11236> A_IWL<11235> A_IWL<11234> A_IWL<11233> A_IWL<11232> A_IWL<11231> A_IWL<11230> A_IWL<11229> A_IWL<11228> A_IWL<11227> A_IWL<11226> A_IWL<11225> A_IWL<11224> A_IWL<11223> A_IWL<11222> A_IWL<11221> A_IWL<11220> A_IWL<11219> A_IWL<11218> A_IWL<11217> A_IWL<11216> A_IWL<11215> A_IWL<11214> A_IWL<11213> A_IWL<11212> A_IWL<11211> A_IWL<11210> A_IWL<11209> A_IWL<11208> A_IWL<11207> A_IWL<11206> A_IWL<11205> A_IWL<11204> A_IWL<11203> A_IWL<11202> A_IWL<11201> A_IWL<11200> A_IWL<11199> A_IWL<11198> A_IWL<11197> A_IWL<11196> A_IWL<11195> A_IWL<11194> A_IWL<11193> A_IWL<11192> A_IWL<11191> A_IWL<11190> A_IWL<11189> A_IWL<11188> A_IWL<11187> A_IWL<11186> A_IWL<11185> A_IWL<11184> A_IWL<11183> A_IWL<11182> A_IWL<11181> A_IWL<11180> A_IWL<11179> A_IWL<11178> A_IWL<11177> A_IWL<11176> A_IWL<11175> A_IWL<11174> A_IWL<11173> A_IWL<11172> A_IWL<11171> A_IWL<11170> A_IWL<11169> A_IWL<11168> A_IWL<11167> A_IWL<11166> A_IWL<11165> A_IWL<11164> A_IWL<11163> A_IWL<11162> A_IWL<11161> A_IWL<11160> A_IWL<11159> A_IWL<11158> A_IWL<11157> A_IWL<11156> A_IWL<11155> A_IWL<11154> A_IWL<11153> A_IWL<11152> A_IWL<11151> A_IWL<11150> A_IWL<11149> A_IWL<11148> A_IWL<11147> A_IWL<11146> A_IWL<11145> A_IWL<11144> A_IWL<11143> A_IWL<11142> A_IWL<11141> A_IWL<11140> A_IWL<11139> A_IWL<11138> A_IWL<11137> A_IWL<11136> A_IWL<11135> A_IWL<11134> A_IWL<11133> A_IWL<11132> A_IWL<11131> A_IWL<11130> A_IWL<11129> A_IWL<11128> A_IWL<11127> A_IWL<11126> A_IWL<11125> A_IWL<11124> A_IWL<11123> A_IWL<11122> A_IWL<11121> A_IWL<11120> A_IWL<11119> A_IWL<11118> A_IWL<11117> A_IWL<11116> A_IWL<11115> A_IWL<11114> A_IWL<11113> A_IWL<11112> A_IWL<11111> A_IWL<11110> A_IWL<11109> A_IWL<11108> A_IWL<11107> A_IWL<11106> A_IWL<11105> A_IWL<11104> A_IWL<11103> A_IWL<11102> A_IWL<11101> A_IWL<11100> A_IWL<11099> A_IWL<11098> A_IWL<11097> A_IWL<11096> A_IWL<11095> A_IWL<11094> A_IWL<11093> A_IWL<11092> A_IWL<11091> A_IWL<11090> A_IWL<11089> A_IWL<11088> A_IWL<11087> A_IWL<11086> A_IWL<11085> A_IWL<11084> A_IWL<11083> A_IWL<11082> A_IWL<11081> A_IWL<11080> A_IWL<11079> A_IWL<11078> A_IWL<11077> A_IWL<11076> A_IWL<11075> A_IWL<11074> A_IWL<11073> A_IWL<11072> A_IWL<11071> A_IWL<11070> A_IWL<11069> A_IWL<11068> A_IWL<11067> A_IWL<11066> A_IWL<11065> A_IWL<11064> A_IWL<11063> A_IWL<11062> A_IWL<11061> A_IWL<11060> A_IWL<11059> A_IWL<11058> A_IWL<11057> A_IWL<11056> A_IWL<11055> A_IWL<11054> A_IWL<11053> A_IWL<11052> A_IWL<11051> A_IWL<11050> A_IWL<11049> A_IWL<11048> A_IWL<11047> A_IWL<11046> A_IWL<11045> A_IWL<11044> A_IWL<11043> A_IWL<11042> A_IWL<11041> A_IWL<11040> A_IWL<11039> A_IWL<11038> A_IWL<11037> A_IWL<11036> A_IWL<11035> A_IWL<11034> A_IWL<11033> A_IWL<11032> A_IWL<11031> A_IWL<11030> A_IWL<11029> A_IWL<11028> A_IWL<11027> A_IWL<11026> A_IWL<11025> A_IWL<11024> A_IWL<11023> A_IWL<11022> A_IWL<11021> A_IWL<11020> A_IWL<11019> A_IWL<11018> A_IWL<11017> A_IWL<11016> A_IWL<11015> A_IWL<11014> A_IWL<11013> A_IWL<11012> A_IWL<11011> A_IWL<11010> A_IWL<11009> A_IWL<11008> A_IWL<11007> A_IWL<11006> A_IWL<11005> A_IWL<11004> A_IWL<11003> A_IWL<11002> A_IWL<11001> A_IWL<11000> A_IWL<10999> A_IWL<10998> A_IWL<10997> A_IWL<10996> A_IWL<10995> A_IWL<10994> A_IWL<10993> A_IWL<10992> A_IWL<10991> A_IWL<10990> A_IWL<10989> A_IWL<10988> A_IWL<10987> A_IWL<10986> A_IWL<10985> A_IWL<10984> A_IWL<10983> A_IWL<10982> A_IWL<10981> A_IWL<10980> A_IWL<10979> A_IWL<10978> A_IWL<10977> A_IWL<10976> A_IWL<10975> A_IWL<10974> A_IWL<10973> A_IWL<10972> A_IWL<10971> A_IWL<10970> A_IWL<10969> A_IWL<10968> A_IWL<10967> A_IWL<10966> A_IWL<10965> A_IWL<10964> A_IWL<10963> A_IWL<10962> A_IWL<10961> A_IWL<10960> A_IWL<10959> A_IWL<10958> A_IWL<10957> A_IWL<10956> A_IWL<10955> A_IWL<10954> A_IWL<10953> A_IWL<10952> A_IWL<10951> A_IWL<10950> A_IWL<10949> A_IWL<10948> A_IWL<10947> A_IWL<10946> A_IWL<10945> A_IWL<10944> A_IWL<10943> A_IWL<10942> A_IWL<10941> A_IWL<10940> A_IWL<10939> A_IWL<10938> A_IWL<10937> A_IWL<10936> A_IWL<10935> A_IWL<10934> A_IWL<10933> A_IWL<10932> A_IWL<10931> A_IWL<10930> A_IWL<10929> A_IWL<10928> A_IWL<10927> A_IWL<10926> A_IWL<10925> A_IWL<10924> A_IWL<10923> A_IWL<10922> A_IWL<10921> A_IWL<10920> A_IWL<10919> A_IWL<10918> A_IWL<10917> A_IWL<10916> A_IWL<10915> A_IWL<10914> A_IWL<10913> A_IWL<10912> A_IWL<10911> A_IWL<10910> A_IWL<10909> A_IWL<10908> A_IWL<10907> A_IWL<10906> A_IWL<10905> A_IWL<10904> A_IWL<10903> A_IWL<10902> A_IWL<10901> A_IWL<10900> A_IWL<10899> A_IWL<10898> A_IWL<10897> A_IWL<10896> A_IWL<10895> A_IWL<10894> A_IWL<10893> A_IWL<10892> A_IWL<10891> A_IWL<10890> A_IWL<10889> A_IWL<10888> A_IWL<10887> A_IWL<10886> A_IWL<10885> A_IWL<10884> A_IWL<10883> A_IWL<10882> A_IWL<10881> A_IWL<10880> A_IWL<10879> A_IWL<10878> A_IWL<10877> A_IWL<10876> A_IWL<10875> A_IWL<10874> A_IWL<10873> A_IWL<10872> A_IWL<10871> A_IWL<10870> A_IWL<10869> A_IWL<10868> A_IWL<10867> A_IWL<10866> A_IWL<10865> A_IWL<10864> A_IWL<10863> A_IWL<10862> A_IWL<10861> A_IWL<10860> A_IWL<10859> A_IWL<10858> A_IWL<10857> A_IWL<10856> A_IWL<10855> A_IWL<10854> A_IWL<10853> A_IWL<10852> A_IWL<10851> A_IWL<10850> A_IWL<10849> A_IWL<10848> A_IWL<10847> A_IWL<10846> A_IWL<10845> A_IWL<10844> A_IWL<10843> A_IWL<10842> A_IWL<10841> A_IWL<10840> A_IWL<10839> A_IWL<10838> A_IWL<10837> A_IWL<10836> A_IWL<10835> A_IWL<10834> A_IWL<10833> A_IWL<10832> A_IWL<10831> A_IWL<10830> A_IWL<10829> A_IWL<10828> A_IWL<10827> A_IWL<10826> A_IWL<10825> A_IWL<10824> A_IWL<10823> A_IWL<10822> A_IWL<10821> A_IWL<10820> A_IWL<10819> A_IWL<10818> A_IWL<10817> A_IWL<10816> A_IWL<10815> A_IWL<10814> A_IWL<10813> A_IWL<10812> A_IWL<10811> A_IWL<10810> A_IWL<10809> A_IWL<10808> A_IWL<10807> A_IWL<10806> A_IWL<10805> A_IWL<10804> A_IWL<10803> A_IWL<10802> A_IWL<10801> A_IWL<10800> A_IWL<10799> A_IWL<10798> A_IWL<10797> A_IWL<10796> A_IWL<10795> A_IWL<10794> A_IWL<10793> A_IWL<10792> A_IWL<10791> A_IWL<10790> A_IWL<10789> A_IWL<10788> A_IWL<10787> A_IWL<10786> A_IWL<10785> A_IWL<10784> A_IWL<10783> A_IWL<10782> A_IWL<10781> A_IWL<10780> A_IWL<10779> A_IWL<10778> A_IWL<10777> A_IWL<10776> A_IWL<10775> A_IWL<10774> A_IWL<10773> A_IWL<10772> A_IWL<10771> A_IWL<10770> A_IWL<10769> A_IWL<10768> A_IWL<10767> A_IWL<10766> A_IWL<10765> A_IWL<10764> A_IWL<10763> A_IWL<10762> A_IWL<10761> A_IWL<10760> A_IWL<10759> A_IWL<10758> A_IWL<10757> A_IWL<10756> A_IWL<10755> A_IWL<10754> A_IWL<10753> A_IWL<10752> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_COLUMN_pcell_0 +XCOL<20> A_BLC<41> A_BLC<40> A_BLC_TOP<41> A_BLC_TOP<40> A_BLT<41> A_BLT<40> A_BLT_TOP<41> A_BLT_TOP<40> A_IWL<10239> A_IWL<10238> A_IWL<10237> A_IWL<10236> A_IWL<10235> A_IWL<10234> A_IWL<10233> A_IWL<10232> A_IWL<10231> A_IWL<10230> A_IWL<10229> A_IWL<10228> A_IWL<10227> A_IWL<10226> A_IWL<10225> A_IWL<10224> A_IWL<10223> A_IWL<10222> A_IWL<10221> A_IWL<10220> A_IWL<10219> A_IWL<10218> A_IWL<10217> A_IWL<10216> A_IWL<10215> A_IWL<10214> A_IWL<10213> A_IWL<10212> A_IWL<10211> A_IWL<10210> A_IWL<10209> A_IWL<10208> A_IWL<10207> A_IWL<10206> A_IWL<10205> A_IWL<10204> A_IWL<10203> A_IWL<10202> A_IWL<10201> A_IWL<10200> A_IWL<10199> A_IWL<10198> A_IWL<10197> A_IWL<10196> A_IWL<10195> A_IWL<10194> A_IWL<10193> A_IWL<10192> A_IWL<10191> A_IWL<10190> A_IWL<10189> A_IWL<10188> A_IWL<10187> A_IWL<10186> A_IWL<10185> A_IWL<10184> A_IWL<10183> A_IWL<10182> A_IWL<10181> A_IWL<10180> A_IWL<10179> A_IWL<10178> A_IWL<10177> A_IWL<10176> A_IWL<10175> A_IWL<10174> A_IWL<10173> A_IWL<10172> A_IWL<10171> A_IWL<10170> A_IWL<10169> A_IWL<10168> A_IWL<10167> A_IWL<10166> A_IWL<10165> A_IWL<10164> A_IWL<10163> A_IWL<10162> A_IWL<10161> A_IWL<10160> A_IWL<10159> A_IWL<10158> A_IWL<10157> A_IWL<10156> A_IWL<10155> A_IWL<10154> A_IWL<10153> A_IWL<10152> A_IWL<10151> A_IWL<10150> A_IWL<10149> A_IWL<10148> A_IWL<10147> A_IWL<10146> A_IWL<10145> A_IWL<10144> A_IWL<10143> A_IWL<10142> A_IWL<10141> A_IWL<10140> A_IWL<10139> A_IWL<10138> A_IWL<10137> A_IWL<10136> A_IWL<10135> A_IWL<10134> A_IWL<10133> A_IWL<10132> A_IWL<10131> A_IWL<10130> A_IWL<10129> A_IWL<10128> A_IWL<10127> A_IWL<10126> A_IWL<10125> A_IWL<10124> A_IWL<10123> A_IWL<10122> A_IWL<10121> A_IWL<10120> A_IWL<10119> A_IWL<10118> A_IWL<10117> A_IWL<10116> A_IWL<10115> A_IWL<10114> A_IWL<10113> A_IWL<10112> A_IWL<10111> A_IWL<10110> A_IWL<10109> A_IWL<10108> A_IWL<10107> A_IWL<10106> A_IWL<10105> A_IWL<10104> A_IWL<10103> A_IWL<10102> A_IWL<10101> A_IWL<10100> A_IWL<10099> A_IWL<10098> A_IWL<10097> A_IWL<10096> A_IWL<10095> A_IWL<10094> A_IWL<10093> A_IWL<10092> A_IWL<10091> A_IWL<10090> A_IWL<10089> A_IWL<10088> A_IWL<10087> A_IWL<10086> A_IWL<10085> A_IWL<10084> A_IWL<10083> A_IWL<10082> A_IWL<10081> A_IWL<10080> A_IWL<10079> A_IWL<10078> A_IWL<10077> A_IWL<10076> A_IWL<10075> A_IWL<10074> A_IWL<10073> A_IWL<10072> A_IWL<10071> A_IWL<10070> A_IWL<10069> A_IWL<10068> A_IWL<10067> A_IWL<10066> A_IWL<10065> A_IWL<10064> A_IWL<10063> A_IWL<10062> A_IWL<10061> A_IWL<10060> A_IWL<10059> A_IWL<10058> A_IWL<10057> A_IWL<10056> A_IWL<10055> A_IWL<10054> A_IWL<10053> A_IWL<10052> A_IWL<10051> A_IWL<10050> A_IWL<10049> A_IWL<10048> A_IWL<10047> A_IWL<10046> A_IWL<10045> A_IWL<10044> A_IWL<10043> A_IWL<10042> A_IWL<10041> A_IWL<10040> A_IWL<10039> A_IWL<10038> A_IWL<10037> A_IWL<10036> A_IWL<10035> A_IWL<10034> A_IWL<10033> A_IWL<10032> A_IWL<10031> A_IWL<10030> A_IWL<10029> A_IWL<10028> A_IWL<10027> A_IWL<10026> A_IWL<10025> A_IWL<10024> A_IWL<10023> A_IWL<10022> A_IWL<10021> A_IWL<10020> A_IWL<10019> A_IWL<10018> A_IWL<10017> A_IWL<10016> A_IWL<10015> A_IWL<10014> A_IWL<10013> A_IWL<10012> A_IWL<10011> A_IWL<10010> A_IWL<10009> A_IWL<10008> A_IWL<10007> A_IWL<10006> A_IWL<10005> A_IWL<10004> A_IWL<10003> A_IWL<10002> A_IWL<10001> A_IWL<10000> A_IWL<9999> A_IWL<9998> A_IWL<9997> A_IWL<9996> A_IWL<9995> A_IWL<9994> A_IWL<9993> A_IWL<9992> A_IWL<9991> A_IWL<9990> A_IWL<9989> A_IWL<9988> A_IWL<9987> A_IWL<9986> A_IWL<9985> A_IWL<9984> A_IWL<9983> A_IWL<9982> A_IWL<9981> A_IWL<9980> A_IWL<9979> A_IWL<9978> A_IWL<9977> A_IWL<9976> A_IWL<9975> A_IWL<9974> A_IWL<9973> A_IWL<9972> A_IWL<9971> A_IWL<9970> A_IWL<9969> A_IWL<9968> A_IWL<9967> A_IWL<9966> A_IWL<9965> A_IWL<9964> A_IWL<9963> A_IWL<9962> A_IWL<9961> A_IWL<9960> A_IWL<9959> A_IWL<9958> A_IWL<9957> A_IWL<9956> A_IWL<9955> A_IWL<9954> A_IWL<9953> A_IWL<9952> A_IWL<9951> A_IWL<9950> A_IWL<9949> A_IWL<9948> A_IWL<9947> A_IWL<9946> A_IWL<9945> A_IWL<9944> A_IWL<9943> A_IWL<9942> A_IWL<9941> A_IWL<9940> A_IWL<9939> A_IWL<9938> A_IWL<9937> A_IWL<9936> A_IWL<9935> A_IWL<9934> A_IWL<9933> A_IWL<9932> A_IWL<9931> A_IWL<9930> A_IWL<9929> A_IWL<9928> A_IWL<9927> A_IWL<9926> A_IWL<9925> A_IWL<9924> A_IWL<9923> A_IWL<9922> A_IWL<9921> A_IWL<9920> A_IWL<9919> A_IWL<9918> A_IWL<9917> A_IWL<9916> A_IWL<9915> A_IWL<9914> A_IWL<9913> A_IWL<9912> A_IWL<9911> A_IWL<9910> A_IWL<9909> A_IWL<9908> A_IWL<9907> A_IWL<9906> A_IWL<9905> A_IWL<9904> A_IWL<9903> A_IWL<9902> A_IWL<9901> A_IWL<9900> A_IWL<9899> A_IWL<9898> A_IWL<9897> A_IWL<9896> A_IWL<9895> A_IWL<9894> A_IWL<9893> A_IWL<9892> A_IWL<9891> A_IWL<9890> A_IWL<9889> A_IWL<9888> A_IWL<9887> A_IWL<9886> A_IWL<9885> A_IWL<9884> A_IWL<9883> A_IWL<9882> A_IWL<9881> A_IWL<9880> A_IWL<9879> A_IWL<9878> A_IWL<9877> A_IWL<9876> A_IWL<9875> A_IWL<9874> A_IWL<9873> A_IWL<9872> A_IWL<9871> A_IWL<9870> A_IWL<9869> A_IWL<9868> A_IWL<9867> A_IWL<9866> A_IWL<9865> A_IWL<9864> A_IWL<9863> A_IWL<9862> A_IWL<9861> A_IWL<9860> A_IWL<9859> A_IWL<9858> A_IWL<9857> A_IWL<9856> A_IWL<9855> A_IWL<9854> A_IWL<9853> A_IWL<9852> A_IWL<9851> A_IWL<9850> A_IWL<9849> A_IWL<9848> A_IWL<9847> A_IWL<9846> A_IWL<9845> A_IWL<9844> A_IWL<9843> A_IWL<9842> A_IWL<9841> A_IWL<9840> A_IWL<9839> A_IWL<9838> A_IWL<9837> A_IWL<9836> A_IWL<9835> A_IWL<9834> A_IWL<9833> A_IWL<9832> A_IWL<9831> A_IWL<9830> A_IWL<9829> A_IWL<9828> A_IWL<9827> A_IWL<9826> A_IWL<9825> A_IWL<9824> A_IWL<9823> A_IWL<9822> A_IWL<9821> A_IWL<9820> A_IWL<9819> A_IWL<9818> A_IWL<9817> A_IWL<9816> A_IWL<9815> A_IWL<9814> A_IWL<9813> A_IWL<9812> A_IWL<9811> A_IWL<9810> A_IWL<9809> A_IWL<9808> A_IWL<9807> A_IWL<9806> A_IWL<9805> A_IWL<9804> A_IWL<9803> A_IWL<9802> A_IWL<9801> A_IWL<9800> A_IWL<9799> A_IWL<9798> A_IWL<9797> A_IWL<9796> A_IWL<9795> A_IWL<9794> A_IWL<9793> A_IWL<9792> A_IWL<9791> A_IWL<9790> A_IWL<9789> A_IWL<9788> A_IWL<9787> A_IWL<9786> A_IWL<9785> A_IWL<9784> A_IWL<9783> A_IWL<9782> A_IWL<9781> A_IWL<9780> A_IWL<9779> A_IWL<9778> A_IWL<9777> A_IWL<9776> A_IWL<9775> A_IWL<9774> A_IWL<9773> A_IWL<9772> A_IWL<9771> A_IWL<9770> A_IWL<9769> A_IWL<9768> A_IWL<9767> A_IWL<9766> A_IWL<9765> A_IWL<9764> A_IWL<9763> A_IWL<9762> A_IWL<9761> A_IWL<9760> A_IWL<9759> A_IWL<9758> A_IWL<9757> A_IWL<9756> A_IWL<9755> A_IWL<9754> A_IWL<9753> A_IWL<9752> A_IWL<9751> A_IWL<9750> A_IWL<9749> A_IWL<9748> A_IWL<9747> A_IWL<9746> A_IWL<9745> A_IWL<9744> A_IWL<9743> A_IWL<9742> A_IWL<9741> A_IWL<9740> A_IWL<9739> A_IWL<9738> A_IWL<9737> A_IWL<9736> A_IWL<9735> A_IWL<9734> A_IWL<9733> A_IWL<9732> A_IWL<9731> A_IWL<9730> A_IWL<9729> A_IWL<9728> A_IWL<10751> A_IWL<10750> A_IWL<10749> A_IWL<10748> A_IWL<10747> A_IWL<10746> A_IWL<10745> A_IWL<10744> A_IWL<10743> A_IWL<10742> A_IWL<10741> A_IWL<10740> A_IWL<10739> A_IWL<10738> A_IWL<10737> A_IWL<10736> A_IWL<10735> A_IWL<10734> A_IWL<10733> A_IWL<10732> A_IWL<10731> A_IWL<10730> A_IWL<10729> A_IWL<10728> A_IWL<10727> A_IWL<10726> A_IWL<10725> A_IWL<10724> A_IWL<10723> A_IWL<10722> A_IWL<10721> A_IWL<10720> A_IWL<10719> A_IWL<10718> A_IWL<10717> A_IWL<10716> A_IWL<10715> A_IWL<10714> A_IWL<10713> A_IWL<10712> A_IWL<10711> A_IWL<10710> A_IWL<10709> A_IWL<10708> A_IWL<10707> A_IWL<10706> A_IWL<10705> A_IWL<10704> A_IWL<10703> A_IWL<10702> A_IWL<10701> A_IWL<10700> A_IWL<10699> A_IWL<10698> A_IWL<10697> A_IWL<10696> A_IWL<10695> A_IWL<10694> A_IWL<10693> A_IWL<10692> A_IWL<10691> A_IWL<10690> A_IWL<10689> A_IWL<10688> A_IWL<10687> A_IWL<10686> A_IWL<10685> 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A_IWL<10453> A_IWL<10452> A_IWL<10451> A_IWL<10450> A_IWL<10449> A_IWL<10448> A_IWL<10447> A_IWL<10446> A_IWL<10445> A_IWL<10444> A_IWL<10443> A_IWL<10442> A_IWL<10441> A_IWL<10440> A_IWL<10439> A_IWL<10438> A_IWL<10437> A_IWL<10436> A_IWL<10435> A_IWL<10434> A_IWL<10433> A_IWL<10432> A_IWL<10431> A_IWL<10430> A_IWL<10429> A_IWL<10428> A_IWL<10427> A_IWL<10426> A_IWL<10425> A_IWL<10424> A_IWL<10423> A_IWL<10422> A_IWL<10421> A_IWL<10420> A_IWL<10419> A_IWL<10418> A_IWL<10417> A_IWL<10416> A_IWL<10415> A_IWL<10414> A_IWL<10413> A_IWL<10412> A_IWL<10411> A_IWL<10410> A_IWL<10409> A_IWL<10408> A_IWL<10407> A_IWL<10406> A_IWL<10405> A_IWL<10404> A_IWL<10403> A_IWL<10402> A_IWL<10401> A_IWL<10400> A_IWL<10399> A_IWL<10398> A_IWL<10397> A_IWL<10396> A_IWL<10395> A_IWL<10394> A_IWL<10393> A_IWL<10392> A_IWL<10391> A_IWL<10390> A_IWL<10389> A_IWL<10388> A_IWL<10387> A_IWL<10386> A_IWL<10385> A_IWL<10384> A_IWL<10383> A_IWL<10382> A_IWL<10381> A_IWL<10380> A_IWL<10379> A_IWL<10378> A_IWL<10377> A_IWL<10376> A_IWL<10375> A_IWL<10374> A_IWL<10373> A_IWL<10372> A_IWL<10371> A_IWL<10370> A_IWL<10369> A_IWL<10368> A_IWL<10367> A_IWL<10366> A_IWL<10365> A_IWL<10364> A_IWL<10363> A_IWL<10362> A_IWL<10361> A_IWL<10360> A_IWL<10359> A_IWL<10358> A_IWL<10357> A_IWL<10356> A_IWL<10355> A_IWL<10354> A_IWL<10353> A_IWL<10352> A_IWL<10351> A_IWL<10350> A_IWL<10349> A_IWL<10348> A_IWL<10347> A_IWL<10346> A_IWL<10345> A_IWL<10344> A_IWL<10343> A_IWL<10342> A_IWL<10341> A_IWL<10340> A_IWL<10339> A_IWL<10338> A_IWL<10337> A_IWL<10336> A_IWL<10335> A_IWL<10334> A_IWL<10333> A_IWL<10332> A_IWL<10331> A_IWL<10330> A_IWL<10329> A_IWL<10328> A_IWL<10327> A_IWL<10326> A_IWL<10325> A_IWL<10324> A_IWL<10323> A_IWL<10322> A_IWL<10321> A_IWL<10320> A_IWL<10319> A_IWL<10318> A_IWL<10317> A_IWL<10316> A_IWL<10315> A_IWL<10314> A_IWL<10313> A_IWL<10312> A_IWL<10311> A_IWL<10310> A_IWL<10309> A_IWL<10308> A_IWL<10307> A_IWL<10306> A_IWL<10305> A_IWL<10304> A_IWL<10303> A_IWL<10302> A_IWL<10301> A_IWL<10300> A_IWL<10299> A_IWL<10298> A_IWL<10297> A_IWL<10296> A_IWL<10295> A_IWL<10294> A_IWL<10293> A_IWL<10292> A_IWL<10291> A_IWL<10290> A_IWL<10289> A_IWL<10288> A_IWL<10287> A_IWL<10286> A_IWL<10285> A_IWL<10284> A_IWL<10283> A_IWL<10282> A_IWL<10281> A_IWL<10280> A_IWL<10279> A_IWL<10278> A_IWL<10277> A_IWL<10276> A_IWL<10275> A_IWL<10274> A_IWL<10273> A_IWL<10272> A_IWL<10271> A_IWL<10270> A_IWL<10269> A_IWL<10268> A_IWL<10267> A_IWL<10266> A_IWL<10265> A_IWL<10264> A_IWL<10263> A_IWL<10262> A_IWL<10261> A_IWL<10260> A_IWL<10259> A_IWL<10258> A_IWL<10257> A_IWL<10256> A_IWL<10255> A_IWL<10254> A_IWL<10253> A_IWL<10252> A_IWL<10251> A_IWL<10250> A_IWL<10249> A_IWL<10248> A_IWL<10247> A_IWL<10246> A_IWL<10245> A_IWL<10244> A_IWL<10243> A_IWL<10242> A_IWL<10241> A_IWL<10240> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_COLUMN_pcell_0 +XCOL<19> A_BLC<39> A_BLC<38> A_BLC_TOP<39> A_BLC_TOP<38> A_BLT<39> A_BLT<38> A_BLT_TOP<39> A_BLT_TOP<38> A_IWL<9727> A_IWL<9726> A_IWL<9725> A_IWL<9724> A_IWL<9723> A_IWL<9722> A_IWL<9721> A_IWL<9720> A_IWL<9719> A_IWL<9718> A_IWL<9717> A_IWL<9716> A_IWL<9715> A_IWL<9714> A_IWL<9713> A_IWL<9712> A_IWL<9711> A_IWL<9710> A_IWL<9709> A_IWL<9708> A_IWL<9707> A_IWL<9706> A_IWL<9705> A_IWL<9704> A_IWL<9703> A_IWL<9702> A_IWL<9701> A_IWL<9700> A_IWL<9699> A_IWL<9698> A_IWL<9697> A_IWL<9696> A_IWL<9695> A_IWL<9694> A_IWL<9693> A_IWL<9692> A_IWL<9691> A_IWL<9690> A_IWL<9689> A_IWL<9688> A_IWL<9687> A_IWL<9686> A_IWL<9685> A_IWL<9684> A_IWL<9683> A_IWL<9682> A_IWL<9681> A_IWL<9680> A_IWL<9679> A_IWL<9678> A_IWL<9677> A_IWL<9676> A_IWL<9675> A_IWL<9674> A_IWL<9673> A_IWL<9672> A_IWL<9671> A_IWL<9670> A_IWL<9669> A_IWL<9668> A_IWL<9667> A_IWL<9666> A_IWL<9665> A_IWL<9664> A_IWL<9663> A_IWL<9662> A_IWL<9661> A_IWL<9660> A_IWL<9659> A_IWL<9658> A_IWL<9657> A_IWL<9656> A_IWL<9655> A_IWL<9654> A_IWL<9653> A_IWL<9652> A_IWL<9651> A_IWL<9650> A_IWL<9649> A_IWL<9648> A_IWL<9647> A_IWL<9646> A_IWL<9645> A_IWL<9644> A_IWL<9643> A_IWL<9642> A_IWL<9641> A_IWL<9640> A_IWL<9639> A_IWL<9638> A_IWL<9637> A_IWL<9636> A_IWL<9635> A_IWL<9634> A_IWL<9633> A_IWL<9632> A_IWL<9631> A_IWL<9630> A_IWL<9629> A_IWL<9628> A_IWL<9627> A_IWL<9626> A_IWL<9625> A_IWL<9624> A_IWL<9623> A_IWL<9622> A_IWL<9621> A_IWL<9620> A_IWL<9619> A_IWL<9618> A_IWL<9617> A_IWL<9616> A_IWL<9615> A_IWL<9614> A_IWL<9613> A_IWL<9612> A_IWL<9611> A_IWL<9610> A_IWL<9609> A_IWL<9608> A_IWL<9607> A_IWL<9606> A_IWL<9605> A_IWL<9604> A_IWL<9603> A_IWL<9602> A_IWL<9601> A_IWL<9600> A_IWL<9599> A_IWL<9598> A_IWL<9597> A_IWL<9596> A_IWL<9595> A_IWL<9594> A_IWL<9593> A_IWL<9592> A_IWL<9591> A_IWL<9590> A_IWL<9589> A_IWL<9588> A_IWL<9587> A_IWL<9586> A_IWL<9585> A_IWL<9584> A_IWL<9583> A_IWL<9582> A_IWL<9581> A_IWL<9580> A_IWL<9579> A_IWL<9578> A_IWL<9577> A_IWL<9576> A_IWL<9575> A_IWL<9574> A_IWL<9573> A_IWL<9572> A_IWL<9571> A_IWL<9570> A_IWL<9569> A_IWL<9568> A_IWL<9567> A_IWL<9566> A_IWL<9565> A_IWL<9564> A_IWL<9563> A_IWL<9562> A_IWL<9561> A_IWL<9560> A_IWL<9559> A_IWL<9558> A_IWL<9557> A_IWL<9556> A_IWL<9555> A_IWL<9554> A_IWL<9553> A_IWL<9552> A_IWL<9551> A_IWL<9550> A_IWL<9549> A_IWL<9548> A_IWL<9547> A_IWL<9546> A_IWL<9545> A_IWL<9544> A_IWL<9543> A_IWL<9542> A_IWL<9541> A_IWL<9540> A_IWL<9539> A_IWL<9538> A_IWL<9537> A_IWL<9536> A_IWL<9535> A_IWL<9534> A_IWL<9533> A_IWL<9532> A_IWL<9531> A_IWL<9530> A_IWL<9529> A_IWL<9528> A_IWL<9527> A_IWL<9526> A_IWL<9525> A_IWL<9524> A_IWL<9523> A_IWL<9522> A_IWL<9521> A_IWL<9520> A_IWL<9519> A_IWL<9518> A_IWL<9517> A_IWL<9516> A_IWL<9515> A_IWL<9514> A_IWL<9513> A_IWL<9512> A_IWL<9511> A_IWL<9510> A_IWL<9509> A_IWL<9508> A_IWL<9507> A_IWL<9506> A_IWL<9505> A_IWL<9504> A_IWL<9503> A_IWL<9502> A_IWL<9501> A_IWL<9500> A_IWL<9499> A_IWL<9498> A_IWL<9497> A_IWL<9496> A_IWL<9495> A_IWL<9494> A_IWL<9493> A_IWL<9492> A_IWL<9491> A_IWL<9490> A_IWL<9489> A_IWL<9488> A_IWL<9487> A_IWL<9486> A_IWL<9485> A_IWL<9484> A_IWL<9483> A_IWL<9482> A_IWL<9481> A_IWL<9480> A_IWL<9479> A_IWL<9478> A_IWL<9477> A_IWL<9476> A_IWL<9475> A_IWL<9474> A_IWL<9473> A_IWL<9472> A_IWL<9471> A_IWL<9470> A_IWL<9469> A_IWL<9468> A_IWL<9467> A_IWL<9466> A_IWL<9465> A_IWL<9464> A_IWL<9463> A_IWL<9462> A_IWL<9461> A_IWL<9460> A_IWL<9459> A_IWL<9458> A_IWL<9457> A_IWL<9456> A_IWL<9455> A_IWL<9454> A_IWL<9453> A_IWL<9452> A_IWL<9451> A_IWL<9450> A_IWL<9449> A_IWL<9448> A_IWL<9447> A_IWL<9446> A_IWL<9445> A_IWL<9444> A_IWL<9443> A_IWL<9442> A_IWL<9441> A_IWL<9440> A_IWL<9439> A_IWL<9438> A_IWL<9437> A_IWL<9436> A_IWL<9435> A_IWL<9434> A_IWL<9433> A_IWL<9432> A_IWL<9431> A_IWL<9430> A_IWL<9429> A_IWL<9428> A_IWL<9427> A_IWL<9426> A_IWL<9425> A_IWL<9424> A_IWL<9423> A_IWL<9422> A_IWL<9421> A_IWL<9420> A_IWL<9419> A_IWL<9418> A_IWL<9417> A_IWL<9416> A_IWL<9415> A_IWL<9414> A_IWL<9413> A_IWL<9412> A_IWL<9411> A_IWL<9410> A_IWL<9409> A_IWL<9408> A_IWL<9407> A_IWL<9406> A_IWL<9405> A_IWL<9404> A_IWL<9403> A_IWL<9402> A_IWL<9401> A_IWL<9400> A_IWL<9399> A_IWL<9398> A_IWL<9397> A_IWL<9396> A_IWL<9395> A_IWL<9394> A_IWL<9393> A_IWL<9392> A_IWL<9391> A_IWL<9390> A_IWL<9389> A_IWL<9388> A_IWL<9387> A_IWL<9386> A_IWL<9385> A_IWL<9384> A_IWL<9383> A_IWL<9382> A_IWL<9381> A_IWL<9380> A_IWL<9379> A_IWL<9378> A_IWL<9377> A_IWL<9376> A_IWL<9375> A_IWL<9374> A_IWL<9373> A_IWL<9372> A_IWL<9371> A_IWL<9370> A_IWL<9369> A_IWL<9368> A_IWL<9367> A_IWL<9366> A_IWL<9365> A_IWL<9364> A_IWL<9363> A_IWL<9362> A_IWL<9361> A_IWL<9360> A_IWL<9359> A_IWL<9358> A_IWL<9357> A_IWL<9356> A_IWL<9355> A_IWL<9354> A_IWL<9353> A_IWL<9352> A_IWL<9351> A_IWL<9350> A_IWL<9349> A_IWL<9348> A_IWL<9347> A_IWL<9346> A_IWL<9345> A_IWL<9344> A_IWL<9343> A_IWL<9342> A_IWL<9341> A_IWL<9340> A_IWL<9339> A_IWL<9338> A_IWL<9337> A_IWL<9336> A_IWL<9335> A_IWL<9334> A_IWL<9333> A_IWL<9332> A_IWL<9331> A_IWL<9330> A_IWL<9329> A_IWL<9328> A_IWL<9327> A_IWL<9326> A_IWL<9325> A_IWL<9324> A_IWL<9323> A_IWL<9322> A_IWL<9321> A_IWL<9320> A_IWL<9319> A_IWL<9318> A_IWL<9317> A_IWL<9316> A_IWL<9315> A_IWL<9314> A_IWL<9313> A_IWL<9312> A_IWL<9311> A_IWL<9310> A_IWL<9309> A_IWL<9308> A_IWL<9307> A_IWL<9306> A_IWL<9305> A_IWL<9304> A_IWL<9303> A_IWL<9302> A_IWL<9301> A_IWL<9300> A_IWL<9299> A_IWL<9298> A_IWL<9297> A_IWL<9296> A_IWL<9295> A_IWL<9294> A_IWL<9293> A_IWL<9292> A_IWL<9291> A_IWL<9290> A_IWL<9289> A_IWL<9288> A_IWL<9287> A_IWL<9286> A_IWL<9285> A_IWL<9284> A_IWL<9283> A_IWL<9282> A_IWL<9281> A_IWL<9280> A_IWL<9279> A_IWL<9278> A_IWL<9277> A_IWL<9276> A_IWL<9275> A_IWL<9274> A_IWL<9273> A_IWL<9272> A_IWL<9271> A_IWL<9270> A_IWL<9269> A_IWL<9268> A_IWL<9267> A_IWL<9266> A_IWL<9265> A_IWL<9264> A_IWL<9263> A_IWL<9262> A_IWL<9261> A_IWL<9260> A_IWL<9259> A_IWL<9258> A_IWL<9257> A_IWL<9256> A_IWL<9255> A_IWL<9254> A_IWL<9253> A_IWL<9252> A_IWL<9251> A_IWL<9250> A_IWL<9249> A_IWL<9248> A_IWL<9247> A_IWL<9246> A_IWL<9245> A_IWL<9244> A_IWL<9243> A_IWL<9242> A_IWL<9241> A_IWL<9240> A_IWL<9239> A_IWL<9238> A_IWL<9237> A_IWL<9236> A_IWL<9235> A_IWL<9234> A_IWL<9233> A_IWL<9232> A_IWL<9231> A_IWL<9230> A_IWL<9229> A_IWL<9228> A_IWL<9227> A_IWL<9226> A_IWL<9225> A_IWL<9224> A_IWL<9223> A_IWL<9222> A_IWL<9221> A_IWL<9220> A_IWL<9219> A_IWL<9218> A_IWL<9217> A_IWL<9216> A_IWL<10239> A_IWL<10238> A_IWL<10237> A_IWL<10236> A_IWL<10235> A_IWL<10234> A_IWL<10233> A_IWL<10232> A_IWL<10231> A_IWL<10230> A_IWL<10229> A_IWL<10228> A_IWL<10227> A_IWL<10226> A_IWL<10225> A_IWL<10224> A_IWL<10223> A_IWL<10222> A_IWL<10221> A_IWL<10220> A_IWL<10219> A_IWL<10218> A_IWL<10217> A_IWL<10216> A_IWL<10215> A_IWL<10214> A_IWL<10213> A_IWL<10212> A_IWL<10211> A_IWL<10210> A_IWL<10209> A_IWL<10208> A_IWL<10207> A_IWL<10206> A_IWL<10205> A_IWL<10204> A_IWL<10203> A_IWL<10202> A_IWL<10201> A_IWL<10200> A_IWL<10199> A_IWL<10198> A_IWL<10197> A_IWL<10196> A_IWL<10195> A_IWL<10194> A_IWL<10193> A_IWL<10192> A_IWL<10191> A_IWL<10190> A_IWL<10189> A_IWL<10188> A_IWL<10187> A_IWL<10186> A_IWL<10185> A_IWL<10184> A_IWL<10183> A_IWL<10182> A_IWL<10181> A_IWL<10180> A_IWL<10179> A_IWL<10178> A_IWL<10177> A_IWL<10176> A_IWL<10175> A_IWL<10174> A_IWL<10173> A_IWL<10172> A_IWL<10171> A_IWL<10170> A_IWL<10169> A_IWL<10168> A_IWL<10167> A_IWL<10166> A_IWL<10165> A_IWL<10164> A_IWL<10163> A_IWL<10162> A_IWL<10161> A_IWL<10160> A_IWL<10159> A_IWL<10158> A_IWL<10157> A_IWL<10156> A_IWL<10155> A_IWL<10154> A_IWL<10153> A_IWL<10152> A_IWL<10151> A_IWL<10150> A_IWL<10149> A_IWL<10148> A_IWL<10147> A_IWL<10146> A_IWL<10145> A_IWL<10144> A_IWL<10143> A_IWL<10142> A_IWL<10141> A_IWL<10140> A_IWL<10139> A_IWL<10138> A_IWL<10137> A_IWL<10136> A_IWL<10135> A_IWL<10134> A_IWL<10133> A_IWL<10132> A_IWL<10131> A_IWL<10130> A_IWL<10129> A_IWL<10128> A_IWL<10127> A_IWL<10126> A_IWL<10125> A_IWL<10124> A_IWL<10123> A_IWL<10122> A_IWL<10121> A_IWL<10120> A_IWL<10119> A_IWL<10118> A_IWL<10117> A_IWL<10116> A_IWL<10115> A_IWL<10114> A_IWL<10113> A_IWL<10112> A_IWL<10111> A_IWL<10110> A_IWL<10109> A_IWL<10108> A_IWL<10107> A_IWL<10106> A_IWL<10105> A_IWL<10104> A_IWL<10103> A_IWL<10102> A_IWL<10101> A_IWL<10100> A_IWL<10099> A_IWL<10098> A_IWL<10097> A_IWL<10096> A_IWL<10095> A_IWL<10094> A_IWL<10093> A_IWL<10092> A_IWL<10091> A_IWL<10090> A_IWL<10089> A_IWL<10088> A_IWL<10087> A_IWL<10086> A_IWL<10085> A_IWL<10084> A_IWL<10083> A_IWL<10082> A_IWL<10081> A_IWL<10080> A_IWL<10079> A_IWL<10078> A_IWL<10077> A_IWL<10076> A_IWL<10075> A_IWL<10074> A_IWL<10073> A_IWL<10072> A_IWL<10071> A_IWL<10070> A_IWL<10069> A_IWL<10068> A_IWL<10067> A_IWL<10066> A_IWL<10065> A_IWL<10064> A_IWL<10063> A_IWL<10062> A_IWL<10061> A_IWL<10060> A_IWL<10059> A_IWL<10058> A_IWL<10057> A_IWL<10056> A_IWL<10055> A_IWL<10054> A_IWL<10053> A_IWL<10052> A_IWL<10051> A_IWL<10050> A_IWL<10049> A_IWL<10048> A_IWL<10047> A_IWL<10046> A_IWL<10045> A_IWL<10044> A_IWL<10043> A_IWL<10042> A_IWL<10041> A_IWL<10040> A_IWL<10039> A_IWL<10038> A_IWL<10037> A_IWL<10036> A_IWL<10035> A_IWL<10034> A_IWL<10033> A_IWL<10032> A_IWL<10031> A_IWL<10030> A_IWL<10029> A_IWL<10028> A_IWL<10027> A_IWL<10026> A_IWL<10025> A_IWL<10024> A_IWL<10023> A_IWL<10022> A_IWL<10021> A_IWL<10020> A_IWL<10019> A_IWL<10018> A_IWL<10017> A_IWL<10016> A_IWL<10015> A_IWL<10014> A_IWL<10013> A_IWL<10012> A_IWL<10011> A_IWL<10010> A_IWL<10009> A_IWL<10008> A_IWL<10007> A_IWL<10006> A_IWL<10005> A_IWL<10004> A_IWL<10003> A_IWL<10002> A_IWL<10001> A_IWL<10000> A_IWL<9999> A_IWL<9998> A_IWL<9997> A_IWL<9996> A_IWL<9995> A_IWL<9994> A_IWL<9993> A_IWL<9992> A_IWL<9991> A_IWL<9990> A_IWL<9989> A_IWL<9988> A_IWL<9987> A_IWL<9986> A_IWL<9985> A_IWL<9984> A_IWL<9983> A_IWL<9982> A_IWL<9981> A_IWL<9980> A_IWL<9979> A_IWL<9978> A_IWL<9977> A_IWL<9976> A_IWL<9975> A_IWL<9974> A_IWL<9973> A_IWL<9972> A_IWL<9971> A_IWL<9970> A_IWL<9969> A_IWL<9968> A_IWL<9967> A_IWL<9966> A_IWL<9965> A_IWL<9964> A_IWL<9963> A_IWL<9962> A_IWL<9961> A_IWL<9960> A_IWL<9959> A_IWL<9958> A_IWL<9957> A_IWL<9956> A_IWL<9955> A_IWL<9954> A_IWL<9953> A_IWL<9952> A_IWL<9951> A_IWL<9950> A_IWL<9949> A_IWL<9948> A_IWL<9947> A_IWL<9946> A_IWL<9945> A_IWL<9944> A_IWL<9943> A_IWL<9942> A_IWL<9941> A_IWL<9940> A_IWL<9939> A_IWL<9938> A_IWL<9937> A_IWL<9936> A_IWL<9935> A_IWL<9934> A_IWL<9933> A_IWL<9932> A_IWL<9931> A_IWL<9930> A_IWL<9929> A_IWL<9928> A_IWL<9927> A_IWL<9926> A_IWL<9925> A_IWL<9924> A_IWL<9923> A_IWL<9922> A_IWL<9921> A_IWL<9920> A_IWL<9919> A_IWL<9918> A_IWL<9917> A_IWL<9916> A_IWL<9915> A_IWL<9914> A_IWL<9913> A_IWL<9912> A_IWL<9911> A_IWL<9910> A_IWL<9909> A_IWL<9908> A_IWL<9907> A_IWL<9906> A_IWL<9905> A_IWL<9904> A_IWL<9903> A_IWL<9902> A_IWL<9901> A_IWL<9900> A_IWL<9899> A_IWL<9898> A_IWL<9897> A_IWL<9896> A_IWL<9895> A_IWL<9894> A_IWL<9893> A_IWL<9892> A_IWL<9891> A_IWL<9890> A_IWL<9889> A_IWL<9888> A_IWL<9887> A_IWL<9886> A_IWL<9885> A_IWL<9884> A_IWL<9883> A_IWL<9882> A_IWL<9881> A_IWL<9880> A_IWL<9879> A_IWL<9878> A_IWL<9877> A_IWL<9876> A_IWL<9875> A_IWL<9874> A_IWL<9873> A_IWL<9872> A_IWL<9871> A_IWL<9870> A_IWL<9869> A_IWL<9868> A_IWL<9867> A_IWL<9866> A_IWL<9865> A_IWL<9864> A_IWL<9863> A_IWL<9862> A_IWL<9861> A_IWL<9860> A_IWL<9859> A_IWL<9858> A_IWL<9857> A_IWL<9856> A_IWL<9855> A_IWL<9854> A_IWL<9853> A_IWL<9852> A_IWL<9851> A_IWL<9850> A_IWL<9849> A_IWL<9848> A_IWL<9847> A_IWL<9846> A_IWL<9845> A_IWL<9844> A_IWL<9843> A_IWL<9842> A_IWL<9841> A_IWL<9840> A_IWL<9839> A_IWL<9838> A_IWL<9837> A_IWL<9836> A_IWL<9835> A_IWL<9834> A_IWL<9833> A_IWL<9832> A_IWL<9831> A_IWL<9830> A_IWL<9829> A_IWL<9828> A_IWL<9827> A_IWL<9826> A_IWL<9825> A_IWL<9824> A_IWL<9823> A_IWL<9822> A_IWL<9821> A_IWL<9820> A_IWL<9819> A_IWL<9818> A_IWL<9817> A_IWL<9816> A_IWL<9815> A_IWL<9814> A_IWL<9813> A_IWL<9812> A_IWL<9811> A_IWL<9810> A_IWL<9809> A_IWL<9808> A_IWL<9807> A_IWL<9806> A_IWL<9805> A_IWL<9804> A_IWL<9803> A_IWL<9802> A_IWL<9801> A_IWL<9800> A_IWL<9799> A_IWL<9798> A_IWL<9797> A_IWL<9796> A_IWL<9795> A_IWL<9794> A_IWL<9793> A_IWL<9792> A_IWL<9791> A_IWL<9790> A_IWL<9789> A_IWL<9788> A_IWL<9787> A_IWL<9786> A_IWL<9785> A_IWL<9784> A_IWL<9783> A_IWL<9782> A_IWL<9781> A_IWL<9780> A_IWL<9779> A_IWL<9778> A_IWL<9777> A_IWL<9776> A_IWL<9775> A_IWL<9774> A_IWL<9773> A_IWL<9772> A_IWL<9771> A_IWL<9770> A_IWL<9769> A_IWL<9768> A_IWL<9767> A_IWL<9766> A_IWL<9765> A_IWL<9764> A_IWL<9763> A_IWL<9762> A_IWL<9761> A_IWL<9760> A_IWL<9759> A_IWL<9758> A_IWL<9757> A_IWL<9756> A_IWL<9755> A_IWL<9754> A_IWL<9753> A_IWL<9752> A_IWL<9751> A_IWL<9750> A_IWL<9749> A_IWL<9748> A_IWL<9747> A_IWL<9746> A_IWL<9745> A_IWL<9744> A_IWL<9743> A_IWL<9742> A_IWL<9741> A_IWL<9740> A_IWL<9739> A_IWL<9738> A_IWL<9737> A_IWL<9736> A_IWL<9735> A_IWL<9734> A_IWL<9733> A_IWL<9732> A_IWL<9731> A_IWL<9730> A_IWL<9729> A_IWL<9728> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_COLUMN_pcell_0 +XCOL<18> A_BLC<37> A_BLC<36> A_BLC_TOP<37> A_BLC_TOP<36> A_BLT<37> A_BLT<36> A_BLT_TOP<37> A_BLT_TOP<36> A_IWL<9215> A_IWL<9214> A_IWL<9213> A_IWL<9212> A_IWL<9211> A_IWL<9210> A_IWL<9209> A_IWL<9208> A_IWL<9207> A_IWL<9206> A_IWL<9205> A_IWL<9204> A_IWL<9203> A_IWL<9202> A_IWL<9201> A_IWL<9200> A_IWL<9199> A_IWL<9198> A_IWL<9197> A_IWL<9196> A_IWL<9195> A_IWL<9194> A_IWL<9193> A_IWL<9192> A_IWL<9191> A_IWL<9190> A_IWL<9189> A_IWL<9188> A_IWL<9187> A_IWL<9186> A_IWL<9185> A_IWL<9184> A_IWL<9183> A_IWL<9182> A_IWL<9181> A_IWL<9180> A_IWL<9179> A_IWL<9178> A_IWL<9177> A_IWL<9176> A_IWL<9175> A_IWL<9174> A_IWL<9173> A_IWL<9172> A_IWL<9171> A_IWL<9170> A_IWL<9169> A_IWL<9168> A_IWL<9167> A_IWL<9166> A_IWL<9165> A_IWL<9164> A_IWL<9163> A_IWL<9162> A_IWL<9161> A_IWL<9160> A_IWL<9159> A_IWL<9158> A_IWL<9157> A_IWL<9156> A_IWL<9155> A_IWL<9154> A_IWL<9153> A_IWL<9152> A_IWL<9151> A_IWL<9150> A_IWL<9149> A_IWL<9148> A_IWL<9147> A_IWL<9146> A_IWL<9145> A_IWL<9144> A_IWL<9143> A_IWL<9142> A_IWL<9141> A_IWL<9140> A_IWL<9139> A_IWL<9138> A_IWL<9137> A_IWL<9136> A_IWL<9135> A_IWL<9134> A_IWL<9133> A_IWL<9132> A_IWL<9131> A_IWL<9130> A_IWL<9129> A_IWL<9128> A_IWL<9127> A_IWL<9126> A_IWL<9125> A_IWL<9124> A_IWL<9123> A_IWL<9122> A_IWL<9121> A_IWL<9120> A_IWL<9119> A_IWL<9118> A_IWL<9117> A_IWL<9116> A_IWL<9115> A_IWL<9114> A_IWL<9113> A_IWL<9112> A_IWL<9111> A_IWL<9110> A_IWL<9109> A_IWL<9108> A_IWL<9107> A_IWL<9106> A_IWL<9105> A_IWL<9104> A_IWL<9103> A_IWL<9102> A_IWL<9101> A_IWL<9100> A_IWL<9099> A_IWL<9098> A_IWL<9097> A_IWL<9096> A_IWL<9095> A_IWL<9094> A_IWL<9093> A_IWL<9092> A_IWL<9091> A_IWL<9090> A_IWL<9089> A_IWL<9088> A_IWL<9087> A_IWL<9086> A_IWL<9085> A_IWL<9084> A_IWL<9083> A_IWL<9082> A_IWL<9081> A_IWL<9080> A_IWL<9079> A_IWL<9078> A_IWL<9077> A_IWL<9076> A_IWL<9075> A_IWL<9074> A_IWL<9073> A_IWL<9072> A_IWL<9071> A_IWL<9070> A_IWL<9069> A_IWL<9068> A_IWL<9067> A_IWL<9066> A_IWL<9065> A_IWL<9064> A_IWL<9063> A_IWL<9062> A_IWL<9061> A_IWL<9060> A_IWL<9059> A_IWL<9058> A_IWL<9057> A_IWL<9056> A_IWL<9055> A_IWL<9054> A_IWL<9053> A_IWL<9052> A_IWL<9051> A_IWL<9050> A_IWL<9049> A_IWL<9048> A_IWL<9047> A_IWL<9046> A_IWL<9045> A_IWL<9044> A_IWL<9043> A_IWL<9042> A_IWL<9041> A_IWL<9040> A_IWL<9039> A_IWL<9038> A_IWL<9037> A_IWL<9036> A_IWL<9035> A_IWL<9034> A_IWL<9033> A_IWL<9032> A_IWL<9031> A_IWL<9030> A_IWL<9029> A_IWL<9028> A_IWL<9027> A_IWL<9026> A_IWL<9025> A_IWL<9024> A_IWL<9023> A_IWL<9022> A_IWL<9021> A_IWL<9020> A_IWL<9019> A_IWL<9018> A_IWL<9017> A_IWL<9016> A_IWL<9015> A_IWL<9014> A_IWL<9013> A_IWL<9012> A_IWL<9011> A_IWL<9010> A_IWL<9009> A_IWL<9008> A_IWL<9007> A_IWL<9006> A_IWL<9005> A_IWL<9004> A_IWL<9003> A_IWL<9002> A_IWL<9001> A_IWL<9000> A_IWL<8999> A_IWL<8998> A_IWL<8997> A_IWL<8996> A_IWL<8995> A_IWL<8994> A_IWL<8993> A_IWL<8992> A_IWL<8991> A_IWL<8990> A_IWL<8989> A_IWL<8988> A_IWL<8987> A_IWL<8986> A_IWL<8985> A_IWL<8984> A_IWL<8983> A_IWL<8982> A_IWL<8981> A_IWL<8980> A_IWL<8979> A_IWL<8978> A_IWL<8977> A_IWL<8976> A_IWL<8975> A_IWL<8974> A_IWL<8973> A_IWL<8972> A_IWL<8971> A_IWL<8970> A_IWL<8969> A_IWL<8968> A_IWL<8967> A_IWL<8966> A_IWL<8965> A_IWL<8964> A_IWL<8963> A_IWL<8962> A_IWL<8961> A_IWL<8960> A_IWL<8959> A_IWL<8958> A_IWL<8957> A_IWL<8956> A_IWL<8955> A_IWL<8954> A_IWL<8953> A_IWL<8952> A_IWL<8951> A_IWL<8950> A_IWL<8949> A_IWL<8948> A_IWL<8947> A_IWL<8946> A_IWL<8945> A_IWL<8944> A_IWL<8943> A_IWL<8942> A_IWL<8941> A_IWL<8940> A_IWL<8939> A_IWL<8938> A_IWL<8937> A_IWL<8936> A_IWL<8935> A_IWL<8934> A_IWL<8933> A_IWL<8932> A_IWL<8931> A_IWL<8930> A_IWL<8929> A_IWL<8928> A_IWL<8927> A_IWL<8926> A_IWL<8925> A_IWL<8924> A_IWL<8923> A_IWL<8922> A_IWL<8921> A_IWL<8920> A_IWL<8919> A_IWL<8918> A_IWL<8917> A_IWL<8916> A_IWL<8915> A_IWL<8914> A_IWL<8913> A_IWL<8912> A_IWL<8911> A_IWL<8910> A_IWL<8909> A_IWL<8908> A_IWL<8907> A_IWL<8906> A_IWL<8905> A_IWL<8904> A_IWL<8903> A_IWL<8902> A_IWL<8901> A_IWL<8900> A_IWL<8899> A_IWL<8898> A_IWL<8897> A_IWL<8896> A_IWL<8895> A_IWL<8894> A_IWL<8893> A_IWL<8892> A_IWL<8891> A_IWL<8890> A_IWL<8889> A_IWL<8888> A_IWL<8887> A_IWL<8886> A_IWL<8885> A_IWL<8884> A_IWL<8883> A_IWL<8882> A_IWL<8881> A_IWL<8880> A_IWL<8879> A_IWL<8878> A_IWL<8877> A_IWL<8876> A_IWL<8875> A_IWL<8874> A_IWL<8873> A_IWL<8872> A_IWL<8871> A_IWL<8870> A_IWL<8869> A_IWL<8868> A_IWL<8867> A_IWL<8866> A_IWL<8865> A_IWL<8864> A_IWL<8863> A_IWL<8862> A_IWL<8861> A_IWL<8860> A_IWL<8859> A_IWL<8858> A_IWL<8857> A_IWL<8856> A_IWL<8855> A_IWL<8854> A_IWL<8853> A_IWL<8852> A_IWL<8851> A_IWL<8850> A_IWL<8849> A_IWL<8848> A_IWL<8847> A_IWL<8846> A_IWL<8845> A_IWL<8844> A_IWL<8843> A_IWL<8842> A_IWL<8841> A_IWL<8840> A_IWL<8839> A_IWL<8838> A_IWL<8837> A_IWL<8836> A_IWL<8835> A_IWL<8834> A_IWL<8833> A_IWL<8832> A_IWL<8831> A_IWL<8830> A_IWL<8829> A_IWL<8828> A_IWL<8827> A_IWL<8826> A_IWL<8825> A_IWL<8824> A_IWL<8823> A_IWL<8822> A_IWL<8821> A_IWL<8820> A_IWL<8819> A_IWL<8818> A_IWL<8817> A_IWL<8816> A_IWL<8815> A_IWL<8814> A_IWL<8813> A_IWL<8812> A_IWL<8811> A_IWL<8810> A_IWL<8809> A_IWL<8808> A_IWL<8807> A_IWL<8806> A_IWL<8805> A_IWL<8804> A_IWL<8803> A_IWL<8802> A_IWL<8801> A_IWL<8800> A_IWL<8799> A_IWL<8798> A_IWL<8797> A_IWL<8796> A_IWL<8795> A_IWL<8794> A_IWL<8793> A_IWL<8792> A_IWL<8791> A_IWL<8790> A_IWL<8789> A_IWL<8788> A_IWL<8787> A_IWL<8786> A_IWL<8785> A_IWL<8784> A_IWL<8783> A_IWL<8782> A_IWL<8781> A_IWL<8780> A_IWL<8779> A_IWL<8778> A_IWL<8777> A_IWL<8776> A_IWL<8775> A_IWL<8774> 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A_IWL<9714> A_IWL<9713> A_IWL<9712> A_IWL<9711> A_IWL<9710> A_IWL<9709> A_IWL<9708> A_IWL<9707> A_IWL<9706> A_IWL<9705> A_IWL<9704> A_IWL<9703> A_IWL<9702> A_IWL<9701> A_IWL<9700> A_IWL<9699> A_IWL<9698> A_IWL<9697> A_IWL<9696> A_IWL<9695> A_IWL<9694> A_IWL<9693> A_IWL<9692> A_IWL<9691> A_IWL<9690> A_IWL<9689> A_IWL<9688> A_IWL<9687> A_IWL<9686> A_IWL<9685> A_IWL<9684> A_IWL<9683> A_IWL<9682> A_IWL<9681> A_IWL<9680> A_IWL<9679> A_IWL<9678> A_IWL<9677> A_IWL<9676> A_IWL<9675> A_IWL<9674> A_IWL<9673> A_IWL<9672> A_IWL<9671> A_IWL<9670> A_IWL<9669> A_IWL<9668> A_IWL<9667> A_IWL<9666> A_IWL<9665> A_IWL<9664> A_IWL<9663> A_IWL<9662> A_IWL<9661> A_IWL<9660> A_IWL<9659> A_IWL<9658> A_IWL<9657> A_IWL<9656> A_IWL<9655> A_IWL<9654> A_IWL<9653> A_IWL<9652> A_IWL<9651> A_IWL<9650> A_IWL<9649> A_IWL<9648> A_IWL<9647> A_IWL<9646> A_IWL<9645> A_IWL<9644> A_IWL<9643> A_IWL<9642> A_IWL<9641> A_IWL<9640> A_IWL<9639> A_IWL<9638> A_IWL<9637> A_IWL<9636> A_IWL<9635> A_IWL<9634> A_IWL<9633> A_IWL<9632> A_IWL<9631> A_IWL<9630> A_IWL<9629> A_IWL<9628> A_IWL<9627> A_IWL<9626> A_IWL<9625> A_IWL<9624> A_IWL<9623> A_IWL<9622> A_IWL<9621> A_IWL<9620> A_IWL<9619> A_IWL<9618> A_IWL<9617> A_IWL<9616> A_IWL<9615> A_IWL<9614> A_IWL<9613> A_IWL<9612> A_IWL<9611> A_IWL<9610> A_IWL<9609> A_IWL<9608> A_IWL<9607> A_IWL<9606> A_IWL<9605> A_IWL<9604> A_IWL<9603> A_IWL<9602> A_IWL<9601> A_IWL<9600> A_IWL<9599> A_IWL<9598> A_IWL<9597> A_IWL<9596> A_IWL<9595> A_IWL<9594> A_IWL<9593> A_IWL<9592> A_IWL<9591> A_IWL<9590> A_IWL<9589> A_IWL<9588> A_IWL<9587> A_IWL<9586> A_IWL<9585> A_IWL<9584> A_IWL<9583> A_IWL<9582> A_IWL<9581> A_IWL<9580> A_IWL<9579> A_IWL<9578> A_IWL<9577> A_IWL<9576> A_IWL<9575> A_IWL<9574> A_IWL<9573> A_IWL<9572> A_IWL<9571> A_IWL<9570> A_IWL<9569> A_IWL<9568> A_IWL<9567> A_IWL<9566> A_IWL<9565> A_IWL<9564> A_IWL<9563> A_IWL<9562> A_IWL<9561> A_IWL<9560> A_IWL<9559> A_IWL<9558> A_IWL<9557> A_IWL<9556> A_IWL<9555> A_IWL<9554> A_IWL<9553> A_IWL<9552> A_IWL<9551> A_IWL<9550> A_IWL<9549> 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A_IWL<8634> A_IWL<8633> A_IWL<8632> A_IWL<8631> A_IWL<8630> A_IWL<8629> A_IWL<8628> A_IWL<8627> A_IWL<8626> A_IWL<8625> A_IWL<8624> A_IWL<8623> A_IWL<8622> A_IWL<8621> A_IWL<8620> A_IWL<8619> A_IWL<8618> A_IWL<8617> A_IWL<8616> A_IWL<8615> A_IWL<8614> A_IWL<8613> A_IWL<8612> A_IWL<8611> A_IWL<8610> A_IWL<8609> A_IWL<8608> A_IWL<8607> A_IWL<8606> A_IWL<8605> A_IWL<8604> A_IWL<8603> A_IWL<8602> A_IWL<8601> A_IWL<8600> A_IWL<8599> A_IWL<8598> A_IWL<8597> A_IWL<8596> A_IWL<8595> A_IWL<8594> A_IWL<8593> A_IWL<8592> A_IWL<8591> A_IWL<8590> A_IWL<8589> A_IWL<8588> A_IWL<8587> A_IWL<8586> A_IWL<8585> A_IWL<8584> A_IWL<8583> A_IWL<8582> A_IWL<8581> A_IWL<8580> A_IWL<8579> A_IWL<8578> A_IWL<8577> A_IWL<8576> A_IWL<8575> A_IWL<8574> A_IWL<8573> A_IWL<8572> A_IWL<8571> A_IWL<8570> A_IWL<8569> A_IWL<8568> A_IWL<8567> A_IWL<8566> A_IWL<8565> A_IWL<8564> A_IWL<8563> A_IWL<8562> A_IWL<8561> A_IWL<8560> A_IWL<8559> A_IWL<8558> A_IWL<8557> A_IWL<8556> A_IWL<8555> A_IWL<8554> A_IWL<8553> A_IWL<8552> A_IWL<8551> A_IWL<8550> A_IWL<8549> A_IWL<8548> A_IWL<8547> A_IWL<8546> A_IWL<8545> A_IWL<8544> A_IWL<8543> A_IWL<8542> A_IWL<8541> A_IWL<8540> A_IWL<8539> A_IWL<8538> A_IWL<8537> A_IWL<8536> A_IWL<8535> A_IWL<8534> A_IWL<8533> A_IWL<8532> A_IWL<8531> A_IWL<8530> A_IWL<8529> A_IWL<8528> A_IWL<8527> A_IWL<8526> A_IWL<8525> A_IWL<8524> A_IWL<8523> A_IWL<8522> A_IWL<8521> A_IWL<8520> A_IWL<8519> A_IWL<8518> A_IWL<8517> A_IWL<8516> A_IWL<8515> A_IWL<8514> A_IWL<8513> A_IWL<8512> A_IWL<8511> A_IWL<8510> A_IWL<8509> A_IWL<8508> A_IWL<8507> A_IWL<8506> A_IWL<8505> A_IWL<8504> A_IWL<8503> A_IWL<8502> A_IWL<8501> A_IWL<8500> A_IWL<8499> A_IWL<8498> A_IWL<8497> A_IWL<8496> A_IWL<8495> A_IWL<8494> A_IWL<8493> A_IWL<8492> A_IWL<8491> A_IWL<8490> A_IWL<8489> A_IWL<8488> A_IWL<8487> A_IWL<8486> A_IWL<8485> A_IWL<8484> A_IWL<8483> A_IWL<8482> A_IWL<8481> A_IWL<8480> A_IWL<8479> A_IWL<8478> A_IWL<8477> A_IWL<8476> A_IWL<8475> A_IWL<8474> A_IWL<8473> A_IWL<8472> A_IWL<8471> A_IWL<8470> A_IWL<8469> A_IWL<8468> A_IWL<8467> A_IWL<8466> A_IWL<8465> A_IWL<8464> A_IWL<8463> A_IWL<8462> A_IWL<8461> A_IWL<8460> A_IWL<8459> A_IWL<8458> A_IWL<8457> A_IWL<8456> A_IWL<8455> A_IWL<8454> A_IWL<8453> A_IWL<8452> A_IWL<8451> A_IWL<8450> A_IWL<8449> A_IWL<8448> A_IWL<8447> A_IWL<8446> A_IWL<8445> A_IWL<8444> A_IWL<8443> A_IWL<8442> A_IWL<8441> A_IWL<8440> A_IWL<8439> A_IWL<8438> A_IWL<8437> A_IWL<8436> A_IWL<8435> A_IWL<8434> A_IWL<8433> A_IWL<8432> A_IWL<8431> A_IWL<8430> A_IWL<8429> A_IWL<8428> A_IWL<8427> A_IWL<8426> A_IWL<8425> A_IWL<8424> A_IWL<8423> A_IWL<8422> A_IWL<8421> A_IWL<8420> A_IWL<8419> A_IWL<8418> A_IWL<8417> A_IWL<8416> A_IWL<8415> A_IWL<8414> A_IWL<8413> A_IWL<8412> A_IWL<8411> A_IWL<8410> A_IWL<8409> A_IWL<8408> A_IWL<8407> A_IWL<8406> A_IWL<8405> A_IWL<8404> A_IWL<8403> A_IWL<8402> A_IWL<8401> A_IWL<8400> A_IWL<8399> A_IWL<8398> A_IWL<8397> A_IWL<8396> A_IWL<8395> A_IWL<8394> A_IWL<8393> A_IWL<8392> A_IWL<8391> A_IWL<8390> A_IWL<8389> A_IWL<8388> A_IWL<8387> A_IWL<8386> A_IWL<8385> A_IWL<8384> A_IWL<8383> A_IWL<8382> A_IWL<8381> A_IWL<8380> A_IWL<8379> A_IWL<8378> A_IWL<8377> A_IWL<8376> A_IWL<8375> A_IWL<8374> A_IWL<8373> A_IWL<8372> A_IWL<8371> A_IWL<8370> A_IWL<8369> A_IWL<8368> A_IWL<8367> A_IWL<8366> A_IWL<8365> A_IWL<8364> A_IWL<8363> A_IWL<8362> A_IWL<8361> A_IWL<8360> A_IWL<8359> A_IWL<8358> A_IWL<8357> A_IWL<8356> A_IWL<8355> A_IWL<8354> A_IWL<8353> A_IWL<8352> A_IWL<8351> A_IWL<8350> A_IWL<8349> A_IWL<8348> A_IWL<8347> A_IWL<8346> A_IWL<8345> A_IWL<8344> A_IWL<8343> A_IWL<8342> A_IWL<8341> A_IWL<8340> A_IWL<8339> A_IWL<8338> A_IWL<8337> A_IWL<8336> A_IWL<8335> A_IWL<8334> A_IWL<8333> A_IWL<8332> A_IWL<8331> A_IWL<8330> A_IWL<8329> A_IWL<8328> A_IWL<8327> A_IWL<8326> A_IWL<8325> A_IWL<8324> A_IWL<8323> A_IWL<8322> A_IWL<8321> A_IWL<8320> A_IWL<8319> A_IWL<8318> A_IWL<8317> A_IWL<8316> A_IWL<8315> A_IWL<8314> A_IWL<8313> A_IWL<8312> A_IWL<8311> A_IWL<8310> A_IWL<8309> A_IWL<8308> A_IWL<8307> A_IWL<8306> A_IWL<8305> A_IWL<8304> A_IWL<8303> A_IWL<8302> A_IWL<8301> A_IWL<8300> A_IWL<8299> A_IWL<8298> A_IWL<8297> A_IWL<8296> A_IWL<8295> A_IWL<8294> A_IWL<8293> A_IWL<8292> A_IWL<8291> A_IWL<8290> A_IWL<8289> A_IWL<8288> A_IWL<8287> A_IWL<8286> A_IWL<8285> A_IWL<8284> A_IWL<8283> A_IWL<8282> A_IWL<8281> A_IWL<8280> A_IWL<8279> A_IWL<8278> A_IWL<8277> A_IWL<8276> A_IWL<8275> A_IWL<8274> A_IWL<8273> A_IWL<8272> A_IWL<8271> A_IWL<8270> A_IWL<8269> A_IWL<8268> A_IWL<8267> A_IWL<8266> A_IWL<8265> A_IWL<8264> A_IWL<8263> A_IWL<8262> A_IWL<8261> A_IWL<8260> A_IWL<8259> A_IWL<8258> A_IWL<8257> A_IWL<8256> A_IWL<8255> A_IWL<8254> A_IWL<8253> A_IWL<8252> A_IWL<8251> A_IWL<8250> A_IWL<8249> A_IWL<8248> A_IWL<8247> A_IWL<8246> A_IWL<8245> A_IWL<8244> A_IWL<8243> A_IWL<8242> A_IWL<8241> A_IWL<8240> A_IWL<8239> A_IWL<8238> A_IWL<8237> A_IWL<8236> A_IWL<8235> A_IWL<8234> A_IWL<8233> A_IWL<8232> A_IWL<8231> A_IWL<8230> A_IWL<8229> A_IWL<8228> A_IWL<8227> A_IWL<8226> A_IWL<8225> A_IWL<8224> A_IWL<8223> A_IWL<8222> A_IWL<8221> A_IWL<8220> A_IWL<8219> A_IWL<8218> A_IWL<8217> A_IWL<8216> A_IWL<8215> A_IWL<8214> A_IWL<8213> A_IWL<8212> A_IWL<8211> A_IWL<8210> A_IWL<8209> A_IWL<8208> A_IWL<8207> A_IWL<8206> A_IWL<8205> A_IWL<8204> A_IWL<8203> A_IWL<8202> A_IWL<8201> A_IWL<8200> A_IWL<8199> A_IWL<8198> A_IWL<8197> A_IWL<8196> A_IWL<8195> A_IWL<8194> A_IWL<8193> A_IWL<8192> A_IWL<9215> A_IWL<9214> A_IWL<9213> A_IWL<9212> A_IWL<9211> A_IWL<9210> A_IWL<9209> A_IWL<9208> A_IWL<9207> A_IWL<9206> A_IWL<9205> A_IWL<9204> A_IWL<9203> A_IWL<9202> A_IWL<9201> A_IWL<9200> A_IWL<9199> A_IWL<9198> A_IWL<9197> A_IWL<9196> A_IWL<9195> A_IWL<9194> A_IWL<9193> A_IWL<9192> A_IWL<9191> A_IWL<9190> A_IWL<9189> A_IWL<9188> A_IWL<9187> A_IWL<9186> A_IWL<9185> A_IWL<9184> A_IWL<9183> A_IWL<9182> A_IWL<9181> A_IWL<9180> A_IWL<9179> A_IWL<9178> A_IWL<9177> A_IWL<9176> A_IWL<9175> A_IWL<9174> A_IWL<9173> A_IWL<9172> A_IWL<9171> A_IWL<9170> A_IWL<9169> A_IWL<9168> A_IWL<9167> A_IWL<9166> A_IWL<9165> A_IWL<9164> A_IWL<9163> A_IWL<9162> A_IWL<9161> A_IWL<9160> A_IWL<9159> A_IWL<9158> A_IWL<9157> A_IWL<9156> A_IWL<9155> A_IWL<9154> A_IWL<9153> A_IWL<9152> A_IWL<9151> A_IWL<9150> A_IWL<9149> A_IWL<9148> A_IWL<9147> A_IWL<9146> A_IWL<9145> A_IWL<9144> A_IWL<9143> A_IWL<9142> A_IWL<9141> A_IWL<9140> A_IWL<9139> A_IWL<9138> A_IWL<9137> A_IWL<9136> A_IWL<9135> A_IWL<9134> A_IWL<9133> A_IWL<9132> A_IWL<9131> A_IWL<9130> A_IWL<9129> A_IWL<9128> A_IWL<9127> A_IWL<9126> A_IWL<9125> A_IWL<9124> A_IWL<9123> A_IWL<9122> A_IWL<9121> A_IWL<9120> A_IWL<9119> A_IWL<9118> A_IWL<9117> A_IWL<9116> A_IWL<9115> A_IWL<9114> A_IWL<9113> A_IWL<9112> A_IWL<9111> A_IWL<9110> A_IWL<9109> A_IWL<9108> A_IWL<9107> A_IWL<9106> A_IWL<9105> A_IWL<9104> A_IWL<9103> A_IWL<9102> A_IWL<9101> A_IWL<9100> A_IWL<9099> A_IWL<9098> A_IWL<9097> A_IWL<9096> A_IWL<9095> A_IWL<9094> A_IWL<9093> A_IWL<9092> A_IWL<9091> A_IWL<9090> A_IWL<9089> A_IWL<9088> A_IWL<9087> A_IWL<9086> A_IWL<9085> A_IWL<9084> A_IWL<9083> A_IWL<9082> A_IWL<9081> A_IWL<9080> A_IWL<9079> A_IWL<9078> A_IWL<9077> A_IWL<9076> A_IWL<9075> A_IWL<9074> A_IWL<9073> A_IWL<9072> A_IWL<9071> A_IWL<9070> A_IWL<9069> A_IWL<9068> A_IWL<9067> A_IWL<9066> A_IWL<9065> A_IWL<9064> A_IWL<9063> A_IWL<9062> A_IWL<9061> A_IWL<9060> A_IWL<9059> A_IWL<9058> A_IWL<9057> A_IWL<9056> A_IWL<9055> A_IWL<9054> A_IWL<9053> A_IWL<9052> A_IWL<9051> A_IWL<9050> A_IWL<9049> A_IWL<9048> A_IWL<9047> A_IWL<9046> A_IWL<9045> A_IWL<9044> A_IWL<9043> A_IWL<9042> A_IWL<9041> A_IWL<9040> A_IWL<9039> A_IWL<9038> A_IWL<9037> A_IWL<9036> A_IWL<9035> A_IWL<9034> A_IWL<9033> A_IWL<9032> A_IWL<9031> A_IWL<9030> A_IWL<9029> A_IWL<9028> A_IWL<9027> A_IWL<9026> A_IWL<9025> A_IWL<9024> A_IWL<9023> A_IWL<9022> A_IWL<9021> A_IWL<9020> A_IWL<9019> A_IWL<9018> A_IWL<9017> A_IWL<9016> A_IWL<9015> A_IWL<9014> A_IWL<9013> A_IWL<9012> A_IWL<9011> A_IWL<9010> A_IWL<9009> A_IWL<9008> A_IWL<9007> A_IWL<9006> A_IWL<9005> A_IWL<9004> A_IWL<9003> A_IWL<9002> A_IWL<9001> A_IWL<9000> A_IWL<8999> A_IWL<8998> A_IWL<8997> A_IWL<8996> A_IWL<8995> A_IWL<8994> A_IWL<8993> A_IWL<8992> A_IWL<8991> A_IWL<8990> A_IWL<8989> A_IWL<8988> A_IWL<8987> A_IWL<8986> A_IWL<8985> A_IWL<8984> A_IWL<8983> A_IWL<8982> A_IWL<8981> A_IWL<8980> A_IWL<8979> A_IWL<8978> A_IWL<8977> A_IWL<8976> A_IWL<8975> A_IWL<8974> A_IWL<8973> A_IWL<8972> A_IWL<8971> A_IWL<8970> A_IWL<8969> A_IWL<8968> A_IWL<8967> A_IWL<8966> A_IWL<8965> A_IWL<8964> A_IWL<8963> A_IWL<8962> A_IWL<8961> A_IWL<8960> A_IWL<8959> A_IWL<8958> A_IWL<8957> A_IWL<8956> A_IWL<8955> A_IWL<8954> A_IWL<8953> A_IWL<8952> A_IWL<8951> A_IWL<8950> A_IWL<8949> A_IWL<8948> A_IWL<8947> A_IWL<8946> A_IWL<8945> A_IWL<8944> A_IWL<8943> A_IWL<8942> A_IWL<8941> A_IWL<8940> A_IWL<8939> A_IWL<8938> A_IWL<8937> A_IWL<8936> A_IWL<8935> A_IWL<8934> A_IWL<8933> A_IWL<8932> A_IWL<8931> A_IWL<8930> A_IWL<8929> A_IWL<8928> A_IWL<8927> A_IWL<8926> A_IWL<8925> A_IWL<8924> A_IWL<8923> A_IWL<8922> A_IWL<8921> A_IWL<8920> A_IWL<8919> A_IWL<8918> A_IWL<8917> A_IWL<8916> A_IWL<8915> A_IWL<8914> A_IWL<8913> A_IWL<8912> A_IWL<8911> A_IWL<8910> A_IWL<8909> A_IWL<8908> A_IWL<8907> A_IWL<8906> A_IWL<8905> A_IWL<8904> A_IWL<8903> A_IWL<8902> A_IWL<8901> A_IWL<8900> A_IWL<8899> A_IWL<8898> A_IWL<8897> A_IWL<8896> A_IWL<8895> A_IWL<8894> A_IWL<8893> A_IWL<8892> A_IWL<8891> A_IWL<8890> A_IWL<8889> A_IWL<8888> A_IWL<8887> A_IWL<8886> A_IWL<8885> A_IWL<8884> A_IWL<8883> A_IWL<8882> A_IWL<8881> A_IWL<8880> A_IWL<8879> A_IWL<8878> A_IWL<8877> A_IWL<8876> A_IWL<8875> A_IWL<8874> A_IWL<8873> A_IWL<8872> A_IWL<8871> A_IWL<8870> A_IWL<8869> A_IWL<8868> A_IWL<8867> A_IWL<8866> A_IWL<8865> A_IWL<8864> A_IWL<8863> A_IWL<8862> A_IWL<8861> A_IWL<8860> A_IWL<8859> A_IWL<8858> A_IWL<8857> A_IWL<8856> A_IWL<8855> A_IWL<8854> A_IWL<8853> A_IWL<8852> A_IWL<8851> A_IWL<8850> A_IWL<8849> A_IWL<8848> A_IWL<8847> A_IWL<8846> A_IWL<8845> A_IWL<8844> A_IWL<8843> A_IWL<8842> A_IWL<8841> A_IWL<8840> A_IWL<8839> A_IWL<8838> A_IWL<8837> A_IWL<8836> A_IWL<8835> A_IWL<8834> A_IWL<8833> A_IWL<8832> A_IWL<8831> A_IWL<8830> A_IWL<8829> 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A_IWL<8745> A_IWL<8744> A_IWL<8743> A_IWL<8742> A_IWL<8741> A_IWL<8740> A_IWL<8739> A_IWL<8738> A_IWL<8737> A_IWL<8736> A_IWL<8735> A_IWL<8734> A_IWL<8733> A_IWL<8732> A_IWL<8731> A_IWL<8730> A_IWL<8729> A_IWL<8728> A_IWL<8727> A_IWL<8726> A_IWL<8725> A_IWL<8724> A_IWL<8723> A_IWL<8722> A_IWL<8721> A_IWL<8720> A_IWL<8719> A_IWL<8718> A_IWL<8717> A_IWL<8716> A_IWL<8715> A_IWL<8714> A_IWL<8713> A_IWL<8712> A_IWL<8711> A_IWL<8710> A_IWL<8709> A_IWL<8708> A_IWL<8707> A_IWL<8706> A_IWL<8705> A_IWL<8704> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_COLUMN_pcell_0 +XCOL<16> A_BLC<33> A_BLC<32> A_BLC_TOP<33> A_BLC_TOP<32> A_BLT<33> A_BLT<32> A_BLT_TOP<33> A_BLT_TOP<32> A_IWL<8191> A_IWL<8190> A_IWL<8189> A_IWL<8188> A_IWL<8187> A_IWL<8186> A_IWL<8185> A_IWL<8184> A_IWL<8183> A_IWL<8182> A_IWL<8181> A_IWL<8180> A_IWL<8179> A_IWL<8178> A_IWL<8177> A_IWL<8176> A_IWL<8175> A_IWL<8174> A_IWL<8173> A_IWL<8172> A_IWL<8171> A_IWL<8170> A_IWL<8169> A_IWL<8168> A_IWL<8167> A_IWL<8166> A_IWL<8165> A_IWL<8164> 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A_IWL<6723> A_IWL<6722> A_IWL<6721> A_IWL<6720> A_IWL<6719> A_IWL<6718> A_IWL<6717> A_IWL<6716> A_IWL<6715> A_IWL<6714> A_IWL<6713> A_IWL<6712> A_IWL<6711> A_IWL<6710> A_IWL<6709> A_IWL<6708> A_IWL<6707> A_IWL<6706> A_IWL<6705> A_IWL<6704> A_IWL<6703> A_IWL<6702> A_IWL<6701> A_IWL<6700> A_IWL<6699> A_IWL<6698> A_IWL<6697> A_IWL<6696> A_IWL<6695> A_IWL<6694> A_IWL<6693> A_IWL<6692> A_IWL<6691> A_IWL<6690> A_IWL<6689> A_IWL<6688> A_IWL<6687> A_IWL<6686> A_IWL<6685> A_IWL<6684> A_IWL<6683> A_IWL<6682> A_IWL<6681> A_IWL<6680> A_IWL<6679> A_IWL<6678> A_IWL<6677> A_IWL<6676> A_IWL<6675> A_IWL<6674> A_IWL<6673> A_IWL<6672> A_IWL<6671> A_IWL<6670> A_IWL<6669> A_IWL<6668> A_IWL<6667> A_IWL<6666> A_IWL<6665> A_IWL<6664> A_IWL<6663> A_IWL<6662> A_IWL<6661> A_IWL<6660> A_IWL<6659> A_IWL<6658> A_IWL<6657> A_IWL<6656> A_IWL<7679> A_IWL<7678> A_IWL<7677> A_IWL<7676> A_IWL<7675> A_IWL<7674> A_IWL<7673> A_IWL<7672> A_IWL<7671> A_IWL<7670> A_IWL<7669> A_IWL<7668> A_IWL<7667> A_IWL<7666> A_IWL<7665> A_IWL<7664> A_IWL<7663> A_IWL<7662> A_IWL<7661> A_IWL<7660> A_IWL<7659> A_IWL<7658> A_IWL<7657> A_IWL<7656> A_IWL<7655> A_IWL<7654> A_IWL<7653> A_IWL<7652> A_IWL<7651> A_IWL<7650> A_IWL<7649> A_IWL<7648> A_IWL<7647> A_IWL<7646> A_IWL<7645> A_IWL<7644> A_IWL<7643> A_IWL<7642> A_IWL<7641> A_IWL<7640> A_IWL<7639> A_IWL<7638> A_IWL<7637> A_IWL<7636> A_IWL<7635> A_IWL<7634> A_IWL<7633> A_IWL<7632> A_IWL<7631> A_IWL<7630> A_IWL<7629> A_IWL<7628> A_IWL<7627> A_IWL<7626> A_IWL<7625> A_IWL<7624> A_IWL<7623> A_IWL<7622> A_IWL<7621> A_IWL<7620> A_IWL<7619> A_IWL<7618> A_IWL<7617> A_IWL<7616> A_IWL<7615> A_IWL<7614> A_IWL<7613> A_IWL<7612> A_IWL<7611> A_IWL<7610> A_IWL<7609> A_IWL<7608> A_IWL<7607> A_IWL<7606> A_IWL<7605> A_IWL<7604> A_IWL<7603> A_IWL<7602> A_IWL<7601> A_IWL<7600> A_IWL<7599> A_IWL<7598> A_IWL<7597> A_IWL<7596> A_IWL<7595> A_IWL<7594> A_IWL<7593> A_IWL<7592> A_IWL<7591> A_IWL<7590> A_IWL<7589> A_IWL<7588> A_IWL<7587> A_IWL<7586> A_IWL<7585> A_IWL<7584> A_IWL<7583> A_IWL<7582> A_IWL<7581> A_IWL<7580> A_IWL<7579> A_IWL<7578> A_IWL<7577> A_IWL<7576> A_IWL<7575> A_IWL<7574> A_IWL<7573> A_IWL<7572> A_IWL<7571> A_IWL<7570> A_IWL<7569> A_IWL<7568> A_IWL<7567> A_IWL<7566> A_IWL<7565> A_IWL<7564> A_IWL<7563> A_IWL<7562> A_IWL<7561> A_IWL<7560> A_IWL<7559> A_IWL<7558> A_IWL<7557> A_IWL<7556> A_IWL<7555> A_IWL<7554> A_IWL<7553> A_IWL<7552> A_IWL<7551> A_IWL<7550> A_IWL<7549> A_IWL<7548> A_IWL<7547> A_IWL<7546> A_IWL<7545> A_IWL<7544> A_IWL<7543> A_IWL<7542> A_IWL<7541> A_IWL<7540> A_IWL<7539> A_IWL<7538> A_IWL<7537> A_IWL<7536> A_IWL<7535> A_IWL<7534> A_IWL<7533> A_IWL<7532> A_IWL<7531> A_IWL<7530> A_IWL<7529> A_IWL<7528> A_IWL<7527> A_IWL<7526> A_IWL<7525> A_IWL<7524> A_IWL<7523> A_IWL<7522> A_IWL<7521> A_IWL<7520> A_IWL<7519> A_IWL<7518> A_IWL<7517> A_IWL<7516> A_IWL<7515> A_IWL<7514> A_IWL<7513> A_IWL<7512> A_IWL<7511> A_IWL<7510> A_IWL<7509> A_IWL<7508> A_IWL<7507> A_IWL<7506> A_IWL<7505> A_IWL<7504> A_IWL<7503> A_IWL<7502> A_IWL<7501> A_IWL<7500> A_IWL<7499> A_IWL<7498> A_IWL<7497> A_IWL<7496> A_IWL<7495> A_IWL<7494> A_IWL<7493> A_IWL<7492> A_IWL<7491> A_IWL<7490> A_IWL<7489> A_IWL<7488> A_IWL<7487> A_IWL<7486> A_IWL<7485> A_IWL<7484> A_IWL<7483> A_IWL<7482> A_IWL<7481> A_IWL<7480> A_IWL<7479> A_IWL<7478> A_IWL<7477> A_IWL<7476> A_IWL<7475> A_IWL<7474> A_IWL<7473> A_IWL<7472> A_IWL<7471> A_IWL<7470> A_IWL<7469> A_IWL<7468> A_IWL<7467> A_IWL<7466> A_IWL<7465> A_IWL<7464> A_IWL<7463> A_IWL<7462> A_IWL<7461> A_IWL<7460> A_IWL<7459> A_IWL<7458> A_IWL<7457> A_IWL<7456> A_IWL<7455> A_IWL<7454> A_IWL<7453> A_IWL<7452> A_IWL<7451> A_IWL<7450> A_IWL<7449> A_IWL<7448> A_IWL<7447> A_IWL<7446> A_IWL<7445> A_IWL<7444> A_IWL<7443> A_IWL<7442> A_IWL<7441> A_IWL<7440> A_IWL<7439> A_IWL<7438> A_IWL<7437> A_IWL<7436> A_IWL<7435> A_IWL<7434> A_IWL<7433> A_IWL<7432> A_IWL<7431> A_IWL<7430> A_IWL<7429> A_IWL<7428> A_IWL<7427> A_IWL<7426> A_IWL<7425> A_IWL<7424> A_IWL<7423> A_IWL<7422> A_IWL<7421> A_IWL<7420> A_IWL<7419> A_IWL<7418> A_IWL<7417> A_IWL<7416> A_IWL<7415> A_IWL<7414> A_IWL<7413> A_IWL<7412> A_IWL<7411> A_IWL<7410> A_IWL<7409> A_IWL<7408> A_IWL<7407> A_IWL<7406> A_IWL<7405> A_IWL<7404> A_IWL<7403> A_IWL<7402> A_IWL<7401> A_IWL<7400> A_IWL<7399> A_IWL<7398> A_IWL<7397> A_IWL<7396> A_IWL<7395> A_IWL<7394> A_IWL<7393> A_IWL<7392> A_IWL<7391> A_IWL<7390> A_IWL<7389> A_IWL<7388> A_IWL<7387> A_IWL<7386> A_IWL<7385> A_IWL<7384> A_IWL<7383> A_IWL<7382> A_IWL<7381> A_IWL<7380> A_IWL<7379> A_IWL<7378> A_IWL<7377> A_IWL<7376> A_IWL<7375> A_IWL<7374> A_IWL<7373> A_IWL<7372> A_IWL<7371> A_IWL<7370> A_IWL<7369> A_IWL<7368> A_IWL<7367> A_IWL<7366> A_IWL<7365> A_IWL<7364> A_IWL<7363> A_IWL<7362> A_IWL<7361> A_IWL<7360> A_IWL<7359> A_IWL<7358> A_IWL<7357> A_IWL<7356> A_IWL<7355> A_IWL<7354> A_IWL<7353> A_IWL<7352> A_IWL<7351> A_IWL<7350> A_IWL<7349> A_IWL<7348> A_IWL<7347> A_IWL<7346> A_IWL<7345> A_IWL<7344> A_IWL<7343> A_IWL<7342> A_IWL<7341> A_IWL<7340> A_IWL<7339> A_IWL<7338> A_IWL<7337> A_IWL<7336> A_IWL<7335> A_IWL<7334> A_IWL<7333> A_IWL<7332> A_IWL<7331> A_IWL<7330> A_IWL<7329> A_IWL<7328> A_IWL<7327> A_IWL<7326> A_IWL<7325> A_IWL<7324> A_IWL<7323> A_IWL<7322> A_IWL<7321> A_IWL<7320> A_IWL<7319> A_IWL<7318> A_IWL<7317> A_IWL<7316> A_IWL<7315> A_IWL<7314> A_IWL<7313> A_IWL<7312> A_IWL<7311> A_IWL<7310> A_IWL<7309> A_IWL<7308> A_IWL<7307> A_IWL<7306> A_IWL<7305> A_IWL<7304> A_IWL<7303> A_IWL<7302> A_IWL<7301> A_IWL<7300> A_IWL<7299> A_IWL<7298> A_IWL<7297> A_IWL<7296> A_IWL<7295> A_IWL<7294> A_IWL<7293> A_IWL<7292> A_IWL<7291> A_IWL<7290> A_IWL<7289> A_IWL<7288> A_IWL<7287> A_IWL<7286> A_IWL<7285> A_IWL<7284> A_IWL<7283> A_IWL<7282> A_IWL<7281> A_IWL<7280> A_IWL<7279> A_IWL<7278> A_IWL<7277> A_IWL<7276> A_IWL<7275> A_IWL<7274> A_IWL<7273> A_IWL<7272> A_IWL<7271> A_IWL<7270> A_IWL<7269> A_IWL<7268> A_IWL<7267> A_IWL<7266> A_IWL<7265> A_IWL<7264> A_IWL<7263> A_IWL<7262> A_IWL<7261> A_IWL<7260> A_IWL<7259> A_IWL<7258> A_IWL<7257> A_IWL<7256> A_IWL<7255> A_IWL<7254> A_IWL<7253> A_IWL<7252> A_IWL<7251> A_IWL<7250> A_IWL<7249> A_IWL<7248> A_IWL<7247> A_IWL<7246> A_IWL<7245> A_IWL<7244> A_IWL<7243> A_IWL<7242> A_IWL<7241> A_IWL<7240> A_IWL<7239> A_IWL<7238> A_IWL<7237> A_IWL<7236> A_IWL<7235> A_IWL<7234> A_IWL<7233> A_IWL<7232> A_IWL<7231> A_IWL<7230> A_IWL<7229> A_IWL<7228> A_IWL<7227> A_IWL<7226> A_IWL<7225> A_IWL<7224> A_IWL<7223> A_IWL<7222> A_IWL<7221> A_IWL<7220> A_IWL<7219> A_IWL<7218> A_IWL<7217> A_IWL<7216> A_IWL<7215> A_IWL<7214> A_IWL<7213> A_IWL<7212> A_IWL<7211> A_IWL<7210> A_IWL<7209> A_IWL<7208> A_IWL<7207> A_IWL<7206> A_IWL<7205> A_IWL<7204> A_IWL<7203> A_IWL<7202> A_IWL<7201> A_IWL<7200> A_IWL<7199> A_IWL<7198> A_IWL<7197> A_IWL<7196> A_IWL<7195> A_IWL<7194> A_IWL<7193> A_IWL<7192> A_IWL<7191> A_IWL<7190> A_IWL<7189> A_IWL<7188> A_IWL<7187> A_IWL<7186> A_IWL<7185> A_IWL<7184> A_IWL<7183> A_IWL<7182> A_IWL<7181> A_IWL<7180> A_IWL<7179> A_IWL<7178> A_IWL<7177> A_IWL<7176> A_IWL<7175> A_IWL<7174> A_IWL<7173> A_IWL<7172> A_IWL<7171> A_IWL<7170> A_IWL<7169> A_IWL<7168> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_COLUMN_pcell_0 +XCOL<13> A_BLC<27> A_BLC<26> A_BLC_TOP<27> A_BLC_TOP<26> A_BLT<27> A_BLT<26> A_BLT_TOP<27> A_BLT_TOP<26> A_IWL<6655> A_IWL<6654> A_IWL<6653> A_IWL<6652> A_IWL<6651> A_IWL<6650> A_IWL<6649> A_IWL<6648> A_IWL<6647> A_IWL<6646> A_IWL<6645> A_IWL<6644> A_IWL<6643> A_IWL<6642> A_IWL<6641> A_IWL<6640> A_IWL<6639> A_IWL<6638> A_IWL<6637> A_IWL<6636> A_IWL<6635> A_IWL<6634> A_IWL<6633> A_IWL<6632> A_IWL<6631> A_IWL<6630> A_IWL<6629> A_IWL<6628> A_IWL<6627> A_IWL<6626> A_IWL<6625> A_IWL<6624> A_IWL<6623> A_IWL<6622> A_IWL<6621> A_IWL<6620> A_IWL<6619> A_IWL<6618> A_IWL<6617> A_IWL<6616> A_IWL<6615> A_IWL<6614> A_IWL<6613> A_IWL<6612> A_IWL<6611> A_IWL<6610> A_IWL<6609> A_IWL<6608> A_IWL<6607> A_IWL<6606> A_IWL<6605> A_IWL<6604> A_IWL<6603> A_IWL<6602> A_IWL<6601> A_IWL<6600> A_IWL<6599> A_IWL<6598> A_IWL<6597> A_IWL<6596> A_IWL<6595> A_IWL<6594> A_IWL<6593> A_IWL<6592> A_IWL<6591> A_IWL<6590> A_IWL<6589> A_IWL<6588> A_IWL<6587> A_IWL<6586> A_IWL<6585> A_IWL<6584> A_IWL<6583> A_IWL<6582> A_IWL<6581> A_IWL<6580> A_IWL<6579> A_IWL<6578> A_IWL<6577> A_IWL<6576> A_IWL<6575> A_IWL<6574> A_IWL<6573> A_IWL<6572> A_IWL<6571> A_IWL<6570> A_IWL<6569> A_IWL<6568> A_IWL<6567> A_IWL<6566> A_IWL<6565> A_IWL<6564> A_IWL<6563> A_IWL<6562> A_IWL<6561> A_IWL<6560> A_IWL<6559> A_IWL<6558> A_IWL<6557> A_IWL<6556> A_IWL<6555> A_IWL<6554> A_IWL<6553> A_IWL<6552> A_IWL<6551> A_IWL<6550> A_IWL<6549> A_IWL<6548> A_IWL<6547> A_IWL<6546> A_IWL<6545> A_IWL<6544> A_IWL<6543> A_IWL<6542> A_IWL<6541> A_IWL<6540> A_IWL<6539> A_IWL<6538> A_IWL<6537> A_IWL<6536> A_IWL<6535> A_IWL<6534> A_IWL<6533> A_IWL<6532> A_IWL<6531> A_IWL<6530> A_IWL<6529> A_IWL<6528> A_IWL<6527> A_IWL<6526> A_IWL<6525> A_IWL<6524> A_IWL<6523> A_IWL<6522> A_IWL<6521> A_IWL<6520> A_IWL<6519> A_IWL<6518> A_IWL<6517> A_IWL<6516> A_IWL<6515> A_IWL<6514> A_IWL<6513> A_IWL<6512> A_IWL<6511> A_IWL<6510> A_IWL<6509> A_IWL<6508> A_IWL<6507> A_IWL<6506> A_IWL<6505> A_IWL<6504> A_IWL<6503> A_IWL<6502> A_IWL<6501> A_IWL<6500> A_IWL<6499> A_IWL<6498> A_IWL<6497> A_IWL<6496> A_IWL<6495> A_IWL<6494> A_IWL<6493> A_IWL<6492> A_IWL<6491> A_IWL<6490> A_IWL<6489> A_IWL<6488> A_IWL<6487> A_IWL<6486> A_IWL<6485> A_IWL<6484> A_IWL<6483> A_IWL<6482> A_IWL<6481> A_IWL<6480> A_IWL<6479> A_IWL<6478> A_IWL<6477> A_IWL<6476> A_IWL<6475> A_IWL<6474> A_IWL<6473> A_IWL<6472> A_IWL<6471> A_IWL<6470> A_IWL<6469> A_IWL<6468> A_IWL<6467> A_IWL<6466> A_IWL<6465> A_IWL<6464> A_IWL<6463> A_IWL<6462> A_IWL<6461> A_IWL<6460> A_IWL<6459> A_IWL<6458> A_IWL<6457> A_IWL<6456> A_IWL<6455> A_IWL<6454> A_IWL<6453> A_IWL<6452> A_IWL<6451> A_IWL<6450> A_IWL<6449> A_IWL<6448> A_IWL<6447> A_IWL<6446> A_IWL<6445> A_IWL<6444> A_IWL<6443> A_IWL<6442> A_IWL<6441> A_IWL<6440> A_IWL<6439> A_IWL<6438> A_IWL<6437> A_IWL<6436> A_IWL<6435> A_IWL<6434> A_IWL<6433> A_IWL<6432> A_IWL<6431> A_IWL<6430> A_IWL<6429> A_IWL<6428> A_IWL<6427> A_IWL<6426> A_IWL<6425> A_IWL<6424> A_IWL<6423> A_IWL<6422> A_IWL<6421> A_IWL<6420> A_IWL<6419> A_IWL<6418> A_IWL<6417> A_IWL<6416> A_IWL<6415> A_IWL<6414> A_IWL<6413> A_IWL<6412> A_IWL<6411> A_IWL<6410> A_IWL<6409> A_IWL<6408> A_IWL<6407> A_IWL<6406> A_IWL<6405> A_IWL<6404> A_IWL<6403> A_IWL<6402> A_IWL<6401> A_IWL<6400> A_IWL<6399> A_IWL<6398> A_IWL<6397> A_IWL<6396> A_IWL<6395> A_IWL<6394> A_IWL<6393> A_IWL<6392> A_IWL<6391> A_IWL<6390> A_IWL<6389> A_IWL<6388> A_IWL<6387> A_IWL<6386> A_IWL<6385> A_IWL<6384> A_IWL<6383> A_IWL<6382> A_IWL<6381> A_IWL<6380> A_IWL<6379> A_IWL<6378> A_IWL<6377> A_IWL<6376> A_IWL<6375> A_IWL<6374> A_IWL<6373> A_IWL<6372> A_IWL<6371> A_IWL<6370> A_IWL<6369> A_IWL<6368> A_IWL<6367> A_IWL<6366> A_IWL<6365> A_IWL<6364> A_IWL<6363> A_IWL<6362> A_IWL<6361> A_IWL<6360> A_IWL<6359> A_IWL<6358> A_IWL<6357> A_IWL<6356> A_IWL<6355> A_IWL<6354> A_IWL<6353> A_IWL<6352> A_IWL<6351> A_IWL<6350> A_IWL<6349> A_IWL<6348> A_IWL<6347> A_IWL<6346> A_IWL<6345> A_IWL<6344> A_IWL<6343> A_IWL<6342> A_IWL<6341> A_IWL<6340> A_IWL<6339> A_IWL<6338> A_IWL<6337> A_IWL<6336> A_IWL<6335> A_IWL<6334> A_IWL<6333> A_IWL<6332> A_IWL<6331> A_IWL<6330> A_IWL<6329> A_IWL<6328> A_IWL<6327> A_IWL<6326> A_IWL<6325> A_IWL<6324> A_IWL<6323> A_IWL<6322> A_IWL<6321> A_IWL<6320> A_IWL<6319> A_IWL<6318> A_IWL<6317> A_IWL<6316> A_IWL<6315> A_IWL<6314> A_IWL<6313> A_IWL<6312> A_IWL<6311> A_IWL<6310> A_IWL<6309> A_IWL<6308> A_IWL<6307> A_IWL<6306> A_IWL<6305> A_IWL<6304> A_IWL<6303> A_IWL<6302> A_IWL<6301> A_IWL<6300> A_IWL<6299> A_IWL<6298> A_IWL<6297> A_IWL<6296> A_IWL<6295> A_IWL<6294> A_IWL<6293> A_IWL<6292> A_IWL<6291> A_IWL<6290> A_IWL<6289> A_IWL<6288> A_IWL<6287> A_IWL<6286> A_IWL<6285> A_IWL<6284> A_IWL<6283> A_IWL<6282> A_IWL<6281> A_IWL<6280> A_IWL<6279> A_IWL<6278> A_IWL<6277> A_IWL<6276> A_IWL<6275> A_IWL<6274> A_IWL<6273> A_IWL<6272> A_IWL<6271> A_IWL<6270> A_IWL<6269> A_IWL<6268> A_IWL<6267> A_IWL<6266> A_IWL<6265> A_IWL<6264> A_IWL<6263> A_IWL<6262> A_IWL<6261> A_IWL<6260> A_IWL<6259> A_IWL<6258> A_IWL<6257> A_IWL<6256> A_IWL<6255> A_IWL<6254> A_IWL<6253> A_IWL<6252> A_IWL<6251> A_IWL<6250> A_IWL<6249> A_IWL<6248> A_IWL<6247> A_IWL<6246> A_IWL<6245> A_IWL<6244> A_IWL<6243> A_IWL<6242> A_IWL<6241> A_IWL<6240> A_IWL<6239> A_IWL<6238> A_IWL<6237> A_IWL<6236> A_IWL<6235> A_IWL<6234> A_IWL<6233> A_IWL<6232> A_IWL<6231> A_IWL<6230> A_IWL<6229> A_IWL<6228> A_IWL<6227> A_IWL<6226> A_IWL<6225> A_IWL<6224> A_IWL<6223> A_IWL<6222> A_IWL<6221> A_IWL<6220> A_IWL<6219> A_IWL<6218> A_IWL<6217> A_IWL<6216> A_IWL<6215> A_IWL<6214> A_IWL<6213> A_IWL<6212> A_IWL<6211> A_IWL<6210> A_IWL<6209> A_IWL<6208> A_IWL<6207> A_IWL<6206> A_IWL<6205> A_IWL<6204> A_IWL<6203> A_IWL<6202> A_IWL<6201> A_IWL<6200> A_IWL<6199> A_IWL<6198> A_IWL<6197> A_IWL<6196> A_IWL<6195> A_IWL<6194> A_IWL<6193> A_IWL<6192> A_IWL<6191> A_IWL<6190> A_IWL<6189> A_IWL<6188> A_IWL<6187> A_IWL<6186> A_IWL<6185> A_IWL<6184> A_IWL<6183> A_IWL<6182> A_IWL<6181> A_IWL<6180> A_IWL<6179> A_IWL<6178> A_IWL<6177> A_IWL<6176> A_IWL<6175> A_IWL<6174> A_IWL<6173> A_IWL<6172> A_IWL<6171> A_IWL<6170> A_IWL<6169> A_IWL<6168> A_IWL<6167> A_IWL<6166> A_IWL<6165> A_IWL<6164> A_IWL<6163> A_IWL<6162> A_IWL<6161> A_IWL<6160> A_IWL<6159> A_IWL<6158> A_IWL<6157> A_IWL<6156> A_IWL<6155> A_IWL<6154> A_IWL<6153> A_IWL<6152> A_IWL<6151> A_IWL<6150> A_IWL<6149> A_IWL<6148> A_IWL<6147> A_IWL<6146> A_IWL<6145> A_IWL<6144> A_IWL<7167> A_IWL<7166> A_IWL<7165> A_IWL<7164> A_IWL<7163> A_IWL<7162> A_IWL<7161> A_IWL<7160> A_IWL<7159> A_IWL<7158> A_IWL<7157> A_IWL<7156> A_IWL<7155> A_IWL<7154> A_IWL<7153> A_IWL<7152> A_IWL<7151> A_IWL<7150> A_IWL<7149> A_IWL<7148> A_IWL<7147> A_IWL<7146> A_IWL<7145> A_IWL<7144> A_IWL<7143> A_IWL<7142> A_IWL<7141> A_IWL<7140> A_IWL<7139> A_IWL<7138> A_IWL<7137> A_IWL<7136> A_IWL<7135> A_IWL<7134> A_IWL<7133> A_IWL<7132> A_IWL<7131> A_IWL<7130> A_IWL<7129> A_IWL<7128> A_IWL<7127> A_IWL<7126> A_IWL<7125> A_IWL<7124> A_IWL<7123> A_IWL<7122> A_IWL<7121> A_IWL<7120> A_IWL<7119> A_IWL<7118> A_IWL<7117> A_IWL<7116> A_IWL<7115> A_IWL<7114> A_IWL<7113> A_IWL<7112> A_IWL<7111> A_IWL<7110> A_IWL<7109> A_IWL<7108> A_IWL<7107> A_IWL<7106> A_IWL<7105> A_IWL<7104> A_IWL<7103> A_IWL<7102> A_IWL<7101> A_IWL<7100> A_IWL<7099> A_IWL<7098> A_IWL<7097> A_IWL<7096> A_IWL<7095> A_IWL<7094> A_IWL<7093> A_IWL<7092> A_IWL<7091> A_IWL<7090> A_IWL<7089> A_IWL<7088> A_IWL<7087> A_IWL<7086> A_IWL<7085> A_IWL<7084> A_IWL<7083> A_IWL<7082> A_IWL<7081> A_IWL<7080> A_IWL<7079> A_IWL<7078> A_IWL<7077> A_IWL<7076> A_IWL<7075> A_IWL<7074> A_IWL<7073> A_IWL<7072> A_IWL<7071> A_IWL<7070> A_IWL<7069> A_IWL<7068> A_IWL<7067> A_IWL<7066> A_IWL<7065> A_IWL<7064> A_IWL<7063> A_IWL<7062> A_IWL<7061> A_IWL<7060> A_IWL<7059> A_IWL<7058> A_IWL<7057> A_IWL<7056> A_IWL<7055> A_IWL<7054> A_IWL<7053> A_IWL<7052> A_IWL<7051> A_IWL<7050> A_IWL<7049> A_IWL<7048> A_IWL<7047> A_IWL<7046> A_IWL<7045> A_IWL<7044> A_IWL<7043> A_IWL<7042> A_IWL<7041> A_IWL<7040> A_IWL<7039> A_IWL<7038> A_IWL<7037> A_IWL<7036> A_IWL<7035> A_IWL<7034> A_IWL<7033> A_IWL<7032> A_IWL<7031> A_IWL<7030> A_IWL<7029> A_IWL<7028> A_IWL<7027> A_IWL<7026> A_IWL<7025> A_IWL<7024> A_IWL<7023> A_IWL<7022> A_IWL<7021> A_IWL<7020> A_IWL<7019> A_IWL<7018> A_IWL<7017> A_IWL<7016> A_IWL<7015> A_IWL<7014> A_IWL<7013> A_IWL<7012> A_IWL<7011> A_IWL<7010> A_IWL<7009> A_IWL<7008> A_IWL<7007> A_IWL<7006> A_IWL<7005> A_IWL<7004> A_IWL<7003> A_IWL<7002> A_IWL<7001> A_IWL<7000> A_IWL<6999> A_IWL<6998> A_IWL<6997> A_IWL<6996> A_IWL<6995> A_IWL<6994> A_IWL<6993> A_IWL<6992> A_IWL<6991> A_IWL<6990> A_IWL<6989> A_IWL<6988> A_IWL<6987> A_IWL<6986> A_IWL<6985> A_IWL<6984> A_IWL<6983> A_IWL<6982> A_IWL<6981> A_IWL<6980> A_IWL<6979> A_IWL<6978> A_IWL<6977> A_IWL<6976> A_IWL<6975> A_IWL<6974> A_IWL<6973> A_IWL<6972> A_IWL<6971> A_IWL<6970> A_IWL<6969> A_IWL<6968> A_IWL<6967> A_IWL<6966> A_IWL<6965> A_IWL<6964> A_IWL<6963> A_IWL<6962> A_IWL<6961> A_IWL<6960> A_IWL<6959> A_IWL<6958> A_IWL<6957> A_IWL<6956> A_IWL<6955> A_IWL<6954> A_IWL<6953> A_IWL<6952> A_IWL<6951> A_IWL<6950> A_IWL<6949> A_IWL<6948> A_IWL<6947> A_IWL<6946> A_IWL<6945> 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A_IWL<6307> A_IWL<6306> A_IWL<6305> A_IWL<6304> A_IWL<6303> A_IWL<6302> A_IWL<6301> A_IWL<6300> A_IWL<6299> A_IWL<6298> A_IWL<6297> A_IWL<6296> A_IWL<6295> A_IWL<6294> A_IWL<6293> A_IWL<6292> A_IWL<6291> A_IWL<6290> A_IWL<6289> A_IWL<6288> A_IWL<6287> A_IWL<6286> A_IWL<6285> A_IWL<6284> A_IWL<6283> A_IWL<6282> A_IWL<6281> A_IWL<6280> A_IWL<6279> A_IWL<6278> A_IWL<6277> A_IWL<6276> A_IWL<6275> A_IWL<6274> A_IWL<6273> A_IWL<6272> A_IWL<6271> A_IWL<6270> A_IWL<6269> A_IWL<6268> A_IWL<6267> A_IWL<6266> A_IWL<6265> A_IWL<6264> A_IWL<6263> A_IWL<6262> A_IWL<6261> A_IWL<6260> A_IWL<6259> A_IWL<6258> A_IWL<6257> A_IWL<6256> A_IWL<6255> A_IWL<6254> A_IWL<6253> A_IWL<6252> A_IWL<6251> A_IWL<6250> A_IWL<6249> A_IWL<6248> A_IWL<6247> A_IWL<6246> A_IWL<6245> A_IWL<6244> A_IWL<6243> A_IWL<6242> A_IWL<6241> A_IWL<6240> A_IWL<6239> A_IWL<6238> A_IWL<6237> A_IWL<6236> A_IWL<6235> A_IWL<6234> A_IWL<6233> A_IWL<6232> A_IWL<6231> A_IWL<6230> A_IWL<6229> A_IWL<6228> A_IWL<6227> A_IWL<6226> A_IWL<6225> A_IWL<6224> A_IWL<6223> A_IWL<6222> A_IWL<6221> A_IWL<6220> A_IWL<6219> A_IWL<6218> A_IWL<6217> A_IWL<6216> A_IWL<6215> A_IWL<6214> A_IWL<6213> A_IWL<6212> A_IWL<6211> A_IWL<6210> A_IWL<6209> A_IWL<6208> A_IWL<6207> A_IWL<6206> A_IWL<6205> A_IWL<6204> A_IWL<6203> A_IWL<6202> A_IWL<6201> A_IWL<6200> A_IWL<6199> A_IWL<6198> A_IWL<6197> A_IWL<6196> A_IWL<6195> A_IWL<6194> A_IWL<6193> A_IWL<6192> A_IWL<6191> A_IWL<6190> A_IWL<6189> A_IWL<6188> A_IWL<6187> A_IWL<6186> A_IWL<6185> A_IWL<6184> A_IWL<6183> A_IWL<6182> A_IWL<6181> A_IWL<6180> A_IWL<6179> A_IWL<6178> A_IWL<6177> A_IWL<6176> A_IWL<6175> A_IWL<6174> A_IWL<6173> A_IWL<6172> A_IWL<6171> A_IWL<6170> A_IWL<6169> A_IWL<6168> A_IWL<6167> A_IWL<6166> A_IWL<6165> A_IWL<6164> A_IWL<6163> A_IWL<6162> A_IWL<6161> A_IWL<6160> A_IWL<6159> A_IWL<6158> A_IWL<6157> A_IWL<6156> A_IWL<6155> A_IWL<6154> A_IWL<6153> A_IWL<6152> A_IWL<6151> A_IWL<6150> A_IWL<6149> A_IWL<6148> A_IWL<6147> A_IWL<6146> A_IWL<6145> A_IWL<6144> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_COLUMN_pcell_0 +XCOL<11> A_BLC<23> A_BLC<22> A_BLC_TOP<23> A_BLC_TOP<22> A_BLT<23> A_BLT<22> A_BLT_TOP<23> A_BLT_TOP<22> A_IWL<5631> A_IWL<5630> A_IWL<5629> A_IWL<5628> A_IWL<5627> A_IWL<5626> A_IWL<5625> A_IWL<5624> A_IWL<5623> A_IWL<5622> A_IWL<5621> A_IWL<5620> A_IWL<5619> A_IWL<5618> A_IWL<5617> A_IWL<5616> A_IWL<5615> A_IWL<5614> A_IWL<5613> A_IWL<5612> A_IWL<5611> A_IWL<5610> A_IWL<5609> A_IWL<5608> A_IWL<5607> A_IWL<5606> A_IWL<5605> A_IWL<5604> A_IWL<5603> A_IWL<5602> A_IWL<5601> A_IWL<5600> A_IWL<5599> A_IWL<5598> A_IWL<5597> A_IWL<5596> A_IWL<5595> A_IWL<5594> A_IWL<5593> A_IWL<5592> A_IWL<5591> A_IWL<5590> A_IWL<5589> A_IWL<5588> A_IWL<5587> A_IWL<5586> A_IWL<5585> A_IWL<5584> A_IWL<5583> A_IWL<5582> A_IWL<5581> A_IWL<5580> A_IWL<5579> A_IWL<5578> A_IWL<5577> A_IWL<5576> A_IWL<5575> A_IWL<5574> A_IWL<5573> A_IWL<5572> A_IWL<5571> A_IWL<5570> A_IWL<5569> A_IWL<5568> A_IWL<5567> A_IWL<5566> A_IWL<5565> A_IWL<5564> A_IWL<5563> A_IWL<5562> A_IWL<5561> A_IWL<5560> A_IWL<5559> A_IWL<5558> A_IWL<5557> A_IWL<5556> A_IWL<5555> A_IWL<5554> A_IWL<5553> A_IWL<5552> A_IWL<5551> A_IWL<5550> A_IWL<5549> A_IWL<5548> A_IWL<5547> A_IWL<5546> A_IWL<5545> A_IWL<5544> A_IWL<5543> A_IWL<5542> A_IWL<5541> A_IWL<5540> A_IWL<5539> A_IWL<5538> A_IWL<5537> A_IWL<5536> A_IWL<5535> A_IWL<5534> A_IWL<5533> A_IWL<5532> A_IWL<5531> A_IWL<5530> A_IWL<5529> A_IWL<5528> A_IWL<5527> A_IWL<5526> A_IWL<5525> A_IWL<5524> A_IWL<5523> A_IWL<5522> A_IWL<5521> A_IWL<5520> A_IWL<5519> A_IWL<5518> A_IWL<5517> A_IWL<5516> A_IWL<5515> A_IWL<5514> A_IWL<5513> A_IWL<5512> A_IWL<5511> A_IWL<5510> A_IWL<5509> A_IWL<5508> A_IWL<5507> A_IWL<5506> A_IWL<5505> A_IWL<5504> A_IWL<5503> A_IWL<5502> A_IWL<5501> A_IWL<5500> A_IWL<5499> A_IWL<5498> A_IWL<5497> A_IWL<5496> A_IWL<5495> A_IWL<5494> A_IWL<5493> A_IWL<5492> A_IWL<5491> A_IWL<5490> A_IWL<5489> A_IWL<5488> A_IWL<5487> A_IWL<5486> A_IWL<5485> A_IWL<5484> A_IWL<5483> A_IWL<5482> A_IWL<5481> A_IWL<5480> A_IWL<5479> A_IWL<5478> A_IWL<5477> A_IWL<5476> A_IWL<5475> A_IWL<5474> A_IWL<5473> A_IWL<5472> A_IWL<5471> A_IWL<5470> A_IWL<5469> A_IWL<5468> A_IWL<5467> A_IWL<5466> A_IWL<5465> A_IWL<5464> A_IWL<5463> A_IWL<5462> A_IWL<5461> A_IWL<5460> A_IWL<5459> A_IWL<5458> A_IWL<5457> A_IWL<5456> A_IWL<5455> A_IWL<5454> A_IWL<5453> A_IWL<5452> A_IWL<5451> A_IWL<5450> A_IWL<5449> A_IWL<5448> A_IWL<5447> A_IWL<5446> A_IWL<5445> A_IWL<5444> A_IWL<5443> A_IWL<5442> A_IWL<5441> A_IWL<5440> A_IWL<5439> A_IWL<5438> A_IWL<5437> A_IWL<5436> A_IWL<5435> A_IWL<5434> A_IWL<5433> A_IWL<5432> A_IWL<5431> A_IWL<5430> A_IWL<5429> A_IWL<5428> A_IWL<5427> A_IWL<5426> A_IWL<5425> A_IWL<5424> A_IWL<5423> A_IWL<5422> A_IWL<5421> A_IWL<5420> A_IWL<5419> A_IWL<5418> A_IWL<5417> A_IWL<5416> A_IWL<5415> A_IWL<5414> A_IWL<5413> A_IWL<5412> A_IWL<5411> A_IWL<5410> A_IWL<5409> A_IWL<5408> A_IWL<5407> A_IWL<5406> A_IWL<5405> A_IWL<5404> A_IWL<5403> A_IWL<5402> A_IWL<5401> A_IWL<5400> A_IWL<5399> A_IWL<5398> A_IWL<5397> A_IWL<5396> A_IWL<5395> A_IWL<5394> A_IWL<5393> A_IWL<5392> A_IWL<5391> A_IWL<5390> A_IWL<5389> A_IWL<5388> A_IWL<5387> A_IWL<5386> A_IWL<5385> A_IWL<5384> A_IWL<5383> A_IWL<5382> A_IWL<5381> A_IWL<5380> A_IWL<5379> A_IWL<5378> A_IWL<5377> A_IWL<5376> A_IWL<5375> A_IWL<5374> A_IWL<5373> A_IWL<5372> A_IWL<5371> A_IWL<5370> A_IWL<5369> A_IWL<5368> A_IWL<5367> A_IWL<5366> A_IWL<5365> A_IWL<5364> A_IWL<5363> A_IWL<5362> A_IWL<5361> A_IWL<5360> A_IWL<5359> A_IWL<5358> A_IWL<5357> A_IWL<5356> A_IWL<5355> A_IWL<5354> A_IWL<5353> A_IWL<5352> A_IWL<5351> A_IWL<5350> A_IWL<5349> A_IWL<5348> A_IWL<5347> A_IWL<5346> A_IWL<5345> A_IWL<5344> A_IWL<5343> A_IWL<5342> A_IWL<5341> A_IWL<5340> A_IWL<5339> A_IWL<5338> A_IWL<5337> A_IWL<5336> A_IWL<5335> A_IWL<5334> A_IWL<5333> A_IWL<5332> A_IWL<5331> A_IWL<5330> A_IWL<5329> A_IWL<5328> A_IWL<5327> A_IWL<5326> A_IWL<5325> A_IWL<5324> A_IWL<5323> A_IWL<5322> A_IWL<5321> A_IWL<5320> A_IWL<5319> A_IWL<5318> A_IWL<5317> A_IWL<5316> A_IWL<5315> A_IWL<5314> A_IWL<5313> A_IWL<5312> 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A_IWL<5228> A_IWL<5227> A_IWL<5226> A_IWL<5225> A_IWL<5224> A_IWL<5223> A_IWL<5222> A_IWL<5221> A_IWL<5220> A_IWL<5219> A_IWL<5218> A_IWL<5217> A_IWL<5216> A_IWL<5215> A_IWL<5214> A_IWL<5213> A_IWL<5212> A_IWL<5211> A_IWL<5210> A_IWL<5209> A_IWL<5208> A_IWL<5207> A_IWL<5206> A_IWL<5205> A_IWL<5204> A_IWL<5203> A_IWL<5202> A_IWL<5201> A_IWL<5200> A_IWL<5199> A_IWL<5198> A_IWL<5197> A_IWL<5196> A_IWL<5195> A_IWL<5194> A_IWL<5193> A_IWL<5192> A_IWL<5191> A_IWL<5190> A_IWL<5189> A_IWL<5188> A_IWL<5187> A_IWL<5186> A_IWL<5185> A_IWL<5184> A_IWL<5183> A_IWL<5182> A_IWL<5181> A_IWL<5180> A_IWL<5179> A_IWL<5178> A_IWL<5177> A_IWL<5176> A_IWL<5175> A_IWL<5174> A_IWL<5173> A_IWL<5172> A_IWL<5171> A_IWL<5170> A_IWL<5169> A_IWL<5168> A_IWL<5167> A_IWL<5166> A_IWL<5165> A_IWL<5164> A_IWL<5163> A_IWL<5162> A_IWL<5161> A_IWL<5160> A_IWL<5159> A_IWL<5158> A_IWL<5157> A_IWL<5156> A_IWL<5155> A_IWL<5154> A_IWL<5153> A_IWL<5152> A_IWL<5151> A_IWL<5150> A_IWL<5149> A_IWL<5148> A_IWL<5147> A_IWL<5146> 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A_IWL<6086> A_IWL<6085> A_IWL<6084> A_IWL<6083> A_IWL<6082> A_IWL<6081> A_IWL<6080> A_IWL<6079> A_IWL<6078> A_IWL<6077> A_IWL<6076> A_IWL<6075> A_IWL<6074> A_IWL<6073> A_IWL<6072> A_IWL<6071> A_IWL<6070> A_IWL<6069> A_IWL<6068> A_IWL<6067> A_IWL<6066> A_IWL<6065> A_IWL<6064> A_IWL<6063> A_IWL<6062> A_IWL<6061> A_IWL<6060> A_IWL<6059> A_IWL<6058> A_IWL<6057> A_IWL<6056> A_IWL<6055> A_IWL<6054> A_IWL<6053> A_IWL<6052> A_IWL<6051> A_IWL<6050> A_IWL<6049> A_IWL<6048> A_IWL<6047> A_IWL<6046> A_IWL<6045> A_IWL<6044> A_IWL<6043> A_IWL<6042> A_IWL<6041> A_IWL<6040> A_IWL<6039> A_IWL<6038> A_IWL<6037> A_IWL<6036> A_IWL<6035> A_IWL<6034> A_IWL<6033> A_IWL<6032> A_IWL<6031> A_IWL<6030> A_IWL<6029> A_IWL<6028> A_IWL<6027> A_IWL<6026> A_IWL<6025> A_IWL<6024> A_IWL<6023> A_IWL<6022> A_IWL<6021> A_IWL<6020> A_IWL<6019> A_IWL<6018> A_IWL<6017> A_IWL<6016> A_IWL<6015> A_IWL<6014> A_IWL<6013> A_IWL<6012> A_IWL<6011> A_IWL<6010> A_IWL<6009> A_IWL<6008> A_IWL<6007> A_IWL<6006> A_IWL<6005> A_IWL<6004> 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A_IWL<5615> A_IWL<5614> A_IWL<5613> A_IWL<5612> A_IWL<5611> A_IWL<5610> A_IWL<5609> A_IWL<5608> A_IWL<5607> A_IWL<5606> A_IWL<5605> A_IWL<5604> A_IWL<5603> A_IWL<5602> A_IWL<5601> A_IWL<5600> A_IWL<5599> A_IWL<5598> A_IWL<5597> A_IWL<5596> A_IWL<5595> A_IWL<5594> A_IWL<5593> A_IWL<5592> A_IWL<5591> A_IWL<5590> A_IWL<5589> A_IWL<5588> A_IWL<5587> A_IWL<5586> A_IWL<5585> A_IWL<5584> A_IWL<5583> A_IWL<5582> A_IWL<5581> A_IWL<5580> A_IWL<5579> A_IWL<5578> A_IWL<5577> A_IWL<5576> A_IWL<5575> A_IWL<5574> A_IWL<5573> A_IWL<5572> A_IWL<5571> A_IWL<5570> A_IWL<5569> A_IWL<5568> A_IWL<5567> A_IWL<5566> A_IWL<5565> A_IWL<5564> A_IWL<5563> A_IWL<5562> A_IWL<5561> A_IWL<5560> A_IWL<5559> A_IWL<5558> A_IWL<5557> A_IWL<5556> A_IWL<5555> A_IWL<5554> A_IWL<5553> A_IWL<5552> A_IWL<5551> A_IWL<5550> A_IWL<5549> A_IWL<5548> A_IWL<5547> A_IWL<5546> A_IWL<5545> A_IWL<5544> A_IWL<5543> A_IWL<5542> A_IWL<5541> A_IWL<5540> A_IWL<5539> A_IWL<5538> A_IWL<5537> A_IWL<5536> A_IWL<5535> A_IWL<5534> A_IWL<5533> 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A_IWL<4536> A_IWL<4535> A_IWL<4534> A_IWL<4533> A_IWL<4532> A_IWL<4531> A_IWL<4530> A_IWL<4529> A_IWL<4528> A_IWL<4527> A_IWL<4526> A_IWL<4525> A_IWL<4524> A_IWL<4523> A_IWL<4522> A_IWL<4521> A_IWL<4520> A_IWL<4519> A_IWL<4518> A_IWL<4517> A_IWL<4516> A_IWL<4515> A_IWL<4514> A_IWL<4513> A_IWL<4512> A_IWL<4511> A_IWL<4510> A_IWL<4509> A_IWL<4508> A_IWL<4507> A_IWL<4506> A_IWL<4505> A_IWL<4504> A_IWL<4503> A_IWL<4502> A_IWL<4501> A_IWL<4500> A_IWL<4499> A_IWL<4498> A_IWL<4497> A_IWL<4496> A_IWL<4495> A_IWL<4494> A_IWL<4493> A_IWL<4492> A_IWL<4491> A_IWL<4490> A_IWL<4489> A_IWL<4488> A_IWL<4487> A_IWL<4486> A_IWL<4485> A_IWL<4484> A_IWL<4483> A_IWL<4482> A_IWL<4481> A_IWL<4480> A_IWL<4479> A_IWL<4478> A_IWL<4477> A_IWL<4476> A_IWL<4475> A_IWL<4474> A_IWL<4473> A_IWL<4472> A_IWL<4471> A_IWL<4470> A_IWL<4469> A_IWL<4468> A_IWL<4467> A_IWL<4466> A_IWL<4465> A_IWL<4464> A_IWL<4463> A_IWL<4462> A_IWL<4461> A_IWL<4460> A_IWL<4459> A_IWL<4458> A_IWL<4457> A_IWL<4456> A_IWL<4455> A_IWL<4454> A_IWL<4453> A_IWL<4452> A_IWL<4451> A_IWL<4450> A_IWL<4449> A_IWL<4448> A_IWL<4447> A_IWL<4446> A_IWL<4445> A_IWL<4444> A_IWL<4443> A_IWL<4442> A_IWL<4441> A_IWL<4440> A_IWL<4439> A_IWL<4438> A_IWL<4437> A_IWL<4436> A_IWL<4435> A_IWL<4434> A_IWL<4433> A_IWL<4432> A_IWL<4431> A_IWL<4430> A_IWL<4429> A_IWL<4428> A_IWL<4427> A_IWL<4426> A_IWL<4425> A_IWL<4424> A_IWL<4423> A_IWL<4422> A_IWL<4421> A_IWL<4420> A_IWL<4419> A_IWL<4418> A_IWL<4417> A_IWL<4416> A_IWL<4415> A_IWL<4414> A_IWL<4413> A_IWL<4412> A_IWL<4411> A_IWL<4410> A_IWL<4409> A_IWL<4408> A_IWL<4407> A_IWL<4406> A_IWL<4405> A_IWL<4404> A_IWL<4403> A_IWL<4402> A_IWL<4401> A_IWL<4400> A_IWL<4399> A_IWL<4398> A_IWL<4397> A_IWL<4396> A_IWL<4395> A_IWL<4394> A_IWL<4393> A_IWL<4392> A_IWL<4391> A_IWL<4390> A_IWL<4389> A_IWL<4388> A_IWL<4387> A_IWL<4386> A_IWL<4385> A_IWL<4384> A_IWL<4383> A_IWL<4382> A_IWL<4381> A_IWL<4380> A_IWL<4379> A_IWL<4378> A_IWL<4377> A_IWL<4376> A_IWL<4375> A_IWL<4374> A_IWL<4373> A_IWL<4372> A_IWL<4371> A_IWL<4370> A_IWL<4369> A_IWL<4368> A_IWL<4367> A_IWL<4366> A_IWL<4365> A_IWL<4364> A_IWL<4363> A_IWL<4362> A_IWL<4361> A_IWL<4360> A_IWL<4359> A_IWL<4358> A_IWL<4357> A_IWL<4356> A_IWL<4355> A_IWL<4354> A_IWL<4353> A_IWL<4352> A_IWL<4351> A_IWL<4350> A_IWL<4349> A_IWL<4348> A_IWL<4347> A_IWL<4346> A_IWL<4345> A_IWL<4344> A_IWL<4343> A_IWL<4342> A_IWL<4341> A_IWL<4340> A_IWL<4339> A_IWL<4338> A_IWL<4337> A_IWL<4336> A_IWL<4335> A_IWL<4334> A_IWL<4333> A_IWL<4332> A_IWL<4331> A_IWL<4330> A_IWL<4329> A_IWL<4328> A_IWL<4327> A_IWL<4326> A_IWL<4325> A_IWL<4324> A_IWL<4323> A_IWL<4322> A_IWL<4321> A_IWL<4320> A_IWL<4319> A_IWL<4318> A_IWL<4317> A_IWL<4316> A_IWL<4315> A_IWL<4314> A_IWL<4313> A_IWL<4312> A_IWL<4311> A_IWL<4310> A_IWL<4309> A_IWL<4308> A_IWL<4307> A_IWL<4306> A_IWL<4305> A_IWL<4304> A_IWL<4303> A_IWL<4302> A_IWL<4301> A_IWL<4300> A_IWL<4299> A_IWL<4298> A_IWL<4297> A_IWL<4296> A_IWL<4295> A_IWL<4294> A_IWL<4293> A_IWL<4292> A_IWL<4291> A_IWL<4290> A_IWL<4289> A_IWL<4288> A_IWL<4287> A_IWL<4286> A_IWL<4285> A_IWL<4284> A_IWL<4283> A_IWL<4282> A_IWL<4281> A_IWL<4280> A_IWL<4279> A_IWL<4278> A_IWL<4277> A_IWL<4276> A_IWL<4275> A_IWL<4274> A_IWL<4273> A_IWL<4272> A_IWL<4271> A_IWL<4270> A_IWL<4269> A_IWL<4268> A_IWL<4267> A_IWL<4266> A_IWL<4265> A_IWL<4264> A_IWL<4263> A_IWL<4262> A_IWL<4261> A_IWL<4260> A_IWL<4259> A_IWL<4258> A_IWL<4257> A_IWL<4256> A_IWL<4255> A_IWL<4254> A_IWL<4253> A_IWL<4252> A_IWL<4251> A_IWL<4250> A_IWL<4249> A_IWL<4248> A_IWL<4247> A_IWL<4246> A_IWL<4245> A_IWL<4244> A_IWL<4243> A_IWL<4242> A_IWL<4241> A_IWL<4240> A_IWL<4239> A_IWL<4238> A_IWL<4237> A_IWL<4236> A_IWL<4235> A_IWL<4234> A_IWL<4233> A_IWL<4232> A_IWL<4231> A_IWL<4230> A_IWL<4229> A_IWL<4228> A_IWL<4227> A_IWL<4226> A_IWL<4225> A_IWL<4224> A_IWL<4223> A_IWL<4222> A_IWL<4221> A_IWL<4220> A_IWL<4219> A_IWL<4218> A_IWL<4217> A_IWL<4216> A_IWL<4215> A_IWL<4214> A_IWL<4213> A_IWL<4212> A_IWL<4211> A_IWL<4210> A_IWL<4209> A_IWL<4208> A_IWL<4207> A_IWL<4206> A_IWL<4205> A_IWL<4204> A_IWL<4203> A_IWL<4202> A_IWL<4201> A_IWL<4200> A_IWL<4199> A_IWL<4198> A_IWL<4197> A_IWL<4196> A_IWL<4195> A_IWL<4194> A_IWL<4193> A_IWL<4192> A_IWL<4191> A_IWL<4190> A_IWL<4189> A_IWL<4188> A_IWL<4187> A_IWL<4186> A_IWL<4185> A_IWL<4184> A_IWL<4183> A_IWL<4182> A_IWL<4181> A_IWL<4180> A_IWL<4179> A_IWL<4178> A_IWL<4177> A_IWL<4176> A_IWL<4175> A_IWL<4174> A_IWL<4173> A_IWL<4172> A_IWL<4171> A_IWL<4170> A_IWL<4169> A_IWL<4168> A_IWL<4167> A_IWL<4166> A_IWL<4165> A_IWL<4164> A_IWL<4163> A_IWL<4162> A_IWL<4161> A_IWL<4160> A_IWL<4159> A_IWL<4158> A_IWL<4157> A_IWL<4156> A_IWL<4155> A_IWL<4154> A_IWL<4153> A_IWL<4152> A_IWL<4151> A_IWL<4150> A_IWL<4149> A_IWL<4148> A_IWL<4147> A_IWL<4146> A_IWL<4145> A_IWL<4144> A_IWL<4143> A_IWL<4142> A_IWL<4141> A_IWL<4140> A_IWL<4139> A_IWL<4138> A_IWL<4137> A_IWL<4136> A_IWL<4135> A_IWL<4134> A_IWL<4133> A_IWL<4132> A_IWL<4131> A_IWL<4130> A_IWL<4129> A_IWL<4128> A_IWL<4127> A_IWL<4126> A_IWL<4125> A_IWL<4124> A_IWL<4123> A_IWL<4122> A_IWL<4121> A_IWL<4120> A_IWL<4119> A_IWL<4118> A_IWL<4117> A_IWL<4116> A_IWL<4115> A_IWL<4114> A_IWL<4113> A_IWL<4112> A_IWL<4111> A_IWL<4110> A_IWL<4109> A_IWL<4108> A_IWL<4107> A_IWL<4106> A_IWL<4105> A_IWL<4104> A_IWL<4103> A_IWL<4102> A_IWL<4101> A_IWL<4100> A_IWL<4099> A_IWL<4098> A_IWL<4097> A_IWL<4096> A_IWL<5119> A_IWL<5118> A_IWL<5117> A_IWL<5116> A_IWL<5115> A_IWL<5114> A_IWL<5113> A_IWL<5112> A_IWL<5111> A_IWL<5110> A_IWL<5109> A_IWL<5108> A_IWL<5107> A_IWL<5106> A_IWL<5105> A_IWL<5104> A_IWL<5103> A_IWL<5102> A_IWL<5101> A_IWL<5100> A_IWL<5099> A_IWL<5098> A_IWL<5097> A_IWL<5096> A_IWL<5095> A_IWL<5094> A_IWL<5093> A_IWL<5092> A_IWL<5091> A_IWL<5090> A_IWL<5089> A_IWL<5088> A_IWL<5087> A_IWL<5086> A_IWL<5085> A_IWL<5084> A_IWL<5083> A_IWL<5082> A_IWL<5081> A_IWL<5080> A_IWL<5079> A_IWL<5078> A_IWL<5077> A_IWL<5076> A_IWL<5075> A_IWL<5074> A_IWL<5073> A_IWL<5072> A_IWL<5071> A_IWL<5070> A_IWL<5069> A_IWL<5068> A_IWL<5067> A_IWL<5066> A_IWL<5065> A_IWL<5064> A_IWL<5063> A_IWL<5062> A_IWL<5061> A_IWL<5060> A_IWL<5059> A_IWL<5058> A_IWL<5057> A_IWL<5056> A_IWL<5055> A_IWL<5054> A_IWL<5053> A_IWL<5052> A_IWL<5051> A_IWL<5050> A_IWL<5049> A_IWL<5048> A_IWL<5047> A_IWL<5046> A_IWL<5045> A_IWL<5044> A_IWL<5043> A_IWL<5042> A_IWL<5041> A_IWL<5040> A_IWL<5039> A_IWL<5038> A_IWL<5037> A_IWL<5036> A_IWL<5035> A_IWL<5034> A_IWL<5033> A_IWL<5032> A_IWL<5031> A_IWL<5030> A_IWL<5029> A_IWL<5028> A_IWL<5027> A_IWL<5026> A_IWL<5025> A_IWL<5024> A_IWL<5023> A_IWL<5022> A_IWL<5021> A_IWL<5020> A_IWL<5019> A_IWL<5018> A_IWL<5017> A_IWL<5016> A_IWL<5015> A_IWL<5014> A_IWL<5013> A_IWL<5012> A_IWL<5011> A_IWL<5010> A_IWL<5009> A_IWL<5008> A_IWL<5007> A_IWL<5006> A_IWL<5005> A_IWL<5004> A_IWL<5003> A_IWL<5002> A_IWL<5001> A_IWL<5000> A_IWL<4999> A_IWL<4998> A_IWL<4997> A_IWL<4996> A_IWL<4995> A_IWL<4994> A_IWL<4993> A_IWL<4992> A_IWL<4991> A_IWL<4990> A_IWL<4989> A_IWL<4988> A_IWL<4987> A_IWL<4986> A_IWL<4985> A_IWL<4984> A_IWL<4983> A_IWL<4982> A_IWL<4981> A_IWL<4980> A_IWL<4979> A_IWL<4978> A_IWL<4977> A_IWL<4976> A_IWL<4975> A_IWL<4974> A_IWL<4973> A_IWL<4972> A_IWL<4971> A_IWL<4970> A_IWL<4969> A_IWL<4968> A_IWL<4967> A_IWL<4966> A_IWL<4965> A_IWL<4964> A_IWL<4963> A_IWL<4962> A_IWL<4961> A_IWL<4960> A_IWL<4959> A_IWL<4958> A_IWL<4957> A_IWL<4956> A_IWL<4955> A_IWL<4954> A_IWL<4953> A_IWL<4952> A_IWL<4951> A_IWL<4950> A_IWL<4949> A_IWL<4948> A_IWL<4947> A_IWL<4946> A_IWL<4945> A_IWL<4944> A_IWL<4943> A_IWL<4942> A_IWL<4941> A_IWL<4940> A_IWL<4939> A_IWL<4938> A_IWL<4937> A_IWL<4936> A_IWL<4935> A_IWL<4934> A_IWL<4933> A_IWL<4932> A_IWL<4931> A_IWL<4930> A_IWL<4929> A_IWL<4928> A_IWL<4927> A_IWL<4926> A_IWL<4925> A_IWL<4924> A_IWL<4923> A_IWL<4922> A_IWL<4921> A_IWL<4920> A_IWL<4919> A_IWL<4918> A_IWL<4917> A_IWL<4916> A_IWL<4915> A_IWL<4914> A_IWL<4913> A_IWL<4912> A_IWL<4911> A_IWL<4910> A_IWL<4909> A_IWL<4908> A_IWL<4907> A_IWL<4906> A_IWL<4905> A_IWL<4904> A_IWL<4903> A_IWL<4902> A_IWL<4901> A_IWL<4900> A_IWL<4899> A_IWL<4898> A_IWL<4897> A_IWL<4896> A_IWL<4895> A_IWL<4894> A_IWL<4893> A_IWL<4892> A_IWL<4891> A_IWL<4890> A_IWL<4889> A_IWL<4888> A_IWL<4887> A_IWL<4886> A_IWL<4885> A_IWL<4884> A_IWL<4883> A_IWL<4882> A_IWL<4881> A_IWL<4880> A_IWL<4879> A_IWL<4878> A_IWL<4877> A_IWL<4876> A_IWL<4875> A_IWL<4874> A_IWL<4873> A_IWL<4872> A_IWL<4871> A_IWL<4870> A_IWL<4869> A_IWL<4868> A_IWL<4867> A_IWL<4866> A_IWL<4865> A_IWL<4864> A_IWL<4863> A_IWL<4862> A_IWL<4861> A_IWL<4860> A_IWL<4859> A_IWL<4858> A_IWL<4857> A_IWL<4856> A_IWL<4855> A_IWL<4854> A_IWL<4853> A_IWL<4852> A_IWL<4851> A_IWL<4850> A_IWL<4849> A_IWL<4848> A_IWL<4847> A_IWL<4846> A_IWL<4845> A_IWL<4844> A_IWL<4843> A_IWL<4842> A_IWL<4841> A_IWL<4840> A_IWL<4839> A_IWL<4838> A_IWL<4837> A_IWL<4836> A_IWL<4835> A_IWL<4834> A_IWL<4833> A_IWL<4832> A_IWL<4831> A_IWL<4830> A_IWL<4829> A_IWL<4828> A_IWL<4827> A_IWL<4826> A_IWL<4825> A_IWL<4824> A_IWL<4823> A_IWL<4822> A_IWL<4821> A_IWL<4820> A_IWL<4819> A_IWL<4818> A_IWL<4817> A_IWL<4816> A_IWL<4815> A_IWL<4814> A_IWL<4813> A_IWL<4812> A_IWL<4811> A_IWL<4810> A_IWL<4809> A_IWL<4808> A_IWL<4807> A_IWL<4806> A_IWL<4805> A_IWL<4804> A_IWL<4803> A_IWL<4802> A_IWL<4801> A_IWL<4800> A_IWL<4799> A_IWL<4798> A_IWL<4797> A_IWL<4796> A_IWL<4795> A_IWL<4794> A_IWL<4793> A_IWL<4792> A_IWL<4791> A_IWL<4790> A_IWL<4789> A_IWL<4788> A_IWL<4787> A_IWL<4786> A_IWL<4785> A_IWL<4784> A_IWL<4783> A_IWL<4782> A_IWL<4781> A_IWL<4780> A_IWL<4779> A_IWL<4778> A_IWL<4777> A_IWL<4776> A_IWL<4775> A_IWL<4774> A_IWL<4773> A_IWL<4772> A_IWL<4771> A_IWL<4770> A_IWL<4769> A_IWL<4768> A_IWL<4767> A_IWL<4766> A_IWL<4765> A_IWL<4764> A_IWL<4763> A_IWL<4762> A_IWL<4761> A_IWL<4760> A_IWL<4759> A_IWL<4758> A_IWL<4757> A_IWL<4756> A_IWL<4755> A_IWL<4754> A_IWL<4753> A_IWL<4752> A_IWL<4751> A_IWL<4750> A_IWL<4749> A_IWL<4748> A_IWL<4747> A_IWL<4746> A_IWL<4745> A_IWL<4744> A_IWL<4743> A_IWL<4742> A_IWL<4741> A_IWL<4740> A_IWL<4739> A_IWL<4738> A_IWL<4737> A_IWL<4736> A_IWL<4735> A_IWL<4734> A_IWL<4733> A_IWL<4732> A_IWL<4731> A_IWL<4730> A_IWL<4729> A_IWL<4728> A_IWL<4727> A_IWL<4726> A_IWL<4725> A_IWL<4724> A_IWL<4723> A_IWL<4722> A_IWL<4721> A_IWL<4720> A_IWL<4719> A_IWL<4718> A_IWL<4717> A_IWL<4716> A_IWL<4715> A_IWL<4714> A_IWL<4713> A_IWL<4712> A_IWL<4711> A_IWL<4710> A_IWL<4709> A_IWL<4708> A_IWL<4707> A_IWL<4706> A_IWL<4705> A_IWL<4704> A_IWL<4703> A_IWL<4702> A_IWL<4701> A_IWL<4700> A_IWL<4699> A_IWL<4698> A_IWL<4697> A_IWL<4696> A_IWL<4695> A_IWL<4694> A_IWL<4693> A_IWL<4692> A_IWL<4691> A_IWL<4690> A_IWL<4689> A_IWL<4688> A_IWL<4687> A_IWL<4686> A_IWL<4685> A_IWL<4684> A_IWL<4683> A_IWL<4682> A_IWL<4681> A_IWL<4680> A_IWL<4679> A_IWL<4678> A_IWL<4677> A_IWL<4676> A_IWL<4675> A_IWL<4674> A_IWL<4673> A_IWL<4672> A_IWL<4671> A_IWL<4670> A_IWL<4669> A_IWL<4668> A_IWL<4667> A_IWL<4666> A_IWL<4665> A_IWL<4664> A_IWL<4663> A_IWL<4662> A_IWL<4661> A_IWL<4660> A_IWL<4659> A_IWL<4658> A_IWL<4657> A_IWL<4656> A_IWL<4655> A_IWL<4654> A_IWL<4653> A_IWL<4652> A_IWL<4651> A_IWL<4650> A_IWL<4649> A_IWL<4648> A_IWL<4647> A_IWL<4646> A_IWL<4645> A_IWL<4644> A_IWL<4643> A_IWL<4642> A_IWL<4641> A_IWL<4640> A_IWL<4639> A_IWL<4638> A_IWL<4637> A_IWL<4636> A_IWL<4635> A_IWL<4634> A_IWL<4633> A_IWL<4632> A_IWL<4631> A_IWL<4630> A_IWL<4629> A_IWL<4628> A_IWL<4627> A_IWL<4626> A_IWL<4625> A_IWL<4624> A_IWL<4623> A_IWL<4622> A_IWL<4621> A_IWL<4620> A_IWL<4619> A_IWL<4618> A_IWL<4617> A_IWL<4616> A_IWL<4615> A_IWL<4614> A_IWL<4613> A_IWL<4612> A_IWL<4611> A_IWL<4610> A_IWL<4609> A_IWL<4608> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_COLUMN_pcell_0 +XCOL<8> A_BLC<17> A_BLC<16> A_BLC_TOP<17> A_BLC_TOP<16> A_BLT<17> A_BLT<16> A_BLT_TOP<17> A_BLT_TOP<16> A_IWL<4095> A_IWL<4094> A_IWL<4093> A_IWL<4092> A_IWL<4091> A_IWL<4090> A_IWL<4089> A_IWL<4088> A_IWL<4087> A_IWL<4086> A_IWL<4085> A_IWL<4084> A_IWL<4083> A_IWL<4082> A_IWL<4081> A_IWL<4080> A_IWL<4079> A_IWL<4078> A_IWL<4077> A_IWL<4076> A_IWL<4075> A_IWL<4074> A_IWL<4073> A_IWL<4072> A_IWL<4071> A_IWL<4070> A_IWL<4069> A_IWL<4068> A_IWL<4067> A_IWL<4066> A_IWL<4065> A_IWL<4064> A_IWL<4063> A_IWL<4062> A_IWL<4061> A_IWL<4060> A_IWL<4059> A_IWL<4058> A_IWL<4057> A_IWL<4056> A_IWL<4055> A_IWL<4054> A_IWL<4053> A_IWL<4052> A_IWL<4051> A_IWL<4050> A_IWL<4049> A_IWL<4048> A_IWL<4047> A_IWL<4046> A_IWL<4045> A_IWL<4044> A_IWL<4043> A_IWL<4042> A_IWL<4041> A_IWL<4040> A_IWL<4039> A_IWL<4038> A_IWL<4037> A_IWL<4036> A_IWL<4035> A_IWL<4034> A_IWL<4033> A_IWL<4032> A_IWL<4031> A_IWL<4030> A_IWL<4029> A_IWL<4028> A_IWL<4027> A_IWL<4026> A_IWL<4025> A_IWL<4024> A_IWL<4023> A_IWL<4022> A_IWL<4021> A_IWL<4020> A_IWL<4019> A_IWL<4018> A_IWL<4017> A_IWL<4016> A_IWL<4015> A_IWL<4014> A_IWL<4013> A_IWL<4012> A_IWL<4011> A_IWL<4010> A_IWL<4009> A_IWL<4008> A_IWL<4007> A_IWL<4006> A_IWL<4005> A_IWL<4004> A_IWL<4003> A_IWL<4002> A_IWL<4001> A_IWL<4000> A_IWL<3999> A_IWL<3998> A_IWL<3997> A_IWL<3996> A_IWL<3995> A_IWL<3994> A_IWL<3993> A_IWL<3992> A_IWL<3991> A_IWL<3990> A_IWL<3989> A_IWL<3988> A_IWL<3987> A_IWL<3986> A_IWL<3985> A_IWL<3984> A_IWL<3983> A_IWL<3982> A_IWL<3981> A_IWL<3980> A_IWL<3979> A_IWL<3978> A_IWL<3977> A_IWL<3976> A_IWL<3975> A_IWL<3974> A_IWL<3973> A_IWL<3972> A_IWL<3971> A_IWL<3970> A_IWL<3969> A_IWL<3968> A_IWL<3967> A_IWL<3966> A_IWL<3965> A_IWL<3964> A_IWL<3963> A_IWL<3962> A_IWL<3961> A_IWL<3960> A_IWL<3959> A_IWL<3958> A_IWL<3957> A_IWL<3956> A_IWL<3955> A_IWL<3954> A_IWL<3953> A_IWL<3952> A_IWL<3951> A_IWL<3950> A_IWL<3949> A_IWL<3948> A_IWL<3947> A_IWL<3946> A_IWL<3945> A_IWL<3944> A_IWL<3943> A_IWL<3942> A_IWL<3941> A_IWL<3940> A_IWL<3939> A_IWL<3938> A_IWL<3937> A_IWL<3936> A_IWL<3935> A_IWL<3934> A_IWL<3933> A_IWL<3932> A_IWL<3931> A_IWL<3930> A_IWL<3929> A_IWL<3928> A_IWL<3927> A_IWL<3926> A_IWL<3925> A_IWL<3924> A_IWL<3923> A_IWL<3922> A_IWL<3921> A_IWL<3920> A_IWL<3919> A_IWL<3918> A_IWL<3917> A_IWL<3916> A_IWL<3915> A_IWL<3914> A_IWL<3913> A_IWL<3912> A_IWL<3911> A_IWL<3910> A_IWL<3909> A_IWL<3908> A_IWL<3907> A_IWL<3906> A_IWL<3905> A_IWL<3904> A_IWL<3903> A_IWL<3902> A_IWL<3901> A_IWL<3900> A_IWL<3899> A_IWL<3898> A_IWL<3897> A_IWL<3896> A_IWL<3895> A_IWL<3894> A_IWL<3893> A_IWL<3892> A_IWL<3891> A_IWL<3890> A_IWL<3889> A_IWL<3888> A_IWL<3887> A_IWL<3886> A_IWL<3885> A_IWL<3884> A_IWL<3883> A_IWL<3882> A_IWL<3881> A_IWL<3880> A_IWL<3879> A_IWL<3878> A_IWL<3877> A_IWL<3876> A_IWL<3875> A_IWL<3874> A_IWL<3873> A_IWL<3872> A_IWL<3871> A_IWL<3870> A_IWL<3869> A_IWL<3868> A_IWL<3867> A_IWL<3866> A_IWL<3865> A_IWL<3864> A_IWL<3863> A_IWL<3862> A_IWL<3861> A_IWL<3860> A_IWL<3859> A_IWL<3858> A_IWL<3857> A_IWL<3856> A_IWL<3855> A_IWL<3854> A_IWL<3853> A_IWL<3852> A_IWL<3851> A_IWL<3850> A_IWL<3849> A_IWL<3848> A_IWL<3847> A_IWL<3846> A_IWL<3845> A_IWL<3844> A_IWL<3843> A_IWL<3842> A_IWL<3841> A_IWL<3840> A_IWL<3839> A_IWL<3838> A_IWL<3837> A_IWL<3836> A_IWL<3835> A_IWL<3834> A_IWL<3833> A_IWL<3832> A_IWL<3831> A_IWL<3830> A_IWL<3829> A_IWL<3828> A_IWL<3827> A_IWL<3826> A_IWL<3825> A_IWL<3824> A_IWL<3823> A_IWL<3822> A_IWL<3821> A_IWL<3820> A_IWL<3819> A_IWL<3818> A_IWL<3817> A_IWL<3816> A_IWL<3815> A_IWL<3814> A_IWL<3813> A_IWL<3812> A_IWL<3811> A_IWL<3810> A_IWL<3809> A_IWL<3808> A_IWL<3807> A_IWL<3806> A_IWL<3805> A_IWL<3804> A_IWL<3803> A_IWL<3802> A_IWL<3801> A_IWL<3800> A_IWL<3799> A_IWL<3798> A_IWL<3797> A_IWL<3796> A_IWL<3795> A_IWL<3794> A_IWL<3793> A_IWL<3792> A_IWL<3791> A_IWL<3790> A_IWL<3789> A_IWL<3788> A_IWL<3787> A_IWL<3786> A_IWL<3785> A_IWL<3784> A_IWL<3783> A_IWL<3782> A_IWL<3781> A_IWL<3780> A_IWL<3779> A_IWL<3778> A_IWL<3777> A_IWL<3776> A_IWL<3775> A_IWL<3774> A_IWL<3773> A_IWL<3772> A_IWL<3771> A_IWL<3770> A_IWL<3769> A_IWL<3768> A_IWL<3767> A_IWL<3766> A_IWL<3765> A_IWL<3764> A_IWL<3763> A_IWL<3762> A_IWL<3761> A_IWL<3760> A_IWL<3759> A_IWL<3758> A_IWL<3757> A_IWL<3756> A_IWL<3755> A_IWL<3754> A_IWL<3753> A_IWL<3752> A_IWL<3751> A_IWL<3750> A_IWL<3749> A_IWL<3748> A_IWL<3747> A_IWL<3746> A_IWL<3745> A_IWL<3744> A_IWL<3743> A_IWL<3742> A_IWL<3741> A_IWL<3740> A_IWL<3739> A_IWL<3738> A_IWL<3737> A_IWL<3736> A_IWL<3735> A_IWL<3734> A_IWL<3733> A_IWL<3732> A_IWL<3731> A_IWL<3730> A_IWL<3729> A_IWL<3728> A_IWL<3727> A_IWL<3726> A_IWL<3725> A_IWL<3724> A_IWL<3723> A_IWL<3722> A_IWL<3721> A_IWL<3720> A_IWL<3719> A_IWL<3718> A_IWL<3717> A_IWL<3716> A_IWL<3715> A_IWL<3714> A_IWL<3713> A_IWL<3712> A_IWL<3711> A_IWL<3710> A_IWL<3709> A_IWL<3708> A_IWL<3707> A_IWL<3706> A_IWL<3705> A_IWL<3704> A_IWL<3703> A_IWL<3702> A_IWL<3701> A_IWL<3700> A_IWL<3699> A_IWL<3698> A_IWL<3697> A_IWL<3696> A_IWL<3695> A_IWL<3694> A_IWL<3693> A_IWL<3692> A_IWL<3691> A_IWL<3690> A_IWL<3689> A_IWL<3688> A_IWL<3687> A_IWL<3686> A_IWL<3685> A_IWL<3684> A_IWL<3683> A_IWL<3682> A_IWL<3681> A_IWL<3680> A_IWL<3679> A_IWL<3678> A_IWL<3677> A_IWL<3676> A_IWL<3675> A_IWL<3674> A_IWL<3673> A_IWL<3672> A_IWL<3671> A_IWL<3670> A_IWL<3669> A_IWL<3668> A_IWL<3667> A_IWL<3666> A_IWL<3665> A_IWL<3664> A_IWL<3663> A_IWL<3662> A_IWL<3661> A_IWL<3660> A_IWL<3659> A_IWL<3658> A_IWL<3657> A_IWL<3656> A_IWL<3655> A_IWL<3654> A_IWL<3653> A_IWL<3652> A_IWL<3651> A_IWL<3650> A_IWL<3649> A_IWL<3648> A_IWL<3647> A_IWL<3646> A_IWL<3645> A_IWL<3644> A_IWL<3643> A_IWL<3642> A_IWL<3641> A_IWL<3640> A_IWL<3639> A_IWL<3638> A_IWL<3637> A_IWL<3636> A_IWL<3635> A_IWL<3634> A_IWL<3633> A_IWL<3632> A_IWL<3631> A_IWL<3630> A_IWL<3629> A_IWL<3628> A_IWL<3627> A_IWL<3626> A_IWL<3625> A_IWL<3624> A_IWL<3623> A_IWL<3622> A_IWL<3621> A_IWL<3620> A_IWL<3619> A_IWL<3618> A_IWL<3617> A_IWL<3616> A_IWL<3615> A_IWL<3614> A_IWL<3613> A_IWL<3612> A_IWL<3611> A_IWL<3610> A_IWL<3609> A_IWL<3608> A_IWL<3607> A_IWL<3606> A_IWL<3605> A_IWL<3604> A_IWL<3603> A_IWL<3602> A_IWL<3601> A_IWL<3600> A_IWL<3599> A_IWL<3598> A_IWL<3597> A_IWL<3596> A_IWL<3595> A_IWL<3594> A_IWL<3593> A_IWL<3592> A_IWL<3591> A_IWL<3590> A_IWL<3589> A_IWL<3588> A_IWL<3587> A_IWL<3586> A_IWL<3585> A_IWL<3584> A_IWL<4607> A_IWL<4606> A_IWL<4605> A_IWL<4604> A_IWL<4603> A_IWL<4602> A_IWL<4601> A_IWL<4600> A_IWL<4599> A_IWL<4598> A_IWL<4597> A_IWL<4596> A_IWL<4595> A_IWL<4594> A_IWL<4593> A_IWL<4592> A_IWL<4591> A_IWL<4590> A_IWL<4589> A_IWL<4588> A_IWL<4587> A_IWL<4586> A_IWL<4585> A_IWL<4584> A_IWL<4583> A_IWL<4582> A_IWL<4581> A_IWL<4580> A_IWL<4579> A_IWL<4578> A_IWL<4577> A_IWL<4576> A_IWL<4575> A_IWL<4574> A_IWL<4573> A_IWL<4572> A_IWL<4571> A_IWL<4570> A_IWL<4569> A_IWL<4568> A_IWL<4567> A_IWL<4566> A_IWL<4565> A_IWL<4564> A_IWL<4563> A_IWL<4562> A_IWL<4561> A_IWL<4560> A_IWL<4559> A_IWL<4558> A_IWL<4557> A_IWL<4556> A_IWL<4555> A_IWL<4554> A_IWL<4553> A_IWL<4552> A_IWL<4551> A_IWL<4550> A_IWL<4549> A_IWL<4548> A_IWL<4547> A_IWL<4546> A_IWL<4545> A_IWL<4544> A_IWL<4543> A_IWL<4542> A_IWL<4541> A_IWL<4540> A_IWL<4539> A_IWL<4538> A_IWL<4537> A_IWL<4536> A_IWL<4535> A_IWL<4534> A_IWL<4533> A_IWL<4532> A_IWL<4531> A_IWL<4530> A_IWL<4529> A_IWL<4528> A_IWL<4527> A_IWL<4526> A_IWL<4525> A_IWL<4524> A_IWL<4523> A_IWL<4522> A_IWL<4521> A_IWL<4520> A_IWL<4519> A_IWL<4518> A_IWL<4517> A_IWL<4516> A_IWL<4515> A_IWL<4514> A_IWL<4513> A_IWL<4512> A_IWL<4511> A_IWL<4510> A_IWL<4509> A_IWL<4508> A_IWL<4507> A_IWL<4506> A_IWL<4505> A_IWL<4504> A_IWL<4503> A_IWL<4502> A_IWL<4501> A_IWL<4500> A_IWL<4499> A_IWL<4498> A_IWL<4497> A_IWL<4496> A_IWL<4495> A_IWL<4494> A_IWL<4493> A_IWL<4492> A_IWL<4491> A_IWL<4490> A_IWL<4489> A_IWL<4488> A_IWL<4487> A_IWL<4486> A_IWL<4485> A_IWL<4484> A_IWL<4483> A_IWL<4482> A_IWL<4481> A_IWL<4480> A_IWL<4479> A_IWL<4478> A_IWL<4477> A_IWL<4476> A_IWL<4475> A_IWL<4474> A_IWL<4473> A_IWL<4472> A_IWL<4471> A_IWL<4470> A_IWL<4469> A_IWL<4468> A_IWL<4467> A_IWL<4466> A_IWL<4465> A_IWL<4464> A_IWL<4463> A_IWL<4462> A_IWL<4461> A_IWL<4460> A_IWL<4459> A_IWL<4458> A_IWL<4457> A_IWL<4456> A_IWL<4455> A_IWL<4454> A_IWL<4453> A_IWL<4452> A_IWL<4451> A_IWL<4450> A_IWL<4449> A_IWL<4448> A_IWL<4447> A_IWL<4446> A_IWL<4445> A_IWL<4444> A_IWL<4443> A_IWL<4442> A_IWL<4441> A_IWL<4440> A_IWL<4439> A_IWL<4438> A_IWL<4437> A_IWL<4436> A_IWL<4435> A_IWL<4434> A_IWL<4433> A_IWL<4432> A_IWL<4431> A_IWL<4430> A_IWL<4429> A_IWL<4428> A_IWL<4427> A_IWL<4426> A_IWL<4425> A_IWL<4424> A_IWL<4423> A_IWL<4422> A_IWL<4421> A_IWL<4420> A_IWL<4419> A_IWL<4418> A_IWL<4417> A_IWL<4416> A_IWL<4415> A_IWL<4414> A_IWL<4413> A_IWL<4412> A_IWL<4411> A_IWL<4410> A_IWL<4409> A_IWL<4408> A_IWL<4407> A_IWL<4406> A_IWL<4405> A_IWL<4404> A_IWL<4403> A_IWL<4402> A_IWL<4401> A_IWL<4400> A_IWL<4399> A_IWL<4398> A_IWL<4397> A_IWL<4396> A_IWL<4395> A_IWL<4394> A_IWL<4393> A_IWL<4392> A_IWL<4391> A_IWL<4390> A_IWL<4389> A_IWL<4388> A_IWL<4387> A_IWL<4386> A_IWL<4385> A_IWL<4384> A_IWL<4383> A_IWL<4382> A_IWL<4381> A_IWL<4380> A_IWL<4379> A_IWL<4378> A_IWL<4377> A_IWL<4376> A_IWL<4375> A_IWL<4374> A_IWL<4373> A_IWL<4372> A_IWL<4371> A_IWL<4370> A_IWL<4369> A_IWL<4368> A_IWL<4367> A_IWL<4366> A_IWL<4365> A_IWL<4364> A_IWL<4363> A_IWL<4362> A_IWL<4361> A_IWL<4360> A_IWL<4359> A_IWL<4358> A_IWL<4357> A_IWL<4356> A_IWL<4355> A_IWL<4354> A_IWL<4353> A_IWL<4352> A_IWL<4351> A_IWL<4350> A_IWL<4349> A_IWL<4348> A_IWL<4347> A_IWL<4346> A_IWL<4345> A_IWL<4344> A_IWL<4343> A_IWL<4342> A_IWL<4341> A_IWL<4340> A_IWL<4339> A_IWL<4338> A_IWL<4337> A_IWL<4336> A_IWL<4335> A_IWL<4334> A_IWL<4333> A_IWL<4332> A_IWL<4331> A_IWL<4330> A_IWL<4329> A_IWL<4328> A_IWL<4327> A_IWL<4326> A_IWL<4325> A_IWL<4324> A_IWL<4323> A_IWL<4322> A_IWL<4321> A_IWL<4320> A_IWL<4319> A_IWL<4318> A_IWL<4317> A_IWL<4316> A_IWL<4315> A_IWL<4314> A_IWL<4313> A_IWL<4312> A_IWL<4311> A_IWL<4310> A_IWL<4309> A_IWL<4308> A_IWL<4307> A_IWL<4306> A_IWL<4305> A_IWL<4304> A_IWL<4303> A_IWL<4302> A_IWL<4301> A_IWL<4300> A_IWL<4299> A_IWL<4298> A_IWL<4297> A_IWL<4296> A_IWL<4295> A_IWL<4294> A_IWL<4293> A_IWL<4292> A_IWL<4291> A_IWL<4290> A_IWL<4289> A_IWL<4288> A_IWL<4287> A_IWL<4286> A_IWL<4285> A_IWL<4284> A_IWL<4283> A_IWL<4282> A_IWL<4281> A_IWL<4280> A_IWL<4279> A_IWL<4278> A_IWL<4277> A_IWL<4276> A_IWL<4275> A_IWL<4274> A_IWL<4273> A_IWL<4272> A_IWL<4271> A_IWL<4270> A_IWL<4269> A_IWL<4268> A_IWL<4267> A_IWL<4266> A_IWL<4265> A_IWL<4264> A_IWL<4263> A_IWL<4262> A_IWL<4261> A_IWL<4260> A_IWL<4259> A_IWL<4258> A_IWL<4257> A_IWL<4256> A_IWL<4255> A_IWL<4254> A_IWL<4253> A_IWL<4252> A_IWL<4251> A_IWL<4250> A_IWL<4249> A_IWL<4248> A_IWL<4247> A_IWL<4246> A_IWL<4245> A_IWL<4244> A_IWL<4243> A_IWL<4242> A_IWL<4241> A_IWL<4240> A_IWL<4239> A_IWL<4238> A_IWL<4237> A_IWL<4236> A_IWL<4235> A_IWL<4234> A_IWL<4233> A_IWL<4232> A_IWL<4231> A_IWL<4230> A_IWL<4229> A_IWL<4228> A_IWL<4227> A_IWL<4226> A_IWL<4225> A_IWL<4224> A_IWL<4223> A_IWL<4222> A_IWL<4221> A_IWL<4220> A_IWL<4219> A_IWL<4218> A_IWL<4217> A_IWL<4216> A_IWL<4215> A_IWL<4214> A_IWL<4213> A_IWL<4212> A_IWL<4211> A_IWL<4210> A_IWL<4209> A_IWL<4208> A_IWL<4207> A_IWL<4206> A_IWL<4205> A_IWL<4204> A_IWL<4203> A_IWL<4202> A_IWL<4201> A_IWL<4200> A_IWL<4199> A_IWL<4198> A_IWL<4197> A_IWL<4196> A_IWL<4195> A_IWL<4194> A_IWL<4193> A_IWL<4192> A_IWL<4191> A_IWL<4190> A_IWL<4189> A_IWL<4188> A_IWL<4187> A_IWL<4186> A_IWL<4185> A_IWL<4184> A_IWL<4183> A_IWL<4182> A_IWL<4181> A_IWL<4180> A_IWL<4179> A_IWL<4178> A_IWL<4177> A_IWL<4176> A_IWL<4175> A_IWL<4174> A_IWL<4173> A_IWL<4172> A_IWL<4171> A_IWL<4170> A_IWL<4169> A_IWL<4168> A_IWL<4167> A_IWL<4166> A_IWL<4165> A_IWL<4164> A_IWL<4163> A_IWL<4162> A_IWL<4161> A_IWL<4160> A_IWL<4159> A_IWL<4158> A_IWL<4157> A_IWL<4156> A_IWL<4155> A_IWL<4154> A_IWL<4153> A_IWL<4152> A_IWL<4151> A_IWL<4150> A_IWL<4149> A_IWL<4148> A_IWL<4147> A_IWL<4146> A_IWL<4145> A_IWL<4144> A_IWL<4143> A_IWL<4142> A_IWL<4141> A_IWL<4140> A_IWL<4139> A_IWL<4138> A_IWL<4137> A_IWL<4136> A_IWL<4135> A_IWL<4134> A_IWL<4133> A_IWL<4132> A_IWL<4131> A_IWL<4130> A_IWL<4129> A_IWL<4128> A_IWL<4127> A_IWL<4126> A_IWL<4125> A_IWL<4124> A_IWL<4123> A_IWL<4122> A_IWL<4121> A_IWL<4120> A_IWL<4119> A_IWL<4118> A_IWL<4117> A_IWL<4116> A_IWL<4115> A_IWL<4114> A_IWL<4113> A_IWL<4112> A_IWL<4111> A_IWL<4110> A_IWL<4109> A_IWL<4108> A_IWL<4107> A_IWL<4106> A_IWL<4105> A_IWL<4104> A_IWL<4103> A_IWL<4102> A_IWL<4101> A_IWL<4100> A_IWL<4099> A_IWL<4098> A_IWL<4097> A_IWL<4096> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_COLUMN_pcell_0 +XCOL<7> A_BLC<15> A_BLC<14> A_BLC_TOP<15> A_BLC_TOP<14> A_BLT<15> A_BLT<14> A_BLT_TOP<15> A_BLT_TOP<14> A_IWL<3583> A_IWL<3582> A_IWL<3581> A_IWL<3580> A_IWL<3579> A_IWL<3578> A_IWL<3577> A_IWL<3576> A_IWL<3575> A_IWL<3574> A_IWL<3573> A_IWL<3572> A_IWL<3571> A_IWL<3570> A_IWL<3569> A_IWL<3568> A_IWL<3567> A_IWL<3566> A_IWL<3565> A_IWL<3564> A_IWL<3563> A_IWL<3562> A_IWL<3561> A_IWL<3560> A_IWL<3559> A_IWL<3558> A_IWL<3557> A_IWL<3556> A_IWL<3555> A_IWL<3554> A_IWL<3553> A_IWL<3552> A_IWL<3551> A_IWL<3550> A_IWL<3549> A_IWL<3548> A_IWL<3547> A_IWL<3546> A_IWL<3545> A_IWL<3544> A_IWL<3543> A_IWL<3542> A_IWL<3541> A_IWL<3540> A_IWL<3539> A_IWL<3538> A_IWL<3537> A_IWL<3536> A_IWL<3535> A_IWL<3534> A_IWL<3533> A_IWL<3532> A_IWL<3531> A_IWL<3530> A_IWL<3529> A_IWL<3528> A_IWL<3527> A_IWL<3526> A_IWL<3525> A_IWL<3524> A_IWL<3523> A_IWL<3522> A_IWL<3521> A_IWL<3520> A_IWL<3519> A_IWL<3518> A_IWL<3517> A_IWL<3516> A_IWL<3515> A_IWL<3514> A_IWL<3513> A_IWL<3512> A_IWL<3511> A_IWL<3510> A_IWL<3509> A_IWL<3508> A_IWL<3507> A_IWL<3506> A_IWL<3505> A_IWL<3504> A_IWL<3503> A_IWL<3502> A_IWL<3501> A_IWL<3500> A_IWL<3499> A_IWL<3498> A_IWL<3497> A_IWL<3496> A_IWL<3495> A_IWL<3494> A_IWL<3493> A_IWL<3492> A_IWL<3491> A_IWL<3490> A_IWL<3489> A_IWL<3488> A_IWL<3487> A_IWL<3486> A_IWL<3485> A_IWL<3484> A_IWL<3483> A_IWL<3482> A_IWL<3481> A_IWL<3480> A_IWL<3479> A_IWL<3478> A_IWL<3477> A_IWL<3476> A_IWL<3475> A_IWL<3474> A_IWL<3473> A_IWL<3472> A_IWL<3471> A_IWL<3470> A_IWL<3469> A_IWL<3468> A_IWL<3467> A_IWL<3466> A_IWL<3465> A_IWL<3464> A_IWL<3463> A_IWL<3462> A_IWL<3461> A_IWL<3460> A_IWL<3459> A_IWL<3458> A_IWL<3457> A_IWL<3456> A_IWL<3455> A_IWL<3454> A_IWL<3453> A_IWL<3452> A_IWL<3451> A_IWL<3450> A_IWL<3449> A_IWL<3448> A_IWL<3447> A_IWL<3446> A_IWL<3445> A_IWL<3444> A_IWL<3443> A_IWL<3442> A_IWL<3441> A_IWL<3440> A_IWL<3439> A_IWL<3438> A_IWL<3437> A_IWL<3436> A_IWL<3435> A_IWL<3434> A_IWL<3433> A_IWL<3432> A_IWL<3431> A_IWL<3430> A_IWL<3429> A_IWL<3428> A_IWL<3427> A_IWL<3426> A_IWL<3425> A_IWL<3424> A_IWL<3423> A_IWL<3422> A_IWL<3421> A_IWL<3420> A_IWL<3419> A_IWL<3418> A_IWL<3417> A_IWL<3416> A_IWL<3415> A_IWL<3414> A_IWL<3413> A_IWL<3412> A_IWL<3411> A_IWL<3410> A_IWL<3409> A_IWL<3408> A_IWL<3407> A_IWL<3406> A_IWL<3405> A_IWL<3404> A_IWL<3403> A_IWL<3402> A_IWL<3401> A_IWL<3400> A_IWL<3399> A_IWL<3398> A_IWL<3397> A_IWL<3396> A_IWL<3395> A_IWL<3394> A_IWL<3393> A_IWL<3392> A_IWL<3391> A_IWL<3390> A_IWL<3389> A_IWL<3388> A_IWL<3387> A_IWL<3386> A_IWL<3385> A_IWL<3384> A_IWL<3383> A_IWL<3382> A_IWL<3381> A_IWL<3380> A_IWL<3379> A_IWL<3378> A_IWL<3377> A_IWL<3376> A_IWL<3375> A_IWL<3374> A_IWL<3373> A_IWL<3372> A_IWL<3371> A_IWL<3370> A_IWL<3369> A_IWL<3368> A_IWL<3367> A_IWL<3366> A_IWL<3365> A_IWL<3364> A_IWL<3363> A_IWL<3362> A_IWL<3361> A_IWL<3360> A_IWL<3359> A_IWL<3358> A_IWL<3357> A_IWL<3356> A_IWL<3355> A_IWL<3354> A_IWL<3353> A_IWL<3352> A_IWL<3351> A_IWL<3350> A_IWL<3349> A_IWL<3348> A_IWL<3347> A_IWL<3346> A_IWL<3345> A_IWL<3344> A_IWL<3343> A_IWL<3342> A_IWL<3341> A_IWL<3340> A_IWL<3339> A_IWL<3338> A_IWL<3337> A_IWL<3336> A_IWL<3335> A_IWL<3334> A_IWL<3333> A_IWL<3332> A_IWL<3331> A_IWL<3330> A_IWL<3329> A_IWL<3328> A_IWL<3327> A_IWL<3326> A_IWL<3325> A_IWL<3324> A_IWL<3323> A_IWL<3322> A_IWL<3321> A_IWL<3320> A_IWL<3319> A_IWL<3318> A_IWL<3317> A_IWL<3316> A_IWL<3315> A_IWL<3314> A_IWL<3313> A_IWL<3312> A_IWL<3311> A_IWL<3310> A_IWL<3309> A_IWL<3308> A_IWL<3307> A_IWL<3306> A_IWL<3305> A_IWL<3304> A_IWL<3303> A_IWL<3302> A_IWL<3301> A_IWL<3300> A_IWL<3299> A_IWL<3298> A_IWL<3297> A_IWL<3296> A_IWL<3295> A_IWL<3294> A_IWL<3293> A_IWL<3292> A_IWL<3291> A_IWL<3290> A_IWL<3289> A_IWL<3288> A_IWL<3287> A_IWL<3286> A_IWL<3285> A_IWL<3284> A_IWL<3283> A_IWL<3282> A_IWL<3281> A_IWL<3280> A_IWL<3279> A_IWL<3278> A_IWL<3277> A_IWL<3276> A_IWL<3275> A_IWL<3274> A_IWL<3273> A_IWL<3272> A_IWL<3271> A_IWL<3270> A_IWL<3269> A_IWL<3268> A_IWL<3267> A_IWL<3266> A_IWL<3265> A_IWL<3264> A_IWL<3263> A_IWL<3262> A_IWL<3261> A_IWL<3260> A_IWL<3259> A_IWL<3258> A_IWL<3257> A_IWL<3256> A_IWL<3255> A_IWL<3254> A_IWL<3253> A_IWL<3252> A_IWL<3251> A_IWL<3250> A_IWL<3249> A_IWL<3248> A_IWL<3247> A_IWL<3246> A_IWL<3245> A_IWL<3244> A_IWL<3243> A_IWL<3242> A_IWL<3241> A_IWL<3240> A_IWL<3239> A_IWL<3238> A_IWL<3237> A_IWL<3236> A_IWL<3235> A_IWL<3234> A_IWL<3233> A_IWL<3232> A_IWL<3231> A_IWL<3230> A_IWL<3229> A_IWL<3228> A_IWL<3227> A_IWL<3226> A_IWL<3225> A_IWL<3224> A_IWL<3223> A_IWL<3222> A_IWL<3221> A_IWL<3220> A_IWL<3219> A_IWL<3218> A_IWL<3217> A_IWL<3216> A_IWL<3215> A_IWL<3214> A_IWL<3213> A_IWL<3212> A_IWL<3211> A_IWL<3210> A_IWL<3209> A_IWL<3208> A_IWL<3207> A_IWL<3206> A_IWL<3205> A_IWL<3204> A_IWL<3203> A_IWL<3202> A_IWL<3201> A_IWL<3200> A_IWL<3199> A_IWL<3198> A_IWL<3197> A_IWL<3196> A_IWL<3195> A_IWL<3194> A_IWL<3193> A_IWL<3192> A_IWL<3191> A_IWL<3190> A_IWL<3189> A_IWL<3188> A_IWL<3187> A_IWL<3186> A_IWL<3185> A_IWL<3184> A_IWL<3183> A_IWL<3182> A_IWL<3181> A_IWL<3180> A_IWL<3179> A_IWL<3178> A_IWL<3177> A_IWL<3176> A_IWL<3175> A_IWL<3174> A_IWL<3173> A_IWL<3172> A_IWL<3171> A_IWL<3170> A_IWL<3169> A_IWL<3168> A_IWL<3167> A_IWL<3166> A_IWL<3165> A_IWL<3164> A_IWL<3163> A_IWL<3162> A_IWL<3161> A_IWL<3160> A_IWL<3159> A_IWL<3158> A_IWL<3157> A_IWL<3156> A_IWL<3155> A_IWL<3154> A_IWL<3153> A_IWL<3152> A_IWL<3151> A_IWL<3150> A_IWL<3149> A_IWL<3148> A_IWL<3147> A_IWL<3146> A_IWL<3145> A_IWL<3144> A_IWL<3143> A_IWL<3142> A_IWL<3141> A_IWL<3140> A_IWL<3139> A_IWL<3138> A_IWL<3137> A_IWL<3136> A_IWL<3135> A_IWL<3134> A_IWL<3133> A_IWL<3132> A_IWL<3131> A_IWL<3130> A_IWL<3129> A_IWL<3128> A_IWL<3127> A_IWL<3126> A_IWL<3125> A_IWL<3124> A_IWL<3123> A_IWL<3122> A_IWL<3121> A_IWL<3120> A_IWL<3119> A_IWL<3118> A_IWL<3117> A_IWL<3116> A_IWL<3115> A_IWL<3114> A_IWL<3113> A_IWL<3112> A_IWL<3111> A_IWL<3110> A_IWL<3109> A_IWL<3108> A_IWL<3107> A_IWL<3106> A_IWL<3105> A_IWL<3104> A_IWL<3103> A_IWL<3102> A_IWL<3101> A_IWL<3100> A_IWL<3099> A_IWL<3098> A_IWL<3097> A_IWL<3096> A_IWL<3095> A_IWL<3094> A_IWL<3093> A_IWL<3092> A_IWL<3091> A_IWL<3090> A_IWL<3089> A_IWL<3088> A_IWL<3087> A_IWL<3086> A_IWL<3085> A_IWL<3084> A_IWL<3083> A_IWL<3082> A_IWL<3081> A_IWL<3080> A_IWL<3079> A_IWL<3078> A_IWL<3077> A_IWL<3076> A_IWL<3075> A_IWL<3074> A_IWL<3073> A_IWL<3072> A_IWL<4095> A_IWL<4094> A_IWL<4093> A_IWL<4092> A_IWL<4091> A_IWL<4090> A_IWL<4089> A_IWL<4088> A_IWL<4087> A_IWL<4086> A_IWL<4085> A_IWL<4084> A_IWL<4083> A_IWL<4082> A_IWL<4081> A_IWL<4080> A_IWL<4079> A_IWL<4078> A_IWL<4077> A_IWL<4076> A_IWL<4075> A_IWL<4074> A_IWL<4073> A_IWL<4072> A_IWL<4071> A_IWL<4070> A_IWL<4069> A_IWL<4068> A_IWL<4067> A_IWL<4066> A_IWL<4065> A_IWL<4064> A_IWL<4063> A_IWL<4062> A_IWL<4061> A_IWL<4060> A_IWL<4059> A_IWL<4058> A_IWL<4057> A_IWL<4056> A_IWL<4055> A_IWL<4054> A_IWL<4053> A_IWL<4052> A_IWL<4051> A_IWL<4050> A_IWL<4049> A_IWL<4048> A_IWL<4047> A_IWL<4046> A_IWL<4045> A_IWL<4044> A_IWL<4043> A_IWL<4042> A_IWL<4041> A_IWL<4040> A_IWL<4039> A_IWL<4038> A_IWL<4037> A_IWL<4036> A_IWL<4035> A_IWL<4034> A_IWL<4033> A_IWL<4032> A_IWL<4031> A_IWL<4030> A_IWL<4029> A_IWL<4028> A_IWL<4027> A_IWL<4026> A_IWL<4025> A_IWL<4024> A_IWL<4023> A_IWL<4022> A_IWL<4021> A_IWL<4020> A_IWL<4019> A_IWL<4018> A_IWL<4017> A_IWL<4016> A_IWL<4015> A_IWL<4014> A_IWL<4013> A_IWL<4012> A_IWL<4011> A_IWL<4010> A_IWL<4009> A_IWL<4008> A_IWL<4007> A_IWL<4006> A_IWL<4005> A_IWL<4004> A_IWL<4003> A_IWL<4002> A_IWL<4001> A_IWL<4000> A_IWL<3999> A_IWL<3998> A_IWL<3997> A_IWL<3996> A_IWL<3995> A_IWL<3994> A_IWL<3993> A_IWL<3992> A_IWL<3991> A_IWL<3990> A_IWL<3989> A_IWL<3988> A_IWL<3987> A_IWL<3986> A_IWL<3985> A_IWL<3984> A_IWL<3983> A_IWL<3982> A_IWL<3981> A_IWL<3980> A_IWL<3979> A_IWL<3978> A_IWL<3977> A_IWL<3976> A_IWL<3975> A_IWL<3974> A_IWL<3973> A_IWL<3972> A_IWL<3971> A_IWL<3970> A_IWL<3969> A_IWL<3968> A_IWL<3967> A_IWL<3966> A_IWL<3965> A_IWL<3964> A_IWL<3963> A_IWL<3962> A_IWL<3961> A_IWL<3960> A_IWL<3959> A_IWL<3958> A_IWL<3957> A_IWL<3956> A_IWL<3955> A_IWL<3954> A_IWL<3953> A_IWL<3952> A_IWL<3951> A_IWL<3950> A_IWL<3949> A_IWL<3948> A_IWL<3947> A_IWL<3946> A_IWL<3945> A_IWL<3944> A_IWL<3943> A_IWL<3942> A_IWL<3941> A_IWL<3940> A_IWL<3939> A_IWL<3938> A_IWL<3937> A_IWL<3936> A_IWL<3935> A_IWL<3934> A_IWL<3933> A_IWL<3932> A_IWL<3931> A_IWL<3930> A_IWL<3929> A_IWL<3928> A_IWL<3927> A_IWL<3926> A_IWL<3925> A_IWL<3924> A_IWL<3923> A_IWL<3922> A_IWL<3921> A_IWL<3920> A_IWL<3919> A_IWL<3918> A_IWL<3917> A_IWL<3916> A_IWL<3915> A_IWL<3914> A_IWL<3913> A_IWL<3912> A_IWL<3911> A_IWL<3910> A_IWL<3909> A_IWL<3908> A_IWL<3907> A_IWL<3906> A_IWL<3905> A_IWL<3904> A_IWL<3903> A_IWL<3902> A_IWL<3901> A_IWL<3900> A_IWL<3899> A_IWL<3898> A_IWL<3897> A_IWL<3896> A_IWL<3895> A_IWL<3894> A_IWL<3893> A_IWL<3892> A_IWL<3891> A_IWL<3890> A_IWL<3889> A_IWL<3888> A_IWL<3887> A_IWL<3886> A_IWL<3885> A_IWL<3884> A_IWL<3883> A_IWL<3882> A_IWL<3881> A_IWL<3880> A_IWL<3879> A_IWL<3878> A_IWL<3877> A_IWL<3876> A_IWL<3875> A_IWL<3874> A_IWL<3873> A_IWL<3872> A_IWL<3871> A_IWL<3870> A_IWL<3869> A_IWL<3868> A_IWL<3867> A_IWL<3866> A_IWL<3865> A_IWL<3864> A_IWL<3863> A_IWL<3862> A_IWL<3861> A_IWL<3860> A_IWL<3859> A_IWL<3858> A_IWL<3857> A_IWL<3856> A_IWL<3855> A_IWL<3854> A_IWL<3853> A_IWL<3852> A_IWL<3851> A_IWL<3850> A_IWL<3849> A_IWL<3848> A_IWL<3847> A_IWL<3846> A_IWL<3845> A_IWL<3844> A_IWL<3843> A_IWL<3842> A_IWL<3841> A_IWL<3840> A_IWL<3839> A_IWL<3838> A_IWL<3837> A_IWL<3836> A_IWL<3835> A_IWL<3834> A_IWL<3833> A_IWL<3832> A_IWL<3831> A_IWL<3830> A_IWL<3829> A_IWL<3828> A_IWL<3827> A_IWL<3826> A_IWL<3825> A_IWL<3824> A_IWL<3823> A_IWL<3822> A_IWL<3821> A_IWL<3820> A_IWL<3819> A_IWL<3818> A_IWL<3817> A_IWL<3816> A_IWL<3815> A_IWL<3814> A_IWL<3813> A_IWL<3812> A_IWL<3811> A_IWL<3810> A_IWL<3809> A_IWL<3808> A_IWL<3807> A_IWL<3806> A_IWL<3805> A_IWL<3804> A_IWL<3803> A_IWL<3802> A_IWL<3801> A_IWL<3800> A_IWL<3799> A_IWL<3798> A_IWL<3797> A_IWL<3796> A_IWL<3795> A_IWL<3794> A_IWL<3793> A_IWL<3792> A_IWL<3791> A_IWL<3790> A_IWL<3789> A_IWL<3788> A_IWL<3787> A_IWL<3786> A_IWL<3785> A_IWL<3784> A_IWL<3783> A_IWL<3782> A_IWL<3781> A_IWL<3780> A_IWL<3779> A_IWL<3778> A_IWL<3777> A_IWL<3776> A_IWL<3775> A_IWL<3774> A_IWL<3773> A_IWL<3772> A_IWL<3771> A_IWL<3770> A_IWL<3769> A_IWL<3768> A_IWL<3767> A_IWL<3766> A_IWL<3765> A_IWL<3764> A_IWL<3763> A_IWL<3762> A_IWL<3761> A_IWL<3760> A_IWL<3759> A_IWL<3758> A_IWL<3757> A_IWL<3756> A_IWL<3755> A_IWL<3754> A_IWL<3753> A_IWL<3752> A_IWL<3751> A_IWL<3750> A_IWL<3749> A_IWL<3748> A_IWL<3747> A_IWL<3746> A_IWL<3745> A_IWL<3744> A_IWL<3743> A_IWL<3742> A_IWL<3741> A_IWL<3740> A_IWL<3739> A_IWL<3738> A_IWL<3737> A_IWL<3736> A_IWL<3735> A_IWL<3734> A_IWL<3733> A_IWL<3732> A_IWL<3731> A_IWL<3730> A_IWL<3729> A_IWL<3728> A_IWL<3727> A_IWL<3726> A_IWL<3725> A_IWL<3724> A_IWL<3723> A_IWL<3722> A_IWL<3721> A_IWL<3720> A_IWL<3719> A_IWL<3718> A_IWL<3717> A_IWL<3716> A_IWL<3715> A_IWL<3714> A_IWL<3713> A_IWL<3712> A_IWL<3711> A_IWL<3710> A_IWL<3709> A_IWL<3708> A_IWL<3707> A_IWL<3706> A_IWL<3705> A_IWL<3704> A_IWL<3703> A_IWL<3702> A_IWL<3701> A_IWL<3700> A_IWL<3699> A_IWL<3698> A_IWL<3697> A_IWL<3696> A_IWL<3695> A_IWL<3694> A_IWL<3693> A_IWL<3692> A_IWL<3691> A_IWL<3690> A_IWL<3689> A_IWL<3688> A_IWL<3687> A_IWL<3686> A_IWL<3685> A_IWL<3684> A_IWL<3683> A_IWL<3682> A_IWL<3681> A_IWL<3680> A_IWL<3679> A_IWL<3678> A_IWL<3677> A_IWL<3676> A_IWL<3675> A_IWL<3674> A_IWL<3673> A_IWL<3672> A_IWL<3671> A_IWL<3670> A_IWL<3669> A_IWL<3668> A_IWL<3667> A_IWL<3666> A_IWL<3665> A_IWL<3664> A_IWL<3663> A_IWL<3662> A_IWL<3661> A_IWL<3660> A_IWL<3659> A_IWL<3658> A_IWL<3657> A_IWL<3656> A_IWL<3655> A_IWL<3654> A_IWL<3653> A_IWL<3652> A_IWL<3651> A_IWL<3650> A_IWL<3649> A_IWL<3648> A_IWL<3647> A_IWL<3646> A_IWL<3645> A_IWL<3644> A_IWL<3643> A_IWL<3642> A_IWL<3641> A_IWL<3640> A_IWL<3639> A_IWL<3638> A_IWL<3637> A_IWL<3636> A_IWL<3635> A_IWL<3634> A_IWL<3633> A_IWL<3632> A_IWL<3631> A_IWL<3630> A_IWL<3629> A_IWL<3628> A_IWL<3627> A_IWL<3626> A_IWL<3625> A_IWL<3624> A_IWL<3623> A_IWL<3622> A_IWL<3621> A_IWL<3620> A_IWL<3619> A_IWL<3618> A_IWL<3617> A_IWL<3616> A_IWL<3615> A_IWL<3614> A_IWL<3613> A_IWL<3612> A_IWL<3611> A_IWL<3610> A_IWL<3609> A_IWL<3608> A_IWL<3607> A_IWL<3606> A_IWL<3605> A_IWL<3604> A_IWL<3603> A_IWL<3602> A_IWL<3601> A_IWL<3600> A_IWL<3599> A_IWL<3598> A_IWL<3597> A_IWL<3596> A_IWL<3595> A_IWL<3594> A_IWL<3593> A_IWL<3592> A_IWL<3591> A_IWL<3590> A_IWL<3589> A_IWL<3588> A_IWL<3587> A_IWL<3586> A_IWL<3585> A_IWL<3584> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_COLUMN_pcell_0 +XCOL<6> A_BLC<13> A_BLC<12> A_BLC_TOP<13> A_BLC_TOP<12> A_BLT<13> A_BLT<12> A_BLT_TOP<13> A_BLT_TOP<12> A_IWL<3071> A_IWL<3070> A_IWL<3069> A_IWL<3068> A_IWL<3067> A_IWL<3066> A_IWL<3065> A_IWL<3064> A_IWL<3063> A_IWL<3062> A_IWL<3061> A_IWL<3060> A_IWL<3059> A_IWL<3058> A_IWL<3057> A_IWL<3056> A_IWL<3055> A_IWL<3054> A_IWL<3053> A_IWL<3052> A_IWL<3051> A_IWL<3050> A_IWL<3049> A_IWL<3048> A_IWL<3047> A_IWL<3046> A_IWL<3045> A_IWL<3044> A_IWL<3043> A_IWL<3042> A_IWL<3041> A_IWL<3040> A_IWL<3039> A_IWL<3038> A_IWL<3037> A_IWL<3036> A_IWL<3035> A_IWL<3034> A_IWL<3033> A_IWL<3032> A_IWL<3031> A_IWL<3030> A_IWL<3029> A_IWL<3028> A_IWL<3027> A_IWL<3026> A_IWL<3025> A_IWL<3024> A_IWL<3023> A_IWL<3022> A_IWL<3021> A_IWL<3020> A_IWL<3019> A_IWL<3018> A_IWL<3017> A_IWL<3016> A_IWL<3015> A_IWL<3014> A_IWL<3013> A_IWL<3012> A_IWL<3011> A_IWL<3010> A_IWL<3009> A_IWL<3008> A_IWL<3007> A_IWL<3006> A_IWL<3005> A_IWL<3004> A_IWL<3003> A_IWL<3002> A_IWL<3001> A_IWL<3000> A_IWL<2999> A_IWL<2998> A_IWL<2997> A_IWL<2996> A_IWL<2995> A_IWL<2994> A_IWL<2993> A_IWL<2992> A_IWL<2991> A_IWL<2990> A_IWL<2989> A_IWL<2988> A_IWL<2987> A_IWL<2986> A_IWL<2985> A_IWL<2984> A_IWL<2983> A_IWL<2982> A_IWL<2981> A_IWL<2980> A_IWL<2979> A_IWL<2978> A_IWL<2977> A_IWL<2976> A_IWL<2975> A_IWL<2974> A_IWL<2973> A_IWL<2972> A_IWL<2971> A_IWL<2970> A_IWL<2969> A_IWL<2968> A_IWL<2967> A_IWL<2966> A_IWL<2965> A_IWL<2964> A_IWL<2963> A_IWL<2962> A_IWL<2961> A_IWL<2960> A_IWL<2959> A_IWL<2958> A_IWL<2957> A_IWL<2956> A_IWL<2955> A_IWL<2954> A_IWL<2953> A_IWL<2952> A_IWL<2951> A_IWL<2950> A_IWL<2949> A_IWL<2948> A_IWL<2947> A_IWL<2946> A_IWL<2945> A_IWL<2944> A_IWL<2943> A_IWL<2942> A_IWL<2941> A_IWL<2940> A_IWL<2939> A_IWL<2938> A_IWL<2937> A_IWL<2936> A_IWL<2935> A_IWL<2934> A_IWL<2933> A_IWL<2932> A_IWL<2931> A_IWL<2930> A_IWL<2929> A_IWL<2928> A_IWL<2927> A_IWL<2926> A_IWL<2925> A_IWL<2924> A_IWL<2923> A_IWL<2922> A_IWL<2921> A_IWL<2920> A_IWL<2919> A_IWL<2918> A_IWL<2917> A_IWL<2916> A_IWL<2915> A_IWL<2914> A_IWL<2913> A_IWL<2912> A_IWL<2911> A_IWL<2910> A_IWL<2909> A_IWL<2908> A_IWL<2907> A_IWL<2906> A_IWL<2905> A_IWL<2904> A_IWL<2903> A_IWL<2902> A_IWL<2901> A_IWL<2900> A_IWL<2899> A_IWL<2898> A_IWL<2897> A_IWL<2896> A_IWL<2895> A_IWL<2894> A_IWL<2893> A_IWL<2892> A_IWL<2891> A_IWL<2890> A_IWL<2889> A_IWL<2888> A_IWL<2887> A_IWL<2886> A_IWL<2885> A_IWL<2884> A_IWL<2883> A_IWL<2882> A_IWL<2881> A_IWL<2880> A_IWL<2879> A_IWL<2878> A_IWL<2877> A_IWL<2876> A_IWL<2875> A_IWL<2874> A_IWL<2873> A_IWL<2872> A_IWL<2871> A_IWL<2870> A_IWL<2869> A_IWL<2868> A_IWL<2867> A_IWL<2866> A_IWL<2865> A_IWL<2864> A_IWL<2863> A_IWL<2862> A_IWL<2861> A_IWL<2860> A_IWL<2859> A_IWL<2858> A_IWL<2857> A_IWL<2856> A_IWL<2855> A_IWL<2854> A_IWL<2853> A_IWL<2852> A_IWL<2851> A_IWL<2850> A_IWL<2849> A_IWL<2848> A_IWL<2847> A_IWL<2846> A_IWL<2845> A_IWL<2844> A_IWL<2843> A_IWL<2842> A_IWL<2841> A_IWL<2840> A_IWL<2839> A_IWL<2838> A_IWL<2837> A_IWL<2836> A_IWL<2835> A_IWL<2834> A_IWL<2833> A_IWL<2832> A_IWL<2831> A_IWL<2830> A_IWL<2829> A_IWL<2828> A_IWL<2827> A_IWL<2826> A_IWL<2825> A_IWL<2824> A_IWL<2823> A_IWL<2822> A_IWL<2821> A_IWL<2820> A_IWL<2819> A_IWL<2818> A_IWL<2817> A_IWL<2816> A_IWL<2815> A_IWL<2814> A_IWL<2813> A_IWL<2812> A_IWL<2811> A_IWL<2810> A_IWL<2809> A_IWL<2808> A_IWL<2807> A_IWL<2806> A_IWL<2805> A_IWL<2804> A_IWL<2803> A_IWL<2802> A_IWL<2801> A_IWL<2800> A_IWL<2799> A_IWL<2798> A_IWL<2797> A_IWL<2796> A_IWL<2795> A_IWL<2794> A_IWL<2793> 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A_IWL<2709> A_IWL<2708> A_IWL<2707> A_IWL<2706> A_IWL<2705> A_IWL<2704> A_IWL<2703> A_IWL<2702> A_IWL<2701> A_IWL<2700> A_IWL<2699> A_IWL<2698> A_IWL<2697> A_IWL<2696> A_IWL<2695> A_IWL<2694> A_IWL<2693> A_IWL<2692> A_IWL<2691> A_IWL<2690> A_IWL<2689> A_IWL<2688> A_IWL<2687> A_IWL<2686> A_IWL<2685> A_IWL<2684> A_IWL<2683> A_IWL<2682> A_IWL<2681> A_IWL<2680> A_IWL<2679> A_IWL<2678> A_IWL<2677> A_IWL<2676> A_IWL<2675> A_IWL<2674> A_IWL<2673> A_IWL<2672> A_IWL<2671> A_IWL<2670> A_IWL<2669> A_IWL<2668> A_IWL<2667> A_IWL<2666> A_IWL<2665> A_IWL<2664> A_IWL<2663> A_IWL<2662> A_IWL<2661> A_IWL<2660> A_IWL<2659> A_IWL<2658> A_IWL<2657> A_IWL<2656> A_IWL<2655> A_IWL<2654> A_IWL<2653> A_IWL<2652> A_IWL<2651> A_IWL<2650> A_IWL<2649> A_IWL<2648> A_IWL<2647> A_IWL<2646> A_IWL<2645> A_IWL<2644> A_IWL<2643> A_IWL<2642> A_IWL<2641> A_IWL<2640> A_IWL<2639> A_IWL<2638> A_IWL<2637> A_IWL<2636> A_IWL<2635> A_IWL<2634> A_IWL<2633> A_IWL<2632> A_IWL<2631> A_IWL<2630> A_IWL<2629> A_IWL<2628> A_IWL<2627> A_IWL<2626> A_IWL<2625> A_IWL<2624> A_IWL<2623> A_IWL<2622> A_IWL<2621> A_IWL<2620> A_IWL<2619> A_IWL<2618> A_IWL<2617> A_IWL<2616> A_IWL<2615> A_IWL<2614> A_IWL<2613> A_IWL<2612> A_IWL<2611> A_IWL<2610> A_IWL<2609> A_IWL<2608> A_IWL<2607> A_IWL<2606> A_IWL<2605> A_IWL<2604> A_IWL<2603> A_IWL<2602> A_IWL<2601> A_IWL<2600> A_IWL<2599> A_IWL<2598> A_IWL<2597> A_IWL<2596> A_IWL<2595> A_IWL<2594> A_IWL<2593> A_IWL<2592> A_IWL<2591> A_IWL<2590> A_IWL<2589> A_IWL<2588> A_IWL<2587> A_IWL<2586> A_IWL<2585> A_IWL<2584> A_IWL<2583> A_IWL<2582> A_IWL<2581> A_IWL<2580> A_IWL<2579> A_IWL<2578> A_IWL<2577> A_IWL<2576> A_IWL<2575> A_IWL<2574> A_IWL<2573> A_IWL<2572> A_IWL<2571> A_IWL<2570> A_IWL<2569> A_IWL<2568> A_IWL<2567> A_IWL<2566> A_IWL<2565> A_IWL<2564> A_IWL<2563> A_IWL<2562> A_IWL<2561> A_IWL<2560> A_IWL<3583> A_IWL<3582> A_IWL<3581> A_IWL<3580> A_IWL<3579> A_IWL<3578> A_IWL<3577> A_IWL<3576> A_IWL<3575> A_IWL<3574> A_IWL<3573> A_IWL<3572> A_IWL<3571> A_IWL<3570> A_IWL<3569> A_IWL<3568> A_IWL<3567> A_IWL<3566> A_IWL<3565> A_IWL<3564> A_IWL<3563> A_IWL<3562> A_IWL<3561> A_IWL<3560> A_IWL<3559> A_IWL<3558> A_IWL<3557> A_IWL<3556> A_IWL<3555> A_IWL<3554> A_IWL<3553> A_IWL<3552> A_IWL<3551> A_IWL<3550> A_IWL<3549> A_IWL<3548> A_IWL<3547> A_IWL<3546> A_IWL<3545> A_IWL<3544> A_IWL<3543> A_IWL<3542> A_IWL<3541> A_IWL<3540> A_IWL<3539> A_IWL<3538> A_IWL<3537> A_IWL<3536> A_IWL<3535> A_IWL<3534> A_IWL<3533> A_IWL<3532> A_IWL<3531> A_IWL<3530> A_IWL<3529> A_IWL<3528> A_IWL<3527> A_IWL<3526> A_IWL<3525> A_IWL<3524> A_IWL<3523> A_IWL<3522> A_IWL<3521> A_IWL<3520> A_IWL<3519> A_IWL<3518> A_IWL<3517> A_IWL<3516> A_IWL<3515> A_IWL<3514> A_IWL<3513> A_IWL<3512> A_IWL<3511> A_IWL<3510> A_IWL<3509> A_IWL<3508> A_IWL<3507> A_IWL<3506> A_IWL<3505> A_IWL<3504> A_IWL<3503> A_IWL<3502> A_IWL<3501> A_IWL<3500> A_IWL<3499> A_IWL<3498> A_IWL<3497> A_IWL<3496> A_IWL<3495> A_IWL<3494> A_IWL<3493> A_IWL<3492> A_IWL<3491> A_IWL<3490> A_IWL<3489> A_IWL<3488> A_IWL<3487> A_IWL<3486> A_IWL<3485> A_IWL<3484> A_IWL<3483> A_IWL<3482> A_IWL<3481> A_IWL<3480> A_IWL<3479> A_IWL<3478> A_IWL<3477> A_IWL<3476> A_IWL<3475> A_IWL<3474> A_IWL<3473> A_IWL<3472> A_IWL<3471> A_IWL<3470> A_IWL<3469> A_IWL<3468> A_IWL<3467> A_IWL<3466> A_IWL<3465> A_IWL<3464> A_IWL<3463> A_IWL<3462> A_IWL<3461> A_IWL<3460> A_IWL<3459> A_IWL<3458> A_IWL<3457> A_IWL<3456> A_IWL<3455> A_IWL<3454> A_IWL<3453> A_IWL<3452> A_IWL<3451> A_IWL<3450> A_IWL<3449> A_IWL<3448> A_IWL<3447> A_IWL<3446> A_IWL<3445> A_IWL<3444> A_IWL<3443> A_IWL<3442> A_IWL<3441> A_IWL<3440> A_IWL<3439> A_IWL<3438> A_IWL<3437> A_IWL<3436> A_IWL<3435> A_IWL<3434> A_IWL<3433> A_IWL<3432> A_IWL<3431> A_IWL<3430> A_IWL<3429> A_IWL<3428> A_IWL<3427> A_IWL<3426> A_IWL<3425> A_IWL<3424> A_IWL<3423> A_IWL<3422> A_IWL<3421> A_IWL<3420> A_IWL<3419> A_IWL<3418> A_IWL<3417> A_IWL<3416> A_IWL<3415> A_IWL<3414> A_IWL<3413> A_IWL<3412> A_IWL<3411> A_IWL<3410> A_IWL<3409> A_IWL<3408> A_IWL<3407> A_IWL<3406> A_IWL<3405> A_IWL<3404> A_IWL<3403> A_IWL<3402> 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A_IWL<3318> A_IWL<3317> A_IWL<3316> A_IWL<3315> A_IWL<3314> A_IWL<3313> A_IWL<3312> A_IWL<3311> A_IWL<3310> A_IWL<3309> A_IWL<3308> A_IWL<3307> A_IWL<3306> A_IWL<3305> A_IWL<3304> A_IWL<3303> A_IWL<3302> A_IWL<3301> A_IWL<3300> A_IWL<3299> A_IWL<3298> A_IWL<3297> A_IWL<3296> A_IWL<3295> A_IWL<3294> A_IWL<3293> A_IWL<3292> A_IWL<3291> A_IWL<3290> A_IWL<3289> A_IWL<3288> A_IWL<3287> A_IWL<3286> A_IWL<3285> A_IWL<3284> A_IWL<3283> A_IWL<3282> A_IWL<3281> A_IWL<3280> A_IWL<3279> A_IWL<3278> A_IWL<3277> A_IWL<3276> A_IWL<3275> A_IWL<3274> A_IWL<3273> A_IWL<3272> A_IWL<3271> A_IWL<3270> A_IWL<3269> A_IWL<3268> A_IWL<3267> A_IWL<3266> A_IWL<3265> A_IWL<3264> A_IWL<3263> A_IWL<3262> A_IWL<3261> A_IWL<3260> A_IWL<3259> A_IWL<3258> A_IWL<3257> A_IWL<3256> A_IWL<3255> A_IWL<3254> A_IWL<3253> A_IWL<3252> A_IWL<3251> A_IWL<3250> A_IWL<3249> A_IWL<3248> A_IWL<3247> A_IWL<3246> A_IWL<3245> A_IWL<3244> A_IWL<3243> A_IWL<3242> A_IWL<3241> A_IWL<3240> A_IWL<3239> A_IWL<3238> A_IWL<3237> A_IWL<3236> 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A_IWL<3152> A_IWL<3151> A_IWL<3150> A_IWL<3149> A_IWL<3148> A_IWL<3147> A_IWL<3146> A_IWL<3145> A_IWL<3144> A_IWL<3143> A_IWL<3142> A_IWL<3141> A_IWL<3140> A_IWL<3139> A_IWL<3138> A_IWL<3137> A_IWL<3136> A_IWL<3135> A_IWL<3134> A_IWL<3133> A_IWL<3132> A_IWL<3131> A_IWL<3130> A_IWL<3129> A_IWL<3128> A_IWL<3127> A_IWL<3126> A_IWL<3125> A_IWL<3124> A_IWL<3123> A_IWL<3122> A_IWL<3121> A_IWL<3120> A_IWL<3119> A_IWL<3118> A_IWL<3117> A_IWL<3116> A_IWL<3115> A_IWL<3114> A_IWL<3113> A_IWL<3112> A_IWL<3111> A_IWL<3110> A_IWL<3109> A_IWL<3108> A_IWL<3107> A_IWL<3106> A_IWL<3105> A_IWL<3104> A_IWL<3103> A_IWL<3102> A_IWL<3101> A_IWL<3100> A_IWL<3099> A_IWL<3098> A_IWL<3097> A_IWL<3096> A_IWL<3095> A_IWL<3094> A_IWL<3093> A_IWL<3092> A_IWL<3091> A_IWL<3090> A_IWL<3089> A_IWL<3088> A_IWL<3087> A_IWL<3086> A_IWL<3085> A_IWL<3084> A_IWL<3083> A_IWL<3082> A_IWL<3081> A_IWL<3080> A_IWL<3079> A_IWL<3078> A_IWL<3077> A_IWL<3076> A_IWL<3075> A_IWL<3074> A_IWL<3073> A_IWL<3072> VDD_CORE VSS / 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A_IWL<2488> A_IWL<2487> A_IWL<2486> A_IWL<2485> A_IWL<2484> A_IWL<2483> A_IWL<2482> A_IWL<2481> A_IWL<2480> A_IWL<2479> A_IWL<2478> A_IWL<2477> A_IWL<2476> A_IWL<2475> A_IWL<2474> A_IWL<2473> A_IWL<2472> A_IWL<2471> A_IWL<2470> A_IWL<2469> A_IWL<2468> A_IWL<2467> A_IWL<2466> A_IWL<2465> A_IWL<2464> A_IWL<2463> A_IWL<2462> A_IWL<2461> A_IWL<2460> A_IWL<2459> A_IWL<2458> A_IWL<2457> A_IWL<2456> A_IWL<2455> A_IWL<2454> A_IWL<2453> A_IWL<2452> A_IWL<2451> A_IWL<2450> A_IWL<2449> A_IWL<2448> A_IWL<2447> A_IWL<2446> A_IWL<2445> A_IWL<2444> A_IWL<2443> A_IWL<2442> A_IWL<2441> A_IWL<2440> A_IWL<2439> A_IWL<2438> A_IWL<2437> A_IWL<2436> A_IWL<2435> A_IWL<2434> A_IWL<2433> A_IWL<2432> A_IWL<2431> A_IWL<2430> A_IWL<2429> A_IWL<2428> A_IWL<2427> A_IWL<2426> A_IWL<2425> A_IWL<2424> A_IWL<2423> A_IWL<2422> A_IWL<2421> A_IWL<2420> A_IWL<2419> A_IWL<2418> A_IWL<2417> A_IWL<2416> A_IWL<2415> A_IWL<2414> A_IWL<2413> A_IWL<2412> A_IWL<2411> A_IWL<2410> A_IWL<2409> A_IWL<2408> A_IWL<2407> A_IWL<2406> A_IWL<2405> A_IWL<2404> A_IWL<2403> A_IWL<2402> A_IWL<2401> A_IWL<2400> A_IWL<2399> A_IWL<2398> A_IWL<2397> A_IWL<2396> A_IWL<2395> A_IWL<2394> A_IWL<2393> A_IWL<2392> A_IWL<2391> A_IWL<2390> A_IWL<2389> A_IWL<2388> A_IWL<2387> A_IWL<2386> A_IWL<2385> A_IWL<2384> A_IWL<2383> A_IWL<2382> A_IWL<2381> A_IWL<2380> A_IWL<2379> A_IWL<2378> A_IWL<2377> A_IWL<2376> A_IWL<2375> A_IWL<2374> A_IWL<2373> A_IWL<2372> A_IWL<2371> A_IWL<2370> A_IWL<2369> A_IWL<2368> A_IWL<2367> A_IWL<2366> A_IWL<2365> A_IWL<2364> A_IWL<2363> A_IWL<2362> A_IWL<2361> A_IWL<2360> A_IWL<2359> A_IWL<2358> A_IWL<2357> A_IWL<2356> A_IWL<2355> A_IWL<2354> A_IWL<2353> A_IWL<2352> A_IWL<2351> A_IWL<2350> A_IWL<2349> A_IWL<2348> A_IWL<2347> A_IWL<2346> A_IWL<2345> A_IWL<2344> A_IWL<2343> A_IWL<2342> A_IWL<2341> A_IWL<2340> A_IWL<2339> A_IWL<2338> A_IWL<2337> A_IWL<2336> A_IWL<2335> A_IWL<2334> A_IWL<2333> A_IWL<2332> A_IWL<2331> A_IWL<2330> A_IWL<2329> A_IWL<2328> A_IWL<2327> A_IWL<2326> A_IWL<2325> A_IWL<2324> A_IWL<2323> A_IWL<2322> A_IWL<2321> A_IWL<2320> A_IWL<2319> A_IWL<2318> A_IWL<2317> A_IWL<2316> A_IWL<2315> A_IWL<2314> A_IWL<2313> A_IWL<2312> A_IWL<2311> A_IWL<2310> A_IWL<2309> A_IWL<2308> A_IWL<2307> A_IWL<2306> A_IWL<2305> A_IWL<2304> A_IWL<2303> A_IWL<2302> A_IWL<2301> A_IWL<2300> A_IWL<2299> A_IWL<2298> A_IWL<2297> A_IWL<2296> A_IWL<2295> A_IWL<2294> A_IWL<2293> A_IWL<2292> A_IWL<2291> A_IWL<2290> A_IWL<2289> A_IWL<2288> A_IWL<2287> A_IWL<2286> A_IWL<2285> A_IWL<2284> A_IWL<2283> A_IWL<2282> A_IWL<2281> A_IWL<2280> A_IWL<2279> A_IWL<2278> A_IWL<2277> A_IWL<2276> A_IWL<2275> A_IWL<2274> A_IWL<2273> A_IWL<2272> A_IWL<2271> A_IWL<2270> A_IWL<2269> A_IWL<2268> A_IWL<2267> A_IWL<2266> A_IWL<2265> A_IWL<2264> A_IWL<2263> A_IWL<2262> A_IWL<2261> A_IWL<2260> A_IWL<2259> A_IWL<2258> A_IWL<2257> A_IWL<2256> A_IWL<2255> A_IWL<2254> A_IWL<2253> A_IWL<2252> A_IWL<2251> A_IWL<2250> A_IWL<2249> A_IWL<2248> A_IWL<2247> A_IWL<2246> A_IWL<2245> A_IWL<2244> A_IWL<2243> A_IWL<2242> A_IWL<2241> A_IWL<2240> A_IWL<2239> A_IWL<2238> A_IWL<2237> A_IWL<2236> A_IWL<2235> A_IWL<2234> A_IWL<2233> A_IWL<2232> A_IWL<2231> A_IWL<2230> A_IWL<2229> A_IWL<2228> A_IWL<2227> A_IWL<2226> A_IWL<2225> A_IWL<2224> A_IWL<2223> A_IWL<2222> A_IWL<2221> A_IWL<2220> A_IWL<2219> A_IWL<2218> A_IWL<2217> A_IWL<2216> A_IWL<2215> A_IWL<2214> A_IWL<2213> A_IWL<2212> A_IWL<2211> A_IWL<2210> A_IWL<2209> A_IWL<2208> A_IWL<2207> A_IWL<2206> A_IWL<2205> A_IWL<2204> A_IWL<2203> A_IWL<2202> A_IWL<2201> A_IWL<2200> A_IWL<2199> A_IWL<2198> A_IWL<2197> A_IWL<2196> A_IWL<2195> A_IWL<2194> A_IWL<2193> A_IWL<2192> A_IWL<2191> A_IWL<2190> A_IWL<2189> A_IWL<2188> A_IWL<2187> A_IWL<2186> A_IWL<2185> A_IWL<2184> A_IWL<2183> A_IWL<2182> A_IWL<2181> A_IWL<2180> A_IWL<2179> A_IWL<2178> A_IWL<2177> A_IWL<2176> A_IWL<2175> A_IWL<2174> A_IWL<2173> A_IWL<2172> A_IWL<2171> A_IWL<2170> A_IWL<2169> A_IWL<2168> A_IWL<2167> A_IWL<2166> A_IWL<2165> A_IWL<2164> A_IWL<2163> A_IWL<2162> A_IWL<2161> A_IWL<2160> A_IWL<2159> A_IWL<2158> A_IWL<2157> A_IWL<2156> A_IWL<2155> A_IWL<2154> A_IWL<2153> A_IWL<2152> A_IWL<2151> A_IWL<2150> A_IWL<2149> A_IWL<2148> A_IWL<2147> A_IWL<2146> A_IWL<2145> A_IWL<2144> A_IWL<2143> A_IWL<2142> A_IWL<2141> A_IWL<2140> A_IWL<2139> A_IWL<2138> A_IWL<2137> A_IWL<2136> A_IWL<2135> A_IWL<2134> A_IWL<2133> A_IWL<2132> A_IWL<2131> A_IWL<2130> A_IWL<2129> A_IWL<2128> A_IWL<2127> A_IWL<2126> A_IWL<2125> A_IWL<2124> A_IWL<2123> A_IWL<2122> A_IWL<2121> A_IWL<2120> A_IWL<2119> A_IWL<2118> A_IWL<2117> A_IWL<2116> A_IWL<2115> A_IWL<2114> A_IWL<2113> A_IWL<2112> A_IWL<2111> A_IWL<2110> A_IWL<2109> A_IWL<2108> A_IWL<2107> A_IWL<2106> A_IWL<2105> A_IWL<2104> A_IWL<2103> A_IWL<2102> A_IWL<2101> A_IWL<2100> A_IWL<2099> A_IWL<2098> A_IWL<2097> A_IWL<2096> A_IWL<2095> A_IWL<2094> A_IWL<2093> A_IWL<2092> A_IWL<2091> A_IWL<2090> A_IWL<2089> A_IWL<2088> A_IWL<2087> A_IWL<2086> A_IWL<2085> A_IWL<2084> A_IWL<2083> A_IWL<2082> A_IWL<2081> A_IWL<2080> A_IWL<2079> A_IWL<2078> A_IWL<2077> A_IWL<2076> A_IWL<2075> A_IWL<2074> A_IWL<2073> A_IWL<2072> A_IWL<2071> A_IWL<2070> A_IWL<2069> A_IWL<2068> A_IWL<2067> A_IWL<2066> A_IWL<2065> A_IWL<2064> A_IWL<2063> A_IWL<2062> A_IWL<2061> A_IWL<2060> A_IWL<2059> A_IWL<2058> A_IWL<2057> A_IWL<2056> A_IWL<2055> A_IWL<2054> A_IWL<2053> A_IWL<2052> A_IWL<2051> A_IWL<2050> A_IWL<2049> A_IWL<2048> A_IWL<3071> A_IWL<3070> A_IWL<3069> A_IWL<3068> A_IWL<3067> A_IWL<3066> A_IWL<3065> A_IWL<3064> A_IWL<3063> A_IWL<3062> A_IWL<3061> A_IWL<3060> A_IWL<3059> A_IWL<3058> A_IWL<3057> A_IWL<3056> A_IWL<3055> A_IWL<3054> A_IWL<3053> A_IWL<3052> A_IWL<3051> A_IWL<3050> A_IWL<3049> A_IWL<3048> A_IWL<3047> A_IWL<3046> A_IWL<3045> A_IWL<3044> A_IWL<3043> A_IWL<3042> A_IWL<3041> A_IWL<3040> A_IWL<3039> A_IWL<3038> A_IWL<3037> A_IWL<3036> A_IWL<3035> A_IWL<3034> A_IWL<3033> A_IWL<3032> A_IWL<3031> A_IWL<3030> A_IWL<3029> A_IWL<3028> A_IWL<3027> A_IWL<3026> A_IWL<3025> A_IWL<3024> A_IWL<3023> A_IWL<3022> A_IWL<3021> A_IWL<3020> A_IWL<3019> A_IWL<3018> A_IWL<3017> A_IWL<3016> A_IWL<3015> A_IWL<3014> A_IWL<3013> A_IWL<3012> A_IWL<3011> A_IWL<3010> A_IWL<3009> A_IWL<3008> A_IWL<3007> A_IWL<3006> A_IWL<3005> A_IWL<3004> A_IWL<3003> A_IWL<3002> A_IWL<3001> A_IWL<3000> A_IWL<2999> A_IWL<2998> A_IWL<2997> A_IWL<2996> A_IWL<2995> A_IWL<2994> A_IWL<2993> A_IWL<2992> A_IWL<2991> A_IWL<2990> A_IWL<2989> A_IWL<2988> A_IWL<2987> A_IWL<2986> A_IWL<2985> A_IWL<2984> A_IWL<2983> A_IWL<2982> A_IWL<2981> A_IWL<2980> A_IWL<2979> A_IWL<2978> A_IWL<2977> A_IWL<2976> A_IWL<2975> A_IWL<2974> A_IWL<2973> A_IWL<2972> A_IWL<2971> A_IWL<2970> A_IWL<2969> A_IWL<2968> A_IWL<2967> A_IWL<2966> A_IWL<2965> A_IWL<2964> A_IWL<2963> A_IWL<2962> A_IWL<2961> A_IWL<2960> A_IWL<2959> A_IWL<2958> A_IWL<2957> A_IWL<2956> A_IWL<2955> A_IWL<2954> A_IWL<2953> A_IWL<2952> A_IWL<2951> A_IWL<2950> A_IWL<2949> A_IWL<2948> A_IWL<2947> A_IWL<2946> A_IWL<2945> A_IWL<2944> A_IWL<2943> A_IWL<2942> A_IWL<2941> A_IWL<2940> A_IWL<2939> A_IWL<2938> A_IWL<2937> A_IWL<2936> A_IWL<2935> A_IWL<2934> A_IWL<2933> A_IWL<2932> A_IWL<2931> A_IWL<2930> A_IWL<2929> A_IWL<2928> A_IWL<2927> A_IWL<2926> A_IWL<2925> A_IWL<2924> A_IWL<2923> A_IWL<2922> A_IWL<2921> A_IWL<2920> A_IWL<2919> A_IWL<2918> A_IWL<2917> A_IWL<2916> A_IWL<2915> A_IWL<2914> A_IWL<2913> A_IWL<2912> A_IWL<2911> A_IWL<2910> A_IWL<2909> A_IWL<2908> A_IWL<2907> A_IWL<2906> A_IWL<2905> A_IWL<2904> A_IWL<2903> A_IWL<2902> A_IWL<2901> A_IWL<2900> A_IWL<2899> A_IWL<2898> A_IWL<2897> A_IWL<2896> A_IWL<2895> A_IWL<2894> A_IWL<2893> A_IWL<2892> A_IWL<2891> A_IWL<2890> A_IWL<2889> A_IWL<2888> A_IWL<2887> A_IWL<2886> A_IWL<2885> A_IWL<2884> A_IWL<2883> A_IWL<2882> A_IWL<2881> A_IWL<2880> A_IWL<2879> A_IWL<2878> A_IWL<2877> A_IWL<2876> A_IWL<2875> A_IWL<2874> A_IWL<2873> A_IWL<2872> A_IWL<2871> A_IWL<2870> A_IWL<2869> A_IWL<2868> A_IWL<2867> A_IWL<2866> A_IWL<2865> A_IWL<2864> A_IWL<2863> A_IWL<2862> A_IWL<2861> A_IWL<2860> A_IWL<2859> A_IWL<2858> A_IWL<2857> A_IWL<2856> A_IWL<2855> A_IWL<2854> A_IWL<2853> A_IWL<2852> A_IWL<2851> A_IWL<2850> A_IWL<2849> A_IWL<2848> A_IWL<2847> A_IWL<2846> A_IWL<2845> A_IWL<2844> A_IWL<2843> A_IWL<2842> A_IWL<2841> A_IWL<2840> A_IWL<2839> A_IWL<2838> A_IWL<2837> A_IWL<2836> A_IWL<2835> A_IWL<2834> A_IWL<2833> A_IWL<2832> A_IWL<2831> A_IWL<2830> A_IWL<2829> A_IWL<2828> A_IWL<2827> A_IWL<2826> A_IWL<2825> A_IWL<2824> A_IWL<2823> A_IWL<2822> A_IWL<2821> A_IWL<2820> A_IWL<2819> A_IWL<2818> A_IWL<2817> A_IWL<2816> A_IWL<2815> A_IWL<2814> A_IWL<2813> A_IWL<2812> A_IWL<2811> A_IWL<2810> A_IWL<2809> A_IWL<2808> A_IWL<2807> A_IWL<2806> A_IWL<2805> A_IWL<2804> A_IWL<2803> A_IWL<2802> A_IWL<2801> A_IWL<2800> A_IWL<2799> A_IWL<2798> A_IWL<2797> A_IWL<2796> A_IWL<2795> A_IWL<2794> A_IWL<2793> A_IWL<2792> A_IWL<2791> A_IWL<2790> A_IWL<2789> A_IWL<2788> A_IWL<2787> A_IWL<2786> A_IWL<2785> A_IWL<2784> A_IWL<2783> A_IWL<2782> A_IWL<2781> A_IWL<2780> A_IWL<2779> A_IWL<2778> A_IWL<2777> A_IWL<2776> A_IWL<2775> A_IWL<2774> A_IWL<2773> A_IWL<2772> A_IWL<2771> A_IWL<2770> A_IWL<2769> A_IWL<2768> A_IWL<2767> A_IWL<2766> A_IWL<2765> A_IWL<2764> A_IWL<2763> A_IWL<2762> A_IWL<2761> A_IWL<2760> A_IWL<2759> A_IWL<2758> A_IWL<2757> A_IWL<2756> A_IWL<2755> A_IWL<2754> A_IWL<2753> A_IWL<2752> A_IWL<2751> A_IWL<2750> A_IWL<2749> A_IWL<2748> A_IWL<2747> A_IWL<2746> A_IWL<2745> A_IWL<2744> A_IWL<2743> A_IWL<2742> A_IWL<2741> A_IWL<2740> A_IWL<2739> A_IWL<2738> A_IWL<2737> A_IWL<2736> A_IWL<2735> A_IWL<2734> A_IWL<2733> A_IWL<2732> A_IWL<2731> A_IWL<2730> A_IWL<2729> A_IWL<2728> A_IWL<2727> A_IWL<2726> A_IWL<2725> A_IWL<2724> A_IWL<2723> A_IWL<2722> A_IWL<2721> A_IWL<2720> A_IWL<2719> A_IWL<2718> A_IWL<2717> A_IWL<2716> A_IWL<2715> A_IWL<2714> A_IWL<2713> A_IWL<2712> A_IWL<2711> A_IWL<2710> A_IWL<2709> A_IWL<2708> A_IWL<2707> A_IWL<2706> A_IWL<2705> A_IWL<2704> A_IWL<2703> A_IWL<2702> A_IWL<2701> A_IWL<2700> A_IWL<2699> A_IWL<2698> A_IWL<2697> A_IWL<2696> A_IWL<2695> A_IWL<2694> A_IWL<2693> A_IWL<2692> A_IWL<2691> A_IWL<2690> A_IWL<2689> A_IWL<2688> A_IWL<2687> A_IWL<2686> A_IWL<2685> A_IWL<2684> A_IWL<2683> A_IWL<2682> A_IWL<2681> A_IWL<2680> A_IWL<2679> A_IWL<2678> A_IWL<2677> A_IWL<2676> A_IWL<2675> A_IWL<2674> A_IWL<2673> A_IWL<2672> A_IWL<2671> A_IWL<2670> A_IWL<2669> A_IWL<2668> A_IWL<2667> A_IWL<2666> A_IWL<2665> A_IWL<2664> A_IWL<2663> A_IWL<2662> A_IWL<2661> A_IWL<2660> A_IWL<2659> A_IWL<2658> A_IWL<2657> A_IWL<2656> A_IWL<2655> A_IWL<2654> A_IWL<2653> A_IWL<2652> A_IWL<2651> A_IWL<2650> A_IWL<2649> A_IWL<2648> A_IWL<2647> A_IWL<2646> A_IWL<2645> A_IWL<2644> A_IWL<2643> A_IWL<2642> A_IWL<2641> A_IWL<2640> A_IWL<2639> A_IWL<2638> A_IWL<2637> A_IWL<2636> A_IWL<2635> A_IWL<2634> A_IWL<2633> A_IWL<2632> A_IWL<2631> A_IWL<2630> A_IWL<2629> A_IWL<2628> A_IWL<2627> A_IWL<2626> A_IWL<2625> A_IWL<2624> A_IWL<2623> A_IWL<2622> A_IWL<2621> A_IWL<2620> A_IWL<2619> A_IWL<2618> A_IWL<2617> A_IWL<2616> A_IWL<2615> A_IWL<2614> A_IWL<2613> A_IWL<2612> A_IWL<2611> A_IWL<2610> A_IWL<2609> A_IWL<2608> A_IWL<2607> A_IWL<2606> A_IWL<2605> A_IWL<2604> A_IWL<2603> A_IWL<2602> A_IWL<2601> A_IWL<2600> A_IWL<2599> A_IWL<2598> A_IWL<2597> A_IWL<2596> A_IWL<2595> A_IWL<2594> A_IWL<2593> A_IWL<2592> A_IWL<2591> A_IWL<2590> A_IWL<2589> A_IWL<2588> A_IWL<2587> A_IWL<2586> A_IWL<2585> A_IWL<2584> A_IWL<2583> A_IWL<2582> A_IWL<2581> A_IWL<2580> A_IWL<2579> A_IWL<2578> A_IWL<2577> A_IWL<2576> A_IWL<2575> A_IWL<2574> A_IWL<2573> A_IWL<2572> A_IWL<2571> A_IWL<2570> A_IWL<2569> A_IWL<2568> A_IWL<2567> A_IWL<2566> A_IWL<2565> A_IWL<2564> A_IWL<2563> A_IWL<2562> A_IWL<2561> A_IWL<2560> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_COLUMN_pcell_0 +XCOL<4> A_BLC<9> A_BLC<8> A_BLC_TOP<9> A_BLC_TOP<8> A_BLT<9> A_BLT<8> A_BLT_TOP<9> A_BLT_TOP<8> A_IWL<2047> A_IWL<2046> A_IWL<2045> A_IWL<2044> A_IWL<2043> A_IWL<2042> A_IWL<2041> A_IWL<2040> A_IWL<2039> A_IWL<2038> A_IWL<2037> A_IWL<2036> A_IWL<2035> A_IWL<2034> A_IWL<2033> A_IWL<2032> A_IWL<2031> A_IWL<2030> A_IWL<2029> A_IWL<2028> A_IWL<2027> A_IWL<2026> A_IWL<2025> A_IWL<2024> A_IWL<2023> A_IWL<2022> A_IWL<2021> A_IWL<2020> A_IWL<2019> A_IWL<2018> A_IWL<2017> A_IWL<2016> A_IWL<2015> A_IWL<2014> A_IWL<2013> A_IWL<2012> A_IWL<2011> A_IWL<2010> A_IWL<2009> A_IWL<2008> A_IWL<2007> A_IWL<2006> A_IWL<2005> A_IWL<2004> A_IWL<2003> A_IWL<2002> A_IWL<2001> A_IWL<2000> A_IWL<1999> A_IWL<1998> A_IWL<1997> A_IWL<1996> A_IWL<1995> A_IWL<1994> A_IWL<1993> A_IWL<1992> A_IWL<1991> A_IWL<1990> A_IWL<1989> A_IWL<1988> A_IWL<1987> A_IWL<1986> A_IWL<1985> A_IWL<1984> A_IWL<1983> A_IWL<1982> A_IWL<1981> A_IWL<1980> A_IWL<1979> A_IWL<1978> A_IWL<1977> A_IWL<1976> A_IWL<1975> A_IWL<1974> A_IWL<1973> A_IWL<1972> A_IWL<1971> A_IWL<1970> A_IWL<1969> A_IWL<1968> A_IWL<1967> A_IWL<1966> A_IWL<1965> A_IWL<1964> A_IWL<1963> A_IWL<1962> A_IWL<1961> A_IWL<1960> A_IWL<1959> A_IWL<1958> A_IWL<1957> A_IWL<1956> A_IWL<1955> A_IWL<1954> A_IWL<1953> A_IWL<1952> A_IWL<1951> A_IWL<1950> A_IWL<1949> A_IWL<1948> A_IWL<1947> A_IWL<1946> A_IWL<1945> A_IWL<1944> A_IWL<1943> A_IWL<1942> A_IWL<1941> A_IWL<1940> A_IWL<1939> A_IWL<1938> A_IWL<1937> A_IWL<1936> A_IWL<1935> A_IWL<1934> A_IWL<1933> A_IWL<1932> A_IWL<1931> A_IWL<1930> A_IWL<1929> A_IWL<1928> A_IWL<1927> A_IWL<1926> A_IWL<1925> A_IWL<1924> A_IWL<1923> A_IWL<1922> A_IWL<1921> A_IWL<1920> A_IWL<1919> A_IWL<1918> A_IWL<1917> A_IWL<1916> A_IWL<1915> A_IWL<1914> A_IWL<1913> A_IWL<1912> A_IWL<1911> A_IWL<1910> A_IWL<1909> A_IWL<1908> A_IWL<1907> A_IWL<1906> A_IWL<1905> A_IWL<1904> A_IWL<1903> A_IWL<1902> A_IWL<1901> A_IWL<1900> A_IWL<1899> A_IWL<1898> A_IWL<1897> A_IWL<1896> A_IWL<1895> A_IWL<1894> A_IWL<1893> A_IWL<1892> A_IWL<1891> A_IWL<1890> A_IWL<1889> A_IWL<1888> A_IWL<1887> A_IWL<1886> A_IWL<1885> A_IWL<1884> A_IWL<1883> A_IWL<1882> A_IWL<1881> A_IWL<1880> A_IWL<1879> A_IWL<1878> A_IWL<1877> A_IWL<1876> A_IWL<1875> A_IWL<1874> A_IWL<1873> A_IWL<1872> A_IWL<1871> A_IWL<1870> A_IWL<1869> A_IWL<1868> A_IWL<1867> A_IWL<1866> A_IWL<1865> A_IWL<1864> A_IWL<1863> A_IWL<1862> A_IWL<1861> A_IWL<1860> A_IWL<1859> A_IWL<1858> A_IWL<1857> A_IWL<1856> A_IWL<1855> A_IWL<1854> A_IWL<1853> A_IWL<1852> A_IWL<1851> A_IWL<1850> A_IWL<1849> A_IWL<1848> A_IWL<1847> A_IWL<1846> A_IWL<1845> A_IWL<1844> A_IWL<1843> A_IWL<1842> A_IWL<1841> A_IWL<1840> A_IWL<1839> A_IWL<1838> A_IWL<1837> A_IWL<1836> A_IWL<1835> A_IWL<1834> A_IWL<1833> A_IWL<1832> A_IWL<1831> A_IWL<1830> A_IWL<1829> A_IWL<1828> A_IWL<1827> A_IWL<1826> A_IWL<1825> A_IWL<1824> A_IWL<1823> A_IWL<1822> A_IWL<1821> A_IWL<1820> A_IWL<1819> A_IWL<1818> A_IWL<1817> A_IWL<1816> A_IWL<1815> A_IWL<1814> A_IWL<1813> A_IWL<1812> A_IWL<1811> A_IWL<1810> A_IWL<1809> A_IWL<1808> A_IWL<1807> A_IWL<1806> A_IWL<1805> A_IWL<1804> A_IWL<1803> A_IWL<1802> A_IWL<1801> A_IWL<1800> A_IWL<1799> A_IWL<1798> A_IWL<1797> A_IWL<1796> A_IWL<1795> A_IWL<1794> A_IWL<1793> A_IWL<1792> A_IWL<1791> A_IWL<1790> A_IWL<1789> A_IWL<1788> A_IWL<1787> A_IWL<1786> A_IWL<1785> A_IWL<1784> A_IWL<1783> A_IWL<1782> A_IWL<1781> A_IWL<1780> A_IWL<1779> A_IWL<1778> A_IWL<1777> A_IWL<1776> A_IWL<1775> A_IWL<1774> A_IWL<1773> A_IWL<1772> A_IWL<1771> A_IWL<1770> A_IWL<1769> A_IWL<1768> A_IWL<1767> A_IWL<1766> A_IWL<1765> A_IWL<1764> A_IWL<1763> A_IWL<1762> A_IWL<1761> A_IWL<1760> A_IWL<1759> A_IWL<1758> A_IWL<1757> A_IWL<1756> A_IWL<1755> A_IWL<1754> A_IWL<1753> A_IWL<1752> A_IWL<1751> A_IWL<1750> A_IWL<1749> A_IWL<1748> A_IWL<1747> A_IWL<1746> A_IWL<1745> A_IWL<1744> A_IWL<1743> A_IWL<1742> A_IWL<1741> A_IWL<1740> A_IWL<1739> A_IWL<1738> A_IWL<1737> A_IWL<1736> A_IWL<1735> A_IWL<1734> A_IWL<1733> A_IWL<1732> A_IWL<1731> A_IWL<1730> A_IWL<1729> A_IWL<1728> A_IWL<1727> A_IWL<1726> A_IWL<1725> A_IWL<1724> A_IWL<1723> A_IWL<1722> A_IWL<1721> A_IWL<1720> A_IWL<1719> A_IWL<1718> A_IWL<1717> A_IWL<1716> A_IWL<1715> A_IWL<1714> A_IWL<1713> A_IWL<1712> A_IWL<1711> A_IWL<1710> A_IWL<1709> A_IWL<1708> A_IWL<1707> A_IWL<1706> A_IWL<1705> A_IWL<1704> A_IWL<1703> A_IWL<1702> A_IWL<1701> A_IWL<1700> A_IWL<1699> A_IWL<1698> A_IWL<1697> A_IWL<1696> A_IWL<1695> A_IWL<1694> A_IWL<1693> A_IWL<1692> A_IWL<1691> A_IWL<1690> A_IWL<1689> A_IWL<1688> A_IWL<1687> A_IWL<1686> A_IWL<1685> A_IWL<1684> A_IWL<1683> A_IWL<1682> A_IWL<1681> A_IWL<1680> A_IWL<1679> A_IWL<1678> A_IWL<1677> A_IWL<1676> A_IWL<1675> A_IWL<1674> A_IWL<1673> A_IWL<1672> A_IWL<1671> A_IWL<1670> A_IWL<1669> A_IWL<1668> A_IWL<1667> A_IWL<1666> A_IWL<1665> A_IWL<1664> A_IWL<1663> A_IWL<1662> A_IWL<1661> A_IWL<1660> A_IWL<1659> A_IWL<1658> A_IWL<1657> A_IWL<1656> A_IWL<1655> A_IWL<1654> A_IWL<1653> A_IWL<1652> A_IWL<1651> A_IWL<1650> A_IWL<1649> A_IWL<1648> A_IWL<1647> A_IWL<1646> A_IWL<1645> A_IWL<1644> A_IWL<1643> A_IWL<1642> A_IWL<1641> A_IWL<1640> A_IWL<1639> A_IWL<1638> A_IWL<1637> A_IWL<1636> A_IWL<1635> A_IWL<1634> A_IWL<1633> A_IWL<1632> A_IWL<1631> A_IWL<1630> A_IWL<1629> A_IWL<1628> A_IWL<1627> A_IWL<1626> A_IWL<1625> A_IWL<1624> A_IWL<1623> A_IWL<1622> A_IWL<1621> A_IWL<1620> A_IWL<1619> A_IWL<1618> A_IWL<1617> A_IWL<1616> A_IWL<1615> A_IWL<1614> A_IWL<1613> A_IWL<1612> A_IWL<1611> A_IWL<1610> A_IWL<1609> A_IWL<1608> A_IWL<1607> A_IWL<1606> A_IWL<1605> A_IWL<1604> A_IWL<1603> A_IWL<1602> A_IWL<1601> A_IWL<1600> A_IWL<1599> A_IWL<1598> A_IWL<1597> A_IWL<1596> A_IWL<1595> A_IWL<1594> A_IWL<1593> A_IWL<1592> A_IWL<1591> A_IWL<1590> A_IWL<1589> A_IWL<1588> A_IWL<1587> A_IWL<1586> A_IWL<1585> A_IWL<1584> A_IWL<1583> A_IWL<1582> A_IWL<1581> A_IWL<1580> A_IWL<1579> A_IWL<1578> A_IWL<1577> A_IWL<1576> A_IWL<1575> A_IWL<1574> A_IWL<1573> A_IWL<1572> A_IWL<1571> A_IWL<1570> A_IWL<1569> A_IWL<1568> A_IWL<1567> A_IWL<1566> A_IWL<1565> A_IWL<1564> A_IWL<1563> A_IWL<1562> A_IWL<1561> A_IWL<1560> A_IWL<1559> A_IWL<1558> A_IWL<1557> A_IWL<1556> A_IWL<1555> A_IWL<1554> A_IWL<1553> A_IWL<1552> A_IWL<1551> A_IWL<1550> A_IWL<1549> A_IWL<1548> A_IWL<1547> A_IWL<1546> A_IWL<1545> A_IWL<1544> A_IWL<1543> A_IWL<1542> A_IWL<1541> A_IWL<1540> A_IWL<1539> A_IWL<1538> A_IWL<1537> A_IWL<1536> A_IWL<2559> A_IWL<2558> A_IWL<2557> A_IWL<2556> A_IWL<2555> A_IWL<2554> A_IWL<2553> A_IWL<2552> A_IWL<2551> A_IWL<2550> A_IWL<2549> A_IWL<2548> A_IWL<2547> A_IWL<2546> A_IWL<2545> A_IWL<2544> A_IWL<2543> A_IWL<2542> A_IWL<2541> A_IWL<2540> A_IWL<2539> A_IWL<2538> A_IWL<2537> A_IWL<2536> A_IWL<2535> A_IWL<2534> A_IWL<2533> A_IWL<2532> A_IWL<2531> A_IWL<2530> A_IWL<2529> A_IWL<2528> A_IWL<2527> A_IWL<2526> A_IWL<2525> A_IWL<2524> A_IWL<2523> A_IWL<2522> A_IWL<2521> A_IWL<2520> A_IWL<2519> A_IWL<2518> A_IWL<2517> A_IWL<2516> A_IWL<2515> A_IWL<2514> A_IWL<2513> A_IWL<2512> A_IWL<2511> A_IWL<2510> A_IWL<2509> A_IWL<2508> A_IWL<2507> A_IWL<2506> A_IWL<2505> A_IWL<2504> A_IWL<2503> A_IWL<2502> A_IWL<2501> A_IWL<2500> A_IWL<2499> A_IWL<2498> A_IWL<2497> A_IWL<2496> A_IWL<2495> A_IWL<2494> A_IWL<2493> A_IWL<2492> A_IWL<2491> A_IWL<2490> A_IWL<2489> A_IWL<2488> A_IWL<2487> A_IWL<2486> A_IWL<2485> A_IWL<2484> A_IWL<2483> A_IWL<2482> A_IWL<2481> A_IWL<2480> A_IWL<2479> A_IWL<2478> A_IWL<2477> A_IWL<2476> A_IWL<2475> A_IWL<2474> A_IWL<2473> A_IWL<2472> A_IWL<2471> A_IWL<2470> A_IWL<2469> A_IWL<2468> A_IWL<2467> A_IWL<2466> A_IWL<2465> A_IWL<2464> A_IWL<2463> A_IWL<2462> A_IWL<2461> A_IWL<2460> A_IWL<2459> A_IWL<2458> A_IWL<2457> A_IWL<2456> A_IWL<2455> A_IWL<2454> A_IWL<2453> A_IWL<2452> A_IWL<2451> A_IWL<2450> A_IWL<2449> A_IWL<2448> A_IWL<2447> A_IWL<2446> A_IWL<2445> A_IWL<2444> A_IWL<2443> A_IWL<2442> A_IWL<2441> A_IWL<2440> A_IWL<2439> A_IWL<2438> A_IWL<2437> A_IWL<2436> A_IWL<2435> A_IWL<2434> A_IWL<2433> A_IWL<2432> A_IWL<2431> A_IWL<2430> A_IWL<2429> A_IWL<2428> A_IWL<2427> A_IWL<2426> A_IWL<2425> A_IWL<2424> A_IWL<2423> A_IWL<2422> A_IWL<2421> A_IWL<2420> A_IWL<2419> A_IWL<2418> A_IWL<2417> A_IWL<2416> A_IWL<2415> A_IWL<2414> A_IWL<2413> A_IWL<2412> A_IWL<2411> A_IWL<2410> A_IWL<2409> A_IWL<2408> A_IWL<2407> A_IWL<2406> A_IWL<2405> A_IWL<2404> A_IWL<2403> A_IWL<2402> A_IWL<2401> A_IWL<2400> A_IWL<2399> A_IWL<2398> A_IWL<2397> A_IWL<2396> A_IWL<2395> A_IWL<2394> A_IWL<2393> A_IWL<2392> A_IWL<2391> A_IWL<2390> A_IWL<2389> A_IWL<2388> A_IWL<2387> A_IWL<2386> A_IWL<2385> A_IWL<2384> A_IWL<2383> A_IWL<2382> A_IWL<2381> A_IWL<2380> A_IWL<2379> A_IWL<2378> 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A_IWL<1906> A_IWL<1905> A_IWL<1904> A_IWL<1903> A_IWL<1902> A_IWL<1901> A_IWL<1900> A_IWL<1899> A_IWL<1898> A_IWL<1897> A_IWL<1896> A_IWL<1895> A_IWL<1894> A_IWL<1893> A_IWL<1892> A_IWL<1891> A_IWL<1890> A_IWL<1889> A_IWL<1888> A_IWL<1887> A_IWL<1886> A_IWL<1885> A_IWL<1884> A_IWL<1883> A_IWL<1882> A_IWL<1881> A_IWL<1880> A_IWL<1879> A_IWL<1878> A_IWL<1877> A_IWL<1876> A_IWL<1875> A_IWL<1874> A_IWL<1873> A_IWL<1872> A_IWL<1871> A_IWL<1870> A_IWL<1869> A_IWL<1868> A_IWL<1867> A_IWL<1866> A_IWL<1865> A_IWL<1864> A_IWL<1863> A_IWL<1862> A_IWL<1861> A_IWL<1860> A_IWL<1859> A_IWL<1858> A_IWL<1857> A_IWL<1856> A_IWL<1855> A_IWL<1854> A_IWL<1853> A_IWL<1852> A_IWL<1851> A_IWL<1850> A_IWL<1849> A_IWL<1848> A_IWL<1847> A_IWL<1846> A_IWL<1845> A_IWL<1844> A_IWL<1843> A_IWL<1842> A_IWL<1841> A_IWL<1840> A_IWL<1839> A_IWL<1838> A_IWL<1837> A_IWL<1836> A_IWL<1835> A_IWL<1834> A_IWL<1833> A_IWL<1832> A_IWL<1831> A_IWL<1830> A_IWL<1829> A_IWL<1828> A_IWL<1827> A_IWL<1826> A_IWL<1825> A_IWL<1824> A_IWL<1823> A_IWL<1822> A_IWL<1821> A_IWL<1820> A_IWL<1819> A_IWL<1818> A_IWL<1817> A_IWL<1816> A_IWL<1815> A_IWL<1814> A_IWL<1813> A_IWL<1812> A_IWL<1811> A_IWL<1810> A_IWL<1809> A_IWL<1808> A_IWL<1807> A_IWL<1806> A_IWL<1805> A_IWL<1804> A_IWL<1803> A_IWL<1802> A_IWL<1801> A_IWL<1800> A_IWL<1799> A_IWL<1798> A_IWL<1797> A_IWL<1796> A_IWL<1795> A_IWL<1794> A_IWL<1793> A_IWL<1792> A_IWL<1791> A_IWL<1790> A_IWL<1789> A_IWL<1788> A_IWL<1787> A_IWL<1786> A_IWL<1785> A_IWL<1784> A_IWL<1783> A_IWL<1782> A_IWL<1781> A_IWL<1780> A_IWL<1779> A_IWL<1778> A_IWL<1777> A_IWL<1776> A_IWL<1775> A_IWL<1774> A_IWL<1773> A_IWL<1772> A_IWL<1771> A_IWL<1770> A_IWL<1769> A_IWL<1768> A_IWL<1767> A_IWL<1766> A_IWL<1765> A_IWL<1764> A_IWL<1763> A_IWL<1762> A_IWL<1761> A_IWL<1760> A_IWL<1759> A_IWL<1758> A_IWL<1757> A_IWL<1756> A_IWL<1755> A_IWL<1754> A_IWL<1753> A_IWL<1752> A_IWL<1751> A_IWL<1750> A_IWL<1749> A_IWL<1748> A_IWL<1747> A_IWL<1746> A_IWL<1745> A_IWL<1744> A_IWL<1743> A_IWL<1742> A_IWL<1741> A_IWL<1740> A_IWL<1739> A_IWL<1738> A_IWL<1737> A_IWL<1736> A_IWL<1735> A_IWL<1734> A_IWL<1733> A_IWL<1732> A_IWL<1731> A_IWL<1730> A_IWL<1729> A_IWL<1728> A_IWL<1727> A_IWL<1726> A_IWL<1725> A_IWL<1724> A_IWL<1723> A_IWL<1722> A_IWL<1721> A_IWL<1720> A_IWL<1719> A_IWL<1718> A_IWL<1717> A_IWL<1716> A_IWL<1715> A_IWL<1714> A_IWL<1713> A_IWL<1712> A_IWL<1711> A_IWL<1710> A_IWL<1709> A_IWL<1708> A_IWL<1707> A_IWL<1706> A_IWL<1705> A_IWL<1704> A_IWL<1703> A_IWL<1702> A_IWL<1701> A_IWL<1700> A_IWL<1699> A_IWL<1698> A_IWL<1697> A_IWL<1696> A_IWL<1695> A_IWL<1694> A_IWL<1693> A_IWL<1692> A_IWL<1691> A_IWL<1690> A_IWL<1689> A_IWL<1688> A_IWL<1687> A_IWL<1686> A_IWL<1685> A_IWL<1684> A_IWL<1683> A_IWL<1682> A_IWL<1681> A_IWL<1680> A_IWL<1679> A_IWL<1678> A_IWL<1677> A_IWL<1676> A_IWL<1675> A_IWL<1674> A_IWL<1673> A_IWL<1672> A_IWL<1671> A_IWL<1670> A_IWL<1669> A_IWL<1668> A_IWL<1667> A_IWL<1666> A_IWL<1665> A_IWL<1664> A_IWL<1663> A_IWL<1662> A_IWL<1661> A_IWL<1660> A_IWL<1659> A_IWL<1658> A_IWL<1657> A_IWL<1656> A_IWL<1655> A_IWL<1654> A_IWL<1653> A_IWL<1652> A_IWL<1651> A_IWL<1650> A_IWL<1649> A_IWL<1648> A_IWL<1647> A_IWL<1646> A_IWL<1645> A_IWL<1644> A_IWL<1643> A_IWL<1642> A_IWL<1641> A_IWL<1640> A_IWL<1639> A_IWL<1638> A_IWL<1637> A_IWL<1636> A_IWL<1635> A_IWL<1634> A_IWL<1633> A_IWL<1632> A_IWL<1631> A_IWL<1630> A_IWL<1629> A_IWL<1628> A_IWL<1627> A_IWL<1626> A_IWL<1625> A_IWL<1624> A_IWL<1623> A_IWL<1622> A_IWL<1621> A_IWL<1620> A_IWL<1619> A_IWL<1618> A_IWL<1617> A_IWL<1616> A_IWL<1615> A_IWL<1614> A_IWL<1613> A_IWL<1612> A_IWL<1611> A_IWL<1610> A_IWL<1609> A_IWL<1608> A_IWL<1607> A_IWL<1606> A_IWL<1605> A_IWL<1604> A_IWL<1603> A_IWL<1602> A_IWL<1601> A_IWL<1600> A_IWL<1599> A_IWL<1598> A_IWL<1597> A_IWL<1596> A_IWL<1595> A_IWL<1594> A_IWL<1593> A_IWL<1592> A_IWL<1591> A_IWL<1590> A_IWL<1589> A_IWL<1588> A_IWL<1587> A_IWL<1586> A_IWL<1585> A_IWL<1584> A_IWL<1583> A_IWL<1582> A_IWL<1581> A_IWL<1580> A_IWL<1579> A_IWL<1578> A_IWL<1577> A_IWL<1576> A_IWL<1575> A_IWL<1574> A_IWL<1573> A_IWL<1572> A_IWL<1571> A_IWL<1570> A_IWL<1569> A_IWL<1568> A_IWL<1567> A_IWL<1566> A_IWL<1565> A_IWL<1564> A_IWL<1563> A_IWL<1562> A_IWL<1561> A_IWL<1560> A_IWL<1559> A_IWL<1558> A_IWL<1557> A_IWL<1556> A_IWL<1555> A_IWL<1554> A_IWL<1553> A_IWL<1552> A_IWL<1551> A_IWL<1550> A_IWL<1549> A_IWL<1548> A_IWL<1547> A_IWL<1546> A_IWL<1545> A_IWL<1544> A_IWL<1543> A_IWL<1542> A_IWL<1541> A_IWL<1540> A_IWL<1539> A_IWL<1538> A_IWL<1537> A_IWL<1536> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_COLUMN_pcell_0 +XCOL<2> A_BLC<5> A_BLC<4> A_BLC_TOP<5> A_BLC_TOP<4> A_BLT<5> A_BLT<4> A_BLT_TOP<5> A_BLT_TOP<4> A_IWL<1023> A_IWL<1022> A_IWL<1021> A_IWL<1020> A_IWL<1019> A_IWL<1018> A_IWL<1017> A_IWL<1016> A_IWL<1015> A_IWL<1014> A_IWL<1013> A_IWL<1012> A_IWL<1011> A_IWL<1010> A_IWL<1009> A_IWL<1008> A_IWL<1007> A_IWL<1006> A_IWL<1005> A_IWL<1004> A_IWL<1003> A_IWL<1002> A_IWL<1001> A_IWL<1000> A_IWL<999> A_IWL<998> A_IWL<997> A_IWL<996> A_IWL<995> A_IWL<994> A_IWL<993> A_IWL<992> A_IWL<991> A_IWL<990> A_IWL<989> A_IWL<988> A_IWL<987> A_IWL<986> A_IWL<985> A_IWL<984> A_IWL<983> A_IWL<982> A_IWL<981> A_IWL<980> A_IWL<979> A_IWL<978> A_IWL<977> A_IWL<976> A_IWL<975> A_IWL<974> A_IWL<973> A_IWL<972> A_IWL<971> A_IWL<970> A_IWL<969> A_IWL<968> A_IWL<967> A_IWL<966> A_IWL<965> A_IWL<964> A_IWL<963> A_IWL<962> A_IWL<961> A_IWL<960> A_IWL<959> A_IWL<958> A_IWL<957> A_IWL<956> A_IWL<955> A_IWL<954> A_IWL<953> A_IWL<952> A_IWL<951> A_IWL<950> A_IWL<949> A_IWL<948> A_IWL<947> A_IWL<946> A_IWL<945> A_IWL<944> A_IWL<943> A_IWL<942> A_IWL<941> A_IWL<940> A_IWL<939> A_IWL<938> A_IWL<937> A_IWL<936> A_IWL<935> A_IWL<934> A_IWL<933> A_IWL<932> A_IWL<931> A_IWL<930> A_IWL<929> A_IWL<928> A_IWL<927> A_IWL<926> A_IWL<925> A_IWL<924> A_IWL<923> A_IWL<922> A_IWL<921> A_IWL<920> A_IWL<919> A_IWL<918> A_IWL<917> A_IWL<916> A_IWL<915> A_IWL<914> A_IWL<913> A_IWL<912> A_IWL<911> A_IWL<910> A_IWL<909> A_IWL<908> A_IWL<907> A_IWL<906> A_IWL<905> A_IWL<904> A_IWL<903> A_IWL<902> A_IWL<901> A_IWL<900> A_IWL<899> A_IWL<898> A_IWL<897> A_IWL<896> A_IWL<895> A_IWL<894> A_IWL<893> A_IWL<892> A_IWL<891> A_IWL<890> A_IWL<889> A_IWL<888> A_IWL<887> A_IWL<886> A_IWL<885> A_IWL<884> A_IWL<883> A_IWL<882> A_IWL<881> A_IWL<880> A_IWL<879> A_IWL<878> A_IWL<877> A_IWL<876> A_IWL<875> A_IWL<874> A_IWL<873> A_IWL<872> A_IWL<871> A_IWL<870> A_IWL<869> A_IWL<868> A_IWL<867> A_IWL<866> A_IWL<865> A_IWL<864> A_IWL<863> A_IWL<862> A_IWL<861> A_IWL<860> A_IWL<859> A_IWL<858> A_IWL<857> A_IWL<856> A_IWL<855> A_IWL<854> A_IWL<853> A_IWL<852> A_IWL<851> A_IWL<850> A_IWL<849> A_IWL<848> A_IWL<847> A_IWL<846> A_IWL<845> A_IWL<844> A_IWL<843> A_IWL<842> A_IWL<841> A_IWL<840> A_IWL<839> A_IWL<838> A_IWL<837> A_IWL<836> A_IWL<835> A_IWL<834> A_IWL<833> A_IWL<832> A_IWL<831> A_IWL<830> A_IWL<829> A_IWL<828> A_IWL<827> A_IWL<826> A_IWL<825> A_IWL<824> A_IWL<823> A_IWL<822> A_IWL<821> A_IWL<820> A_IWL<819> A_IWL<818> A_IWL<817> A_IWL<816> A_IWL<815> A_IWL<814> A_IWL<813> A_IWL<812> A_IWL<811> A_IWL<810> A_IWL<809> A_IWL<808> A_IWL<807> A_IWL<806> A_IWL<805> A_IWL<804> A_IWL<803> A_IWL<802> A_IWL<801> A_IWL<800> A_IWL<799> A_IWL<798> A_IWL<797> A_IWL<796> A_IWL<795> A_IWL<794> A_IWL<793> A_IWL<792> A_IWL<791> A_IWL<790> A_IWL<789> A_IWL<788> A_IWL<787> A_IWL<786> A_IWL<785> A_IWL<784> A_IWL<783> A_IWL<782> A_IWL<781> A_IWL<780> A_IWL<779> A_IWL<778> A_IWL<777> A_IWL<776> A_IWL<775> A_IWL<774> A_IWL<773> A_IWL<772> A_IWL<771> A_IWL<770> A_IWL<769> A_IWL<768> A_IWL<767> A_IWL<766> A_IWL<765> A_IWL<764> A_IWL<763> A_IWL<762> A_IWL<761> A_IWL<760> A_IWL<759> A_IWL<758> A_IWL<757> A_IWL<756> A_IWL<755> A_IWL<754> A_IWL<753> A_IWL<752> A_IWL<751> A_IWL<750> A_IWL<749> A_IWL<748> A_IWL<747> A_IWL<746> A_IWL<745> A_IWL<744> A_IWL<743> A_IWL<742> A_IWL<741> A_IWL<740> A_IWL<739> A_IWL<738> A_IWL<737> A_IWL<736> A_IWL<735> A_IWL<734> A_IWL<733> A_IWL<732> A_IWL<731> A_IWL<730> A_IWL<729> A_IWL<728> A_IWL<727> A_IWL<726> A_IWL<725> A_IWL<724> A_IWL<723> A_IWL<722> A_IWL<721> A_IWL<720> A_IWL<719> A_IWL<718> A_IWL<717> A_IWL<716> A_IWL<715> A_IWL<714> A_IWL<713> A_IWL<712> A_IWL<711> A_IWL<710> A_IWL<709> A_IWL<708> A_IWL<707> A_IWL<706> A_IWL<705> A_IWL<704> A_IWL<703> A_IWL<702> A_IWL<701> A_IWL<700> A_IWL<699> A_IWL<698> A_IWL<697> A_IWL<696> A_IWL<695> A_IWL<694> A_IWL<693> A_IWL<692> A_IWL<691> A_IWL<690> A_IWL<689> A_IWL<688> A_IWL<687> A_IWL<686> A_IWL<685> A_IWL<684> A_IWL<683> A_IWL<682> A_IWL<681> A_IWL<680> A_IWL<679> A_IWL<678> A_IWL<677> A_IWL<676> A_IWL<675> A_IWL<674> A_IWL<673> A_IWL<672> A_IWL<671> A_IWL<670> A_IWL<669> A_IWL<668> A_IWL<667> A_IWL<666> A_IWL<665> A_IWL<664> A_IWL<663> A_IWL<662> A_IWL<661> A_IWL<660> A_IWL<659> A_IWL<658> A_IWL<657> A_IWL<656> A_IWL<655> A_IWL<654> A_IWL<653> A_IWL<652> A_IWL<651> A_IWL<650> A_IWL<649> A_IWL<648> A_IWL<647> A_IWL<646> A_IWL<645> A_IWL<644> A_IWL<643> A_IWL<642> A_IWL<641> A_IWL<640> A_IWL<639> A_IWL<638> A_IWL<637> A_IWL<636> A_IWL<635> A_IWL<634> A_IWL<633> A_IWL<632> A_IWL<631> A_IWL<630> A_IWL<629> A_IWL<628> A_IWL<627> A_IWL<626> A_IWL<625> A_IWL<624> A_IWL<623> A_IWL<622> A_IWL<621> A_IWL<620> A_IWL<619> A_IWL<618> A_IWL<617> A_IWL<616> A_IWL<615> A_IWL<614> A_IWL<613> A_IWL<612> A_IWL<611> A_IWL<610> A_IWL<609> A_IWL<608> A_IWL<607> A_IWL<606> A_IWL<605> A_IWL<604> A_IWL<603> A_IWL<602> A_IWL<601> A_IWL<600> A_IWL<599> A_IWL<598> A_IWL<597> A_IWL<596> A_IWL<595> A_IWL<594> A_IWL<593> A_IWL<592> A_IWL<591> A_IWL<590> A_IWL<589> A_IWL<588> A_IWL<587> A_IWL<586> A_IWL<585> A_IWL<584> A_IWL<583> A_IWL<582> A_IWL<581> A_IWL<580> A_IWL<579> A_IWL<578> A_IWL<577> A_IWL<576> A_IWL<575> A_IWL<574> A_IWL<573> A_IWL<572> A_IWL<571> A_IWL<570> A_IWL<569> A_IWL<568> A_IWL<567> A_IWL<566> A_IWL<565> A_IWL<564> A_IWL<563> A_IWL<562> A_IWL<561> A_IWL<560> A_IWL<559> A_IWL<558> A_IWL<557> A_IWL<556> A_IWL<555> A_IWL<554> A_IWL<553> A_IWL<552> A_IWL<551> A_IWL<550> A_IWL<549> A_IWL<548> A_IWL<547> A_IWL<546> A_IWL<545> A_IWL<544> A_IWL<543> A_IWL<542> A_IWL<541> A_IWL<540> A_IWL<539> A_IWL<538> A_IWL<537> A_IWL<536> A_IWL<535> A_IWL<534> A_IWL<533> A_IWL<532> A_IWL<531> A_IWL<530> A_IWL<529> A_IWL<528> A_IWL<527> A_IWL<526> A_IWL<525> A_IWL<524> A_IWL<523> A_IWL<522> A_IWL<521> A_IWL<520> A_IWL<519> A_IWL<518> A_IWL<517> A_IWL<516> A_IWL<515> A_IWL<514> A_IWL<513> A_IWL<512> A_IWL<1535> A_IWL<1534> A_IWL<1533> A_IWL<1532> A_IWL<1531> A_IWL<1530> A_IWL<1529> A_IWL<1528> A_IWL<1527> A_IWL<1526> A_IWL<1525> A_IWL<1524> A_IWL<1523> A_IWL<1522> A_IWL<1521> A_IWL<1520> A_IWL<1519> A_IWL<1518> A_IWL<1517> A_IWL<1516> A_IWL<1515> A_IWL<1514> A_IWL<1513> A_IWL<1512> A_IWL<1511> A_IWL<1510> A_IWL<1509> A_IWL<1508> A_IWL<1507> A_IWL<1506> A_IWL<1505> A_IWL<1504> A_IWL<1503> A_IWL<1502> A_IWL<1501> A_IWL<1500> A_IWL<1499> A_IWL<1498> A_IWL<1497> A_IWL<1496> A_IWL<1495> A_IWL<1494> A_IWL<1493> A_IWL<1492> A_IWL<1491> A_IWL<1490> A_IWL<1489> A_IWL<1488> A_IWL<1487> A_IWL<1486> A_IWL<1485> A_IWL<1484> A_IWL<1483> A_IWL<1482> A_IWL<1481> A_IWL<1480> A_IWL<1479> A_IWL<1478> A_IWL<1477> A_IWL<1476> A_IWL<1475> A_IWL<1474> A_IWL<1473> A_IWL<1472> A_IWL<1471> A_IWL<1470> A_IWL<1469> A_IWL<1468> A_IWL<1467> A_IWL<1466> A_IWL<1465> A_IWL<1464> A_IWL<1463> A_IWL<1462> A_IWL<1461> A_IWL<1460> A_IWL<1459> A_IWL<1458> A_IWL<1457> A_IWL<1456> A_IWL<1455> A_IWL<1454> A_IWL<1453> A_IWL<1452> A_IWL<1451> A_IWL<1450> A_IWL<1449> A_IWL<1448> A_IWL<1447> A_IWL<1446> A_IWL<1445> A_IWL<1444> A_IWL<1443> A_IWL<1442> A_IWL<1441> A_IWL<1440> A_IWL<1439> A_IWL<1438> A_IWL<1437> A_IWL<1436> A_IWL<1435> A_IWL<1434> A_IWL<1433> A_IWL<1432> A_IWL<1431> A_IWL<1430> A_IWL<1429> A_IWL<1428> A_IWL<1427> A_IWL<1426> A_IWL<1425> A_IWL<1424> A_IWL<1423> A_IWL<1422> A_IWL<1421> A_IWL<1420> A_IWL<1419> A_IWL<1418> A_IWL<1417> A_IWL<1416> A_IWL<1415> A_IWL<1414> A_IWL<1413> A_IWL<1412> A_IWL<1411> A_IWL<1410> A_IWL<1409> A_IWL<1408> A_IWL<1407> A_IWL<1406> A_IWL<1405> A_IWL<1404> A_IWL<1403> A_IWL<1402> A_IWL<1401> A_IWL<1400> A_IWL<1399> A_IWL<1398> A_IWL<1397> A_IWL<1396> A_IWL<1395> A_IWL<1394> A_IWL<1393> A_IWL<1392> A_IWL<1391> A_IWL<1390> A_IWL<1389> A_IWL<1388> A_IWL<1387> A_IWL<1386> A_IWL<1385> A_IWL<1384> A_IWL<1383> A_IWL<1382> A_IWL<1381> A_IWL<1380> A_IWL<1379> A_IWL<1378> A_IWL<1377> A_IWL<1376> A_IWL<1375> A_IWL<1374> A_IWL<1373> A_IWL<1372> A_IWL<1371> A_IWL<1370> A_IWL<1369> A_IWL<1368> A_IWL<1367> A_IWL<1366> A_IWL<1365> A_IWL<1364> A_IWL<1363> A_IWL<1362> A_IWL<1361> A_IWL<1360> A_IWL<1359> A_IWL<1358> A_IWL<1357> A_IWL<1356> A_IWL<1355> A_IWL<1354> A_IWL<1353> A_IWL<1352> A_IWL<1351> A_IWL<1350> A_IWL<1349> A_IWL<1348> A_IWL<1347> A_IWL<1346> A_IWL<1345> A_IWL<1344> A_IWL<1343> A_IWL<1342> A_IWL<1341> A_IWL<1340> A_IWL<1339> A_IWL<1338> A_IWL<1337> A_IWL<1336> A_IWL<1335> A_IWL<1334> A_IWL<1333> A_IWL<1332> A_IWL<1331> A_IWL<1330> A_IWL<1329> A_IWL<1328> A_IWL<1327> A_IWL<1326> A_IWL<1325> A_IWL<1324> A_IWL<1323> A_IWL<1322> A_IWL<1321> A_IWL<1320> A_IWL<1319> A_IWL<1318> A_IWL<1317> A_IWL<1316> A_IWL<1315> A_IWL<1314> A_IWL<1313> A_IWL<1312> A_IWL<1311> A_IWL<1310> A_IWL<1309> A_IWL<1308> A_IWL<1307> A_IWL<1306> A_IWL<1305> A_IWL<1304> A_IWL<1303> A_IWL<1302> A_IWL<1301> A_IWL<1300> A_IWL<1299> A_IWL<1298> A_IWL<1297> A_IWL<1296> A_IWL<1295> A_IWL<1294> A_IWL<1293> A_IWL<1292> A_IWL<1291> A_IWL<1290> A_IWL<1289> A_IWL<1288> A_IWL<1287> A_IWL<1286> A_IWL<1285> A_IWL<1284> A_IWL<1283> A_IWL<1282> A_IWL<1281> A_IWL<1280> A_IWL<1279> A_IWL<1278> A_IWL<1277> A_IWL<1276> A_IWL<1275> A_IWL<1274> A_IWL<1273> A_IWL<1272> A_IWL<1271> A_IWL<1270> A_IWL<1269> A_IWL<1268> A_IWL<1267> A_IWL<1266> A_IWL<1265> A_IWL<1264> A_IWL<1263> A_IWL<1262> A_IWL<1261> A_IWL<1260> A_IWL<1259> A_IWL<1258> A_IWL<1257> A_IWL<1256> A_IWL<1255> A_IWL<1254> A_IWL<1253> A_IWL<1252> A_IWL<1251> A_IWL<1250> A_IWL<1249> A_IWL<1248> A_IWL<1247> A_IWL<1246> A_IWL<1245> A_IWL<1244> A_IWL<1243> A_IWL<1242> A_IWL<1241> A_IWL<1240> A_IWL<1239> A_IWL<1238> A_IWL<1237> A_IWL<1236> A_IWL<1235> A_IWL<1234> A_IWL<1233> A_IWL<1232> A_IWL<1231> A_IWL<1230> A_IWL<1229> A_IWL<1228> A_IWL<1227> A_IWL<1226> A_IWL<1225> A_IWL<1224> A_IWL<1223> A_IWL<1222> A_IWL<1221> A_IWL<1220> A_IWL<1219> A_IWL<1218> A_IWL<1217> A_IWL<1216> A_IWL<1215> A_IWL<1214> A_IWL<1213> A_IWL<1212> A_IWL<1211> A_IWL<1210> A_IWL<1209> A_IWL<1208> A_IWL<1207> A_IWL<1206> A_IWL<1205> A_IWL<1204> A_IWL<1203> A_IWL<1202> A_IWL<1201> A_IWL<1200> A_IWL<1199> A_IWL<1198> A_IWL<1197> A_IWL<1196> A_IWL<1195> A_IWL<1194> A_IWL<1193> A_IWL<1192> A_IWL<1191> A_IWL<1190> A_IWL<1189> A_IWL<1188> A_IWL<1187> A_IWL<1186> A_IWL<1185> A_IWL<1184> A_IWL<1183> A_IWL<1182> A_IWL<1181> A_IWL<1180> A_IWL<1179> A_IWL<1178> A_IWL<1177> A_IWL<1176> A_IWL<1175> A_IWL<1174> A_IWL<1173> A_IWL<1172> A_IWL<1171> A_IWL<1170> A_IWL<1169> A_IWL<1168> A_IWL<1167> A_IWL<1166> A_IWL<1165> A_IWL<1164> A_IWL<1163> A_IWL<1162> A_IWL<1161> A_IWL<1160> A_IWL<1159> A_IWL<1158> A_IWL<1157> A_IWL<1156> A_IWL<1155> A_IWL<1154> A_IWL<1153> A_IWL<1152> A_IWL<1151> A_IWL<1150> A_IWL<1149> A_IWL<1148> A_IWL<1147> A_IWL<1146> A_IWL<1145> A_IWL<1144> A_IWL<1143> A_IWL<1142> A_IWL<1141> A_IWL<1140> A_IWL<1139> A_IWL<1138> A_IWL<1137> A_IWL<1136> A_IWL<1135> A_IWL<1134> A_IWL<1133> A_IWL<1132> A_IWL<1131> A_IWL<1130> A_IWL<1129> A_IWL<1128> A_IWL<1127> A_IWL<1126> A_IWL<1125> A_IWL<1124> A_IWL<1123> A_IWL<1122> A_IWL<1121> A_IWL<1120> A_IWL<1119> A_IWL<1118> A_IWL<1117> A_IWL<1116> A_IWL<1115> A_IWL<1114> A_IWL<1113> A_IWL<1112> A_IWL<1111> A_IWL<1110> A_IWL<1109> A_IWL<1108> A_IWL<1107> A_IWL<1106> A_IWL<1105> A_IWL<1104> A_IWL<1103> A_IWL<1102> A_IWL<1101> A_IWL<1100> A_IWL<1099> A_IWL<1098> A_IWL<1097> A_IWL<1096> A_IWL<1095> A_IWL<1094> A_IWL<1093> A_IWL<1092> A_IWL<1091> A_IWL<1090> A_IWL<1089> A_IWL<1088> A_IWL<1087> A_IWL<1086> A_IWL<1085> A_IWL<1084> A_IWL<1083> A_IWL<1082> A_IWL<1081> A_IWL<1080> A_IWL<1079> A_IWL<1078> A_IWL<1077> A_IWL<1076> A_IWL<1075> A_IWL<1074> A_IWL<1073> A_IWL<1072> A_IWL<1071> A_IWL<1070> A_IWL<1069> A_IWL<1068> A_IWL<1067> A_IWL<1066> A_IWL<1065> A_IWL<1064> A_IWL<1063> A_IWL<1062> A_IWL<1061> A_IWL<1060> A_IWL<1059> A_IWL<1058> A_IWL<1057> A_IWL<1056> A_IWL<1055> A_IWL<1054> A_IWL<1053> A_IWL<1052> A_IWL<1051> A_IWL<1050> A_IWL<1049> A_IWL<1048> A_IWL<1047> A_IWL<1046> A_IWL<1045> A_IWL<1044> A_IWL<1043> A_IWL<1042> A_IWL<1041> A_IWL<1040> A_IWL<1039> A_IWL<1038> A_IWL<1037> A_IWL<1036> A_IWL<1035> A_IWL<1034> A_IWL<1033> A_IWL<1032> A_IWL<1031> A_IWL<1030> A_IWL<1029> A_IWL<1028> A_IWL<1027> A_IWL<1026> A_IWL<1025> A_IWL<1024> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_COLUMN_pcell_0 +XCOL<1> A_BLC<3> A_BLC<2> A_BLC_TOP<3> A_BLC_TOP<2> A_BLT<3> A_BLT<2> A_BLT_TOP<3> A_BLT_TOP<2> A_IWL<511> A_IWL<510> A_IWL<509> A_IWL<508> A_IWL<507> A_IWL<506> A_IWL<505> A_IWL<504> A_IWL<503> A_IWL<502> A_IWL<501> A_IWL<500> A_IWL<499> A_IWL<498> A_IWL<497> A_IWL<496> A_IWL<495> A_IWL<494> A_IWL<493> A_IWL<492> A_IWL<491> A_IWL<490> A_IWL<489> A_IWL<488> A_IWL<487> A_IWL<486> A_IWL<485> A_IWL<484> A_IWL<483> A_IWL<482> A_IWL<481> A_IWL<480> A_IWL<479> A_IWL<478> A_IWL<477> A_IWL<476> A_IWL<475> A_IWL<474> A_IWL<473> A_IWL<472> A_IWL<471> A_IWL<470> A_IWL<469> A_IWL<468> A_IWL<467> A_IWL<466> A_IWL<465> A_IWL<464> A_IWL<463> A_IWL<462> A_IWL<461> A_IWL<460> A_IWL<459> A_IWL<458> A_IWL<457> A_IWL<456> A_IWL<455> A_IWL<454> A_IWL<453> A_IWL<452> A_IWL<451> A_IWL<450> A_IWL<449> A_IWL<448> A_IWL<447> A_IWL<446> A_IWL<445> A_IWL<444> A_IWL<443> A_IWL<442> A_IWL<441> A_IWL<440> A_IWL<439> A_IWL<438> A_IWL<437> A_IWL<436> A_IWL<435> A_IWL<434> A_IWL<433> A_IWL<432> A_IWL<431> A_IWL<430> A_IWL<429> A_IWL<428> A_IWL<427> A_IWL<426> A_IWL<425> A_IWL<424> A_IWL<423> A_IWL<422> A_IWL<421> A_IWL<420> A_IWL<419> A_IWL<418> A_IWL<417> A_IWL<416> A_IWL<415> A_IWL<414> A_IWL<413> A_IWL<412> A_IWL<411> A_IWL<410> A_IWL<409> A_IWL<408> A_IWL<407> A_IWL<406> A_IWL<405> A_IWL<404> A_IWL<403> A_IWL<402> A_IWL<401> A_IWL<400> A_IWL<399> A_IWL<398> A_IWL<397> A_IWL<396> A_IWL<395> A_IWL<394> A_IWL<393> A_IWL<392> A_IWL<391> A_IWL<390> A_IWL<389> A_IWL<388> A_IWL<387> A_IWL<386> A_IWL<385> A_IWL<384> A_IWL<383> A_IWL<382> A_IWL<381> A_IWL<380> A_IWL<379> A_IWL<378> A_IWL<377> A_IWL<376> A_IWL<375> A_IWL<374> A_IWL<373> A_IWL<372> A_IWL<371> A_IWL<370> A_IWL<369> A_IWL<368> A_IWL<367> A_IWL<366> A_IWL<365> A_IWL<364> A_IWL<363> A_IWL<362> A_IWL<361> A_IWL<360> A_IWL<359> A_IWL<358> A_IWL<357> A_IWL<356> A_IWL<355> A_IWL<354> A_IWL<353> A_IWL<352> A_IWL<351> A_IWL<350> A_IWL<349> A_IWL<348> A_IWL<347> A_IWL<346> A_IWL<345> A_IWL<344> A_IWL<343> A_IWL<342> A_IWL<341> A_IWL<340> A_IWL<339> A_IWL<338> A_IWL<337> A_IWL<336> A_IWL<335> A_IWL<334> A_IWL<333> A_IWL<332> A_IWL<331> A_IWL<330> A_IWL<329> A_IWL<328> A_IWL<327> A_IWL<326> A_IWL<325> A_IWL<324> A_IWL<323> A_IWL<322> A_IWL<321> A_IWL<320> A_IWL<319> A_IWL<318> A_IWL<317> A_IWL<316> A_IWL<315> A_IWL<314> A_IWL<313> A_IWL<312> A_IWL<311> A_IWL<310> A_IWL<309> A_IWL<308> A_IWL<307> A_IWL<306> A_IWL<305> A_IWL<304> A_IWL<303> A_IWL<302> A_IWL<301> A_IWL<300> A_IWL<299> A_IWL<298> A_IWL<297> A_IWL<296> A_IWL<295> A_IWL<294> A_IWL<293> A_IWL<292> A_IWL<291> A_IWL<290> A_IWL<289> A_IWL<288> A_IWL<287> A_IWL<286> A_IWL<285> A_IWL<284> A_IWL<283> A_IWL<282> A_IWL<281> A_IWL<280> A_IWL<279> A_IWL<278> A_IWL<277> A_IWL<276> A_IWL<275> A_IWL<274> A_IWL<273> A_IWL<272> A_IWL<271> A_IWL<270> A_IWL<269> A_IWL<268> A_IWL<267> A_IWL<266> A_IWL<265> A_IWL<264> A_IWL<263> A_IWL<262> A_IWL<261> A_IWL<260> A_IWL<259> A_IWL<258> A_IWL<257> A_IWL<256> A_IWL<255> A_IWL<254> A_IWL<253> A_IWL<252> A_IWL<251> A_IWL<250> A_IWL<249> A_IWL<248> A_IWL<247> A_IWL<246> A_IWL<245> A_IWL<244> A_IWL<243> A_IWL<242> A_IWL<241> A_IWL<240> A_IWL<239> A_IWL<238> A_IWL<237> A_IWL<236> A_IWL<235> A_IWL<234> A_IWL<233> A_IWL<232> A_IWL<231> A_IWL<230> A_IWL<229> A_IWL<228> A_IWL<227> A_IWL<226> A_IWL<225> A_IWL<224> A_IWL<223> A_IWL<222> A_IWL<221> A_IWL<220> A_IWL<219> A_IWL<218> A_IWL<217> A_IWL<216> A_IWL<215> A_IWL<214> A_IWL<213> A_IWL<212> A_IWL<211> A_IWL<210> A_IWL<209> A_IWL<208> A_IWL<207> A_IWL<206> A_IWL<205> A_IWL<204> A_IWL<203> A_IWL<202> A_IWL<201> A_IWL<200> A_IWL<199> A_IWL<198> A_IWL<197> A_IWL<196> A_IWL<195> A_IWL<194> A_IWL<193> A_IWL<192> A_IWL<191> A_IWL<190> A_IWL<189> A_IWL<188> A_IWL<187> A_IWL<186> A_IWL<185> A_IWL<184> A_IWL<183> A_IWL<182> A_IWL<181> A_IWL<180> A_IWL<179> A_IWL<178> A_IWL<177> A_IWL<176> A_IWL<175> A_IWL<174> A_IWL<173> A_IWL<172> A_IWL<171> A_IWL<170> A_IWL<169> A_IWL<168> A_IWL<167> A_IWL<166> A_IWL<165> A_IWL<164> A_IWL<163> A_IWL<162> A_IWL<161> A_IWL<160> A_IWL<159> A_IWL<158> A_IWL<157> A_IWL<156> A_IWL<155> A_IWL<154> A_IWL<153> A_IWL<152> A_IWL<151> A_IWL<150> A_IWL<149> A_IWL<148> A_IWL<147> A_IWL<146> A_IWL<145> A_IWL<144> A_IWL<143> A_IWL<142> A_IWL<141> A_IWL<140> A_IWL<139> A_IWL<138> A_IWL<137> A_IWL<136> A_IWL<135> A_IWL<134> A_IWL<133> A_IWL<132> A_IWL<131> A_IWL<130> A_IWL<129> A_IWL<128> A_IWL<127> A_IWL<126> A_IWL<125> A_IWL<124> A_IWL<123> A_IWL<122> A_IWL<121> A_IWL<120> A_IWL<119> A_IWL<118> A_IWL<117> A_IWL<116> A_IWL<115> A_IWL<114> A_IWL<113> A_IWL<112> A_IWL<111> A_IWL<110> A_IWL<109> A_IWL<108> A_IWL<107> A_IWL<106> A_IWL<105> A_IWL<104> A_IWL<103> A_IWL<102> A_IWL<101> A_IWL<100> A_IWL<99> A_IWL<98> A_IWL<97> A_IWL<96> A_IWL<95> A_IWL<94> A_IWL<93> A_IWL<92> A_IWL<91> A_IWL<90> A_IWL<89> A_IWL<88> A_IWL<87> A_IWL<86> A_IWL<85> A_IWL<84> A_IWL<83> A_IWL<82> A_IWL<81> A_IWL<80> A_IWL<79> A_IWL<78> A_IWL<77> A_IWL<76> A_IWL<75> A_IWL<74> A_IWL<73> A_IWL<72> A_IWL<71> A_IWL<70> A_IWL<69> A_IWL<68> A_IWL<67> A_IWL<66> A_IWL<65> A_IWL<64> A_IWL<63> A_IWL<62> A_IWL<61> A_IWL<60> A_IWL<59> A_IWL<58> A_IWL<57> A_IWL<56> A_IWL<55> A_IWL<54> A_IWL<53> A_IWL<52> A_IWL<51> A_IWL<50> A_IWL<49> A_IWL<48> A_IWL<47> A_IWL<46> A_IWL<45> A_IWL<44> A_IWL<43> A_IWL<42> A_IWL<41> A_IWL<40> A_IWL<39> A_IWL<38> A_IWL<37> A_IWL<36> A_IWL<35> A_IWL<34> A_IWL<33> A_IWL<32> A_IWL<31> A_IWL<30> A_IWL<29> A_IWL<28> A_IWL<27> A_IWL<26> A_IWL<25> A_IWL<24> A_IWL<23> A_IWL<22> A_IWL<21> A_IWL<20> A_IWL<19> A_IWL<18> A_IWL<17> A_IWL<16> A_IWL<15> A_IWL<14> A_IWL<13> A_IWL<12> A_IWL<11> A_IWL<10> A_IWL<9> A_IWL<8> A_IWL<7> A_IWL<6> A_IWL<5> A_IWL<4> A_IWL<3> A_IWL<2> A_IWL<1> A_IWL<0> A_IWL<1023> A_IWL<1022> A_IWL<1021> A_IWL<1020> A_IWL<1019> A_IWL<1018> A_IWL<1017> A_IWL<1016> A_IWL<1015> A_IWL<1014> A_IWL<1013> A_IWL<1012> A_IWL<1011> A_IWL<1010> A_IWL<1009> A_IWL<1008> A_IWL<1007> A_IWL<1006> A_IWL<1005> A_IWL<1004> A_IWL<1003> A_IWL<1002> A_IWL<1001> A_IWL<1000> A_IWL<999> A_IWL<998> A_IWL<997> A_IWL<996> A_IWL<995> A_IWL<994> A_IWL<993> A_IWL<992> A_IWL<991> A_IWL<990> A_IWL<989> A_IWL<988> A_IWL<987> A_IWL<986> A_IWL<985> A_IWL<984> A_IWL<983> A_IWL<982> A_IWL<981> A_IWL<980> A_IWL<979> A_IWL<978> A_IWL<977> A_IWL<976> A_IWL<975> A_IWL<974> A_IWL<973> A_IWL<972> A_IWL<971> A_IWL<970> A_IWL<969> A_IWL<968> A_IWL<967> A_IWL<966> A_IWL<965> A_IWL<964> A_IWL<963> A_IWL<962> A_IWL<961> A_IWL<960> A_IWL<959> A_IWL<958> A_IWL<957> A_IWL<956> A_IWL<955> A_IWL<954> A_IWL<953> A_IWL<952> A_IWL<951> A_IWL<950> A_IWL<949> A_IWL<948> A_IWL<947> A_IWL<946> A_IWL<945> A_IWL<944> A_IWL<943> A_IWL<942> A_IWL<941> A_IWL<940> A_IWL<939> A_IWL<938> A_IWL<937> A_IWL<936> A_IWL<935> A_IWL<934> A_IWL<933> A_IWL<932> A_IWL<931> A_IWL<930> A_IWL<929> A_IWL<928> A_IWL<927> A_IWL<926> A_IWL<925> A_IWL<924> A_IWL<923> A_IWL<922> A_IWL<921> A_IWL<920> A_IWL<919> A_IWL<918> A_IWL<917> A_IWL<916> A_IWL<915> A_IWL<914> A_IWL<913> A_IWL<912> A_IWL<911> A_IWL<910> A_IWL<909> A_IWL<908> A_IWL<907> A_IWL<906> A_IWL<905> A_IWL<904> A_IWL<903> A_IWL<902> A_IWL<901> A_IWL<900> A_IWL<899> A_IWL<898> A_IWL<897> A_IWL<896> A_IWL<895> A_IWL<894> A_IWL<893> A_IWL<892> A_IWL<891> A_IWL<890> A_IWL<889> A_IWL<888> A_IWL<887> A_IWL<886> A_IWL<885> A_IWL<884> A_IWL<883> A_IWL<882> A_IWL<881> A_IWL<880> A_IWL<879> A_IWL<878> A_IWL<877> A_IWL<876> A_IWL<875> A_IWL<874> A_IWL<873> A_IWL<872> A_IWL<871> A_IWL<870> A_IWL<869> A_IWL<868> A_IWL<867> A_IWL<866> A_IWL<865> A_IWL<864> A_IWL<863> A_IWL<862> A_IWL<861> A_IWL<860> A_IWL<859> A_IWL<858> A_IWL<857> A_IWL<856> A_IWL<855> A_IWL<854> A_IWL<853> A_IWL<852> A_IWL<851> A_IWL<850> A_IWL<849> A_IWL<848> A_IWL<847> A_IWL<846> A_IWL<845> A_IWL<844> A_IWL<843> A_IWL<842> A_IWL<841> A_IWL<840> A_IWL<839> A_IWL<838> A_IWL<837> A_IWL<836> A_IWL<835> A_IWL<834> A_IWL<833> A_IWL<832> A_IWL<831> A_IWL<830> A_IWL<829> A_IWL<828> A_IWL<827> A_IWL<826> A_IWL<825> A_IWL<824> A_IWL<823> A_IWL<822> A_IWL<821> A_IWL<820> A_IWL<819> A_IWL<818> A_IWL<817> A_IWL<816> A_IWL<815> A_IWL<814> A_IWL<813> A_IWL<812> A_IWL<811> A_IWL<810> A_IWL<809> A_IWL<808> A_IWL<807> A_IWL<806> A_IWL<805> A_IWL<804> A_IWL<803> A_IWL<802> A_IWL<801> A_IWL<800> A_IWL<799> A_IWL<798> A_IWL<797> A_IWL<796> A_IWL<795> A_IWL<794> A_IWL<793> A_IWL<792> A_IWL<791> A_IWL<790> A_IWL<789> A_IWL<788> A_IWL<787> A_IWL<786> A_IWL<785> A_IWL<784> A_IWL<783> A_IWL<782> A_IWL<781> A_IWL<780> A_IWL<779> A_IWL<778> A_IWL<777> A_IWL<776> A_IWL<775> A_IWL<774> A_IWL<773> A_IWL<772> A_IWL<771> A_IWL<770> A_IWL<769> A_IWL<768> A_IWL<767> A_IWL<766> A_IWL<765> A_IWL<764> A_IWL<763> A_IWL<762> A_IWL<761> A_IWL<760> A_IWL<759> A_IWL<758> A_IWL<757> A_IWL<756> A_IWL<755> A_IWL<754> A_IWL<753> A_IWL<752> A_IWL<751> A_IWL<750> A_IWL<749> A_IWL<748> A_IWL<747> A_IWL<746> A_IWL<745> A_IWL<744> A_IWL<743> A_IWL<742> A_IWL<741> A_IWL<740> A_IWL<739> A_IWL<738> A_IWL<737> A_IWL<736> A_IWL<735> A_IWL<734> A_IWL<733> A_IWL<732> A_IWL<731> A_IWL<730> A_IWL<729> A_IWL<728> A_IWL<727> A_IWL<726> A_IWL<725> A_IWL<724> A_IWL<723> A_IWL<722> A_IWL<721> A_IWL<720> A_IWL<719> A_IWL<718> A_IWL<717> A_IWL<716> A_IWL<715> A_IWL<714> A_IWL<713> A_IWL<712> A_IWL<711> A_IWL<710> A_IWL<709> A_IWL<708> A_IWL<707> A_IWL<706> A_IWL<705> A_IWL<704> A_IWL<703> A_IWL<702> A_IWL<701> A_IWL<700> A_IWL<699> A_IWL<698> A_IWL<697> A_IWL<696> A_IWL<695> A_IWL<694> A_IWL<693> A_IWL<692> A_IWL<691> A_IWL<690> A_IWL<689> A_IWL<688> A_IWL<687> A_IWL<686> A_IWL<685> A_IWL<684> A_IWL<683> A_IWL<682> A_IWL<681> A_IWL<680> A_IWL<679> A_IWL<678> A_IWL<677> A_IWL<676> A_IWL<675> A_IWL<674> A_IWL<673> A_IWL<672> A_IWL<671> A_IWL<670> A_IWL<669> A_IWL<668> A_IWL<667> A_IWL<666> A_IWL<665> A_IWL<664> A_IWL<663> A_IWL<662> A_IWL<661> A_IWL<660> A_IWL<659> A_IWL<658> A_IWL<657> A_IWL<656> A_IWL<655> A_IWL<654> A_IWL<653> A_IWL<652> A_IWL<651> A_IWL<650> A_IWL<649> A_IWL<648> A_IWL<647> A_IWL<646> A_IWL<645> A_IWL<644> A_IWL<643> A_IWL<642> A_IWL<641> A_IWL<640> A_IWL<639> A_IWL<638> A_IWL<637> A_IWL<636> A_IWL<635> A_IWL<634> A_IWL<633> A_IWL<632> A_IWL<631> A_IWL<630> A_IWL<629> A_IWL<628> A_IWL<627> A_IWL<626> A_IWL<625> A_IWL<624> A_IWL<623> A_IWL<622> A_IWL<621> A_IWL<620> A_IWL<619> A_IWL<618> A_IWL<617> A_IWL<616> A_IWL<615> A_IWL<614> A_IWL<613> A_IWL<612> A_IWL<611> A_IWL<610> A_IWL<609> A_IWL<608> A_IWL<607> A_IWL<606> A_IWL<605> A_IWL<604> A_IWL<603> A_IWL<602> A_IWL<601> A_IWL<600> A_IWL<599> A_IWL<598> A_IWL<597> A_IWL<596> A_IWL<595> A_IWL<594> A_IWL<593> A_IWL<592> A_IWL<591> A_IWL<590> A_IWL<589> A_IWL<588> A_IWL<587> A_IWL<586> A_IWL<585> A_IWL<584> A_IWL<583> A_IWL<582> A_IWL<581> A_IWL<580> A_IWL<579> A_IWL<578> A_IWL<577> A_IWL<576> A_IWL<575> A_IWL<574> A_IWL<573> A_IWL<572> A_IWL<571> A_IWL<570> A_IWL<569> A_IWL<568> A_IWL<567> A_IWL<566> A_IWL<565> A_IWL<564> A_IWL<563> A_IWL<562> A_IWL<561> A_IWL<560> A_IWL<559> A_IWL<558> A_IWL<557> A_IWL<556> A_IWL<555> A_IWL<554> A_IWL<553> A_IWL<552> A_IWL<551> A_IWL<550> A_IWL<549> A_IWL<548> A_IWL<547> A_IWL<546> A_IWL<545> A_IWL<544> A_IWL<543> A_IWL<542> A_IWL<541> A_IWL<540> A_IWL<539> A_IWL<538> A_IWL<537> A_IWL<536> A_IWL<535> A_IWL<534> A_IWL<533> A_IWL<532> A_IWL<531> A_IWL<530> A_IWL<529> A_IWL<528> A_IWL<527> A_IWL<526> A_IWL<525> A_IWL<524> A_IWL<523> A_IWL<522> A_IWL<521> A_IWL<520> A_IWL<519> A_IWL<518> A_IWL<517> A_IWL<516> A_IWL<515> A_IWL<514> A_IWL<513> A_IWL<512> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_COLUMN_pcell_0 +XCOL<0> A_BLC<1> A_BLC<0> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT<1> A_BLT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_WL<511> A_WL<510> A_WL<509> A_WL<508> A_WL<507> A_WL<506> A_WL<505> A_WL<504> A_WL<503> A_WL<502> A_WL<501> A_WL<500> A_WL<499> A_WL<498> A_WL<497> A_WL<496> A_WL<495> A_WL<494> A_WL<493> A_WL<492> A_WL<491> A_WL<490> A_WL<489> A_WL<488> A_WL<487> A_WL<486> A_WL<485> A_WL<484> A_WL<483> A_WL<482> A_WL<481> A_WL<480> A_WL<479> A_WL<478> A_WL<477> A_WL<476> A_WL<475> A_WL<474> A_WL<473> A_WL<472> A_WL<471> A_WL<470> A_WL<469> A_WL<468> A_WL<467> A_WL<466> A_WL<465> A_WL<464> A_WL<463> A_WL<462> A_WL<461> A_WL<460> A_WL<459> A_WL<458> A_WL<457> A_WL<456> A_WL<455> A_WL<454> A_WL<453> A_WL<452> A_WL<451> A_WL<450> A_WL<449> A_WL<448> A_WL<447> A_WL<446> A_WL<445> A_WL<444> A_WL<443> A_WL<442> A_WL<441> A_WL<440> A_WL<439> A_WL<438> A_WL<437> A_WL<436> A_WL<435> A_WL<434> A_WL<433> A_WL<432> A_WL<431> A_WL<430> A_WL<429> A_WL<428> A_WL<427> A_WL<426> A_WL<425> A_WL<424> A_WL<423> A_WL<422> A_WL<421> A_WL<420> A_WL<419> A_WL<418> A_WL<417> A_WL<416> A_WL<415> A_WL<414> A_WL<413> A_WL<412> A_WL<411> A_WL<410> A_WL<409> A_WL<408> A_WL<407> A_WL<406> A_WL<405> A_WL<404> A_WL<403> A_WL<402> A_WL<401> A_WL<400> A_WL<399> A_WL<398> A_WL<397> A_WL<396> A_WL<395> A_WL<394> A_WL<393> A_WL<392> A_WL<391> A_WL<390> A_WL<389> A_WL<388> A_WL<387> A_WL<386> A_WL<385> A_WL<384> A_WL<383> A_WL<382> A_WL<381> A_WL<380> A_WL<379> A_WL<378> A_WL<377> A_WL<376> A_WL<375> A_WL<374> A_WL<373> A_WL<372> A_WL<371> A_WL<370> A_WL<369> A_WL<368> A_WL<367> A_WL<366> A_WL<365> A_WL<364> A_WL<363> A_WL<362> A_WL<361> A_WL<360> A_WL<359> A_WL<358> A_WL<357> A_WL<356> A_WL<355> A_WL<354> A_WL<353> A_WL<352> A_WL<351> A_WL<350> A_WL<349> A_WL<348> A_WL<347> A_WL<346> A_WL<345> A_WL<344> A_WL<343> A_WL<342> A_WL<341> A_WL<340> A_WL<339> A_WL<338> A_WL<337> A_WL<336> A_WL<335> A_WL<334> A_WL<333> A_WL<332> A_WL<331> A_WL<330> A_WL<329> A_WL<328> A_WL<327> A_WL<326> A_WL<325> A_WL<324> A_WL<323> A_WL<322> A_WL<321> A_WL<320> A_WL<319> A_WL<318> A_WL<317> A_WL<316> A_WL<315> A_WL<314> A_WL<313> A_WL<312> A_WL<311> A_WL<310> A_WL<309> A_WL<308> A_WL<307> A_WL<306> A_WL<305> A_WL<304> A_WL<303> A_WL<302> A_WL<301> A_WL<300> A_WL<299> A_WL<298> A_WL<297> A_WL<296> A_WL<295> A_WL<294> A_WL<293> A_WL<292> A_WL<291> A_WL<290> A_WL<289> A_WL<288> A_WL<287> A_WL<286> A_WL<285> A_WL<284> A_WL<283> A_WL<282> A_WL<281> A_WL<280> A_WL<279> A_WL<278> A_WL<277> A_WL<276> A_WL<275> A_WL<274> A_WL<273> A_WL<272> A_WL<271> A_WL<270> A_WL<269> A_WL<268> A_WL<267> A_WL<266> A_WL<265> A_WL<264> A_WL<263> A_WL<262> A_WL<261> A_WL<260> A_WL<259> A_WL<258> A_WL<257> A_WL<256> A_WL<255> A_WL<254> A_WL<253> A_WL<252> A_WL<251> A_WL<250> A_WL<249> A_WL<248> A_WL<247> A_WL<246> A_WL<245> A_WL<244> A_WL<243> A_WL<242> A_WL<241> A_WL<240> A_WL<239> A_WL<238> A_WL<237> A_WL<236> A_WL<235> A_WL<234> A_WL<233> A_WL<232> A_WL<231> A_WL<230> A_WL<229> A_WL<228> A_WL<227> A_WL<226> A_WL<225> A_WL<224> A_WL<223> A_WL<222> A_WL<221> A_WL<220> A_WL<219> A_WL<218> A_WL<217> A_WL<216> A_WL<215> A_WL<214> A_WL<213> A_WL<212> A_WL<211> A_WL<210> A_WL<209> A_WL<208> A_WL<207> A_WL<206> A_WL<205> A_WL<204> A_WL<203> A_WL<202> A_WL<201> A_WL<200> A_WL<199> A_WL<198> A_WL<197> A_WL<196> A_WL<195> A_WL<194> A_WL<193> A_WL<192> A_WL<191> A_WL<190> A_WL<189> A_WL<188> A_WL<187> A_WL<186> A_WL<185> A_WL<184> A_WL<183> A_WL<182> A_WL<181> A_WL<180> A_WL<179> A_WL<178> A_WL<177> A_WL<176> A_WL<175> A_WL<174> A_WL<173> A_WL<172> A_WL<171> A_WL<170> A_WL<169> A_WL<168> A_WL<167> A_WL<166> A_WL<165> A_WL<164> A_WL<163> A_WL<162> A_WL<161> A_WL<160> A_WL<159> A_WL<158> A_WL<157> A_WL<156> A_WL<155> A_WL<154> A_WL<153> A_WL<152> A_WL<151> A_WL<150> A_WL<149> A_WL<148> A_WL<147> A_WL<146> A_WL<145> A_WL<144> A_WL<143> A_WL<142> A_WL<141> A_WL<140> A_WL<139> A_WL<138> A_WL<137> A_WL<136> A_WL<135> A_WL<134> A_WL<133> A_WL<132> A_WL<131> A_WL<130> A_WL<129> A_WL<128> A_WL<127> A_WL<126> A_WL<125> A_WL<124> A_WL<123> A_WL<122> A_WL<121> A_WL<120> A_WL<119> A_WL<118> A_WL<117> A_WL<116> A_WL<115> A_WL<114> A_WL<113> A_WL<112> A_WL<111> A_WL<110> A_WL<109> A_WL<108> A_WL<107> A_WL<106> A_WL<105> A_WL<104> A_WL<103> A_WL<102> A_WL<101> A_WL<100> A_WL<99> A_WL<98> A_WL<97> A_WL<96> A_WL<95> A_WL<94> A_WL<93> A_WL<92> A_WL<91> A_WL<90> A_WL<89> A_WL<88> A_WL<87> A_WL<86> A_WL<85> A_WL<84> A_WL<83> A_WL<82> A_WL<81> A_WL<80> A_WL<79> A_WL<78> A_WL<77> A_WL<76> A_WL<75> A_WL<74> A_WL<73> A_WL<72> A_WL<71> A_WL<70> A_WL<69> A_WL<68> A_WL<67> A_WL<66> A_WL<65> A_WL<64> A_WL<63> A_WL<62> A_WL<61> A_WL<60> A_WL<59> A_WL<58> A_WL<57> A_WL<56> A_WL<55> A_WL<54> A_WL<53> A_WL<52> A_WL<51> A_WL<50> A_WL<49> A_WL<48> A_WL<47> A_WL<46> A_WL<45> A_WL<44> A_WL<43> A_WL<42> A_WL<41> A_WL<40> A_WL<39> A_WL<38> A_WL<37> A_WL<36> A_WL<35> A_WL<34> A_WL<33> A_WL<32> A_WL<31> A_WL<30> A_WL<29> A_WL<28> A_WL<27> A_WL<26> A_WL<25> A_WL<24> A_WL<23> A_WL<22> A_WL<21> A_WL<20> A_WL<19> A_WL<18> A_WL<17> A_WL<16> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> A_IWL<511> A_IWL<510> A_IWL<509> A_IWL<508> A_IWL<507> A_IWL<506> A_IWL<505> A_IWL<504> A_IWL<503> A_IWL<502> A_IWL<501> A_IWL<500> A_IWL<499> A_IWL<498> A_IWL<497> A_IWL<496> A_IWL<495> A_IWL<494> A_IWL<493> A_IWL<492> A_IWL<491> A_IWL<490> A_IWL<489> A_IWL<488> A_IWL<487> A_IWL<486> A_IWL<485> A_IWL<484> A_IWL<483> A_IWL<482> A_IWL<481> A_IWL<480> A_IWL<479> A_IWL<478> A_IWL<477> A_IWL<476> A_IWL<475> A_IWL<474> A_IWL<473> A_IWL<472> A_IWL<471> A_IWL<470> A_IWL<469> A_IWL<468> A_IWL<467> A_IWL<466> A_IWL<465> A_IWL<464> A_IWL<463> A_IWL<462> A_IWL<461> A_IWL<460> A_IWL<459> A_IWL<458> A_IWL<457> A_IWL<456> A_IWL<455> A_IWL<454> A_IWL<453> A_IWL<452> A_IWL<451> A_IWL<450> A_IWL<449> A_IWL<448> A_IWL<447> A_IWL<446> A_IWL<445> A_IWL<444> A_IWL<443> A_IWL<442> A_IWL<441> A_IWL<440> A_IWL<439> A_IWL<438> A_IWL<437> A_IWL<436> A_IWL<435> A_IWL<434> A_IWL<433> A_IWL<432> A_IWL<431> A_IWL<430> A_IWL<429> A_IWL<428> A_IWL<427> A_IWL<426> A_IWL<425> A_IWL<424> A_IWL<423> A_IWL<422> A_IWL<421> A_IWL<420> A_IWL<419> A_IWL<418> A_IWL<417> A_IWL<416> A_IWL<415> A_IWL<414> A_IWL<413> A_IWL<412> A_IWL<411> A_IWL<410> A_IWL<409> A_IWL<408> A_IWL<407> A_IWL<406> A_IWL<405> A_IWL<404> A_IWL<403> A_IWL<402> A_IWL<401> A_IWL<400> A_IWL<399> A_IWL<398> A_IWL<397> A_IWL<396> A_IWL<395> A_IWL<394> A_IWL<393> A_IWL<392> A_IWL<391> A_IWL<390> A_IWL<389> A_IWL<388> A_IWL<387> A_IWL<386> A_IWL<385> A_IWL<384> A_IWL<383> A_IWL<382> A_IWL<381> A_IWL<380> A_IWL<379> A_IWL<378> A_IWL<377> A_IWL<376> A_IWL<375> A_IWL<374> A_IWL<373> A_IWL<372> A_IWL<371> A_IWL<370> A_IWL<369> A_IWL<368> A_IWL<367> A_IWL<366> A_IWL<365> A_IWL<364> A_IWL<363> A_IWL<362> A_IWL<361> A_IWL<360> A_IWL<359> A_IWL<358> A_IWL<357> A_IWL<356> A_IWL<355> A_IWL<354> A_IWL<353> A_IWL<352> A_IWL<351> A_IWL<350> A_IWL<349> A_IWL<348> A_IWL<347> A_IWL<346> A_IWL<345> A_IWL<344> A_IWL<343> A_IWL<342> A_IWL<341> A_IWL<340> A_IWL<339> A_IWL<338> A_IWL<337> A_IWL<336> A_IWL<335> A_IWL<334> A_IWL<333> A_IWL<332> A_IWL<331> A_IWL<330> A_IWL<329> A_IWL<328> A_IWL<327> A_IWL<326> A_IWL<325> A_IWL<324> A_IWL<323> A_IWL<322> A_IWL<321> A_IWL<320> A_IWL<319> A_IWL<318> A_IWL<317> A_IWL<316> A_IWL<315> A_IWL<314> A_IWL<313> A_IWL<312> A_IWL<311> A_IWL<310> A_IWL<309> A_IWL<308> A_IWL<307> A_IWL<306> A_IWL<305> A_IWL<304> A_IWL<303> A_IWL<302> A_IWL<301> A_IWL<300> A_IWL<299> A_IWL<298> A_IWL<297> A_IWL<296> A_IWL<295> A_IWL<294> A_IWL<293> A_IWL<292> A_IWL<291> A_IWL<290> A_IWL<289> A_IWL<288> A_IWL<287> A_IWL<286> A_IWL<285> A_IWL<284> A_IWL<283> A_IWL<282> A_IWL<281> A_IWL<280> A_IWL<279> A_IWL<278> A_IWL<277> A_IWL<276> A_IWL<275> A_IWL<274> A_IWL<273> A_IWL<272> A_IWL<271> A_IWL<270> A_IWL<269> A_IWL<268> A_IWL<267> A_IWL<266> A_IWL<265> A_IWL<264> A_IWL<263> A_IWL<262> A_IWL<261> A_IWL<260> A_IWL<259> A_IWL<258> A_IWL<257> A_IWL<256> A_IWL<255> A_IWL<254> A_IWL<253> A_IWL<252> A_IWL<251> A_IWL<250> A_IWL<249> A_IWL<248> A_IWL<247> A_IWL<246> A_IWL<245> A_IWL<244> A_IWL<243> A_IWL<242> A_IWL<241> A_IWL<240> A_IWL<239> A_IWL<238> A_IWL<237> A_IWL<236> A_IWL<235> A_IWL<234> A_IWL<233> A_IWL<232> A_IWL<231> A_IWL<230> A_IWL<229> A_IWL<228> A_IWL<227> A_IWL<226> A_IWL<225> A_IWL<224> A_IWL<223> A_IWL<222> A_IWL<221> A_IWL<220> A_IWL<219> A_IWL<218> A_IWL<217> A_IWL<216> A_IWL<215> A_IWL<214> A_IWL<213> A_IWL<212> A_IWL<211> A_IWL<210> A_IWL<209> A_IWL<208> A_IWL<207> A_IWL<206> A_IWL<205> A_IWL<204> A_IWL<203> A_IWL<202> A_IWL<201> A_IWL<200> A_IWL<199> A_IWL<198> A_IWL<197> A_IWL<196> A_IWL<195> A_IWL<194> A_IWL<193> A_IWL<192> A_IWL<191> A_IWL<190> A_IWL<189> A_IWL<188> A_IWL<187> A_IWL<186> A_IWL<185> A_IWL<184> A_IWL<183> A_IWL<182> A_IWL<181> A_IWL<180> A_IWL<179> A_IWL<178> A_IWL<177> A_IWL<176> A_IWL<175> A_IWL<174> A_IWL<173> A_IWL<172> A_IWL<171> A_IWL<170> A_IWL<169> A_IWL<168> A_IWL<167> A_IWL<166> A_IWL<165> A_IWL<164> A_IWL<163> A_IWL<162> A_IWL<161> A_IWL<160> A_IWL<159> A_IWL<158> A_IWL<157> A_IWL<156> A_IWL<155> A_IWL<154> A_IWL<153> A_IWL<152> A_IWL<151> A_IWL<150> A_IWL<149> A_IWL<148> A_IWL<147> A_IWL<146> A_IWL<145> A_IWL<144> A_IWL<143> A_IWL<142> A_IWL<141> A_IWL<140> A_IWL<139> A_IWL<138> A_IWL<137> A_IWL<136> A_IWL<135> A_IWL<134> A_IWL<133> A_IWL<132> A_IWL<131> A_IWL<130> A_IWL<129> A_IWL<128> A_IWL<127> A_IWL<126> A_IWL<125> A_IWL<124> A_IWL<123> A_IWL<122> A_IWL<121> A_IWL<120> A_IWL<119> A_IWL<118> A_IWL<117> A_IWL<116> A_IWL<115> A_IWL<114> A_IWL<113> A_IWL<112> A_IWL<111> A_IWL<110> A_IWL<109> A_IWL<108> A_IWL<107> A_IWL<106> A_IWL<105> A_IWL<104> A_IWL<103> A_IWL<102> A_IWL<101> A_IWL<100> A_IWL<99> A_IWL<98> A_IWL<97> A_IWL<96> A_IWL<95> A_IWL<94> A_IWL<93> A_IWL<92> A_IWL<91> A_IWL<90> A_IWL<89> A_IWL<88> A_IWL<87> A_IWL<86> A_IWL<85> A_IWL<84> A_IWL<83> A_IWL<82> A_IWL<81> A_IWL<80> A_IWL<79> A_IWL<78> A_IWL<77> A_IWL<76> A_IWL<75> A_IWL<74> A_IWL<73> A_IWL<72> A_IWL<71> A_IWL<70> A_IWL<69> A_IWL<68> A_IWL<67> A_IWL<66> A_IWL<65> A_IWL<64> A_IWL<63> A_IWL<62> A_IWL<61> A_IWL<60> A_IWL<59> A_IWL<58> A_IWL<57> A_IWL<56> A_IWL<55> A_IWL<54> A_IWL<53> A_IWL<52> A_IWL<51> A_IWL<50> A_IWL<49> A_IWL<48> A_IWL<47> A_IWL<46> A_IWL<45> A_IWL<44> A_IWL<43> A_IWL<42> A_IWL<41> A_IWL<40> A_IWL<39> A_IWL<38> A_IWL<37> A_IWL<36> A_IWL<35> A_IWL<34> A_IWL<33> A_IWL<32> A_IWL<31> A_IWL<30> A_IWL<29> A_IWL<28> A_IWL<27> A_IWL<26> A_IWL<25> A_IWL<24> A_IWL<23> A_IWL<22> A_IWL<21> A_IWL<20> A_IWL<19> A_IWL<18> A_IWL<17> A_IWL<16> A_IWL<15> A_IWL<14> A_IWL<13> A_IWL<12> A_IWL<11> A_IWL<10> A_IWL<9> A_IWL<8> A_IWL<7> A_IWL<6> A_IWL<5> A_IWL<4> A_IWL<3> A_IWL<2> A_IWL<1> A_IWL<0> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_COLUMN_pcell_0 +.ENDS + + + + +.SUBCKT RM_IHPSG13_4096x16_c3_1P_DLY_pcell_2 A Z VDD VSS + XIDL<3> D<7> Z VDD VSS / RSC_IHPSG13_CDLYX1 + XIDL<2> D<6> D<7> VDD VSS / RSC_IHPSG13_CDLYX1 + XIDL<1> D<5> D<6> VDD VSS / RSC_IHPSG13_CDLYX1 + XIDM<5> D<4> D<5> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<4> D<3> D<4> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY +.ENDS + + +.SUBCKT RM_IHPSG13_4096x16_c3_1P_DLY_pcell_3 A Z VDD VSS + XIDL<7> D<7> Z VDD VSS / RSC_IHPSG13_CDLYX1 + XIDL<6> D<6> D<7> VDD VSS / RSC_IHPSG13_CDLYX1 + XIDL<5> D<5> D<6> VDD VSS / RSC_IHPSG13_CDLYX1 + XIDL<4> D<4> D<5> VDD VSS / RSC_IHPSG13_CDLYX1 + XIDL<3> D<3> D<4> VDD VSS / RSC_IHPSG13_CDLYX1 + XIDL<2> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1 + XIDL<1> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1 + XIDM A D<1> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY +.ENDS + + + +.SUBCKT RM_IHPSG13_1P_4096x16_c3_bm_bist A_ADDR<11> A_ADDR<10> A_ADDR<9> A_ADDR<8> A_ADDR<7> A_ADDR<6> A_ADDR<5> A_ADDR<4> A_ADDR<3> A_ADDR<2> A_ADDR<1> A_ADDR<0> A_BIST_ADDR<11> A_BIST_ADDR<10> A_BIST_ADDR<9> A_BIST_ADDR<8> A_BIST_ADDR<7> A_BIST_ADDR<6> A_BIST_ADDR<5> A_BIST_ADDR<4> A_BIST_ADDR<3> A_BIST_ADDR<2> A_BIST_ADDR<1> A_BIST_ADDR<0> A_BIST_BM<15> A_BIST_BM<14> A_BIST_BM<13> A_BIST_BM<12> A_BIST_BM<11> A_BIST_BM<10> A_BIST_BM<9> A_BIST_BM<8> A_BIST_BM<7> A_BIST_BM<6> A_BIST_BM<5> A_BIST_BM<4> A_BIST_BM<3> A_BIST_BM<2> A_BIST_BM<1> A_BIST_BM<0> A_BIST_CLK A_BIST_DIN<15> A_BIST_DIN<14> A_BIST_DIN<13> A_BIST_DIN<12> A_BIST_DIN<11> A_BIST_DIN<10> A_BIST_DIN<9> A_BIST_DIN<8> A_BIST_DIN<7> A_BIST_DIN<6> A_BIST_DIN<5> A_BIST_DIN<4> A_BIST_DIN<3> A_BIST_DIN<2> A_BIST_DIN<1> A_BIST_DIN<0> A_BIST_EN A_BIST_MEN A_BIST_REN A_BIST_WEN A_BM<15> A_BM<14> A_BM<13> A_BM<12> A_BM<11> A_BM<10> A_BM<9> A_BM<8> A_BM<7> A_BM<6> A_BM<5> A_BM<4> A_BM<3> A_BM<2> A_BM<1> A_BM<0> A_CLK A_DIN<15> A_DIN<14> A_DIN<13> A_DIN<12> A_DIN<11> A_DIN<10> A_DIN<9> A_DIN<8> A_DIN<7> A_DIN<6> A_DIN<5> A_DIN<4> A_DIN<3> A_DIN<2> A_DIN<1> A_DIN<0> A_DLY A_DOUT<15> A_DOUT<14> A_DOUT<13> A_DOUT<12> A_DOUT<11> A_DOUT<10> A_DOUT<9> A_DOUT<8> A_DOUT<7> A_DOUT<6> A_DOUT<5> A_DOUT<4> A_DOUT<3> A_DOUT<2> A_DOUT<1> A_DOUT<0> A_MEN A_REN A_WEN VDD! VDDARRAY! VSS! + + +XRAM<1> a_blc_r<63> a_blc_r<62> a_blc_r<61> a_blc_r<60> a_blc_r<59> a_blc_r<58> a_blc_r<57> a_blc_r<56> a_blc_r<55> a_blc_r<54> a_blc_r<53> a_blc_r<52> a_blc_r<51> a_blc_r<50> a_blc_r<49> a_blc_r<48> a_blc_r<47> a_blc_r<46> a_blc_r<45> a_blc_r<44> a_blc_r<43> a_blc_r<42> a_blc_r<41> a_blc_r<40> a_blc_r<39> a_blc_r<38> a_blc_r<37> a_blc_r<36> a_blc_r<35> a_blc_r<34> a_blc_r<33> a_blc_r<32> a_blc_r<31> a_blc_r<30> a_blc_r<29> a_blc_r<28> a_blc_r<27> a_blc_r<26> a_blc_r<25> a_blc_r<24> a_blc_r<23> a_blc_r<22> a_blc_r<21> a_blc_r<20> a_blc_r<19> a_blc_r<18> a_blc_r<17> a_blc_r<16> a_blc_r<15> a_blc_r<14> a_blc_r<13> a_blc_r<12> a_blc_r<11> a_blc_r<10> a_blc_r<9> a_blc_r<8> a_blc_r<7> a_blc_r<6> a_blc_r<5> a_blc_r<4> a_blc_r<3> a_blc_r<2> a_blc_r<1> a_blc_r<0> a_blt_r<63> a_blt_r<62> a_blt_r<61> a_blt_r<60> a_blt_r<59> a_blt_r<58> a_blt_r<57> a_blt_r<56> a_blt_r<55> a_blt_r<54> a_blt_r<53> a_blt_r<52> a_blt_r<51> a_blt_r<50> a_blt_r<49> a_blt_r<48> a_blt_r<47> a_blt_r<46> a_blt_r<45> a_blt_r<44> a_blt_r<43> a_blt_r<42> a_blt_r<41> a_blt_r<40> a_blt_r<39> a_blt_r<38> a_blt_r<37> a_blt_r<36> a_blt_r<35> a_blt_r<34> a_blt_r<33> a_blt_r<32> a_blt_r<31> a_blt_r<30> a_blt_r<29> a_blt_r<28> a_blt_r<27> a_blt_r<26> a_blt_r<25> a_blt_r<24> a_blt_r<23> a_blt_r<22> a_blt_r<21> a_blt_r<20> a_blt_r<19> a_blt_r<18> a_blt_r<17> a_blt_r<16> a_blt_r<15> a_blt_r<14> a_blt_r<13> a_blt_r<12> a_blt_r<11> a_blt_r<10> a_blt_r<9> a_blt_r<8> a_blt_r<7> a_blt_r<6> a_blt_r<5> a_blt_r<4> a_blt_r<3> a_blt_r<2> a_blt_r<1> a_blt_r<0> a_wl_r<511> a_wl_r<510> a_wl_r<509> a_wl_r<508> a_wl_r<507> a_wl_r<506> a_wl_r<505> a_wl_r<504> a_wl_r<503> a_wl_r<502> a_wl_r<501> a_wl_r<500> a_wl_r<499> a_wl_r<498> a_wl_r<497> a_wl_r<496> a_wl_r<495> a_wl_r<494> a_wl_r<493> a_wl_r<492> a_wl_r<491> a_wl_r<490> a_wl_r<489> a_wl_r<488> a_wl_r<487> a_wl_r<486> a_wl_r<485> a_wl_r<484> a_wl_r<483> a_wl_r<482> a_wl_r<481> a_wl_r<480> a_wl_r<479> a_wl_r<478> a_wl_r<477> a_wl_r<476> a_wl_r<475> a_wl_r<474> a_wl_r<473> a_wl_r<472> a_wl_r<471> a_wl_r<470> a_wl_r<469> a_wl_r<468> a_wl_r<467> a_wl_r<466> a_wl_r<465> a_wl_r<464> a_wl_r<463> a_wl_r<462> a_wl_r<461> a_wl_r<460> a_wl_r<459> a_wl_r<458> a_wl_r<457> a_wl_r<456> a_wl_r<455> a_wl_r<454> a_wl_r<453> a_wl_r<452> a_wl_r<451> a_wl_r<450> a_wl_r<449> a_wl_r<448> a_wl_r<447> a_wl_r<446> a_wl_r<445> a_wl_r<444> a_wl_r<443> a_wl_r<442> a_wl_r<441> a_wl_r<440> a_wl_r<439> a_wl_r<438> a_wl_r<437> a_wl_r<436> a_wl_r<435> a_wl_r<434> a_wl_r<433> a_wl_r<432> a_wl_r<431> a_wl_r<430> a_wl_r<429> a_wl_r<428> a_wl_r<427> a_wl_r<426> a_wl_r<425> a_wl_r<424> a_wl_r<423> a_wl_r<422> a_wl_r<421> a_wl_r<420> a_wl_r<419> a_wl_r<418> a_wl_r<417> a_wl_r<416> a_wl_r<415> a_wl_r<414> a_wl_r<413> a_wl_r<412> a_wl_r<411> a_wl_r<410> a_wl_r<409> a_wl_r<408> a_wl_r<407> a_wl_r<406> a_wl_r<405> a_wl_r<404> a_wl_r<403> a_wl_r<402> a_wl_r<401> a_wl_r<400> a_wl_r<399> a_wl_r<398> a_wl_r<397> a_wl_r<396> a_wl_r<395> a_wl_r<394> a_wl_r<393> a_wl_r<392> a_wl_r<391> a_wl_r<390> a_wl_r<389> a_wl_r<388> a_wl_r<387> a_wl_r<386> a_wl_r<385> a_wl_r<384> a_wl_r<383> a_wl_r<382> a_wl_r<381> a_wl_r<380> a_wl_r<379> a_wl_r<378> a_wl_r<377> a_wl_r<376> a_wl_r<375> a_wl_r<374> a_wl_r<373> a_wl_r<372> a_wl_r<371> a_wl_r<370> a_wl_r<369> a_wl_r<368> a_wl_r<367> a_wl_r<366> a_wl_r<365> a_wl_r<364> a_wl_r<363> a_wl_r<362> a_wl_r<361> a_wl_r<360> a_wl_r<359> a_wl_r<358> a_wl_r<357> a_wl_r<356> a_wl_r<355> a_wl_r<354> a_wl_r<353> a_wl_r<352> a_wl_r<351> a_wl_r<350> a_wl_r<349> a_wl_r<348> a_wl_r<347> a_wl_r<346> a_wl_r<345> a_wl_r<344> a_wl_r<343> a_wl_r<342> a_wl_r<341> a_wl_r<340> a_wl_r<339> a_wl_r<338> a_wl_r<337> a_wl_r<336> a_wl_r<335> a_wl_r<334> a_wl_r<333> a_wl_r<332> a_wl_r<331> a_wl_r<330> a_wl_r<329> a_wl_r<328> a_wl_r<327> a_wl_r<326> a_wl_r<325> a_wl_r<324> a_wl_r<323> a_wl_r<322> a_wl_r<321> a_wl_r<320> a_wl_r<319> a_wl_r<318> a_wl_r<317> a_wl_r<316> a_wl_r<315> a_wl_r<314> a_wl_r<313> a_wl_r<312> a_wl_r<311> a_wl_r<310> a_wl_r<309> a_wl_r<308> a_wl_r<307> a_wl_r<306> a_wl_r<305> a_wl_r<304> a_wl_r<303> a_wl_r<302> a_wl_r<301> a_wl_r<300> a_wl_r<299> a_wl_r<298> a_wl_r<297> a_wl_r<296> a_wl_r<295> a_wl_r<294> a_wl_r<293> a_wl_r<292> a_wl_r<291> a_wl_r<290> a_wl_r<289> a_wl_r<288> a_wl_r<287> a_wl_r<286> a_wl_r<285> a_wl_r<284> a_wl_r<283> a_wl_r<282> a_wl_r<281> a_wl_r<280> a_wl_r<279> a_wl_r<278> a_wl_r<277> a_wl_r<276> a_wl_r<275> a_wl_r<274> a_wl_r<273> a_wl_r<272> a_wl_r<271> a_wl_r<270> a_wl_r<269> a_wl_r<268> a_wl_r<267> a_wl_r<266> a_wl_r<265> a_wl_r<264> a_wl_r<263> a_wl_r<262> a_wl_r<261> a_wl_r<260> a_wl_r<259> a_wl_r<258> a_wl_r<257> a_wl_r<256> a_wl_r<255> a_wl_r<254> a_wl_r<253> a_wl_r<252> a_wl_r<251> a_wl_r<250> a_wl_r<249> a_wl_r<248> a_wl_r<247> a_wl_r<246> a_wl_r<245> a_wl_r<244> a_wl_r<243> a_wl_r<242> a_wl_r<241> a_wl_r<240> a_wl_r<239> a_wl_r<238> a_wl_r<237> a_wl_r<236> a_wl_r<235> a_wl_r<234> a_wl_r<233> a_wl_r<232> a_wl_r<231> a_wl_r<230> a_wl_r<229> a_wl_r<228> a_wl_r<227> a_wl_r<226> a_wl_r<225> a_wl_r<224> a_wl_r<223> a_wl_r<222> a_wl_r<221> a_wl_r<220> a_wl_r<219> a_wl_r<218> a_wl_r<217> a_wl_r<216> a_wl_r<215> a_wl_r<214> a_wl_r<213> a_wl_r<212> a_wl_r<211> a_wl_r<210> a_wl_r<209> a_wl_r<208> a_wl_r<207> a_wl_r<206> a_wl_r<205> a_wl_r<204> a_wl_r<203> a_wl_r<202> a_wl_r<201> a_wl_r<200> a_wl_r<199> a_wl_r<198> a_wl_r<197> a_wl_r<196> a_wl_r<195> a_wl_r<194> a_wl_r<193> a_wl_r<192> a_wl_r<191> a_wl_r<190> a_wl_r<189> a_wl_r<188> a_wl_r<187> a_wl_r<186> a_wl_r<185> a_wl_r<184> a_wl_r<183> a_wl_r<182> a_wl_r<181> a_wl_r<180> a_wl_r<179> a_wl_r<178> a_wl_r<177> a_wl_r<176> a_wl_r<175> a_wl_r<174> a_wl_r<173> a_wl_r<172> a_wl_r<171> a_wl_r<170> a_wl_r<169> a_wl_r<168> a_wl_r<167> a_wl_r<166> a_wl_r<165> a_wl_r<164> a_wl_r<163> a_wl_r<162> a_wl_r<161> a_wl_r<160> a_wl_r<159> a_wl_r<158> a_wl_r<157> a_wl_r<156> a_wl_r<155> a_wl_r<154> a_wl_r<153> a_wl_r<152> a_wl_r<151> a_wl_r<150> a_wl_r<149> a_wl_r<148> a_wl_r<147> a_wl_r<146> a_wl_r<145> a_wl_r<144> a_wl_r<143> a_wl_r<142> a_wl_r<141> a_wl_r<140> a_wl_r<139> a_wl_r<138> a_wl_r<137> a_wl_r<136> a_wl_r<135> a_wl_r<134> a_wl_r<133> a_wl_r<132> a_wl_r<131> a_wl_r<130> a_wl_r<129> a_wl_r<128> a_wl_r<127> a_wl_r<126> a_wl_r<125> a_wl_r<124> a_wl_r<123> a_wl_r<122> a_wl_r<121> a_wl_r<120> a_wl_r<119> a_wl_r<118> a_wl_r<117> a_wl_r<116> a_wl_r<115> a_wl_r<114> a_wl_r<113> a_wl_r<112> a_wl_r<111> a_wl_r<110> a_wl_r<109> a_wl_r<108> a_wl_r<107> a_wl_r<106> a_wl_r<105> a_wl_r<104> a_wl_r<103> a_wl_r<102> a_wl_r<101> a_wl_r<100> a_wl_r<99> a_wl_r<98> a_wl_r<97> a_wl_r<96> a_wl_r<95> a_wl_r<94> a_wl_r<93> a_wl_r<92> a_wl_r<91> a_wl_r<90> a_wl_r<89> a_wl_r<88> a_wl_r<87> a_wl_r<86> a_wl_r<85> a_wl_r<84> a_wl_r<83> a_wl_r<82> a_wl_r<81> a_wl_r<80> a_wl_r<79> a_wl_r<78> a_wl_r<77> a_wl_r<76> a_wl_r<75> a_wl_r<74> a_wl_r<73> a_wl_r<72> a_wl_r<71> a_wl_r<70> a_wl_r<69> a_wl_r<68> a_wl_r<67> a_wl_r<66> a_wl_r<65> a_wl_r<64> a_wl_r<63> a_wl_r<62> a_wl_r<61> a_wl_r<60> a_wl_r<59> a_wl_r<58> a_wl_r<57> a_wl_r<56> a_wl_r<55> a_wl_r<54> a_wl_r<53> a_wl_r<52> a_wl_r<51> a_wl_r<50> a_wl_r<49> a_wl_r<48> a_wl_r<47> a_wl_r<46> a_wl_r<45> a_wl_r<44> a_wl_r<43> a_wl_r<42> a_wl_r<41> a_wl_r<40> a_wl_r<39> a_wl_r<38> a_wl_r<37> a_wl_r<36> a_wl_r<35> a_wl_r<34> a_wl_r<33> a_wl_r<32> a_wl_r<31> a_wl_r<30> a_wl_r<29> a_wl_r<28> a_wl_r<27> a_wl_r<26> a_wl_r<25> a_wl_r<24> a_wl_r<23> a_wl_r<22> a_wl_r<21> a_wl_r<20> a_wl_r<19> a_wl_r<18> a_wl_r<17> a_wl_r<16> a_wl_r<15> a_wl_r<14> a_wl_r<13> a_wl_r<12> a_wl_r<11> a_wl_r<10> a_wl_r<9> a_wl_r<8> a_wl_r<7> a_wl_r<6> a_wl_r<5> a_wl_r<4> a_wl_r<3> a_wl_r<2> a_wl_r<1> a_wl_r<0> VDDARRAY! VSS! / RM_IHPSG13_4096x16_c3_1P_MATRIX_pcell_1 +XRAM<0> a_blc_l<63> a_blc_l<62> a_blc_l<61> a_blc_l<60> a_blc_l<59> a_blc_l<58> a_blc_l<57> a_blc_l<56> a_blc_l<55> a_blc_l<54> a_blc_l<53> a_blc_l<52> a_blc_l<51> a_blc_l<50> a_blc_l<49> a_blc_l<48> a_blc_l<47> a_blc_l<46> a_blc_l<45> a_blc_l<44> a_blc_l<43> a_blc_l<42> a_blc_l<41> a_blc_l<40> a_blc_l<39> a_blc_l<38> a_blc_l<37> a_blc_l<36> a_blc_l<35> a_blc_l<34> a_blc_l<33> a_blc_l<32> a_blc_l<31> a_blc_l<30> a_blc_l<29> a_blc_l<28> a_blc_l<27> a_blc_l<26> a_blc_l<25> a_blc_l<24> a_blc_l<23> a_blc_l<22> a_blc_l<21> a_blc_l<20> a_blc_l<19> a_blc_l<18> a_blc_l<17> a_blc_l<16> a_blc_l<15> a_blc_l<14> a_blc_l<13> a_blc_l<12> a_blc_l<11> a_blc_l<10> a_blc_l<9> a_blc_l<8> a_blc_l<7> a_blc_l<6> a_blc_l<5> a_blc_l<4> a_blc_l<3> a_blc_l<2> a_blc_l<1> a_blc_l<0> a_blt_l<63> a_blt_l<62> a_blt_l<61> a_blt_l<60> a_blt_l<59> a_blt_l<58> a_blt_l<57> a_blt_l<56> a_blt_l<55> a_blt_l<54> a_blt_l<53> a_blt_l<52> a_blt_l<51> a_blt_l<50> a_blt_l<49> a_blt_l<48> a_blt_l<47> a_blt_l<46> a_blt_l<45> a_blt_l<44> a_blt_l<43> a_blt_l<42> a_blt_l<41> a_blt_l<40> a_blt_l<39> a_blt_l<38> a_blt_l<37> a_blt_l<36> a_blt_l<35> a_blt_l<34> a_blt_l<33> a_blt_l<32> a_blt_l<31> a_blt_l<30> a_blt_l<29> a_blt_l<28> a_blt_l<27> a_blt_l<26> a_blt_l<25> a_blt_l<24> a_blt_l<23> a_blt_l<22> a_blt_l<21> a_blt_l<20> a_blt_l<19> a_blt_l<18> a_blt_l<17> a_blt_l<16> a_blt_l<15> a_blt_l<14> a_blt_l<13> a_blt_l<12> a_blt_l<11> a_blt_l<10> a_blt_l<9> a_blt_l<8> a_blt_l<7> a_blt_l<6> a_blt_l<5> a_blt_l<4> a_blt_l<3> a_blt_l<2> a_blt_l<1> a_blt_l<0> a_wl_l<511> a_wl_l<510> a_wl_l<509> a_wl_l<508> a_wl_l<507> a_wl_l<506> a_wl_l<505> a_wl_l<504> a_wl_l<503> a_wl_l<502> a_wl_l<501> a_wl_l<500> a_wl_l<499> a_wl_l<498> a_wl_l<497> a_wl_l<496> a_wl_l<495> a_wl_l<494> a_wl_l<493> a_wl_l<492> a_wl_l<491> a_wl_l<490> a_wl_l<489> a_wl_l<488> a_wl_l<487> a_wl_l<486> a_wl_l<485> a_wl_l<484> a_wl_l<483> a_wl_l<482> a_wl_l<481> a_wl_l<480> a_wl_l<479> a_wl_l<478> a_wl_l<477> a_wl_l<476> a_wl_l<475> a_wl_l<474> a_wl_l<473> a_wl_l<472> a_wl_l<471> a_wl_l<470> a_wl_l<469> a_wl_l<468> a_wl_l<467> a_wl_l<466> a_wl_l<465> a_wl_l<464> a_wl_l<463> a_wl_l<462> a_wl_l<461> a_wl_l<460> a_wl_l<459> a_wl_l<458> a_wl_l<457> a_wl_l<456> a_wl_l<455> a_wl_l<454> a_wl_l<453> a_wl_l<452> a_wl_l<451> a_wl_l<450> a_wl_l<449> a_wl_l<448> a_wl_l<447> a_wl_l<446> a_wl_l<445> a_wl_l<444> a_wl_l<443> a_wl_l<442> a_wl_l<441> a_wl_l<440> a_wl_l<439> a_wl_l<438> a_wl_l<437> a_wl_l<436> a_wl_l<435> a_wl_l<434> a_wl_l<433> a_wl_l<432> a_wl_l<431> a_wl_l<430> a_wl_l<429> a_wl_l<428> a_wl_l<427> a_wl_l<426> a_wl_l<425> a_wl_l<424> a_wl_l<423> a_wl_l<422> a_wl_l<421> a_wl_l<420> a_wl_l<419> a_wl_l<418> a_wl_l<417> a_wl_l<416> a_wl_l<415> a_wl_l<414> a_wl_l<413> a_wl_l<412> a_wl_l<411> a_wl_l<410> a_wl_l<409> a_wl_l<408> a_wl_l<407> a_wl_l<406> a_wl_l<405> a_wl_l<404> a_wl_l<403> a_wl_l<402> a_wl_l<401> a_wl_l<400> a_wl_l<399> a_wl_l<398> a_wl_l<397> a_wl_l<396> a_wl_l<395> a_wl_l<394> a_wl_l<393> a_wl_l<392> a_wl_l<391> a_wl_l<390> a_wl_l<389> a_wl_l<388> a_wl_l<387> a_wl_l<386> a_wl_l<385> a_wl_l<384> a_wl_l<383> a_wl_l<382> a_wl_l<381> a_wl_l<380> a_wl_l<379> a_wl_l<378> a_wl_l<377> a_wl_l<376> a_wl_l<375> a_wl_l<374> a_wl_l<373> a_wl_l<372> a_wl_l<371> a_wl_l<370> a_wl_l<369> a_wl_l<368> a_wl_l<367> a_wl_l<366> a_wl_l<365> a_wl_l<364> a_wl_l<363> a_wl_l<362> a_wl_l<361> a_wl_l<360> a_wl_l<359> a_wl_l<358> a_wl_l<357> a_wl_l<356> a_wl_l<355> a_wl_l<354> a_wl_l<353> a_wl_l<352> a_wl_l<351> a_wl_l<350> a_wl_l<349> a_wl_l<348> a_wl_l<347> a_wl_l<346> a_wl_l<345> a_wl_l<344> a_wl_l<343> a_wl_l<342> a_wl_l<341> a_wl_l<340> a_wl_l<339> a_wl_l<338> a_wl_l<337> a_wl_l<336> a_wl_l<335> a_wl_l<334> a_wl_l<333> a_wl_l<332> a_wl_l<331> a_wl_l<330> a_wl_l<329> a_wl_l<328> a_wl_l<327> a_wl_l<326> a_wl_l<325> a_wl_l<324> a_wl_l<323> a_wl_l<322> a_wl_l<321> a_wl_l<320> a_wl_l<319> a_wl_l<318> a_wl_l<317> a_wl_l<316> a_wl_l<315> a_wl_l<314> a_wl_l<313> a_wl_l<312> a_wl_l<311> a_wl_l<310> a_wl_l<309> a_wl_l<308> a_wl_l<307> a_wl_l<306> a_wl_l<305> a_wl_l<304> a_wl_l<303> a_wl_l<302> a_wl_l<301> a_wl_l<300> a_wl_l<299> a_wl_l<298> a_wl_l<297> a_wl_l<296> a_wl_l<295> a_wl_l<294> a_wl_l<293> a_wl_l<292> a_wl_l<291> a_wl_l<290> a_wl_l<289> a_wl_l<288> a_wl_l<287> a_wl_l<286> a_wl_l<285> a_wl_l<284> a_wl_l<283> a_wl_l<282> a_wl_l<281> a_wl_l<280> a_wl_l<279> a_wl_l<278> a_wl_l<277> a_wl_l<276> a_wl_l<275> a_wl_l<274> a_wl_l<273> a_wl_l<272> a_wl_l<271> a_wl_l<270> a_wl_l<269> a_wl_l<268> a_wl_l<267> a_wl_l<266> a_wl_l<265> a_wl_l<264> a_wl_l<263> a_wl_l<262> a_wl_l<261> a_wl_l<260> a_wl_l<259> a_wl_l<258> a_wl_l<257> a_wl_l<256> a_wl_l<255> a_wl_l<254> a_wl_l<253> a_wl_l<252> a_wl_l<251> a_wl_l<250> a_wl_l<249> a_wl_l<248> a_wl_l<247> a_wl_l<246> a_wl_l<245> a_wl_l<244> a_wl_l<243> a_wl_l<242> a_wl_l<241> a_wl_l<240> a_wl_l<239> a_wl_l<238> a_wl_l<237> a_wl_l<236> a_wl_l<235> a_wl_l<234> a_wl_l<233> a_wl_l<232> a_wl_l<231> a_wl_l<230> a_wl_l<229> a_wl_l<228> a_wl_l<227> a_wl_l<226> a_wl_l<225> a_wl_l<224> a_wl_l<223> a_wl_l<222> a_wl_l<221> a_wl_l<220> a_wl_l<219> a_wl_l<218> a_wl_l<217> a_wl_l<216> a_wl_l<215> a_wl_l<214> a_wl_l<213> a_wl_l<212> a_wl_l<211> a_wl_l<210> a_wl_l<209> a_wl_l<208> a_wl_l<207> a_wl_l<206> a_wl_l<205> a_wl_l<204> a_wl_l<203> a_wl_l<202> a_wl_l<201> a_wl_l<200> a_wl_l<199> a_wl_l<198> a_wl_l<197> a_wl_l<196> a_wl_l<195> a_wl_l<194> a_wl_l<193> a_wl_l<192> a_wl_l<191> a_wl_l<190> a_wl_l<189> a_wl_l<188> a_wl_l<187> a_wl_l<186> a_wl_l<185> a_wl_l<184> a_wl_l<183> a_wl_l<182> a_wl_l<181> a_wl_l<180> a_wl_l<179> a_wl_l<178> a_wl_l<177> a_wl_l<176> a_wl_l<175> a_wl_l<174> a_wl_l<173> a_wl_l<172> a_wl_l<171> a_wl_l<170> a_wl_l<169> a_wl_l<168> a_wl_l<167> a_wl_l<166> a_wl_l<165> a_wl_l<164> a_wl_l<163> a_wl_l<162> a_wl_l<161> a_wl_l<160> a_wl_l<159> a_wl_l<158> a_wl_l<157> a_wl_l<156> a_wl_l<155> a_wl_l<154> a_wl_l<153> a_wl_l<152> a_wl_l<151> a_wl_l<150> a_wl_l<149> a_wl_l<148> a_wl_l<147> a_wl_l<146> a_wl_l<145> a_wl_l<144> a_wl_l<143> a_wl_l<142> a_wl_l<141> a_wl_l<140> a_wl_l<139> a_wl_l<138> a_wl_l<137> a_wl_l<136> a_wl_l<135> a_wl_l<134> a_wl_l<133> a_wl_l<132> a_wl_l<131> a_wl_l<130> a_wl_l<129> a_wl_l<128> a_wl_l<127> a_wl_l<126> a_wl_l<125> a_wl_l<124> a_wl_l<123> a_wl_l<122> a_wl_l<121> a_wl_l<120> a_wl_l<119> a_wl_l<118> a_wl_l<117> a_wl_l<116> a_wl_l<115> a_wl_l<114> a_wl_l<113> a_wl_l<112> a_wl_l<111> a_wl_l<110> a_wl_l<109> a_wl_l<108> a_wl_l<107> a_wl_l<106> a_wl_l<105> a_wl_l<104> a_wl_l<103> a_wl_l<102> a_wl_l<101> a_wl_l<100> a_wl_l<99> a_wl_l<98> a_wl_l<97> a_wl_l<96> a_wl_l<95> a_wl_l<94> a_wl_l<93> a_wl_l<92> a_wl_l<91> a_wl_l<90> a_wl_l<89> a_wl_l<88> a_wl_l<87> a_wl_l<86> a_wl_l<85> a_wl_l<84> a_wl_l<83> a_wl_l<82> a_wl_l<81> a_wl_l<80> a_wl_l<79> a_wl_l<78> a_wl_l<77> a_wl_l<76> a_wl_l<75> a_wl_l<74> a_wl_l<73> a_wl_l<72> a_wl_l<71> a_wl_l<70> a_wl_l<69> a_wl_l<68> a_wl_l<67> a_wl_l<66> a_wl_l<65> a_wl_l<64> a_wl_l<63> a_wl_l<62> a_wl_l<61> a_wl_l<60> a_wl_l<59> a_wl_l<58> a_wl_l<57> a_wl_l<56> a_wl_l<55> a_wl_l<54> a_wl_l<53> a_wl_l<52> a_wl_l<51> a_wl_l<50> a_wl_l<49> a_wl_l<48> a_wl_l<47> a_wl_l<46> a_wl_l<45> a_wl_l<44> a_wl_l<43> a_wl_l<42> a_wl_l<41> a_wl_l<40> a_wl_l<39> a_wl_l<38> a_wl_l<37> a_wl_l<36> a_wl_l<35> a_wl_l<34> a_wl_l<33> a_wl_l<32> a_wl_l<31> a_wl_l<30> a_wl_l<29> a_wl_l<28> a_wl_l<27> a_wl_l<26> a_wl_l<25> a_wl_l<24> a_wl_l<23> a_wl_l<22> a_wl_l<21> a_wl_l<20> a_wl_l<19> a_wl_l<18> a_wl_l<17> a_wl_l<16> a_wl_l<15> a_wl_l<14> a_wl_l<13> a_wl_l<12> a_wl_l<11> a_wl_l<10> a_wl_l<9> a_wl_l<8> a_wl_l<7> a_wl_l<6> a_wl_l<5> a_wl_l<4> a_wl_l<3> a_wl_l<2> a_wl_l<1> a_wl_l<0> VDDARRAY! VSS! / RM_IHPSG13_4096x16_c3_1P_MATRIX_pcell_1 + + +XA_COLDRV<1> a_addr_col<1> a_addr_col<0> a_addr_col_r<1> a_addr_col_r<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> a_dclk a_dclk_p_r<0> a_rclk a_rclk_p_r<0> a_wclk a_wclk_p_r<0> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_COLDRV13X4 +XA_COLDRV<0> a_addr_col<1> a_addr_col<0> a_addr_col_l<1> a_addr_col_l<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> a_dclk a_dclk_p_l<0> a_rclk a_rclk_p_l<0> a_wclk a_wclk_p_l<0> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_COLDRV13X4 + + +XA_WLDRV<63> a_wi<511> a_wi<510> a_wi<509> a_wi<508> a_wi<507> a_wi<506> a_wi<505> a_wi<504> a_wi<503> a_wi<502> a_wi<501> a_wi<500> a_wi<499> a_wi<498> a_wi<497> a_wi<496> a_wl_r<511> a_wl_r<510> a_wl_r<509> a_wl_r<508> a_wl_r<507> a_wl_r<506> a_wl_r<505> a_wl_r<504> a_wl_r<503> a_wl_r<502> a_wl_r<501> a_wl_r<500> a_wl_r<499> a_wl_r<498> a_wl_r<497> a_wl_r<496> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4 +XA_WLDRV<62> a_wi<495> a_wi<494> a_wi<493> a_wi<492> a_wi<491> a_wi<490> a_wi<489> a_wi<488> a_wi<487> a_wi<486> a_wi<485> a_wi<484> a_wi<483> a_wi<482> a_wi<481> a_wi<480> a_wl_r<495> a_wl_r<494> a_wl_r<493> a_wl_r<492> a_wl_r<491> a_wl_r<490> a_wl_r<489> a_wl_r<488> a_wl_r<487> a_wl_r<486> a_wl_r<485> a_wl_r<484> a_wl_r<483> a_wl_r<482> a_wl_r<481> a_wl_r<480> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4 +XA_WLDRV<61> a_wi<479> a_wi<478> a_wi<477> a_wi<476> a_wi<475> a_wi<474> a_wi<473> a_wi<472> a_wi<471> a_wi<470> a_wi<469> a_wi<468> a_wi<467> a_wi<466> a_wi<465> a_wi<464> a_wl_r<479> a_wl_r<478> a_wl_r<477> a_wl_r<476> a_wl_r<475> a_wl_r<474> a_wl_r<473> a_wl_r<472> a_wl_r<471> a_wl_r<470> a_wl_r<469> a_wl_r<468> a_wl_r<467> a_wl_r<466> a_wl_r<465> a_wl_r<464> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4 +XA_WLDRV<60> a_wi<463> a_wi<462> a_wi<461> a_wi<460> a_wi<459> a_wi<458> a_wi<457> a_wi<456> a_wi<455> a_wi<454> a_wi<453> a_wi<452> a_wi<451> a_wi<450> a_wi<449> a_wi<448> a_wl_r<463> a_wl_r<462> a_wl_r<461> a_wl_r<460> a_wl_r<459> a_wl_r<458> a_wl_r<457> a_wl_r<456> a_wl_r<455> a_wl_r<454> a_wl_r<453> a_wl_r<452> a_wl_r<451> a_wl_r<450> a_wl_r<449> a_wl_r<448> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4 +XA_WLDRV<59> a_wi<447> a_wi<446> a_wi<445> a_wi<444> a_wi<443> a_wi<442> a_wi<441> a_wi<440> a_wi<439> a_wi<438> a_wi<437> a_wi<436> a_wi<435> a_wi<434> a_wi<433> a_wi<432> a_wl_r<447> a_wl_r<446> a_wl_r<445> a_wl_r<444> a_wl_r<443> a_wl_r<442> a_wl_r<441> a_wl_r<440> a_wl_r<439> a_wl_r<438> a_wl_r<437> a_wl_r<436> a_wl_r<435> a_wl_r<434> a_wl_r<433> a_wl_r<432> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4 +XA_WLDRV<58> a_wi<431> a_wi<430> a_wi<429> a_wi<428> a_wi<427> a_wi<426> a_wi<425> a_wi<424> a_wi<423> a_wi<422> a_wi<421> a_wi<420> a_wi<419> a_wi<418> a_wi<417> a_wi<416> a_wl_r<431> a_wl_r<430> a_wl_r<429> a_wl_r<428> a_wl_r<427> a_wl_r<426> a_wl_r<425> a_wl_r<424> a_wl_r<423> a_wl_r<422> a_wl_r<421> a_wl_r<420> a_wl_r<419> a_wl_r<418> a_wl_r<417> a_wl_r<416> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4 +XA_WLDRV<57> a_wi<415> a_wi<414> a_wi<413> a_wi<412> a_wi<411> a_wi<410> a_wi<409> a_wi<408> a_wi<407> a_wi<406> a_wi<405> a_wi<404> a_wi<403> a_wi<402> a_wi<401> a_wi<400> a_wl_r<415> a_wl_r<414> a_wl_r<413> a_wl_r<412> a_wl_r<411> a_wl_r<410> a_wl_r<409> a_wl_r<408> a_wl_r<407> a_wl_r<406> a_wl_r<405> a_wl_r<404> a_wl_r<403> a_wl_r<402> a_wl_r<401> a_wl_r<400> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4 +XA_WLDRV<56> a_wi<399> a_wi<398> a_wi<397> a_wi<396> a_wi<395> a_wi<394> a_wi<393> a_wi<392> a_wi<391> a_wi<390> a_wi<389> a_wi<388> a_wi<387> a_wi<386> a_wi<385> a_wi<384> a_wl_r<399> a_wl_r<398> a_wl_r<397> a_wl_r<396> a_wl_r<395> a_wl_r<394> a_wl_r<393> a_wl_r<392> a_wl_r<391> a_wl_r<390> a_wl_r<389> a_wl_r<388> a_wl_r<387> a_wl_r<386> a_wl_r<385> a_wl_r<384> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4 +XA_WLDRV<55> a_wi<383> a_wi<382> a_wi<381> a_wi<380> a_wi<379> a_wi<378> a_wi<377> a_wi<376> a_wi<375> a_wi<374> a_wi<373> a_wi<372> a_wi<371> a_wi<370> a_wi<369> a_wi<368> a_wl_r<383> a_wl_r<382> a_wl_r<381> a_wl_r<380> a_wl_r<379> a_wl_r<378> a_wl_r<377> a_wl_r<376> a_wl_r<375> a_wl_r<374> a_wl_r<373> a_wl_r<372> a_wl_r<371> a_wl_r<370> a_wl_r<369> a_wl_r<368> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4 +XA_WLDRV<54> a_wi<367> a_wi<366> a_wi<365> a_wi<364> a_wi<363> a_wi<362> a_wi<361> a_wi<360> a_wi<359> a_wi<358> a_wi<357> a_wi<356> a_wi<355> a_wi<354> a_wi<353> a_wi<352> a_wl_r<367> a_wl_r<366> a_wl_r<365> a_wl_r<364> a_wl_r<363> a_wl_r<362> a_wl_r<361> a_wl_r<360> a_wl_r<359> a_wl_r<358> a_wl_r<357> a_wl_r<356> a_wl_r<355> a_wl_r<354> a_wl_r<353> a_wl_r<352> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4 +XA_WLDRV<53> a_wi<351> a_wi<350> a_wi<349> a_wi<348> a_wi<347> a_wi<346> a_wi<345> a_wi<344> a_wi<343> a_wi<342> a_wi<341> a_wi<340> a_wi<339> a_wi<338> a_wi<337> a_wi<336> a_wl_r<351> a_wl_r<350> a_wl_r<349> a_wl_r<348> a_wl_r<347> a_wl_r<346> a_wl_r<345> a_wl_r<344> a_wl_r<343> a_wl_r<342> a_wl_r<341> a_wl_r<340> a_wl_r<339> a_wl_r<338> a_wl_r<337> a_wl_r<336> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4 +XA_WLDRV<52> a_wi<335> a_wi<334> a_wi<333> a_wi<332> a_wi<331> a_wi<330> a_wi<329> a_wi<328> a_wi<327> a_wi<326> a_wi<325> a_wi<324> a_wi<323> a_wi<322> a_wi<321> a_wi<320> a_wl_r<335> a_wl_r<334> a_wl_r<333> a_wl_r<332> a_wl_r<331> a_wl_r<330> a_wl_r<329> a_wl_r<328> a_wl_r<327> a_wl_r<326> a_wl_r<325> a_wl_r<324> a_wl_r<323> a_wl_r<322> a_wl_r<321> a_wl_r<320> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4 +XA_WLDRV<51> a_wi<319> a_wi<318> a_wi<317> a_wi<316> a_wi<315> a_wi<314> a_wi<313> a_wi<312> a_wi<311> a_wi<310> a_wi<309> a_wi<308> a_wi<307> a_wi<306> a_wi<305> a_wi<304> a_wl_r<319> a_wl_r<318> a_wl_r<317> a_wl_r<316> a_wl_r<315> a_wl_r<314> a_wl_r<313> a_wl_r<312> a_wl_r<311> a_wl_r<310> a_wl_r<309> a_wl_r<308> a_wl_r<307> a_wl_r<306> a_wl_r<305> a_wl_r<304> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4 +XA_WLDRV<50> a_wi<303> a_wi<302> a_wi<301> a_wi<300> a_wi<299> a_wi<298> a_wi<297> a_wi<296> a_wi<295> a_wi<294> a_wi<293> a_wi<292> a_wi<291> a_wi<290> a_wi<289> a_wi<288> a_wl_r<303> a_wl_r<302> a_wl_r<301> a_wl_r<300> a_wl_r<299> a_wl_r<298> a_wl_r<297> a_wl_r<296> a_wl_r<295> a_wl_r<294> a_wl_r<293> a_wl_r<292> a_wl_r<291> a_wl_r<290> a_wl_r<289> a_wl_r<288> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4 +XA_WLDRV<49> a_wi<287> a_wi<286> a_wi<285> a_wi<284> a_wi<283> a_wi<282> a_wi<281> a_wi<280> a_wi<279> a_wi<278> a_wi<277> a_wi<276> a_wi<275> a_wi<274> a_wi<273> a_wi<272> a_wl_r<287> a_wl_r<286> a_wl_r<285> a_wl_r<284> a_wl_r<283> a_wl_r<282> a_wl_r<281> a_wl_r<280> a_wl_r<279> a_wl_r<278> a_wl_r<277> a_wl_r<276> a_wl_r<275> a_wl_r<274> a_wl_r<273> a_wl_r<272> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4 +XA_WLDRV<48> a_wi<271> a_wi<270> a_wi<269> a_wi<268> a_wi<267> a_wi<266> a_wi<265> a_wi<264> a_wi<263> a_wi<262> a_wi<261> a_wi<260> a_wi<259> a_wi<258> a_wi<257> a_wi<256> a_wl_r<271> a_wl_r<270> a_wl_r<269> a_wl_r<268> a_wl_r<267> a_wl_r<266> a_wl_r<265> a_wl_r<264> a_wl_r<263> a_wl_r<262> a_wl_r<261> a_wl_r<260> a_wl_r<259> a_wl_r<258> a_wl_r<257> a_wl_r<256> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4 +XA_WLDRV<47> a_wi<255> a_wi<254> a_wi<253> a_wi<252> a_wi<251> a_wi<250> a_wi<249> a_wi<248> a_wi<247> a_wi<246> a_wi<245> a_wi<244> a_wi<243> a_wi<242> a_wi<241> a_wi<240> a_wl_r<255> a_wl_r<254> a_wl_r<253> a_wl_r<252> a_wl_r<251> a_wl_r<250> a_wl_r<249> a_wl_r<248> a_wl_r<247> a_wl_r<246> a_wl_r<245> a_wl_r<244> a_wl_r<243> a_wl_r<242> a_wl_r<241> a_wl_r<240> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4 +XA_WLDRV<46> a_wi<239> a_wi<238> a_wi<237> a_wi<236> a_wi<235> a_wi<234> a_wi<233> a_wi<232> a_wi<231> a_wi<230> a_wi<229> a_wi<228> a_wi<227> a_wi<226> a_wi<225> a_wi<224> a_wl_r<239> a_wl_r<238> a_wl_r<237> a_wl_r<236> a_wl_r<235> a_wl_r<234> a_wl_r<233> a_wl_r<232> a_wl_r<231> a_wl_r<230> a_wl_r<229> a_wl_r<228> a_wl_r<227> a_wl_r<226> a_wl_r<225> a_wl_r<224> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4 +XA_WLDRV<45> a_wi<223> a_wi<222> a_wi<221> a_wi<220> a_wi<219> a_wi<218> a_wi<217> a_wi<216> a_wi<215> a_wi<214> a_wi<213> a_wi<212> a_wi<211> a_wi<210> a_wi<209> a_wi<208> a_wl_r<223> a_wl_r<222> a_wl_r<221> a_wl_r<220> a_wl_r<219> a_wl_r<218> a_wl_r<217> a_wl_r<216> a_wl_r<215> a_wl_r<214> a_wl_r<213> a_wl_r<212> a_wl_r<211> a_wl_r<210> a_wl_r<209> a_wl_r<208> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4 +XA_WLDRV<44> a_wi<207> a_wi<206> a_wi<205> a_wi<204> a_wi<203> a_wi<202> a_wi<201> a_wi<200> a_wi<199> a_wi<198> a_wi<197> a_wi<196> a_wi<195> a_wi<194> a_wi<193> a_wi<192> a_wl_r<207> a_wl_r<206> a_wl_r<205> a_wl_r<204> a_wl_r<203> a_wl_r<202> a_wl_r<201> a_wl_r<200> a_wl_r<199> a_wl_r<198> a_wl_r<197> a_wl_r<196> a_wl_r<195> a_wl_r<194> a_wl_r<193> a_wl_r<192> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4 +XA_WLDRV<43> a_wi<191> a_wi<190> a_wi<189> a_wi<188> a_wi<187> a_wi<186> a_wi<185> a_wi<184> a_wi<183> a_wi<182> a_wi<181> a_wi<180> a_wi<179> a_wi<178> a_wi<177> a_wi<176> a_wl_r<191> a_wl_r<190> a_wl_r<189> a_wl_r<188> a_wl_r<187> a_wl_r<186> a_wl_r<185> a_wl_r<184> a_wl_r<183> a_wl_r<182> a_wl_r<181> a_wl_r<180> a_wl_r<179> a_wl_r<178> a_wl_r<177> a_wl_r<176> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4 +XA_WLDRV<42> a_wi<175> a_wi<174> a_wi<173> a_wi<172> a_wi<171> a_wi<170> a_wi<169> a_wi<168> a_wi<167> a_wi<166> a_wi<165> a_wi<164> a_wi<163> a_wi<162> a_wi<161> a_wi<160> a_wl_r<175> a_wl_r<174> a_wl_r<173> a_wl_r<172> a_wl_r<171> a_wl_r<170> a_wl_r<169> a_wl_r<168> a_wl_r<167> a_wl_r<166> a_wl_r<165> a_wl_r<164> a_wl_r<163> a_wl_r<162> a_wl_r<161> a_wl_r<160> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4 +XA_WLDRV<41> a_wi<159> a_wi<158> a_wi<157> a_wi<156> a_wi<155> a_wi<154> a_wi<153> a_wi<152> a_wi<151> a_wi<150> a_wi<149> a_wi<148> a_wi<147> a_wi<146> a_wi<145> a_wi<144> a_wl_r<159> a_wl_r<158> a_wl_r<157> a_wl_r<156> a_wl_r<155> a_wl_r<154> a_wl_r<153> a_wl_r<152> a_wl_r<151> a_wl_r<150> a_wl_r<149> a_wl_r<148> a_wl_r<147> a_wl_r<146> a_wl_r<145> a_wl_r<144> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4 +XA_WLDRV<40> a_wi<143> a_wi<142> a_wi<141> a_wi<140> a_wi<139> a_wi<138> a_wi<137> a_wi<136> a_wi<135> a_wi<134> a_wi<133> a_wi<132> a_wi<131> a_wi<130> a_wi<129> a_wi<128> a_wl_r<143> a_wl_r<142> a_wl_r<141> a_wl_r<140> a_wl_r<139> a_wl_r<138> a_wl_r<137> a_wl_r<136> a_wl_r<135> a_wl_r<134> a_wl_r<133> a_wl_r<132> a_wl_r<131> a_wl_r<130> a_wl_r<129> a_wl_r<128> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4 +XA_WLDRV<39> a_wi<127> a_wi<126> a_wi<125> a_wi<124> a_wi<123> a_wi<122> a_wi<121> a_wi<120> a_wi<119> a_wi<118> a_wi<117> a_wi<116> a_wi<115> a_wi<114> a_wi<113> a_wi<112> a_wl_r<127> a_wl_r<126> a_wl_r<125> a_wl_r<124> a_wl_r<123> a_wl_r<122> a_wl_r<121> a_wl_r<120> a_wl_r<119> a_wl_r<118> a_wl_r<117> a_wl_r<116> a_wl_r<115> a_wl_r<114> a_wl_r<113> a_wl_r<112> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4 +XA_WLDRV<38> a_wi<111> a_wi<110> a_wi<109> a_wi<108> a_wi<107> a_wi<106> a_wi<105> a_wi<104> a_wi<103> a_wi<102> a_wi<101> a_wi<100> a_wi<99> a_wi<98> a_wi<97> a_wi<96> a_wl_r<111> a_wl_r<110> a_wl_r<109> a_wl_r<108> a_wl_r<107> a_wl_r<106> a_wl_r<105> a_wl_r<104> a_wl_r<103> a_wl_r<102> a_wl_r<101> a_wl_r<100> a_wl_r<99> a_wl_r<98> a_wl_r<97> a_wl_r<96> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4 +XA_WLDRV<37> a_wi<95> a_wi<94> a_wi<93> a_wi<92> a_wi<91> a_wi<90> a_wi<89> a_wi<88> a_wi<87> a_wi<86> a_wi<85> a_wi<84> a_wi<83> a_wi<82> a_wi<81> a_wi<80> a_wl_r<95> a_wl_r<94> a_wl_r<93> a_wl_r<92> a_wl_r<91> a_wl_r<90> a_wl_r<89> a_wl_r<88> a_wl_r<87> a_wl_r<86> a_wl_r<85> a_wl_r<84> a_wl_r<83> a_wl_r<82> a_wl_r<81> a_wl_r<80> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4 +XA_WLDRV<36> a_wi<79> a_wi<78> a_wi<77> a_wi<76> a_wi<75> a_wi<74> a_wi<73> a_wi<72> a_wi<71> a_wi<70> a_wi<69> a_wi<68> a_wi<67> a_wi<66> a_wi<65> a_wi<64> a_wl_r<79> a_wl_r<78> a_wl_r<77> a_wl_r<76> a_wl_r<75> a_wl_r<74> a_wl_r<73> a_wl_r<72> a_wl_r<71> a_wl_r<70> a_wl_r<69> a_wl_r<68> a_wl_r<67> a_wl_r<66> a_wl_r<65> a_wl_r<64> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4 +XA_WLDRV<35> a_wi<63> a_wi<62> a_wi<61> a_wi<60> a_wi<59> a_wi<58> a_wi<57> a_wi<56> a_wi<55> a_wi<54> a_wi<53> a_wi<52> a_wi<51> a_wi<50> a_wi<49> a_wi<48> a_wl_r<63> a_wl_r<62> a_wl_r<61> a_wl_r<60> a_wl_r<59> a_wl_r<58> a_wl_r<57> a_wl_r<56> a_wl_r<55> a_wl_r<54> a_wl_r<53> a_wl_r<52> a_wl_r<51> a_wl_r<50> a_wl_r<49> a_wl_r<48> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4 +XA_WLDRV<34> a_wi<47> a_wi<46> a_wi<45> a_wi<44> a_wi<43> a_wi<42> a_wi<41> a_wi<40> a_wi<39> a_wi<38> a_wi<37> a_wi<36> a_wi<35> a_wi<34> a_wi<33> a_wi<32> a_wl_r<47> a_wl_r<46> a_wl_r<45> a_wl_r<44> a_wl_r<43> a_wl_r<42> a_wl_r<41> a_wl_r<40> a_wl_r<39> a_wl_r<38> a_wl_r<37> a_wl_r<36> a_wl_r<35> a_wl_r<34> a_wl_r<33> a_wl_r<32> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4 +XA_WLDRV<33> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wl_r<31> a_wl_r<30> a_wl_r<29> a_wl_r<28> a_wl_r<27> a_wl_r<26> a_wl_r<25> a_wl_r<24> a_wl_r<23> a_wl_r<22> a_wl_r<21> a_wl_r<20> a_wl_r<19> a_wl_r<18> a_wl_r<17> a_wl_r<16> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4 +XA_WLDRV<32> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> a_wl_r<15> a_wl_r<14> a_wl_r<13> a_wl_r<12> a_wl_r<11> a_wl_r<10> a_wl_r<9> a_wl_r<8> a_wl_r<7> a_wl_r<6> a_wl_r<5> a_wl_r<4> a_wl_r<3> a_wl_r<2> a_wl_r<1> a_wl_r<0> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4 +XA_WLDRV<31> a_wi<511> a_wi<510> a_wi<509> a_wi<508> a_wi<507> a_wi<506> a_wi<505> a_wi<504> a_wi<503> a_wi<502> a_wi<501> a_wi<500> a_wi<499> a_wi<498> a_wi<497> a_wi<496> a_wl_l<511> a_wl_l<510> a_wl_l<509> a_wl_l<508> a_wl_l<507> a_wl_l<506> a_wl_l<505> a_wl_l<504> a_wl_l<503> a_wl_l<502> a_wl_l<501> a_wl_l<500> a_wl_l<499> a_wl_l<498> a_wl_l<497> a_wl_l<496> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4 +XA_WLDRV<30> a_wi<495> a_wi<494> a_wi<493> a_wi<492> a_wi<491> a_wi<490> a_wi<489> a_wi<488> a_wi<487> a_wi<486> a_wi<485> a_wi<484> a_wi<483> a_wi<482> a_wi<481> a_wi<480> a_wl_l<495> a_wl_l<494> a_wl_l<493> a_wl_l<492> a_wl_l<491> a_wl_l<490> a_wl_l<489> a_wl_l<488> a_wl_l<487> a_wl_l<486> a_wl_l<485> a_wl_l<484> a_wl_l<483> a_wl_l<482> a_wl_l<481> a_wl_l<480> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4 +XA_WLDRV<29> a_wi<479> a_wi<478> a_wi<477> a_wi<476> a_wi<475> a_wi<474> a_wi<473> a_wi<472> a_wi<471> a_wi<470> a_wi<469> a_wi<468> a_wi<467> a_wi<466> a_wi<465> a_wi<464> a_wl_l<479> a_wl_l<478> a_wl_l<477> a_wl_l<476> a_wl_l<475> a_wl_l<474> a_wl_l<473> a_wl_l<472> a_wl_l<471> a_wl_l<470> a_wl_l<469> a_wl_l<468> a_wl_l<467> a_wl_l<466> a_wl_l<465> a_wl_l<464> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4 +XA_WLDRV<28> a_wi<463> a_wi<462> a_wi<461> a_wi<460> a_wi<459> a_wi<458> a_wi<457> a_wi<456> a_wi<455> a_wi<454> a_wi<453> a_wi<452> a_wi<451> a_wi<450> a_wi<449> a_wi<448> a_wl_l<463> a_wl_l<462> a_wl_l<461> a_wl_l<460> a_wl_l<459> a_wl_l<458> a_wl_l<457> a_wl_l<456> a_wl_l<455> a_wl_l<454> a_wl_l<453> a_wl_l<452> a_wl_l<451> a_wl_l<450> a_wl_l<449> a_wl_l<448> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4 +XA_WLDRV<27> a_wi<447> a_wi<446> a_wi<445> a_wi<444> a_wi<443> a_wi<442> a_wi<441> a_wi<440> a_wi<439> a_wi<438> a_wi<437> a_wi<436> a_wi<435> a_wi<434> a_wi<433> a_wi<432> a_wl_l<447> a_wl_l<446> a_wl_l<445> a_wl_l<444> a_wl_l<443> a_wl_l<442> a_wl_l<441> a_wl_l<440> a_wl_l<439> a_wl_l<438> a_wl_l<437> a_wl_l<436> a_wl_l<435> a_wl_l<434> a_wl_l<433> a_wl_l<432> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4 +XA_WLDRV<26> a_wi<431> a_wi<430> a_wi<429> a_wi<428> a_wi<427> a_wi<426> a_wi<425> a_wi<424> a_wi<423> a_wi<422> a_wi<421> a_wi<420> a_wi<419> a_wi<418> a_wi<417> a_wi<416> a_wl_l<431> a_wl_l<430> a_wl_l<429> a_wl_l<428> a_wl_l<427> a_wl_l<426> a_wl_l<425> a_wl_l<424> a_wl_l<423> a_wl_l<422> a_wl_l<421> a_wl_l<420> a_wl_l<419> a_wl_l<418> a_wl_l<417> a_wl_l<416> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4 +XA_WLDRV<25> a_wi<415> a_wi<414> a_wi<413> a_wi<412> a_wi<411> a_wi<410> a_wi<409> a_wi<408> a_wi<407> a_wi<406> a_wi<405> a_wi<404> a_wi<403> a_wi<402> a_wi<401> a_wi<400> a_wl_l<415> a_wl_l<414> a_wl_l<413> a_wl_l<412> a_wl_l<411> a_wl_l<410> a_wl_l<409> a_wl_l<408> a_wl_l<407> a_wl_l<406> a_wl_l<405> a_wl_l<404> a_wl_l<403> a_wl_l<402> a_wl_l<401> a_wl_l<400> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4 +XA_WLDRV<24> a_wi<399> a_wi<398> a_wi<397> a_wi<396> a_wi<395> a_wi<394> a_wi<393> a_wi<392> a_wi<391> a_wi<390> a_wi<389> a_wi<388> a_wi<387> a_wi<386> a_wi<385> a_wi<384> a_wl_l<399> a_wl_l<398> a_wl_l<397> a_wl_l<396> a_wl_l<395> a_wl_l<394> a_wl_l<393> a_wl_l<392> a_wl_l<391> a_wl_l<390> a_wl_l<389> a_wl_l<388> a_wl_l<387> a_wl_l<386> a_wl_l<385> a_wl_l<384> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4 +XA_WLDRV<23> a_wi<383> a_wi<382> a_wi<381> a_wi<380> a_wi<379> a_wi<378> a_wi<377> a_wi<376> a_wi<375> a_wi<374> a_wi<373> a_wi<372> a_wi<371> a_wi<370> a_wi<369> a_wi<368> a_wl_l<383> a_wl_l<382> a_wl_l<381> a_wl_l<380> a_wl_l<379> a_wl_l<378> a_wl_l<377> a_wl_l<376> a_wl_l<375> a_wl_l<374> a_wl_l<373> a_wl_l<372> a_wl_l<371> a_wl_l<370> a_wl_l<369> a_wl_l<368> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4 +XA_WLDRV<22> a_wi<367> a_wi<366> a_wi<365> a_wi<364> a_wi<363> a_wi<362> a_wi<361> a_wi<360> a_wi<359> a_wi<358> a_wi<357> a_wi<356> a_wi<355> a_wi<354> a_wi<353> a_wi<352> a_wl_l<367> a_wl_l<366> a_wl_l<365> a_wl_l<364> a_wl_l<363> a_wl_l<362> a_wl_l<361> a_wl_l<360> a_wl_l<359> a_wl_l<358> a_wl_l<357> a_wl_l<356> a_wl_l<355> a_wl_l<354> a_wl_l<353> a_wl_l<352> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4 +XA_WLDRV<21> a_wi<351> a_wi<350> a_wi<349> a_wi<348> a_wi<347> a_wi<346> a_wi<345> a_wi<344> a_wi<343> a_wi<342> a_wi<341> a_wi<340> a_wi<339> a_wi<338> a_wi<337> a_wi<336> a_wl_l<351> a_wl_l<350> a_wl_l<349> a_wl_l<348> a_wl_l<347> a_wl_l<346> a_wl_l<345> a_wl_l<344> a_wl_l<343> a_wl_l<342> a_wl_l<341> a_wl_l<340> a_wl_l<339> a_wl_l<338> a_wl_l<337> a_wl_l<336> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4 +XA_WLDRV<20> a_wi<335> a_wi<334> a_wi<333> a_wi<332> a_wi<331> a_wi<330> a_wi<329> a_wi<328> a_wi<327> a_wi<326> a_wi<325> a_wi<324> a_wi<323> a_wi<322> a_wi<321> a_wi<320> a_wl_l<335> a_wl_l<334> a_wl_l<333> a_wl_l<332> a_wl_l<331> a_wl_l<330> a_wl_l<329> a_wl_l<328> a_wl_l<327> a_wl_l<326> a_wl_l<325> a_wl_l<324> a_wl_l<323> a_wl_l<322> a_wl_l<321> a_wl_l<320> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4 +XA_WLDRV<19> a_wi<319> a_wi<318> a_wi<317> a_wi<316> a_wi<315> a_wi<314> a_wi<313> a_wi<312> a_wi<311> a_wi<310> a_wi<309> a_wi<308> a_wi<307> a_wi<306> a_wi<305> a_wi<304> a_wl_l<319> a_wl_l<318> a_wl_l<317> a_wl_l<316> a_wl_l<315> a_wl_l<314> a_wl_l<313> a_wl_l<312> a_wl_l<311> a_wl_l<310> a_wl_l<309> a_wl_l<308> a_wl_l<307> a_wl_l<306> a_wl_l<305> a_wl_l<304> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4 +XA_WLDRV<18> a_wi<303> a_wi<302> a_wi<301> a_wi<300> a_wi<299> a_wi<298> a_wi<297> a_wi<296> a_wi<295> a_wi<294> a_wi<293> a_wi<292> a_wi<291> a_wi<290> a_wi<289> a_wi<288> a_wl_l<303> a_wl_l<302> a_wl_l<301> a_wl_l<300> a_wl_l<299> a_wl_l<298> a_wl_l<297> a_wl_l<296> a_wl_l<295> a_wl_l<294> a_wl_l<293> a_wl_l<292> a_wl_l<291> a_wl_l<290> a_wl_l<289> a_wl_l<288> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4 +XA_WLDRV<17> a_wi<287> a_wi<286> a_wi<285> a_wi<284> a_wi<283> a_wi<282> a_wi<281> a_wi<280> a_wi<279> a_wi<278> a_wi<277> a_wi<276> a_wi<275> a_wi<274> a_wi<273> a_wi<272> a_wl_l<287> a_wl_l<286> a_wl_l<285> a_wl_l<284> a_wl_l<283> a_wl_l<282> a_wl_l<281> a_wl_l<280> a_wl_l<279> a_wl_l<278> a_wl_l<277> a_wl_l<276> a_wl_l<275> a_wl_l<274> a_wl_l<273> a_wl_l<272> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4 +XA_WLDRV<16> a_wi<271> a_wi<270> a_wi<269> a_wi<268> a_wi<267> a_wi<266> a_wi<265> a_wi<264> a_wi<263> a_wi<262> a_wi<261> a_wi<260> a_wi<259> a_wi<258> a_wi<257> a_wi<256> a_wl_l<271> a_wl_l<270> a_wl_l<269> a_wl_l<268> a_wl_l<267> a_wl_l<266> a_wl_l<265> a_wl_l<264> a_wl_l<263> a_wl_l<262> a_wl_l<261> a_wl_l<260> a_wl_l<259> a_wl_l<258> a_wl_l<257> a_wl_l<256> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4 +XA_WLDRV<15> a_wi<255> a_wi<254> a_wi<253> a_wi<252> a_wi<251> a_wi<250> a_wi<249> a_wi<248> a_wi<247> a_wi<246> a_wi<245> a_wi<244> a_wi<243> a_wi<242> a_wi<241> a_wi<240> a_wl_l<255> a_wl_l<254> a_wl_l<253> a_wl_l<252> a_wl_l<251> a_wl_l<250> a_wl_l<249> a_wl_l<248> a_wl_l<247> a_wl_l<246> a_wl_l<245> a_wl_l<244> a_wl_l<243> a_wl_l<242> a_wl_l<241> a_wl_l<240> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4 +XA_WLDRV<14> a_wi<239> a_wi<238> a_wi<237> a_wi<236> a_wi<235> a_wi<234> a_wi<233> a_wi<232> a_wi<231> a_wi<230> a_wi<229> a_wi<228> a_wi<227> a_wi<226> a_wi<225> a_wi<224> a_wl_l<239> a_wl_l<238> a_wl_l<237> a_wl_l<236> a_wl_l<235> a_wl_l<234> a_wl_l<233> a_wl_l<232> a_wl_l<231> a_wl_l<230> a_wl_l<229> a_wl_l<228> a_wl_l<227> a_wl_l<226> a_wl_l<225> a_wl_l<224> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4 +XA_WLDRV<13> a_wi<223> a_wi<222> a_wi<221> a_wi<220> a_wi<219> a_wi<218> a_wi<217> a_wi<216> a_wi<215> a_wi<214> a_wi<213> a_wi<212> a_wi<211> a_wi<210> a_wi<209> a_wi<208> a_wl_l<223> a_wl_l<222> a_wl_l<221> a_wl_l<220> a_wl_l<219> a_wl_l<218> a_wl_l<217> a_wl_l<216> a_wl_l<215> a_wl_l<214> a_wl_l<213> a_wl_l<212> a_wl_l<211> a_wl_l<210> a_wl_l<209> a_wl_l<208> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4 +XA_WLDRV<12> a_wi<207> a_wi<206> a_wi<205> a_wi<204> a_wi<203> a_wi<202> a_wi<201> a_wi<200> a_wi<199> a_wi<198> a_wi<197> a_wi<196> a_wi<195> a_wi<194> a_wi<193> a_wi<192> a_wl_l<207> a_wl_l<206> a_wl_l<205> a_wl_l<204> a_wl_l<203> a_wl_l<202> a_wl_l<201> a_wl_l<200> a_wl_l<199> a_wl_l<198> a_wl_l<197> a_wl_l<196> a_wl_l<195> a_wl_l<194> a_wl_l<193> a_wl_l<192> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4 +XA_WLDRV<11> a_wi<191> a_wi<190> a_wi<189> a_wi<188> a_wi<187> a_wi<186> a_wi<185> a_wi<184> a_wi<183> a_wi<182> a_wi<181> a_wi<180> a_wi<179> a_wi<178> a_wi<177> a_wi<176> a_wl_l<191> a_wl_l<190> a_wl_l<189> a_wl_l<188> a_wl_l<187> a_wl_l<186> a_wl_l<185> a_wl_l<184> a_wl_l<183> a_wl_l<182> a_wl_l<181> a_wl_l<180> a_wl_l<179> a_wl_l<178> a_wl_l<177> a_wl_l<176> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4 +XA_WLDRV<10> a_wi<175> a_wi<174> a_wi<173> a_wi<172> a_wi<171> a_wi<170> a_wi<169> a_wi<168> a_wi<167> a_wi<166> a_wi<165> a_wi<164> a_wi<163> a_wi<162> a_wi<161> a_wi<160> a_wl_l<175> a_wl_l<174> a_wl_l<173> a_wl_l<172> a_wl_l<171> a_wl_l<170> a_wl_l<169> a_wl_l<168> a_wl_l<167> a_wl_l<166> a_wl_l<165> a_wl_l<164> a_wl_l<163> a_wl_l<162> a_wl_l<161> a_wl_l<160> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4 +XA_WLDRV<9> a_wi<159> a_wi<158> a_wi<157> a_wi<156> a_wi<155> a_wi<154> a_wi<153> a_wi<152> a_wi<151> a_wi<150> a_wi<149> a_wi<148> a_wi<147> a_wi<146> a_wi<145> a_wi<144> a_wl_l<159> a_wl_l<158> a_wl_l<157> a_wl_l<156> a_wl_l<155> a_wl_l<154> a_wl_l<153> a_wl_l<152> a_wl_l<151> a_wl_l<150> a_wl_l<149> a_wl_l<148> a_wl_l<147> a_wl_l<146> a_wl_l<145> a_wl_l<144> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4 +XA_WLDRV<8> a_wi<143> a_wi<142> a_wi<141> a_wi<140> a_wi<139> a_wi<138> a_wi<137> a_wi<136> a_wi<135> a_wi<134> a_wi<133> a_wi<132> a_wi<131> a_wi<130> a_wi<129> a_wi<128> a_wl_l<143> a_wl_l<142> a_wl_l<141> a_wl_l<140> a_wl_l<139> a_wl_l<138> a_wl_l<137> a_wl_l<136> a_wl_l<135> a_wl_l<134> a_wl_l<133> a_wl_l<132> a_wl_l<131> a_wl_l<130> a_wl_l<129> a_wl_l<128> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4 +XA_WLDRV<7> a_wi<127> a_wi<126> a_wi<125> a_wi<124> a_wi<123> a_wi<122> a_wi<121> a_wi<120> a_wi<119> a_wi<118> a_wi<117> a_wi<116> a_wi<115> a_wi<114> a_wi<113> a_wi<112> a_wl_l<127> a_wl_l<126> a_wl_l<125> a_wl_l<124> a_wl_l<123> a_wl_l<122> a_wl_l<121> a_wl_l<120> a_wl_l<119> a_wl_l<118> a_wl_l<117> a_wl_l<116> a_wl_l<115> a_wl_l<114> a_wl_l<113> a_wl_l<112> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4 +XA_WLDRV<6> a_wi<111> a_wi<110> a_wi<109> a_wi<108> a_wi<107> a_wi<106> a_wi<105> a_wi<104> a_wi<103> a_wi<102> a_wi<101> a_wi<100> a_wi<99> a_wi<98> a_wi<97> a_wi<96> a_wl_l<111> a_wl_l<110> a_wl_l<109> a_wl_l<108> a_wl_l<107> a_wl_l<106> a_wl_l<105> a_wl_l<104> a_wl_l<103> a_wl_l<102> a_wl_l<101> a_wl_l<100> a_wl_l<99> a_wl_l<98> a_wl_l<97> a_wl_l<96> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4 +XA_WLDRV<5> a_wi<95> a_wi<94> a_wi<93> a_wi<92> a_wi<91> a_wi<90> a_wi<89> a_wi<88> a_wi<87> a_wi<86> a_wi<85> a_wi<84> a_wi<83> a_wi<82> a_wi<81> a_wi<80> a_wl_l<95> a_wl_l<94> a_wl_l<93> a_wl_l<92> a_wl_l<91> a_wl_l<90> a_wl_l<89> a_wl_l<88> a_wl_l<87> a_wl_l<86> a_wl_l<85> a_wl_l<84> a_wl_l<83> a_wl_l<82> a_wl_l<81> a_wl_l<80> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4 +XA_WLDRV<4> a_wi<79> a_wi<78> a_wi<77> a_wi<76> a_wi<75> a_wi<74> a_wi<73> a_wi<72> a_wi<71> a_wi<70> a_wi<69> a_wi<68> a_wi<67> a_wi<66> a_wi<65> a_wi<64> a_wl_l<79> a_wl_l<78> a_wl_l<77> a_wl_l<76> a_wl_l<75> a_wl_l<74> a_wl_l<73> a_wl_l<72> a_wl_l<71> a_wl_l<70> a_wl_l<69> a_wl_l<68> a_wl_l<67> a_wl_l<66> a_wl_l<65> a_wl_l<64> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4 +XA_WLDRV<3> a_wi<63> a_wi<62> a_wi<61> a_wi<60> a_wi<59> a_wi<58> a_wi<57> a_wi<56> a_wi<55> a_wi<54> a_wi<53> a_wi<52> a_wi<51> a_wi<50> a_wi<49> a_wi<48> a_wl_l<63> a_wl_l<62> a_wl_l<61> a_wl_l<60> a_wl_l<59> a_wl_l<58> a_wl_l<57> a_wl_l<56> a_wl_l<55> a_wl_l<54> a_wl_l<53> a_wl_l<52> a_wl_l<51> a_wl_l<50> a_wl_l<49> a_wl_l<48> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4 +XA_WLDRV<2> a_wi<47> a_wi<46> a_wi<45> a_wi<44> a_wi<43> a_wi<42> a_wi<41> a_wi<40> a_wi<39> a_wi<38> a_wi<37> a_wi<36> a_wi<35> a_wi<34> a_wi<33> a_wi<32> a_wl_l<47> a_wl_l<46> a_wl_l<45> a_wl_l<44> a_wl_l<43> a_wl_l<42> a_wl_l<41> a_wl_l<40> a_wl_l<39> a_wl_l<38> a_wl_l<37> a_wl_l<36> a_wl_l<35> a_wl_l<34> a_wl_l<33> a_wl_l<32> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4 +XA_WLDRV<1> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wl_l<31> a_wl_l<30> a_wl_l<29> a_wl_l<28> a_wl_l<27> a_wl_l<26> a_wl_l<25> a_wl_l<24> a_wl_l<23> a_wl_l<22> a_wl_l<21> a_wl_l<20> a_wl_l<19> a_wl_l<18> a_wl_l<17> a_wl_l<16> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4 +XA_WLDRV<0> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> a_wl_l<15> a_wl_l<14> a_wl_l<13> a_wl_l<12> a_wl_l<11> a_wl_l<10> a_wl_l<9> a_wl_l<8> a_wl_l<7> a_wl_l<6> a_wl_l<5> a_wl_l<4> a_wl_l<3> a_wl_l<2> a_wl_l<1> a_wl_l<0> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4 + + +XA_CTRL a_aclk_n A_BIST_CLK A_BIST_MEN A_BIST_EN A_BIST_REN A_BIST_WEN a_tiel A_CLK A_MEN a_dclk a_eclk a_pulse_h a_pulse_l a_pulse a_rclk A_REN a_cs a_wclk A_WEN VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_CTRL + + +XA_ROWDEC a_addr_row<8> a_addr_row<7> a_addr_row<6> a_addr_row<5> a_addr_row<4> a_addr_row<3> a_addr_row<2> a_addr_row<1> a_addr_row<0> a_cs a_eclk a_wi<511> a_wi<510> a_wi<509> a_wi<508> a_wi<507> a_wi<506> a_wi<505> a_wi<504> a_wi<503> a_wi<502> a_wi<501> a_wi<500> a_wi<499> a_wi<498> a_wi<497> a_wi<496> a_wi<495> a_wi<494> a_wi<493> a_wi<492> a_wi<491> a_wi<490> a_wi<489> a_wi<488> a_wi<487> a_wi<486> a_wi<485> a_wi<484> a_wi<483> a_wi<482> a_wi<481> a_wi<480> a_wi<479> a_wi<478> a_wi<477> a_wi<476> a_wi<475> a_wi<474> a_wi<473> a_wi<472> a_wi<471> a_wi<470> a_wi<469> a_wi<468> a_wi<467> a_wi<466> a_wi<465> a_wi<464> a_wi<463> a_wi<462> a_wi<461> a_wi<460> a_wi<459> a_wi<458> a_wi<457> a_wi<456> a_wi<455> a_wi<454> a_wi<453> a_wi<452> a_wi<451> a_wi<450> a_wi<449> a_wi<448> a_wi<447> a_wi<446> a_wi<445> a_wi<444> a_wi<443> a_wi<442> a_wi<441> a_wi<440> a_wi<439> a_wi<438> a_wi<437> a_wi<436> a_wi<435> a_wi<434> a_wi<433> a_wi<432> a_wi<431> a_wi<430> a_wi<429> a_wi<428> a_wi<427> a_wi<426> a_wi<425> a_wi<424> a_wi<423> a_wi<422> a_wi<421> a_wi<420> a_wi<419> a_wi<418> a_wi<417> a_wi<416> a_wi<415> a_wi<414> a_wi<413> a_wi<412> a_wi<411> a_wi<410> a_wi<409> a_wi<408> a_wi<407> a_wi<406> a_wi<405> a_wi<404> a_wi<403> a_wi<402> a_wi<401> a_wi<400> a_wi<399> a_wi<398> a_wi<397> a_wi<396> a_wi<395> a_wi<394> a_wi<393> a_wi<392> a_wi<391> a_wi<390> a_wi<389> a_wi<388> a_wi<387> a_wi<386> a_wi<385> a_wi<384> a_wi<383> a_wi<382> a_wi<381> a_wi<380> a_wi<379> a_wi<378> a_wi<377> a_wi<376> a_wi<375> a_wi<374> a_wi<373> a_wi<372> a_wi<371> a_wi<370> a_wi<369> a_wi<368> a_wi<367> a_wi<366> a_wi<365> a_wi<364> a_wi<363> a_wi<362> a_wi<361> a_wi<360> a_wi<359> a_wi<358> a_wi<357> a_wi<356> a_wi<355> a_wi<354> a_wi<353> a_wi<352> a_wi<351> a_wi<350> a_wi<349> a_wi<348> a_wi<347> a_wi<346> a_wi<345> a_wi<344> a_wi<343> a_wi<342> a_wi<341> a_wi<340> a_wi<339> a_wi<338> a_wi<337> a_wi<336> a_wi<335> a_wi<334> a_wi<333> a_wi<332> a_wi<331> a_wi<330> a_wi<329> a_wi<328> a_wi<327> a_wi<326> a_wi<325> a_wi<324> a_wi<323> a_wi<322> a_wi<321> a_wi<320> a_wi<319> a_wi<318> a_wi<317> a_wi<316> a_wi<315> a_wi<314> a_wi<313> a_wi<312> a_wi<311> a_wi<310> a_wi<309> a_wi<308> a_wi<307> a_wi<306> a_wi<305> a_wi<304> a_wi<303> a_wi<302> a_wi<301> a_wi<300> a_wi<299> a_wi<298> a_wi<297> a_wi<296> a_wi<295> a_wi<294> a_wi<293> a_wi<292> a_wi<291> a_wi<290> a_wi<289> a_wi<288> a_wi<287> a_wi<286> a_wi<285> a_wi<284> a_wi<283> a_wi<282> a_wi<281> a_wi<280> a_wi<279> a_wi<278> a_wi<277> a_wi<276> a_wi<275> a_wi<274> a_wi<273> a_wi<272> a_wi<271> a_wi<270> a_wi<269> a_wi<268> a_wi<267> a_wi<266> a_wi<265> a_wi<264> a_wi<263> a_wi<262> a_wi<261> a_wi<260> a_wi<259> a_wi<258> a_wi<257> a_wi<256> a_wi<255> a_wi<254> a_wi<253> a_wi<252> a_wi<251> a_wi<250> a_wi<249> a_wi<248> a_wi<247> a_wi<246> a_wi<245> a_wi<244> a_wi<243> a_wi<242> a_wi<241> a_wi<240> a_wi<239> a_wi<238> a_wi<237> a_wi<236> a_wi<235> a_wi<234> a_wi<233> a_wi<232> a_wi<231> a_wi<230> a_wi<229> a_wi<228> a_wi<227> a_wi<226> a_wi<225> a_wi<224> a_wi<223> a_wi<222> a_wi<221> a_wi<220> a_wi<219> a_wi<218> a_wi<217> a_wi<216> a_wi<215> a_wi<214> a_wi<213> a_wi<212> a_wi<211> a_wi<210> a_wi<209> a_wi<208> a_wi<207> a_wi<206> a_wi<205> a_wi<204> a_wi<203> a_wi<202> a_wi<201> a_wi<200> a_wi<199> a_wi<198> a_wi<197> a_wi<196> a_wi<195> a_wi<194> a_wi<193> a_wi<192> a_wi<191> a_wi<190> a_wi<189> a_wi<188> a_wi<187> a_wi<186> a_wi<185> a_wi<184> a_wi<183> a_wi<182> a_wi<181> a_wi<180> a_wi<179> a_wi<178> a_wi<177> a_wi<176> a_wi<175> a_wi<174> a_wi<173> a_wi<172> a_wi<171> a_wi<170> a_wi<169> a_wi<168> a_wi<167> a_wi<166> a_wi<165> a_wi<164> a_wi<163> a_wi<162> a_wi<161> a_wi<160> a_wi<159> a_wi<158> a_wi<157> a_wi<156> a_wi<155> a_wi<154> a_wi<153> a_wi<152> a_wi<151> a_wi<150> a_wi<149> a_wi<148> a_wi<147> a_wi<146> a_wi<145> a_wi<144> a_wi<143> a_wi<142> a_wi<141> a_wi<140> a_wi<139> a_wi<138> a_wi<137> a_wi<136> a_wi<135> a_wi<134> a_wi<133> a_wi<132> a_wi<131> a_wi<130> a_wi<129> a_wi<128> a_wi<127> a_wi<126> a_wi<125> a_wi<124> a_wi<123> a_wi<122> a_wi<121> a_wi<120> a_wi<119> a_wi<118> a_wi<117> a_wi<116> a_wi<115> a_wi<114> a_wi<113> a_wi<112> a_wi<111> a_wi<110> a_wi<109> a_wi<108> a_wi<107> a_wi<106> a_wi<105> a_wi<104> a_wi<103> a_wi<102> a_wi<101> a_wi<100> a_wi<99> a_wi<98> a_wi<97> a_wi<96> a_wi<95> a_wi<94> a_wi<93> a_wi<92> a_wi<91> a_wi<90> a_wi<89> a_wi<88> a_wi<87> a_wi<86> a_wi<85> a_wi<84> a_wi<83> a_wi<82> a_wi<81> a_wi<80> a_wi<79> a_wi<78> a_wi<77> a_wi<76> a_wi<75> a_wi<74> a_wi<73> a_wi<72> a_wi<71> a_wi<70> a_wi<69> a_wi<68> a_wi<67> a_wi<66> a_wi<65> a_wi<64> a_wi<63> a_wi<62> a_wi<61> a_wi<60> a_wi<59> a_wi<58> a_wi<57> a_wi<56> a_wi<55> a_wi<54> a_wi<53> a_wi<52> a_wi<51> a_wi<50> a_wi<49> a_wi<48> a_wi<47> a_wi<46> a_wi<45> a_wi<44> a_wi<43> a_wi<42> a_wi<41> a_wi<40> a_wi<39> a_wi<38> a_wi<37> a_wi<36> a_wi<35> a_wi<34> a_wi<33> a_wi<32> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_ROWDEC9 +XA_ROWREG a_aclk_n A_ADDR<11> A_ADDR<10> A_ADDR<9> A_ADDR<8> A_ADDR<7> A_ADDR<6> A_ADDR<5> A_ADDR<4> A_ADDR<3> a_addr_row<8> a_addr_row<7> a_addr_row<6> a_addr_row<5> a_addr_row<4> a_addr_row<3> a_addr_row<2> a_addr_row<1> a_addr_row<0> A_BIST_ADDR<11> A_BIST_ADDR<10> A_BIST_ADDR<9> A_BIST_ADDR<8> A_BIST_ADDR<7> A_BIST_ADDR<6> A_BIST_ADDR<5> A_BIST_ADDR<4> A_BIST_ADDR<3> A_BIST_EN VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_ROWREG9 +XA_COLDEC a_aclk_n A_ADDR<2> A_ADDR<1> A_ADDR<0> a_addr_col<1> a_addr_col<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> A_BIST_ADDR<2> A_BIST_ADDR<1> A_BIST_ADDR<0> A_BIST_EN VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_COLDEC3 + + +XA_DLYH a_pulse a_pulse_h VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_DLY_pcell_2 +XA_DLYL a_pulse_x a_pulse_l VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_DLY_pcell_3 +XA_DLYMUX a_pulse_h A_DLY a_pulse_x VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_DLY_MUX + +XCOLCTRL<15> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<15> A_BIST_DIN<15> A_BIST_EN a_blc_r<63> a_blc_r<62> a_blc_r<61> a_blc_r<60> a_blc_r<59> a_blc_r<58> a_blc_r<57> a_blc_r<56> a_blt_r<63> a_blt_r<62> a_blt_r<61> a_blt_r<60> a_blt_r<59> a_blt_r<58> a_blt_r<57> a_blt_r<56> A_BM<15> a_dclk_n_r<7> a_dclk_n_r<8> a_dclk_p_r<7> a_dclk_p_r<8> A_DOUT<15> A_DIN<15> a_rclk_n_r<7> a_rclk_n_r<8> a_rclk_p_r<7> a_rclk_p_r<8> a_tieh<15> a_wclk_n_r<7> a_wclk_n_r<8> a_wclk_p_r<7> a_wclk_p_r<8> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_COLCTRL3 +XCOLCTRL<14> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<14> A_BIST_DIN<14> A_BIST_EN a_blc_r<55> a_blc_r<54> a_blc_r<53> a_blc_r<52> a_blc_r<51> a_blc_r<50> a_blc_r<49> a_blc_r<48> a_blt_r<55> a_blt_r<54> a_blt_r<53> a_blt_r<52> a_blt_r<51> a_blt_r<50> a_blt_r<49> a_blt_r<48> A_BM<14> a_dclk_n_r<6> a_dclk_n_r<7> a_dclk_p_r<6> a_dclk_p_r<7> A_DOUT<14> A_DIN<14> a_rclk_n_r<6> a_rclk_n_r<7> a_rclk_p_r<6> a_rclk_p_r<7> a_tieh<14> a_wclk_n_r<6> a_wclk_n_r<7> a_wclk_p_r<6> a_wclk_p_r<7> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_COLCTRL3 +XCOLCTRL<13> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<13> A_BIST_DIN<13> A_BIST_EN a_blc_r<47> a_blc_r<46> a_blc_r<45> a_blc_r<44> a_blc_r<43> a_blc_r<42> a_blc_r<41> a_blc_r<40> a_blt_r<47> a_blt_r<46> a_blt_r<45> a_blt_r<44> a_blt_r<43> a_blt_r<42> a_blt_r<41> a_blt_r<40> A_BM<13> a_dclk_n_r<5> a_dclk_n_r<6> a_dclk_p_r<5> a_dclk_p_r<6> A_DOUT<13> A_DIN<13> a_rclk_n_r<5> a_rclk_n_r<6> a_rclk_p_r<5> a_rclk_p_r<6> a_tieh<13> a_wclk_n_r<5> a_wclk_n_r<6> a_wclk_p_r<5> a_wclk_p_r<6> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_COLCTRL3 +XCOLCTRL<12> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<12> A_BIST_DIN<12> A_BIST_EN a_blc_r<39> a_blc_r<38> a_blc_r<37> a_blc_r<36> a_blc_r<35> a_blc_r<34> a_blc_r<33> a_blc_r<32> a_blt_r<39> a_blt_r<38> a_blt_r<37> a_blt_r<36> a_blt_r<35> a_blt_r<34> a_blt_r<33> a_blt_r<32> A_BM<12> a_dclk_n_r<4> a_dclk_n_r<5> a_dclk_p_r<4> a_dclk_p_r<5> A_DOUT<12> A_DIN<12> a_rclk_n_r<4> a_rclk_n_r<5> a_rclk_p_r<4> a_rclk_p_r<5> a_tieh<12> a_wclk_n_r<4> a_wclk_n_r<5> a_wclk_p_r<4> a_wclk_p_r<5> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_COLCTRL3 +XCOLCTRL<11> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<11> A_BIST_DIN<11> A_BIST_EN a_blc_r<31> a_blc_r<30> a_blc_r<29> a_blc_r<28> a_blc_r<27> a_blc_r<26> a_blc_r<25> a_blc_r<24> a_blt_r<31> a_blt_r<30> a_blt_r<29> a_blt_r<28> a_blt_r<27> a_blt_r<26> a_blt_r<25> a_blt_r<24> A_BM<11> a_dclk_n_r<3> a_dclk_n_r<4> a_dclk_p_r<3> a_dclk_p_r<4> A_DOUT<11> A_DIN<11> a_rclk_n_r<3> a_rclk_n_r<4> a_rclk_p_r<3> a_rclk_p_r<4> a_tieh<11> a_wclk_n_r<3> a_wclk_n_r<4> a_wclk_p_r<3> a_wclk_p_r<4> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_COLCTRL3 +XCOLCTRL<10> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<10> A_BIST_DIN<10> A_BIST_EN a_blc_r<23> a_blc_r<22> a_blc_r<21> a_blc_r<20> a_blc_r<19> a_blc_r<18> a_blc_r<17> a_blc_r<16> a_blt_r<23> a_blt_r<22> a_blt_r<21> a_blt_r<20> a_blt_r<19> a_blt_r<18> a_blt_r<17> a_blt_r<16> A_BM<10> a_dclk_n_r<2> a_dclk_n_r<3> a_dclk_p_r<2> a_dclk_p_r<3> A_DOUT<10> A_DIN<10> a_rclk_n_r<2> a_rclk_n_r<3> a_rclk_p_r<2> a_rclk_p_r<3> a_tieh<10> a_wclk_n_r<2> a_wclk_n_r<3> a_wclk_p_r<2> a_wclk_p_r<3> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_COLCTRL3 +XCOLCTRL<9> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<9> A_BIST_DIN<9> A_BIST_EN a_blc_r<15> a_blc_r<14> a_blc_r<13> a_blc_r<12> a_blc_r<11> a_blc_r<10> a_blc_r<9> a_blc_r<8> a_blt_r<15> a_blt_r<14> a_blt_r<13> a_blt_r<12> a_blt_r<11> a_blt_r<10> a_blt_r<9> a_blt_r<8> A_BM<9> a_dclk_n_r<1> a_dclk_n_r<2> a_dclk_p_r<1> a_dclk_p_r<2> A_DOUT<9> A_DIN<9> a_rclk_n_r<1> a_rclk_n_r<2> a_rclk_p_r<1> a_rclk_p_r<2> a_tieh<9> a_wclk_n_r<1> a_wclk_n_r<2> a_wclk_p_r<1> a_wclk_p_r<2> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_COLCTRL3 +XCOLCTRL<8> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<8> A_BIST_DIN<8> A_BIST_EN a_blc_r<7> a_blc_r<6> a_blc_r<5> a_blc_r<4> a_blc_r<3> a_blc_r<2> a_blc_r<1> a_blc_r<0> a_blt_r<7> a_blt_r<6> a_blt_r<5> a_blt_r<4> a_blt_r<3> a_blt_r<2> a_blt_r<1> a_blt_r<0> A_BM<8> a_dclk_n_r<0> a_dclk_n_r<1> a_dclk_p_r<0> a_dclk_p_r<1> A_DOUT<8> A_DIN<8> a_rclk_n_r<0> a_rclk_n_r<1> a_rclk_p_r<0> a_rclk_p_r<1> a_tieh<8> a_wclk_n_r<0> a_wclk_n_r<1> a_wclk_p_r<0> a_wclk_p_r<1> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_COLCTRL3 +XCOLCTRL<7> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<0> A_BIST_DIN<0> A_BIST_EN a_blc_l<63> a_blc_l<62> a_blc_l<61> a_blc_l<60> a_blc_l<59> a_blc_l<58> a_blc_l<57> a_blc_l<56> a_blt_l<63> a_blt_l<62> a_blt_l<61> a_blt_l<60> a_blt_l<59> a_blt_l<58> a_blt_l<57> a_blt_l<56> A_BM<0> a_dclk_n_l<7> a_dclk_n_l<8> a_dclk_p_l<7> a_dclk_p_l<8> A_DOUT<0> A_DIN<0> a_rclk_n_l<7> a_rclk_n_l<8> a_rclk_p_l<7> a_rclk_p_l<8> a_tieh<0> a_wclk_n_l<7> a_wclk_n_l<8> a_wclk_p_l<7> a_wclk_p_l<8> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_COLCTRL3 +XCOLCTRL<6> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<1> A_BIST_DIN<1> A_BIST_EN a_blc_l<55> a_blc_l<54> a_blc_l<53> a_blc_l<52> a_blc_l<51> a_blc_l<50> a_blc_l<49> a_blc_l<48> a_blt_l<55> a_blt_l<54> a_blt_l<53> a_blt_l<52> a_blt_l<51> a_blt_l<50> a_blt_l<49> a_blt_l<48> A_BM<1> a_dclk_n_l<6> a_dclk_n_l<7> a_dclk_p_l<6> a_dclk_p_l<7> A_DOUT<1> A_DIN<1> a_rclk_n_l<6> a_rclk_n_l<7> a_rclk_p_l<6> a_rclk_p_l<7> a_tieh<1> a_wclk_n_l<6> a_wclk_n_l<7> a_wclk_p_l<6> a_wclk_p_l<7> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_COLCTRL3 +XCOLCTRL<5> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<2> A_BIST_DIN<2> A_BIST_EN a_blc_l<47> a_blc_l<46> a_blc_l<45> a_blc_l<44> a_blc_l<43> a_blc_l<42> a_blc_l<41> a_blc_l<40> a_blt_l<47> a_blt_l<46> a_blt_l<45> a_blt_l<44> a_blt_l<43> a_blt_l<42> a_blt_l<41> a_blt_l<40> A_BM<2> a_dclk_n_l<5> a_dclk_n_l<6> a_dclk_p_l<5> a_dclk_p_l<6> A_DOUT<2> A_DIN<2> a_rclk_n_l<5> a_rclk_n_l<6> a_rclk_p_l<5> a_rclk_p_l<6> a_tieh<2> a_wclk_n_l<5> a_wclk_n_l<6> a_wclk_p_l<5> a_wclk_p_l<6> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_COLCTRL3 +XCOLCTRL<4> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<3> A_BIST_DIN<3> A_BIST_EN a_blc_l<39> a_blc_l<38> a_blc_l<37> a_blc_l<36> a_blc_l<35> a_blc_l<34> a_blc_l<33> a_blc_l<32> a_blt_l<39> a_blt_l<38> a_blt_l<37> a_blt_l<36> a_blt_l<35> a_blt_l<34> a_blt_l<33> a_blt_l<32> A_BM<3> a_dclk_n_l<4> a_dclk_n_l<5> a_dclk_p_l<4> a_dclk_p_l<5> A_DOUT<3> A_DIN<3> a_rclk_n_l<4> a_rclk_n_l<5> a_rclk_p_l<4> a_rclk_p_l<5> a_tieh<3> a_wclk_n_l<4> a_wclk_n_l<5> a_wclk_p_l<4> a_wclk_p_l<5> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_COLCTRL3 +XCOLCTRL<3> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<4> A_BIST_DIN<4> A_BIST_EN a_blc_l<31> a_blc_l<30> a_blc_l<29> a_blc_l<28> a_blc_l<27> a_blc_l<26> a_blc_l<25> a_blc_l<24> a_blt_l<31> a_blt_l<30> a_blt_l<29> a_blt_l<28> a_blt_l<27> a_blt_l<26> a_blt_l<25> a_blt_l<24> A_BM<4> a_dclk_n_l<3> a_dclk_n_l<4> a_dclk_p_l<3> a_dclk_p_l<4> A_DOUT<4> A_DIN<4> a_rclk_n_l<3> a_rclk_n_l<4> a_rclk_p_l<3> a_rclk_p_l<4> a_tieh<4> a_wclk_n_l<3> a_wclk_n_l<4> a_wclk_p_l<3> a_wclk_p_l<4> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_COLCTRL3 +XCOLCTRL<2> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<5> A_BIST_DIN<5> A_BIST_EN a_blc_l<23> a_blc_l<22> a_blc_l<21> a_blc_l<20> a_blc_l<19> a_blc_l<18> a_blc_l<17> a_blc_l<16> a_blt_l<23> a_blt_l<22> a_blt_l<21> a_blt_l<20> a_blt_l<19> a_blt_l<18> a_blt_l<17> a_blt_l<16> A_BM<5> a_dclk_n_l<2> a_dclk_n_l<3> a_dclk_p_l<2> a_dclk_p_l<3> A_DOUT<5> A_DIN<5> a_rclk_n_l<2> a_rclk_n_l<3> a_rclk_p_l<2> a_rclk_p_l<3> a_tieh<5> a_wclk_n_l<2> a_wclk_n_l<3> a_wclk_p_l<2> a_wclk_p_l<3> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_COLCTRL3 +XCOLCTRL<1> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<6> A_BIST_DIN<6> A_BIST_EN a_blc_l<15> a_blc_l<14> a_blc_l<13> a_blc_l<12> a_blc_l<11> a_blc_l<10> a_blc_l<9> a_blc_l<8> a_blt_l<15> a_blt_l<14> a_blt_l<13> a_blt_l<12> a_blt_l<11> a_blt_l<10> a_blt_l<9> a_blt_l<8> A_BM<6> a_dclk_n_l<1> a_dclk_n_l<2> a_dclk_p_l<1> a_dclk_p_l<2> A_DOUT<6> A_DIN<6> a_rclk_n_l<1> a_rclk_n_l<2> a_rclk_p_l<1> a_rclk_p_l<2> a_tieh<6> a_wclk_n_l<1> a_wclk_n_l<2> a_wclk_p_l<1> a_wclk_p_l<2> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_COLCTRL3 +XCOLCTRL<0> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<7> A_BIST_DIN<7> A_BIST_EN a_blc_l<7> a_blc_l<6> a_blc_l<5> a_blc_l<4> a_blc_l<3> a_blc_l<2> a_blc_l<1> a_blc_l<0> a_blt_l<7> a_blt_l<6> a_blt_l<5> a_blt_l<4> a_blt_l<3> a_blt_l<2> a_blt_l<1> a_blt_l<0> A_BM<7> a_dclk_n_l<0> a_dclk_n_l<1> a_dclk_p_l<0> a_dclk_p_l<1> A_DOUT<7> A_DIN<7> a_rclk_n_l<0> a_rclk_n_l<1> a_rclk_p_l<0> a_rclk_p_l<1> a_tieh<7> a_wclk_n_l<0> a_wclk_n_l<1> a_wclk_p_l<0> a_wclk_p_l<1> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_COLCTRL3 + + +XDRVFILL4<1> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_COLDRV13_FILL4 +XDRVFILL4<2> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_COLDRV13_FILL4 +.ENDS diff --git a/flow/platforms/ihp-sg13g2/cdl/RM_IHPSG13_1P_4096x8_c3_bm_bist.cdl b/flow/platforms/ihp-sg13g2/cdl/RM_IHPSG13_1P_4096x8_c3_bm_bist.cdl new file mode 100644 index 0000000000..408d8604c9 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/cdl/RM_IHPSG13_1P_4096x8_c3_bm_bist.cdl @@ -0,0 +1,6457 @@ +* ------------------------------------------------------ +* +* Copyright 2024 IHP PDK Authors +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* https://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* +* Generated on Fri Jul 19 08:59:30 2024 +* +* ------------------------------------------------------ + +.SUBCKT RM_IHPSG13_4096x8_c3_1P_BITKIT_CORNER NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_CORNER VDD_CORE VSS +XI16 VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x8_c3_1P_BITKIT_CORNER +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_1P_BITKIT_EDGE_LR LWL NW PW VDD VSS +MN1 VSS LWL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN0 VSS net9 VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR A_WL<15> A_WL<14> A_WL<13> A_WL<12> ++ A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> ++ A_WL<2> A_WL<1> A_WL<0> VDD_CORE VSS +XI0<15> A_WL<15> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x8_c3_1P_BITKIT_EDGE_LR +XI0<14> A_WL<14> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x8_c3_1P_BITKIT_EDGE_LR +XI0<13> A_WL<13> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x8_c3_1P_BITKIT_EDGE_LR +XI0<12> A_WL<12> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x8_c3_1P_BITKIT_EDGE_LR +XI0<11> A_WL<11> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x8_c3_1P_BITKIT_EDGE_LR +XI0<10> A_WL<10> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x8_c3_1P_BITKIT_EDGE_LR +XI0<9> A_WL<9> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x8_c3_1P_BITKIT_EDGE_LR +XI0<8> A_WL<8> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x8_c3_1P_BITKIT_EDGE_LR +XI0<7> A_WL<7> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x8_c3_1P_BITKIT_EDGE_LR +XI0<6> A_WL<6> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x8_c3_1P_BITKIT_EDGE_LR +XI0<5> A_WL<5> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x8_c3_1P_BITKIT_EDGE_LR +XI0<4> A_WL<4> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x8_c3_1P_BITKIT_EDGE_LR +XI0<3> A_WL<3> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x8_c3_1P_BITKIT_EDGE_LR +XI0<2> A_WL<2> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x8_c3_1P_BITKIT_EDGE_LR +XI0<1> A_WL<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x8_c3_1P_BITKIT_EDGE_LR +XI0<0> A_WL<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x8_c3_1P_BITKIT_EDGE_LR +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_1P_BITKIT_CELL BLC_BOT BLC_TOP BLT_BOT BLT_TOP LWL NW PW ++ RWL VDD VSS +MN0 NC NT VSS PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN1 NT NC VSS PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN3 NC RWL BLC_TOP PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN2 BLT_BOT LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MP1 NT NC VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 NC NT VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +R1 BLC_BOT BLC_TOP lvsres w=2.6e-07 l=6e-07 +R0 BLT_BOT BLT_TOP lvsres w=2.6e-07 l=6e-07 +R2 RWL LWL lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_SRAM A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> ++ A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<15> ++ A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> ++ A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> ++ A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> ++ A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> VDD_CORE ++ VSS +XCELL<31> A_BLC_TOP<1> A_RBLC<15> A_BLT_TOP<1> A_RBLT<15> A_RWL<15> ++ VDD_CORE VSS A_XWL<15> VDD_CORE VSS / ++ RM_IHPSG13_4096x8_c3_1P_BITKIT_CELL +XCELL<30> A_RBLC<14> A_RBLC<15> A_RBLT<14> A_RBLT<15> A_RWL<14> VDD_CORE ++ VSS A_XWL<14> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_CELL +XCELL<29> A_RBLC<14> A_RBLC<13> A_RBLT<14> A_RBLT<13> A_RWL<13> VDD_CORE ++ VSS A_XWL<13> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_CELL +XCELL<28> A_RBLC<12> A_RBLC<13> A_RBLT<12> A_RBLT<13> A_RWL<12> VDD_CORE ++ VSS A_XWL<12> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_CELL +XCELL<27> A_RBLC<12> A_RBLC<11> A_RBLT<12> A_RBLT<11> A_RWL<11> VDD_CORE ++ VSS A_XWL<11> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_CELL +XCELL<26> A_RBLC<10> A_RBLC<11> A_RBLT<10> A_RBLT<11> A_RWL<10> VDD_CORE ++ VSS A_XWL<10> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_CELL +XCELL<25> A_RBLC<10> A_RBLC<9> A_RBLT<10> A_RBLT<9> A_RWL<9> VDD_CORE ++ VSS A_XWL<9> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_CELL +XCELL<24> A_RBLC<8> A_RBLC<9> A_RBLT<8> A_RBLT<9> A_RWL<8> VDD_CORE ++ VSS A_XWL<8> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_CELL +XCELL<23> A_RBLC<8> A_RBLC<7> A_RBLT<8> A_RBLT<7> A_RWL<7> VDD_CORE ++ VSS A_XWL<7> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_CELL +XCELL<22> A_RBLC<6> A_RBLC<7> A_RBLT<6> A_RBLT<7> A_RWL<6> VDD_CORE ++ VSS A_XWL<6> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_CELL +XCELL<21> A_RBLC<6> A_RBLC<5> A_RBLT<6> A_RBLT<5> A_RWL<5> VDD_CORE ++ VSS A_XWL<5> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_CELL +XCELL<20> A_RBLC<4> A_RBLC<5> A_RBLT<4> A_RBLT<5> A_RWL<4> VDD_CORE ++ VSS A_XWL<4> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_CELL +XCELL<19> A_RBLC<4> A_RBLC<3> A_RBLT<4> A_RBLT<3> A_RWL<3> VDD_CORE ++ VSS A_XWL<3> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_CELL +XCELL<18> A_RBLC<2> A_RBLC<3> A_RBLT<2> A_RBLT<3> A_RWL<2> VDD_CORE ++ VSS A_XWL<2> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_CELL +XCELL<17> A_RBLC<2> A_RBLC<1> A_RBLT<2> A_RBLT<1> A_RWL<1> VDD_CORE ++ VSS A_XWL<1> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_CELL +XCELL<16> A_BLC_BOT<1> A_RBLC<1> A_BLT_BOT<1> A_RBLT<1> A_RWL<0> VDD_CORE ++ VSS A_XWL<0> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_CELL +XCELL<15> A_BLC_TOP<0> A_LBLC<15> A_BLT_TOP<0> A_LBLT<15> A_LWL<15> ++ VDD_CORE VSS A_XWL<15> VDD_CORE VSS / ++ RM_IHPSG13_4096x8_c3_1P_BITKIT_CELL +XCELL<14> A_LBLC<14> A_LBLC<15> A_LBLT<14> A_LBLT<15> A_LWL<14> VDD_CORE ++ VSS A_XWL<14> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_CELL +XCELL<13> A_LBLC<14> A_LBLC<13> A_LBLT<14> A_LBLT<13> A_LWL<13> VDD_CORE ++ VSS A_XWL<13> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_CELL +XCELL<12> A_LBLC<12> A_LBLC<13> A_LBLT<12> A_LBLT<13> A_LWL<12> VDD_CORE ++ VSS A_XWL<12> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_CELL +XCELL<11> A_LBLC<12> A_LBLC<11> A_LBLT<12> A_LBLT<11> A_LWL<11> VDD_CORE ++ VSS A_XWL<11> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_CELL +XCELL<10> A_LBLC<10> A_LBLC<11> A_LBLT<10> A_LBLT<11> A_LWL<10> VDD_CORE ++ VSS A_XWL<10> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_CELL +XCELL<9> A_LBLC<10> A_LBLC<9> A_LBLT<10> A_LBLT<9> A_LWL<9> VDD_CORE ++ VSS A_XWL<9> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_CELL +XCELL<8> A_LBLC<8> A_LBLC<9> A_LBLT<8> A_LBLT<9> A_LWL<8> VDD_CORE ++ VSS A_XWL<8> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_CELL +XCELL<7> A_LBLC<8> A_LBLC<7> A_LBLT<8> A_LBLT<7> A_LWL<7> VDD_CORE ++ VSS A_XWL<7> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_CELL +XCELL<6> A_LBLC<6> A_LBLC<7> A_LBLT<6> A_LBLT<7> A_LWL<6> VDD_CORE ++ VSS A_XWL<6> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_CELL +XCELL<5> A_LBLC<6> A_LBLC<5> A_LBLT<6> A_LBLT<5> A_LWL<5> VDD_CORE ++ VSS A_XWL<5> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_CELL +XCELL<4> A_LBLC<4> A_LBLC<5> A_LBLT<4> A_LBLT<5> A_LWL<4> VDD_CORE ++ VSS A_XWL<4> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_CELL +XCELL<3> A_LBLC<4> A_LBLC<3> A_LBLT<4> A_LBLT<3> A_LWL<3> VDD_CORE ++ VSS A_XWL<3> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_CELL +XCELL<2> A_LBLC<2> A_LBLC<3> A_LBLT<2> A_LBLT<3> A_LWL<2> VDD_CORE ++ VSS A_XWL<2> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_CELL +XCELL<1> A_LBLC<2> A_LBLC<1> A_LBLT<2> A_LBLT<1> A_LWL<1> VDD_CORE ++ VSS A_XWL<1> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_CELL +XCELL<0> A_BLC_BOT<0> A_LBLC<1> A_BLT_BOT<0> A_LBLT<1> A_LWL<0> VDD_CORE ++ VSS A_XWL<0> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_CELL +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_1P_BITKIT_EDGE_TB BLC BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_TB A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ VDD_CORE VSS +XEDGE<1> A_BLC<1> A_BLT<1> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_4096x8_c3_1P_BITKIT_EDGE_TB +XEDGE<0> A_BLC<0> A_BLT<0> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_4096x8_c3_1P_BITKIT_EDGE_TB +.ENDS + +.SUBCKT RSC_IHPSG13_CBUFX4 A Z VDD VSS +MN0 net9 A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 Z net9 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MP0 net9 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP1 Z net9 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_1P_COLDRV13X4 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX4 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_1P_WLDRV16X4 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX4 +.ENDS +.SUBCKT RSC_IHPSG13_FILLCAP8 VDD VSS +MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=4.98u l=130.00n ng=6 nrd=0 ++ nrs=0 +MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=6.48u l=385.000n ng=4 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_LHPQX2 CP D Q VDD VSS +MN3 QIN CPN net14 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN2 net14 net10 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN5 net21 D VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN6 QIN CP net21 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net10 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 CPN CP VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 Q QIN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP2 QIN CP net16 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 CPN CP VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 Q QIN VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP3 net10 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net16 net10 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP6 QIN CPN net20 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP5 net20 D VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_NAND2X2 A B Z VDD VSS +MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z B net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net7 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX4 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX2 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_INVX2 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_NAND3X2 A B C Z VDD VSS +MP2 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z C VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN1 net12 B net16 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z C net12 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN2 net16 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_NOR3X2 A B C Z VDD VSS +MP0 net13 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z C net10 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP1 net10 B net13 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN1 Z B VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z C VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0 +MN2 Z A VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_FILLCAP4 VDD VSS +MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=2.49u l=130.00n ng=3 nrd=0 ++ nrs=0 +MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=3.24u l=385.000n ng=2 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_MET2RES A B +R0 B A lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_1P_DEC04 ADDR<3> ADDR<2> ADDR<1> ADDR<0> CS ECLK_H_BOT ++ ECLK_H_TOP ECLK_L_BOT ECLK_L_TOP WL<15> WL<14> WL<13> WL<12> WL<11> WL<10> ++ WL<9> WL<8> WL<7> WL<6> WL<5> WL<4> WL<3> WL<2> WL<1> WL<0> VDD VSS +XLATCH<3> CS ADDR<3> PADR<3> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<2> CS ADDR<2> PADR<2> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<1> CS ADDR<1> PADR<1> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<0> CS ADDR<0> PADR<0> VDD VSS / RSC_IHPSG13_LHPQX2 +XI0<3> PADR<1> PADR<0> sel01<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<2> PADR<1> NADR<0> sel01<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<1> NADR<1> PADR<0> sel01<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<0> NADR<1> NADR<0> sel01<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI4 ECLK_L_BOT EN VDD VSS / RSC_IHPSG13_CINVX4 +XI5 ECLK_H_BOT ECLK_L_BOT VDD VSS / RSC_IHPSG13_CINVX2 +XI3<3> PADR<3> NADR<3> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> PADR<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> PADR<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> PADR<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI1<3> PADR<2> PADR<3> CS sel23<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<2> PADR<3> CS sel23<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<2> NADR<3> CS sel23<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<2> NADR<3> CS sel23<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI2<15> sel23<3> sel01<3> EN WL<15> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<14> sel23<3> sel01<2> EN WL<14> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<13> sel23<3> sel01<1> EN WL<13> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<12> sel23<3> sel01<0> EN WL<12> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<11> sel23<2> sel01<3> EN WL<11> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<10> sel23<2> sel01<2> EN WL<10> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<9> sel23<2> sel01<1> EN WL<9> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<8> sel23<2> sel01<0> EN WL<8> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<7> sel23<1> sel01<3> EN WL<7> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<6> sel23<1> sel01<2> EN WL<6> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<5> sel23<1> sel01<1> EN WL<5> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<4> sel23<1> sel01<0> EN WL<4> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<3> sel23<0> sel01<3> EN WL<3> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<2> sel23<0> sel01<2> EN WL<2> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<1> sel23<0> sel01<1> EN WL<1> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<0> sel23<0> sel01<0> EN WL<0> VDD VSS / RSC_IHPSG13_NOR3X2 +XCAPS4 VDD VSS / RSC_IHPSG13_FILLCAP4 +XI11 ECLK_L_BOT ECLK_L_TOP / RSC_IHPSG13_MET2RES +XR0 ECLK_H_BOT ECLK_H_TOP / RSC_IHPSG13_MET2RES +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_1P_ROWDEC4 ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> ++ CS_I ECLK_I WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XSEL ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ECLK_H<1> ++ ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> ++ WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> ++ WL_O<0> VDD VSS / RM_IHPSG13_4096x8_c3_1P_DEC04 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX8 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=2.82u l=130.00n ng=4 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_DFNQMX2IX1 BE BI CN D QI QIN VDD VSS +MN15 net026 BI VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN14 MXI_OUT BE net026 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net025 D VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 MXI_OUT BEN net025 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN10 QI CNN net21 VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 nrd=0 nrs=0 +MN11 net21 QI_MS VSS VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN7 net30 QI_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN6 QIN_MS CNN net30 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 QI_MS QIN_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN12 CNN CN VSS VSS sg13_lv_nmos m=1 w=495.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN9 net37 MXI_OUT VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN8 QIN_MS CN net37 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 QI CN net25 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN4 net25 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 QIN QI VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN13 BEN BE VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP15 MXI_OUT BEN net027 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP14 net027 BI VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP1 MXI_OUT BE net024 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 net024 D VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP13 BEN BE VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP6 QI_MS QIN_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP3 QI CNN net27 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MP2 net27 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP10 net36 MXI_OUT VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP11 QIN_MS CNN net36 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net32 QI_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP5 QIN_MS CN net32 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 QIN QI VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP12 CNN CN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP9 QI CN net19 VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 nrd=0 nrs=0 +MP8 net19 QI_MS VDD VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_1P_ROWREG4 ACLK_N_I ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RSC_IHPSG13_CDLYX1 A Z VDD VSS +MN1 net010 net032 VSS VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 ++ nrd=0 nrs=0 +MN2 net032 A net014 VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 ++ nrs=0 +MN0 Z net032 net010 VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 ++ nrs=0 +MN3 net014 A VSS VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 ++ nrs=0 +MP1 Z net032 net07 VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 ++ nrs=0 +MP3 net011 A VDD VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 ++ nrs=0 +MP0 net07 net032 VDD VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 ++ nrd=0 nrs=0 +MP2 net032 A net011 VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CDLYX1_DUMMY A Z VDD VSS +MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=2.49u l=300.0n ng=3 nrd=0 ++ nrs=0 +MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=3.24u l=640.00n ng=2 nrd=0 ++ nrs=0 +R0 Z A lvsres w=2.6e-07 l=6e-07 +.ENDS + +.SUBCKT RSC_IHPSG13_MX2IX1 A0 A1 S ZN VDD VSS +MP4 SN S VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 nrs=0 +MP3 ZN SN net12 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 nrs=0 +MP2 net12 A1 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 ZN S net17 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 nrs=0 +MP0 net17 A0 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 SN S VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN3 net13 A1 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 ZN S net13 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net15 A0 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 ZN SN net15 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_1P_DLY_MUX A SEL Z VDD VSS +XI11 net4 Z VDD VSS / RSC_IHPSG13_CINVX2 +XI8 A D<3> SEL net4 VDD VSS / RSC_IHPSG13_MX2IX1 +XI20<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1 +.ENDS +.SUBCKT RSC_IHPSG13_DFNQX2 CN D Q VDD VSS +MN0 Q QIN_SL VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN10 QIN_SL CNN net21 VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN11 net21 QI_MS VSS VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN7 net30 QI_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN6 QIN_MS CNN net30 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 QI_MS QIN_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN12 CNN CN VSS VSS sg13_lv_nmos m=1 w=495.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN9 net37 D VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN8 QIN_MS CN net37 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 QIN_SL CN net25 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net25 QI_SL VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN2 QI_SL QIN_SL VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP0 Q QIN_SL VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP6 QI_MS QIN_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP3 QIN_SL CNN net27 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 net27 QI_SL VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP10 net36 D VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP11 QIN_MS CNN net36 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net32 QI_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP5 QIN_MS CN net32 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 QI_SL QIN_SL VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP12 CNN CN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP9 QIN_SL CN net19 VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP8 net19 QI_MS VDD VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CNAND2X2 A B Z VDD VSS +MN0 Z B net6 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 net6 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CGATEPX4 CP E Q VDD VSS +MN1 net08 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 net019 net08 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN3 QIN CP net019 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0 +MN6 Q net015 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 ++ nrs=0 +MN5 net015 net08 net018 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MN8 QIN CPN net023 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN7 net023 E VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net018 CP VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 CPN CP VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP3 net08 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 QIN CPN net017 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net017 net08 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP0 CPN CP VDD VDD sg13_lv_pmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP8 QIN CP net024 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 net024 E VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net015 CP VDD VDD sg13_lv_pmos m=1 w=1.27u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP6 Q net015 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 ++ nrs=0 +MP5 net015 net08 VDD VDD sg13_lv_pmos m=1 w=1.27u l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CBUFX8 A Z VDD VSS +MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0 +MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=2.82u l=130.00n ng=4 nrd=0 nrs=0 +MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CDLYX2 A Z VDD VSS +MN2 net4 A net9 VSS sg13_lv_nmos m=1 w=320.00n l=200.0n ng=1 nrd=0 nrs=0 +MN0 Z net4 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net9 A VSS VSS sg13_lv_nmos m=1 w=320.00n l=200.0n ng=1 nrd=0 nrs=0 +MP2 net4 A net10 VDD sg13_lv_pmos m=1 w=1.2u l=200.0n ng=1 nrd=0 nrs=0 +MP1 net10 A VDD VDD sg13_lv_pmos m=1 w=1.2u l=200.0n ng=1 nrd=0 nrs=0 +MP0 Z net4 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_MX2X2 A0 A1 S Z VDD VSS +MP6 Z net010 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 SN S VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 nrs=0 +MP3 net010 SN net12 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 net12 A1 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net010 S net17 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 net17 A0 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN6 Z net010 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 SN S VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 nrs=0 +MN3 net13 A1 VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 net010 S net13 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net15 A0 VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 net010 SN net15 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_AND2X2 A B Z VDD VSS +MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_TIEL Z VDD VSS +MN0 Z net2 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 net2 net2 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_XOR2X2 A B Z VDD VSS +MP8 net012 B net7 VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP7 net011 net3 net012 VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP6 Z net012 VDD VDD sg13_lv_pmos m=1 w=1.535u l=130.00n ng=1 nrd=0 ++ nrs=0 +MP2 net7 A VDD VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP4 net011 net7 VDD VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +MP5 net3 B VDD VDD sg13_lv_pmos m=1 w=580.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN7 net012 B net011 VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN6 net7 net3 net012 VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN5 Z net012 VSS VSS sg13_lv_nmos m=1 w=775.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN2 net7 A VSS VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN4 net3 B VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 net011 net7 VSS VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 ++ nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_OA12X1 A B C Z VDD VSS +MN2 net7 C VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN3 Z net17 VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN1 net17 B net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN0 net17 A net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 net24 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP3 Z net17 VDD VDD sg13_lv_pmos m=1 w=905.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net17 B net24 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP2 net17 C VDD VDD sg13_lv_pmos m=1 w=905.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_1P_CTRL ACLK_N BIST_CK_I BIST_CS_I BIST_EN BIST_RE_I ++ BIST_WE_I B_TIEL_O CK_I CS_I DCLK ECLK PULSE_H PULSE_L PULSE_O RCLK RE_I ++ ROW_CS WCLK WE_I VDD VSS +XI17 ck_regs we col_we VDD VSS / RSC_IHPSG13_DFNQX2 +XI16 ck_regs re col_re VDD VSS / RSC_IHPSG13_DFNQX2 +XI18 ck_regs cs net7 VDD VSS / RSC_IHPSG13_DFNQX2 +XI71 ACLK_N net012 PULSE_O VDD VSS / RSC_IHPSG13_DFNQX2 +XI77 col_we net9 net016 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI76 col_re net9 net018 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI15 ck_dly WEorREandCS aclk VDD VSS / RSC_IHPSG13_CGATEPX4 +XI14 ck WEandCS DCLK VDD VSS / RSC_IHPSG13_CGATEPX4 +XI60 net7 ROW_CS VDD VSS / RSC_IHPSG13_CBUFX8 +XI73 PULSE_O net012 VDD VSS / RSC_IHPSG13_CINVX2 +XI8 net9 net8 VDD VSS / RSC_IHPSG13_CINVX2 +XI64 ck ck_dly VDD VSS / RSC_IHPSG13_CDLYX2 +XI86 CS_I BIST_CS_I BIST_EN cs VDD VSS / RSC_IHPSG13_MX2X2 +XI87 CK_I BIST_CK_I BIST_EN ck VDD VSS / RSC_IHPSG13_MX2X2 +XI85 WE_I BIST_WE_I BIST_EN we VDD VSS / RSC_IHPSG13_MX2X2 +XI84 RE_I BIST_RE_I BIST_EN re VDD VSS / RSC_IHPSG13_MX2X2 +XI22 we cs WEandCS VDD VSS / RSC_IHPSG13_AND2X2 +XBM_TIEL B_TIEL_O VDD VSS / RSC_IHPSG13_TIEL +XI48 ck_dly ck_regs VDD VSS / RSC_IHPSG13_CINVX4 +XI81 net016 WCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI80 net018 RCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI78 net8 net020 VDD VSS / RSC_IHPSG13_CINVX4 +XI6 PULSE_L PULSE_H net9 VDD VSS / RSC_IHPSG13_XOR2X2 +XI79 net020 ECLK VDD VSS / RSC_IHPSG13_CINVX8 +XI63 aclk ACLK_N VDD VSS / RSC_IHPSG13_CINVX8 +XI21 re we cs WEorREandCS VDD VSS / RSC_IHPSG13_OA12X1 +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_1P_COLDEC2 ACLK_N ADDR<1> ADDR<0> ADDR_COL<1> ADDR_COL<0> ++ ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ADDR_DEC<2> ++ ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI14<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI14<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net6<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net6<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI1<3> PADR<1> PADR<0> addr_n<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<2> PADR<1> NADR<0> addr_n<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<1> NADR<1> PADR<0> addr_n<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<0> NADR<1> NADR<0> addr_n<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI16<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI17<3> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_TIEL +XI17<2> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_TIEL +XI17<1> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_TIEL +XI17<0> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RSC_IHPSG13_NOR2X2 A B Z VDD VSS +MP1 Z B net9 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 net9 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MN0 Z B VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN1 Z A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CINVX4_WN A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_1P_BLDRV BLC BLC_SEL BLT BLT_SEL PRE_N SEL_P WR_ONE WR_ZERO ++ VDD VSS +XCDEC SEL_P WR_ZERO BLC_PMOS_DRIVE VDD VSS / RSC_IHPSG13_NAND2X2 +XTDEC SEL_P WR_ONE BLT_PMOS_DRIVE VDD VSS / RSC_IHPSG13_NAND2X2 +MTWN BLT BLT_NMOS_DRIVE VSS VSS sg13_lv_nmos m=1 w=4.82u l=130.00n ++ ng=2 nrd=0 nrs=0 +MCWN BLC BLC_NMOS_DRIVE VSS VSS sg13_lv_nmos m=1 w=4.82u l=130.00n ++ ng=2 nrd=0 nrs=0 +MCWP BLC BLC_PMOS_DRIVE VDD VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 ++ nrd=0 nrs=0 +MTWP BLT BLT_PMOS_DRIVE VDD VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 ++ nrd=0 nrs=0 +MTSP BLT_SEL SEL_N BLT VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 nrd=0 ++ nrs=0 +MTPR BLT PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ng=2 nrd=0 ++ nrs=0 +MCSP BLC_SEL SEL_N BLC VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 nrd=0 ++ nrs=0 +MCPR BLC PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ng=2 nrd=0 ++ nrs=0 +XI86 SEL_P SEL_N VDD VSS / RSC_IHPSG13_INVX2 +XTINV BLC_PMOS_DRIVE BLT_NMOS_DRIVE VDD VSS / RSC_IHPSG13_INVX2 +XCINV BLT_PMOS_DRIVE BLC_NMOS_DRIVE VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RSC_IHPSG13_TIEH Z VDD VSS +MN0 net2 net2 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP0 Z net2 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_MET3RES A B +R0 B A lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RSC_IHPSG13_DFPQD_MSAFFX2 CP DN DP QN QP VDD VSS +MN12 SN RN DIFFP VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN13 TAIL CP VSS VSS sg13_lv_nmos m=1 w=2.4u l=130.00n ng=2 nrd=0 nrs=0 +MN9 DIFFP DP TAIL VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN10 DIFFN DN TAIL VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN11 RN SN DIFFN VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0 +MN19 net33 SN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN20 QN QP net37 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MN18 net37 RN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN17 QP QN net33 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0 +MP15 SN RN VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP16 RN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP14 DIFFP CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP12 RN SN VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP13 DIFFN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP11 SN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0 +MP19 QN QP VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +MP20 QP SN VDD VDD sg13_lv_pmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP18 QN RN VDD VDD sg13_lv_pmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP17 QP QN VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_CBUFX2 A Z VDD VSS +MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 ++ nrs=0 +MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=540.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0 +MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=1.1u l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RSC_IHPSG13_INVX4 A Z VDD VSS +MN0 Z A VSS VSS sg13_lv_nmos m=1 w=1.96u l=130.00n ng=2 nrd=0 nrs=0 +MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_1P_COLCTRL2 A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<3> A_BLC<2> A_BLC<1> ++ A_BLC<0> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_I80 A_WCLK_B_R A_RCLK_B_R net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I44 A_WCLK_B_R A_BM_N A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_ADDR_DEC<2> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_ADDR_DEC<1> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<0> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_R A_RCLK_B_L / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_R A_RCLK_L / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_R A_WCLK_B_L / RSC_IHPSG13_MET3RES +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_I78 A_RCLK_B_R A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_R VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_R A_RCLK_B_R VDD VSS / RSC_IHPSG13_CINVX2 +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_1P_COLDRV13_FILL4 VDD VSS +XI0<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_1P_COLDRV13_FILL4C2 VDD VSS +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_4096x8_c3_1P_COLDEC4 ACLK_N ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<3> BIST_ADDR<2> ++ BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI15 ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI14 addr_int ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int net7<0> VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net7<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net7<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net7<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RSC_IHPSG13_AND2X4 A B Z VDD VSS +MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.96u l=130.00n ng=2 nrd=0 nrs=0 +MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_1P_COLCTRL4 A_ADDR_COL A_ADDR_DEC<7> A_ADDR_DEC<6> ++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<15> A_BLC<14> ++ A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> ++ A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<15> A_BLT<14> ++ A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L ++ A_DCLK_B_R A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L ++ A_RCLK_R A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_I80 A_WCLK_B_L A_RCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DO_WRITE_P A_DI_N A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4 +XA_CAPS<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_N0 A_P0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL A_N0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_I81<1> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_BLTMUX<15> A_BLC<15> A_BLC_SEL A_BLT<15> A_BLT_SEL A_PRE_N A_SEL_P<15> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV +XA_BLTMUX<14> A_BLC<14> A_BLC_SEL A_BLT<14> A_BLT_SEL A_PRE_N A_SEL_P<14> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV +XA_BLTMUX<13> A_BLC<13> A_BLC_SEL A_BLT<13> A_BLT_SEL A_PRE_N A_SEL_P<13> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV +XA_BLTMUX<12> A_BLC<12> A_BLC_SEL A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<12> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV +XA_BLTMUX<11> A_BLC<11> A_BLC_SEL A_BLT<11> A_BLT_SEL A_PRE_N A_SEL_P<11> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV +XA_BLTMUX<10> A_BLC<10> A_BLC_SEL A_BLT<10> A_BLT_SEL A_PRE_N A_SEL_P<10> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV +XA_BLTMUX<9> A_BLC<9> A_BLC_SEL A_BLT<9> A_BLT_SEL A_PRE_N A_SEL_P<9> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV +XA_BLTMUX<8> A_BLC<8> A_BLC_SEL A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<8> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV +XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_SEL_P<7> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV +XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_SEL_P<6> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV +XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_SEL_P<5> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV +XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<4> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_SEL_P<3> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_SEL_P<2> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_SEL_P<1> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<0> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net24 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_DEC3INV<15> net23<0> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<1> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<2> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<3> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<4> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<5> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<6> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<7> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<8> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<9> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<10> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<11> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<12> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<13> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<14> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<15> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I70<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI73<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_DEC3<15> A_P0 A_ADDR_DEC<7> net23<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<14> A_P0 A_ADDR_DEC<6> net23<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<13> A_P0 A_ADDR_DEC<5> net23<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<12> A_P0 A_ADDR_DEC<4> net23<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<11> A_P0 A_ADDR_DEC<3> net23<4> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<10> A_P0 A_ADDR_DEC<2> net23<5> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<9> A_P0 A_ADDR_DEC<1> net23<6> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<8> A_P0 A_ADDR_DEC<0> net23<7> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<7> A_N0 A_ADDR_DEC<7> net23<8> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<6> A_N0 A_ADDR_DEC<6> net23<9> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<5> A_N0 A_ADDR_DEC<5> net23<10> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<4> A_N0 A_ADDR_DEC<4> net23<11> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<3> A_N0 A_ADDR_DEC<3> net23<12> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<2> A_N0 A_ADDR_DEC<2> net23<13> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<1> A_N0 A_ADDR_DEC<1> net23<14> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<0> A_N0 A_ADDR_DEC<0> net23<15> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS + + +.SUBCKT RM_IHPSG13_4096x8_c3_1P_COLDEC3 ACLK_N ADDR<2> ADDR<1> ADDR<0> ADDR_COL<1> ++ ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ++ ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> ++ BIST_EN_I VDD VSS +XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net6<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net6<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net6<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_1P_COLCTRL3 A_ADDR_DEC<7> A_ADDR_DEC<6> A_ADDR_DEC<5> ++ A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> A_ADDR_DEC<0> ++ A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> ++ A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> ++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R A_DCLK_L ++ A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R A_TIEH_O ++ A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_R A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_I70<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I70<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I44 A_BM_N A_WCLK_B_R A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_ADDR_DEC<7> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV +XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_ADDR_DEC<6> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV +XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_ADDR_DEC<5> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV +XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_ADDR_DEC<4> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_ADDR_DEC<2> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_ADDR_DEC<1> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<0> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I80 A_WCLK_B_R A_RCLK_B_R net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_4096x8_c3_2P_BITKIT_16x2_CORNER VDD_CORE VSS +XI16 VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x8_c3_1P_BITKIT_CORNER +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_2P_BITKIT_EDGE_LR A_WL B_WL NW PW VDD VSS +MN1 VSS A_WL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN0 VSS B_WL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_2P_BITKIT_16x2_EDGE_LR A_WL<15> A_WL<14> A_WL<13> A_WL<12> ++ A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> ++ A_WL<2> A_WL<1> A_WL<0> B_WL<15> B_WL<14> B_WL<13> B_WL<12> B_WL<11> ++ B_WL<10> B_WL<9> B_WL<8> B_WL<7> B_WL<6> B_WL<5> B_WL<4> B_WL<3> B_WL<2> ++ B_WL<1> B_WL<0> VDD_CORE VSS +XI0<15> A_WL<15> B_WL<15> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_4096x8_c3_2P_BITKIT_EDGE_LR +XI0<14> A_WL<14> B_WL<14> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_4096x8_c3_2P_BITKIT_EDGE_LR +XI0<13> A_WL<13> B_WL<13> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_4096x8_c3_2P_BITKIT_EDGE_LR +XI0<12> A_WL<12> B_WL<12> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_4096x8_c3_2P_BITKIT_EDGE_LR +XI0<11> A_WL<11> B_WL<11> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_4096x8_c3_2P_BITKIT_EDGE_LR +XI0<10> A_WL<10> B_WL<10> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_4096x8_c3_2P_BITKIT_EDGE_LR +XI0<9> A_WL<9> B_WL<9> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x8_c3_2P_BITKIT_EDGE_LR +XI0<8> A_WL<8> B_WL<8> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x8_c3_2P_BITKIT_EDGE_LR +XI0<7> A_WL<7> B_WL<7> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x8_c3_2P_BITKIT_EDGE_LR +XI0<6> A_WL<6> B_WL<6> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x8_c3_2P_BITKIT_EDGE_LR +XI0<5> A_WL<5> B_WL<5> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x8_c3_2P_BITKIT_EDGE_LR +XI0<4> A_WL<4> B_WL<4> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x8_c3_2P_BITKIT_EDGE_LR +XI0<3> A_WL<3> B_WL<3> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x8_c3_2P_BITKIT_EDGE_LR +XI0<2> A_WL<2> B_WL<2> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x8_c3_2P_BITKIT_EDGE_LR +XI0<1> A_WL<1> B_WL<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x8_c3_2P_BITKIT_EDGE_LR +XI0<0> A_WL<0> B_WL<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x8_c3_2P_BITKIT_EDGE_LR +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_2P_BITKIT_CELL A_BLC_BOT A_BLC_TOP A_BLT_BOT A_BLT_TOP ++ A_LWL A_RWL B_BLC_BOT B_BLC_TOP B_BLT_BOT B_BLT_TOP B_LWL B_RWL NW PW VDD VSS +MN5 NC B_RWL B_BLC_BOT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN4 B_BLT_BOT B_LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN0 NC NT VSS PW sg13_lv_nmos m=1 w=600.0n l=130.00n ng=2 nrd=0 nrs=0 +MN1 NT NC VSS PW sg13_lv_nmos m=1 w=600.0n l=130.00n ng=2 nrd=0 nrs=0 +MN3 NC A_RWL A_BLC_TOP PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MN2 A_BLT_TOP A_LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0 +MP1 NT NC VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +MP0 NC NT VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0 +R5 B_RWL B_LWL lvsres w=2.6e-07 l=6e-07 +R4 B_BLC_BOT B_BLC_TOP lvsres w=2.6e-07 l=6e-07 +R3 B_BLT_BOT B_BLT_TOP lvsres w=2.6e-07 l=6e-07 +R1 A_BLC_BOT A_BLC_TOP lvsres w=2.6e-07 l=6e-07 +R0 A_BLT_BOT A_BLT_TOP lvsres w=2.6e-07 l=6e-07 +R2 A_RWL A_LWL lvsres w=2.6e-07 l=6e-07 +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_2P_BITKIT_16x2_SRAM A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> ++ A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<15> ++ A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> ++ A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> ++ A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> ++ A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> B_BLC_BOT<1> ++ B_BLC_BOT<0> B_BLC_TOP<1> B_BLC_TOP<0> B_BLT_BOT<1> B_BLT_BOT<0> ++ B_BLT_TOP<1> B_BLT_TOP<0> B_LWL<15> B_LWL<14> B_LWL<13> B_LWL<12> B_LWL<11> ++ B_LWL<10> B_LWL<9> B_LWL<8> B_LWL<7> B_LWL<6> B_LWL<5> B_LWL<4> B_LWL<3> ++ B_LWL<2> B_LWL<1> B_LWL<0> B_RWL<15> B_RWL<14> B_RWL<13> B_RWL<12> B_RWL<11> ++ B_RWL<10> B_RWL<9> B_RWL<8> B_RWL<7> B_RWL<6> B_RWL<5> B_RWL<4> B_RWL<3> ++ B_RWL<2> B_RWL<1> B_RWL<0> VDD_CORE VSS +XCELL<31> A_BLC_TOP<1> A_RBLC<15> A_BLT_TOP<1> A_RBLT<15> A_XWL<15> A_RWL<15> ++ B_BLC_TOP<1> B_RBLC<15> B_BLT_TOP<1> B_RBLT<15> B_XWL<15> B_RWL<15> ++ VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x8_c3_2P_BITKIT_CELL +XCELL<30> A_RBLC<14> A_RBLC<15> A_RBLT<14> A_RBLT<15> A_XWL<14> A_RWL<14> ++ B_RBLC<14> B_RBLC<15> B_RBLT<14> B_RBLT<15> B_XWL<14> B_RWL<14> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_CELL +XCELL<29> A_RBLC<14> A_RBLC<13> A_RBLT<14> A_RBLT<13> A_XWL<13> A_RWL<13> ++ B_RBLC<14> B_RBLC<13> B_RBLT<14> B_RBLT<13> B_XWL<13> B_RWL<13> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_CELL +XCELL<28> A_RBLC<12> A_RBLC<13> A_RBLT<12> A_RBLT<13> A_XWL<12> A_RWL<12> ++ B_RBLC<12> B_RBLC<13> B_RBLT<12> B_RBLT<13> B_XWL<12> B_RWL<12> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_CELL +XCELL<27> A_RBLC<12> A_RBLC<11> A_RBLT<12> A_RBLT<11> A_XWL<11> A_RWL<11> ++ B_RBLC<12> B_RBLC<11> B_RBLT<12> B_RBLT<11> B_XWL<11> B_RWL<11> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_CELL +XCELL<26> A_RBLC<10> A_RBLC<11> A_RBLT<10> A_RBLT<11> A_XWL<10> A_RWL<10> ++ B_RBLC<10> B_RBLC<11> B_RBLT<10> B_RBLT<11> B_XWL<10> B_RWL<10> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_CELL +XCELL<25> A_RBLC<10> A_RBLC<9> A_RBLT<10> A_RBLT<9> A_XWL<9> A_RWL<9> ++ B_RBLC<10> B_RBLC<9> B_RBLT<10> B_RBLT<9> B_XWL<9> B_RWL<9> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_CELL +XCELL<24> A_RBLC<8> A_RBLC<9> A_RBLT<8> A_RBLT<9> A_XWL<8> A_RWL<8> B_RBLC<8> ++ B_RBLC<9> B_RBLT<8> B_RBLT<9> B_XWL<8> B_RWL<8> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_CELL +XCELL<23> A_RBLC<8> A_RBLC<7> A_RBLT<8> A_RBLT<7> A_XWL<7> A_RWL<7> B_RBLC<8> ++ B_RBLC<7> B_RBLT<8> B_RBLT<7> B_XWL<7> B_RWL<7> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_CELL +XCELL<22> A_RBLC<6> A_RBLC<7> A_RBLT<6> A_RBLT<7> A_XWL<6> A_RWL<6> B_RBLC<6> ++ B_RBLC<7> B_RBLT<6> B_RBLT<7> B_XWL<6> B_RWL<6> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_CELL +XCELL<21> A_RBLC<6> A_RBLC<5> A_RBLT<6> A_RBLT<5> A_XWL<5> A_RWL<5> B_RBLC<6> ++ B_RBLC<5> B_RBLT<6> B_RBLT<5> B_XWL<5> B_RWL<5> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_CELL +XCELL<20> A_RBLC<4> A_RBLC<5> A_RBLT<4> A_RBLT<5> A_XWL<4> A_RWL<4> B_RBLC<4> ++ B_RBLC<5> B_RBLT<4> B_RBLT<5> B_XWL<4> B_RWL<4> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_CELL +XCELL<19> A_RBLC<4> A_RBLC<3> A_RBLT<4> A_RBLT<3> A_XWL<3> A_RWL<3> B_RBLC<4> ++ B_RBLC<3> B_RBLT<4> B_RBLT<3> B_XWL<3> B_RWL<3> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_CELL +XCELL<18> A_RBLC<2> A_RBLC<3> A_RBLT<2> A_RBLT<3> A_XWL<2> A_RWL<2> B_RBLC<2> ++ B_RBLC<3> B_RBLT<2> B_RBLT<3> B_XWL<2> B_RWL<2> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_CELL +XCELL<17> A_RBLC<2> A_RBLC<1> A_RBLT<2> A_RBLT<1> A_XWL<1> A_RWL<1> B_RBLC<2> ++ B_RBLC<1> B_RBLT<2> B_RBLT<1> B_XWL<1> B_RWL<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_CELL +XCELL<16> A_BLC_BOT<1> A_RBLC<1> A_BLT_BOT<1> A_RBLT<1> A_XWL<0> A_RWL<0> ++ B_BLC_BOT<1> B_RBLC<1> B_BLT_BOT<1> B_RBLT<1> B_XWL<0> B_RWL<0> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_CELL +XCELL<15> A_BLC_TOP<0> A_LBLC<15> A_BLT_TOP<0> A_LBLT<15> A_LWL<15> A_XWL<15> ++ B_BLC_TOP<0> B_LBLC<15> B_BLT_TOP<0> B_LBLT<15> B_LWL<15> B_XWL<15> ++ VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x8_c3_2P_BITKIT_CELL +XCELL<14> A_LBLC<14> A_LBLC<15> A_LBLT<14> A_LBLT<15> A_LWL<14> A_XWL<14> ++ B_LBLC<14> B_LBLC<15> B_LBLT<14> B_LBLT<15> B_LWL<14> B_XWL<14> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_CELL +XCELL<13> A_LBLC<14> A_LBLC<13> A_LBLT<14> A_LBLT<13> A_LWL<13> A_XWL<13> ++ B_LBLC<14> B_LBLC<13> B_LBLT<14> B_LBLT<13> B_LWL<13> B_XWL<13> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_CELL +XCELL<12> A_LBLC<12> A_LBLC<13> A_LBLT<12> A_LBLT<13> A_LWL<12> A_XWL<12> ++ B_LBLC<12> B_LBLC<13> B_LBLT<12> B_LBLT<13> B_LWL<12> B_XWL<12> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_CELL +XCELL<11> A_LBLC<12> A_LBLC<11> A_LBLT<12> A_LBLT<11> A_LWL<11> A_XWL<11> ++ B_LBLC<12> B_LBLC<11> B_LBLT<12> B_LBLT<11> B_LWL<11> B_XWL<11> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_CELL +XCELL<10> A_LBLC<10> A_LBLC<11> A_LBLT<10> A_LBLT<11> A_LWL<10> A_XWL<10> ++ B_LBLC<10> B_LBLC<11> B_LBLT<10> B_LBLT<11> B_LWL<10> B_XWL<10> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_CELL +XCELL<9> A_LBLC<10> A_LBLC<9> A_LBLT<10> A_LBLT<9> A_LWL<9> A_XWL<9> ++ B_LBLC<10> B_LBLC<9> B_LBLT<10> B_LBLT<9> B_LWL<9> B_XWL<9> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_CELL +XCELL<8> A_LBLC<8> A_LBLC<9> A_LBLT<8> A_LBLT<9> A_LWL<8> A_XWL<8> B_LBLC<8> ++ B_LBLC<9> B_LBLT<8> B_LBLT<9> B_LWL<8> B_XWL<8> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_CELL +XCELL<7> A_LBLC<8> A_LBLC<7> A_LBLT<8> A_LBLT<7> A_LWL<7> A_XWL<7> B_LBLC<8> ++ B_LBLC<7> B_LBLT<8> B_LBLT<7> B_LWL<7> B_XWL<7> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_CELL +XCELL<6> A_LBLC<6> A_LBLC<7> A_LBLT<6> A_LBLT<7> A_LWL<6> A_XWL<6> B_LBLC<6> ++ B_LBLC<7> B_LBLT<6> B_LBLT<7> B_LWL<6> B_XWL<6> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_CELL +XCELL<5> A_LBLC<6> A_LBLC<5> A_LBLT<6> A_LBLT<5> A_LWL<5> A_XWL<5> B_LBLC<6> ++ B_LBLC<5> B_LBLT<6> B_LBLT<5> B_LWL<5> B_XWL<5> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_CELL +XCELL<4> A_LBLC<4> A_LBLC<5> A_LBLT<4> A_LBLT<5> A_LWL<4> A_XWL<4> B_LBLC<4> ++ B_LBLC<5> B_LBLT<4> B_LBLT<5> B_LWL<4> B_XWL<4> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_CELL +XCELL<3> A_LBLC<4> A_LBLC<3> A_LBLT<4> A_LBLT<3> A_LWL<3> A_XWL<3> B_LBLC<4> ++ B_LBLC<3> B_LBLT<4> B_LBLT<3> B_LWL<3> B_XWL<3> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_CELL +XCELL<2> A_LBLC<2> A_LBLC<3> A_LBLT<2> A_LBLT<3> A_LWL<2> A_XWL<2> B_LBLC<2> ++ B_LBLC<3> B_LBLT<2> B_LBLT<3> B_LWL<2> B_XWL<2> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_CELL +XCELL<1> A_LBLC<2> A_LBLC<1> A_LBLT<2> A_LBLT<1> A_LWL<1> A_XWL<1> B_LBLC<2> ++ B_LBLC<1> B_LBLT<2> B_LBLT<1> B_LWL<1> B_XWL<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_CELL +XCELL<0> A_BLC_BOT<0> A_LBLC<1> A_BLT_BOT<0> A_LBLT<1> A_LWL<0> A_XWL<0> ++ B_BLC_BOT<0> B_LBLC<1> B_BLT_BOT<0> B_LBLT<1> B_LWL<0> B_XWL<0> VDD_CORE ++ VSS VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_CELL +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_2P_BITKIT_EDGE_TB A_BLC A_BLT B_BLC B_BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_2P_BITKIT_16x2_EDGE_TB A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ B_BLC<1> B_BLC<0> B_BLT<1> B_BLT<0> VDD_CORE VSS +XEDGE<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_EDGE_TB +XEDGE<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_EDGE_TB +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_2P_BITKIT_TAP A_BLC A_BLT B_BLC B_BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_2P_BITKIT_16x2_TAP A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ B_BLC<1> B_BLC<0> B_BLT<1> B_BLT<0> VDD_CORE VSS +XIEDGEBP_COL1<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_EDGE_TB +XIEDGEBP_COL1<0> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_EDGE_TB +XIEDGEBP_COL2<1> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_EDGE_TB +XIEDGEBP_COL2<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_EDGE_TB +XITAP<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_TAP +XITAP<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS ++ VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_TAP +.ENDS + + +.SUBCKT RM_IHPSG13_4096x8_c3_1P_BITKIT_TAP_LR NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_2P_BITKIT_16x2_TAP_LR VDD_CORE VSS +XCORNER<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x8_c3_1P_BITKIT_CORNER +XCORNER<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x8_c3_1P_BITKIT_CORNER +XTAP_BORDER VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x8_c3_1P_BITKIT_TAP_LR +.ENDS + +.SUBCKT RSC_IHPSG13_CBUFX12 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=4.23u l=130.00n ng=6 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=9.72u l=130.00n ng=6 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_2P_COLDRV13X12 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX12 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=9.72u l=130.00n ng=6 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_2P_WLDRV16X12 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX12 +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_2P_DEC04 ADDR<3> ADDR<2> ADDR<1> ADDR<0> CS ECLK_H_BOT ++ ECLK_H_TOP ECLK_L_BOT ECLK_L_TOP WL<15> WL<14> WL<13> WL<12> WL<11> WL<10> ++ WL<9> WL<8> WL<7> WL<6> WL<5> WL<4> WL<3> WL<2> WL<1> WL<0> VDD VSS +XI0<3> PADR<1> PADR<0> sel01<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<2> PADR<1> NADR<0> sel01<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<1> NADR<1> PADR<0> sel01<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI0<0> NADR<1> NADR<0> sel01<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI4 ECLK_L_BOT EN VDD VSS / RSC_IHPSG13_CINVX4 +XI5 ECLK_H_BOT ECLK_L_BOT VDD VSS / RSC_IHPSG13_CINVX2 +XI3<3> PADR<3> NADR<3> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> PADR<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> PADR<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> PADR<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XR0 ECLK_H_BOT ECLK_H_TOP / RSC_IHPSG13_MET2RES +XI11 ECLK_L_BOT ECLK_L_TOP / RSC_IHPSG13_MET2RES +XI1<3> PADR<2> PADR<3> CS sel23<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<2> PADR<3> CS sel23<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<2> NADR<3> CS sel23<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<2> NADR<3> CS sel23<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI2<15> sel23<3> sel01<3> EN WL<15> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<14> sel23<3> sel01<2> EN WL<14> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<13> sel23<3> sel01<1> EN WL<13> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<12> sel23<3> sel01<0> EN WL<12> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<11> sel23<2> sel01<3> EN WL<11> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<10> sel23<2> sel01<2> EN WL<10> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<9> sel23<2> sel01<1> EN WL<9> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<8> sel23<2> sel01<0> EN WL<8> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<7> sel23<1> sel01<3> EN WL<7> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<6> sel23<1> sel01<2> EN WL<6> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<5> sel23<1> sel01<1> EN WL<5> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<4> sel23<1> sel01<0> EN WL<4> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<3> sel23<0> sel01<3> EN WL<3> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<2> sel23<0> sel01<2> EN WL<2> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<1> sel23<0> sel01<1> EN WL<1> VDD VSS / RSC_IHPSG13_NOR3X2 +XI2<0> sel23<0> sel01<0> EN WL<0> VDD VSS / RSC_IHPSG13_NOR3X2 +XCAPS4 VDD VSS / RSC_IHPSG13_FILLCAP4 +XLATCH<3> CS ADDR<3> PADR<3> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<2> CS ADDR<2> PADR<2> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<1> CS ADDR<1> PADR<1> VDD VSS / RSC_IHPSG13_LHPQX2 +XLATCH<0> CS ADDR<0> PADR<0> VDD VSS / RSC_IHPSG13_LHPQX2 +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_2P_DEC02 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC ADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI2<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI2<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_2P_DEC01 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC NADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI2<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI2<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_2P_DEC00 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC NADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV<1> ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +XADDRINV<0> ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_2P_DEC03 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDEC ADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_2P_ROWDEC9 ADDR_N_I<8> ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ++ ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ++ WL_O<511> WL_O<510> WL_O<509> WL_O<508> WL_O<507> WL_O<506> WL_O<505> ++ WL_O<504> WL_O<503> WL_O<502> WL_O<501> WL_O<500> WL_O<499> WL_O<498> ++ WL_O<497> WL_O<496> WL_O<495> WL_O<494> WL_O<493> WL_O<492> WL_O<491> ++ WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> WL_O<484> ++ WL_O<483> WL_O<482> WL_O<481> WL_O<480> WL_O<479> WL_O<478> WL_O<477> ++ WL_O<476> WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> ++ WL_O<469> WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> WL_O<463> ++ WL_O<462> WL_O<461> WL_O<460> WL_O<459> WL_O<458> WL_O<457> WL_O<456> ++ WL_O<455> WL_O<454> WL_O<453> WL_O<452> WL_O<451> WL_O<450> WL_O<449> ++ WL_O<448> WL_O<447> WL_O<446> WL_O<445> WL_O<444> WL_O<443> WL_O<442> ++ WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> WL_O<436> WL_O<435> ++ WL_O<434> WL_O<433> WL_O<432> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> WL_O<415> WL_O<414> ++ WL_O<413> WL_O<412> WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> ++ WL_O<406> WL_O<405> WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> ++ WL_O<399> WL_O<398> WL_O<397> WL_O<396> WL_O<395> WL_O<394> WL_O<393> ++ WL_O<392> WL_O<391> WL_O<390> WL_O<389> WL_O<388> WL_O<387> WL_O<386> ++ WL_O<385> WL_O<384> WL_O<383> WL_O<382> WL_O<381> WL_O<380> WL_O<379> ++ WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> WL_O<372> ++ WL_O<371> WL_O<370> WL_O<369> WL_O<368> WL_O<367> WL_O<366> WL_O<365> ++ WL_O<364> WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> ++ WL_O<357> WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> WL_O<351> ++ WL_O<350> WL_O<349> WL_O<348> WL_O<347> WL_O<346> WL_O<345> WL_O<344> ++ WL_O<343> WL_O<342> WL_O<341> WL_O<340> WL_O<339> WL_O<338> WL_O<337> ++ WL_O<336> WL_O<335> WL_O<334> WL_O<333> WL_O<332> WL_O<331> WL_O<330> ++ WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> WL_O<324> WL_O<323> ++ WL_O<322> WL_O<321> WL_O<320> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> WL_O<303> WL_O<302> ++ WL_O<301> WL_O<300> WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> ++ WL_O<294> WL_O<293> WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> ++ WL_O<287> WL_O<286> WL_O<285> WL_O<284> WL_O<283> WL_O<282> WL_O<281> ++ WL_O<280> WL_O<279> WL_O<278> WL_O<277> WL_O<276> WL_O<275> WL_O<274> ++ WL_O<273> WL_O<272> WL_O<271> WL_O<270> WL_O<269> WL_O<268> WL_O<267> ++ WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> WL_O<260> ++ WL_O<259> WL_O<258> WL_O<257> WL_O<256> WL_O<255> WL_O<254> WL_O<253> ++ WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> ++ WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> WL_O<239> ++ WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> WL_O<233> WL_O<232> ++ WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> WL_O<226> WL_O<225> ++ WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> WL_O<219> WL_O<218> ++ WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> WL_O<212> WL_O<211> ++ WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> WL_O<191> WL_O<190> ++ WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> ++ WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> ++ WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> WL_O<170> WL_O<169> ++ WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> WL_O<163> WL_O<162> ++ WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> WL_O<156> WL_O<155> ++ WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> WL_O<148> ++ WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> WL_O<142> WL_O<141> ++ WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> ++ WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> WL_O<127> ++ WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> ++ WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> ++ WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> ++ WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> ++ WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XSEL<31> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<31> ECLK_H<31> ++ ECLK_H<32> ECLK_B<31> ECLK_B<32> WL_O<511> WL_O<510> WL_O<509> WL_O<508> ++ WL_O<507> WL_O<506> WL_O<505> WL_O<504> WL_O<503> WL_O<502> WL_O<501> ++ WL_O<500> WL_O<499> WL_O<498> WL_O<497> WL_O<496> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC04 +XSEL<30> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<30> ECLK_H<30> ++ ECLK_H<31> ECLK_B<30> ECLK_B<31> WL_O<495> WL_O<494> WL_O<493> WL_O<492> ++ WL_O<491> WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> ++ WL_O<484> WL_O<483> WL_O<482> WL_O<481> WL_O<480> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC04 +XSEL<29> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<29> ECLK_H<29> ++ ECLK_H<30> ECLK_B<29> ECLK_B<30> WL_O<479> WL_O<478> WL_O<477> WL_O<476> ++ WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> WL_O<469> ++ WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC04 +XSEL<28> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<28> ECLK_H<28> ++ ECLK_H<29> ECLK_B<28> ECLK_B<29> WL_O<463> WL_O<462> WL_O<461> WL_O<460> ++ WL_O<459> WL_O<458> WL_O<457> WL_O<456> WL_O<455> WL_O<454> WL_O<453> ++ WL_O<452> WL_O<451> WL_O<450> WL_O<449> WL_O<448> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC04 +XSEL<27> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<27> ECLK_H<27> ++ ECLK_H<28> ECLK_B<27> ECLK_B<28> WL_O<447> WL_O<446> WL_O<445> WL_O<444> ++ WL_O<443> WL_O<442> WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> ++ WL_O<436> WL_O<435> WL_O<434> WL_O<433> WL_O<432> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC04 +XSEL<26> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<26> ECLK_H<26> ++ ECLK_H<27> ECLK_B<26> ECLK_B<27> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC04 +XSEL<25> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<25> ECLK_H<25> ++ ECLK_H<26> ECLK_B<25> ECLK_B<26> WL_O<415> WL_O<414> WL_O<413> WL_O<412> ++ WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> WL_O<406> WL_O<405> ++ WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC04 +XSEL<24> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<24> ECLK_H<24> ++ ECLK_H<25> ECLK_B<24> ECLK_B<25> WL_O<399> WL_O<398> WL_O<397> WL_O<396> ++ WL_O<395> WL_O<394> WL_O<393> WL_O<392> WL_O<391> WL_O<390> WL_O<389> ++ WL_O<388> WL_O<387> WL_O<386> WL_O<385> WL_O<384> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC04 +XSEL<23> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<23> ECLK_H<23> ++ ECLK_H<24> ECLK_B<23> ECLK_B<24> WL_O<383> WL_O<382> WL_O<381> WL_O<380> ++ WL_O<379> WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> ++ WL_O<372> WL_O<371> WL_O<370> WL_O<369> WL_O<368> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC04 +XSEL<22> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<22> ECLK_H<22> ++ ECLK_H<23> ECLK_B<22> ECLK_B<23> WL_O<367> WL_O<366> WL_O<365> WL_O<364> ++ WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> WL_O<357> ++ WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC04 +XSEL<21> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<21> ECLK_H<21> ++ ECLK_H<22> ECLK_B<21> ECLK_B<22> WL_O<351> WL_O<350> WL_O<349> WL_O<348> ++ WL_O<347> WL_O<346> WL_O<345> WL_O<344> WL_O<343> WL_O<342> WL_O<341> ++ WL_O<340> WL_O<339> WL_O<338> WL_O<337> WL_O<336> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC04 +XSEL<20> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<20> ECLK_H<20> ++ ECLK_H<21> ECLK_B<20> ECLK_B<21> WL_O<335> WL_O<334> WL_O<333> WL_O<332> ++ WL_O<331> WL_O<330> WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> ++ WL_O<324> WL_O<323> WL_O<322> WL_O<321> WL_O<320> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC04 +XSEL<19> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<19> ECLK_H<19> ++ ECLK_H<20> ECLK_B<19> ECLK_B<20> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC04 +XSEL<18> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<18> ECLK_H<18> ++ ECLK_H<19> ECLK_B<18> ECLK_B<19> WL_O<303> WL_O<302> WL_O<301> WL_O<300> ++ WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> WL_O<294> WL_O<293> ++ WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC04 +XSEL<17> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<17> ECLK_H<17> ++ ECLK_H<18> ECLK_B<17> ECLK_B<18> WL_O<287> WL_O<286> WL_O<285> WL_O<284> ++ WL_O<283> WL_O<282> WL_O<281> WL_O<280> WL_O<279> WL_O<278> WL_O<277> ++ WL_O<276> WL_O<275> WL_O<274> WL_O<273> WL_O<272> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC04 +XSEL<16> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<16> ECLK_H<16> ++ ECLK_H<17> ECLK_B<16> ECLK_B<17> WL_O<271> WL_O<270> WL_O<269> WL_O<268> ++ WL_O<267> WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> ++ WL_O<260> WL_O<259> WL_O<258> WL_O<257> WL_O<256> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC04 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_4096x8_c3_2P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_4096x8_c3_2P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_4096x8_c3_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_4096x8_c3_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_4096x8_c3_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_4096x8_c3_2P_DEC04 +XDEC10<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<6> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC02 +XDEC10<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<2> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC02 +XDEC10<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<30> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC02 +XDEC10<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<26> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC02 +XDEC10<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<22> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC02 +XDEC10<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<18> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<14> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<10> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<6> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<2> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC02 +XDEC01<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC01 +XDEC01<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<5> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC01 +XDEC01<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<1> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC01 +XDEC01<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<29> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC01 +XDEC01<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<25> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC01 +XDEC01<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<21> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC01 +XDEC01<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<17> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<13> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<9> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<5> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<1> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC01 +XL2<258> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<257> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<256> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<255> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<254> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<253> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<252> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<251> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<250> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<249> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<248> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<247> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<246> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<245> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<244> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<243> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<242> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<241> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<240> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<239> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<238> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<237> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<236> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<235> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<234> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<233> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<232> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<231> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<230> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<229> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<228> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<227> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<226> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<225> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<224> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<223> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<222> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<221> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<220> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<219> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<218> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<217> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<216> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<215> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<214> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<213> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<212> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<211> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<210> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<209> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<208> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<207> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<206> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<205> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<204> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<203> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<202> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<201> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<200> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<199> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<198> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<197> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<196> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<195> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<194> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<193> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<192> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<191> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<190> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<189> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<188> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<187> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<186> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<185> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<184> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<183> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<182> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<181> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<180> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<179> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<178> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<177> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<176> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<175> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<174> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<173> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<172> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<171> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<170> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<169> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<168> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<167> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<166> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<165> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<164> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<163> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<162> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<161> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<160> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<159> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<158> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<157> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<156> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<155> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<154> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<153> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<152> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<151> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<150> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<149> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<148> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<147> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<146> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<145> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<144> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<143> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<142> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<141> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<140> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<139> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<138> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<137> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<136> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<135> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<134> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<133> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC00<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC00 +XDEC00<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<4> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC00 +XDEC00<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<0> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC00 +XDEC00<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<28> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC00 +XDEC00<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<24> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC00 +XDEC00<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<20> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC00 +XDEC00<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<16> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<12> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<8> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<4> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<0> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC00 +XDEC11<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<7> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC03 +XDEC11<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<3> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC03 +XDEC11<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<31> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC03 +XDEC11<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<27> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC03 +XDEC11<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<23> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC03 +XDEC11<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<19> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<15> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<11> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<7> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<3> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC03 +XI0 ADDR_N_I<9> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_2P_ROWREG9 ACLK_N_I ADDR_I<8> ADDR_I<7> ADDR_I<6> ADDR_I<5> ++ ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<8> ADDR_N_O<7> ++ ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ++ ADDR_N_O<0> BIST_ADDR_I<8> BIST_ADDR_I<7> BIST_ADDR_I<6> BIST_ADDR_I<5> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XDFF<8> BIST_EN_I BIST_ADDR_I<8> ACLK_N_I ADDR_I<8> q_int<8> net04<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net04<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net04<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net04<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net04<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net04<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net04<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net04<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net04<8> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDRV<8> qn_int<8> ADDR_N_O<8> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XINV<8> q_int<8> qn_int<8> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +.ENDS + +.SUBCKT RM_IHPSG13_4096x8_c3_2P_DLY_MUX A SEL Z VDD VSS +XI11 net4 Z VDD VSS / RSC_IHPSG13_CINVX2 +XI8 A D<3> SEL net4 VDD VSS / RSC_IHPSG13_MX2IX1 +XI20<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1 +XI20<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1 +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_2P_CTRL ACLK_N BIST_CK_I BIST_CS_I BIST_EN BIST_RE_I ++ BIST_WE_I B_TIEL_O CK_I CS_I DCLK ECLK PULSE_H PULSE_L PULSE_O RCLK RE_I ++ ROW_CS WCLK WE_I VDD VSS +XI17 ck_regs we col_we VDD VSS / RSC_IHPSG13_DFNQX2 +XI16 ck_regs re col_re VDD VSS / RSC_IHPSG13_DFNQX2 +XI18 ck_regs cs net7 VDD VSS / RSC_IHPSG13_DFNQX2 +XI71 ACLK_N net012 PULSE_O VDD VSS / RSC_IHPSG13_DFNQX2 +XI77 col_we net017 net016 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI76 col_re net017 net018 VDD VSS / RSC_IHPSG13_CNAND2X2 +XI15 ck_dly WEorREandCS aclk VDD VSS / RSC_IHPSG13_CGATEPX4 +XI14 ck WEandCS DCLK VDD VSS / RSC_IHPSG13_CGATEPX4 +XI60 net7 ROW_CS VDD VSS / RSC_IHPSG13_CBUFX8 +XI73 PULSE_O net012 VDD VSS / RSC_IHPSG13_CINVX2 +XI8 net017 net8 VDD VSS / RSC_IHPSG13_CINVX2 +XCAPS4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XCAPS4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XBM_TIEL B_TIEL_O VDD VSS / RSC_IHPSG13_TIEL +XI64 ck ck_dly VDD VSS / RSC_IHPSG13_CDLYX2 +XI86 CS_I BIST_CS_I BIST_EN cs VDD VSS / RSC_IHPSG13_MX2X2 +XI87 CK_I BIST_CK_I BIST_EN ck VDD VSS / RSC_IHPSG13_MX2X2 +XI85 WE_I BIST_WE_I BIST_EN we VDD VSS / RSC_IHPSG13_MX2X2 +XI84 RE_I BIST_RE_I BIST_EN re VDD VSS / RSC_IHPSG13_MX2X2 +XI48 ck_dly ck_regs VDD VSS / RSC_IHPSG13_CINVX4 +XI81 net016 WCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI80 net018 RCLK VDD VSS / RSC_IHPSG13_CINVX4 +XI78 net8 net020 VDD VSS / RSC_IHPSG13_CINVX4 +XCAPS8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XCAPS8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI6 PULSE_L PULSE_H net017 VDD VSS / RSC_IHPSG13_XOR2X2 +XI22 we cs WEandCS VDD VSS / RSC_IHPSG13_AND2X2 +XI79 net020 ECLK VDD VSS / RSC_IHPSG13_CINVX8 +XI63 aclk ACLK_N VDD VSS / RSC_IHPSG13_CINVX8 +XI21 re we cs WEorREandCS VDD VSS / RSC_IHPSG13_OA12X1 +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_2P_COLDEC5 ACLK_N ADDR<4> ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<4> BIST_ADDR<3> ++ BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<4> BIST_EN_I BIST_ADDR<4> ACLK_N ADDR<4> addr_int<1> net13<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int<0> net13<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net13<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net13<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net13<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI15<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI15<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI15<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> addr_int<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_CBUFX2 +XI13<0> addr_int<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XI14<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI14<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_2P_BLDRV A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL ++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> ++ A_SEL_P<1> A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> ++ B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> ++ B_SEL_P<2> B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS +MA_CWN<3> A_BLC<3> A_BLC_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CWN<2> A_BLC<2> A_BLC_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CWN<1> A_BLC<1> A_BLC_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CWN<0> A_BLC<0> A_BLC_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<3> A_BLT<3> A_BLT_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<2> A_BLT<2> A_BLT_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<1> A_BLT<1> A_BLT_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_TWN<0> A_BLT<0> A_BLT_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<3> B_BLT<3> B_BLT_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<2> B_BLT<2> B_BLT_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<1> B_BLT<1> B_BLT_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_TWN<0> B_BLT<0> B_BLT_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<3> B_BLC<3> B_BLC_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<2> B_BLC<2> B_BLC_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<1> B_BLC<1> B_BLC_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MB_CWN<0> B_BLC<0> B_BLC_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 ++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0 +MA_CPR<3> A_BLC<3> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_CPR<2> A_BLC<2> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_CPR<1> A_BLC<1> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_CPR<0> A_BLC<0> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TWP<3> A_BLT<3> A_BLT_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TWP<2> A_BLT<2> A_BLT_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TWP<1> A_BLT<1> A_BLT_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TWP<0> A_BLT<0> A_BLT_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<3> A_BLC<3> A_BLC_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<2> A_BLC<2> A_BLC_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<1> A_BLC<1> A_BLC_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CWP<0> A_BLC<0> A_BLC_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TPR<3> A_BLT<3> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TPR<2> A_BLT<2> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TPR<1> A_BLT<1> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TPR<0> A_BLT<0> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MA_TSP<3> A_BLT_SEL A_SEL_N<3> A_BLT<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TSP<2> A_BLT_SEL A_SEL_N<2> A_BLT<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TSP<1> A_BLT_SEL A_SEL_N<1> A_BLT<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_TSP<0> A_BLT_SEL A_SEL_N<0> A_BLT<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<3> A_BLC_SEL A_SEL_N<3> A_BLC<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<2> A_BLC_SEL A_SEL_N<2> A_BLC<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<1> A_BLC_SEL A_SEL_N<1> A_BLC<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MA_CSP<0> A_BLC_SEL A_SEL_N<0> A_BLC<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<3> B_BLC<3> B_BLC_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<2> B_BLC<2> B_BLC_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<1> B_BLC<1> B_BLC_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CWP<0> B_BLC<0> B_BLC_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<3> B_BLT<3> B_BLT_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<2> B_BLT<2> B_BLT_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<1> B_BLT<1> B_BLT_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TWP<0> B_BLT<0> B_BLT_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<3> B_BLT_SEL B_SEL_N<3> B_BLT<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<2> B_BLT_SEL B_SEL_N<2> B_BLT<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<1> B_BLT_SEL B_SEL_N<1> B_BLT<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TSP<0> B_BLT_SEL B_SEL_N<0> B_BLT<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_TPR<3> B_BLT<3> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_TPR<2> B_BLT<2> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_TPR<1> B_BLT<1> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_TPR<0> B_BLT<0> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CSP<3> B_BLC_SEL B_SEL_N<3> B_BLC<3> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CSP<2> B_BLC_SEL B_SEL_N<2> B_BLC<2> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CSP<1> B_BLC_SEL B_SEL_N<1> B_BLC<1> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CSP<0> B_BLC_SEL B_SEL_N<0> B_BLC<0> VDD sg13_lv_pmos m=1 w=1.5u ++ l=130.00n ng=1 nrd=0 nrs=0 +MB_CPR<3> B_BLC<3> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CPR<2> B_BLC<2> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CPR<1> B_BLC<1> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +MB_CPR<0> B_BLC<0> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ++ ng=2 nrd=0 nrs=0 +XA_SEL<3> A_SEL_P<3> A_SEL_N<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_SEL<2> A_SEL_P<2> A_SEL_N<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_SEL<1> A_SEL_P<1> A_SEL_N<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_SEL<0> A_SEL_P<0> A_SEL_N<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_CINV<3> A_BLT_PMOS_DRIVE<3> A_BLC_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_CINV<2> A_BLT_PMOS_DRIVE<2> A_BLC_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_CINV<1> A_BLT_PMOS_DRIVE<1> A_BLC_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_CINV<0> A_BLT_PMOS_DRIVE<0> A_BLC_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<3> A_BLC_PMOS_DRIVE<3> A_BLT_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<2> A_BLC_PMOS_DRIVE<2> A_BLT_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<1> A_BLC_PMOS_DRIVE<1> A_BLT_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TINV<0> A_BLC_PMOS_DRIVE<0> A_BLT_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_SEL<3> B_SEL_P<3> B_SEL_N<3> VDD VSS / RSC_IHPSG13_INVX2 +XB_SEL<2> B_SEL_P<2> B_SEL_N<2> VDD VSS / RSC_IHPSG13_INVX2 +XB_SEL<1> B_SEL_P<1> B_SEL_N<1> VDD VSS / RSC_IHPSG13_INVX2 +XB_SEL<0> B_SEL_P<0> B_SEL_N<0> VDD VSS / RSC_IHPSG13_INVX2 +XB_TINV<3> B_BLC_PMOS_DRIVE<3> B_BLT_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_TINV<2> B_BLC_PMOS_DRIVE<2> B_BLT_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_TINV<1> B_BLC_PMOS_DRIVE<1> B_BLT_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_TINV<0> B_BLC_PMOS_DRIVE<0> B_BLT_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<3> B_BLT_PMOS_DRIVE<3> B_BLC_NMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<2> B_BLT_PMOS_DRIVE<2> B_BLC_NMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<1> B_BLT_PMOS_DRIVE<1> B_BLC_NMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_INVX2 +XB_CINV<0> B_BLT_PMOS_DRIVE<0> B_BLC_NMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_INVX2 +XA_TDEC<3> A_SEL_P<3> A_WR_ONE A_BLT_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_TDEC<2> A_SEL_P<2> A_WR_ONE A_BLT_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_TDEC<1> A_SEL_P<1> A_WR_ONE A_BLT_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_TDEC<0> A_SEL_P<0> A_WR_ONE A_BLT_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<3> A_SEL_P<3> A_WR_ZERO A_BLC_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<2> A_SEL_P<2> A_WR_ZERO A_BLC_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<1> A_SEL_P<1> A_WR_ZERO A_BLC_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XA_CDEC<0> A_SEL_P<0> A_WR_ZERO A_BLC_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<3> B_SEL_P<3> B_WR_ZERO B_BLC_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<2> B_SEL_P<2> B_WR_ZERO B_BLC_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<1> B_SEL_P<1> B_WR_ZERO B_BLC_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_CDEC<0> B_SEL_P<0> B_WR_ZERO B_BLC_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<3> B_SEL_P<3> B_WR_ONE B_BLT_PMOS_DRIVE<3> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<2> B_SEL_P<2> B_WR_ONE B_BLT_PMOS_DRIVE<2> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<1> B_SEL_P<1> B_WR_ONE B_BLT_PMOS_DRIVE<1> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +XB_TDEC<0> B_SEL_P<0> B_WR_ONE B_BLT_PMOS_DRIVE<0> VDD VSS / ++ RSC_IHPSG13_NAND2X2 +.ENDS +.SUBCKT RSC_IHPSG13_AND2X6 A B Z VDD VSS +MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=2.94u l=130.00n ng=3 nrd=0 nrs=0 +MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0 +MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=4.86u l=130.00n ng=3 nrd=0 nrs=0 +MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 ++ nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_2P_COLCTRL5 A_ADDR_COL<1> A_ADDR_COL<0> A_ADDR_DEC<7> ++ A_ADDR_DEC<6> A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<31> ++ A_BLC<30> A_BLC<29> A_BLC<28> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> ++ A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC<19> A_BLC<18> A_BLC<17> ++ A_BLC<16> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> ++ A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> ++ A_BLC<1> A_BLC<0> A_BLT<31> A_BLT<30> A_BLT<29> A_BLT<28> A_BLT<27> ++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT<23> A_BLT<22> A_BLT<21> A_BLT<20> ++ A_BLT<19> A_BLT<18> A_BLT<17> A_BLT<16> A_BLT<15> A_BLT<14> A_BLT<13> ++ A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> ++ A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_COL<1> B_ADDR_COL<0> ++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> ++ B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I ++ B_BIST_EN_I B_BLC<31> B_BLC<30> B_BLC<29> B_BLC<28> B_BLC<27> B_BLC<26> ++ B_BLC<25> B_BLC<24> B_BLC<23> B_BLC<22> B_BLC<21> B_BLC<20> B_BLC<19> ++ B_BLC<18> B_BLC<17> B_BLC<16> B_BLC<15> B_BLC<14> B_BLC<13> B_BLC<12> ++ B_BLC<11> B_BLC<10> B_BLC<9> B_BLC<8> B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> ++ B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<31> B_BLT<30> B_BLT<29> B_BLT<28> ++ B_BLT<27> B_BLT<26> B_BLT<25> B_BLT<24> B_BLT<23> B_BLT<22> B_BLT<21> ++ B_BLT<20> B_BLT<19> B_BLT<18> B_BLT<17> B_BLT<16> B_BLT<15> B_BLT<14> ++ B_BLT<13> B_BLT<12> B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT<7> B_BLT<6> ++ B_BLT<5> B_BLT<4> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L ++ B_DCLK_B_R B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L ++ B_RCLK_R B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS +XB_I80<1> B_WCLK_B_L B_RCLK_B_L B_W_nor_R<1> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XB_I80<0> B_WCLK_B_L B_RCLK_B_L B_W_nor_R<0> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I80<1> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<1> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I80<0> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<0> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XI_FILL4<16> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<15> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<14> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<13> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<12> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XB_INV<6> B_N1<1> B_P1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<5> B_N0<1> B_P0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<4> B_N0<0> B_P0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<3> B_ADDR_COL<1> B_N1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<2> B_ADDR_COL<1> B_N1<0> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<1> B_ADDR_COL<0> B_N0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<0> B_ADDR_COL<0> B_N0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<6> A_N1<1> A_P1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<5> A_N0<1> A_P0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<4> A_N0<0> A_P0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<3> A_ADDR_COL<1> A_N1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<2> A_ADDR_COL<1> A_N1<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_ADDR_COL<0> A_N0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL<0> A_N0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XB_I81<3> B_W_nor_R<1> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<2> B_W_nor_R<1> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<1> B_W_nor_R<0> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<0> B_W_nor_R<0> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<3> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<2> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<1> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XI_FILL8<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XAB_BLMUX<7> A_BLC<31> A_BLC<30> A_BLC<29> A_BLC<28> A_BLC_SEL A_BLT<31> ++ A_BLT<30> A_BLT<29> A_BLT<28> A_BLT_SEL A_PRE_N A_SEL_P<31> A_SEL_P<30> ++ A_SEL_P<29> A_SEL_P<28> A_WR_ONE A_WR_ZERO B_BLC<31> B_BLC<30> B_BLC<29> ++ B_BLC<28> B_BLC_SEL B_BLT<31> B_BLT<30> B_BLT<29> B_BLT<28> B_BLT_SEL ++ B_PRE_N B_SEL_P<31> B_SEL_P<30> B_SEL_P<29> B_SEL_P<28> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_4096x8_c3_2P_BLDRV +XAB_BLMUX<6> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> A_BLC_SEL A_BLT<27> ++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT_SEL A_PRE_N A_SEL_P<27> A_SEL_P<26> ++ A_SEL_P<25> A_SEL_P<24> A_WR_ONE A_WR_ZERO B_BLC<27> B_BLC<26> B_BLC<25> ++ B_BLC<24> B_BLC_SEL B_BLT<27> B_BLT<26> B_BLT<25> B_BLT<24> B_BLT_SEL ++ B_PRE_N B_SEL_P<27> B_SEL_P<26> B_SEL_P<25> B_SEL_P<24> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_4096x8_c3_2P_BLDRV +XAB_BLMUX<5> A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC_SEL A_BLT<23> ++ A_BLT<22> A_BLT<21> A_BLT<20> A_BLT_SEL A_PRE_N A_SEL_P<23> A_SEL_P<22> ++ A_SEL_P<21> A_SEL_P<20> A_WR_ONE A_WR_ZERO B_BLC<23> B_BLC<22> B_BLC<21> ++ B_BLC<20> B_BLC_SEL B_BLT<23> B_BLT<22> B_BLT<21> B_BLT<20> B_BLT_SEL ++ B_PRE_N B_SEL_P<23> B_SEL_P<22> B_SEL_P<21> B_SEL_P<20> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_4096x8_c3_2P_BLDRV +XAB_BLMUX<4> A_BLC<19> A_BLC<18> A_BLC<17> A_BLC<16> A_BLC_SEL A_BLT<19> ++ A_BLT<18> A_BLT<17> A_BLT<16> A_BLT_SEL A_PRE_N A_SEL_P<19> A_SEL_P<18> ++ A_SEL_P<17> A_SEL_P<16> A_WR_ONE A_WR_ZERO B_BLC<19> B_BLC<18> B_BLC<17> ++ B_BLC<16> B_BLC_SEL B_BLT<19> B_BLT<18> B_BLT<17> B_BLT<16> B_BLT_SEL ++ B_PRE_N B_SEL_P<19> B_SEL_P<18> B_SEL_P<17> B_SEL_P<16> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_4096x8_c3_2P_BLDRV +XAB_BLMUX<3> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC_SEL A_BLT<15> ++ A_BLT<14> A_BLT<13> A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<15> A_SEL_P<14> ++ A_SEL_P<13> A_SEL_P<12> A_WR_ONE A_WR_ZERO B_BLC<15> B_BLC<14> B_BLC<13> ++ B_BLC<12> B_BLC_SEL B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT_SEL ++ B_PRE_N B_SEL_P<15> B_SEL_P<14> B_SEL_P<13> B_SEL_P<12> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_4096x8_c3_2P_BLDRV +XAB_BLMUX<2> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC_SEL A_BLT<11> ++ A_BLT<10> A_BLT<9> A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<11> A_SEL_P<10> ++ A_SEL_P<9> A_SEL_P<8> A_WR_ONE A_WR_ZERO B_BLC<11> B_BLC<10> B_BLC<9> ++ B_BLC<8> B_BLC_SEL B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT_SEL B_PRE_N ++ B_SEL_P<11> B_SEL_P<10> B_SEL_P<9> B_SEL_P<8> B_WR_ONE B_WR_ZERO VDD ++ VSS / RM_IHPSG13_4096x8_c3_2P_BLDRV +XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<7> A_SEL_P<6> A_SEL_P<5> ++ A_SEL_P<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC_SEL ++ B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N B_SEL_P<7> B_SEL_P<6> ++ B_SEL_P<5> B_SEL_P<4> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_BLDRV +XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> A_SEL_P<1> ++ A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLC_SEL ++ B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> B_SEL_P<2> ++ B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_BLDRV +XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6 +XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<31> net041<0> B_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<30> net041<1> B_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<29> net041<2> B_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<28> net041<3> B_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<27> net041<4> B_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<26> net041<5> B_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<25> net041<6> B_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<24> net041<7> B_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<23> net041<8> B_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<22> net041<9> B_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<21> net041<10> B_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<20> net041<11> B_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<19> net041<12> B_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<18> net041<13> B_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<17> net041<14> B_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<16> net041<15> B_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<15> net041<16> B_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<14> net041<17> B_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<13> net041<18> B_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<12> net041<19> B_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<11> net041<20> B_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<10> net041<21> B_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<9> net041<22> B_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<8> net041<23> B_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<7> net041<24> B_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<6> net041<25> B_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<5> net041<26> B_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<4> net041<27> B_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<3> net041<28> B_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<2> net041<29> B_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<1> net041<30> B_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<0> net041<31> B_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<31> net23<0> A_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<30> net23<1> A_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<29> net23<2> A_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<28> net23<3> A_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<27> net23<4> A_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<26> net23<5> A_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<25> net23<6> A_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<24> net23<7> A_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<23> net23<8> A_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<22> net23<9> A_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<21> net23<10> A_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<20> net23<11> A_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<19> net23<12> A_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<18> net23<13> A_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<17> net23<14> A_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<16> net23<15> A_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<15> net23<16> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<17> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<18> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<19> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<20> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<21> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<22> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<23> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<24> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<25> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<26> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<27> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<28> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<29> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<30> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<31> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net042 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net043 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net21 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XB_DEC3<31> B_P1<1> B_P0<1> B_ADDR_DEC<7> net041<0> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<30> B_P1<1> B_P0<1> B_ADDR_DEC<6> net041<1> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<29> B_P1<1> B_P0<1> B_ADDR_DEC<5> net041<2> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<28> B_P1<1> B_P0<1> B_ADDR_DEC<4> net041<3> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<27> B_P1<1> B_P0<1> B_ADDR_DEC<3> net041<4> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<26> B_P1<1> B_P0<1> B_ADDR_DEC<2> net041<5> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<25> B_P1<1> B_P0<1> B_ADDR_DEC<1> net041<6> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<24> B_P1<1> B_P0<1> B_ADDR_DEC<0> net041<7> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<23> B_P1<1> B_N0<1> B_ADDR_DEC<7> net041<8> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<22> B_P1<1> B_N0<1> B_ADDR_DEC<6> net041<9> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<21> B_P1<1> B_N0<1> B_ADDR_DEC<5> net041<10> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<20> B_P1<1> B_N0<1> B_ADDR_DEC<4> net041<11> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<19> B_P1<1> B_N0<1> B_ADDR_DEC<3> net041<12> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<18> B_P1<1> B_N0<1> B_ADDR_DEC<2> net041<13> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<17> B_P1<1> B_N0<1> B_ADDR_DEC<1> net041<14> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<16> B_P1<1> B_N0<1> B_ADDR_DEC<0> net041<15> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<15> B_N1<0> B_P0<0> B_ADDR_DEC<7> net041<16> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<14> B_N1<0> B_P0<0> B_ADDR_DEC<6> net041<17> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<13> B_N1<0> B_P0<0> B_ADDR_DEC<5> net041<18> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<12> B_N1<0> B_P0<0> B_ADDR_DEC<4> net041<19> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<11> B_N1<0> B_P0<0> B_ADDR_DEC<3> net041<20> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<10> B_N1<0> B_P0<0> B_ADDR_DEC<2> net041<21> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<9> B_N1<0> B_P0<0> B_ADDR_DEC<1> net041<22> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<8> B_N1<0> B_P0<0> B_ADDR_DEC<0> net041<23> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<7> B_N1<0> B_N0<0> B_ADDR_DEC<7> net041<24> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<6> B_N1<0> B_N0<0> B_ADDR_DEC<6> net041<25> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<5> B_N1<0> B_N0<0> B_ADDR_DEC<5> net041<26> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<4> B_N1<0> B_N0<0> B_ADDR_DEC<4> net041<27> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<3> B_N1<0> B_N0<0> B_ADDR_DEC<3> net041<28> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<2> B_N1<0> B_N0<0> B_ADDR_DEC<2> net041<29> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<1> B_N1<0> B_N0<0> B_ADDR_DEC<1> net041<30> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_DEC3<0> B_N1<0> B_N0<0> B_ADDR_DEC<0> net041<31> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<31> A_P1<1> A_P0<1> A_ADDR_DEC<7> net23<0> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<30> A_P1<1> A_P0<1> A_ADDR_DEC<6> net23<1> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<29> A_P1<1> A_P0<1> A_ADDR_DEC<5> net23<2> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<28> A_P1<1> A_P0<1> A_ADDR_DEC<4> net23<3> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<27> A_P1<1> A_P0<1> A_ADDR_DEC<3> net23<4> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<26> A_P1<1> A_P0<1> A_ADDR_DEC<2> net23<5> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<25> A_P1<1> A_P0<1> A_ADDR_DEC<1> net23<6> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<24> A_P1<1> A_P0<1> A_ADDR_DEC<0> net23<7> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<23> A_P1<1> A_N0<1> A_ADDR_DEC<7> net23<8> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<22> A_P1<1> A_N0<1> A_ADDR_DEC<6> net23<9> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<21> A_P1<1> A_N0<1> A_ADDR_DEC<5> net23<10> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<20> A_P1<1> A_N0<1> A_ADDR_DEC<4> net23<11> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<19> A_P1<1> A_N0<1> A_ADDR_DEC<3> net23<12> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<18> A_P1<1> A_N0<1> A_ADDR_DEC<2> net23<13> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<17> A_P1<1> A_N0<1> A_ADDR_DEC<1> net23<14> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<16> A_P1<1> A_N0<1> A_ADDR_DEC<0> net23<15> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<15> A_N1<0> A_P0<0> A_ADDR_DEC<7> net23<16> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<14> A_N1<0> A_P0<0> A_ADDR_DEC<6> net23<17> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<13> A_N1<0> A_P0<0> A_ADDR_DEC<5> net23<18> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<12> A_N1<0> A_P0<0> A_ADDR_DEC<4> net23<19> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<11> A_N1<0> A_P0<0> A_ADDR_DEC<3> net23<20> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<10> A_N1<0> A_P0<0> A_ADDR_DEC<2> net23<21> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<9> A_N1<0> A_P0<0> A_ADDR_DEC<1> net23<22> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<8> A_N1<0> A_P0<0> A_ADDR_DEC<0> net23<23> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<7> A_N1<0> A_N0<0> A_ADDR_DEC<7> net23<24> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<6> A_N1<0> A_N0<0> A_ADDR_DEC<6> net23<25> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<5> A_N1<0> A_N0<0> A_ADDR_DEC<5> net23<26> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<4> A_N1<0> A_N0<0> A_ADDR_DEC<4> net23<27> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<3> A_N1<0> A_N0<0> A_ADDR_DEC<3> net23<28> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<2> A_N1<0> A_N0<0> A_ADDR_DEC<2> net23<29> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<1> A_N1<0> A_N0<0> A_ADDR_DEC<1> net23<30> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<0> A_N1<0> A_N0<0> A_ADDR_DEC<0> net23<31> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_2P_COLDRV13_FILL4 VDD VSS +XI0<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RSC_IHPSG13_CBUFX16 A Z VDD VSS +MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=2.115u l=130.00n ng=3 nrd=0 nrs=0 +MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=5.64u l=130.00n ng=8 nrd=0 nrs=0 +MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=13.000u l=130.00n ng=8 nrd=0 ++ nrs=0 +MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=4.89u l=130.00n ng=3 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_1P_COLDRV13X16 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP8 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX16 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=12.96u l=130.00n ng=8 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_1P_WLDRV16X16 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX16 +.ENDS + + +.SUBCKT RM_IHPSG13_4096x8_c3_2P_COLDRV13X4 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX4 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1 VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_2P_WLDRV16X4 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX4 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX4 +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_2P_ROWDEC8 ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ++ ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<255> ++ WL_O<254> WL_O<253> WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> ++ WL_O<247> WL_O<246> WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> ++ WL_O<240> WL_O<239> WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> ++ WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> ++ WL_O<226> WL_O<225> WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> ++ WL_O<205> WL_O<204> WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> ++ WL_O<198> WL_O<197> WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> ++ WL_O<191> WL_O<190> WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> ++ WL_O<184> WL_O<183> WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> ++ WL_O<177> WL_O<176> WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> ++ WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> ++ WL_O<163> WL_O<162> WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> ++ WL_O<156> WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> ++ WL_O<149> WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> ++ WL_O<142> WL_O<141> WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> ++ WL_O<135> WL_O<134> WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> ++ WL_O<128> WL_O<127> WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> ++ WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> ++ WL_O<114> WL_O<113> WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> ++ WL_O<92> WL_O<91> WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> ++ WL_O<84> WL_O<83> WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> ++ WL_O<76> WL_O<75> WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> ++ WL_O<68> WL_O<67> WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> ++ WL_O<60> WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> ++ WL_O<52> WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> ++ WL_O<44> WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> ++ WL_O<36> WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> ++ WL_O<28> WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> ++ WL_O<20> WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> ++ WL_O<12> WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> ++ WL_O<3> WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC11<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<3> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<15> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<11> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC03 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_4096x8_c3_2P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_4096x8_c3_2P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_4096x8_c3_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_4096x8_c3_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_4096x8_c3_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_4096x8_c3_2P_DEC04 +XDEC10<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<2> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<14> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<10> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC02 +XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC00<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<12> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<8> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC00 +XDEC01<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<13> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<9> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC01 +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_2P_ROWREG8 ACLK_N_I ADDR_I<7> ADDR_I<6> ADDR_I<5> ADDR_I<4> ++ ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<7> ADDR_N_O<6> ADDR_N_O<5> ++ ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<7> ++ BIST_ADDR_I<6> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> ++ BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI10 VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_2P_COLDEC4 ACLK_N ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<3> BIST_ADDR<2> ++ BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int net12<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net12<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net12<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net12<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI14 addr_int ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI15 ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_2P_COLCTRL4 A_ADDR_COL A_ADDR_DEC<7> A_ADDR_DEC<6> ++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<15> A_BLC<14> ++ A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> ++ A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<15> A_BLT<14> ++ A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L ++ A_DCLK_B_R A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L ++ A_RCLK_R A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_COL ++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> ++ B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I ++ B_BIST_EN_I B_BLC<15> B_BLC<14> B_BLC<13> B_BLC<12> B_BLC<11> B_BLC<10> ++ B_BLC<9> B_BLC<8> B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC<3> B_BLC<2> ++ B_BLC<1> B_BLC<0> B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT<11> ++ B_BLT<10> B_BLT<9> B_BLT<8> B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT<3> ++ B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L B_DCLK_B_R B_DCLK_L B_DCLK_R ++ B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L B_RCLK_R B_TIEH_O B_WCLK_B_L ++ B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS +XB_I80 B_RCLK_B_L B_WCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I80 A_RCLK_B_L A_WCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4 +XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4 +XI_FILL4<26> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<25> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<24> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<23> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<22> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<21> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<20> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<19> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<18> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<17> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<16> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<15> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<14> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<13> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<12> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<1> B_N0 B_P0 VDD VSS / RSC_IHPSG13_CINVX4 +XB_INV<0> B_ADDR_COL B_N0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_N0 A_P0 VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL A_N0 VDD VSS / RSC_IHPSG13_CINVX4 +XB_I81<1> net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_I81<0> net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<1> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XAB_BLMUX<3> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC_SEL A_BLT<15> ++ A_BLT<14> A_BLT<13> A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<15> A_SEL_P<14> ++ A_SEL_P<13> A_SEL_P<12> A_WR_ONE A_WR_ZERO B_BLC<15> B_BLC<14> B_BLC<13> ++ B_BLC<12> B_BLC_SEL B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT_SEL ++ B_PRE_N B_SEL_P<15> B_SEL_P<14> B_SEL_P<13> B_SEL_P<12> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_4096x8_c3_2P_BLDRV +XAB_BLMUX<2> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC_SEL A_BLT<11> ++ A_BLT<10> A_BLT<9> A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<11> A_SEL_P<10> ++ A_SEL_P<9> A_SEL_P<8> A_WR_ONE A_WR_ZERO B_BLC<11> B_BLC<10> B_BLC<9> ++ B_BLC<8> B_BLC_SEL B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT_SEL B_PRE_N ++ B_SEL_P<11> B_SEL_P<10> B_SEL_P<9> B_SEL_P<8> B_WR_ONE B_WR_ZERO VDD ++ VSS / RM_IHPSG13_4096x8_c3_2P_BLDRV +XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<7> A_SEL_P<6> A_SEL_P<5> ++ A_SEL_P<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC_SEL ++ B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N B_SEL_P<7> B_SEL_P<6> ++ B_SEL_P<5> B_SEL_P<4> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_BLDRV +XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> A_SEL_P<1> ++ A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLC_SEL ++ B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> B_SEL_P<2> ++ B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_BLDRV +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net046 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net045 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net24 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_DEC3INV<15> net23<0> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<1> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<2> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<3> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<4> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<5> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<6> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<7> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<8> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<9> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<10> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<11> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<12> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<13> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<14> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<15> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<15> net044<0> B_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<14> net044<1> B_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<13> net044<2> B_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<12> net044<3> B_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<11> net044<4> B_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<10> net044<5> B_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<9> net044<6> B_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<8> net044<7> B_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<7> net044<8> B_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<6> net044<9> B_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<5> net044<10> B_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<4> net044<11> B_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<3> net044<12> B_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<2> net044<13> B_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<1> net044<14> B_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XB_DEC3INV<0> net044<15> B_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XI_FILL8<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_DEC3<15> A_P0 A_ADDR_DEC<7> net23<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<14> A_P0 A_ADDR_DEC<6> net23<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<13> A_P0 A_ADDR_DEC<5> net23<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<12> A_P0 A_ADDR_DEC<4> net23<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<11> A_P0 A_ADDR_DEC<3> net23<4> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<10> A_P0 A_ADDR_DEC<2> net23<5> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<9> A_P0 A_ADDR_DEC<1> net23<6> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<8> A_P0 A_ADDR_DEC<0> net23<7> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<7> A_N0 A_ADDR_DEC<7> net23<8> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<6> A_N0 A_ADDR_DEC<6> net23<9> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<5> A_N0 A_ADDR_DEC<5> net23<10> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<4> A_N0 A_ADDR_DEC<4> net23<11> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<3> A_N0 A_ADDR_DEC<3> net23<12> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<2> A_N0 A_ADDR_DEC<2> net23<13> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<1> A_N0 A_ADDR_DEC<1> net23<14> VDD VSS / RSC_IHPSG13_NAND2X2 +XA_DEC3<0> A_N0 A_ADDR_DEC<0> net23<15> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<15> B_P0 B_ADDR_DEC<7> net044<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<14> B_P0 B_ADDR_DEC<6> net044<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<13> B_P0 B_ADDR_DEC<5> net044<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<12> B_P0 B_ADDR_DEC<4> net044<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<11> B_P0 B_ADDR_DEC<3> net044<4> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<10> B_P0 B_ADDR_DEC<2> net044<5> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<9> B_P0 B_ADDR_DEC<1> net044<6> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<8> B_P0 B_ADDR_DEC<0> net044<7> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<7> B_N0 B_ADDR_DEC<7> net044<8> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<6> B_N0 B_ADDR_DEC<6> net044<9> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<5> B_N0 B_ADDR_DEC<5> net044<10> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<4> B_N0 B_ADDR_DEC<4> net044<11> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<3> B_N0 B_ADDR_DEC<3> net044<12> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<2> B_N0 B_ADDR_DEC<2> net044<13> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<1> B_N0 B_ADDR_DEC<1> net044<14> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_DEC3<0> B_N0 B_ADDR_DEC<0> net044<15> VDD VSS / RSC_IHPSG13_NAND2X2 +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS + + +.SUBCKT RM_IHPSG13_4096x8_c3_2P_ROWDEC5 ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ++ ADDR_N_I<0> CS_I ECLK_I WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC00 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_4096x8_c3_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_4096x8_c3_2P_DEC04 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC01 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0 ADDR_N_I<5> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_2P_ROWREG5 ACLK_N_I ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ++ ADDR_I<0> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_4096x8_c3_2P_COLDEC3 ACLK_N ADDR<2> ADDR<1> ADDR<0> ADDR_COL<1> ++ ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ++ ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> ++ BIST_EN_I VDD VSS +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net13<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net13<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net13<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RSC_IHPSG13_DFPQD_MSAFFX2P CP DN DP QN QP VDD VSS +XI_AMP CP DN DP QN QP VDD VSS / RSC_IHPSG13_DFPQD_MSAFFX2 +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_2P_COLCTRL3 A_ADDR_DEC<7> A_ADDR_DEC<6> A_ADDR_DEC<5> ++ A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> A_ADDR_DEC<0> ++ A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> ++ A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> ++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R A_DCLK_L ++ A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R A_TIEH_O ++ A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_DEC<7> B_ADDR_DEC<6> ++ B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> ++ B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I B_BIST_EN_I B_BLC<7> B_BLC<6> B_BLC<5> ++ B_BLC<4> B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<7> B_BLT<6> B_BLT<5> ++ B_BLT<4> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L B_DCLK_B_R ++ B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L B_RCLK_R ++ B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net044 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net043 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2P +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2P +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> ++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_ADDR_DEC<7> A_ADDR_DEC<6> ++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> ++ B_BLC<4> B_BLC_SEL B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N ++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_4096x8_c3_2P_BLDRV +XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> ++ B_BLC<0> B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N ++ B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_4096x8_c3_2P_BLDRV +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I80 B_WCLK_B_L B_RCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2 +XB_I76 B_DO_WRITE_P B_DI_N B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XB_I75 B_DO_WRITE_P B_DI_R B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_I80 A_WCLK_B_L A_RCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XB_I81 net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_4096x8_c3_2P_ROWDEC6 ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ++ ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<63> WL_O<62> WL_O<61> WL_O<60> ++ WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> ++ WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> ++ WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> ++ WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> ++ WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> ++ WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> ++ WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> ++ WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC10 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<2> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC02 +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC00 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_4096x8_c3_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_4096x8_c3_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_4096x8_c3_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_4096x8_c3_2P_DEC04 +XDEC11 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<3> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC03 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC01 +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_2P_ROWREG6 ACLK_N_I ADDR_I<5> ADDR_I<4> ADDR_I<3> ADDR_I<2> ++ ADDR_I<1> ADDR_I<0> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ++ ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_4096x8_c3_2P_COLDRV13X16 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX16 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX16 +XI1<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_2P_WLDRV16X16 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX16 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX16 +.ENDS + + +.SUBCKT RM_IHPSG13_4096x8_c3_1P_DEC01 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XDEC NADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XI2 VDD VSS / RSC_IHPSG13_FILLCAP4 +XADDRINV ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_1P_DEC00 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XDEC NADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XADDRINV<1> ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2 +XADDRINV<0> ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI1 VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_1P_ROWDEC5 ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ++ ADDR_N_I<0> CS_I ECLK_I WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC01 +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC00 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_4096x8_c3_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_4096x8_c3_1P_DEC04 +XI0 ADDR_N_I<5> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_1P_ROWREG5 ACLK_N_I ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ++ ADDR_I<0> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + + +.SUBCKT RM_IHPSG13_4096x8_c3_1P_COLDEC5 ACLK_N ADDR<4> ADDR<3> ADDR<2> ADDR<1> ADDR<0> ++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<4> BIST_ADDR<3> ++ BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI13<1> addr_int<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_CBUFX2 +XI13<0> addr_int<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2 +XDFF<4> BIST_EN_I BIST_ADDR<4> ACLK_N ADDR<4> addr_int<1> net7<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int<0> net7<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net7<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net7<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net7<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2 +XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2 +XI15<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI15<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI15<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2 +XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2 +XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2 +XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_1P_COLCTRL5 A_ADDR_COL<1> A_ADDR_COL<0> A_ADDR_DEC<7> ++ A_ADDR_DEC<6> A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<31> ++ A_BLC<30> A_BLC<29> A_BLC<28> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> ++ A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC<19> A_BLC<18> A_BLC<17> ++ A_BLC<16> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> ++ A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> ++ A_BLC<1> A_BLC<0> A_BLT<31> A_BLT<30> A_BLT<29> A_BLT<28> A_BLT<27> ++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT<23> A_BLT<22> A_BLT<21> A_BLT<20> ++ A_BLT<19> A_BLT<18> A_BLT<17> A_BLT<16> A_BLT<15> A_BLT<14> A_BLT<13> ++ A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> ++ A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS +XA_I80<1> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<1> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I80<0> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<0> VDD VSS / ++ RSC_IHPSG13_AND2X2 +XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XI80<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI80<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_I74<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XA_INV<6> A_N1<1> A_P1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<5> A_N0<1> A_P0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<4> A_N0<0> A_P0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<3> A_ADDR_COL<1> A_N1<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<2> A_ADDR_COL<1> A_N1<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<1> A_ADDR_COL<0> A_N0<1> VDD VSS / RSC_IHPSG13_CINVX4 +XA_INV<0> A_ADDR_COL<0> A_N0<0> VDD VSS / RSC_IHPSG13_CINVX4 +XA_I81<3> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<2> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<1> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81<0> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_BLTMUX<31> A_BLC<31> A_BLC_SEL A_BLT<31> A_BLT_SEL A_PRE_N A_SEL_P<31> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV +XA_BLTMUX<30> A_BLC<30> A_BLC_SEL A_BLT<30> A_BLT_SEL A_PRE_N A_SEL_P<30> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV +XA_BLTMUX<29> A_BLC<29> A_BLC_SEL A_BLT<29> A_BLT_SEL A_PRE_N A_SEL_P<29> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV +XA_BLTMUX<28> A_BLC<28> A_BLC_SEL A_BLT<28> A_BLT_SEL A_PRE_N A_SEL_P<28> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV +XA_BLTMUX<27> A_BLC<27> A_BLC_SEL A_BLT<27> A_BLT_SEL A_PRE_N A_SEL_P<27> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV +XA_BLTMUX<26> A_BLC<26> A_BLC_SEL A_BLT<26> A_BLT_SEL A_PRE_N A_SEL_P<26> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV +XA_BLTMUX<25> A_BLC<25> A_BLC_SEL A_BLT<25> A_BLT_SEL A_PRE_N A_SEL_P<25> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV +XA_BLTMUX<24> A_BLC<24> A_BLC_SEL A_BLT<24> A_BLT_SEL A_PRE_N A_SEL_P<24> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV +XA_BLTMUX<23> A_BLC<23> A_BLC_SEL A_BLT<23> A_BLT_SEL A_PRE_N A_SEL_P<23> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV +XA_BLTMUX<22> A_BLC<22> A_BLC_SEL A_BLT<22> A_BLT_SEL A_PRE_N A_SEL_P<22> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV +XA_BLTMUX<21> A_BLC<21> A_BLC_SEL A_BLT<21> A_BLT_SEL A_PRE_N A_SEL_P<21> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV +XA_BLTMUX<20> A_BLC<20> A_BLC_SEL A_BLT<20> A_BLT_SEL A_PRE_N A_SEL_P<20> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV +XA_BLTMUX<19> A_BLC<19> A_BLC_SEL A_BLT<19> A_BLT_SEL A_PRE_N A_SEL_P<19> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV +XA_BLTMUX<18> A_BLC<18> A_BLC_SEL A_BLT<18> A_BLT_SEL A_PRE_N A_SEL_P<18> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV +XA_BLTMUX<17> A_BLC<17> A_BLC_SEL A_BLT<17> A_BLT_SEL A_PRE_N A_SEL_P<17> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV +XA_BLTMUX<16> A_BLC<16> A_BLC_SEL A_BLT<16> A_BLT_SEL A_PRE_N A_SEL_P<16> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV +XA_BLTMUX<15> A_BLC<15> A_BLC_SEL A_BLT<15> A_BLT_SEL A_PRE_N A_SEL_P<15> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV +XA_BLTMUX<14> A_BLC<14> A_BLC_SEL A_BLT<14> A_BLT_SEL A_PRE_N A_SEL_P<14> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV +XA_BLTMUX<13> A_BLC<13> A_BLC_SEL A_BLT<13> A_BLT_SEL A_PRE_N A_SEL_P<13> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV +XA_BLTMUX<12> A_BLC<12> A_BLC_SEL A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<12> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV +XA_BLTMUX<11> A_BLC<11> A_BLC_SEL A_BLT<11> A_BLT_SEL A_PRE_N A_SEL_P<11> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV +XA_BLTMUX<10> A_BLC<10> A_BLC_SEL A_BLT<10> A_BLT_SEL A_PRE_N A_SEL_P<10> ++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV +XA_BLTMUX<9> A_BLC<9> A_BLC_SEL A_BLT<9> A_BLT_SEL A_PRE_N A_SEL_P<9> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV +XA_BLTMUX<8> A_BLC<8> A_BLC_SEL A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<8> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV +XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_SEL_P<7> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV +XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_SEL_P<6> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV +XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_SEL_P<5> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV +XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<4> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV +XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_SEL_P<3> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV +XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_SEL_P<2> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV +XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_SEL_P<1> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV +XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<0> A_WR_ONE ++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV +XA_CAPS<17> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<16> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<15> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<14> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<13> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<12> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<11> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<10> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<9> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<8> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<7> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<6> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<31> net23<0> A_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<30> net23<1> A_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<29> net23<2> A_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<28> net23<3> A_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<27> net23<4> A_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<26> net23<5> A_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<25> net23<6> A_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<24> net23<7> A_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<23> net23<8> A_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<22> net23<9> A_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<21> net23<10> A_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<20> net23<11> A_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<19> net23<12> A_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<18> net23<13> A_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<17> net23<14> A_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<16> net23<15> A_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<15> net23<16> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<14> net23<17> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<13> net23<18> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<12> net23<19> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<11> net23<20> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<10> net23<21> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<9> net23<22> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<8> net23<23> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<7> net23<24> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<6> net23<25> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<5> net23<26> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<4> net23<27> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<3> net23<28> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<2> net23<29> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<1> net23<30> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2 +XA_DEC3INV<0> net23<31> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net21 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_DEC3<31> A_P1<1> A_P0<1> A_ADDR_DEC<7> net23<0> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<30> A_P1<1> A_P0<1> A_ADDR_DEC<6> net23<1> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<29> A_P1<1> A_P0<1> A_ADDR_DEC<5> net23<2> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<28> A_P1<1> A_P0<1> A_ADDR_DEC<4> net23<3> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<27> A_P1<1> A_P0<1> A_ADDR_DEC<3> net23<4> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<26> A_P1<1> A_P0<1> A_ADDR_DEC<2> net23<5> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<25> A_P1<1> A_P0<1> A_ADDR_DEC<1> net23<6> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<24> A_P1<1> A_P0<1> A_ADDR_DEC<0> net23<7> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<23> A_P1<1> A_N0<1> A_ADDR_DEC<7> net23<8> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<22> A_P1<1> A_N0<1> A_ADDR_DEC<6> net23<9> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<21> A_P1<1> A_N0<1> A_ADDR_DEC<5> net23<10> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<20> A_P1<1> A_N0<1> A_ADDR_DEC<4> net23<11> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<19> A_P1<1> A_N0<1> A_ADDR_DEC<3> net23<12> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<18> A_P1<1> A_N0<1> A_ADDR_DEC<2> net23<13> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<17> A_P1<1> A_N0<1> A_ADDR_DEC<1> net23<14> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<16> A_P1<1> A_N0<1> A_ADDR_DEC<0> net23<15> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<15> A_N1<0> A_P0<0> A_ADDR_DEC<7> net23<16> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<14> A_N1<0> A_P0<0> A_ADDR_DEC<6> net23<17> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<13> A_N1<0> A_P0<0> A_ADDR_DEC<5> net23<18> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<12> A_N1<0> A_P0<0> A_ADDR_DEC<4> net23<19> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<11> A_N1<0> A_P0<0> A_ADDR_DEC<3> net23<20> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<10> A_N1<0> A_P0<0> A_ADDR_DEC<2> net23<21> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<9> A_N1<0> A_P0<0> A_ADDR_DEC<1> net23<22> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<8> A_N1<0> A_P0<0> A_ADDR_DEC<0> net23<23> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<7> A_N1<0> A_N0<0> A_ADDR_DEC<7> net23<24> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<6> A_N1<0> A_N0<0> A_ADDR_DEC<6> net23<25> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<5> A_N1<0> A_N0<0> A_ADDR_DEC<5> net23<26> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<4> A_N1<0> A_N0<0> A_ADDR_DEC<4> net23<27> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<3> A_N1<0> A_N0<0> A_ADDR_DEC<3> net23<28> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<2> A_N1<0> A_N0<0> A_ADDR_DEC<2> net23<29> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<1> A_N1<0> A_N0<0> A_ADDR_DEC<1> net23<30> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_DEC3<0> A_N1<0> A_N0<0> A_ADDR_DEC<0> net23<31> VDD VSS / ++ RSC_IHPSG13_NAND3X2 +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +.ENDS + +.SUBCKT RM_IHPSG13_4096x8_c3_1P_COLDRV13X12 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP8 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX12 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX12 +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_1P_WLDRV16X12 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX12 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX12 +.ENDS + + + +.SUBCKT RM_IHPSG13_4096x8_c3_2P_COLDRV13X8 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RSC_IHPSG13_WLDRVX8 A Z VDD VSS +MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0 +MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0 +MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0 +MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0 +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_2P_WLDRV16X8 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX8 +.ENDS + + + +.SUBCKT RM_IHPSG13_4096x8_c3_2P_COLDEC2 ACLK_N ADDR<1> ADDR<0> ADDR_COL<1> ADDR_COL<0> ++ ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ADDR_DEC<2> ++ ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS +XI16<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI18<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI1<3> PADR<0> PADR<1> addr_n<3> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<2> NADR<0> PADR<1> addr_n<2> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<1> PADR<0> NADR<1> addr_n<1> VDD VSS / RSC_IHPSG13_NAND2X2 +XI1<0> NADR<0> NADR<1> addr_n<0> VDD VSS / RSC_IHPSG13_NAND2X2 +XI17<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL +XI17<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL +XI14<3> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_TIEL +XI14<2> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_TIEL +XI14<1> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_TIEL +XI14<0> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_TIEL +XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2 +XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2 +XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2 +XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2 +XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2 +XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2 +XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net12<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net12<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI15<5> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI15<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI19<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_2P_COLCTRL2 A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> ++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<3> A_BLC<2> A_BLC<1> ++ A_BLC<0> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R ++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R ++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_DEC<3> B_ADDR_DEC<2> ++ B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I B_BIST_EN_I B_BLC<3> ++ B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I ++ B_DCLK_B_L B_DCLK_B_R B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R ++ B_RCLK_L B_RCLK_R B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD ++ VSS +XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net046 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net045 VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS ++ / RSC_IHPSG13_DFNQMX2IX1 +XB_CAPS VDD VSS / RSC_IHPSG13_FILLCAP4 +XA_CAPS VDD VSS / RSC_IHPSG13_FILLCAP4 +XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XB_I80 B_RCLK_B_L B_WCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2 +XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XA_I80 A_RCLK_B_L A_WCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2 +XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2 +XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2 +XB_I44 B_WCLK_B_L B_BM_N B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XA_I44 A_WCLK_B_L A_BM_N A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2 +XB_I81 net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN +XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH +XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES +XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES +XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES +XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES +XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES +XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES +XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES +XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES +XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES +XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES +XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES +XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES +XAB_BLMUX A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> ++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> A_ADDR_DEC<2> ++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> ++ B_BLC<0> B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N ++ B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_WR_ONE B_WR_ZERO ++ VDD VSS / RM_IHPSG13_4096x8_c3_2P_BLDRV +XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net039 net040 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / ++ RSC_IHPSG13_DFPQD_MSAFFX2 +XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2 +XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2 +XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2 +XB_I51 net039 B_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4 +XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2 +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_2P_COLDRV13_FILL4C2 VDD VSS +XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_4096x8_c3_2P_ROWDEC7 ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ++ ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<127> WL_O<126> ++ WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> ++ WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> ++ WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> WL_O<105> ++ WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> WL_O<98> WL_O<97> ++ WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> WL_O<90> WL_O<89> ++ WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> WL_O<82> WL_O<81> ++ WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> WL_O<74> WL_O<73> ++ WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> WL_O<66> WL_O<65> ++ WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> WL_O<58> WL_O<57> ++ WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> WL_O<50> WL_O<49> ++ WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> WL_O<42> WL_O<41> ++ WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> WL_O<34> WL_O<33> ++ WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> WL_O<26> WL_O<25> ++ WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> WL_O<18> WL_O<17> ++ WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_4096x8_c3_2P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_4096x8_c3_2P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_4096x8_c3_2P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_4096x8_c3_2P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_4096x8_c3_2P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_4096x8_c3_2P_DEC04 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC03 +XDEC01<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC01 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC02 +XDEC00<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_4096x8_c3_2P_DEC00 +XI0 ADDR_N_I<7> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_2P_ROWREG7 ACLK_N_I ADDR_I<6> ADDR_I<5> ADDR_I<4> ADDR_I<3> ++ ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<6> ++ BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> ++ BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<0> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + +.SUBCKT RM_IHPSG13_4096x8_c3_2P_ROWDEC4 ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> ++ CS_I ECLK_I WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XSEL ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ECLK_H<1> ++ ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> ++ WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> ++ WL_O<0> VDD VSS / RM_IHPSG13_4096x8_c3_2P_DEC04 +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_2P_ROWREG4 ACLK_N_I ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net7<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net7<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net7<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net7<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI12<4> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<3> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +.ENDS + + +.SUBCKT RM_IHPSG13_4096x8_c3_1P_BITKIT_TAP BLC BLT NW PW VDD VSS +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_TAP A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> ++ VDD_CORE VSS +XITAP<1> A_BLC<1> A_BLT<1> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_4096x8_c3_1P_BITKIT_TAP +XITAP<0> A_BLC<0> A_BLT<0> VDD_CORE VSS VDD_CORE VSS ++ / RM_IHPSG13_4096x8_c3_1P_BITKIT_TAP +XIEDGEBP_COL1<1> BLC<1> BLT<1> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_EDGE_TB +XIEDGEBP_COL1<0> BLC<1> BLT<1> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_EDGE_TB +XIEDGEBP_COL2<1> BLC<0> BLT<0> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_EDGE_TB +XIEDGEBP_COL2<0> BLC<0> BLT<0> VDD_CORE VSS VDD_CORE ++ VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_EDGE_TB +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_TAP_LR VDD_CORE VSS +XCORNER<1> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x8_c3_1P_BITKIT_CORNER +XCORNER<0> VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x8_c3_1P_BITKIT_CORNER +XTAP_BORDER VDD_CORE VSS VDD_CORE VSS / ++ RM_IHPSG13_4096x8_c3_1P_BITKIT_TAP_LR +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_1P_DEC03 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XI0 VDD VSS / RSC_IHPSG13_FILLCAP4 +XDEC ADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_1P_DEC02 ADDR<1> ADDR<0> CS CS_OUT VDD VSS +XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4 +XDEC ADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2 +XI2 VDD VSS / RSC_IHPSG13_FILLCAP4 +XADDRINV ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2 +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_1P_ROWDEC8 ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ++ ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<255> ++ WL_O<254> WL_O<253> WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> ++ WL_O<247> WL_O<246> WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> ++ WL_O<240> WL_O<239> WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> ++ WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> ++ WL_O<226> WL_O<225> WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> ++ WL_O<205> WL_O<204> WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> ++ WL_O<198> WL_O<197> WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> ++ WL_O<191> WL_O<190> WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> ++ WL_O<184> WL_O<183> WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> ++ WL_O<177> WL_O<176> WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> ++ WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> ++ WL_O<163> WL_O<162> WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> ++ WL_O<156> WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> ++ WL_O<149> WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> ++ WL_O<142> WL_O<141> WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> ++ WL_O<135> WL_O<134> WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> ++ WL_O<128> WL_O<127> WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> ++ WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> ++ WL_O<114> WL_O<113> WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> ++ WL_O<92> WL_O<91> WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> ++ WL_O<84> WL_O<83> WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> ++ WL_O<76> WL_O<75> WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> ++ WL_O<68> WL_O<67> WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> ++ WL_O<60> WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> ++ WL_O<52> WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> ++ WL_O<44> WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> ++ WL_O<36> WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> ++ WL_O<28> WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> ++ WL_O<20> WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> ++ WL_O<12> WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> ++ WL_O<3> WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC11<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<3> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<15> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<11> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC03 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC10<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<2> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<14> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<10> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC02 +XDEC00<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<12> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<8> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC00 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_4096x8_c3_1P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_4096x8_c3_1P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_4096x8_c3_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_4096x8_c3_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_4096x8_c3_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_4096x8_c3_1P_DEC04 +XDEC01<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<13> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<9> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC01 +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_1P_ROWREG8 ACLK_N_I ADDR_I<7> ADDR_I<6> ADDR_I<5> ADDR_I<4> ++ ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<7> ADDR_N_O<6> ADDR_N_O<5> ++ ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<7> ++ BIST_ADDR_I<6> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> ++ BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + +.SUBCKT RM_IHPSG13_4096x8_c3_1P_ROWDEC9 ADDR_N_I<8> ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ++ ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ++ WL_O<511> WL_O<510> WL_O<509> WL_O<508> WL_O<507> WL_O<506> WL_O<505> ++ WL_O<504> WL_O<503> WL_O<502> WL_O<501> WL_O<500> WL_O<499> WL_O<498> ++ WL_O<497> WL_O<496> WL_O<495> WL_O<494> WL_O<493> WL_O<492> WL_O<491> ++ WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> WL_O<484> ++ WL_O<483> WL_O<482> WL_O<481> WL_O<480> WL_O<479> WL_O<478> WL_O<477> ++ WL_O<476> WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> ++ WL_O<469> WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> WL_O<463> ++ WL_O<462> WL_O<461> WL_O<460> WL_O<459> WL_O<458> WL_O<457> WL_O<456> ++ WL_O<455> WL_O<454> WL_O<453> WL_O<452> WL_O<451> WL_O<450> WL_O<449> ++ WL_O<448> WL_O<447> WL_O<446> WL_O<445> WL_O<444> WL_O<443> WL_O<442> ++ WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> WL_O<436> WL_O<435> ++ WL_O<434> WL_O<433> WL_O<432> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> WL_O<415> WL_O<414> ++ WL_O<413> WL_O<412> WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> ++ WL_O<406> WL_O<405> WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> ++ WL_O<399> WL_O<398> WL_O<397> WL_O<396> WL_O<395> WL_O<394> WL_O<393> ++ WL_O<392> WL_O<391> WL_O<390> WL_O<389> WL_O<388> WL_O<387> WL_O<386> ++ WL_O<385> WL_O<384> WL_O<383> WL_O<382> WL_O<381> WL_O<380> WL_O<379> ++ WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> WL_O<372> ++ WL_O<371> WL_O<370> WL_O<369> WL_O<368> WL_O<367> WL_O<366> WL_O<365> ++ WL_O<364> WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> ++ WL_O<357> WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> WL_O<351> ++ WL_O<350> WL_O<349> WL_O<348> WL_O<347> WL_O<346> WL_O<345> WL_O<344> ++ WL_O<343> WL_O<342> WL_O<341> WL_O<340> WL_O<339> WL_O<338> WL_O<337> ++ WL_O<336> WL_O<335> WL_O<334> WL_O<333> WL_O<332> WL_O<331> WL_O<330> ++ WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> WL_O<324> WL_O<323> ++ WL_O<322> WL_O<321> WL_O<320> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> WL_O<303> WL_O<302> ++ WL_O<301> WL_O<300> WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> ++ WL_O<294> WL_O<293> WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> ++ WL_O<287> WL_O<286> WL_O<285> WL_O<284> WL_O<283> WL_O<282> WL_O<281> ++ WL_O<280> WL_O<279> WL_O<278> WL_O<277> WL_O<276> WL_O<275> WL_O<274> ++ WL_O<273> WL_O<272> WL_O<271> WL_O<270> WL_O<269> WL_O<268> WL_O<267> ++ WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> WL_O<260> ++ WL_O<259> WL_O<258> WL_O<257> WL_O<256> WL_O<255> WL_O<254> WL_O<253> ++ WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> ++ WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> WL_O<239> ++ WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> WL_O<233> WL_O<232> ++ WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> WL_O<226> WL_O<225> ++ WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> WL_O<219> WL_O<218> ++ WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> WL_O<212> WL_O<211> ++ WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> WL_O<191> WL_O<190> ++ WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> ++ WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> ++ WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> WL_O<170> WL_O<169> ++ WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> WL_O<163> WL_O<162> ++ WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> WL_O<156> WL_O<155> ++ WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> WL_O<148> ++ WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> WL_O<142> WL_O<141> ++ WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> ++ WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> WL_O<127> ++ WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> ++ WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> ++ WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> ++ WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> ++ WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS +XL2<172> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<171> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<170> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<169> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<168> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<167> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<166> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<165> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<164> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<163> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<162> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<161> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<160> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<159> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<158> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<157> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<156> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<155> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<154> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<153> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<152> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<151> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<150> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<149> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<148> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<147> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<146> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<145> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<144> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<143> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<142> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<141> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<140> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<139> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<138> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<137> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<136> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<135> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<134> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<133> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XDEC11<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<7> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC03 +XDEC11<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<3> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC03 +XDEC11<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<31> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC03 +XDEC11<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<27> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC03 +XDEC11<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<23> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC03 +XDEC11<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<19> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC03 +XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<15> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC03 +XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<11> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC03 +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<7> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<3> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC03 +XDEC00<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC00 +XDEC00<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<4> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC00 +XDEC00<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<0> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC00 +XDEC00<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<28> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC00 +XDEC00<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<24> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC00 +XDEC00<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<20> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC00 +XDEC00<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<16> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC00 +XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<12> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC00 +XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<8> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<4> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<0> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC00 +XSEL<31> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<31> ECLK_H<31> ++ ECLK_H<32> ECLK_B<31> ECLK_B<32> WL_O<511> WL_O<510> WL_O<509> WL_O<508> ++ WL_O<507> WL_O<506> WL_O<505> WL_O<504> WL_O<503> WL_O<502> WL_O<501> ++ WL_O<500> WL_O<499> WL_O<498> WL_O<497> WL_O<496> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC04 +XSEL<30> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<30> ECLK_H<30> ++ ECLK_H<31> ECLK_B<30> ECLK_B<31> WL_O<495> WL_O<494> WL_O<493> WL_O<492> ++ WL_O<491> WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> ++ WL_O<484> WL_O<483> WL_O<482> WL_O<481> WL_O<480> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC04 +XSEL<29> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<29> ECLK_H<29> ++ ECLK_H<30> ECLK_B<29> ECLK_B<30> WL_O<479> WL_O<478> WL_O<477> WL_O<476> ++ WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> WL_O<469> ++ WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC04 +XSEL<28> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<28> ECLK_H<28> ++ ECLK_H<29> ECLK_B<28> ECLK_B<29> WL_O<463> WL_O<462> WL_O<461> WL_O<460> ++ WL_O<459> WL_O<458> WL_O<457> WL_O<456> WL_O<455> WL_O<454> WL_O<453> ++ WL_O<452> WL_O<451> WL_O<450> WL_O<449> WL_O<448> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC04 +XSEL<27> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<27> ECLK_H<27> ++ ECLK_H<28> ECLK_B<27> ECLK_B<28> WL_O<447> WL_O<446> WL_O<445> WL_O<444> ++ WL_O<443> WL_O<442> WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> ++ WL_O<436> WL_O<435> WL_O<434> WL_O<433> WL_O<432> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC04 +XSEL<26> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<26> ECLK_H<26> ++ ECLK_H<27> ECLK_B<26> ECLK_B<27> WL_O<431> WL_O<430> WL_O<429> WL_O<428> ++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> ++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC04 +XSEL<25> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<25> ECLK_H<25> ++ ECLK_H<26> ECLK_B<25> ECLK_B<26> WL_O<415> WL_O<414> WL_O<413> WL_O<412> ++ WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> WL_O<406> WL_O<405> ++ WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC04 +XSEL<24> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<24> ECLK_H<24> ++ ECLK_H<25> ECLK_B<24> ECLK_B<25> WL_O<399> WL_O<398> WL_O<397> WL_O<396> ++ WL_O<395> WL_O<394> WL_O<393> WL_O<392> WL_O<391> WL_O<390> WL_O<389> ++ WL_O<388> WL_O<387> WL_O<386> WL_O<385> WL_O<384> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC04 +XSEL<23> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<23> ECLK_H<23> ++ ECLK_H<24> ECLK_B<23> ECLK_B<24> WL_O<383> WL_O<382> WL_O<381> WL_O<380> ++ WL_O<379> WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> ++ WL_O<372> WL_O<371> WL_O<370> WL_O<369> WL_O<368> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC04 +XSEL<22> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<22> ECLK_H<22> ++ ECLK_H<23> ECLK_B<22> ECLK_B<23> WL_O<367> WL_O<366> WL_O<365> WL_O<364> ++ WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> WL_O<357> ++ WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC04 +XSEL<21> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<21> ECLK_H<21> ++ ECLK_H<22> ECLK_B<21> ECLK_B<22> WL_O<351> WL_O<350> WL_O<349> WL_O<348> ++ WL_O<347> WL_O<346> WL_O<345> WL_O<344> WL_O<343> WL_O<342> WL_O<341> ++ WL_O<340> WL_O<339> WL_O<338> WL_O<337> WL_O<336> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC04 +XSEL<20> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<20> ECLK_H<20> ++ ECLK_H<21> ECLK_B<20> ECLK_B<21> WL_O<335> WL_O<334> WL_O<333> WL_O<332> ++ WL_O<331> WL_O<330> WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> ++ WL_O<324> WL_O<323> WL_O<322> WL_O<321> WL_O<320> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC04 +XSEL<19> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<19> ECLK_H<19> ++ ECLK_H<20> ECLK_B<19> ECLK_B<20> WL_O<319> WL_O<318> WL_O<317> WL_O<316> ++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> ++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC04 +XSEL<18> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<18> ECLK_H<18> ++ ECLK_H<19> ECLK_B<18> ECLK_B<19> WL_O<303> WL_O<302> WL_O<301> WL_O<300> ++ WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> WL_O<294> WL_O<293> ++ WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC04 +XSEL<17> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<17> ECLK_H<17> ++ ECLK_H<18> ECLK_B<17> ECLK_B<18> WL_O<287> WL_O<286> WL_O<285> WL_O<284> ++ WL_O<283> WL_O<282> WL_O<281> WL_O<280> WL_O<279> WL_O<278> WL_O<277> ++ WL_O<276> WL_O<275> WL_O<274> WL_O<273> WL_O<272> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC04 +XSEL<16> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<16> ECLK_H<16> ++ ECLK_H<17> ECLK_B<16> ECLK_B<17> WL_O<271> WL_O<270> WL_O<269> WL_O<268> ++ WL_O<267> WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> ++ WL_O<260> WL_O<259> WL_O<258> WL_O<257> WL_O<256> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC04 +XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> ++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> ++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> ++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC04 +XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> ++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> ++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> ++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC04 +XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> ++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> ++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> ++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC04 +XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> ++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> ++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> ++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC04 +XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> ++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> ++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> ++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC04 +XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> ++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> ++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> ++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC04 +XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> ++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> ++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> ++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC04 +XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> ++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> ++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> ++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC04 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_4096x8_c3_1P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_4096x8_c3_1P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_4096x8_c3_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_4096x8_c3_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_4096x8_c3_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_4096x8_c3_1P_DEC04 +XDEC01<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC01 +XDEC01<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<5> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC01 +XDEC01<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<1> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC01 +XDEC01<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<29> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC01 +XDEC01<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<25> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC01 +XDEC01<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<21> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC01 +XDEC01<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<17> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC01 +XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<13> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC01 +XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<9> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<5> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<1> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC01 +XDEC10<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<6> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC02 +XDEC10<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<2> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC02 +XDEC10<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<30> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC02 +XDEC10<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<26> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC02 +XDEC10<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<22> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC02 +XDEC10<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<18> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC02 +XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<14> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC02 +XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<10> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC02 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<6> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<2> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC02 +XI0 ADDR_N_I<9> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_1P_ROWREG9 ACLK_N_I ADDR_I<8> ADDR_I<7> ADDR_I<6> ADDR_I<5> ++ ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<8> ADDR_N_O<7> ++ ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ++ ADDR_N_O<0> BIST_ADDR_I<8> BIST_ADDR_I<7> BIST_ADDR_I<6> BIST_ADDR_I<5> ++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> ++ BIST_EN_I VDD VSS +XINV<8> q_int<8> qn_int<8> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<8> qn_int<8> ADDR_N_O<8> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<8> BIST_EN_I BIST_ADDR_I<8> ACLK_N_I ADDR_I<8> q_int<8> net04<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net04<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net04<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net04<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net04<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net04<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net04<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net04<7> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net04<8> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +.ENDS + +.SUBCKT RM_IHPSG13_4096x8_c3_1P_ROWDEC7 ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ++ ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<127> WL_O<126> ++ WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> ++ WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> ++ WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> WL_O<105> ++ WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> WL_O<98> WL_O<97> ++ WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> WL_O<90> WL_O<89> ++ WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> WL_O<82> WL_O<81> ++ WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> WL_O<74> WL_O<73> ++ WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> WL_O<66> WL_O<65> ++ WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> WL_O<58> WL_O<57> ++ WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> WL_O<50> WL_O<49> ++ WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> WL_O<42> WL_O<41> ++ WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> WL_O<34> WL_O<33> ++ WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> WL_O<26> WL_O<25> ++ WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> WL_O<18> WL_O<17> ++ WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> ++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> ++ VDD VSS +XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC03 +XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC03 +XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC02 +XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC02 +XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> ++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> ++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> ++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC04 +XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> ++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> ++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> ++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC04 +XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> ++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> ++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> ++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_4096x8_c3_1P_DEC04 +XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> ++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> ++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> ++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_4096x8_c3_1P_DEC04 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_4096x8_c3_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_4096x8_c3_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_4096x8_c3_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_4096x8_c3_1P_DEC04 +XDEC00<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC00 +XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC00 +XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC00 +XDEC01<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC01 +XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC01 +XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC01 +XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI0 ADDR_N_I<7> VDD VSS / RSC_IHPSG13_TIEL +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_1P_ROWREG7 ACLK_N_I ADDR_I<6> ADDR_I<5> ADDR_I<4> ADDR_I<3> ++ ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<6> ++ BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> ++ BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<6> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + +.SUBCKT RM_IHPSG13_4096x8_c3_1P_COLDRV13X8 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> ++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> ++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> ++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> ++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O ++ VDD VSS +XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4 +XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP4 +XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / ++ RSC_IHPSG13_CBUFX8 +XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX8 +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_1P_WLDRV16X8 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> ++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> ++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS +XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX8 +XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX8 +.ENDS + + + +.SUBCKT RM_IHPSG13_4096x8_c3_1P_ROWDEC6 ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ++ ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<63> WL_O<62> WL_O<61> WL_O<60> ++ WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> ++ WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> ++ WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> ++ WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> ++ WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> ++ WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> ++ WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> ++ WL_O<2> WL_O<1> WL_O<0> VDD VSS +XDEC11 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<3> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC03 +XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC00 +XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC01 +XDEC10 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<2> VDD VSS / ++ RM_IHPSG13_4096x8_c3_1P_DEC02 +XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> ++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> ++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> ++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_4096x8_c3_1P_DEC04 +XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> ++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> ++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> ++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_4096x8_c3_1P_DEC04 +XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> ++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> ++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> ++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_4096x8_c3_1P_DEC04 +XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I ++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> ++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> ++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_4096x8_c3_1P_DEC04 +XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS +.SUBCKT RM_IHPSG13_4096x8_c3_1P_ROWREG6 ACLK_N_I ADDR_I<5> ADDR_I<4> ADDR_I<3> ADDR_I<2> ++ ADDR_I<1> ADDR_I<0> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ++ ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> ++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS +XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2 +XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2 +XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8 +XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8 +XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<0> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<1> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<2> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<3> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<4> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<5> VDD ++ VSS / RSC_IHPSG13_DFNQMX2IX1 +XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8 +XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8 +.ENDS + + +.SUBCKT RM_IHPSG13_4096x8_c3_1P_COLUMN_pcell_0 A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<511> A_LWL<510> A_LWL<509> A_LWL<508> A_LWL<507> A_LWL<506> A_LWL<505> A_LWL<504> A_LWL<503> A_LWL<502> A_LWL<501> A_LWL<500> A_LWL<499> A_LWL<498> A_LWL<497> A_LWL<496> A_LWL<495> A_LWL<494> A_LWL<493> A_LWL<492> A_LWL<491> A_LWL<490> A_LWL<489> A_LWL<488> A_LWL<487> A_LWL<486> A_LWL<485> A_LWL<484> A_LWL<483> A_LWL<482> A_LWL<481> A_LWL<480> A_LWL<479> A_LWL<478> A_LWL<477> A_LWL<476> A_LWL<475> A_LWL<474> A_LWL<473> A_LWL<472> A_LWL<471> A_LWL<470> A_LWL<469> A_LWL<468> A_LWL<467> A_LWL<466> A_LWL<465> A_LWL<464> A_LWL<463> A_LWL<462> A_LWL<461> A_LWL<460> A_LWL<459> A_LWL<458> A_LWL<457> A_LWL<456> A_LWL<455> A_LWL<454> A_LWL<453> A_LWL<452> A_LWL<451> A_LWL<450> A_LWL<449> A_LWL<448> A_LWL<447> A_LWL<446> A_LWL<445> A_LWL<444> A_LWL<443> A_LWL<442> A_LWL<441> A_LWL<440> A_LWL<439> A_LWL<438> A_LWL<437> A_LWL<436> A_LWL<435> A_LWL<434> A_LWL<433> A_LWL<432> A_LWL<431> A_LWL<430> A_LWL<429> A_LWL<428> A_LWL<427> A_LWL<426> A_LWL<425> A_LWL<424> A_LWL<423> A_LWL<422> A_LWL<421> A_LWL<420> A_LWL<419> A_LWL<418> A_LWL<417> A_LWL<416> A_LWL<415> A_LWL<414> A_LWL<413> A_LWL<412> A_LWL<411> A_LWL<410> A_LWL<409> A_LWL<408> A_LWL<407> A_LWL<406> A_LWL<405> A_LWL<404> A_LWL<403> A_LWL<402> A_LWL<401> A_LWL<400> A_LWL<399> A_LWL<398> A_LWL<397> A_LWL<396> A_LWL<395> A_LWL<394> A_LWL<393> A_LWL<392> A_LWL<391> A_LWL<390> A_LWL<389> A_LWL<388> A_LWL<387> A_LWL<386> A_LWL<385> A_LWL<384> A_LWL<383> A_LWL<382> A_LWL<381> A_LWL<380> A_LWL<379> A_LWL<378> A_LWL<377> A_LWL<376> A_LWL<375> A_LWL<374> A_LWL<373> A_LWL<372> A_LWL<371> A_LWL<370> A_LWL<369> A_LWL<368> A_LWL<367> A_LWL<366> A_LWL<365> A_LWL<364> A_LWL<363> A_LWL<362> A_LWL<361> A_LWL<360> A_LWL<359> A_LWL<358> A_LWL<357> A_LWL<356> A_LWL<355> A_LWL<354> A_LWL<353> A_LWL<352> A_LWL<351> A_LWL<350> A_LWL<349> A_LWL<348> A_LWL<347> A_LWL<346> A_LWL<345> A_LWL<344> A_LWL<343> A_LWL<342> A_LWL<341> A_LWL<340> A_LWL<339> A_LWL<338> A_LWL<337> A_LWL<336> A_LWL<335> A_LWL<334> A_LWL<333> A_LWL<332> A_LWL<331> A_LWL<330> A_LWL<329> A_LWL<328> A_LWL<327> A_LWL<326> A_LWL<325> A_LWL<324> A_LWL<323> A_LWL<322> A_LWL<321> A_LWL<320> A_LWL<319> A_LWL<318> A_LWL<317> A_LWL<316> A_LWL<315> A_LWL<314> A_LWL<313> A_LWL<312> A_LWL<311> A_LWL<310> A_LWL<309> A_LWL<308> A_LWL<307> A_LWL<306> A_LWL<305> A_LWL<304> A_LWL<303> A_LWL<302> A_LWL<301> A_LWL<300> A_LWL<299> A_LWL<298> A_LWL<297> A_LWL<296> A_LWL<295> A_LWL<294> A_LWL<293> A_LWL<292> A_LWL<291> A_LWL<290> A_LWL<289> A_LWL<288> A_LWL<287> A_LWL<286> A_LWL<285> A_LWL<284> A_LWL<283> A_LWL<282> A_LWL<281> A_LWL<280> A_LWL<279> A_LWL<278> A_LWL<277> A_LWL<276> A_LWL<275> A_LWL<274> A_LWL<273> A_LWL<272> A_LWL<271> A_LWL<270> A_LWL<269> A_LWL<268> A_LWL<267> A_LWL<266> A_LWL<265> A_LWL<264> A_LWL<263> A_LWL<262> A_LWL<261> A_LWL<260> A_LWL<259> A_LWL<258> A_LWL<257> A_LWL<256> A_LWL<255> A_LWL<254> A_LWL<253> A_LWL<252> A_LWL<251> A_LWL<250> A_LWL<249> A_LWL<248> A_LWL<247> A_LWL<246> A_LWL<245> A_LWL<244> A_LWL<243> A_LWL<242> A_LWL<241> A_LWL<240> A_LWL<239> A_LWL<238> A_LWL<237> A_LWL<236> A_LWL<235> A_LWL<234> A_LWL<233> A_LWL<232> A_LWL<231> A_LWL<230> A_LWL<229> A_LWL<228> A_LWL<227> A_LWL<226> A_LWL<225> A_LWL<224> A_LWL<223> A_LWL<222> A_LWL<221> A_LWL<220> A_LWL<219> A_LWL<218> A_LWL<217> A_LWL<216> A_LWL<215> A_LWL<214> A_LWL<213> A_LWL<212> A_LWL<211> A_LWL<210> A_LWL<209> A_LWL<208> A_LWL<207> A_LWL<206> A_LWL<205> A_LWL<204> A_LWL<203> A_LWL<202> A_LWL<201> A_LWL<200> A_LWL<199> A_LWL<198> A_LWL<197> A_LWL<196> A_LWL<195> A_LWL<194> A_LWL<193> A_LWL<192> A_LWL<191> A_LWL<190> A_LWL<189> A_LWL<188> A_LWL<187> A_LWL<186> A_LWL<185> A_LWL<184> A_LWL<183> A_LWL<182> A_LWL<181> A_LWL<180> A_LWL<179> A_LWL<178> A_LWL<177> A_LWL<176> A_LWL<175> A_LWL<174> A_LWL<173> A_LWL<172> A_LWL<171> A_LWL<170> A_LWL<169> A_LWL<168> A_LWL<167> A_LWL<166> A_LWL<165> A_LWL<164> A_LWL<163> A_LWL<162> A_LWL<161> A_LWL<160> A_LWL<159> A_LWL<158> A_LWL<157> A_LWL<156> A_LWL<155> A_LWL<154> A_LWL<153> A_LWL<152> A_LWL<151> A_LWL<150> A_LWL<149> A_LWL<148> A_LWL<147> A_LWL<146> A_LWL<145> A_LWL<144> A_LWL<143> A_LWL<142> A_LWL<141> A_LWL<140> A_LWL<139> A_LWL<138> A_LWL<137> A_LWL<136> A_LWL<135> A_LWL<134> A_LWL<133> A_LWL<132> A_LWL<131> A_LWL<130> A_LWL<129> A_LWL<128> A_LWL<127> A_LWL<126> A_LWL<125> A_LWL<124> A_LWL<123> A_LWL<122> A_LWL<121> A_LWL<120> A_LWL<119> A_LWL<118> A_LWL<117> A_LWL<116> A_LWL<115> A_LWL<114> A_LWL<113> A_LWL<112> A_LWL<111> A_LWL<110> A_LWL<109> A_LWL<108> A_LWL<107> A_LWL<106> A_LWL<105> A_LWL<104> A_LWL<103> A_LWL<102> A_LWL<101> A_LWL<100> A_LWL<99> A_LWL<98> A_LWL<97> A_LWL<96> A_LWL<95> A_LWL<94> A_LWL<93> A_LWL<92> A_LWL<91> A_LWL<90> A_LWL<89> A_LWL<88> A_LWL<87> A_LWL<86> A_LWL<85> A_LWL<84> A_LWL<83> A_LWL<82> A_LWL<81> A_LWL<80> A_LWL<79> A_LWL<78> A_LWL<77> A_LWL<76> A_LWL<75> A_LWL<74> A_LWL<73> A_LWL<72> A_LWL<71> A_LWL<70> A_LWL<69> A_LWL<68> A_LWL<67> A_LWL<66> A_LWL<65> A_LWL<64> A_LWL<63> A_LWL<62> A_LWL<61> A_LWL<60> A_LWL<59> A_LWL<58> A_LWL<57> A_LWL<56> A_LWL<55> A_LWL<54> A_LWL<53> A_LWL<52> A_LWL<51> A_LWL<50> A_LWL<49> A_LWL<48> A_LWL<47> A_LWL<46> A_LWL<45> A_LWL<44> A_LWL<43> A_LWL<42> A_LWL<41> A_LWL<40> A_LWL<39> A_LWL<38> A_LWL<37> A_LWL<36> A_LWL<35> A_LWL<34> A_LWL<33> A_LWL<32> A_LWL<31> A_LWL<30> A_LWL<29> A_LWL<28> A_LWL<27> A_LWL<26> A_LWL<25> A_LWL<24> A_LWL<23> A_LWL<22> A_LWL<21> A_LWL<20> A_LWL<19> A_LWL<18> A_LWL<17> A_LWL<16> A_LWL<15> A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<511> A_RWL<510> A_RWL<509> A_RWL<508> A_RWL<507> A_RWL<506> A_RWL<505> A_RWL<504> A_RWL<503> A_RWL<502> A_RWL<501> A_RWL<500> A_RWL<499> A_RWL<498> A_RWL<497> A_RWL<496> A_RWL<495> A_RWL<494> A_RWL<493> A_RWL<492> A_RWL<491> A_RWL<490> A_RWL<489> A_RWL<488> A_RWL<487> A_RWL<486> A_RWL<485> A_RWL<484> A_RWL<483> A_RWL<482> A_RWL<481> A_RWL<480> A_RWL<479> A_RWL<478> A_RWL<477> A_RWL<476> A_RWL<475> A_RWL<474> A_RWL<473> A_RWL<472> A_RWL<471> A_RWL<470> A_RWL<469> A_RWL<468> A_RWL<467> A_RWL<466> A_RWL<465> A_RWL<464> A_RWL<463> A_RWL<462> A_RWL<461> A_RWL<460> A_RWL<459> A_RWL<458> A_RWL<457> A_RWL<456> A_RWL<455> A_RWL<454> A_RWL<453> A_RWL<452> A_RWL<451> A_RWL<450> A_RWL<449> A_RWL<448> A_RWL<447> A_RWL<446> A_RWL<445> A_RWL<444> A_RWL<443> A_RWL<442> A_RWL<441> A_RWL<440> A_RWL<439> A_RWL<438> A_RWL<437> A_RWL<436> A_RWL<435> A_RWL<434> A_RWL<433> A_RWL<432> A_RWL<431> A_RWL<430> A_RWL<429> A_RWL<428> A_RWL<427> A_RWL<426> A_RWL<425> A_RWL<424> A_RWL<423> A_RWL<422> A_RWL<421> A_RWL<420> A_RWL<419> A_RWL<418> A_RWL<417> A_RWL<416> A_RWL<415> A_RWL<414> A_RWL<413> A_RWL<412> A_RWL<411> A_RWL<410> A_RWL<409> A_RWL<408> A_RWL<407> A_RWL<406> A_RWL<405> A_RWL<404> A_RWL<403> A_RWL<402> A_RWL<401> A_RWL<400> A_RWL<399> A_RWL<398> A_RWL<397> A_RWL<396> A_RWL<395> A_RWL<394> A_RWL<393> A_RWL<392> A_RWL<391> A_RWL<390> A_RWL<389> A_RWL<388> A_RWL<387> A_RWL<386> A_RWL<385> A_RWL<384> A_RWL<383> A_RWL<382> A_RWL<381> A_RWL<380> A_RWL<379> A_RWL<378> A_RWL<377> A_RWL<376> A_RWL<375> A_RWL<374> A_RWL<373> A_RWL<372> A_RWL<371> A_RWL<370> A_RWL<369> A_RWL<368> A_RWL<367> A_RWL<366> A_RWL<365> A_RWL<364> A_RWL<363> A_RWL<362> A_RWL<361> A_RWL<360> A_RWL<359> A_RWL<358> A_RWL<357> A_RWL<356> A_RWL<355> A_RWL<354> A_RWL<353> A_RWL<352> A_RWL<351> A_RWL<350> A_RWL<349> A_RWL<348> A_RWL<347> A_RWL<346> A_RWL<345> A_RWL<344> A_RWL<343> A_RWL<342> A_RWL<341> A_RWL<340> A_RWL<339> A_RWL<338> A_RWL<337> A_RWL<336> A_RWL<335> A_RWL<334> A_RWL<333> A_RWL<332> A_RWL<331> A_RWL<330> A_RWL<329> A_RWL<328> A_RWL<327> A_RWL<326> A_RWL<325> A_RWL<324> A_RWL<323> A_RWL<322> A_RWL<321> A_RWL<320> A_RWL<319> A_RWL<318> A_RWL<317> A_RWL<316> A_RWL<315> A_RWL<314> A_RWL<313> A_RWL<312> A_RWL<311> A_RWL<310> A_RWL<309> A_RWL<308> A_RWL<307> A_RWL<306> A_RWL<305> A_RWL<304> A_RWL<303> A_RWL<302> A_RWL<301> A_RWL<300> A_RWL<299> A_RWL<298> A_RWL<297> A_RWL<296> A_RWL<295> A_RWL<294> A_RWL<293> A_RWL<292> A_RWL<291> A_RWL<290> A_RWL<289> A_RWL<288> A_RWL<287> A_RWL<286> A_RWL<285> A_RWL<284> A_RWL<283> A_RWL<282> A_RWL<281> A_RWL<280> A_RWL<279> A_RWL<278> A_RWL<277> A_RWL<276> A_RWL<275> A_RWL<274> A_RWL<273> A_RWL<272> A_RWL<271> A_RWL<270> A_RWL<269> A_RWL<268> A_RWL<267> A_RWL<266> A_RWL<265> A_RWL<264> A_RWL<263> A_RWL<262> A_RWL<261> A_RWL<260> A_RWL<259> A_RWL<258> A_RWL<257> A_RWL<256> A_RWL<255> A_RWL<254> A_RWL<253> A_RWL<252> A_RWL<251> A_RWL<250> A_RWL<249> A_RWL<248> A_RWL<247> A_RWL<246> A_RWL<245> A_RWL<244> A_RWL<243> A_RWL<242> A_RWL<241> A_RWL<240> A_RWL<239> A_RWL<238> A_RWL<237> A_RWL<236> A_RWL<235> A_RWL<234> A_RWL<233> A_RWL<232> A_RWL<231> A_RWL<230> A_RWL<229> A_RWL<228> A_RWL<227> A_RWL<226> A_RWL<225> A_RWL<224> A_RWL<223> A_RWL<222> A_RWL<221> A_RWL<220> A_RWL<219> A_RWL<218> A_RWL<217> A_RWL<216> A_RWL<215> A_RWL<214> A_RWL<213> A_RWL<212> A_RWL<211> A_RWL<210> A_RWL<209> A_RWL<208> A_RWL<207> A_RWL<206> A_RWL<205> A_RWL<204> A_RWL<203> A_RWL<202> A_RWL<201> A_RWL<200> A_RWL<199> A_RWL<198> A_RWL<197> A_RWL<196> A_RWL<195> A_RWL<194> A_RWL<193> A_RWL<192> A_RWL<191> A_RWL<190> A_RWL<189> A_RWL<188> A_RWL<187> A_RWL<186> A_RWL<185> A_RWL<184> A_RWL<183> A_RWL<182> A_RWL<181> A_RWL<180> A_RWL<179> A_RWL<178> A_RWL<177> A_RWL<176> A_RWL<175> A_RWL<174> A_RWL<173> A_RWL<172> A_RWL<171> A_RWL<170> A_RWL<169> A_RWL<168> A_RWL<167> A_RWL<166> A_RWL<165> A_RWL<164> A_RWL<163> A_RWL<162> A_RWL<161> A_RWL<160> A_RWL<159> A_RWL<158> A_RWL<157> A_RWL<156> A_RWL<155> A_RWL<154> A_RWL<153> A_RWL<152> A_RWL<151> A_RWL<150> A_RWL<149> A_RWL<148> A_RWL<147> A_RWL<146> A_RWL<145> A_RWL<144> A_RWL<143> A_RWL<142> A_RWL<141> A_RWL<140> A_RWL<139> A_RWL<138> A_RWL<137> A_RWL<136> A_RWL<135> A_RWL<134> A_RWL<133> A_RWL<132> A_RWL<131> A_RWL<130> A_RWL<129> A_RWL<128> A_RWL<127> A_RWL<126> A_RWL<125> A_RWL<124> A_RWL<123> A_RWL<122> A_RWL<121> A_RWL<120> A_RWL<119> A_RWL<118> A_RWL<117> A_RWL<116> A_RWL<115> A_RWL<114> A_RWL<113> A_RWL<112> A_RWL<111> A_RWL<110> A_RWL<109> A_RWL<108> A_RWL<107> A_RWL<106> A_RWL<105> A_RWL<104> A_RWL<103> A_RWL<102> A_RWL<101> A_RWL<100> A_RWL<99> A_RWL<98> A_RWL<97> A_RWL<96> A_RWL<95> A_RWL<94> A_RWL<93> A_RWL<92> A_RWL<91> A_RWL<90> A_RWL<89> A_RWL<88> A_RWL<87> A_RWL<86> A_RWL<85> A_RWL<84> A_RWL<83> A_RWL<82> A_RWL<81> A_RWL<80> A_RWL<79> A_RWL<78> A_RWL<77> A_RWL<76> A_RWL<75> A_RWL<74> A_RWL<73> A_RWL<72> A_RWL<71> A_RWL<70> A_RWL<69> A_RWL<68> A_RWL<67> A_RWL<66> A_RWL<65> A_RWL<64> A_RWL<63> A_RWL<62> A_RWL<61> A_RWL<60> A_RWL<59> A_RWL<58> A_RWL<57> A_RWL<56> A_RWL<55> A_RWL<54> A_RWL<53> A_RWL<52> A_RWL<51> A_RWL<50> A_RWL<49> A_RWL<48> A_RWL<47> A_RWL<46> A_RWL<45> A_RWL<44> A_RWL<43> A_RWL<42> A_RWL<41> A_RWL<40> A_RWL<39> A_RWL<38> A_RWL<37> A_RWL<36> A_RWL<35> A_RWL<34> A_RWL<33> A_RWL<32> A_RWL<31> A_RWL<30> A_RWL<29> A_RWL<28> A_RWL<27> A_RWL<26> A_RWL<25> A_RWL<24> A_RWL<23> A_RWL<22> A_RWL<21> A_RWL<20> A_RWL<19> A_RWL<18> A_RWL<17> A_RWL<16> A_RWL<15> A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> VDD_CORE VSS +XRAM<32> A_BLC<61> A_BLC<60> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT<61> A_BLT<60> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<511> A_LWL<510> A_LWL<509> A_LWL<508> A_LWL<507> A_LWL<506> A_LWL<505> A_LWL<504> A_LWL<503> A_LWL<502> A_LWL<501> A_LWL<500> A_LWL<499> A_LWL<498> A_LWL<497> A_LWL<496> A_RWL<511> A_RWL<510> A_RWL<509> A_RWL<508> A_RWL<507> A_RWL<506> A_RWL<505> A_RWL<504> A_RWL<503> A_RWL<502> A_RWL<501> A_RWL<500> A_RWL<499> A_RWL<498> A_RWL<497> A_RWL<496> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_SRAM +XRAM<31> A_BLC<59> A_BLC<58> A_BLC<61> A_BLC<60> A_BLT<59> A_BLT<58> A_BLT<61> A_BLT<60> A_LWL<495> A_LWL<494> A_LWL<493> A_LWL<492> A_LWL<491> A_LWL<490> A_LWL<489> A_LWL<488> A_LWL<487> A_LWL<486> A_LWL<485> A_LWL<484> A_LWL<483> A_LWL<482> A_LWL<481> A_LWL<480> A_RWL<495> A_RWL<494> A_RWL<493> A_RWL<492> A_RWL<491> A_RWL<490> A_RWL<489> A_RWL<488> A_RWL<487> A_RWL<486> A_RWL<485> A_RWL<484> A_RWL<483> A_RWL<482> A_RWL<481> A_RWL<480> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_SRAM +XRAM<30> A_BLC<57> A_BLC<56> A_BLC<59> A_BLC<58> A_BLT<57> A_BLT<56> A_BLT<59> A_BLT<58> A_LWL<479> A_LWL<478> A_LWL<477> A_LWL<476> A_LWL<475> A_LWL<474> A_LWL<473> A_LWL<472> A_LWL<471> A_LWL<470> A_LWL<469> A_LWL<468> A_LWL<467> A_LWL<466> A_LWL<465> A_LWL<464> A_RWL<479> A_RWL<478> A_RWL<477> A_RWL<476> A_RWL<475> A_RWL<474> A_RWL<473> A_RWL<472> A_RWL<471> A_RWL<470> A_RWL<469> A_RWL<468> A_RWL<467> A_RWL<466> A_RWL<465> A_RWL<464> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_SRAM +XRAM<29> A_BLC<55> A_BLC<54> A_BLC<57> A_BLC<56> A_BLT<55> A_BLT<54> A_BLT<57> A_BLT<56> A_LWL<463> A_LWL<462> A_LWL<461> A_LWL<460> A_LWL<459> A_LWL<458> A_LWL<457> A_LWL<456> A_LWL<455> A_LWL<454> A_LWL<453> A_LWL<452> A_LWL<451> A_LWL<450> A_LWL<449> A_LWL<448> A_RWL<463> A_RWL<462> A_RWL<461> A_RWL<460> A_RWL<459> A_RWL<458> A_RWL<457> A_RWL<456> A_RWL<455> A_RWL<454> A_RWL<453> A_RWL<452> A_RWL<451> A_RWL<450> A_RWL<449> A_RWL<448> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_SRAM +XRAM<28> A_BLC<53> A_BLC<52> A_BLC<55> A_BLC<54> A_BLT<53> A_BLT<52> A_BLT<55> A_BLT<54> A_LWL<447> A_LWL<446> A_LWL<445> A_LWL<444> A_LWL<443> A_LWL<442> A_LWL<441> A_LWL<440> A_LWL<439> A_LWL<438> A_LWL<437> A_LWL<436> A_LWL<435> A_LWL<434> A_LWL<433> A_LWL<432> A_RWL<447> A_RWL<446> A_RWL<445> A_RWL<444> A_RWL<443> A_RWL<442> A_RWL<441> A_RWL<440> A_RWL<439> A_RWL<438> A_RWL<437> A_RWL<436> A_RWL<435> A_RWL<434> A_RWL<433> A_RWL<432> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_SRAM +XRAM<27> A_BLC<51> A_BLC<50> A_BLC<53> A_BLC<52> A_BLT<51> A_BLT<50> A_BLT<53> A_BLT<52> A_LWL<431> A_LWL<430> A_LWL<429> A_LWL<428> A_LWL<427> A_LWL<426> A_LWL<425> A_LWL<424> A_LWL<423> A_LWL<422> A_LWL<421> A_LWL<420> A_LWL<419> A_LWL<418> A_LWL<417> A_LWL<416> A_RWL<431> A_RWL<430> A_RWL<429> A_RWL<428> A_RWL<427> A_RWL<426> A_RWL<425> A_RWL<424> A_RWL<423> A_RWL<422> A_RWL<421> A_RWL<420> A_RWL<419> A_RWL<418> A_RWL<417> A_RWL<416> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_SRAM +XRAM<26> A_BLC<49> A_BLC<48> A_BLC<51> A_BLC<50> A_BLT<49> A_BLT<48> A_BLT<51> A_BLT<50> A_LWL<415> A_LWL<414> A_LWL<413> A_LWL<412> A_LWL<411> A_LWL<410> A_LWL<409> A_LWL<408> A_LWL<407> A_LWL<406> A_LWL<405> A_LWL<404> A_LWL<403> A_LWL<402> A_LWL<401> A_LWL<400> A_RWL<415> A_RWL<414> A_RWL<413> A_RWL<412> A_RWL<411> A_RWL<410> A_RWL<409> A_RWL<408> A_RWL<407> A_RWL<406> A_RWL<405> A_RWL<404> A_RWL<403> A_RWL<402> A_RWL<401> A_RWL<400> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_SRAM +XRAM<25> A_BLC<47> A_BLC<46> A_BLC<49> A_BLC<48> A_BLT<47> A_BLT<46> A_BLT<49> A_BLT<48> A_LWL<399> A_LWL<398> A_LWL<397> A_LWL<396> A_LWL<395> A_LWL<394> A_LWL<393> A_LWL<392> A_LWL<391> A_LWL<390> A_LWL<389> A_LWL<388> A_LWL<387> A_LWL<386> A_LWL<385> A_LWL<384> A_RWL<399> A_RWL<398> A_RWL<397> A_RWL<396> A_RWL<395> A_RWL<394> A_RWL<393> A_RWL<392> A_RWL<391> A_RWL<390> A_RWL<389> A_RWL<388> A_RWL<387> A_RWL<386> A_RWL<385> A_RWL<384> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_SRAM +XRAM<24> A_BLC<45> A_BLC<44> A_BLC<47> A_BLC<46> A_BLT<45> A_BLT<44> A_BLT<47> A_BLT<46> A_LWL<383> A_LWL<382> A_LWL<381> A_LWL<380> A_LWL<379> A_LWL<378> A_LWL<377> A_LWL<376> A_LWL<375> A_LWL<374> A_LWL<373> A_LWL<372> A_LWL<371> A_LWL<370> A_LWL<369> A_LWL<368> A_RWL<383> A_RWL<382> A_RWL<381> A_RWL<380> A_RWL<379> A_RWL<378> A_RWL<377> A_RWL<376> A_RWL<375> A_RWL<374> A_RWL<373> A_RWL<372> A_RWL<371> A_RWL<370> A_RWL<369> A_RWL<368> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_SRAM +XRAM<23> A_BLC<43> A_BLC<42> A_BLC<45> A_BLC<44> A_BLT<43> A_BLT<42> A_BLT<45> A_BLT<44> A_LWL<367> A_LWL<366> A_LWL<365> A_LWL<364> A_LWL<363> A_LWL<362> A_LWL<361> A_LWL<360> A_LWL<359> A_LWL<358> A_LWL<357> A_LWL<356> A_LWL<355> A_LWL<354> A_LWL<353> A_LWL<352> A_RWL<367> A_RWL<366> A_RWL<365> A_RWL<364> A_RWL<363> A_RWL<362> A_RWL<361> A_RWL<360> A_RWL<359> A_RWL<358> A_RWL<357> A_RWL<356> A_RWL<355> A_RWL<354> A_RWL<353> A_RWL<352> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_SRAM +XRAM<22> A_BLC<41> A_BLC<40> A_BLC<43> A_BLC<42> A_BLT<41> A_BLT<40> A_BLT<43> A_BLT<42> A_LWL<351> A_LWL<350> A_LWL<349> A_LWL<348> A_LWL<347> A_LWL<346> A_LWL<345> A_LWL<344> A_LWL<343> A_LWL<342> A_LWL<341> A_LWL<340> A_LWL<339> A_LWL<338> A_LWL<337> A_LWL<336> A_RWL<351> A_RWL<350> A_RWL<349> A_RWL<348> A_RWL<347> A_RWL<346> A_RWL<345> A_RWL<344> A_RWL<343> A_RWL<342> A_RWL<341> A_RWL<340> A_RWL<339> A_RWL<338> A_RWL<337> A_RWL<336> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_SRAM +XRAM<21> A_BLC<39> A_BLC<38> A_BLC<41> A_BLC<40> A_BLT<39> A_BLT<38> A_BLT<41> A_BLT<40> A_LWL<335> A_LWL<334> A_LWL<333> A_LWL<332> A_LWL<331> A_LWL<330> A_LWL<329> A_LWL<328> A_LWL<327> A_LWL<326> A_LWL<325> A_LWL<324> A_LWL<323> A_LWL<322> A_LWL<321> A_LWL<320> A_RWL<335> A_RWL<334> A_RWL<333> A_RWL<332> A_RWL<331> A_RWL<330> A_RWL<329> A_RWL<328> A_RWL<327> A_RWL<326> A_RWL<325> A_RWL<324> A_RWL<323> A_RWL<322> A_RWL<321> A_RWL<320> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_SRAM +XRAM<20> A_BLC<37> A_BLC<36> A_BLC<39> A_BLC<38> A_BLT<37> A_BLT<36> A_BLT<39> A_BLT<38> A_LWL<319> A_LWL<318> A_LWL<317> A_LWL<316> A_LWL<315> A_LWL<314> A_LWL<313> A_LWL<312> A_LWL<311> A_LWL<310> A_LWL<309> A_LWL<308> A_LWL<307> A_LWL<306> A_LWL<305> A_LWL<304> A_RWL<319> A_RWL<318> A_RWL<317> A_RWL<316> A_RWL<315> A_RWL<314> A_RWL<313> A_RWL<312> A_RWL<311> A_RWL<310> A_RWL<309> A_RWL<308> A_RWL<307> A_RWL<306> A_RWL<305> A_RWL<304> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_SRAM +XRAM<19> A_BLC<35> A_BLC<34> A_BLC<37> A_BLC<36> A_BLT<35> A_BLT<34> A_BLT<37> A_BLT<36> A_LWL<303> A_LWL<302> A_LWL<301> A_LWL<300> A_LWL<299> A_LWL<298> A_LWL<297> A_LWL<296> A_LWL<295> A_LWL<294> A_LWL<293> A_LWL<292> A_LWL<291> A_LWL<290> A_LWL<289> A_LWL<288> A_RWL<303> A_RWL<302> A_RWL<301> A_RWL<300> A_RWL<299> A_RWL<298> A_RWL<297> A_RWL<296> A_RWL<295> A_RWL<294> A_RWL<293> A_RWL<292> A_RWL<291> A_RWL<290> A_RWL<289> A_RWL<288> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_SRAM +XRAM<18> A_BLC<33> A_BLC<32> A_BLC<35> A_BLC<34> A_BLT<33> A_BLT<32> A_BLT<35> A_BLT<34> A_LWL<287> A_LWL<286> A_LWL<285> A_LWL<284> A_LWL<283> A_LWL<282> A_LWL<281> A_LWL<280> A_LWL<279> A_LWL<278> A_LWL<277> A_LWL<276> A_LWL<275> A_LWL<274> A_LWL<273> A_LWL<272> A_RWL<287> A_RWL<286> A_RWL<285> A_RWL<284> A_RWL<283> A_RWL<282> A_RWL<281> A_RWL<280> A_RWL<279> A_RWL<278> A_RWL<277> A_RWL<276> A_RWL<275> A_RWL<274> A_RWL<273> A_RWL<272> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_SRAM +XRAM<17> A_BLC<31> A_BLC<30> A_BLC<33> A_BLC<32> A_BLT<31> A_BLT<30> A_BLT<33> A_BLT<32> A_LWL<271> A_LWL<270> A_LWL<269> A_LWL<268> A_LWL<267> A_LWL<266> A_LWL<265> A_LWL<264> A_LWL<263> A_LWL<262> A_LWL<261> A_LWL<260> A_LWL<259> A_LWL<258> A_LWL<257> A_LWL<256> A_RWL<271> A_RWL<270> A_RWL<269> A_RWL<268> A_RWL<267> A_RWL<266> A_RWL<265> A_RWL<264> A_RWL<263> A_RWL<262> A_RWL<261> A_RWL<260> A_RWL<259> A_RWL<258> A_RWL<257> A_RWL<256> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_SRAM +XRAM<16> A_BLC<29> A_BLC<28> A_BLC<31> A_BLC<30> A_BLT<29> A_BLT<28> A_BLT<31> A_BLT<30> A_LWL<255> A_LWL<254> A_LWL<253> A_LWL<252> A_LWL<251> A_LWL<250> A_LWL<249> A_LWL<248> A_LWL<247> A_LWL<246> A_LWL<245> A_LWL<244> A_LWL<243> A_LWL<242> A_LWL<241> A_LWL<240> A_RWL<255> A_RWL<254> A_RWL<253> A_RWL<252> A_RWL<251> A_RWL<250> A_RWL<249> A_RWL<248> A_RWL<247> A_RWL<246> A_RWL<245> A_RWL<244> A_RWL<243> A_RWL<242> A_RWL<241> A_RWL<240> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_SRAM +XRAM<15> A_BLC<27> A_BLC<26> A_BLC<29> A_BLC<28> A_BLT<27> A_BLT<26> A_BLT<29> A_BLT<28> A_LWL<239> A_LWL<238> A_LWL<237> A_LWL<236> A_LWL<235> A_LWL<234> A_LWL<233> A_LWL<232> A_LWL<231> A_LWL<230> A_LWL<229> A_LWL<228> A_LWL<227> A_LWL<226> A_LWL<225> A_LWL<224> A_RWL<239> A_RWL<238> A_RWL<237> A_RWL<236> A_RWL<235> A_RWL<234> A_RWL<233> A_RWL<232> A_RWL<231> A_RWL<230> A_RWL<229> A_RWL<228> A_RWL<227> A_RWL<226> A_RWL<225> A_RWL<224> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_SRAM +XRAM<14> A_BLC<25> A_BLC<24> A_BLC<27> A_BLC<26> A_BLT<25> A_BLT<24> A_BLT<27> A_BLT<26> A_LWL<223> A_LWL<222> A_LWL<221> A_LWL<220> A_LWL<219> A_LWL<218> A_LWL<217> A_LWL<216> A_LWL<215> A_LWL<214> A_LWL<213> A_LWL<212> A_LWL<211> A_LWL<210> A_LWL<209> A_LWL<208> A_RWL<223> A_RWL<222> A_RWL<221> A_RWL<220> A_RWL<219> A_RWL<218> A_RWL<217> A_RWL<216> A_RWL<215> A_RWL<214> A_RWL<213> A_RWL<212> A_RWL<211> A_RWL<210> A_RWL<209> A_RWL<208> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_SRAM +XRAM<13> A_BLC<23> A_BLC<22> A_BLC<25> A_BLC<24> A_BLT<23> A_BLT<22> A_BLT<25> A_BLT<24> A_LWL<207> A_LWL<206> A_LWL<205> A_LWL<204> A_LWL<203> A_LWL<202> A_LWL<201> A_LWL<200> A_LWL<199> A_LWL<198> A_LWL<197> A_LWL<196> A_LWL<195> A_LWL<194> A_LWL<193> A_LWL<192> A_RWL<207> A_RWL<206> A_RWL<205> A_RWL<204> A_RWL<203> A_RWL<202> A_RWL<201> A_RWL<200> A_RWL<199> A_RWL<198> A_RWL<197> A_RWL<196> A_RWL<195> A_RWL<194> A_RWL<193> A_RWL<192> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_SRAM +XRAM<12> A_BLC<21> A_BLC<20> A_BLC<23> A_BLC<22> A_BLT<21> A_BLT<20> A_BLT<23> A_BLT<22> A_LWL<191> A_LWL<190> A_LWL<189> A_LWL<188> A_LWL<187> A_LWL<186> A_LWL<185> A_LWL<184> A_LWL<183> A_LWL<182> A_LWL<181> A_LWL<180> A_LWL<179> A_LWL<178> A_LWL<177> A_LWL<176> A_RWL<191> A_RWL<190> A_RWL<189> A_RWL<188> A_RWL<187> A_RWL<186> A_RWL<185> A_RWL<184> A_RWL<183> A_RWL<182> A_RWL<181> A_RWL<180> A_RWL<179> A_RWL<178> A_RWL<177> A_RWL<176> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_SRAM +XRAM<11> A_BLC<19> A_BLC<18> A_BLC<21> A_BLC<20> A_BLT<19> A_BLT<18> A_BLT<21> A_BLT<20> A_LWL<175> A_LWL<174> A_LWL<173> A_LWL<172> A_LWL<171> A_LWL<170> A_LWL<169> A_LWL<168> A_LWL<167> A_LWL<166> A_LWL<165> A_LWL<164> A_LWL<163> A_LWL<162> A_LWL<161> A_LWL<160> A_RWL<175> A_RWL<174> A_RWL<173> A_RWL<172> A_RWL<171> A_RWL<170> A_RWL<169> A_RWL<168> A_RWL<167> A_RWL<166> A_RWL<165> A_RWL<164> A_RWL<163> A_RWL<162> A_RWL<161> A_RWL<160> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_SRAM +XRAM<10> A_BLC<17> A_BLC<16> A_BLC<19> A_BLC<18> A_BLT<17> A_BLT<16> A_BLT<19> A_BLT<18> A_LWL<159> A_LWL<158> A_LWL<157> A_LWL<156> A_LWL<155> A_LWL<154> A_LWL<153> A_LWL<152> A_LWL<151> A_LWL<150> A_LWL<149> A_LWL<148> A_LWL<147> A_LWL<146> A_LWL<145> A_LWL<144> A_RWL<159> A_RWL<158> A_RWL<157> A_RWL<156> A_RWL<155> A_RWL<154> A_RWL<153> A_RWL<152> A_RWL<151> A_RWL<150> A_RWL<149> A_RWL<148> A_RWL<147> A_RWL<146> A_RWL<145> A_RWL<144> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_SRAM +XRAM<9> A_BLC<15> A_BLC<14> A_BLC<17> A_BLC<16> A_BLT<15> A_BLT<14> A_BLT<17> A_BLT<16> A_LWL<143> A_LWL<142> A_LWL<141> A_LWL<140> A_LWL<139> A_LWL<138> A_LWL<137> A_LWL<136> A_LWL<135> A_LWL<134> A_LWL<133> A_LWL<132> A_LWL<131> A_LWL<130> A_LWL<129> A_LWL<128> A_RWL<143> A_RWL<142> A_RWL<141> A_RWL<140> A_RWL<139> A_RWL<138> A_RWL<137> A_RWL<136> A_RWL<135> A_RWL<134> A_RWL<133> A_RWL<132> A_RWL<131> A_RWL<130> A_RWL<129> A_RWL<128> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_SRAM +XRAM<8> A_BLC<13> A_BLC<12> A_BLC<15> A_BLC<14> A_BLT<13> A_BLT<12> A_BLT<15> A_BLT<14> A_LWL<127> A_LWL<126> A_LWL<125> A_LWL<124> A_LWL<123> A_LWL<122> A_LWL<121> A_LWL<120> A_LWL<119> A_LWL<118> A_LWL<117> A_LWL<116> A_LWL<115> A_LWL<114> A_LWL<113> A_LWL<112> A_RWL<127> A_RWL<126> A_RWL<125> A_RWL<124> A_RWL<123> A_RWL<122> A_RWL<121> A_RWL<120> A_RWL<119> A_RWL<118> A_RWL<117> A_RWL<116> A_RWL<115> A_RWL<114> A_RWL<113> A_RWL<112> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_SRAM +XRAM<7> A_BLC<11> A_BLC<10> A_BLC<13> A_BLC<12> A_BLT<11> A_BLT<10> A_BLT<13> A_BLT<12> A_LWL<111> A_LWL<110> A_LWL<109> A_LWL<108> A_LWL<107> A_LWL<106> A_LWL<105> A_LWL<104> A_LWL<103> A_LWL<102> A_LWL<101> A_LWL<100> A_LWL<99> A_LWL<98> A_LWL<97> A_LWL<96> A_RWL<111> A_RWL<110> A_RWL<109> A_RWL<108> A_RWL<107> A_RWL<106> A_RWL<105> A_RWL<104> A_RWL<103> A_RWL<102> A_RWL<101> A_RWL<100> A_RWL<99> A_RWL<98> A_RWL<97> A_RWL<96> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_SRAM +XRAM<6> A_BLC<9> A_BLC<8> A_BLC<11> A_BLC<10> A_BLT<9> A_BLT<8> A_BLT<11> A_BLT<10> A_LWL<95> A_LWL<94> A_LWL<93> A_LWL<92> A_LWL<91> A_LWL<90> A_LWL<89> A_LWL<88> A_LWL<87> A_LWL<86> A_LWL<85> A_LWL<84> A_LWL<83> A_LWL<82> A_LWL<81> A_LWL<80> A_RWL<95> A_RWL<94> A_RWL<93> A_RWL<92> A_RWL<91> A_RWL<90> A_RWL<89> A_RWL<88> A_RWL<87> A_RWL<86> A_RWL<85> A_RWL<84> A_RWL<83> A_RWL<82> A_RWL<81> A_RWL<80> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_SRAM +XRAM<5> A_BLC<7> A_BLC<6> A_BLC<9> A_BLC<8> A_BLT<7> A_BLT<6> A_BLT<9> A_BLT<8> A_LWL<79> A_LWL<78> A_LWL<77> A_LWL<76> A_LWL<75> A_LWL<74> A_LWL<73> A_LWL<72> A_LWL<71> A_LWL<70> A_LWL<69> A_LWL<68> A_LWL<67> A_LWL<66> A_LWL<65> A_LWL<64> A_RWL<79> A_RWL<78> A_RWL<77> A_RWL<76> A_RWL<75> A_RWL<74> A_RWL<73> A_RWL<72> A_RWL<71> A_RWL<70> A_RWL<69> A_RWL<68> A_RWL<67> A_RWL<66> A_RWL<65> A_RWL<64> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_SRAM +XRAM<4> A_BLC<5> A_BLC<4> A_BLC<7> A_BLC<6> A_BLT<5> A_BLT<4> A_BLT<7> A_BLT<6> A_LWL<63> A_LWL<62> A_LWL<61> A_LWL<60> A_LWL<59> A_LWL<58> A_LWL<57> A_LWL<56> A_LWL<55> A_LWL<54> A_LWL<53> A_LWL<52> A_LWL<51> A_LWL<50> A_LWL<49> A_LWL<48> A_RWL<63> A_RWL<62> A_RWL<61> A_RWL<60> A_RWL<59> A_RWL<58> A_RWL<57> A_RWL<56> A_RWL<55> A_RWL<54> A_RWL<53> A_RWL<52> A_RWL<51> A_RWL<50> A_RWL<49> A_RWL<48> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_SRAM +XRAM<3> A_BLC<3> A_BLC<2> A_BLC<5> A_BLC<4> A_BLT<3> A_BLT<2> A_BLT<5> A_BLT<4> A_LWL<47> A_LWL<46> A_LWL<45> A_LWL<44> A_LWL<43> A_LWL<42> A_LWL<41> A_LWL<40> A_LWL<39> A_LWL<38> A_LWL<37> A_LWL<36> A_LWL<35> A_LWL<34> A_LWL<33> A_LWL<32> A_RWL<47> A_RWL<46> A_RWL<45> A_RWL<44> A_RWL<43> A_RWL<42> A_RWL<41> A_RWL<40> A_RWL<39> A_RWL<38> A_RWL<37> A_RWL<36> A_RWL<35> A_RWL<34> A_RWL<33> A_RWL<32> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_SRAM +XRAM<2> A_BLC<1> A_BLC<0> A_BLC<3> A_BLC<2> A_BLT<1> A_BLT<0> A_BLT<3> A_BLT<2> A_LWL<31> A_LWL<30> A_LWL<29> A_LWL<28> A_LWL<27> A_LWL<26> A_LWL<25> A_LWL<24> A_LWL<23> A_LWL<22> A_LWL<21> A_LWL<20> A_LWL<19> A_LWL<18> A_LWL<17> A_LWL<16> A_RWL<31> A_RWL<30> A_RWL<29> A_RWL<28> A_RWL<27> A_RWL<26> A_RWL<25> A_RWL<24> A_RWL<23> A_RWL<22> A_RWL<21> A_RWL<20> A_RWL<19> A_RWL<18> A_RWL<17> A_RWL<16> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_SRAM +XRAM<1> A_BLC_BOT<1> A_BLC_BOT<0> A_BLC<1> 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VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<25> A_WL<415> A_WL<414> A_WL<413> A_WL<412> A_WL<411> A_WL<410> A_WL<409> A_WL<408> A_WL<407> A_WL<406> A_WL<405> A_WL<404> A_WL<403> A_WL<402> A_WL<401> A_WL<400> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<24> A_WL<399> A_WL<398> A_WL<397> A_WL<396> A_WL<395> A_WL<394> A_WL<393> A_WL<392> A_WL<391> A_WL<390> A_WL<389> A_WL<388> A_WL<387> A_WL<386> A_WL<385> A_WL<384> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<23> A_WL<383> A_WL<382> A_WL<381> A_WL<380> A_WL<379> A_WL<378> A_WL<377> A_WL<376> A_WL<375> A_WL<374> A_WL<373> A_WL<372> A_WL<371> A_WL<370> A_WL<369> A_WL<368> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<22> A_WL<367> A_WL<366> A_WL<365> A_WL<364> A_WL<363> A_WL<362> A_WL<361> A_WL<360> A_WL<359> A_WL<358> A_WL<357> A_WL<356> A_WL<355> A_WL<354> A_WL<353> A_WL<352> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<21> A_WL<351> A_WL<350> A_WL<349> A_WL<348> A_WL<347> A_WL<346> A_WL<345> A_WL<344> A_WL<343> A_WL<342> A_WL<341> A_WL<340> A_WL<339> A_WL<338> A_WL<337> A_WL<336> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<20> A_WL<335> A_WL<334> A_WL<333> A_WL<332> A_WL<331> A_WL<330> A_WL<329> A_WL<328> A_WL<327> A_WL<326> A_WL<325> A_WL<324> A_WL<323> A_WL<322> A_WL<321> A_WL<320> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<19> A_WL<319> A_WL<318> A_WL<317> A_WL<316> A_WL<315> A_WL<314> A_WL<313> A_WL<312> A_WL<311> A_WL<310> A_WL<309> A_WL<308> A_WL<307> A_WL<306> A_WL<305> A_WL<304> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<18> A_WL<303> A_WL<302> A_WL<301> A_WL<300> A_WL<299> A_WL<298> A_WL<297> A_WL<296> A_WL<295> A_WL<294> A_WL<293> A_WL<292> A_WL<291> A_WL<290> A_WL<289> A_WL<288> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<17> A_WL<287> A_WL<286> A_WL<285> A_WL<284> A_WL<283> A_WL<282> A_WL<281> A_WL<280> A_WL<279> A_WL<278> A_WL<277> A_WL<276> A_WL<275> A_WL<274> A_WL<273> A_WL<272> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<16> A_WL<271> A_WL<270> A_WL<269> A_WL<268> A_WL<267> A_WL<266> A_WL<265> A_WL<264> A_WL<263> A_WL<262> A_WL<261> A_WL<260> A_WL<259> A_WL<258> A_WL<257> A_WL<256> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<15> A_WL<255> A_WL<254> A_WL<253> A_WL<252> A_WL<251> A_WL<250> A_WL<249> A_WL<248> A_WL<247> A_WL<246> A_WL<245> A_WL<244> A_WL<243> A_WL<242> A_WL<241> A_WL<240> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<14> A_WL<239> A_WL<238> A_WL<237> A_WL<236> A_WL<235> A_WL<234> A_WL<233> A_WL<232> A_WL<231> A_WL<230> A_WL<229> A_WL<228> A_WL<227> A_WL<226> A_WL<225> A_WL<224> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<13> A_WL<223> A_WL<222> A_WL<221> A_WL<220> A_WL<219> A_WL<218> A_WL<217> A_WL<216> A_WL<215> A_WL<214> A_WL<213> A_WL<212> A_WL<211> A_WL<210> A_WL<209> A_WL<208> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<12> A_WL<207> A_WL<206> A_WL<205> A_WL<204> A_WL<203> A_WL<202> A_WL<201> A_WL<200> A_WL<199> A_WL<198> A_WL<197> A_WL<196> A_WL<195> A_WL<194> A_WL<193> A_WL<192> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<11> A_WL<191> A_WL<190> A_WL<189> A_WL<188> A_WL<187> A_WL<186> A_WL<185> A_WL<184> A_WL<183> A_WL<182> A_WL<181> A_WL<180> A_WL<179> A_WL<178> A_WL<177> A_WL<176> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<10> A_WL<175> A_WL<174> A_WL<173> A_WL<172> A_WL<171> A_WL<170> A_WL<169> A_WL<168> A_WL<167> A_WL<166> A_WL<165> A_WL<164> A_WL<163> A_WL<162> A_WL<161> A_WL<160> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<9> A_WL<159> A_WL<158> A_WL<157> A_WL<156> A_WL<155> A_WL<154> A_WL<153> A_WL<152> A_WL<151> A_WL<150> A_WL<149> A_WL<148> A_WL<147> A_WL<146> A_WL<145> A_WL<144> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<8> A_WL<143> A_WL<142> A_WL<141> A_WL<140> A_WL<139> A_WL<138> A_WL<137> A_WL<136> A_WL<135> A_WL<134> A_WL<133> A_WL<132> A_WL<131> A_WL<130> A_WL<129> A_WL<128> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<7> A_WL<127> A_WL<126> A_WL<125> A_WL<124> A_WL<123> A_WL<122> A_WL<121> A_WL<120> A_WL<119> A_WL<118> A_WL<117> A_WL<116> A_WL<115> A_WL<114> A_WL<113> A_WL<112> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<6> A_WL<111> A_WL<110> A_WL<109> A_WL<108> A_WL<107> A_WL<106> A_WL<105> A_WL<104> A_WL<103> A_WL<102> A_WL<101> A_WL<100> A_WL<99> A_WL<98> A_WL<97> A_WL<96> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<5> A_WL<95> A_WL<94> A_WL<93> A_WL<92> A_WL<91> A_WL<90> A_WL<89> A_WL<88> A_WL<87> A_WL<86> A_WL<85> A_WL<84> A_WL<83> A_WL<82> A_WL<81> A_WL<80> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<4> A_WL<79> A_WL<78> A_WL<77> A_WL<76> A_WL<75> A_WL<74> A_WL<73> A_WL<72> A_WL<71> A_WL<70> A_WL<69> A_WL<68> A_WL<67> A_WL<66> A_WL<65> A_WL<64> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<3> A_WL<63> A_WL<62> A_WL<61> A_WL<60> A_WL<59> A_WL<58> A_WL<57> A_WL<56> A_WL<55> A_WL<54> A_WL<53> A_WL<52> A_WL<51> A_WL<50> A_WL<49> A_WL<48> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<2> A_WL<47> A_WL<46> A_WL<45> A_WL<44> A_WL<43> A_WL<42> A_WL<41> A_WL<40> A_WL<39> A_WL<38> A_WL<37> A_WL<36> A_WL<35> A_WL<34> A_WL<33> A_WL<32> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<1> A_WL<31> A_WL<30> A_WL<29> A_WL<28> A_WL<27> A_WL<26> A_WL<25> A_WL<24> A_WL<23> A_WL<22> A_WL<21> A_WL<20> A_WL<19> A_WL<18> A_WL<17> A_WL<16> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_L<0> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<31> A_IWL<8191> A_IWL<8190> A_IWL<8189> A_IWL<8188> A_IWL<8187> A_IWL<8186> A_IWL<8185> A_IWL<8184> A_IWL<8183> A_IWL<8182> A_IWL<8181> A_IWL<8180> A_IWL<8179> A_IWL<8178> A_IWL<8177> A_IWL<8176> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<30> A_IWL<8175> A_IWL<8174> A_IWL<8173> A_IWL<8172> A_IWL<8171> A_IWL<8170> A_IWL<8169> A_IWL<8168> A_IWL<8167> A_IWL<8166> A_IWL<8165> A_IWL<8164> A_IWL<8163> A_IWL<8162> A_IWL<8161> A_IWL<8160> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<29> A_IWL<8159> A_IWL<8158> A_IWL<8157> A_IWL<8156> A_IWL<8155> A_IWL<8154> A_IWL<8153> A_IWL<8152> A_IWL<8151> A_IWL<8150> A_IWL<8149> A_IWL<8148> A_IWL<8147> A_IWL<8146> A_IWL<8145> A_IWL<8144> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<28> A_IWL<8143> A_IWL<8142> A_IWL<8141> A_IWL<8140> A_IWL<8139> A_IWL<8138> A_IWL<8137> A_IWL<8136> A_IWL<8135> A_IWL<8134> A_IWL<8133> A_IWL<8132> A_IWL<8131> A_IWL<8130> A_IWL<8129> A_IWL<8128> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<27> A_IWL<8127> A_IWL<8126> A_IWL<8125> A_IWL<8124> A_IWL<8123> A_IWL<8122> A_IWL<8121> A_IWL<8120> A_IWL<8119> A_IWL<8118> A_IWL<8117> A_IWL<8116> A_IWL<8115> A_IWL<8114> A_IWL<8113> A_IWL<8112> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<26> A_IWL<8111> A_IWL<8110> A_IWL<8109> A_IWL<8108> A_IWL<8107> A_IWL<8106> A_IWL<8105> A_IWL<8104> A_IWL<8103> A_IWL<8102> A_IWL<8101> A_IWL<8100> A_IWL<8099> A_IWL<8098> A_IWL<8097> A_IWL<8096> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<25> A_IWL<8095> A_IWL<8094> A_IWL<8093> A_IWL<8092> A_IWL<8091> A_IWL<8090> A_IWL<8089> A_IWL<8088> A_IWL<8087> A_IWL<8086> A_IWL<8085> A_IWL<8084> A_IWL<8083> A_IWL<8082> A_IWL<8081> A_IWL<8080> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<24> A_IWL<8079> A_IWL<8078> A_IWL<8077> A_IWL<8076> A_IWL<8075> A_IWL<8074> A_IWL<8073> A_IWL<8072> A_IWL<8071> A_IWL<8070> A_IWL<8069> A_IWL<8068> A_IWL<8067> A_IWL<8066> A_IWL<8065> A_IWL<8064> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<23> A_IWL<8063> A_IWL<8062> A_IWL<8061> A_IWL<8060> A_IWL<8059> A_IWL<8058> A_IWL<8057> A_IWL<8056> A_IWL<8055> A_IWL<8054> A_IWL<8053> A_IWL<8052> A_IWL<8051> A_IWL<8050> A_IWL<8049> A_IWL<8048> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<22> A_IWL<8047> A_IWL<8046> A_IWL<8045> A_IWL<8044> A_IWL<8043> A_IWL<8042> A_IWL<8041> A_IWL<8040> A_IWL<8039> A_IWL<8038> A_IWL<8037> A_IWL<8036> A_IWL<8035> A_IWL<8034> A_IWL<8033> A_IWL<8032> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<21> A_IWL<8031> A_IWL<8030> A_IWL<8029> A_IWL<8028> A_IWL<8027> A_IWL<8026> A_IWL<8025> A_IWL<8024> A_IWL<8023> A_IWL<8022> A_IWL<8021> A_IWL<8020> A_IWL<8019> A_IWL<8018> A_IWL<8017> A_IWL<8016> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<20> A_IWL<8015> A_IWL<8014> A_IWL<8013> A_IWL<8012> A_IWL<8011> A_IWL<8010> A_IWL<8009> A_IWL<8008> A_IWL<8007> A_IWL<8006> A_IWL<8005> A_IWL<8004> A_IWL<8003> A_IWL<8002> A_IWL<8001> A_IWL<8000> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<19> A_IWL<7999> A_IWL<7998> A_IWL<7997> A_IWL<7996> A_IWL<7995> A_IWL<7994> A_IWL<7993> A_IWL<7992> A_IWL<7991> A_IWL<7990> A_IWL<7989> A_IWL<7988> A_IWL<7987> A_IWL<7986> A_IWL<7985> A_IWL<7984> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<18> A_IWL<7983> A_IWL<7982> A_IWL<7981> A_IWL<7980> A_IWL<7979> A_IWL<7978> A_IWL<7977> A_IWL<7976> A_IWL<7975> A_IWL<7974> A_IWL<7973> A_IWL<7972> A_IWL<7971> A_IWL<7970> A_IWL<7969> A_IWL<7968> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<17> A_IWL<7967> A_IWL<7966> A_IWL<7965> A_IWL<7964> A_IWL<7963> A_IWL<7962> A_IWL<7961> A_IWL<7960> A_IWL<7959> A_IWL<7958> A_IWL<7957> A_IWL<7956> A_IWL<7955> A_IWL<7954> A_IWL<7953> A_IWL<7952> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<16> A_IWL<7951> A_IWL<7950> A_IWL<7949> A_IWL<7948> A_IWL<7947> A_IWL<7946> A_IWL<7945> A_IWL<7944> A_IWL<7943> A_IWL<7942> A_IWL<7941> A_IWL<7940> A_IWL<7939> A_IWL<7938> A_IWL<7937> A_IWL<7936> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<15> A_IWL<7935> A_IWL<7934> A_IWL<7933> A_IWL<7932> A_IWL<7931> A_IWL<7930> A_IWL<7929> A_IWL<7928> A_IWL<7927> A_IWL<7926> A_IWL<7925> A_IWL<7924> A_IWL<7923> A_IWL<7922> A_IWL<7921> A_IWL<7920> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<14> A_IWL<7919> A_IWL<7918> A_IWL<7917> A_IWL<7916> A_IWL<7915> A_IWL<7914> A_IWL<7913> A_IWL<7912> A_IWL<7911> A_IWL<7910> A_IWL<7909> A_IWL<7908> A_IWL<7907> A_IWL<7906> A_IWL<7905> A_IWL<7904> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<13> A_IWL<7903> A_IWL<7902> A_IWL<7901> A_IWL<7900> A_IWL<7899> A_IWL<7898> A_IWL<7897> A_IWL<7896> A_IWL<7895> A_IWL<7894> A_IWL<7893> A_IWL<7892> A_IWL<7891> A_IWL<7890> A_IWL<7889> A_IWL<7888> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<12> A_IWL<7887> A_IWL<7886> A_IWL<7885> A_IWL<7884> A_IWL<7883> A_IWL<7882> A_IWL<7881> A_IWL<7880> A_IWL<7879> A_IWL<7878> A_IWL<7877> A_IWL<7876> A_IWL<7875> A_IWL<7874> A_IWL<7873> A_IWL<7872> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<11> A_IWL<7871> A_IWL<7870> A_IWL<7869> A_IWL<7868> A_IWL<7867> A_IWL<7866> A_IWL<7865> A_IWL<7864> A_IWL<7863> A_IWL<7862> A_IWL<7861> A_IWL<7860> A_IWL<7859> A_IWL<7858> A_IWL<7857> A_IWL<7856> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<10> A_IWL<7855> A_IWL<7854> A_IWL<7853> A_IWL<7852> A_IWL<7851> A_IWL<7850> A_IWL<7849> A_IWL<7848> A_IWL<7847> A_IWL<7846> A_IWL<7845> A_IWL<7844> A_IWL<7843> A_IWL<7842> A_IWL<7841> A_IWL<7840> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<9> A_IWL<7839> A_IWL<7838> A_IWL<7837> A_IWL<7836> A_IWL<7835> A_IWL<7834> A_IWL<7833> A_IWL<7832> A_IWL<7831> A_IWL<7830> A_IWL<7829> A_IWL<7828> A_IWL<7827> A_IWL<7826> A_IWL<7825> A_IWL<7824> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<8> A_IWL<7823> A_IWL<7822> A_IWL<7821> A_IWL<7820> A_IWL<7819> A_IWL<7818> A_IWL<7817> A_IWL<7816> A_IWL<7815> A_IWL<7814> A_IWL<7813> A_IWL<7812> A_IWL<7811> A_IWL<7810> A_IWL<7809> A_IWL<7808> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<7> A_IWL<7807> A_IWL<7806> A_IWL<7805> A_IWL<7804> A_IWL<7803> A_IWL<7802> A_IWL<7801> A_IWL<7800> A_IWL<7799> A_IWL<7798> A_IWL<7797> A_IWL<7796> A_IWL<7795> A_IWL<7794> A_IWL<7793> A_IWL<7792> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<6> A_IWL<7791> A_IWL<7790> A_IWL<7789> A_IWL<7788> A_IWL<7787> A_IWL<7786> A_IWL<7785> A_IWL<7784> A_IWL<7783> A_IWL<7782> A_IWL<7781> A_IWL<7780> A_IWL<7779> A_IWL<7778> A_IWL<7777> A_IWL<7776> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<5> A_IWL<7775> A_IWL<7774> A_IWL<7773> A_IWL<7772> A_IWL<7771> A_IWL<7770> A_IWL<7769> A_IWL<7768> A_IWL<7767> A_IWL<7766> A_IWL<7765> A_IWL<7764> A_IWL<7763> A_IWL<7762> A_IWL<7761> A_IWL<7760> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<4> A_IWL<7759> A_IWL<7758> A_IWL<7757> A_IWL<7756> A_IWL<7755> A_IWL<7754> A_IWL<7753> A_IWL<7752> A_IWL<7751> A_IWL<7750> A_IWL<7749> A_IWL<7748> A_IWL<7747> A_IWL<7746> A_IWL<7745> A_IWL<7744> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<3> A_IWL<7743> A_IWL<7742> A_IWL<7741> A_IWL<7740> A_IWL<7739> A_IWL<7738> A_IWL<7737> A_IWL<7736> A_IWL<7735> A_IWL<7734> A_IWL<7733> A_IWL<7732> A_IWL<7731> A_IWL<7730> A_IWL<7729> A_IWL<7728> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<2> A_IWL<7727> A_IWL<7726> A_IWL<7725> A_IWL<7724> A_IWL<7723> A_IWL<7722> A_IWL<7721> A_IWL<7720> A_IWL<7719> A_IWL<7718> A_IWL<7717> A_IWL<7716> A_IWL<7715> A_IWL<7714> A_IWL<7713> A_IWL<7712> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<1> A_IWL<7711> A_IWL<7710> A_IWL<7709> A_IWL<7708> A_IWL<7707> A_IWL<7706> A_IWL<7705> A_IWL<7704> A_IWL<7703> A_IWL<7702> A_IWL<7701> A_IWL<7700> A_IWL<7699> A_IWL<7698> A_IWL<7697> A_IWL<7696> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR +XRAMEDGE_R<0> A_IWL<7695> A_IWL<7694> A_IWL<7693> A_IWL<7692> A_IWL<7691> A_IWL<7690> A_IWL<7689> A_IWL<7688> A_IWL<7687> A_IWL<7686> A_IWL<7685> A_IWL<7684> A_IWL<7683> A_IWL<7682> A_IWL<7681> A_IWL<7680> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR +XCOL<15> A_BLC<31> A_BLC<30> A_BLC_TOP<31> A_BLC_TOP<30> A_BLT<31> A_BLT<30> A_BLT_TOP<31> A_BLT_TOP<30> A_IWL<7679> A_IWL<7678> A_IWL<7677> A_IWL<7676> A_IWL<7675> A_IWL<7674> A_IWL<7673> A_IWL<7672> A_IWL<7671> A_IWL<7670> A_IWL<7669> A_IWL<7668> A_IWL<7667> A_IWL<7666> A_IWL<7665> A_IWL<7664> A_IWL<7663> A_IWL<7662> A_IWL<7661> A_IWL<7660> A_IWL<7659> A_IWL<7658> A_IWL<7657> A_IWL<7656> A_IWL<7655> A_IWL<7654> A_IWL<7653> A_IWL<7652> A_IWL<7651> A_IWL<7650> A_IWL<7649> A_IWL<7648> A_IWL<7647> A_IWL<7646> A_IWL<7645> A_IWL<7644> A_IWL<7643> A_IWL<7642> A_IWL<7641> A_IWL<7640> A_IWL<7639> A_IWL<7638> A_IWL<7637> A_IWL<7636> A_IWL<7635> A_IWL<7634> A_IWL<7633> A_IWL<7632> A_IWL<7631> A_IWL<7630> A_IWL<7629> A_IWL<7628> A_IWL<7627> A_IWL<7626> A_IWL<7625> A_IWL<7624> A_IWL<7623> A_IWL<7622> A_IWL<7621> A_IWL<7620> A_IWL<7619> A_IWL<7618> A_IWL<7617> A_IWL<7616> A_IWL<7615> A_IWL<7614> A_IWL<7613> A_IWL<7612> A_IWL<7611> A_IWL<7610> A_IWL<7609> A_IWL<7608> A_IWL<7607> A_IWL<7606> A_IWL<7605> A_IWL<7604> A_IWL<7603> A_IWL<7602> A_IWL<7601> A_IWL<7600> A_IWL<7599> A_IWL<7598> A_IWL<7597> A_IWL<7596> A_IWL<7595> A_IWL<7594> A_IWL<7593> A_IWL<7592> A_IWL<7591> A_IWL<7590> A_IWL<7589> A_IWL<7588> A_IWL<7587> A_IWL<7586> A_IWL<7585> A_IWL<7584> A_IWL<7583> A_IWL<7582> A_IWL<7581> A_IWL<7580> A_IWL<7579> A_IWL<7578> A_IWL<7577> A_IWL<7576> A_IWL<7575> A_IWL<7574> A_IWL<7573> A_IWL<7572> A_IWL<7571> A_IWL<7570> A_IWL<7569> A_IWL<7568> A_IWL<7567> A_IWL<7566> A_IWL<7565> A_IWL<7564> A_IWL<7563> A_IWL<7562> A_IWL<7561> A_IWL<7560> A_IWL<7559> A_IWL<7558> A_IWL<7557> A_IWL<7556> A_IWL<7555> A_IWL<7554> A_IWL<7553> A_IWL<7552> A_IWL<7551> A_IWL<7550> A_IWL<7549> A_IWL<7548> A_IWL<7547> A_IWL<7546> A_IWL<7545> A_IWL<7544> A_IWL<7543> A_IWL<7542> A_IWL<7541> A_IWL<7540> A_IWL<7539> A_IWL<7538> A_IWL<7537> A_IWL<7536> A_IWL<7535> A_IWL<7534> A_IWL<7533> A_IWL<7532> A_IWL<7531> A_IWL<7530> A_IWL<7529> A_IWL<7528> A_IWL<7527> A_IWL<7526> A_IWL<7525> A_IWL<7524> A_IWL<7523> A_IWL<7522> A_IWL<7521> A_IWL<7520> A_IWL<7519> A_IWL<7518> A_IWL<7517> A_IWL<7516> A_IWL<7515> A_IWL<7514> A_IWL<7513> A_IWL<7512> A_IWL<7511> A_IWL<7510> A_IWL<7509> A_IWL<7508> A_IWL<7507> A_IWL<7506> A_IWL<7505> A_IWL<7504> A_IWL<7503> A_IWL<7502> A_IWL<7501> A_IWL<7500> A_IWL<7499> A_IWL<7498> A_IWL<7497> A_IWL<7496> A_IWL<7495> A_IWL<7494> A_IWL<7493> A_IWL<7492> A_IWL<7491> A_IWL<7490> A_IWL<7489> A_IWL<7488> A_IWL<7487> A_IWL<7486> A_IWL<7485> A_IWL<7484> A_IWL<7483> A_IWL<7482> A_IWL<7481> A_IWL<7480> A_IWL<7479> A_IWL<7478> A_IWL<7477> A_IWL<7476> A_IWL<7475> A_IWL<7474> A_IWL<7473> A_IWL<7472> A_IWL<7471> A_IWL<7470> A_IWL<7469> A_IWL<7468> A_IWL<7467> A_IWL<7466> A_IWL<7465> A_IWL<7464> A_IWL<7463> A_IWL<7462> A_IWL<7461> A_IWL<7460> A_IWL<7459> A_IWL<7458> A_IWL<7457> A_IWL<7456> A_IWL<7455> A_IWL<7454> A_IWL<7453> A_IWL<7452> A_IWL<7451> A_IWL<7450> A_IWL<7449> A_IWL<7448> A_IWL<7447> A_IWL<7446> A_IWL<7445> A_IWL<7444> A_IWL<7443> A_IWL<7442> A_IWL<7441> A_IWL<7440> A_IWL<7439> A_IWL<7438> A_IWL<7437> A_IWL<7436> A_IWL<7435> A_IWL<7434> A_IWL<7433> A_IWL<7432> A_IWL<7431> A_IWL<7430> A_IWL<7429> A_IWL<7428> A_IWL<7427> A_IWL<7426> A_IWL<7425> A_IWL<7424> A_IWL<7423> A_IWL<7422> A_IWL<7421> A_IWL<7420> A_IWL<7419> A_IWL<7418> A_IWL<7417> A_IWL<7416> A_IWL<7415> A_IWL<7414> A_IWL<7413> A_IWL<7412> A_IWL<7411> A_IWL<7410> A_IWL<7409> A_IWL<7408> A_IWL<7407> A_IWL<7406> A_IWL<7405> A_IWL<7404> A_IWL<7403> A_IWL<7402> A_IWL<7401> A_IWL<7400> A_IWL<7399> A_IWL<7398> A_IWL<7397> A_IWL<7396> A_IWL<7395> A_IWL<7394> A_IWL<7393> A_IWL<7392> A_IWL<7391> A_IWL<7390> A_IWL<7389> A_IWL<7388> A_IWL<7387> A_IWL<7386> A_IWL<7385> A_IWL<7384> A_IWL<7383> A_IWL<7382> A_IWL<7381> A_IWL<7380> A_IWL<7379> A_IWL<7378> A_IWL<7377> A_IWL<7376> A_IWL<7375> A_IWL<7374> A_IWL<7373> A_IWL<7372> A_IWL<7371> A_IWL<7370> A_IWL<7369> A_IWL<7368> A_IWL<7367> A_IWL<7366> A_IWL<7365> A_IWL<7364> A_IWL<7363> A_IWL<7362> A_IWL<7361> A_IWL<7360> A_IWL<7359> A_IWL<7358> A_IWL<7357> A_IWL<7356> A_IWL<7355> A_IWL<7354> A_IWL<7353> A_IWL<7352> A_IWL<7351> A_IWL<7350> A_IWL<7349> A_IWL<7348> A_IWL<7347> A_IWL<7346> A_IWL<7345> A_IWL<7344> A_IWL<7343> A_IWL<7342> A_IWL<7341> A_IWL<7340> A_IWL<7339> A_IWL<7338> A_IWL<7337> A_IWL<7336> A_IWL<7335> A_IWL<7334> A_IWL<7333> A_IWL<7332> A_IWL<7331> A_IWL<7330> A_IWL<7329> A_IWL<7328> A_IWL<7327> A_IWL<7326> A_IWL<7325> A_IWL<7324> A_IWL<7323> A_IWL<7322> A_IWL<7321> A_IWL<7320> A_IWL<7319> A_IWL<7318> A_IWL<7317> A_IWL<7316> A_IWL<7315> A_IWL<7314> A_IWL<7313> A_IWL<7312> A_IWL<7311> A_IWL<7310> A_IWL<7309> A_IWL<7308> A_IWL<7307> A_IWL<7306> A_IWL<7305> A_IWL<7304> A_IWL<7303> A_IWL<7302> A_IWL<7301> A_IWL<7300> A_IWL<7299> A_IWL<7298> A_IWL<7297> A_IWL<7296> A_IWL<7295> A_IWL<7294> A_IWL<7293> A_IWL<7292> A_IWL<7291> A_IWL<7290> A_IWL<7289> A_IWL<7288> A_IWL<7287> A_IWL<7286> A_IWL<7285> A_IWL<7284> A_IWL<7283> A_IWL<7282> A_IWL<7281> A_IWL<7280> A_IWL<7279> A_IWL<7278> A_IWL<7277> A_IWL<7276> A_IWL<7275> A_IWL<7274> A_IWL<7273> A_IWL<7272> A_IWL<7271> A_IWL<7270> A_IWL<7269> A_IWL<7268> A_IWL<7267> A_IWL<7266> A_IWL<7265> A_IWL<7264> A_IWL<7263> A_IWL<7262> A_IWL<7261> A_IWL<7260> A_IWL<7259> A_IWL<7258> A_IWL<7257> A_IWL<7256> A_IWL<7255> A_IWL<7254> A_IWL<7253> A_IWL<7252> A_IWL<7251> A_IWL<7250> A_IWL<7249> A_IWL<7248> A_IWL<7247> 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A_IWL<6775> A_IWL<6774> A_IWL<6773> A_IWL<6772> A_IWL<6771> A_IWL<6770> A_IWL<6769> A_IWL<6768> A_IWL<6767> A_IWL<6766> A_IWL<6765> A_IWL<6764> A_IWL<6763> A_IWL<6762> A_IWL<6761> A_IWL<6760> A_IWL<6759> A_IWL<6758> A_IWL<6757> A_IWL<6756> A_IWL<6755> A_IWL<6754> A_IWL<6753> A_IWL<6752> A_IWL<6751> A_IWL<6750> A_IWL<6749> A_IWL<6748> A_IWL<6747> A_IWL<6746> A_IWL<6745> A_IWL<6744> A_IWL<6743> A_IWL<6742> A_IWL<6741> A_IWL<6740> A_IWL<6739> A_IWL<6738> A_IWL<6737> A_IWL<6736> A_IWL<6735> A_IWL<6734> A_IWL<6733> A_IWL<6732> A_IWL<6731> A_IWL<6730> A_IWL<6729> A_IWL<6728> A_IWL<6727> A_IWL<6726> A_IWL<6725> A_IWL<6724> A_IWL<6723> A_IWL<6722> A_IWL<6721> A_IWL<6720> A_IWL<6719> A_IWL<6718> A_IWL<6717> A_IWL<6716> A_IWL<6715> A_IWL<6714> A_IWL<6713> A_IWL<6712> A_IWL<6711> A_IWL<6710> A_IWL<6709> A_IWL<6708> A_IWL<6707> A_IWL<6706> A_IWL<6705> A_IWL<6704> A_IWL<6703> A_IWL<6702> A_IWL<6701> A_IWL<6700> A_IWL<6699> A_IWL<6698> A_IWL<6697> A_IWL<6696> A_IWL<6695> A_IWL<6694> A_IWL<6693> A_IWL<6692> A_IWL<6691> A_IWL<6690> A_IWL<6689> A_IWL<6688> A_IWL<6687> A_IWL<6686> A_IWL<6685> A_IWL<6684> A_IWL<6683> A_IWL<6682> A_IWL<6681> A_IWL<6680> A_IWL<6679> A_IWL<6678> A_IWL<6677> A_IWL<6676> A_IWL<6675> A_IWL<6674> A_IWL<6673> A_IWL<6672> A_IWL<6671> A_IWL<6670> A_IWL<6669> A_IWL<6668> A_IWL<6667> A_IWL<6666> A_IWL<6665> A_IWL<6664> A_IWL<6663> A_IWL<6662> A_IWL<6661> A_IWL<6660> A_IWL<6659> A_IWL<6658> A_IWL<6657> A_IWL<6656> A_IWL<7679> A_IWL<7678> A_IWL<7677> A_IWL<7676> A_IWL<7675> A_IWL<7674> A_IWL<7673> A_IWL<7672> A_IWL<7671> A_IWL<7670> A_IWL<7669> A_IWL<7668> A_IWL<7667> A_IWL<7666> A_IWL<7665> A_IWL<7664> A_IWL<7663> A_IWL<7662> A_IWL<7661> A_IWL<7660> A_IWL<7659> A_IWL<7658> A_IWL<7657> A_IWL<7656> A_IWL<7655> A_IWL<7654> A_IWL<7653> A_IWL<7652> A_IWL<7651> A_IWL<7650> A_IWL<7649> A_IWL<7648> A_IWL<7647> A_IWL<7646> A_IWL<7645> A_IWL<7644> A_IWL<7643> A_IWL<7642> A_IWL<7641> A_IWL<7640> A_IWL<7639> A_IWL<7638> A_IWL<7637> A_IWL<7636> A_IWL<7635> A_IWL<7634> A_IWL<7633> A_IWL<7632> A_IWL<7631> A_IWL<7630> A_IWL<7629> A_IWL<7628> A_IWL<7627> A_IWL<7626> A_IWL<7625> A_IWL<7624> A_IWL<7623> A_IWL<7622> A_IWL<7621> A_IWL<7620> A_IWL<7619> A_IWL<7618> A_IWL<7617> A_IWL<7616> A_IWL<7615> A_IWL<7614> A_IWL<7613> A_IWL<7612> A_IWL<7611> A_IWL<7610> A_IWL<7609> A_IWL<7608> A_IWL<7607> A_IWL<7606> A_IWL<7605> A_IWL<7604> A_IWL<7603> A_IWL<7602> A_IWL<7601> A_IWL<7600> A_IWL<7599> A_IWL<7598> A_IWL<7597> A_IWL<7596> A_IWL<7595> A_IWL<7594> A_IWL<7593> A_IWL<7592> A_IWL<7591> A_IWL<7590> A_IWL<7589> A_IWL<7588> A_IWL<7587> A_IWL<7586> A_IWL<7585> A_IWL<7584> A_IWL<7583> A_IWL<7582> A_IWL<7581> A_IWL<7580> A_IWL<7579> A_IWL<7578> A_IWL<7577> A_IWL<7576> A_IWL<7575> A_IWL<7574> A_IWL<7573> A_IWL<7572> A_IWL<7571> A_IWL<7570> A_IWL<7569> A_IWL<7568> A_IWL<7567> A_IWL<7566> A_IWL<7565> A_IWL<7564> A_IWL<7563> A_IWL<7562> A_IWL<7561> A_IWL<7560> A_IWL<7559> A_IWL<7558> A_IWL<7557> A_IWL<7556> A_IWL<7555> A_IWL<7554> A_IWL<7553> A_IWL<7552> A_IWL<7551> A_IWL<7550> A_IWL<7549> A_IWL<7548> A_IWL<7547> A_IWL<7546> A_IWL<7545> A_IWL<7544> A_IWL<7543> A_IWL<7542> A_IWL<7541> A_IWL<7540> A_IWL<7539> A_IWL<7538> A_IWL<7537> A_IWL<7536> A_IWL<7535> A_IWL<7534> A_IWL<7533> A_IWL<7532> A_IWL<7531> A_IWL<7530> A_IWL<7529> A_IWL<7528> A_IWL<7527> A_IWL<7526> A_IWL<7525> A_IWL<7524> A_IWL<7523> A_IWL<7522> A_IWL<7521> A_IWL<7520> A_IWL<7519> A_IWL<7518> A_IWL<7517> A_IWL<7516> A_IWL<7515> A_IWL<7514> A_IWL<7513> A_IWL<7512> A_IWL<7511> A_IWL<7510> A_IWL<7509> A_IWL<7508> A_IWL<7507> A_IWL<7506> A_IWL<7505> A_IWL<7504> A_IWL<7503> A_IWL<7502> A_IWL<7501> A_IWL<7500> A_IWL<7499> A_IWL<7498> A_IWL<7497> A_IWL<7496> A_IWL<7495> A_IWL<7494> A_IWL<7493> A_IWL<7492> A_IWL<7491> A_IWL<7490> A_IWL<7489> A_IWL<7488> A_IWL<7487> A_IWL<7486> A_IWL<7485> A_IWL<7484> A_IWL<7483> A_IWL<7482> A_IWL<7481> A_IWL<7480> A_IWL<7479> A_IWL<7478> A_IWL<7477> A_IWL<7476> A_IWL<7475> A_IWL<7474> A_IWL<7473> A_IWL<7472> A_IWL<7471> A_IWL<7470> A_IWL<7469> A_IWL<7468> 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A_IWL<7384> A_IWL<7383> A_IWL<7382> A_IWL<7381> A_IWL<7380> A_IWL<7379> A_IWL<7378> A_IWL<7377> A_IWL<7376> A_IWL<7375> A_IWL<7374> A_IWL<7373> A_IWL<7372> A_IWL<7371> A_IWL<7370> A_IWL<7369> A_IWL<7368> A_IWL<7367> A_IWL<7366> A_IWL<7365> A_IWL<7364> A_IWL<7363> A_IWL<7362> A_IWL<7361> A_IWL<7360> A_IWL<7359> A_IWL<7358> A_IWL<7357> A_IWL<7356> A_IWL<7355> A_IWL<7354> A_IWL<7353> A_IWL<7352> A_IWL<7351> A_IWL<7350> A_IWL<7349> A_IWL<7348> A_IWL<7347> A_IWL<7346> A_IWL<7345> A_IWL<7344> A_IWL<7343> A_IWL<7342> A_IWL<7341> A_IWL<7340> A_IWL<7339> A_IWL<7338> A_IWL<7337> A_IWL<7336> A_IWL<7335> A_IWL<7334> A_IWL<7333> A_IWL<7332> A_IWL<7331> A_IWL<7330> A_IWL<7329> A_IWL<7328> A_IWL<7327> A_IWL<7326> A_IWL<7325> A_IWL<7324> A_IWL<7323> A_IWL<7322> A_IWL<7321> A_IWL<7320> A_IWL<7319> A_IWL<7318> A_IWL<7317> A_IWL<7316> A_IWL<7315> A_IWL<7314> A_IWL<7313> A_IWL<7312> A_IWL<7311> A_IWL<7310> A_IWL<7309> A_IWL<7308> A_IWL<7307> A_IWL<7306> A_IWL<7305> A_IWL<7304> A_IWL<7303> A_IWL<7302> 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A_IWL<7218> A_IWL<7217> A_IWL<7216> A_IWL<7215> A_IWL<7214> A_IWL<7213> A_IWL<7212> A_IWL<7211> A_IWL<7210> A_IWL<7209> A_IWL<7208> A_IWL<7207> A_IWL<7206> A_IWL<7205> A_IWL<7204> A_IWL<7203> A_IWL<7202> A_IWL<7201> A_IWL<7200> A_IWL<7199> A_IWL<7198> A_IWL<7197> A_IWL<7196> A_IWL<7195> A_IWL<7194> A_IWL<7193> A_IWL<7192> A_IWL<7191> A_IWL<7190> A_IWL<7189> A_IWL<7188> A_IWL<7187> A_IWL<7186> A_IWL<7185> A_IWL<7184> A_IWL<7183> A_IWL<7182> A_IWL<7181> A_IWL<7180> A_IWL<7179> A_IWL<7178> A_IWL<7177> A_IWL<7176> A_IWL<7175> A_IWL<7174> A_IWL<7173> A_IWL<7172> A_IWL<7171> A_IWL<7170> A_IWL<7169> A_IWL<7168> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_COLUMN_pcell_0 +XCOL<13> A_BLC<27> A_BLC<26> A_BLC_TOP<27> A_BLC_TOP<26> A_BLT<27> A_BLT<26> A_BLT_TOP<27> A_BLT_TOP<26> A_IWL<6655> A_IWL<6654> A_IWL<6653> A_IWL<6652> A_IWL<6651> A_IWL<6650> A_IWL<6649> A_IWL<6648> A_IWL<6647> A_IWL<6646> A_IWL<6645> A_IWL<6644> A_IWL<6643> A_IWL<6642> A_IWL<6641> A_IWL<6640> A_IWL<6639> A_IWL<6638> A_IWL<6637> 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A_IWL<6082> A_IWL<6081> A_IWL<6080> A_IWL<6079> A_IWL<6078> A_IWL<6077> A_IWL<6076> A_IWL<6075> A_IWL<6074> A_IWL<6073> A_IWL<6072> A_IWL<6071> A_IWL<6070> A_IWL<6069> A_IWL<6068> A_IWL<6067> A_IWL<6066> A_IWL<6065> A_IWL<6064> A_IWL<6063> A_IWL<6062> A_IWL<6061> A_IWL<6060> A_IWL<6059> A_IWL<6058> A_IWL<6057> A_IWL<6056> A_IWL<6055> A_IWL<6054> A_IWL<6053> A_IWL<6052> A_IWL<6051> A_IWL<6050> A_IWL<6049> A_IWL<6048> A_IWL<6047> A_IWL<6046> A_IWL<6045> A_IWL<6044> A_IWL<6043> A_IWL<6042> A_IWL<6041> A_IWL<6040> A_IWL<6039> A_IWL<6038> A_IWL<6037> A_IWL<6036> A_IWL<6035> A_IWL<6034> A_IWL<6033> A_IWL<6032> A_IWL<6031> A_IWL<6030> A_IWL<6029> A_IWL<6028> A_IWL<6027> A_IWL<6026> A_IWL<6025> A_IWL<6024> A_IWL<6023> A_IWL<6022> A_IWL<6021> A_IWL<6020> A_IWL<6019> A_IWL<6018> A_IWL<6017> A_IWL<6016> A_IWL<6015> A_IWL<6014> A_IWL<6013> A_IWL<6012> A_IWL<6011> A_IWL<6010> A_IWL<6009> A_IWL<6008> A_IWL<6007> A_IWL<6006> A_IWL<6005> A_IWL<6004> A_IWL<6003> A_IWL<6002> A_IWL<6001> A_IWL<6000> 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A_IWL<5916> A_IWL<5915> A_IWL<5914> A_IWL<5913> A_IWL<5912> A_IWL<5911> A_IWL<5910> A_IWL<5909> A_IWL<5908> A_IWL<5907> A_IWL<5906> A_IWL<5905> A_IWL<5904> A_IWL<5903> A_IWL<5902> A_IWL<5901> A_IWL<5900> A_IWL<5899> A_IWL<5898> A_IWL<5897> A_IWL<5896> A_IWL<5895> A_IWL<5894> A_IWL<5893> A_IWL<5892> A_IWL<5891> A_IWL<5890> A_IWL<5889> A_IWL<5888> A_IWL<5887> A_IWL<5886> A_IWL<5885> A_IWL<5884> A_IWL<5883> A_IWL<5882> A_IWL<5881> A_IWL<5880> A_IWL<5879> A_IWL<5878> A_IWL<5877> A_IWL<5876> A_IWL<5875> A_IWL<5874> A_IWL<5873> A_IWL<5872> A_IWL<5871> A_IWL<5870> A_IWL<5869> A_IWL<5868> A_IWL<5867> A_IWL<5866> A_IWL<5865> A_IWL<5864> A_IWL<5863> A_IWL<5862> A_IWL<5861> A_IWL<5860> A_IWL<5859> A_IWL<5858> A_IWL<5857> A_IWL<5856> A_IWL<5855> A_IWL<5854> A_IWL<5853> A_IWL<5852> A_IWL<5851> A_IWL<5850> A_IWL<5849> A_IWL<5848> A_IWL<5847> A_IWL<5846> A_IWL<5845> A_IWL<5844> A_IWL<5843> A_IWL<5842> A_IWL<5841> A_IWL<5840> A_IWL<5839> A_IWL<5838> A_IWL<5837> A_IWL<5836> A_IWL<5835> A_IWL<5834> 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A_IWL<6359> A_IWL<6358> A_IWL<6357> A_IWL<6356> A_IWL<6355> A_IWL<6354> A_IWL<6353> A_IWL<6352> A_IWL<6351> A_IWL<6350> A_IWL<6349> A_IWL<6348> A_IWL<6347> A_IWL<6346> A_IWL<6345> A_IWL<6344> A_IWL<6343> A_IWL<6342> A_IWL<6341> A_IWL<6340> A_IWL<6339> A_IWL<6338> A_IWL<6337> A_IWL<6336> A_IWL<6335> A_IWL<6334> A_IWL<6333> A_IWL<6332> A_IWL<6331> A_IWL<6330> A_IWL<6329> A_IWL<6328> A_IWL<6327> A_IWL<6326> A_IWL<6325> A_IWL<6324> A_IWL<6323> A_IWL<6322> A_IWL<6321> A_IWL<6320> A_IWL<6319> A_IWL<6318> A_IWL<6317> A_IWL<6316> A_IWL<6315> A_IWL<6314> A_IWL<6313> A_IWL<6312> A_IWL<6311> A_IWL<6310> A_IWL<6309> A_IWL<6308> A_IWL<6307> A_IWL<6306> A_IWL<6305> A_IWL<6304> A_IWL<6303> A_IWL<6302> A_IWL<6301> A_IWL<6300> A_IWL<6299> A_IWL<6298> A_IWL<6297> A_IWL<6296> A_IWL<6295> A_IWL<6294> A_IWL<6293> A_IWL<6292> A_IWL<6291> A_IWL<6290> A_IWL<6289> A_IWL<6288> A_IWL<6287> A_IWL<6286> A_IWL<6285> A_IWL<6284> A_IWL<6283> A_IWL<6282> A_IWL<6281> A_IWL<6280> A_IWL<6279> A_IWL<6278> A_IWL<6277> A_IWL<6276> A_IWL<6275> A_IWL<6274> A_IWL<6273> A_IWL<6272> A_IWL<6271> A_IWL<6270> A_IWL<6269> A_IWL<6268> A_IWL<6267> A_IWL<6266> A_IWL<6265> A_IWL<6264> A_IWL<6263> A_IWL<6262> A_IWL<6261> A_IWL<6260> A_IWL<6259> A_IWL<6258> A_IWL<6257> A_IWL<6256> A_IWL<6255> A_IWL<6254> A_IWL<6253> A_IWL<6252> A_IWL<6251> A_IWL<6250> A_IWL<6249> A_IWL<6248> A_IWL<6247> A_IWL<6246> A_IWL<6245> A_IWL<6244> A_IWL<6243> A_IWL<6242> A_IWL<6241> A_IWL<6240> A_IWL<6239> A_IWL<6238> A_IWL<6237> A_IWL<6236> A_IWL<6235> A_IWL<6234> A_IWL<6233> A_IWL<6232> A_IWL<6231> A_IWL<6230> A_IWL<6229> A_IWL<6228> A_IWL<6227> A_IWL<6226> A_IWL<6225> A_IWL<6224> A_IWL<6223> A_IWL<6222> A_IWL<6221> A_IWL<6220> A_IWL<6219> A_IWL<6218> A_IWL<6217> A_IWL<6216> A_IWL<6215> A_IWL<6214> A_IWL<6213> A_IWL<6212> A_IWL<6211> A_IWL<6210> A_IWL<6209> A_IWL<6208> A_IWL<6207> A_IWL<6206> A_IWL<6205> A_IWL<6204> A_IWL<6203> A_IWL<6202> A_IWL<6201> A_IWL<6200> A_IWL<6199> A_IWL<6198> A_IWL<6197> A_IWL<6196> A_IWL<6195> A_IWL<6194> A_IWL<6193> A_IWL<6192> A_IWL<6191> A_IWL<6190> A_IWL<6189> A_IWL<6188> A_IWL<6187> A_IWL<6186> A_IWL<6185> A_IWL<6184> A_IWL<6183> A_IWL<6182> A_IWL<6181> A_IWL<6180> A_IWL<6179> A_IWL<6178> A_IWL<6177> A_IWL<6176> A_IWL<6175> A_IWL<6174> A_IWL<6173> A_IWL<6172> A_IWL<6171> A_IWL<6170> A_IWL<6169> A_IWL<6168> A_IWL<6167> A_IWL<6166> A_IWL<6165> A_IWL<6164> A_IWL<6163> A_IWL<6162> A_IWL<6161> A_IWL<6160> A_IWL<6159> A_IWL<6158> A_IWL<6157> A_IWL<6156> A_IWL<6155> A_IWL<6154> A_IWL<6153> A_IWL<6152> A_IWL<6151> A_IWL<6150> A_IWL<6149> A_IWL<6148> A_IWL<6147> A_IWL<6146> A_IWL<6145> A_IWL<6144> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_COLUMN_pcell_0 +XCOL<11> A_BLC<23> A_BLC<22> A_BLC_TOP<23> A_BLC_TOP<22> A_BLT<23> A_BLT<22> A_BLT_TOP<23> A_BLT_TOP<22> A_IWL<5631> A_IWL<5630> A_IWL<5629> A_IWL<5628> A_IWL<5627> A_IWL<5626> A_IWL<5625> A_IWL<5624> A_IWL<5623> A_IWL<5622> A_IWL<5621> A_IWL<5620> A_IWL<5619> A_IWL<5618> A_IWL<5617> A_IWL<5616> A_IWL<5615> A_IWL<5614> A_IWL<5613> A_IWL<5612> A_IWL<5611> A_IWL<5610> A_IWL<5609> A_IWL<5608> A_IWL<5607> A_IWL<5606> A_IWL<5605> A_IWL<5604> A_IWL<5603> A_IWL<5602> A_IWL<5601> A_IWL<5600> A_IWL<5599> A_IWL<5598> A_IWL<5597> A_IWL<5596> A_IWL<5595> A_IWL<5594> A_IWL<5593> A_IWL<5592> A_IWL<5591> A_IWL<5590> A_IWL<5589> A_IWL<5588> A_IWL<5587> A_IWL<5586> A_IWL<5585> A_IWL<5584> A_IWL<5583> A_IWL<5582> A_IWL<5581> A_IWL<5580> A_IWL<5579> A_IWL<5578> A_IWL<5577> A_IWL<5576> A_IWL<5575> A_IWL<5574> A_IWL<5573> A_IWL<5572> A_IWL<5571> A_IWL<5570> A_IWL<5569> A_IWL<5568> A_IWL<5567> A_IWL<5566> A_IWL<5565> A_IWL<5564> A_IWL<5563> A_IWL<5562> A_IWL<5561> A_IWL<5560> A_IWL<5559> A_IWL<5558> A_IWL<5557> A_IWL<5556> A_IWL<5555> A_IWL<5554> A_IWL<5553> A_IWL<5552> A_IWL<5551> A_IWL<5550> A_IWL<5549> A_IWL<5548> A_IWL<5547> A_IWL<5546> A_IWL<5545> A_IWL<5544> A_IWL<5543> A_IWL<5542> A_IWL<5541> A_IWL<5540> A_IWL<5539> A_IWL<5538> A_IWL<5537> A_IWL<5536> A_IWL<5535> A_IWL<5534> A_IWL<5533> A_IWL<5532> A_IWL<5531> A_IWL<5530> A_IWL<5529> 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A_IWL<5445> A_IWL<5444> A_IWL<5443> A_IWL<5442> A_IWL<5441> A_IWL<5440> A_IWL<5439> A_IWL<5438> A_IWL<5437> A_IWL<5436> A_IWL<5435> A_IWL<5434> A_IWL<5433> A_IWL<5432> A_IWL<5431> A_IWL<5430> A_IWL<5429> A_IWL<5428> A_IWL<5427> A_IWL<5426> A_IWL<5425> A_IWL<5424> A_IWL<5423> A_IWL<5422> A_IWL<5421> A_IWL<5420> A_IWL<5419> A_IWL<5418> A_IWL<5417> A_IWL<5416> A_IWL<5415> A_IWL<5414> A_IWL<5413> A_IWL<5412> A_IWL<5411> A_IWL<5410> A_IWL<5409> A_IWL<5408> A_IWL<5407> A_IWL<5406> A_IWL<5405> A_IWL<5404> A_IWL<5403> A_IWL<5402> A_IWL<5401> A_IWL<5400> A_IWL<5399> A_IWL<5398> A_IWL<5397> A_IWL<5396> A_IWL<5395> A_IWL<5394> A_IWL<5393> A_IWL<5392> A_IWL<5391> A_IWL<5390> A_IWL<5389> A_IWL<5388> A_IWL<5387> A_IWL<5386> A_IWL<5385> A_IWL<5384> A_IWL<5383> A_IWL<5382> A_IWL<5381> A_IWL<5380> A_IWL<5379> A_IWL<5378> A_IWL<5377> A_IWL<5376> A_IWL<5375> A_IWL<5374> A_IWL<5373> A_IWL<5372> A_IWL<5371> A_IWL<5370> A_IWL<5369> A_IWL<5368> A_IWL<5367> A_IWL<5366> A_IWL<5365> A_IWL<5364> A_IWL<5363> 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A_IWL<5279> A_IWL<5278> A_IWL<5277> A_IWL<5276> A_IWL<5275> A_IWL<5274> A_IWL<5273> A_IWL<5272> A_IWL<5271> A_IWL<5270> A_IWL<5269> A_IWL<5268> A_IWL<5267> A_IWL<5266> A_IWL<5265> A_IWL<5264> A_IWL<5263> A_IWL<5262> A_IWL<5261> A_IWL<5260> A_IWL<5259> A_IWL<5258> A_IWL<5257> A_IWL<5256> A_IWL<5255> A_IWL<5254> A_IWL<5253> A_IWL<5252> A_IWL<5251> A_IWL<5250> A_IWL<5249> A_IWL<5248> A_IWL<5247> A_IWL<5246> A_IWL<5245> A_IWL<5244> A_IWL<5243> A_IWL<5242> A_IWL<5241> A_IWL<5240> A_IWL<5239> A_IWL<5238> A_IWL<5237> A_IWL<5236> A_IWL<5235> A_IWL<5234> A_IWL<5233> A_IWL<5232> A_IWL<5231> A_IWL<5230> A_IWL<5229> A_IWL<5228> A_IWL<5227> A_IWL<5226> A_IWL<5225> A_IWL<5224> A_IWL<5223> A_IWL<5222> A_IWL<5221> A_IWL<5220> A_IWL<5219> A_IWL<5218> A_IWL<5217> A_IWL<5216> A_IWL<5215> A_IWL<5214> A_IWL<5213> A_IWL<5212> A_IWL<5211> A_IWL<5210> A_IWL<5209> A_IWL<5208> A_IWL<5207> A_IWL<5206> A_IWL<5205> A_IWL<5204> A_IWL<5203> A_IWL<5202> A_IWL<5201> A_IWL<5200> A_IWL<5199> A_IWL<5198> A_IWL<5197> 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A_IWL<6137> A_IWL<6136> A_IWL<6135> A_IWL<6134> A_IWL<6133> A_IWL<6132> A_IWL<6131> A_IWL<6130> A_IWL<6129> A_IWL<6128> A_IWL<6127> A_IWL<6126> A_IWL<6125> A_IWL<6124> A_IWL<6123> A_IWL<6122> A_IWL<6121> A_IWL<6120> A_IWL<6119> A_IWL<6118> A_IWL<6117> A_IWL<6116> A_IWL<6115> A_IWL<6114> A_IWL<6113> A_IWL<6112> A_IWL<6111> A_IWL<6110> A_IWL<6109> A_IWL<6108> A_IWL<6107> A_IWL<6106> A_IWL<6105> A_IWL<6104> A_IWL<6103> A_IWL<6102> A_IWL<6101> A_IWL<6100> A_IWL<6099> A_IWL<6098> A_IWL<6097> A_IWL<6096> A_IWL<6095> A_IWL<6094> A_IWL<6093> A_IWL<6092> A_IWL<6091> A_IWL<6090> A_IWL<6089> A_IWL<6088> A_IWL<6087> A_IWL<6086> A_IWL<6085> A_IWL<6084> A_IWL<6083> A_IWL<6082> A_IWL<6081> A_IWL<6080> A_IWL<6079> A_IWL<6078> A_IWL<6077> A_IWL<6076> A_IWL<6075> A_IWL<6074> A_IWL<6073> A_IWL<6072> A_IWL<6071> A_IWL<6070> A_IWL<6069> A_IWL<6068> A_IWL<6067> A_IWL<6066> A_IWL<6065> A_IWL<6064> A_IWL<6063> A_IWL<6062> A_IWL<6061> A_IWL<6060> A_IWL<6059> A_IWL<6058> A_IWL<6057> A_IWL<6056> A_IWL<6055> A_IWL<6054> A_IWL<6053> A_IWL<6052> A_IWL<6051> A_IWL<6050> A_IWL<6049> A_IWL<6048> A_IWL<6047> A_IWL<6046> A_IWL<6045> A_IWL<6044> A_IWL<6043> A_IWL<6042> A_IWL<6041> A_IWL<6040> A_IWL<6039> A_IWL<6038> A_IWL<6037> A_IWL<6036> A_IWL<6035> A_IWL<6034> A_IWL<6033> A_IWL<6032> A_IWL<6031> A_IWL<6030> A_IWL<6029> A_IWL<6028> A_IWL<6027> A_IWL<6026> A_IWL<6025> A_IWL<6024> A_IWL<6023> A_IWL<6022> A_IWL<6021> A_IWL<6020> A_IWL<6019> A_IWL<6018> A_IWL<6017> A_IWL<6016> A_IWL<6015> A_IWL<6014> A_IWL<6013> A_IWL<6012> A_IWL<6011> A_IWL<6010> A_IWL<6009> A_IWL<6008> A_IWL<6007> A_IWL<6006> A_IWL<6005> A_IWL<6004> A_IWL<6003> A_IWL<6002> A_IWL<6001> A_IWL<6000> A_IWL<5999> A_IWL<5998> A_IWL<5997> A_IWL<5996> A_IWL<5995> A_IWL<5994> A_IWL<5993> A_IWL<5992> A_IWL<5991> A_IWL<5990> A_IWL<5989> A_IWL<5988> A_IWL<5987> A_IWL<5986> A_IWL<5985> A_IWL<5984> A_IWL<5983> A_IWL<5982> A_IWL<5981> A_IWL<5980> A_IWL<5979> A_IWL<5978> A_IWL<5977> A_IWL<5976> A_IWL<5975> A_IWL<5974> A_IWL<5973> A_IWL<5972> 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A_IWL<4337> A_IWL<4336> A_IWL<4335> A_IWL<4334> A_IWL<4333> A_IWL<4332> A_IWL<4331> A_IWL<4330> A_IWL<4329> A_IWL<4328> A_IWL<4327> A_IWL<4326> A_IWL<4325> A_IWL<4324> A_IWL<4323> A_IWL<4322> A_IWL<4321> A_IWL<4320> A_IWL<4319> A_IWL<4318> A_IWL<4317> A_IWL<4316> A_IWL<4315> A_IWL<4314> A_IWL<4313> A_IWL<4312> A_IWL<4311> A_IWL<4310> A_IWL<4309> A_IWL<4308> A_IWL<4307> A_IWL<4306> A_IWL<4305> A_IWL<4304> A_IWL<4303> A_IWL<4302> A_IWL<4301> A_IWL<4300> A_IWL<4299> A_IWL<4298> A_IWL<4297> A_IWL<4296> A_IWL<4295> A_IWL<4294> A_IWL<4293> A_IWL<4292> A_IWL<4291> A_IWL<4290> A_IWL<4289> A_IWL<4288> A_IWL<4287> A_IWL<4286> A_IWL<4285> A_IWL<4284> A_IWL<4283> A_IWL<4282> A_IWL<4281> A_IWL<4280> A_IWL<4279> A_IWL<4278> A_IWL<4277> A_IWL<4276> A_IWL<4275> A_IWL<4274> A_IWL<4273> A_IWL<4272> A_IWL<4271> A_IWL<4270> A_IWL<4269> A_IWL<4268> A_IWL<4267> A_IWL<4266> A_IWL<4265> A_IWL<4264> A_IWL<4263> A_IWL<4262> A_IWL<4261> A_IWL<4260> A_IWL<4259> A_IWL<4258> A_IWL<4257> A_IWL<4256> A_IWL<4255> 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A_IWL<4614> A_IWL<4613> A_IWL<4612> A_IWL<4611> A_IWL<4610> A_IWL<4609> A_IWL<4608> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_COLUMN_pcell_0 +XCOL<8> A_BLC<17> A_BLC<16> A_BLC_TOP<17> A_BLC_TOP<16> A_BLT<17> A_BLT<16> A_BLT_TOP<17> A_BLT_TOP<16> A_IWL<4095> A_IWL<4094> A_IWL<4093> A_IWL<4092> A_IWL<4091> A_IWL<4090> A_IWL<4089> A_IWL<4088> A_IWL<4087> A_IWL<4086> A_IWL<4085> A_IWL<4084> A_IWL<4083> A_IWL<4082> A_IWL<4081> A_IWL<4080> A_IWL<4079> A_IWL<4078> A_IWL<4077> A_IWL<4076> A_IWL<4075> A_IWL<4074> A_IWL<4073> A_IWL<4072> A_IWL<4071> A_IWL<4070> A_IWL<4069> A_IWL<4068> A_IWL<4067> A_IWL<4066> A_IWL<4065> A_IWL<4064> A_IWL<4063> A_IWL<4062> A_IWL<4061> A_IWL<4060> A_IWL<4059> A_IWL<4058> A_IWL<4057> A_IWL<4056> A_IWL<4055> A_IWL<4054> A_IWL<4053> A_IWL<4052> A_IWL<4051> A_IWL<4050> A_IWL<4049> A_IWL<4048> A_IWL<4047> A_IWL<4046> A_IWL<4045> A_IWL<4044> A_IWL<4043> A_IWL<4042> A_IWL<4041> A_IWL<4040> A_IWL<4039> A_IWL<4038> A_IWL<4037> A_IWL<4036> A_IWL<4035> A_IWL<4034> A_IWL<4033> A_IWL<4032> A_IWL<4031> A_IWL<4030> A_IWL<4029> A_IWL<4028> A_IWL<4027> A_IWL<4026> A_IWL<4025> A_IWL<4024> A_IWL<4023> A_IWL<4022> A_IWL<4021> A_IWL<4020> A_IWL<4019> A_IWL<4018> A_IWL<4017> A_IWL<4016> A_IWL<4015> A_IWL<4014> A_IWL<4013> A_IWL<4012> A_IWL<4011> A_IWL<4010> A_IWL<4009> A_IWL<4008> A_IWL<4007> A_IWL<4006> A_IWL<4005> A_IWL<4004> A_IWL<4003> A_IWL<4002> A_IWL<4001> A_IWL<4000> A_IWL<3999> A_IWL<3998> A_IWL<3997> A_IWL<3996> A_IWL<3995> A_IWL<3994> A_IWL<3993> A_IWL<3992> A_IWL<3991> A_IWL<3990> A_IWL<3989> A_IWL<3988> A_IWL<3987> A_IWL<3986> A_IWL<3985> A_IWL<3984> A_IWL<3983> A_IWL<3982> A_IWL<3981> A_IWL<3980> A_IWL<3979> A_IWL<3978> A_IWL<3977> A_IWL<3976> A_IWL<3975> A_IWL<3974> A_IWL<3973> A_IWL<3972> A_IWL<3971> A_IWL<3970> A_IWL<3969> A_IWL<3968> A_IWL<3967> A_IWL<3966> A_IWL<3965> A_IWL<3964> A_IWL<3963> A_IWL<3962> A_IWL<3961> A_IWL<3960> A_IWL<3959> A_IWL<3958> A_IWL<3957> A_IWL<3956> A_IWL<3955> A_IWL<3954> A_IWL<3953> A_IWL<3952> A_IWL<3951> A_IWL<3950> A_IWL<3949> A_IWL<3948> A_IWL<3947> A_IWL<3946> A_IWL<3945> A_IWL<3944> A_IWL<3943> A_IWL<3942> A_IWL<3941> A_IWL<3940> A_IWL<3939> A_IWL<3938> A_IWL<3937> A_IWL<3936> A_IWL<3935> A_IWL<3934> A_IWL<3933> A_IWL<3932> A_IWL<3931> A_IWL<3930> A_IWL<3929> A_IWL<3928> A_IWL<3927> A_IWL<3926> A_IWL<3925> A_IWL<3924> A_IWL<3923> A_IWL<3922> A_IWL<3921> A_IWL<3920> A_IWL<3919> A_IWL<3918> A_IWL<3917> A_IWL<3916> A_IWL<3915> A_IWL<3914> A_IWL<3913> A_IWL<3912> A_IWL<3911> A_IWL<3910> A_IWL<3909> A_IWL<3908> A_IWL<3907> A_IWL<3906> A_IWL<3905> A_IWL<3904> A_IWL<3903> A_IWL<3902> A_IWL<3901> A_IWL<3900> A_IWL<3899> A_IWL<3898> A_IWL<3897> A_IWL<3896> A_IWL<3895> A_IWL<3894> A_IWL<3893> A_IWL<3892> A_IWL<3891> A_IWL<3890> A_IWL<3889> A_IWL<3888> A_IWL<3887> A_IWL<3886> A_IWL<3885> A_IWL<3884> A_IWL<3883> A_IWL<3882> A_IWL<3881> A_IWL<3880> A_IWL<3879> A_IWL<3878> A_IWL<3877> A_IWL<3876> A_IWL<3875> A_IWL<3874> A_IWL<3873> A_IWL<3872> A_IWL<3871> A_IWL<3870> A_IWL<3869> A_IWL<3868> A_IWL<3867> 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A_IWL<3783> A_IWL<3782> A_IWL<3781> A_IWL<3780> A_IWL<3779> A_IWL<3778> A_IWL<3777> A_IWL<3776> A_IWL<3775> A_IWL<3774> A_IWL<3773> A_IWL<3772> A_IWL<3771> A_IWL<3770> A_IWL<3769> A_IWL<3768> A_IWL<3767> A_IWL<3766> A_IWL<3765> A_IWL<3764> A_IWL<3763> A_IWL<3762> A_IWL<3761> A_IWL<3760> A_IWL<3759> A_IWL<3758> A_IWL<3757> A_IWL<3756> A_IWL<3755> A_IWL<3754> A_IWL<3753> A_IWL<3752> A_IWL<3751> A_IWL<3750> A_IWL<3749> A_IWL<3748> A_IWL<3747> A_IWL<3746> A_IWL<3745> A_IWL<3744> A_IWL<3743> A_IWL<3742> A_IWL<3741> A_IWL<3740> A_IWL<3739> A_IWL<3738> A_IWL<3737> A_IWL<3736> A_IWL<3735> A_IWL<3734> A_IWL<3733> A_IWL<3732> A_IWL<3731> A_IWL<3730> A_IWL<3729> A_IWL<3728> A_IWL<3727> A_IWL<3726> A_IWL<3725> A_IWL<3724> A_IWL<3723> A_IWL<3722> A_IWL<3721> A_IWL<3720> A_IWL<3719> A_IWL<3718> A_IWL<3717> A_IWL<3716> A_IWL<3715> A_IWL<3714> A_IWL<3713> A_IWL<3712> A_IWL<3711> A_IWL<3710> A_IWL<3709> A_IWL<3708> A_IWL<3707> A_IWL<3706> A_IWL<3705> A_IWL<3704> A_IWL<3703> A_IWL<3702> A_IWL<3701> A_IWL<3700> A_IWL<3699> A_IWL<3698> A_IWL<3697> A_IWL<3696> A_IWL<3695> A_IWL<3694> A_IWL<3693> A_IWL<3692> A_IWL<3691> A_IWL<3690> A_IWL<3689> A_IWL<3688> A_IWL<3687> A_IWL<3686> A_IWL<3685> A_IWL<3684> A_IWL<3683> A_IWL<3682> A_IWL<3681> A_IWL<3680> A_IWL<3679> A_IWL<3678> A_IWL<3677> A_IWL<3676> A_IWL<3675> A_IWL<3674> A_IWL<3673> A_IWL<3672> A_IWL<3671> A_IWL<3670> A_IWL<3669> A_IWL<3668> A_IWL<3667> A_IWL<3666> A_IWL<3665> A_IWL<3664> A_IWL<3663> A_IWL<3662> A_IWL<3661> A_IWL<3660> A_IWL<3659> A_IWL<3658> A_IWL<3657> A_IWL<3656> A_IWL<3655> A_IWL<3654> A_IWL<3653> A_IWL<3652> A_IWL<3651> A_IWL<3650> A_IWL<3649> A_IWL<3648> A_IWL<3647> A_IWL<3646> A_IWL<3645> A_IWL<3644> A_IWL<3643> A_IWL<3642> A_IWL<3641> A_IWL<3640> A_IWL<3639> A_IWL<3638> A_IWL<3637> A_IWL<3636> A_IWL<3635> A_IWL<3634> A_IWL<3633> A_IWL<3632> A_IWL<3631> A_IWL<3630> A_IWL<3629> A_IWL<3628> A_IWL<3627> A_IWL<3626> A_IWL<3625> A_IWL<3624> A_IWL<3623> A_IWL<3622> A_IWL<3621> A_IWL<3620> A_IWL<3619> A_IWL<3618> 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A_IWL<4558> A_IWL<4557> A_IWL<4556> A_IWL<4555> A_IWL<4554> A_IWL<4553> A_IWL<4552> A_IWL<4551> A_IWL<4550> A_IWL<4549> A_IWL<4548> A_IWL<4547> A_IWL<4546> A_IWL<4545> A_IWL<4544> A_IWL<4543> A_IWL<4542> A_IWL<4541> A_IWL<4540> A_IWL<4539> A_IWL<4538> A_IWL<4537> A_IWL<4536> A_IWL<4535> A_IWL<4534> A_IWL<4533> A_IWL<4532> A_IWL<4531> A_IWL<4530> A_IWL<4529> A_IWL<4528> A_IWL<4527> A_IWL<4526> A_IWL<4525> A_IWL<4524> A_IWL<4523> A_IWL<4522> A_IWL<4521> A_IWL<4520> A_IWL<4519> A_IWL<4518> A_IWL<4517> A_IWL<4516> A_IWL<4515> A_IWL<4514> A_IWL<4513> A_IWL<4512> A_IWL<4511> A_IWL<4510> A_IWL<4509> A_IWL<4508> A_IWL<4507> A_IWL<4506> A_IWL<4505> A_IWL<4504> A_IWL<4503> A_IWL<4502> A_IWL<4501> A_IWL<4500> A_IWL<4499> A_IWL<4498> A_IWL<4497> A_IWL<4496> A_IWL<4495> A_IWL<4494> A_IWL<4493> A_IWL<4492> A_IWL<4491> A_IWL<4490> A_IWL<4489> A_IWL<4488> A_IWL<4487> A_IWL<4486> A_IWL<4485> A_IWL<4484> A_IWL<4483> A_IWL<4482> A_IWL<4481> A_IWL<4480> A_IWL<4479> A_IWL<4478> A_IWL<4477> A_IWL<4476> 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A_IWL<4392> A_IWL<4391> A_IWL<4390> A_IWL<4389> A_IWL<4388> A_IWL<4387> A_IWL<4386> A_IWL<4385> A_IWL<4384> A_IWL<4383> A_IWL<4382> A_IWL<4381> A_IWL<4380> A_IWL<4379> A_IWL<4378> A_IWL<4377> A_IWL<4376> A_IWL<4375> A_IWL<4374> A_IWL<4373> A_IWL<4372> A_IWL<4371> A_IWL<4370> A_IWL<4369> A_IWL<4368> A_IWL<4367> A_IWL<4366> A_IWL<4365> A_IWL<4364> A_IWL<4363> A_IWL<4362> A_IWL<4361> A_IWL<4360> A_IWL<4359> A_IWL<4358> A_IWL<4357> A_IWL<4356> A_IWL<4355> A_IWL<4354> A_IWL<4353> A_IWL<4352> A_IWL<4351> A_IWL<4350> A_IWL<4349> A_IWL<4348> A_IWL<4347> A_IWL<4346> A_IWL<4345> A_IWL<4344> A_IWL<4343> A_IWL<4342> A_IWL<4341> A_IWL<4340> A_IWL<4339> A_IWL<4338> A_IWL<4337> A_IWL<4336> A_IWL<4335> A_IWL<4334> A_IWL<4333> A_IWL<4332> A_IWL<4331> A_IWL<4330> A_IWL<4329> A_IWL<4328> A_IWL<4327> A_IWL<4326> A_IWL<4325> A_IWL<4324> A_IWL<4323> A_IWL<4322> A_IWL<4321> A_IWL<4320> A_IWL<4319> A_IWL<4318> A_IWL<4317> A_IWL<4316> A_IWL<4315> A_IWL<4314> A_IWL<4313> A_IWL<4312> A_IWL<4311> A_IWL<4310> A_IWL<4309> A_IWL<4308> A_IWL<4307> A_IWL<4306> A_IWL<4305> A_IWL<4304> A_IWL<4303> A_IWL<4302> A_IWL<4301> A_IWL<4300> A_IWL<4299> A_IWL<4298> A_IWL<4297> A_IWL<4296> A_IWL<4295> A_IWL<4294> A_IWL<4293> A_IWL<4292> A_IWL<4291> A_IWL<4290> A_IWL<4289> A_IWL<4288> A_IWL<4287> A_IWL<4286> A_IWL<4285> A_IWL<4284> A_IWL<4283> A_IWL<4282> A_IWL<4281> A_IWL<4280> A_IWL<4279> A_IWL<4278> A_IWL<4277> A_IWL<4276> A_IWL<4275> A_IWL<4274> A_IWL<4273> A_IWL<4272> A_IWL<4271> A_IWL<4270> A_IWL<4269> A_IWL<4268> A_IWL<4267> A_IWL<4266> A_IWL<4265> A_IWL<4264> A_IWL<4263> A_IWL<4262> A_IWL<4261> A_IWL<4260> A_IWL<4259> A_IWL<4258> A_IWL<4257> A_IWL<4256> A_IWL<4255> A_IWL<4254> A_IWL<4253> A_IWL<4252> A_IWL<4251> A_IWL<4250> A_IWL<4249> A_IWL<4248> A_IWL<4247> A_IWL<4246> A_IWL<4245> A_IWL<4244> A_IWL<4243> A_IWL<4242> A_IWL<4241> A_IWL<4240> A_IWL<4239> A_IWL<4238> A_IWL<4237> A_IWL<4236> A_IWL<4235> A_IWL<4234> A_IWL<4233> A_IWL<4232> A_IWL<4231> A_IWL<4230> A_IWL<4229> A_IWL<4228> A_IWL<4227> A_IWL<4226> A_IWL<4225> A_IWL<4224> A_IWL<4223> A_IWL<4222> A_IWL<4221> A_IWL<4220> A_IWL<4219> A_IWL<4218> A_IWL<4217> A_IWL<4216> A_IWL<4215> A_IWL<4214> A_IWL<4213> A_IWL<4212> A_IWL<4211> A_IWL<4210> A_IWL<4209> A_IWL<4208> A_IWL<4207> A_IWL<4206> A_IWL<4205> A_IWL<4204> A_IWL<4203> A_IWL<4202> A_IWL<4201> A_IWL<4200> A_IWL<4199> A_IWL<4198> A_IWL<4197> A_IWL<4196> A_IWL<4195> A_IWL<4194> A_IWL<4193> A_IWL<4192> A_IWL<4191> A_IWL<4190> A_IWL<4189> A_IWL<4188> A_IWL<4187> A_IWL<4186> A_IWL<4185> A_IWL<4184> A_IWL<4183> A_IWL<4182> A_IWL<4181> A_IWL<4180> A_IWL<4179> A_IWL<4178> A_IWL<4177> A_IWL<4176> A_IWL<4175> A_IWL<4174> A_IWL<4173> A_IWL<4172> A_IWL<4171> A_IWL<4170> A_IWL<4169> A_IWL<4168> A_IWL<4167> A_IWL<4166> A_IWL<4165> A_IWL<4164> A_IWL<4163> A_IWL<4162> A_IWL<4161> A_IWL<4160> A_IWL<4159> A_IWL<4158> A_IWL<4157> A_IWL<4156> A_IWL<4155> A_IWL<4154> A_IWL<4153> A_IWL<4152> A_IWL<4151> A_IWL<4150> A_IWL<4149> A_IWL<4148> A_IWL<4147> A_IWL<4146> A_IWL<4145> A_IWL<4144> A_IWL<4143> A_IWL<4142> A_IWL<4141> A_IWL<4140> A_IWL<4139> A_IWL<4138> A_IWL<4137> A_IWL<4136> A_IWL<4135> A_IWL<4134> A_IWL<4133> A_IWL<4132> A_IWL<4131> A_IWL<4130> A_IWL<4129> A_IWL<4128> A_IWL<4127> A_IWL<4126> A_IWL<4125> A_IWL<4124> A_IWL<4123> A_IWL<4122> A_IWL<4121> A_IWL<4120> A_IWL<4119> A_IWL<4118> A_IWL<4117> A_IWL<4116> A_IWL<4115> A_IWL<4114> A_IWL<4113> A_IWL<4112> A_IWL<4111> A_IWL<4110> A_IWL<4109> A_IWL<4108> A_IWL<4107> A_IWL<4106> A_IWL<4105> A_IWL<4104> A_IWL<4103> A_IWL<4102> A_IWL<4101> A_IWL<4100> A_IWL<4099> A_IWL<4098> A_IWL<4097> A_IWL<4096> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_COLUMN_pcell_0 +XCOL<7> A_BLC<15> A_BLC<14> A_BLC_TOP<15> A_BLC_TOP<14> A_BLT<15> A_BLT<14> A_BLT_TOP<15> A_BLT_TOP<14> A_IWL<3583> A_IWL<3582> A_IWL<3581> A_IWL<3580> A_IWL<3579> A_IWL<3578> A_IWL<3577> A_IWL<3576> A_IWL<3575> A_IWL<3574> A_IWL<3573> A_IWL<3572> A_IWL<3571> A_IWL<3570> A_IWL<3569> A_IWL<3568> A_IWL<3567> A_IWL<3566> A_IWL<3565> A_IWL<3564> A_IWL<3563> A_IWL<3562> A_IWL<3561> A_IWL<3560> A_IWL<3559> A_IWL<3558> A_IWL<3557> A_IWL<3556> A_IWL<3555> A_IWL<3554> A_IWL<3553> A_IWL<3552> A_IWL<3551> A_IWL<3550> A_IWL<3549> A_IWL<3548> A_IWL<3547> A_IWL<3546> A_IWL<3545> A_IWL<3544> A_IWL<3543> A_IWL<3542> A_IWL<3541> A_IWL<3540> A_IWL<3539> A_IWL<3538> A_IWL<3537> A_IWL<3536> A_IWL<3535> A_IWL<3534> A_IWL<3533> A_IWL<3532> A_IWL<3531> A_IWL<3530> A_IWL<3529> A_IWL<3528> A_IWL<3527> A_IWL<3526> A_IWL<3525> A_IWL<3524> A_IWL<3523> A_IWL<3522> A_IWL<3521> A_IWL<3520> A_IWL<3519> A_IWL<3518> A_IWL<3517> A_IWL<3516> A_IWL<3515> A_IWL<3514> A_IWL<3513> A_IWL<3512> A_IWL<3511> A_IWL<3510> A_IWL<3509> A_IWL<3508> A_IWL<3507> A_IWL<3506> A_IWL<3505> A_IWL<3504> A_IWL<3503> A_IWL<3502> A_IWL<3501> A_IWL<3500> A_IWL<3499> A_IWL<3498> A_IWL<3497> A_IWL<3496> A_IWL<3495> A_IWL<3494> A_IWL<3493> A_IWL<3492> A_IWL<3491> A_IWL<3490> A_IWL<3489> A_IWL<3488> A_IWL<3487> A_IWL<3486> A_IWL<3485> A_IWL<3484> A_IWL<3483> A_IWL<3482> A_IWL<3481> A_IWL<3480> A_IWL<3479> A_IWL<3478> A_IWL<3477> A_IWL<3476> A_IWL<3475> A_IWL<3474> A_IWL<3473> A_IWL<3472> A_IWL<3471> A_IWL<3470> A_IWL<3469> A_IWL<3468> A_IWL<3467> A_IWL<3466> A_IWL<3465> A_IWL<3464> A_IWL<3463> A_IWL<3462> A_IWL<3461> A_IWL<3460> A_IWL<3459> A_IWL<3458> A_IWL<3457> A_IWL<3456> A_IWL<3455> A_IWL<3454> A_IWL<3453> A_IWL<3452> A_IWL<3451> A_IWL<3450> A_IWL<3449> A_IWL<3448> A_IWL<3447> A_IWL<3446> A_IWL<3445> A_IWL<3444> A_IWL<3443> A_IWL<3442> A_IWL<3441> A_IWL<3440> A_IWL<3439> A_IWL<3438> A_IWL<3437> A_IWL<3436> A_IWL<3435> A_IWL<3434> A_IWL<3433> A_IWL<3432> A_IWL<3431> A_IWL<3430> A_IWL<3429> A_IWL<3428> A_IWL<3427> A_IWL<3426> A_IWL<3425> A_IWL<3424> A_IWL<3423> A_IWL<3422> A_IWL<3421> A_IWL<3420> A_IWL<3419> A_IWL<3418> A_IWL<3417> A_IWL<3416> A_IWL<3415> A_IWL<3414> A_IWL<3413> A_IWL<3412> A_IWL<3411> A_IWL<3410> A_IWL<3409> A_IWL<3408> A_IWL<3407> A_IWL<3406> A_IWL<3405> A_IWL<3404> A_IWL<3403> A_IWL<3402> A_IWL<3401> A_IWL<3400> A_IWL<3399> A_IWL<3398> A_IWL<3397> A_IWL<3396> A_IWL<3395> A_IWL<3394> A_IWL<3393> A_IWL<3392> A_IWL<3391> A_IWL<3390> A_IWL<3389> A_IWL<3388> A_IWL<3387> A_IWL<3386> A_IWL<3385> A_IWL<3384> A_IWL<3383> A_IWL<3382> A_IWL<3381> A_IWL<3380> A_IWL<3379> A_IWL<3378> A_IWL<3377> A_IWL<3376> A_IWL<3375> A_IWL<3374> A_IWL<3373> A_IWL<3372> A_IWL<3371> A_IWL<3370> A_IWL<3369> A_IWL<3368> A_IWL<3367> A_IWL<3366> A_IWL<3365> A_IWL<3364> A_IWL<3363> A_IWL<3362> A_IWL<3361> A_IWL<3360> A_IWL<3359> A_IWL<3358> A_IWL<3357> A_IWL<3356> A_IWL<3355> A_IWL<3354> A_IWL<3353> A_IWL<3352> A_IWL<3351> A_IWL<3350> A_IWL<3349> A_IWL<3348> A_IWL<3347> A_IWL<3346> A_IWL<3345> A_IWL<3344> A_IWL<3343> A_IWL<3342> A_IWL<3341> A_IWL<3340> A_IWL<3339> A_IWL<3338> A_IWL<3337> A_IWL<3336> A_IWL<3335> A_IWL<3334> A_IWL<3333> A_IWL<3332> A_IWL<3331> A_IWL<3330> A_IWL<3329> A_IWL<3328> A_IWL<3327> A_IWL<3326> A_IWL<3325> A_IWL<3324> A_IWL<3323> A_IWL<3322> A_IWL<3321> A_IWL<3320> A_IWL<3319> A_IWL<3318> A_IWL<3317> A_IWL<3316> A_IWL<3315> A_IWL<3314> A_IWL<3313> A_IWL<3312> A_IWL<3311> A_IWL<3310> A_IWL<3309> A_IWL<3308> A_IWL<3307> A_IWL<3306> A_IWL<3305> A_IWL<3304> A_IWL<3303> A_IWL<3302> A_IWL<3301> A_IWL<3300> A_IWL<3299> A_IWL<3298> A_IWL<3297> A_IWL<3296> A_IWL<3295> A_IWL<3294> A_IWL<3293> A_IWL<3292> A_IWL<3291> A_IWL<3290> A_IWL<3289> A_IWL<3288> A_IWL<3287> A_IWL<3286> A_IWL<3285> A_IWL<3284> A_IWL<3283> A_IWL<3282> A_IWL<3281> A_IWL<3280> A_IWL<3279> A_IWL<3278> A_IWL<3277> A_IWL<3276> A_IWL<3275> A_IWL<3274> A_IWL<3273> A_IWL<3272> A_IWL<3271> A_IWL<3270> A_IWL<3269> A_IWL<3268> A_IWL<3267> A_IWL<3266> A_IWL<3265> A_IWL<3264> A_IWL<3263> A_IWL<3262> A_IWL<3261> A_IWL<3260> A_IWL<3259> A_IWL<3258> A_IWL<3257> A_IWL<3256> A_IWL<3255> A_IWL<3254> A_IWL<3253> A_IWL<3252> A_IWL<3251> A_IWL<3250> A_IWL<3249> A_IWL<3248> A_IWL<3247> A_IWL<3246> A_IWL<3245> A_IWL<3244> A_IWL<3243> A_IWL<3242> A_IWL<3241> A_IWL<3240> A_IWL<3239> A_IWL<3238> A_IWL<3237> A_IWL<3236> A_IWL<3235> A_IWL<3234> A_IWL<3233> A_IWL<3232> A_IWL<3231> A_IWL<3230> A_IWL<3229> A_IWL<3228> A_IWL<3227> A_IWL<3226> A_IWL<3225> A_IWL<3224> A_IWL<3223> A_IWL<3222> A_IWL<3221> A_IWL<3220> A_IWL<3219> A_IWL<3218> A_IWL<3217> A_IWL<3216> A_IWL<3215> A_IWL<3214> A_IWL<3213> A_IWL<3212> A_IWL<3211> A_IWL<3210> A_IWL<3209> A_IWL<3208> A_IWL<3207> A_IWL<3206> A_IWL<3205> A_IWL<3204> A_IWL<3203> A_IWL<3202> A_IWL<3201> A_IWL<3200> A_IWL<3199> A_IWL<3198> A_IWL<3197> A_IWL<3196> A_IWL<3195> A_IWL<3194> A_IWL<3193> A_IWL<3192> A_IWL<3191> A_IWL<3190> A_IWL<3189> A_IWL<3188> A_IWL<3187> A_IWL<3186> A_IWL<3185> A_IWL<3184> A_IWL<3183> A_IWL<3182> A_IWL<3181> A_IWL<3180> A_IWL<3179> A_IWL<3178> A_IWL<3177> A_IWL<3176> A_IWL<3175> A_IWL<3174> A_IWL<3173> A_IWL<3172> A_IWL<3171> A_IWL<3170> A_IWL<3169> A_IWL<3168> A_IWL<3167> A_IWL<3166> A_IWL<3165> A_IWL<3164> A_IWL<3163> A_IWL<3162> A_IWL<3161> A_IWL<3160> A_IWL<3159> A_IWL<3158> A_IWL<3157> A_IWL<3156> A_IWL<3155> A_IWL<3154> A_IWL<3153> A_IWL<3152> A_IWL<3151> A_IWL<3150> A_IWL<3149> A_IWL<3148> A_IWL<3147> A_IWL<3146> A_IWL<3145> A_IWL<3144> A_IWL<3143> A_IWL<3142> A_IWL<3141> A_IWL<3140> A_IWL<3139> A_IWL<3138> A_IWL<3137> A_IWL<3136> A_IWL<3135> A_IWL<3134> A_IWL<3133> A_IWL<3132> A_IWL<3131> A_IWL<3130> A_IWL<3129> A_IWL<3128> A_IWL<3127> A_IWL<3126> A_IWL<3125> A_IWL<3124> A_IWL<3123> A_IWL<3122> A_IWL<3121> A_IWL<3120> A_IWL<3119> A_IWL<3118> A_IWL<3117> A_IWL<3116> A_IWL<3115> A_IWL<3114> A_IWL<3113> A_IWL<3112> A_IWL<3111> A_IWL<3110> A_IWL<3109> A_IWL<3108> A_IWL<3107> A_IWL<3106> A_IWL<3105> A_IWL<3104> A_IWL<3103> A_IWL<3102> A_IWL<3101> A_IWL<3100> A_IWL<3099> A_IWL<3098> A_IWL<3097> A_IWL<3096> A_IWL<3095> A_IWL<3094> A_IWL<3093> A_IWL<3092> A_IWL<3091> A_IWL<3090> A_IWL<3089> A_IWL<3088> A_IWL<3087> A_IWL<3086> A_IWL<3085> A_IWL<3084> A_IWL<3083> A_IWL<3082> A_IWL<3081> A_IWL<3080> A_IWL<3079> A_IWL<3078> A_IWL<3077> A_IWL<3076> A_IWL<3075> A_IWL<3074> A_IWL<3073> A_IWL<3072> A_IWL<4095> A_IWL<4094> A_IWL<4093> A_IWL<4092> A_IWL<4091> A_IWL<4090> A_IWL<4089> A_IWL<4088> A_IWL<4087> A_IWL<4086> A_IWL<4085> A_IWL<4084> A_IWL<4083> A_IWL<4082> A_IWL<4081> A_IWL<4080> A_IWL<4079> A_IWL<4078> A_IWL<4077> A_IWL<4076> A_IWL<4075> A_IWL<4074> A_IWL<4073> A_IWL<4072> A_IWL<4071> A_IWL<4070> A_IWL<4069> A_IWL<4068> A_IWL<4067> A_IWL<4066> A_IWL<4065> A_IWL<4064> A_IWL<4063> A_IWL<4062> A_IWL<4061> A_IWL<4060> A_IWL<4059> A_IWL<4058> A_IWL<4057> A_IWL<4056> A_IWL<4055> A_IWL<4054> A_IWL<4053> A_IWL<4052> A_IWL<4051> A_IWL<4050> A_IWL<4049> A_IWL<4048> A_IWL<4047> A_IWL<4046> A_IWL<4045> A_IWL<4044> A_IWL<4043> A_IWL<4042> A_IWL<4041> A_IWL<4040> A_IWL<4039> A_IWL<4038> A_IWL<4037> A_IWL<4036> A_IWL<4035> A_IWL<4034> A_IWL<4033> A_IWL<4032> A_IWL<4031> A_IWL<4030> A_IWL<4029> A_IWL<4028> A_IWL<4027> A_IWL<4026> A_IWL<4025> A_IWL<4024> A_IWL<4023> A_IWL<4022> A_IWL<4021> A_IWL<4020> A_IWL<4019> A_IWL<4018> A_IWL<4017> A_IWL<4016> A_IWL<4015> A_IWL<4014> A_IWL<4013> A_IWL<4012> A_IWL<4011> A_IWL<4010> A_IWL<4009> A_IWL<4008> A_IWL<4007> A_IWL<4006> A_IWL<4005> A_IWL<4004> A_IWL<4003> A_IWL<4002> A_IWL<4001> A_IWL<4000> A_IWL<3999> A_IWL<3998> A_IWL<3997> A_IWL<3996> A_IWL<3995> A_IWL<3994> A_IWL<3993> A_IWL<3992> A_IWL<3991> A_IWL<3990> A_IWL<3989> A_IWL<3988> A_IWL<3987> A_IWL<3986> A_IWL<3985> A_IWL<3984> A_IWL<3983> A_IWL<3982> A_IWL<3981> A_IWL<3980> A_IWL<3979> A_IWL<3978> A_IWL<3977> A_IWL<3976> A_IWL<3975> A_IWL<3974> A_IWL<3973> A_IWL<3972> A_IWL<3971> A_IWL<3970> A_IWL<3969> A_IWL<3968> A_IWL<3967> A_IWL<3966> A_IWL<3965> A_IWL<3964> A_IWL<3963> A_IWL<3962> A_IWL<3961> A_IWL<3960> A_IWL<3959> A_IWL<3958> A_IWL<3957> A_IWL<3956> A_IWL<3955> A_IWL<3954> A_IWL<3953> A_IWL<3952> A_IWL<3951> A_IWL<3950> A_IWL<3949> A_IWL<3948> A_IWL<3947> A_IWL<3946> A_IWL<3945> A_IWL<3944> A_IWL<3943> A_IWL<3942> A_IWL<3941> A_IWL<3940> A_IWL<3939> A_IWL<3938> A_IWL<3937> A_IWL<3936> A_IWL<3935> A_IWL<3934> A_IWL<3933> A_IWL<3932> A_IWL<3931> A_IWL<3930> A_IWL<3929> A_IWL<3928> A_IWL<3927> A_IWL<3926> A_IWL<3925> A_IWL<3924> A_IWL<3923> A_IWL<3922> A_IWL<3921> A_IWL<3920> A_IWL<3919> A_IWL<3918> A_IWL<3917> A_IWL<3916> A_IWL<3915> A_IWL<3914> A_IWL<3913> A_IWL<3912> A_IWL<3911> A_IWL<3910> A_IWL<3909> A_IWL<3908> A_IWL<3907> A_IWL<3906> A_IWL<3905> A_IWL<3904> A_IWL<3903> A_IWL<3902> A_IWL<3901> A_IWL<3900> A_IWL<3899> A_IWL<3898> A_IWL<3897> A_IWL<3896> A_IWL<3895> A_IWL<3894> A_IWL<3893> A_IWL<3892> A_IWL<3891> A_IWL<3890> A_IWL<3889> A_IWL<3888> A_IWL<3887> A_IWL<3886> A_IWL<3885> A_IWL<3884> A_IWL<3883> A_IWL<3882> A_IWL<3881> A_IWL<3880> A_IWL<3879> A_IWL<3878> A_IWL<3877> A_IWL<3876> A_IWL<3875> A_IWL<3874> A_IWL<3873> A_IWL<3872> A_IWL<3871> A_IWL<3870> A_IWL<3869> A_IWL<3868> A_IWL<3867> A_IWL<3866> A_IWL<3865> A_IWL<3864> A_IWL<3863> A_IWL<3862> A_IWL<3861> A_IWL<3860> A_IWL<3859> A_IWL<3858> A_IWL<3857> A_IWL<3856> A_IWL<3855> A_IWL<3854> A_IWL<3853> A_IWL<3852> A_IWL<3851> A_IWL<3850> A_IWL<3849> A_IWL<3848> A_IWL<3847> A_IWL<3846> A_IWL<3845> A_IWL<3844> A_IWL<3843> A_IWL<3842> A_IWL<3841> A_IWL<3840> A_IWL<3839> A_IWL<3838> A_IWL<3837> A_IWL<3836> A_IWL<3835> A_IWL<3834> A_IWL<3833> A_IWL<3832> A_IWL<3831> A_IWL<3830> A_IWL<3829> A_IWL<3828> A_IWL<3827> A_IWL<3826> A_IWL<3825> A_IWL<3824> A_IWL<3823> A_IWL<3822> A_IWL<3821> A_IWL<3820> A_IWL<3819> A_IWL<3818> A_IWL<3817> A_IWL<3816> A_IWL<3815> A_IWL<3814> A_IWL<3813> A_IWL<3812> A_IWL<3811> A_IWL<3810> A_IWL<3809> A_IWL<3808> A_IWL<3807> A_IWL<3806> A_IWL<3805> A_IWL<3804> A_IWL<3803> A_IWL<3802> A_IWL<3801> A_IWL<3800> A_IWL<3799> A_IWL<3798> A_IWL<3797> A_IWL<3796> A_IWL<3795> A_IWL<3794> A_IWL<3793> A_IWL<3792> A_IWL<3791> A_IWL<3790> A_IWL<3789> A_IWL<3788> A_IWL<3787> A_IWL<3786> A_IWL<3785> A_IWL<3784> A_IWL<3783> A_IWL<3782> A_IWL<3781> A_IWL<3780> A_IWL<3779> A_IWL<3778> A_IWL<3777> A_IWL<3776> A_IWL<3775> A_IWL<3774> A_IWL<3773> A_IWL<3772> A_IWL<3771> A_IWL<3770> A_IWL<3769> A_IWL<3768> A_IWL<3767> A_IWL<3766> A_IWL<3765> A_IWL<3764> A_IWL<3763> A_IWL<3762> A_IWL<3761> A_IWL<3760> A_IWL<3759> A_IWL<3758> A_IWL<3757> A_IWL<3756> A_IWL<3755> A_IWL<3754> A_IWL<3753> A_IWL<3752> A_IWL<3751> A_IWL<3750> A_IWL<3749> A_IWL<3748> A_IWL<3747> A_IWL<3746> A_IWL<3745> A_IWL<3744> A_IWL<3743> A_IWL<3742> A_IWL<3741> A_IWL<3740> A_IWL<3739> A_IWL<3738> A_IWL<3737> A_IWL<3736> A_IWL<3735> A_IWL<3734> A_IWL<3733> A_IWL<3732> A_IWL<3731> A_IWL<3730> A_IWL<3729> A_IWL<3728> A_IWL<3727> A_IWL<3726> A_IWL<3725> A_IWL<3724> A_IWL<3723> A_IWL<3722> A_IWL<3721> A_IWL<3720> A_IWL<3719> A_IWL<3718> A_IWL<3717> A_IWL<3716> A_IWL<3715> A_IWL<3714> A_IWL<3713> A_IWL<3712> A_IWL<3711> A_IWL<3710> A_IWL<3709> A_IWL<3708> A_IWL<3707> A_IWL<3706> A_IWL<3705> A_IWL<3704> A_IWL<3703> A_IWL<3702> A_IWL<3701> A_IWL<3700> A_IWL<3699> A_IWL<3698> A_IWL<3697> A_IWL<3696> A_IWL<3695> A_IWL<3694> A_IWL<3693> A_IWL<3692> A_IWL<3691> A_IWL<3690> A_IWL<3689> A_IWL<3688> A_IWL<3687> A_IWL<3686> A_IWL<3685> A_IWL<3684> A_IWL<3683> A_IWL<3682> A_IWL<3681> A_IWL<3680> A_IWL<3679> A_IWL<3678> A_IWL<3677> A_IWL<3676> A_IWL<3675> A_IWL<3674> A_IWL<3673> A_IWL<3672> A_IWL<3671> A_IWL<3670> A_IWL<3669> A_IWL<3668> A_IWL<3667> A_IWL<3666> A_IWL<3665> A_IWL<3664> A_IWL<3663> A_IWL<3662> A_IWL<3661> A_IWL<3660> A_IWL<3659> A_IWL<3658> A_IWL<3657> A_IWL<3656> A_IWL<3655> A_IWL<3654> A_IWL<3653> A_IWL<3652> A_IWL<3651> A_IWL<3650> A_IWL<3649> A_IWL<3648> A_IWL<3647> A_IWL<3646> A_IWL<3645> A_IWL<3644> A_IWL<3643> A_IWL<3642> A_IWL<3641> A_IWL<3640> A_IWL<3639> A_IWL<3638> A_IWL<3637> A_IWL<3636> A_IWL<3635> A_IWL<3634> A_IWL<3633> A_IWL<3632> A_IWL<3631> A_IWL<3630> A_IWL<3629> A_IWL<3628> A_IWL<3627> A_IWL<3626> A_IWL<3625> A_IWL<3624> A_IWL<3623> A_IWL<3622> A_IWL<3621> A_IWL<3620> A_IWL<3619> A_IWL<3618> A_IWL<3617> A_IWL<3616> A_IWL<3615> A_IWL<3614> A_IWL<3613> A_IWL<3612> A_IWL<3611> A_IWL<3610> A_IWL<3609> A_IWL<3608> A_IWL<3607> A_IWL<3606> A_IWL<3605> A_IWL<3604> A_IWL<3603> A_IWL<3602> A_IWL<3601> A_IWL<3600> A_IWL<3599> A_IWL<3598> A_IWL<3597> A_IWL<3596> A_IWL<3595> A_IWL<3594> A_IWL<3593> A_IWL<3592> A_IWL<3591> A_IWL<3590> A_IWL<3589> A_IWL<3588> A_IWL<3587> A_IWL<3586> A_IWL<3585> A_IWL<3584> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_COLUMN_pcell_0 +XCOL<6> A_BLC<13> A_BLC<12> A_BLC_TOP<13> A_BLC_TOP<12> A_BLT<13> A_BLT<12> A_BLT_TOP<13> A_BLT_TOP<12> A_IWL<3071> A_IWL<3070> A_IWL<3069> A_IWL<3068> A_IWL<3067> A_IWL<3066> A_IWL<3065> A_IWL<3064> A_IWL<3063> A_IWL<3062> A_IWL<3061> A_IWL<3060> A_IWL<3059> A_IWL<3058> A_IWL<3057> A_IWL<3056> A_IWL<3055> A_IWL<3054> A_IWL<3053> A_IWL<3052> A_IWL<3051> A_IWL<3050> A_IWL<3049> A_IWL<3048> A_IWL<3047> A_IWL<3046> A_IWL<3045> A_IWL<3044> A_IWL<3043> A_IWL<3042> A_IWL<3041> A_IWL<3040> A_IWL<3039> A_IWL<3038> A_IWL<3037> A_IWL<3036> A_IWL<3035> A_IWL<3034> A_IWL<3033> A_IWL<3032> A_IWL<3031> A_IWL<3030> A_IWL<3029> A_IWL<3028> A_IWL<3027> A_IWL<3026> A_IWL<3025> A_IWL<3024> A_IWL<3023> A_IWL<3022> A_IWL<3021> A_IWL<3020> A_IWL<3019> A_IWL<3018> A_IWL<3017> A_IWL<3016> A_IWL<3015> A_IWL<3014> A_IWL<3013> A_IWL<3012> A_IWL<3011> A_IWL<3010> A_IWL<3009> A_IWL<3008> A_IWL<3007> A_IWL<3006> A_IWL<3005> A_IWL<3004> A_IWL<3003> A_IWL<3002> A_IWL<3001> A_IWL<3000> A_IWL<2999> A_IWL<2998> A_IWL<2997> A_IWL<2996> A_IWL<2995> A_IWL<2994> A_IWL<2993> A_IWL<2992> A_IWL<2991> A_IWL<2990> A_IWL<2989> A_IWL<2988> A_IWL<2987> A_IWL<2986> A_IWL<2985> A_IWL<2984> A_IWL<2983> A_IWL<2982> A_IWL<2981> A_IWL<2980> A_IWL<2979> A_IWL<2978> A_IWL<2977> A_IWL<2976> A_IWL<2975> A_IWL<2974> A_IWL<2973> A_IWL<2972> A_IWL<2971> A_IWL<2970> A_IWL<2969> A_IWL<2968> A_IWL<2967> A_IWL<2966> A_IWL<2965> A_IWL<2964> A_IWL<2963> A_IWL<2962> A_IWL<2961> A_IWL<2960> A_IWL<2959> A_IWL<2958> A_IWL<2957> A_IWL<2956> A_IWL<2955> A_IWL<2954> A_IWL<2953> A_IWL<2952> A_IWL<2951> A_IWL<2950> A_IWL<2949> A_IWL<2948> A_IWL<2947> A_IWL<2946> A_IWL<2945> A_IWL<2944> A_IWL<2943> A_IWL<2942> A_IWL<2941> A_IWL<2940> A_IWL<2939> A_IWL<2938> A_IWL<2937> A_IWL<2936> A_IWL<2935> A_IWL<2934> A_IWL<2933> A_IWL<2932> A_IWL<2931> A_IWL<2930> A_IWL<2929> A_IWL<2928> A_IWL<2927> A_IWL<2926> A_IWL<2925> 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A_IWL<2841> A_IWL<2840> A_IWL<2839> A_IWL<2838> A_IWL<2837> A_IWL<2836> A_IWL<2835> A_IWL<2834> A_IWL<2833> A_IWL<2832> A_IWL<2831> A_IWL<2830> A_IWL<2829> A_IWL<2828> A_IWL<2827> A_IWL<2826> A_IWL<2825> A_IWL<2824> A_IWL<2823> A_IWL<2822> A_IWL<2821> A_IWL<2820> A_IWL<2819> A_IWL<2818> A_IWL<2817> A_IWL<2816> A_IWL<2815> A_IWL<2814> A_IWL<2813> A_IWL<2812> A_IWL<2811> A_IWL<2810> A_IWL<2809> A_IWL<2808> A_IWL<2807> A_IWL<2806> A_IWL<2805> A_IWL<2804> A_IWL<2803> A_IWL<2802> A_IWL<2801> A_IWL<2800> A_IWL<2799> A_IWL<2798> A_IWL<2797> A_IWL<2796> A_IWL<2795> A_IWL<2794> A_IWL<2793> A_IWL<2792> A_IWL<2791> A_IWL<2790> A_IWL<2789> A_IWL<2788> A_IWL<2787> A_IWL<2786> A_IWL<2785> A_IWL<2784> A_IWL<2783> A_IWL<2782> A_IWL<2781> A_IWL<2780> A_IWL<2779> A_IWL<2778> A_IWL<2777> A_IWL<2776> A_IWL<2775> A_IWL<2774> A_IWL<2773> A_IWL<2772> A_IWL<2771> A_IWL<2770> A_IWL<2769> A_IWL<2768> A_IWL<2767> A_IWL<2766> A_IWL<2765> A_IWL<2764> A_IWL<2763> A_IWL<2762> A_IWL<2761> A_IWL<2760> A_IWL<2759> A_IWL<2758> A_IWL<2757> A_IWL<2756> A_IWL<2755> A_IWL<2754> A_IWL<2753> A_IWL<2752> A_IWL<2751> A_IWL<2750> A_IWL<2749> A_IWL<2748> A_IWL<2747> A_IWL<2746> A_IWL<2745> A_IWL<2744> A_IWL<2743> A_IWL<2742> A_IWL<2741> A_IWL<2740> A_IWL<2739> A_IWL<2738> A_IWL<2737> A_IWL<2736> A_IWL<2735> A_IWL<2734> A_IWL<2733> A_IWL<2732> A_IWL<2731> A_IWL<2730> A_IWL<2729> A_IWL<2728> A_IWL<2727> A_IWL<2726> A_IWL<2725> A_IWL<2724> A_IWL<2723> A_IWL<2722> A_IWL<2721> A_IWL<2720> A_IWL<2719> A_IWL<2718> A_IWL<2717> A_IWL<2716> A_IWL<2715> A_IWL<2714> A_IWL<2713> A_IWL<2712> A_IWL<2711> A_IWL<2710> A_IWL<2709> A_IWL<2708> A_IWL<2707> A_IWL<2706> A_IWL<2705> A_IWL<2704> A_IWL<2703> A_IWL<2702> A_IWL<2701> A_IWL<2700> A_IWL<2699> A_IWL<2698> A_IWL<2697> A_IWL<2696> A_IWL<2695> A_IWL<2694> A_IWL<2693> A_IWL<2692> A_IWL<2691> A_IWL<2690> A_IWL<2689> A_IWL<2688> A_IWL<2687> A_IWL<2686> A_IWL<2685> A_IWL<2684> A_IWL<2683> A_IWL<2682> A_IWL<2681> A_IWL<2680> A_IWL<2679> A_IWL<2678> A_IWL<2677> A_IWL<2676> A_IWL<2675> A_IWL<2674> A_IWL<2673> A_IWL<2672> A_IWL<2671> A_IWL<2670> A_IWL<2669> A_IWL<2668> A_IWL<2667> A_IWL<2666> A_IWL<2665> A_IWL<2664> A_IWL<2663> A_IWL<2662> A_IWL<2661> A_IWL<2660> A_IWL<2659> A_IWL<2658> A_IWL<2657> A_IWL<2656> A_IWL<2655> A_IWL<2654> A_IWL<2653> A_IWL<2652> A_IWL<2651> A_IWL<2650> A_IWL<2649> A_IWL<2648> A_IWL<2647> A_IWL<2646> A_IWL<2645> A_IWL<2644> A_IWL<2643> A_IWL<2642> A_IWL<2641> A_IWL<2640> A_IWL<2639> A_IWL<2638> A_IWL<2637> A_IWL<2636> A_IWL<2635> A_IWL<2634> A_IWL<2633> A_IWL<2632> A_IWL<2631> A_IWL<2630> A_IWL<2629> A_IWL<2628> A_IWL<2627> A_IWL<2626> A_IWL<2625> A_IWL<2624> A_IWL<2623> A_IWL<2622> A_IWL<2621> A_IWL<2620> A_IWL<2619> A_IWL<2618> A_IWL<2617> A_IWL<2616> A_IWL<2615> A_IWL<2614> A_IWL<2613> A_IWL<2612> A_IWL<2611> A_IWL<2610> A_IWL<2609> A_IWL<2608> A_IWL<2607> A_IWL<2606> A_IWL<2605> A_IWL<2604> A_IWL<2603> A_IWL<2602> A_IWL<2601> A_IWL<2600> A_IWL<2599> A_IWL<2598> A_IWL<2597> A_IWL<2596> A_IWL<2595> A_IWL<2594> A_IWL<2593> A_IWL<2592> A_IWL<2591> A_IWL<2590> A_IWL<2589> A_IWL<2588> A_IWL<2587> A_IWL<2586> A_IWL<2585> A_IWL<2584> A_IWL<2583> A_IWL<2582> A_IWL<2581> A_IWL<2580> A_IWL<2579> A_IWL<2578> A_IWL<2577> A_IWL<2576> A_IWL<2575> A_IWL<2574> A_IWL<2573> A_IWL<2572> A_IWL<2571> A_IWL<2570> A_IWL<2569> A_IWL<2568> A_IWL<2567> A_IWL<2566> A_IWL<2565> A_IWL<2564> A_IWL<2563> A_IWL<2562> A_IWL<2561> A_IWL<2560> A_IWL<3583> A_IWL<3582> A_IWL<3581> A_IWL<3580> A_IWL<3579> A_IWL<3578> A_IWL<3577> A_IWL<3576> A_IWL<3575> A_IWL<3574> A_IWL<3573> A_IWL<3572> A_IWL<3571> A_IWL<3570> A_IWL<3569> A_IWL<3568> A_IWL<3567> A_IWL<3566> A_IWL<3565> A_IWL<3564> A_IWL<3563> A_IWL<3562> A_IWL<3561> A_IWL<3560> A_IWL<3559> A_IWL<3558> A_IWL<3557> A_IWL<3556> A_IWL<3555> A_IWL<3554> A_IWL<3553> A_IWL<3552> A_IWL<3551> A_IWL<3550> A_IWL<3549> A_IWL<3548> A_IWL<3547> A_IWL<3546> A_IWL<3545> A_IWL<3544> A_IWL<3543> A_IWL<3542> A_IWL<3541> A_IWL<3540> A_IWL<3539> A_IWL<3538> A_IWL<3537> A_IWL<3536> A_IWL<3535> A_IWL<3534> A_IWL<3533> A_IWL<3532> A_IWL<3531> A_IWL<3530> A_IWL<3529> A_IWL<3528> A_IWL<3527> A_IWL<3526> A_IWL<3525> A_IWL<3524> A_IWL<3523> A_IWL<3522> A_IWL<3521> A_IWL<3520> A_IWL<3519> A_IWL<3518> A_IWL<3517> A_IWL<3516> A_IWL<3515> A_IWL<3514> A_IWL<3513> A_IWL<3512> A_IWL<3511> A_IWL<3510> A_IWL<3509> A_IWL<3508> A_IWL<3507> A_IWL<3506> A_IWL<3505> A_IWL<3504> A_IWL<3503> A_IWL<3502> A_IWL<3501> A_IWL<3500> A_IWL<3499> A_IWL<3498> A_IWL<3497> A_IWL<3496> A_IWL<3495> A_IWL<3494> A_IWL<3493> A_IWL<3492> A_IWL<3491> A_IWL<3490> A_IWL<3489> A_IWL<3488> A_IWL<3487> A_IWL<3486> A_IWL<3485> A_IWL<3484> A_IWL<3483> A_IWL<3482> A_IWL<3481> A_IWL<3480> A_IWL<3479> A_IWL<3478> A_IWL<3477> A_IWL<3476> A_IWL<3475> A_IWL<3474> A_IWL<3473> A_IWL<3472> A_IWL<3471> A_IWL<3470> A_IWL<3469> A_IWL<3468> A_IWL<3467> A_IWL<3466> A_IWL<3465> A_IWL<3464> A_IWL<3463> A_IWL<3462> A_IWL<3461> A_IWL<3460> A_IWL<3459> A_IWL<3458> A_IWL<3457> A_IWL<3456> A_IWL<3455> A_IWL<3454> A_IWL<3453> A_IWL<3452> A_IWL<3451> A_IWL<3450> A_IWL<3449> A_IWL<3448> A_IWL<3447> A_IWL<3446> A_IWL<3445> A_IWL<3444> A_IWL<3443> A_IWL<3442> A_IWL<3441> A_IWL<3440> A_IWL<3439> A_IWL<3438> A_IWL<3437> A_IWL<3436> A_IWL<3435> A_IWL<3434> A_IWL<3433> A_IWL<3432> A_IWL<3431> A_IWL<3430> A_IWL<3429> A_IWL<3428> A_IWL<3427> A_IWL<3426> A_IWL<3425> A_IWL<3424> A_IWL<3423> A_IWL<3422> A_IWL<3421> A_IWL<3420> A_IWL<3419> A_IWL<3418> A_IWL<3417> A_IWL<3416> A_IWL<3415> A_IWL<3414> A_IWL<3413> A_IWL<3412> A_IWL<3411> A_IWL<3410> A_IWL<3409> A_IWL<3408> A_IWL<3407> A_IWL<3406> A_IWL<3405> A_IWL<3404> A_IWL<3403> A_IWL<3402> A_IWL<3401> A_IWL<3400> A_IWL<3399> A_IWL<3398> A_IWL<3397> A_IWL<3396> A_IWL<3395> A_IWL<3394> A_IWL<3393> A_IWL<3392> A_IWL<3391> A_IWL<3390> A_IWL<3389> A_IWL<3388> A_IWL<3387> A_IWL<3386> A_IWL<3385> A_IWL<3384> A_IWL<3383> A_IWL<3382> A_IWL<3381> A_IWL<3380> A_IWL<3379> A_IWL<3378> A_IWL<3377> A_IWL<3376> A_IWL<3375> A_IWL<3374> A_IWL<3373> A_IWL<3372> A_IWL<3371> A_IWL<3370> A_IWL<3369> A_IWL<3368> A_IWL<3367> A_IWL<3366> A_IWL<3365> A_IWL<3364> A_IWL<3363> A_IWL<3362> A_IWL<3361> A_IWL<3360> A_IWL<3359> A_IWL<3358> A_IWL<3357> A_IWL<3356> A_IWL<3355> A_IWL<3354> A_IWL<3353> A_IWL<3352> A_IWL<3351> A_IWL<3350> A_IWL<3349> A_IWL<3348> A_IWL<3347> A_IWL<3346> A_IWL<3345> A_IWL<3344> A_IWL<3343> A_IWL<3342> A_IWL<3341> A_IWL<3340> A_IWL<3339> A_IWL<3338> A_IWL<3337> A_IWL<3336> A_IWL<3335> A_IWL<3334> A_IWL<3333> A_IWL<3332> A_IWL<3331> A_IWL<3330> A_IWL<3329> A_IWL<3328> A_IWL<3327> A_IWL<3326> A_IWL<3325> A_IWL<3324> A_IWL<3323> A_IWL<3322> A_IWL<3321> A_IWL<3320> A_IWL<3319> A_IWL<3318> A_IWL<3317> A_IWL<3316> A_IWL<3315> A_IWL<3314> A_IWL<3313> A_IWL<3312> A_IWL<3311> A_IWL<3310> A_IWL<3309> A_IWL<3308> A_IWL<3307> A_IWL<3306> A_IWL<3305> A_IWL<3304> A_IWL<3303> A_IWL<3302> A_IWL<3301> A_IWL<3300> A_IWL<3299> A_IWL<3298> A_IWL<3297> A_IWL<3296> A_IWL<3295> A_IWL<3294> A_IWL<3293> A_IWL<3292> A_IWL<3291> A_IWL<3290> A_IWL<3289> A_IWL<3288> A_IWL<3287> A_IWL<3286> A_IWL<3285> A_IWL<3284> A_IWL<3283> A_IWL<3282> A_IWL<3281> A_IWL<3280> A_IWL<3279> A_IWL<3278> A_IWL<3277> A_IWL<3276> A_IWL<3275> A_IWL<3274> A_IWL<3273> A_IWL<3272> A_IWL<3271> A_IWL<3270> A_IWL<3269> A_IWL<3268> A_IWL<3267> A_IWL<3266> A_IWL<3265> A_IWL<3264> A_IWL<3263> A_IWL<3262> A_IWL<3261> A_IWL<3260> A_IWL<3259> A_IWL<3258> A_IWL<3257> A_IWL<3256> A_IWL<3255> A_IWL<3254> A_IWL<3253> A_IWL<3252> A_IWL<3251> A_IWL<3250> A_IWL<3249> A_IWL<3248> A_IWL<3247> A_IWL<3246> A_IWL<3245> A_IWL<3244> A_IWL<3243> A_IWL<3242> A_IWL<3241> A_IWL<3240> A_IWL<3239> A_IWL<3238> A_IWL<3237> A_IWL<3236> A_IWL<3235> A_IWL<3234> A_IWL<3233> A_IWL<3232> A_IWL<3231> A_IWL<3230> A_IWL<3229> A_IWL<3228> A_IWL<3227> A_IWL<3226> A_IWL<3225> A_IWL<3224> A_IWL<3223> A_IWL<3222> A_IWL<3221> A_IWL<3220> A_IWL<3219> A_IWL<3218> A_IWL<3217> A_IWL<3216> A_IWL<3215> A_IWL<3214> A_IWL<3213> A_IWL<3212> A_IWL<3211> A_IWL<3210> A_IWL<3209> A_IWL<3208> A_IWL<3207> A_IWL<3206> A_IWL<3205> A_IWL<3204> A_IWL<3203> A_IWL<3202> A_IWL<3201> A_IWL<3200> A_IWL<3199> A_IWL<3198> A_IWL<3197> A_IWL<3196> A_IWL<3195> A_IWL<3194> A_IWL<3193> A_IWL<3192> A_IWL<3191> A_IWL<3190> A_IWL<3189> A_IWL<3188> A_IWL<3187> A_IWL<3186> A_IWL<3185> A_IWL<3184> A_IWL<3183> A_IWL<3182> A_IWL<3181> A_IWL<3180> A_IWL<3179> A_IWL<3178> A_IWL<3177> A_IWL<3176> A_IWL<3175> A_IWL<3174> A_IWL<3173> A_IWL<3172> A_IWL<3171> A_IWL<3170> A_IWL<3169> A_IWL<3168> A_IWL<3167> A_IWL<3166> A_IWL<3165> A_IWL<3164> A_IWL<3163> A_IWL<3162> A_IWL<3161> A_IWL<3160> A_IWL<3159> A_IWL<3158> A_IWL<3157> A_IWL<3156> A_IWL<3155> A_IWL<3154> A_IWL<3153> A_IWL<3152> A_IWL<3151> A_IWL<3150> A_IWL<3149> A_IWL<3148> A_IWL<3147> A_IWL<3146> A_IWL<3145> A_IWL<3144> A_IWL<3143> A_IWL<3142> A_IWL<3141> A_IWL<3140> A_IWL<3139> A_IWL<3138> A_IWL<3137> A_IWL<3136> A_IWL<3135> A_IWL<3134> A_IWL<3133> A_IWL<3132> A_IWL<3131> A_IWL<3130> A_IWL<3129> A_IWL<3128> A_IWL<3127> A_IWL<3126> A_IWL<3125> A_IWL<3124> A_IWL<3123> A_IWL<3122> A_IWL<3121> A_IWL<3120> A_IWL<3119> A_IWL<3118> A_IWL<3117> A_IWL<3116> A_IWL<3115> A_IWL<3114> A_IWL<3113> A_IWL<3112> A_IWL<3111> A_IWL<3110> A_IWL<3109> A_IWL<3108> A_IWL<3107> A_IWL<3106> A_IWL<3105> A_IWL<3104> A_IWL<3103> A_IWL<3102> A_IWL<3101> A_IWL<3100> A_IWL<3099> A_IWL<3098> A_IWL<3097> A_IWL<3096> A_IWL<3095> A_IWL<3094> A_IWL<3093> A_IWL<3092> A_IWL<3091> A_IWL<3090> A_IWL<3089> A_IWL<3088> A_IWL<3087> A_IWL<3086> A_IWL<3085> A_IWL<3084> A_IWL<3083> A_IWL<3082> A_IWL<3081> A_IWL<3080> A_IWL<3079> A_IWL<3078> A_IWL<3077> A_IWL<3076> A_IWL<3075> A_IWL<3074> A_IWL<3073> A_IWL<3072> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_COLUMN_pcell_0 +XCOL<5> A_BLC<11> A_BLC<10> A_BLC_TOP<11> A_BLC_TOP<10> A_BLT<11> A_BLT<10> A_BLT_TOP<11> A_BLT_TOP<10> A_IWL<2559> A_IWL<2558> A_IWL<2557> A_IWL<2556> A_IWL<2555> A_IWL<2554> A_IWL<2553> A_IWL<2552> A_IWL<2551> A_IWL<2550> A_IWL<2549> A_IWL<2548> A_IWL<2547> A_IWL<2546> A_IWL<2545> A_IWL<2544> A_IWL<2543> A_IWL<2542> A_IWL<2541> A_IWL<2540> A_IWL<2539> A_IWL<2538> A_IWL<2537> A_IWL<2536> A_IWL<2535> A_IWL<2534> A_IWL<2533> A_IWL<2532> A_IWL<2531> A_IWL<2530> A_IWL<2529> A_IWL<2528> A_IWL<2527> A_IWL<2526> A_IWL<2525> A_IWL<2524> A_IWL<2523> A_IWL<2522> A_IWL<2521> A_IWL<2520> A_IWL<2519> A_IWL<2518> A_IWL<2517> A_IWL<2516> A_IWL<2515> A_IWL<2514> A_IWL<2513> A_IWL<2512> A_IWL<2511> A_IWL<2510> A_IWL<2509> A_IWL<2508> A_IWL<2507> A_IWL<2506> A_IWL<2505> A_IWL<2504> A_IWL<2503> A_IWL<2502> A_IWL<2501> A_IWL<2500> A_IWL<2499> A_IWL<2498> A_IWL<2497> A_IWL<2496> A_IWL<2495> A_IWL<2494> A_IWL<2493> A_IWL<2492> A_IWL<2491> A_IWL<2490> A_IWL<2489> A_IWL<2488> A_IWL<2487> A_IWL<2486> A_IWL<2485> A_IWL<2484> A_IWL<2483> A_IWL<2482> A_IWL<2481> A_IWL<2480> A_IWL<2479> A_IWL<2478> A_IWL<2477> A_IWL<2476> A_IWL<2475> A_IWL<2474> A_IWL<2473> A_IWL<2472> A_IWL<2471> A_IWL<2470> A_IWL<2469> A_IWL<2468> A_IWL<2467> A_IWL<2466> A_IWL<2465> A_IWL<2464> A_IWL<2463> A_IWL<2462> A_IWL<2461> A_IWL<2460> A_IWL<2459> A_IWL<2458> A_IWL<2457> A_IWL<2456> A_IWL<2455> A_IWL<2454> A_IWL<2453> A_IWL<2452> A_IWL<2451> A_IWL<2450> A_IWL<2449> A_IWL<2448> A_IWL<2447> A_IWL<2446> A_IWL<2445> A_IWL<2444> A_IWL<2443> A_IWL<2442> A_IWL<2441> A_IWL<2440> A_IWL<2439> A_IWL<2438> A_IWL<2437> A_IWL<2436> A_IWL<2435> A_IWL<2434> A_IWL<2433> A_IWL<2432> A_IWL<2431> A_IWL<2430> A_IWL<2429> A_IWL<2428> A_IWL<2427> A_IWL<2426> A_IWL<2425> A_IWL<2424> A_IWL<2423> A_IWL<2422> A_IWL<2421> A_IWL<2420> A_IWL<2419> A_IWL<2418> A_IWL<2417> A_IWL<2416> A_IWL<2415> A_IWL<2414> A_IWL<2413> A_IWL<2412> A_IWL<2411> A_IWL<2410> A_IWL<2409> A_IWL<2408> A_IWL<2407> A_IWL<2406> A_IWL<2405> A_IWL<2404> A_IWL<2403> A_IWL<2402> A_IWL<2401> A_IWL<2400> A_IWL<2399> A_IWL<2398> A_IWL<2397> A_IWL<2396> A_IWL<2395> A_IWL<2394> A_IWL<2393> A_IWL<2392> A_IWL<2391> A_IWL<2390> A_IWL<2389> A_IWL<2388> A_IWL<2387> A_IWL<2386> A_IWL<2385> A_IWL<2384> A_IWL<2383> A_IWL<2382> A_IWL<2381> A_IWL<2380> A_IWL<2379> A_IWL<2378> A_IWL<2377> A_IWL<2376> A_IWL<2375> A_IWL<2374> A_IWL<2373> A_IWL<2372> A_IWL<2371> A_IWL<2370> A_IWL<2369> A_IWL<2368> A_IWL<2367> A_IWL<2366> A_IWL<2365> A_IWL<2364> A_IWL<2363> A_IWL<2362> A_IWL<2361> A_IWL<2360> A_IWL<2359> A_IWL<2358> A_IWL<2357> A_IWL<2356> A_IWL<2355> A_IWL<2354> A_IWL<2353> A_IWL<2352> A_IWL<2351> A_IWL<2350> A_IWL<2349> A_IWL<2348> A_IWL<2347> A_IWL<2346> A_IWL<2345> A_IWL<2344> A_IWL<2343> A_IWL<2342> A_IWL<2341> A_IWL<2340> A_IWL<2339> A_IWL<2338> A_IWL<2337> A_IWL<2336> A_IWL<2335> A_IWL<2334> A_IWL<2333> A_IWL<2332> A_IWL<2331> A_IWL<2330> A_IWL<2329> A_IWL<2328> A_IWL<2327> A_IWL<2326> A_IWL<2325> A_IWL<2324> A_IWL<2323> A_IWL<2322> A_IWL<2321> A_IWL<2320> A_IWL<2319> A_IWL<2318> A_IWL<2317> A_IWL<2316> A_IWL<2315> A_IWL<2314> A_IWL<2313> A_IWL<2312> A_IWL<2311> A_IWL<2310> A_IWL<2309> A_IWL<2308> A_IWL<2307> A_IWL<2306> A_IWL<2305> A_IWL<2304> A_IWL<2303> A_IWL<2302> A_IWL<2301> A_IWL<2300> A_IWL<2299> A_IWL<2298> A_IWL<2297> A_IWL<2296> A_IWL<2295> A_IWL<2294> A_IWL<2293> A_IWL<2292> A_IWL<2291> A_IWL<2290> A_IWL<2289> A_IWL<2288> A_IWL<2287> A_IWL<2286> A_IWL<2285> A_IWL<2284> A_IWL<2283> A_IWL<2282> A_IWL<2281> A_IWL<2280> A_IWL<2279> A_IWL<2278> A_IWL<2277> A_IWL<2276> A_IWL<2275> A_IWL<2274> A_IWL<2273> A_IWL<2272> A_IWL<2271> A_IWL<2270> A_IWL<2269> A_IWL<2268> A_IWL<2267> A_IWL<2266> A_IWL<2265> A_IWL<2264> A_IWL<2263> A_IWL<2262> A_IWL<2261> A_IWL<2260> A_IWL<2259> A_IWL<2258> A_IWL<2257> A_IWL<2256> A_IWL<2255> A_IWL<2254> A_IWL<2253> A_IWL<2252> A_IWL<2251> A_IWL<2250> A_IWL<2249> A_IWL<2248> A_IWL<2247> A_IWL<2246> A_IWL<2245> A_IWL<2244> A_IWL<2243> A_IWL<2242> A_IWL<2241> A_IWL<2240> A_IWL<2239> A_IWL<2238> A_IWL<2237> A_IWL<2236> A_IWL<2235> A_IWL<2234> A_IWL<2233> A_IWL<2232> A_IWL<2231> A_IWL<2230> A_IWL<2229> A_IWL<2228> A_IWL<2227> A_IWL<2226> A_IWL<2225> A_IWL<2224> A_IWL<2223> A_IWL<2222> A_IWL<2221> A_IWL<2220> A_IWL<2219> A_IWL<2218> A_IWL<2217> A_IWL<2216> A_IWL<2215> A_IWL<2214> A_IWL<2213> A_IWL<2212> A_IWL<2211> A_IWL<2210> A_IWL<2209> A_IWL<2208> A_IWL<2207> A_IWL<2206> A_IWL<2205> A_IWL<2204> A_IWL<2203> A_IWL<2202> A_IWL<2201> A_IWL<2200> A_IWL<2199> A_IWL<2198> A_IWL<2197> A_IWL<2196> A_IWL<2195> A_IWL<2194> A_IWL<2193> A_IWL<2192> A_IWL<2191> A_IWL<2190> A_IWL<2189> A_IWL<2188> A_IWL<2187> A_IWL<2186> A_IWL<2185> A_IWL<2184> A_IWL<2183> A_IWL<2182> A_IWL<2181> A_IWL<2180> A_IWL<2179> A_IWL<2178> A_IWL<2177> A_IWL<2176> A_IWL<2175> A_IWL<2174> A_IWL<2173> A_IWL<2172> A_IWL<2171> A_IWL<2170> A_IWL<2169> A_IWL<2168> A_IWL<2167> A_IWL<2166> A_IWL<2165> A_IWL<2164> A_IWL<2163> A_IWL<2162> A_IWL<2161> A_IWL<2160> A_IWL<2159> A_IWL<2158> A_IWL<2157> A_IWL<2156> A_IWL<2155> A_IWL<2154> A_IWL<2153> A_IWL<2152> A_IWL<2151> A_IWL<2150> A_IWL<2149> A_IWL<2148> A_IWL<2147> A_IWL<2146> A_IWL<2145> A_IWL<2144> A_IWL<2143> A_IWL<2142> A_IWL<2141> A_IWL<2140> A_IWL<2139> A_IWL<2138> A_IWL<2137> A_IWL<2136> A_IWL<2135> A_IWL<2134> A_IWL<2133> A_IWL<2132> A_IWL<2131> A_IWL<2130> A_IWL<2129> A_IWL<2128> A_IWL<2127> A_IWL<2126> A_IWL<2125> A_IWL<2124> A_IWL<2123> A_IWL<2122> A_IWL<2121> A_IWL<2120> A_IWL<2119> A_IWL<2118> A_IWL<2117> A_IWL<2116> A_IWL<2115> A_IWL<2114> A_IWL<2113> A_IWL<2112> A_IWL<2111> A_IWL<2110> A_IWL<2109> A_IWL<2108> A_IWL<2107> A_IWL<2106> A_IWL<2105> A_IWL<2104> A_IWL<2103> A_IWL<2102> A_IWL<2101> A_IWL<2100> A_IWL<2099> A_IWL<2098> A_IWL<2097> A_IWL<2096> A_IWL<2095> A_IWL<2094> A_IWL<2093> A_IWL<2092> A_IWL<2091> A_IWL<2090> A_IWL<2089> A_IWL<2088> A_IWL<2087> A_IWL<2086> A_IWL<2085> A_IWL<2084> A_IWL<2083> A_IWL<2082> A_IWL<2081> A_IWL<2080> A_IWL<2079> A_IWL<2078> A_IWL<2077> A_IWL<2076> A_IWL<2075> A_IWL<2074> A_IWL<2073> A_IWL<2072> A_IWL<2071> A_IWL<2070> A_IWL<2069> A_IWL<2068> A_IWL<2067> A_IWL<2066> A_IWL<2065> A_IWL<2064> A_IWL<2063> A_IWL<2062> A_IWL<2061> A_IWL<2060> A_IWL<2059> A_IWL<2058> A_IWL<2057> A_IWL<2056> A_IWL<2055> A_IWL<2054> A_IWL<2053> A_IWL<2052> A_IWL<2051> A_IWL<2050> A_IWL<2049> A_IWL<2048> A_IWL<3071> A_IWL<3070> A_IWL<3069> A_IWL<3068> A_IWL<3067> A_IWL<3066> A_IWL<3065> A_IWL<3064> A_IWL<3063> A_IWL<3062> A_IWL<3061> A_IWL<3060> A_IWL<3059> A_IWL<3058> A_IWL<3057> A_IWL<3056> A_IWL<3055> A_IWL<3054> A_IWL<3053> A_IWL<3052> A_IWL<3051> A_IWL<3050> A_IWL<3049> A_IWL<3048> A_IWL<3047> A_IWL<3046> A_IWL<3045> A_IWL<3044> A_IWL<3043> A_IWL<3042> A_IWL<3041> A_IWL<3040> A_IWL<3039> A_IWL<3038> A_IWL<3037> A_IWL<3036> A_IWL<3035> A_IWL<3034> A_IWL<3033> A_IWL<3032> A_IWL<3031> A_IWL<3030> A_IWL<3029> A_IWL<3028> A_IWL<3027> A_IWL<3026> A_IWL<3025> A_IWL<3024> A_IWL<3023> A_IWL<3022> A_IWL<3021> A_IWL<3020> A_IWL<3019> A_IWL<3018> A_IWL<3017> A_IWL<3016> A_IWL<3015> A_IWL<3014> A_IWL<3013> A_IWL<3012> A_IWL<3011> A_IWL<3010> A_IWL<3009> A_IWL<3008> A_IWL<3007> A_IWL<3006> A_IWL<3005> A_IWL<3004> A_IWL<3003> A_IWL<3002> A_IWL<3001> A_IWL<3000> A_IWL<2999> A_IWL<2998> A_IWL<2997> A_IWL<2996> A_IWL<2995> A_IWL<2994> A_IWL<2993> A_IWL<2992> A_IWL<2991> A_IWL<2990> A_IWL<2989> A_IWL<2988> A_IWL<2987> A_IWL<2986> A_IWL<2985> A_IWL<2984> A_IWL<2983> A_IWL<2982> A_IWL<2981> A_IWL<2980> A_IWL<2979> A_IWL<2978> A_IWL<2977> A_IWL<2976> A_IWL<2975> A_IWL<2974> A_IWL<2973> A_IWL<2972> A_IWL<2971> A_IWL<2970> A_IWL<2969> A_IWL<2968> A_IWL<2967> A_IWL<2966> A_IWL<2965> A_IWL<2964> A_IWL<2963> A_IWL<2962> A_IWL<2961> A_IWL<2960> A_IWL<2959> A_IWL<2958> A_IWL<2957> A_IWL<2956> A_IWL<2955> A_IWL<2954> A_IWL<2953> A_IWL<2952> A_IWL<2951> A_IWL<2950> A_IWL<2949> A_IWL<2948> A_IWL<2947> A_IWL<2946> A_IWL<2945> A_IWL<2944> A_IWL<2943> A_IWL<2942> A_IWL<2941> A_IWL<2940> A_IWL<2939> A_IWL<2938> A_IWL<2937> A_IWL<2936> A_IWL<2935> A_IWL<2934> A_IWL<2933> A_IWL<2932> A_IWL<2931> A_IWL<2930> A_IWL<2929> A_IWL<2928> A_IWL<2927> A_IWL<2926> A_IWL<2925> A_IWL<2924> A_IWL<2923> A_IWL<2922> A_IWL<2921> A_IWL<2920> A_IWL<2919> A_IWL<2918> A_IWL<2917> A_IWL<2916> A_IWL<2915> A_IWL<2914> A_IWL<2913> A_IWL<2912> A_IWL<2911> A_IWL<2910> A_IWL<2909> A_IWL<2908> A_IWL<2907> A_IWL<2906> A_IWL<2905> A_IWL<2904> A_IWL<2903> A_IWL<2902> A_IWL<2901> A_IWL<2900> A_IWL<2899> A_IWL<2898> A_IWL<2897> A_IWL<2896> A_IWL<2895> A_IWL<2894> A_IWL<2893> A_IWL<2892> A_IWL<2891> A_IWL<2890> A_IWL<2889> A_IWL<2888> A_IWL<2887> A_IWL<2886> A_IWL<2885> A_IWL<2884> A_IWL<2883> A_IWL<2882> A_IWL<2881> A_IWL<2880> A_IWL<2879> A_IWL<2878> A_IWL<2877> A_IWL<2876> A_IWL<2875> A_IWL<2874> A_IWL<2873> A_IWL<2872> A_IWL<2871> A_IWL<2870> A_IWL<2869> A_IWL<2868> A_IWL<2867> A_IWL<2866> A_IWL<2865> A_IWL<2864> A_IWL<2863> A_IWL<2862> A_IWL<2861> A_IWL<2860> A_IWL<2859> A_IWL<2858> A_IWL<2857> A_IWL<2856> A_IWL<2855> A_IWL<2854> A_IWL<2853> A_IWL<2852> A_IWL<2851> A_IWL<2850> A_IWL<2849> A_IWL<2848> A_IWL<2847> A_IWL<2846> A_IWL<2845> A_IWL<2844> A_IWL<2843> A_IWL<2842> A_IWL<2841> A_IWL<2840> A_IWL<2839> A_IWL<2838> A_IWL<2837> A_IWL<2836> A_IWL<2835> A_IWL<2834> A_IWL<2833> A_IWL<2832> A_IWL<2831> A_IWL<2830> A_IWL<2829> A_IWL<2828> A_IWL<2827> A_IWL<2826> A_IWL<2825> A_IWL<2824> A_IWL<2823> A_IWL<2822> A_IWL<2821> A_IWL<2820> A_IWL<2819> A_IWL<2818> A_IWL<2817> A_IWL<2816> A_IWL<2815> A_IWL<2814> A_IWL<2813> A_IWL<2812> A_IWL<2811> A_IWL<2810> A_IWL<2809> A_IWL<2808> A_IWL<2807> A_IWL<2806> A_IWL<2805> A_IWL<2804> A_IWL<2803> A_IWL<2802> A_IWL<2801> A_IWL<2800> A_IWL<2799> A_IWL<2798> A_IWL<2797> A_IWL<2796> A_IWL<2795> A_IWL<2794> A_IWL<2793> A_IWL<2792> A_IWL<2791> A_IWL<2790> A_IWL<2789> A_IWL<2788> A_IWL<2787> A_IWL<2786> A_IWL<2785> A_IWL<2784> A_IWL<2783> A_IWL<2782> A_IWL<2781> A_IWL<2780> A_IWL<2779> A_IWL<2778> A_IWL<2777> A_IWL<2776> A_IWL<2775> A_IWL<2774> A_IWL<2773> A_IWL<2772> A_IWL<2771> A_IWL<2770> A_IWL<2769> A_IWL<2768> A_IWL<2767> A_IWL<2766> A_IWL<2765> A_IWL<2764> A_IWL<2763> A_IWL<2762> A_IWL<2761> A_IWL<2760> A_IWL<2759> A_IWL<2758> A_IWL<2757> A_IWL<2756> A_IWL<2755> A_IWL<2754> A_IWL<2753> A_IWL<2752> A_IWL<2751> A_IWL<2750> A_IWL<2749> A_IWL<2748> A_IWL<2747> A_IWL<2746> A_IWL<2745> A_IWL<2744> A_IWL<2743> A_IWL<2742> A_IWL<2741> A_IWL<2740> A_IWL<2739> A_IWL<2738> A_IWL<2737> A_IWL<2736> A_IWL<2735> A_IWL<2734> A_IWL<2733> A_IWL<2732> A_IWL<2731> A_IWL<2730> A_IWL<2729> A_IWL<2728> A_IWL<2727> A_IWL<2726> A_IWL<2725> A_IWL<2724> A_IWL<2723> A_IWL<2722> A_IWL<2721> A_IWL<2720> A_IWL<2719> A_IWL<2718> A_IWL<2717> A_IWL<2716> A_IWL<2715> A_IWL<2714> A_IWL<2713> A_IWL<2712> A_IWL<2711> A_IWL<2710> A_IWL<2709> A_IWL<2708> A_IWL<2707> A_IWL<2706> A_IWL<2705> A_IWL<2704> A_IWL<2703> A_IWL<2702> A_IWL<2701> A_IWL<2700> A_IWL<2699> A_IWL<2698> A_IWL<2697> A_IWL<2696> A_IWL<2695> A_IWL<2694> A_IWL<2693> A_IWL<2692> A_IWL<2691> A_IWL<2690> A_IWL<2689> A_IWL<2688> A_IWL<2687> A_IWL<2686> A_IWL<2685> A_IWL<2684> A_IWL<2683> A_IWL<2682> A_IWL<2681> A_IWL<2680> A_IWL<2679> A_IWL<2678> A_IWL<2677> A_IWL<2676> A_IWL<2675> A_IWL<2674> A_IWL<2673> A_IWL<2672> A_IWL<2671> A_IWL<2670> A_IWL<2669> A_IWL<2668> A_IWL<2667> A_IWL<2666> A_IWL<2665> A_IWL<2664> A_IWL<2663> A_IWL<2662> A_IWL<2661> A_IWL<2660> A_IWL<2659> A_IWL<2658> A_IWL<2657> A_IWL<2656> A_IWL<2655> A_IWL<2654> A_IWL<2653> A_IWL<2652> A_IWL<2651> A_IWL<2650> A_IWL<2649> A_IWL<2648> A_IWL<2647> A_IWL<2646> A_IWL<2645> A_IWL<2644> A_IWL<2643> A_IWL<2642> A_IWL<2641> A_IWL<2640> A_IWL<2639> A_IWL<2638> A_IWL<2637> A_IWL<2636> A_IWL<2635> A_IWL<2634> A_IWL<2633> A_IWL<2632> A_IWL<2631> A_IWL<2630> A_IWL<2629> A_IWL<2628> A_IWL<2627> A_IWL<2626> A_IWL<2625> A_IWL<2624> A_IWL<2623> A_IWL<2622> A_IWL<2621> A_IWL<2620> A_IWL<2619> A_IWL<2618> A_IWL<2617> A_IWL<2616> A_IWL<2615> A_IWL<2614> A_IWL<2613> A_IWL<2612> A_IWL<2611> A_IWL<2610> A_IWL<2609> A_IWL<2608> A_IWL<2607> A_IWL<2606> A_IWL<2605> A_IWL<2604> A_IWL<2603> A_IWL<2602> A_IWL<2601> A_IWL<2600> A_IWL<2599> A_IWL<2598> A_IWL<2597> A_IWL<2596> A_IWL<2595> A_IWL<2594> A_IWL<2593> A_IWL<2592> A_IWL<2591> A_IWL<2590> A_IWL<2589> A_IWL<2588> A_IWL<2587> A_IWL<2586> A_IWL<2585> A_IWL<2584> A_IWL<2583> A_IWL<2582> A_IWL<2581> A_IWL<2580> A_IWL<2579> A_IWL<2578> A_IWL<2577> A_IWL<2576> A_IWL<2575> A_IWL<2574> A_IWL<2573> A_IWL<2572> A_IWL<2571> A_IWL<2570> A_IWL<2569> A_IWL<2568> A_IWL<2567> A_IWL<2566> A_IWL<2565> A_IWL<2564> A_IWL<2563> A_IWL<2562> A_IWL<2561> A_IWL<2560> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_COLUMN_pcell_0 +XCOL<4> A_BLC<9> A_BLC<8> A_BLC_TOP<9> A_BLC_TOP<8> A_BLT<9> A_BLT<8> A_BLT_TOP<9> A_BLT_TOP<8> A_IWL<2047> A_IWL<2046> A_IWL<2045> A_IWL<2044> A_IWL<2043> A_IWL<2042> A_IWL<2041> A_IWL<2040> A_IWL<2039> A_IWL<2038> A_IWL<2037> A_IWL<2036> A_IWL<2035> A_IWL<2034> A_IWL<2033> A_IWL<2032> A_IWL<2031> A_IWL<2030> A_IWL<2029> A_IWL<2028> A_IWL<2027> A_IWL<2026> A_IWL<2025> A_IWL<2024> A_IWL<2023> A_IWL<2022> A_IWL<2021> A_IWL<2020> A_IWL<2019> A_IWL<2018> A_IWL<2017> A_IWL<2016> A_IWL<2015> A_IWL<2014> A_IWL<2013> A_IWL<2012> A_IWL<2011> A_IWL<2010> A_IWL<2009> A_IWL<2008> A_IWL<2007> A_IWL<2006> A_IWL<2005> A_IWL<2004> A_IWL<2003> A_IWL<2002> A_IWL<2001> A_IWL<2000> A_IWL<1999> A_IWL<1998> A_IWL<1997> A_IWL<1996> A_IWL<1995> A_IWL<1994> A_IWL<1993> A_IWL<1992> A_IWL<1991> A_IWL<1990> A_IWL<1989> A_IWL<1988> A_IWL<1987> A_IWL<1986> A_IWL<1985> A_IWL<1984> A_IWL<1983> A_IWL<1982> A_IWL<1981> A_IWL<1980> A_IWL<1979> A_IWL<1978> A_IWL<1977> A_IWL<1976> A_IWL<1975> A_IWL<1974> A_IWL<1973> A_IWL<1972> A_IWL<1971> A_IWL<1970> A_IWL<1969> A_IWL<1968> A_IWL<1967> A_IWL<1966> A_IWL<1965> A_IWL<1964> A_IWL<1963> A_IWL<1962> A_IWL<1961> A_IWL<1960> A_IWL<1959> A_IWL<1958> A_IWL<1957> A_IWL<1956> A_IWL<1955> A_IWL<1954> A_IWL<1953> A_IWL<1952> A_IWL<1951> A_IWL<1950> A_IWL<1949> A_IWL<1948> A_IWL<1947> A_IWL<1946> A_IWL<1945> A_IWL<1944> A_IWL<1943> A_IWL<1942> A_IWL<1941> A_IWL<1940> A_IWL<1939> A_IWL<1938> A_IWL<1937> A_IWL<1936> A_IWL<1935> A_IWL<1934> A_IWL<1933> A_IWL<1932> A_IWL<1931> A_IWL<1930> A_IWL<1929> A_IWL<1928> A_IWL<1927> A_IWL<1926> A_IWL<1925> A_IWL<1924> A_IWL<1923> A_IWL<1922> A_IWL<1921> A_IWL<1920> A_IWL<1919> A_IWL<1918> A_IWL<1917> A_IWL<1916> A_IWL<1915> A_IWL<1914> A_IWL<1913> A_IWL<1912> A_IWL<1911> A_IWL<1910> A_IWL<1909> A_IWL<1908> A_IWL<1907> A_IWL<1906> A_IWL<1905> A_IWL<1904> A_IWL<1903> A_IWL<1902> A_IWL<1901> A_IWL<1900> A_IWL<1899> A_IWL<1898> A_IWL<1897> A_IWL<1896> A_IWL<1895> A_IWL<1894> A_IWL<1893> A_IWL<1892> A_IWL<1891> A_IWL<1890> A_IWL<1889> A_IWL<1888> A_IWL<1887> A_IWL<1886> A_IWL<1885> A_IWL<1884> A_IWL<1883> A_IWL<1882> A_IWL<1881> A_IWL<1880> A_IWL<1879> A_IWL<1878> A_IWL<1877> A_IWL<1876> A_IWL<1875> A_IWL<1874> A_IWL<1873> A_IWL<1872> A_IWL<1871> A_IWL<1870> A_IWL<1869> A_IWL<1868> A_IWL<1867> A_IWL<1866> A_IWL<1865> A_IWL<1864> A_IWL<1863> A_IWL<1862> A_IWL<1861> A_IWL<1860> A_IWL<1859> A_IWL<1858> A_IWL<1857> A_IWL<1856> A_IWL<1855> A_IWL<1854> A_IWL<1853> A_IWL<1852> A_IWL<1851> A_IWL<1850> A_IWL<1849> A_IWL<1848> A_IWL<1847> A_IWL<1846> A_IWL<1845> A_IWL<1844> A_IWL<1843> A_IWL<1842> A_IWL<1841> A_IWL<1840> A_IWL<1839> A_IWL<1838> A_IWL<1837> A_IWL<1836> A_IWL<1835> A_IWL<1834> A_IWL<1833> A_IWL<1832> A_IWL<1831> A_IWL<1830> A_IWL<1829> A_IWL<1828> A_IWL<1827> A_IWL<1826> A_IWL<1825> A_IWL<1824> A_IWL<1823> A_IWL<1822> A_IWL<1821> A_IWL<1820> A_IWL<1819> A_IWL<1818> A_IWL<1817> A_IWL<1816> A_IWL<1815> A_IWL<1814> A_IWL<1813> A_IWL<1812> A_IWL<1811> A_IWL<1810> A_IWL<1809> A_IWL<1808> A_IWL<1807> A_IWL<1806> A_IWL<1805> A_IWL<1804> A_IWL<1803> A_IWL<1802> A_IWL<1801> A_IWL<1800> A_IWL<1799> A_IWL<1798> A_IWL<1797> A_IWL<1796> A_IWL<1795> A_IWL<1794> A_IWL<1793> A_IWL<1792> A_IWL<1791> A_IWL<1790> A_IWL<1789> A_IWL<1788> A_IWL<1787> A_IWL<1786> A_IWL<1785> A_IWL<1784> A_IWL<1783> A_IWL<1782> A_IWL<1781> A_IWL<1780> A_IWL<1779> A_IWL<1778> A_IWL<1777> A_IWL<1776> A_IWL<1775> A_IWL<1774> A_IWL<1773> A_IWL<1772> A_IWL<1771> A_IWL<1770> A_IWL<1769> A_IWL<1768> A_IWL<1767> A_IWL<1766> A_IWL<1765> A_IWL<1764> A_IWL<1763> A_IWL<1762> A_IWL<1761> A_IWL<1760> A_IWL<1759> A_IWL<1758> A_IWL<1757> A_IWL<1756> A_IWL<1755> A_IWL<1754> A_IWL<1753> A_IWL<1752> A_IWL<1751> A_IWL<1750> A_IWL<1749> A_IWL<1748> A_IWL<1747> A_IWL<1746> A_IWL<1745> A_IWL<1744> A_IWL<1743> A_IWL<1742> A_IWL<1741> A_IWL<1740> A_IWL<1739> A_IWL<1738> A_IWL<1737> A_IWL<1736> A_IWL<1735> A_IWL<1734> A_IWL<1733> A_IWL<1732> A_IWL<1731> A_IWL<1730> A_IWL<1729> A_IWL<1728> A_IWL<1727> A_IWL<1726> A_IWL<1725> A_IWL<1724> A_IWL<1723> A_IWL<1722> A_IWL<1721> A_IWL<1720> A_IWL<1719> A_IWL<1718> A_IWL<1717> A_IWL<1716> A_IWL<1715> A_IWL<1714> A_IWL<1713> A_IWL<1712> A_IWL<1711> A_IWL<1710> A_IWL<1709> A_IWL<1708> A_IWL<1707> A_IWL<1706> A_IWL<1705> A_IWL<1704> A_IWL<1703> A_IWL<1702> A_IWL<1701> A_IWL<1700> A_IWL<1699> A_IWL<1698> A_IWL<1697> A_IWL<1696> A_IWL<1695> A_IWL<1694> A_IWL<1693> A_IWL<1692> A_IWL<1691> A_IWL<1690> A_IWL<1689> A_IWL<1688> A_IWL<1687> A_IWL<1686> A_IWL<1685> A_IWL<1684> A_IWL<1683> A_IWL<1682> A_IWL<1681> A_IWL<1680> A_IWL<1679> A_IWL<1678> A_IWL<1677> A_IWL<1676> A_IWL<1675> A_IWL<1674> A_IWL<1673> A_IWL<1672> A_IWL<1671> A_IWL<1670> A_IWL<1669> A_IWL<1668> A_IWL<1667> A_IWL<1666> A_IWL<1665> A_IWL<1664> A_IWL<1663> A_IWL<1662> A_IWL<1661> A_IWL<1660> A_IWL<1659> A_IWL<1658> A_IWL<1657> A_IWL<1656> A_IWL<1655> A_IWL<1654> A_IWL<1653> A_IWL<1652> A_IWL<1651> A_IWL<1650> A_IWL<1649> A_IWL<1648> A_IWL<1647> A_IWL<1646> A_IWL<1645> A_IWL<1644> A_IWL<1643> A_IWL<1642> A_IWL<1641> A_IWL<1640> A_IWL<1639> A_IWL<1638> A_IWL<1637> A_IWL<1636> A_IWL<1635> A_IWL<1634> A_IWL<1633> A_IWL<1632> A_IWL<1631> A_IWL<1630> A_IWL<1629> A_IWL<1628> A_IWL<1627> A_IWL<1626> A_IWL<1625> A_IWL<1624> A_IWL<1623> A_IWL<1622> A_IWL<1621> A_IWL<1620> A_IWL<1619> A_IWL<1618> A_IWL<1617> A_IWL<1616> A_IWL<1615> A_IWL<1614> A_IWL<1613> A_IWL<1612> A_IWL<1611> A_IWL<1610> A_IWL<1609> A_IWL<1608> A_IWL<1607> A_IWL<1606> A_IWL<1605> A_IWL<1604> A_IWL<1603> A_IWL<1602> A_IWL<1601> A_IWL<1600> A_IWL<1599> A_IWL<1598> A_IWL<1597> A_IWL<1596> A_IWL<1595> A_IWL<1594> A_IWL<1593> A_IWL<1592> A_IWL<1591> A_IWL<1590> A_IWL<1589> A_IWL<1588> A_IWL<1587> A_IWL<1586> A_IWL<1585> A_IWL<1584> A_IWL<1583> A_IWL<1582> A_IWL<1581> A_IWL<1580> A_IWL<1579> A_IWL<1578> A_IWL<1577> A_IWL<1576> A_IWL<1575> A_IWL<1574> A_IWL<1573> A_IWL<1572> A_IWL<1571> A_IWL<1570> A_IWL<1569> A_IWL<1568> A_IWL<1567> A_IWL<1566> A_IWL<1565> A_IWL<1564> A_IWL<1563> A_IWL<1562> A_IWL<1561> A_IWL<1560> A_IWL<1559> A_IWL<1558> A_IWL<1557> A_IWL<1556> A_IWL<1555> A_IWL<1554> A_IWL<1553> A_IWL<1552> A_IWL<1551> A_IWL<1550> A_IWL<1549> A_IWL<1548> A_IWL<1547> A_IWL<1546> A_IWL<1545> A_IWL<1544> A_IWL<1543> A_IWL<1542> A_IWL<1541> A_IWL<1540> A_IWL<1539> A_IWL<1538> A_IWL<1537> A_IWL<1536> A_IWL<2559> A_IWL<2558> A_IWL<2557> A_IWL<2556> A_IWL<2555> A_IWL<2554> A_IWL<2553> A_IWL<2552> A_IWL<2551> A_IWL<2550> A_IWL<2549> A_IWL<2548> A_IWL<2547> A_IWL<2546> A_IWL<2545> A_IWL<2544> A_IWL<2543> A_IWL<2542> A_IWL<2541> A_IWL<2540> A_IWL<2539> A_IWL<2538> A_IWL<2537> A_IWL<2536> A_IWL<2535> A_IWL<2534> A_IWL<2533> A_IWL<2532> A_IWL<2531> A_IWL<2530> A_IWL<2529> A_IWL<2528> A_IWL<2527> A_IWL<2526> A_IWL<2525> A_IWL<2524> A_IWL<2523> A_IWL<2522> A_IWL<2521> A_IWL<2520> A_IWL<2519> A_IWL<2518> A_IWL<2517> A_IWL<2516> A_IWL<2515> A_IWL<2514> A_IWL<2513> A_IWL<2512> A_IWL<2511> A_IWL<2510> A_IWL<2509> A_IWL<2508> A_IWL<2507> A_IWL<2506> A_IWL<2505> A_IWL<2504> A_IWL<2503> A_IWL<2502> A_IWL<2501> A_IWL<2500> A_IWL<2499> A_IWL<2498> A_IWL<2497> A_IWL<2496> A_IWL<2495> A_IWL<2494> A_IWL<2493> A_IWL<2492> A_IWL<2491> A_IWL<2490> A_IWL<2489> A_IWL<2488> A_IWL<2487> A_IWL<2486> A_IWL<2485> A_IWL<2484> A_IWL<2483> A_IWL<2482> A_IWL<2481> A_IWL<2480> A_IWL<2479> A_IWL<2478> A_IWL<2477> A_IWL<2476> A_IWL<2475> A_IWL<2474> A_IWL<2473> A_IWL<2472> A_IWL<2471> A_IWL<2470> A_IWL<2469> A_IWL<2468> A_IWL<2467> A_IWL<2466> A_IWL<2465> A_IWL<2464> A_IWL<2463> A_IWL<2462> A_IWL<2461> A_IWL<2460> A_IWL<2459> A_IWL<2458> A_IWL<2457> A_IWL<2456> A_IWL<2455> A_IWL<2454> A_IWL<2453> A_IWL<2452> A_IWL<2451> A_IWL<2450> A_IWL<2449> A_IWL<2448> A_IWL<2447> A_IWL<2446> A_IWL<2445> A_IWL<2444> A_IWL<2443> A_IWL<2442> A_IWL<2441> A_IWL<2440> A_IWL<2439> A_IWL<2438> A_IWL<2437> A_IWL<2436> A_IWL<2435> A_IWL<2434> A_IWL<2433> A_IWL<2432> A_IWL<2431> A_IWL<2430> A_IWL<2429> A_IWL<2428> A_IWL<2427> A_IWL<2426> A_IWL<2425> A_IWL<2424> A_IWL<2423> A_IWL<2422> A_IWL<2421> A_IWL<2420> A_IWL<2419> A_IWL<2418> A_IWL<2417> A_IWL<2416> A_IWL<2415> A_IWL<2414> A_IWL<2413> A_IWL<2412> A_IWL<2411> A_IWL<2410> A_IWL<2409> A_IWL<2408> A_IWL<2407> A_IWL<2406> A_IWL<2405> A_IWL<2404> A_IWL<2403> A_IWL<2402> A_IWL<2401> A_IWL<2400> A_IWL<2399> A_IWL<2398> A_IWL<2397> A_IWL<2396> A_IWL<2395> A_IWL<2394> A_IWL<2393> A_IWL<2392> A_IWL<2391> A_IWL<2390> A_IWL<2389> A_IWL<2388> A_IWL<2387> A_IWL<2386> A_IWL<2385> A_IWL<2384> A_IWL<2383> A_IWL<2382> A_IWL<2381> A_IWL<2380> A_IWL<2379> A_IWL<2378> A_IWL<2377> A_IWL<2376> A_IWL<2375> A_IWL<2374> A_IWL<2373> A_IWL<2372> A_IWL<2371> A_IWL<2370> A_IWL<2369> A_IWL<2368> A_IWL<2367> A_IWL<2366> A_IWL<2365> A_IWL<2364> A_IWL<2363> A_IWL<2362> A_IWL<2361> A_IWL<2360> A_IWL<2359> A_IWL<2358> A_IWL<2357> A_IWL<2356> A_IWL<2355> A_IWL<2354> A_IWL<2353> A_IWL<2352> A_IWL<2351> A_IWL<2350> A_IWL<2349> A_IWL<2348> A_IWL<2347> A_IWL<2346> A_IWL<2345> A_IWL<2344> A_IWL<2343> A_IWL<2342> A_IWL<2341> A_IWL<2340> A_IWL<2339> A_IWL<2338> A_IWL<2337> A_IWL<2336> A_IWL<2335> A_IWL<2334> A_IWL<2333> A_IWL<2332> A_IWL<2331> A_IWL<2330> A_IWL<2329> A_IWL<2328> A_IWL<2327> A_IWL<2326> A_IWL<2325> A_IWL<2324> A_IWL<2323> A_IWL<2322> A_IWL<2321> A_IWL<2320> A_IWL<2319> A_IWL<2318> A_IWL<2317> A_IWL<2316> A_IWL<2315> A_IWL<2314> A_IWL<2313> A_IWL<2312> A_IWL<2311> A_IWL<2310> A_IWL<2309> A_IWL<2308> A_IWL<2307> A_IWL<2306> A_IWL<2305> A_IWL<2304> A_IWL<2303> A_IWL<2302> A_IWL<2301> A_IWL<2300> A_IWL<2299> A_IWL<2298> A_IWL<2297> A_IWL<2296> A_IWL<2295> A_IWL<2294> A_IWL<2293> A_IWL<2292> A_IWL<2291> A_IWL<2290> A_IWL<2289> A_IWL<2288> A_IWL<2287> A_IWL<2286> A_IWL<2285> A_IWL<2284> A_IWL<2283> A_IWL<2282> A_IWL<2281> A_IWL<2280> A_IWL<2279> A_IWL<2278> A_IWL<2277> A_IWL<2276> A_IWL<2275> A_IWL<2274> A_IWL<2273> A_IWL<2272> A_IWL<2271> A_IWL<2270> A_IWL<2269> A_IWL<2268> A_IWL<2267> A_IWL<2266> A_IWL<2265> A_IWL<2264> A_IWL<2263> A_IWL<2262> A_IWL<2261> A_IWL<2260> A_IWL<2259> A_IWL<2258> A_IWL<2257> A_IWL<2256> A_IWL<2255> A_IWL<2254> A_IWL<2253> A_IWL<2252> A_IWL<2251> A_IWL<2250> A_IWL<2249> A_IWL<2248> A_IWL<2247> A_IWL<2246> A_IWL<2245> A_IWL<2244> A_IWL<2243> A_IWL<2242> A_IWL<2241> A_IWL<2240> A_IWL<2239> A_IWL<2238> A_IWL<2237> A_IWL<2236> A_IWL<2235> A_IWL<2234> A_IWL<2233> A_IWL<2232> A_IWL<2231> A_IWL<2230> A_IWL<2229> A_IWL<2228> A_IWL<2227> A_IWL<2226> A_IWL<2225> A_IWL<2224> A_IWL<2223> A_IWL<2222> A_IWL<2221> A_IWL<2220> A_IWL<2219> A_IWL<2218> A_IWL<2217> A_IWL<2216> A_IWL<2215> A_IWL<2214> A_IWL<2213> A_IWL<2212> A_IWL<2211> A_IWL<2210> A_IWL<2209> A_IWL<2208> A_IWL<2207> A_IWL<2206> A_IWL<2205> A_IWL<2204> A_IWL<2203> A_IWL<2202> A_IWL<2201> A_IWL<2200> A_IWL<2199> A_IWL<2198> A_IWL<2197> A_IWL<2196> A_IWL<2195> A_IWL<2194> A_IWL<2193> A_IWL<2192> A_IWL<2191> A_IWL<2190> A_IWL<2189> A_IWL<2188> A_IWL<2187> A_IWL<2186> A_IWL<2185> A_IWL<2184> A_IWL<2183> A_IWL<2182> A_IWL<2181> A_IWL<2180> A_IWL<2179> A_IWL<2178> A_IWL<2177> A_IWL<2176> A_IWL<2175> A_IWL<2174> A_IWL<2173> A_IWL<2172> A_IWL<2171> A_IWL<2170> A_IWL<2169> A_IWL<2168> A_IWL<2167> A_IWL<2166> A_IWL<2165> A_IWL<2164> A_IWL<2163> A_IWL<2162> A_IWL<2161> A_IWL<2160> A_IWL<2159> A_IWL<2158> A_IWL<2157> A_IWL<2156> A_IWL<2155> A_IWL<2154> A_IWL<2153> A_IWL<2152> A_IWL<2151> A_IWL<2150> A_IWL<2149> A_IWL<2148> A_IWL<2147> A_IWL<2146> A_IWL<2145> A_IWL<2144> A_IWL<2143> A_IWL<2142> A_IWL<2141> A_IWL<2140> A_IWL<2139> A_IWL<2138> A_IWL<2137> A_IWL<2136> A_IWL<2135> A_IWL<2134> A_IWL<2133> A_IWL<2132> A_IWL<2131> A_IWL<2130> A_IWL<2129> A_IWL<2128> A_IWL<2127> A_IWL<2126> A_IWL<2125> A_IWL<2124> A_IWL<2123> A_IWL<2122> A_IWL<2121> A_IWL<2120> A_IWL<2119> A_IWL<2118> A_IWL<2117> A_IWL<2116> A_IWL<2115> A_IWL<2114> A_IWL<2113> A_IWL<2112> A_IWL<2111> A_IWL<2110> A_IWL<2109> A_IWL<2108> A_IWL<2107> A_IWL<2106> A_IWL<2105> A_IWL<2104> A_IWL<2103> A_IWL<2102> A_IWL<2101> A_IWL<2100> A_IWL<2099> A_IWL<2098> A_IWL<2097> A_IWL<2096> A_IWL<2095> A_IWL<2094> A_IWL<2093> A_IWL<2092> A_IWL<2091> A_IWL<2090> A_IWL<2089> A_IWL<2088> A_IWL<2087> A_IWL<2086> A_IWL<2085> A_IWL<2084> A_IWL<2083> A_IWL<2082> A_IWL<2081> A_IWL<2080> A_IWL<2079> A_IWL<2078> A_IWL<2077> A_IWL<2076> A_IWL<2075> A_IWL<2074> A_IWL<2073> A_IWL<2072> A_IWL<2071> A_IWL<2070> A_IWL<2069> A_IWL<2068> A_IWL<2067> A_IWL<2066> A_IWL<2065> A_IWL<2064> A_IWL<2063> A_IWL<2062> A_IWL<2061> A_IWL<2060> A_IWL<2059> A_IWL<2058> A_IWL<2057> A_IWL<2056> A_IWL<2055> A_IWL<2054> A_IWL<2053> A_IWL<2052> A_IWL<2051> A_IWL<2050> A_IWL<2049> A_IWL<2048> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_COLUMN_pcell_0 +XCOL<3> A_BLC<7> A_BLC<6> A_BLC_TOP<7> A_BLC_TOP<6> A_BLT<7> A_BLT<6> A_BLT_TOP<7> A_BLT_TOP<6> A_IWL<1535> A_IWL<1534> A_IWL<1533> A_IWL<1532> A_IWL<1531> A_IWL<1530> A_IWL<1529> A_IWL<1528> A_IWL<1527> A_IWL<1526> A_IWL<1525> A_IWL<1524> A_IWL<1523> A_IWL<1522> A_IWL<1521> A_IWL<1520> A_IWL<1519> A_IWL<1518> A_IWL<1517> A_IWL<1516> A_IWL<1515> A_IWL<1514> A_IWL<1513> A_IWL<1512> A_IWL<1511> A_IWL<1510> A_IWL<1509> A_IWL<1508> A_IWL<1507> A_IWL<1506> A_IWL<1505> A_IWL<1504> A_IWL<1503> A_IWL<1502> A_IWL<1501> A_IWL<1500> A_IWL<1499> A_IWL<1498> A_IWL<1497> A_IWL<1496> A_IWL<1495> A_IWL<1494> A_IWL<1493> A_IWL<1492> A_IWL<1491> A_IWL<1490> A_IWL<1489> A_IWL<1488> A_IWL<1487> A_IWL<1486> A_IWL<1485> A_IWL<1484> A_IWL<1483> A_IWL<1482> A_IWL<1481> A_IWL<1480> A_IWL<1479> A_IWL<1478> A_IWL<1477> A_IWL<1476> A_IWL<1475> A_IWL<1474> A_IWL<1473> A_IWL<1472> A_IWL<1471> A_IWL<1470> A_IWL<1469> A_IWL<1468> A_IWL<1467> A_IWL<1466> A_IWL<1465> A_IWL<1464> A_IWL<1463> A_IWL<1462> A_IWL<1461> A_IWL<1460> A_IWL<1459> A_IWL<1458> A_IWL<1457> A_IWL<1456> A_IWL<1455> A_IWL<1454> A_IWL<1453> A_IWL<1452> A_IWL<1451> A_IWL<1450> A_IWL<1449> A_IWL<1448> A_IWL<1447> A_IWL<1446> A_IWL<1445> A_IWL<1444> A_IWL<1443> A_IWL<1442> A_IWL<1441> A_IWL<1440> A_IWL<1439> A_IWL<1438> A_IWL<1437> A_IWL<1436> A_IWL<1435> A_IWL<1434> A_IWL<1433> A_IWL<1432> A_IWL<1431> A_IWL<1430> A_IWL<1429> A_IWL<1428> A_IWL<1427> A_IWL<1426> A_IWL<1425> A_IWL<1424> A_IWL<1423> A_IWL<1422> A_IWL<1421> A_IWL<1420> A_IWL<1419> A_IWL<1418> A_IWL<1417> A_IWL<1416> A_IWL<1415> A_IWL<1414> A_IWL<1413> A_IWL<1412> A_IWL<1411> A_IWL<1410> A_IWL<1409> A_IWL<1408> A_IWL<1407> A_IWL<1406> A_IWL<1405> A_IWL<1404> A_IWL<1403> A_IWL<1402> A_IWL<1401> A_IWL<1400> A_IWL<1399> A_IWL<1398> A_IWL<1397> A_IWL<1396> A_IWL<1395> A_IWL<1394> A_IWL<1393> A_IWL<1392> A_IWL<1391> A_IWL<1390> A_IWL<1389> A_IWL<1388> A_IWL<1387> A_IWL<1386> A_IWL<1385> A_IWL<1384> A_IWL<1383> A_IWL<1382> A_IWL<1381> A_IWL<1380> A_IWL<1379> A_IWL<1378> A_IWL<1377> A_IWL<1376> A_IWL<1375> A_IWL<1374> A_IWL<1373> A_IWL<1372> A_IWL<1371> A_IWL<1370> A_IWL<1369> A_IWL<1368> A_IWL<1367> A_IWL<1366> A_IWL<1365> A_IWL<1364> A_IWL<1363> A_IWL<1362> A_IWL<1361> A_IWL<1360> A_IWL<1359> A_IWL<1358> A_IWL<1357> A_IWL<1356> A_IWL<1355> A_IWL<1354> A_IWL<1353> A_IWL<1352> A_IWL<1351> A_IWL<1350> A_IWL<1349> A_IWL<1348> A_IWL<1347> A_IWL<1346> A_IWL<1345> A_IWL<1344> A_IWL<1343> A_IWL<1342> A_IWL<1341> A_IWL<1340> A_IWL<1339> A_IWL<1338> A_IWL<1337> A_IWL<1336> A_IWL<1335> A_IWL<1334> A_IWL<1333> A_IWL<1332> A_IWL<1331> A_IWL<1330> A_IWL<1329> A_IWL<1328> A_IWL<1327> A_IWL<1326> A_IWL<1325> A_IWL<1324> A_IWL<1323> A_IWL<1322> A_IWL<1321> A_IWL<1320> A_IWL<1319> A_IWL<1318> A_IWL<1317> A_IWL<1316> A_IWL<1315> A_IWL<1314> A_IWL<1313> A_IWL<1312> A_IWL<1311> A_IWL<1310> A_IWL<1309> A_IWL<1308> A_IWL<1307> A_IWL<1306> A_IWL<1305> A_IWL<1304> A_IWL<1303> A_IWL<1302> A_IWL<1301> A_IWL<1300> A_IWL<1299> A_IWL<1298> A_IWL<1297> A_IWL<1296> A_IWL<1295> A_IWL<1294> A_IWL<1293> A_IWL<1292> A_IWL<1291> A_IWL<1290> A_IWL<1289> A_IWL<1288> A_IWL<1287> A_IWL<1286> A_IWL<1285> A_IWL<1284> A_IWL<1283> A_IWL<1282> A_IWL<1281> A_IWL<1280> A_IWL<1279> A_IWL<1278> A_IWL<1277> A_IWL<1276> A_IWL<1275> A_IWL<1274> A_IWL<1273> A_IWL<1272> A_IWL<1271> A_IWL<1270> A_IWL<1269> A_IWL<1268> A_IWL<1267> A_IWL<1266> A_IWL<1265> A_IWL<1264> A_IWL<1263> A_IWL<1262> A_IWL<1261> A_IWL<1260> A_IWL<1259> A_IWL<1258> A_IWL<1257> A_IWL<1256> A_IWL<1255> A_IWL<1254> A_IWL<1253> A_IWL<1252> A_IWL<1251> A_IWL<1250> A_IWL<1249> A_IWL<1248> A_IWL<1247> A_IWL<1246> A_IWL<1245> A_IWL<1244> A_IWL<1243> A_IWL<1242> A_IWL<1241> A_IWL<1240> A_IWL<1239> A_IWL<1238> A_IWL<1237> A_IWL<1236> A_IWL<1235> A_IWL<1234> A_IWL<1233> A_IWL<1232> A_IWL<1231> A_IWL<1230> A_IWL<1229> A_IWL<1228> A_IWL<1227> A_IWL<1226> A_IWL<1225> A_IWL<1224> A_IWL<1223> A_IWL<1222> A_IWL<1221> A_IWL<1220> A_IWL<1219> A_IWL<1218> A_IWL<1217> A_IWL<1216> A_IWL<1215> A_IWL<1214> A_IWL<1213> A_IWL<1212> A_IWL<1211> A_IWL<1210> A_IWL<1209> A_IWL<1208> A_IWL<1207> A_IWL<1206> A_IWL<1205> A_IWL<1204> A_IWL<1203> A_IWL<1202> A_IWL<1201> A_IWL<1200> A_IWL<1199> A_IWL<1198> A_IWL<1197> A_IWL<1196> A_IWL<1195> A_IWL<1194> A_IWL<1193> A_IWL<1192> A_IWL<1191> A_IWL<1190> A_IWL<1189> A_IWL<1188> A_IWL<1187> A_IWL<1186> A_IWL<1185> A_IWL<1184> A_IWL<1183> A_IWL<1182> A_IWL<1181> A_IWL<1180> A_IWL<1179> A_IWL<1178> A_IWL<1177> A_IWL<1176> A_IWL<1175> A_IWL<1174> A_IWL<1173> A_IWL<1172> A_IWL<1171> A_IWL<1170> A_IWL<1169> A_IWL<1168> A_IWL<1167> A_IWL<1166> A_IWL<1165> A_IWL<1164> A_IWL<1163> A_IWL<1162> A_IWL<1161> A_IWL<1160> A_IWL<1159> A_IWL<1158> A_IWL<1157> A_IWL<1156> A_IWL<1155> A_IWL<1154> A_IWL<1153> A_IWL<1152> A_IWL<1151> A_IWL<1150> A_IWL<1149> A_IWL<1148> A_IWL<1147> A_IWL<1146> A_IWL<1145> A_IWL<1144> A_IWL<1143> A_IWL<1142> A_IWL<1141> A_IWL<1140> A_IWL<1139> A_IWL<1138> A_IWL<1137> A_IWL<1136> A_IWL<1135> A_IWL<1134> A_IWL<1133> A_IWL<1132> A_IWL<1131> A_IWL<1130> A_IWL<1129> A_IWL<1128> A_IWL<1127> A_IWL<1126> A_IWL<1125> A_IWL<1124> A_IWL<1123> A_IWL<1122> A_IWL<1121> A_IWL<1120> A_IWL<1119> A_IWL<1118> A_IWL<1117> A_IWL<1116> A_IWL<1115> A_IWL<1114> A_IWL<1113> A_IWL<1112> A_IWL<1111> A_IWL<1110> A_IWL<1109> A_IWL<1108> A_IWL<1107> A_IWL<1106> A_IWL<1105> A_IWL<1104> A_IWL<1103> A_IWL<1102> A_IWL<1101> A_IWL<1100> A_IWL<1099> A_IWL<1098> A_IWL<1097> A_IWL<1096> A_IWL<1095> A_IWL<1094> A_IWL<1093> A_IWL<1092> A_IWL<1091> A_IWL<1090> A_IWL<1089> A_IWL<1088> A_IWL<1087> A_IWL<1086> A_IWL<1085> A_IWL<1084> A_IWL<1083> A_IWL<1082> A_IWL<1081> A_IWL<1080> A_IWL<1079> A_IWL<1078> A_IWL<1077> A_IWL<1076> A_IWL<1075> A_IWL<1074> A_IWL<1073> A_IWL<1072> A_IWL<1071> A_IWL<1070> A_IWL<1069> A_IWL<1068> A_IWL<1067> A_IWL<1066> A_IWL<1065> A_IWL<1064> A_IWL<1063> A_IWL<1062> A_IWL<1061> A_IWL<1060> A_IWL<1059> A_IWL<1058> A_IWL<1057> A_IWL<1056> A_IWL<1055> A_IWL<1054> A_IWL<1053> A_IWL<1052> A_IWL<1051> A_IWL<1050> A_IWL<1049> A_IWL<1048> A_IWL<1047> A_IWL<1046> A_IWL<1045> A_IWL<1044> A_IWL<1043> A_IWL<1042> A_IWL<1041> A_IWL<1040> A_IWL<1039> A_IWL<1038> A_IWL<1037> A_IWL<1036> A_IWL<1035> A_IWL<1034> A_IWL<1033> A_IWL<1032> A_IWL<1031> A_IWL<1030> A_IWL<1029> A_IWL<1028> A_IWL<1027> A_IWL<1026> A_IWL<1025> A_IWL<1024> A_IWL<2047> A_IWL<2046> A_IWL<2045> A_IWL<2044> A_IWL<2043> A_IWL<2042> A_IWL<2041> A_IWL<2040> A_IWL<2039> A_IWL<2038> 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A_IWL<1539> A_IWL<1538> A_IWL<1537> A_IWL<1536> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_COLUMN_pcell_0 +XCOL<2> A_BLC<5> A_BLC<4> A_BLC_TOP<5> A_BLC_TOP<4> A_BLT<5> A_BLT<4> A_BLT_TOP<5> A_BLT_TOP<4> A_IWL<1023> A_IWL<1022> A_IWL<1021> A_IWL<1020> A_IWL<1019> A_IWL<1018> A_IWL<1017> A_IWL<1016> A_IWL<1015> A_IWL<1014> A_IWL<1013> A_IWL<1012> A_IWL<1011> A_IWL<1010> A_IWL<1009> A_IWL<1008> A_IWL<1007> A_IWL<1006> A_IWL<1005> A_IWL<1004> A_IWL<1003> A_IWL<1002> A_IWL<1001> A_IWL<1000> A_IWL<999> A_IWL<998> A_IWL<997> A_IWL<996> A_IWL<995> A_IWL<994> A_IWL<993> A_IWL<992> A_IWL<991> A_IWL<990> A_IWL<989> A_IWL<988> A_IWL<987> A_IWL<986> A_IWL<985> A_IWL<984> A_IWL<983> A_IWL<982> A_IWL<981> A_IWL<980> A_IWL<979> A_IWL<978> A_IWL<977> A_IWL<976> A_IWL<975> A_IWL<974> A_IWL<973> A_IWL<972> A_IWL<971> A_IWL<970> A_IWL<969> A_IWL<968> A_IWL<967> A_IWL<966> A_IWL<965> A_IWL<964> A_IWL<963> A_IWL<962> A_IWL<961> A_IWL<960> A_IWL<959> A_IWL<958> A_IWL<957> A_IWL<956> A_IWL<955> A_IWL<954> A_IWL<953> A_IWL<952> A_IWL<951> A_IWL<950> A_IWL<949> A_IWL<948> A_IWL<947> A_IWL<946> A_IWL<945> A_IWL<944> A_IWL<943> A_IWL<942> A_IWL<941> A_IWL<940> A_IWL<939> A_IWL<938> A_IWL<937> A_IWL<936> A_IWL<935> A_IWL<934> A_IWL<933> A_IWL<932> A_IWL<931> A_IWL<930> A_IWL<929> A_IWL<928> A_IWL<927> A_IWL<926> A_IWL<925> A_IWL<924> A_IWL<923> A_IWL<922> A_IWL<921> A_IWL<920> A_IWL<919> A_IWL<918> A_IWL<917> A_IWL<916> A_IWL<915> A_IWL<914> A_IWL<913> A_IWL<912> A_IWL<911> A_IWL<910> A_IWL<909> A_IWL<908> A_IWL<907> A_IWL<906> A_IWL<905> A_IWL<904> A_IWL<903> A_IWL<902> A_IWL<901> A_IWL<900> A_IWL<899> A_IWL<898> A_IWL<897> A_IWL<896> A_IWL<895> A_IWL<894> A_IWL<893> A_IWL<892> A_IWL<891> A_IWL<890> A_IWL<889> A_IWL<888> A_IWL<887> A_IWL<886> A_IWL<885> A_IWL<884> A_IWL<883> A_IWL<882> A_IWL<881> A_IWL<880> A_IWL<879> A_IWL<878> A_IWL<877> A_IWL<876> A_IWL<875> A_IWL<874> A_IWL<873> A_IWL<872> A_IWL<871> A_IWL<870> A_IWL<869> A_IWL<868> A_IWL<867> A_IWL<866> A_IWL<865> A_IWL<864> A_IWL<863> A_IWL<862> A_IWL<861> A_IWL<860> A_IWL<859> A_IWL<858> A_IWL<857> A_IWL<856> A_IWL<855> A_IWL<854> A_IWL<853> A_IWL<852> A_IWL<851> A_IWL<850> A_IWL<849> A_IWL<848> A_IWL<847> A_IWL<846> A_IWL<845> A_IWL<844> A_IWL<843> A_IWL<842> A_IWL<841> A_IWL<840> A_IWL<839> A_IWL<838> A_IWL<837> A_IWL<836> A_IWL<835> A_IWL<834> A_IWL<833> A_IWL<832> A_IWL<831> A_IWL<830> A_IWL<829> A_IWL<828> A_IWL<827> A_IWL<826> A_IWL<825> A_IWL<824> A_IWL<823> A_IWL<822> A_IWL<821> A_IWL<820> A_IWL<819> A_IWL<818> A_IWL<817> A_IWL<816> A_IWL<815> A_IWL<814> A_IWL<813> A_IWL<812> A_IWL<811> A_IWL<810> A_IWL<809> A_IWL<808> A_IWL<807> A_IWL<806> A_IWL<805> A_IWL<804> A_IWL<803> A_IWL<802> A_IWL<801> A_IWL<800> A_IWL<799> A_IWL<798> A_IWL<797> A_IWL<796> A_IWL<795> A_IWL<794> A_IWL<793> A_IWL<792> A_IWL<791> A_IWL<790> A_IWL<789> A_IWL<788> A_IWL<787> A_IWL<786> A_IWL<785> A_IWL<784> A_IWL<783> A_IWL<782> A_IWL<781> A_IWL<780> A_IWL<779> A_IWL<778> A_IWL<777> A_IWL<776> A_IWL<775> A_IWL<774> A_IWL<773> A_IWL<772> A_IWL<771> A_IWL<770> A_IWL<769> A_IWL<768> A_IWL<767> A_IWL<766> A_IWL<765> A_IWL<764> A_IWL<763> A_IWL<762> A_IWL<761> A_IWL<760> A_IWL<759> A_IWL<758> A_IWL<757> A_IWL<756> A_IWL<755> A_IWL<754> A_IWL<753> A_IWL<752> A_IWL<751> A_IWL<750> A_IWL<749> A_IWL<748> A_IWL<747> A_IWL<746> A_IWL<745> A_IWL<744> A_IWL<743> A_IWL<742> A_IWL<741> A_IWL<740> A_IWL<739> A_IWL<738> A_IWL<737> A_IWL<736> A_IWL<735> A_IWL<734> A_IWL<733> A_IWL<732> A_IWL<731> A_IWL<730> A_IWL<729> A_IWL<728> A_IWL<727> A_IWL<726> A_IWL<725> A_IWL<724> A_IWL<723> A_IWL<722> A_IWL<721> A_IWL<720> A_IWL<719> A_IWL<718> A_IWL<717> A_IWL<716> A_IWL<715> A_IWL<714> A_IWL<713> A_IWL<712> A_IWL<711> A_IWL<710> A_IWL<709> A_IWL<708> A_IWL<707> A_IWL<706> A_IWL<705> A_IWL<704> A_IWL<703> A_IWL<702> A_IWL<701> A_IWL<700> A_IWL<699> A_IWL<698> A_IWL<697> A_IWL<696> A_IWL<695> A_IWL<694> A_IWL<693> A_IWL<692> A_IWL<691> A_IWL<690> A_IWL<689> A_IWL<688> A_IWL<687> A_IWL<686> A_IWL<685> A_IWL<684> A_IWL<683> A_IWL<682> A_IWL<681> A_IWL<680> A_IWL<679> A_IWL<678> A_IWL<677> A_IWL<676> A_IWL<675> A_IWL<674> A_IWL<673> A_IWL<672> A_IWL<671> A_IWL<670> A_IWL<669> A_IWL<668> A_IWL<667> A_IWL<666> A_IWL<665> A_IWL<664> A_IWL<663> A_IWL<662> A_IWL<661> A_IWL<660> A_IWL<659> A_IWL<658> A_IWL<657> A_IWL<656> A_IWL<655> A_IWL<654> A_IWL<653> A_IWL<652> A_IWL<651> A_IWL<650> A_IWL<649> A_IWL<648> A_IWL<647> A_IWL<646> A_IWL<645> A_IWL<644> A_IWL<643> A_IWL<642> A_IWL<641> A_IWL<640> A_IWL<639> A_IWL<638> A_IWL<637> A_IWL<636> A_IWL<635> A_IWL<634> A_IWL<633> A_IWL<632> A_IWL<631> A_IWL<630> A_IWL<629> A_IWL<628> A_IWL<627> A_IWL<626> A_IWL<625> A_IWL<624> A_IWL<623> A_IWL<622> A_IWL<621> A_IWL<620> A_IWL<619> A_IWL<618> A_IWL<617> A_IWL<616> A_IWL<615> A_IWL<614> A_IWL<613> A_IWL<612> A_IWL<611> A_IWL<610> A_IWL<609> A_IWL<608> A_IWL<607> A_IWL<606> A_IWL<605> A_IWL<604> A_IWL<603> A_IWL<602> A_IWL<601> A_IWL<600> A_IWL<599> A_IWL<598> A_IWL<597> A_IWL<596> A_IWL<595> A_IWL<594> A_IWL<593> A_IWL<592> A_IWL<591> A_IWL<590> A_IWL<589> A_IWL<588> A_IWL<587> A_IWL<586> A_IWL<585> A_IWL<584> A_IWL<583> A_IWL<582> A_IWL<581> A_IWL<580> A_IWL<579> A_IWL<578> A_IWL<577> A_IWL<576> A_IWL<575> A_IWL<574> A_IWL<573> A_IWL<572> A_IWL<571> A_IWL<570> A_IWL<569> A_IWL<568> A_IWL<567> A_IWL<566> A_IWL<565> A_IWL<564> A_IWL<563> A_IWL<562> A_IWL<561> A_IWL<560> A_IWL<559> A_IWL<558> A_IWL<557> A_IWL<556> A_IWL<555> A_IWL<554> A_IWL<553> A_IWL<552> A_IWL<551> A_IWL<550> A_IWL<549> A_IWL<548> A_IWL<547> A_IWL<546> A_IWL<545> A_IWL<544> A_IWL<543> A_IWL<542> A_IWL<541> A_IWL<540> A_IWL<539> A_IWL<538> A_IWL<537> A_IWL<536> A_IWL<535> A_IWL<534> A_IWL<533> A_IWL<532> A_IWL<531> A_IWL<530> A_IWL<529> A_IWL<528> A_IWL<527> A_IWL<526> A_IWL<525> A_IWL<524> A_IWL<523> A_IWL<522> A_IWL<521> A_IWL<520> A_IWL<519> A_IWL<518> A_IWL<517> A_IWL<516> A_IWL<515> A_IWL<514> A_IWL<513> A_IWL<512> A_IWL<1535> A_IWL<1534> A_IWL<1533> A_IWL<1532> A_IWL<1531> A_IWL<1530> A_IWL<1529> A_IWL<1528> A_IWL<1527> A_IWL<1526> A_IWL<1525> A_IWL<1524> A_IWL<1523> A_IWL<1522> A_IWL<1521> A_IWL<1520> A_IWL<1519> A_IWL<1518> A_IWL<1517> A_IWL<1516> A_IWL<1515> A_IWL<1514> A_IWL<1513> A_IWL<1512> A_IWL<1511> A_IWL<1510> A_IWL<1509> A_IWL<1508> A_IWL<1507> A_IWL<1506> A_IWL<1505> A_IWL<1504> A_IWL<1503> A_IWL<1502> A_IWL<1501> A_IWL<1500> A_IWL<1499> A_IWL<1498> A_IWL<1497> A_IWL<1496> A_IWL<1495> A_IWL<1494> A_IWL<1493> A_IWL<1492> A_IWL<1491> A_IWL<1490> A_IWL<1489> A_IWL<1488> A_IWL<1487> A_IWL<1486> A_IWL<1485> A_IWL<1484> A_IWL<1483> A_IWL<1482> A_IWL<1481> A_IWL<1480> A_IWL<1479> A_IWL<1478> A_IWL<1477> A_IWL<1476> A_IWL<1475> A_IWL<1474> A_IWL<1473> A_IWL<1472> A_IWL<1471> A_IWL<1470> A_IWL<1469> A_IWL<1468> A_IWL<1467> A_IWL<1466> A_IWL<1465> A_IWL<1464> A_IWL<1463> A_IWL<1462> A_IWL<1461> A_IWL<1460> A_IWL<1459> A_IWL<1458> A_IWL<1457> A_IWL<1456> A_IWL<1455> A_IWL<1454> A_IWL<1453> A_IWL<1452> A_IWL<1451> A_IWL<1450> A_IWL<1449> A_IWL<1448> A_IWL<1447> A_IWL<1446> A_IWL<1445> A_IWL<1444> A_IWL<1443> A_IWL<1442> A_IWL<1441> A_IWL<1440> A_IWL<1439> A_IWL<1438> A_IWL<1437> A_IWL<1436> A_IWL<1435> A_IWL<1434> A_IWL<1433> A_IWL<1432> A_IWL<1431> A_IWL<1430> A_IWL<1429> A_IWL<1428> A_IWL<1427> A_IWL<1426> A_IWL<1425> A_IWL<1424> A_IWL<1423> A_IWL<1422> A_IWL<1421> A_IWL<1420> A_IWL<1419> A_IWL<1418> A_IWL<1417> A_IWL<1416> A_IWL<1415> A_IWL<1414> A_IWL<1413> A_IWL<1412> A_IWL<1411> A_IWL<1410> A_IWL<1409> A_IWL<1408> A_IWL<1407> A_IWL<1406> A_IWL<1405> A_IWL<1404> A_IWL<1403> A_IWL<1402> A_IWL<1401> A_IWL<1400> A_IWL<1399> A_IWL<1398> A_IWL<1397> A_IWL<1396> A_IWL<1395> A_IWL<1394> A_IWL<1393> A_IWL<1392> A_IWL<1391> A_IWL<1390> A_IWL<1389> A_IWL<1388> A_IWL<1387> A_IWL<1386> A_IWL<1385> A_IWL<1384> A_IWL<1383> A_IWL<1382> A_IWL<1381> A_IWL<1380> A_IWL<1379> A_IWL<1378> A_IWL<1377> A_IWL<1376> A_IWL<1375> A_IWL<1374> A_IWL<1373> A_IWL<1372> A_IWL<1371> A_IWL<1370> A_IWL<1369> A_IWL<1368> A_IWL<1367> A_IWL<1366> A_IWL<1365> A_IWL<1364> A_IWL<1363> A_IWL<1362> A_IWL<1361> A_IWL<1360> A_IWL<1359> A_IWL<1358> A_IWL<1357> A_IWL<1356> A_IWL<1355> A_IWL<1354> A_IWL<1353> A_IWL<1352> A_IWL<1351> A_IWL<1350> A_IWL<1349> A_IWL<1348> A_IWL<1347> A_IWL<1346> A_IWL<1345> A_IWL<1344> A_IWL<1343> A_IWL<1342> A_IWL<1341> A_IWL<1340> A_IWL<1339> A_IWL<1338> A_IWL<1337> A_IWL<1336> A_IWL<1335> A_IWL<1334> A_IWL<1333> A_IWL<1332> A_IWL<1331> A_IWL<1330> A_IWL<1329> A_IWL<1328> A_IWL<1327> A_IWL<1326> A_IWL<1325> A_IWL<1324> A_IWL<1323> A_IWL<1322> A_IWL<1321> A_IWL<1320> A_IWL<1319> A_IWL<1318> A_IWL<1317> A_IWL<1316> A_IWL<1315> A_IWL<1314> A_IWL<1313> A_IWL<1312> A_IWL<1311> A_IWL<1310> A_IWL<1309> A_IWL<1308> A_IWL<1307> A_IWL<1306> A_IWL<1305> A_IWL<1304> A_IWL<1303> A_IWL<1302> A_IWL<1301> A_IWL<1300> A_IWL<1299> A_IWL<1298> A_IWL<1297> A_IWL<1296> A_IWL<1295> A_IWL<1294> A_IWL<1293> A_IWL<1292> A_IWL<1291> A_IWL<1290> A_IWL<1289> A_IWL<1288> A_IWL<1287> A_IWL<1286> A_IWL<1285> A_IWL<1284> A_IWL<1283> A_IWL<1282> A_IWL<1281> A_IWL<1280> A_IWL<1279> A_IWL<1278> A_IWL<1277> A_IWL<1276> A_IWL<1275> A_IWL<1274> A_IWL<1273> A_IWL<1272> A_IWL<1271> A_IWL<1270> A_IWL<1269> A_IWL<1268> A_IWL<1267> A_IWL<1266> A_IWL<1265> A_IWL<1264> A_IWL<1263> A_IWL<1262> A_IWL<1261> A_IWL<1260> A_IWL<1259> A_IWL<1258> A_IWL<1257> A_IWL<1256> A_IWL<1255> A_IWL<1254> A_IWL<1253> A_IWL<1252> A_IWL<1251> A_IWL<1250> A_IWL<1249> A_IWL<1248> A_IWL<1247> A_IWL<1246> A_IWL<1245> A_IWL<1244> A_IWL<1243> A_IWL<1242> A_IWL<1241> A_IWL<1240> A_IWL<1239> A_IWL<1238> A_IWL<1237> A_IWL<1236> A_IWL<1235> A_IWL<1234> A_IWL<1233> A_IWL<1232> A_IWL<1231> A_IWL<1230> A_IWL<1229> A_IWL<1228> A_IWL<1227> A_IWL<1226> A_IWL<1225> A_IWL<1224> A_IWL<1223> A_IWL<1222> A_IWL<1221> A_IWL<1220> A_IWL<1219> A_IWL<1218> A_IWL<1217> A_IWL<1216> A_IWL<1215> A_IWL<1214> A_IWL<1213> A_IWL<1212> A_IWL<1211> A_IWL<1210> A_IWL<1209> A_IWL<1208> A_IWL<1207> A_IWL<1206> A_IWL<1205> A_IWL<1204> A_IWL<1203> A_IWL<1202> A_IWL<1201> A_IWL<1200> A_IWL<1199> A_IWL<1198> A_IWL<1197> A_IWL<1196> A_IWL<1195> A_IWL<1194> A_IWL<1193> A_IWL<1192> A_IWL<1191> A_IWL<1190> A_IWL<1189> A_IWL<1188> A_IWL<1187> A_IWL<1186> A_IWL<1185> A_IWL<1184> A_IWL<1183> A_IWL<1182> A_IWL<1181> A_IWL<1180> A_IWL<1179> A_IWL<1178> A_IWL<1177> A_IWL<1176> A_IWL<1175> A_IWL<1174> A_IWL<1173> A_IWL<1172> A_IWL<1171> A_IWL<1170> A_IWL<1169> A_IWL<1168> A_IWL<1167> A_IWL<1166> A_IWL<1165> A_IWL<1164> A_IWL<1163> A_IWL<1162> A_IWL<1161> A_IWL<1160> A_IWL<1159> A_IWL<1158> A_IWL<1157> A_IWL<1156> A_IWL<1155> A_IWL<1154> A_IWL<1153> A_IWL<1152> A_IWL<1151> A_IWL<1150> A_IWL<1149> A_IWL<1148> A_IWL<1147> A_IWL<1146> A_IWL<1145> A_IWL<1144> A_IWL<1143> A_IWL<1142> A_IWL<1141> A_IWL<1140> A_IWL<1139> A_IWL<1138> A_IWL<1137> A_IWL<1136> A_IWL<1135> A_IWL<1134> A_IWL<1133> A_IWL<1132> A_IWL<1131> A_IWL<1130> A_IWL<1129> A_IWL<1128> A_IWL<1127> A_IWL<1126> A_IWL<1125> A_IWL<1124> A_IWL<1123> A_IWL<1122> A_IWL<1121> A_IWL<1120> A_IWL<1119> A_IWL<1118> A_IWL<1117> A_IWL<1116> A_IWL<1115> A_IWL<1114> A_IWL<1113> A_IWL<1112> A_IWL<1111> A_IWL<1110> A_IWL<1109> A_IWL<1108> A_IWL<1107> A_IWL<1106> A_IWL<1105> A_IWL<1104> A_IWL<1103> A_IWL<1102> A_IWL<1101> A_IWL<1100> A_IWL<1099> A_IWL<1098> A_IWL<1097> A_IWL<1096> A_IWL<1095> A_IWL<1094> A_IWL<1093> A_IWL<1092> A_IWL<1091> A_IWL<1090> A_IWL<1089> A_IWL<1088> A_IWL<1087> A_IWL<1086> A_IWL<1085> A_IWL<1084> A_IWL<1083> A_IWL<1082> A_IWL<1081> A_IWL<1080> A_IWL<1079> A_IWL<1078> A_IWL<1077> A_IWL<1076> A_IWL<1075> A_IWL<1074> A_IWL<1073> A_IWL<1072> A_IWL<1071> A_IWL<1070> A_IWL<1069> A_IWL<1068> A_IWL<1067> A_IWL<1066> A_IWL<1065> A_IWL<1064> A_IWL<1063> A_IWL<1062> A_IWL<1061> A_IWL<1060> A_IWL<1059> A_IWL<1058> A_IWL<1057> A_IWL<1056> A_IWL<1055> A_IWL<1054> A_IWL<1053> A_IWL<1052> A_IWL<1051> A_IWL<1050> A_IWL<1049> A_IWL<1048> A_IWL<1047> A_IWL<1046> A_IWL<1045> A_IWL<1044> A_IWL<1043> A_IWL<1042> A_IWL<1041> A_IWL<1040> A_IWL<1039> A_IWL<1038> A_IWL<1037> A_IWL<1036> A_IWL<1035> A_IWL<1034> A_IWL<1033> A_IWL<1032> A_IWL<1031> A_IWL<1030> A_IWL<1029> A_IWL<1028> A_IWL<1027> A_IWL<1026> A_IWL<1025> A_IWL<1024> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_COLUMN_pcell_0 +XCOL<1> A_BLC<3> A_BLC<2> A_BLC_TOP<3> A_BLC_TOP<2> A_BLT<3> A_BLT<2> A_BLT_TOP<3> A_BLT_TOP<2> A_IWL<511> A_IWL<510> A_IWL<509> A_IWL<508> A_IWL<507> A_IWL<506> A_IWL<505> A_IWL<504> A_IWL<503> A_IWL<502> A_IWL<501> A_IWL<500> A_IWL<499> A_IWL<498> A_IWL<497> A_IWL<496> A_IWL<495> A_IWL<494> A_IWL<493> A_IWL<492> A_IWL<491> A_IWL<490> A_IWL<489> A_IWL<488> A_IWL<487> A_IWL<486> A_IWL<485> A_IWL<484> A_IWL<483> A_IWL<482> A_IWL<481> A_IWL<480> A_IWL<479> A_IWL<478> A_IWL<477> A_IWL<476> A_IWL<475> A_IWL<474> A_IWL<473> A_IWL<472> A_IWL<471> A_IWL<470> A_IWL<469> A_IWL<468> A_IWL<467> A_IWL<466> A_IWL<465> A_IWL<464> A_IWL<463> A_IWL<462> A_IWL<461> A_IWL<460> A_IWL<459> A_IWL<458> A_IWL<457> A_IWL<456> A_IWL<455> A_IWL<454> A_IWL<453> A_IWL<452> A_IWL<451> A_IWL<450> A_IWL<449> A_IWL<448> A_IWL<447> A_IWL<446> A_IWL<445> A_IWL<444> A_IWL<443> A_IWL<442> A_IWL<441> A_IWL<440> A_IWL<439> A_IWL<438> A_IWL<437> A_IWL<436> A_IWL<435> A_IWL<434> A_IWL<433> A_IWL<432> A_IWL<431> A_IWL<430> A_IWL<429> A_IWL<428> A_IWL<427> A_IWL<426> A_IWL<425> A_IWL<424> A_IWL<423> A_IWL<422> A_IWL<421> A_IWL<420> A_IWL<419> A_IWL<418> A_IWL<417> A_IWL<416> A_IWL<415> A_IWL<414> A_IWL<413> A_IWL<412> A_IWL<411> A_IWL<410> A_IWL<409> A_IWL<408> A_IWL<407> A_IWL<406> A_IWL<405> A_IWL<404> A_IWL<403> A_IWL<402> A_IWL<401> A_IWL<400> A_IWL<399> A_IWL<398> A_IWL<397> A_IWL<396> A_IWL<395> A_IWL<394> A_IWL<393> A_IWL<392> A_IWL<391> A_IWL<390> A_IWL<389> A_IWL<388> A_IWL<387> A_IWL<386> A_IWL<385> A_IWL<384> A_IWL<383> A_IWL<382> A_IWL<381> A_IWL<380> A_IWL<379> A_IWL<378> A_IWL<377> A_IWL<376> A_IWL<375> A_IWL<374> A_IWL<373> A_IWL<372> A_IWL<371> A_IWL<370> A_IWL<369> A_IWL<368> A_IWL<367> A_IWL<366> A_IWL<365> A_IWL<364> A_IWL<363> A_IWL<362> A_IWL<361> A_IWL<360> A_IWL<359> A_IWL<358> A_IWL<357> A_IWL<356> A_IWL<355> A_IWL<354> A_IWL<353> A_IWL<352> A_IWL<351> A_IWL<350> A_IWL<349> A_IWL<348> A_IWL<347> A_IWL<346> A_IWL<345> A_IWL<344> A_IWL<343> A_IWL<342> A_IWL<341> A_IWL<340> A_IWL<339> A_IWL<338> A_IWL<337> A_IWL<336> A_IWL<335> A_IWL<334> A_IWL<333> A_IWL<332> A_IWL<331> A_IWL<330> A_IWL<329> A_IWL<328> A_IWL<327> A_IWL<326> A_IWL<325> A_IWL<324> A_IWL<323> A_IWL<322> A_IWL<321> A_IWL<320> A_IWL<319> A_IWL<318> A_IWL<317> A_IWL<316> A_IWL<315> A_IWL<314> A_IWL<313> A_IWL<312> A_IWL<311> A_IWL<310> A_IWL<309> A_IWL<308> A_IWL<307> A_IWL<306> A_IWL<305> A_IWL<304> A_IWL<303> A_IWL<302> A_IWL<301> A_IWL<300> A_IWL<299> A_IWL<298> A_IWL<297> A_IWL<296> A_IWL<295> A_IWL<294> A_IWL<293> A_IWL<292> A_IWL<291> A_IWL<290> A_IWL<289> A_IWL<288> A_IWL<287> A_IWL<286> A_IWL<285> A_IWL<284> A_IWL<283> A_IWL<282> A_IWL<281> A_IWL<280> A_IWL<279> A_IWL<278> A_IWL<277> A_IWL<276> A_IWL<275> A_IWL<274> A_IWL<273> A_IWL<272> A_IWL<271> A_IWL<270> A_IWL<269> A_IWL<268> A_IWL<267> A_IWL<266> A_IWL<265> A_IWL<264> A_IWL<263> A_IWL<262> A_IWL<261> A_IWL<260> A_IWL<259> A_IWL<258> A_IWL<257> A_IWL<256> A_IWL<255> A_IWL<254> A_IWL<253> A_IWL<252> A_IWL<251> A_IWL<250> A_IWL<249> A_IWL<248> A_IWL<247> A_IWL<246> A_IWL<245> A_IWL<244> A_IWL<243> A_IWL<242> A_IWL<241> A_IWL<240> A_IWL<239> A_IWL<238> A_IWL<237> A_IWL<236> A_IWL<235> A_IWL<234> A_IWL<233> A_IWL<232> A_IWL<231> A_IWL<230> A_IWL<229> A_IWL<228> A_IWL<227> A_IWL<226> A_IWL<225> A_IWL<224> A_IWL<223> A_IWL<222> A_IWL<221> A_IWL<220> A_IWL<219> A_IWL<218> A_IWL<217> A_IWL<216> A_IWL<215> A_IWL<214> A_IWL<213> A_IWL<212> A_IWL<211> A_IWL<210> A_IWL<209> A_IWL<208> A_IWL<207> A_IWL<206> A_IWL<205> A_IWL<204> A_IWL<203> A_IWL<202> A_IWL<201> A_IWL<200> A_IWL<199> A_IWL<198> A_IWL<197> A_IWL<196> A_IWL<195> A_IWL<194> A_IWL<193> A_IWL<192> A_IWL<191> A_IWL<190> A_IWL<189> A_IWL<188> A_IWL<187> A_IWL<186> A_IWL<185> A_IWL<184> A_IWL<183> A_IWL<182> A_IWL<181> A_IWL<180> A_IWL<179> A_IWL<178> A_IWL<177> A_IWL<176> A_IWL<175> A_IWL<174> A_IWL<173> A_IWL<172> A_IWL<171> A_IWL<170> A_IWL<169> A_IWL<168> A_IWL<167> A_IWL<166> A_IWL<165> A_IWL<164> A_IWL<163> A_IWL<162> A_IWL<161> A_IWL<160> A_IWL<159> A_IWL<158> A_IWL<157> A_IWL<156> A_IWL<155> A_IWL<154> A_IWL<153> A_IWL<152> A_IWL<151> A_IWL<150> A_IWL<149> A_IWL<148> A_IWL<147> A_IWL<146> A_IWL<145> A_IWL<144> A_IWL<143> A_IWL<142> A_IWL<141> A_IWL<140> A_IWL<139> A_IWL<138> A_IWL<137> A_IWL<136> A_IWL<135> A_IWL<134> A_IWL<133> A_IWL<132> A_IWL<131> A_IWL<130> A_IWL<129> A_IWL<128> A_IWL<127> A_IWL<126> A_IWL<125> A_IWL<124> A_IWL<123> A_IWL<122> A_IWL<121> A_IWL<120> A_IWL<119> A_IWL<118> A_IWL<117> A_IWL<116> A_IWL<115> A_IWL<114> A_IWL<113> A_IWL<112> A_IWL<111> A_IWL<110> A_IWL<109> A_IWL<108> A_IWL<107> A_IWL<106> A_IWL<105> A_IWL<104> A_IWL<103> A_IWL<102> A_IWL<101> A_IWL<100> A_IWL<99> A_IWL<98> A_IWL<97> A_IWL<96> A_IWL<95> A_IWL<94> A_IWL<93> A_IWL<92> A_IWL<91> A_IWL<90> A_IWL<89> A_IWL<88> A_IWL<87> A_IWL<86> A_IWL<85> A_IWL<84> A_IWL<83> A_IWL<82> A_IWL<81> A_IWL<80> A_IWL<79> A_IWL<78> A_IWL<77> A_IWL<76> A_IWL<75> A_IWL<74> A_IWL<73> A_IWL<72> A_IWL<71> A_IWL<70> A_IWL<69> A_IWL<68> A_IWL<67> A_IWL<66> A_IWL<65> A_IWL<64> A_IWL<63> A_IWL<62> A_IWL<61> A_IWL<60> A_IWL<59> A_IWL<58> A_IWL<57> A_IWL<56> A_IWL<55> A_IWL<54> A_IWL<53> A_IWL<52> A_IWL<51> A_IWL<50> A_IWL<49> A_IWL<48> A_IWL<47> A_IWL<46> A_IWL<45> A_IWL<44> A_IWL<43> A_IWL<42> A_IWL<41> A_IWL<40> A_IWL<39> A_IWL<38> A_IWL<37> A_IWL<36> A_IWL<35> A_IWL<34> A_IWL<33> A_IWL<32> A_IWL<31> A_IWL<30> A_IWL<29> A_IWL<28> A_IWL<27> A_IWL<26> A_IWL<25> A_IWL<24> A_IWL<23> A_IWL<22> A_IWL<21> A_IWL<20> A_IWL<19> A_IWL<18> A_IWL<17> A_IWL<16> A_IWL<15> A_IWL<14> A_IWL<13> A_IWL<12> A_IWL<11> A_IWL<10> A_IWL<9> A_IWL<8> A_IWL<7> A_IWL<6> A_IWL<5> A_IWL<4> A_IWL<3> A_IWL<2> A_IWL<1> A_IWL<0> A_IWL<1023> A_IWL<1022> A_IWL<1021> A_IWL<1020> A_IWL<1019> A_IWL<1018> A_IWL<1017> A_IWL<1016> A_IWL<1015> A_IWL<1014> A_IWL<1013> A_IWL<1012> A_IWL<1011> A_IWL<1010> A_IWL<1009> A_IWL<1008> A_IWL<1007> A_IWL<1006> A_IWL<1005> A_IWL<1004> A_IWL<1003> A_IWL<1002> A_IWL<1001> A_IWL<1000> A_IWL<999> A_IWL<998> A_IWL<997> A_IWL<996> A_IWL<995> A_IWL<994> A_IWL<993> A_IWL<992> A_IWL<991> A_IWL<990> A_IWL<989> A_IWL<988> A_IWL<987> A_IWL<986> A_IWL<985> A_IWL<984> A_IWL<983> A_IWL<982> A_IWL<981> A_IWL<980> A_IWL<979> A_IWL<978> A_IWL<977> A_IWL<976> A_IWL<975> A_IWL<974> A_IWL<973> A_IWL<972> A_IWL<971> A_IWL<970> A_IWL<969> A_IWL<968> A_IWL<967> A_IWL<966> A_IWL<965> A_IWL<964> A_IWL<963> A_IWL<962> A_IWL<961> A_IWL<960> A_IWL<959> A_IWL<958> A_IWL<957> A_IWL<956> A_IWL<955> A_IWL<954> A_IWL<953> A_IWL<952> A_IWL<951> A_IWL<950> A_IWL<949> A_IWL<948> A_IWL<947> A_IWL<946> A_IWL<945> A_IWL<944> A_IWL<943> A_IWL<942> A_IWL<941> A_IWL<940> A_IWL<939> A_IWL<938> A_IWL<937> A_IWL<936> A_IWL<935> A_IWL<934> A_IWL<933> A_IWL<932> A_IWL<931> A_IWL<930> A_IWL<929> A_IWL<928> A_IWL<927> A_IWL<926> A_IWL<925> A_IWL<924> A_IWL<923> A_IWL<922> A_IWL<921> A_IWL<920> A_IWL<919> A_IWL<918> A_IWL<917> A_IWL<916> A_IWL<915> A_IWL<914> A_IWL<913> A_IWL<912> A_IWL<911> A_IWL<910> A_IWL<909> A_IWL<908> A_IWL<907> A_IWL<906> A_IWL<905> A_IWL<904> A_IWL<903> A_IWL<902> A_IWL<901> A_IWL<900> A_IWL<899> A_IWL<898> A_IWL<897> A_IWL<896> A_IWL<895> A_IWL<894> A_IWL<893> A_IWL<892> A_IWL<891> A_IWL<890> A_IWL<889> A_IWL<888> A_IWL<887> A_IWL<886> A_IWL<885> A_IWL<884> A_IWL<883> A_IWL<882> A_IWL<881> A_IWL<880> A_IWL<879> A_IWL<878> A_IWL<877> A_IWL<876> A_IWL<875> A_IWL<874> A_IWL<873> A_IWL<872> A_IWL<871> A_IWL<870> A_IWL<869> A_IWL<868> A_IWL<867> A_IWL<866> A_IWL<865> A_IWL<864> A_IWL<863> A_IWL<862> A_IWL<861> A_IWL<860> A_IWL<859> A_IWL<858> A_IWL<857> A_IWL<856> A_IWL<855> A_IWL<854> A_IWL<853> A_IWL<852> A_IWL<851> A_IWL<850> A_IWL<849> A_IWL<848> A_IWL<847> A_IWL<846> A_IWL<845> A_IWL<844> A_IWL<843> A_IWL<842> A_IWL<841> A_IWL<840> A_IWL<839> A_IWL<838> A_IWL<837> A_IWL<836> A_IWL<835> A_IWL<834> A_IWL<833> A_IWL<832> A_IWL<831> A_IWL<830> A_IWL<829> A_IWL<828> A_IWL<827> A_IWL<826> A_IWL<825> A_IWL<824> A_IWL<823> A_IWL<822> A_IWL<821> A_IWL<820> A_IWL<819> A_IWL<818> A_IWL<817> A_IWL<816> A_IWL<815> A_IWL<814> A_IWL<813> A_IWL<812> A_IWL<811> A_IWL<810> A_IWL<809> A_IWL<808> A_IWL<807> A_IWL<806> A_IWL<805> A_IWL<804> A_IWL<803> A_IWL<802> A_IWL<801> A_IWL<800> A_IWL<799> A_IWL<798> A_IWL<797> A_IWL<796> A_IWL<795> A_IWL<794> A_IWL<793> A_IWL<792> A_IWL<791> A_IWL<790> A_IWL<789> A_IWL<788> A_IWL<787> A_IWL<786> A_IWL<785> A_IWL<784> A_IWL<783> A_IWL<782> A_IWL<781> A_IWL<780> A_IWL<779> A_IWL<778> A_IWL<777> A_IWL<776> A_IWL<775> A_IWL<774> A_IWL<773> A_IWL<772> A_IWL<771> A_IWL<770> A_IWL<769> A_IWL<768> A_IWL<767> A_IWL<766> A_IWL<765> A_IWL<764> A_IWL<763> A_IWL<762> A_IWL<761> A_IWL<760> A_IWL<759> A_IWL<758> A_IWL<757> A_IWL<756> A_IWL<755> A_IWL<754> A_IWL<753> A_IWL<752> A_IWL<751> A_IWL<750> A_IWL<749> A_IWL<748> A_IWL<747> A_IWL<746> A_IWL<745> A_IWL<744> A_IWL<743> A_IWL<742> A_IWL<741> A_IWL<740> A_IWL<739> A_IWL<738> A_IWL<737> A_IWL<736> A_IWL<735> A_IWL<734> A_IWL<733> A_IWL<732> A_IWL<731> A_IWL<730> A_IWL<729> A_IWL<728> A_IWL<727> A_IWL<726> A_IWL<725> A_IWL<724> A_IWL<723> A_IWL<722> A_IWL<721> A_IWL<720> A_IWL<719> A_IWL<718> A_IWL<717> A_IWL<716> A_IWL<715> A_IWL<714> A_IWL<713> A_IWL<712> A_IWL<711> A_IWL<710> A_IWL<709> A_IWL<708> A_IWL<707> A_IWL<706> A_IWL<705> A_IWL<704> A_IWL<703> A_IWL<702> A_IWL<701> A_IWL<700> A_IWL<699> A_IWL<698> A_IWL<697> A_IWL<696> A_IWL<695> A_IWL<694> A_IWL<693> A_IWL<692> A_IWL<691> A_IWL<690> A_IWL<689> A_IWL<688> A_IWL<687> A_IWL<686> A_IWL<685> A_IWL<684> A_IWL<683> A_IWL<682> A_IWL<681> A_IWL<680> A_IWL<679> A_IWL<678> A_IWL<677> A_IWL<676> A_IWL<675> A_IWL<674> A_IWL<673> A_IWL<672> A_IWL<671> A_IWL<670> A_IWL<669> A_IWL<668> A_IWL<667> A_IWL<666> A_IWL<665> A_IWL<664> A_IWL<663> A_IWL<662> A_IWL<661> A_IWL<660> A_IWL<659> A_IWL<658> A_IWL<657> A_IWL<656> A_IWL<655> A_IWL<654> A_IWL<653> A_IWL<652> A_IWL<651> A_IWL<650> A_IWL<649> A_IWL<648> A_IWL<647> A_IWL<646> A_IWL<645> A_IWL<644> A_IWL<643> A_IWL<642> A_IWL<641> A_IWL<640> A_IWL<639> A_IWL<638> A_IWL<637> A_IWL<636> A_IWL<635> A_IWL<634> A_IWL<633> A_IWL<632> A_IWL<631> A_IWL<630> A_IWL<629> A_IWL<628> A_IWL<627> A_IWL<626> A_IWL<625> A_IWL<624> A_IWL<623> A_IWL<622> A_IWL<621> A_IWL<620> A_IWL<619> A_IWL<618> A_IWL<617> A_IWL<616> A_IWL<615> A_IWL<614> A_IWL<613> A_IWL<612> A_IWL<611> A_IWL<610> A_IWL<609> A_IWL<608> A_IWL<607> A_IWL<606> A_IWL<605> A_IWL<604> A_IWL<603> A_IWL<602> A_IWL<601> A_IWL<600> A_IWL<599> A_IWL<598> A_IWL<597> A_IWL<596> A_IWL<595> A_IWL<594> A_IWL<593> A_IWL<592> A_IWL<591> A_IWL<590> A_IWL<589> A_IWL<588> A_IWL<587> A_IWL<586> A_IWL<585> A_IWL<584> A_IWL<583> A_IWL<582> A_IWL<581> A_IWL<580> A_IWL<579> A_IWL<578> A_IWL<577> A_IWL<576> A_IWL<575> A_IWL<574> A_IWL<573> A_IWL<572> A_IWL<571> A_IWL<570> A_IWL<569> A_IWL<568> A_IWL<567> A_IWL<566> A_IWL<565> A_IWL<564> A_IWL<563> A_IWL<562> A_IWL<561> A_IWL<560> A_IWL<559> A_IWL<558> A_IWL<557> A_IWL<556> A_IWL<555> A_IWL<554> A_IWL<553> A_IWL<552> A_IWL<551> A_IWL<550> A_IWL<549> A_IWL<548> A_IWL<547> A_IWL<546> A_IWL<545> A_IWL<544> A_IWL<543> A_IWL<542> A_IWL<541> A_IWL<540> A_IWL<539> A_IWL<538> A_IWL<537> A_IWL<536> A_IWL<535> A_IWL<534> A_IWL<533> A_IWL<532> A_IWL<531> A_IWL<530> A_IWL<529> A_IWL<528> A_IWL<527> A_IWL<526> A_IWL<525> A_IWL<524> A_IWL<523> A_IWL<522> A_IWL<521> A_IWL<520> A_IWL<519> A_IWL<518> A_IWL<517> A_IWL<516> A_IWL<515> A_IWL<514> A_IWL<513> A_IWL<512> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_COLUMN_pcell_0 +XCOL<0> A_BLC<1> A_BLC<0> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT<1> A_BLT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_WL<511> A_WL<510> A_WL<509> A_WL<508> A_WL<507> A_WL<506> A_WL<505> A_WL<504> A_WL<503> A_WL<502> A_WL<501> A_WL<500> A_WL<499> A_WL<498> A_WL<497> A_WL<496> A_WL<495> A_WL<494> A_WL<493> A_WL<492> A_WL<491> A_WL<490> A_WL<489> A_WL<488> A_WL<487> A_WL<486> A_WL<485> A_WL<484> A_WL<483> A_WL<482> A_WL<481> A_WL<480> A_WL<479> A_WL<478> A_WL<477> A_WL<476> A_WL<475> A_WL<474> A_WL<473> A_WL<472> A_WL<471> A_WL<470> A_WL<469> A_WL<468> A_WL<467> A_WL<466> A_WL<465> A_WL<464> A_WL<463> A_WL<462> A_WL<461> A_WL<460> A_WL<459> A_WL<458> A_WL<457> A_WL<456> A_WL<455> A_WL<454> A_WL<453> A_WL<452> A_WL<451> A_WL<450> A_WL<449> A_WL<448> A_WL<447> A_WL<446> A_WL<445> A_WL<444> A_WL<443> A_WL<442> A_WL<441> A_WL<440> A_WL<439> A_WL<438> A_WL<437> A_WL<436> A_WL<435> A_WL<434> A_WL<433> A_WL<432> A_WL<431> A_WL<430> A_WL<429> A_WL<428> A_WL<427> A_WL<426> A_WL<425> A_WL<424> A_WL<423> A_WL<422> A_WL<421> A_WL<420> A_WL<419> A_WL<418> A_WL<417> A_WL<416> A_WL<415> A_WL<414> A_WL<413> A_WL<412> A_WL<411> A_WL<410> A_WL<409> A_WL<408> A_WL<407> A_WL<406> A_WL<405> A_WL<404> A_WL<403> A_WL<402> A_WL<401> A_WL<400> A_WL<399> A_WL<398> A_WL<397> A_WL<396> A_WL<395> A_WL<394> A_WL<393> A_WL<392> A_WL<391> A_WL<390> A_WL<389> A_WL<388> A_WL<387> A_WL<386> A_WL<385> A_WL<384> A_WL<383> A_WL<382> A_WL<381> A_WL<380> A_WL<379> A_WL<378> A_WL<377> A_WL<376> A_WL<375> A_WL<374> A_WL<373> A_WL<372> A_WL<371> A_WL<370> A_WL<369> A_WL<368> A_WL<367> A_WL<366> A_WL<365> A_WL<364> A_WL<363> A_WL<362> A_WL<361> A_WL<360> A_WL<359> A_WL<358> A_WL<357> A_WL<356> A_WL<355> A_WL<354> A_WL<353> A_WL<352> A_WL<351> A_WL<350> A_WL<349> A_WL<348> A_WL<347> A_WL<346> A_WL<345> A_WL<344> A_WL<343> A_WL<342> A_WL<341> A_WL<340> A_WL<339> A_WL<338> A_WL<337> A_WL<336> A_WL<335> A_WL<334> A_WL<333> A_WL<332> A_WL<331> A_WL<330> A_WL<329> A_WL<328> A_WL<327> A_WL<326> A_WL<325> A_WL<324> A_WL<323> A_WL<322> A_WL<321> A_WL<320> A_WL<319> A_WL<318> A_WL<317> A_WL<316> A_WL<315> A_WL<314> A_WL<313> A_WL<312> A_WL<311> A_WL<310> A_WL<309> A_WL<308> A_WL<307> A_WL<306> A_WL<305> A_WL<304> A_WL<303> A_WL<302> A_WL<301> A_WL<300> A_WL<299> A_WL<298> A_WL<297> A_WL<296> A_WL<295> A_WL<294> A_WL<293> A_WL<292> A_WL<291> A_WL<290> A_WL<289> A_WL<288> A_WL<287> A_WL<286> A_WL<285> A_WL<284> A_WL<283> A_WL<282> A_WL<281> A_WL<280> A_WL<279> A_WL<278> A_WL<277> A_WL<276> A_WL<275> A_WL<274> A_WL<273> A_WL<272> A_WL<271> A_WL<270> A_WL<269> A_WL<268> A_WL<267> A_WL<266> A_WL<265> A_WL<264> A_WL<263> A_WL<262> A_WL<261> A_WL<260> A_WL<259> A_WL<258> A_WL<257> A_WL<256> A_WL<255> A_WL<254> A_WL<253> A_WL<252> A_WL<251> A_WL<250> A_WL<249> A_WL<248> A_WL<247> A_WL<246> A_WL<245> A_WL<244> A_WL<243> A_WL<242> A_WL<241> A_WL<240> A_WL<239> A_WL<238> A_WL<237> A_WL<236> A_WL<235> A_WL<234> A_WL<233> A_WL<232> A_WL<231> A_WL<230> A_WL<229> A_WL<228> A_WL<227> A_WL<226> A_WL<225> A_WL<224> A_WL<223> A_WL<222> A_WL<221> A_WL<220> A_WL<219> A_WL<218> A_WL<217> A_WL<216> A_WL<215> A_WL<214> A_WL<213> A_WL<212> A_WL<211> A_WL<210> A_WL<209> A_WL<208> A_WL<207> A_WL<206> A_WL<205> A_WL<204> A_WL<203> A_WL<202> A_WL<201> A_WL<200> A_WL<199> A_WL<198> A_WL<197> A_WL<196> A_WL<195> A_WL<194> A_WL<193> A_WL<192> A_WL<191> A_WL<190> A_WL<189> A_WL<188> A_WL<187> A_WL<186> A_WL<185> A_WL<184> A_WL<183> A_WL<182> A_WL<181> A_WL<180> A_WL<179> A_WL<178> A_WL<177> A_WL<176> A_WL<175> A_WL<174> A_WL<173> A_WL<172> A_WL<171> A_WL<170> A_WL<169> A_WL<168> A_WL<167> A_WL<166> A_WL<165> A_WL<164> A_WL<163> A_WL<162> A_WL<161> A_WL<160> A_WL<159> A_WL<158> A_WL<157> A_WL<156> A_WL<155> A_WL<154> A_WL<153> A_WL<152> A_WL<151> A_WL<150> A_WL<149> A_WL<148> A_WL<147> A_WL<146> A_WL<145> A_WL<144> A_WL<143> A_WL<142> A_WL<141> A_WL<140> A_WL<139> A_WL<138> A_WL<137> A_WL<136> A_WL<135> A_WL<134> A_WL<133> A_WL<132> A_WL<131> A_WL<130> A_WL<129> A_WL<128> A_WL<127> A_WL<126> A_WL<125> A_WL<124> A_WL<123> A_WL<122> A_WL<121> A_WL<120> A_WL<119> A_WL<118> A_WL<117> A_WL<116> A_WL<115> A_WL<114> A_WL<113> A_WL<112> A_WL<111> A_WL<110> A_WL<109> A_WL<108> A_WL<107> A_WL<106> A_WL<105> A_WL<104> A_WL<103> A_WL<102> A_WL<101> A_WL<100> A_WL<99> A_WL<98> A_WL<97> A_WL<96> A_WL<95> A_WL<94> A_WL<93> A_WL<92> A_WL<91> A_WL<90> A_WL<89> A_WL<88> A_WL<87> A_WL<86> A_WL<85> A_WL<84> A_WL<83> A_WL<82> A_WL<81> A_WL<80> A_WL<79> A_WL<78> A_WL<77> A_WL<76> A_WL<75> A_WL<74> A_WL<73> A_WL<72> A_WL<71> A_WL<70> A_WL<69> A_WL<68> A_WL<67> A_WL<66> A_WL<65> A_WL<64> A_WL<63> A_WL<62> A_WL<61> A_WL<60> A_WL<59> A_WL<58> A_WL<57> A_WL<56> A_WL<55> A_WL<54> A_WL<53> A_WL<52> A_WL<51> A_WL<50> A_WL<49> A_WL<48> A_WL<47> A_WL<46> A_WL<45> A_WL<44> A_WL<43> A_WL<42> A_WL<41> A_WL<40> A_WL<39> A_WL<38> A_WL<37> A_WL<36> A_WL<35> A_WL<34> A_WL<33> A_WL<32> A_WL<31> A_WL<30> A_WL<29> A_WL<28> A_WL<27> A_WL<26> A_WL<25> A_WL<24> A_WL<23> A_WL<22> A_WL<21> A_WL<20> A_WL<19> A_WL<18> A_WL<17> A_WL<16> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> A_IWL<511> A_IWL<510> A_IWL<509> A_IWL<508> A_IWL<507> A_IWL<506> A_IWL<505> A_IWL<504> A_IWL<503> A_IWL<502> A_IWL<501> A_IWL<500> A_IWL<499> A_IWL<498> A_IWL<497> A_IWL<496> A_IWL<495> A_IWL<494> A_IWL<493> A_IWL<492> A_IWL<491> A_IWL<490> A_IWL<489> A_IWL<488> A_IWL<487> A_IWL<486> A_IWL<485> A_IWL<484> A_IWL<483> A_IWL<482> A_IWL<481> A_IWL<480> A_IWL<479> A_IWL<478> A_IWL<477> A_IWL<476> A_IWL<475> A_IWL<474> A_IWL<473> A_IWL<472> A_IWL<471> A_IWL<470> A_IWL<469> A_IWL<468> A_IWL<467> A_IWL<466> A_IWL<465> A_IWL<464> A_IWL<463> A_IWL<462> A_IWL<461> A_IWL<460> A_IWL<459> A_IWL<458> A_IWL<457> A_IWL<456> A_IWL<455> A_IWL<454> A_IWL<453> A_IWL<452> A_IWL<451> A_IWL<450> A_IWL<449> A_IWL<448> A_IWL<447> A_IWL<446> A_IWL<445> A_IWL<444> A_IWL<443> A_IWL<442> A_IWL<441> A_IWL<440> A_IWL<439> A_IWL<438> A_IWL<437> A_IWL<436> A_IWL<435> A_IWL<434> A_IWL<433> A_IWL<432> A_IWL<431> A_IWL<430> A_IWL<429> A_IWL<428> A_IWL<427> A_IWL<426> A_IWL<425> A_IWL<424> A_IWL<423> A_IWL<422> A_IWL<421> A_IWL<420> A_IWL<419> A_IWL<418> A_IWL<417> A_IWL<416> A_IWL<415> A_IWL<414> A_IWL<413> A_IWL<412> A_IWL<411> A_IWL<410> A_IWL<409> A_IWL<408> A_IWL<407> A_IWL<406> A_IWL<405> A_IWL<404> A_IWL<403> A_IWL<402> A_IWL<401> A_IWL<400> A_IWL<399> A_IWL<398> A_IWL<397> A_IWL<396> A_IWL<395> A_IWL<394> A_IWL<393> A_IWL<392> A_IWL<391> A_IWL<390> A_IWL<389> A_IWL<388> A_IWL<387> A_IWL<386> A_IWL<385> A_IWL<384> A_IWL<383> A_IWL<382> A_IWL<381> A_IWL<380> A_IWL<379> A_IWL<378> A_IWL<377> A_IWL<376> A_IWL<375> A_IWL<374> A_IWL<373> A_IWL<372> A_IWL<371> A_IWL<370> A_IWL<369> A_IWL<368> A_IWL<367> A_IWL<366> A_IWL<365> A_IWL<364> A_IWL<363> A_IWL<362> A_IWL<361> A_IWL<360> A_IWL<359> A_IWL<358> A_IWL<357> A_IWL<356> A_IWL<355> A_IWL<354> A_IWL<353> A_IWL<352> A_IWL<351> A_IWL<350> A_IWL<349> A_IWL<348> A_IWL<347> A_IWL<346> A_IWL<345> A_IWL<344> A_IWL<343> A_IWL<342> A_IWL<341> A_IWL<340> A_IWL<339> A_IWL<338> A_IWL<337> A_IWL<336> A_IWL<335> A_IWL<334> A_IWL<333> A_IWL<332> A_IWL<331> A_IWL<330> A_IWL<329> A_IWL<328> A_IWL<327> A_IWL<326> A_IWL<325> A_IWL<324> A_IWL<323> A_IWL<322> A_IWL<321> A_IWL<320> A_IWL<319> A_IWL<318> A_IWL<317> A_IWL<316> A_IWL<315> A_IWL<314> A_IWL<313> A_IWL<312> A_IWL<311> A_IWL<310> A_IWL<309> A_IWL<308> A_IWL<307> A_IWL<306> A_IWL<305> A_IWL<304> A_IWL<303> A_IWL<302> A_IWL<301> A_IWL<300> A_IWL<299> A_IWL<298> A_IWL<297> A_IWL<296> A_IWL<295> A_IWL<294> A_IWL<293> A_IWL<292> A_IWL<291> A_IWL<290> A_IWL<289> A_IWL<288> A_IWL<287> A_IWL<286> A_IWL<285> A_IWL<284> A_IWL<283> A_IWL<282> A_IWL<281> A_IWL<280> A_IWL<279> A_IWL<278> A_IWL<277> A_IWL<276> A_IWL<275> A_IWL<274> A_IWL<273> A_IWL<272> A_IWL<271> A_IWL<270> A_IWL<269> A_IWL<268> A_IWL<267> A_IWL<266> A_IWL<265> A_IWL<264> A_IWL<263> A_IWL<262> A_IWL<261> A_IWL<260> A_IWL<259> A_IWL<258> A_IWL<257> A_IWL<256> A_IWL<255> A_IWL<254> A_IWL<253> A_IWL<252> A_IWL<251> A_IWL<250> A_IWL<249> A_IWL<248> A_IWL<247> A_IWL<246> A_IWL<245> A_IWL<244> A_IWL<243> A_IWL<242> A_IWL<241> A_IWL<240> A_IWL<239> A_IWL<238> A_IWL<237> A_IWL<236> A_IWL<235> A_IWL<234> A_IWL<233> A_IWL<232> A_IWL<231> A_IWL<230> A_IWL<229> A_IWL<228> A_IWL<227> A_IWL<226> A_IWL<225> A_IWL<224> A_IWL<223> A_IWL<222> A_IWL<221> A_IWL<220> A_IWL<219> A_IWL<218> A_IWL<217> A_IWL<216> A_IWL<215> A_IWL<214> A_IWL<213> A_IWL<212> A_IWL<211> A_IWL<210> A_IWL<209> A_IWL<208> A_IWL<207> A_IWL<206> A_IWL<205> A_IWL<204> A_IWL<203> A_IWL<202> A_IWL<201> A_IWL<200> A_IWL<199> A_IWL<198> A_IWL<197> A_IWL<196> A_IWL<195> A_IWL<194> A_IWL<193> A_IWL<192> A_IWL<191> A_IWL<190> A_IWL<189> A_IWL<188> A_IWL<187> A_IWL<186> A_IWL<185> A_IWL<184> A_IWL<183> A_IWL<182> A_IWL<181> A_IWL<180> A_IWL<179> A_IWL<178> A_IWL<177> A_IWL<176> A_IWL<175> A_IWL<174> A_IWL<173> A_IWL<172> A_IWL<171> A_IWL<170> A_IWL<169> A_IWL<168> A_IWL<167> A_IWL<166> A_IWL<165> A_IWL<164> A_IWL<163> A_IWL<162> A_IWL<161> A_IWL<160> A_IWL<159> A_IWL<158> A_IWL<157> A_IWL<156> A_IWL<155> A_IWL<154> A_IWL<153> A_IWL<152> A_IWL<151> A_IWL<150> A_IWL<149> A_IWL<148> A_IWL<147> A_IWL<146> A_IWL<145> A_IWL<144> A_IWL<143> A_IWL<142> A_IWL<141> A_IWL<140> A_IWL<139> A_IWL<138> A_IWL<137> A_IWL<136> A_IWL<135> A_IWL<134> A_IWL<133> A_IWL<132> A_IWL<131> A_IWL<130> A_IWL<129> A_IWL<128> A_IWL<127> A_IWL<126> A_IWL<125> A_IWL<124> A_IWL<123> A_IWL<122> A_IWL<121> A_IWL<120> A_IWL<119> A_IWL<118> A_IWL<117> A_IWL<116> A_IWL<115> A_IWL<114> A_IWL<113> A_IWL<112> A_IWL<111> A_IWL<110> A_IWL<109> A_IWL<108> A_IWL<107> A_IWL<106> A_IWL<105> A_IWL<104> A_IWL<103> A_IWL<102> A_IWL<101> A_IWL<100> A_IWL<99> A_IWL<98> A_IWL<97> A_IWL<96> A_IWL<95> A_IWL<94> A_IWL<93> A_IWL<92> A_IWL<91> A_IWL<90> A_IWL<89> A_IWL<88> A_IWL<87> A_IWL<86> A_IWL<85> A_IWL<84> A_IWL<83> A_IWL<82> A_IWL<81> A_IWL<80> A_IWL<79> A_IWL<78> A_IWL<77> A_IWL<76> A_IWL<75> A_IWL<74> A_IWL<73> A_IWL<72> A_IWL<71> A_IWL<70> A_IWL<69> A_IWL<68> A_IWL<67> A_IWL<66> A_IWL<65> A_IWL<64> A_IWL<63> A_IWL<62> A_IWL<61> A_IWL<60> A_IWL<59> A_IWL<58> A_IWL<57> A_IWL<56> A_IWL<55> A_IWL<54> A_IWL<53> A_IWL<52> A_IWL<51> A_IWL<50> A_IWL<49> A_IWL<48> A_IWL<47> A_IWL<46> A_IWL<45> A_IWL<44> A_IWL<43> A_IWL<42> A_IWL<41> A_IWL<40> A_IWL<39> A_IWL<38> A_IWL<37> A_IWL<36> A_IWL<35> A_IWL<34> A_IWL<33> A_IWL<32> A_IWL<31> A_IWL<30> A_IWL<29> A_IWL<28> A_IWL<27> A_IWL<26> A_IWL<25> A_IWL<24> A_IWL<23> A_IWL<22> A_IWL<21> A_IWL<20> A_IWL<19> A_IWL<18> A_IWL<17> A_IWL<16> A_IWL<15> A_IWL<14> A_IWL<13> A_IWL<12> A_IWL<11> A_IWL<10> A_IWL<9> A_IWL<8> A_IWL<7> A_IWL<6> A_IWL<5> A_IWL<4> A_IWL<3> A_IWL<2> A_IWL<1> A_IWL<0> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_COLUMN_pcell_0 +.ENDS + + + + +.SUBCKT RM_IHPSG13_4096x8_c3_1P_DLY_pcell_2 A Z VDD VSS + XIDL<3> D<7> Z VDD VSS / RSC_IHPSG13_CDLYX1 + XIDL<2> D<6> D<7> VDD VSS / RSC_IHPSG13_CDLYX1 + XIDL<1> D<5> D<6> VDD VSS / RSC_IHPSG13_CDLYX1 + XIDM<5> D<4> D<5> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<4> D<3> D<4> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY + XIDM<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY +.ENDS + + +.SUBCKT RM_IHPSG13_4096x8_c3_1P_DLY_pcell_3 A Z VDD VSS + XIDL<7> D<7> Z VDD VSS / RSC_IHPSG13_CDLYX1 + XIDL<6> D<6> D<7> VDD VSS / RSC_IHPSG13_CDLYX1 + XIDL<5> D<5> D<6> VDD VSS / RSC_IHPSG13_CDLYX1 + XIDL<4> D<4> D<5> VDD VSS / RSC_IHPSG13_CDLYX1 + XIDL<3> D<3> D<4> VDD VSS / RSC_IHPSG13_CDLYX1 + XIDL<2> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1 + XIDL<1> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1 + XIDM A D<1> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY +.ENDS + + + +.SUBCKT RM_IHPSG13_1P_4096x8_c3_bm_bist A_ADDR<11> A_ADDR<10> A_ADDR<9> A_ADDR<8> A_ADDR<7> A_ADDR<6> A_ADDR<5> A_ADDR<4> A_ADDR<3> A_ADDR<2> A_ADDR<1> A_ADDR<0> A_BIST_ADDR<11> A_BIST_ADDR<10> A_BIST_ADDR<9> A_BIST_ADDR<8> A_BIST_ADDR<7> A_BIST_ADDR<6> A_BIST_ADDR<5> A_BIST_ADDR<4> A_BIST_ADDR<3> A_BIST_ADDR<2> A_BIST_ADDR<1> A_BIST_ADDR<0> A_BIST_BM<7> A_BIST_BM<6> A_BIST_BM<5> A_BIST_BM<4> A_BIST_BM<3> A_BIST_BM<2> A_BIST_BM<1> A_BIST_BM<0> A_BIST_CLK A_BIST_DIN<7> A_BIST_DIN<6> A_BIST_DIN<5> A_BIST_DIN<4> A_BIST_DIN<3> A_BIST_DIN<2> A_BIST_DIN<1> A_BIST_DIN<0> A_BIST_EN A_BIST_MEN A_BIST_REN A_BIST_WEN A_BM<7> A_BM<6> A_BM<5> A_BM<4> A_BM<3> A_BM<2> A_BM<1> A_BM<0> A_CLK A_DIN<7> A_DIN<6> A_DIN<5> A_DIN<4> A_DIN<3> A_DIN<2> A_DIN<1> A_DIN<0> A_DLY A_DOUT<7> A_DOUT<6> A_DOUT<5> A_DOUT<4> A_DOUT<3> A_DOUT<2> A_DOUT<1> A_DOUT<0> A_MEN A_REN A_WEN VDD! VDDARRAY! VSS! + + +XRAM<1> a_blc_r<31> a_blc_r<30> a_blc_r<29> a_blc_r<28> a_blc_r<27> a_blc_r<26> a_blc_r<25> a_blc_r<24> a_blc_r<23> a_blc_r<22> a_blc_r<21> a_blc_r<20> a_blc_r<19> a_blc_r<18> a_blc_r<17> a_blc_r<16> a_blc_r<15> a_blc_r<14> a_blc_r<13> a_blc_r<12> a_blc_r<11> a_blc_r<10> a_blc_r<9> a_blc_r<8> a_blc_r<7> a_blc_r<6> a_blc_r<5> a_blc_r<4> a_blc_r<3> a_blc_r<2> a_blc_r<1> a_blc_r<0> a_blt_r<31> a_blt_r<30> a_blt_r<29> a_blt_r<28> a_blt_r<27> a_blt_r<26> a_blt_r<25> a_blt_r<24> a_blt_r<23> a_blt_r<22> a_blt_r<21> a_blt_r<20> a_blt_r<19> a_blt_r<18> a_blt_r<17> a_blt_r<16> a_blt_r<15> a_blt_r<14> a_blt_r<13> a_blt_r<12> a_blt_r<11> a_blt_r<10> a_blt_r<9> a_blt_r<8> a_blt_r<7> a_blt_r<6> a_blt_r<5> a_blt_r<4> a_blt_r<3> a_blt_r<2> a_blt_r<1> a_blt_r<0> a_wl_r<511> a_wl_r<510> a_wl_r<509> a_wl_r<508> a_wl_r<507> a_wl_r<506> a_wl_r<505> a_wl_r<504> a_wl_r<503> a_wl_r<502> a_wl_r<501> a_wl_r<500> a_wl_r<499> a_wl_r<498> a_wl_r<497> a_wl_r<496> a_wl_r<495> a_wl_r<494> a_wl_r<493> a_wl_r<492> a_wl_r<491> a_wl_r<490> a_wl_r<489> a_wl_r<488> a_wl_r<487> a_wl_r<486> a_wl_r<485> a_wl_r<484> a_wl_r<483> a_wl_r<482> a_wl_r<481> a_wl_r<480> a_wl_r<479> a_wl_r<478> a_wl_r<477> a_wl_r<476> a_wl_r<475> a_wl_r<474> a_wl_r<473> a_wl_r<472> a_wl_r<471> a_wl_r<470> a_wl_r<469> a_wl_r<468> a_wl_r<467> a_wl_r<466> a_wl_r<465> a_wl_r<464> a_wl_r<463> a_wl_r<462> a_wl_r<461> a_wl_r<460> a_wl_r<459> a_wl_r<458> a_wl_r<457> a_wl_r<456> a_wl_r<455> a_wl_r<454> a_wl_r<453> a_wl_r<452> a_wl_r<451> a_wl_r<450> a_wl_r<449> a_wl_r<448> a_wl_r<447> a_wl_r<446> a_wl_r<445> a_wl_r<444> a_wl_r<443> a_wl_r<442> a_wl_r<441> a_wl_r<440> a_wl_r<439> a_wl_r<438> a_wl_r<437> a_wl_r<436> a_wl_r<435> a_wl_r<434> a_wl_r<433> a_wl_r<432> a_wl_r<431> a_wl_r<430> a_wl_r<429> a_wl_r<428> a_wl_r<427> a_wl_r<426> a_wl_r<425> a_wl_r<424> a_wl_r<423> a_wl_r<422> a_wl_r<421> a_wl_r<420> a_wl_r<419> a_wl_r<418> a_wl_r<417> a_wl_r<416> a_wl_r<415> a_wl_r<414> a_wl_r<413> a_wl_r<412> a_wl_r<411> a_wl_r<410> a_wl_r<409> a_wl_r<408> a_wl_r<407> a_wl_r<406> a_wl_r<405> a_wl_r<404> a_wl_r<403> a_wl_r<402> a_wl_r<401> a_wl_r<400> a_wl_r<399> a_wl_r<398> a_wl_r<397> a_wl_r<396> a_wl_r<395> a_wl_r<394> a_wl_r<393> a_wl_r<392> a_wl_r<391> a_wl_r<390> a_wl_r<389> a_wl_r<388> a_wl_r<387> a_wl_r<386> a_wl_r<385> a_wl_r<384> a_wl_r<383> a_wl_r<382> a_wl_r<381> a_wl_r<380> a_wl_r<379> a_wl_r<378> a_wl_r<377> a_wl_r<376> a_wl_r<375> a_wl_r<374> a_wl_r<373> a_wl_r<372> a_wl_r<371> a_wl_r<370> a_wl_r<369> a_wl_r<368> a_wl_r<367> a_wl_r<366> a_wl_r<365> a_wl_r<364> a_wl_r<363> a_wl_r<362> a_wl_r<361> a_wl_r<360> a_wl_r<359> a_wl_r<358> a_wl_r<357> a_wl_r<356> a_wl_r<355> a_wl_r<354> a_wl_r<353> a_wl_r<352> a_wl_r<351> a_wl_r<350> a_wl_r<349> a_wl_r<348> a_wl_r<347> a_wl_r<346> a_wl_r<345> a_wl_r<344> a_wl_r<343> a_wl_r<342> a_wl_r<341> a_wl_r<340> a_wl_r<339> a_wl_r<338> a_wl_r<337> a_wl_r<336> a_wl_r<335> a_wl_r<334> a_wl_r<333> a_wl_r<332> a_wl_r<331> a_wl_r<330> a_wl_r<329> a_wl_r<328> a_wl_r<327> a_wl_r<326> a_wl_r<325> a_wl_r<324> a_wl_r<323> a_wl_r<322> a_wl_r<321> a_wl_r<320> a_wl_r<319> a_wl_r<318> a_wl_r<317> a_wl_r<316> a_wl_r<315> a_wl_r<314> a_wl_r<313> a_wl_r<312> a_wl_r<311> a_wl_r<310> a_wl_r<309> a_wl_r<308> a_wl_r<307> a_wl_r<306> a_wl_r<305> a_wl_r<304> a_wl_r<303> a_wl_r<302> a_wl_r<301> a_wl_r<300> a_wl_r<299> a_wl_r<298> a_wl_r<297> a_wl_r<296> a_wl_r<295> a_wl_r<294> a_wl_r<293> a_wl_r<292> a_wl_r<291> a_wl_r<290> a_wl_r<289> a_wl_r<288> a_wl_r<287> a_wl_r<286> a_wl_r<285> a_wl_r<284> a_wl_r<283> a_wl_r<282> a_wl_r<281> a_wl_r<280> a_wl_r<279> a_wl_r<278> a_wl_r<277> a_wl_r<276> a_wl_r<275> a_wl_r<274> a_wl_r<273> a_wl_r<272> a_wl_r<271> a_wl_r<270> a_wl_r<269> a_wl_r<268> a_wl_r<267> a_wl_r<266> a_wl_r<265> a_wl_r<264> a_wl_r<263> a_wl_r<262> a_wl_r<261> a_wl_r<260> a_wl_r<259> a_wl_r<258> a_wl_r<257> a_wl_r<256> a_wl_r<255> a_wl_r<254> a_wl_r<253> a_wl_r<252> a_wl_r<251> a_wl_r<250> a_wl_r<249> a_wl_r<248> a_wl_r<247> a_wl_r<246> a_wl_r<245> a_wl_r<244> a_wl_r<243> a_wl_r<242> a_wl_r<241> a_wl_r<240> a_wl_r<239> a_wl_r<238> a_wl_r<237> a_wl_r<236> a_wl_r<235> a_wl_r<234> a_wl_r<233> a_wl_r<232> a_wl_r<231> a_wl_r<230> a_wl_r<229> a_wl_r<228> a_wl_r<227> a_wl_r<226> a_wl_r<225> a_wl_r<224> a_wl_r<223> a_wl_r<222> a_wl_r<221> a_wl_r<220> a_wl_r<219> a_wl_r<218> a_wl_r<217> a_wl_r<216> a_wl_r<215> a_wl_r<214> a_wl_r<213> a_wl_r<212> a_wl_r<211> a_wl_r<210> a_wl_r<209> a_wl_r<208> a_wl_r<207> a_wl_r<206> a_wl_r<205> a_wl_r<204> a_wl_r<203> a_wl_r<202> a_wl_r<201> a_wl_r<200> a_wl_r<199> a_wl_r<198> a_wl_r<197> a_wl_r<196> a_wl_r<195> a_wl_r<194> a_wl_r<193> a_wl_r<192> a_wl_r<191> a_wl_r<190> a_wl_r<189> a_wl_r<188> a_wl_r<187> a_wl_r<186> a_wl_r<185> a_wl_r<184> a_wl_r<183> a_wl_r<182> a_wl_r<181> a_wl_r<180> a_wl_r<179> a_wl_r<178> a_wl_r<177> a_wl_r<176> a_wl_r<175> a_wl_r<174> a_wl_r<173> a_wl_r<172> a_wl_r<171> a_wl_r<170> a_wl_r<169> a_wl_r<168> a_wl_r<167> a_wl_r<166> a_wl_r<165> a_wl_r<164> a_wl_r<163> a_wl_r<162> a_wl_r<161> a_wl_r<160> a_wl_r<159> a_wl_r<158> a_wl_r<157> a_wl_r<156> a_wl_r<155> a_wl_r<154> a_wl_r<153> a_wl_r<152> a_wl_r<151> a_wl_r<150> a_wl_r<149> a_wl_r<148> a_wl_r<147> a_wl_r<146> a_wl_r<145> a_wl_r<144> a_wl_r<143> a_wl_r<142> a_wl_r<141> a_wl_r<140> a_wl_r<139> a_wl_r<138> a_wl_r<137> a_wl_r<136> a_wl_r<135> a_wl_r<134> a_wl_r<133> a_wl_r<132> a_wl_r<131> a_wl_r<130> a_wl_r<129> a_wl_r<128> a_wl_r<127> a_wl_r<126> a_wl_r<125> a_wl_r<124> a_wl_r<123> a_wl_r<122> a_wl_r<121> a_wl_r<120> a_wl_r<119> a_wl_r<118> a_wl_r<117> a_wl_r<116> a_wl_r<115> a_wl_r<114> a_wl_r<113> a_wl_r<112> a_wl_r<111> a_wl_r<110> a_wl_r<109> a_wl_r<108> a_wl_r<107> a_wl_r<106> a_wl_r<105> a_wl_r<104> a_wl_r<103> a_wl_r<102> a_wl_r<101> a_wl_r<100> a_wl_r<99> a_wl_r<98> a_wl_r<97> a_wl_r<96> a_wl_r<95> a_wl_r<94> a_wl_r<93> a_wl_r<92> a_wl_r<91> a_wl_r<90> a_wl_r<89> a_wl_r<88> a_wl_r<87> a_wl_r<86> a_wl_r<85> a_wl_r<84> a_wl_r<83> a_wl_r<82> a_wl_r<81> a_wl_r<80> a_wl_r<79> a_wl_r<78> a_wl_r<77> a_wl_r<76> a_wl_r<75> a_wl_r<74> a_wl_r<73> a_wl_r<72> a_wl_r<71> a_wl_r<70> a_wl_r<69> a_wl_r<68> a_wl_r<67> a_wl_r<66> a_wl_r<65> a_wl_r<64> a_wl_r<63> a_wl_r<62> a_wl_r<61> a_wl_r<60> a_wl_r<59> a_wl_r<58> a_wl_r<57> a_wl_r<56> a_wl_r<55> a_wl_r<54> a_wl_r<53> a_wl_r<52> a_wl_r<51> a_wl_r<50> a_wl_r<49> a_wl_r<48> a_wl_r<47> a_wl_r<46> a_wl_r<45> a_wl_r<44> a_wl_r<43> a_wl_r<42> a_wl_r<41> a_wl_r<40> a_wl_r<39> a_wl_r<38> a_wl_r<37> a_wl_r<36> a_wl_r<35> a_wl_r<34> a_wl_r<33> a_wl_r<32> a_wl_r<31> a_wl_r<30> a_wl_r<29> a_wl_r<28> a_wl_r<27> a_wl_r<26> a_wl_r<25> a_wl_r<24> a_wl_r<23> a_wl_r<22> a_wl_r<21> a_wl_r<20> a_wl_r<19> a_wl_r<18> a_wl_r<17> a_wl_r<16> a_wl_r<15> a_wl_r<14> a_wl_r<13> a_wl_r<12> a_wl_r<11> a_wl_r<10> a_wl_r<9> a_wl_r<8> a_wl_r<7> a_wl_r<6> a_wl_r<5> a_wl_r<4> a_wl_r<3> a_wl_r<2> a_wl_r<1> a_wl_r<0> VDDARRAY! VSS! / RM_IHPSG13_4096x8_c3_1P_MATRIX_pcell_1 +XRAM<0> a_blc_l<31> a_blc_l<30> a_blc_l<29> a_blc_l<28> a_blc_l<27> a_blc_l<26> a_blc_l<25> a_blc_l<24> a_blc_l<23> a_blc_l<22> a_blc_l<21> a_blc_l<20> a_blc_l<19> a_blc_l<18> a_blc_l<17> a_blc_l<16> a_blc_l<15> a_blc_l<14> a_blc_l<13> a_blc_l<12> a_blc_l<11> a_blc_l<10> a_blc_l<9> a_blc_l<8> a_blc_l<7> a_blc_l<6> a_blc_l<5> a_blc_l<4> a_blc_l<3> a_blc_l<2> a_blc_l<1> a_blc_l<0> a_blt_l<31> a_blt_l<30> a_blt_l<29> a_blt_l<28> a_blt_l<27> a_blt_l<26> a_blt_l<25> a_blt_l<24> a_blt_l<23> a_blt_l<22> a_blt_l<21> a_blt_l<20> a_blt_l<19> a_blt_l<18> a_blt_l<17> a_blt_l<16> a_blt_l<15> a_blt_l<14> a_blt_l<13> a_blt_l<12> a_blt_l<11> a_blt_l<10> a_blt_l<9> a_blt_l<8> a_blt_l<7> a_blt_l<6> a_blt_l<5> a_blt_l<4> a_blt_l<3> a_blt_l<2> a_blt_l<1> a_blt_l<0> a_wl_l<511> a_wl_l<510> a_wl_l<509> a_wl_l<508> a_wl_l<507> a_wl_l<506> a_wl_l<505> a_wl_l<504> a_wl_l<503> a_wl_l<502> a_wl_l<501> a_wl_l<500> a_wl_l<499> a_wl_l<498> a_wl_l<497> a_wl_l<496> a_wl_l<495> a_wl_l<494> a_wl_l<493> a_wl_l<492> a_wl_l<491> a_wl_l<490> a_wl_l<489> a_wl_l<488> a_wl_l<487> a_wl_l<486> a_wl_l<485> a_wl_l<484> a_wl_l<483> a_wl_l<482> a_wl_l<481> a_wl_l<480> a_wl_l<479> a_wl_l<478> a_wl_l<477> a_wl_l<476> a_wl_l<475> a_wl_l<474> a_wl_l<473> a_wl_l<472> a_wl_l<471> a_wl_l<470> a_wl_l<469> a_wl_l<468> a_wl_l<467> a_wl_l<466> a_wl_l<465> a_wl_l<464> a_wl_l<463> a_wl_l<462> a_wl_l<461> a_wl_l<460> a_wl_l<459> a_wl_l<458> a_wl_l<457> a_wl_l<456> a_wl_l<455> a_wl_l<454> a_wl_l<453> a_wl_l<452> a_wl_l<451> a_wl_l<450> a_wl_l<449> a_wl_l<448> a_wl_l<447> a_wl_l<446> a_wl_l<445> a_wl_l<444> a_wl_l<443> a_wl_l<442> a_wl_l<441> a_wl_l<440> a_wl_l<439> a_wl_l<438> a_wl_l<437> a_wl_l<436> a_wl_l<435> a_wl_l<434> a_wl_l<433> a_wl_l<432> a_wl_l<431> a_wl_l<430> a_wl_l<429> a_wl_l<428> a_wl_l<427> a_wl_l<426> a_wl_l<425> a_wl_l<424> a_wl_l<423> a_wl_l<422> a_wl_l<421> a_wl_l<420> a_wl_l<419> a_wl_l<418> a_wl_l<417> a_wl_l<416> a_wl_l<415> a_wl_l<414> a_wl_l<413> a_wl_l<412> a_wl_l<411> a_wl_l<410> a_wl_l<409> a_wl_l<408> a_wl_l<407> a_wl_l<406> a_wl_l<405> a_wl_l<404> a_wl_l<403> a_wl_l<402> a_wl_l<401> a_wl_l<400> a_wl_l<399> a_wl_l<398> a_wl_l<397> a_wl_l<396> a_wl_l<395> a_wl_l<394> a_wl_l<393> a_wl_l<392> a_wl_l<391> a_wl_l<390> a_wl_l<389> a_wl_l<388> a_wl_l<387> a_wl_l<386> a_wl_l<385> a_wl_l<384> a_wl_l<383> a_wl_l<382> a_wl_l<381> a_wl_l<380> a_wl_l<379> a_wl_l<378> a_wl_l<377> a_wl_l<376> a_wl_l<375> a_wl_l<374> a_wl_l<373> a_wl_l<372> a_wl_l<371> a_wl_l<370> a_wl_l<369> a_wl_l<368> a_wl_l<367> a_wl_l<366> a_wl_l<365> a_wl_l<364> a_wl_l<363> a_wl_l<362> a_wl_l<361> a_wl_l<360> a_wl_l<359> a_wl_l<358> a_wl_l<357> a_wl_l<356> a_wl_l<355> a_wl_l<354> a_wl_l<353> a_wl_l<352> a_wl_l<351> a_wl_l<350> a_wl_l<349> a_wl_l<348> a_wl_l<347> a_wl_l<346> a_wl_l<345> a_wl_l<344> a_wl_l<343> a_wl_l<342> a_wl_l<341> a_wl_l<340> a_wl_l<339> a_wl_l<338> a_wl_l<337> a_wl_l<336> a_wl_l<335> a_wl_l<334> a_wl_l<333> a_wl_l<332> a_wl_l<331> a_wl_l<330> a_wl_l<329> a_wl_l<328> a_wl_l<327> a_wl_l<326> a_wl_l<325> a_wl_l<324> a_wl_l<323> a_wl_l<322> a_wl_l<321> a_wl_l<320> a_wl_l<319> a_wl_l<318> a_wl_l<317> a_wl_l<316> a_wl_l<315> a_wl_l<314> a_wl_l<313> a_wl_l<312> a_wl_l<311> a_wl_l<310> a_wl_l<309> a_wl_l<308> a_wl_l<307> a_wl_l<306> a_wl_l<305> a_wl_l<304> a_wl_l<303> a_wl_l<302> a_wl_l<301> a_wl_l<300> a_wl_l<299> a_wl_l<298> a_wl_l<297> a_wl_l<296> a_wl_l<295> a_wl_l<294> a_wl_l<293> a_wl_l<292> a_wl_l<291> a_wl_l<290> a_wl_l<289> a_wl_l<288> a_wl_l<287> a_wl_l<286> a_wl_l<285> a_wl_l<284> a_wl_l<283> a_wl_l<282> a_wl_l<281> a_wl_l<280> a_wl_l<279> a_wl_l<278> a_wl_l<277> a_wl_l<276> a_wl_l<275> a_wl_l<274> a_wl_l<273> a_wl_l<272> a_wl_l<271> a_wl_l<270> a_wl_l<269> a_wl_l<268> a_wl_l<267> a_wl_l<266> a_wl_l<265> a_wl_l<264> a_wl_l<263> a_wl_l<262> a_wl_l<261> a_wl_l<260> a_wl_l<259> a_wl_l<258> a_wl_l<257> a_wl_l<256> a_wl_l<255> a_wl_l<254> a_wl_l<253> a_wl_l<252> a_wl_l<251> a_wl_l<250> a_wl_l<249> a_wl_l<248> a_wl_l<247> a_wl_l<246> a_wl_l<245> a_wl_l<244> a_wl_l<243> a_wl_l<242> a_wl_l<241> a_wl_l<240> a_wl_l<239> a_wl_l<238> a_wl_l<237> a_wl_l<236> a_wl_l<235> a_wl_l<234> a_wl_l<233> a_wl_l<232> a_wl_l<231> a_wl_l<230> a_wl_l<229> a_wl_l<228> a_wl_l<227> a_wl_l<226> a_wl_l<225> a_wl_l<224> a_wl_l<223> a_wl_l<222> a_wl_l<221> a_wl_l<220> a_wl_l<219> a_wl_l<218> a_wl_l<217> a_wl_l<216> a_wl_l<215> a_wl_l<214> a_wl_l<213> a_wl_l<212> a_wl_l<211> a_wl_l<210> a_wl_l<209> a_wl_l<208> a_wl_l<207> a_wl_l<206> a_wl_l<205> a_wl_l<204> a_wl_l<203> a_wl_l<202> a_wl_l<201> a_wl_l<200> a_wl_l<199> a_wl_l<198> a_wl_l<197> a_wl_l<196> a_wl_l<195> a_wl_l<194> a_wl_l<193> a_wl_l<192> a_wl_l<191> a_wl_l<190> a_wl_l<189> a_wl_l<188> a_wl_l<187> a_wl_l<186> a_wl_l<185> a_wl_l<184> a_wl_l<183> a_wl_l<182> a_wl_l<181> a_wl_l<180> a_wl_l<179> a_wl_l<178> a_wl_l<177> a_wl_l<176> a_wl_l<175> a_wl_l<174> a_wl_l<173> a_wl_l<172> a_wl_l<171> a_wl_l<170> a_wl_l<169> a_wl_l<168> a_wl_l<167> a_wl_l<166> a_wl_l<165> a_wl_l<164> a_wl_l<163> a_wl_l<162> a_wl_l<161> a_wl_l<160> a_wl_l<159> a_wl_l<158> a_wl_l<157> a_wl_l<156> a_wl_l<155> a_wl_l<154> a_wl_l<153> a_wl_l<152> a_wl_l<151> a_wl_l<150> a_wl_l<149> a_wl_l<148> a_wl_l<147> a_wl_l<146> a_wl_l<145> a_wl_l<144> a_wl_l<143> a_wl_l<142> a_wl_l<141> a_wl_l<140> a_wl_l<139> a_wl_l<138> a_wl_l<137> a_wl_l<136> a_wl_l<135> a_wl_l<134> a_wl_l<133> a_wl_l<132> a_wl_l<131> a_wl_l<130> a_wl_l<129> a_wl_l<128> a_wl_l<127> a_wl_l<126> a_wl_l<125> a_wl_l<124> a_wl_l<123> a_wl_l<122> a_wl_l<121> a_wl_l<120> a_wl_l<119> a_wl_l<118> a_wl_l<117> a_wl_l<116> a_wl_l<115> a_wl_l<114> a_wl_l<113> a_wl_l<112> a_wl_l<111> a_wl_l<110> a_wl_l<109> a_wl_l<108> a_wl_l<107> a_wl_l<106> a_wl_l<105> a_wl_l<104> a_wl_l<103> a_wl_l<102> a_wl_l<101> a_wl_l<100> a_wl_l<99> a_wl_l<98> a_wl_l<97> a_wl_l<96> a_wl_l<95> a_wl_l<94> a_wl_l<93> a_wl_l<92> a_wl_l<91> a_wl_l<90> a_wl_l<89> a_wl_l<88> a_wl_l<87> a_wl_l<86> a_wl_l<85> a_wl_l<84> a_wl_l<83> a_wl_l<82> a_wl_l<81> a_wl_l<80> a_wl_l<79> a_wl_l<78> a_wl_l<77> a_wl_l<76> a_wl_l<75> a_wl_l<74> a_wl_l<73> a_wl_l<72> a_wl_l<71> a_wl_l<70> a_wl_l<69> a_wl_l<68> a_wl_l<67> a_wl_l<66> a_wl_l<65> a_wl_l<64> a_wl_l<63> a_wl_l<62> a_wl_l<61> a_wl_l<60> a_wl_l<59> a_wl_l<58> a_wl_l<57> a_wl_l<56> a_wl_l<55> a_wl_l<54> a_wl_l<53> a_wl_l<52> a_wl_l<51> a_wl_l<50> a_wl_l<49> a_wl_l<48> a_wl_l<47> a_wl_l<46> a_wl_l<45> a_wl_l<44> a_wl_l<43> a_wl_l<42> a_wl_l<41> a_wl_l<40> a_wl_l<39> a_wl_l<38> a_wl_l<37> a_wl_l<36> a_wl_l<35> a_wl_l<34> a_wl_l<33> a_wl_l<32> a_wl_l<31> a_wl_l<30> a_wl_l<29> a_wl_l<28> a_wl_l<27> a_wl_l<26> a_wl_l<25> a_wl_l<24> a_wl_l<23> a_wl_l<22> a_wl_l<21> a_wl_l<20> a_wl_l<19> a_wl_l<18> a_wl_l<17> a_wl_l<16> a_wl_l<15> a_wl_l<14> a_wl_l<13> a_wl_l<12> a_wl_l<11> a_wl_l<10> a_wl_l<9> a_wl_l<8> a_wl_l<7> a_wl_l<6> a_wl_l<5> a_wl_l<4> a_wl_l<3> a_wl_l<2> a_wl_l<1> a_wl_l<0> VDDARRAY! VSS! / RM_IHPSG13_4096x8_c3_1P_MATRIX_pcell_1 + + +XA_COLDRV<1> a_addr_col<1> a_addr_col<0> a_addr_col_r<1> a_addr_col_r<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> a_dclk a_dclk_p_r<0> a_rclk a_rclk_p_r<0> a_wclk a_wclk_p_r<0> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_COLDRV13X4 +XA_COLDRV<0> a_addr_col<1> a_addr_col<0> a_addr_col_l<1> a_addr_col_l<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> a_dclk a_dclk_p_l<0> a_rclk a_rclk_p_l<0> a_wclk a_wclk_p_l<0> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_COLDRV13X4 + + +XA_WLDRV<63> a_wi<511> a_wi<510> a_wi<509> a_wi<508> a_wi<507> a_wi<506> a_wi<505> a_wi<504> a_wi<503> a_wi<502> a_wi<501> a_wi<500> a_wi<499> a_wi<498> a_wi<497> a_wi<496> a_wl_r<511> a_wl_r<510> a_wl_r<509> a_wl_r<508> a_wl_r<507> a_wl_r<506> a_wl_r<505> a_wl_r<504> a_wl_r<503> a_wl_r<502> a_wl_r<501> a_wl_r<500> a_wl_r<499> a_wl_r<498> a_wl_r<497> a_wl_r<496> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4 +XA_WLDRV<62> a_wi<495> a_wi<494> a_wi<493> a_wi<492> a_wi<491> a_wi<490> a_wi<489> a_wi<488> a_wi<487> a_wi<486> a_wi<485> a_wi<484> a_wi<483> a_wi<482> a_wi<481> a_wi<480> a_wl_r<495> a_wl_r<494> a_wl_r<493> a_wl_r<492> a_wl_r<491> a_wl_r<490> a_wl_r<489> a_wl_r<488> a_wl_r<487> a_wl_r<486> a_wl_r<485> a_wl_r<484> a_wl_r<483> a_wl_r<482> a_wl_r<481> a_wl_r<480> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4 +XA_WLDRV<61> a_wi<479> a_wi<478> a_wi<477> a_wi<476> a_wi<475> a_wi<474> a_wi<473> a_wi<472> a_wi<471> a_wi<470> a_wi<469> a_wi<468> a_wi<467> a_wi<466> a_wi<465> a_wi<464> a_wl_r<479> a_wl_r<478> a_wl_r<477> a_wl_r<476> a_wl_r<475> a_wl_r<474> a_wl_r<473> a_wl_r<472> a_wl_r<471> a_wl_r<470> a_wl_r<469> a_wl_r<468> a_wl_r<467> a_wl_r<466> a_wl_r<465> a_wl_r<464> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4 +XA_WLDRV<60> a_wi<463> a_wi<462> a_wi<461> a_wi<460> a_wi<459> a_wi<458> a_wi<457> a_wi<456> a_wi<455> a_wi<454> a_wi<453> a_wi<452> a_wi<451> a_wi<450> a_wi<449> a_wi<448> a_wl_r<463> a_wl_r<462> a_wl_r<461> a_wl_r<460> a_wl_r<459> a_wl_r<458> a_wl_r<457> a_wl_r<456> a_wl_r<455> a_wl_r<454> a_wl_r<453> a_wl_r<452> a_wl_r<451> a_wl_r<450> a_wl_r<449> a_wl_r<448> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4 +XA_WLDRV<59> a_wi<447> a_wi<446> a_wi<445> a_wi<444> a_wi<443> a_wi<442> a_wi<441> a_wi<440> a_wi<439> a_wi<438> a_wi<437> a_wi<436> a_wi<435> a_wi<434> a_wi<433> a_wi<432> a_wl_r<447> a_wl_r<446> a_wl_r<445> a_wl_r<444> a_wl_r<443> a_wl_r<442> a_wl_r<441> a_wl_r<440> a_wl_r<439> a_wl_r<438> a_wl_r<437> a_wl_r<436> a_wl_r<435> a_wl_r<434> a_wl_r<433> a_wl_r<432> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4 +XA_WLDRV<58> a_wi<431> a_wi<430> a_wi<429> a_wi<428> a_wi<427> a_wi<426> a_wi<425> a_wi<424> a_wi<423> a_wi<422> a_wi<421> a_wi<420> a_wi<419> a_wi<418> a_wi<417> a_wi<416> a_wl_r<431> a_wl_r<430> a_wl_r<429> a_wl_r<428> a_wl_r<427> a_wl_r<426> a_wl_r<425> a_wl_r<424> a_wl_r<423> a_wl_r<422> a_wl_r<421> a_wl_r<420> a_wl_r<419> a_wl_r<418> a_wl_r<417> a_wl_r<416> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4 +XA_WLDRV<57> a_wi<415> a_wi<414> a_wi<413> a_wi<412> a_wi<411> a_wi<410> a_wi<409> a_wi<408> a_wi<407> a_wi<406> a_wi<405> a_wi<404> a_wi<403> a_wi<402> a_wi<401> a_wi<400> a_wl_r<415> a_wl_r<414> a_wl_r<413> a_wl_r<412> a_wl_r<411> a_wl_r<410> a_wl_r<409> a_wl_r<408> a_wl_r<407> a_wl_r<406> a_wl_r<405> a_wl_r<404> a_wl_r<403> a_wl_r<402> a_wl_r<401> a_wl_r<400> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4 +XA_WLDRV<56> a_wi<399> a_wi<398> a_wi<397> a_wi<396> a_wi<395> a_wi<394> a_wi<393> a_wi<392> a_wi<391> a_wi<390> a_wi<389> a_wi<388> a_wi<387> a_wi<386> a_wi<385> a_wi<384> a_wl_r<399> a_wl_r<398> a_wl_r<397> a_wl_r<396> a_wl_r<395> a_wl_r<394> a_wl_r<393> a_wl_r<392> a_wl_r<391> a_wl_r<390> a_wl_r<389> a_wl_r<388> a_wl_r<387> a_wl_r<386> a_wl_r<385> a_wl_r<384> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4 +XA_WLDRV<55> a_wi<383> a_wi<382> a_wi<381> a_wi<380> a_wi<379> a_wi<378> a_wi<377> a_wi<376> a_wi<375> a_wi<374> a_wi<373> a_wi<372> a_wi<371> a_wi<370> a_wi<369> a_wi<368> a_wl_r<383> a_wl_r<382> a_wl_r<381> a_wl_r<380> a_wl_r<379> a_wl_r<378> a_wl_r<377> a_wl_r<376> a_wl_r<375> a_wl_r<374> a_wl_r<373> a_wl_r<372> a_wl_r<371> a_wl_r<370> a_wl_r<369> a_wl_r<368> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4 +XA_WLDRV<54> a_wi<367> a_wi<366> a_wi<365> a_wi<364> a_wi<363> a_wi<362> a_wi<361> a_wi<360> a_wi<359> a_wi<358> a_wi<357> a_wi<356> a_wi<355> a_wi<354> a_wi<353> a_wi<352> a_wl_r<367> a_wl_r<366> a_wl_r<365> a_wl_r<364> a_wl_r<363> a_wl_r<362> a_wl_r<361> a_wl_r<360> a_wl_r<359> a_wl_r<358> a_wl_r<357> a_wl_r<356> a_wl_r<355> a_wl_r<354> a_wl_r<353> a_wl_r<352> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4 +XA_WLDRV<53> a_wi<351> a_wi<350> a_wi<349> a_wi<348> a_wi<347> a_wi<346> a_wi<345> a_wi<344> a_wi<343> a_wi<342> a_wi<341> a_wi<340> a_wi<339> a_wi<338> a_wi<337> a_wi<336> a_wl_r<351> a_wl_r<350> a_wl_r<349> a_wl_r<348> a_wl_r<347> a_wl_r<346> a_wl_r<345> a_wl_r<344> a_wl_r<343> a_wl_r<342> a_wl_r<341> a_wl_r<340> a_wl_r<339> a_wl_r<338> a_wl_r<337> a_wl_r<336> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4 +XA_WLDRV<52> a_wi<335> a_wi<334> a_wi<333> a_wi<332> a_wi<331> a_wi<330> a_wi<329> a_wi<328> a_wi<327> a_wi<326> a_wi<325> a_wi<324> a_wi<323> a_wi<322> a_wi<321> a_wi<320> a_wl_r<335> a_wl_r<334> a_wl_r<333> a_wl_r<332> a_wl_r<331> a_wl_r<330> a_wl_r<329> a_wl_r<328> a_wl_r<327> a_wl_r<326> a_wl_r<325> a_wl_r<324> a_wl_r<323> a_wl_r<322> a_wl_r<321> a_wl_r<320> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4 +XA_WLDRV<51> a_wi<319> a_wi<318> a_wi<317> a_wi<316> a_wi<315> a_wi<314> a_wi<313> a_wi<312> a_wi<311> a_wi<310> a_wi<309> a_wi<308> a_wi<307> a_wi<306> a_wi<305> a_wi<304> a_wl_r<319> a_wl_r<318> a_wl_r<317> a_wl_r<316> a_wl_r<315> a_wl_r<314> a_wl_r<313> a_wl_r<312> a_wl_r<311> a_wl_r<310> a_wl_r<309> a_wl_r<308> a_wl_r<307> a_wl_r<306> a_wl_r<305> a_wl_r<304> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4 +XA_WLDRV<50> a_wi<303> a_wi<302> a_wi<301> a_wi<300> a_wi<299> a_wi<298> a_wi<297> a_wi<296> a_wi<295> a_wi<294> a_wi<293> a_wi<292> a_wi<291> a_wi<290> a_wi<289> a_wi<288> a_wl_r<303> a_wl_r<302> a_wl_r<301> a_wl_r<300> a_wl_r<299> a_wl_r<298> a_wl_r<297> a_wl_r<296> a_wl_r<295> a_wl_r<294> a_wl_r<293> a_wl_r<292> a_wl_r<291> a_wl_r<290> a_wl_r<289> a_wl_r<288> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4 +XA_WLDRV<49> a_wi<287> a_wi<286> a_wi<285> a_wi<284> a_wi<283> a_wi<282> a_wi<281> a_wi<280> a_wi<279> a_wi<278> a_wi<277> a_wi<276> a_wi<275> a_wi<274> a_wi<273> a_wi<272> a_wl_r<287> a_wl_r<286> a_wl_r<285> a_wl_r<284> a_wl_r<283> a_wl_r<282> a_wl_r<281> a_wl_r<280> a_wl_r<279> a_wl_r<278> a_wl_r<277> a_wl_r<276> a_wl_r<275> a_wl_r<274> a_wl_r<273> a_wl_r<272> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4 +XA_WLDRV<48> a_wi<271> a_wi<270> a_wi<269> a_wi<268> a_wi<267> a_wi<266> a_wi<265> a_wi<264> a_wi<263> a_wi<262> a_wi<261> a_wi<260> a_wi<259> a_wi<258> a_wi<257> a_wi<256> a_wl_r<271> a_wl_r<270> a_wl_r<269> a_wl_r<268> a_wl_r<267> a_wl_r<266> a_wl_r<265> a_wl_r<264> a_wl_r<263> a_wl_r<262> a_wl_r<261> a_wl_r<260> a_wl_r<259> a_wl_r<258> a_wl_r<257> a_wl_r<256> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4 +XA_WLDRV<47> a_wi<255> a_wi<254> a_wi<253> a_wi<252> a_wi<251> a_wi<250> a_wi<249> a_wi<248> a_wi<247> a_wi<246> a_wi<245> a_wi<244> a_wi<243> a_wi<242> a_wi<241> a_wi<240> a_wl_r<255> a_wl_r<254> a_wl_r<253> a_wl_r<252> a_wl_r<251> a_wl_r<250> a_wl_r<249> a_wl_r<248> a_wl_r<247> a_wl_r<246> a_wl_r<245> a_wl_r<244> a_wl_r<243> a_wl_r<242> a_wl_r<241> a_wl_r<240> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4 +XA_WLDRV<46> a_wi<239> a_wi<238> a_wi<237> a_wi<236> a_wi<235> a_wi<234> a_wi<233> a_wi<232> a_wi<231> a_wi<230> a_wi<229> a_wi<228> a_wi<227> a_wi<226> a_wi<225> a_wi<224> a_wl_r<239> a_wl_r<238> a_wl_r<237> a_wl_r<236> a_wl_r<235> a_wl_r<234> a_wl_r<233> a_wl_r<232> a_wl_r<231> a_wl_r<230> a_wl_r<229> a_wl_r<228> a_wl_r<227> a_wl_r<226> a_wl_r<225> a_wl_r<224> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4 +XA_WLDRV<45> a_wi<223> a_wi<222> a_wi<221> a_wi<220> a_wi<219> a_wi<218> a_wi<217> a_wi<216> a_wi<215> a_wi<214> a_wi<213> a_wi<212> a_wi<211> a_wi<210> a_wi<209> a_wi<208> a_wl_r<223> a_wl_r<222> a_wl_r<221> a_wl_r<220> a_wl_r<219> a_wl_r<218> a_wl_r<217> a_wl_r<216> a_wl_r<215> a_wl_r<214> a_wl_r<213> a_wl_r<212> a_wl_r<211> a_wl_r<210> a_wl_r<209> a_wl_r<208> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4 +XA_WLDRV<44> a_wi<207> a_wi<206> a_wi<205> a_wi<204> a_wi<203> a_wi<202> a_wi<201> a_wi<200> a_wi<199> a_wi<198> a_wi<197> a_wi<196> a_wi<195> a_wi<194> a_wi<193> a_wi<192> a_wl_r<207> a_wl_r<206> a_wl_r<205> a_wl_r<204> a_wl_r<203> a_wl_r<202> a_wl_r<201> a_wl_r<200> a_wl_r<199> a_wl_r<198> a_wl_r<197> a_wl_r<196> a_wl_r<195> a_wl_r<194> a_wl_r<193> a_wl_r<192> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4 +XA_WLDRV<43> a_wi<191> a_wi<190> a_wi<189> a_wi<188> a_wi<187> a_wi<186> a_wi<185> a_wi<184> a_wi<183> a_wi<182> a_wi<181> a_wi<180> a_wi<179> a_wi<178> a_wi<177> a_wi<176> a_wl_r<191> a_wl_r<190> a_wl_r<189> a_wl_r<188> a_wl_r<187> a_wl_r<186> a_wl_r<185> a_wl_r<184> a_wl_r<183> a_wl_r<182> a_wl_r<181> a_wl_r<180> a_wl_r<179> a_wl_r<178> a_wl_r<177> a_wl_r<176> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4 +XA_WLDRV<42> a_wi<175> a_wi<174> a_wi<173> a_wi<172> a_wi<171> a_wi<170> a_wi<169> a_wi<168> a_wi<167> a_wi<166> a_wi<165> a_wi<164> a_wi<163> a_wi<162> a_wi<161> a_wi<160> a_wl_r<175> a_wl_r<174> a_wl_r<173> a_wl_r<172> a_wl_r<171> a_wl_r<170> a_wl_r<169> a_wl_r<168> a_wl_r<167> a_wl_r<166> a_wl_r<165> a_wl_r<164> a_wl_r<163> a_wl_r<162> a_wl_r<161> a_wl_r<160> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4 +XA_WLDRV<41> a_wi<159> a_wi<158> a_wi<157> a_wi<156> a_wi<155> a_wi<154> a_wi<153> a_wi<152> a_wi<151> a_wi<150> a_wi<149> a_wi<148> a_wi<147> a_wi<146> a_wi<145> a_wi<144> a_wl_r<159> a_wl_r<158> a_wl_r<157> a_wl_r<156> a_wl_r<155> a_wl_r<154> a_wl_r<153> a_wl_r<152> a_wl_r<151> a_wl_r<150> a_wl_r<149> a_wl_r<148> a_wl_r<147> a_wl_r<146> a_wl_r<145> a_wl_r<144> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4 +XA_WLDRV<40> a_wi<143> a_wi<142> a_wi<141> a_wi<140> a_wi<139> a_wi<138> a_wi<137> a_wi<136> a_wi<135> a_wi<134> a_wi<133> a_wi<132> a_wi<131> a_wi<130> a_wi<129> a_wi<128> a_wl_r<143> a_wl_r<142> a_wl_r<141> a_wl_r<140> a_wl_r<139> a_wl_r<138> a_wl_r<137> a_wl_r<136> a_wl_r<135> a_wl_r<134> a_wl_r<133> a_wl_r<132> a_wl_r<131> a_wl_r<130> a_wl_r<129> a_wl_r<128> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4 +XA_WLDRV<39> a_wi<127> a_wi<126> a_wi<125> a_wi<124> a_wi<123> a_wi<122> a_wi<121> a_wi<120> a_wi<119> a_wi<118> a_wi<117> a_wi<116> a_wi<115> a_wi<114> a_wi<113> a_wi<112> a_wl_r<127> a_wl_r<126> a_wl_r<125> a_wl_r<124> a_wl_r<123> a_wl_r<122> a_wl_r<121> a_wl_r<120> a_wl_r<119> a_wl_r<118> a_wl_r<117> a_wl_r<116> a_wl_r<115> a_wl_r<114> a_wl_r<113> a_wl_r<112> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4 +XA_WLDRV<38> a_wi<111> a_wi<110> a_wi<109> a_wi<108> a_wi<107> a_wi<106> a_wi<105> a_wi<104> a_wi<103> a_wi<102> a_wi<101> a_wi<100> a_wi<99> a_wi<98> a_wi<97> a_wi<96> a_wl_r<111> a_wl_r<110> a_wl_r<109> a_wl_r<108> a_wl_r<107> a_wl_r<106> a_wl_r<105> a_wl_r<104> a_wl_r<103> a_wl_r<102> a_wl_r<101> a_wl_r<100> a_wl_r<99> a_wl_r<98> a_wl_r<97> a_wl_r<96> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4 +XA_WLDRV<37> a_wi<95> a_wi<94> a_wi<93> a_wi<92> a_wi<91> a_wi<90> a_wi<89> a_wi<88> a_wi<87> a_wi<86> a_wi<85> a_wi<84> a_wi<83> a_wi<82> a_wi<81> a_wi<80> a_wl_r<95> a_wl_r<94> a_wl_r<93> a_wl_r<92> a_wl_r<91> a_wl_r<90> a_wl_r<89> a_wl_r<88> a_wl_r<87> a_wl_r<86> a_wl_r<85> a_wl_r<84> a_wl_r<83> a_wl_r<82> a_wl_r<81> a_wl_r<80> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4 +XA_WLDRV<36> a_wi<79> a_wi<78> a_wi<77> a_wi<76> a_wi<75> a_wi<74> a_wi<73> a_wi<72> a_wi<71> a_wi<70> a_wi<69> a_wi<68> a_wi<67> a_wi<66> a_wi<65> a_wi<64> a_wl_r<79> a_wl_r<78> a_wl_r<77> a_wl_r<76> a_wl_r<75> a_wl_r<74> a_wl_r<73> a_wl_r<72> a_wl_r<71> a_wl_r<70> a_wl_r<69> a_wl_r<68> a_wl_r<67> a_wl_r<66> a_wl_r<65> a_wl_r<64> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4 +XA_WLDRV<35> a_wi<63> a_wi<62> a_wi<61> a_wi<60> a_wi<59> a_wi<58> a_wi<57> a_wi<56> a_wi<55> a_wi<54> a_wi<53> a_wi<52> a_wi<51> a_wi<50> a_wi<49> a_wi<48> a_wl_r<63> a_wl_r<62> a_wl_r<61> a_wl_r<60> a_wl_r<59> a_wl_r<58> a_wl_r<57> a_wl_r<56> a_wl_r<55> a_wl_r<54> a_wl_r<53> a_wl_r<52> a_wl_r<51> a_wl_r<50> a_wl_r<49> a_wl_r<48> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4 +XA_WLDRV<34> a_wi<47> a_wi<46> a_wi<45> a_wi<44> a_wi<43> a_wi<42> a_wi<41> a_wi<40> a_wi<39> a_wi<38> a_wi<37> a_wi<36> a_wi<35> a_wi<34> a_wi<33> a_wi<32> a_wl_r<47> a_wl_r<46> a_wl_r<45> a_wl_r<44> a_wl_r<43> a_wl_r<42> a_wl_r<41> a_wl_r<40> a_wl_r<39> a_wl_r<38> a_wl_r<37> a_wl_r<36> a_wl_r<35> a_wl_r<34> a_wl_r<33> a_wl_r<32> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4 +XA_WLDRV<33> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wl_r<31> a_wl_r<30> a_wl_r<29> a_wl_r<28> a_wl_r<27> a_wl_r<26> a_wl_r<25> a_wl_r<24> a_wl_r<23> a_wl_r<22> a_wl_r<21> a_wl_r<20> a_wl_r<19> a_wl_r<18> a_wl_r<17> a_wl_r<16> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4 +XA_WLDRV<32> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> a_wl_r<15> a_wl_r<14> a_wl_r<13> a_wl_r<12> a_wl_r<11> a_wl_r<10> a_wl_r<9> a_wl_r<8> a_wl_r<7> a_wl_r<6> a_wl_r<5> a_wl_r<4> a_wl_r<3> a_wl_r<2> a_wl_r<1> a_wl_r<0> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4 +XA_WLDRV<31> a_wi<511> a_wi<510> a_wi<509> a_wi<508> a_wi<507> a_wi<506> a_wi<505> a_wi<504> a_wi<503> a_wi<502> a_wi<501> a_wi<500> a_wi<499> a_wi<498> a_wi<497> a_wi<496> a_wl_l<511> a_wl_l<510> a_wl_l<509> a_wl_l<508> a_wl_l<507> a_wl_l<506> a_wl_l<505> a_wl_l<504> a_wl_l<503> a_wl_l<502> a_wl_l<501> a_wl_l<500> a_wl_l<499> a_wl_l<498> a_wl_l<497> a_wl_l<496> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4 +XA_WLDRV<30> a_wi<495> a_wi<494> a_wi<493> a_wi<492> a_wi<491> a_wi<490> a_wi<489> a_wi<488> a_wi<487> a_wi<486> a_wi<485> a_wi<484> a_wi<483> a_wi<482> a_wi<481> a_wi<480> a_wl_l<495> a_wl_l<494> a_wl_l<493> a_wl_l<492> a_wl_l<491> a_wl_l<490> a_wl_l<489> a_wl_l<488> a_wl_l<487> a_wl_l<486> a_wl_l<485> a_wl_l<484> a_wl_l<483> a_wl_l<482> a_wl_l<481> a_wl_l<480> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4 +XA_WLDRV<29> a_wi<479> a_wi<478> a_wi<477> a_wi<476> a_wi<475> a_wi<474> a_wi<473> a_wi<472> a_wi<471> a_wi<470> a_wi<469> a_wi<468> a_wi<467> a_wi<466> a_wi<465> a_wi<464> a_wl_l<479> a_wl_l<478> a_wl_l<477> a_wl_l<476> a_wl_l<475> a_wl_l<474> a_wl_l<473> a_wl_l<472> a_wl_l<471> a_wl_l<470> a_wl_l<469> a_wl_l<468> a_wl_l<467> a_wl_l<466> a_wl_l<465> a_wl_l<464> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4 +XA_WLDRV<28> a_wi<463> a_wi<462> a_wi<461> a_wi<460> a_wi<459> a_wi<458> a_wi<457> a_wi<456> a_wi<455> a_wi<454> a_wi<453> a_wi<452> a_wi<451> a_wi<450> a_wi<449> a_wi<448> a_wl_l<463> a_wl_l<462> a_wl_l<461> a_wl_l<460> a_wl_l<459> a_wl_l<458> a_wl_l<457> a_wl_l<456> a_wl_l<455> a_wl_l<454> a_wl_l<453> a_wl_l<452> a_wl_l<451> a_wl_l<450> a_wl_l<449> a_wl_l<448> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4 +XA_WLDRV<27> a_wi<447> a_wi<446> a_wi<445> a_wi<444> a_wi<443> a_wi<442> a_wi<441> a_wi<440> a_wi<439> a_wi<438> a_wi<437> a_wi<436> a_wi<435> a_wi<434> a_wi<433> a_wi<432> a_wl_l<447> a_wl_l<446> a_wl_l<445> a_wl_l<444> a_wl_l<443> a_wl_l<442> a_wl_l<441> a_wl_l<440> a_wl_l<439> a_wl_l<438> a_wl_l<437> a_wl_l<436> a_wl_l<435> a_wl_l<434> a_wl_l<433> a_wl_l<432> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4 +XA_WLDRV<26> a_wi<431> a_wi<430> a_wi<429> a_wi<428> a_wi<427> a_wi<426> a_wi<425> a_wi<424> a_wi<423> a_wi<422> a_wi<421> a_wi<420> a_wi<419> a_wi<418> a_wi<417> a_wi<416> a_wl_l<431> a_wl_l<430> a_wl_l<429> a_wl_l<428> a_wl_l<427> a_wl_l<426> a_wl_l<425> a_wl_l<424> a_wl_l<423> a_wl_l<422> a_wl_l<421> a_wl_l<420> a_wl_l<419> a_wl_l<418> a_wl_l<417> a_wl_l<416> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4 +XA_WLDRV<25> a_wi<415> a_wi<414> a_wi<413> a_wi<412> a_wi<411> a_wi<410> a_wi<409> a_wi<408> a_wi<407> a_wi<406> a_wi<405> a_wi<404> a_wi<403> a_wi<402> a_wi<401> a_wi<400> a_wl_l<415> a_wl_l<414> a_wl_l<413> a_wl_l<412> a_wl_l<411> a_wl_l<410> a_wl_l<409> a_wl_l<408> a_wl_l<407> a_wl_l<406> a_wl_l<405> a_wl_l<404> a_wl_l<403> a_wl_l<402> a_wl_l<401> a_wl_l<400> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4 +XA_WLDRV<24> a_wi<399> a_wi<398> a_wi<397> a_wi<396> a_wi<395> a_wi<394> a_wi<393> a_wi<392> a_wi<391> a_wi<390> a_wi<389> a_wi<388> a_wi<387> a_wi<386> a_wi<385> a_wi<384> a_wl_l<399> a_wl_l<398> a_wl_l<397> a_wl_l<396> a_wl_l<395> a_wl_l<394> a_wl_l<393> a_wl_l<392> a_wl_l<391> a_wl_l<390> a_wl_l<389> a_wl_l<388> a_wl_l<387> a_wl_l<386> a_wl_l<385> a_wl_l<384> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4 +XA_WLDRV<23> a_wi<383> a_wi<382> a_wi<381> a_wi<380> a_wi<379> a_wi<378> a_wi<377> a_wi<376> a_wi<375> a_wi<374> a_wi<373> a_wi<372> a_wi<371> a_wi<370> a_wi<369> a_wi<368> a_wl_l<383> a_wl_l<382> a_wl_l<381> a_wl_l<380> a_wl_l<379> a_wl_l<378> a_wl_l<377> a_wl_l<376> a_wl_l<375> a_wl_l<374> a_wl_l<373> a_wl_l<372> a_wl_l<371> a_wl_l<370> a_wl_l<369> a_wl_l<368> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4 +XA_WLDRV<22> a_wi<367> a_wi<366> a_wi<365> a_wi<364> a_wi<363> a_wi<362> a_wi<361> a_wi<360> a_wi<359> a_wi<358> a_wi<357> a_wi<356> a_wi<355> a_wi<354> a_wi<353> a_wi<352> a_wl_l<367> a_wl_l<366> a_wl_l<365> a_wl_l<364> a_wl_l<363> a_wl_l<362> a_wl_l<361> a_wl_l<360> a_wl_l<359> a_wl_l<358> a_wl_l<357> a_wl_l<356> a_wl_l<355> a_wl_l<354> a_wl_l<353> a_wl_l<352> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4 +XA_WLDRV<21> a_wi<351> a_wi<350> a_wi<349> a_wi<348> a_wi<347> a_wi<346> a_wi<345> a_wi<344> a_wi<343> a_wi<342> a_wi<341> a_wi<340> a_wi<339> a_wi<338> a_wi<337> a_wi<336> a_wl_l<351> a_wl_l<350> a_wl_l<349> a_wl_l<348> a_wl_l<347> a_wl_l<346> a_wl_l<345> a_wl_l<344> a_wl_l<343> a_wl_l<342> a_wl_l<341> a_wl_l<340> a_wl_l<339> a_wl_l<338> a_wl_l<337> a_wl_l<336> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4 +XA_WLDRV<20> a_wi<335> a_wi<334> a_wi<333> a_wi<332> a_wi<331> a_wi<330> a_wi<329> a_wi<328> a_wi<327> a_wi<326> a_wi<325> a_wi<324> a_wi<323> a_wi<322> a_wi<321> a_wi<320> a_wl_l<335> a_wl_l<334> a_wl_l<333> a_wl_l<332> a_wl_l<331> a_wl_l<330> a_wl_l<329> a_wl_l<328> a_wl_l<327> a_wl_l<326> a_wl_l<325> a_wl_l<324> a_wl_l<323> a_wl_l<322> a_wl_l<321> a_wl_l<320> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4 +XA_WLDRV<19> a_wi<319> a_wi<318> a_wi<317> a_wi<316> a_wi<315> a_wi<314> a_wi<313> a_wi<312> a_wi<311> a_wi<310> a_wi<309> a_wi<308> a_wi<307> a_wi<306> a_wi<305> a_wi<304> a_wl_l<319> a_wl_l<318> a_wl_l<317> a_wl_l<316> a_wl_l<315> a_wl_l<314> a_wl_l<313> a_wl_l<312> a_wl_l<311> a_wl_l<310> a_wl_l<309> a_wl_l<308> a_wl_l<307> a_wl_l<306> a_wl_l<305> a_wl_l<304> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4 +XA_WLDRV<18> a_wi<303> a_wi<302> a_wi<301> a_wi<300> a_wi<299> a_wi<298> a_wi<297> a_wi<296> a_wi<295> a_wi<294> a_wi<293> a_wi<292> a_wi<291> a_wi<290> a_wi<289> a_wi<288> a_wl_l<303> a_wl_l<302> a_wl_l<301> a_wl_l<300> a_wl_l<299> a_wl_l<298> a_wl_l<297> a_wl_l<296> a_wl_l<295> a_wl_l<294> a_wl_l<293> a_wl_l<292> a_wl_l<291> a_wl_l<290> a_wl_l<289> a_wl_l<288> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4 +XA_WLDRV<17> a_wi<287> a_wi<286> a_wi<285> a_wi<284> a_wi<283> a_wi<282> a_wi<281> a_wi<280> a_wi<279> a_wi<278> a_wi<277> a_wi<276> a_wi<275> a_wi<274> a_wi<273> a_wi<272> a_wl_l<287> a_wl_l<286> a_wl_l<285> a_wl_l<284> a_wl_l<283> a_wl_l<282> a_wl_l<281> a_wl_l<280> a_wl_l<279> a_wl_l<278> a_wl_l<277> a_wl_l<276> a_wl_l<275> a_wl_l<274> a_wl_l<273> a_wl_l<272> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4 +XA_WLDRV<16> a_wi<271> a_wi<270> a_wi<269> a_wi<268> a_wi<267> a_wi<266> a_wi<265> a_wi<264> a_wi<263> a_wi<262> a_wi<261> a_wi<260> a_wi<259> a_wi<258> a_wi<257> a_wi<256> a_wl_l<271> a_wl_l<270> a_wl_l<269> a_wl_l<268> a_wl_l<267> a_wl_l<266> a_wl_l<265> a_wl_l<264> a_wl_l<263> a_wl_l<262> a_wl_l<261> a_wl_l<260> a_wl_l<259> a_wl_l<258> a_wl_l<257> a_wl_l<256> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4 +XA_WLDRV<15> a_wi<255> a_wi<254> a_wi<253> a_wi<252> a_wi<251> a_wi<250> a_wi<249> a_wi<248> a_wi<247> a_wi<246> a_wi<245> a_wi<244> a_wi<243> a_wi<242> a_wi<241> a_wi<240> a_wl_l<255> a_wl_l<254> a_wl_l<253> a_wl_l<252> a_wl_l<251> a_wl_l<250> a_wl_l<249> a_wl_l<248> a_wl_l<247> a_wl_l<246> a_wl_l<245> a_wl_l<244> a_wl_l<243> a_wl_l<242> a_wl_l<241> a_wl_l<240> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4 +XA_WLDRV<14> a_wi<239> a_wi<238> a_wi<237> a_wi<236> a_wi<235> a_wi<234> a_wi<233> a_wi<232> a_wi<231> a_wi<230> a_wi<229> a_wi<228> a_wi<227> a_wi<226> a_wi<225> a_wi<224> a_wl_l<239> a_wl_l<238> a_wl_l<237> a_wl_l<236> a_wl_l<235> a_wl_l<234> a_wl_l<233> a_wl_l<232> a_wl_l<231> a_wl_l<230> a_wl_l<229> a_wl_l<228> a_wl_l<227> a_wl_l<226> a_wl_l<225> a_wl_l<224> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4 +XA_WLDRV<13> a_wi<223> a_wi<222> a_wi<221> a_wi<220> a_wi<219> a_wi<218> a_wi<217> a_wi<216> a_wi<215> a_wi<214> a_wi<213> a_wi<212> a_wi<211> a_wi<210> a_wi<209> a_wi<208> a_wl_l<223> a_wl_l<222> a_wl_l<221> a_wl_l<220> a_wl_l<219> a_wl_l<218> a_wl_l<217> a_wl_l<216> a_wl_l<215> a_wl_l<214> a_wl_l<213> a_wl_l<212> a_wl_l<211> a_wl_l<210> a_wl_l<209> a_wl_l<208> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4 +XA_WLDRV<12> a_wi<207> a_wi<206> a_wi<205> a_wi<204> a_wi<203> a_wi<202> a_wi<201> a_wi<200> a_wi<199> a_wi<198> a_wi<197> a_wi<196> a_wi<195> a_wi<194> a_wi<193> a_wi<192> a_wl_l<207> a_wl_l<206> a_wl_l<205> a_wl_l<204> a_wl_l<203> a_wl_l<202> a_wl_l<201> a_wl_l<200> a_wl_l<199> a_wl_l<198> a_wl_l<197> a_wl_l<196> a_wl_l<195> a_wl_l<194> a_wl_l<193> a_wl_l<192> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4 +XA_WLDRV<11> a_wi<191> a_wi<190> a_wi<189> a_wi<188> a_wi<187> a_wi<186> a_wi<185> a_wi<184> a_wi<183> a_wi<182> a_wi<181> a_wi<180> a_wi<179> a_wi<178> a_wi<177> a_wi<176> a_wl_l<191> a_wl_l<190> a_wl_l<189> a_wl_l<188> a_wl_l<187> a_wl_l<186> a_wl_l<185> a_wl_l<184> a_wl_l<183> a_wl_l<182> a_wl_l<181> a_wl_l<180> a_wl_l<179> a_wl_l<178> a_wl_l<177> a_wl_l<176> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4 +XA_WLDRV<10> a_wi<175> a_wi<174> a_wi<173> a_wi<172> a_wi<171> a_wi<170> a_wi<169> a_wi<168> a_wi<167> a_wi<166> a_wi<165> a_wi<164> a_wi<163> a_wi<162> a_wi<161> a_wi<160> a_wl_l<175> a_wl_l<174> a_wl_l<173> a_wl_l<172> a_wl_l<171> a_wl_l<170> a_wl_l<169> a_wl_l<168> a_wl_l<167> a_wl_l<166> a_wl_l<165> a_wl_l<164> a_wl_l<163> a_wl_l<162> a_wl_l<161> a_wl_l<160> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4 +XA_WLDRV<9> a_wi<159> a_wi<158> a_wi<157> a_wi<156> a_wi<155> a_wi<154> a_wi<153> a_wi<152> a_wi<151> a_wi<150> a_wi<149> a_wi<148> a_wi<147> a_wi<146> a_wi<145> a_wi<144> a_wl_l<159> a_wl_l<158> a_wl_l<157> a_wl_l<156> a_wl_l<155> a_wl_l<154> a_wl_l<153> a_wl_l<152> a_wl_l<151> a_wl_l<150> a_wl_l<149> a_wl_l<148> a_wl_l<147> a_wl_l<146> a_wl_l<145> a_wl_l<144> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4 +XA_WLDRV<8> a_wi<143> a_wi<142> a_wi<141> a_wi<140> a_wi<139> a_wi<138> a_wi<137> a_wi<136> a_wi<135> a_wi<134> a_wi<133> a_wi<132> a_wi<131> a_wi<130> a_wi<129> a_wi<128> a_wl_l<143> a_wl_l<142> a_wl_l<141> a_wl_l<140> a_wl_l<139> a_wl_l<138> a_wl_l<137> a_wl_l<136> a_wl_l<135> a_wl_l<134> a_wl_l<133> a_wl_l<132> a_wl_l<131> a_wl_l<130> a_wl_l<129> a_wl_l<128> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4 +XA_WLDRV<7> a_wi<127> a_wi<126> a_wi<125> a_wi<124> a_wi<123> a_wi<122> a_wi<121> a_wi<120> a_wi<119> a_wi<118> a_wi<117> a_wi<116> a_wi<115> a_wi<114> a_wi<113> a_wi<112> a_wl_l<127> a_wl_l<126> a_wl_l<125> a_wl_l<124> a_wl_l<123> a_wl_l<122> a_wl_l<121> a_wl_l<120> a_wl_l<119> a_wl_l<118> a_wl_l<117> a_wl_l<116> a_wl_l<115> a_wl_l<114> a_wl_l<113> a_wl_l<112> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4 +XA_WLDRV<6> a_wi<111> a_wi<110> a_wi<109> a_wi<108> a_wi<107> a_wi<106> a_wi<105> a_wi<104> a_wi<103> a_wi<102> a_wi<101> a_wi<100> a_wi<99> a_wi<98> a_wi<97> a_wi<96> a_wl_l<111> a_wl_l<110> a_wl_l<109> a_wl_l<108> a_wl_l<107> a_wl_l<106> a_wl_l<105> a_wl_l<104> a_wl_l<103> a_wl_l<102> a_wl_l<101> a_wl_l<100> a_wl_l<99> a_wl_l<98> a_wl_l<97> a_wl_l<96> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4 +XA_WLDRV<5> a_wi<95> a_wi<94> a_wi<93> a_wi<92> a_wi<91> a_wi<90> a_wi<89> a_wi<88> a_wi<87> a_wi<86> a_wi<85> a_wi<84> a_wi<83> a_wi<82> a_wi<81> a_wi<80> a_wl_l<95> a_wl_l<94> a_wl_l<93> a_wl_l<92> a_wl_l<91> a_wl_l<90> a_wl_l<89> a_wl_l<88> a_wl_l<87> a_wl_l<86> a_wl_l<85> a_wl_l<84> a_wl_l<83> a_wl_l<82> a_wl_l<81> a_wl_l<80> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4 +XA_WLDRV<4> a_wi<79> a_wi<78> a_wi<77> a_wi<76> a_wi<75> a_wi<74> a_wi<73> a_wi<72> a_wi<71> a_wi<70> a_wi<69> a_wi<68> a_wi<67> a_wi<66> a_wi<65> a_wi<64> a_wl_l<79> a_wl_l<78> a_wl_l<77> a_wl_l<76> a_wl_l<75> a_wl_l<74> a_wl_l<73> a_wl_l<72> a_wl_l<71> a_wl_l<70> a_wl_l<69> a_wl_l<68> a_wl_l<67> a_wl_l<66> a_wl_l<65> a_wl_l<64> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4 +XA_WLDRV<3> a_wi<63> a_wi<62> a_wi<61> a_wi<60> a_wi<59> a_wi<58> a_wi<57> a_wi<56> a_wi<55> a_wi<54> a_wi<53> a_wi<52> a_wi<51> a_wi<50> a_wi<49> a_wi<48> a_wl_l<63> a_wl_l<62> a_wl_l<61> a_wl_l<60> a_wl_l<59> a_wl_l<58> a_wl_l<57> a_wl_l<56> a_wl_l<55> a_wl_l<54> a_wl_l<53> a_wl_l<52> a_wl_l<51> a_wl_l<50> a_wl_l<49> a_wl_l<48> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4 +XA_WLDRV<2> a_wi<47> a_wi<46> a_wi<45> a_wi<44> a_wi<43> a_wi<42> a_wi<41> a_wi<40> a_wi<39> a_wi<38> a_wi<37> a_wi<36> a_wi<35> a_wi<34> a_wi<33> a_wi<32> a_wl_l<47> a_wl_l<46> a_wl_l<45> a_wl_l<44> a_wl_l<43> a_wl_l<42> a_wl_l<41> a_wl_l<40> a_wl_l<39> a_wl_l<38> a_wl_l<37> a_wl_l<36> a_wl_l<35> a_wl_l<34> a_wl_l<33> a_wl_l<32> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4 +XA_WLDRV<1> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wl_l<31> a_wl_l<30> a_wl_l<29> a_wl_l<28> a_wl_l<27> a_wl_l<26> a_wl_l<25> a_wl_l<24> a_wl_l<23> a_wl_l<22> a_wl_l<21> a_wl_l<20> a_wl_l<19> a_wl_l<18> a_wl_l<17> a_wl_l<16> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4 +XA_WLDRV<0> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> a_wl_l<15> a_wl_l<14> a_wl_l<13> a_wl_l<12> a_wl_l<11> a_wl_l<10> a_wl_l<9> a_wl_l<8> a_wl_l<7> a_wl_l<6> a_wl_l<5> a_wl_l<4> a_wl_l<3> a_wl_l<2> a_wl_l<1> a_wl_l<0> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4 + + +XA_CTRL a_aclk_n A_BIST_CLK A_BIST_MEN A_BIST_EN A_BIST_REN A_BIST_WEN a_tiel A_CLK A_MEN a_dclk a_eclk a_pulse_h a_pulse_l a_pulse a_rclk A_REN a_cs a_wclk A_WEN VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_CTRL + + +XA_ROWDEC a_addr_row<8> a_addr_row<7> a_addr_row<6> a_addr_row<5> a_addr_row<4> a_addr_row<3> a_addr_row<2> a_addr_row<1> a_addr_row<0> a_cs a_eclk a_wi<511> a_wi<510> a_wi<509> a_wi<508> a_wi<507> a_wi<506> a_wi<505> a_wi<504> a_wi<503> a_wi<502> a_wi<501> a_wi<500> a_wi<499> a_wi<498> a_wi<497> a_wi<496> a_wi<495> a_wi<494> a_wi<493> a_wi<492> a_wi<491> a_wi<490> a_wi<489> a_wi<488> a_wi<487> a_wi<486> a_wi<485> a_wi<484> a_wi<483> a_wi<482> a_wi<481> a_wi<480> a_wi<479> a_wi<478> a_wi<477> a_wi<476> a_wi<475> a_wi<474> a_wi<473> a_wi<472> a_wi<471> a_wi<470> a_wi<469> a_wi<468> a_wi<467> a_wi<466> a_wi<465> a_wi<464> a_wi<463> a_wi<462> a_wi<461> a_wi<460> a_wi<459> a_wi<458> a_wi<457> a_wi<456> a_wi<455> a_wi<454> a_wi<453> a_wi<452> a_wi<451> a_wi<450> a_wi<449> a_wi<448> a_wi<447> a_wi<446> a_wi<445> a_wi<444> a_wi<443> a_wi<442> a_wi<441> a_wi<440> a_wi<439> a_wi<438> a_wi<437> a_wi<436> a_wi<435> a_wi<434> a_wi<433> a_wi<432> a_wi<431> a_wi<430> a_wi<429> a_wi<428> a_wi<427> a_wi<426> a_wi<425> a_wi<424> a_wi<423> a_wi<422> a_wi<421> a_wi<420> a_wi<419> a_wi<418> a_wi<417> a_wi<416> a_wi<415> a_wi<414> a_wi<413> a_wi<412> a_wi<411> a_wi<410> a_wi<409> a_wi<408> a_wi<407> a_wi<406> a_wi<405> a_wi<404> a_wi<403> a_wi<402> a_wi<401> a_wi<400> a_wi<399> a_wi<398> a_wi<397> a_wi<396> a_wi<395> a_wi<394> a_wi<393> a_wi<392> a_wi<391> a_wi<390> a_wi<389> a_wi<388> a_wi<387> a_wi<386> a_wi<385> a_wi<384> a_wi<383> a_wi<382> a_wi<381> a_wi<380> a_wi<379> a_wi<378> a_wi<377> a_wi<376> a_wi<375> a_wi<374> a_wi<373> a_wi<372> a_wi<371> a_wi<370> a_wi<369> a_wi<368> a_wi<367> a_wi<366> a_wi<365> a_wi<364> a_wi<363> a_wi<362> a_wi<361> a_wi<360> a_wi<359> a_wi<358> a_wi<357> a_wi<356> a_wi<355> a_wi<354> a_wi<353> a_wi<352> a_wi<351> a_wi<350> a_wi<349> a_wi<348> a_wi<347> a_wi<346> a_wi<345> a_wi<344> a_wi<343> a_wi<342> a_wi<341> a_wi<340> a_wi<339> a_wi<338> a_wi<337> a_wi<336> a_wi<335> a_wi<334> a_wi<333> a_wi<332> a_wi<331> a_wi<330> a_wi<329> a_wi<328> a_wi<327> a_wi<326> a_wi<325> a_wi<324> a_wi<323> a_wi<322> a_wi<321> a_wi<320> a_wi<319> a_wi<318> a_wi<317> a_wi<316> a_wi<315> a_wi<314> a_wi<313> a_wi<312> a_wi<311> a_wi<310> a_wi<309> a_wi<308> a_wi<307> a_wi<306> a_wi<305> a_wi<304> a_wi<303> a_wi<302> a_wi<301> a_wi<300> a_wi<299> a_wi<298> a_wi<297> a_wi<296> a_wi<295> a_wi<294> a_wi<293> a_wi<292> a_wi<291> a_wi<290> a_wi<289> a_wi<288> a_wi<287> a_wi<286> a_wi<285> a_wi<284> a_wi<283> a_wi<282> a_wi<281> a_wi<280> a_wi<279> a_wi<278> a_wi<277> a_wi<276> a_wi<275> a_wi<274> a_wi<273> a_wi<272> a_wi<271> a_wi<270> a_wi<269> a_wi<268> a_wi<267> a_wi<266> a_wi<265> a_wi<264> a_wi<263> a_wi<262> a_wi<261> a_wi<260> a_wi<259> a_wi<258> a_wi<257> a_wi<256> a_wi<255> a_wi<254> a_wi<253> a_wi<252> a_wi<251> a_wi<250> a_wi<249> a_wi<248> a_wi<247> a_wi<246> a_wi<245> a_wi<244> a_wi<243> a_wi<242> a_wi<241> a_wi<240> a_wi<239> a_wi<238> a_wi<237> a_wi<236> a_wi<235> a_wi<234> a_wi<233> a_wi<232> a_wi<231> a_wi<230> a_wi<229> a_wi<228> a_wi<227> a_wi<226> a_wi<225> a_wi<224> a_wi<223> a_wi<222> a_wi<221> a_wi<220> a_wi<219> a_wi<218> a_wi<217> a_wi<216> a_wi<215> a_wi<214> a_wi<213> a_wi<212> a_wi<211> a_wi<210> a_wi<209> a_wi<208> a_wi<207> a_wi<206> a_wi<205> a_wi<204> a_wi<203> a_wi<202> a_wi<201> a_wi<200> a_wi<199> a_wi<198> a_wi<197> a_wi<196> a_wi<195> a_wi<194> a_wi<193> a_wi<192> a_wi<191> a_wi<190> a_wi<189> a_wi<188> a_wi<187> a_wi<186> a_wi<185> a_wi<184> a_wi<183> a_wi<182> a_wi<181> a_wi<180> a_wi<179> a_wi<178> a_wi<177> a_wi<176> a_wi<175> a_wi<174> a_wi<173> a_wi<172> a_wi<171> a_wi<170> a_wi<169> a_wi<168> a_wi<167> a_wi<166> a_wi<165> a_wi<164> a_wi<163> a_wi<162> a_wi<161> a_wi<160> a_wi<159> a_wi<158> a_wi<157> a_wi<156> a_wi<155> a_wi<154> a_wi<153> a_wi<152> a_wi<151> a_wi<150> a_wi<149> a_wi<148> a_wi<147> a_wi<146> a_wi<145> a_wi<144> a_wi<143> a_wi<142> a_wi<141> a_wi<140> a_wi<139> a_wi<138> a_wi<137> a_wi<136> a_wi<135> a_wi<134> a_wi<133> a_wi<132> a_wi<131> a_wi<130> a_wi<129> a_wi<128> a_wi<127> a_wi<126> a_wi<125> a_wi<124> a_wi<123> a_wi<122> a_wi<121> a_wi<120> a_wi<119> a_wi<118> a_wi<117> a_wi<116> a_wi<115> a_wi<114> a_wi<113> a_wi<112> a_wi<111> a_wi<110> a_wi<109> a_wi<108> a_wi<107> a_wi<106> a_wi<105> a_wi<104> a_wi<103> a_wi<102> a_wi<101> a_wi<100> a_wi<99> a_wi<98> a_wi<97> a_wi<96> a_wi<95> a_wi<94> a_wi<93> a_wi<92> a_wi<91> a_wi<90> a_wi<89> a_wi<88> a_wi<87> a_wi<86> a_wi<85> a_wi<84> a_wi<83> a_wi<82> a_wi<81> a_wi<80> a_wi<79> a_wi<78> a_wi<77> a_wi<76> a_wi<75> a_wi<74> a_wi<73> a_wi<72> a_wi<71> a_wi<70> a_wi<69> a_wi<68> a_wi<67> a_wi<66> a_wi<65> a_wi<64> a_wi<63> a_wi<62> a_wi<61> a_wi<60> a_wi<59> a_wi<58> a_wi<57> a_wi<56> a_wi<55> a_wi<54> a_wi<53> a_wi<52> a_wi<51> a_wi<50> a_wi<49> a_wi<48> a_wi<47> a_wi<46> a_wi<45> a_wi<44> a_wi<43> a_wi<42> a_wi<41> a_wi<40> a_wi<39> a_wi<38> a_wi<37> a_wi<36> a_wi<35> a_wi<34> a_wi<33> a_wi<32> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_ROWDEC9 +XA_ROWREG a_aclk_n A_ADDR<11> A_ADDR<10> A_ADDR<9> A_ADDR<8> A_ADDR<7> A_ADDR<6> A_ADDR<5> A_ADDR<4> A_ADDR<3> a_addr_row<8> a_addr_row<7> a_addr_row<6> a_addr_row<5> a_addr_row<4> a_addr_row<3> a_addr_row<2> a_addr_row<1> a_addr_row<0> A_BIST_ADDR<11> A_BIST_ADDR<10> A_BIST_ADDR<9> A_BIST_ADDR<8> A_BIST_ADDR<7> A_BIST_ADDR<6> A_BIST_ADDR<5> A_BIST_ADDR<4> A_BIST_ADDR<3> A_BIST_EN VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_ROWREG9 +XA_COLDEC a_aclk_n A_ADDR<2> A_ADDR<1> A_ADDR<0> a_addr_col<1> a_addr_col<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> A_BIST_ADDR<2> A_BIST_ADDR<1> A_BIST_ADDR<0> A_BIST_EN VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_COLDEC3 + + +XA_DLYH a_pulse a_pulse_h VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_DLY_pcell_2 +XA_DLYL a_pulse_x a_pulse_l VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_DLY_pcell_3 +XA_DLYMUX a_pulse_h A_DLY a_pulse_x VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_DLY_MUX + +XCOLCTRL<7> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<7> A_BIST_DIN<7> A_BIST_EN a_blc_r<31> a_blc_r<30> a_blc_r<29> a_blc_r<28> a_blc_r<27> a_blc_r<26> a_blc_r<25> a_blc_r<24> a_blt_r<31> a_blt_r<30> a_blt_r<29> a_blt_r<28> a_blt_r<27> a_blt_r<26> a_blt_r<25> a_blt_r<24> A_BM<7> a_dclk_n_r<3> a_dclk_n_r<4> a_dclk_p_r<3> a_dclk_p_r<4> A_DOUT<7> A_DIN<7> a_rclk_n_r<3> a_rclk_n_r<4> a_rclk_p_r<3> a_rclk_p_r<4> a_tieh<7> a_wclk_n_r<3> a_wclk_n_r<4> a_wclk_p_r<3> a_wclk_p_r<4> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_COLCTRL3 +XCOLCTRL<6> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<6> A_BIST_DIN<6> A_BIST_EN a_blc_r<23> a_blc_r<22> a_blc_r<21> a_blc_r<20> a_blc_r<19> a_blc_r<18> a_blc_r<17> a_blc_r<16> a_blt_r<23> a_blt_r<22> a_blt_r<21> a_blt_r<20> a_blt_r<19> a_blt_r<18> a_blt_r<17> a_blt_r<16> A_BM<6> a_dclk_n_r<2> a_dclk_n_r<3> a_dclk_p_r<2> a_dclk_p_r<3> A_DOUT<6> A_DIN<6> a_rclk_n_r<2> a_rclk_n_r<3> a_rclk_p_r<2> a_rclk_p_r<3> a_tieh<6> a_wclk_n_r<2> a_wclk_n_r<3> a_wclk_p_r<2> a_wclk_p_r<3> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_COLCTRL3 +XCOLCTRL<5> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<5> A_BIST_DIN<5> A_BIST_EN a_blc_r<15> a_blc_r<14> a_blc_r<13> a_blc_r<12> a_blc_r<11> a_blc_r<10> a_blc_r<9> a_blc_r<8> a_blt_r<15> a_blt_r<14> a_blt_r<13> a_blt_r<12> a_blt_r<11> a_blt_r<10> a_blt_r<9> a_blt_r<8> A_BM<5> a_dclk_n_r<1> a_dclk_n_r<2> a_dclk_p_r<1> a_dclk_p_r<2> A_DOUT<5> A_DIN<5> a_rclk_n_r<1> a_rclk_n_r<2> a_rclk_p_r<1> a_rclk_p_r<2> a_tieh<5> a_wclk_n_r<1> a_wclk_n_r<2> a_wclk_p_r<1> a_wclk_p_r<2> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_COLCTRL3 +XCOLCTRL<4> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<4> A_BIST_DIN<4> A_BIST_EN a_blc_r<7> a_blc_r<6> a_blc_r<5> a_blc_r<4> a_blc_r<3> a_blc_r<2> a_blc_r<1> a_blc_r<0> a_blt_r<7> a_blt_r<6> a_blt_r<5> a_blt_r<4> a_blt_r<3> a_blt_r<2> a_blt_r<1> a_blt_r<0> A_BM<4> a_dclk_n_r<0> a_dclk_n_r<1> a_dclk_p_r<0> a_dclk_p_r<1> A_DOUT<4> A_DIN<4> a_rclk_n_r<0> a_rclk_n_r<1> a_rclk_p_r<0> a_rclk_p_r<1> a_tieh<4> a_wclk_n_r<0> a_wclk_n_r<1> a_wclk_p_r<0> a_wclk_p_r<1> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_COLCTRL3 +XCOLCTRL<3> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<0> A_BIST_DIN<0> A_BIST_EN a_blc_l<31> a_blc_l<30> a_blc_l<29> a_blc_l<28> a_blc_l<27> a_blc_l<26> a_blc_l<25> a_blc_l<24> a_blt_l<31> a_blt_l<30> a_blt_l<29> a_blt_l<28> a_blt_l<27> a_blt_l<26> a_blt_l<25> a_blt_l<24> A_BM<0> a_dclk_n_l<3> a_dclk_n_l<4> a_dclk_p_l<3> a_dclk_p_l<4> A_DOUT<0> A_DIN<0> a_rclk_n_l<3> a_rclk_n_l<4> a_rclk_p_l<3> a_rclk_p_l<4> a_tieh<0> a_wclk_n_l<3> a_wclk_n_l<4> a_wclk_p_l<3> a_wclk_p_l<4> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_COLCTRL3 +XCOLCTRL<2> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<1> A_BIST_DIN<1> A_BIST_EN a_blc_l<23> a_blc_l<22> a_blc_l<21> a_blc_l<20> a_blc_l<19> a_blc_l<18> a_blc_l<17> a_blc_l<16> a_blt_l<23> a_blt_l<22> a_blt_l<21> a_blt_l<20> a_blt_l<19> a_blt_l<18> a_blt_l<17> a_blt_l<16> A_BM<1> a_dclk_n_l<2> a_dclk_n_l<3> a_dclk_p_l<2> a_dclk_p_l<3> A_DOUT<1> A_DIN<1> a_rclk_n_l<2> a_rclk_n_l<3> a_rclk_p_l<2> a_rclk_p_l<3> a_tieh<1> a_wclk_n_l<2> a_wclk_n_l<3> a_wclk_p_l<2> a_wclk_p_l<3> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_COLCTRL3 +XCOLCTRL<1> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<2> A_BIST_DIN<2> A_BIST_EN a_blc_l<15> a_blc_l<14> a_blc_l<13> a_blc_l<12> a_blc_l<11> a_blc_l<10> a_blc_l<9> a_blc_l<8> a_blt_l<15> a_blt_l<14> a_blt_l<13> a_blt_l<12> a_blt_l<11> a_blt_l<10> a_blt_l<9> a_blt_l<8> A_BM<2> a_dclk_n_l<1> a_dclk_n_l<2> a_dclk_p_l<1> a_dclk_p_l<2> A_DOUT<2> A_DIN<2> a_rclk_n_l<1> a_rclk_n_l<2> a_rclk_p_l<1> a_rclk_p_l<2> a_tieh<2> a_wclk_n_l<1> a_wclk_n_l<2> a_wclk_p_l<1> a_wclk_p_l<2> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_COLCTRL3 +XCOLCTRL<0> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<3> A_BIST_DIN<3> A_BIST_EN a_blc_l<7> a_blc_l<6> a_blc_l<5> a_blc_l<4> a_blc_l<3> a_blc_l<2> a_blc_l<1> a_blc_l<0> a_blt_l<7> a_blt_l<6> a_blt_l<5> a_blt_l<4> a_blt_l<3> a_blt_l<2> a_blt_l<1> a_blt_l<0> A_BM<3> a_dclk_n_l<0> a_dclk_n_l<1> a_dclk_p_l<0> a_dclk_p_l<1> A_DOUT<3> A_DIN<3> a_rclk_n_l<0> a_rclk_n_l<1> a_rclk_p_l<0> a_rclk_p_l<1> a_tieh<3> a_wclk_n_l<0> a_wclk_n_l<1> a_wclk_p_l<0> a_wclk_p_l<1> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_COLCTRL3 + + +XDRVFILL4<1> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_COLDRV13_FILL4 +XDRVFILL4<2> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_COLDRV13_FILL4 +.ENDS diff --git a/flow/platforms/ihp-sg13g2/cdl/sg13g2_io.cdl b/flow/platforms/ihp-sg13g2/cdl/sg13g2_io.cdl new file mode 100644 index 0000000000..65b4f4c527 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/cdl/sg13g2_io.cdl @@ -0,0 +1,757 @@ +************************************************************************ +* +* Copyright 2024 IHP PDK Authors +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* https://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* +************************************************************************ + +*.BIPOLAR +*.RESI = 2000 +*.RESVAL +*.CAPVAL +*.DIOPERI +*.DIOAREA +*.EQUATION +*.SCALE METER +*.MEGA +.PARAM + +************************************************************************ +* Library Name: sg13g2_io +* Cell Name: DCNDiode +* View Name: schematic +************************************************************************ + +.SUBCKT DCNDiode anode cathode guard +*.PININFO anode:B cathode:B guard:B +DD0 anode cathode dantenna m=1 w=1.26u l=27.78u a=35.003p p=58.08u +.ENDS + +************************************************************************ +* Library Name: sg13g2_io +* Cell Name: DCPDiode +* View Name: schematic +************************************************************************ + +.SUBCKT DCPDiode anode cathode guard +*.PININFO anode:B cathode:B guard:B +DD0 anode cathode dpantenna m=1 w=1.26u l=27.78u a=35.003p p=58.08u +.ENDS + +************************************************************************ +* Library Name: sg13g2_io +* Cell Name: inv_x1 +* View Name: schematic +************************************************************************ + +.SUBCKT inv_x1 i nq vdd vss +*.PININFO i:I nq:O vdd:B vss:B +MN0 nq i vss vss sg13_lv_nmos m=1 w=3.93u l=130.00n ng=1 +MP0 nq i vdd vdd sg13_lv_pmos m=1 w=4.41u l=130.00n ng=1 +.ENDS + +************************************************************************ +* Library Name: sg13g2_io +* Cell Name: LevelUp +* View Name: schematic +************************************************************************ + +.SUBCKT LevelUp i iovdd o vdd vss +*.PININFO i:I o:O iovdd:B vdd:B vss:B +MN0 net2 i vss vss sg13_lv_nmos m=1 w=2.75u l=130.00n ng=1 +MP0 net2 i vdd vdd sg13_lv_pmos m=1 w=4.75u l=130.00n ng=1 +MN3 o net4 vss vss sg13_hv_nmos m=1 w=1.9u l=450.00n ng=1 +MN2 net4 i vss vss sg13_hv_nmos m=1 w=1.9u l=450.00n ng=1 +MN1 net3 net2 vss vss sg13_hv_nmos m=1 w=1.9u l=450.00n ng=1 +MP3 o net4 iovdd iovdd sg13_hv_pmos m=1 w=3.9u l=450.00n ng=1 +MP2 net3 net4 iovdd iovdd sg13_hv_pmos m=1 w=300.0n l=450.00n ng=1 +MP1 net4 net3 iovdd iovdd sg13_hv_pmos m=1 w=300.0n l=450.00n ng=1 +.ENDS + +************************************************************************ +* Library Name: sg13g2_io +* Cell Name: nor2_x1 +* View Name: schematic +************************************************************************ + +.SUBCKT nor2_x1 i0 i1 nq vdd vss +*.PININFO i0:I i1:I nq:O vdd:B vss:B +MN0 nq i0 vss vss sg13_lv_nmos m=1 w=3.93u l=130.00n ng=1 +MN1 nq i1 vss vss sg13_lv_nmos m=1 w=3.93u l=130.00n ng=1 +MP1 net1 i0 vdd vdd sg13_lv_pmos m=1 w=4.41u l=130.00n ng=1 +MP0 nq i1 net1 vdd sg13_lv_pmos m=1 w=4.41u l=130.00n ng=1 +.ENDS + +************************************************************************ +* Library Name: sg13g2_io +* Cell Name: nand2_x1 +* View Name: schematic +************************************************************************ + +.SUBCKT nand2_x1 i0 i1 nq vdd vss +*.PININFO i0:I i1:I nq:O vdd:B vss:B +MP1 nq i1 vdd vdd sg13_lv_pmos m=1 w=4.41u l=130.00n ng=1 +MP0 nq i0 vdd vdd sg13_lv_pmos m=1 w=4.41u l=130.00n ng=1 +MN1 net1 i0 vss vss sg13_lv_nmos m=1 w=3.93u l=130.00n ng=1 +MN0 nq i1 net1 vss sg13_lv_nmos m=1 w=3.93u l=130.00n ng=1 +.ENDS + +************************************************************************ +* Library Name: sg13g2_io +* Cell Name: GateDecode +* View Name: schematic +************************************************************************ + +.SUBCKT GateDecode core en iovdd ngate pgate vdd vss +*.PININFO core:I en:I ngate:O pgate:O iovdd:B vdd:B vss:B +XI2 en net3 vdd vss / inv_x1 +XI4 net4 iovdd ngate vdd vss / LevelUp +XI3 net2 iovdd pgate vdd vss / LevelUp +XI0 core net3 net4 vdd vss / nor2_x1 +XI1 core en net2 vdd vss / nand2_x1 +.ENDS + +************************************************************************ +* Library Name: sg13g2_io +* Cell Name: SecondaryProtection +* View Name: schematic +************************************************************************ + +.SUBCKT SecondaryProtection core minus pad plus +*.PININFO core:B minus:B pad:B plus:B +RR0 pad core rppd 586.899 m=1 l=2u w=1u ps=180n trise=0.0 b=0 +DD0 minus core dantenna m=1 w=780n l=3.1u a=2.418p p=7.76u +DD1 core plus dpantenna m=1 w=780.00n l=4.98u a=3.884p p=11.52u +.ENDS + +************************************************************************ +* Library Name: sg13g2_io +* Cell Name: LevelDown +* View Name: schematic +************************************************************************ + +.SUBCKT LevelDown core iovdd iovss pad vdd vss +*.PININFO core:O iovdd:B iovss:B pad:B vdd:B vss:B +XI0 net4 iovss pad iovdd / SecondaryProtection +MP0 net2 net4 vdd vdd sg13_hv_pmos m=1 w=4.65u l=450.00n ng=1 +MN0 net2 net4 vss vss sg13_hv_nmos m=1 w=2.65u l=450.00n ng=1 +MN1 core net2 vss vss sg13_lv_nmos m=1 w=2.75u l=130.00n ng=1 +MP1 core net2 vdd vdd sg13_lv_pmos m=1 w=4.75u l=130.00n ng=1 +.ENDS + +************************************************************************ +* Library Name: sg13g2_io +* Cell Name: sg13g2_IOPadInOut30mA +* View Name: schematic +************************************************************************ + +.SUBCKT sg13g2_IOPadInOut30mA c2p c2p_en iovdd iovss p2c pad vdd vss +*.PININFO c2p:I c2p_en:I p2c:O iovdd:B iovss:B pad:B vdd:B vss:B +XI3 iovss pad iovdd / DCNDiode +XI2 pad iovdd iovss / DCPDiode +MN0 pad net2 iovss iovss sg13_hv_nmos m=1 w=66.000u l=600.0n ng=15 +MP0 pad net1 iovdd iovdd sg13_hv_pmos m=1 w=199.8u l=600.0n ng=30 +XI0 c2p c2p_en iovdd net2 net1 vdd vss / GateDecode +XI1 p2c iovdd iovss pad vdd vss / LevelDown +.ENDS + +************************************************************************ +* Library Name: sg13g2_io +* Cell Name: LevelUpInv +* View Name: schematic +************************************************************************ + +.SUBCKT LevelUpInv i iovdd o vdd vss +*.PININFO i:I o:O iovdd:B vdd:B vss:B +MN0 net2 i vss vss sg13_lv_nmos m=1 w=2.75u l=130.00n ng=1 +MP0 net2 i vdd vdd sg13_lv_pmos m=1 w=4.75u l=130.00n ng=1 +MN3 o net4 vss vss sg13_hv_nmos m=1 w=1.9u l=450.00n ng=1 +MN2 net4 net2 vss vss sg13_hv_nmos m=1 w=1.9u l=450.00n ng=1 +MN1 net3 i vss vss sg13_hv_nmos m=1 w=1.9u l=450.00n ng=1 +MP3 o net4 iovdd iovdd sg13_hv_pmos m=1 w=3.9u l=450.00n ng=1 +MP2 net3 net4 iovdd iovdd sg13_hv_pmos m=1 w=300.0n l=450.00n ng=1 +MP1 net4 net3 iovdd iovdd sg13_hv_pmos m=1 w=300.0n l=450.00n ng=1 +.ENDS + +************************************************************************ +* Library Name: sg13g2_io +* Cell Name: GateLevelUpInv +* View Name: schematic +************************************************************************ + +.SUBCKT GateLevelUpInv core iovdd ngate pgate vdd vss +*.PININFO core:I ngate:O pgate:O iovdd:B vdd:B vss:B +XI1 core iovdd pgate vdd vss / LevelUpInv +XI0 core iovdd ngate vdd vss / LevelUpInv +.ENDS + +************************************************************************ +* Library Name: sg13g2_io +* Cell Name: sg13g2_IOPadOut4mA +* View Name: schematic +************************************************************************ + +.SUBCKT sg13g2_IOPadOut4mA c2p iovdd iovss pad vdd vss +*.PININFO c2p:I iovdd:B iovss:B pad:B vdd:B vss:B +XI6 c2p iovdd net2 net1 vdd vss / GateLevelUpInv +XI2 pad iovdd iovss / DCPDiode +MN0 pad net2 iovss iovss sg13_hv_nmos m=1 w=8.8u l=600.0n ng=2 +MP0 pad net1 iovdd iovdd sg13_hv_pmos m=1 w=26.64u l=600.0n ng=4 +XI3 iovss pad iovdd / DCNDiode +.ENDS + +************************************************************************ +* Library Name: sg13g2_io +* Cell Name: sg13g2_Filler10000 +* View Name: schematic +************************************************************************ + +.SUBCKT sg13g2_Filler10000 iovdd iovss vdd vss +*.PININFO iovdd:B iovss:B vdd:B vss:B +.ENDS + +************************************************************************ +* Library Name: sg13g2_io +* Cell Name: sg13g2_IOPadVss +* View Name: schematic +************************************************************************ + +.SUBCKT sg13g2_IOPadVss iovdd iovss vdd vss +*.PININFO iovdd:B iovss:B vdd:B vss:B +XI2 vss iovdd iovss / DCPDiode +XI1 iovss vss iovss / DCNDiode +.ENDS + +************************************************************************ +* Library Name: sg13g2_io +* Cell Name: sg13g2_IOPadIOVss +* View Name: schematic +************************************************************************ + +.SUBCKT sg13g2_IOPadIOVss iovdd iovss vdd vss +*.PININFO iovdd:B iovss:B vdd:B vss:B +DD2 iovss iovss dantenna m=1 w=1.26u l=27.78u a=35.003p p=58.08u +DD1 iovss iovdd dpantenna m=1 w=1.26u l=27.78u a=35.003p p=58.08u +.ENDS + +************************************************************************ +* Library Name: sg13g2_io +* Cell Name: sg13g2_IOPadOut16mA +* View Name: schematic +************************************************************************ + +.SUBCKT sg13g2_IOPadOut16mA c2p iovdd iovss pad vdd vss +*.PININFO c2p:I iovdd:B iovss:B pad:B vdd:B vss:B +XI6 c2p iovdd net2 net1 vdd vss / GateLevelUpInv +XI2 pad iovdd iovss / DCPDiode +MN0 pad net2 iovss iovss sg13_hv_nmos m=1 w=35.2u l=600.0n ng=8 +MP0 pad net1 iovdd iovdd sg13_hv_pmos m=1 w=106.56u l=600.0n ng=16 +XI3 iovss pad iovdd / DCNDiode +.ENDS + +************************************************************************ +* Library Name: sg13g2_io +* Cell Name: RCClampResistor +* View Name: schematic +************************************************************************ + +.SUBCKT RCClampResistor pin1 pin2 +*.PININFO pin1:B pin2:B +RR29 net15 net16 rppd 5.239K m=1 l=20u w=1u ps=180n ++ trise=0.0 b=0 +RR28 net20 net21 rppd 5.239K m=1 l=20u w=1u ps=180n ++ trise=0.0 b=0 +RR27 net23 net24 rppd 5.239K m=1 l=20u w=1u ps=180n ++ trise=0.0 b=0 +RR26 net26 net27 rppd 5.239K m=1 l=20u w=1u ps=180n ++ trise=0.0 b=0 +RR25 net29 pin2 rppd 5.239K m=1 l=20u w=1u ps=180n trise=0.0 ++ b=0 +RR24 net17 net18 rppd 5.239K m=1 l=20u w=1u ps=180n ++ trise=0.0 b=0 +RR23 net16 net17 rppd 5.239K m=1 l=20u w=1u ps=180n ++ trise=0.0 b=0 +RR22 net28 net29 rppd 5.239K m=1 l=20u w=1u ps=180n ++ trise=0.0 b=0 +RR21 net25 net26 rppd 5.239K m=1 l=20u w=1u ps=180n ++ trise=0.0 b=0 +RR20 net22 net23 rppd 5.239K m=1 l=20u w=1u ps=180n ++ trise=0.0 b=0 +RR19 net19 net20 rppd 5.239K m=1 l=20u w=1u ps=180n ++ trise=0.0 b=0 +RR18 net27 net28 rppd 5.239K m=1 l=20u w=1u ps=180n ++ trise=0.0 b=0 +RR17 net24 net25 rppd 5.239K m=1 l=20u w=1u ps=180n ++ trise=0.0 b=0 +RR16 net21 net22 rppd 5.239K m=1 l=20u w=1u ps=180n ++ trise=0.0 b=0 +RR15 net18 net19 rppd 5.239K m=1 l=20u w=1u ps=180n ++ trise=0.0 b=0 +RR14 net5 net6 rppd 5.239K m=1 l=20u w=1u ps=180n trise=0.0 ++ b=0 +RR13 net8 net9 rppd 5.239K m=1 l=20u w=1u ps=180n trise=0.0 ++ b=0 +RR12 net11 net12 rppd 5.239K m=1 l=20u w=1u ps=180n ++ trise=0.0 b=0 +RR11 net14 net15 rppd 5.239K m=1 l=20u w=1u ps=180n ++ trise=0.0 b=0 +RR10 net2 net3 rppd 5.239K m=1 l=20u w=1u ps=180n trise=0.0 ++ b=0 +RR9 net1 net2 rppd 5.239K m=1 l=20u w=1u ps=180n trise=0.0 ++ b=0 +RR8 net13 net14 rppd 5.239K m=1 l=20u w=1u ps=180n trise=0.0 ++ b=0 +RR7 net10 net11 rppd 5.239K m=1 l=20u w=1u ps=180n trise=0.0 ++ b=0 +RR6 net7 net8 rppd 5.239K m=1 l=20u w=1u ps=180n trise=0.0 ++ b=0 +RR5 net4 net5 rppd 5.239K m=1 l=20u w=1u ps=180n trise=0.0 ++ b=0 +RR4 net12 net13 rppd 5.239K m=1 l=20u w=1u ps=180n trise=0.0 ++ b=0 +RR3 net9 net10 rppd 5.239K m=1 l=20u w=1u ps=180n trise=0.0 ++ b=0 +RR2 net6 net7 rppd 5.239K m=1 l=20u w=1u ps=180n trise=0.0 ++ b=0 +RR1 net3 net4 rppd 5.239K m=1 l=20u w=1u ps=180n trise=0.0 ++ b=0 +RR0 pin1 net1 rppd 5.239K m=1 l=20u w=1u ps=180n trise=0.0 ++ b=0 +.ENDS + +************************************************************************ +* Library Name: sg13g2_io +* Cell Name: Clamp_N43N43D4R +* View Name: schematic +************************************************************************ + +.SUBCKT Clamp_N43N43D4R gate pad tie +*.PININFO gate:I pad:B tie:B +MN0<1> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<2> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<3> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<4> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<5> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<6> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<7> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<8> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<9> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<10> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<11> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<12> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<13> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<14> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<15> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<16> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<17> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<18> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<19> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<20> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<21> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<22> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<23> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<24> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<25> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<26> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<27> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<28> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<29> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<30> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<31> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<32> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<33> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<34> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<35> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<36> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<37> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<38> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<39> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<40> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<41> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<42> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<43> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<44> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<45> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<46> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<47> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<48> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<49> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<50> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<51> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<52> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<53> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<54> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<55> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<56> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<57> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<58> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<59> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<60> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<61> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<62> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<63> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<64> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<65> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<66> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<67> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<68> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<69> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<70> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<71> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<72> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<73> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<74> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<75> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<76> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<77> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<78> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<79> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<80> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<81> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<82> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<83> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<84> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<85> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<86> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<87> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<88> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<89> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<90> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<91> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<92> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<93> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<94> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<95> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<96> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<97> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<98> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<99> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<100> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<101> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<102> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<103> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<104> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<105> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<106> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<107> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<108> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<109> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<110> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<111> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<112> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<113> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<114> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<115> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<116> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<117> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<118> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<119> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<120> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<121> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<122> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<123> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<124> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<125> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<126> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<127> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<128> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<129> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<130> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<131> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<132> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<133> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<134> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<135> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<136> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<137> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<138> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<139> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<140> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<141> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<142> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<143> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<144> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<145> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<146> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<147> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<148> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<149> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<150> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<151> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<152> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<153> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<154> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<155> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<156> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<157> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<158> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<159> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<160> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<161> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<162> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<163> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<164> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<165> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<166> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<167> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<168> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<169> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<170> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<171> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +MN0<172> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1 +.ENDS + +************************************************************************ +* Library Name: sg13g2_io +* Cell Name: RCClampInverter +* View Name: schematic +************************************************************************ + +.SUBCKT RCClampInverter in iovss out supply +*.PININFO in:B iovss:B out:B supply:B +MN1 iovss in iovss iovss sg13_hv_nmos m=1 w=126.000u l=9.5u ng=14 +MN0 out in iovss iovss sg13_hv_nmos m=1 w=108.000u l=500.0n ng=12 +MP0 out in supply supply sg13_hv_pmos m=1 w=350.000u l=500.0n ng=50 +.ENDS + +************************************************************************ +* Library Name: sg13g2_io +* Cell Name: sg13g2_IOPadIOVdd +* View Name: schematic +************************************************************************ + +.SUBCKT sg13g2_IOPadIOVdd iovdd iovss vdd vss +*.PININFO iovdd:B iovss:B vdd:B vss:B +XI2 iovdd net1 / RCClampResistor +XI0 net2 iovdd iovss / Clamp_N43N43D4R +XI1 net1 iovss net2 iovdd / RCClampInverter +.ENDS + +************************************************************************ +* Library Name: sg13g2_io +* Cell Name: sg13g2_IOPadTriOut30mA +* View Name: schematic +************************************************************************ + +.SUBCKT sg13g2_IOPadTriOut30mA c2p c2p_en iovdd iovss pad vdd vss +*.PININFO c2p:I c2p_en:I iovdd:B iovss:B pad:B vdd:B vss:B +XI7 c2p c2p_en iovdd net2 net1 vdd vss / GateDecode +XI2 pad iovdd iovss / DCPDiode +MN0 pad net2 iovss iovss sg13_hv_nmos m=1 w=66.000u l=600.0n ng=15 +MP0 pad net1 iovdd iovdd sg13_hv_pmos m=1 w=199.8u l=600.0n ng=30 +XI3 iovss pad iovdd / DCNDiode +.ENDS + +************************************************************************ +* Library Name: sg13g2_io +* Cell Name: sg13g2_IOPadTriOut16mA +* View Name: schematic +************************************************************************ + +.SUBCKT sg13g2_IOPadTriOut16mA c2p c2p_en iovdd iovss pad vdd vss +*.PININFO c2p:I c2p_en:I iovdd:B iovss:B pad:B vdd:B vss:B +XI7 c2p c2p_en iovdd net2 net1 vdd vss / GateDecode +XI2 pad iovdd iovss / DCPDiode +MN0 pad net2 iovss iovss sg13_hv_nmos m=1 w=35.2u l=600.0n ng=8 +MP0 pad net1 iovdd iovdd sg13_hv_pmos m=1 w=106.56u l=600.0n ng=16 +XI3 iovss pad iovdd / DCNDiode +.ENDS + +************************************************************************ +* Library Name: sg13g2_io +* Cell Name: sg13g2_IOPadInOut16mA +* View Name: schematic +************************************************************************ + +.SUBCKT sg13g2_IOPadInOut16mA c2p c2p_en iovdd iovss p2c pad vdd vss +*.PININFO c2p:I c2p_en:I p2c:O iovdd:B iovss:B pad:B vdd:B vss:B +XI3 iovss pad iovdd / DCNDiode +XI2 pad iovdd iovss / DCPDiode +MN0 pad net2 iovss iovss sg13_hv_nmos m=1 w=35.2u l=600.0n ng=8 +MP0 pad net1 iovdd iovdd sg13_hv_pmos m=1 w=106.56u l=600.0n ng=16 +XI0 c2p c2p_en iovdd net2 net1 vdd vss / GateDecode +XI1 p2c iovdd iovss pad vdd vss / LevelDown +.ENDS + +************************************************************************ +* Library Name: sg13g2_io +* Cell Name: sg13g2_Filler200 +* View Name: schematic +************************************************************************ + +.SUBCKT sg13g2_Filler200 iovdd iovss vdd vss +*.PININFO iovdd:B iovss:B vdd:B vss:B +.ENDS + +************************************************************************ +* Library Name: sg13g2_io +* Cell Name: sg13g2_Filler2000 +* View Name: schematic +************************************************************************ + +.SUBCKT sg13g2_Filler2000 iovdd iovss vdd vss +*.PININFO iovdd:B iovss:B vdd:B vss:B +.ENDS + +************************************************************************ +* Library Name: sg13g2_io +* Cell Name: sg13g2_IOPadOut30mA +* View Name: schematic +************************************************************************ + +.SUBCKT sg13g2_IOPadOut30mA c2p iovdd iovss pad vdd vss +*.PININFO c2p:I iovdd:B iovss:B pad:B vdd:B vss:B +XI6 c2p iovdd net2 net1 vdd vss / GateLevelUpInv +XI2 pad iovdd iovss / DCPDiode +MN0 pad net2 iovss iovss sg13_hv_nmos m=1 w=66.000u l=600.0n ng=15 +MP0 pad net1 iovdd iovdd sg13_hv_pmos m=1 w=199.8u l=600.0n ng=30 +XI3 iovss pad iovdd / DCNDiode +.ENDS + +************************************************************************ +* Library Name: sg13g2_io +* Cell Name: sg13g2_IOPadInOut4mA +* View Name: schematic +************************************************************************ + +.SUBCKT sg13g2_IOPadInOut4mA c2p c2p_en iovdd iovss p2c pad vdd vss +*.PININFO c2p:I c2p_en:I p2c:O iovdd:B iovss:B pad:B vdd:B vss:B +XI3 iovss pad iovdd / DCNDiode +XI2 pad iovdd iovss / DCPDiode +MN0 pad net2 iovss iovss sg13_hv_nmos m=1 w=8.8u l=600.0n ng=2 +MP0 pad net1 iovdd iovdd sg13_hv_pmos m=1 w=26.64u l=600.0n ng=4 +XI0 c2p c2p_en iovdd net2 net1 vdd vss / GateDecode +XI1 p2c iovdd iovss pad vdd vss / LevelDown +.ENDS + +************************************************************************ +* Library Name: sg13g2_io +* Cell Name: Clamp_N20N0D +* View Name: schematic +************************************************************************ + +.SUBCKT Clamp_N20N0D iovss pad +*.PININFO iovss:B pad:B +MN0 pad net2 iovss iovss sg13_hv_nmos m=1 w=88.000u l=600.0n ng=20 +RR1 iovss net2 rppd 1.959K m=1 l=3.54u w=500n ps=180n ++ trise=0.0 b=0 +.ENDS + +************************************************************************ +* Library Name: sg13g2_io +* Cell Name: Clamp_P20N0D +* View Name: schematic +************************************************************************ + +.SUBCKT Clamp_P20N0D iovdd iovss pad +*.PININFO iovdd:B iovss:B pad:B +MP0 pad net2 iovdd iovdd sg13_hv_pmos m=1 w=266.4u l=600.0n ng=40 +RR0 net2 iovdd rppd 6.768K m=1 l=12.9u w=500n ps=180n ++ trise=0.0 b=0 +.ENDS + +************************************************************************ +* Library Name: sg13g2_io +* Cell Name: sg13g2_IOPadAnalog +* View Name: schematic +************************************************************************ + +.SUBCKT sg13g2_IOPadAnalog iovdd iovss pad padres vdd vss +*.PININFO iovdd:B iovss:B pad:B padres:B vdd:B vss:B +XI8 iovss pad / Clamp_N20N0D +XI9 iovdd iovss pad / Clamp_P20N0D +XI3 iovss pad iovdd / DCNDiode +XI2 pad iovdd iovss / DCPDiode +XI6 padres iovss pad iovdd / SecondaryProtection +.ENDS + +************************************************************************ +* Library Name: sg13g2_io +* Cell Name: sg13g2_Filler4000 +* View Name: schematic +************************************************************************ + +.SUBCKT sg13g2_Filler4000 iovdd iovss vdd vss +*.PININFO iovdd:B iovss:B vdd:B vss:B +.ENDS + +************************************************************************ +* Library Name: sg13g2_io +* Cell Name: sg13g2_Corner +* View Name: schematic +************************************************************************ + +.SUBCKT sg13g2_Corner iovdd iovss vdd vss +*.PININFO iovdd:B iovss:B vdd:B vss:B +.ENDS + +************************************************************************ +* Library Name: sg13g2_io +* Cell Name: sg13g2_Filler400 +* View Name: schematic +************************************************************************ + +.SUBCKT sg13g2_Filler400 iovdd iovss vdd vss +*.PININFO iovdd:B iovss:B vdd:B vss:B +.ENDS + +************************************************************************ +* Library Name: sg13g2_io +* Cell Name: sg13g2_IOPadTriOut4mA +* View Name: schematic +************************************************************************ + +.SUBCKT sg13g2_IOPadTriOut4mA c2p c2p_en iovdd iovss pad vdd vss +*.PININFO c2p:I c2p_en:I iovdd:B iovss:B pad:B vdd:B vss:B +XI7 c2p c2p_en iovdd net2 net1 vdd vss / GateDecode +XI2 pad iovdd iovss / DCPDiode +MN0 pad net2 iovss iovss sg13_hv_nmos m=1 w=8.8u l=600.0n ng=2 +MP0 pad net1 iovdd iovdd sg13_hv_pmos m=1 w=26.64u l=600.0n ng=4 +XI3 iovss pad iovdd / DCNDiode +.ENDS + +************************************************************************ +* Library Name: sg13g2_io +* Cell Name: sg13g2_IOPadIn +* View Name: schematic +************************************************************************ + +.SUBCKT sg13g2_IOPadIn iovdd iovss p2c pad vdd vss +*.PININFO p2c:O iovdd:B iovss:B pad:B vdd:B vss:B +XI1 p2c iovdd iovss pad vdd vss / LevelDown +XI2 pad iovdd iovss / DCPDiode +XI3 iovss pad iovdd / DCNDiode +.ENDS + +************************************************************************ +* Library Name: sg13g2_io +* Cell Name: sg13g2_IOPadVdd +* View Name: schematic +************************************************************************ + +.SUBCKT sg13g2_IOPadVdd iovdd iovss vdd vss +*.PININFO iovdd:B iovss:B vdd:B vss:B +DD1 vdd iovdd dpantenna m=1 w=1.26u l=27.78u a=35.003p p=58.08u +DD0 iovss vdd dantenna m=1 w=1.26u l=27.78u a=35.003p p=58.08u +.ENDS + +************************************************************************ +* Library Name: sg13g2_io +* Cell Name: sg13g2_Filler1000 +* View Name: schematic +************************************************************************ + +.SUBCKT sg13g2_Filler1000 iovdd iovss vdd vss +*.PININFO iovdd:B iovss:B vdd:B vss:B +.ENDS diff --git a/flow/platforms/ihp-sg13g2/config.mk b/flow/platforms/ihp-sg13g2/config.mk index 176cd3831f..90be2e80e3 100644 --- a/flow/platforms/ihp-sg13g2/config.mk +++ b/flow/platforms/ihp-sg13g2/config.mk @@ -9,7 +9,7 @@ export PROCESS = ihp-sg13g2 ifdef FOOTPRINT_TCL export ADDITIONAL_LEFS += $(PLATFORM_DIR)/lef/sg13g2_io.lef \ $(PLATFORM_DIR)/lef/bondpad_70x70.lef - export ADDITIONAL_LIBS += $(PLATFORM_DIR)/lib/sg13g2_io_dummy.lib + export ADDITIONAL_LIBS += $(PLATFORM_DIR)/lib/sg13g2_io_typ_1p2V_3p3V_25C.lib export ADDITIONAL_GDS += $(PLATFORM_DIR)/gds/sg13g2_io.gds \ $(PLATFORM_DIR)/gds/bondpad_70x70.gds endif @@ -122,10 +122,10 @@ export GND_NETS_VOLTAGES ?= "VSS 0.0" export IR_DROP_LAYER ?= Metal1 # DRC Check -export KLAYOUT_DRC_FILE = $(PLATFORM_DIR)/drc/sg13g2.lydrc +export KLAYOUT_DRC_FILE ?= $(PLATFORM_DIR)/drc/sg13g2_minimal.lydrc #LVS Check -export CDL_FILE = $(PLATFORM_DIR)/cdl/sg13g2_stdcell.cdl +export CDL_FILE ?= $(PLATFORM_DIR)/cdl/sg13g2_stdcell.cdl #export KLAYOUT_LVS_FILE = $(PLATFORM_DIR)/lvs/$(PLATFORM).lylvs #Temporary: skip post-DRT repair antennas diff --git a/flow/platforms/ihp-sg13g2/drc/sg13g2.lydrc b/flow/platforms/ihp-sg13g2/drc/sg13g2.lydrc deleted file mode 100644 index 4238b0c055..0000000000 --- a/flow/platforms/ihp-sg13g2/drc/sg13g2.lydrc +++ /dev/null @@ -1,766 +0,0 @@ - - - - - - drc - - - - false - false - - true - drc_scripts - tools_menu.drc.end - dsl - drc-dsl-xml - -application = RBA::Application.instance -main_window = application.main_window -if main_window - curr_layout_view = main_window.current_view() - unless curr_layout_view - layout_path = RBA::FileDialog::ask_open_file_name("Chose your layout file.", ".", "GDSII files (*.GDS *.gds *.GDS.gz *.gds.gz *.GDS2 *.gds2 *.GDS2.gz *.gds2.gz);; All files (*)") - main_window.load_layout(layout_path, 1) - curr_layout_view = main_window.current_view() - end - active_cellname = RBA::CellView::active.cell_name -else - puts "DRC: batch mode" - if $cell - active_cellname = $cell - puts "Active cell: " + active_cellname - else - raise("ERROR: 'cell' script variable must be defined on cmd line") - end -end -active_layout = RBA::CellView::active.layout - -source(active_layout, active_cellname) -if active_layout.dbu != 0.001 - puts "WARNING: Layout dbu value (" + active_layout.dbu.to_s + " ) deviates from rule file dbu value (0.001). This will scale the layout and may not be intended." -end -report("design rules: sg13g2 | layout cell: " + active_cellname, "sg13g2_#{active_cellname}.lyrdb", active_cellname) - -deep - -# Initial definitions of control flow variables -conditional_enabled = {} -conditional_enabled[:density] = true -conditional_enabled[:sanityRules] = true - -class DRC::DRCLayer - def ext_and(other) - self_min_coherence_state = self.data.min_coherence? - other_min_coherence_state = other.data.min_coherence? - self.data.min_coherence = true - other.data.min_coherence = true - output_layer = self & other - self.data.min_coherence = self_min_coherence_state - other.data.min_coherence = other_min_coherence_state - return output_layer - end - - def ext_area(constraint) - output_layer = self.dup - constraint.each do |expression| - output_layer.data.min_coherence = true - relation = expression[0] - value = expression[1].to_i - if relation == ">" - output_layer = output_layer.with_area((value + 1), nil) - elsif relation == "<" - output_layer = output_layer.with_area(nil, value) - elsif relation == "==" - output_layer = output_layer.with_area(value) - elsif relation == "!=" - output_layer = output_layer.without_area(value) - elsif relation == ">=" - output_layer = output_layer.with_area(value, nil) - elsif relation == "<=" - output_layer = output_layer.with_area(nil, (value + 1)) - else - raise "invalid expression" - end - end - return output_layer - end - - def ext_constraint_satisfied(value, constraint) - output_bool = true - constraint.each do |expression| - if expression[0] == ">" - output_bool = output_bool && (value > expression[1]) - elsif expression[0] == "<" - output_bool = output_bool && (value < expression[1]) - elsif expression[0] == "==" - output_bool = output_bool && (value == expression[1]) - elsif expression[0] == "!=" - output_bool = output_bool && (value != expression[1]) - elsif expression[0] == ">=" - output_bool = output_bool && (value >= expression[1]) - elsif expression[0] == "<=" - output_bool = output_bool && (value <= expression[1]) - else - raise "invalid expression" - end - end - return output_bool - end - - def ext_covering(other) - self_min_coherence_state = self.data.min_coherence? - other_min_coherence_state = other.data.min_coherence? - self.data.min_coherence = true - other.data.min_coherence = true - output_layer = self.covering(other.inside(self)) - self.data.min_coherence = self_min_coherence_state - other.data.min_coherence = other_min_coherence_state - return output_layer - end - - def ext_not(other) - self_min_coherence_state = self.data.min_coherence? - other_min_coherence_state = other.data.min_coherence? - self.data.min_coherence = true - other.data.min_coherence = true - output_layer = self - other - self.data.min_coherence = self_min_coherence_state - other.data.min_coherence = other_min_coherence_state - return output_layer - end - - def ext_or(other) - self_min_coherence_state = self.data.min_coherence? - other_min_coherence_state = other.data.min_coherence? - self.data.min_coherence = true - other.data.min_coherence = true - output_layer = self | other - self.data.min_coherence = self_min_coherence_state - other.data.min_coherence = other_min_coherence_state - return output_layer - end - - def ext_rectangles(axis_aligned = false, use_bbox = false, constraint1 = nil, constraint2 = nil, aspect_ratio_constraint = nil, inverted: false) - self_min_coherence_state = self.data.min_coherence? - self.data.min_coherence = true - if ( ( constraint1 && ( !constraint2 || constraint1.length() > 1 || constraint1[0][0] != "==") ) || - ( constraint2 && ( constraint2.length() > 1 || constraint2[0][0] != "==" ) ) || - ( constraint1 && constraint2 && constraint1[0][1] != constraint2[0][1] ) ) - raise "ext_rectangle: unsupported options" - end - square = constraint1 ? true : false - shape_filter = - if use_bbox - @engine.extents - elsif axis_aligned - @engine.rectangles - else - @engine.if_all((@engine.corners == 270).count == 4, @engine.corners.count == 4) - end - if square - if use_bbox - shape_filter = @engine.if_all((@engine.extents.length == constraint1[0][1]).count == 4) - else - square_filter = (@engine.length == constraint1[0][1]).count == 4 - shape_filter = @engine.if_all(shape_filter, square_filter) - end - end - if inverted - output_layer = self.drc(! shape_filter) - else - output_layer = self.drc(shape_filter) - end - self.data.min_coherence = self_min_coherence_state - return output_layer - end - - def ext_ring - holes = self.holes - hulls = self.hulls - covering = hulls.covering(holes) - result = covering.and(self) - return result - end - - def ext_interacting_with_text(text_layer_number, text) - text_layer = @engine.labels(text_layer_number) - initial_merged_semantics = self.data.merged_semantics? - self.data.merged_semantics = false - result = self.interacting(text_layer.texts(text)) - self.data.merged_semantics = initial_merged_semantics - return result - end - - def ext_with_density(range, *args) - if self.is_empty? - return DRC::DRCLayer::new(@engine, RBA::Region::new()) - end - origin = 'cc' - tile_size = nil - tile_step = nil - arguments = [range] - args.each do |a| - if a.is_a?(DRC::DRCTileSize) - tile_size = a - arguments.push(tile_size) - elsif a.is_a?(DRC::DRCTileStep) - tile_step = a - arguments.push(tile_step) - elsif a.is_a?(String) - origin = a - else - raise "argument error" - end - end - bbox = @engine.extent.bbox - if origin == 'll' - origin_x = bbox.left - origin_y = bbox.bottom - tile_origin = DRC::DRCTileOrigin::new(origin_x, origin_y) - arguments.push(tile_origin) - elsif origin != 'cc' - raise "Unkown origin: 'cc' or 'll' expected" - end - if tile_size - return self.with_density(*arguments) - else - tile_size = DRC::DRCTileSize::new(bbox.width, bbox.height) - tile_count = DRC::DRCTileCount::new(1,2) - enlarged_bbox = bbox.enlarged(1.1).to_itype(@engine.dbu) - boundary_layer = DRC::DRCLayer::new(@engine, RBA::Region::new(enlarged_bbox)) - tile_boundary = DRC::DRCTileBoundary::new(boundary_layer) - result = self.with_density(*arguments, tile_size, tile_count, tile_boundary) - return result.raw.overlapping(DRC::DRCLayer::new(@engine, RBA::Region::new(bbox.to_itype(@engine.dbu)))) - end - end -end -NWell_org = source.polygons("31/0") -NWell_pin_org = source.polygons("31/2") -Activ_org = source.polygons("1/0") -Activ_pin_org = source.polygons("1/2") -Activ_filler_org = source.polygons("1/22") -ThickGateOx_org = source.polygons("44/0") -GatPoly_org = source.polygons("5/0") -GatPoly_pin_org = source.polygons("5/2") -GatPoly_filler_org = source.polygons("5/22") -Cont_org = source.polygons("6/0") -Metal1_org = source.polygons("8/0") -Metal1_pin_org = source.polygons("8/2") -Metal1_filler_org = source.polygons("8/22") -Metal1_slit_org = source.polygons("8/24") -Via1_org = source.polygons("19/0") -Metal2_org = source.polygons("10/0") -Metal2_pin_org = source.polygons("10/2") -Metal2_filler_org = source.polygons("10/22") -Metal2_slit_org = source.polygons("10/24") -Via2_org = source.polygons("29/0") -Metal3_org = source.polygons("30/0") -Metal3_pin_org = source.polygons("30/2") -Metal3_filler_org = source.polygons("30/22") -Metal3_slit_org = source.polygons("30/24") -Via3_org = source.polygons("49/0") -Metal4_org = source.polygons("50/0") -Metal4_pin_org = source.polygons("50/2") -Metal4_filler_org = source.polygons("50/22") -Metal4_slit_org = source.polygons("50/24") -Via4_org = source.polygons("66/0") -Metal5_org = source.polygons("67/0") -Metal5_pin_org = source.polygons("67/2") -Metal5_filler_org = source.polygons("67/22") -Metal5_slit_org = source.polygons("67/24") -TopVia1_org = source.polygons("125/0") -TopMetal1_org = source.polygons("126/0") -TopMetal1_pin_org = source.polygons("126/2") -TopMetal1_filler_org = source.polygons("126/22") -TopMetal1_slit_org = source.polygons("126/24") -Vmim_org = source.polygons("129/0") -TopVia2_org = source.polygons("133/0") -TopMetal2_org = source.polygons("134/0") -TopMetal2_pin_org = source.polygons("134/2") -TopMetal2_filler_org = source.polygons("134/22") -TopMetal2_slit_org = source.polygons("134/24") -Passiv_org = source.polygons("9/0") -EdgeSeal_org = source.polygons("39/0") -BiWind_org = source.polygons("3/0") -PEmWind_org = source.polygons("11/0") -BasPoly_org = source.polygons("13/0") -DeepCo_org = source.polygons("35/0") -PEmPoly_org = source.polygons("53/0", "70/0") -EmPoly_org = source.polygons("55/0") -LDMOS_org = source.polygons("57/0") -PBiWind_org = source.polygons("58/0") -Flash_org = source.polygons("71/0") -ColWind_org = source.polygons("139/0") -SRAM_org = source.polygons("25/0") -TRANS_org = source.polygons("26/0") -NoDRC = source.polygons("62/0") -LBE_org = source.polygons("157/0") -NWell = NWell_org.ext_not(NoDRC) -Activ = Activ_org.ext_not(NoDRC) -ThickGateOx = ThickGateOx_org.ext_not(NoDRC) -GatPoly = GatPoly_org.ext_not(NoDRC) -Cont = Cont_org.ext_not(NoDRC) -ActFiller = Activ_filler_org.ext_not(NoDRC) -GatFiller = GatPoly_filler_org.ext_not(NoDRC) -Activ_pin = Activ_pin_org.ext_not(NoDRC) -GatPoly_pin = GatPoly_pin_org.ext_not(NoDRC) -NWell_pin = NWell_pin_org.ext_not(NoDRC) -Metal1 = Metal1_org.ext_not(NoDRC) -Via1 = Via1_org.ext_not(NoDRC) -Metal2 = Metal2_org.ext_not(NoDRC) -Via2 = Via2_org.ext_not(NoDRC) -Metal3 = Metal3_org.ext_not(NoDRC) -Via3 = Via3_org.ext_not(NoDRC) -Metal4 = Metal4_org.ext_not(NoDRC) -Via4 = Via4_org.ext_not(NoDRC) -Metal5 = Metal5_org.ext_not(NoDRC) -Vmim = Vmim_org.ext_not(NoDRC) -TopMetal1 = TopMetal1_org.ext_not(NoDRC) -TopVia2 = TopVia2_org.ext_not(NoDRC) -TopMetal2 = TopMetal2_org.ext_not(NoDRC) -Passiv = Passiv_org.ext_not(NoDRC) -EdgeSeal = EdgeSeal_org.ext_not(NoDRC) -M1Filler = Metal1_filler_org.ext_not(NoDRC) -M2Filler = Metal2_filler_org.ext_not(NoDRC) -M3Filler = Metal3_filler_org.ext_not(NoDRC) -M4Filler = Metal4_filler_org.ext_not(NoDRC) -M5Filler = Metal5_filler_org.ext_not(NoDRC) -TopMet1Filler = TopMetal1_filler_org.ext_not(NoDRC) -TopMet2Filler = TopMetal2_filler_org.ext_not(NoDRC) -M1Slit = Metal1_slit_org.ext_not(NoDRC) -M2Slit = Metal2_slit_org.ext_not(NoDRC) -M3Slit = Metal3_slit_org.ext_not(NoDRC) -M4Slit = Metal4_slit_org.ext_not(NoDRC) -M5Slit = Metal5_slit_org.ext_not(NoDRC) -TopMet1Slit = TopMetal1_slit_org.ext_not(NoDRC) -TopMet2Slit = TopMetal2_slit_org.ext_not(NoDRC) -Metal1_pin = Metal1_pin_org.ext_not(NoDRC) -Metal2_pin = Metal2_pin_org.ext_not(NoDRC) -Metal3_pin = Metal3_pin_org.ext_not(NoDRC) -Metal4_pin = Metal4_pin_org.ext_not(NoDRC) -Metal5_pin = Metal5_pin_org.ext_not(NoDRC) -TopMetal1_pin = TopMetal1_pin_org.ext_not(NoDRC) -TopMetal2_pin = TopMetal2_pin_org.ext_not(NoDRC) -TRANS = TRANS_org.ext_not(NoDRC) -SRAM = SRAM_org.ext_not(NoDRC) -LBE = LBE_org.ext_not(NoDRC) -TopVia1 = NoDRC.ext_or(Vmim_org).ext_or(TopVia1_org.ext_not(NoDRC)) -Activ_Act_a = Activ.width(150) -ThickGateOx_TGO_f = ThickGateOx.width(860) -Cont_SQ = Cont.ext_rectangles(true, false, [["==", 160]], [["==", 160]], nil) -ContBar = Cont.ext_area([[">", (0.16*0.16)*1000.0*1000.0]]) -Act_density = ActFiller.ext_or(Activ) -Gat_density = GatFiller.ext_or(GatPoly) -Act_Nsram = Activ.ext_not(SRAM) -GP_Nsram = GatPoly.ext_not(SRAM) -M1_Nsram = Metal1.ext_not(SRAM) -M2_Nsram = Metal2.ext_not(SRAM) -M3_Nsram = Metal3.ext_not(SRAM) -M4_Nsram = Metal4.ext_not(SRAM) -M5_Nsram = Metal5.ext_not(SRAM) -M1_density = M1Filler.ext_or(Metal1).ext_not(M1Slit) -M2_density = M2Filler.ext_or(Metal2).ext_not(M2Slit) -M3_density = M3Filler.ext_or(Metal3).ext_not(M3Slit) -M4_density = M4Filler.ext_or(Metal4).ext_not(M4Slit) -M5_density = M5Filler.ext_or(Metal5).ext_not(M5Slit) -TM1_density = TopMet1Filler.ext_or(TopMetal1).ext_not(TopMet1Slit) -TM2_density = TopMet2Filler.ext_or(TopMetal2).ext_not(TopMet2Slit) -emi2Pin = Metal2_pin.ext_and(TRANS).ext_interacting_with_text(63, "E") -GP_Nsram_Gat_a = GP_Nsram.width(130) -GP_Nsram_Gat_b = GP_Nsram.space(180) -transG2L = TRANS.ext_interacting_with_text(63, "npn13G2L").ext_covering(emi2Pin) - --> do - Activ_Act_a.dup -end.().output("Act.a", "Min. Activ width = 0.15") - --> do - Act_Nsram.space(210) -end.().output("Act.b", "Act.b: Min. Activ space or notch = 0.21") - --> do - ThickGateOx_TGO_f.dup -end.().output("TGO.f", "Min. ThickGateOx width = 0.86") - --> do - GP_Nsram_Gat_a.dup -end.().output("Gat.a", "Min GatPoly width = 0.13") - --> do - GP_Nsram_Gat_b.dup -end.().output("Gat.b", "Min. GatPoly space or notch = 0.18") - --> do - GP_Nsram.separation(Act_Nsram, 70) -end.().output("Gat.d", "Min. GatPoly to Activ space = 0.07") - --> do - Cont.merged(true, 0).outside(EdgeSeal).ext_not(ContBar.ext_or(Cont_SQ)) -end.().output("Cnt.a", "Min.and max. size of Cont = 0.16") - --> do - Cont.merged(true, 0).outside(EdgeSeal).space(180) -end.().output("Cnt.b", "Min. Cont space = 0.18") - --> do - Passiv.width(2100) -end.().output("Pas.a", "Min. Passiv width = 2.10") - --> do - Passiv.space(3500) -end.().output("Pas.b", "Min. Passiv space or notch = 3.50") - --> do - Metal1.width(160) -end.().output("M1.a", "Min. width of Metal1 = 0.16") - --> do - M1_Nsram.space(180) -end.().output("M1.b", "Min. Metal1 space or notch = 0.18") - --> do - Metal2.width(200) -end.().output("M2.a", "Min. width of Metal2 = 0.2") - --> do - M2_Nsram.space(210) -end.().output("M2.b", "Min. Metal2 space or notch = 0.21") - --> do - Metal3.width(200) -end.().output("M3.a", "Min. width of Metal3 = 0.2") - --> do - M3_Nsram.space(210) -end.().output("M3.b", "Min. Metal3 space or notch = 0.21") - --> do - Metal4.width(200) -end.().output("M4.a", "Min. width of Metal4 = 0.2") - --> do - M4_Nsram.space(210) -end.().output("M4.b", "Min. Metal4 space or notch = 0.21") - --> do - Metal5.width(200) -end.().output("M5.a", "Min. width of Metal5 = 0.2") - --> do - M5_Nsram.space(210) -end.().output("M5.b", "Min. Metal5 space or notch = 0.21") - --> do - Via1.ext_not(EdgeSeal).merged(true, 0).outside(transG2L).ext_rectangles(false, false, [["==", 190]], [["==", 190]], nil, inverted: true) -end.().output("Via1.a", "Via1.a: Min. and Maxi. size of Via1 = 0.19") - --> do - Via1.ext_not(EdgeSeal).space(220) -end.().output("Via1.b", "Via1.b: Min. Via1 space = 0.22") - --> do - Via2.ext_not(EdgeSeal).merged(true, 0).outside(transG2L).ext_rectangles(false, false, [["==", 190]], [["==", 190]], nil, inverted: true) -end.().output("Via2.a", "Via2.a: Min. and Maxi. size of Via2 = 0.19") - --> do - Via2.ext_not(EdgeSeal).space(220) -end.().output("Via2.b", "Via2.b: Min. Via2 space = 0.22") - --> do - Via3.ext_not(EdgeSeal).merged(true, 0).outside(transG2L).ext_rectangles(false, false, [["==", 190]], [["==", 190]], nil, inverted: true) -end.().output("Via3.a", "Via3.a: Min. and Maxi. size of Via3 = 0.19") - --> do - Via3.ext_not(EdgeSeal).space(220) -end.().output("Via3.b", "Via3.b: Min. Via3 space = 0.22") - --> do - Via4.ext_not(EdgeSeal).merged(true, 0).outside(transG2L).ext_rectangles(false, false, [["==", 190]], [["==", 190]], nil, inverted: true) -end.().output("Via4.a", "Via4.a: Min. and Maxi. size of Via4 = 0.19") - --> do - Via4.ext_not(EdgeSeal).space(220) -end.().output("Via4.b", "Via4.b: Min. Via4 space = 0.22") - --> do - Vmim.ext_or(TopVia1.ext_not(EdgeSeal)).ext_rectangles(false, false, [["==", 420]], [["==", 420]], nil, inverted: true) -end.().output("TV1.a", "Min.and Max. TopVia1 (µm²) = 0.42") - --> do - TopVia1.ext_or(Vmim).space(420) -end.().output("TV1.b", "Min. TopVia1 space = 0.42") - --> do - TopMetal1.width(1640) -end.().output("TM1.a", "Min. width of TopMetal1 = 1.64") - --> do - TopMetal1.space(1640) -end.().output("TM1.b", "Min. TopMetal1 space or notch = 1.64") - --> do - TopMetal2.width(2000) -end.().output("TM2.a", "Min. width of TopMetal2 = 2.0") - --> do - TopMetal2.space(2000) -end.().output("TM2.b", "Min. TopMetal2 space or notch = 2.0") - --> do - TopVia2.ext_not(EdgeSeal).ext_rectangles(false, false, [["==", 900]], [["==", 900]], nil, inverted: true) -end.().output("TV2.a", "Min.and Max. TopVia2 = 0.90") - --> do - TopVia2.space(1060) -end.().output("TV2.b", "Min. TopVia2 space = 1.06") - -if conditional_enabled[:density] - - -> do - Act_density.ext_with_density(0.0 .. 0.35, 'll') - end.().output("aFil.g", "Min. global Activ coverage = 35.0 %") - - -> do - Act_density.ext_with_density(0.55 .. 1.0, 'll') - end.().output("aFil.g1", "Max. global Activ coverage = 55.0 %") - - -> do - Act_density.ext_with_density(0.0 .. 0.25, 'll', tile_size(800.0), tile_step(400.0)) - end.().output("aFil.g2", "Min. Active coverage ratio for any 800 x 800 µm² chip area = 25.0 %") - - -> do - Act_density.ext_with_density(0.65 .. 1.0, 'll', tile_size(800.0), tile_step(400.0)) - end.().output("aFil.g3", "Max. Active coverage ratio for any 800 x 800 µm² chip area = 65.0 %") - - -> do - Gat_density.ext_with_density(0.0 .. 0.15, 'll') - end.().output("GFil.g", "Min. global GatPoly density [%] = 15.0") - - -> do - M1_density.ext_with_density(0.0 .. 0.35, 'll') - end.().output("M1.j", "Min. global Metal1 density [%] = 35.0") - - -> do - M1_density.ext_with_density(0.6 .. 1.0, 'll') - end.().output("M1.k", "Max. global Metal1 density [%] = 60.0") - - -> do - M2_density.ext_with_density(0.0 .. 0.35, 'll') - end.().output("M2.j", "Min. global Metal2 density [%] = 35.0") - - -> do - M2_density.ext_with_density(0.6 .. 1.0, 'll') - end.().output("M2.k", "Max. global Metal2 density [%] = 60.0") - - -> do - M3_density.ext_with_density(0.0 .. 0.35, 'll') - end.().output("M3.j", "Min. global Metal3 density [%] = 35.0") - - -> do - M3_density.ext_with_density(0.6 .. 1.0, 'll') - end.().output("M3.k", "Max. global Metal3 density [%] = 60.0") - - -> do - M4_density.ext_with_density(0.0 .. 0.35, 'll') - end.().output("M4.j", "Min. global Metal4 density [%] = 35.0") - - -> do - M4_density.ext_with_density(0.6 .. 1.0, 'll') - end.().output("M4.k", "Max. global Metal4 density [%] = 60.0") - - -> do - M5_density.ext_with_density(0.0 .. 0.35, 'll') - end.().output("M5.j", "Min. global Metal5 density [%] = 35.0") - - -> do - M5_density.ext_with_density(0.6 .. 1.0, 'll') - end.().output("M5.k", "Max. global Metal5 density [%] = 60.0") - - -> do - M1_density.ext_with_density(0.0 .. 0.25, 'll', tile_size(800.0), tile_step(400.0)) - end.().output("M1Fil.h", "Min. Metal coverage MM1Filler ratio for any 800 x 800 µm² chip area [%] = 25.0") - - -> do - M1_density.ext_with_density(0.75 .. 1.0, 'll', tile_size(800.0), tile_step(400.0)) - end.().output("M1Fil.k", "Max. Metal coverage MM1Filler ratio for any 800 x 800 µm² chip area [%] = 75.0") - - -> do - M2_density.ext_with_density(0.0 .. 0.25, 'll', tile_size(800.0), tile_step(400.0)) - end.().output("M2Fil.h", "Min. Metal coverage MM2Filler ratio for any 800 x 800 µm² chip area [%] = 25.0") - - -> do - M2_density.ext_with_density(0.75 .. 1.0, 'll', tile_size(800.0), tile_step(400.0)) - end.().output("M2Fil.k", "Max. Metal coverage MM2Filler ratio for any 800 x 800 µm² chip area [%] = 75.0") - - -> do - M3_density.ext_with_density(0.0 .. 0.25, 'll', tile_size(800.0), tile_step(400.0)) - end.().output("M3Fil.h", "Min. Metal coverage MM3Filler ratio for any 800 x 800 µm² chip area [%] = 25.0") - - -> do - M3_density.ext_with_density(0.75 .. 1.0, 'll', tile_size(800.0), tile_step(400.0)) - end.().output("M3Fil.k", "Max. Metal coverage MM3Filler ratio for any 800 x 800 µm² chip area [%] = 75.0") - - -> do - M4_density.ext_with_density(0.0 .. 0.25, 'll', tile_size(800.0), tile_step(400.0)) - end.().output("M4Fil.h", "Min. Metal coverage MM4Filler ratio for any 800 x 800 µm² chip area [%] = 25.0") - - -> do - M4_density.ext_with_density(0.75 .. 1.0, 'll', tile_size(800.0), tile_step(400.0)) - end.().output("M4Fil.k", "Max. Metal coverage MM4Filler ratio for any 800 x 800 µm² chip area [%] = 75.0") - - -> do - M5_density.ext_with_density(0.0 .. 0.25, 'll', tile_size(800.0), tile_step(400.0)) - end.().output("M5Fil.h", "Min. Metal coverage MM5Filler ratio for any 800 x 800 µm² chip area [%] = 25.0") - - -> do - M5_density.ext_with_density(0.75 .. 1.0, 'll', tile_size(800.0), tile_step(400.0)) - end.().output("M5Fil.k", "Max. Metal coverage MM5Filler ratio for any 800 x 800 µm² chip area [%] = 75.0") - - -> do - TM1_density.ext_with_density(0.0 .. 0.25, 'll') - end.().output("TM1.c", "Min. global TopMetal1 density [%] = 25.00") - - -> do - TM1_density.ext_with_density(0.7 .. 1.0, 'll') - end.().output("TM1.d", "Max. global TopMetal1 density [%] = 70.00") - - -> do - TM2_density.ext_with_density(0.0 .. 0.25, 'll') - end.().output("TM2.c", "Min. global TopMetal1 density [%] = 25.0") - - -> do - TM2_density.ext_with_density(0.7 .. 1.0, 'll') - end.().output("TM2.c1", "Max. global TopMetal1 density [%] = 70.0") - - -> do - LBE.ext_with_density(0.2 .. 1.0, 'll') - end.().output("LBE.i", "Max. global LBE density [%] = 20.0 %") - -end - -if conditional_enabled[:sanityRules] - - -> do - Activ_pin.ext_not(Activ) - end.().output("forbidden.a", "Activ enclosure of Activ_pin = 0.0") - - -> do - GatPoly_pin.ext_not(GatPoly) - end.().output("forbidden.b", "GatPoly enclosure of GatPoly_pin = 0.0") - - -> do - NWell_pin.ext_not(NWell) - end.().output("forbidden.c", "NWell enclosure of NWell_pin = 0.0") - - -> do - Metal1_pin.ext_not(Metal1) - end.().output("forbidden.d", "Metal1 enclosure of Metal1_pin = 0.0") - - -> do - Metal2_pin.ext_not(Metal2) - end.().output("forbidden.f.M1", "Metal2 enclosure of Metal2_pin = 0.0") - - -> do - Metal3_pin.ext_not(Metal3) - end.().output("forbidden.f.M2", "Metal3 enclosure of Metal3_pin = 0.0") - - -> do - Metal4_pin.ext_not(Metal4) - end.().output("forbidden.f.M3", "Metal4 enclosure of Metal4_pin = 0.0") - - -> do - Metal5_pin.ext_not(Metal5) - end.().output("forbidden.f.M4", "Metal5 enclosure of Metal5_pin = 0.0") - - -> do - TopMetal1_pin.ext_not(TopMetal1) - end.().output("forbidden.f.M5", "TopMetal1 enclosure of TopMetal1_pin = 0.0") - - -> do - TopMetal2_pin.ext_not(TopMetal2) - end.().output("forbidden.f.MT1", "TopMetal2 enclosure of TopMetal2_pin = 0.0") - - -> do - BiWind_org.dup - end.().output("forbidden.Biwind", "Biwind forbidden layer in 0.13um designs") - - -> do - PEmWind_org.dup - end.().output("forbidden.PEmWind", "PEmWind forbidden layer in 0.13um designs") - - -> do - BasPoly_org.dup - end.().output("forbidden.BasPoly", "BasPoly forbidden layer in 0.13um designs") - - -> do - DeepCo_org.dup - end.().output("forbidden.DeepCo", "DeepCo forbidden layer in 0.13um designs") - - -> do - PEmPoly_org.dup - end.().output("forbidden.PEmPoly", "PEmPoly forbidden layer in 0.13um designs") - - -> do - EmPoly_org.dup - end.().output("forbidden.EmPoly", "EmPoly forbidden layer in 0.13um designs") - - -> do - LDMOS_org.dup - end.().output("forbidden.LDMOS", "LDMOS forbidden layer in 0.13um designs") - - -> do - PBiWind_org.dup - end.().output("forbidden.PBiWind", "PBiWind forbidden layer in 0.13um designs") - - -> do - Flash_org.dup - end.().output("forbidden.Flash", "Flash forbidden layer in 0.13um designs") - - -> do - ColWind_org.dup - end.().output("forbidden.ColWind", "ColWind forbidden layer in 0.13um designs") - -end - --> do - LBE.width(100000) -end.().output("LBE.a", "LBE.a: Min. width of LBE = 100.0") - --> do - LBE.drc(width > 1500000) -end.().output("LBE.b", "LBE.b: Max. width of LBE = 1500.0") - --> do - LBE.ext_area([[">", 250000.0*1000.0*1000.0]]) -end.().output("LBE.b1", "LBE.b1: Max allowed LBE area = 250000.0") - --> do - LBE.space(100000) -end.().output("LBE.c", "LBE.c: Min. LBE space or notch = 100.0") - --> (;lbe_in_seal) do - lbe_in_seal = LBE.merged(true, 0).inside(EdgeSeal.holes.merge) - lbe_in_seal.separation(EdgeSeal, 150000) -end.().output("LBE.d", "LBE.d: Min. space of LBE to inner edge of Edge Seal = 150.0") - --> do - LBE.ext_ring.dup -end.().output("LBE.h", "LBE.h: No LBE ring allowed") - - diff --git a/flow/platforms/ihp-sg13g2/drc/sg13g2_maximal.lydrc b/flow/platforms/ihp-sg13g2/drc/sg13g2_maximal.lydrc new file mode 100644 index 0000000000..435f9147e6 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/drc/sg13g2_maximal.lydrc @@ -0,0 +1,3250 @@ + + + + + + drc + + + + false + false + + true + drc_scripts + tools_menu.drc.end + dsl + drc-dsl-xml + # Supported variables that can be set using "-rd <name>=<value>" on the command line: +# log_file - path to the log file [default: no log file] +# in_gds - path to the GDS layout to check (required in batch mode) +# cell - name of the cell to check +# report_file - path to the report database [default: sg13g2_maximal.lyrdb in the script directory] + +# to set logfile: -rd logfile="sg13g2_maximal.log" +if $log_file + log_file($log_file) +end + +application = RBA::Application.instance +main_window = application.main_window +if main_window and not $in_gds + curr_layout_view = main_window.current_view() + unless curr_layout_view + layout_path = RBA::FileDialog::ask_open_file_name("Chose your layout file.", ".", "GDSII files (*.GDS *.gds *.GDS.gz *.gds.gz *.GDS2 *.gds2 *.GDS2.gz *.gds2.gz);; All files (*)") + unless layout_path + return + end + main_window.load_layout(layout_path, 1) + curr_layout_view = main_window.current_view() + end + active_layout = RBA::CellView::active.layout + active_cellname = RBA::CellView::active.cell_name + source(active_layout, active_cellname) +else + log("DRC: batch mode") + # to set input layout: -rd in_gds="path to GDS file" + # to set cell: -rd cell="topcell" + if $cell + active_cellname = $cell + log("Active cell: " + active_cellname) + source($in_gds, active_cellname) + active_layout = source.layout + else + source($in_gds) + active_layout = source.layout + active_cellname = source.cell_name + end +end + +unless active_layout or $in_gds + raise("layout file must be defined on command line or via 'in_gds' script variable") +end + +if active_layout.dbu != 0.001 + puts "WARNING: Layout dbu value (" + active_layout.dbu.to_s + " ) deviates from rule file dbu value (0.001). This will scale the layout and may not be intended." +end + +report_file = __dir__ + "/sg13g2_maximal.lyrdb" +# to set report file: -rd report_file="sg13g2_maximal.lyrdb" +if $report_file + report_file = File.expand_path($report_file) +end + +report("design rules: sg13g2_maximal | layout cell: " + active_cellname, report_file) + +deep + +$drc_error_count = 0 + +class DRC::DRCLayer + unless method_defined?(:original_output) + alias_method :original_output, :output + end + + def output(*args) + count = self.count() + $drc_error_count += count + puts("Rule %s: %d error(s)" % [args[0], count]) + original_output(*args) + end +end + +# Initial definitions of control flow variables +# Strings from the command line have to be converted +if defined? $offGrid + $offGrid = $offGrid.to_s.downcase == "true" +else + $offGrid = true +end +if defined? $filler + $filler = $filler.to_s.downcase == "true" +else + $filler = true +end +if defined? $density + $density = $density.to_s.downcase == "true" +else + $density = true +end +if defined? $noRecommendedRules + $noRecommendedRules = $noRecommendedRules.to_s.downcase == "true" +else + $noRecommendedRules = false +end +if defined? $sanityRules + $sanityRules = $sanityRules.to_s.downcase == "true" +else + $sanityRules = true +end + +class DRC::DRCEngine + def find_intersecting_edges_errors(dbu_value, + error_edge_pairs_90, + error_edge_pairs_180, + inverse_error_edge_pairs_90 = nil, + inverse_error_edge_pairs_180 = nil, + options = {}) + consider_intersecting_edges = options.fetch(:consider_intersecting_edges, false) + consider_touch_points = options.fetch(:consider_touch_points, false) + ignore_non_axis_aligned_edges = options.fetch(:ignore_non_axis_aligned_edges, false) + min_angle = options.fetch(:min_angle, 0) + max_angle = options.fetch(:max_angle, 90) + include_min_angle = options.fetch(:include_min_angle, true) + include_max_angle = options.fetch(:include_max_angle, false) + area_of_right_angle = dbu_value**2/2 + errors_ep = RBA::EdgePairs::new() + touch_point_errors_ep = RBA::EdgePairs::new() + intersecting_edges_errors_ep = RBA::EdgePairs::new() + intersecting_edges_error_candidates = Hash.new() + no_touch_point_error = Hash.new() + error_edge_pairs_90.data.each do |edge_pair| + ip = nil + if edge_pair.first.p1 == edge_pair.second.p1 or + edge_pair.first.p1 == edge_pair.second.p2 + ip = edge_pair.first.p1 + elsif edge_pair.first.p2 == edge_pair.second.p1 or + edge_pair.first.p2 == edge_pair.second.p2 + ip = edge_pair.first.p2 + else + ip = edge_pair.first.intersection_point(edge_pair.second) + end + if ip + intersecting_edges_error_candidates[ip] = edge_pair + if !edge_pair.first.is_degenerate? and !edge_pair.second.is_degenerate? + if (edge_pair.first.contains?(edge_pair.second.p1) and + edge_pair.first.contains?(edge_pair.second.p2)) or + (edge_pair.second.contains?(edge_pair.first.p1) and + edge_pair.second.contains?(edge_pair.first.p2)) + no_touch_point_error[ip] = true + end + end + end + end + if consider_intersecting_edges or consider_touch_points + touch_point_candidates = Hash.new() + touch_point_errors = Hash.new() + if inverse_error_edge_pairs_90 and inverse_error_edge_pairs_180 + (inverse_error_edge_pairs_90 + inverse_error_edge_pairs_180).data.each do |edge_pair| + ip = edge_pair.first.intersection_point(edge_pair.second) + if ip + if touch_point_candidates[ip] + touch_point_errors[ip] = true + touch_point_candidates.delete(ip) + elsif !no_touch_point_error[ip] + touch_point_candidates[ip] = edge_pair + end + end + end + end + touch_point_candidates = Hash.new() + (error_edge_pairs_90 + error_edge_pairs_180).data.each do |edge_pair| + ip = nil + if edge_pair.first.p1 == edge_pair.second.p1 or + edge_pair.first.p1 == edge_pair.second.p2 + ip = edge_pair.first.p1 + elsif edge_pair.first.p2 == edge_pair.second.p1 or + edge_pair.first.p2 == edge_pair.second.p2 + ip = edge_pair.first.p2 + end + if ip + if edge_pair.area == area_of_right_angle or max_angle == 180 + intersecting_edges_error_candidates[ip] = edge_pair + end + if touch_point_errors[ip] + touch_point_errors_ep.insert(edge_pair) + intersecting_edges_error_candidates.delete(ip) + elsif touch_point_candidates[ip] + touch_point_errors_ep.insert(edge_pair) + touch_point_errors_ep.insert(touch_point_candidates[ip]) + touch_point_candidates.delete(ip) + intersecting_edges_error_candidates.delete(ip) + elsif !no_touch_point_error[ip] + touch_point_candidates[ip] = edge_pair + end + end + end + if consider_intersecting_edges + intersecting_edges_errors_ep = RBA::EdgePairs::new(intersecting_edges_error_candidates.values) + if max_angle != 180 + intersecting_edges_errors_ep = intersecting_edges_errors_ep.with_internal_angle(min_angle, max_angle, false, include_min_angle, include_max_angle) + end + errors_ep = errors_ep + intersecting_edges_errors_ep + end + end + if ignore_non_axis_aligned_edges + errors_ep = errors_ep.with_angle_both(RBA::Edges::OrthoEdges, false) + end + if consider_touch_points + errors_ep = errors_ep + touch_point_errors_ep + end + return DRC::DRCLayer::new(self, errors_ep) + end +end + +class DRC::DRCLayer + def ext_and(other) + self_min_coherence_state = self.data.min_coherence? + other_min_coherence_state = other.data.min_coherence? + self.data.min_coherence = true + other.data.min_coherence = true + output_layer = self & other + self.data.min_coherence = self_min_coherence_state + other.data.min_coherence = other_min_coherence_state + return output_layer + end + + def ext_with_angle(constraint) + if self.polygons? + self_min_coherence_state = self.data.min_coherence? + self.data.min_coherence = true + self_edges = self.edges + self.data.min_coherence = self_min_coherence_state + else + self_edges = self + end + lower_bound = nil + upper_bound = nil + output_layer = nil + constraint.each do |expression| + relation = expression[0] + value = expression[1] + if relation == ">" + lower_bound = value + 1e-6 + elsif relation == "<" + upper_bound = value + elsif relation == "==" + output_layer = self_edges.with_angle(value) + if value > 0 and value < 90 + output_layer += self_edges.with_angle(-value) + end + elsif relation == "!=" + output_layer = self_edges.without_angle(value) + if value > 0 and value < 90 + output_layer += self_edges.without_angle(-value) + end + elsif relation == ">=" + lower_bound = value + elsif relation == "<=" + upper_bound = value + 1e-6 + else + raise "invalid expression" + end + end + if lower_bound or upper_bound + output_layer = self_edges.with_angle(lower_bound, upper_bound) + output_layer += self_edges.with_angle(-upper_bound, -lower_bound) + end + return output_layer + end + + def ext_with_area(constraint) + lower_bound = nil + upper_bound = nil + output_layer = nil + self_min_coherence_state = self.data.min_coherence? + self.data.min_coherence = true + constraint.each do |expression| + relation = expression[0] + value = expression[1] + if relation == ">" + lower_bound = value + 1e-6 + elsif relation == "<" + upper_bound = value + elsif relation == "==" + output_layer = self.with_area(value) + elsif relation == "!=" + output_layer = self.without_area(value) + elsif relation == ">=" + lower_bound = value + elsif relation == "<=" + upper_bound = value + 1e-6 + else + raise "invalid expression" + end + end + if lower_bound or upper_bound + output_layer = self.with_area(lower_bound, upper_bound) + end + self.data.min_coherence = self_min_coherence_state + return output_layer + end + + def ext_coincident_part(other, outside: false, inverted: false) + if outside and !inverted and self.polygons? and other.polygons? + return self.separation(other, 1).first_edges + end + if self.polygons? + self_min_coherence_state = self.data.min_coherence? + self.data.min_coherence = true + self_edges = self.edges + self.data.min_coherence = self_min_coherence_state + else + self_edges = self + end + if other.polygons? + other_min_coherence_state = other.data.min_coherence? + other.data.min_coherence = true + other_edges = other.edges + other.data.min_coherence = other_min_coherence_state + else + other_edges = other + end + if outside + if inverted + return self_edges.not(self_edges.separation(other_edges, 1).first_edges) + else + return self_edges.separation(other_edges, 1).first_edges + end + else + if inverted + return self_edges.not(other_edges) + else + return self_edges.and(other_edges) + end + end + end + + def ext_coincident_edges(other, outside: false, consider_touch_points: false) + if self.polygons? + self_min_coherence_state = self.data.min_coherence? + self.data.min_coherence = true + self_edges = self.edges + self.data.min_coherence = self_min_coherence_state + else + self_edges = self + end + if other.polygons? + other_min_coherence_state = other.data.min_coherence? + other.data.min_coherence = true + other_edges = other.edges + other.data.min_coherence = other_min_coherence_state + else + other_edges = other + end + if outside + if consider_touch_points + return self_edges.not_outside(self_edges.separation(other_edges, 1, @engine.whole_edges).first_edges) + else + return self_edges.not_outside(self_edges.separation(other_edges, 1, @engine.whole_edges, @engine.without_touching_corners).first_edges) + end + else + if consider_touch_points + raise "not implemented" + else + return met1_edges.not_outside(self_edges & other_edges) + end + end + end + + def ext_constraint_satisfied(value, constraint) + output_bool = true + constraint.each do |expression| + if expression[0] == ">" + output_bool = output_bool && (value > expression[1]) + elsif expression[0] == "<" + output_bool = output_bool && (value < expression[1]) + elsif expression[0] == "==" + output_bool = output_bool && (value == expression[1]) + elsif expression[0] == "!=" + output_bool = output_bool && (value != expression[1]) + elsif expression[0] == ">=" + output_bool = output_bool && (value >= expression[1]) + elsif expression[0] == "<=" + output_bool = output_bool && (value <= expression[1]) + else + raise "invalid expression" + end + end + return output_bool + end + + def ext_overlapping(other, constraint = []) + self_min_coherence_state = self.data.min_coherence? + other_min_coherence_state = other.data.min_coherence? + self.data.min_coherence = true + other.data.min_coherence = true + overlap_filter = @engine.overlapping(other.not_inside(self)) + constraint.each do |expression| + overlap_filter = overlap_filter.public_send(expression[0], expression[1]) + end + output_layer = self.drc(@engine.if_all(overlap_filter, ! @engine.inside(other))) + self.data.min_coherence = self_min_coherence_state + other.data.min_coherence = other_min_coherence_state + return output_layer + end + + def ext_covering(other) + self_min_coherence_state = self.data.min_coherence? + other_min_coherence_state = other.data.min_coherence? + self.data.min_coherence = true + other.data.min_coherence = true + output_layer = self.covering(other.inside(self)) + self.data.min_coherence = self_min_coherence_state + other.data.min_coherence = other_min_coherence_state + return output_layer + end + + def ext_fast_enclosed(other, value, polygon_output: false) + self_min_coherence_state = self.data.min_coherence? + other_min_coherence_state = other.data.min_coherence? + self.data.min_coherence = true + other.data.min_coherence = true + output_layer = self.enclosed(other, value, @engine.projection) + self.data.min_coherence = self_min_coherence_state + other.data.min_coherence = other_min_coherence_state + if polygon_output + return output_layer.polygons.merge(true, 0) + else + return output_layer + end + end + + def ext_extended(outside = 0, inside = 0) + if self.polygons? + self_min_coherence_state = self.data.min_coherence? + self.data.min_coherence = true + edge_layer = self.edges + self.data.min_coherence = self_min_coherence_state + else + edge_layer = self + end + return edge_layer.extended(:out => outside, :in => inside).merge(true, 0) + end + + def ext_extents + self_min_coherence_state = self.data.min_coherence? + self.data.min_coherence = true + output_layer = self.extents.merge(true, 0) + self.data.min_coherence = self_min_coherence_state + return output_layer + end + + def ext_separation_at_intersecting_edges(other, + value, + metric=RBA::Region::Euclidian, + consider_intersecting_edges=false, + consider_touch_points=false, + ignore_non_axis_aligned_edges=false, + min_angle=0, + max_angle=90, + include_min_angle=true, + include_max_angle=false, + polygons=false) + self_min_coherence_state = self.data.min_coherence? + other_min_coherence_state = other.data.min_coherence? + self.data.min_coherence = true + other.data.min_coherence = true + if metric.is_a?(DRC::DRCMetrics) + metric = metric.value + end + if value.is_a? Float + dbu_value = (value/1.dbu).round + else + dbu_value = value + end + error_edge_pairs_90 = DRC::DRCLayer::new(@engine, + self.data.separation_check(other.data, dbu_value, false, metric, 90, 1, nil)) + error_edge_pairs_180 = DRC::DRCLayer::new(@engine, + self.data.separation_check(other.data, dbu_value, false, metric, 180, nil, 1)) + width_error_edge_pairs_90 = DRC::DRCLayer::new(@engine, + self.data.width_check(dbu_value, false, metric, 90, 1, nil) + + other.data.width_check(dbu_value, false, metric, 90, 1, nil)) + width_error_edge_pairs_180 = DRC::DRCLayer::new(@engine, + self.data.width_check(dbu_value, false, metric, 180, nil, 1) + + other.data.width_check(dbu_value, false, metric, 180, nil, 1)) + separation_errors = @engine.find_intersecting_edges_errors( + dbu_value, + error_edge_pairs_90, + error_edge_pairs_180, + width_error_edge_pairs_90, + width_error_edge_pairs_180, + { + consider_intersecting_edges: consider_intersecting_edges, + consider_touch_points: consider_touch_points, + ignore_non_axis_aligned_edges: ignore_non_axis_aligned_edges, + min_angle: min_angle, + max_angle: max_angle, + include_min_angle: include_min_angle, + include_max_angle: include_max_angle + } + ) + self.data.min_coherence = self_min_coherence_state + other.data.min_coherence = other_min_coherence_state + if polygons + return separation_errors.polygons.merge(true, 0) + else + return separation_errors + end + end + + def ext_fast_separation(other, + value, + metric: @engine.euclidian, + consider_intersecting_edges: true, + consider_touch_points: true, + ignore_non_axis_aligned_edges: false, + min_angle: 0, + max_angle: 90, + include_min_angle: true, + include_max_angle: false, + polygon_output: false) + self_min_coherence_state = self.data.min_coherence? + other_min_coherence_state = other.data.min_coherence? + self.data.min_coherence = true + other.data.min_coherence = true + output_layer = self.separation(other, value, metric, @engine.angle_limit(max_angle)) + if !consider_intersecting_edges and !consider_touch_points + output_layer = output_layer.with_distance(1, nil) + if ignore_non_axis_aligned_edges + output_layer = output_layer.with_angle(@engine.ortho, @engine.both) + end + elsif consider_intersecting_edges ^ consider_touch_points + intersecting_edges_errors = output_layer.with_distance(0).edges + candidate_layer1 = self.interacting(intersecting_edges_errors) + candidate_layer2 = other.interacting(intersecting_edges_errors) + output_layer = output_layer.with_distance(1, nil) + output_layer = output_layer + candidate_layer1.ext_separation_at_intersecting_edges( + candidate_layer2, + value, + metric, + consider_intersecting_edges, + consider_touch_points, + ignore_non_axis_aligned_edges, + min_angle, + max_angle, + include_min_angle, + include_max_angle, + false) + end + self.data.min_coherence = self_min_coherence_state + other.data.min_coherence = other_min_coherence_state + if polygon_output + return output_layer.polygons.merge(true, 0) + else + return output_layer + end + end + + def ext_inside_part(other, inverted: false) + if self.polygons? + self_min_coherence_state = self.data.min_coherence? + self.data.min_coherence = true + edge_layer = self.edges + self.data.min_coherence = self_min_coherence_state + else + edge_layer = self + end + if inverted + return edge_layer.outside_part(other.merged(true, 0)) + else + return edge_layer.inside_part(other.merged(true, 0)) + end + end + + def ext_interacting(other, constraint=nil, inverted: false) + self_min_coherence_state = self.data.min_coherence? + other_min_coherence_state = other.data.min_coherence? + self.data.min_coherence = true + other.data.min_coherence = true + overlap_filter = @engine.secondary(other).overlapping(@engine.primary) + if not constraint + touch_filter = @engine.secondary(other).outside(@engine.primary).edges & @engine.primary + if inverted + output_layer = self.drc(@engine.if_none(overlap_filter, touch_filter)) + else + output_layer = self.drc(@engine.if_any(overlap_filter, touch_filter)) + end + else + touch_filter = (@engine.secondary(other).outside(@engine.primary).edges & @engine.primary).polygons(0.1.um).merged + filter = (overlap_filter + touch_filter).count + constraint.each do |expression| + filter = filter.public_send(expression[0], expression[1]) + end + if inverted + output_layer = self.drc(@engine.if_none(filter)) + else + output_layer = self.drc(@engine.if_any(filter)) + end + end + self.data.min_coherence = self_min_coherence_state + other.data.min_coherence = other_min_coherence_state + return output_layer + end + + def ext_overlap_at_intersecting_edges(other, + value, + metric=RBA::Region::Euclidian, + consider_intersecting_edges=false, + consider_touch_points=false, + ignore_non_axis_aligned_edges=false, + min_angle=0, + max_angle=90, + include_min_angle=true, + include_max_angle=false, + polygons=false) + self_min_coherence_state = self.data.min_coherence? + other_min_coherence_state = other.data.min_coherence? + self.data.min_coherence = true + other.data.min_coherence = true + if metric.is_a?(DRC::DRCMetrics) + metric = metric.value + end + if value.is_a? Float + dbu_value = (value/1.dbu).round + else + dbu_value = value + end + error_edge_pairs_90 = DRC::DRCLayer::new(@engine, + self.data.overlap_check(other.data, dbu_value, false, metric, 90, 1, nil)) + error_edge_pairs_180 = DRC::DRCLayer::new(@engine, + self.data.overlap_check(other.data, dbu_value, false, metric, 180, nil, 1)) + overlap_errors = @engine.find_intersecting_edges_errors( + dbu_value, + error_edge_pairs_90, + error_edge_pairs_180, + nil, + nil, + { + consider_intersecting_edges: consider_intersecting_edges, + consider_touch_points: consider_touch_points, + ignore_non_axis_aligned_edges: ignore_non_axis_aligned_edges, + min_angle: min_angle, + max_angle: max_angle, + include_min_angle: include_min_angle, + include_max_angle: include_max_angle + } + ) + self.data.min_coherence = self_min_coherence_state + other.data.min_coherence = other_min_coherence_state + if polygons + return overlap_errors.polygons.merge(true, 0) + else + return overlap_errors + end + end + + def ext_fast_overlap(other, + value, + metric: @engine.euclidian, + consider_intersecting_edges: true, + consider_touch_points: true, + ignore_non_axis_aligned_edges: false, + min_angle: 0, + max_angle: 90, + include_min_angle: true, + include_max_angle: false, + polygon_output: false) + if self.polygons? + self_min_coherence_state = self.data.min_coherence? + self.data.min_coherence = true + end + if other.polygons? + other_min_coherence_state = other.data.min_coherence? + other.data.min_coherence = true + end + if self.polygons? and other.polygons? + output_layer = self.overlap(other, value) + else + if self.polygons? + self_edges = self.edges + else + self_edges = self + end + if other.polygons? + other_edges = other.edges + else + other_edges = other + end + output_layer = self_edges.overlap(other_edges, value) + end + if !consider_intersecting_edges and !consider_touch_points + output_layer = output_layer.with_distance(1, nil) + if ignore_non_axis_aligned_edges + output_layer = output_layer.with_angle(@engine.ortho, @engine.both) + end + elsif consider_intersecting_edges ^ consider_touch_points + intersecting_edges_errors = output_layer.with_distance(0).edges + candidate_layer1 = self.interacting(intersecting_edges_errors) + candidate_layer2 = other.interacting(intersecting_edges_errors) + output_layer = output_layer.with_distance(1, nil) + output_layer = output_layer + candidate_layer1.ext_overlap_at_intersecting_edges( + candidate_layer2, + value, + metric, + consider_intersecting_edges, + consider_touch_points, + ignore_non_axis_aligned_edges, + min_angle, + max_angle, + include_min_angle, + include_max_angle, + false) + end + if self.polygons? + self.data.min_coherence = self_min_coherence_state + end + if other.polygons? + other.data.min_coherence = other_min_coherence_state + end + if polygon_output + return output_layer.polygons.merge(true, 0) + else + return output_layer + end + end + + def ext_with_coincident_edges(other) + coincident_edges = self.edges & other + return self.interacting(coincident_edges) + end + + def ext_with_length(constraint) + if self.polygons? + self_min_coherence_state = self.data.min_coherence? + self.data.min_coherence = true + edge_layer = self.edges + self.data.min_coherence = self_min_coherence_state + else + edge_layer = self.dup + end + constraint.each do |expression| + if expression[0] == ">" + edge_layer = edge_layer.with_length((expression[1] + 1), nil) + elsif expression[0] == "<" + edge_layer = edge_layer.with_length(nil, expression[1]) + elsif expression[0] == "==" + edge_layer = edge_layer.with_length(expression[1]) + elsif expression[0] == "!=" + edge_layer = edge_layer.without_length(expression[1]) + elsif expression[0] == ">=" + edge_layer = edge_layer.with_length(expression[1], nil) + elsif expression[0] == "<=" + edge_layer = edge_layer.with_length(nil, (expression[1] + 1)) + else + raise "invalid expression" + end + end + return edge_layer + end + + def ext_not(other) + self_min_coherence_state = self.data.min_coherence? + other_min_coherence_state = other.data.min_coherence? + self.data.min_coherence = true + other.data.min_coherence = true + output_layer = self - other + self.data.min_coherence = self_min_coherence_state + other.data.min_coherence = other_min_coherence_state + return output_layer + end + + def ext_or(other, *further_layers) + self_min_coherence_state = self.data.min_coherence? + other_min_coherence_state = other.data.min_coherence? + self.data.min_coherence = true + other.data.min_coherence = true + output_layer = self.join(other) + further_layers.each do |further_layer| + further_layer_min_coherence_state = further_layer.data.min_coherence? + further_layer.data.min_coherence = true + output_layer = output_layer.join(further_layer) + further_layer.data.min_coherence = further_layer_min_coherence_state + end + self.data.min_coherence = self_min_coherence_state + other.data.min_coherence = other_min_coherence_state + return output_layer + end + + def ext_rectangles(axis_aligned = false, use_bbox = false, constraint1 = nil, constraint2 = nil, aspect_ratio_constraint = nil, inverted: false) + self_min_coherence_state = self.data.min_coherence? + self.data.min_coherence = true + if ( ( constraint1 && ( !constraint2 || constraint1.length() > 1 || constraint1[0][0] != "==") ) || + ( constraint2 && ( constraint2.length() > 1 || constraint2[0][0] != "==" ) ) || + ( constraint1 && constraint2 && constraint1[0][1] != constraint2[0][1] ) ) + raise "ext_rectangle: unsupported options" + end + square = constraint1 ? true : false + shape_filter = + if use_bbox + @engine.extents + elsif axis_aligned + @engine.rectangles + else + @engine.if_all((@engine.corners == 270).count == 4, @engine.corners.count == 4) + end + if square + if use_bbox + shape_filter = @engine.if_all((@engine.extents.length == constraint1[0][1]).count == 4) + else + square_filter = (@engine.length == constraint1[0][1]).count == 4 + shape_filter = @engine.if_all(shape_filter, square_filter) + end + end + if inverted + output_layer = self.drc(! shape_filter) + else + output_layer = self.drc(shape_filter) + end + self.data.min_coherence = self_min_coherence_state + return output_layer + end + + def ext_space_at_intersecting_edges(value, + metric=RBA::Region::Euclidian, + consider_intersecting_edges=false, + consider_touch_points=false, + ignore_non_axis_aligned_edges=false, + min_angle=0, + max_angle=90, + include_min_angle=true, + include_max_angle=false, + polygons=false) + self_min_coherence_state = self.data.min_coherence? + self.data.min_coherence = true + if metric.is_a?(DRC::DRCMetrics) + metric = metric.value + end + if value.is_a? Float + dbu_value = (value/1.dbu).round + else + dbu_value = value + end + error_edge_pairs_90 = DRC::DRCLayer::new(@engine, self.data.space_check(dbu_value, false, metric, 90, 1, nil)) + error_edge_pairs_180 = DRC::DRCLayer::new(@engine, self.data.space_check(dbu_value, false, metric, 180, nil, 1)) + width_error_edge_pairs_90 = DRC::DRCLayer::new(@engine, self.data.width_check(dbu_value, false, metric, 90, 1, nil)) + width_error_edge_pairs_180 = DRC::DRCLayer::new(@engine, self.data.width_check(dbu_value, false, metric, 180, nil, 1)) + space_errors = @engine.find_intersecting_edges_errors( + dbu_value, + error_edge_pairs_90, + error_edge_pairs_180, + width_error_edge_pairs_90, + width_error_edge_pairs_180, + { + consider_intersecting_edges: consider_intersecting_edges, + consider_touch_points: consider_touch_points, + ignore_non_axis_aligned_edges: ignore_non_axis_aligned_edges, + min_angle: min_angle, + max_angle: max_angle, + include_min_angle: include_min_angle, + include_max_angle: include_max_angle + } + ) + self.data.min_coherence = self_min_coherence_state + if polygons + return space_errors.polygons.merge(true, 0) + else + return space_errors + end + end + + def ext_fast_space(value, + metric: @engine.euclidian, + consider_intersecting_edges: true, + consider_touch_points: true, + ignore_non_axis_aligned_edges: false, + min_angle: 0, + max_angle: 90, + include_min_angle: true, + include_max_angle: false, + polygon_output: false) + self_min_coherence_state = self.data.min_coherence? + self.data.min_coherence = true + output_layer = self.space(value, metric, @engine.angle_limit(max_angle)) + if !consider_intersecting_edges and !consider_touch_points + output_layer = output_layer.with_distance(1, nil) + if ignore_non_axis_aligned_edges + output_layer = output_layer.with_angle(@engine.ortho, @engine.both) + end + elsif consider_intersecting_edges ^ consider_touch_points + candidate_layer = self.interacting(output_layer.with_distance(0).edges) + output_layer = output_layer.with_distance(1, nil) + output_layer = output_layer + candidate_layer.ext_space_at_intersecting_edges( + value, + metric, + consider_intersecting_edges, + consider_touch_points, + ignore_non_axis_aligned_edges, + min_angle, + max_angle, + include_min_angle, + include_max_angle, + false) + end + self.data.min_coherence = self_min_coherence_state + if polygon_output + return output_layer.polygons.merge(true, 0) + else + return output_layer + end + end + + def ext_width_at_intersecting_edges(value, + metric=RBA::Region::Euclidian, + consider_intersecting_edges=false, + consider_touch_points=false, + ignore_non_axis_aligned_edges=false, + min_angle=0, + max_angle=90, + include_min_angle=true, + include_max_angle=false, + polygons=false) + self_min_coherence_state = self.data.min_coherence? + self.data.min_coherence = true + if metric.is_a?(DRC::DRCMetrics) + metric = metric.value + end + if value.is_a? Float + dbu_value = (value/1.dbu).round + else + dbu_value = value + end + error_edge_pairs_90 = DRC::DRCLayer::new(@engine, self.data.width_check(dbu_value, false, metric, 90, 1, nil)) + error_edge_pairs_180 = DRC::DRCLayer::new(@engine, self.data.width_check(dbu_value, false, metric, 180, nil, 1)) + space_error_edge_pairs_90 = DRC::DRCLayer::new(@engine, self.data.space_check(dbu_value, false, metric, 90, 1, nil)) + space_error_edge_pairs_180 = DRC::DRCLayer::new(@engine, self.data.space_check(dbu_value, false, metric, 180, nil, 1)) + width_errors = @engine.find_intersecting_edges_errors( + dbu_value, + error_edge_pairs_90, + error_edge_pairs_180, + space_error_edge_pairs_90, + space_error_edge_pairs_180, + { + consider_intersecting_edges: consider_intersecting_edges, + consider_touch_points: consider_touch_points, + ignore_non_axis_aligned_edges: ignore_non_axis_aligned_edges, + min_angle: min_angle, + max_angle: max_angle, + include_min_angle: include_min_angle, + include_max_angle: include_max_angle + } + ) + self.data.min_coherence = self_min_coherence_state + if polygons + return width_errors.polygons.merge(true, 0) + else + return width_errors + end + end + + def ext_fast_width(value, + metric: @engine.euclidian, + consider_intersecting_edges: true, + consider_touch_points: true, + ignore_non_axis_aligned_edges: false, + min_angle: 0, + max_angle: 90, + include_min_angle: true, + include_max_angle: false, + polygon_output: false) + if self.polygons? + self_min_coherence_state = self.data.min_coherence? + self.data.min_coherence = true + self_edges = self.edges + self.data.min_coherence = self_min_coherence_state + else + self_edges = self + end + output_layer = self_edges.width(value, metric, @engine.angle_limit(max_angle)) + if !consider_intersecting_edges and !consider_touch_points + output_layer = output_layer.with_distance(1, nil) + if ignore_non_axis_aligned_edges + output_layer = output_layer.with_angle(@engine.ortho, @engine.both) + end + elsif consider_intersecting_edges ^ consider_touch_points + candidate_layer = self.interacting(output_layer.with_distance(0).edges) + output_layer = output_layer.with_distance(1, nil) + output_layer = output_layer + candidate_layer.ext_width_at_intersecting_edges( + value, + metric, + consider_intersecting_edges, + consider_touch_points, + ignore_non_axis_aligned_edges, + min_angle, + max_angle, + include_min_angle, + include_max_angle, + false) + end + if polygon_output + return output_layer.polygons.merge(true, 0) + else + return output_layer + end + end + + def ext_enlarge_inside(other, distance, step) + enlarged_layer = self.dup + num_steps = (distance / step + 0.5).to_i + for i in 1..num_steps + enlarged_layer = enlarged_layer.sized(step, @engine.acute_limit) & other + end + rest = distance - num_steps * step + if rest > 1.dbu + enlarged_layer = enlarged_layer.sized(rest, @engine.acute_limit) & other + end + return enlarged_layer + end + + def ext_touching(other, constraint = [[">", 0]]) + self_min_coherence_state = self.data.min_coherence? + other_min_coherence_state = other.data.min_coherence? + self.data.min_coherence = true + other.data.min_coherence = true + outside_filter = @engine.outside(other) + touch_filter = @engine.primary.edges & @engine.secondary(other) + if constraint + touch_filter = touch_filter.count + constraint.each do |expression| + touch_filter = touch_filter.public_send(expression[0], expression[1]) + end + end + output_layer = self.drc(@engine.if_all(outside_filter, touch_filter)) + self.data.min_coherence = self_min_coherence_state + other.data.min_coherence = other_min_coherence_state + return output_layer + end + + def ext_interacting_with_text(text_layer, text) + if text_layer.is_a? Integer + text_layer = @engine.labels(text_layer) + end + initial_merged_semantics = self.data.merged_semantics? + self.data.merged_semantics = false + result = self.interacting(text_layer.texts(text)) + self.data.merged_semantics = initial_merged_semantics + return result + end + + def ext_with_density(range, *args) + if self.is_empty? + return DRC::DRCLayer::new(@engine, RBA::Region::new()) + end + if self.is_merged? + merged_layer = self + else + merged_layer = self.merged(true, 0) + end + origin = 'cc' + tile_size = nil + tile_step = nil + arguments = [range] + args.each do |a| + if a.is_a?(DRC::DRCTileSize) + tile_size = a + arguments.push(tile_size) + elsif a.is_a?(DRC::DRCTileStep) + tile_step = a + arguments.push(tile_step) + elsif a.is_a?(String) + origin = a + else + raise "argument error" + end + end + bbox = @engine.extent.bbox + if origin == 'll' + origin_x = bbox.left + origin_y = bbox.bottom + if tile_size and tile_step and (tile_size.get[0] != tile_step.get[0] or tile_size.get[1] != tile_step.get[1]) + origin_x = bbox.left + tile_step.get[0]/2 + origin_y = bbox.bottom + tile_step.get[1]/2 + end + tile_origin = DRC::DRCTileOrigin::new(origin_x, origin_y) + arguments.push(tile_origin) + elsif origin != 'cc' + raise "Unknown origin: 'cc' or 'll' expected" + end + if tile_size + boundary_layer = DRC::DRCLayer::new(@engine, RBA::Region::new(bbox.to_itype(@engine.dbu))) + tile_boundary = DRC::DRCTileBoundary::new(boundary_layer) + return merged_layer.with_density(*arguments, tile_boundary, @engine.padding_ignore) + else + tile_size = DRC::DRCTileSize::new(bbox.width, bbox.height) + tile_count = DRC::DRCTileCount::new(1,2) + enlarged_bbox = bbox.enlarged(1.1).to_itype(@engine.dbu) + boundary_layer = DRC::DRCLayer::new(@engine, RBA::Region::new(enlarged_bbox)) + tile_boundary = DRC::DRCTileBoundary::new(boundary_layer) + result = merged_layer.with_density(*arguments, tile_size, tile_count, tile_boundary, @engine.padding_ignore) + return result.raw.overlapping(DRC::DRCLayer::new(@engine, RBA::Region::new(bbox.to_itype(@engine.dbu)))) + end + end +end + +Activ = source.polygons("1/0") +Activ_pin = source.polygons("1/2") +Activ_mask = source.polygons("1/20") +Activ_filler = source.polygons("1/22") +Activ_nofill = source.polygons("1/23") +BiWind = source.polygons("3/0") +GatPoly = source.polygons("5/0") +GatPoly_pin = source.polygons("5/2") +GatPoly_filler = source.polygons("5/22") +GatPoly_nofill = source.polygons("5/23") +Cont = source.polygons("6/0") +nSD = source.polygons("7/0") +nSD_block = source.polygons("7/21") +Metal1 = source.polygons("8/0") +Metal1_pin = source.polygons("8/2") +Metal1_filler = source.polygons("8/22") +Metal1_nofill = source.polygons("8/23") +Metal1_slit = source.polygons("8/24") +Passiv = source.polygons("9/0") +Metal2 = source.polygons("10/0") +Metal2_pin = source.polygons("10/2") +Metal2_filler = source.polygons("10/22") +Metal2_nofill = source.polygons("10/23") +Metal2_slit = source.polygons("10/24") +BasPoly = source.polygons("13/0") +pSD = source.polygons("14/0") +DigiBnd = source.polygons("16/0") +Via1 = source.polygons("19/0") +RES = source.polygons("24/0") +SRAM = source.polygons("25/0") +TRANS = source.polygons("26/0") +IND = source.polygons("27/0") +SalBlock = source.polygons("28/0") +Via2 = source.polygons("29/0") +Metal3 = source.polygons("30/0") +Metal3_pin = source.polygons("30/2") +Metal3_filler = source.polygons("30/22") +Metal3_nofill = source.polygons("30/23") +Metal3_slit = source.polygons("30/24") +NWell = source.polygons("31/0") +NWell_pin = source.polygons("31/2") +nBuLay = source.polygons("32/0") +nBuLay_block = source.polygons("32/21") +EmWind = source.polygons("33/0") +DeepCo = source.polygons("35/0") +MIM = source.polygons("36/0") +EdgeSeal = source.polygons("39/0") +dfpad = source.polygons("41/0") +dfpad_pillar = source.polygons("41/35") +dfpad_sbump = source.polygons("41/36") +ThickGateOx = source.polygons("44/0") +PWell = source.polygons("46/0") +PWell_block = source.polygons("46/21") +Via3 = source.polygons("49/0") +Metal4 = source.polygons("50/0") +Metal4_pin = source.polygons("50/2") +Metal4_filler = source.polygons("50/22") +Metal4_nofill = source.polygons("50/23") +Metal4_slit = source.polygons("50/24") +EmPoly = source.polygons("55/0") +DigiSub = source.polygons("60/0") +TEXT_0 = source.labels("63/0") +Via4 = source.polygons("66/0") +Metal5 = source.polygons("67/0") +Metal5_pin = source.polygons("67/2") +Metal5_filler = source.polygons("67/22") +Metal5_nofill = source.polygons("67/23") +Metal5_slit = source.polygons("67/24") +Polimide = source.polygons("98/0") +Recog = source.polygons("99/0") +Recog_esd = source.polygons("99/30") +Recog_diode = source.polygons("99/31") +Recog_tsv = source.polygons("99/32") +EXTBlock = source.polygons("111/0") +TopVia1 = source.polygons("125/0") +TopMetal1 = source.polygons("126/0") +TopMetal1_pin = source.polygons("126/2") +TopMetal1_filler = source.polygons("126/22") +TopMetal1_nofill = source.polygons("126/23") +TopMetal1_slit = source.polygons("126/24") +PolyRes = source.polygons("128/0") +Vmim = source.polygons("129/0") +TopVia2 = source.polygons("133/0") +TopMetal2 = source.polygons("134/0") +TopMetal2_pin = source.polygons("134/2") +TopMetal2_filler = source.polygons("134/22") +TopMetal2_nofill = source.polygons("134/23") +TopMetal2_slit = source.polygons("134/24") +ColWind = source.polygons("139/0") +RFMEM = source.polygons("147/0") +DeepVia = source.polygons("152/0") +LBE = source.polygons("157/0") +NoMetFiller = source.polygons("160/0") + +if $sanityRules + PEmWind = source.polygons("11/0") + PEmPoly = source.polygons("53/0") + LDMOS = source.polygons("57/0") + PBiWind = source.polygons("58/0") + Flash = source.polygons("71/0") +end + +Activ_Act_a = Activ.ext_fast_width(0.15.um) +Activ_Act_d = Activ.ext_with_area([["<", 0.122.um2]]) +nmosi_relevant_activ = Activ.ext_or(Activ_mask) +Act_density = Activ.ext_or(Activ_filler) +GP_or_Act = Activ.ext_or(GatPoly) +Gate = Activ.ext_and(GatPoly) +Act_connect = Activ.ext_not(GatPoly) +GatPoly_Gat_e = GatPoly.ext_with_area([["<", 0.09.um2]]) +Gat_density = GatPoly.ext_or(GatPoly_filler) +Cont_SQ = Cont.ext_rectangles(true, false, [["==", 0.16.um]], [["==", 0.16.um]], nil) +ContBar = Cont.ext_with_area([[">", (0.16*0.16).um2]]) +Activ_and_nSD_block = Activ.ext_and(nSD_block) +selring_pass = Passiv.with_holes +Passiv_Pad_a1 = Passiv.drc((width(projection) > 150.0.um).polygons) +X2 = nSD_block.ext_or(pSD) +pSD_not_nSD = nSD.ext_not(pSD) +subst_tie_hole = (pSD.holes - pSD.with_holes).without_holes +pSD_pSD_a = pSD.ext_fast_width(0.31.um) +pSD_pSD_k = pSD.ext_with_area([["<", 0.25.um2]]) +Act_Nsram = Activ.ext_not(SRAM) +pSD_Nsram = pSD.ext_not(SRAM) +GP_Nsram = GatPoly.ext_not(SRAM) +Cont_Nsram = Cont.ext_not(SRAM) +V1_Nsram = Via1.ext_not(SRAM) +M1_Nsram = Metal1.ext_not(SRAM) +M2_Nsram = Metal2.ext_not(SRAM) +M2_SRAM = Metal2.ext_and(SRAM) +V2_Nsram = Via2.ext_not(SRAM) +M3_Nsram = Metal3.ext_not(SRAM) +M3_SRAM = Metal3.ext_and(SRAM) +Act_NWell = Activ.ext_and(NWell) +NWell_NW_a = NWell.ext_fast_width(0.62.um) +NWell_nBuLay = NWell.ext_and(nBuLay) +isoPWell = nBuLay.ext_not(NWell) +nBuLay_block_NBLB_a = nBuLay_block.ext_fast_width(1.5.um) +nBuLay_nBuLay_block_enc_tmp = nBuLay_block.ext_fast_enclosed(nBuLay, 1.0.um, polygon_output: true) +nBuLay_nBuLay_block_enc_tmp2 = nBuLay_block.ext_overlapping(nBuLay) +MIM_Mim_a = MIM.ext_fast_width(1.14.um, consider_intersecting_edges: false, polygon_output: true) +MIM_Mim_f = MIM.ext_with_area([["<", 1.3.um2]]) +sealring = EdgeSeal.with_holes +Act_EdgeSeal = Activ.ext_and(EdgeSeal) +Act_Not_EdgeSeal = Activ.ext_not(EdgeSeal) +pSD_edgA1_in = pSD.ext_and(EdgeSeal) +Metal1_edgA1_in = Metal1.ext_and(EdgeSeal) +Metal2_edgA1_in = Metal2.ext_and(EdgeSeal) +Metal3_edgA1_in = Metal3.ext_and(EdgeSeal) +Cont_edgC1_in = Cont.ext_and(EdgeSeal) +Via1_edgC1_in = Via1.ext_and(EdgeSeal) +Via1_edgC1_out = Via1.ext_not(EdgeSeal) +Via2_edgC1_in = Via2.ext_and(EdgeSeal) +Via2_edgC1_out = Via2.ext_not(EdgeSeal) +Cont_outside_EdgeSeal = Cont.outside(EdgeSeal) +Metal1_outside_EdgeSeal = Metal1.outside(EdgeSeal) +Metal2_outside_EdgeSeal = Metal2.outside(EdgeSeal) +Metal3_outside_EdgeSeal = Metal3.outside(EdgeSeal) +Passiv_dfpad = Passiv.ext_and(dfpad) +pad = dfpad.not_outside(Passiv) +cupPad_candidat = Passiv.ext_and(dfpad_pillar) +dfpad_all = dfpad.ext_or(dfpad_pillar, dfpad_sbump) +ThickGateOx_TGO_e = ThickGateOx.ext_fast_space(0.86.um, consider_intersecting_edges: false, polygon_output: true) +ThickGateOx_TGO_f = ThickGateOx.ext_fast_width(0.86.um, consider_intersecting_edges: false, polygon_output: true) +X1 = NWell.ext_or(PWell_block) +PWell_block_PWB_a = PWell_block.ext_fast_width(0.62.um) +PWell_block_PWB_b = PWell_block.ext_fast_space(0.62.um, consider_intersecting_edges: false, polygon_output: true) +V3_Nsram = Via3.ext_not(SRAM) +Via3_edgC1_in = Via3.ext_and(EdgeSeal) +Via3_edgC1_out = Via3.ext_not(EdgeSeal) +M4_Nsram = Metal4.ext_not(SRAM) +M4_SRAM = Metal4.ext_and(SRAM) +Metal4_edgA1_in = Metal4.ext_and(EdgeSeal) +Metal4_outside_EdgeSeal = Metal4.outside(EdgeSeal) +V4_Nsram = Via4.ext_not(SRAM) +Via4_edgC1_in = Via4.ext_and(EdgeSeal) +Via4_edgC1_out = Via4.ext_not(EdgeSeal) +M5_Nsram = Metal5.ext_not(SRAM) +M5_SRAM = Metal5.ext_and(SRAM) +belowTopMetaln_dfpad = Metal5.ext_and(dfpad) +Metal5_edgA1_in = Metal5.ext_and(EdgeSeal) +Metal5_outside_EdgeSeal = Metal5.outside(EdgeSeal) +Metal5_slit_MIM_Slt_g_M5_sep_tmp1 = Metal5_slit.ext_fast_separation(MIM, 0.6.um, consider_intersecting_edges: false, consider_touch_points: false, polygon_output: true) +Metal5_slit_MIM_Slt_g_M5_sep_tmp2 = MIM.ext_coincident_edges(Metal5_slit, outside: true, consider_touch_points: true) +Metal5_slit_MIM_Slt_g_M5_sep_tmp5 = Metal5_slit.ext_and(MIM) +scr1 = Recog_esd.ext_interacting_with_text(TEXT_0, "scr1") +nmoscl_2 = Recog_esd.ext_interacting_with_text(TEXT_0, "nmoscl_2") +nmoscl_4 = Recog_esd.ext_interacting_with_text(TEXT_0, "nmoscl_4") +Rhigh_recognition_0 = EXTBlock.ext_and(pSD) +TopVia1_edgC1_in = TopVia1.ext_and(EdgeSeal) +TopVia1_edgC1_out = TopVia1.ext_not(EdgeSeal) +TopMetal1_edgA1_in = TopMetal1.ext_and(EdgeSeal) +TopMetal1_slit_MIM_Slt_g_TM1_sep_tmp1 = TopMetal1_slit.ext_fast_separation(MIM, 0.6.um, consider_intersecting_edges: false, consider_touch_points: false, polygon_output: true) +TopMetal1_slit_MIM_Slt_g_TM1_sep_tmp2 = MIM.ext_coincident_edges(TopMetal1_slit, outside: true, consider_touch_points: true) +TopMetal1_slit_MIM_Slt_g_TM1_sep_tmp5 = TopMetal1_slit.ext_and(MIM) +GatPoly_res = GatPoly.ext_or(PolyRes) +TopVia1_or_Vmim = TopVia1.ext_or(Vmim) +TopVia2_edgC1_in = TopVia2.ext_and(EdgeSeal) +TopVia2_edgC1_out = TopVia2.ext_not(EdgeSeal) +TopMetal2_edgA1_in = TopMetal2.ext_and(EdgeSeal) +holes_TopMetal2 = TopMetal2.holes.merge +tsv_tmp2 = (DeepVia.holes - DeepVia.with_holes).without_holes.outside(DeepVia) +bad_tsv = DeepVia.without_holes +M1_density = Metal1.ext_or(Metal1_filler).ext_not(Metal1_slit) +M2_density = Metal2.ext_or(Metal2_filler).ext_not(Metal2_slit) +DigiBnd_ring = DigiBnd.sized(0.01.um, acute_limit).ext_not(DigiBnd) +emi2Pin = Metal2_pin.ext_and(TRANS).ext_interacting_with_text(TEXT_0, "E") +M3_density = Metal3.ext_or(Metal3_filler).ext_not(Metal3_slit) +nBuLayGen_sized = NWell.sized((-1+1.to_f/2).um, acute_limit).sized((1.to_f/2).um, acute_limit) +Act_out_ThickGateOx = Activ.ext_not(Activ.ext_interacting(ThickGateOx)) +PWellBlock_relatedNWell_0 = NWell.not_inside(PWell_block).ext_interacting(PWell_block) +M4_density = Metal4.ext_or(Metal4_filler).ext_not(Metal4_slit) +M5_density = Metal5.ext_or(Metal5_filler).ext_not(Metal5_slit) +SalBlock_not_nSDBlock_not_esd = SalBlock.ext_not(Recog_esd.ext_or(nSD_block)) +TM1_density = TopMetal1.ext_or(TopMetal1_filler).ext_not(TopMetal1_slit) +TM2_density = TopMetal2.ext_or(TopMetal2_filler).ext_not(TopMetal2_slit) +GP_mosHV = Gate.not_outside(ThickGateOx) +GP_out_ThickGateOx = Gate.outside(ThickGateOx) +size_Cont = Cont.ext_enlarge_inside(Act_connect, 6.0.um, 0.21.um) +Cont_Act = Cont_SQ.ext_and(Activ) +Cont_not_M1 = Cont_SQ.ext_not(Metal1) +Cont_Act_GP = Cont_SQ.ext_and(Gate) +CntB_a1_error = ContBar.ext_with_area([["<", (0.16*0.34).um2]]) +ContBar_GP = ContBar.ext_and(GatPoly) +ContBar_Act = ContBar.ext_and(Activ) +ContBar_not_M1 = ContBar.ext_not(Metal1) +ContBar_Act_GP = ContBar.ext_and(Gate) +ContBar_outside_TRANS = ContBar.outside(TRANS) +dschottky_1 = Activ_and_nSD_block.ext_and(nBuLay) +dpin_0 = BasPoly.ext_and(Activ).ext_and(BiWind).ext_and(nSD_block) +nSD_not_pSD = pSD_not_nSD.dup +subst_tie_hole_w_npn = subst_tie_hole.ext_interacting_with_text(TEXT_0, "npn*") +pSDL_enc_area = subst_tie_hole.ext_not(pSD) +Act_SRAM = Activ.ext_not(Act_Nsram) +pSD_SRAM = pSD.ext_not(pSD_Nsram) +pSDHV_Nsram = pSD_Nsram.inside(ThickGateOx) +GP_SRAM = GatPoly.ext_not(GP_Nsram) +GP_Nsram_Gat_a = GP_Nsram.ext_fast_width(0.13.um, consider_intersecting_edges: false, polygon_output: true) +GP_Nsram_Gat_b = GP_Nsram.ext_fast_space(0.18.um, consider_intersecting_edges: false, polygon_output: true) +Cont_SRAM = Cont.ext_not(Cont_Nsram) +V1_SRAM = Via1.ext_not(V1_Nsram) +V1_Nsram_outside_EdgeSeal = V1_Nsram.outside(EdgeSeal) +M1_SRAM = Metal1.ext_not(M1_Nsram) +npnMPA_0 = nBuLay.ext_and(Activ.ext_and(SalBlock.ext_and(nSD_block))) +V2_SRAM = Via2.ext_not(V2_Nsram) +V2_Nsram_outside_EdgeSeal = V2_Nsram.outside(EdgeSeal) +nBuLay_nBuLay_block_enc_tmp3 = nBuLay_nBuLay_block_enc_tmp + nBuLay_nBuLay_block_enc_tmp2 +Act_EdgeSeal_not_HRACT = Act_EdgeSeal.ext_not(Recog) +Activ_edgA1_in = Act_EdgeSeal.dup +Metal1_slit_not_pad = Metal1_slit.ext_not(pad) +Metal2_slit_not_pad = Metal2_slit.ext_not(pad) +Metal3_slit_not_pad = Metal3_slit.ext_not(pad) +Metal4_slit_not_pad = Metal4_slit.ext_not(pad) +Metal5_slit_not_pad = Metal5_slit.ext_not(pad) +TopMetal1_slit_not_pad = TopMetal1_slit.ext_not(pad) +TopMetal2_slit_not_pad = TopMetal2_slit.ext_not(pad) +Recog_or_dfpad_all = Recog.ext_or(dfpad_all) +Recog_or_MIM_or_dfpad_all = MIM.ext_or(Recog, dfpad_all) +Iso_PWell_Act = Activ.ext_and(nBuLay).ext_not(X1) +V3_SRAM = Via3.ext_not(V3_Nsram) +V3_Nsram_outside_EdgeSeal = V3_Nsram.outside(EdgeSeal) +V4_SRAM = Via4.ext_not(V4_Nsram) +V4_Nsram_outside_EdgeSeal = V4_Nsram.outside(EdgeSeal) +cmim_a = MIM.not_outside(Metal5).not_outside(TopMetal1).not_outside(Vmim) +Metal5_slit_MIM_Slt_g_M5_sep_tmp3 = Metal5_slit.ext_with_coincident_edges(Metal5_slit_MIM_Slt_g_M5_sep_tmp2) +nmoscl = nmoscl_2.ext_or(nmoscl_4) +Rhigh_recognition_1 = Rhigh_recognition_0.ext_and(nSD) +TopMetal1_slit_MIM_Slt_g_TM1_sep_tmp3 = TopMetal1_slit.ext_with_coincident_edges(TopMetal1_slit_MIM_Slt_g_TM1_sep_tmp2) +temp_layer_1 = MIM.ext_covering(TopVia1_or_Vmim) +temp_layer_6 = TopMetal2.ext_or(holes_TopMetal2) +tsv = DeepVia.with_holes.ext_not(bad_tsv) +Cont_not_Act_GP = Cont_SQ.ext_not(GP_or_Act).outside(TRANS) +ContBar_not_Act_GP = ContBar.ext_not(GP_or_Act).outside(TRANS) +nSD_drv = nSD.ext_or(Activ.ext_not(X2)) +X2_Extent = X2.ext_extents.sized(0.001.um, acute_limit) +transG2 = TRANS.ext_interacting_with_text(TEXT_0, "npn13G2").ext_covering(emi2Pin) +transG2C = TRANS.ext_interacting_with_text(TEXT_0, "npn13G2C").ext_covering(emi2Pin) +transG2L = TRANS.ext_interacting_with_text(TEXT_0, "npn13G2L").ext_covering(emi2Pin) +transG2V = TRANS.ext_interacting_with_text(TEXT_0, "npn13G2V").ext_covering(emi2Pin) +nBuLayGen = nBuLayGen_sized.ext_not(nBuLay_block) +ThickGateOx_Act_out_ThickGateOx_TGO_b_sep_tmp1 = ThickGateOx.ext_fast_separation(Act_out_ThickGateOx, 0.27.um, consider_intersecting_edges: false, consider_touch_points: false, polygon_output: true) +ThickGateOx_Act_out_ThickGateOx_TGO_b_sep_tmp2 = Act_out_ThickGateOx.ext_coincident_edges(ThickGateOx, outside: true, consider_touch_points: true) +ThickGateOx_Act_out_ThickGateOx_TGO_b_sep_tmp5 = ThickGateOx.ext_and(Act_out_ThickGateOx) +PWellBlock_relatedNWell = PWellBlock_relatedNWell_0.ext_or(NWell.inside(PWell_block)) +Rppd_0 = GatPoly_res.ext_and(pSD).ext_and(SalBlock_not_nSDBlock_not_esd) +tsv_fill = DeepVia.ext_or(tsv_tmp2).ext_not(bad_tsv) +GP_mosHV_Gat_b1 = GP_mosHV.ext_fast_space(0.25.um, consider_intersecting_edges: false, polygon_output: true) +ThickGateOx_GP_out_ThickGateOx_TGO_d_sep_tmp1 = ThickGateOx.ext_fast_separation(GP_out_ThickGateOx, 0.34.um, consider_intersecting_edges: false, consider_touch_points: false, polygon_output: true) +ThickGateOx_GP_out_ThickGateOx_TGO_d_sep_tmp2 = GP_out_ThickGateOx.ext_coincident_edges(ThickGateOx, outside: true, consider_touch_points: true) +ThickGateOx_GP_out_ThickGateOx_TGO_d_sep_tmp5 = ThickGateOx.ext_and(GP_out_ThickGateOx) +dschottky_2 = dschottky_1.sized(1.12.um, acute_limit) +seal_passiv = selring_pass.ext_interacting(selring_pass.holes.merge.not_outside(sealring)) +dpin_1 = dpin_0.sized(1.12.um, acute_limit) +pSD_not_nSD_or_nSD_not_pSD = nSD_not_pSD.ext_or(pSD_not_nSD) +pSDL_enc_area_pSD_l = pSDL_enc_area.ext_with_area([["<", 0.25.um2]]) +DigiBnd_hole = DigiBnd.ext_or(DigiBnd_ring.holes.merge) +GP_SRAM_Gat_a_SRAM = GP_SRAM.ext_fast_width(0.13.um, consider_intersecting_edges: false, polygon_output: true) +GP_SRAM_Gat_b_SRAM = GP_SRAM.ext_fast_space(0.149.um, consider_intersecting_edges: false, polygon_output: true) +V1_SRAM_outside_EdgeSeal = V1_SRAM.outside(EdgeSeal) +M1_SRAM_outside_EdgeSeal = M1_SRAM.outside(EdgeSeal) +npnMPA = npnMPA_0.ext_interacting_with_text(TEXT_0, "npnMPA") +V2_SRAM_outside_EdgeSeal = V2_SRAM.outside(EdgeSeal) +nBuLay_nBuLay_block_enc_tmp6 = nBuLay_nBuLay_block_enc_tmp3.dup +sltc_M1 = Metal1.ext_not(Recog_or_dfpad_all) +sltc_M2 = Metal2.ext_not(Recog_or_dfpad_all) +sltc_M3 = Metal3.ext_not(Recog_or_dfpad_all) +sltc_M4 = Metal4.ext_not(Recog_or_dfpad_all) +sltc_TM2 = TopMetal2.ext_not(Recog_or_dfpad_all) +sltc_M5 = Metal5.ext_not(Recog_or_MIM_or_dfpad_all) +sltc_TM1 = TopMetal1.ext_not(Recog_or_MIM_or_dfpad_all) +nSDBlock_Iso_PWell_Act = nSD_block.not_outside(Iso_PWell_Act) +SalBlock_Iso_PWell_Act = SalBlock.not_outside(Iso_PWell_Act) +V3_SRAM_outside_EdgeSeal = V3_SRAM.outside(EdgeSeal) +V4_SRAM_outside_EdgeSeal = V4_SRAM.outside(EdgeSeal) +rfcmim_a = cmim_a.not_outside(PWell_block.ext_interacting_with_text(TEXT_0, "rfcmim")) +Metal5_slit_MIM_Slt_g_M5_sep_tmp4 = Metal5_slit_MIM_Slt_g_M5_sep_tmp1 + Metal5_slit_MIM_Slt_g_M5_sep_tmp3 +Rhigh_recognition = Rhigh_recognition_1.ext_covering(GatPoly) +TopMetal1_slit_MIM_Slt_g_TM1_sep_tmp4 = TopMetal1_slit_MIM_Slt_g_TM1_sep_tmp1 + TopMetal1_slit_MIM_Slt_g_TM1_sep_tmp3 +Rsil_all = GatPoly_res.ext_and(RES).ext_and(EXTBlock).ext_interacting(SalBlock, inverted: true) +NAct = Activ.ext_and(nSD_drv) +pSD_nSD = pSD.ext_and(nSD_drv) +Y2 = X2_Extent.ext_not(X2) +emit_npn13G2 = EmWind.inside(transG2) +emit_npn13G2L = EmWind.inside(transG2L) +trans_bip = transG2.ext_or(transG2C, transG2L, transG2V) +emit_npn13G2V = EmWind.inside(transG2V) +nBuLayGen_nBuLay = nBuLay.ext_or(nBuLayGen) +schottky_nbl_rec = isoPWell.not_outside(SalBlock).not_outside(nSD_block).not_outside(Recog_diode).not_outside(ThickGateOx) +ThickGateOx_Act_out_ThickGateOx_TGO_b_sep_tmp3 = ThickGateOx.ext_with_coincident_edges(ThickGateOx_Act_out_ThickGateOx_TGO_b_sep_tmp2) +PWellBlock_unrelatedNWell = NWell.ext_not(PWellBlock_relatedNWell) +tsvOutRing = tsv_fill.ext_extents +tsv_fill_TSV_G_d = tsv_fill.ext_fast_space(25.0.um, consider_intersecting_edges: false, polygon_output: true) +ThickGateOx_GP_out_ThickGateOx_TGO_d_sep_tmp3 = ThickGateOx.ext_with_coincident_edges(ThickGateOx_GP_out_ThickGateOx_TGO_d_sep_tmp2) +dschottky_3 = dschottky_2.ext_and(PWell_block) +dpin = dpin_1.ext_and(PWell_block) +Rppd_all = Rppd_0.ext_interacting(Activ.ext_or(nSD_drv), inverted: true) +nBuLay_nBuLay_block_enc = nBuLay_nBuLay_block_enc_tmp6.dup +Metal5_slit_MIM_Slt_g_M5_sep_tmp6 = Metal5_slit_MIM_Slt_g_M5_sep_tmp4 + Metal5_slit_MIM_Slt_g_M5_sep_tmp5 +Rhigh_identical_nsd_psd_edge = pSD_not_nSD_or_nSD_not_pSD.ext_coincident_part(Rhigh_recognition, outside: true) +TopMetal1_slit_MIM_Slt_g_TM1_sep_tmp6 = TopMetal1_slit_MIM_Slt_g_TM1_sep_tmp4 + TopMetal1_slit_MIM_Slt_g_TM1_sep_tmp5 +rsil_gatpoly = GatPoly_res.not_outside(Rsil_all) +Rsil_all_not_interact_NWell = Rsil_all.ext_interacting(NWell, inverted: true) +NGate = Gate.not_outside(NAct) +PAct = Activ.ext_not(NAct) +PAct_connect = Act_connect.ext_not(NAct) +NActLV = NAct.ext_not(ThickGateOx) +NAct_NWell = NAct.ext_and(X1) +sal_nActiv = NAct.ext_not(SalBlock) +ContBar_NAct = ContBar.ext_and(NAct) +Cont_not_outside_NAct = Cont.not_outside(NAct) +nBuLayGen_nBuLay_NBL_a = nBuLayGen_nBuLay.ext_fast_width(1.0.um) +ThickGateOx_Act_out_ThickGateOx_TGO_b_sep_tmp4 = ThickGateOx_Act_out_ThickGateOx_TGO_b_sep_tmp1 + ThickGateOx_Act_out_ThickGateOx_TGO_b_sep_tmp3 +rfcmim = PWell_block.not_outside(rfcmim_a).sized(0.65.um, acute_limit) +PWell_block_tsvOutRing_enc_tmp = tsvOutRing.ext_fast_enclosed(PWell_block, 2.5.um, polygon_output: true) +PWell_block_tsvOutRing_enc_tmp2 = tsvOutRing.ext_overlapping(PWell_block) +Metal1_tsvOutRing_enc_tmp = tsvOutRing.ext_fast_enclosed(Metal1, 1.5.um, polygon_output: true) +Metal1_tsvOutRing_enc_tmp2 = tsvOutRing.ext_overlapping(Metal1) +ThickGateOx_GP_out_ThickGateOx_TGO_d_sep_tmp4 = ThickGateOx_GP_out_ThickGateOx_TGO_d_sep_tmp1 + ThickGateOx_GP_out_ThickGateOx_TGO_d_sep_tmp3 +dschottky = dschottky_3.ext_not(dpin) +SalBlock_Rppd = SalBlock.ext_and(Rppd_all) +Rppd_all_enclosure_pSD = Rppd_all.ext_fast_enclosed(pSD, 0.18.um, polygon_output: true) +Rhigh_a = GatPoly_res.ext_and(pSD_nSD).ext_and(SalBlock_not_nSDBlock_not_esd) +schottky_nbl1_nw = NWell.ext_interacting(NWell.holes.merge.ext_covering(schottky_nbl_rec)) +schottky_nw1_rect = NWell.not_outside(nSD_block).ext_interacting(schottky_nbl_rec, inverted: true).ext_and(Recog_diode) +Metal5_slit_MIM_Slt_g_M5_sep_tmp9 = Metal5_slit_MIM_Slt_g_M5_sep_tmp6.dup +Rhigh_identical_nsd_psd = pSD_not_nSD_or_nSD_not_pSD.ext_with_coincident_edges(Rhigh_identical_nsd_psd_edge) +TopMetal1_slit_MIM_Slt_g_TM1_sep_tmp9 = TopMetal1_slit_MIM_Slt_g_TM1_sep_tmp6.dup +Rsil = Rsil_all_not_interact_NWell.ext_interacting(nBuLay, inverted: true) +PGate = Gate.outside(NGate) +PAct_NWell = PAct.ext_and(X1) +ContBar_PAct = ContBar.ext_and(PAct) +Cont_not_outside_PAct = Cont.not_outside(PAct) +NActHV = NAct.ext_not(NActLV) +NAct_PWell = NAct.ext_not(NAct_NWell) +WellContDev = NAct_NWell.ext_interacting_with_text(TEXT_0, "well") +NAct_NWell_not_Gate = NAct_NWell.ext_not(Gate) +sal_nactive = sal_nActiv.dup +Rppd_Cont = EXTBlock.ext_covering(Rppd_all).ext_and(Cont) +n_tie = NWell.ext_and(Activ.ext_and(Y2)).ext_not(SalBlock) +ThickGateOx_Act_out_ThickGateOx_TGO_b_sep_tmp6 = ThickGateOx_Act_out_ThickGateOx_TGO_b_sep_tmp4 + ThickGateOx_Act_out_ThickGateOx_TGO_b_sep_tmp5 +PWell_block_tsvOutRing_enc_tmp3 = PWell_block_tsvOutRing_enc_tmp + PWell_block_tsvOutRing_enc_tmp2 +Metal1_tsvOutRing_enc_tmp3 = Metal1_tsvOutRing_enc_tmp + Metal1_tsvOutRing_enc_tmp2 +ThickGateOx_GP_out_ThickGateOx_TGO_d_sep_tmp6 = ThickGateOx_GP_out_ThickGateOx_TGO_d_sep_tmp4 + ThickGateOx_GP_out_ThickGateOx_TGO_d_sep_tmp5 +SVaricap_gate_0 = NGate.not_outside(NWell).not_outside(nBuLay) +GP_Rhigh_extended = GatPoly_res.ext_covering(Rhigh_a) +SalBlock_Rhigh = SalBlock.ext_and(Rhigh_a) +schottky_nbl1 = schottky_nbl1_nw.sized(1.36.um, acute_limit) +Metal5_slit_MIM_Slt_g_M5_sep_tmp11 = Metal5_slit_MIM_Slt_g_M5_sep_tmp9.dup +TopMetal1_slit_MIM_Slt_g_TM1_sep_tmp11 = TopMetal1_slit_MIM_Slt_g_TM1_sep_tmp9.dup +GP_Rsil_extended = GatPoly_res.ext_covering(Rsil) +PAct_PWell = PAct.ext_not(PAct_NWell) +Abut_NWell_Tie_Edge = NAct_NWell.ext_coincident_part(PAct_NWell, outside: true) +MVaricap = PWell_block.ext_and(NWell.sized(1.0.um, acute_limit)).not_outside(GatPoly).not_outside(nBuLay).not_outside(PAct).not_outside(NAct).ext_interacting_with_text(TEXT_0, "MVaricap") +NActHV_digi = NActHV.not_outside(DigiBnd_hole) +abut_tie_edge_NWell = NAct_NWell_not_Gate.ext_coincident_part(PAct_NWell, outside: true) +ntaparea = sal_nactive.ext_and(NWell) +Rhigh_Cont = EXTBlock.ext_covering(Rhigh_a).ext_and(Cont) +hard_n_tie = n_tie.ext_covering(Cont) +schottky_nw1_sized = schottky_nw1_rect.sized(1.36.um, acute_limit).ext_and(ThickGateOx) +ThickGateOx_Act_out_ThickGateOx_TGO_b_sep_tmp9 = ThickGateOx_Act_out_ThickGateOx_TGO_b_sep_tmp6.dup +PWell_block_tsvOutRing_enc_tmp6 = PWell_block_tsvOutRing_enc_tmp3.dup +Metal1_tsvOutRing_enc_tmp6 = Metal1_tsvOutRing_enc_tmp3.dup +ThickGateOx_GP_out_ThickGateOx_TGO_d_sep_tmp9 = ThickGateOx_GP_out_ThickGateOx_TGO_d_sep_tmp6.dup +SVaricap_poly = GatPoly.not_outside(SVaricap_gate_0) +NWell_Tie = NAct_NWell.ext_not(WellContDev.ext_or(SalBlock.ext_or(TRANS))) +schottky_pwb = schottky_nbl1.ext_and(PWell_block) +schottky_nSDBlock = schottky_nbl1.ext_and(nSD_block) +schottky_salblock = schottky_nbl1.ext_and(SalBlock) +schottky_contbar = schottky_nbl1.ext_and(ContBar) +scr1_or_schottky_nbl1 = schottky_nbl1.ext_or(scr1) +Metal5_slit_MIM_Slt_g_M5_sep = Metal5_slit_MIM_Slt_g_M5_sep_tmp11.dup +TopMetal1_slit_MIM_Slt_g_TM1_sep = TopMetal1_slit_MIM_Slt_g_TM1_sep_tmp11.dup +GP_Rsil_extended_external_pSD = GP_Rsil_extended.ext_fast_separation(pSD, 0.18.um) +SVaricap_text = Activ.not_outside(SVaricap_gate_0).ext_interacting_with_text(TEXT_0, "SVaricap") +PAct_PWellLV = PAct_PWell.ext_not(ThickGateOx) +cmim_tie = PAct_PWell.not_outside(rfcmim) +Abut_PWell_Tie_Edge = PAct_PWell.ext_coincident_part(NAct_PWell, outside: true) +BJT_ring_a = PAct_PWell.with_holes +PAct_PWell_not_Gate = PAct_PWell.ext_not(Gate) +Abut_NWell_Tie = NAct_NWell.ext_with_coincident_edges(Abut_NWell_Tie_Edge) +NActHV_ana = NActHV.ext_not(NActHV_digi) +soft_n_tie = n_tie.ext_not(hard_n_tie) +schottky_nbl1_b = PAct_connect.not_outside(schottky_nbl1).ext_not(schottky_nbl1) +schottky_nw1 = schottky_nw1_sized.ext_interacting_with_text(TEXT_0, "schottky_nw1") +ThickGateOx_Act_out_ThickGateOx_TGO_b_sep_tmp11 = ThickGateOx_Act_out_ThickGateOx_TGO_b_sep_tmp9.dup +PWell_block_tsvOutRing_enc = PWell_block_tsvOutRing_enc_tmp6.dup +Metal1_tsvOutRing_enc = Metal1_tsvOutRing_enc_tmp6.dup +ThickGateOx_GP_out_ThickGateOx_TGO_d_sep_tmp11 = ThickGateOx_GP_out_ThickGateOx_TGO_d_sep_tmp9.dup +MOSvaricap = MVaricap.ext_or(SVaricap_poly) +SubContDev_basic = PAct_PWell.ext_interacting_with_text(TEXT_0, "sub!").ext_not(Recog_esd) +NwellRing_innermost = NWell_Tie.holes.merge.outside(NWell_Tie) +ntap = ntaparea.ext_covering(Cont.ext_and(ntaparea)) +SVaricap = NWell.not_outside(SVaricap_text) +PAct_PWellHV = PAct_PWell.ext_not(PAct_PWellLV) +Abut_PWell_Tie = PAct_PWell.ext_with_coincident_edges(Abut_PWell_Tie_Edge) +abut_tie_edge_PWell = PAct_PWell_not_Gate.ext_coincident_part(NAct_PWell, outside: true) +Abut_NWell_Tie_PAct = PAct.ext_interacting(Abut_NWell_Tie) +nsdb_exlcDev = dschottky.ext_or(schottky_nbl1, schottky_nw1, trans_bip) +schottky_nbl1_or_schottky_nw1 = schottky_nbl1.ext_or(schottky_nw1) +ThickGateOx_Act_out_ThickGateOx_TGO_b_sep = ThickGateOx_Act_out_ThickGateOx_TGO_b_sep_tmp11.dup +ThickGateOx_GP_out_ThickGateOx_TGO_d_sep = ThickGateOx_GP_out_ThickGateOx_TGO_d_sep_tmp11.dup +SubContDev = SubContDev_basic.ext_interacting(nBuLay, inverted: true) +SubContDev_iso = SubContDev_basic.not_outside(nBuLay) +PGate_inside_NwellRing = PGate.not_outside(NwellRing_innermost) +NwellRing_edge = NWell_Tie.ext_coincident_part(NwellRing_innermost, outside: true) +all_ntie = ntap.ext_or(soft_n_tie) +schottky_nw1_b = PAct_connect.not_outside(schottky_nw1).ext_not(schottky_nw1) +pSD_c_tmp1 = pSD.outside(SVaricap) +devExclud = Recog_diode.ext_or(SVaricap, nmoscl_2, nmoscl_4, npnMPA, schottky_nbl1, scr1, subst_tie_hole_w_npn, trans_bip) +SVaricap_or_schottky_nbl1 = SVaricap.ext_or(schottky_nbl1) +NGate_outside_SVaricap = NGate.outside(SVaricap) +PAct_PWellHV_digi = PAct_PWellHV.not_outside(DigiBnd_hole) +Abut_PWell_Tie_NAct = NAct.ext_interacting(Abut_PWell_Tie) +Abut_NWell_Tie_Cont = Cont.inside(Abut_NWell_Tie_PAct) +SVaricap_Tie = PAct_PWell.not_outside(Activ.not_outside(SVaricap)) +NwellRing = NWell_Tie.ext_with_coincident_edges(NwellRing_edge) +PAct_PWellHV_ana = PAct_PWellHV.ext_not(PAct_PWellHV_digi) +Abut_PWell_Tie_Cont = Cont.inside(Abut_PWell_Tie_NAct) +PWell_Tie_w_rf = PAct_PWell.ext_not(Recog_esd.ext_or(SalBlock, SubContDev, SubContDev_iso, cmim_tie, schottky_nbl1, schottky_nbl1_b, schottky_nw1, schottky_nw1_b)) +Holes_NwellRing = NwellRing.holes.merge +PwellRing_innermost = PWell_Tie_w_rf.holes.merge.outside(PWell_Tie_w_rf) +NoHoles_NwellRing = Holes_NwellRing.ext_or(NwellRing) +NGate_inside_PwellRing = NGate.not_outside(PwellRing_innermost) +PwellRing_edge = PWell_Tie_w_rf.ext_coincident_part(PwellRing_innermost, outside: true) +rfNwellRing = NoHoles_NwellRing.ext_interacting_with_text(TEXT_0, "rfpmos*") +PwellRing = PWell_Tie_w_rf.ext_with_coincident_edges(PwellRing_edge) +rfpmos_all = PGate_inside_NwellRing.not_outside(rfNwellRing) +Holes_PwellRing = PwellRing.holes.merge +NoHoles_PwellRing = Holes_PwellRing.ext_or(PwellRing) +pmosHV = PGate.ext_or(rfpmos_all).ext_not(MOSvaricap).not_outside(ThickGateOx) +rfPwellRing = NoHoles_PwellRing.ext_interacting_with_text(TEXT_0, "rfnmos*") +pnpMPARing = NoHoles_PwellRing.ext_interacting_with_text(TEXT_0, "pnpMPA") +rfnmos_all = NGate_inside_PwellRing.not_outside(rfPwellRing) +pnpMPA = PAct_NWell.not_outside(nBuLay).not_outside(pnpMPARing) +BJT_hole = (BJT_ring_a.holes - BJT_ring_a.with_holes).without_holes.ext_covering(TRANS.ext_or(pnpMPA)) +nmosHV = NGate.ext_or(rfnmos_all).ext_not(MOSvaricap).not_outside(ThickGateOx) +BJT_ring = BJT_ring_a.ext_interacting(BJT_hole) +PWell_Tie_wo_varicap_abut = PAct_PWell.ext_interacting(Abut_PWell_Tie.ext_or(BJT_ring, SVaricap_Tie), inverted: true) +-> do + NWell_NW_a.dup +end.().output("NW.a", "Min. NWell width = 0.62") +-> do + NWell.ext_fast_separation(NActHV_ana, 0.62.um) +end.().output("NW.d1", "Min. NWell space to external N+Activ inside ThickGateOx = 0.62") +-> (;x, y) do + x = PAct_PWellLV.ext_coincident_edges(SVaricap, outside: true) + y = PAct_PWellLV.ext_with_coincident_edges(x) + NWell.ext_fast_separation(PAct_PWellLV.ext_not(y), 0.24.um) +end.().output("NW.f", "Min. NWell space to substrate tie in P+Activ not inside ThickGateOx = 0.24") +-> do + NWell.ext_fast_separation(PAct_PWellHV_ana.ext_interacting(SVaricap, inverted: true), 0.62.um) +end.().output("NW.f1", "Min. NWell space to substrate tie in P+Activ inside ThickGateOx = 0.62") +-> do + PWell_block_PWB_a.dup +end.().output("PWB.a", "Min. PWell:block width = 0.62") +-> do + PWell_block_PWB_b.dup +end.().output("PWB.b", "Min. PWell:block space or notch = 0.62") +-> do + PWellBlock_unrelatedNWell.ext_fast_separation(PWell_block, 0.62.um, consider_touch_points: false, include_min_angle: false) +end.().output("PWB.c", "Min. PWell:block space to unrelated NWell = 0.62") +-> do + nBuLayGen_nBuLay_NBL_a.dup +end.().output("NBL.a", "Min. nBuLay width = 1.00") +-> do + nBuLay_block_NBLB_a.dup +end.().output("NBLB.a", "Min. nBuLay:block width = 1.50") +-> do + nBuLay_block.ext_fast_space(1.0.um) +end.().output("NBLB.b", "Min. nBuLay:block space or notch = 1.00") +-> do + nBuLay_nBuLay_block_enc.dup +end.().output("NBLB.c", "Min. nBuLay enclosure of nBuLay:block = 1.00") +-> do + nBuLay_block.ext_fast_separation(nBuLay, 1.5.um, consider_touch_points: false) +end.().output("NBLB.d", "Min. nBuLay:block space to unrelated nBuLay = 1.50") +-> do + Activ_Act_a.dup +end.().output("Act.a", "Min. Activ width = 0.15") +-> do + Act_Nsram.ext_fast_space(0.21.um) +end.().output("Act.b", "Min. Activ space or notch = 0.21") +-> do + Activ_Act_d.dup +end.().output("Act.d", "Min. Activ area (µm²) = 0.122") +-> do + (Activ.holes - Activ.with_holes).without_holes.ext_not(Activ).ext_with_area([["<", 0.15.um2]]) +end.().output("Act.e", "Min. Activ enclosed area (µm²) = 0.15") + +if $filler + -> do + Activ_filler.drc((width(projection) > 5.0.um).polygons) + end.().output("AFil.a", "Max. Activ:filler width = 5.00") + -> do + Activ_filler.ext_fast_width(1.0.um) + end.().output("AFil.a1", "Min. Activ:filler width = 1.00") + -> do + Activ_filler.ext_fast_space(0.42.um) + end.().output("AFil.b", "Min. Activ:filler space = 0.42") +end + + +if $density + -> do + Act_density.ext_with_density(0.0 .. 0.35, 'll') + end.().output("AFil.g", "Min. global Activ density [%] = 35.00") + -> do + Act_density.ext_with_density(0.55 .. 1.0, 'll') + end.().output("AFil.g1", "Max. global Activ density [%] = 55.00") + -> do + Act_density.ext_with_density(0.0 .. 0.25, 'll', tile_size(800.0.um), tile_step(400.0.um)) + end.().output("AFil.g2", "Min. Activ coverage ratio for any 800 x 800 µm² chip area [%] = 25.00") + -> do + Act_density.ext_with_density(0.65 .. 1.0, 'll', tile_size(800.0.um), tile_step(400.0.um)) + end.().output("AFil.g3", "Max. Activ coverage ratio for any 800 x 800 µm² chip area [%] = 65.00") +end + +-> do + Activ.ext_fast_enclosed(ThickGateOx, 0.27.um, polygon_output: true) +end.().output("TGO.a", "Min. ThickGateOx extension over Activ = 0.27") +-> do + ThickGateOx_Act_out_ThickGateOx_TGO_b_sep.dup +end.().output("TGO.b", "Min. space between ThickGateOx and Activ outside thick gate oxide region = 0.27") +-> (;a) do + a = Gate.ext_fast_enclosed(ThickGateOx, 0.34.um, polygon_output: true) + a.ext_and(Activ) +end.().output("TGO.c", "Min. ThickGateOx extension over GatPoly over Activ = 0.34") +-> do + ThickGateOx_GP_out_ThickGateOx_TGO_d_sep.dup +end.().output("TGO.d", "Min. space between ThickGateOx and GatPoly over Activ outside thick gate oxide region = 0.34") +-> do + ThickGateOx_TGO_e.dup +end.().output("TGO.e", "Min. ThickGateOx space (merge if less than this value) = 0.86") +-> do + ThickGateOx_TGO_f.dup +end.().output("TGO.f", "Min. ThickGateOx width = 0.86") +-> do + GP_Nsram_Gat_a.dup +end.().output("Gat.a", "Min. GatPoly width = 0.13") +-> (;a) do + a = Activ.ext_not(nmosHV).ext_interacting(nmosHV).ext_fast_space(0.45.um, metric: projection, consider_touch_points: false, include_max_angle: true, polygon_output: true) + a.ext_and(Activ).outside(nmoscl.ext_or(scr1)) +end.().output("Gat.a3", "Min. GatPoly width for channel length of 3.3 V NFET = 0.45") +-> (;b) do + b = Activ.ext_not(pmosHV).ext_interacting(pmosHV).ext_fast_space(0.4.um, metric: projection, consider_touch_points: false, include_max_angle: true, polygon_output: true) + b.ext_and(Activ) +end.().output("Gat.a4", "Min. GatPoly width for channel length of 3.3 V PFET = 0.4") +-> do + GP_Nsram_Gat_b.dup +end.().output("Gat.b", "Min. GatPoly space or notch = 0.18") +-> do + GP_mosHV_Gat_b1.dup +end.().output("Gat.b1", "Min. space between unrelated 3.3 V GatPoly over Activ regions = 0.25") +-> do + [ Activ.ext_fast_enclosed(GP_Nsram, 0.18.um, polygon_output: true), + Activ.ext_fast_enclosed(GatPoly_filler, 0.18.um, polygon_output: true), + GatPoly.inside(Activ) + ].each { |result| result.output("Gat.c", "Min. GatPoly extension over Activ (end cap) = 0.18") } +end.() +-> do + GP_Nsram.ext_fast_separation(Act_Nsram, 0.07.um) +end.().output("Gat.d", "Min. GatPoly space to Activ = 0.07") +-> do + GatPoly_Gat_e.dup +end.().output("Gat.e", "Min. GatPoly area (µm²) = 0.09") +-> do + Gate.ext_not(SVaricap).ext_rectangles(true, false, nil, nil, nil, inverted: true) +end.().output("Gat.f", "45-degree and 90-degree angles for GatPoly on Activ area are not allowed") + +if $filler + -> do + GatPoly_filler.drc((width(projection) > 5.0.um).polygons) + end.().output("GFil.a", "Max. GatPoly:filler width = 5.00") + -> do + GatPoly_filler.ext_fast_width(0.7.um, consider_touch_points: false) + end.().output("GFil.b", "Min. GatPoly:filler width = 0.70") + -> do + GatPoly_filler.ext_fast_space(0.8.um) + end.().output("GFil.c", "Min. GatPoly:filler space = 0.80") + -> do + Activ.ext_fast_separation(GatPoly_filler, 1.1.um, max_angle: 180) + end.().output("GFil.d.Activ", "Min. GatPoly:filler space to Activ = 1.10") + -> do + GatPoly.ext_fast_separation(GatPoly_filler, 1.1.um, max_angle: 180) + end.().output("GFil.d.GatPoly", "Min. GatPoly:filler space to GatPoly = 1.10") + -> do + Cont.ext_fast_separation(GatPoly_filler, 1.1.um, max_angle: 180) + end.().output("GFil.d.Cont", "Min. GatPoly:filler space to Cont = 1.10") + -> do + pSD.ext_fast_separation(GatPoly_filler, 1.1.um, max_angle: 180) + end.().output("GFil.d.pSD", "Min. GatPoly:filler space to pSD = 1.10") + -> do + nSD_block.ext_fast_separation(GatPoly_filler, 1.1.um, max_angle: 180) + end.().output("GFil.d.nSD_block", "Min. GatPoly:filler space to nSD:block = 1.10") + -> do + SalBlock.ext_fast_separation(GatPoly_filler, 1.1.um, max_angle: 180) + end.().output("GFil.d.SalBlock", "Min. GatPoly:filler space to SalBlock = 1.10") + -> do + GatPoly_filler.ext_fast_separation(TRANS, 1.1.um) + end.().output("GFil.f", "Min. GatPoly:filler space to TRANS = 1.10") +end + + +if $density + -> do + Gat_density.ext_with_density(0.0 .. 0.15, 'll') + end.().output("GFil.g", "Min. global GatPoly density [%] = 15.00") +end + + +if $filler + -> do + GatPoly_nofill.ext_fast_space(20.um) + end.().output("GFil.j", "Min. GatPoly:filler extension over Activ:filler (end cap) = 0.18") +end + +-> do + pSD_pSD_a.dup +end.().output("pSD.a", "Min. pSD width = 0.31") +-> do + pSD.ext_fast_space(0.31.um) +end.().output("pSD.b", "Min. pSD space or notch (Note 1) = 0.31") +-> do + Act_NWell.ext_fast_enclosed(pSD_c_tmp1, 0.18.um, polygon_output: true) +end.().output("pSD.c", "Min. pSD enclosure of P+Activ in NWell = 0.18") +-> do + pSD.ext_fast_separation(NAct_PWell, 0.18.um, consider_intersecting_edges: false) +end.().output("pSD.d", "Min. pSD space to unrelated N+Activ in PWell = 0.18") +-> do + pSD.ext_fast_separation(NAct_NWell, 0.03.um, consider_intersecting_edges: false) +end.().output("pSD.d1", "Min. pSD space to N+Activ in NWell = 0.03") +-> (;layA, layB, layC, layD) do + layA = Act_Nsram.not_inside(pSD).ext_interacting(pSD) + layB = layA.ext_and(pSD).outside(SVaricap) + layC = layB.ext_fast_width(0.3.um, metric: projection, consider_intersecting_edges: false, consider_touch_points: false, polygon_output: true) + layD = layC.ext_covering(layB) + layD.dup +end.().output("pSD.e", "Min. pSD overlap of Activ at one position when forming abutted substrate tie (Note 2) = 0.30") +-> (;abuttedNTAP, bad_region, good_region) do + abuttedNTAP = NAct_NWell.ext_interacting(PAct_NWell) + bad_region = abuttedNTAP.ext_coincident_part(PAct_NWell, outside: true).ext_fast_overlap(NAct_NWell, 0.3.um, metric: projection, consider_intersecting_edges: false, consider_touch_points: false, polygon_output: true) + good_region = abuttedNTAP.ext_not(bad_region) + abuttedNTAP.outside(good_region) +end.().output("pSD.f", "Min. Activ extension over pSD at one position when forming abutted NWell tie (Note 2) = 0.30") +-> (;x, y) do + x = NAct_NWell_not_Gate.ext_interacting(SVaricap_or_schottky_nbl1, inverted: true).outside(SRAM) + y = PAct_PWell_not_Gate.ext_interacting(SVaricap_or_schottky_nbl1, inverted: true).outside(SRAM) + [ x.ext_interacting(Gate, inverted: true).ext_with_area([["<", 0.09.um2]]), + y.ext_interacting(Gate, inverted: true).ext_with_area([["<", 0.09.um2]]) + ].each { |result| result.output("pSD.g", "Min. N+Activ or P+Activ area (µm²) when forming abutted tie (Note 2) = 0.09") } +end.() +-> do + PGate.ext_fast_enclosed(pSD_Nsram, 0.3.um, polygon_output: true) +end.().output("pSD.i", "Min. pSD enclosure of PFET gate not inside ThickGateOx = 0.30") +-> do + PGate.ext_fast_enclosed(pSDHV_Nsram, 0.4.um, polygon_output: true) +end.().output("pSD.i1", "Min. pSD enclosure of PFET gate inside ThickGateOx = 0.40") +-> do + pSD_Nsram.ext_fast_separation(NGate_outside_SVaricap, 0.3.um) +end.().output("pSD.j", "Min. pSD space to NFET gate not inside ThickGateOx = 0.30") +-> do + pSD_Nsram.ext_fast_separation(NGate_outside_SVaricap.inside(ThickGateOx), 0.4.um) +end.().output("pSD.j1", "Min. pSD space to NFET gate inside ThickGateOx = 0.40") +-> do + pSD_pSD_k.dup +end.().output("pSD.k", "Min. pSD area (µm²) = 0.25") +-> do + pSDL_enc_area_pSD_l.dup +end.().output("pSD.l", "Min. pSD enclosed area (µm²) = 0.25") +-> do + GP_Rsil_extended_external_pSD.dup +end.().output("pSD.m", "Min. pSD space to n-type poly resistors = 0.18") +-> do + Rppd_all_enclosure_pSD.dup +end.().output("pSD.n", "Min. pSD enclosure of p-type poly resistors = 0.18") +-> do + nSD_block.ext_fast_width(0.31.um) +end.().output("nSDB.a", "Min. nSD:block width = 0.31") +-> do + nSD_block.ext_fast_space(0.31.um) +end.().output("nSDB.b", "Min. nSD:block space or notch = 0.31") +-> do + nSD_block.ext_fast_separation(pSD.ext_interacting(nSD_block, inverted: true), 0.31.um, consider_touch_points: false) +end.().output("nSDB.c", "Min. nSD:block space to unrelated pSD = 0.31") +-> do + Cont.outside(nsdb_exlcDev).ext_and(nSD_block) +end.().output("nSDB.e", "Min. nSD:block space to Cont (Note 2) = 0.00") +-> do + EXTBlock.ext_fast_width(0.31.um) +end.().output("EXT.a", "Min. EXTBlock width = 0.31") +-> do + EXTBlock.ext_fast_space(0.31.um) +end.().output("EXT.b", "Min. EXTBlock space or notch = 0.31") +-> do + EXTBlock.ext_fast_separation(pSD, 0.31.um) +end.().output("EXT.c", "Min. EXTBlock space to pSD = 0.31") +-> do + SalBlock.ext_fast_width(0.42.um) +end.().output("Sal.a", "Min. SalBlock width = 0.42") +-> do + SalBlock.ext_fast_space(0.42.um) +end.().output("Sal.b", "Min. SalBlock space or notch = 0.42") +-> do + [ GatPoly_res.ext_fast_enclosed(SalBlock, 0.2.um, polygon_output: true), + Activ.ext_fast_enclosed(SalBlock, 0.2.um, polygon_output: true) + ].each { |result| result.output("Sal.c", "Min. SalBlock extension over Activ or GatPoly = 0.20") } +end.() +-> do + [ SalBlock.ext_fast_separation(GatPoly_res, 0.2.um, consider_touch_points: false), + SalBlock.ext_fast_separation(nmosi_relevant_activ, 0.2.um, consider_touch_points: false) + ].each { |result| result.output("Sal.d", "Min. SalBlock space to unrelated Activ or GatPoly = 0.20") } +end.() +-> do + SalBlock.ext_fast_separation(Cont, 0.2.um) +end.().output("Sal.e", "Min. SalBlock space to Cont = 0.20") +-> do + Cont_outside_EdgeSeal.ext_not(ContBar.ext_or(Cont_SQ)) +end.().output("Cnt.a", "Min. and max. Cont width = 0.16") +-> do + Cont_outside_EdgeSeal.ext_fast_space(0.18.um, consider_intersecting_edges: false) +end.().output("Cnt.b", "Min. Cont space = 0.18") +-> (;x1, viaLargeArray, viaInLargeArray, viaInLargeArray_error, badViaLine) do + x1 = Cont.sized((0.20*0.5).um, acute_limit).sized(-(0.20*0.5).um, acute_limit) + viaLargeArray = x1.sized(-((5*0.16)+(3*0.18)/2-0.001).um, acute_limit).sized(((5*0.16)+(3*0.18)/2-0.001).um, acute_limit) + viaInLargeArray = Cont.inside(viaLargeArray) + viaInLargeArray_error = viaInLargeArray.sized((0.20/2-0.001).um, acute_limit).sized(-(0.20/2-0.001).um, acute_limit) + badViaLine = viaInLargeArray_error.ext_not(viaInLargeArray) + badViaLine.ext_rectangles(inverted: true) +end.().output("Cnt.b1", "Min. Cont space in a contact array of more than 4 rows and more then 4 columns (Note 1) = 0.20") +-> do + Cont_Act.ext_not(SVaricap).ext_fast_separation(GP_Nsram, 0.11.um) +end.().output("Cnt.f", "Min. Cont on Activ space to GatPoly = 0.11") +-> do + Cont_not_Act_GP.dup +end.().output("Cnt.g", "Cont must be within Activ or GatPoly") +-> do + Cont_not_M1.dup +end.().output("Cnt.h", "Cont must be covered with Metal1") +-> do + Cont_Act_GP.ext_not(SVaricap) +end.().output("Cnt.j", "Cont on GatPoly over Activ is not allowed") +-> do + [ ContBar.outside(EdgeSeal).ext_not(schottky_nbl1_or_schottky_nw1).ext_fast_width(0.16.um), + Cont_outside_EdgeSeal.ext_not(schottky_nbl1_or_schottky_nw1).drc((width(projection) > 0.16.um).polygons) + ].each { |result| result.output("CntB.a", "Min. and max. ContBar width = 0.16") } +end.() +-> do + CntB_a1_error.dup +end.().output("CntB.a1", "Min. ContBar length = 0.34") +-> do + ContBar_outside_TRANS.ext_fast_space(0.28.um) +end.().output("CntB.b", "Min. ContBar space = 0.28") +-> do + ContBar.ext_fast_separation(Cont_SQ, 0.22.um) +end.().output("CntB.b2", "Min. ContBar space to Cont = 0.22") +-> do + ContBar_GP.ext_fast_separation(Activ, 0.14.um) +end.().output("CntB.e", "Min. ContBar on GatPoly space to Activ = 0.14") +-> do + ContBar_Act.ext_fast_separation(GatPoly, 0.11.um) +end.().output("CntB.f", "Min. ContBar on Activ space to GatPoly = 0.11") +-> do + ContBar_not_Act_GP.dup +end.().output("CntB.g", "ContBar must be within Activ or GatPoly") +-> do + pSD.ext_fast_separation(ContBar_NAct, 0.09.um, max_angle: 0, include_max_angle: true, polygon_output: true) +end.().output("CntB.g1", "Min. pSD space to ContBar on nSD-Activ = 0.09") +-> do + ContBar_PAct.ext_fast_enclosed(pSD, 0.09.um, polygon_output: true) +end.().output("CntB.g2", "Min. pSD overlap of ContBar on pSD-Activ = 0.09") +-> do + ContBar_not_M1.dup +end.().output("CntB.h", "ContBar must be covered with Metal1") +-> do + ContBar_Act_GP.dup +end.().output("CntB.j", "ContBar on GatPoly over Activ is not allowed") +-> do + Metal1.ext_fast_width(0.16.um) +end.().output("M1.a", "Min. Metal1 width = 0.16") +-> do + M1_Nsram.ext_fast_space(0.18.um, consider_intersecting_edges: false, ignore_non_axis_aligned_edges: true) +end.().output("M1.b", "Min. Metal1 space or notch = 0.18") +-> do + Cont_Nsram.ext_not(M1_Nsram) +end.().output("M1.c", "Min. Metal1 enclosure of Cont = 0.00") +-> do + Cont_Nsram.outside(EdgeSeal).drc(if_any( + !rectangles, + primary-secondary(Metal1_outside_EdgeSeal), + ((enclosed(Metal1_outside_EdgeSeal, projection, whole_edges, one_side_allowed, two_opposite_sides_allowed) < 0.05.um)))) +end.().output("M1.c1", "Min. Metal1 endcap enclosure of Cont (Note 1) = 0.05") +-> do + Metal1_outside_EdgeSeal.ext_with_area([["<", 0.09.um2]]) +end.().output("M1.d", "Min. Metal1 area (µm²) = 0.09") + +if $density + -> do + M1_density.ext_with_density(0.0 .. 0.35, 'll') + end.().output("M1.j", "Min. global Metal1 density [%] = 35.0") + -> do + M1_density.ext_with_density(0.6 .. 1.0, 'll') + end.().output("M1.k", "Max. global Metal1 density [%] = 60.0") +end + +-> do + Metal2.ext_fast_width(0.2.um) +end.().output("M2.a", "Min. Metal2 width = 0.20") +-> do + M2_Nsram.ext_fast_space(0.21.um, consider_intersecting_edges: false, ignore_non_axis_aligned_edges: true) +end.().output("M2.b", "Min. Metal2 space or notch = 0.21") +-> do + Via1.outside(EdgeSeal).ext_fast_enclosed(Metal2_outside_EdgeSeal, 0.005.um, polygon_output: true) +end.().output("M2.c", "Min. Metal2 enclosure of Via1 = 0.005") +-> do + V1_Nsram_outside_EdgeSeal.drc(if_any( + !rectangles, + primary-secondary(Metal2_outside_EdgeSeal), + ((enclosed(Metal2_outside_EdgeSeal, projection, whole_edges, one_side_allowed, two_opposite_sides_allowed) < 0.05.um)))) +end.().output("M2.c1", "Min. Metal2 endcap enclosure of Via1 (Note 1) = 0.05") +-> do + Metal2_outside_EdgeSeal.ext_with_area([["<", 0.144.um2]]) +end.().output("M2.d", "Min. Metal2 area (µm²) = 0.144") + +if $density + -> do + M2_density.ext_with_density(0.0 .. 0.35, 'll') + end.().output("M2.j", "Min. global Metal2 density [%] = 35.00") + -> do + M2_density.ext_with_density(0.6 .. 1.0, 'll') + end.().output("M2.k", "Max. global Metal2 density [%] = 60.00") +end + +-> do + Metal3.ext_fast_width(0.2.um) +end.().output("M3.a", "Min. Metal3 width = 0.20") +-> do + M3_Nsram.ext_fast_space(0.21.um, consider_intersecting_edges: false, ignore_non_axis_aligned_edges: true) +end.().output("M3.b", "Min. Metal3 space or notch = 0.21") +-> do + Via2.outside(EdgeSeal).ext_fast_enclosed(Metal3_outside_EdgeSeal, 0.005.um, polygon_output: true) +end.().output("M3.c", "Min. Metal3 enclosure of Via2 = 0.005") +-> do + V2_Nsram_outside_EdgeSeal.drc(if_any( + !rectangles, + primary-secondary(Metal3_outside_EdgeSeal), + ((enclosed(Metal3_outside_EdgeSeal, projection, whole_edges, one_side_allowed, two_opposite_sides_allowed) < 0.05.um)))) +end.().output("M3.c1", "Min. Metal3 endcap enclosure of Via2 (Note 1) = 0.05") +-> do + Metal3_outside_EdgeSeal.ext_with_area([["<", 0.144.um2]]) +end.().output("M3.d", "Min. Metal3 area (µm²) = 0.144") + +if $density + -> do + M3_density.ext_with_density(0.0 .. 0.35, 'll') + end.().output("M3.j", "Min. global Metal3 density [%] = 35.00") + -> do + M3_density.ext_with_density(0.6 .. 1.0, 'll') + end.().output("M3.k", "Max. global Metal3 density [%] = 60.00") +end + +-> do + Metal4.ext_fast_width(0.2.um) +end.().output("M4.a", "Min. Metal4 width = 0.20") +-> do + M4_Nsram.ext_fast_space(0.21.um, consider_intersecting_edges: false, ignore_non_axis_aligned_edges: true) +end.().output("M4.b", "Min. Metal4 space or notch = 0.21") +-> do + Via3.outside(EdgeSeal).ext_fast_enclosed(Metal4_outside_EdgeSeal, 0.005.um, polygon_output: true) +end.().output("M4.c", "Min. Metal4 enclosure of Via3 = 0.005") +-> do + V3_Nsram_outside_EdgeSeal.drc(if_any( + !rectangles, + primary-secondary(Metal4_outside_EdgeSeal), + ((enclosed(Metal4_outside_EdgeSeal, projection, whole_edges, one_side_allowed, two_opposite_sides_allowed) < 0.05.um)))) +end.().output("M4.c1", "Min. Metal4 endcap enclosure of Via3 (Note 1) = 0.05") +-> do + Metal4_outside_EdgeSeal.ext_with_area([["<", 0.144.um2]]) +end.().output("M4.d", "Min. Metal4 area (µm²) = 0.144") + +if $density + -> do + M4_density.ext_with_density(0.0 .. 0.35, 'll') + end.().output("M4.j", "Min. global Metal4 density [%] = 35.00") + -> do + M4_density.ext_with_density(0.6 .. 1.0, 'll') + end.().output("M4.k", "Max. global Metal4 density [%] = 60.00") +end + +-> do + Metal5.ext_fast_width(0.2.um) +end.().output("M5.a", "Min. Metal5 width = 0.20") +-> do + M5_Nsram.ext_fast_space(0.21.um, consider_intersecting_edges: false, ignore_non_axis_aligned_edges: true) +end.().output("M5.b", "Min. Metal5 space or notch = 0.21") +-> do + Via4.outside(EdgeSeal).ext_fast_enclosed(Metal5_outside_EdgeSeal, 0.005.um, polygon_output: true) +end.().output("M5.c", "Min. Metal5 enclosure of Via4 = 0.005") +-> do + V4_Nsram_outside_EdgeSeal.drc(if_any( + !rectangles, + primary-secondary(Metal5_outside_EdgeSeal), + ((enclosed(Metal5_outside_EdgeSeal, projection, whole_edges, one_side_allowed, two_opposite_sides_allowed) < 0.05.um)))) +end.().output("M5.c1", "Min. Metal5 endcap enclosure of Via4 (Note 1) = 0.05") +-> do + Metal5_outside_EdgeSeal.ext_with_area([["<", 0.144.um2]]) +end.().output("M5.d", "Min. Metal5 area (µm²) = 0.144") + +if $density + -> do + M5_density.ext_with_density(0.0 .. 0.35, 'll') + end.().output("M5.j", "Min. global Metal5 density [%] = 35.00") + -> do + M5_density.ext_with_density(0.6 .. 1.0, 'll') + end.().output("M5.k", "Max. global Metal5 density [%] = 60.00") +end + + +if $filler + -> do + Metal1_filler.ext_fast_width(1.0.um) + end.().output("M1Fil.a1", "Min. Metal1:filler width = 1.00") + -> do + Metal1_filler.ext_fast_space(0.6.um) + end.().output("M1Fil.b", "Min. Metal1:filler space = 0.42") + -> do + Metal1_filler.ext_fast_separation(Metal1, 0.42.um) + end.().output("M1Fil.c", "Min. Metal1:filler space to Metal1 = 0.42") + -> do + Metal1_filler.ext_fast_separation(TRANS, 1.0.um) + end.().output("M1Fil.d", "Min. Metal1:filler space to TRANS = 1.00") +end + + +if $density + -> do + M1_density.ext_with_density(0.0 .. 0.25, 'll', tile_size(800.0.um), tile_step(400.0.um)) + end.().output("M1Fil.h", "Min. Metal1 and Metal1:filler coverage ratio for any 800 x 800 µm² chip area [%] = 25.00") + -> do + M1_density.ext_with_density(0.75 .. 1.0, 'll', tile_size(800.0.um), tile_step(400.0.um)) + end.().output("M1Fil.k", "Max. Metal1 and Metal1:filler coverage ratio for any 800 x 800 µm² chip area [%] = 75.00") +end + + +if $filler + -> do + Metal2_filler.ext_fast_width(1.0.um) + end.().output("M2Fil.a1", "Min. Metal2:filler width = 1.00") + -> do + Metal2_filler.ext_fast_space(0.6.um) + end.().output("M2Fil.b", "Min. Metal2:filler space = 0.42") + -> do + Metal2_filler.ext_fast_separation(Metal2, 0.42.um) + end.().output("M2Fil.c", "Min. Metal2:filler space to Metal2 = 0.42") + -> do + Metal2_filler.ext_fast_separation(TRANS, 1.0.um) + end.().output("M2Fil.d", "Min. Metal2:filler space to TRANS = 1.00") +end + + +if $density + -> do + M2_density.ext_with_density(0.0 .. 0.25, 'll', tile_size(800.0.um), tile_step(400.0.um)) + end.().output("M2Fil.h", "Min. Metal2 and Metal2:filler coverage ratio for any 800 x 800 µm² chip area [%] = 25.00") + -> do + M2_density.ext_with_density(0.75 .. 1.0, 'll', tile_size(800.0.um), tile_step(400.0.um)) + end.().output("M2Fil.k", "Max. Metal2 and Metal2:filler coverage ratio for any 800 x 800 µm² chip area [%] = 75.00") +end + + +if $filler + -> do + Metal3_filler.ext_fast_width(1.0.um) + end.().output("M3Fil.a1", "Min. Metal3:filler width = 1.00") + -> do + Metal3_filler.ext_fast_space(0.6.um) + end.().output("M3Fil.b", "Min. Metal3:filler space = 0.42") + -> do + Metal3_filler.ext_fast_separation(Metal3, 0.42.um) + end.().output("M3Fil.c", "Min. Metal3:filler space to Metal3 = 0.42") + -> do + Metal3_filler.ext_fast_separation(TRANS, 1.0.um) + end.().output("M3Fil.d", "Min. Metal3:filler space to TRANS = 1.00") +end + + +if $density + -> do + M3_density.ext_with_density(0.0 .. 0.25, 'll', tile_size(800.0.um), tile_step(400.0.um)) + end.().output("M3Fil.h", "Min. Metal3 and Metal3:filler coverage ratio for any 800 x 800 µm² chip area [%] = 25.00") + -> do + M3_density.ext_with_density(0.75 .. 1.0, 'll', tile_size(800.0.um), tile_step(400.0.um)) + end.().output("M3Fil.k", "Max. Metal3 and Metal3:filler coverage ratio for any 800 x 800 µm² chip area [%] = 75.00") +end + + +if $filler + -> do + Metal4_filler.ext_fast_width(1.0.um) + end.().output("M4Fil.a1", "Min. Metal4:filler width = 1.00") + -> do + Metal4_filler.ext_fast_space(0.6.um) + end.().output("M4Fil.b", "Min. Metal4:filler space = 0.42") + -> do + Metal4_filler.ext_fast_separation(Metal4, 0.42.um) + end.().output("M4Fil.c", "Min. Metal4:filler space to Metal4 = 0.42") + -> do + Metal4_filler.ext_fast_separation(TRANS, 1.0.um) + end.().output("M4Fil.d", "Min. Metal4:filler space to TRANS = 1.00") +end + + +if $density + -> do + M4_density.ext_with_density(0.0 .. 0.25, 'll', tile_size(800.0.um), tile_step(400.0.um)) + end.().output("M4Fil.h", "Min. Metal4 and Metal4:filler coverage ratio for any 800 x 800 µm² chip area [%] = 25.00") + -> do + M4_density.ext_with_density(0.75 .. 1.0, 'll', tile_size(800.0.um), tile_step(400.0.um)) + end.().output("M4Fil.k", "Max. Metal4 and Metal4:filler coverage ratio for any 800 x 800 µm² chip area [%] = 75.00") +end + + +if $filler + -> do + Metal5_filler.ext_fast_width(1.0.um) + end.().output("M5Fil.a1", "Min. Metal5:filler width = 1.00") + -> do + Metal5_filler.ext_fast_space(0.6.um) + end.().output("M5Fil.b", "Min. Metal5:filler space = 0.42") + -> do + Metal5_filler.ext_fast_separation(Metal5, 0.42.um) + end.().output("M5Fil.c", "Min. Metal5:filler space to Metal5 = 0.42") + -> do + Metal5_filler.ext_fast_separation(TRANS, 1.0.um) + end.().output("M5Fil.d", "Min. Metal5:filler space to TRANS = 1.00") +end + + +if $density + -> do + M5_density.ext_with_density(0.0 .. 0.25, 'll', tile_size(800.0.um), tile_step(400.0.um)) + end.().output("M5Fil.h", "Min. Metal5 and Metal5:filler coverage ratio for any 800 x 800 µm² chip area [%] = 25.00") + -> do + M5_density.ext_with_density(0.75 .. 1.0, 'll', tile_size(800.0.um), tile_step(400.0.um)) + end.().output("M5Fil.k", "Max. Metal5 and Metal5:filler coverage ratio for any 800 x 800 µm² chip area [%] = 75.00") +end + +-> do + Via1_edgC1_out.outside(transG2L).ext_rectangles(false, false, [["==", 0.19.um]], [["==", 0.19.um]], nil, inverted: true) +end.().output("V1.a", "Min. and max. Via1 width = 0.19") +-> do + Via1_edgC1_out.ext_fast_space(0.22.um, consider_intersecting_edges: false) +end.().output("V1.b", "Min. Via1 space = 0.22") +-> (;via1NoES, x1, via1Array, via1In, via1BigArray, via1SepErr_1, via1SepErr_2) do + via1NoES = Via1_edgC1_out.dup + x1 = via1NoES.sized((0.29*0.5).um, acute_limit).sized(-(0.29*0.5).um, acute_limit) + via1Array = x1.sized(-(((4*0.19+3*0.22)-0.05)*0.5).um, acute_limit).sized((((4*0.19+3*0.22)-0.05)*0.5).um, acute_limit) + via1In = via1NoES.inside(via1Array) + via1BigArray = via1In.sized(0.143.um, acute_limit).sized(-0.143.um, acute_limit) + via1SepErr_1 = via1BigArray.ext_not(via1In) + via1SepErr_2 = via1SepErr_1.ext_not(via1SepErr_1.ext_rectangles) + via1SepErr_2.ext_or(via1In.ext_touching(via1SepErr_2)) +end.().output("V1.b1", "Min. Via1 space in an array of more than 3 rows and more then 3 columns (Note 1) = 0.29") +-> (;x) do + x = V1_Nsram_outside_EdgeSeal.ext_rectangles(false, false, [["==", 0.19.um]], [["==", 0.19.um]], nil) + x.drc(if_any( + !rectangles, + primary-secondary(Metal1_outside_EdgeSeal), + (if_any(enclosed(Metal1_outside_EdgeSeal) < 0.01.um, enclosed(Metal1_outside_EdgeSeal, projection, whole_edges, one_side_allowed, two_opposite_sides_allowed) < 0.05.um)))) +end.().output("V1.c1", "Min. Metal1 endcap enclosure of Via1 (Note 2) = 0.05") +-> do + Via2_edgC1_out.outside(transG2L).ext_rectangles(false, false, [["==", 0.19.um]], [["==", 0.19.um]], nil, inverted: true) +end.().output("V2.a", "Min. and max. Via2 width = 0.19") +-> do + Via2_edgC1_out.ext_fast_space(0.22.um, consider_intersecting_edges: false) +end.().output("V2.b", "Min. Via2 space = 0.22") +-> (;via2NoES, x1, via2Array, via2In, via2BigArray, via2SepErr_1, via2SepErr_2) do + via2NoES = Via2_edgC1_out.dup + x1 = via2NoES.sized((0.29*0.5).um, acute_limit).sized(-(0.29*0.5).um, acute_limit) + via2Array = x1.sized(-(((4*0.19+3*0.22)-0.05)*0.5).um, acute_limit).sized((((4*0.19+3*0.22)-0.05)*0.5).um, acute_limit) + via2In = via2NoES.inside(via2Array) + via2BigArray = via2In.sized(0.143.um, acute_limit).sized(-0.143.um, acute_limit) + via2SepErr_1 = via2BigArray.ext_not(via2In) + via2SepErr_2 = via2SepErr_1.ext_not(via2SepErr_1.ext_rectangles) + via2SepErr_2.ext_or(via2In.ext_touching(via2SepErr_2)) +end.().output("V2.b1", "Min. Via2 space in an array of more than 3 rows and more then 3 columns (Note 1) = 0.29") +-> (;x) do + x = V2_Nsram_outside_EdgeSeal.ext_rectangles(false, false, [["==", 0.19.um]], [["==", 0.19.um]], nil) + x.drc(if_any( + !rectangles, + primary-secondary(Metal2_outside_EdgeSeal), + (if_any(enclosed(Metal2_outside_EdgeSeal) < 0.005.um, enclosed(Metal2_outside_EdgeSeal, projection, whole_edges, one_side_allowed, two_opposite_sides_allowed) < 0.05.um)))) +end.().output("V2.c1", "Min. Metal2 endcap enclosure of Via2 (Note 2) = 0.05") +-> do + Via3_edgC1_out.outside(transG2L).ext_rectangles(false, false, [["==", 0.19.um]], [["==", 0.19.um]], nil, inverted: true) +end.().output("V3.a", "Min. and max. Via3 width = 0.19") +-> do + Via3_edgC1_out.ext_fast_space(0.22.um, consider_intersecting_edges: false) +end.().output("V3.b", "Min. Via3 space = 0.22") +-> (;via3NoES, x1, via3Array, via3In, via3BigArray, via3SepErr_1, via3SepErr_2) do + via3NoES = Via3_edgC1_out.dup + x1 = via3NoES.sized((0.29*0.5).um, acute_limit).sized(-(0.29*0.5).um, acute_limit) + via3Array = x1.sized(-(((4*0.19+3*0.22)-0.05)*0.5).um, acute_limit).sized((((4*0.19+3*0.22)-0.05)*0.5).um, acute_limit) + via3In = via3NoES.inside(via3Array) + via3BigArray = via3In.sized(0.143.um, acute_limit).sized(-0.143.um, acute_limit) + via3SepErr_1 = via3BigArray.ext_not(via3In) + via3SepErr_2 = via3SepErr_1.ext_not(via3SepErr_1.ext_rectangles) + via3SepErr_2.ext_or(via3In.ext_touching(via3SepErr_2)) +end.().output("V3.b1", "Min. Via3 space in an array of more than 3 rows and more then 3 columns (Note 1) = 0.29") +-> (;x) do + x = V3_Nsram_outside_EdgeSeal.ext_rectangles(false, false, [["==", 0.19.um]], [["==", 0.19.um]], nil) + x.drc(if_any( + !rectangles, + primary-secondary(Metal3_outside_EdgeSeal), + (if_any(enclosed(Metal3_outside_EdgeSeal) < 0.005.um, enclosed(Metal3_outside_EdgeSeal, projection, whole_edges, one_side_allowed, two_opposite_sides_allowed) < 0.05.um)))) +end.().output("V3.c1", "Min. Metal3 endcap enclosure of Via3 (Note 2) = 0.05") +-> do + Via4_edgC1_out.outside(transG2L).ext_rectangles(false, false, [["==", 0.19.um]], [["==", 0.19.um]], nil, inverted: true) +end.().output("V4.a", "Min. and max. Via4 width = 0.19") +-> do + Via4_edgC1_out.ext_fast_space(0.22.um, consider_intersecting_edges: false) +end.().output("V4.b", "Min. Via4 space = 0.22") +-> (;via4NoES, x1, via4Array, via4In, via4BigArray, via4SepErr_1, via4SepErr_2) do + via4NoES = Via4_edgC1_out.dup + x1 = via4NoES.sized((0.29*0.5).um, acute_limit).sized(-(0.29*0.5).um, acute_limit) + via4Array = x1.sized(-(((4*0.19+3*0.22)-0.05)*0.5).um, acute_limit).sized((((4*0.19+3*0.22)-0.05)*0.5).um, acute_limit) + via4In = via4NoES.inside(via4Array) + via4BigArray = via4In.sized(0.143.um, acute_limit).sized(-0.143.um, acute_limit) + via4SepErr_1 = via4BigArray.ext_not(via4In) + via4SepErr_2 = via4SepErr_1.ext_not(via4SepErr_1.ext_rectangles) + via4SepErr_2.ext_or(via4In.ext_touching(via4SepErr_2)) +end.().output("V4.b1", "Min. Via4 space in an array of more than 3 rows and more then 3 columns (Note 1) = 0.29") +-> (;x) do + x = V4_Nsram_outside_EdgeSeal.ext_rectangles(false, false, [["==", 0.19.um]], [["==", 0.19.um]], nil) + x.drc(if_any( + !rectangles, + primary-secondary(Metal4_outside_EdgeSeal), + (if_any(enclosed(Metal4_outside_EdgeSeal) < 0.005.um, enclosed(Metal4_outside_EdgeSeal, projection, whole_edges, one_side_allowed, two_opposite_sides_allowed) < 0.05.um)))) +end.().output("V4.c1", "Min. Metal4 endcap enclosure of Via4 (Note 2) = 0.05") +-> do + TopVia1_edgC1_out.ext_or(Vmim).ext_rectangles(false, false, [["==", 0.42.um]], [["==", 0.42.um]], nil, inverted: true) +end.().output("TV1.a", "Min. and max. TopVia1 width = 0.42") +-> do + TopVia1_or_Vmim.ext_fast_space(0.42.um) +end.().output("TV1.b", "Min. TopVia1 space = 0.42") +-> do + TopMetal1.ext_fast_width(1.64.um) +end.().output("TM1.a", "Min. TopMetal1 width = 1.64") +-> do + TopMetal1.ext_fast_space(1.64.um) +end.().output("TM1.b", "Min. TopMetal1 space or notch = 1.64") + +if $density + -> do + TM1_density.ext_with_density(0.0 .. 0.25, 'll') + end.().output("TM1.c", "Min. global TopMetal1 density [%] = 25.00") + -> do + TM1_density.ext_with_density(0.7 .. 1.0, 'll') + end.().output("TM1.d", "Max. global TopMetal1 density [%] = 70.00") +end + + +if $filler + -> do + TopMetal1_filler.ext_fast_width(5.0.um) + end.().output("TM1Fil.a", "Min. TopMetal1:filler width = 5.00") + -> do + TopMetal1_filler.ext_fast_space(3.0.um) + end.().output("TM1Fil.b", "Min. TopMetal1:filler space = 3.00") + -> do + TopMetal1_filler.ext_fast_separation(TopMetal1, 3.0.um) + end.().output("TM1Fil.c", "Min. TopMetal1:filler space to TopMetal1 = 3.00") + -> do + TopMetal1_filler.ext_fast_separation(TRANS, 4.9.um) + end.().output("TM1Fil.d", "Min. TopMetal1:filler space to TRANS = 4.90") +end + +-> do + TopVia2_edgC1_out.ext_rectangles(false, false, [["==", 0.9.um]], [["==", 0.9.um]], nil, inverted: true) +end.().output("TV2.a", "Min. and max. TopVia2 width = 0.90") +-> do + TopVia2.ext_fast_space(1.06.um) +end.().output("TV2.b", "Min. TopVia2 space = 1.06") +-> do + TopMetal2.ext_fast_width(2.0.um) +end.().output("TM2.a", "Min. TopMetal2 width = 2.00") +-> do + TopMetal2.ext_fast_space(2.0.um) +end.().output("TM2.b", "Min. TopMetal2 space or notch = 2.00") + +if $density + -> do + TM2_density.ext_with_density(0.0 .. 0.25, 'll') + end.().output("TM2.c", "Min. global TopMetal2 density [%] = 25.00") + -> do + TM2_density.ext_with_density(0.7 .. 1.0, 'll') + end.().output("TM2.d", "Max. global TopMetal2 density [%] = 70.00") +end + + +if $filler + -> do + TopMetal2_filler.ext_fast_width(5.0.um) + end.().output("TM2Fil.a", "Min. TopMetal2:filler width = 5.00") + -> do + TopMetal2_filler.ext_fast_space(3.0.um) + end.().output("TM2Fil.b", "Min. TopMetal2:filler space = 3.00") + -> do + TopMetal2_filler.ext_fast_separation(TopMetal2, 3.0.um) + end.().output("TM2Fil.c", "Min. TopMetal2:filler space to TopMetal2 = 3.00") + -> do + TopMetal2_filler.ext_fast_separation(TRANS, 4.9.um) + end.().output("TM2Fil.d", "Min. TopMetal2:filler space to TRANS = 4.90") +end + +-> do + Passiv.ext_fast_width(2.1.um) +end.().output("Pas.a", "Min. Passiv width = 2.10") +-> do + Passiv.ext_fast_space(3.5.um) +end.().output("Pas.b", "Min. Passiv space or notch = 3.50") +-> do + emit_npn13G2.ext_with_length([[">", 0.07.um], ["<", 0.9.um]]) +end.().output("npn13G2.a", "Min. and max. npn13G2 emitter length = 0.90") +-> do + emit_npn13G2L.ext_with_length([[">", 0.07.um], ["<", 1.0.um]]) +end.().output("npn13G2L.a", "Min. npn13G2L emitter length = 1.00") +-> do + emit_npn13G2L.ext_with_length([[">", 2.5.um]]) +end.().output("npn13G2L.b", "Max. npn13G2L emitter length = 2.50") +-> do + emit_npn13G2V.ext_with_length([[">", 0.12.um], ["<", 1.0.um]]) +end.().output("npn13G2V.a", "Min. npn13G2V emitter length = 1.00") +-> do + emit_npn13G2V.ext_with_length([[">", 5.0.um]]) +end.().output("npn13G2V.b", "Max. npn13G2V emitter length = 5.00") +-> do + Rsil_all.ext_fast_width(0.5.um) +end.().output("Rsil.a", "Min. GatPoly width = 0.50") +-> do + RES.ext_fast_separation(Cont, 0.12.um) +end.().output("Rsil.b", "Min. RES space to Cont = 0.12") +-> (;x) do + x = rsil_gatpoly.ext_fast_enclosed(RES, 1.0.um, polygon_output: true) + x.outside(Cont) +end.().output("Rsil.c", "Min. RES extension over GatPoly = 0.00") +-> do + GP_Rsil_extended_external_pSD.dup +end.().output("Rsil.d", "Min. pSD space to GatPoly = 0.18") +-> do + GP_Rsil_extended.ext_fast_enclosed(EXTBlock, 0.18.um, polygon_output: true) +end.().output("Rsil.e", "Min. EXTBlock enclosure of GatPoly = 0.18") +-> do + RES.ext_fast_width(0.5.um) +end.().output("Rsil.f", "Min. RES length = 0.50") +-> do + Rppd_all.ext_fast_width(0.5.um) +end.().output("Rppd.a", "Min. GatPoly width = 0.50") +-> do + Rppd_all_enclosure_pSD.dup +end.().output("Rppd.b", "Min. pSD enclosure of GatPoly = 0.18") +-> (;x) do + x = SalBlock_Rppd.ext_extended(0.2.um, 0.2.um) + [ Rppd_Cont.ext_fast_separation(SalBlock_Rppd, 0.2.um), + Rppd_Cont.ext_interacting(x, inverted: true) + ].each { |result| result.output("Rppd.c", "Min. and max. SalBlock space to Cont = 0.20") } +end.() +-> do + SalBlock_Rppd.ext_fast_width(0.5.um) +end.().output("Rppd.e", "Min. SalBlock length = 0.50") +-> do + Rhigh_a.ext_fast_width(0.5.um) +end.().output("Rhi.a", "Min. GatPoly width = 0.50") +-> do + Rhigh_identical_nsd_psd.dup +end.().output("Rhi.b", "pSD and nSD are identical (Note 1)") +-> do + GP_Rhigh_extended.ext_fast_enclosed(pSD_nSD, 0.18.um, polygon_output: true) +end.().output("Rhi.c", "Min. pSD and nSD enclosure of GatPoly = 0.18") +-> (;x) do + x = SalBlock_Rhigh.ext_extended(0.2.um, 0.2.um) + [ Rhigh_Cont.ext_fast_separation(SalBlock_Rhigh, 0.2.um), + Rhigh_Cont.ext_interacting(x, inverted: true) + ].each { |result| result.output("Rhi.d", "Min. and max. SalBlock space to Cont = 0.20") } +end.() +-> do + SalBlock_Rhigh.ext_fast_width(0.5.um) +end.().output("Rhi.f", "Min. SalBlock length = 0.50") +-> do + Iso_PWell_Act.outside(schottky_nbl1).ext_fast_enclosed(nBuLay, 1.24.um, polygon_output: true) +end.().output("nmosi.b", "Min. nBuLay enclosure of Iso-PWell-Activ (Note 1) = 1.24") +-> do + Iso_PWell_Act.ext_not(scr1_or_schottky_nbl1).ext_fast_separation(NWell.with_holes, 0.39.um, max_angle: 180) +end.().output("nmosi.c", "Min. NWell space to Iso-PWell-Activ = 0.39") +-> do + NWell_nBuLay.ext_fast_width(0.62.um) +end.().output("nmosi.d", "Min. NWell-nBuLay width forming an unbroken ring around any Iso-PWell-Activ (Note 2) = 0.62") +-> do + nSDBlock_Iso_PWell_Act.ext_fast_width(0.62.um) +end.().output("nmosi.f", "Min. nSD:block width to separate ptap in nmosi = 0.62") +-> (;tmp, x1) do + tmp = SalBlock_Iso_PWell_Act.ext_not(scr1_or_schottky_nbl1) + x1 = nSDBlock_Iso_PWell_Act.ext_fast_enclosed(tmp.ext_not(tmp.ext_covering(npnMPA)), 0.15.um, polygon_output: true) + x1.ext_and(Activ) +end.().output("nmosi.g", "Min. SalBlock overlap of nSD:block over Activ = 0.15") +-> do + schottky_contbar.ext_fast_enclosed(schottky_pwb, 0.25.um, polygon_output: true) +end.().output("Sdiod.a", "Min. and max. PWell:block enclosure of ContBar = 0.25") +-> do + schottky_contbar.ext_fast_enclosed(schottky_nSDBlock, 0.4.um, polygon_output: true) +end.().output("Sdiod.b", "Min. and max. nSD:block enclosure of ContBar = 0.40") +-> do + schottky_contbar.ext_fast_enclosed(schottky_salblock, 0.45.um, polygon_output: true) +end.().output("Sdiod.c", "Min. and max. SalBlock enclosure of ContBar = 0.45") + +if not $noRecommendedRules + -> do + Passiv_dfpad.ext_fast_width(30.0.um) + end.().output("Pad.aR", "Min. recommended Pad width = 30.00") +end + +-> do + Passiv_Pad_a1.dup +end.().output("Pad.a1", "Max. Pad width = 150.00") + +if not $noRecommendedRules + -> do + Passiv_dfpad.ext_fast_space(8.4.um) + end.().output("Pad.bR", "Min. recommended Pad space = 8.40") +end + +-> do + Passiv_dfpad.ext_fast_separation(Act_EdgeSeal_not_HRACT, 7.5.um) +end.().output("Pad.d", "Min. Pad space to EdgeSeal = 7.50") + +if not $noRecommendedRules + -> do + Passiv_dfpad.ext_fast_separation(Act_EdgeSeal_not_HRACT, 25.0.um) + end.().output("Pad.dR", "Min. recommended Pad to EdgeSeal space (Note 1) = 25.00") + -> do + Passiv_dfpad.ext_fast_separation(Act_Not_EdgeSeal, 11.2.um) + end.().output("Pad.d1R", "Min. recommended Pad to Activ (inside chip area) space = 11.20") + -> do + TopVia2.ext_fast_enclosed(belowTopMetaln_dfpad, 1.4.um, polygon_output: true) + end.().output("Pad.gR", "TopMetal1 (within dfpad) enclosure of TopVia2 = 1.40") + -> do + [ MIM.ext_and(Passiv_dfpad), + Gate.ext_and(Passiv_dfpad) + ].each { |result| result.output("Pad.jR", "No devices under Pad allowed (Note 2)") } + end.() + -> do + TopVia2.inside(Passiv_dfpad) + end.().output("Pad.kR", "TopVia2 under Pad not allowed (Note 3)") +end + +-> do + cupPad_candidat.ext_fast_space(45.0.um, polygon_output: true) +end.().output("Padc.b", "Min. CuPillarPad space = Table 6.1") +-> do + cupPad_candidat.ext_fast_separation(Act_EdgeSeal_not_HRACT, 30.0.um, consider_touch_points: false, polygon_output: true) +end.().output("Padc.d", "Min. CuPillarPad space to EdgeSeal = 30.00") +-> do + Activ_edgA1_in.ext_fast_width(3.5.um, metric: projection, include_max_angle: true) +end.().output("Seal.a_Activ", "Min. EdgeSeal-Activ width = 3.50") +-> do + pSD_edgA1_in.ext_fast_width(3.5.um, metric: projection, include_max_angle: true) +end.().output("Seal.a_pSD", "Min. EdgeSeal-pSD width = 3.50") +-> do + Metal1_edgA1_in.ext_fast_width(3.5.um, metric: projection, include_max_angle: true) +end.().output("Seal.a_Metal1", "Min. EdgeSeal-Metal1 width = 3.50") +-> do + Metal2_edgA1_in.ext_fast_width(3.5.um, metric: projection, include_max_angle: true) +end.().output("Seal.a_Metal2", "Min. EdgeSeal-Metal2 width = 3.50") +-> do + Metal3_edgA1_in.ext_fast_width(3.5.um, metric: projection, include_max_angle: true) +end.().output("Seal.a_Metal3", "Min. EdgeSeal-Metal3 width = 3.50") +-> do + Metal4_edgA1_in.ext_fast_width(3.5.um, metric: projection, include_max_angle: true) +end.().output("Seal.a_Metal4", "Min. EdgeSeal-Metal4 width = 3.50") +-> do + Metal5_edgA1_in.ext_fast_width(3.5.um, metric: projection, include_max_angle: true) +end.().output("Seal.a_Metal5", "Min. EdgeSeal-Metal5 width = 3.50") +-> do + TopMetal1_edgA1_in.ext_fast_width(3.5.um, metric: projection, include_max_angle: true) +end.().output("Seal.a_TopMetal1", "Min. EdgeSeal-TopMetal1 width = 3.50") +-> do + TopMetal2_edgA1_in.ext_fast_width(3.5.um, metric: projection, include_max_angle: true) +end.().output("Seal.a_TopMetal2", "Min. EdgeSeal-TopMetal2 width = 3.50") +-> do + [ Cont_edgC1_in.ext_fast_width(0.16.um), + Cont_edgC1_in.drc((width(projection) > 0.16.um).polygons) + ].each { |result| result.output("Seal.c", "EdgeSeal-Cont ring width = 0.16") } +end.() +-> do + [ Via1_edgC1_in.ext_fast_width(0.19.um), + Via1_edgC1_in.drc((width(projection) > 0.19.um).polygons) + ].each { |result| result.output("Seal.c1.Via1", "EdgeSeal-Via1 ring width = 0.19") } +end.() +-> do + [ Via2_edgC1_in.ext_fast_width(0.19.um), + Via2_edgC1_in.drc((width(projection) > 0.19.um).polygons) + ].each { |result| result.output("Seal.c1.Via2", "EdgeSeal-Via2 ring width = 0.19") } +end.() +-> do + [ Via3_edgC1_in.ext_fast_width(0.19.um), + Via3_edgC1_in.drc((width(projection) > 0.19.um).polygons) + ].each { |result| result.output("Seal.c1.Via3", "EdgeSeal-Via3 ring width = 0.19") } +end.() +-> do + [ Via4_edgC1_in.ext_fast_width(0.19.um), + Via4_edgC1_in.drc((width(projection) > 0.19.um).polygons) + ].each { |result| result.output("Seal.c1.Via4", "EdgeSeal-Via4 ring width = 0.19") } +end.() +-> do + [ TopVia1_edgC1_in.ext_fast_width(0.42.um), + TopVia1_edgC1_in.drc((width(projection) > 0.42.um).polygons) + ].each { |result| result.output("Seal.c2", "EdgeSeal-TopVia1 ring width = 0.42") } +end.() +-> do + [ TopVia2_edgC1_in.ext_fast_width(0.9.um), + TopVia2_edgC1_in.drc((width(projection) > 0.9.um).polygons) + ].each { |result| result.output("Seal.c3", "EdgeSeal-TopVia2 ring width = 0.90") } +end.() +-> do + seal_passiv.ext_fast_width(4.2.um) +end.().output("Seal.e", "Min. Passiv ring width outside of sealring = 4.20") +-> do + MIM_Mim_a.dup +end.().output("MIM.a", "Min. MIM width = 1.14") +-> do + MIM.ext_fast_space(0.6.um) +end.().output("MIM.b", "Min. MIM space = 0.60") +-> do + TopMetal1.ext_fast_separation(MIM, 0.6.um) +end.().output("MIM.e", "Min. TopMetal1 space to MIM = 0.60") +-> do + MIM_Mim_f.dup +end.().output("MIM.f", "Min. MIM area per MIM device (µm²) = 1.30") +-> do + MIM.ext_with_area([[">", 5625.0.um2]]) +end.().output("MIM.g", "Max. MIM area per MIM device (µm²) = 5625.00") +-> do + MIM.ext_not(temp_layer_1) +end.().output("MIM.h", "TopVia1 must be over MIM") +-> (;x) do + x = all_ntie.ext_enlarge_inside(NWell, 20.0.um, 0.1.um) + PAct_NWell.ext_not(x).outside(devExclud) +end.().output("LU.a", "Max. space from any portion of P+Activ inside NWell to an nSD-NWell tie = 20.00") +-> (;sizedA, drcErrA, drcErrA_Edge, drcErrA_Poly) do + sizedA = Abut_NWell_Tie_Cont.ext_enlarge_inside(Act_connect.ext_interacting(Gate), 6.0.um, 0.21.um).ext_interacting(Cont_not_outside_NAct, inverted: true) + drcErrA = Abut_NWell_Tie.ext_not(sizedA) + drcErrA_Edge = drcErrA.ext_coincident_part(sizedA, outside: true) + drcErrA_Poly = drcErrA.ext_with_coincident_edges(drcErrA_Edge) + drcErrA_Poly.ext_interacting(Cont_not_outside_NAct, inverted: true) +end.().output("LU.c", "Max. extension of an abutted NWell tie beyond Cont = 6.00") +-> (;sizedA, drcErrA, drcErrA_Edge, drcErrA_Poly) do + sizedA = Abut_PWell_Tie_Cont.ext_enlarge_inside(Act_connect, 6.0.um, 0.21.um).ext_interacting(Cont_not_outside_PAct, inverted: true) + drcErrA = Abut_PWell_Tie.ext_not(sizedA) + drcErrA_Edge = drcErrA.ext_coincident_part(sizedA, outside: true) + drcErrA_Poly = drcErrA.ext_with_coincident_edges(drcErrA_Edge) + drcErrA_Poly.ext_interacting(Cont_not_outside_PAct, inverted: true) +end.().output("LU.c1", "Max. extension of an abutted substrate tie beyond Cont = 6.00") +-> (;sizedA, tmp, drcErrA, drcErrA_Edge) do + sizedA = size_Cont.dup + tmp = NAct_NWell.outside(scr1).ext_interacting(Activ.ext_interacting(GatPoly), inverted: true) + drcErrA = tmp.ext_not(sizedA) + drcErrA_Edge = drcErrA.ext_coincident_part(sizedA, outside: true) + drcErrA.ext_with_coincident_edges(drcErrA_Edge) +end.().output("LU.d", "Max. extension of NWell tie Activ tie beyond Cont = 6.00") +-> (;sizedA, drcErrA, drcErrA_Edge) do + sizedA = Cont.ext_enlarge_inside(Act_connect, 6.0.um, 0.21.um) + drcErrA = PWell_Tie_wo_varicap_abut.ext_not(sizedA).ext_not(GatPoly) + drcErrA_Edge = drcErrA.ext_coincident_part(sizedA, outside: true) + drcErrA.ext_with_coincident_edges(drcErrA_Edge) +end.().output("LU.d1", "Max. extension of an substrate tie Activ beyond Cont = 6.00") +-> do + Metal1_slit_not_pad.ext_fast_width(2.8.um) +end.().output("Slt.a.M1", "Min. Metal1:slit width = 2.80") +-> (;tmp) do + tmp = Metal1_slit_not_pad.ext_with_length([[">", 20.0.um]]) + Metal1_slit.ext_with_coincident_edges(tmp) +end.().output("Slt.b.M1", "Max. Metal1:slit width = 20.00") +-> (;m1mitSlots, m1_L1, m1_L2) do + m1mitSlots = sltc_M1.ext_not(Metal1_slit) + m1_L1 = m1mitSlots.sized(-3.0.um, acute_limit) + m1_L2 = m1_L1.sized(-12.0.um, acute_limit) + m1_L2.sized(15.0.um, acute_limit) +end.().output("Slt.c.M1", "Max. Metal1 width without requiring a slit = 30.00") +-> do + Metal1_slit.ext_and(pad) +end.().output("Slt.e.M1", "No slits required on bond pads") +-> do + Metal1_slit_not_pad.ext_fast_enclosed(Metal1, 1.0.um, polygon_output: true) +end.().output("Slt.f.M1", "Min. Metal1 enclosure of Metal1:slit = 1.00") +-> do + [ Metal1_slit_not_pad.ext_fast_separation(Cont, 0.3.um), + Metal1_slit_not_pad.ext_fast_separation(Via1, 0.3.um) + ].each { |result| result.output("Slt.h1", "Min. Metal1:slit space to Cont and Via1 = 0.30") } +end.() +-> do + Metal2_slit_not_pad.ext_fast_width(2.8.um) +end.().output("Slt.a.M2", "Min. Metal2:slit width = 2.80") +-> (;tmp) do + tmp = Metal2_slit_not_pad.ext_with_length([[">", 20.0.um]]) + Metal2_slit.ext_with_coincident_edges(tmp) +end.().output("Slt.b.M2", "Max. Metal2:slit width = 20.00") +-> (;m2mitSlots, m2_L1, m2_L2) do + m2mitSlots = sltc_M2.ext_not(Metal2_slit) + m2_L1 = m2mitSlots.sized(-3.0.um, acute_limit) + m2_L2 = m2_L1.sized(-12.0.um, acute_limit) + m2_L2.sized(15.0.um, acute_limit) +end.().output("Slt.c.M2", "Max. Metal2 width without requiring a slit = 30.00") +-> do + Metal2_slit.ext_and(pad) +end.().output("Slt.e.M2", "No slits required on bond pads") +-> do + Metal2_slit_not_pad.ext_fast_enclosed(Metal2, 1.0.um, polygon_output: true) +end.().output("Slt.f.M2", "Min. Metal2 enclosure of Metal2:slit = 1.00") +-> do + [ Metal2_slit_not_pad.ext_fast_separation(Via1, 0.3.um), + Metal2_slit_not_pad.ext_fast_separation(Via2, 0.3.um) + ].each { |result| result.output("Slt.h2.M2", "Min. Metal2:slit space to Via1 and Via2 = 0.30") } +end.() +-> do + Metal3_slit_not_pad.ext_fast_width(2.8.um) +end.().output("Slt.a.M3", "Min. Metal3:slit width = 2.80") +-> (;tmp) do + tmp = Metal3_slit_not_pad.ext_with_length([[">", 20.0.um]]) + Metal3_slit.ext_with_coincident_edges(tmp) +end.().output("Slt.b.M3", "Max. Metal3:slit width = 20.00") +-> (;m3mitSlots, m3_L1, m3_L2) do + m3mitSlots = sltc_M3.ext_not(Metal3_slit) + m3_L1 = m3mitSlots.sized(-3.0.um, acute_limit) + m3_L2 = m3_L1.sized(-12.0.um, acute_limit) + m3_L2.sized(15.0.um, acute_limit) +end.().output("Slt.c.M3", "Max. Metal3 width without requiring a slit = 30.00") +-> do + Metal3_slit.ext_and(pad) +end.().output("Slt.e.M3", "No slits required on bond pads") +-> do + Metal3_slit_not_pad.ext_fast_enclosed(Metal3, 1.0.um, polygon_output: true) +end.().output("Slt.f.M3", "Min. Metal3 enclosure of Metal2:slit = 1.00") +-> do + [ Metal3_slit_not_pad.ext_fast_separation(Via2, 0.3.um), + Metal3_slit_not_pad.ext_fast_separation(Via3, 0.3.um) + ].each { |result| result.output("Slt.h2.M3", "Min. Metal3:slit space to Via2 and Via3 = 0.30") } +end.() +-> do + Metal4_slit_not_pad.ext_fast_width(2.8.um) +end.().output("Slt.a.M4", "Min. Metal4:slit width = 2.80") +-> (;tmp) do + tmp = Metal4_slit_not_pad.ext_with_length([[">", 20.0.um]]) + Metal4_slit.ext_with_coincident_edges(tmp) +end.().output("Slt.b.M4", "Max. Metal4:slit width = 20.00") +-> (;m4mitSlots, m4_L1, m4_L2) do + m4mitSlots = sltc_M4.ext_not(Metal4_slit) + m4_L1 = m4mitSlots.sized(-3.0.um, acute_limit) + m4_L2 = m4_L1.sized(-12.0.um, acute_limit) + m4_L2.sized(15.0.um, acute_limit) +end.().output("Slt.c.M4", "Max. Metal4 width without requiring a slit = 30.00") +-> do + Metal4_slit.ext_and(pad) +end.().output("Slt.e.M4", "No slits required on bond pads") +-> do + Metal4_slit_not_pad.ext_fast_enclosed(Metal4, 1.0.um, polygon_output: true) +end.().output("Slt.f.M4", "Min. Metal4 enclosure of Metal4:slit = 1.00") +-> do + [ Metal4_slit_not_pad.ext_fast_separation(Via3, 0.3.um), + Metal4_slit_not_pad.ext_fast_separation(Via4, 0.3.um) + ].each { |result| result.output("Slt.h2.M4", "Min. Metal4:slit space to Via3 and Via4 = 0.30") } +end.() +-> do + Metal5_slit_not_pad.ext_fast_width(2.8.um) +end.().output("Slt.a.M5", "Min. Metal5:slit width = 2.80") +-> (;tmp) do + tmp = Metal5_slit_not_pad.ext_with_length([[">", 20.0.um]]) + Metal5_slit.ext_with_coincident_edges(tmp) +end.().output("Slt.b.M5", "Max. Metal5:slit width = 20.00") +-> (;m5mitSlots, m5_L1, m5_L2) do + m5mitSlots = sltc_M5.ext_not(Metal5_slit) + m5_L1 = m5mitSlots.sized(-3.0.um, acute_limit) + m5_L2 = m5_L1.sized(-12.0.um, acute_limit) + m5_L2.sized(15.0.um, acute_limit) +end.().output("Slt.c.M5", "Max. Metal5 width without requiring a slit = 30.00") +-> do + Metal5_slit.ext_and(pad) +end.().output("Slt.e.M5", "No slits required on bond pads") +-> do + Metal5_slit_not_pad.ext_fast_enclosed(Metal5, 1.0.um, polygon_output: true) +end.().output("Slt.f.M5", "Min. Metal5 enclosure of Metal5:slit = 1.00") +-> do + Metal5_slit_MIM_Slt_g_M5_sep.dup +end.().output("Slt.g.M5", "Min. Metal5:slit and TopMetal1:slit space to MIM = 0.60") +-> do + [ Metal5_slit_not_pad.ext_fast_separation(Via4, 0.3.um), + Metal5_slit_not_pad.ext_fast_separation(TopVia1, 0.3.um) + ].each { |result| result.output("Slt.h2.M5", "Min. Metal5:slit space to Via4 and Via5 = 0.30") } +end.() +-> do + TopMetal1_slit_not_pad.ext_fast_width(2.8.um) +end.().output("Slt.a.TM1", "Min. TopMetal1:slit width = 2.80") +-> (;tmp) do + tmp = TopMetal1_slit_not_pad.ext_with_length([[">", 20.0.um]]) + TopMetal1_slit.ext_with_coincident_edges(tmp) +end.().output("Slt.b.TM1", "Max. TopMetal1:slit width = 20.00") +-> (;tM1mitSlots, tM1_L1, tM1_L2) do + tM1mitSlots = sltc_TM1.ext_not(TopMetal1_slit) + tM1_L1 = tM1mitSlots.sized(-3.0.um, acute_limit) + tM1_L2 = tM1_L1.sized(-12.0.um, acute_limit) + tM1_L2.sized(15.0.um, acute_limit) +end.().output("Slt.c.TM1", "Max. TopMetal1 width without requiring a slit = 30.00") +-> do + TopMetal1_slit.ext_and(pad) +end.().output("Slt.e.TM1", "No slits required on bond pads") +-> do + TopMetal1_slit_not_pad.ext_fast_enclosed(TopMetal1, 1.0.um, polygon_output: true) +end.().output("Slt.f.TM1", "Min. TopMetal1 enclosure of TopMetal1:slit = 1.00") +-> do + TopMetal1_slit_MIM_Slt_g_TM1_sep.dup +end.().output("Slt.g.TM1", "Min. Metal5:slit and TopMetal1:slit space to MIM = 0.60") +-> do + TopMetal1_slit_not_pad.ext_fast_separation(TopVia1, 1.0.um) +end.().output("Slt.h3", "Min. TopMetal1:slit space to TopVia1 and TopVia2 = 1.00") +-> do + TopMetal2_slit_not_pad.ext_fast_width(2.8.um) +end.().output("Slt.a.TM2", "Min. TopMetal2:slit width = 2.80") +-> (;tmp) do + tmp = TopMetal2_slit_not_pad.ext_with_length([[">", 20.0.um]]) + TopMetal2_slit.ext_with_coincident_edges(tmp) +end.().output("Slt.b.TM2", "Max. TopMetal2:slit width = 20.00") +-> (;tM2mitSlots, tM2_L1, tM2_L2) do + tM2mitSlots = sltc_TM2.ext_not(TopMetal2_slit) + tM2_L1 = tM2mitSlots.sized(-3.0.um, acute_limit) + tM2_L2 = tM2_L1.sized(-12.0.um, acute_limit) + tM2_L2.sized(15.0.um, acute_limit) +end.().output("Slt.c.TM2", "Max. TopMetal2 width without requiring a slit = 30.00") +-> do + TopMetal2_slit.ext_and(pad) +end.().output("Slt.e.TM2", "No slits required on bond pads") +-> do + TopMetal2_slit_not_pad.ext_fast_enclosed(TopMetal2, 1.0.um, polygon_output: true) +end.().output("Slt.f.TM2", "Min. TopMetal2 enclosure of TopMetal2:slit = 1.00") +-> do + TopMetal2_slit_not_pad.ext_fast_separation(TopVia2, 1.0.um) +end.().output("Slt.h4", "Min. TopMetal2:slit space to TopVia2 = 1.00") + +if $sanityRules + -> do + Activ_pin.ext_not(Activ) + end.().output("Pin.a", "Min. Activ enclosure of Activ:pin = 0.00") + -> do + GatPoly_pin.ext_not(GatPoly) + end.().output("Pin.b", "Min. GatPoly enclosure of GatPoly:pin = 0.00") + -> do + Metal1_pin.ext_not(Metal1) + end.().output("Pin.e", "Min. Metal1 enclosure of Metal1:pin = 0.00") + -> do + Metal2_pin.ext_not(Metal2) + end.().output("Pin.f.M2", "Min. Metal2 enclosure of Metal2:pin = 0.00") + -> do + Metal3_pin.ext_not(Metal3) + end.().output("Pin.f.M3", "Min. Metal3 enclosure of Metal3:pin = 0.00") + -> do + Metal4_pin.ext_not(Metal4) + end.().output("Pin.f.M4", "Min. Metal4 enclosure of Metal4:pin = 0.00") + -> do + Metal5_pin.ext_not(Metal5) + end.().output("Pin.f.M5", "Min. Metal5 enclosure of Metal5:pin = 0.00") + -> do + TopMetal1_pin.ext_not(TopMetal1) + end.().output("Pin.g", "Min. TopMetal1 enclosure of TopMetal1:pin = 0.00") + -> do + TopMetal2_pin.ext_not(TopMetal2) + end.().output("Pin.h", "Min. TopMetal2 enclosure of TopMetal2:pin = 0.00") +end + +-> do + NWell.ext_fast_separation(NActHV_digi, 0.31.um) +end.().output("NW.d1.dig", "Min. NWell space to external N+Activ inside ThickGateOx = 0.31") +-> do + NWell.ext_fast_separation(PAct_PWellHV_digi, 0.24.um) +end.().output("NW.f1.dig", "Min. NWell space to substrate tie in P+Activ inside ThickGateOx = 0.24") +-> do + GP_SRAM_Gat_a_SRAM.dup +end.().output("Gat.a.SRAM", "Min. GatPoly width = 0.069") +-> do + GP_SRAM_Gat_b_SRAM.dup +end.().output("Gat.b.SRAM", "Min. GatPoly space or notch = 0.149") +-> do + Activ.ext_fast_enclosed(GP_SRAM, 0.079.um, polygon_output: true) +end.().output("Gat.c.SRAM", "Min. GatPoly extension over Activ (end cap) = 0.079") +-> do + GP_SRAM.ext_fast_separation(Act_SRAM, 0.029.um) +end.().output("Gat.d.SRAM", "Min. GatPoly space to Activ = 0.029") +-> (;layA, layB, layC, layD) do + layA = Activ.ext_and(SRAM).not_inside(pSD).ext_interacting(pSD) + layB = layA.ext_and(pSD) + layC = layB.ext_fast_width(0.28.um, metric: projection, consider_intersecting_edges: false, consider_touch_points: false, polygon_output: true) + layD = layC.ext_covering(layB) + layD.dup +end.().output("pSD.e.SRAM", "Min. pSD overlap of Activ when forming abutted substrate tie = 0.28") +-> (;x, y) do + x = abut_tie_edge_NWell.ext_inside_part(SRAM) + y = abut_tie_edge_PWell.ext_inside_part(SRAM) + [ x.ext_with_length([["<", 0.15.um]]), + y.ext_with_length([["<", 0.15.um]]) + ].each { |result| result.output("pSD.g.SRAM", "Min. N+Activ or P+Activ width when forming abutted tie = 0.15") } +end.() +-> do + PGate.ext_fast_enclosed(pSD_SRAM, 0.068.um, polygon_output: true) +end.().output("pSD.i.SRAM", "Min. pSD enclosure of PFET gate not inside ThickGateOx = 0.068") +-> do + pSD_SRAM.ext_fast_separation(NGate_outside_SVaricap, 0.239.um) +end.().output("pSD.j.SRAM", "Min. pSD space to NFET gate not inside ThickGateOx = 0.239") +-> do + Cont_Act.ext_fast_separation(GP_SRAM, 0.059.um) +end.().output("Cnt.f.SRAM", "Min. Cont on Activ space to GatPoly = 0.059") +-> do + M1_SRAM.ext_fast_space(0.159.um, consider_intersecting_edges: false, ignore_non_axis_aligned_edges: true) +end.().output("M1.b.SRAM", "Min. Metal1 space or notch = 0.159") +-> do + Cont_SRAM.outside(EdgeSeal).drc(if_any( + !rectangles, + primary-secondary(M1_SRAM_outside_EdgeSeal), + ((enclosed(M1_SRAM_outside_EdgeSeal, projection, whole_edges, one_side_allowed, two_opposite_sides_allowed) < 0.005.um)))) +end.().output("M1.c1.SRAM", "Min. Metal1 endcap enclosure of Cont = 0.005") +-> do + M2_SRAM.ext_fast_space(0.169.um, consider_intersecting_edges: false, ignore_non_axis_aligned_edges: true) +end.().output("M2.b.SRAM", "Min. Metal2 space or notch = 0.169") +-> do + V1_SRAM_outside_EdgeSeal.drc(if_any( + !rectangles, + primary-secondary(M2_SRAM.outside(EdgeSeal)), + ((enclosed(M2_SRAM.outside(EdgeSeal), projection, whole_edges, one_side_allowed, two_opposite_sides_allowed) < 0.02.um)))) +end.().output("M2.c1.SRAM", "Min. Metal2 endcap enclosure of Via1 = 0.02") +-> do + M3_SRAM.ext_fast_space(0.169.um, consider_intersecting_edges: false, ignore_non_axis_aligned_edges: true) +end.().output("M3.b.SRAM", "Min. Metal3 space or notch = 0.169") +-> do + V2_SRAM_outside_EdgeSeal.drc(if_any( + !rectangles, + primary-secondary(M3_SRAM.outside(EdgeSeal)), + ((enclosed(M3_SRAM.outside(EdgeSeal), projection, whole_edges, one_side_allowed, two_opposite_sides_allowed) < 0.02.um)))) +end.().output("M3.c1.SRAM", "Min. Metal3 endcap enclosure of Via2 = 0.02") +-> do + M4_SRAM.ext_fast_space(0.169.um, consider_intersecting_edges: false, ignore_non_axis_aligned_edges: true) +end.().output("M4.b.SRAM", "Min. Metal4 space or notch = 0.169") +-> do + V3_SRAM_outside_EdgeSeal.drc(if_any( + !rectangles, + primary-secondary(M4_SRAM.outside(EdgeSeal)), + ((enclosed(M4_SRAM.outside(EdgeSeal), projection, whole_edges, one_side_allowed, two_opposite_sides_allowed) < 0.02.um)))) +end.().output("M4.c1.SRAM", "Min. Metal4 endcap enclosure of Via3 = 0.02") +-> do + M5_SRAM.ext_fast_space(0.169.um, consider_intersecting_edges: false, ignore_non_axis_aligned_edges: true) +end.().output("M5.b.SRAM", "Min. Metal5 space or notch = 0.169") +-> do + V4_SRAM_outside_EdgeSeal.drc(if_any( + !rectangles, + primary-secondary(M5_SRAM.outside(EdgeSeal)), + ((enclosed(M5_SRAM.outside(EdgeSeal), projection, whole_edges, one_side_allowed, two_opposite_sides_allowed) < 0.02.um)))) +end.().output("M5.c1.SRAM", "Min. Metal5 endcap enclosure of Via4 = 0.02") +-> do + LBE.ext_fast_width(100.0.um) +end.().output("LBE.a", "Min. LBE width = 100.00") +-> do + LBE.drc((width(projection) > 1500.0.um).polygons) +end.().output("LBE.b", "Max. LBE width = 1500.00") +-> do + LBE.ext_with_area([[">", 250000.0.um2]]) +end.().output("LBE.b1", "Max. LBE area (µm²) = 250000.00") +-> do + LBE.ext_with_area([["<", 250000.0.um2]]) +end.().output("LBE.b2", "Min. LBE area (µm²) = 30000.00") +-> do + LBE.ext_fast_space(100.0.um, consider_intersecting_edges: false, ignore_non_axis_aligned_edges: true) +end.().output("LBE.c", "Min. LBE space or notch = 100.00") +-> (;lbe_in_seal) do + lbe_in_seal = LBE.inside(EdgeSeal.holes.merge) + lbe_in_seal.ext_fast_separation(EdgeSeal, 150.0.um, consider_intersecting_edges: false, ignore_non_axis_aligned_edges: true) +end.().output("LBE.d", "Min. LBE space to inner edge of EdgeSeal = 150.00") +-> do + LBE.ext_fast_separation(dfpad, 50.0.um, consider_intersecting_edges: false, ignore_non_axis_aligned_edges: true) +end.().output("LBE.e.dfPad", "Min. LBE space to dfpad and Passiv = 50.00") +-> do + LBE.ext_fast_separation(Passiv, 50.0.um, consider_intersecting_edges: false, ignore_non_axis_aligned_edges: true) +end.().output("LBE.e.Passiv", "Min. LBE space to dfpad and Passiv = 50.00") +-> do + LBE.ext_fast_separation(Activ, 30.0.um, consider_intersecting_edges: false, ignore_non_axis_aligned_edges: true) +end.().output("LBE.f", "Min. LBE space to Activ = 30.00") +-> do + LBE.with_holes.dup +end.().output("LBE.h", "No LBE ring allowed") + +if $density + -> do + LBE.ext_with_density(0.2 .. 1.0, 'll') + end.().output("LBE.i", "Max. global LBE density [%] = 20.00") +end + +-> do + bad_tsv.dup +end.().output("TSV_G.a", "DeepVia has to be a ring structure") +-> do + tsv_fill_TSV_G_d.dup +end.().output("TSV_G.d", "Min. DeepVia space = 25.00") +-> do + PWell_block_tsvOutRing_enc.dup +end.().output("TSV_G.f", "Min. PWell:block enclosure of DeepVia = 2.50") +-> do + Metal1_tsvOutRing_enc.dup +end.().output("TSV_G.g", "Min. Metal1 enclosure of DeepVia ring structure = 1.50") + +if $checkDensityRules + -> do + tsv.ext_with_density(0.0 .. 0.0001, 'll') + end.().output("TSV_G.i", "Max. global DeepVia density [%] = 1.00") + -> do + tsv.ext_with_density(0.001 .. 1.0, 'll') + end.().output("TSV_G.j", "Max. DeepVia coverage ratio for any 500.0 x 500.0 µm² chip area [%] = 10.00") +end + + +if $sanityRules + -> do + BiWind.dup + end.().output("forbidden.BiWind", "Forbidden drawn layer BiWind on GDS layer 3/0 = 3/0") + -> do + PEmWind.dup + end.().output("forbidden.PEmWind", "Forbidden drawn layer PEmWind on GDS layer 11/0 = 11/0") + -> do + BasPoly.dup + end.().output("forbidden.BasPoly", "Forbidden drawn layer BasPoly on GDS layer 13/0 = 13/0") + -> do + DeepCo.dup + end.().output("forbidden.DeepCo", "Forbidden drawn layer DeepCo on GDS layer 35/0 = 35/0") + -> do + PEmPoly.dup + end.().output("forbidden.PEmPoly", "Forbidden drawn layer PEmPoly on GDS layer 53/0 = 53/0") + -> do + EmPoly.dup + end.().output("forbidden.EmPoly", "Forbidden gen./drawn layer EmPoly on GDS layer 53/0 = 53/0") + -> do + LDMOS.dup + end.().output("forbidden.LDMOS", "Forbidden drawn layer LDMOS on GDS layer 57/0 = 57/0") + -> do + PBiWind.dup + end.().output("forbidden.PBiWind", "Forbidden drawn layer PBiWind on GDS layer 58/0 = 58/0") + -> do + Flash.dup + end.().output("forbidden.Flash", "Forbidden drawn layer Flash on GDS layer 71/0 = 71/0") + -> do + ColWind.dup + end.().output("forbidden.ColWind", "Forbidden drawn layer ColWind on GDS layer 139/0 = 139/0") +end + + +if $offGrid + -> do + NWell.ongrid(5) + end.().output("OffGrid.NWell", "NWell is off-grid") + -> do + PWell.ongrid(5) + end.().output("OffGrid.PWell", "PWell is off-grid") + -> do + PWell_block.ongrid(5) + end.().output("OffGrid.PWell_block", "PWell_block is off-grid") + -> do + nBuLay.ongrid(5) + end.().output("OffGrid.nBuLay", "nBuLay is off-grid") + -> do + nBuLay_block.ongrid(5) + end.().output("OffGrid.nBuLay_block", "nBuLay_block is off-grid") + -> do + Activ.ongrid(5) + end.().output("OffGrid.Activ", "Activ is off-grid") + -> do + ThickGateOx.ongrid(5) + end.().output("OffGrid.ThickGateOx", "ThickGateOx is off-grid") + -> do + Activ_filler.ongrid(5) + end.().output("OffGrid.Activ_filler", "Activ_filler is off-grid") + -> do + GatPoly_filler.ongrid(5) + end.().output("OffGrid.GatPoly_filler", "GatPoly_filler is off-grid") + -> do + GatPoly.ongrid(5) + end.().output("OffGrid.GatPoly", "GatPoly is off-grid") + -> do + pSD.ongrid(5) + end.().output("OffGrid.pSD", "pSD is off-grid") + -> do + nSD.ongrid(5) + end.().output("OffGrid.nSD", "nSD is off-grid") + -> do + nSD_block.ongrid(5) + end.().output("OffGrid.nSD_block", "nSD_block is off-grid") + -> do + EXTBlock.ongrid(5) + end.().output("OffGrid.EXTBlock", "EXTBlock is off-grid") + -> do + SalBlock.ongrid(5) + end.().output("OffGrid.SalBlock", "SalBlock is off-grid") + -> do + Cont.ongrid(5) + end.().output("OffGrid.Cont", "Cont is off-grid") + -> do + Activ_nofill.ongrid(5) + end.().output("OffGrid.Activ_nofill", "Activ_nofill is off-grid") + -> do + GatPoly_nofill.ongrid(5) + end.().output("OffGrid.GatPoly_nofill", "GatPoly_nofill is off-grid") + -> do + Metal1.ongrid(5) + end.().output("OffGrid.Metal1", "Metal1 is off-grid") + -> do + Via1.ongrid(5) + end.().output("OffGrid.Via1", "Via1 is off-grid") + -> do + Metal2.ongrid(5) + end.().output("OffGrid.Metal2", "Metal2 is off-grid") + -> do + Via2.ongrid(5) + end.().output("OffGrid.Via2", "Via2 is off-grid") + -> do + Metal3.ongrid(5) + end.().output("OffGrid.Metal3", "Metal3 is off-grid") + -> do + Via3.ongrid(5) + end.().output("OffGrid.Via3", "Via3 is off-grid") + -> do + Metal4.ongrid(5) + end.().output("OffGrid.Metal4", "Metal4 is off-grid") + -> do + Via4.ongrid(5) + end.().output("OffGrid.Via4", "Via4 is off-grid") + -> do + Metal5.ongrid(5) + end.().output("OffGrid.Metal5", "Metal5 is off-grid") + -> do + MIM.ongrid(5) + end.().output("OffGrid.MIM", "MIM is off-grid") + -> do + Vmim.ongrid(5) + end.().output("OffGrid.Vmim", "Vmim is off-grid") + -> do + TopVia1.ongrid(5) + end.().output("OffGrid.TopVia1", "TopVia1 is off-grid") + -> do + TopMetal1.ongrid(5) + end.().output("OffGrid.TopMetal1", "TopMetal1 is off-grid") + -> do + TopVia2.ongrid(5) + end.().output("OffGrid.TopVia2", "TopVia2 is off-grid") + -> do + TopMetal2.ongrid(5) + end.().output("OffGrid.TopMetal2", "TopMetal2 is off-grid") + -> do + Passiv.ongrid(5) + end.().output("OffGrid.Passiv", "Passiv is off-grid") + -> do + Metal1_filler.ongrid(5) + end.().output("OffGrid.Metal1_filler", "Metal1_filler is off-grid") + -> do + Metal2_filler.ongrid(5) + end.().output("OffGrid.Metal2_filler", "Metal2_filler is off-grid") + -> do + Metal3_filler.ongrid(5) + end.().output("OffGrid.Metal3_filler", "Metal3_filler is off-grid") + -> do + Metal4_filler.ongrid(5) + end.().output("OffGrid.Metal4_filler", "Metal4_filler is off-grid") + -> do + Metal5_filler.ongrid(5) + end.().output("OffGrid.Metal5_filler", "Metal5_filler is off-grid") + -> do + TopMetal1_filler.ongrid(5) + end.().output("OffGrid.TopMetal1_filler", "TopMetal1_filler is off-grid") + -> do + TopMetal2_filler.ongrid(5) + end.().output("OffGrid.TopMetal2_filler", "TopMetal2_filler is off-grid") + -> do + Metal1_nofill.ongrid(5) + end.().output("OffGrid.Metal1_nofill", "Metal1_nofill is off-grid") + -> do + Metal2_nofill.ongrid(5) + end.().output("OffGrid.Metal2_nofill", "Metal2_nofill is off-grid") + -> do + Metal3_nofill.ongrid(5) + end.().output("OffGrid.Metal3_nofill", "Metal3_nofill is off-grid") + -> do + Metal4_nofill.ongrid(5) + end.().output("OffGrid.Metal4_nofill", "Metal4_nofill is off-grid") + -> do + Metal5_nofill.ongrid(5) + end.().output("OffGrid.Metal5_nofill", "Metal5_nofill is off-grid") + -> do + TopMetal1_nofill.ongrid(5) + end.().output("OffGrid.TopMetal1_nofill", "TopMetal1_nofill is off-grid") + -> do + TopMetal2_nofill.ongrid(5) + end.().output("OffGrid.TopMetal2_nofill", "TopMetal2_nofill is off-grid") + -> do + NoMetFiller.ongrid(5) + end.().output("OffGrid.NoMetFiller", "NoMetFiller is off-grid") + -> do + Metal1_slit.ongrid(5) + end.().output("OffGrid.Metal1_slit", "Metal1_slit is off-grid") + -> do + Metal2_slit.ongrid(5) + end.().output("OffGrid.Metal2_slit", "Metal2_slit is off-grid") + -> do + Metal3_slit.ongrid(5) + end.().output("OffGrid.Metal3_slit", "Metal3_slit is off-grid") + -> do + Metal4_slit.ongrid(5) + end.().output("OffGrid.Metal4_slit", "Metal4_slit is off-grid") + -> do + Metal5_slit.ongrid(5) + end.().output("OffGrid.Metal5_slit", "Metal5_slit is off-grid") + -> do + TopMetal1_slit.ongrid(5) + end.().output("OffGrid.TopMetal1_slit", "TopMetal1_slit is off-grid") + -> do + TopMetal2_slit.ongrid(5) + end.().output("OffGrid.TopMetal2_slit", "TopMetal2_slit is off-grid") + -> do + EdgeSeal.ongrid(5) + end.().output("OffGrid.EdgeSeal", "EdgeSeal is off-grid") + -> do + EmWind.ongrid(5) + end.().output("OffGrid.EmWind", "EmWind is off-grid") + -> do + dfpad.ongrid(5) + end.().output("OffGrid.dfpad", "dfpad is off-grid") + -> do + Polimide.ongrid(5) + end.().output("OffGrid.Polimide", "Polimide is off-grid") + -> do + TRANS.ongrid(5) + end.().output("OffGrid.TRANS", "TRANS is off-grid") + -> do + IND.ongrid(5) + end.().output("OffGrid.IND", "IND is off-grid") + -> do + RES.ongrid(5) + end.().output("OffGrid.RES", "RES is off-grid") + -> do + RFMEM.ongrid(5) + end.().output("OffGrid.RFMEM", "RFMEM is off-grid") + -> do + Recog_diode.ongrid(5) + end.().output("OffGrid.Recog_diode", "Recog_diode is off-grid") + -> do + Recog_esd.ongrid(5) + end.().output("OffGrid.Recog_esd", "Recog_esd is off-grid") + -> do + DigiBnd.ongrid(5) + end.().output("OffGrid.DigiBnd", "DigiBnd is off-grid") + -> do + DigiSub.ongrid(5) + end.().output("OffGrid.DigiSub", "DigiSub is off-grid") + -> do + SRAM.ongrid(5) + end.().output("OffGrid.SRAM", "SRAM is off-grid") + -> do + dfpad_pillar.ongrid(5) + end.().output("OffGrid.dfpad_pillar", "dfpad_pillar is off-grid") + -> do + dfpad_sbump.ongrid(5) + end.().output("OffGrid.dfpad_sbump", "dfpad_sbump is off-grid") + -> do + DeepVia.ongrid(5) + end.().output("OffGrid.DeepVia", "DeepVia is off-grid") + -> do + LBE.ongrid(5) + end.().output("OffGrid.LBE", "LBE is off-grid") + -> do + PolyRes.ongrid(5) + end.().output("OffGrid.PolyRes", "PolyRes is off-grid") +end + +puts("Number of DRC errors: #{$drc_error_count}") + + diff --git a/flow/platforms/ihp-sg13g2/drc/sg13g2_minimal.lydrc b/flow/platforms/ihp-sg13g2/drc/sg13g2_minimal.lydrc new file mode 100644 index 0000000000..89de48a440 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/drc/sg13g2_minimal.lydrc @@ -0,0 +1,1137 @@ + + + + + + drc + + + + false + false + + true + drc_scripts + tools_menu.drc.end + dsl + drc-dsl-xml + # Supported variables that can be set using "-rd <name>=<value>" on the command line: +# log_file - path to the log file [default: no log file] +# in_gds - path to the GDS layout to check (required in batch mode) +# cell - name of the cell to check +# report_file - path to the report database [default: sg13g2_minimal.lyrdb in the script directory] + +# to set logfile: -rd logfile="sg13g2_minimal.log" +if $log_file + log_file($log_file) +end + +application = RBA::Application.instance +main_window = application.main_window +if main_window and not $in_gds + curr_layout_view = main_window.current_view() + unless curr_layout_view + layout_path = RBA::FileDialog::ask_open_file_name("Chose your layout file.", ".", "GDSII files (*.GDS *.gds *.GDS.gz *.gds.gz *.GDS2 *.gds2 *.GDS2.gz *.gds2.gz);; All files (*)") + unless layout_path + return + end + main_window.load_layout(layout_path, 1) + curr_layout_view = main_window.current_view() + end + active_layout = RBA::CellView::active.layout + active_cellname = RBA::CellView::active.cell_name + source(active_layout, active_cellname) +else + log("DRC: batch mode") + # to set input layout: -rd in_gds="path to GDS file" + # to set cell: -rd cell="topcell" + if $cell + active_cellname = $cell + log("Active cell: " + active_cellname) + source($in_gds, active_cellname) + active_layout = source.layout + else + source($in_gds) + active_layout = source.layout + active_cellname = source.cell_name + end +end + +unless active_layout or $in_gds + raise("layout file must be defined on command line or via 'in_gds' script variable") +end + +if active_layout.dbu != 0.001 + puts "WARNING: Layout dbu value (" + active_layout.dbu.to_s + " ) deviates from rule file dbu value (0.001). This will scale the layout and may not be intended." +end + +report_file = __dir__ + "/sg13g2_minimal.lyrdb" +# to set report file: -rd report_file="sg13g2_minimal.lyrdb" +if $report_file + report_file = File.expand_path($report_file) +end + +report("design rules: sg13g2_minimal | layout cell: " + active_cellname, report_file) + +deep + +$drc_error_count = 0 + +class DRC::DRCLayer + unless method_defined?(:original_output) + alias_method :original_output, :output + end + + def output(*args) + count = self.count() + $drc_error_count += count + puts("Rule %s: %d error(s)" % [args[0], count]) + original_output(*args) + end +end + +# Initial definitions of control flow variables +# Strings from the command line have to be converted +if defined? $density + $density = $density.to_s.downcase == "true" +else + $density = true +end +if defined? $sanityRules + $sanityRules = $sanityRules.to_s.downcase == "true" +else + $sanityRules = true +end + +class DRC::DRCEngine + def find_intersecting_edges_errors(dbu_value, + error_edge_pairs_90, + error_edge_pairs_180, + inverse_error_edge_pairs_90 = nil, + inverse_error_edge_pairs_180 = nil, + options = {}) + consider_intersecting_edges = options.fetch(:consider_intersecting_edges, false) + consider_touch_points = options.fetch(:consider_touch_points, false) + ignore_non_axis_aligned_edges = options.fetch(:ignore_non_axis_aligned_edges, false) + min_angle = options.fetch(:min_angle, 0) + max_angle = options.fetch(:max_angle, 90) + include_min_angle = options.fetch(:include_min_angle, true) + include_max_angle = options.fetch(:include_max_angle, false) + area_of_right_angle = dbu_value**2/2 + errors_ep = RBA::EdgePairs::new() + touch_point_errors_ep = RBA::EdgePairs::new() + intersecting_edges_errors_ep = RBA::EdgePairs::new() + intersecting_edges_error_candidates = Hash.new() + no_touch_point_error = Hash.new() + error_edge_pairs_90.data.each do |edge_pair| + ip = nil + if edge_pair.first.p1 == edge_pair.second.p1 or + edge_pair.first.p1 == edge_pair.second.p2 + ip = edge_pair.first.p1 + elsif edge_pair.first.p2 == edge_pair.second.p1 or + edge_pair.first.p2 == edge_pair.second.p2 + ip = edge_pair.first.p2 + else + ip = edge_pair.first.intersection_point(edge_pair.second) + end + if ip + intersecting_edges_error_candidates[ip] = edge_pair + if !edge_pair.first.is_degenerate? and !edge_pair.second.is_degenerate? + if (edge_pair.first.contains?(edge_pair.second.p1) and + edge_pair.first.contains?(edge_pair.second.p2)) or + (edge_pair.second.contains?(edge_pair.first.p1) and + edge_pair.second.contains?(edge_pair.first.p2)) + no_touch_point_error[ip] = true + end + end + end + end + if consider_intersecting_edges or consider_touch_points + touch_point_candidates = Hash.new() + touch_point_errors = Hash.new() + if inverse_error_edge_pairs_90 and inverse_error_edge_pairs_180 + (inverse_error_edge_pairs_90 + inverse_error_edge_pairs_180).data.each do |edge_pair| + ip = edge_pair.first.intersection_point(edge_pair.second) + if ip + if touch_point_candidates[ip] + touch_point_errors[ip] = true + touch_point_candidates.delete(ip) + elsif !no_touch_point_error[ip] + touch_point_candidates[ip] = edge_pair + end + end + end + end + touch_point_candidates = Hash.new() + (error_edge_pairs_90 + error_edge_pairs_180).data.each do |edge_pair| + ip = nil + if edge_pair.first.p1 == edge_pair.second.p1 or + edge_pair.first.p1 == edge_pair.second.p2 + ip = edge_pair.first.p1 + elsif edge_pair.first.p2 == edge_pair.second.p1 or + edge_pair.first.p2 == edge_pair.second.p2 + ip = edge_pair.first.p2 + end + if ip + if edge_pair.area == area_of_right_angle or max_angle == 180 + intersecting_edges_error_candidates[ip] = edge_pair + end + if touch_point_errors[ip] + touch_point_errors_ep.insert(edge_pair) + intersecting_edges_error_candidates.delete(ip) + elsif touch_point_candidates[ip] + touch_point_errors_ep.insert(edge_pair) + touch_point_errors_ep.insert(touch_point_candidates[ip]) + touch_point_candidates.delete(ip) + intersecting_edges_error_candidates.delete(ip) + elsif !no_touch_point_error[ip] + touch_point_candidates[ip] = edge_pair + end + end + end + if consider_intersecting_edges + intersecting_edges_errors_ep = RBA::EdgePairs::new(intersecting_edges_error_candidates.values) + if max_angle != 180 + intersecting_edges_errors_ep = intersecting_edges_errors_ep.with_internal_angle(min_angle, max_angle, false, include_min_angle, include_max_angle) + end + errors_ep = errors_ep + intersecting_edges_errors_ep + end + end + if ignore_non_axis_aligned_edges + errors_ep = errors_ep.with_angle_both(RBA::Edges::OrthoEdges, false) + end + if consider_touch_points + errors_ep = errors_ep + touch_point_errors_ep + end + return DRC::DRCLayer::new(self, errors_ep) + end +end + +class DRC::DRCLayer + def ext_and(other) + self_min_coherence_state = self.data.min_coherence? + other_min_coherence_state = other.data.min_coherence? + self.data.min_coherence = true + other.data.min_coherence = true + output_layer = self & other + self.data.min_coherence = self_min_coherence_state + other.data.min_coherence = other_min_coherence_state + return output_layer + end + + def ext_with_area(constraint) + lower_bound = nil + upper_bound = nil + output_layer = nil + self_min_coherence_state = self.data.min_coherence? + self.data.min_coherence = true + constraint.each do |expression| + relation = expression[0] + value = expression[1] + if relation == ">" + lower_bound = value + 1e-6 + elsif relation == "<" + upper_bound = value + elsif relation == "==" + output_layer = self.with_area(value) + elsif relation == "!=" + output_layer = self.without_area(value) + elsif relation == ">=" + lower_bound = value + elsif relation == "<=" + upper_bound = value + 1e-6 + else + raise "invalid expression" + end + end + if lower_bound or upper_bound + output_layer = self.with_area(lower_bound, upper_bound) + end + self.data.min_coherence = self_min_coherence_state + return output_layer + end + + def ext_constraint_satisfied(value, constraint) + output_bool = true + constraint.each do |expression| + if expression[0] == ">" + output_bool = output_bool && (value > expression[1]) + elsif expression[0] == "<" + output_bool = output_bool && (value < expression[1]) + elsif expression[0] == "==" + output_bool = output_bool && (value == expression[1]) + elsif expression[0] == "!=" + output_bool = output_bool && (value != expression[1]) + elsif expression[0] == ">=" + output_bool = output_bool && (value >= expression[1]) + elsif expression[0] == "<=" + output_bool = output_bool && (value <= expression[1]) + else + raise "invalid expression" + end + end + return output_bool + end + + def ext_covering(other) + self_min_coherence_state = self.data.min_coherence? + other_min_coherence_state = other.data.min_coherence? + self.data.min_coherence = true + other.data.min_coherence = true + output_layer = self.covering(other.inside(self)) + self.data.min_coherence = self_min_coherence_state + other.data.min_coherence = other_min_coherence_state + return output_layer + end + + def ext_separation_at_intersecting_edges(other, + value, + metric=RBA::Region::Euclidian, + consider_intersecting_edges=false, + consider_touch_points=false, + ignore_non_axis_aligned_edges=false, + min_angle=0, + max_angle=90, + include_min_angle=true, + include_max_angle=false, + polygons=false) + self_min_coherence_state = self.data.min_coherence? + other_min_coherence_state = other.data.min_coherence? + self.data.min_coherence = true + other.data.min_coherence = true + if metric.is_a?(DRC::DRCMetrics) + metric = metric.value + end + if value.is_a? Float + dbu_value = (value/1.dbu).round + else + dbu_value = value + end + error_edge_pairs_90 = DRC::DRCLayer::new(@engine, + self.data.separation_check(other.data, dbu_value, false, metric, 90, 1, nil)) + error_edge_pairs_180 = DRC::DRCLayer::new(@engine, + self.data.separation_check(other.data, dbu_value, false, metric, 180, nil, 1)) + width_error_edge_pairs_90 = DRC::DRCLayer::new(@engine, + self.data.width_check(dbu_value, false, metric, 90, 1, nil) + + other.data.width_check(dbu_value, false, metric, 90, 1, nil)) + width_error_edge_pairs_180 = DRC::DRCLayer::new(@engine, + self.data.width_check(dbu_value, false, metric, 180, nil, 1) + + other.data.width_check(dbu_value, false, metric, 180, nil, 1)) + separation_errors = @engine.find_intersecting_edges_errors( + dbu_value, + error_edge_pairs_90, + error_edge_pairs_180, + width_error_edge_pairs_90, + width_error_edge_pairs_180, + { + consider_intersecting_edges: consider_intersecting_edges, + consider_touch_points: consider_touch_points, + ignore_non_axis_aligned_edges: ignore_non_axis_aligned_edges, + min_angle: min_angle, + max_angle: max_angle, + include_min_angle: include_min_angle, + include_max_angle: include_max_angle + } + ) + self.data.min_coherence = self_min_coherence_state + other.data.min_coherence = other_min_coherence_state + if polygons + return separation_errors.polygons.merge(true, 0) + else + return separation_errors + end + end + + def ext_fast_separation(other, + value, + metric: @engine.euclidian, + consider_intersecting_edges: true, + consider_touch_points: true, + ignore_non_axis_aligned_edges: false, + min_angle: 0, + max_angle: 90, + include_min_angle: true, + include_max_angle: false, + polygon_output: false) + self_min_coherence_state = self.data.min_coherence? + other_min_coherence_state = other.data.min_coherence? + self.data.min_coherence = true + other.data.min_coherence = true + output_layer = self.separation(other, value, metric, @engine.angle_limit(max_angle)) + if !consider_intersecting_edges and !consider_touch_points + output_layer = output_layer.with_distance(1, nil) + if ignore_non_axis_aligned_edges + output_layer = output_layer.with_angle(@engine.ortho, @engine.both) + end + elsif consider_intersecting_edges ^ consider_touch_points + intersecting_edges_errors = output_layer.with_distance(0).edges + candidate_layer1 = self.interacting(intersecting_edges_errors) + candidate_layer2 = other.interacting(intersecting_edges_errors) + output_layer = output_layer.with_distance(1, nil) + output_layer = output_layer + candidate_layer1.ext_separation_at_intersecting_edges( + candidate_layer2, + value, + metric, + consider_intersecting_edges, + consider_touch_points, + ignore_non_axis_aligned_edges, + min_angle, + max_angle, + include_min_angle, + include_max_angle, + false) + end + self.data.min_coherence = self_min_coherence_state + other.data.min_coherence = other_min_coherence_state + if polygon_output + return output_layer.polygons.merge(true, 0) + else + return output_layer + end + end + + def ext_not(other) + self_min_coherence_state = self.data.min_coherence? + other_min_coherence_state = other.data.min_coherence? + self.data.min_coherence = true + other.data.min_coherence = true + output_layer = self - other + self.data.min_coherence = self_min_coherence_state + other.data.min_coherence = other_min_coherence_state + return output_layer + end + + def ext_or(other, *further_layers) + self_min_coherence_state = self.data.min_coherence? + other_min_coherence_state = other.data.min_coherence? + self.data.min_coherence = true + other.data.min_coherence = true + output_layer = self.join(other) + further_layers.each do |further_layer| + further_layer_min_coherence_state = further_layer.data.min_coherence? + further_layer.data.min_coherence = true + output_layer = output_layer.join(further_layer) + further_layer.data.min_coherence = further_layer_min_coherence_state + end + self.data.min_coherence = self_min_coherence_state + other.data.min_coherence = other_min_coherence_state + return output_layer + end + + def ext_rectangles(axis_aligned = false, use_bbox = false, constraint1 = nil, constraint2 = nil, aspect_ratio_constraint = nil, inverted: false) + self_min_coherence_state = self.data.min_coherence? + self.data.min_coherence = true + if ( ( constraint1 && ( !constraint2 || constraint1.length() > 1 || constraint1[0][0] != "==") ) || + ( constraint2 && ( constraint2.length() > 1 || constraint2[0][0] != "==" ) ) || + ( constraint1 && constraint2 && constraint1[0][1] != constraint2[0][1] ) ) + raise "ext_rectangle: unsupported options" + end + square = constraint1 ? true : false + shape_filter = + if use_bbox + @engine.extents + elsif axis_aligned + @engine.rectangles + else + @engine.if_all((@engine.corners == 270).count == 4, @engine.corners.count == 4) + end + if square + if use_bbox + shape_filter = @engine.if_all((@engine.extents.length == constraint1[0][1]).count == 4) + else + square_filter = (@engine.length == constraint1[0][1]).count == 4 + shape_filter = @engine.if_all(shape_filter, square_filter) + end + end + if inverted + output_layer = self.drc(! shape_filter) + else + output_layer = self.drc(shape_filter) + end + self.data.min_coherence = self_min_coherence_state + return output_layer + end + + def ext_space_at_intersecting_edges(value, + metric=RBA::Region::Euclidian, + consider_intersecting_edges=false, + consider_touch_points=false, + ignore_non_axis_aligned_edges=false, + min_angle=0, + max_angle=90, + include_min_angle=true, + include_max_angle=false, + polygons=false) + self_min_coherence_state = self.data.min_coherence? + self.data.min_coherence = true + if metric.is_a?(DRC::DRCMetrics) + metric = metric.value + end + if value.is_a? Float + dbu_value = (value/1.dbu).round + else + dbu_value = value + end + error_edge_pairs_90 = DRC::DRCLayer::new(@engine, self.data.space_check(dbu_value, false, metric, 90, 1, nil)) + error_edge_pairs_180 = DRC::DRCLayer::new(@engine, self.data.space_check(dbu_value, false, metric, 180, nil, 1)) + width_error_edge_pairs_90 = DRC::DRCLayer::new(@engine, self.data.width_check(dbu_value, false, metric, 90, 1, nil)) + width_error_edge_pairs_180 = DRC::DRCLayer::new(@engine, self.data.width_check(dbu_value, false, metric, 180, nil, 1)) + space_errors = @engine.find_intersecting_edges_errors( + dbu_value, + error_edge_pairs_90, + error_edge_pairs_180, + width_error_edge_pairs_90, + width_error_edge_pairs_180, + { + consider_intersecting_edges: consider_intersecting_edges, + consider_touch_points: consider_touch_points, + ignore_non_axis_aligned_edges: ignore_non_axis_aligned_edges, + min_angle: min_angle, + max_angle: max_angle, + include_min_angle: include_min_angle, + include_max_angle: include_max_angle + } + ) + self.data.min_coherence = self_min_coherence_state + if polygons + return space_errors.polygons.merge(true, 0) + else + return space_errors + end + end + + def ext_fast_space(value, + metric: @engine.euclidian, + consider_intersecting_edges: true, + consider_touch_points: true, + ignore_non_axis_aligned_edges: false, + min_angle: 0, + max_angle: 90, + include_min_angle: true, + include_max_angle: false, + polygon_output: false) + self_min_coherence_state = self.data.min_coherence? + self.data.min_coherence = true + output_layer = self.space(value, metric, @engine.angle_limit(max_angle)) + if !consider_intersecting_edges and !consider_touch_points + output_layer = output_layer.with_distance(1, nil) + if ignore_non_axis_aligned_edges + output_layer = output_layer.with_angle(@engine.ortho, @engine.both) + end + elsif consider_intersecting_edges ^ consider_touch_points + candidate_layer = self.interacting(output_layer.with_distance(0).edges) + output_layer = output_layer.with_distance(1, nil) + output_layer = output_layer + candidate_layer.ext_space_at_intersecting_edges( + value, + metric, + consider_intersecting_edges, + consider_touch_points, + ignore_non_axis_aligned_edges, + min_angle, + max_angle, + include_min_angle, + include_max_angle, + false) + end + self.data.min_coherence = self_min_coherence_state + if polygon_output + return output_layer.polygons.merge(true, 0) + else + return output_layer + end + end + + def ext_width_at_intersecting_edges(value, + metric=RBA::Region::Euclidian, + consider_intersecting_edges=false, + consider_touch_points=false, + ignore_non_axis_aligned_edges=false, + min_angle=0, + max_angle=90, + include_min_angle=true, + include_max_angle=false, + polygons=false) + self_min_coherence_state = self.data.min_coherence? + self.data.min_coherence = true + if metric.is_a?(DRC::DRCMetrics) + metric = metric.value + end + if value.is_a? Float + dbu_value = (value/1.dbu).round + else + dbu_value = value + end + error_edge_pairs_90 = DRC::DRCLayer::new(@engine, self.data.width_check(dbu_value, false, metric, 90, 1, nil)) + error_edge_pairs_180 = DRC::DRCLayer::new(@engine, self.data.width_check(dbu_value, false, metric, 180, nil, 1)) + space_error_edge_pairs_90 = DRC::DRCLayer::new(@engine, self.data.space_check(dbu_value, false, metric, 90, 1, nil)) + space_error_edge_pairs_180 = DRC::DRCLayer::new(@engine, self.data.space_check(dbu_value, false, metric, 180, nil, 1)) + width_errors = @engine.find_intersecting_edges_errors( + dbu_value, + error_edge_pairs_90, + error_edge_pairs_180, + space_error_edge_pairs_90, + space_error_edge_pairs_180, + { + consider_intersecting_edges: consider_intersecting_edges, + consider_touch_points: consider_touch_points, + ignore_non_axis_aligned_edges: ignore_non_axis_aligned_edges, + min_angle: min_angle, + max_angle: max_angle, + include_min_angle: include_min_angle, + include_max_angle: include_max_angle + } + ) + self.data.min_coherence = self_min_coherence_state + if polygons + return width_errors.polygons.merge(true, 0) + else + return width_errors + end + end + + def ext_fast_width(value, + metric: @engine.euclidian, + consider_intersecting_edges: true, + consider_touch_points: true, + ignore_non_axis_aligned_edges: false, + min_angle: 0, + max_angle: 90, + include_min_angle: true, + include_max_angle: false, + polygon_output: false) + if self.polygons? + self_min_coherence_state = self.data.min_coherence? + self.data.min_coherence = true + self_edges = self.edges + self.data.min_coherence = self_min_coherence_state + else + self_edges = self + end + output_layer = self_edges.width(value, metric, @engine.angle_limit(max_angle)) + if !consider_intersecting_edges and !consider_touch_points + output_layer = output_layer.with_distance(1, nil) + if ignore_non_axis_aligned_edges + output_layer = output_layer.with_angle(@engine.ortho, @engine.both) + end + elsif consider_intersecting_edges ^ consider_touch_points + candidate_layer = self.interacting(output_layer.with_distance(0).edges) + output_layer = output_layer.with_distance(1, nil) + output_layer = output_layer + candidate_layer.ext_width_at_intersecting_edges( + value, + metric, + consider_intersecting_edges, + consider_touch_points, + ignore_non_axis_aligned_edges, + min_angle, + max_angle, + include_min_angle, + include_max_angle, + false) + end + if polygon_output + return output_layer.polygons.merge(true, 0) + else + return output_layer + end + end + + def ext_interacting_with_text(text_layer, text) + if text_layer.is_a? Integer + text_layer = @engine.labels(text_layer) + end + initial_merged_semantics = self.data.merged_semantics? + self.data.merged_semantics = false + result = self.interacting(text_layer.texts(text)) + self.data.merged_semantics = initial_merged_semantics + return result + end + + def ext_with_density(range, *args) + if self.is_empty? + return DRC::DRCLayer::new(@engine, RBA::Region::new()) + end + if self.is_merged? + merged_layer = self + else + merged_layer = self.merged(true, 0) + end + origin = 'cc' + tile_size = nil + tile_step = nil + arguments = [range] + args.each do |a| + if a.is_a?(DRC::DRCTileSize) + tile_size = a + arguments.push(tile_size) + elsif a.is_a?(DRC::DRCTileStep) + tile_step = a + arguments.push(tile_step) + elsif a.is_a?(String) + origin = a + else + raise "argument error" + end + end + bbox = @engine.extent.bbox + if origin == 'll' + origin_x = bbox.left + origin_y = bbox.bottom + if tile_size and tile_step and (tile_size.get[0] != tile_step.get[0] or tile_size.get[1] != tile_step.get[1]) + origin_x = bbox.left + tile_step.get[0]/2 + origin_y = bbox.bottom + tile_step.get[1]/2 + end + tile_origin = DRC::DRCTileOrigin::new(origin_x, origin_y) + arguments.push(tile_origin) + elsif origin != 'cc' + raise "Unknown origin: 'cc' or 'll' expected" + end + if tile_size + boundary_layer = DRC::DRCLayer::new(@engine, RBA::Region::new(bbox.to_itype(@engine.dbu))) + tile_boundary = DRC::DRCTileBoundary::new(boundary_layer) + return merged_layer.with_density(*arguments, tile_boundary, @engine.padding_ignore) + else + tile_size = DRC::DRCTileSize::new(bbox.width, bbox.height) + tile_count = DRC::DRCTileCount::new(1,2) + enlarged_bbox = bbox.enlarged(1.1).to_itype(@engine.dbu) + boundary_layer = DRC::DRCLayer::new(@engine, RBA::Region::new(enlarged_bbox)) + tile_boundary = DRC::DRCTileBoundary::new(boundary_layer) + result = merged_layer.with_density(*arguments, tile_size, tile_count, tile_boundary, @engine.padding_ignore) + return result.raw.overlapping(DRC::DRCLayer::new(@engine, RBA::Region::new(bbox.to_itype(@engine.dbu)))) + end + end +end + +Activ = source.polygons("1/0") +Activ_pin = source.polygons("1/2") +Activ_filler = source.polygons("1/22") +BiWind = source.polygons("3/0") +GatPoly = source.polygons("5/0") +GatPoly_pin = source.polygons("5/2") +GatPoly_filler = source.polygons("5/22") +Cont = source.polygons("6/0") +Metal1 = source.polygons("8/0") +Metal1_pin = source.polygons("8/2") +Metal1_filler = source.polygons("8/22") +Metal1_slit = source.polygons("8/24") +Passiv = source.polygons("9/0") +Metal2 = source.polygons("10/0") +Metal2_pin = source.polygons("10/2") +Metal2_filler = source.polygons("10/22") +Metal2_slit = source.polygons("10/24") +BasPoly = source.polygons("13/0") +Via1 = source.polygons("19/0") +SRAM = source.polygons("25/0") +TRANS = source.polygons("26/0") +Via2 = source.polygons("29/0") +Metal3 = source.polygons("30/0") +Metal3_pin = source.polygons("30/2") +Metal3_filler = source.polygons("30/22") +Metal3_slit = source.polygons("30/24") +DeepCo = source.polygons("35/0") +EdgeSeal = source.polygons("39/0") +ThickGateOx = source.polygons("44/0") +Via3 = source.polygons("49/0") +Metal4 = source.polygons("50/0") +Metal4_pin = source.polygons("50/2") +Metal4_filler = source.polygons("50/22") +Metal4_slit = source.polygons("50/24") +EmPoly = source.polygons("55/0") +TEXT_0 = source.labels("63/0") +Via4 = source.polygons("66/0") +Metal5 = source.polygons("67/0") +Metal5_pin = source.polygons("67/2") +Metal5_filler = source.polygons("67/22") +Metal5_slit = source.polygons("67/24") +TopVia1 = source.polygons("125/0") +TopMetal1 = source.polygons("126/0") +TopMetal1_pin = source.polygons("126/2") +TopMetal1_filler = source.polygons("126/22") +TopMetal1_slit = source.polygons("126/24") +Vmim = source.polygons("129/0") +TopVia2 = source.polygons("133/0") +TopMetal2 = source.polygons("134/0") +TopMetal2_pin = source.polygons("134/2") +TopMetal2_filler = source.polygons("134/22") +TopMetal2_slit = source.polygons("134/24") +ColWind = source.polygons("139/0") +LBE = source.polygons("157/0") + +if $sanityRules + PEmWind = source.polygons("11/0") + PEmPoly = source.polygons("53/0") + LDMOS = source.polygons("57/0") + PBiWind = source.polygons("58/0") + Flash = source.polygons("71/0") +end + +Activ_Act_a = Activ.ext_fast_width(0.15.um) +Act_density = Activ.ext_or(Activ_filler) +Gat_density = GatPoly.ext_or(GatPoly_filler) +Cont_SQ = Cont.ext_rectangles(true, false, [["==", 0.16.um]], [["==", 0.16.um]], nil) +ContBar = Cont.ext_with_area([[">", (0.16*0.16).um2]]) +Act_Nsram = Activ.ext_not(SRAM) +GP_Nsram = GatPoly.ext_not(SRAM) +M1_Nsram = Metal1.ext_not(SRAM) +M2_Nsram = Metal2.ext_not(SRAM) +M3_Nsram = Metal3.ext_not(SRAM) +Via1_edgC1_out = Via1.ext_not(EdgeSeal) +Via2_edgC1_out = Via2.ext_not(EdgeSeal) +Cont_outside_EdgeSeal = Cont.outside(EdgeSeal) +ThickGateOx_TGO_f = ThickGateOx.ext_fast_width(0.86.um, consider_intersecting_edges: false, polygon_output: true) +Via3_edgC1_out = Via3.ext_not(EdgeSeal) +M4_Nsram = Metal4.ext_not(SRAM) +Via4_edgC1_out = Via4.ext_not(EdgeSeal) +M5_Nsram = Metal5.ext_not(SRAM) +TopVia1_edgC1_out = TopVia1.ext_not(EdgeSeal) +TopVia1_or_Vmim = TopVia1.ext_or(Vmim) +TopVia2_edgC1_out = TopVia2.ext_not(EdgeSeal) +M1_density = Metal1.ext_or(Metal1_filler).ext_not(Metal1_slit) +M2_density = Metal2.ext_or(Metal2_filler).ext_not(Metal2_slit) +emi2Pin = Metal2_pin.ext_and(TRANS).ext_interacting_with_text(TEXT_0, "E") +M3_density = Metal3.ext_or(Metal3_filler).ext_not(Metal3_slit) +M4_density = Metal4.ext_or(Metal4_filler).ext_not(Metal4_slit) +M5_density = Metal5.ext_or(Metal5_filler).ext_not(Metal5_slit) +TM1_density = TopMetal1.ext_or(TopMetal1_filler).ext_not(TopMetal1_slit) +TM2_density = TopMetal2.ext_or(TopMetal2_filler).ext_not(TopMetal2_slit) +GP_Nsram_Gat_a = GP_Nsram.ext_fast_width(0.13.um, consider_intersecting_edges: false, polygon_output: true) +GP_Nsram_Gat_b = GP_Nsram.ext_fast_space(0.18.um, consider_intersecting_edges: false, polygon_output: true) +transG2L = TRANS.ext_interacting_with_text(TEXT_0, "npn13G2L").ext_covering(emi2Pin) +-> do + Activ_Act_a.dup +end.().output("Act.a", "Min. Activ width = 0.15") +-> do + Act_Nsram.ext_fast_space(0.21.um) +end.().output("Act.b", "Min. Activ space or notch = 0.21") + +if $density + -> do + Act_density.ext_with_density(0.0 .. 0.35, 'll') + end.().output("AFil.g", "Min. global Activ density [%] = 35.00") + -> do + Act_density.ext_with_density(0.55 .. 1.0, 'll') + end.().output("AFil.g1", "Max. global Activ density [%] = 55.00") + -> do + Act_density.ext_with_density(0.0 .. 0.25, 'll', tile_size(800.0.um), tile_step(400.0.um)) + end.().output("AFil.g2", "Min. Activ coverage ratio for any 800 x 800 µm² chip area [%] = 25.00") + -> do + Act_density.ext_with_density(0.65 .. 1.0, 'll', tile_size(800.0.um), tile_step(400.0.um)) + end.().output("AFil.g3", "Max. Activ coverage ratio for any 800 x 800 µm² chip area [%] = 65.00") +end + +-> do + ThickGateOx_TGO_f.dup +end.().output("TGO.f", "Min. ThickGateOx width = 0.86") +-> do + GP_Nsram_Gat_a.dup +end.().output("Gat.a", "Min. GatPoly width = 0.13") +-> do + GP_Nsram_Gat_b.dup +end.().output("Gat.b", "Min. GatPoly space or notch = 0.18") +-> do + GP_Nsram.ext_fast_separation(Act_Nsram, 0.07.um) +end.().output("Gat.d", "Min. GatPoly space to Activ = 0.07") + +if $density + -> do + Gat_density.ext_with_density(0.0 .. 0.15, 'll') + end.().output("GFil.g", "Min. global GatPoly density [%] = 15.00") +end + +-> do + Cont_outside_EdgeSeal.ext_not(ContBar.ext_or(Cont_SQ)) +end.().output("Cnt.a", "Min. and max. Cont width = 0.16") +-> do + Cont_outside_EdgeSeal.ext_fast_space(0.18.um, consider_intersecting_edges: false) +end.().output("Cnt.b", "Min. Cont space = 0.18") +-> do + Metal1.ext_fast_width(0.16.um) +end.().output("M1.a", "Min. Metal1 width = 0.16") +-> do + M1_Nsram.ext_fast_space(0.18.um, consider_intersecting_edges: false, ignore_non_axis_aligned_edges: true) +end.().output("M1.b", "Min. Metal1 space or notch = 0.18") + +if $density + -> do + M1_density.ext_with_density(0.0 .. 0.35, 'll') + end.().output("M1.j", "Min. global Metal1 density [%] = 35.0") + -> do + M1_density.ext_with_density(0.6 .. 1.0, 'll') + end.().output("M1.k", "Max. global Metal1 density [%] = 60.0") +end + +-> do + Metal2.ext_fast_width(0.2.um) +end.().output("M2.a", "Min. Metal2 width = 0.20") +-> do + M2_Nsram.ext_fast_space(0.21.um, consider_intersecting_edges: false, ignore_non_axis_aligned_edges: true) +end.().output("M2.b", "Min. Metal2 space or notch = 0.21") + +if $density + -> do + M2_density.ext_with_density(0.0 .. 0.35, 'll') + end.().output("M2.j", "Min. global Metal2 density [%] = 35.00") + -> do + M2_density.ext_with_density(0.6 .. 1.0, 'll') + end.().output("M2.k", "Max. global Metal2 density [%] = 60.00") +end + +-> do + Metal3.ext_fast_width(0.2.um) +end.().output("M3.a", "Min. Metal3 width = 0.20") +-> do + M3_Nsram.ext_fast_space(0.21.um, consider_intersecting_edges: false, ignore_non_axis_aligned_edges: true) +end.().output("M3.b", "Min. Metal3 space or notch = 0.21") + +if $density + -> do + M3_density.ext_with_density(0.0 .. 0.35, 'll') + end.().output("M3.j", "Min. global Metal3 density [%] = 35.00") + -> do + M3_density.ext_with_density(0.6 .. 1.0, 'll') + end.().output("M3.k", "Max. global Metal3 density [%] = 60.00") +end + +-> do + Metal4.ext_fast_width(0.2.um) +end.().output("M4.a", "Min. Metal4 width = 0.20") +-> do + M4_Nsram.ext_fast_space(0.21.um, consider_intersecting_edges: false, ignore_non_axis_aligned_edges: true) +end.().output("M4.b", "Min. Metal4 space or notch = 0.21") + +if $density + -> do + M4_density.ext_with_density(0.0 .. 0.35, 'll') + end.().output("M4.j", "Min. global Metal4 density [%] = 35.00") + -> do + M4_density.ext_with_density(0.6 .. 1.0, 'll') + end.().output("M4.k", "Max. global Metal4 density [%] = 60.00") +end + +-> do + Metal5.ext_fast_width(0.2.um) +end.().output("M5.a", "Min. Metal5 width = 0.20") +-> do + M5_Nsram.ext_fast_space(0.21.um, consider_intersecting_edges: false, ignore_non_axis_aligned_edges: true) +end.().output("M5.b", "Min. Metal5 space or notch = 0.21") + +if $density + -> do + M5_density.ext_with_density(0.0 .. 0.35, 'll') + end.().output("M5.j", "Min. global Metal5 density [%] = 35.00") + -> do + M5_density.ext_with_density(0.6 .. 1.0, 'll') + end.().output("M5.k", "Max. global Metal5 density [%] = 60.00") + -> do + M1_density.ext_with_density(0.0 .. 0.25, 'll', tile_size(800.0.um), tile_step(400.0.um)) + end.().output("M1Fil.h", "Min. Metal1 and Metal1:filler coverage ratio for any 800 x 800 µm² chip area [%] = 25.00") + -> do + M1_density.ext_with_density(0.75 .. 1.0, 'll', tile_size(800.0.um), tile_step(400.0.um)) + end.().output("M1Fil.k", "Max. Metal1 and Metal1:filler coverage ratio for any 800 x 800 µm² chip area [%] = 75.00") + -> do + M2_density.ext_with_density(0.0 .. 0.25, 'll', tile_size(800.0.um), tile_step(400.0.um)) + end.().output("M2Fil.h", "Min. Metal2 and Metal2:filler coverage ratio for any 800 x 800 µm² chip area [%] = 25.00") + -> do + M2_density.ext_with_density(0.75 .. 1.0, 'll', tile_size(800.0.um), tile_step(400.0.um)) + end.().output("M2Fil.k", "Max. Metal2 and Metal2:filler coverage ratio for any 800 x 800 µm² chip area [%] = 75.00") + -> do + M3_density.ext_with_density(0.0 .. 0.25, 'll', tile_size(800.0.um), tile_step(400.0.um)) + end.().output("M3Fil.h", "Min. Metal3 and Metal3:filler coverage ratio for any 800 x 800 µm² chip area [%] = 25.00") + -> do + M3_density.ext_with_density(0.75 .. 1.0, 'll', tile_size(800.0.um), tile_step(400.0.um)) + end.().output("M3Fil.k", "Max. Metal3 and Metal3:filler coverage ratio for any 800 x 800 µm² chip area [%] = 75.00") + -> do + M4_density.ext_with_density(0.0 .. 0.25, 'll', tile_size(800.0.um), tile_step(400.0.um)) + end.().output("M4Fil.h", "Min. Metal4 and Metal4:filler coverage ratio for any 800 x 800 µm² chip area [%] = 25.00") + -> do + M4_density.ext_with_density(0.75 .. 1.0, 'll', tile_size(800.0.um), tile_step(400.0.um)) + end.().output("M4Fil.k", "Max. Metal4 and Metal4:filler coverage ratio for any 800 x 800 µm² chip area [%] = 75.00") + -> do + M5_density.ext_with_density(0.0 .. 0.25, 'll', tile_size(800.0.um), tile_step(400.0.um)) + end.().output("M5Fil.h", "Min. Metal5 and Metal5:filler coverage ratio for any 800 x 800 µm² chip area [%] = 25.00") + -> do + M5_density.ext_with_density(0.75 .. 1.0, 'll', tile_size(800.0.um), tile_step(400.0.um)) + end.().output("M5Fil.k", "Max. Metal5 and Metal5:filler coverage ratio for any 800 x 800 µm² chip area [%] = 75.00") +end + +-> do + Via1_edgC1_out.outside(transG2L).ext_rectangles(false, false, [["==", 0.19.um]], [["==", 0.19.um]], nil, inverted: true) +end.().output("V1.a", "Min. and max. Via1 width = 0.19") +-> do + Via1_edgC1_out.ext_fast_space(0.22.um, consider_intersecting_edges: false) +end.().output("V1.b", "Min. Via1 space = 0.22") +-> do + Via2_edgC1_out.outside(transG2L).ext_rectangles(false, false, [["==", 0.19.um]], [["==", 0.19.um]], nil, inverted: true) +end.().output("V2.a", "Min. and max. Via2 width = 0.19") +-> do + Via2_edgC1_out.ext_fast_space(0.22.um, consider_intersecting_edges: false) +end.().output("V2.b", "Min. Via2 space = 0.22") +-> do + Via3_edgC1_out.outside(transG2L).ext_rectangles(false, false, [["==", 0.19.um]], [["==", 0.19.um]], nil, inverted: true) +end.().output("V3.a", "Min. and max. Via3 width = 0.19") +-> do + Via3_edgC1_out.ext_fast_space(0.22.um, consider_intersecting_edges: false) +end.().output("V3.b", "Min. Via3 space = 0.22") +-> do + Via4_edgC1_out.outside(transG2L).ext_rectangles(false, false, [["==", 0.19.um]], [["==", 0.19.um]], nil, inverted: true) +end.().output("V4.a", "Min. and max. Via4 width = 0.19") +-> do + Via4_edgC1_out.ext_fast_space(0.22.um, consider_intersecting_edges: false) +end.().output("V4.b", "Min. Via4 space = 0.22") +-> do + TopVia1_edgC1_out.ext_or(Vmim).ext_rectangles(false, false, [["==", 0.42.um]], [["==", 0.42.um]], nil, inverted: true) +end.().output("TV1.a", "Min. and max. TopVia1 width = 0.42") +-> do + TopVia1_or_Vmim.ext_fast_space(0.42.um) +end.().output("TV1.b", "Min. TopVia1 space = 0.42") +-> do + TopMetal1.ext_fast_width(1.64.um) +end.().output("TM1.a", "Min. TopMetal1 width = 1.64") +-> do + TopMetal1.ext_fast_space(1.64.um) +end.().output("TM1.b", "Min. TopMetal1 space or notch = 1.64") + +if $density + -> do + TM1_density.ext_with_density(0.0 .. 0.25, 'll') + end.().output("TM1.c", "Min. global TopMetal1 density [%] = 25.00") + -> do + TM1_density.ext_with_density(0.7 .. 1.0, 'll') + end.().output("TM1.d", "Max. global TopMetal1 density [%] = 70.00") +end + +-> do + TopVia2_edgC1_out.ext_rectangles(false, false, [["==", 0.9.um]], [["==", 0.9.um]], nil, inverted: true) +end.().output("TV2.a", "Min. and max. TopVia2 width = 0.90") +-> do + TopVia2.ext_fast_space(1.06.um) +end.().output("TV2.b", "Min. TopVia2 space = 1.06") +-> do + TopMetal2.ext_fast_width(2.0.um) +end.().output("TM2.a", "Min. TopMetal2 width = 2.00") +-> do + TopMetal2.ext_fast_space(2.0.um) +end.().output("TM2.b", "Min. TopMetal2 space or notch = 2.00") + +if $density + -> do + TM2_density.ext_with_density(0.0 .. 0.25, 'll') + end.().output("TM2.c", "Min. global TopMetal2 density [%] = 25.00") + -> do + TM2_density.ext_with_density(0.7 .. 1.0, 'll') + end.().output("TM2.d", "Max. global TopMetal2 density [%] = 70.00") +end + +-> do + Passiv.ext_fast_width(2.1.um) +end.().output("Pas.a", "Min. Passiv width = 2.10") +-> do + Passiv.ext_fast_space(3.5.um) +end.().output("Pas.b", "Min. Passiv space or notch = 3.50") + +if $sanityRules + -> do + Activ_pin.ext_not(Activ) + end.().output("Pin.a", "Min. Activ enclosure of Activ:pin = 0.00") + -> do + GatPoly_pin.ext_not(GatPoly) + end.().output("Pin.b", "Min. GatPoly enclosure of GatPoly:pin = 0.00") + -> do + Metal1_pin.ext_not(Metal1) + end.().output("Pin.e", "Min. Metal1 enclosure of Metal1:pin = 0.00") + -> do + Metal2_pin.ext_not(Metal2) + end.().output("Pin.f.M2", "Min. Metal2 enclosure of Metal2:pin = 0.00") + -> do + Metal3_pin.ext_not(Metal3) + end.().output("Pin.f.M3", "Min. Metal3 enclosure of Metal3:pin = 0.00") + -> do + Metal4_pin.ext_not(Metal4) + end.().output("Pin.f.M4", "Min. Metal4 enclosure of Metal4:pin = 0.00") + -> do + Metal5_pin.ext_not(Metal5) + end.().output("Pin.f.M5", "Min. Metal5 enclosure of Metal5:pin = 0.00") + -> do + TopMetal1_pin.ext_not(TopMetal1) + end.().output("Pin.g", "Min. TopMetal1 enclosure of TopMetal1:pin = 0.00") + -> do + TopMetal2_pin.ext_not(TopMetal2) + end.().output("Pin.h", "Min. TopMetal2 enclosure of TopMetal2:pin = 0.00") +end + +-> do + LBE.ext_fast_width(100.0.um) +end.().output("LBE.a", "Min. LBE width = 100.00") +-> do + LBE.drc((width(projection) > 1500.0.um).polygons) +end.().output("LBE.b", "Max. LBE width = 1500.00") +-> do + LBE.ext_with_area([[">", 250000.0.um2]]) +end.().output("LBE.b1", "Max. LBE area (µm²) = 250000.00") +-> do + LBE.ext_fast_space(100.0.um, consider_intersecting_edges: false, ignore_non_axis_aligned_edges: true) +end.().output("LBE.c", "Min. LBE space or notch = 100.00") +-> (;lbe_in_seal) do + lbe_in_seal = LBE.inside(EdgeSeal.holes.merge) + lbe_in_seal.ext_fast_separation(EdgeSeal, 150.0.um, consider_intersecting_edges: false, ignore_non_axis_aligned_edges: true) +end.().output("LBE.d", "Min. LBE space to inner edge of EdgeSeal = 150.00") +-> do + LBE.with_holes.dup +end.().output("LBE.h", "No LBE ring allowed") + +if $density + -> do + LBE.ext_with_density(0.2 .. 1.0, 'll') + end.().output("LBE.i", "Max. global LBE density [%] = 20.00") +end + + +if $sanityRules + -> do + BiWind.dup + end.().output("forbidden.BiWind", "Forbidden drawn layer BiWind on GDS layer 3/0 = 3/0") + -> do + PEmWind.dup + end.().output("forbidden.PEmWind", "Forbidden drawn layer PEmWind on GDS layer 11/0 = 11/0") + -> do + BasPoly.dup + end.().output("forbidden.BasPoly", "Forbidden drawn layer BasPoly on GDS layer 13/0 = 13/0") + -> do + DeepCo.dup + end.().output("forbidden.DeepCo", "Forbidden drawn layer DeepCo on GDS layer 35/0 = 35/0") + -> do + PEmPoly.dup + end.().output("forbidden.PEmPoly", "Forbidden drawn layer PEmPoly on GDS layer 53/0 = 53/0") + -> do + EmPoly.dup + end.().output("forbidden.EmPoly", "Forbidden gen./drawn layer EmPoly on GDS layer 53/0 = 53/0") + -> do + LDMOS.dup + end.().output("forbidden.LDMOS", "Forbidden drawn layer LDMOS on GDS layer 57/0 = 57/0") + -> do + PBiWind.dup + end.().output("forbidden.PBiWind", "Forbidden drawn layer PBiWind on GDS layer 58/0 = 58/0") + -> do + Flash.dup + end.().output("forbidden.Flash", "Forbidden drawn layer Flash on GDS layer 71/0 = 71/0") + -> do + ColWind.dup + end.().output("forbidden.ColWind", "Forbidden drawn layer ColWind on GDS layer 139/0 = 139/0") +end + +puts("Number of DRC errors: #{$drc_error_count}") + + diff --git a/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_1024x16_c2_bm_bist.gds b/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_1024x16_c2_bm_bist.gds new file mode 100644 index 0000000000..67c00161fc Binary files /dev/null and b/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_1024x16_c2_bm_bist.gds differ diff --git a/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_1024x8_c2_bm_bist.gds b/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_1024x8_c2_bm_bist.gds new file mode 100644 index 0000000000..7aca9b1302 Binary files /dev/null and b/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_1024x8_c2_bm_bist.gds differ diff --git a/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_4096x16_c3_bm_bist.gds b/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_4096x16_c3_bm_bist.gds new file mode 100644 index 0000000000..ee71dbb284 Binary files /dev/null and b/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_4096x16_c3_bm_bist.gds differ diff --git a/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_4096x8_c3_bm_bist.gds b/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_4096x8_c3_bm_bist.gds new file mode 100644 index 0000000000..4153651539 Binary files /dev/null and b/flow/platforms/ihp-sg13g2/gds/RM_IHPSG13_1P_4096x8_c3_bm_bist.gds differ diff --git a/flow/platforms/ihp-sg13g2/gds/sg13g2_io.gds b/flow/platforms/ihp-sg13g2/gds/sg13g2_io.gds index efc29676a4..fc12e448ad 100644 Binary files a/flow/platforms/ihp-sg13g2/gds/sg13g2_io.gds and b/flow/platforms/ihp-sg13g2/gds/sg13g2_io.gds differ diff --git a/flow/platforms/ihp-sg13g2/lef/RM_IHPSG13_1P_1024x16_c2_bm_bist.lef b/flow/platforms/ihp-sg13g2/lef/RM_IHPSG13_1P_1024x16_c2_bm_bist.lef new file mode 100644 index 0000000000..fa8827f696 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lef/RM_IHPSG13_1P_1024x16_c2_bm_bist.lef @@ -0,0 +1,2468 @@ +# ------------------------------------------------------ +# +# Copyright 2024 IHP PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# Generated on Fri Jul 19 08:58:12 2024 +# +# ------------------------------------------------------ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +DIVIDERCHAR "/" ; + +MACRO RM_IHPSG13_1P_1024x16_c2_bm_bist + CLASS BLOCK ; + ORIGIN 0 0 ; + FOREIGN RM_IHPSG13_1P_1024x16_c2_bm_bist 0 0 ; + SIZE 236.8 BY 336.46 ; + SYMMETRY X Y R90 ; + PIN A_DIN[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 154.57 0 154.83 0.26 ; + END + END A_DIN[8] + PIN A_DIN[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 81.97 0 82.23 0.26 ; + END + END A_DIN[7] + PIN A_BIST_DIN[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 153.715 0 153.975 0.26 ; + END + END A_BIST_DIN[8] + PIN A_BIST_DIN[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 82.825 0 83.085 0.26 ; + END + END A_BIST_DIN[7] + PIN A_BM[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 146.73 0 146.99 0.26 ; + END + END A_BM[8] + PIN A_BM[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 89.81 0 90.07 0.26 ; + END + END A_BM[7] + PIN A_BIST_BM[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 148.105 0 148.365 0.26 ; + END + END A_BIST_BM[8] + PIN A_BIST_BM[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 88.435 0 88.695 0.26 ; + END + END A_BIST_BM[7] + PIN A_DOUT[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 147.24 0 147.5 0.26 ; + END + END A_DOUT[8] + PIN A_DOUT[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 89.3 0 89.56 0.26 ; + END + END A_DOUT[7] + PIN VSS! + DIRECTION INOUT ; + USE GROUND ; + NETEXPR "vss VSS!" ; + PORT + LAYER Metal4 ; + RECT 224.11 0 226.92 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 212.87 0 215.68 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 201.63 0 204.44 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 190.39 0 193.2 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 179.15 0 181.96 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 167.91 0 170.72 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 156.67 0 159.48 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 145.43 0 148.24 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 135.02 0 137.83 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 124.72 0 127.53 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 109.27 0 112.08 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 98.97 0 101.78 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 88.56 0 91.37 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 77.32 0 80.13 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 66.08 0 68.89 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 54.84 0 57.65 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 43.6 0 46.41 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 32.36 0 35.17 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 21.12 0 23.93 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 9.88 0 12.69 336.46 ; + END + END VSS! + PIN VDD! + DIRECTION INOUT ; + USE POWER ; + NETEXPR "vdd VDD!" ; + PORT + LAYER Metal4 ; + RECT 229.73 0 232.54 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 218.49 0 221.3 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 207.25 0 210.06 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 196.01 0 198.82 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 184.77 0 187.58 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 173.53 0 176.34 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 162.29 0 165.1 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 151.05 0 153.86 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 129.87 0 132.68 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 119.57 0 122.38 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 114.42 0 117.23 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 104.12 0 106.93 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 82.94 0 85.75 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 71.7 0 74.51 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 60.46 0 63.27 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 49.22 0 52.03 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 37.98 0 40.79 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 26.74 0 29.55 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 15.5 0 18.31 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 4.26 0 7.07 38.825 ; + END + END VDD! + PIN VDDARRAY! + DIRECTION INOUT ; + USE POWER ; + NETEXPR "vddarray VDDARRAY!" ; + PORT + LAYER Metal4 ; + RECT 229.73 45.465 232.54 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 218.49 45.465 221.3 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 207.25 45.465 210.06 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 196.01 45.465 198.82 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 184.77 45.465 187.58 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 173.53 45.465 176.34 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 162.29 45.465 165.1 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 151.05 45.465 153.86 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 82.94 45.465 85.75 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 71.7 45.465 74.51 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 60.46 45.465 63.27 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 49.22 45.465 52.03 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 37.98 45.465 40.79 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 26.74 45.465 29.55 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 15.5 45.465 18.31 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 4.26 45.465 7.07 336.46 ; + END + END VDDARRAY! + PIN A_DIN[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 165.81 0 166.07 0.26 ; + END + END A_DIN[9] + PIN A_DIN[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 70.73 0 70.99 0.26 ; + END + END A_DIN[6] + PIN A_BIST_DIN[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 164.955 0 165.215 0.26 ; + END + END A_BIST_DIN[9] + PIN A_BIST_DIN[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 71.585 0 71.845 0.26 ; + END + END A_BIST_DIN[6] + PIN A_BM[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 157.97 0 158.23 0.26 ; + END + END A_BM[9] + PIN A_BM[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 78.57 0 78.83 0.26 ; + END + END A_BM[6] + PIN A_BIST_BM[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 159.345 0 159.605 0.26 ; + END + END A_BIST_BM[9] + PIN A_BIST_BM[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 77.195 0 77.455 0.26 ; + END + END A_BIST_BM[6] + PIN A_DOUT[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 158.48 0 158.74 0.26 ; + END + END A_DOUT[9] + PIN A_DOUT[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 78.06 0 78.32 0.26 ; + END + END A_DOUT[6] + PIN A_DIN[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 177.05 0 177.31 0.26 ; + END + END A_DIN[10] + PIN A_DIN[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 59.49 0 59.75 0.26 ; + END + END A_DIN[5] + PIN A_BIST_DIN[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 176.195 0 176.455 0.26 ; + END + END A_BIST_DIN[10] + PIN A_BIST_DIN[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 60.345 0 60.605 0.26 ; + END + END A_BIST_DIN[5] + PIN A_BM[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 169.21 0 169.47 0.26 ; + END + END A_BM[10] + PIN A_BM[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 67.33 0 67.59 0.26 ; + END + END A_BM[5] + PIN A_BIST_BM[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 170.585 0 170.845 0.26 ; + END + END A_BIST_BM[10] + PIN A_BIST_BM[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 65.955 0 66.215 0.26 ; + END + END A_BIST_BM[5] + PIN A_DOUT[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 169.72 0 169.98 0.26 ; + END + END A_DOUT[10] + PIN A_DOUT[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 66.82 0 67.08 0.26 ; + END + END A_DOUT[5] + PIN A_DIN[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 188.29 0 188.55 0.26 ; + END + END A_DIN[11] + PIN A_DIN[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 48.25 0 48.51 0.26 ; + END + END A_DIN[4] + PIN A_BIST_DIN[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 187.435 0 187.695 0.26 ; + END + END A_BIST_DIN[11] + PIN A_BIST_DIN[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 49.105 0 49.365 0.26 ; + END + END A_BIST_DIN[4] + PIN A_BM[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 180.45 0 180.71 0.26 ; + END + END A_BM[11] + PIN A_BM[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 56.09 0 56.35 0.26 ; + END + END A_BM[4] + PIN A_BIST_BM[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 181.825 0 182.085 0.26 ; + END + END A_BIST_BM[11] + PIN A_BIST_BM[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 54.715 0 54.975 0.26 ; + END + END A_BIST_BM[4] + PIN A_DOUT[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 180.96 0 181.22 0.26 ; + END + END A_DOUT[11] + PIN A_DOUT[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 55.58 0 55.84 0.26 ; + END + END A_DOUT[4] + PIN A_DIN[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 199.53 0 199.79 0.26 ; + END + END A_DIN[12] + PIN A_DIN[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 37.01 0 37.27 0.26 ; + END + END A_DIN[3] + PIN A_BIST_DIN[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 198.675 0 198.935 0.26 ; + END + END A_BIST_DIN[12] + PIN A_BIST_DIN[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 37.865 0 38.125 0.26 ; + END + END A_BIST_DIN[3] + PIN A_BM[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 191.69 0 191.95 0.26 ; + END + END A_BM[12] + PIN A_BM[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 44.85 0 45.11 0.26 ; + END + END A_BM[3] + PIN A_BIST_BM[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 193.065 0 193.325 0.26 ; + END + END A_BIST_BM[12] + PIN A_BIST_BM[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 43.475 0 43.735 0.26 ; + END + END A_BIST_BM[3] + PIN A_DOUT[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 192.2 0 192.46 0.26 ; + END + END A_DOUT[12] + PIN A_DOUT[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 44.34 0 44.6 0.26 ; + END + END A_DOUT[3] + PIN A_DIN[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 210.77 0 211.03 0.26 ; + END + END A_DIN[13] + PIN A_DIN[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 25.77 0 26.03 0.26 ; + END + END A_DIN[2] + PIN A_BIST_DIN[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 209.915 0 210.175 0.26 ; + END + END A_BIST_DIN[13] + PIN A_BIST_DIN[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 26.625 0 26.885 0.26 ; + END + END A_BIST_DIN[2] + PIN A_BM[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 202.93 0 203.19 0.26 ; + END + END A_BM[13] + PIN A_BM[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 33.61 0 33.87 0.26 ; + END + END A_BM[2] + PIN A_BIST_BM[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 204.305 0 204.565 0.26 ; + END + END A_BIST_BM[13] + PIN A_BIST_BM[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 32.235 0 32.495 0.26 ; + END + END A_BIST_BM[2] + PIN A_DOUT[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 203.44 0 203.7 0.26 ; + END + END A_DOUT[13] + PIN A_DOUT[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 33.1 0 33.36 0.26 ; + END + END A_DOUT[2] + PIN A_DIN[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 222.01 0 222.27 0.26 ; + END + END A_DIN[14] + PIN A_DIN[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 14.53 0 14.79 0.26 ; + END + END A_DIN[1] + PIN A_BIST_DIN[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 221.155 0 221.415 0.26 ; + END + END A_BIST_DIN[14] + PIN A_BIST_DIN[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 15.385 0 15.645 0.26 ; + END + END A_BIST_DIN[1] + PIN A_BM[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 214.17 0 214.43 0.26 ; + END + END A_BM[14] + PIN A_BM[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 22.37 0 22.63 0.26 ; + END + END A_BM[1] + PIN A_BIST_BM[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 215.545 0 215.805 0.26 ; + END + END A_BIST_BM[14] + PIN A_BIST_BM[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 20.995 0 21.255 0.26 ; + END + END A_BIST_BM[1] + PIN A_DOUT[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 214.68 0 214.94 0.26 ; + END + END A_DOUT[14] + PIN A_DOUT[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 21.86 0 22.12 0.26 ; + END + END A_DOUT[1] + PIN A_DIN[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 233.25 0 233.51 0.26 ; + END + END A_DIN[15] + PIN A_DIN[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 3.29 0 3.55 0.26 ; + END + END A_DIN[0] + PIN A_BIST_DIN[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 232.395 0 232.655 0.26 ; + END + END A_BIST_DIN[15] + PIN A_BIST_DIN[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 4.145 0 4.405 0.26 ; + END + END A_BIST_DIN[0] + PIN A_BM[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 225.41 0 225.67 0.26 ; + END + END A_BM[15] + PIN A_BM[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 11.13 0 11.39 0.26 ; + END + END A_BM[0] + PIN A_BIST_BM[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 226.785 0 227.045 0.26 ; + END + END A_BIST_BM[15] + PIN A_BIST_BM[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 9.755 0 10.015 0.26 ; + END + END A_BIST_BM[0] + PIN A_DOUT[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 225.92 0 226.18 0.26 ; + END + END A_DOUT[15] + PIN A_DOUT[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 10.62 0 10.88 0.26 ; + END + END A_DOUT[0] + PIN A_ADDR[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 8.9011 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 45.223301 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 114.6 0 114.86 0.26 ; + END + END A_ADDR[0] + PIN A_BIST_ADDR[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 9.6967 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 49.184466 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 119.19 0 119.45 0.26 ; + END + END A_BIST_ADDR[0] + PIN A_ADDR[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 7.774 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 39.656958 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 114.09 0 114.35 0.26 ; + END + END A_ADDR[1] + PIN A_BIST_ADDR[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 8.5696 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 43.618123 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 118.68 0 118.94 0.26 ; + END + END A_BIST_ADDR[1] + PIN A_ADDR[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 10.6327 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.5246 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 9.415982 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 122.25 0 122.51 0.26 ; + END + END A_ADDR[2] + PIN A_BIST_ADDR[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 10.6327 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.0962 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 7.813791 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 122.76 0 123.02 0.26 ; + END + END A_BIST_ADDR[2] + PIN A_ADDR[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 10.6327 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 3.8367 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 20.927558 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 121.23 0 121.49 0.26 ; + END + END A_ADDR[3] + PIN A_BIST_ADDR[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 10.6327 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 3.5175 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 19.869057 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 121.74 0 122 0.26 ; + END + END A_BIST_ADDR[3] + PIN A_ADDR[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 12.1979 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 61.63754 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 124.8 0 125.06 0.26 ; + END + END A_ADDR[4] + PIN A_BIST_ADDR[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 11.9327 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 60.317152 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 124.29 0 124.55 0.26 ; + END + END A_BIST_ADDR[4] + PIN A_ADDR[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.9269 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 70.245955 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 123.78 0 124.04 0.26 ; + END + END A_ADDR[5] + PIN A_BIST_ADDR[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.6617 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 68.925566 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 123.27 0 123.53 0.26 ; + END + END A_BIST_ADDR[5] + PIN A_ADDR[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 10.9525 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 55.436893 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 102.36 0 102.62 0.26 ; + END + END A_ADDR[6] + PIN A_BIST_ADDR[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 10.6771 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 54.065721 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 102.87 0 103.13 0.26 ; + END + END A_BIST_ADDR[6] + PIN A_ADDR[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 12.4163 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 62.724919 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 103.38 0 103.64 0.26 ; + END + END A_ADDR[7] + PIN A_BIST_ADDR[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 12.1511 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 61.404531 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 103.89 0 104.15 0.26 ; + END + END A_BIST_ADDR[7] + PIN A_ADDR[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 10.3675 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.5897 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 9.740105 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 132.45 0 132.71 0.26 ; + END + END A_ADDR[8] + PIN A_BIST_ADDR[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 10.3675 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.3755 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 9.204381 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 132.96 0 133.22 0.26 ; + END + END A_BIST_ADDR[8] + PIN A_ADDR[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 12.2633 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 61.963157 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 127.35 0 127.61 0.26 ; + END + END A_ADDR[9] + PIN A_BIST_ADDR[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 12.0083 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 60.693552 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 127.86 0 128.12 0.26 ; + END + END A_BIST_ADDR[9] + PIN A_CLK + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.0547 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.093851 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 112.56 0 112.82 0.26 ; + END + END A_CLK + PIN A_REN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.99505 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.796863 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 116.13 0 116.39 0.26 ; + END + END A_REN + PIN A_WEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8847 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.268608 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 115.62 0 115.88 0.26 ; + END + END A_WEN + PIN A_MEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.0247 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.965646 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 113.07 0 113.33 0.26 ; + END + END A_MEN + PIN A_DLY + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 6.058 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.3367 LAYER Metal2 ; + ANTENNAMAXAREACAR 18.532819 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 134.49 0 134.75 0.26 ; + END + END A_DLY + PIN A_BIST_EN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9871 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 114.62575 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 1.43 LAYER Metal2 ; + ANTENNAGATEAREA 16.445 LAYER Metal3 ; + ANTENNAMAXAREACAR 3.213636 LAYER Metal2 ; + ANTENNAMAXAREACAR 17.242977 LAYER Metal3 ; + ANTENNAMAXCUTCAR 0.151469 LAYER Via2 ; + PORT + LAYER Metal2 ; + RECT 115.11 0 115.37 0.26 ; + END + END A_BIST_EN + PIN A_BIST_CLK + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.1639 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.953448 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 111.03 0 111.29 0.26 ; + END + END A_BIST_CLK + PIN A_BIST_REN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.1119 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.694548 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 117.66 0 117.92 0.26 ; + END + END A_BIST_REN + PIN A_BIST_WEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9051 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.686084 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 117.15 0 117.41 0.26 ; + END + END A_BIST_WEN + PIN A_BIST_MEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8977 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.649241 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 111.54 0 111.8 0.26 ; + END + END A_BIST_MEN + OBS + LAYER Metal1 ; + RECT 0 0 236.8 336.46 ; + LAYER Metal2 ; + RECT 0.105 45.465 0.305 336.435 ; + RECT 1.1 335.705 1.3 336.435 ; + RECT 3.29 0.52 3.55 5.16 ; + RECT 2.77 4.9 3.55 5.16 ; + RECT 2.77 4.9 3.03 6.64 ; + RECT 1.92 335.705 2.12 336.435 ; + RECT 2.415 335.705 2.615 336.435 ; + RECT 2.915 335.705 3.115 336.435 ; + RECT 3.415 335.705 3.615 336.435 ; + RECT 3.91 335.705 4.11 336.435 ; + RECT 4.655 0.17 5.425 0.94 ; + RECT 4.655 0.17 4.915 12.9 ; + RECT 5.165 0.17 5.425 12.9 ; + RECT 4.145 0.52 4.405 5.815 ; + RECT 4.73 335.705 4.93 336.435 ; + RECT 5.675 0.17 6.445 0.43 ; + RECT 5.675 0.17 5.935 11.5 ; + RECT 6.185 0.17 6.445 11.5 ; + RECT 5.225 335.705 5.425 336.435 ; + RECT 5.725 335.705 5.925 336.435 ; + RECT 6.225 335.705 6.425 336.435 ; + RECT 7.715 0.17 8.485 0.43 ; + RECT 7.715 0.17 7.975 10.48 ; + RECT 8.225 0.17 8.485 10.99 ; + RECT 6.72 335.705 6.92 336.435 ; + RECT 7.54 335.705 7.74 336.435 ; + RECT 8.735 0.17 9.505 0.94 ; + RECT 8.735 0.17 8.995 8.7 ; + RECT 9.245 0.17 9.505 12.9 ; + RECT 8.035 335.705 8.235 336.435 ; + RECT 8.535 335.705 8.735 336.435 ; + RECT 9.035 335.705 9.235 336.435 ; + RECT 9.53 335.705 9.73 336.435 ; + RECT 9.755 0.52 10.015 2.485 ; + RECT 10.35 335.705 10.55 336.435 ; + RECT 10.62 0.52 10.88 14.11 ; + RECT 10.845 335.705 11.045 336.435 ; + RECT 11.13 0.52 11.39 2.335 ; + RECT 11.345 335.705 11.545 336.435 ; + RECT 11.845 335.705 12.045 336.435 ; + RECT 12.34 335.705 12.54 336.435 ; + RECT 14.53 0.52 14.79 5.16 ; + RECT 14.01 4.9 14.79 5.16 ; + RECT 14.01 4.9 14.27 6.64 ; + RECT 13.16 335.705 13.36 336.435 ; + RECT 13.655 335.705 13.855 336.435 ; + RECT 14.155 335.705 14.355 336.435 ; + RECT 14.655 335.705 14.855 336.435 ; + RECT 15.15 335.705 15.35 336.435 ; + RECT 15.895 0.17 16.665 0.94 ; + RECT 15.895 0.17 16.155 12.9 ; + RECT 16.405 0.17 16.665 12.9 ; + RECT 15.385 0.52 15.645 5.815 ; + RECT 15.97 335.705 16.17 336.435 ; + RECT 16.915 0.17 17.685 0.43 ; + RECT 16.915 0.17 17.175 11.5 ; + RECT 17.425 0.17 17.685 11.5 ; + RECT 16.465 335.705 16.665 336.435 ; + RECT 16.965 335.705 17.165 336.435 ; + RECT 17.465 335.705 17.665 336.435 ; + RECT 18.955 0.17 19.725 0.43 ; + RECT 18.955 0.17 19.215 10.48 ; + RECT 19.465 0.17 19.725 10.99 ; + RECT 17.96 335.705 18.16 336.435 ; + RECT 18.78 335.705 18.98 336.435 ; + RECT 19.975 0.17 20.745 0.94 ; + RECT 19.975 0.17 20.235 8.7 ; + RECT 20.485 0.17 20.745 12.9 ; + RECT 19.275 335.705 19.475 336.435 ; + RECT 19.775 335.705 19.975 336.435 ; + RECT 20.275 335.705 20.475 336.435 ; + RECT 20.77 335.705 20.97 336.435 ; + RECT 20.995 0.52 21.255 2.485 ; + RECT 21.59 335.705 21.79 336.435 ; + RECT 21.86 0.52 22.12 14.11 ; + RECT 22.085 335.705 22.285 336.435 ; + RECT 22.37 0.52 22.63 2.335 ; + RECT 22.585 335.705 22.785 336.435 ; + RECT 23.085 335.705 23.285 336.435 ; + RECT 23.58 335.705 23.78 336.435 ; + RECT 25.77 0.52 26.03 5.16 ; + RECT 25.25 4.9 26.03 5.16 ; + RECT 25.25 4.9 25.51 6.64 ; + RECT 24.4 335.705 24.6 336.435 ; + RECT 24.895 335.705 25.095 336.435 ; + RECT 25.395 335.705 25.595 336.435 ; + RECT 25.895 335.705 26.095 336.435 ; + RECT 26.39 335.705 26.59 336.435 ; + RECT 27.135 0.17 27.905 0.94 ; + RECT 27.135 0.17 27.395 12.9 ; + RECT 27.645 0.17 27.905 12.9 ; + RECT 26.625 0.52 26.885 5.815 ; + RECT 27.21 335.705 27.41 336.435 ; + RECT 28.155 0.17 28.925 0.43 ; + RECT 28.155 0.17 28.415 11.5 ; + RECT 28.665 0.17 28.925 11.5 ; + RECT 27.705 335.705 27.905 336.435 ; + RECT 28.205 335.705 28.405 336.435 ; + RECT 28.705 335.705 28.905 336.435 ; + RECT 30.195 0.17 30.965 0.43 ; + RECT 30.195 0.17 30.455 10.48 ; + RECT 30.705 0.17 30.965 10.99 ; + RECT 29.2 335.705 29.4 336.435 ; + RECT 30.02 335.705 30.22 336.435 ; + RECT 31.215 0.17 31.985 0.94 ; + RECT 31.215 0.17 31.475 8.7 ; + RECT 31.725 0.17 31.985 12.9 ; + RECT 30.515 335.705 30.715 336.435 ; + RECT 31.015 335.705 31.215 336.435 ; + RECT 31.515 335.705 31.715 336.435 ; + RECT 32.01 335.705 32.21 336.435 ; + RECT 32.235 0.52 32.495 2.485 ; + RECT 32.83 335.705 33.03 336.435 ; + RECT 33.1 0.52 33.36 14.11 ; + RECT 33.325 335.705 33.525 336.435 ; + RECT 33.61 0.52 33.87 2.335 ; + RECT 33.825 335.705 34.025 336.435 ; + RECT 34.325 335.705 34.525 336.435 ; + RECT 34.82 335.705 35.02 336.435 ; + RECT 37.01 0.52 37.27 5.16 ; + RECT 36.49 4.9 37.27 5.16 ; + RECT 36.49 4.9 36.75 6.64 ; + RECT 35.64 335.705 35.84 336.435 ; + RECT 36.135 335.705 36.335 336.435 ; + RECT 36.635 335.705 36.835 336.435 ; + RECT 37.135 335.705 37.335 336.435 ; + RECT 37.63 335.705 37.83 336.435 ; + RECT 38.375 0.17 39.145 0.94 ; + RECT 38.375 0.17 38.635 12.9 ; + RECT 38.885 0.17 39.145 12.9 ; + RECT 37.865 0.52 38.125 5.815 ; + RECT 38.45 335.705 38.65 336.435 ; + RECT 39.395 0.17 40.165 0.43 ; + RECT 39.395 0.17 39.655 11.5 ; + RECT 39.905 0.17 40.165 11.5 ; + RECT 38.945 335.705 39.145 336.435 ; + RECT 39.445 335.705 39.645 336.435 ; + RECT 39.945 335.705 40.145 336.435 ; + RECT 41.435 0.17 42.205 0.43 ; + RECT 41.435 0.17 41.695 10.48 ; + RECT 41.945 0.17 42.205 10.99 ; + RECT 40.44 335.705 40.64 336.435 ; + RECT 41.26 335.705 41.46 336.435 ; + RECT 42.455 0.17 43.225 0.94 ; + RECT 42.455 0.17 42.715 8.7 ; + RECT 42.965 0.17 43.225 12.9 ; + RECT 41.755 335.705 41.955 336.435 ; + RECT 42.255 335.705 42.455 336.435 ; + RECT 42.755 335.705 42.955 336.435 ; + RECT 43.25 335.705 43.45 336.435 ; + RECT 43.475 0.52 43.735 2.485 ; + RECT 44.07 335.705 44.27 336.435 ; + RECT 44.34 0.52 44.6 14.11 ; + RECT 44.565 335.705 44.765 336.435 ; + RECT 44.85 0.52 45.11 2.335 ; + RECT 45.065 335.705 45.265 336.435 ; + RECT 45.565 335.705 45.765 336.435 ; + RECT 46.06 335.705 46.26 336.435 ; + RECT 48.25 0.52 48.51 5.16 ; + RECT 47.73 4.9 48.51 5.16 ; + RECT 47.73 4.9 47.99 6.64 ; + RECT 46.88 335.705 47.08 336.435 ; + RECT 47.375 335.705 47.575 336.435 ; + RECT 47.875 335.705 48.075 336.435 ; + RECT 48.375 335.705 48.575 336.435 ; + RECT 48.87 335.705 49.07 336.435 ; + RECT 49.615 0.17 50.385 0.94 ; + RECT 49.615 0.17 49.875 12.9 ; + RECT 50.125 0.17 50.385 12.9 ; + RECT 49.105 0.52 49.365 5.815 ; + RECT 49.69 335.705 49.89 336.435 ; + RECT 50.635 0.17 51.405 0.43 ; + RECT 50.635 0.17 50.895 11.5 ; + RECT 51.145 0.17 51.405 11.5 ; + RECT 50.185 335.705 50.385 336.435 ; + RECT 50.685 335.705 50.885 336.435 ; + RECT 51.185 335.705 51.385 336.435 ; + RECT 52.675 0.17 53.445 0.43 ; + RECT 52.675 0.17 52.935 10.48 ; + RECT 53.185 0.17 53.445 10.99 ; + RECT 51.68 335.705 51.88 336.435 ; + RECT 52.5 335.705 52.7 336.435 ; + RECT 53.695 0.17 54.465 0.94 ; + RECT 53.695 0.17 53.955 8.7 ; + RECT 54.205 0.17 54.465 12.9 ; + RECT 52.995 335.705 53.195 336.435 ; + RECT 53.495 335.705 53.695 336.435 ; + RECT 53.995 335.705 54.195 336.435 ; + RECT 54.49 335.705 54.69 336.435 ; + RECT 54.715 0.52 54.975 2.485 ; + RECT 55.31 335.705 55.51 336.435 ; + RECT 55.58 0.52 55.84 14.11 ; + RECT 55.805 335.705 56.005 336.435 ; + RECT 56.09 0.52 56.35 2.335 ; + RECT 56.305 335.705 56.505 336.435 ; + RECT 56.805 335.705 57.005 336.435 ; + RECT 57.3 335.705 57.5 336.435 ; + RECT 59.49 0.52 59.75 5.16 ; + RECT 58.97 4.9 59.75 5.16 ; + RECT 58.97 4.9 59.23 6.64 ; + RECT 58.12 335.705 58.32 336.435 ; + RECT 58.615 335.705 58.815 336.435 ; + RECT 59.115 335.705 59.315 336.435 ; + RECT 59.615 335.705 59.815 336.435 ; + RECT 60.11 335.705 60.31 336.435 ; + RECT 60.855 0.17 61.625 0.94 ; + RECT 60.855 0.17 61.115 12.9 ; + RECT 61.365 0.17 61.625 12.9 ; + RECT 60.345 0.52 60.605 5.815 ; + RECT 60.93 335.705 61.13 336.435 ; + RECT 61.875 0.17 62.645 0.43 ; + RECT 61.875 0.17 62.135 11.5 ; + RECT 62.385 0.17 62.645 11.5 ; + RECT 61.425 335.705 61.625 336.435 ; + RECT 61.925 335.705 62.125 336.435 ; + RECT 62.425 335.705 62.625 336.435 ; + RECT 63.915 0.17 64.685 0.43 ; + RECT 63.915 0.17 64.175 10.48 ; + RECT 64.425 0.17 64.685 10.99 ; + RECT 62.92 335.705 63.12 336.435 ; + RECT 63.74 335.705 63.94 336.435 ; + RECT 64.935 0.17 65.705 0.94 ; + RECT 64.935 0.17 65.195 8.7 ; + RECT 65.445 0.17 65.705 12.9 ; + RECT 64.235 335.705 64.435 336.435 ; + RECT 64.735 335.705 64.935 336.435 ; + RECT 65.235 335.705 65.435 336.435 ; + RECT 65.73 335.705 65.93 336.435 ; + RECT 65.955 0.52 66.215 2.485 ; + RECT 66.55 335.705 66.75 336.435 ; + RECT 66.82 0.52 67.08 14.11 ; + RECT 67.045 335.705 67.245 336.435 ; + RECT 67.33 0.52 67.59 2.335 ; + RECT 67.545 335.705 67.745 336.435 ; + RECT 68.045 335.705 68.245 336.435 ; + RECT 68.54 335.705 68.74 336.435 ; + RECT 70.73 0.52 70.99 5.16 ; + RECT 70.21 4.9 70.99 5.16 ; + RECT 70.21 4.9 70.47 6.64 ; + RECT 69.36 335.705 69.56 336.435 ; + RECT 69.855 335.705 70.055 336.435 ; + RECT 70.355 335.705 70.555 336.435 ; + RECT 70.855 335.705 71.055 336.435 ; + RECT 71.35 335.705 71.55 336.435 ; + RECT 72.095 0.17 72.865 0.94 ; + RECT 72.095 0.17 72.355 12.9 ; + RECT 72.605 0.17 72.865 12.9 ; + RECT 71.585 0.52 71.845 5.815 ; + RECT 72.17 335.705 72.37 336.435 ; + RECT 73.115 0.17 73.885 0.43 ; + RECT 73.115 0.17 73.375 11.5 ; + RECT 73.625 0.17 73.885 11.5 ; + RECT 72.665 335.705 72.865 336.435 ; + RECT 73.165 335.705 73.365 336.435 ; + RECT 73.665 335.705 73.865 336.435 ; + RECT 75.155 0.17 75.925 0.43 ; + RECT 75.155 0.17 75.415 10.48 ; + RECT 75.665 0.17 75.925 10.99 ; + RECT 74.16 335.705 74.36 336.435 ; + RECT 74.98 335.705 75.18 336.435 ; + RECT 76.175 0.17 76.945 0.94 ; + RECT 76.175 0.17 76.435 8.7 ; + RECT 76.685 0.17 76.945 12.9 ; + RECT 75.475 335.705 75.675 336.435 ; + RECT 75.975 335.705 76.175 336.435 ; + RECT 76.475 335.705 76.675 336.435 ; + RECT 76.97 335.705 77.17 336.435 ; + RECT 77.195 0.52 77.455 2.485 ; + RECT 77.79 335.705 77.99 336.435 ; + RECT 78.06 0.52 78.32 14.11 ; + RECT 78.285 335.705 78.485 336.435 ; + RECT 78.57 0.52 78.83 2.335 ; + RECT 78.785 335.705 78.985 336.435 ; + RECT 79.285 335.705 79.485 336.435 ; + RECT 79.78 335.705 79.98 336.435 ; + RECT 81.97 0.52 82.23 5.16 ; + RECT 81.45 4.9 82.23 5.16 ; + RECT 81.45 4.9 81.71 6.64 ; + RECT 80.6 335.705 80.8 336.435 ; + RECT 81.095 335.705 81.295 336.435 ; + RECT 81.595 335.705 81.795 336.435 ; + RECT 82.095 335.705 82.295 336.435 ; + RECT 82.59 335.705 82.79 336.435 ; + RECT 83.335 0.17 84.105 0.94 ; + RECT 83.335 0.17 83.595 12.9 ; + RECT 83.845 0.17 84.105 12.9 ; + RECT 82.825 0.52 83.085 5.815 ; + RECT 83.41 335.705 83.61 336.435 ; + RECT 84.355 0.17 85.125 0.43 ; + RECT 84.355 0.17 84.615 11.5 ; + RECT 84.865 0.17 85.125 11.5 ; + RECT 83.905 335.705 84.105 336.435 ; + RECT 84.405 335.705 84.605 336.435 ; + RECT 84.905 335.705 85.105 336.435 ; + RECT 86.395 0.17 87.165 0.43 ; + RECT 86.395 0.17 86.655 10.48 ; + RECT 86.905 0.17 87.165 10.99 ; + RECT 85.4 335.705 85.6 336.435 ; + RECT 86.22 335.705 86.42 336.435 ; + RECT 87.415 0.17 88.185 0.94 ; + RECT 87.415 0.17 87.675 8.7 ; + RECT 87.925 0.17 88.185 12.9 ; + RECT 86.715 335.705 86.915 336.435 ; + RECT 87.215 335.705 87.415 336.435 ; + RECT 87.715 335.705 87.915 336.435 ; + RECT 88.21 335.705 88.41 336.435 ; + RECT 88.435 0.52 88.695 2.485 ; + RECT 89.03 335.705 89.23 336.435 ; + RECT 89.3 0.52 89.56 14.11 ; + RECT 89.525 335.705 89.725 336.435 ; + RECT 89.81 0.52 90.07 2.335 ; + RECT 90.025 335.705 90.225 336.435 ; + RECT 90.525 335.705 90.725 336.435 ; + RECT 92.515 0.17 93.285 0.43 ; + RECT 92.515 0.17 92.775 8.7 ; + RECT 93.025 0.17 93.285 8.7 ; + RECT 93.535 0.17 94.305 0.94 ; + RECT 93.535 0.17 93.795 8.7 ; + RECT 94.045 0.17 94.305 8.7 ; + RECT 94.555 0.17 95.325 0.43 ; + RECT 94.555 0.17 94.815 8.7 ; + RECT 95.065 0.17 95.325 8.7 ; + RECT 95.575 0.17 96.345 0.94 ; + RECT 95.575 0.17 95.835 8.7 ; + RECT 96.085 0.17 96.345 8.7 ; + RECT 96.595 0.17 97.365 0.43 ; + RECT 96.595 0.17 96.855 8.7 ; + RECT 97.105 0.17 97.365 8.7 ; + RECT 97.615 0.17 98.385 0.94 ; + RECT 97.615 0.17 97.875 8.7 ; + RECT 98.125 0.17 98.385 8.7 ; + RECT 91.02 335.705 91.22 336.435 ; + RECT 91.84 335.705 92.04 336.435 ; + RECT 92.835 335.705 93.035 336.435 ; + RECT 100.32 0.17 101.09 0.94 ; + RECT 100.32 0.17 100.58 8.7 ; + RECT 100.83 0.17 101.09 8.7 ; + RECT 98.79 0.3 99.05 8.7 ; + RECT 99.3 0 99.56 8.7 ; + RECT 99.81 0 100.07 8.7 ; + RECT 101.34 0 101.6 8.7 ; + RECT 101.85 0 102.11 8.7 ; + RECT 102.36 0.52 102.62 8.7 ; + RECT 102.87 0.52 103.13 8.7 ; + RECT 103.38 0.52 103.64 8.7 ; + RECT 105.42 0.17 106.19 0.94 ; + RECT 105.42 0.17 105.68 8.7 ; + RECT 105.93 0.17 106.19 8.7 ; + RECT 106.44 0.17 107.21 0.43 ; + RECT 106.44 0.17 106.7 8.7 ; + RECT 106.95 0.17 107.21 8.7 ; + RECT 103.89 0.52 104.15 8.7 ; + RECT 104.4 0 104.66 8.7 ; + RECT 104.91 0 105.17 8.7 ; + RECT 107.46 0.3 107.72 8.7 ; + RECT 107.97 0.3 108.23 8.7 ; + RECT 110.01 0.17 110.78 0.94 ; + RECT 110.01 0.17 110.27 8.7 ; + RECT 110.52 0.17 110.78 8.7 ; + RECT 108.48 0.3 108.74 8.7 ; + RECT 108.99 0.3 109.25 8.7 ; + RECT 109.5 0.3 109.76 8.7 ; + RECT 111.03 0.52 111.29 8.7 ; + RECT 111.54 0.52 111.8 8.7 ; + RECT 112.05 0.3 112.31 8.7 ; + RECT 112.56 0.52 112.82 8.7 ; + RECT 113.07 0.52 113.33 8.7 ; + RECT 113.58 0.3 113.84 8.7 ; + RECT 114.09 0.52 114.35 8.7 ; + RECT 114.6 0.52 114.86 8.7 ; + RECT 115.11 0.52 115.37 8.7 ; + RECT 115.62 0.52 115.88 8.7 ; + RECT 116.13 0.52 116.39 8.7 ; + RECT 116.64 0.3 116.9 8.7 ; + RECT 117.15 0.52 117.41 8.7 ; + RECT 117.66 0.52 117.92 8.7 ; + RECT 118.17 0.3 118.43 8.7 ; + RECT 120.21 0.17 120.98 0.94 ; + RECT 120.21 0.17 120.47 8.7 ; + RECT 120.72 0.17 120.98 8.7 ; + RECT 118.68 0.52 118.94 8.7 ; + RECT 119.19 0.52 119.45 8.7 ; + RECT 119.7 0.3 119.96 8.7 ; + RECT 121.23 0.52 121.49 8.7 ; + RECT 121.74 0.52 122 8.7 ; + RECT 122.25 0.52 122.51 8.7 ; + RECT 122.76 0.52 123.02 8.7 ; + RECT 123.27 0.52 123.53 8.7 ; + RECT 123.78 0.52 124.04 8.7 ; + RECT 124.29 0.52 124.55 8.7 ; + RECT 126.33 0.17 127.1 0.94 ; + RECT 126.33 0.17 126.59 8.7 ; + RECT 126.84 0.17 127.1 8.7 ; + RECT 124.8 0.52 125.06 8.7 ; + RECT 125.31 0 125.57 8.7 ; + RECT 125.82 0 126.08 8.7 ; + RECT 127.35 0.52 127.61 8.7 ; + RECT 129.39 0.17 130.16 0.43 ; + RECT 129.39 0.17 129.65 8.7 ; + RECT 129.9 0.17 130.16 8.7 ; + RECT 127.86 0.52 128.12 8.7 ; + RECT 128.37 0.3 128.63 8.7 ; + RECT 128.88 0.3 129.14 8.7 ; + RECT 130.41 0.3 130.67 8.7 ; + RECT 130.92 0.3 131.18 8.7 ; + RECT 131.43 0.3 131.69 8.7 ; + RECT 131.94 0.3 132.2 8.7 ; + RECT 132.45 0.52 132.71 8.7 ; + RECT 132.96 0.52 133.22 8.7 ; + RECT 135 0.17 135.77 0.43 ; + RECT 135 0.17 135.26 8.7 ; + RECT 135.51 0.17 135.77 8.7 ; + RECT 136.02 0.17 136.79 0.94 ; + RECT 136.02 0.17 136.28 25.5 ; + RECT 136.53 0.17 136.79 33.9 ; + RECT 137.04 0.17 137.81 0.43 ; + RECT 137.04 0.17 137.3 8.7 ; + RECT 137.55 0.17 137.81 8.7 ; + RECT 138.415 0.17 139.185 0.94 ; + RECT 138.415 0.17 138.675 8.7 ; + RECT 138.925 0.17 139.185 8.7 ; + RECT 139.435 0.17 140.205 0.43 ; + RECT 139.435 0.17 139.695 8.7 ; + RECT 139.945 0.17 140.205 8.7 ; + RECT 140.455 0.17 141.225 0.94 ; + RECT 140.455 0.17 140.715 8.7 ; + RECT 140.965 0.17 141.225 8.7 ; + RECT 141.475 0.17 142.245 0.43 ; + RECT 141.475 0.17 141.735 8.7 ; + RECT 141.985 0.17 142.245 8.7 ; + RECT 142.495 0.17 143.265 0.94 ; + RECT 142.495 0.17 142.755 8.7 ; + RECT 143.005 0.17 143.265 8.7 ; + RECT 133.47 0.3 133.73 8.7 ; + RECT 143.515 0.17 144.285 0.43 ; + RECT 143.515 0.17 143.775 8.7 ; + RECT 144.025 0.17 144.285 8.7 ; + RECT 133.98 0.3 134.24 8.7 ; + RECT 134.49 0.52 134.75 8.7 ; + RECT 143.765 335.705 143.965 336.435 ; + RECT 144.76 335.705 144.96 336.435 ; + RECT 145.58 335.705 145.78 336.435 ; + RECT 146.075 335.705 146.275 336.435 ; + RECT 146.575 335.705 146.775 336.435 ; + RECT 146.73 0.52 146.99 2.335 ; + RECT 147.075 335.705 147.275 336.435 ; + RECT 147.24 0.52 147.5 14.11 ; + RECT 147.57 335.705 147.77 336.435 ; + RECT 148.615 0.17 149.385 0.94 ; + RECT 149.125 0.17 149.385 8.7 ; + RECT 148.615 0.17 148.875 12.9 ; + RECT 148.105 0.52 148.365 2.485 ; + RECT 148.39 335.705 148.59 336.435 ; + RECT 149.635 0.17 150.405 0.43 ; + RECT 150.145 0.17 150.405 10.48 ; + RECT 149.635 0.17 149.895 10.99 ; + RECT 148.885 335.705 149.085 336.435 ; + RECT 149.385 335.705 149.585 336.435 ; + RECT 149.885 335.705 150.085 336.435 ; + RECT 150.38 335.705 150.58 336.435 ; + RECT 151.675 0.17 152.445 0.43 ; + RECT 151.675 0.17 151.935 11.5 ; + RECT 152.185 0.17 152.445 11.5 ; + RECT 151.2 335.705 151.4 336.435 ; + RECT 151.695 335.705 151.895 336.435 ; + RECT 152.695 0.17 153.465 0.94 ; + RECT 152.695 0.17 152.955 12.9 ; + RECT 153.205 0.17 153.465 12.9 ; + RECT 152.195 335.705 152.395 336.435 ; + RECT 152.695 335.705 152.895 336.435 ; + RECT 153.19 335.705 153.39 336.435 ; + RECT 153.715 0.52 153.975 5.815 ; + RECT 154.57 0.52 154.83 5.16 ; + RECT 154.57 4.9 155.35 5.16 ; + RECT 155.09 4.9 155.35 6.64 ; + RECT 154.01 335.705 154.21 336.435 ; + RECT 154.505 335.705 154.705 336.435 ; + RECT 155.005 335.705 155.205 336.435 ; + RECT 155.505 335.705 155.705 336.435 ; + RECT 156 335.705 156.2 336.435 ; + RECT 156.82 335.705 157.02 336.435 ; + RECT 157.315 335.705 157.515 336.435 ; + RECT 157.815 335.705 158.015 336.435 ; + RECT 157.97 0.52 158.23 2.335 ; + RECT 158.315 335.705 158.515 336.435 ; + RECT 158.48 0.52 158.74 14.11 ; + RECT 158.81 335.705 159.01 336.435 ; + RECT 159.855 0.17 160.625 0.94 ; + RECT 160.365 0.17 160.625 8.7 ; + RECT 159.855 0.17 160.115 12.9 ; + RECT 159.345 0.52 159.605 2.485 ; + RECT 159.63 335.705 159.83 336.435 ; + RECT 160.875 0.17 161.645 0.43 ; + RECT 161.385 0.17 161.645 10.48 ; + RECT 160.875 0.17 161.135 10.99 ; + RECT 160.125 335.705 160.325 336.435 ; + RECT 160.625 335.705 160.825 336.435 ; + RECT 161.125 335.705 161.325 336.435 ; + RECT 161.62 335.705 161.82 336.435 ; + RECT 162.915 0.17 163.685 0.43 ; + RECT 162.915 0.17 163.175 11.5 ; + RECT 163.425 0.17 163.685 11.5 ; + RECT 162.44 335.705 162.64 336.435 ; + RECT 162.935 335.705 163.135 336.435 ; + RECT 163.935 0.17 164.705 0.94 ; + RECT 163.935 0.17 164.195 12.9 ; + RECT 164.445 0.17 164.705 12.9 ; + RECT 163.435 335.705 163.635 336.435 ; + RECT 163.935 335.705 164.135 336.435 ; + RECT 164.43 335.705 164.63 336.435 ; + RECT 164.955 0.52 165.215 5.815 ; + RECT 165.81 0.52 166.07 5.16 ; + RECT 165.81 4.9 166.59 5.16 ; + RECT 166.33 4.9 166.59 6.64 ; + RECT 165.25 335.705 165.45 336.435 ; + RECT 165.745 335.705 165.945 336.435 ; + RECT 166.245 335.705 166.445 336.435 ; + RECT 166.745 335.705 166.945 336.435 ; + RECT 167.24 335.705 167.44 336.435 ; + RECT 168.06 335.705 168.26 336.435 ; + RECT 168.555 335.705 168.755 336.435 ; + RECT 169.055 335.705 169.255 336.435 ; + RECT 169.21 0.52 169.47 2.335 ; + RECT 169.555 335.705 169.755 336.435 ; + RECT 169.72 0.52 169.98 14.11 ; + RECT 170.05 335.705 170.25 336.435 ; + RECT 171.095 0.17 171.865 0.94 ; + RECT 171.605 0.17 171.865 8.7 ; + RECT 171.095 0.17 171.355 12.9 ; + RECT 170.585 0.52 170.845 2.485 ; + RECT 170.87 335.705 171.07 336.435 ; + RECT 172.115 0.17 172.885 0.43 ; + RECT 172.625 0.17 172.885 10.48 ; + RECT 172.115 0.17 172.375 10.99 ; + RECT 171.365 335.705 171.565 336.435 ; + RECT 171.865 335.705 172.065 336.435 ; + RECT 172.365 335.705 172.565 336.435 ; + RECT 172.86 335.705 173.06 336.435 ; + RECT 174.155 0.17 174.925 0.43 ; + RECT 174.155 0.17 174.415 11.5 ; + RECT 174.665 0.17 174.925 11.5 ; + RECT 173.68 335.705 173.88 336.435 ; + RECT 174.175 335.705 174.375 336.435 ; + RECT 175.175 0.17 175.945 0.94 ; + RECT 175.175 0.17 175.435 12.9 ; + RECT 175.685 0.17 175.945 12.9 ; + RECT 174.675 335.705 174.875 336.435 ; + RECT 175.175 335.705 175.375 336.435 ; + RECT 175.67 335.705 175.87 336.435 ; + RECT 176.195 0.52 176.455 5.815 ; + RECT 177.05 0.52 177.31 5.16 ; + RECT 177.05 4.9 177.83 5.16 ; + RECT 177.57 4.9 177.83 6.64 ; + RECT 176.49 335.705 176.69 336.435 ; + RECT 176.985 335.705 177.185 336.435 ; + RECT 177.485 335.705 177.685 336.435 ; + RECT 177.985 335.705 178.185 336.435 ; + RECT 178.48 335.705 178.68 336.435 ; + RECT 179.3 335.705 179.5 336.435 ; + RECT 179.795 335.705 179.995 336.435 ; + RECT 180.295 335.705 180.495 336.435 ; + RECT 180.45 0.52 180.71 2.335 ; + RECT 180.795 335.705 180.995 336.435 ; + RECT 180.96 0.52 181.22 14.11 ; + RECT 181.29 335.705 181.49 336.435 ; + RECT 182.335 0.17 183.105 0.94 ; + RECT 182.845 0.17 183.105 8.7 ; + RECT 182.335 0.17 182.595 12.9 ; + RECT 181.825 0.52 182.085 2.485 ; + RECT 182.11 335.705 182.31 336.435 ; + RECT 183.355 0.17 184.125 0.43 ; + RECT 183.865 0.17 184.125 10.48 ; + RECT 183.355 0.17 183.615 10.99 ; + RECT 182.605 335.705 182.805 336.435 ; + RECT 183.105 335.705 183.305 336.435 ; + RECT 183.605 335.705 183.805 336.435 ; + RECT 184.1 335.705 184.3 336.435 ; + RECT 185.395 0.17 186.165 0.43 ; + RECT 185.395 0.17 185.655 11.5 ; + RECT 185.905 0.17 186.165 11.5 ; + RECT 184.92 335.705 185.12 336.435 ; + RECT 185.415 335.705 185.615 336.435 ; + RECT 186.415 0.17 187.185 0.94 ; + RECT 186.415 0.17 186.675 12.9 ; + RECT 186.925 0.17 187.185 12.9 ; + RECT 185.915 335.705 186.115 336.435 ; + RECT 186.415 335.705 186.615 336.435 ; + RECT 186.91 335.705 187.11 336.435 ; + RECT 187.435 0.52 187.695 5.815 ; + RECT 188.29 0.52 188.55 5.16 ; + RECT 188.29 4.9 189.07 5.16 ; + RECT 188.81 4.9 189.07 6.64 ; + RECT 187.73 335.705 187.93 336.435 ; + RECT 188.225 335.705 188.425 336.435 ; + RECT 188.725 335.705 188.925 336.435 ; + RECT 189.225 335.705 189.425 336.435 ; + RECT 189.72 335.705 189.92 336.435 ; + RECT 190.54 335.705 190.74 336.435 ; + RECT 191.035 335.705 191.235 336.435 ; + RECT 191.535 335.705 191.735 336.435 ; + RECT 191.69 0.52 191.95 2.335 ; + RECT 192.035 335.705 192.235 336.435 ; + RECT 192.2 0.52 192.46 14.11 ; + RECT 192.53 335.705 192.73 336.435 ; + RECT 193.575 0.17 194.345 0.94 ; + RECT 194.085 0.17 194.345 8.7 ; + RECT 193.575 0.17 193.835 12.9 ; + RECT 193.065 0.52 193.325 2.485 ; + RECT 193.35 335.705 193.55 336.435 ; + RECT 194.595 0.17 195.365 0.43 ; + RECT 195.105 0.17 195.365 10.48 ; + RECT 194.595 0.17 194.855 10.99 ; + RECT 193.845 335.705 194.045 336.435 ; + RECT 194.345 335.705 194.545 336.435 ; + RECT 194.845 335.705 195.045 336.435 ; + RECT 195.34 335.705 195.54 336.435 ; + RECT 196.635 0.17 197.405 0.43 ; + RECT 196.635 0.17 196.895 11.5 ; + RECT 197.145 0.17 197.405 11.5 ; + RECT 196.16 335.705 196.36 336.435 ; + RECT 196.655 335.705 196.855 336.435 ; + RECT 197.655 0.17 198.425 0.94 ; + RECT 197.655 0.17 197.915 12.9 ; + RECT 198.165 0.17 198.425 12.9 ; + RECT 197.155 335.705 197.355 336.435 ; + RECT 197.655 335.705 197.855 336.435 ; + RECT 198.15 335.705 198.35 336.435 ; + RECT 198.675 0.52 198.935 5.815 ; + RECT 199.53 0.52 199.79 5.16 ; + RECT 199.53 4.9 200.31 5.16 ; + RECT 200.05 4.9 200.31 6.64 ; + RECT 198.97 335.705 199.17 336.435 ; + RECT 199.465 335.705 199.665 336.435 ; + RECT 199.965 335.705 200.165 336.435 ; + RECT 200.465 335.705 200.665 336.435 ; + RECT 200.96 335.705 201.16 336.435 ; + RECT 201.78 335.705 201.98 336.435 ; + RECT 202.275 335.705 202.475 336.435 ; + RECT 202.775 335.705 202.975 336.435 ; + RECT 202.93 0.52 203.19 2.335 ; + RECT 203.275 335.705 203.475 336.435 ; + RECT 203.44 0.52 203.7 14.11 ; + RECT 203.77 335.705 203.97 336.435 ; + RECT 204.815 0.17 205.585 0.94 ; + RECT 205.325 0.17 205.585 8.7 ; + RECT 204.815 0.17 205.075 12.9 ; + RECT 204.305 0.52 204.565 2.485 ; + RECT 204.59 335.705 204.79 336.435 ; + RECT 205.835 0.17 206.605 0.43 ; + RECT 206.345 0.17 206.605 10.48 ; + RECT 205.835 0.17 206.095 10.99 ; + RECT 205.085 335.705 205.285 336.435 ; + RECT 205.585 335.705 205.785 336.435 ; + RECT 206.085 335.705 206.285 336.435 ; + RECT 206.58 335.705 206.78 336.435 ; + RECT 207.875 0.17 208.645 0.43 ; + RECT 207.875 0.17 208.135 11.5 ; + RECT 208.385 0.17 208.645 11.5 ; + RECT 207.4 335.705 207.6 336.435 ; + RECT 207.895 335.705 208.095 336.435 ; + RECT 208.895 0.17 209.665 0.94 ; + RECT 208.895 0.17 209.155 12.9 ; + RECT 209.405 0.17 209.665 12.9 ; + RECT 208.395 335.705 208.595 336.435 ; + RECT 208.895 335.705 209.095 336.435 ; + RECT 209.39 335.705 209.59 336.435 ; + RECT 209.915 0.52 210.175 5.815 ; + RECT 210.77 0.52 211.03 5.16 ; + RECT 210.77 4.9 211.55 5.16 ; + RECT 211.29 4.9 211.55 6.64 ; + RECT 210.21 335.705 210.41 336.435 ; + RECT 210.705 335.705 210.905 336.435 ; + RECT 211.205 335.705 211.405 336.435 ; + RECT 211.705 335.705 211.905 336.435 ; + RECT 212.2 335.705 212.4 336.435 ; + RECT 213.02 335.705 213.22 336.435 ; + RECT 213.515 335.705 213.715 336.435 ; + RECT 214.015 335.705 214.215 336.435 ; + RECT 214.17 0.52 214.43 2.335 ; + RECT 214.515 335.705 214.715 336.435 ; + RECT 214.68 0.52 214.94 14.11 ; + RECT 215.01 335.705 215.21 336.435 ; + RECT 216.055 0.17 216.825 0.94 ; + RECT 216.565 0.17 216.825 8.7 ; + RECT 216.055 0.17 216.315 12.9 ; + RECT 215.545 0.52 215.805 2.485 ; + RECT 215.83 335.705 216.03 336.435 ; + RECT 217.075 0.17 217.845 0.43 ; + RECT 217.585 0.17 217.845 10.48 ; + RECT 217.075 0.17 217.335 10.99 ; + RECT 216.325 335.705 216.525 336.435 ; + RECT 216.825 335.705 217.025 336.435 ; + RECT 217.325 335.705 217.525 336.435 ; + RECT 217.82 335.705 218.02 336.435 ; + RECT 219.115 0.17 219.885 0.43 ; + RECT 219.115 0.17 219.375 11.5 ; + RECT 219.625 0.17 219.885 11.5 ; + RECT 218.64 335.705 218.84 336.435 ; + RECT 219.135 335.705 219.335 336.435 ; + RECT 220.135 0.17 220.905 0.94 ; + RECT 220.135 0.17 220.395 12.9 ; + RECT 220.645 0.17 220.905 12.9 ; + RECT 219.635 335.705 219.835 336.435 ; + RECT 220.135 335.705 220.335 336.435 ; + RECT 220.63 335.705 220.83 336.435 ; + RECT 221.155 0.52 221.415 5.815 ; + RECT 222.01 0.52 222.27 5.16 ; + RECT 222.01 4.9 222.79 5.16 ; + RECT 222.53 4.9 222.79 6.64 ; + RECT 221.45 335.705 221.65 336.435 ; + RECT 221.945 335.705 222.145 336.435 ; + RECT 222.445 335.705 222.645 336.435 ; + RECT 222.945 335.705 223.145 336.435 ; + RECT 223.44 335.705 223.64 336.435 ; + RECT 224.26 335.705 224.46 336.435 ; + RECT 224.755 335.705 224.955 336.435 ; + RECT 225.255 335.705 225.455 336.435 ; + RECT 225.41 0.52 225.67 2.335 ; + RECT 225.755 335.705 225.955 336.435 ; + RECT 225.92 0.52 226.18 14.11 ; + RECT 226.25 335.705 226.45 336.435 ; + RECT 227.295 0.17 228.065 0.94 ; + RECT 227.805 0.17 228.065 8.7 ; + RECT 227.295 0.17 227.555 12.9 ; + RECT 226.785 0.52 227.045 2.485 ; + RECT 227.07 335.705 227.27 336.435 ; + RECT 228.315 0.17 229.085 0.43 ; + RECT 228.825 0.17 229.085 10.48 ; + RECT 228.315 0.17 228.575 10.99 ; + RECT 227.565 335.705 227.765 336.435 ; + RECT 228.065 335.705 228.265 336.435 ; + RECT 228.565 335.705 228.765 336.435 ; + RECT 229.06 335.705 229.26 336.435 ; + RECT 230.355 0.17 231.125 0.43 ; + RECT 230.355 0.17 230.615 11.5 ; + RECT 230.865 0.17 231.125 11.5 ; + RECT 229.88 335.705 230.08 336.435 ; + RECT 230.375 335.705 230.575 336.435 ; + RECT 231.375 0.17 232.145 0.94 ; + RECT 231.375 0.17 231.635 12.9 ; + RECT 231.885 0.17 232.145 12.9 ; + RECT 230.875 335.705 231.075 336.435 ; + RECT 231.375 335.705 231.575 336.435 ; + RECT 231.87 335.705 232.07 336.435 ; + RECT 232.395 0.52 232.655 5.815 ; + RECT 233.25 0.52 233.51 5.16 ; + RECT 233.25 4.9 234.03 5.16 ; + RECT 233.77 4.9 234.03 6.64 ; + RECT 232.69 335.705 232.89 336.435 ; + RECT 233.185 335.705 233.385 336.435 ; + RECT 233.685 335.705 233.885 336.435 ; + RECT 234.185 335.705 234.385 336.435 ; + RECT 234.68 335.705 234.88 336.435 ; + RECT 235.5 335.705 235.7 336.435 ; + RECT 236.495 45.465 236.695 336.435 ; + LAYER Metal2 SPACING 0.21 ; + RECT 118.18 0 118.42 336.46 ; + RECT 128.38 0 132.19 336.46 ; + RECT 133.48 0 134.23 336.46 ; + RECT 0 0 3.03 336.46 ; + RECT 4.655 0.17 9.505 336.46 ; + RECT 11.65 0 14.27 336.46 ; + RECT 15.895 0.17 20.745 336.46 ; + RECT 22.89 0 25.51 336.46 ; + RECT 27.135 0.17 31.985 336.46 ; + RECT 34.13 0 36.75 336.46 ; + RECT 38.375 0.17 43.225 336.46 ; + RECT 45.37 0 47.99 336.46 ; + RECT 49.615 0.17 54.465 336.46 ; + RECT 56.61 0 59.23 336.46 ; + RECT 60.855 0.17 65.705 336.46 ; + RECT 67.85 0 70.47 336.46 ; + RECT 72.095 0.17 76.945 336.46 ; + RECT 79.09 0 81.71 336.46 ; + RECT 83.335 0.17 88.185 336.46 ; + RECT 90.33 0 102.11 336.46 ; + RECT 104.4 0.17 110.78 336.46 ; + RECT 112.05 0.3 112.31 336.46 ; + RECT 113.58 0.3 113.84 336.46 ; + RECT 116.64 0.3 116.9 336.46 ; + RECT 118.17 0.3 118.43 336.46 ; + RECT 119.71 0.17 120.98 336.46 ; + RECT 119.7 0.3 120.98 336.46 ; + RECT 125.31 0.17 127.1 336.46 ; + RECT 128.37 0.3 132.2 336.46 ; + RECT 133.47 0.3 134.24 336.46 ; + RECT 135.01 0 146.47 336.46 ; + RECT 135 0.17 146.47 336.46 ; + RECT 148.615 0.17 153.465 336.46 ; + RECT 155.09 0 157.71 336.46 ; + RECT 159.855 0.17 164.705 336.46 ; + RECT 166.33 0 168.95 336.46 ; + RECT 171.095 0.17 175.945 336.46 ; + RECT 177.57 0 180.19 336.46 ; + RECT 182.335 0.17 187.185 336.46 ; + RECT 188.81 0 191.43 336.46 ; + RECT 193.575 0.17 198.425 336.46 ; + RECT 200.05 0 202.67 336.46 ; + RECT 204.815 0.17 209.665 336.46 ; + RECT 211.29 0 213.91 336.46 ; + RECT 216.055 0.17 220.905 336.46 ; + RECT 222.53 0 225.15 336.46 ; + RECT 227.295 0.17 232.145 336.46 ; + RECT 233.77 0 236.8 336.46 ; + RECT 0 0.52 236.8 336.46 ; + RECT 4.665 0 9.495 336.46 ; + RECT 15.905 0 20.735 336.46 ; + RECT 27.145 0 31.975 336.46 ; + RECT 38.385 0 43.215 336.46 ; + RECT 49.625 0 54.455 336.46 ; + RECT 60.865 0 65.695 336.46 ; + RECT 72.105 0 76.935 336.46 ; + RECT 83.345 0 88.175 336.46 ; + RECT 104.4 0 110.77 336.46 ; + RECT 119.71 0 120.97 336.46 ; + RECT 125.31 0 127.09 336.46 ; + RECT 148.625 0 153.455 336.46 ; + RECT 159.865 0 164.695 336.46 ; + RECT 171.105 0 175.935 336.46 ; + RECT 182.345 0 187.175 336.46 ; + RECT 193.585 0 198.415 336.46 ; + RECT 204.825 0 209.655 336.46 ; + RECT 216.065 0 220.895 336.46 ; + RECT 227.305 0 232.135 336.46 ; + RECT 112.06 0 112.3 336.46 ; + RECT 113.59 0 113.83 336.46 ; + RECT 116.65 0 116.89 336.46 ; + LAYER Metal3 ; + RECT 0 0 236.8 336.46 ; + LAYER Metal4 SPACING 0.21 ; + RECT 0 39.085 9.62 45.205 ; + RECT 0 0 4 336.46 ; + RECT 7.33 0 9.62 336.46 ; + RECT 12.95 39.085 20.86 45.205 ; + RECT 12.95 0 15.24 336.46 ; + RECT 18.57 0 20.86 336.46 ; + RECT 24.19 39.085 32.1 45.205 ; + RECT 24.19 0 26.48 336.46 ; + RECT 29.81 0 32.1 336.46 ; + RECT 35.43 39.085 43.34 45.205 ; + RECT 35.43 0 37.72 336.46 ; + RECT 41.05 0 43.34 336.46 ; + RECT 46.67 39.085 54.58 45.205 ; + RECT 46.67 0 48.96 336.46 ; + RECT 52.29 0 54.58 336.46 ; + RECT 57.91 39.085 65.82 45.205 ; + RECT 57.91 0 60.2 336.46 ; + RECT 63.53 0 65.82 336.46 ; + RECT 69.15 39.085 77.06 45.205 ; + RECT 69.15 0 71.44 336.46 ; + RECT 74.77 0 77.06 336.46 ; + RECT 80.39 39.085 88.3 45.205 ; + RECT 80.39 0 82.68 336.46 ; + RECT 86.01 0 88.3 336.46 ; + RECT 91.63 0 98.71 336.46 ; + RECT 102.04 0 103.86 336.46 ; + RECT 107.19 0 109.01 336.46 ; + RECT 112.34 0 114.16 336.46 ; + RECT 117.49 0 119.31 336.46 ; + RECT 122.64 0 124.46 336.46 ; + RECT 148.5 39.085 156.41 45.205 ; + RECT 148.5 0 150.79 336.46 ; + RECT 154.12 0 156.41 336.46 ; + RECT 159.74 39.085 167.65 45.205 ; + RECT 159.74 0 162.03 336.46 ; + RECT 165.36 0 167.65 336.46 ; + RECT 170.98 39.085 178.89 45.205 ; + RECT 170.98 0 173.27 336.46 ; + RECT 176.6 0 178.89 336.46 ; + RECT 182.22 39.085 190.13 45.205 ; + RECT 182.22 0 184.51 336.46 ; + RECT 187.84 0 190.13 336.46 ; + RECT 193.46 39.085 201.37 45.205 ; + RECT 193.46 0 195.75 336.46 ; + RECT 199.08 0 201.37 336.46 ; + RECT 204.7 39.085 212.61 45.205 ; + RECT 204.7 0 206.99 336.46 ; + RECT 210.32 0 212.61 336.46 ; + RECT 215.94 39.085 223.85 45.205 ; + RECT 215.94 0 218.23 336.46 ; + RECT 221.56 0 223.85 336.46 ; + RECT 227.18 39.085 236.8 45.205 ; + RECT 227.18 0 229.47 336.46 ; + RECT 232.8 0 236.8 336.46 ; + RECT 127.79 0 129.61 336.46 ; + RECT 132.94 0 134.76 336.46 ; + RECT 138.09 0 145.17 336.46 ; + END +END RM_IHPSG13_1P_1024x16_c2_bm_bist + +END LIBRARY diff --git a/flow/platforms/ihp-sg13g2/lef/RM_IHPSG13_1P_1024x8_c2_bm_bist.lef b/flow/platforms/ihp-sg13g2/lef/RM_IHPSG13_1P_1024x8_c2_bm_bist.lef new file mode 100644 index 0000000000..79735c6ab7 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lef/RM_IHPSG13_1P_1024x8_c2_bm_bist.lef @@ -0,0 +1,1548 @@ +# ------------------------------------------------------ +# +# Copyright 2024 IHP PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# Generated on Fri Jul 19 09:01:22 2024 +# +# ------------------------------------------------------ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +DIVIDERCHAR "/" ; + +MACRO RM_IHPSG13_1P_1024x8_c2_bm_bist + CLASS BLOCK ; + ORIGIN 0 0 ; + FOREIGN RM_IHPSG13_1P_1024x8_c2_bm_bist 0 0 ; + SIZE 146.88 BY 336.46 ; + SYMMETRY X Y R90 ; + PIN A_DIN[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 109.61 0 109.87 0.26 ; + END + END A_DIN[4] + PIN A_DIN[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 37.01 0 37.27 0.26 ; + END + END A_DIN[3] + PIN A_BIST_DIN[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 108.755 0 109.015 0.26 ; + END + END A_BIST_DIN[4] + PIN A_BIST_DIN[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 37.865 0 38.125 0.26 ; + END + END A_BIST_DIN[3] + PIN A_BM[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 101.77 0 102.03 0.26 ; + END + END A_BM[4] + PIN A_BM[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 44.85 0 45.11 0.26 ; + END + END A_BM[3] + PIN A_BIST_BM[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 103.145 0 103.405 0.26 ; + END + END A_BIST_BM[4] + PIN A_BIST_BM[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 43.475 0 43.735 0.26 ; + END + END A_BIST_BM[3] + PIN A_DOUT[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 102.28 0 102.54 0.26 ; + END + END A_DOUT[4] + PIN A_DOUT[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 44.34 0 44.6 0.26 ; + END + END A_DOUT[3] + PIN VSS! + DIRECTION INOUT ; + USE GROUND ; + NETEXPR "vss VSS!" ; + PORT + LAYER Metal4 ; + RECT 134.19 0 137 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 122.95 0 125.76 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 111.71 0 114.52 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 100.47 0 103.28 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 90.06 0 92.87 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 79.76 0 82.57 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 64.31 0 67.12 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 54.01 0 56.82 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 43.6 0 46.41 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 32.36 0 35.17 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 21.12 0 23.93 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 9.88 0 12.69 336.46 ; + END + END VSS! + PIN VDD! + DIRECTION INOUT ; + USE POWER ; + NETEXPR "vdd VDD!" ; + PORT + LAYER Metal4 ; + RECT 139.81 0 142.62 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 128.57 0 131.38 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 117.33 0 120.14 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 106.09 0 108.9 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 84.91 0 87.72 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 74.61 0 77.42 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 69.46 0 72.27 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 59.16 0 61.97 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 37.98 0 40.79 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 26.74 0 29.55 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 15.5 0 18.31 38.825 ; + END + PORT + LAYER Metal4 ; + RECT 4.26 0 7.07 38.825 ; + END + END VDD! + PIN VDDARRAY! + DIRECTION INOUT ; + USE POWER ; + NETEXPR "vddarray VDDARRAY!" ; + PORT + LAYER Metal4 ; + RECT 139.81 45.465 142.62 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 128.57 45.465 131.38 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 117.33 45.465 120.14 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 106.09 45.465 108.9 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 37.98 45.465 40.79 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 26.74 45.465 29.55 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 15.5 45.465 18.31 336.46 ; + END + PORT + LAYER Metal4 ; + RECT 4.26 45.465 7.07 336.46 ; + END + END VDDARRAY! + PIN A_DIN[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 120.85 0 121.11 0.26 ; + END + END A_DIN[5] + PIN A_DIN[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 25.77 0 26.03 0.26 ; + END + END A_DIN[2] + PIN A_BIST_DIN[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 119.995 0 120.255 0.26 ; + END + END A_BIST_DIN[5] + PIN A_BIST_DIN[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 26.625 0 26.885 0.26 ; + END + END A_BIST_DIN[2] + PIN A_BM[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 113.01 0 113.27 0.26 ; + END + END A_BM[5] + PIN A_BM[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 33.61 0 33.87 0.26 ; + END + END A_BM[2] + PIN A_BIST_BM[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 114.385 0 114.645 0.26 ; + END + END A_BIST_BM[5] + PIN A_BIST_BM[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 32.235 0 32.495 0.26 ; + END + END A_BIST_BM[2] + PIN A_DOUT[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 113.52 0 113.78 0.26 ; + END + END A_DOUT[5] + PIN A_DOUT[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 33.1 0 33.36 0.26 ; + END + END A_DOUT[2] + PIN A_DIN[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 132.09 0 132.35 0.26 ; + END + END A_DIN[6] + PIN A_DIN[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 14.53 0 14.79 0.26 ; + END + END A_DIN[1] + PIN A_BIST_DIN[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 131.235 0 131.495 0.26 ; + END + END A_BIST_DIN[6] + PIN A_BIST_DIN[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 15.385 0 15.645 0.26 ; + END + END A_BIST_DIN[1] + PIN A_BM[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 124.25 0 124.51 0.26 ; + END + END A_BM[6] + PIN A_BM[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 22.37 0 22.63 0.26 ; + END + END A_BM[1] + PIN A_BIST_BM[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 125.625 0 125.885 0.26 ; + END + END A_BIST_BM[6] + PIN A_BIST_BM[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 20.995 0 21.255 0.26 ; + END + END A_BIST_BM[1] + PIN A_DOUT[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 124.76 0 125.02 0.26 ; + END + END A_DOUT[6] + PIN A_DOUT[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 21.86 0 22.12 0.26 ; + END + END A_DOUT[1] + PIN A_DIN[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 143.33 0 143.59 0.26 ; + END + END A_DIN[7] + PIN A_DIN[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 3.29 0 3.55 0.26 ; + END + END A_DIN[0] + PIN A_BIST_DIN[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 142.475 0 142.735 0.26 ; + END + END A_BIST_DIN[7] + PIN A_BIST_DIN[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 4.145 0 4.405 0.26 ; + END + END A_BIST_DIN[0] + PIN A_BM[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 135.49 0 135.75 0.26 ; + END + END A_BM[7] + PIN A_BM[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 11.13 0 11.39 0.26 ; + END + END A_BM[0] + PIN A_BIST_BM[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 136.865 0 137.125 0.26 ; + END + END A_BIST_BM[7] + PIN A_BIST_BM[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 9.755 0 10.015 0.26 ; + END + END A_BIST_BM[0] + PIN A_DOUT[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 136 0 136.26 0.26 ; + END + END A_DOUT[7] + PIN A_DOUT[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 10.62 0 10.88 0.26 ; + END + END A_DOUT[0] + PIN A_ADDR[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 8.9011 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 45.223301 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 69.64 0 69.9 0.26 ; + END + END A_ADDR[0] + PIN A_BIST_ADDR[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 9.6967 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 49.184466 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 74.23 0 74.49 0.26 ; + END + END A_BIST_ADDR[0] + PIN A_ADDR[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 7.774 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 39.656958 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 69.13 0 69.39 0.26 ; + END + END A_ADDR[1] + PIN A_BIST_ADDR[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 8.5696 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 43.618123 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 73.72 0 73.98 0.26 ; + END + END A_BIST_ADDR[1] + PIN A_ADDR[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 10.6327 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.5246 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 9.415982 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 77.29 0 77.55 0.26 ; + END + END A_ADDR[2] + PIN A_BIST_ADDR[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 10.6327 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.0962 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 7.813791 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 77.8 0 78.06 0.26 ; + END + END A_BIST_ADDR[2] + PIN A_ADDR[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 10.6327 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 3.8367 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 20.927558 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 76.27 0 76.53 0.26 ; + END + END A_ADDR[3] + PIN A_BIST_ADDR[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 10.6327 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 3.5175 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 19.869057 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 76.78 0 77.04 0.26 ; + END + END A_BIST_ADDR[3] + PIN A_ADDR[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 12.1979 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 61.63754 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 79.84 0 80.1 0.26 ; + END + END A_ADDR[4] + PIN A_BIST_ADDR[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 11.9327 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 60.317152 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 79.33 0 79.59 0.26 ; + END + END A_BIST_ADDR[4] + PIN A_ADDR[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.9269 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 70.245955 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 78.82 0 79.08 0.26 ; + END + END A_ADDR[5] + PIN A_BIST_ADDR[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 13.6617 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 68.925566 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 78.31 0 78.57 0.26 ; + END + END A_BIST_ADDR[5] + PIN A_ADDR[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 10.9525 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 55.436893 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 57.4 0 57.66 0.26 ; + END + END A_ADDR[6] + PIN A_BIST_ADDR[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 10.6771 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 54.065721 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 57.91 0 58.17 0.26 ; + END + END A_BIST_ADDR[6] + PIN A_ADDR[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 12.4163 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 62.724919 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 58.42 0 58.68 0.26 ; + END + END A_ADDR[7] + PIN A_BIST_ADDR[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 12.1511 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 61.404531 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 58.93 0 59.19 0.26 ; + END + END A_BIST_ADDR[7] + PIN A_ADDR[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 10.3675 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.5897 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 9.740105 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 87.49 0 87.75 0.26 ; + END + END A_ADDR[8] + PIN A_BIST_ADDR[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 10.3675 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.3755 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 9.204381 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 88 0 88.26 0.26 ; + END + END A_BIST_ADDR[8] + PIN A_ADDR[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 12.2633 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 61.963157 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 82.39 0 82.65 0.26 ; + END + END A_ADDR[9] + PIN A_BIST_ADDR[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 12.0083 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 60.693552 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 82.9 0 83.16 0.26 ; + END + END A_BIST_ADDR[9] + PIN A_CLK + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.0547 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.093851 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 67.6 0 67.86 0.26 ; + END + END A_CLK + PIN A_REN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.99505 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 20.796863 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 71.17 0 71.43 0.26 ; + END + END A_REN + PIN A_WEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8847 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.268608 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 70.66 0 70.92 0.26 ; + END + END A_WEN + PIN A_MEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.0247 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.965646 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 68.11 0 68.37 0.26 ; + END + END A_MEN + PIN A_DLY + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 6.058 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.3367 LAYER Metal2 ; + ANTENNAMAXAREACAR 18.532819 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 89.53 0 89.79 0.26 ; + END + END A_DLY + PIN A_BIST_EN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.9871 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 70.28015 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 1.43 LAYER Metal2 ; + ANTENNAGATEAREA 10.725 LAYER Metal3 ; + ANTENNAMAXAREACAR 3.213636 LAYER Metal2 ; + ANTENNAMAXAREACAR 16.825655 LAYER Metal3 ; + ANTENNAMAXCUTCAR 0.151469 LAYER Via2 ; + PORT + LAYER Metal2 ; + RECT 70.15 0 70.41 0.26 ; + END + END A_BIST_EN + PIN A_BIST_CLK + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.1639 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.953448 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 66.07 0 66.33 0.26 ; + END + END A_BIST_CLK + PIN A_BIST_REN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 4.1119 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 21.694548 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 72.7 0 72.96 0.26 ; + END + END A_BIST_REN + PIN A_BIST_WEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.9051 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.686084 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 72.19 0 72.45 0.26 ; + END + END A_BIST_WEN + PIN A_BIST_MEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.8977 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 15.649241 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 66.58 0 66.84 0.26 ; + END + END A_BIST_MEN + OBS + LAYER Metal1 ; + RECT 0 0 146.88 336.46 ; + LAYER Metal2 ; + RECT 0.105 45.465 0.305 336.435 ; + RECT 1.1 335.705 1.3 336.435 ; + RECT 3.29 0.52 3.55 5.16 ; + RECT 2.77 4.9 3.55 5.16 ; + RECT 2.77 4.9 3.03 6.64 ; + RECT 1.92 335.705 2.12 336.435 ; + RECT 2.415 335.705 2.615 336.435 ; + RECT 2.915 335.705 3.115 336.435 ; + RECT 3.415 335.705 3.615 336.435 ; + RECT 3.91 335.705 4.11 336.435 ; + RECT 4.655 0.17 5.425 0.94 ; + RECT 4.655 0.17 4.915 12.9 ; + RECT 5.165 0.17 5.425 12.9 ; + RECT 4.145 0.52 4.405 5.815 ; + RECT 4.73 335.705 4.93 336.435 ; + RECT 5.675 0.17 6.445 0.43 ; + RECT 5.675 0.17 5.935 11.5 ; + RECT 6.185 0.17 6.445 11.5 ; + RECT 5.225 335.705 5.425 336.435 ; + RECT 5.725 335.705 5.925 336.435 ; + RECT 6.225 335.705 6.425 336.435 ; + RECT 7.715 0.17 8.485 0.43 ; + RECT 7.715 0.17 7.975 10.48 ; + RECT 8.225 0.17 8.485 10.99 ; + RECT 6.72 335.705 6.92 336.435 ; + RECT 7.54 335.705 7.74 336.435 ; + RECT 8.735 0.17 9.505 0.94 ; + RECT 8.735 0.17 8.995 8.7 ; + RECT 9.245 0.17 9.505 12.9 ; + RECT 8.035 335.705 8.235 336.435 ; + RECT 8.535 335.705 8.735 336.435 ; + RECT 9.035 335.705 9.235 336.435 ; + RECT 9.53 335.705 9.73 336.435 ; + RECT 9.755 0.52 10.015 2.485 ; + RECT 10.35 335.705 10.55 336.435 ; + RECT 10.62 0.52 10.88 14.11 ; + RECT 10.845 335.705 11.045 336.435 ; + RECT 11.13 0.52 11.39 2.335 ; + RECT 11.345 335.705 11.545 336.435 ; + RECT 11.845 335.705 12.045 336.435 ; + RECT 12.34 335.705 12.54 336.435 ; + RECT 14.53 0.52 14.79 5.16 ; + RECT 14.01 4.9 14.79 5.16 ; + RECT 14.01 4.9 14.27 6.64 ; + RECT 13.16 335.705 13.36 336.435 ; + RECT 13.655 335.705 13.855 336.435 ; + RECT 14.155 335.705 14.355 336.435 ; + RECT 14.655 335.705 14.855 336.435 ; + RECT 15.15 335.705 15.35 336.435 ; + RECT 15.895 0.17 16.665 0.94 ; + RECT 15.895 0.17 16.155 12.9 ; + RECT 16.405 0.17 16.665 12.9 ; + RECT 15.385 0.52 15.645 5.815 ; + RECT 15.97 335.705 16.17 336.435 ; + RECT 16.915 0.17 17.685 0.43 ; + RECT 16.915 0.17 17.175 11.5 ; + RECT 17.425 0.17 17.685 11.5 ; + RECT 16.465 335.705 16.665 336.435 ; + RECT 16.965 335.705 17.165 336.435 ; + RECT 17.465 335.705 17.665 336.435 ; + RECT 18.955 0.17 19.725 0.43 ; + RECT 18.955 0.17 19.215 10.48 ; + RECT 19.465 0.17 19.725 10.99 ; + RECT 17.96 335.705 18.16 336.435 ; + RECT 18.78 335.705 18.98 336.435 ; + RECT 19.975 0.17 20.745 0.94 ; + RECT 19.975 0.17 20.235 8.7 ; + RECT 20.485 0.17 20.745 12.9 ; + RECT 19.275 335.705 19.475 336.435 ; + RECT 19.775 335.705 19.975 336.435 ; + RECT 20.275 335.705 20.475 336.435 ; + RECT 20.77 335.705 20.97 336.435 ; + RECT 20.995 0.52 21.255 2.485 ; + RECT 21.59 335.705 21.79 336.435 ; + RECT 21.86 0.52 22.12 14.11 ; + RECT 22.085 335.705 22.285 336.435 ; + RECT 22.37 0.52 22.63 2.335 ; + RECT 22.585 335.705 22.785 336.435 ; + RECT 23.085 335.705 23.285 336.435 ; + RECT 23.58 335.705 23.78 336.435 ; + RECT 25.77 0.52 26.03 5.16 ; + RECT 25.25 4.9 26.03 5.16 ; + RECT 25.25 4.9 25.51 6.64 ; + RECT 24.4 335.705 24.6 336.435 ; + RECT 24.895 335.705 25.095 336.435 ; + RECT 25.395 335.705 25.595 336.435 ; + RECT 25.895 335.705 26.095 336.435 ; + RECT 26.39 335.705 26.59 336.435 ; + RECT 27.135 0.17 27.905 0.94 ; + RECT 27.135 0.17 27.395 12.9 ; + RECT 27.645 0.17 27.905 12.9 ; + RECT 26.625 0.52 26.885 5.815 ; + RECT 27.21 335.705 27.41 336.435 ; + RECT 28.155 0.17 28.925 0.43 ; + RECT 28.155 0.17 28.415 11.5 ; + RECT 28.665 0.17 28.925 11.5 ; + RECT 27.705 335.705 27.905 336.435 ; + RECT 28.205 335.705 28.405 336.435 ; + RECT 28.705 335.705 28.905 336.435 ; + RECT 30.195 0.17 30.965 0.43 ; + RECT 30.195 0.17 30.455 10.48 ; + RECT 30.705 0.17 30.965 10.99 ; + RECT 29.2 335.705 29.4 336.435 ; + RECT 30.02 335.705 30.22 336.435 ; + RECT 31.215 0.17 31.985 0.94 ; + RECT 31.215 0.17 31.475 8.7 ; + RECT 31.725 0.17 31.985 12.9 ; + RECT 30.515 335.705 30.715 336.435 ; + RECT 31.015 335.705 31.215 336.435 ; + RECT 31.515 335.705 31.715 336.435 ; + RECT 32.01 335.705 32.21 336.435 ; + RECT 32.235 0.52 32.495 2.485 ; + RECT 32.83 335.705 33.03 336.435 ; + RECT 33.1 0.52 33.36 14.11 ; + RECT 33.325 335.705 33.525 336.435 ; + RECT 33.61 0.52 33.87 2.335 ; + RECT 33.825 335.705 34.025 336.435 ; + RECT 34.325 335.705 34.525 336.435 ; + RECT 34.82 335.705 35.02 336.435 ; + RECT 37.01 0.52 37.27 5.16 ; + RECT 36.49 4.9 37.27 5.16 ; + RECT 36.49 4.9 36.75 6.64 ; + RECT 35.64 335.705 35.84 336.435 ; + RECT 36.135 335.705 36.335 336.435 ; + RECT 36.635 335.705 36.835 336.435 ; + RECT 37.135 335.705 37.335 336.435 ; + RECT 37.63 335.705 37.83 336.435 ; + RECT 38.375 0.17 39.145 0.94 ; + RECT 38.375 0.17 38.635 12.9 ; + RECT 38.885 0.17 39.145 12.9 ; + RECT 37.865 0.52 38.125 5.815 ; + RECT 38.45 335.705 38.65 336.435 ; + RECT 39.395 0.17 40.165 0.43 ; + RECT 39.395 0.17 39.655 11.5 ; + RECT 39.905 0.17 40.165 11.5 ; + RECT 38.945 335.705 39.145 336.435 ; + RECT 39.445 335.705 39.645 336.435 ; + RECT 39.945 335.705 40.145 336.435 ; + RECT 41.435 0.17 42.205 0.43 ; + RECT 41.435 0.17 41.695 10.48 ; + RECT 41.945 0.17 42.205 10.99 ; + RECT 40.44 335.705 40.64 336.435 ; + RECT 41.26 335.705 41.46 336.435 ; + RECT 42.455 0.17 43.225 0.94 ; + RECT 42.455 0.17 42.715 8.7 ; + RECT 42.965 0.17 43.225 12.9 ; + RECT 41.755 335.705 41.955 336.435 ; + RECT 42.255 335.705 42.455 336.435 ; + RECT 42.755 335.705 42.955 336.435 ; + RECT 43.25 335.705 43.45 336.435 ; + RECT 43.475 0.52 43.735 2.485 ; + RECT 44.07 335.705 44.27 336.435 ; + RECT 44.34 0.52 44.6 14.11 ; + RECT 44.565 335.705 44.765 336.435 ; + RECT 44.85 0.52 45.11 2.335 ; + RECT 45.065 335.705 45.265 336.435 ; + RECT 45.565 335.705 45.765 336.435 ; + RECT 47.555 0.17 48.325 0.43 ; + RECT 47.555 0.17 47.815 8.7 ; + RECT 48.065 0.17 48.325 8.7 ; + RECT 48.575 0.17 49.345 0.94 ; + RECT 48.575 0.17 48.835 8.7 ; + RECT 49.085 0.17 49.345 8.7 ; + RECT 49.595 0.17 50.365 0.43 ; + RECT 49.595 0.17 49.855 8.7 ; + RECT 50.105 0.17 50.365 8.7 ; + RECT 50.615 0.17 51.385 0.94 ; + RECT 50.615 0.17 50.875 8.7 ; + RECT 51.125 0.17 51.385 8.7 ; + RECT 51.635 0.17 52.405 0.43 ; + RECT 51.635 0.17 51.895 8.7 ; + RECT 52.145 0.17 52.405 8.7 ; + RECT 52.655 0.17 53.425 0.94 ; + RECT 52.655 0.17 52.915 8.7 ; + RECT 53.165 0.17 53.425 8.7 ; + RECT 46.06 335.705 46.26 336.435 ; + RECT 46.88 335.705 47.08 336.435 ; + RECT 47.875 335.705 48.075 336.435 ; + RECT 55.36 0.17 56.13 0.94 ; + RECT 55.36 0.17 55.62 8.7 ; + RECT 55.87 0.17 56.13 8.7 ; + RECT 53.83 0.3 54.09 8.7 ; + RECT 54.34 0 54.6 8.7 ; + RECT 54.85 0 55.11 8.7 ; + RECT 56.38 0 56.64 8.7 ; + RECT 56.89 0 57.15 8.7 ; + RECT 57.4 0.52 57.66 8.7 ; + RECT 57.91 0.52 58.17 8.7 ; + RECT 58.42 0.52 58.68 8.7 ; + RECT 60.46 0.17 61.23 0.94 ; + RECT 60.46 0.17 60.72 8.7 ; + RECT 60.97 0.17 61.23 8.7 ; + RECT 61.48 0.17 62.25 0.43 ; + RECT 61.48 0.17 61.74 8.7 ; + RECT 61.99 0.17 62.25 8.7 ; + RECT 58.93 0.52 59.19 8.7 ; + RECT 59.44 0 59.7 8.7 ; + RECT 59.95 0 60.21 8.7 ; + RECT 62.5 0.3 62.76 8.7 ; + RECT 63.01 0.3 63.27 8.7 ; + RECT 65.05 0.17 65.82 0.94 ; + RECT 65.05 0.17 65.31 8.7 ; + RECT 65.56 0.17 65.82 8.7 ; + RECT 63.52 0.3 63.78 8.7 ; + RECT 64.03 0.3 64.29 8.7 ; + RECT 64.54 0.3 64.8 8.7 ; + RECT 66.07 0.52 66.33 8.7 ; + RECT 66.58 0.52 66.84 8.7 ; + RECT 67.09 0.3 67.35 8.7 ; + RECT 67.6 0.52 67.86 8.7 ; + RECT 68.11 0.52 68.37 8.7 ; + RECT 68.62 0.3 68.88 8.7 ; + RECT 69.13 0.52 69.39 8.7 ; + RECT 69.64 0.52 69.9 8.7 ; + RECT 70.15 0.52 70.41 8.7 ; + RECT 70.66 0.52 70.92 8.7 ; + RECT 71.17 0.52 71.43 8.7 ; + RECT 71.68 0.3 71.94 8.7 ; + RECT 72.19 0.52 72.45 8.7 ; + RECT 72.7 0.52 72.96 8.7 ; + RECT 73.21 0.3 73.47 8.7 ; + RECT 75.25 0.17 76.02 0.94 ; + RECT 75.25 0.17 75.51 8.7 ; + RECT 75.76 0.17 76.02 8.7 ; + RECT 73.72 0.52 73.98 8.7 ; + RECT 74.23 0.52 74.49 8.7 ; + RECT 74.74 0.3 75 8.7 ; + RECT 76.27 0.52 76.53 8.7 ; + RECT 76.78 0.52 77.04 8.7 ; + RECT 77.29 0.52 77.55 8.7 ; + RECT 77.8 0.52 78.06 8.7 ; + RECT 78.31 0.52 78.57 8.7 ; + RECT 78.82 0.52 79.08 8.7 ; + RECT 79.33 0.52 79.59 8.7 ; + RECT 81.37 0.17 82.14 0.94 ; + RECT 81.37 0.17 81.63 8.7 ; + RECT 81.88 0.17 82.14 8.7 ; + RECT 79.84 0.52 80.1 8.7 ; + RECT 80.35 0 80.61 8.7 ; + RECT 80.86 0 81.12 8.7 ; + RECT 82.39 0.52 82.65 8.7 ; + RECT 84.43 0.17 85.2 0.43 ; + RECT 84.43 0.17 84.69 8.7 ; + RECT 84.94 0.17 85.2 8.7 ; + RECT 82.9 0.52 83.16 8.7 ; + RECT 83.41 0.3 83.67 8.7 ; + RECT 83.92 0.3 84.18 8.7 ; + RECT 85.45 0.3 85.71 8.7 ; + RECT 85.96 0.3 86.22 8.7 ; + RECT 86.47 0.3 86.73 8.7 ; + RECT 86.98 0.3 87.24 8.7 ; + RECT 87.49 0.52 87.75 8.7 ; + RECT 88 0.52 88.26 8.7 ; + RECT 90.04 0.17 90.81 0.43 ; + RECT 90.04 0.17 90.3 8.7 ; + RECT 90.55 0.17 90.81 8.7 ; + RECT 91.06 0.17 91.83 0.94 ; + RECT 91.06 0.17 91.32 25.5 ; + RECT 91.57 0.17 91.83 33.9 ; + RECT 92.08 0.17 92.85 0.43 ; + RECT 92.08 0.17 92.34 8.7 ; + RECT 92.59 0.17 92.85 8.7 ; + RECT 93.455 0.17 94.225 0.94 ; + RECT 93.455 0.17 93.715 8.7 ; + RECT 93.965 0.17 94.225 8.7 ; + RECT 94.475 0.17 95.245 0.43 ; + RECT 94.475 0.17 94.735 8.7 ; + RECT 94.985 0.17 95.245 8.7 ; + RECT 95.495 0.17 96.265 0.94 ; + RECT 95.495 0.17 95.755 8.7 ; + RECT 96.005 0.17 96.265 8.7 ; + RECT 96.515 0.17 97.285 0.43 ; + RECT 96.515 0.17 96.775 8.7 ; + RECT 97.025 0.17 97.285 8.7 ; + RECT 97.535 0.17 98.305 0.94 ; + RECT 97.535 0.17 97.795 8.7 ; + RECT 98.045 0.17 98.305 8.7 ; + RECT 88.51 0.3 88.77 8.7 ; + RECT 98.555 0.17 99.325 0.43 ; + RECT 98.555 0.17 98.815 8.7 ; + RECT 99.065 0.17 99.325 8.7 ; + RECT 89.02 0.3 89.28 8.7 ; + RECT 89.53 0.52 89.79 8.7 ; + RECT 98.805 335.705 99.005 336.435 ; + RECT 99.8 335.705 100 336.435 ; + RECT 100.62 335.705 100.82 336.435 ; + RECT 101.115 335.705 101.315 336.435 ; + RECT 101.615 335.705 101.815 336.435 ; + RECT 101.77 0.52 102.03 2.335 ; + RECT 102.115 335.705 102.315 336.435 ; + RECT 102.28 0.52 102.54 14.11 ; + RECT 102.61 335.705 102.81 336.435 ; + RECT 103.655 0.17 104.425 0.94 ; + RECT 104.165 0.17 104.425 8.7 ; + RECT 103.655 0.17 103.915 12.9 ; + RECT 103.145 0.52 103.405 2.485 ; + RECT 103.43 335.705 103.63 336.435 ; + RECT 104.675 0.17 105.445 0.43 ; + RECT 105.185 0.17 105.445 10.48 ; + RECT 104.675 0.17 104.935 10.99 ; + RECT 103.925 335.705 104.125 336.435 ; + RECT 104.425 335.705 104.625 336.435 ; + RECT 104.925 335.705 105.125 336.435 ; + RECT 105.42 335.705 105.62 336.435 ; + RECT 106.715 0.17 107.485 0.43 ; + RECT 106.715 0.17 106.975 11.5 ; + RECT 107.225 0.17 107.485 11.5 ; + RECT 106.24 335.705 106.44 336.435 ; + RECT 106.735 335.705 106.935 336.435 ; + RECT 107.735 0.17 108.505 0.94 ; + RECT 107.735 0.17 107.995 12.9 ; + RECT 108.245 0.17 108.505 12.9 ; + RECT 107.235 335.705 107.435 336.435 ; + RECT 107.735 335.705 107.935 336.435 ; + RECT 108.23 335.705 108.43 336.435 ; + RECT 108.755 0.52 109.015 5.815 ; + RECT 109.61 0.52 109.87 5.16 ; + RECT 109.61 4.9 110.39 5.16 ; + RECT 110.13 4.9 110.39 6.64 ; + RECT 109.05 335.705 109.25 336.435 ; + RECT 109.545 335.705 109.745 336.435 ; + RECT 110.045 335.705 110.245 336.435 ; + RECT 110.545 335.705 110.745 336.435 ; + RECT 111.04 335.705 111.24 336.435 ; + RECT 111.86 335.705 112.06 336.435 ; + RECT 112.355 335.705 112.555 336.435 ; + RECT 112.855 335.705 113.055 336.435 ; + RECT 113.01 0.52 113.27 2.335 ; + RECT 113.355 335.705 113.555 336.435 ; + RECT 113.52 0.52 113.78 14.11 ; + RECT 113.85 335.705 114.05 336.435 ; + RECT 114.895 0.17 115.665 0.94 ; + RECT 115.405 0.17 115.665 8.7 ; + RECT 114.895 0.17 115.155 12.9 ; + RECT 114.385 0.52 114.645 2.485 ; + RECT 114.67 335.705 114.87 336.435 ; + RECT 115.915 0.17 116.685 0.43 ; + RECT 116.425 0.17 116.685 10.48 ; + RECT 115.915 0.17 116.175 10.99 ; + RECT 115.165 335.705 115.365 336.435 ; + RECT 115.665 335.705 115.865 336.435 ; + RECT 116.165 335.705 116.365 336.435 ; + RECT 116.66 335.705 116.86 336.435 ; + RECT 117.955 0.17 118.725 0.43 ; + RECT 117.955 0.17 118.215 11.5 ; + RECT 118.465 0.17 118.725 11.5 ; + RECT 117.48 335.705 117.68 336.435 ; + RECT 117.975 335.705 118.175 336.435 ; + RECT 118.975 0.17 119.745 0.94 ; + RECT 118.975 0.17 119.235 12.9 ; + RECT 119.485 0.17 119.745 12.9 ; + RECT 118.475 335.705 118.675 336.435 ; + RECT 118.975 335.705 119.175 336.435 ; + RECT 119.47 335.705 119.67 336.435 ; + RECT 119.995 0.52 120.255 5.815 ; + RECT 120.85 0.52 121.11 5.16 ; + RECT 120.85 4.9 121.63 5.16 ; + RECT 121.37 4.9 121.63 6.64 ; + RECT 120.29 335.705 120.49 336.435 ; + RECT 120.785 335.705 120.985 336.435 ; + RECT 121.285 335.705 121.485 336.435 ; + RECT 121.785 335.705 121.985 336.435 ; + RECT 122.28 335.705 122.48 336.435 ; + RECT 123.1 335.705 123.3 336.435 ; + RECT 123.595 335.705 123.795 336.435 ; + RECT 124.095 335.705 124.295 336.435 ; + RECT 124.25 0.52 124.51 2.335 ; + RECT 124.595 335.705 124.795 336.435 ; + RECT 124.76 0.52 125.02 14.11 ; + RECT 125.09 335.705 125.29 336.435 ; + RECT 126.135 0.17 126.905 0.94 ; + RECT 126.645 0.17 126.905 8.7 ; + RECT 126.135 0.17 126.395 12.9 ; + RECT 125.625 0.52 125.885 2.485 ; + RECT 125.91 335.705 126.11 336.435 ; + RECT 127.155 0.17 127.925 0.43 ; + RECT 127.665 0.17 127.925 10.48 ; + RECT 127.155 0.17 127.415 10.99 ; + RECT 126.405 335.705 126.605 336.435 ; + RECT 126.905 335.705 127.105 336.435 ; + RECT 127.405 335.705 127.605 336.435 ; + RECT 127.9 335.705 128.1 336.435 ; + RECT 129.195 0.17 129.965 0.43 ; + RECT 129.195 0.17 129.455 11.5 ; + RECT 129.705 0.17 129.965 11.5 ; + RECT 128.72 335.705 128.92 336.435 ; + RECT 129.215 335.705 129.415 336.435 ; + RECT 130.215 0.17 130.985 0.94 ; + RECT 130.215 0.17 130.475 12.9 ; + RECT 130.725 0.17 130.985 12.9 ; + RECT 129.715 335.705 129.915 336.435 ; + RECT 130.215 335.705 130.415 336.435 ; + RECT 130.71 335.705 130.91 336.435 ; + RECT 131.235 0.52 131.495 5.815 ; + RECT 132.09 0.52 132.35 5.16 ; + RECT 132.09 4.9 132.87 5.16 ; + RECT 132.61 4.9 132.87 6.64 ; + RECT 131.53 335.705 131.73 336.435 ; + RECT 132.025 335.705 132.225 336.435 ; + RECT 132.525 335.705 132.725 336.435 ; + RECT 133.025 335.705 133.225 336.435 ; + RECT 133.52 335.705 133.72 336.435 ; + RECT 134.34 335.705 134.54 336.435 ; + RECT 134.835 335.705 135.035 336.435 ; + RECT 135.335 335.705 135.535 336.435 ; + RECT 135.49 0.52 135.75 2.335 ; + RECT 135.835 335.705 136.035 336.435 ; + RECT 136 0.52 136.26 14.11 ; + RECT 136.33 335.705 136.53 336.435 ; + RECT 137.375 0.17 138.145 0.94 ; + RECT 137.885 0.17 138.145 8.7 ; + RECT 137.375 0.17 137.635 12.9 ; + RECT 136.865 0.52 137.125 2.485 ; + RECT 137.15 335.705 137.35 336.435 ; + RECT 138.395 0.17 139.165 0.43 ; + RECT 138.905 0.17 139.165 10.48 ; + RECT 138.395 0.17 138.655 10.99 ; + RECT 137.645 335.705 137.845 336.435 ; + RECT 138.145 335.705 138.345 336.435 ; + RECT 138.645 335.705 138.845 336.435 ; + RECT 139.14 335.705 139.34 336.435 ; + RECT 140.435 0.17 141.205 0.43 ; + RECT 140.435 0.17 140.695 11.5 ; + RECT 140.945 0.17 141.205 11.5 ; + RECT 139.96 335.705 140.16 336.435 ; + RECT 140.455 335.705 140.655 336.435 ; + RECT 141.455 0.17 142.225 0.94 ; + RECT 141.455 0.17 141.715 12.9 ; + RECT 141.965 0.17 142.225 12.9 ; + RECT 140.955 335.705 141.155 336.435 ; + RECT 141.455 335.705 141.655 336.435 ; + RECT 141.95 335.705 142.15 336.435 ; + RECT 142.475 0.52 142.735 5.815 ; + RECT 143.33 0.52 143.59 5.16 ; + RECT 143.33 4.9 144.11 5.16 ; + RECT 143.85 4.9 144.11 6.64 ; + RECT 142.77 335.705 142.97 336.435 ; + RECT 143.265 335.705 143.465 336.435 ; + RECT 143.765 335.705 143.965 336.435 ; + RECT 144.265 335.705 144.465 336.435 ; + RECT 144.76 335.705 144.96 336.435 ; + RECT 145.58 335.705 145.78 336.435 ; + RECT 146.575 45.465 146.775 336.435 ; + LAYER Metal2 SPACING 0.21 ; + RECT 27.135 0.17 31.985 336.46 ; + RECT 34.13 0 36.75 336.46 ; + RECT 38.375 0.17 43.225 336.46 ; + RECT 45.37 0 57.15 336.46 ; + RECT 59.44 0.17 65.82 336.46 ; + RECT 67.09 0.3 67.35 336.46 ; + RECT 68.62 0.3 68.88 336.46 ; + RECT 71.68 0.3 71.94 336.46 ; + RECT 73.21 0.3 73.47 336.46 ; + RECT 74.75 0.17 76.02 336.46 ; + RECT 74.74 0.3 76.02 336.46 ; + RECT 80.35 0.17 82.14 336.46 ; + RECT 83.41 0.3 87.24 336.46 ; + RECT 88.51 0.3 89.28 336.46 ; + RECT 90.05 0 101.51 336.46 ; + RECT 90.04 0.17 101.51 336.46 ; + RECT 103.655 0.17 108.505 336.46 ; + RECT 110.13 0 112.75 336.46 ; + RECT 114.895 0.17 119.745 336.46 ; + RECT 121.37 0 123.99 336.46 ; + RECT 126.135 0.17 130.985 336.46 ; + RECT 132.61 0 135.23 336.46 ; + RECT 137.375 0.17 142.225 336.46 ; + RECT 143.85 0 146.88 336.46 ; + RECT 0 0.52 146.88 336.46 ; + RECT 4.665 0 9.495 336.46 ; + RECT 15.905 0 20.735 336.46 ; + RECT 27.145 0 31.975 336.46 ; + RECT 38.385 0 43.215 336.46 ; + RECT 59.44 0 65.81 336.46 ; + RECT 74.75 0 76.01 336.46 ; + RECT 80.35 0 82.13 336.46 ; + RECT 103.665 0 108.495 336.46 ; + RECT 114.905 0 119.735 336.46 ; + RECT 126.145 0 130.975 336.46 ; + RECT 137.385 0 142.215 336.46 ; + RECT 67.1 0 67.34 336.46 ; + RECT 68.63 0 68.87 336.46 ; + RECT 71.69 0 71.93 336.46 ; + RECT 73.22 0 73.46 336.46 ; + RECT 83.42 0 87.23 336.46 ; + RECT 88.52 0 89.27 336.46 ; + RECT 0 0 3.03 336.46 ; + RECT 4.655 0.17 9.505 336.46 ; + RECT 11.65 0 14.27 336.46 ; + RECT 15.895 0.17 20.745 336.46 ; + RECT 22.89 0 25.51 336.46 ; + LAYER Metal3 ; + RECT 0 0 146.88 336.46 ; + LAYER Metal4 SPACING 0.21 ; + RECT 0 39.085 9.62 45.205 ; + RECT 0 0 4 336.46 ; + RECT 7.33 0 9.62 336.46 ; + RECT 12.95 39.085 20.86 45.205 ; + RECT 12.95 0 15.24 336.46 ; + RECT 18.57 0 20.86 336.46 ; + RECT 24.19 39.085 32.1 45.205 ; + RECT 24.19 0 26.48 336.46 ; + RECT 29.81 0 32.1 336.46 ; + RECT 35.43 39.085 43.34 45.205 ; + RECT 35.43 0 37.72 336.46 ; + RECT 41.05 0 43.34 336.46 ; + RECT 46.67 0 53.75 336.46 ; + RECT 57.08 0 58.9 336.46 ; + RECT 62.23 0 64.05 336.46 ; + RECT 67.38 0 69.2 336.46 ; + RECT 72.53 0 74.35 336.46 ; + RECT 77.68 0 79.5 336.46 ; + RECT 103.54 39.085 111.45 45.205 ; + RECT 103.54 0 105.83 336.46 ; + RECT 109.16 0 111.45 336.46 ; + RECT 114.78 39.085 122.69 45.205 ; + RECT 114.78 0 117.07 336.46 ; + RECT 120.4 0 122.69 336.46 ; + RECT 126.02 39.085 133.93 45.205 ; + RECT 126.02 0 128.31 336.46 ; + RECT 131.64 0 133.93 336.46 ; + RECT 137.26 39.085 146.88 45.205 ; + RECT 137.26 0 139.55 336.46 ; + RECT 142.88 0 146.88 336.46 ; + RECT 82.83 0 84.65 336.46 ; + RECT 87.98 0 89.8 336.46 ; + RECT 93.13 0 100.21 336.46 ; + END +END RM_IHPSG13_1P_1024x8_c2_bm_bist + +END LIBRARY diff --git a/flow/platforms/ihp-sg13g2/lef/RM_IHPSG13_1P_4096x16_c3_bm_bist.lef b/flow/platforms/ihp-sg13g2/lef/RM_IHPSG13_1P_4096x16_c3_bm_bist.lef new file mode 100644 index 0000000000..16c930a46d --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lef/RM_IHPSG13_1P_4096x16_c3_bm_bist.lef @@ -0,0 +1,2934 @@ +# ------------------------------------------------------ +# +# Copyright 2024 IHP PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# Generated on Fri Jul 12 17:37:54 2024 +# +# ------------------------------------------------------ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +DIVIDERCHAR "/" ; + +MACRO RM_IHPSG13_1P_4096x16_c3_bm_bist + CLASS BLOCK ; + ORIGIN 0 0 ; + FOREIGN RM_IHPSG13_1P_4096x16_c3_bm_bist 0 0 ; + SIZE 416.64 BY 618.3 ; + SYMMETRY X Y R90 ; + PIN A_DIN[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 245.01 0 245.27 0.26 ; + END + END A_DIN[8] + PIN A_DIN[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 171.37 0 171.63 0.26 ; + END + END A_DIN[7] + PIN A_BIST_DIN[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 243.48 0 243.74 0.26 ; + END + END A_BIST_DIN[8] + PIN A_BIST_DIN[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 172.9 0 173.16 0.26 ; + END + END A_BIST_DIN[7] + PIN A_BM[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 248.89 0 249.15 0.26 ; + END + END A_BM[8] + PIN A_BM[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 167.49 0 167.75 0.26 ; + END + END A_BM[7] + PIN A_BIST_BM[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 250.42 0 250.68 0.26 ; + END + END A_BIST_BM[8] + PIN A_BIST_BM[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 165.96 0 166.22 0.26 ; + END + END A_BIST_BM[7] + PIN A_DOUT[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.0345 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 249.755 0 250.015 0.26 ; + END + END A_DOUT[8] + PIN A_DOUT[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.0345 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 166.625 0 166.885 0.26 ; + END + END A_DOUT[7] + PIN VSS! + DIRECTION INOUT ; + USE GROUND ; + NETEXPR "vss VSS!" ; + PORT + LAYER Metal4 ; + RECT 403.95 0 406.76 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 392.71 0 395.52 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 381.47 0 384.28 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 370.23 0 373.04 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 358.99 0 361.8 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 347.75 0 350.56 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 336.51 0 339.32 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 325.27 0 328.08 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 314.03 0 316.84 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 302.79 0 305.6 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 291.55 0 294.36 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 280.31 0 283.12 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 269.07 0 271.88 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 257.83 0 260.64 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 246.59 0 249.4 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 235.35 0 238.16 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 224.94 0 227.75 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 214.64 0 217.45 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 199.19 0 202 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 188.89 0 191.7 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 178.48 0 181.29 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 167.24 0 170.05 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 156 0 158.81 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 144.76 0 147.57 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 133.52 0 136.33 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 122.28 0 125.09 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 111.04 0 113.85 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 99.8 0 102.61 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 88.56 0 91.37 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 77.32 0 80.13 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 66.08 0 68.89 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 54.84 0 57.65 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 43.6 0 46.41 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 32.36 0 35.17 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 21.12 0 23.93 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 9.88 0 12.69 618.3 ; + END + END VSS! + PIN VDD! + DIRECTION INOUT ; + USE POWER ; + NETEXPR "vdd VDD!" ; + PORT + LAYER Metal4 ; + RECT 409.57 0 412.38 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 398.33 0 401.14 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 387.09 0 389.9 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 375.85 0 378.66 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 364.61 0 367.42 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 353.37 0 356.18 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 342.13 0 344.94 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 330.89 0 333.7 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 319.65 0 322.46 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 308.41 0 311.22 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 297.17 0 299.98 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 285.93 0 288.74 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 274.69 0 277.5 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 263.45 0 266.26 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 252.21 0 255.02 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 240.97 0 243.78 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 219.79 0 222.6 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 209.49 0 212.3 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 204.34 0 207.15 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 194.04 0 196.85 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 172.86 0 175.67 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 161.62 0 164.43 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 150.38 0 153.19 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 139.14 0 141.95 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 127.9 0 130.71 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 116.66 0 119.47 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 105.42 0 108.23 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 94.18 0 96.99 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 82.94 0 85.75 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 71.7 0 74.51 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 60.46 0 63.27 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 49.22 0 52.03 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 37.98 0 40.79 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 26.74 0 29.55 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 15.5 0 18.31 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 4.26 0 7.07 30.425 ; + END + END VDD! + PIN VDDARRAY! + DIRECTION INOUT ; + USE POWER ; + NETEXPR "vddarray VDDARRAY!" ; + PORT + LAYER Metal4 ; + RECT 409.57 37.065 412.38 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 398.33 37.065 401.14 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 387.09 37.065 389.9 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 375.85 37.065 378.66 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 364.61 37.065 367.42 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 353.37 37.065 356.18 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 342.13 37.065 344.94 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 330.89 37.065 333.7 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 319.65 37.065 322.46 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 308.41 37.065 311.22 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 297.17 37.065 299.98 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 285.93 37.065 288.74 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 274.69 37.065 277.5 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 263.45 37.065 266.26 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 252.21 37.065 255.02 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 240.97 37.065 243.78 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 172.86 37.065 175.67 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 161.62 37.065 164.43 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 150.38 37.065 153.19 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 139.14 37.065 141.95 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 127.9 37.065 130.71 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 116.66 37.065 119.47 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 105.42 37.065 108.23 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 94.18 37.065 96.99 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 82.94 37.065 85.75 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 71.7 37.065 74.51 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 60.46 37.065 63.27 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 49.22 37.065 52.03 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 37.98 37.065 40.79 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 26.74 37.065 29.55 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 15.5 37.065 18.31 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 4.26 37.065 7.07 618.3 ; + END + END VDDARRAY! + PIN A_DIN[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 267.49 0 267.75 0.26 ; + END + END A_DIN[9] + PIN A_DIN[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 148.89 0 149.15 0.26 ; + END + END A_DIN[6] + PIN A_BIST_DIN[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 265.96 0 266.22 0.26 ; + END + END A_BIST_DIN[9] + PIN A_BIST_DIN[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 150.42 0 150.68 0.26 ; + END + END A_BIST_DIN[6] + PIN A_BM[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 271.37 0 271.63 0.26 ; + END + END A_BM[9] + PIN A_BM[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 145.01 0 145.27 0.26 ; + END + END A_BM[6] + PIN A_BIST_BM[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 272.9 0 273.16 0.26 ; + END + END A_BIST_BM[9] + PIN A_BIST_BM[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 143.48 0 143.74 0.26 ; + END + END A_BIST_BM[6] + PIN A_DOUT[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.0345 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 272.235 0 272.495 0.26 ; + END + END A_DOUT[9] + PIN A_DOUT[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.0345 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 144.145 0 144.405 0.26 ; + END + END A_DOUT[6] + PIN A_DIN[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 289.97 0 290.23 0.26 ; + END + END A_DIN[10] + PIN A_DIN[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 126.41 0 126.67 0.26 ; + END + END A_DIN[5] + PIN A_BIST_DIN[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 288.44 0 288.7 0.26 ; + END + END A_BIST_DIN[10] + PIN A_BIST_DIN[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 127.94 0 128.2 0.26 ; + END + END A_BIST_DIN[5] + PIN A_BM[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 293.85 0 294.11 0.26 ; + END + END A_BM[10] + PIN A_BM[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 122.53 0 122.79 0.26 ; + END + END A_BM[5] + PIN A_BIST_BM[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 295.38 0 295.64 0.26 ; + END + END A_BIST_BM[10] + PIN A_BIST_BM[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 121 0 121.26 0.26 ; + END + END A_BIST_BM[5] + PIN A_DOUT[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.0345 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 294.715 0 294.975 0.26 ; + END + END A_DOUT[10] + PIN A_DOUT[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.0345 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 121.665 0 121.925 0.26 ; + END + END A_DOUT[5] + PIN A_DIN[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 312.45 0 312.71 0.26 ; + END + END A_DIN[11] + PIN A_DIN[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 103.93 0 104.19 0.26 ; + END + END A_DIN[4] + PIN A_BIST_DIN[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 310.92 0 311.18 0.26 ; + END + END A_BIST_DIN[11] + PIN A_BIST_DIN[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 105.46 0 105.72 0.26 ; + END + END A_BIST_DIN[4] + PIN A_BM[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 316.33 0 316.59 0.26 ; + END + END A_BM[11] + PIN A_BM[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 100.05 0 100.31 0.26 ; + END + END A_BM[4] + PIN A_BIST_BM[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 317.86 0 318.12 0.26 ; + END + END A_BIST_BM[11] + PIN A_BIST_BM[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 98.52 0 98.78 0.26 ; + END + END A_BIST_BM[4] + PIN A_DOUT[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.0345 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 317.195 0 317.455 0.26 ; + END + END A_DOUT[11] + PIN A_DOUT[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.0345 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 99.185 0 99.445 0.26 ; + END + END A_DOUT[4] + PIN A_DIN[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 334.93 0 335.19 0.26 ; + END + END A_DIN[12] + PIN A_DIN[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 81.45 0 81.71 0.26 ; + END + END A_DIN[3] + PIN A_BIST_DIN[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 333.4 0 333.66 0.26 ; + END + END A_BIST_DIN[12] + PIN A_BIST_DIN[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 82.98 0 83.24 0.26 ; + END + END A_BIST_DIN[3] + PIN A_BM[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 338.81 0 339.07 0.26 ; + END + END A_BM[12] + PIN A_BM[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 77.57 0 77.83 0.26 ; + END + END A_BM[3] + PIN A_BIST_BM[12] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 340.34 0 340.6 0.26 ; + END + END A_BIST_BM[12] + PIN A_BIST_BM[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 76.04 0 76.3 0.26 ; + END + END A_BIST_BM[3] + PIN A_DOUT[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.0345 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 339.675 0 339.935 0.26 ; + END + END A_DOUT[12] + PIN A_DOUT[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.0345 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 76.705 0 76.965 0.26 ; + END + END A_DOUT[3] + PIN A_DIN[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 357.41 0 357.67 0.26 ; + END + END A_DIN[13] + PIN A_DIN[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 58.97 0 59.23 0.26 ; + END + END A_DIN[2] + PIN A_BIST_DIN[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 355.88 0 356.14 0.26 ; + END + END A_BIST_DIN[13] + PIN A_BIST_DIN[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 60.5 0 60.76 0.26 ; + END + END A_BIST_DIN[2] + PIN A_BM[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 361.29 0 361.55 0.26 ; + END + END A_BM[13] + PIN A_BM[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 55.09 0 55.35 0.26 ; + END + END A_BM[2] + PIN A_BIST_BM[13] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 362.82 0 363.08 0.26 ; + END + END A_BIST_BM[13] + PIN A_BIST_BM[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 53.56 0 53.82 0.26 ; + END + END A_BIST_BM[2] + PIN A_DOUT[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.0345 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 362.155 0 362.415 0.26 ; + END + END A_DOUT[13] + PIN A_DOUT[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.0345 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 54.225 0 54.485 0.26 ; + END + END A_DOUT[2] + PIN A_DIN[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 379.89 0 380.15 0.26 ; + END + END A_DIN[14] + PIN A_DIN[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 36.49 0 36.75 0.26 ; + END + END A_DIN[1] + PIN A_BIST_DIN[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 378.36 0 378.62 0.26 ; + END + END A_BIST_DIN[14] + PIN A_BIST_DIN[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 38.02 0 38.28 0.26 ; + END + END A_BIST_DIN[1] + PIN A_BM[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 383.77 0 384.03 0.26 ; + END + END A_BM[14] + PIN A_BM[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 32.61 0 32.87 0.26 ; + END + END A_BM[1] + PIN A_BIST_BM[14] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 385.3 0 385.56 0.26 ; + END + END A_BIST_BM[14] + PIN A_BIST_BM[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 31.08 0 31.34 0.26 ; + END + END A_BIST_BM[1] + PIN A_DOUT[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.0345 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 384.635 0 384.895 0.26 ; + END + END A_DOUT[14] + PIN A_DOUT[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.0345 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 31.745 0 32.005 0.26 ; + END + END A_DOUT[1] + PIN A_DIN[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 402.37 0 402.63 0.26 ; + END + END A_DIN[15] + PIN A_DIN[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 14.01 0 14.27 0.26 ; + END + END A_DIN[0] + PIN A_BIST_DIN[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 400.84 0 401.1 0.26 ; + END + END A_BIST_DIN[15] + PIN A_BIST_DIN[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 15.54 0 15.8 0.26 ; + END + END A_BIST_DIN[0] + PIN A_BM[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 406.25 0 406.51 0.26 ; + END + END A_BM[15] + PIN A_BM[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 10.13 0 10.39 0.26 ; + END + END A_BM[0] + PIN A_BIST_BM[15] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 407.78 0 408.04 0.26 ; + END + END A_BIST_BM[15] + PIN A_BIST_BM[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 8.6 0 8.86 0.26 ; + END + END A_BIST_BM[0] + PIN A_DOUT[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.0345 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 407.115 0 407.375 0.26 ; + END + END A_DOUT[15] + PIN A_DOUT[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.0345 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 9.265 0 9.525 0.26 ; + END + END A_DOUT[0] + PIN A_ADDR[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 6.7171 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 34.349515 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 204.52 0 204.78 0.26 ; + END + END A_ADDR[0] + PIN A_BIST_ADDR[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 7.5127 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 38.31068 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 209.11 0 209.37 0.26 ; + END + END A_BIST_ADDR[0] + PIN A_ADDR[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 5.59 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 28.783172 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 204.01 0 204.27 0.26 ; + END + END A_ADDR[1] + PIN A_BIST_ADDR[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 6.3856 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 32.744337 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 208.6 0 208.86 0.26 ; + END + END A_BIST_ADDR[1] + PIN A_ADDR[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 6.4519 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 33.029126 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 189.73 0 189.99 0.26 ; + END + END A_ADDR[2] + PIN A_BIST_ADDR[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 6.1867 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 31.708738 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 191.26 0 191.52 0.26 ; + END + END A_BIST_ADDR[2] + PIN A_ADDR[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 8.4487 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.5246 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 9.415982 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 212.17 0 212.43 0.26 ; + END + END A_ADDR[3] + PIN A_BIST_ADDR[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 8.4487 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.0962 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 7.813791 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 212.68 0 212.94 0.26 ; + END + END A_BIST_ADDR[3] + PIN A_ADDR[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 8.4487 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 3.8367 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 20.927558 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 211.15 0 211.41 0.26 ; + END + END A_ADDR[4] + PIN A_BIST_ADDR[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 8.4487 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 3.5175 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 19.869057 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 211.66 0 211.92 0.26 ; + END + END A_BIST_ADDR[4] + PIN A_ADDR[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 10.0139 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 50.763754 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 214.72 0 214.98 0.26 ; + END + END A_ADDR[5] + PIN A_BIST_ADDR[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 9.7487 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 49.443366 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 214.21 0 214.47 0.26 ; + END + END A_BIST_ADDR[5] + PIN A_ADDR[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 11.7429 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 59.372168 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 213.7 0 213.96 0.26 ; + END + END A_ADDR[6] + PIN A_BIST_ADDR[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 11.4777 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 58.05178 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 213.19 0 213.45 0.26 ; + END + END A_BIST_ADDR[6] + PIN A_ADDR[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 8.7685 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 44.563107 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 192.28 0 192.54 0.26 ; + END + END A_ADDR[7] + PIN A_BIST_ADDR[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 8.4931 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 43.191934 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 192.79 0 193.05 0.26 ; + END + END A_BIST_ADDR[7] + PIN A_ADDR[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 10.2323 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 51.851133 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 193.3 0 193.56 0.26 ; + END + END A_ADDR[8] + PIN A_BIST_ADDR[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 9.9671 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 50.530744 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 193.81 0 194.07 0.26 ; + END + END A_BIST_ADDR[8] + PIN A_ADDR[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 7.9183 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.5897 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 9.740105 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 222.37 0 222.63 0.26 ; + END + END A_ADDR[9] + PIN A_BIST_ADDR[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 7.9183 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.3755 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 9.204381 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 222.88 0 223.14 0.26 ; + END + END A_BIST_ADDR[9] + PIN A_ADDR[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 10.6097 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 53.730147 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 217.27 0 217.53 0.26 ; + END + END A_ADDR[10] + PIN A_BIST_ADDR[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 10.3547 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 52.460543 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 217.78 0 218.04 0.26 ; + END + END A_BIST_ADDR[10] + PIN A_ADDR[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 8.6359 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 43.902913 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 215.23 0 215.49 0.26 ; + END + END A_ADDR[11] + PIN A_BIST_ADDR[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 8.6359 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 43.902913 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 215.74 0 216 0.26 ; + END + END A_BIST_ADDR[11] + PIN A_CLK + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.8707 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 10.220065 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 202.48 0 202.74 0.26 ; + END + END A_CLK + PIN A_REN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.81105 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.923077 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 206.05 0 206.31 0.26 ; + END + END A_REN + PIN A_WEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 205.54 0 205.8 0.26 ; + END + END A_WEN + PIN A_MEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.8407 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.09186 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 202.99 0 203.25 0.26 ; + END + END A_MEN + PIN A_DLY + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.874 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.3367 LAYER Metal2 ; + ANTENNAMAXAREACAR 12.046332 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 224.41 0 224.67 0.26 ; + END + END A_DLY + PIN A_BIST_EN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.8031 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 119.45135 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 1.43 LAYER Metal2 ; + ANTENNAGATEAREA 17.16 LAYER Metal3 ; + ANTENNAMAXAREACAR 1.686364 LAYER Metal2 ; + ANTENNAMAXAREACAR 13.900125 LAYER Metal3 ; + ANTENNAMAXCUTCAR 0.151469 LAYER Via2 ; + PORT + LAYER Metal2 ; + RECT 205.03 0 205.29 0.26 ; + END + END A_BIST_EN + PIN A_BIST_CLK + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.9799 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 11.079661 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 200.95 0 201.21 0.26 ; + END + END A_BIST_CLK + PIN A_BIST_REN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.9279 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 10.820762 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 207.58 0 207.84 0.26 ; + END + END A_BIST_REN + PIN A_BIST_WEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7211 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.812298 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 207.07 0 207.33 0.26 ; + END + END A_BIST_WEN + PIN A_BIST_MEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7137 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.775454 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 201.46 0 201.72 0.26 ; + END + END A_BIST_MEN + OBS + LAYER Metal1 ; + RECT 0 0 416.64 618.3 ; + LAYER Metal2 ; + RECT 0.105 37.065 0.305 618.275 ; + RECT 1.1 617.545 1.3 618.275 ; + RECT 1.92 617.545 2.12 618.275 ; + RECT 2.415 617.545 2.615 618.275 ; + RECT 2.915 617.545 3.115 618.275 ; + RECT 3.415 617.545 3.615 618.275 ; + RECT 3.91 617.545 4.11 618.275 ; + RECT 4.73 617.545 4.93 618.275 ; + RECT 5.225 617.545 5.425 618.275 ; + RECT 5.725 617.545 5.925 618.275 ; + RECT 7.225 0.17 7.995 0.43 ; + RECT 7.225 0.17 7.485 11.38 ; + RECT 7.735 0.17 7.995 17.1 ; + RECT 6.225 617.545 6.425 618.275 ; + RECT 6.72 617.545 6.92 618.275 ; + RECT 7.54 617.545 7.74 618.275 ; + RECT 8.035 617.545 8.235 618.275 ; + RECT 8.535 617.545 8.735 618.275 ; + RECT 8.6 0.52 8.86 2.255 ; + RECT 9.035 617.545 9.235 618.275 ; + RECT 9.265 0.52 9.525 8.085 ; + RECT 9.53 617.545 9.73 618.275 ; + RECT 10.13 0.52 10.39 1.5 ; + RECT 10.35 617.545 10.55 618.275 ; + RECT 10.845 617.545 11.045 618.275 ; + RECT 11.345 617.545 11.545 618.275 ; + RECT 11.845 617.545 12.045 618.275 ; + RECT 12.34 617.545 12.54 618.275 ; + RECT 13.16 617.545 13.36 618.275 ; + RECT 13.655 617.545 13.855 618.275 ; + RECT 14.01 0.52 14.27 2.255 ; + RECT 14.155 617.545 14.355 618.275 ; + RECT 14.655 617.545 14.855 618.275 ; + RECT 15.15 617.545 15.35 618.275 ; + RECT 16.255 0.8 17.025 1.57 ; + RECT 16.255 0.3 16.515 13.03 ; + RECT 16.765 0.3 17.025 13.03 ; + RECT 15.54 0.52 15.8 2.255 ; + RECT 15.97 617.545 16.17 618.275 ; + RECT 16.465 617.545 16.665 618.275 ; + RECT 16.965 617.545 17.165 618.275 ; + RECT 17.465 617.545 17.665 618.275 ; + RECT 17.96 617.545 18.16 618.275 ; + RECT 18.78 617.545 18.98 618.275 ; + RECT 19.975 0.17 20.745 0.43 ; + RECT 19.975 0.17 20.235 13.055 ; + RECT 20.485 0.17 20.745 13.055 ; + RECT 19.275 617.545 19.475 618.275 ; + RECT 19.775 617.545 19.975 618.275 ; + RECT 20.275 617.545 20.475 618.275 ; + RECT 20.77 617.545 20.97 618.275 ; + RECT 21.59 617.545 21.79 618.275 ; + RECT 22.085 617.545 22.285 618.275 ; + RECT 22.585 617.545 22.785 618.275 ; + RECT 23.085 617.545 23.285 618.275 ; + RECT 23.58 617.545 23.78 618.275 ; + RECT 24.4 617.545 24.6 618.275 ; + RECT 24.895 617.545 25.095 618.275 ; + RECT 25.395 617.545 25.595 618.275 ; + RECT 25.895 617.545 26.095 618.275 ; + RECT 26.39 617.545 26.59 618.275 ; + RECT 27.21 617.545 27.41 618.275 ; + RECT 27.705 617.545 27.905 618.275 ; + RECT 28.205 617.545 28.405 618.275 ; + RECT 29.705 0.17 30.475 0.43 ; + RECT 29.705 0.17 29.965 11.38 ; + RECT 30.215 0.17 30.475 17.1 ; + RECT 28.705 617.545 28.905 618.275 ; + RECT 29.2 617.545 29.4 618.275 ; + RECT 30.02 617.545 30.22 618.275 ; + RECT 30.515 617.545 30.715 618.275 ; + RECT 31.015 617.545 31.215 618.275 ; + RECT 31.08 0.52 31.34 2.255 ; + RECT 31.515 617.545 31.715 618.275 ; + RECT 31.745 0.52 32.005 8.085 ; + RECT 32.01 617.545 32.21 618.275 ; + RECT 32.61 0.52 32.87 1.5 ; + RECT 32.83 617.545 33.03 618.275 ; + RECT 33.325 617.545 33.525 618.275 ; + RECT 33.825 617.545 34.025 618.275 ; + RECT 34.325 617.545 34.525 618.275 ; + RECT 34.82 617.545 35.02 618.275 ; + RECT 35.64 617.545 35.84 618.275 ; + RECT 36.135 617.545 36.335 618.275 ; + RECT 36.49 0.52 36.75 2.255 ; + RECT 36.635 617.545 36.835 618.275 ; + RECT 37.135 617.545 37.335 618.275 ; + RECT 37.63 617.545 37.83 618.275 ; + RECT 38.735 0.8 39.505 1.57 ; + RECT 38.735 0.3 38.995 13.03 ; + RECT 39.245 0.3 39.505 13.03 ; + RECT 38.02 0.52 38.28 2.255 ; + RECT 38.45 617.545 38.65 618.275 ; + RECT 38.945 617.545 39.145 618.275 ; + RECT 39.445 617.545 39.645 618.275 ; + RECT 39.945 617.545 40.145 618.275 ; + RECT 40.44 617.545 40.64 618.275 ; + RECT 41.26 617.545 41.46 618.275 ; + RECT 42.455 0.17 43.225 0.43 ; + RECT 42.455 0.17 42.715 13.055 ; + RECT 42.965 0.17 43.225 13.055 ; + RECT 41.755 617.545 41.955 618.275 ; + RECT 42.255 617.545 42.455 618.275 ; + RECT 42.755 617.545 42.955 618.275 ; + RECT 43.25 617.545 43.45 618.275 ; + RECT 44.07 617.545 44.27 618.275 ; + RECT 44.565 617.545 44.765 618.275 ; + RECT 45.065 617.545 45.265 618.275 ; + RECT 45.565 617.545 45.765 618.275 ; + RECT 46.06 617.545 46.26 618.275 ; + RECT 46.88 617.545 47.08 618.275 ; + RECT 47.375 617.545 47.575 618.275 ; + RECT 47.875 617.545 48.075 618.275 ; + RECT 48.375 617.545 48.575 618.275 ; + RECT 48.87 617.545 49.07 618.275 ; + RECT 49.69 617.545 49.89 618.275 ; + RECT 50.185 617.545 50.385 618.275 ; + RECT 50.685 617.545 50.885 618.275 ; + RECT 52.185 0.17 52.955 0.43 ; + RECT 52.185 0.17 52.445 11.38 ; + RECT 52.695 0.17 52.955 17.1 ; + RECT 51.185 617.545 51.385 618.275 ; + RECT 51.68 617.545 51.88 618.275 ; + RECT 52.5 617.545 52.7 618.275 ; + RECT 52.995 617.545 53.195 618.275 ; + RECT 53.495 617.545 53.695 618.275 ; + RECT 53.56 0.52 53.82 2.255 ; + RECT 53.995 617.545 54.195 618.275 ; + RECT 54.225 0.52 54.485 8.085 ; + RECT 54.49 617.545 54.69 618.275 ; + RECT 55.09 0.52 55.35 1.5 ; + RECT 55.31 617.545 55.51 618.275 ; + RECT 55.805 617.545 56.005 618.275 ; + RECT 56.305 617.545 56.505 618.275 ; + RECT 56.805 617.545 57.005 618.275 ; + RECT 57.3 617.545 57.5 618.275 ; + RECT 58.12 617.545 58.32 618.275 ; + RECT 58.615 617.545 58.815 618.275 ; + RECT 58.97 0.52 59.23 2.255 ; + RECT 59.115 617.545 59.315 618.275 ; + RECT 59.615 617.545 59.815 618.275 ; + RECT 60.11 617.545 60.31 618.275 ; + RECT 61.215 0.8 61.985 1.57 ; + RECT 61.215 0.3 61.475 13.03 ; + RECT 61.725 0.3 61.985 13.03 ; + RECT 60.5 0.52 60.76 2.255 ; + RECT 60.93 617.545 61.13 618.275 ; + RECT 61.425 617.545 61.625 618.275 ; + RECT 61.925 617.545 62.125 618.275 ; + RECT 62.425 617.545 62.625 618.275 ; + RECT 62.92 617.545 63.12 618.275 ; + RECT 63.74 617.545 63.94 618.275 ; + RECT 64.935 0.17 65.705 0.43 ; + RECT 64.935 0.17 65.195 13.055 ; + RECT 65.445 0.17 65.705 13.055 ; + RECT 64.235 617.545 64.435 618.275 ; + RECT 64.735 617.545 64.935 618.275 ; + RECT 65.235 617.545 65.435 618.275 ; + RECT 65.73 617.545 65.93 618.275 ; + RECT 66.55 617.545 66.75 618.275 ; + RECT 67.045 617.545 67.245 618.275 ; + RECT 67.545 617.545 67.745 618.275 ; + RECT 68.045 617.545 68.245 618.275 ; + RECT 68.54 617.545 68.74 618.275 ; + RECT 69.36 617.545 69.56 618.275 ; + RECT 69.855 617.545 70.055 618.275 ; + RECT 70.355 617.545 70.555 618.275 ; + RECT 70.855 617.545 71.055 618.275 ; + RECT 71.35 617.545 71.55 618.275 ; + RECT 72.17 617.545 72.37 618.275 ; + RECT 72.665 617.545 72.865 618.275 ; + RECT 73.165 617.545 73.365 618.275 ; + RECT 74.665 0.17 75.435 0.43 ; + RECT 74.665 0.17 74.925 11.38 ; + RECT 75.175 0.17 75.435 17.1 ; + RECT 73.665 617.545 73.865 618.275 ; + RECT 74.16 617.545 74.36 618.275 ; + RECT 74.98 617.545 75.18 618.275 ; + RECT 75.475 617.545 75.675 618.275 ; + RECT 75.975 617.545 76.175 618.275 ; + RECT 76.04 0.52 76.3 2.255 ; + RECT 76.475 617.545 76.675 618.275 ; + RECT 76.705 0.52 76.965 8.085 ; + RECT 76.97 617.545 77.17 618.275 ; + RECT 77.57 0.52 77.83 1.5 ; + RECT 77.79 617.545 77.99 618.275 ; + RECT 78.285 617.545 78.485 618.275 ; + RECT 78.785 617.545 78.985 618.275 ; + RECT 79.285 617.545 79.485 618.275 ; + RECT 79.78 617.545 79.98 618.275 ; + RECT 80.6 617.545 80.8 618.275 ; + RECT 81.095 617.545 81.295 618.275 ; + RECT 81.45 0.52 81.71 2.255 ; + RECT 81.595 617.545 81.795 618.275 ; + RECT 82.095 617.545 82.295 618.275 ; + RECT 82.59 617.545 82.79 618.275 ; + RECT 83.695 0.8 84.465 1.57 ; + RECT 83.695 0.3 83.955 13.03 ; + RECT 84.205 0.3 84.465 13.03 ; + RECT 82.98 0.52 83.24 2.255 ; + RECT 83.41 617.545 83.61 618.275 ; + RECT 83.905 617.545 84.105 618.275 ; + RECT 84.405 617.545 84.605 618.275 ; + RECT 84.905 617.545 85.105 618.275 ; + RECT 85.4 617.545 85.6 618.275 ; + RECT 86.22 617.545 86.42 618.275 ; + RECT 87.415 0.17 88.185 0.43 ; + RECT 87.415 0.17 87.675 13.055 ; + RECT 87.925 0.17 88.185 13.055 ; + RECT 86.715 617.545 86.915 618.275 ; + RECT 87.215 617.545 87.415 618.275 ; + RECT 87.715 617.545 87.915 618.275 ; + RECT 88.21 617.545 88.41 618.275 ; + RECT 89.03 617.545 89.23 618.275 ; + RECT 89.525 617.545 89.725 618.275 ; + RECT 90.025 617.545 90.225 618.275 ; + RECT 90.525 617.545 90.725 618.275 ; + RECT 91.02 617.545 91.22 618.275 ; + RECT 91.84 617.545 92.04 618.275 ; + RECT 92.335 617.545 92.535 618.275 ; + RECT 92.835 617.545 93.035 618.275 ; + RECT 93.335 617.545 93.535 618.275 ; + RECT 93.83 617.545 94.03 618.275 ; + RECT 94.65 617.545 94.85 618.275 ; + RECT 95.145 617.545 95.345 618.275 ; + RECT 95.645 617.545 95.845 618.275 ; + RECT 97.145 0.17 97.915 0.43 ; + RECT 97.145 0.17 97.405 11.38 ; + RECT 97.655 0.17 97.915 17.1 ; + RECT 96.145 617.545 96.345 618.275 ; + RECT 96.64 617.545 96.84 618.275 ; + RECT 97.46 617.545 97.66 618.275 ; + RECT 97.955 617.545 98.155 618.275 ; + RECT 98.455 617.545 98.655 618.275 ; + RECT 98.52 0.52 98.78 2.255 ; + RECT 98.955 617.545 99.155 618.275 ; + RECT 99.185 0.52 99.445 8.085 ; + RECT 99.45 617.545 99.65 618.275 ; + RECT 100.05 0.52 100.31 1.5 ; + RECT 100.27 617.545 100.47 618.275 ; + RECT 100.765 617.545 100.965 618.275 ; + RECT 101.265 617.545 101.465 618.275 ; + RECT 101.765 617.545 101.965 618.275 ; + RECT 102.26 617.545 102.46 618.275 ; + RECT 103.08 617.545 103.28 618.275 ; + RECT 103.575 617.545 103.775 618.275 ; + RECT 103.93 0.52 104.19 2.255 ; + RECT 104.075 617.545 104.275 618.275 ; + RECT 104.575 617.545 104.775 618.275 ; + RECT 105.07 617.545 105.27 618.275 ; + RECT 106.175 0.8 106.945 1.57 ; + RECT 106.175 0.3 106.435 13.03 ; + RECT 106.685 0.3 106.945 13.03 ; + RECT 105.46 0.52 105.72 2.255 ; + RECT 105.89 617.545 106.09 618.275 ; + RECT 106.385 617.545 106.585 618.275 ; + RECT 106.885 617.545 107.085 618.275 ; + RECT 107.385 617.545 107.585 618.275 ; + RECT 107.88 617.545 108.08 618.275 ; + RECT 108.7 617.545 108.9 618.275 ; + RECT 109.895 0.17 110.665 0.43 ; + RECT 109.895 0.17 110.155 13.055 ; + RECT 110.405 0.17 110.665 13.055 ; + RECT 109.195 617.545 109.395 618.275 ; + RECT 109.695 617.545 109.895 618.275 ; + RECT 110.195 617.545 110.395 618.275 ; + RECT 110.69 617.545 110.89 618.275 ; + RECT 111.51 617.545 111.71 618.275 ; + RECT 112.005 617.545 112.205 618.275 ; + RECT 112.505 617.545 112.705 618.275 ; + RECT 113.005 617.545 113.205 618.275 ; + RECT 113.5 617.545 113.7 618.275 ; + RECT 114.32 617.545 114.52 618.275 ; + RECT 114.815 617.545 115.015 618.275 ; + RECT 115.315 617.545 115.515 618.275 ; + RECT 115.815 617.545 116.015 618.275 ; + RECT 116.31 617.545 116.51 618.275 ; + RECT 117.13 617.545 117.33 618.275 ; + RECT 117.625 617.545 117.825 618.275 ; + RECT 118.125 617.545 118.325 618.275 ; + RECT 119.625 0.17 120.395 0.43 ; + RECT 119.625 0.17 119.885 11.38 ; + RECT 120.135 0.17 120.395 17.1 ; + RECT 118.625 617.545 118.825 618.275 ; + RECT 119.12 617.545 119.32 618.275 ; + RECT 119.94 617.545 120.14 618.275 ; + RECT 120.435 617.545 120.635 618.275 ; + RECT 120.935 617.545 121.135 618.275 ; + RECT 121 0.52 121.26 2.255 ; + RECT 121.435 617.545 121.635 618.275 ; + RECT 121.665 0.52 121.925 8.085 ; + RECT 121.93 617.545 122.13 618.275 ; + RECT 122.53 0.52 122.79 1.5 ; + RECT 122.75 617.545 122.95 618.275 ; + RECT 123.245 617.545 123.445 618.275 ; + RECT 123.745 617.545 123.945 618.275 ; + RECT 124.245 617.545 124.445 618.275 ; + RECT 124.74 617.545 124.94 618.275 ; + RECT 125.56 617.545 125.76 618.275 ; + RECT 126.055 617.545 126.255 618.275 ; + RECT 126.41 0.52 126.67 2.255 ; + RECT 126.555 617.545 126.755 618.275 ; + RECT 127.055 617.545 127.255 618.275 ; + RECT 127.55 617.545 127.75 618.275 ; + RECT 128.655 0.8 129.425 1.57 ; + RECT 128.655 0.3 128.915 13.03 ; + RECT 129.165 0.3 129.425 13.03 ; + RECT 127.94 0.52 128.2 2.255 ; + RECT 128.37 617.545 128.57 618.275 ; + RECT 128.865 617.545 129.065 618.275 ; + RECT 129.365 617.545 129.565 618.275 ; + RECT 129.865 617.545 130.065 618.275 ; + RECT 130.36 617.545 130.56 618.275 ; + RECT 131.18 617.545 131.38 618.275 ; + RECT 132.375 0.17 133.145 0.43 ; + RECT 132.375 0.17 132.635 13.055 ; + RECT 132.885 0.17 133.145 13.055 ; + RECT 131.675 617.545 131.875 618.275 ; + RECT 132.175 617.545 132.375 618.275 ; + RECT 132.675 617.545 132.875 618.275 ; + RECT 133.17 617.545 133.37 618.275 ; + RECT 133.99 617.545 134.19 618.275 ; + RECT 134.485 617.545 134.685 618.275 ; + RECT 134.985 617.545 135.185 618.275 ; + RECT 135.485 617.545 135.685 618.275 ; + RECT 135.98 617.545 136.18 618.275 ; + RECT 136.8 617.545 137 618.275 ; + RECT 137.295 617.545 137.495 618.275 ; + RECT 137.795 617.545 137.995 618.275 ; + RECT 138.295 617.545 138.495 618.275 ; + RECT 138.79 617.545 138.99 618.275 ; + RECT 139.61 617.545 139.81 618.275 ; + RECT 140.105 617.545 140.305 618.275 ; + RECT 140.605 617.545 140.805 618.275 ; + RECT 142.105 0.17 142.875 0.43 ; + RECT 142.105 0.17 142.365 11.38 ; + RECT 142.615 0.17 142.875 17.1 ; + RECT 141.105 617.545 141.305 618.275 ; + RECT 141.6 617.545 141.8 618.275 ; + RECT 142.42 617.545 142.62 618.275 ; + RECT 142.915 617.545 143.115 618.275 ; + RECT 143.415 617.545 143.615 618.275 ; + RECT 143.48 0.52 143.74 2.255 ; + RECT 143.915 617.545 144.115 618.275 ; + RECT 144.145 0.52 144.405 8.085 ; + RECT 144.41 617.545 144.61 618.275 ; + RECT 145.01 0.52 145.27 1.5 ; + RECT 145.23 617.545 145.43 618.275 ; + RECT 145.725 617.545 145.925 618.275 ; + RECT 146.225 617.545 146.425 618.275 ; + RECT 146.725 617.545 146.925 618.275 ; + RECT 147.22 617.545 147.42 618.275 ; + RECT 148.04 617.545 148.24 618.275 ; + RECT 148.535 617.545 148.735 618.275 ; + RECT 148.89 0.52 149.15 2.255 ; + RECT 149.035 617.545 149.235 618.275 ; + RECT 149.535 617.545 149.735 618.275 ; + RECT 150.03 617.545 150.23 618.275 ; + RECT 151.135 0.8 151.905 1.57 ; + RECT 151.135 0.3 151.395 13.03 ; + RECT 151.645 0.3 151.905 13.03 ; + RECT 150.42 0.52 150.68 2.255 ; + RECT 150.85 617.545 151.05 618.275 ; + RECT 151.345 617.545 151.545 618.275 ; + RECT 151.845 617.545 152.045 618.275 ; + RECT 152.345 617.545 152.545 618.275 ; + RECT 152.84 617.545 153.04 618.275 ; + RECT 153.66 617.545 153.86 618.275 ; + RECT 154.855 0.17 155.625 0.43 ; + RECT 154.855 0.17 155.115 13.055 ; + RECT 155.365 0.17 155.625 13.055 ; + RECT 154.155 617.545 154.355 618.275 ; + RECT 154.655 617.545 154.855 618.275 ; + RECT 155.155 617.545 155.355 618.275 ; + RECT 155.65 617.545 155.85 618.275 ; + RECT 156.47 617.545 156.67 618.275 ; + RECT 156.965 617.545 157.165 618.275 ; + RECT 157.465 617.545 157.665 618.275 ; + RECT 157.965 617.545 158.165 618.275 ; + RECT 158.46 617.545 158.66 618.275 ; + RECT 159.28 617.545 159.48 618.275 ; + RECT 159.775 617.545 159.975 618.275 ; + RECT 160.275 617.545 160.475 618.275 ; + RECT 160.775 617.545 160.975 618.275 ; + RECT 161.27 617.545 161.47 618.275 ; + RECT 162.09 617.545 162.29 618.275 ; + RECT 162.585 617.545 162.785 618.275 ; + RECT 163.085 617.545 163.285 618.275 ; + RECT 164.585 0.17 165.355 0.43 ; + RECT 164.585 0.17 164.845 11.38 ; + RECT 165.095 0.17 165.355 17.1 ; + RECT 163.585 617.545 163.785 618.275 ; + RECT 164.08 617.545 164.28 618.275 ; + RECT 164.9 617.545 165.1 618.275 ; + RECT 165.395 617.545 165.595 618.275 ; + RECT 165.895 617.545 166.095 618.275 ; + RECT 165.96 0.52 166.22 2.255 ; + RECT 166.395 617.545 166.595 618.275 ; + RECT 166.625 0.52 166.885 8.085 ; + RECT 166.89 617.545 167.09 618.275 ; + RECT 167.49 0.52 167.75 1.5 ; + RECT 167.71 617.545 167.91 618.275 ; + RECT 168.205 617.545 168.405 618.275 ; + RECT 168.705 617.545 168.905 618.275 ; + RECT 169.205 617.545 169.405 618.275 ; + RECT 169.7 617.545 169.9 618.275 ; + RECT 170.52 617.545 170.72 618.275 ; + RECT 171.015 617.545 171.215 618.275 ; + RECT 171.37 0.52 171.63 2.255 ; + RECT 171.515 617.545 171.715 618.275 ; + RECT 172.015 617.545 172.215 618.275 ; + RECT 172.51 617.545 172.71 618.275 ; + RECT 173.615 0.8 174.385 1.57 ; + RECT 173.615 0.3 173.875 13.03 ; + RECT 174.125 0.3 174.385 13.03 ; + RECT 172.9 0.52 173.16 2.255 ; + RECT 173.33 617.545 173.53 618.275 ; + RECT 173.825 617.545 174.025 618.275 ; + RECT 174.325 617.545 174.525 618.275 ; + RECT 174.825 617.545 175.025 618.275 ; + RECT 175.32 617.545 175.52 618.275 ; + RECT 176.14 617.545 176.34 618.275 ; + RECT 177.335 0.17 178.105 0.43 ; + RECT 177.335 0.17 177.595 13.055 ; + RECT 177.845 0.17 178.105 13.055 ; + RECT 176.635 617.545 176.835 618.275 ; + RECT 177.135 617.545 177.335 618.275 ; + RECT 177.635 617.545 177.835 618.275 ; + RECT 178.13 617.545 178.33 618.275 ; + RECT 178.95 617.545 179.15 618.275 ; + RECT 179.445 617.545 179.645 618.275 ; + RECT 179.945 617.545 180.145 618.275 ; + RECT 180.445 617.545 180.645 618.275 ; + RECT 186.515 0.17 187.285 0.43 ; + RECT 186.515 0.17 186.775 36.945 ; + RECT 187.025 0.17 187.285 36.945 ; + RECT 180.94 617.545 181.14 618.275 ; + RECT 181.76 617.545 181.96 618.275 ; + RECT 189.22 0 189.48 4.94 ; + RECT 189.22 4.68 189.99 4.94 ; + RECT 189.73 4.68 189.99 12.9 ; + RECT 189.73 0.52 189.99 1.78 ; + RECT 189.73 1.52 190.5 1.78 ; + RECT 190.24 1.52 190.5 12.9 ; + RECT 182.755 617.545 182.955 618.275 ; + RECT 190.24 0.59 191.01 1.27 ; + RECT 190.75 0.59 191.01 7.965 ; + RECT 187.535 0.3 187.795 37.365 ; + RECT 188.045 0.3 188.305 37.365 ; + RECT 191.26 0.52 191.52 12.9 ; + RECT 191.77 0 192.03 12.9 ; + RECT 192.28 0.52 192.54 12.9 ; + RECT 192.79 0.52 193.05 12.9 ; + RECT 193.3 0.52 193.56 12.9 ; + RECT 196.36 0.17 197.13 0.43 ; + RECT 196.36 0.17 196.62 2.085 ; + RECT 196.87 0.17 197.13 9 ; + RECT 193.81 0.52 194.07 12.9 ; + RECT 194.32 0 194.58 8.565 ; + RECT 194.83 0 195.09 8.055 ; + RECT 200.95 0.52 201.21 6.59 ; + RECT 202.48 0.52 202.74 6.305 ; + RECT 202.48 6.045 203.45 6.305 ; + RECT 201.46 0.52 201.72 2.23 ; + RECT 202.99 0.52 203.25 2.955 ; + RECT 204.01 0.52 204.27 12.9 ; + RECT 204.52 0.52 204.78 12.9 ; + RECT 206.05 0.52 206.31 6.29 ; + RECT 205.54 6.045 206.31 6.29 ; + RECT 205.03 0.52 205.29 6.745 ; + RECT 207.58 0.52 207.84 6.59 ; + RECT 206.935 6.33 207.84 6.59 ; + RECT 205.54 0.52 205.8 2.955 ; + RECT 207.07 0.52 207.33 2.67 ; + RECT 208.6 0.52 208.86 12.9 ; + RECT 209.11 0.52 209.37 12.9 ; + RECT 210.64 0.575 210.9 7.965 ; + RECT 211.15 0.52 211.41 12.9 ; + RECT 211.66 0.52 211.92 12.9 ; + RECT 212.17 0.52 212.43 12.9 ; + RECT 212.68 0.52 212.94 12.9 ; + RECT 213.19 0.52 213.45 12.9 ; + RECT 213.7 0.52 213.96 12.9 ; + RECT 214.21 0.52 214.47 12.9 ; + RECT 214.72 0.52 214.98 12.9 ; + RECT 216.25 0.59 217.02 1.27 ; + RECT 216.25 0.59 216.51 8.83 ; + RECT 215.23 0.52 215.49 12.9 ; + RECT 215.74 0.52 216 12.9 ; + RECT 217.27 0.52 217.53 12.9 ; + RECT 217.78 0.52 218.04 12.9 ; + RECT 224.92 0.17 225.69 0.43 ; + RECT 224.92 0.17 225.18 13.845 ; + RECT 225.43 0.17 225.69 13.845 ; + RECT 226.96 0.17 227.73 0.43 ; + RECT 226.96 0.17 227.22 2.11 ; + RECT 227.47 0.17 227.73 2.11 ; + RECT 222.37 0.52 222.63 3.61 ; + RECT 222.88 0.52 223.14 4.12 ; + RECT 229.355 0.17 230.125 0.43 ; + RECT 229.355 0.17 229.615 36.945 ; + RECT 229.865 0.17 230.125 36.945 ; + RECT 224.41 0.52 224.67 15.16 ; + RECT 228.335 0.3 228.595 37.365 ; + RECT 228.845 0.3 229.105 37.365 ; + RECT 233.685 617.545 233.885 618.275 ; + RECT 234.68 617.545 234.88 618.275 ; + RECT 235.5 617.545 235.7 618.275 ; + RECT 235.995 617.545 236.195 618.275 ; + RECT 236.495 617.545 236.695 618.275 ; + RECT 236.995 617.545 237.195 618.275 ; + RECT 238.535 0.17 239.305 0.43 ; + RECT 238.535 0.17 238.795 13.055 ; + RECT 239.045 0.17 239.305 13.055 ; + RECT 237.49 617.545 237.69 618.275 ; + RECT 238.31 617.545 238.51 618.275 ; + RECT 238.805 617.545 239.005 618.275 ; + RECT 239.305 617.545 239.505 618.275 ; + RECT 239.805 617.545 240.005 618.275 ; + RECT 240.3 617.545 240.5 618.275 ; + RECT 241.12 617.545 241.32 618.275 ; + RECT 242.255 0.8 243.025 1.57 ; + RECT 242.255 0.3 242.515 13.03 ; + RECT 242.765 0.3 243.025 13.03 ; + RECT 241.615 617.545 241.815 618.275 ; + RECT 242.115 617.545 242.315 618.275 ; + RECT 242.615 617.545 242.815 618.275 ; + RECT 243.11 617.545 243.31 618.275 ; + RECT 243.48 0.52 243.74 2.255 ; + RECT 243.93 617.545 244.13 618.275 ; + RECT 244.425 617.545 244.625 618.275 ; + RECT 244.925 617.545 245.125 618.275 ; + RECT 245.01 0.52 245.27 2.255 ; + RECT 245.425 617.545 245.625 618.275 ; + RECT 245.92 617.545 246.12 618.275 ; + RECT 246.74 617.545 246.94 618.275 ; + RECT 247.235 617.545 247.435 618.275 ; + RECT 247.735 617.545 247.935 618.275 ; + RECT 248.235 617.545 248.435 618.275 ; + RECT 248.73 617.545 248.93 618.275 ; + RECT 248.89 0.52 249.15 1.5 ; + RECT 249.55 617.545 249.75 618.275 ; + RECT 249.755 0.52 250.015 8.085 ; + RECT 250.045 617.545 250.245 618.275 ; + RECT 250.42 0.52 250.68 2.255 ; + RECT 251.285 0.17 252.055 0.43 ; + RECT 251.795 0.17 252.055 11.38 ; + RECT 251.285 0.17 251.545 17.1 ; + RECT 250.545 617.545 250.745 618.275 ; + RECT 251.045 617.545 251.245 618.275 ; + RECT 251.54 617.545 251.74 618.275 ; + RECT 252.36 617.545 252.56 618.275 ; + RECT 252.855 617.545 253.055 618.275 ; + RECT 253.355 617.545 253.555 618.275 ; + RECT 253.855 617.545 254.055 618.275 ; + RECT 254.35 617.545 254.55 618.275 ; + RECT 255.17 617.545 255.37 618.275 ; + RECT 255.665 617.545 255.865 618.275 ; + RECT 256.165 617.545 256.365 618.275 ; + RECT 256.665 617.545 256.865 618.275 ; + RECT 257.16 617.545 257.36 618.275 ; + RECT 257.98 617.545 258.18 618.275 ; + RECT 258.475 617.545 258.675 618.275 ; + RECT 258.975 617.545 259.175 618.275 ; + RECT 259.475 617.545 259.675 618.275 ; + RECT 261.015 0.17 261.785 0.43 ; + RECT 261.015 0.17 261.275 13.055 ; + RECT 261.525 0.17 261.785 13.055 ; + RECT 259.97 617.545 260.17 618.275 ; + RECT 260.79 617.545 260.99 618.275 ; + RECT 261.285 617.545 261.485 618.275 ; + RECT 261.785 617.545 261.985 618.275 ; + RECT 262.285 617.545 262.485 618.275 ; + RECT 262.78 617.545 262.98 618.275 ; + RECT 263.6 617.545 263.8 618.275 ; + RECT 264.735 0.8 265.505 1.57 ; + RECT 264.735 0.3 264.995 13.03 ; + RECT 265.245 0.3 265.505 13.03 ; + RECT 264.095 617.545 264.295 618.275 ; + RECT 264.595 617.545 264.795 618.275 ; + RECT 265.095 617.545 265.295 618.275 ; + RECT 265.59 617.545 265.79 618.275 ; + RECT 265.96 0.52 266.22 2.255 ; + RECT 266.41 617.545 266.61 618.275 ; + RECT 266.905 617.545 267.105 618.275 ; + RECT 267.405 617.545 267.605 618.275 ; + RECT 267.49 0.52 267.75 2.255 ; + RECT 267.905 617.545 268.105 618.275 ; + RECT 268.4 617.545 268.6 618.275 ; + RECT 269.22 617.545 269.42 618.275 ; + RECT 269.715 617.545 269.915 618.275 ; + RECT 270.215 617.545 270.415 618.275 ; + RECT 270.715 617.545 270.915 618.275 ; + RECT 271.21 617.545 271.41 618.275 ; + RECT 271.37 0.52 271.63 1.5 ; + RECT 272.03 617.545 272.23 618.275 ; + RECT 272.235 0.52 272.495 8.085 ; + RECT 272.525 617.545 272.725 618.275 ; + RECT 272.9 0.52 273.16 2.255 ; + RECT 273.765 0.17 274.535 0.43 ; + RECT 274.275 0.17 274.535 11.38 ; + RECT 273.765 0.17 274.025 17.1 ; + RECT 273.025 617.545 273.225 618.275 ; + RECT 273.525 617.545 273.725 618.275 ; + RECT 274.02 617.545 274.22 618.275 ; + RECT 274.84 617.545 275.04 618.275 ; + RECT 275.335 617.545 275.535 618.275 ; + RECT 275.835 617.545 276.035 618.275 ; + RECT 276.335 617.545 276.535 618.275 ; + RECT 276.83 617.545 277.03 618.275 ; + RECT 277.65 617.545 277.85 618.275 ; + RECT 278.145 617.545 278.345 618.275 ; + RECT 278.645 617.545 278.845 618.275 ; + RECT 279.145 617.545 279.345 618.275 ; + RECT 279.64 617.545 279.84 618.275 ; + RECT 280.46 617.545 280.66 618.275 ; + RECT 280.955 617.545 281.155 618.275 ; + RECT 281.455 617.545 281.655 618.275 ; + RECT 281.955 617.545 282.155 618.275 ; + RECT 283.495 0.17 284.265 0.43 ; + RECT 283.495 0.17 283.755 13.055 ; + RECT 284.005 0.17 284.265 13.055 ; + RECT 282.45 617.545 282.65 618.275 ; + RECT 283.27 617.545 283.47 618.275 ; + RECT 283.765 617.545 283.965 618.275 ; + RECT 284.265 617.545 284.465 618.275 ; + RECT 284.765 617.545 284.965 618.275 ; + RECT 285.26 617.545 285.46 618.275 ; + RECT 286.08 617.545 286.28 618.275 ; + RECT 287.215 0.8 287.985 1.57 ; + RECT 287.215 0.3 287.475 13.03 ; + RECT 287.725 0.3 287.985 13.03 ; + RECT 286.575 617.545 286.775 618.275 ; + RECT 287.075 617.545 287.275 618.275 ; + RECT 287.575 617.545 287.775 618.275 ; + RECT 288.07 617.545 288.27 618.275 ; + RECT 288.44 0.52 288.7 2.255 ; + RECT 288.89 617.545 289.09 618.275 ; + RECT 289.385 617.545 289.585 618.275 ; + RECT 289.885 617.545 290.085 618.275 ; + RECT 289.97 0.52 290.23 2.255 ; + RECT 290.385 617.545 290.585 618.275 ; + RECT 290.88 617.545 291.08 618.275 ; + RECT 291.7 617.545 291.9 618.275 ; + RECT 292.195 617.545 292.395 618.275 ; + RECT 292.695 617.545 292.895 618.275 ; + RECT 293.195 617.545 293.395 618.275 ; + RECT 293.69 617.545 293.89 618.275 ; + RECT 293.85 0.52 294.11 1.5 ; + RECT 294.51 617.545 294.71 618.275 ; + RECT 294.715 0.52 294.975 8.085 ; + RECT 295.005 617.545 295.205 618.275 ; + RECT 295.38 0.52 295.64 2.255 ; + RECT 296.245 0.17 297.015 0.43 ; + RECT 296.755 0.17 297.015 11.38 ; + RECT 296.245 0.17 296.505 17.1 ; + RECT 295.505 617.545 295.705 618.275 ; + RECT 296.005 617.545 296.205 618.275 ; + RECT 296.5 617.545 296.7 618.275 ; + RECT 297.32 617.545 297.52 618.275 ; + RECT 297.815 617.545 298.015 618.275 ; + RECT 298.315 617.545 298.515 618.275 ; + RECT 298.815 617.545 299.015 618.275 ; + RECT 299.31 617.545 299.51 618.275 ; + RECT 300.13 617.545 300.33 618.275 ; + RECT 300.625 617.545 300.825 618.275 ; + RECT 301.125 617.545 301.325 618.275 ; + RECT 301.625 617.545 301.825 618.275 ; + RECT 302.12 617.545 302.32 618.275 ; + RECT 302.94 617.545 303.14 618.275 ; + RECT 303.435 617.545 303.635 618.275 ; + RECT 303.935 617.545 304.135 618.275 ; + RECT 304.435 617.545 304.635 618.275 ; + RECT 305.975 0.17 306.745 0.43 ; + RECT 305.975 0.17 306.235 13.055 ; + RECT 306.485 0.17 306.745 13.055 ; + RECT 304.93 617.545 305.13 618.275 ; + RECT 305.75 617.545 305.95 618.275 ; + RECT 306.245 617.545 306.445 618.275 ; + RECT 306.745 617.545 306.945 618.275 ; + RECT 307.245 617.545 307.445 618.275 ; + RECT 307.74 617.545 307.94 618.275 ; + RECT 308.56 617.545 308.76 618.275 ; + RECT 309.695 0.8 310.465 1.57 ; + RECT 309.695 0.3 309.955 13.03 ; + RECT 310.205 0.3 310.465 13.03 ; + RECT 309.055 617.545 309.255 618.275 ; + RECT 309.555 617.545 309.755 618.275 ; + RECT 310.055 617.545 310.255 618.275 ; + RECT 310.55 617.545 310.75 618.275 ; + RECT 310.92 0.52 311.18 2.255 ; + RECT 311.37 617.545 311.57 618.275 ; + RECT 311.865 617.545 312.065 618.275 ; + RECT 312.365 617.545 312.565 618.275 ; + RECT 312.45 0.52 312.71 2.255 ; + RECT 312.865 617.545 313.065 618.275 ; + RECT 313.36 617.545 313.56 618.275 ; + RECT 314.18 617.545 314.38 618.275 ; + RECT 314.675 617.545 314.875 618.275 ; + RECT 315.175 617.545 315.375 618.275 ; + RECT 315.675 617.545 315.875 618.275 ; + RECT 316.17 617.545 316.37 618.275 ; + RECT 316.33 0.52 316.59 1.5 ; + RECT 316.99 617.545 317.19 618.275 ; + RECT 317.195 0.52 317.455 8.085 ; + RECT 317.485 617.545 317.685 618.275 ; + RECT 317.86 0.52 318.12 2.255 ; + RECT 318.725 0.17 319.495 0.43 ; + RECT 319.235 0.17 319.495 11.38 ; + RECT 318.725 0.17 318.985 17.1 ; + RECT 317.985 617.545 318.185 618.275 ; + RECT 318.485 617.545 318.685 618.275 ; + RECT 318.98 617.545 319.18 618.275 ; + RECT 319.8 617.545 320 618.275 ; + RECT 320.295 617.545 320.495 618.275 ; + RECT 320.795 617.545 320.995 618.275 ; + RECT 321.295 617.545 321.495 618.275 ; + RECT 321.79 617.545 321.99 618.275 ; + RECT 322.61 617.545 322.81 618.275 ; + RECT 323.105 617.545 323.305 618.275 ; + RECT 323.605 617.545 323.805 618.275 ; + RECT 324.105 617.545 324.305 618.275 ; + RECT 324.6 617.545 324.8 618.275 ; + RECT 325.42 617.545 325.62 618.275 ; + RECT 325.915 617.545 326.115 618.275 ; + RECT 326.415 617.545 326.615 618.275 ; + RECT 326.915 617.545 327.115 618.275 ; + RECT 328.455 0.17 329.225 0.43 ; + RECT 328.455 0.17 328.715 13.055 ; + RECT 328.965 0.17 329.225 13.055 ; + RECT 327.41 617.545 327.61 618.275 ; + RECT 328.23 617.545 328.43 618.275 ; + RECT 328.725 617.545 328.925 618.275 ; + RECT 329.225 617.545 329.425 618.275 ; + RECT 329.725 617.545 329.925 618.275 ; + RECT 330.22 617.545 330.42 618.275 ; + RECT 331.04 617.545 331.24 618.275 ; + RECT 332.175 0.8 332.945 1.57 ; + RECT 332.175 0.3 332.435 13.03 ; + RECT 332.685 0.3 332.945 13.03 ; + RECT 331.535 617.545 331.735 618.275 ; + RECT 332.035 617.545 332.235 618.275 ; + RECT 332.535 617.545 332.735 618.275 ; + RECT 333.03 617.545 333.23 618.275 ; + RECT 333.4 0.52 333.66 2.255 ; + RECT 333.85 617.545 334.05 618.275 ; + RECT 334.345 617.545 334.545 618.275 ; + RECT 334.845 617.545 335.045 618.275 ; + RECT 334.93 0.52 335.19 2.255 ; + RECT 335.345 617.545 335.545 618.275 ; + RECT 335.84 617.545 336.04 618.275 ; + RECT 336.66 617.545 336.86 618.275 ; + RECT 337.155 617.545 337.355 618.275 ; + RECT 337.655 617.545 337.855 618.275 ; + RECT 338.155 617.545 338.355 618.275 ; + RECT 338.65 617.545 338.85 618.275 ; + RECT 338.81 0.52 339.07 1.5 ; + RECT 339.47 617.545 339.67 618.275 ; + RECT 339.675 0.52 339.935 8.085 ; + RECT 339.965 617.545 340.165 618.275 ; + RECT 340.34 0.52 340.6 2.255 ; + RECT 341.205 0.17 341.975 0.43 ; + RECT 341.715 0.17 341.975 11.38 ; + RECT 341.205 0.17 341.465 17.1 ; + RECT 340.465 617.545 340.665 618.275 ; + RECT 340.965 617.545 341.165 618.275 ; + RECT 341.46 617.545 341.66 618.275 ; + RECT 342.28 617.545 342.48 618.275 ; + RECT 342.775 617.545 342.975 618.275 ; + RECT 343.275 617.545 343.475 618.275 ; + RECT 343.775 617.545 343.975 618.275 ; + RECT 344.27 617.545 344.47 618.275 ; + RECT 345.09 617.545 345.29 618.275 ; + RECT 345.585 617.545 345.785 618.275 ; + RECT 346.085 617.545 346.285 618.275 ; + RECT 346.585 617.545 346.785 618.275 ; + RECT 347.08 617.545 347.28 618.275 ; + RECT 347.9 617.545 348.1 618.275 ; + RECT 348.395 617.545 348.595 618.275 ; + RECT 348.895 617.545 349.095 618.275 ; + RECT 349.395 617.545 349.595 618.275 ; + RECT 350.935 0.17 351.705 0.43 ; + RECT 350.935 0.17 351.195 13.055 ; + RECT 351.445 0.17 351.705 13.055 ; + RECT 349.89 617.545 350.09 618.275 ; + RECT 350.71 617.545 350.91 618.275 ; + RECT 351.205 617.545 351.405 618.275 ; + RECT 351.705 617.545 351.905 618.275 ; + RECT 352.205 617.545 352.405 618.275 ; + RECT 352.7 617.545 352.9 618.275 ; + RECT 353.52 617.545 353.72 618.275 ; + RECT 354.655 0.8 355.425 1.57 ; + RECT 354.655 0.3 354.915 13.03 ; + RECT 355.165 0.3 355.425 13.03 ; + RECT 354.015 617.545 354.215 618.275 ; + RECT 354.515 617.545 354.715 618.275 ; + RECT 355.015 617.545 355.215 618.275 ; + RECT 355.51 617.545 355.71 618.275 ; + RECT 355.88 0.52 356.14 2.255 ; + RECT 356.33 617.545 356.53 618.275 ; + RECT 356.825 617.545 357.025 618.275 ; + RECT 357.325 617.545 357.525 618.275 ; + RECT 357.41 0.52 357.67 2.255 ; + RECT 357.825 617.545 358.025 618.275 ; + RECT 358.32 617.545 358.52 618.275 ; + RECT 359.14 617.545 359.34 618.275 ; + RECT 359.635 617.545 359.835 618.275 ; + RECT 360.135 617.545 360.335 618.275 ; + RECT 360.635 617.545 360.835 618.275 ; + RECT 361.13 617.545 361.33 618.275 ; + RECT 361.29 0.52 361.55 1.5 ; + RECT 361.95 617.545 362.15 618.275 ; + RECT 362.155 0.52 362.415 8.085 ; + RECT 362.445 617.545 362.645 618.275 ; + RECT 362.82 0.52 363.08 2.255 ; + RECT 363.685 0.17 364.455 0.43 ; + RECT 364.195 0.17 364.455 11.38 ; + RECT 363.685 0.17 363.945 17.1 ; + RECT 362.945 617.545 363.145 618.275 ; + RECT 363.445 617.545 363.645 618.275 ; + RECT 363.94 617.545 364.14 618.275 ; + RECT 364.76 617.545 364.96 618.275 ; + RECT 365.255 617.545 365.455 618.275 ; + RECT 365.755 617.545 365.955 618.275 ; + RECT 366.255 617.545 366.455 618.275 ; + RECT 366.75 617.545 366.95 618.275 ; + RECT 367.57 617.545 367.77 618.275 ; + RECT 368.065 617.545 368.265 618.275 ; + RECT 368.565 617.545 368.765 618.275 ; + RECT 369.065 617.545 369.265 618.275 ; + RECT 369.56 617.545 369.76 618.275 ; + RECT 370.38 617.545 370.58 618.275 ; + RECT 370.875 617.545 371.075 618.275 ; + RECT 371.375 617.545 371.575 618.275 ; + RECT 371.875 617.545 372.075 618.275 ; + RECT 373.415 0.17 374.185 0.43 ; + RECT 373.415 0.17 373.675 13.055 ; + RECT 373.925 0.17 374.185 13.055 ; + RECT 372.37 617.545 372.57 618.275 ; + RECT 373.19 617.545 373.39 618.275 ; + RECT 373.685 617.545 373.885 618.275 ; + RECT 374.185 617.545 374.385 618.275 ; + RECT 374.685 617.545 374.885 618.275 ; + RECT 375.18 617.545 375.38 618.275 ; + RECT 376 617.545 376.2 618.275 ; + RECT 377.135 0.8 377.905 1.57 ; + RECT 377.135 0.3 377.395 13.03 ; + RECT 377.645 0.3 377.905 13.03 ; + RECT 376.495 617.545 376.695 618.275 ; + RECT 376.995 617.545 377.195 618.275 ; + RECT 377.495 617.545 377.695 618.275 ; + RECT 377.99 617.545 378.19 618.275 ; + RECT 378.36 0.52 378.62 2.255 ; + RECT 378.81 617.545 379.01 618.275 ; + RECT 379.305 617.545 379.505 618.275 ; + RECT 379.805 617.545 380.005 618.275 ; + RECT 379.89 0.52 380.15 2.255 ; + RECT 380.305 617.545 380.505 618.275 ; + RECT 380.8 617.545 381 618.275 ; + RECT 381.62 617.545 381.82 618.275 ; + RECT 382.115 617.545 382.315 618.275 ; + RECT 382.615 617.545 382.815 618.275 ; + RECT 383.115 617.545 383.315 618.275 ; + RECT 383.61 617.545 383.81 618.275 ; + RECT 383.77 0.52 384.03 1.5 ; + RECT 384.43 617.545 384.63 618.275 ; + RECT 384.635 0.52 384.895 8.085 ; + RECT 384.925 617.545 385.125 618.275 ; + RECT 385.3 0.52 385.56 2.255 ; + RECT 386.165 0.17 386.935 0.43 ; + RECT 386.675 0.17 386.935 11.38 ; + RECT 386.165 0.17 386.425 17.1 ; + RECT 385.425 617.545 385.625 618.275 ; + RECT 385.925 617.545 386.125 618.275 ; + RECT 386.42 617.545 386.62 618.275 ; + RECT 387.24 617.545 387.44 618.275 ; + RECT 387.735 617.545 387.935 618.275 ; + RECT 388.235 617.545 388.435 618.275 ; + RECT 388.735 617.545 388.935 618.275 ; + RECT 389.23 617.545 389.43 618.275 ; + RECT 390.05 617.545 390.25 618.275 ; + RECT 390.545 617.545 390.745 618.275 ; + RECT 391.045 617.545 391.245 618.275 ; + RECT 391.545 617.545 391.745 618.275 ; + RECT 392.04 617.545 392.24 618.275 ; + RECT 392.86 617.545 393.06 618.275 ; + RECT 393.355 617.545 393.555 618.275 ; + RECT 393.855 617.545 394.055 618.275 ; + RECT 394.355 617.545 394.555 618.275 ; + RECT 395.895 0.17 396.665 0.43 ; + RECT 395.895 0.17 396.155 13.055 ; + RECT 396.405 0.17 396.665 13.055 ; + RECT 394.85 617.545 395.05 618.275 ; + RECT 395.67 617.545 395.87 618.275 ; + RECT 396.165 617.545 396.365 618.275 ; + RECT 396.665 617.545 396.865 618.275 ; + RECT 397.165 617.545 397.365 618.275 ; + RECT 397.66 617.545 397.86 618.275 ; + RECT 398.48 617.545 398.68 618.275 ; + RECT 399.615 0.8 400.385 1.57 ; + RECT 399.615 0.3 399.875 13.03 ; + RECT 400.125 0.3 400.385 13.03 ; + RECT 398.975 617.545 399.175 618.275 ; + RECT 399.475 617.545 399.675 618.275 ; + RECT 399.975 617.545 400.175 618.275 ; + RECT 400.47 617.545 400.67 618.275 ; + RECT 400.84 0.52 401.1 2.255 ; + RECT 401.29 617.545 401.49 618.275 ; + RECT 401.785 617.545 401.985 618.275 ; + RECT 402.285 617.545 402.485 618.275 ; + RECT 402.37 0.52 402.63 2.255 ; + RECT 402.785 617.545 402.985 618.275 ; + RECT 403.28 617.545 403.48 618.275 ; + RECT 404.1 617.545 404.3 618.275 ; + RECT 404.595 617.545 404.795 618.275 ; + RECT 405.095 617.545 405.295 618.275 ; + RECT 405.595 617.545 405.795 618.275 ; + RECT 406.09 617.545 406.29 618.275 ; + RECT 406.25 0.52 406.51 1.5 ; + RECT 406.91 617.545 407.11 618.275 ; + RECT 407.115 0.52 407.375 8.085 ; + RECT 407.405 617.545 407.605 618.275 ; + RECT 407.78 0.52 408.04 2.255 ; + RECT 408.645 0.17 409.415 0.43 ; + RECT 409.155 0.17 409.415 11.38 ; + RECT 408.645 0.17 408.905 17.1 ; + RECT 407.905 617.545 408.105 618.275 ; + RECT 408.405 617.545 408.605 618.275 ; + RECT 408.9 617.545 409.1 618.275 ; + RECT 409.72 617.545 409.92 618.275 ; + RECT 410.215 617.545 410.415 618.275 ; + RECT 410.715 617.545 410.915 618.275 ; + RECT 411.215 617.545 411.415 618.275 ; + RECT 411.71 617.545 411.91 618.275 ; + RECT 412.53 617.545 412.73 618.275 ; + RECT 413.025 617.545 413.225 618.275 ; + RECT 413.525 617.545 413.725 618.275 ; + RECT 414.025 617.545 414.225 618.275 ; + RECT 414.52 617.545 414.72 618.275 ; + RECT 415.34 617.545 415.54 618.275 ; + RECT 416.335 37.065 416.535 618.275 ; + LAYER Metal2 SPACING 0.21 ; + RECT 0 0.52 416.64 618.3 ; + RECT 408.3 0 416.64 618.3 ; + RECT 402.89 0 405.99 618.3 ; + RECT 401.36 0 402.11 618.3 ; + RECT 385.82 0 400.58 618.3 ; + RECT 380.41 0 383.51 618.3 ; + RECT 378.88 0 379.63 618.3 ; + RECT 363.34 0 378.1 618.3 ; + RECT 357.93 0 361.03 618.3 ; + RECT 356.4 0 357.15 618.3 ; + RECT 340.86 0 355.62 618.3 ; + RECT 335.45 0 338.55 618.3 ; + RECT 333.92 0 334.67 618.3 ; + RECT 318.38 0 333.14 618.3 ; + RECT 312.97 0 316.07 618.3 ; + RECT 311.44 0 312.19 618.3 ; + RECT 295.9 0 310.66 618.3 ; + RECT 290.49 0 293.59 618.3 ; + RECT 288.96 0 289.71 618.3 ; + RECT 273.42 0 288.18 618.3 ; + RECT 268.01 0 271.11 618.3 ; + RECT 266.48 0 267.23 618.3 ; + RECT 250.94 0 265.7 618.3 ; + RECT 245.53 0 248.63 618.3 ; + RECT 244 0 244.75 618.3 ; + RECT 224.92 0.17 243.22 618.3 ; + RECT 224.93 0 243.22 618.3 ; + RECT 223.4 0 224.15 618.3 ; + RECT 218.3 0 222.11 618.3 ; + RECT 216.26 0 217.01 618.3 ; + RECT 209.63 0 210.89 618.3 ; + RECT 208.1 0 208.34 618.3 ; + RECT 206.57 0 206.81 618.3 ; + RECT 203.51 0 203.75 618.3 ; + RECT 201.98 0 202.22 618.3 ; + RECT 194.32 0 200.69 618.3 ; + RECT 191.77 0 192.03 618.3 ; + RECT 190.25 0 191 618.3 ; + RECT 173.42 0 189.48 618.3 ; + RECT 171.89 0 172.64 618.3 ; + RECT 168.01 0 171.11 618.3 ; + RECT 150.94 0 165.7 618.3 ; + RECT 149.41 0 150.16 618.3 ; + RECT 145.53 0 148.63 618.3 ; + RECT 128.46 0 143.22 618.3 ; + RECT 126.93 0 127.68 618.3 ; + RECT 123.05 0 126.15 618.3 ; + RECT 105.98 0 120.74 618.3 ; + RECT 104.45 0 105.2 618.3 ; + RECT 100.57 0 103.67 618.3 ; + RECT 83.5 0 98.26 618.3 ; + RECT 81.97 0 82.72 618.3 ; + RECT 78.09 0 81.19 618.3 ; + RECT 61.02 0 75.78 618.3 ; + RECT 59.49 0 60.24 618.3 ; + RECT 55.61 0 58.71 618.3 ; + RECT 38.54 0 53.3 618.3 ; + RECT 37.01 0 37.76 618.3 ; + RECT 33.13 0 36.23 618.3 ; + RECT 16.06 0 30.82 618.3 ; + RECT 14.53 0 15.28 618.3 ; + RECT 10.65 0 13.75 618.3 ; + RECT 0 0 8.34 618.3 ; + LAYER Metal3 ; + RECT 0 0 416.64 618.3 ; + LAYER Metal4 SPACING 0.21 ; + RECT 228.01 0 235.09 618.3 ; + RECT 222.86 0 224.68 618.3 ; + RECT 217.71 0 219.53 618.3 ; + RECT 412.64 0 416.64 618.3 ; + RECT 407.02 0 409.31 618.3 ; + RECT 407.02 30.685 416.64 36.805 ; + RECT 401.4 0 403.69 618.3 ; + RECT 395.78 0 398.07 618.3 ; + RECT 395.78 30.685 403.69 36.805 ; + RECT 390.16 0 392.45 618.3 ; + RECT 384.54 0 386.83 618.3 ; + RECT 384.54 30.685 392.45 36.805 ; + RECT 378.92 0 381.21 618.3 ; + RECT 373.3 0 375.59 618.3 ; + RECT 373.3 30.685 381.21 36.805 ; + RECT 367.68 0 369.97 618.3 ; + RECT 362.06 0 364.35 618.3 ; + RECT 362.06 30.685 369.97 36.805 ; + RECT 356.44 0 358.73 618.3 ; + RECT 350.82 0 353.11 618.3 ; + RECT 350.82 30.685 358.73 36.805 ; + RECT 345.2 0 347.49 618.3 ; + RECT 339.58 0 341.87 618.3 ; + RECT 339.58 30.685 347.49 36.805 ; + RECT 333.96 0 336.25 618.3 ; + RECT 328.34 0 330.63 618.3 ; + RECT 328.34 30.685 336.25 36.805 ; + RECT 322.72 0 325.01 618.3 ; + RECT 317.1 0 319.39 618.3 ; + RECT 317.1 30.685 325.01 36.805 ; + RECT 311.48 0 313.77 618.3 ; + RECT 305.86 0 308.15 618.3 ; + RECT 305.86 30.685 313.77 36.805 ; + RECT 300.24 0 302.53 618.3 ; + RECT 80.39 0 82.68 618.3 ; + RECT 80.39 30.685 88.3 36.805 ; + RECT 74.77 0 77.06 618.3 ; + RECT 69.15 0 71.44 618.3 ; + RECT 69.15 30.685 77.06 36.805 ; + RECT 63.53 0 65.82 618.3 ; + RECT 57.91 0 60.2 618.3 ; + RECT 57.91 30.685 65.82 36.805 ; + RECT 52.29 0 54.58 618.3 ; + RECT 46.67 0 48.96 618.3 ; + RECT 46.67 30.685 54.58 36.805 ; + RECT 41.05 0 43.34 618.3 ; + RECT 35.43 0 37.72 618.3 ; + RECT 35.43 30.685 43.34 36.805 ; + RECT 29.81 0 32.1 618.3 ; + RECT 24.19 0 26.48 618.3 ; + RECT 24.19 30.685 32.1 36.805 ; + RECT 18.57 0 20.86 618.3 ; + RECT 12.95 0 15.24 618.3 ; + RECT 12.95 30.685 20.86 36.805 ; + RECT 7.33 0 9.62 618.3 ; + RECT 0 0 4 618.3 ; + RECT 0 30.685 9.62 36.805 ; + RECT 294.62 0 296.91 618.3 ; + RECT 294.62 30.685 302.53 36.805 ; + RECT 289 0 291.29 618.3 ; + RECT 283.38 0 285.67 618.3 ; + RECT 283.38 30.685 291.29 36.805 ; + RECT 277.76 0 280.05 618.3 ; + RECT 272.14 0 274.43 618.3 ; + RECT 272.14 30.685 280.05 36.805 ; + RECT 266.52 0 268.81 618.3 ; + RECT 260.9 0 263.19 618.3 ; + RECT 260.9 30.685 268.81 36.805 ; + RECT 255.28 0 257.57 618.3 ; + RECT 249.66 0 251.95 618.3 ; + RECT 249.66 30.685 257.57 36.805 ; + RECT 244.04 0 246.33 618.3 ; + RECT 238.42 0 240.71 618.3 ; + RECT 238.42 30.685 246.33 36.805 ; + RECT 212.56 0 214.38 618.3 ; + RECT 207.41 0 209.23 618.3 ; + RECT 202.26 0 204.08 618.3 ; + RECT 197.11 0 198.93 618.3 ; + RECT 191.96 0 193.78 618.3 ; + RECT 181.55 0 188.63 618.3 ; + RECT 175.93 0 178.22 618.3 ; + RECT 170.31 0 172.6 618.3 ; + RECT 170.31 30.685 178.22 36.805 ; + RECT 164.69 0 166.98 618.3 ; + RECT 159.07 0 161.36 618.3 ; + RECT 159.07 30.685 166.98 36.805 ; + RECT 153.45 0 155.74 618.3 ; + RECT 147.83 0 150.12 618.3 ; + RECT 147.83 30.685 155.74 36.805 ; + RECT 142.21 0 144.5 618.3 ; + RECT 136.59 0 138.88 618.3 ; + RECT 136.59 30.685 144.5 36.805 ; + RECT 130.97 0 133.26 618.3 ; + RECT 125.35 0 127.64 618.3 ; + RECT 125.35 30.685 133.26 36.805 ; + RECT 119.73 0 122.02 618.3 ; + RECT 114.11 0 116.4 618.3 ; + RECT 114.11 30.685 122.02 36.805 ; + RECT 108.49 0 110.78 618.3 ; + RECT 102.87 0 105.16 618.3 ; + RECT 102.87 30.685 110.78 36.805 ; + RECT 97.25 0 99.54 618.3 ; + RECT 91.63 0 93.92 618.3 ; + RECT 91.63 30.685 99.54 36.805 ; + RECT 86.01 0 88.3 618.3 ; + END +END RM_IHPSG13_1P_4096x16_c3_bm_bist + +END LIBRARY diff --git a/flow/platforms/ihp-sg13g2/lef/RM_IHPSG13_1P_4096x8_c3_bm_bist.lef b/flow/platforms/ihp-sg13g2/lef/RM_IHPSG13_1P_4096x8_c3_bm_bist.lef new file mode 100644 index 0000000000..480ef1d04f --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lef/RM_IHPSG13_1P_4096x8_c3_bm_bist.lef @@ -0,0 +1,1774 @@ +# ------------------------------------------------------ +# +# Copyright 2024 IHP PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# Generated on Fri Jul 19 08:59:31 2024 +# +# ------------------------------------------------------ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +DIVIDERCHAR "/" ; + +MACRO RM_IHPSG13_1P_4096x8_c3_bm_bist + CLASS BLOCK ; + ORIGIN 0 0 ; + FOREIGN RM_IHPSG13_1P_4096x8_c3_bm_bist 0 0 ; + SIZE 236.8 BY 618.3 ; + SYMMETRY X Y R90 ; + PIN A_DIN[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 155.09 0 155.35 0.26 ; + END + END A_DIN[4] + PIN A_DIN[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 81.45 0 81.71 0.26 ; + END + END A_DIN[3] + PIN A_BIST_DIN[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 153.56 0 153.82 0.26 ; + END + END A_BIST_DIN[4] + PIN A_BIST_DIN[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 82.98 0 83.24 0.26 ; + END + END A_BIST_DIN[3] + PIN A_BM[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 158.97 0 159.23 0.26 ; + END + END A_BM[4] + PIN A_BM[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 77.57 0 77.83 0.26 ; + END + END A_BM[3] + PIN A_BIST_BM[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 160.5 0 160.76 0.26 ; + END + END A_BIST_BM[4] + PIN A_BIST_BM[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 76.04 0 76.3 0.26 ; + END + END A_BIST_BM[3] + PIN A_DOUT[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.0345 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 159.835 0 160.095 0.26 ; + END + END A_DOUT[4] + PIN A_DOUT[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.0345 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 76.705 0 76.965 0.26 ; + END + END A_DOUT[3] + PIN VSS! + DIRECTION INOUT ; + USE GROUND ; + NETEXPR "vss VSS!" ; + PORT + LAYER Metal4 ; + RECT 224.11 0 226.92 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 212.87 0 215.68 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 201.63 0 204.44 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 190.39 0 193.2 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 179.15 0 181.96 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 167.91 0 170.72 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 156.67 0 159.48 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 145.43 0 148.24 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 135.02 0 137.83 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 124.72 0 127.53 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 109.27 0 112.08 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 98.97 0 101.78 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 88.56 0 91.37 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 77.32 0 80.13 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 66.08 0 68.89 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 54.84 0 57.65 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 43.6 0 46.41 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 32.36 0 35.17 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 21.12 0 23.93 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 9.88 0 12.69 618.3 ; + END + END VSS! + PIN VDD! + DIRECTION INOUT ; + USE POWER ; + NETEXPR "vdd VDD!" ; + PORT + LAYER Metal4 ; + RECT 229.73 0 232.54 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 218.49 0 221.3 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 207.25 0 210.06 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 196.01 0 198.82 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 184.77 0 187.58 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 173.53 0 176.34 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 162.29 0 165.1 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 151.05 0 153.86 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 129.87 0 132.68 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 119.57 0 122.38 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 114.42 0 117.23 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 104.12 0 106.93 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 82.94 0 85.75 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 71.7 0 74.51 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 60.46 0 63.27 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 49.22 0 52.03 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 37.98 0 40.79 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 26.74 0 29.55 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 15.5 0 18.31 30.425 ; + END + PORT + LAYER Metal4 ; + RECT 4.26 0 7.07 30.425 ; + END + END VDD! + PIN VDDARRAY! + DIRECTION INOUT ; + USE POWER ; + NETEXPR "vddarray VDDARRAY!" ; + PORT + LAYER Metal4 ; + RECT 229.73 37.065 232.54 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 218.49 37.065 221.3 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 207.25 37.065 210.06 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 196.01 37.065 198.82 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 184.77 37.065 187.58 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 173.53 37.065 176.34 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 162.29 37.065 165.1 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 151.05 37.065 153.86 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 82.94 37.065 85.75 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 71.7 37.065 74.51 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 60.46 37.065 63.27 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 49.22 37.065 52.03 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 37.98 37.065 40.79 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 26.74 37.065 29.55 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 15.5 37.065 18.31 618.3 ; + END + PORT + LAYER Metal4 ; + RECT 4.26 37.065 7.07 618.3 ; + END + END VDDARRAY! + PIN A_DIN[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 177.57 0 177.83 0.26 ; + END + END A_DIN[5] + PIN A_DIN[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 58.97 0 59.23 0.26 ; + END + END A_DIN[2] + PIN A_BIST_DIN[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 176.04 0 176.3 0.26 ; + END + END A_BIST_DIN[5] + PIN A_BIST_DIN[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 60.5 0 60.76 0.26 ; + END + END A_BIST_DIN[2] + PIN A_BM[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 181.45 0 181.71 0.26 ; + END + END A_BM[5] + PIN A_BM[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 55.09 0 55.35 0.26 ; + END + END A_BM[2] + PIN A_BIST_BM[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 182.98 0 183.24 0.26 ; + END + END A_BIST_BM[5] + PIN A_BIST_BM[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 53.56 0 53.82 0.26 ; + END + END A_BIST_BM[2] + PIN A_DOUT[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.0345 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 182.315 0 182.575 0.26 ; + END + END A_DOUT[5] + PIN A_DOUT[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.0345 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 54.225 0 54.485 0.26 ; + END + END A_DOUT[2] + PIN A_DIN[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 200.05 0 200.31 0.26 ; + END + END A_DIN[6] + PIN A_DIN[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 36.49 0 36.75 0.26 ; + END + END A_DIN[1] + PIN A_BIST_DIN[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 198.52 0 198.78 0.26 ; + END + END A_BIST_DIN[6] + PIN A_BIST_DIN[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 38.02 0 38.28 0.26 ; + END + END A_BIST_DIN[1] + PIN A_BM[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 203.93 0 204.19 0.26 ; + END + END A_BM[6] + PIN A_BM[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 32.61 0 32.87 0.26 ; + END + END A_BM[1] + PIN A_BIST_BM[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 205.46 0 205.72 0.26 ; + END + END A_BIST_BM[6] + PIN A_BIST_BM[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 31.08 0 31.34 0.26 ; + END + END A_BIST_BM[1] + PIN A_DOUT[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.0345 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 204.795 0 205.055 0.26 ; + END + END A_DOUT[6] + PIN A_DOUT[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.0345 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 31.745 0 32.005 0.26 ; + END + END A_DOUT[1] + PIN A_DIN[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 222.53 0 222.79 0.26 ; + END + END A_DIN[7] + PIN A_DIN[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 14.01 0 14.27 0.26 ; + END + END A_DIN[0] + PIN A_BIST_DIN[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 221 0 221.26 0.26 ; + END + END A_BIST_DIN[7] + PIN A_BIST_DIN[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 15.54 0 15.8 0.26 ; + END + END A_BIST_DIN[0] + PIN A_BM[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 226.41 0 226.67 0.26 ; + END + END A_BM[7] + PIN A_BM[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 10.13 0 10.39 0.26 ; + END + END A_BM[0] + PIN A_BIST_BM[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 227.94 0 228.2 0.26 ; + END + END A_BIST_BM[7] + PIN A_BIST_BM[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 8.6 0 8.86 0.26 ; + END + END A_BIST_BM[0] + PIN A_DOUT[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.0345 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 227.275 0 227.535 0.26 ; + END + END A_DOUT[7] + PIN A_DOUT[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 2.0345 LAYER Metal2 ; + ANTENNADIFFAREA 0.988 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 9.265 0 9.525 0.26 ; + END + END A_DOUT[0] + PIN A_ADDR[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 6.7171 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 34.349515 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 114.6 0 114.86 0.26 ; + END + END A_ADDR[0] + PIN A_BIST_ADDR[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 7.5127 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 38.31068 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 119.19 0 119.45 0.26 ; + END + END A_BIST_ADDR[0] + PIN A_ADDR[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 5.59 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 28.783172 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 114.09 0 114.35 0.26 ; + END + END A_ADDR[1] + PIN A_BIST_ADDR[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 6.3856 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 32.744337 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 118.68 0 118.94 0.26 ; + END + END A_BIST_ADDR[1] + PIN A_ADDR[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 6.4519 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 33.029126 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 99.81 0 100.07 0.26 ; + END + END A_ADDR[2] + PIN A_BIST_ADDR[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 6.1867 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 31.708738 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 101.34 0 101.6 0.26 ; + END + END A_BIST_ADDR[2] + PIN A_ADDR[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 8.4487 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.5246 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 9.415982 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 122.25 0 122.51 0.26 ; + END + END A_ADDR[3] + PIN A_BIST_ADDR[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 8.4487 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.0962 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 7.813791 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 122.76 0 123.02 0.26 ; + END + END A_BIST_ADDR[3] + PIN A_ADDR[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 8.4487 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 3.8367 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 20.927558 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 121.23 0 121.49 0.26 ; + END + END A_ADDR[4] + PIN A_BIST_ADDR[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 8.4487 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 3.5175 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 19.869057 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 121.74 0 122 0.26 ; + END + END A_BIST_ADDR[4] + PIN A_ADDR[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 10.0139 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 50.763754 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 124.8 0 125.06 0.26 ; + END + END A_ADDR[5] + PIN A_BIST_ADDR[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 9.7487 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 49.443366 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 124.29 0 124.55 0.26 ; + END + END A_BIST_ADDR[5] + PIN A_ADDR[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 11.7429 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 59.372168 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 123.78 0 124.04 0.26 ; + END + END A_ADDR[6] + PIN A_BIST_ADDR[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 11.4777 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 58.05178 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 123.27 0 123.53 0.26 ; + END + END A_BIST_ADDR[6] + PIN A_ADDR[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 8.7685 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 44.563107 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 102.36 0 102.62 0.26 ; + END + END A_ADDR[7] + PIN A_BIST_ADDR[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 8.4931 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 43.191934 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 102.87 0 103.13 0.26 ; + END + END A_BIST_ADDR[7] + PIN A_ADDR[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 10.2323 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 51.851133 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 103.38 0 103.64 0.26 ; + END + END A_ADDR[8] + PIN A_BIST_ADDR[8] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 9.9671 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 50.530744 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 103.89 0 104.15 0.26 ; + END + END A_BIST_ADDR[8] + PIN A_ADDR[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 7.9183 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.5897 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 9.740105 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 132.45 0 132.71 0.26 ; + END + END A_ADDR[9] + PIN A_BIST_ADDR[9] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 7.9183 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 1.3755 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal3 ; + ANTENNAMAXAREACAR 9.204381 LAYER Metal3 ; + PORT + LAYER Metal2 ; + RECT 132.96 0 133.22 0.26 ; + END + END A_BIST_ADDR[9] + PIN A_ADDR[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 10.6097 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 53.730147 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 127.35 0 127.61 0.26 ; + END + END A_ADDR[10] + PIN A_BIST_ADDR[10] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 10.3547 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 52.460543 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 127.86 0 128.12 0.26 ; + END + END A_BIST_ADDR[10] + PIN A_ADDR[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 8.6359 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 43.902913 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 125.31 0 125.57 0.26 ; + END + END A_ADDR[11] + PIN A_BIST_ADDR[11] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 8.6359 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 43.902913 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 125.82 0 126.08 0.26 ; + END + END A_BIST_ADDR[11] + PIN A_CLK + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.8707 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 10.220065 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 112.56 0 112.82 0.26 ; + END + END A_CLK + PIN A_REN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.81105 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 9.923077 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 116.13 0 116.39 0.26 ; + END + END A_REN + PIN A_WEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 115.62 0 115.88 0.26 ; + END + END A_WEN + PIN A_MEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.8407 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 5.09186 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 113.07 0 113.33 0.26 ; + END + END A_MEN + PIN A_DLY + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 3.874 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.3367 LAYER Metal2 ; + ANTENNAMAXAREACAR 12.046332 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 134.49 0 134.75 0.26 ; + END + END A_DLY + PIN A_BIST_EN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.8031 LAYER Metal2 ; + ANTENNAPARTIALMETALAREA 72.69295 LAYER Metal3 ; + ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 1.43 LAYER Metal2 ; + ANTENNAGATEAREA 11.44 LAYER Metal3 ; + ANTENNAMAXAREACAR 1.686364 LAYER Metal2 ; + ANTENNAMAXAREACAR 13.29337 LAYER Metal3 ; + ANTENNAMAXCUTCAR 0.151469 LAYER Via2 ; + PORT + LAYER Metal2 ; + RECT 115.11 0 115.37 0.26 ; + END + END A_BIST_EN + PIN A_BIST_CLK + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.9799 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 11.079661 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 111.03 0 111.29 0.26 ; + END + END A_BIST_CLK + PIN A_BIST_REN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 1.9279 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 10.820762 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 117.66 0 117.92 0.26 ; + END + END A_BIST_REN + PIN A_BIST_WEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7211 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.812298 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 117.15 0 117.41 0.26 ; + END + END A_BIST_WEN + PIN A_BIST_MEN + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAPARTIALMETALAREA 0.7137 LAYER Metal2 ; + ANTENNAMODEL OXIDE1 ; + ANTENNAGATEAREA 0.20085 LAYER Metal2 ; + ANTENNAMAXAREACAR 4.775454 LAYER Metal2 ; + PORT + LAYER Metal2 ; + RECT 111.54 0 111.8 0.26 ; + END + END A_BIST_MEN + OBS + LAYER Metal1 ; + RECT 0 0 236.8 618.3 ; + LAYER Metal2 ; + RECT 0.105 37.065 0.305 618.275 ; + RECT 1.1 617.545 1.3 618.275 ; + RECT 1.92 617.545 2.12 618.275 ; + RECT 2.415 617.545 2.615 618.275 ; + RECT 2.915 617.545 3.115 618.275 ; + RECT 3.415 617.545 3.615 618.275 ; + RECT 3.91 617.545 4.11 618.275 ; + RECT 4.73 617.545 4.93 618.275 ; + RECT 5.225 617.545 5.425 618.275 ; + RECT 5.725 617.545 5.925 618.275 ; + RECT 7.225 0.17 7.995 0.43 ; + RECT 7.225 0.17 7.485 11.38 ; + RECT 7.735 0.17 7.995 17.1 ; + RECT 6.225 617.545 6.425 618.275 ; + RECT 6.72 617.545 6.92 618.275 ; + RECT 7.54 617.545 7.74 618.275 ; + RECT 8.035 617.545 8.235 618.275 ; + RECT 8.535 617.545 8.735 618.275 ; + RECT 8.6 0.52 8.86 2.255 ; + RECT 9.035 617.545 9.235 618.275 ; + RECT 9.265 0.52 9.525 8.085 ; + RECT 9.53 617.545 9.73 618.275 ; + RECT 10.13 0.52 10.39 1.5 ; + RECT 10.35 617.545 10.55 618.275 ; + RECT 10.845 617.545 11.045 618.275 ; + RECT 11.345 617.545 11.545 618.275 ; + RECT 11.845 617.545 12.045 618.275 ; + RECT 12.34 617.545 12.54 618.275 ; + RECT 13.16 617.545 13.36 618.275 ; + RECT 13.655 617.545 13.855 618.275 ; + RECT 14.01 0.52 14.27 2.255 ; + RECT 14.155 617.545 14.355 618.275 ; + RECT 14.655 617.545 14.855 618.275 ; + RECT 15.15 617.545 15.35 618.275 ; + RECT 16.255 0.8 17.025 1.57 ; + RECT 16.255 0.3 16.515 13.03 ; + RECT 16.765 0.3 17.025 13.03 ; + RECT 15.54 0.52 15.8 2.255 ; + RECT 15.97 617.545 16.17 618.275 ; + RECT 16.465 617.545 16.665 618.275 ; + RECT 16.965 617.545 17.165 618.275 ; + RECT 17.465 617.545 17.665 618.275 ; + RECT 17.96 617.545 18.16 618.275 ; + RECT 18.78 617.545 18.98 618.275 ; + RECT 19.975 0.17 20.745 0.43 ; + RECT 19.975 0.17 20.235 13.055 ; + RECT 20.485 0.17 20.745 13.055 ; + RECT 19.275 617.545 19.475 618.275 ; + RECT 19.775 617.545 19.975 618.275 ; + RECT 20.275 617.545 20.475 618.275 ; + RECT 20.77 617.545 20.97 618.275 ; + RECT 21.59 617.545 21.79 618.275 ; + RECT 22.085 617.545 22.285 618.275 ; + RECT 22.585 617.545 22.785 618.275 ; + RECT 23.085 617.545 23.285 618.275 ; + RECT 23.58 617.545 23.78 618.275 ; + RECT 24.4 617.545 24.6 618.275 ; + RECT 24.895 617.545 25.095 618.275 ; + RECT 25.395 617.545 25.595 618.275 ; + RECT 25.895 617.545 26.095 618.275 ; + RECT 26.39 617.545 26.59 618.275 ; + RECT 27.21 617.545 27.41 618.275 ; + RECT 27.705 617.545 27.905 618.275 ; + RECT 28.205 617.545 28.405 618.275 ; + RECT 29.705 0.17 30.475 0.43 ; + RECT 29.705 0.17 29.965 11.38 ; + RECT 30.215 0.17 30.475 17.1 ; + RECT 28.705 617.545 28.905 618.275 ; + RECT 29.2 617.545 29.4 618.275 ; + RECT 30.02 617.545 30.22 618.275 ; + RECT 30.515 617.545 30.715 618.275 ; + RECT 31.015 617.545 31.215 618.275 ; + RECT 31.08 0.52 31.34 2.255 ; + RECT 31.515 617.545 31.715 618.275 ; + RECT 31.745 0.52 32.005 8.085 ; + RECT 32.01 617.545 32.21 618.275 ; + RECT 32.61 0.52 32.87 1.5 ; + RECT 32.83 617.545 33.03 618.275 ; + RECT 33.325 617.545 33.525 618.275 ; + RECT 33.825 617.545 34.025 618.275 ; + RECT 34.325 617.545 34.525 618.275 ; + RECT 34.82 617.545 35.02 618.275 ; + RECT 35.64 617.545 35.84 618.275 ; + RECT 36.135 617.545 36.335 618.275 ; + RECT 36.49 0.52 36.75 2.255 ; + RECT 36.635 617.545 36.835 618.275 ; + RECT 37.135 617.545 37.335 618.275 ; + RECT 37.63 617.545 37.83 618.275 ; + RECT 38.735 0.8 39.505 1.57 ; + RECT 38.735 0.3 38.995 13.03 ; + RECT 39.245 0.3 39.505 13.03 ; + RECT 38.02 0.52 38.28 2.255 ; + RECT 38.45 617.545 38.65 618.275 ; + RECT 38.945 617.545 39.145 618.275 ; + RECT 39.445 617.545 39.645 618.275 ; + RECT 39.945 617.545 40.145 618.275 ; + RECT 40.44 617.545 40.64 618.275 ; + RECT 41.26 617.545 41.46 618.275 ; + RECT 42.455 0.17 43.225 0.43 ; + RECT 42.455 0.17 42.715 13.055 ; + RECT 42.965 0.17 43.225 13.055 ; + RECT 41.755 617.545 41.955 618.275 ; + RECT 42.255 617.545 42.455 618.275 ; + RECT 42.755 617.545 42.955 618.275 ; + RECT 43.25 617.545 43.45 618.275 ; + RECT 44.07 617.545 44.27 618.275 ; + RECT 44.565 617.545 44.765 618.275 ; + RECT 45.065 617.545 45.265 618.275 ; + RECT 45.565 617.545 45.765 618.275 ; + RECT 46.06 617.545 46.26 618.275 ; + RECT 46.88 617.545 47.08 618.275 ; + RECT 47.375 617.545 47.575 618.275 ; + RECT 47.875 617.545 48.075 618.275 ; + RECT 48.375 617.545 48.575 618.275 ; + RECT 48.87 617.545 49.07 618.275 ; + RECT 49.69 617.545 49.89 618.275 ; + RECT 50.185 617.545 50.385 618.275 ; + RECT 50.685 617.545 50.885 618.275 ; + RECT 52.185 0.17 52.955 0.43 ; + RECT 52.185 0.17 52.445 11.38 ; + RECT 52.695 0.17 52.955 17.1 ; + RECT 51.185 617.545 51.385 618.275 ; + RECT 51.68 617.545 51.88 618.275 ; + RECT 52.5 617.545 52.7 618.275 ; + RECT 52.995 617.545 53.195 618.275 ; + RECT 53.495 617.545 53.695 618.275 ; + RECT 53.56 0.52 53.82 2.255 ; + RECT 53.995 617.545 54.195 618.275 ; + RECT 54.225 0.52 54.485 8.085 ; + RECT 54.49 617.545 54.69 618.275 ; + RECT 55.09 0.52 55.35 1.5 ; + RECT 55.31 617.545 55.51 618.275 ; + RECT 55.805 617.545 56.005 618.275 ; + RECT 56.305 617.545 56.505 618.275 ; + RECT 56.805 617.545 57.005 618.275 ; + RECT 57.3 617.545 57.5 618.275 ; + RECT 58.12 617.545 58.32 618.275 ; + RECT 58.615 617.545 58.815 618.275 ; + RECT 58.97 0.52 59.23 2.255 ; + RECT 59.115 617.545 59.315 618.275 ; + RECT 59.615 617.545 59.815 618.275 ; + RECT 60.11 617.545 60.31 618.275 ; + RECT 61.215 0.8 61.985 1.57 ; + RECT 61.215 0.3 61.475 13.03 ; + RECT 61.725 0.3 61.985 13.03 ; + RECT 60.5 0.52 60.76 2.255 ; + RECT 60.93 617.545 61.13 618.275 ; + RECT 61.425 617.545 61.625 618.275 ; + RECT 61.925 617.545 62.125 618.275 ; + RECT 62.425 617.545 62.625 618.275 ; + RECT 62.92 617.545 63.12 618.275 ; + RECT 63.74 617.545 63.94 618.275 ; + RECT 64.935 0.17 65.705 0.43 ; + RECT 64.935 0.17 65.195 13.055 ; + RECT 65.445 0.17 65.705 13.055 ; + RECT 64.235 617.545 64.435 618.275 ; + RECT 64.735 617.545 64.935 618.275 ; + RECT 65.235 617.545 65.435 618.275 ; + RECT 65.73 617.545 65.93 618.275 ; + RECT 66.55 617.545 66.75 618.275 ; + RECT 67.045 617.545 67.245 618.275 ; + RECT 67.545 617.545 67.745 618.275 ; + RECT 68.045 617.545 68.245 618.275 ; + RECT 68.54 617.545 68.74 618.275 ; + RECT 69.36 617.545 69.56 618.275 ; + RECT 69.855 617.545 70.055 618.275 ; + RECT 70.355 617.545 70.555 618.275 ; + RECT 70.855 617.545 71.055 618.275 ; + RECT 71.35 617.545 71.55 618.275 ; + RECT 72.17 617.545 72.37 618.275 ; + RECT 72.665 617.545 72.865 618.275 ; + RECT 73.165 617.545 73.365 618.275 ; + RECT 74.665 0.17 75.435 0.43 ; + RECT 74.665 0.17 74.925 11.38 ; + RECT 75.175 0.17 75.435 17.1 ; + RECT 73.665 617.545 73.865 618.275 ; + RECT 74.16 617.545 74.36 618.275 ; + RECT 74.98 617.545 75.18 618.275 ; + RECT 75.475 617.545 75.675 618.275 ; + RECT 75.975 617.545 76.175 618.275 ; + RECT 76.04 0.52 76.3 2.255 ; + RECT 76.475 617.545 76.675 618.275 ; + RECT 76.705 0.52 76.965 8.085 ; + RECT 76.97 617.545 77.17 618.275 ; + RECT 77.57 0.52 77.83 1.5 ; + RECT 77.79 617.545 77.99 618.275 ; + RECT 78.285 617.545 78.485 618.275 ; + RECT 78.785 617.545 78.985 618.275 ; + RECT 79.285 617.545 79.485 618.275 ; + RECT 79.78 617.545 79.98 618.275 ; + RECT 80.6 617.545 80.8 618.275 ; + RECT 81.095 617.545 81.295 618.275 ; + RECT 81.45 0.52 81.71 2.255 ; + RECT 81.595 617.545 81.795 618.275 ; + RECT 82.095 617.545 82.295 618.275 ; + RECT 82.59 617.545 82.79 618.275 ; + RECT 83.695 0.8 84.465 1.57 ; + RECT 83.695 0.3 83.955 13.03 ; + RECT 84.205 0.3 84.465 13.03 ; + RECT 82.98 0.52 83.24 2.255 ; + RECT 83.41 617.545 83.61 618.275 ; + RECT 83.905 617.545 84.105 618.275 ; + RECT 84.405 617.545 84.605 618.275 ; + RECT 84.905 617.545 85.105 618.275 ; + RECT 85.4 617.545 85.6 618.275 ; + RECT 86.22 617.545 86.42 618.275 ; + RECT 87.415 0.17 88.185 0.43 ; + RECT 87.415 0.17 87.675 13.055 ; + RECT 87.925 0.17 88.185 13.055 ; + RECT 86.715 617.545 86.915 618.275 ; + RECT 87.215 617.545 87.415 618.275 ; + RECT 87.715 617.545 87.915 618.275 ; + RECT 88.21 617.545 88.41 618.275 ; + RECT 89.03 617.545 89.23 618.275 ; + RECT 89.525 617.545 89.725 618.275 ; + RECT 90.025 617.545 90.225 618.275 ; + RECT 90.525 617.545 90.725 618.275 ; + RECT 96.595 0.17 97.365 0.43 ; + RECT 96.595 0.17 96.855 36.945 ; + RECT 97.105 0.17 97.365 36.945 ; + RECT 91.02 617.545 91.22 618.275 ; + RECT 91.84 617.545 92.04 618.275 ; + RECT 99.3 0 99.56 4.94 ; + RECT 99.3 4.68 100.07 4.94 ; + RECT 99.81 4.68 100.07 12.9 ; + RECT 99.81 0.52 100.07 1.78 ; + RECT 99.81 1.52 100.58 1.78 ; + RECT 100.32 1.52 100.58 12.9 ; + RECT 92.835 617.545 93.035 618.275 ; + RECT 100.32 0.59 101.09 1.27 ; + RECT 100.83 0.59 101.09 7.965 ; + RECT 97.615 0.3 97.875 37.365 ; + RECT 98.125 0.3 98.385 37.365 ; + RECT 101.34 0.52 101.6 12.9 ; + RECT 101.85 0 102.11 12.9 ; + RECT 102.36 0.52 102.62 12.9 ; + RECT 102.87 0.52 103.13 12.9 ; + RECT 103.38 0.52 103.64 12.9 ; + RECT 106.44 0.17 107.21 0.43 ; + RECT 106.44 0.17 106.7 2.085 ; + RECT 106.95 0.17 107.21 9 ; + RECT 103.89 0.52 104.15 12.9 ; + RECT 104.4 0 104.66 8.565 ; + RECT 104.91 0 105.17 8.055 ; + RECT 111.03 0.52 111.29 6.59 ; + RECT 112.56 0.52 112.82 6.305 ; + RECT 112.56 6.045 113.53 6.305 ; + RECT 111.54 0.52 111.8 2.23 ; + RECT 113.07 0.52 113.33 2.955 ; + RECT 114.09 0.52 114.35 12.9 ; + RECT 114.6 0.52 114.86 12.9 ; + RECT 116.13 0.52 116.39 6.29 ; + RECT 115.62 6.045 116.39 6.29 ; + RECT 115.11 0.52 115.37 6.745 ; + RECT 117.66 0.52 117.92 6.59 ; + RECT 117.015 6.33 117.92 6.59 ; + RECT 115.62 0.52 115.88 2.955 ; + RECT 117.15 0.52 117.41 2.67 ; + RECT 118.68 0.52 118.94 12.9 ; + RECT 119.19 0.52 119.45 12.9 ; + RECT 120.72 0.575 120.98 7.965 ; + RECT 121.23 0.52 121.49 12.9 ; + RECT 121.74 0.52 122 12.9 ; + RECT 122.25 0.52 122.51 12.9 ; + RECT 122.76 0.52 123.02 12.9 ; + RECT 123.27 0.52 123.53 12.9 ; + RECT 123.78 0.52 124.04 12.9 ; + RECT 124.29 0.52 124.55 12.9 ; + RECT 124.8 0.52 125.06 12.9 ; + RECT 126.33 0.59 127.1 1.27 ; + RECT 126.33 0.59 126.59 8.83 ; + RECT 125.31 0.52 125.57 12.9 ; + RECT 125.82 0.52 126.08 12.9 ; + RECT 127.35 0.52 127.61 12.9 ; + RECT 127.86 0.52 128.12 12.9 ; + RECT 135 0.17 135.77 0.43 ; + RECT 135 0.17 135.26 13.845 ; + RECT 135.51 0.17 135.77 13.845 ; + RECT 137.04 0.17 137.81 0.43 ; + RECT 137.04 0.17 137.3 2.11 ; + RECT 137.55 0.17 137.81 2.11 ; + RECT 132.45 0.52 132.71 3.61 ; + RECT 132.96 0.52 133.22 4.12 ; + RECT 139.435 0.17 140.205 0.43 ; + RECT 139.435 0.17 139.695 36.945 ; + RECT 139.945 0.17 140.205 36.945 ; + RECT 134.49 0.52 134.75 15.16 ; + RECT 138.415 0.3 138.675 37.365 ; + RECT 138.925 0.3 139.185 37.365 ; + RECT 143.765 617.545 143.965 618.275 ; + RECT 144.76 617.545 144.96 618.275 ; + RECT 145.58 617.545 145.78 618.275 ; + RECT 146.075 617.545 146.275 618.275 ; + RECT 146.575 617.545 146.775 618.275 ; + RECT 147.075 617.545 147.275 618.275 ; + RECT 148.615 0.17 149.385 0.43 ; + RECT 148.615 0.17 148.875 13.055 ; + RECT 149.125 0.17 149.385 13.055 ; + RECT 147.57 617.545 147.77 618.275 ; + RECT 148.39 617.545 148.59 618.275 ; + RECT 148.885 617.545 149.085 618.275 ; + RECT 149.385 617.545 149.585 618.275 ; + RECT 149.885 617.545 150.085 618.275 ; + RECT 150.38 617.545 150.58 618.275 ; + RECT 151.2 617.545 151.4 618.275 ; + RECT 152.335 0.8 153.105 1.57 ; + RECT 152.335 0.3 152.595 13.03 ; + RECT 152.845 0.3 153.105 13.03 ; + RECT 151.695 617.545 151.895 618.275 ; + RECT 152.195 617.545 152.395 618.275 ; + RECT 152.695 617.545 152.895 618.275 ; + RECT 153.19 617.545 153.39 618.275 ; + RECT 153.56 0.52 153.82 2.255 ; + RECT 154.01 617.545 154.21 618.275 ; + RECT 154.505 617.545 154.705 618.275 ; + RECT 155.005 617.545 155.205 618.275 ; + RECT 155.09 0.52 155.35 2.255 ; + RECT 155.505 617.545 155.705 618.275 ; + RECT 156 617.545 156.2 618.275 ; + RECT 156.82 617.545 157.02 618.275 ; + RECT 157.315 617.545 157.515 618.275 ; + RECT 157.815 617.545 158.015 618.275 ; + RECT 158.315 617.545 158.515 618.275 ; + RECT 158.81 617.545 159.01 618.275 ; + RECT 158.97 0.52 159.23 1.5 ; + RECT 159.63 617.545 159.83 618.275 ; + RECT 159.835 0.52 160.095 8.085 ; + RECT 160.125 617.545 160.325 618.275 ; + RECT 160.5 0.52 160.76 2.255 ; + RECT 161.365 0.17 162.135 0.43 ; + RECT 161.875 0.17 162.135 11.38 ; + RECT 161.365 0.17 161.625 17.1 ; + RECT 160.625 617.545 160.825 618.275 ; + RECT 161.125 617.545 161.325 618.275 ; + RECT 161.62 617.545 161.82 618.275 ; + RECT 162.44 617.545 162.64 618.275 ; + RECT 162.935 617.545 163.135 618.275 ; + RECT 163.435 617.545 163.635 618.275 ; + RECT 163.935 617.545 164.135 618.275 ; + RECT 164.43 617.545 164.63 618.275 ; + RECT 165.25 617.545 165.45 618.275 ; + RECT 165.745 617.545 165.945 618.275 ; + RECT 166.245 617.545 166.445 618.275 ; + RECT 166.745 617.545 166.945 618.275 ; + RECT 167.24 617.545 167.44 618.275 ; + RECT 168.06 617.545 168.26 618.275 ; + RECT 168.555 617.545 168.755 618.275 ; + RECT 169.055 617.545 169.255 618.275 ; + RECT 169.555 617.545 169.755 618.275 ; + RECT 171.095 0.17 171.865 0.43 ; + RECT 171.095 0.17 171.355 13.055 ; + RECT 171.605 0.17 171.865 13.055 ; + RECT 170.05 617.545 170.25 618.275 ; + RECT 170.87 617.545 171.07 618.275 ; + RECT 171.365 617.545 171.565 618.275 ; + RECT 171.865 617.545 172.065 618.275 ; + RECT 172.365 617.545 172.565 618.275 ; + RECT 172.86 617.545 173.06 618.275 ; + RECT 173.68 617.545 173.88 618.275 ; + RECT 174.815 0.8 175.585 1.57 ; + RECT 174.815 0.3 175.075 13.03 ; + RECT 175.325 0.3 175.585 13.03 ; + RECT 174.175 617.545 174.375 618.275 ; + RECT 174.675 617.545 174.875 618.275 ; + RECT 175.175 617.545 175.375 618.275 ; + RECT 175.67 617.545 175.87 618.275 ; + RECT 176.04 0.52 176.3 2.255 ; + RECT 176.49 617.545 176.69 618.275 ; + RECT 176.985 617.545 177.185 618.275 ; + RECT 177.485 617.545 177.685 618.275 ; + RECT 177.57 0.52 177.83 2.255 ; + RECT 177.985 617.545 178.185 618.275 ; + RECT 178.48 617.545 178.68 618.275 ; + RECT 179.3 617.545 179.5 618.275 ; + RECT 179.795 617.545 179.995 618.275 ; + RECT 180.295 617.545 180.495 618.275 ; + RECT 180.795 617.545 180.995 618.275 ; + RECT 181.29 617.545 181.49 618.275 ; + RECT 181.45 0.52 181.71 1.5 ; + RECT 182.11 617.545 182.31 618.275 ; + RECT 182.315 0.52 182.575 8.085 ; + RECT 182.605 617.545 182.805 618.275 ; + RECT 182.98 0.52 183.24 2.255 ; + RECT 183.845 0.17 184.615 0.43 ; + RECT 184.355 0.17 184.615 11.38 ; + RECT 183.845 0.17 184.105 17.1 ; + RECT 183.105 617.545 183.305 618.275 ; + RECT 183.605 617.545 183.805 618.275 ; + RECT 184.1 617.545 184.3 618.275 ; + RECT 184.92 617.545 185.12 618.275 ; + RECT 185.415 617.545 185.615 618.275 ; + RECT 185.915 617.545 186.115 618.275 ; + RECT 186.415 617.545 186.615 618.275 ; + RECT 186.91 617.545 187.11 618.275 ; + RECT 187.73 617.545 187.93 618.275 ; + RECT 188.225 617.545 188.425 618.275 ; + RECT 188.725 617.545 188.925 618.275 ; + RECT 189.225 617.545 189.425 618.275 ; + RECT 189.72 617.545 189.92 618.275 ; + RECT 190.54 617.545 190.74 618.275 ; + RECT 191.035 617.545 191.235 618.275 ; + RECT 191.535 617.545 191.735 618.275 ; + RECT 192.035 617.545 192.235 618.275 ; + RECT 193.575 0.17 194.345 0.43 ; + RECT 193.575 0.17 193.835 13.055 ; + RECT 194.085 0.17 194.345 13.055 ; + RECT 192.53 617.545 192.73 618.275 ; + RECT 193.35 617.545 193.55 618.275 ; + RECT 193.845 617.545 194.045 618.275 ; + RECT 194.345 617.545 194.545 618.275 ; + RECT 194.845 617.545 195.045 618.275 ; + RECT 195.34 617.545 195.54 618.275 ; + RECT 196.16 617.545 196.36 618.275 ; + RECT 197.295 0.8 198.065 1.57 ; + RECT 197.295 0.3 197.555 13.03 ; + RECT 197.805 0.3 198.065 13.03 ; + RECT 196.655 617.545 196.855 618.275 ; + RECT 197.155 617.545 197.355 618.275 ; + RECT 197.655 617.545 197.855 618.275 ; + RECT 198.15 617.545 198.35 618.275 ; + RECT 198.52 0.52 198.78 2.255 ; + RECT 198.97 617.545 199.17 618.275 ; + RECT 199.465 617.545 199.665 618.275 ; + RECT 199.965 617.545 200.165 618.275 ; + RECT 200.05 0.52 200.31 2.255 ; + RECT 200.465 617.545 200.665 618.275 ; + RECT 200.96 617.545 201.16 618.275 ; + RECT 201.78 617.545 201.98 618.275 ; + RECT 202.275 617.545 202.475 618.275 ; + RECT 202.775 617.545 202.975 618.275 ; + RECT 203.275 617.545 203.475 618.275 ; + RECT 203.77 617.545 203.97 618.275 ; + RECT 203.93 0.52 204.19 1.5 ; + RECT 204.59 617.545 204.79 618.275 ; + RECT 204.795 0.52 205.055 8.085 ; + RECT 205.085 617.545 205.285 618.275 ; + RECT 205.46 0.52 205.72 2.255 ; + RECT 206.325 0.17 207.095 0.43 ; + RECT 206.835 0.17 207.095 11.38 ; + RECT 206.325 0.17 206.585 17.1 ; + RECT 205.585 617.545 205.785 618.275 ; + RECT 206.085 617.545 206.285 618.275 ; + RECT 206.58 617.545 206.78 618.275 ; + RECT 207.4 617.545 207.6 618.275 ; + RECT 207.895 617.545 208.095 618.275 ; + RECT 208.395 617.545 208.595 618.275 ; + RECT 208.895 617.545 209.095 618.275 ; + RECT 209.39 617.545 209.59 618.275 ; + RECT 210.21 617.545 210.41 618.275 ; + RECT 210.705 617.545 210.905 618.275 ; + RECT 211.205 617.545 211.405 618.275 ; + RECT 211.705 617.545 211.905 618.275 ; + RECT 212.2 617.545 212.4 618.275 ; + RECT 213.02 617.545 213.22 618.275 ; + RECT 213.515 617.545 213.715 618.275 ; + RECT 214.015 617.545 214.215 618.275 ; + RECT 214.515 617.545 214.715 618.275 ; + RECT 216.055 0.17 216.825 0.43 ; + RECT 216.055 0.17 216.315 13.055 ; + RECT 216.565 0.17 216.825 13.055 ; + RECT 215.01 617.545 215.21 618.275 ; + RECT 215.83 617.545 216.03 618.275 ; + RECT 216.325 617.545 216.525 618.275 ; + RECT 216.825 617.545 217.025 618.275 ; + RECT 217.325 617.545 217.525 618.275 ; + RECT 217.82 617.545 218.02 618.275 ; + RECT 218.64 617.545 218.84 618.275 ; + RECT 219.775 0.8 220.545 1.57 ; + RECT 219.775 0.3 220.035 13.03 ; + RECT 220.285 0.3 220.545 13.03 ; + RECT 219.135 617.545 219.335 618.275 ; + RECT 219.635 617.545 219.835 618.275 ; + RECT 220.135 617.545 220.335 618.275 ; + RECT 220.63 617.545 220.83 618.275 ; + RECT 221 0.52 221.26 2.255 ; + RECT 221.45 617.545 221.65 618.275 ; + RECT 221.945 617.545 222.145 618.275 ; + RECT 222.445 617.545 222.645 618.275 ; + RECT 222.53 0.52 222.79 2.255 ; + RECT 222.945 617.545 223.145 618.275 ; + RECT 223.44 617.545 223.64 618.275 ; + RECT 224.26 617.545 224.46 618.275 ; + RECT 224.755 617.545 224.955 618.275 ; + RECT 225.255 617.545 225.455 618.275 ; + RECT 225.755 617.545 225.955 618.275 ; + RECT 226.25 617.545 226.45 618.275 ; + RECT 226.41 0.52 226.67 1.5 ; + RECT 227.07 617.545 227.27 618.275 ; + RECT 227.275 0.52 227.535 8.085 ; + RECT 227.565 617.545 227.765 618.275 ; + RECT 227.94 0.52 228.2 2.255 ; + RECT 228.805 0.17 229.575 0.43 ; + RECT 229.315 0.17 229.575 11.38 ; + RECT 228.805 0.17 229.065 17.1 ; + RECT 228.065 617.545 228.265 618.275 ; + RECT 228.565 617.545 228.765 618.275 ; + RECT 229.06 617.545 229.26 618.275 ; + RECT 229.88 617.545 230.08 618.275 ; + RECT 230.375 617.545 230.575 618.275 ; + RECT 230.875 617.545 231.075 618.275 ; + RECT 231.375 617.545 231.575 618.275 ; + RECT 231.87 617.545 232.07 618.275 ; + RECT 232.69 617.545 232.89 618.275 ; + RECT 233.185 617.545 233.385 618.275 ; + RECT 233.685 617.545 233.885 618.275 ; + RECT 234.185 617.545 234.385 618.275 ; + RECT 234.68 617.545 234.88 618.275 ; + RECT 235.5 617.545 235.7 618.275 ; + RECT 236.495 37.065 236.695 618.275 ; + LAYER Metal2 SPACING 0.21 ; + RECT 0 0.52 236.8 618.3 ; + RECT 228.46 0 236.8 618.3 ; + RECT 223.05 0 226.15 618.3 ; + RECT 221.52 0 222.27 618.3 ; + RECT 205.98 0 220.74 618.3 ; + RECT 200.57 0 203.67 618.3 ; + RECT 199.04 0 199.79 618.3 ; + RECT 183.5 0 198.26 618.3 ; + RECT 178.09 0 181.19 618.3 ; + RECT 176.56 0 177.31 618.3 ; + RECT 161.02 0 175.78 618.3 ; + RECT 155.61 0 158.71 618.3 ; + RECT 154.08 0 154.83 618.3 ; + RECT 135 0.17 153.3 618.3 ; + RECT 135.01 0 153.3 618.3 ; + RECT 133.48 0 134.23 618.3 ; + RECT 128.38 0 132.19 618.3 ; + RECT 126.34 0 127.09 618.3 ; + RECT 119.71 0 120.97 618.3 ; + RECT 118.18 0 118.42 618.3 ; + RECT 116.65 0 116.89 618.3 ; + RECT 113.59 0 113.83 618.3 ; + RECT 112.06 0 112.3 618.3 ; + RECT 104.4 0 110.77 618.3 ; + RECT 101.85 0 102.11 618.3 ; + RECT 100.33 0 101.08 618.3 ; + RECT 83.5 0 99.56 618.3 ; + RECT 81.97 0 82.72 618.3 ; + RECT 78.09 0 81.19 618.3 ; + RECT 61.02 0 75.78 618.3 ; + RECT 59.49 0 60.24 618.3 ; + RECT 55.61 0 58.71 618.3 ; + RECT 38.54 0 53.3 618.3 ; + RECT 37.01 0 37.76 618.3 ; + RECT 33.13 0 36.23 618.3 ; + RECT 16.06 0 30.82 618.3 ; + RECT 14.53 0 15.28 618.3 ; + RECT 10.65 0 13.75 618.3 ; + RECT 0 0 8.34 618.3 ; + LAYER Metal3 ; + RECT 0 0 236.8 618.3 ; + LAYER Metal4 SPACING 0.21 ; + RECT 138.09 0 145.17 618.3 ; + RECT 132.94 0 134.76 618.3 ; + RECT 127.79 0 129.61 618.3 ; + RECT 232.8 0 236.8 618.3 ; + RECT 227.18 0 229.47 618.3 ; + RECT 227.18 30.685 236.8 36.805 ; + RECT 221.56 0 223.85 618.3 ; + RECT 215.94 0 218.23 618.3 ; + RECT 215.94 30.685 223.85 36.805 ; + RECT 210.32 0 212.61 618.3 ; + RECT 204.7 0 206.99 618.3 ; + RECT 204.7 30.685 212.61 36.805 ; + RECT 199.08 0 201.37 618.3 ; + RECT 193.46 0 195.75 618.3 ; + RECT 193.46 30.685 201.37 36.805 ; + RECT 187.84 0 190.13 618.3 ; + RECT 182.22 0 184.51 618.3 ; + RECT 182.22 30.685 190.13 36.805 ; + RECT 24.19 30.685 32.1 36.805 ; + RECT 18.57 0 20.86 618.3 ; + RECT 12.95 0 15.24 618.3 ; + RECT 12.95 30.685 20.86 36.805 ; + RECT 7.33 0 9.62 618.3 ; + RECT 0 0 4 618.3 ; + RECT 0 30.685 9.62 36.805 ; + RECT 176.6 0 178.89 618.3 ; + RECT 170.98 0 173.27 618.3 ; + RECT 170.98 30.685 178.89 36.805 ; + RECT 165.36 0 167.65 618.3 ; + RECT 159.74 0 162.03 618.3 ; + RECT 159.74 30.685 167.65 36.805 ; + RECT 154.12 0 156.41 618.3 ; + RECT 148.5 0 150.79 618.3 ; + RECT 148.5 30.685 156.41 36.805 ; + RECT 122.64 0 124.46 618.3 ; + RECT 117.49 0 119.31 618.3 ; + RECT 112.34 0 114.16 618.3 ; + RECT 107.19 0 109.01 618.3 ; + RECT 102.04 0 103.86 618.3 ; + RECT 91.63 0 98.71 618.3 ; + RECT 86.01 0 88.3 618.3 ; + RECT 80.39 0 82.68 618.3 ; + RECT 80.39 30.685 88.3 36.805 ; + RECT 74.77 0 77.06 618.3 ; + RECT 69.15 0 71.44 618.3 ; + RECT 69.15 30.685 77.06 36.805 ; + RECT 63.53 0 65.82 618.3 ; + RECT 57.91 0 60.2 618.3 ; + RECT 57.91 30.685 65.82 36.805 ; + RECT 52.29 0 54.58 618.3 ; + RECT 46.67 0 48.96 618.3 ; + RECT 46.67 30.685 54.58 36.805 ; + RECT 41.05 0 43.34 618.3 ; + RECT 35.43 0 37.72 618.3 ; + RECT 35.43 30.685 43.34 36.805 ; + RECT 29.81 0 32.1 618.3 ; + RECT 24.19 0 26.48 618.3 ; + END +END RM_IHPSG13_1P_4096x8_c3_bm_bist + +END LIBRARY diff --git a/flow/platforms/ihp-sg13g2/lef/sg13g2_stdcell.lef b/flow/platforms/ihp-sg13g2/lef/sg13g2_stdcell.lef index 01c62c6e04..cf28f6ae50 100644 --- a/flow/platforms/ihp-sg13g2/lef/sg13g2_stdcell.lef +++ b/flow/platforms/ihp-sg13g2/lef/sg13g2_stdcell.lef @@ -4524,7 +4524,7 @@ MACRO sg13g2_nand2b_1 SITE CoreSite ; PIN Y DIRECTION OUTPUT ; - USE ANALOG ; + USE SIGNAL ; ANTENNADIFFAREA 0.6772 LAYER Metal1 ; PORT LAYER Metal1 ; @@ -4536,7 +4536,7 @@ MACRO sg13g2_nand2b_1 END Y PIN B DIRECTION INPUT ; - USE ANALOG ; + USE SIGNAL ; ANTENNAMODEL OXIDE1 ; ANTENNAGATEAREA 0.2418 LAYER Metal1 ; PORT @@ -4546,7 +4546,7 @@ MACRO sg13g2_nand2b_1 END B PIN A_N DIRECTION INPUT ; - USE ANALOG ; + USE SIGNAL ; ANTENNAMODEL OXIDE1 ; ANTENNAGATEAREA 0.1807 LAYER Metal1 ; PORT @@ -5692,7 +5692,7 @@ MACRO sg13g2_or2_1 END X PIN B DIRECTION INPUT ; - USE ANALOG ; + USE SIGNAL ; ANTENNAMODEL OXIDE1 ; ANTENNAGATEAREA 0.1807 LAYER Metal1 ; PORT @@ -5703,7 +5703,7 @@ MACRO sg13g2_or2_1 END B PIN A DIRECTION INPUT ; - USE ANALOG ; + USE SIGNAL ; ANTENNAMODEL OXIDE1 ; ANTENNAGATEAREA 0.1807 LAYER Metal1 ; PORT @@ -5769,7 +5769,7 @@ MACRO sg13g2_or2_2 END X PIN B DIRECTION INPUT ; - USE ANALOG ; + USE SIGNAL ; ANTENNAMODEL OXIDE1 ; ANTENNAGATEAREA 0.1807 LAYER Metal1 ; PORT @@ -5780,7 +5780,7 @@ MACRO sg13g2_or2_2 END B PIN A DIRECTION INPUT ; - USE ANALOG ; + USE SIGNAL ; ANTENNAMODEL OXIDE1 ; ANTENNAGATEAREA 0.1807 LAYER Metal1 ; PORT diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_1024x16_c2_bm_bist_fast_1p32V_m55C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_1024x16_c2_bm_bist_fast_1p32V_m55C.lib new file mode 100644 index 0000000000..dbe648f098 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_1024x16_c2_bm_bist_fast_1p32V_m55C.lib @@ -0,0 +1,1525 @@ +/* ------------------------------------------------------*/ +/**/ +/* Copyright 2024 IHP PDK Authors*/ +/**/ +/* Licensed under the Apache License, Version 2.0 (the "License");*/ +/* you may not use this file except in compliance with the License.*/ +/* You may obtain a copy of the License at*/ +/* */ +/* https://www.apache.org/licenses/LICENSE-2.0*/ +/* */ +/* Unless required by applicable law or agreed to in writing, software*/ +/* distributed under the License is distributed on an "AS IS" BASIS,*/ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/ +/* See the License for the specific language governing permissions and*/ +/* limitations under the License.*/ +/* */ +/* Generated on Fri Jul 19 08:58:02 2024 */ +/* */ +/* ------------------------------------------------------ */ +library(RM_IHPSG13_1P_1024x16_c2_bm_bist_fast_1p32V_m55C) { + technology (cmos) ; + delay_model : table_lookup ; + define ("add_pg_pin_to_lib", "library", "boolean"); + add_pg_pin_to_lib : true; + voltage_map ( VDD, 1.32); + voltage_map ( VDDARRAY, 1.32); + voltage_map ( VSS, 0.000000 ); + + date : "Fri Jul 19 08:58:00 2024" ; + comment : "IHP Microelectronics GmbH, 2024" ; + revision : 1.0.0 ; + simulation : true ; + nom_process : 1 ; + nom_temperature : -55 ; + nom_voltage : 1.32 ; + + operating_conditions("fast_1p32V_m55C"){ + process : 1 ; + temperature : -55 ; + voltage : 1.32 ; + tree_type : "balanced_tree" ; + } + + default_operating_conditions : fast_1p32V_m55C ; + default_max_transition : 1.0 ; + default_fanout_load : 1.0 ; + default_inout_pin_cap : 0.0 ; + default_input_pin_cap : 0.0 ; + default_output_pin_cap : 0.0 ; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + + slew_lower_threshold_pct_rise : 30 ; + slew_upper_threshold_pct_rise : 70 ; + input_threshold_pct_fall : 50 ; + output_threshold_pct_fall : 50 ; + input_threshold_pct_rise : 50 ; + output_threshold_pct_rise : 50 ; + slew_lower_threshold_pct_fall : 30 ; + slew_upper_threshold_pct_fall : 70 ; + slew_derate_from_library : 0.5; + k_volt_cell_leakage_power : 0.0 ; + k_temp_cell_leakage_power : 0.0 ; + k_process_cell_leakage_power : 0.0 ; + k_volt_internal_power : 0.0 ; + k_temp_internal_power : 0.0 ; + k_process_internal_power : 0.0 ; + + capacitive_load_unit (1,pf) ; + voltage_unit : "1V" ; + current_unit : "1uA" ; + time_unit : "1ns" ; + leakage_power_unit : "1nW" ; + pulling_resistance_unit : "1kohm"; + /* + ------------------------------------------------------------------------------------------ + implicit units overview: + cell_area unit : "um" + internal_power unit : "1e-12 * J/toggle = 1 * uW/MHz" + (capacitive_load_unit * voltage_unit^2) per toggle event + ------------------------------------------------------------------------------------------ + */ + library_features(report_delay_calculation); + define_cell_area (pad_drivers,pad_driver_sites) ; + + lu_table_template(CLKTRAN_constraint_template) { + variable_1 : constrained_pin_transition; + index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" ); + } + lu_table_template(SRAM_load_template) { + variable_1 : total_output_net_capacitance; + index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + lu_table_template(SIG2SRAM_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" ); + index_2 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" ); + } + + lu_table_template(SIG2SRAM_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" ); + index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + + type (D_15_0) { + base_type : array; + data_type : bit; + bit_width : 16; + bit_from : 15; + bit_to : 0; + downto : true; + } + + type (A_9_0) { + base_type : array; + data_type : bit; + bit_width : 10; + bit_from : 9; + bit_to : 0; + downto : true; + } + +cell(RM_IHPSG13_1P_1024x16_c2_bm_bist) { +pg_pin (VDD) { + pg_type : primary_power; + voltage_name : VDD; +} +pg_pin (VDDARRAY) { + pg_type : primary_power; + voltage_name : VDDARRAY; +} +pg_pin (VSS) { + pg_type : primary_ground; + voltage_name : VSS; +} + +memory() { + type : ram; + address_width : 10; + word_width : 16; +} + +interface_timing : false; +bus_naming_style : "%s[%d]" ; +area : 79673.728 ; + + pin(A_DLY) { + direction : input ; + capacitance : 0.00421562 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_ADDR) { + bus_type : A_9_0; + direction : input ; + capacitance : 0.00691085 ; + pin(A_ADDR[0]) { + capacitance : 0.00562034 ; + } + pin(A_ADDR[1]) { + capacitance : 0.00462655 ; + } + pin(A_ADDR[2]) { + capacitance : 0.00594295 ; + } + pin(A_ADDR[3]) { + capacitance : 0.00723434 ; + } + pin(A_ADDR[4]) { + capacitance : 0.00481603 ; + } + pin(A_ADDR[5]) { + capacitance : 0.00868123 ; + } + pin(A_ADDR[6]) { + capacitance : 0.010187 ; + } + pin(A_ADDR[7]) { + capacitance : 0.00734489 ; + } + pin(A_ADDR[8]) { + capacitance : 0.00904175 ; + } + max_transition : "0.38" ; + pin(A_ADDR[9:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.2111); + } + fall_power("scalar"){ + values (0.2703); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0286); + } + fall_power("scalar"){ + values (0.0026); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2371,-0.2215,-0.2098,-0.1824,-0.1434,-0.0691,0.0676",\ +"-0.2449,-0.2332,-0.2176,-0.1902,-0.1551,-0.0770,0.0559",\ +"-0.2605,-0.2488,-0.2332,-0.2059,-0.1707,-0.0965,0.0441",\ +"-0.2879,-0.2723,-0.2605,-0.2332,-0.1941,-0.1199,0.0168",\ +"-0.3230,-0.3113,-0.2996,-0.2723,-0.2332,-0.1590,-0.0184",\ +"-0.4012,-0.3895,-0.3738,-0.3465,-0.3074,-0.2332,-0.0965",\ +"-0.5379,-0.5262,-0.5105,-0.4832,-0.4480,-0.3699,-0.2332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1785,-0.1707,-0.1551,-0.1277,-0.0887,-0.0184,0.1145",\ +"-0.1902,-0.1785,-0.1629,-0.1355,-0.1004,-0.0262,0.1027",\ +"-0.2059,-0.1941,-0.1785,-0.1512,-0.1160,-0.0418,0.0871",\ +"-0.2293,-0.2176,-0.2059,-0.1785,-0.1434,-0.0691,0.0598",\ +"-0.2684,-0.2566,-0.2449,-0.2176,-0.1824,-0.1082,0.0207",\ +"-0.3465,-0.3348,-0.3191,-0.2918,-0.2566,-0.1824,-0.0535",\ +"-0.4832,-0.4715,-0.4559,-0.4324,-0.3934,-0.3191,-0.1902"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3410,0.3293,0.3137,0.2863,0.2473,0.1730,0.0324",\ +"0.3488,0.3371,0.3215,0.2941,0.2590,0.1809,0.0480",\ +"0.3684,0.3527,0.3371,0.3098,0.2746,0.1965,0.0598",\ +"0.3918,0.3762,0.3645,0.3371,0.2980,0.2238,0.0871",\ +"0.4309,0.4152,0.4035,0.3762,0.3371,0.2629,0.1223",\ +"0.5051,0.4934,0.4777,0.4504,0.4113,0.3371,0.1965",\ +"0.6418,0.6262,0.6145,0.5871,0.5520,0.4738,0.3332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2824,0.2707,0.2551,0.2277,0.1926,0.1184,-0.0105",\ +"0.2902,0.2785,0.2668,0.2395,0.2043,0.1301,0.0012",\ +"0.3059,0.2941,0.2824,0.2551,0.2199,0.1457,0.0168",\ +"0.3332,0.3215,0.3059,0.2785,0.2434,0.1691,0.0402",\ +"0.3723,0.3605,0.3449,0.3176,0.2824,0.2121,0.0793",\ +"0.4465,0.4348,0.4230,0.3918,0.3566,0.2824,0.1535",\ +"0.5832,0.5715,0.5598,0.5324,0.4934,0.4191,0.2902"); + } + } +} +pin(A_WEN) { + direction : input ; + capacitance : 0.00341384 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.4060); + } + fall_power("scalar"){ + values (0.0178); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0063); + } + fall_power("scalar"){ + values (0.0181); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1887,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3527",\ +"-0.0262,-0.0145,0.0012,0.0246,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1418"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2160,0.2316,0.2590,0.2941,0.3684,0.5012",\ +"0.1926,0.2043,0.2199,0.2473,0.2824,0.3566,0.4895",\ +"0.1770,0.1887,0.2043,0.2316,0.2668,0.3410,0.4777",\ +"0.1535,0.1652,0.1770,0.2043,0.2395,0.3137,0.4504",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2746,0.4113",\ +"0.0402,0.0520,0.0676,0.0910,0.1262,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0730,-0.0457,-0.0066,0.0637,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1496,0.1223,0.0793,0.0090,-0.1316",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0168,-0.1199",\ +"0.2004,0.1887,0.1770,0.1496,0.1066,0.0363,-0.1043",\ +"0.2277,0.2160,0.2004,0.1730,0.1340,0.0598,-0.0809",\ +"0.2668,0.2551,0.2395,0.2121,0.1730,0.0988,-0.0418",\ +"0.3410,0.3293,0.3137,0.2863,0.2434,0.1730,0.0324",\ +"0.4816,0.4699,0.4543,0.4230,0.3801,0.3098,0.1730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1066,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1457,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1613,0.1340,0.0988,0.0246,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2512,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0457",\ +"0.3254,0.3176,0.3020,0.2746,0.2355,0.1652,0.0324",\ +"0.4660,0.4543,0.4387,0.4113,0.3723,0.3020,0.1691"); + } + } + } +pin(A_REN) { + direction : input ; + capacitance : 0.00390661 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0125); + } + fall_power("scalar"){ + values (0.0108); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0263); + } + fall_power("scalar"){ + values (0.0211); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.0027,0.0090,0.0246,0.0520,0.0910,0.1613,0.3020",\ +"-0.0105,0.0012,0.0129,0.0363,0.0793,0.1535,0.2902",\ +"-0.0262,-0.0145,-0.0027,0.0246,0.0637,0.1379,0.2785",\ +"-0.0535,-0.0418,-0.0262,0.0012,0.0363,0.1105,0.2512",\ +"-0.0926,-0.0809,-0.0652,-0.0418,-0.0027,0.0715,0.2121",\ +"-0.1668,-0.1551,-0.1395,-0.1082,-0.0770,-0.0027,0.1379",\ +"-0.3035,-0.2918,-0.2762,-0.2488,-0.2137,-0.1434,-0.0027"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.0832,0.0949,0.1105,0.1379,0.1730,0.2473,0.3801",\ +"0.0754,0.0832,0.0988,0.1223,0.1613,0.2355,0.3684",\ +"0.0598,0.0676,0.0832,0.1066,0.1457,0.2121,0.3527",\ +"0.0324,0.0441,0.0598,0.0871,0.1223,0.1926,0.3293",\ +"-0.0066,0.0051,0.0168,0.0480,0.0832,0.1535,0.2902",\ +"-0.0809,-0.0691,-0.0574,-0.0301,0.0090,0.0832,0.2121",\ +"-0.2176,-0.2059,-0.1941,-0.1668,-0.1277,-0.0574,0.0793"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1160",\ +"0.1965,0.1848,0.1730,0.1457,0.1027,0.0324,-0.1082",\ +"0.2160,0.2004,0.1887,0.1613,0.1184,0.0480,-0.0926",\ +"0.2395,0.2277,0.2121,0.1848,0.1457,0.0715,-0.0652",\ +"0.2785,0.2668,0.2512,0.2238,0.1848,0.1105,-0.0262",\ +"0.3527,0.3410,0.3254,0.2980,0.2551,0.1848,0.0480",\ +"0.4934,0.4816,0.4660,0.4387,0.3957,0.3254,0.1887"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1730,0.1613,0.1496,0.1184,0.0793,0.0129,-0.1238",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0207,-0.1121",\ +"0.2004,0.1887,0.1730,0.1457,0.1066,0.0363,-0.1004",\ +"0.2238,0.2121,0.2004,0.1691,0.1340,0.0598,-0.0730",\ +"0.2629,0.2512,0.2395,0.2121,0.1691,0.0988,-0.0340",\ +"0.3371,0.3254,0.3137,0.2863,0.2434,0.1730,0.0402",\ +"0.4777,0.4660,0.4504,0.4230,0.3840,0.3137,0.1809"); + } + } + } +pin(A_MEN) { + direction : input ; + capacitance : 0.00326046 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.1484); + } + fall_power("scalar"){ + values (0.2101); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1926,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1418,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3488",\ +"-0.0262,-0.0145,0.0012,0.0285,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1379"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2199,0.2316,0.2590,0.2980,0.3723,0.5051",\ +"0.1965,0.2082,0.2199,0.2473,0.2863,0.3605,0.4934",\ +"0.1809,0.1926,0.2043,0.2316,0.2707,0.3449,0.4777",\ +"0.1574,0.1691,0.1809,0.2082,0.2434,0.3176,0.4543",\ +"0.1145,0.1262,0.1418,0.1691,0.2043,0.2785,0.4113",\ +"0.0441,0.0559,0.0676,0.0949,0.1301,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0691,-0.0418,-0.0066,0.0676,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1535,0.1262,0.0832,0.0129,-0.1277",\ +"0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1199",\ +"0.2043,0.1926,0.1770,0.1496,0.1105,0.0363,-0.1043",\ +"0.2277,0.2160,0.2043,0.1770,0.1379,0.0598,-0.0770",\ +"0.2668,0.2551,0.2434,0.2160,0.1730,0.0988,-0.0379",\ +"0.3449,0.3332,0.3176,0.2902,0.2473,0.1730,0.0363",\ +"0.4816,0.4699,0.4543,0.4270,0.3840,0.3098,0.1770"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1105,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1496,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1652,0.1340,0.0988,0.0285,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2551,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0418",\ +"0.3293,0.3176,0.3020,0.2746,0.2395,0.1652,0.0324",\ +"0.4660,0.4543,0.4426,0.4113,0.3762,0.3020,0.1691"); + } + } + } +bus(A_BM) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00310985 ; + max_transition : "0.38" ; + pin(A_BM[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0783); + } + fall_power("scalar"){ + values (0.0812); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.1034); + } + fall_power("scalar"){ + values (0.0834); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1890,-0.1783,-0.1627,-0.1363,-0.0963,-0.0260,0.1088",\ +"-0.1929,-0.1822,-0.1666,-0.1402,-0.1002,-0.0298,0.1049",\ +"-0.1967,-0.1860,-0.1704,-0.1440,-0.1039,-0.0336,0.1011",\ +"-0.2000,-0.1892,-0.1736,-0.1472,-0.1072,-0.0369,0.0979",\ +"-0.2124,-0.2017,-0.1861,-0.1597,-0.1196,-0.0493,0.0854",\ +"-0.2299,-0.2191,-0.2035,-0.1771,-0.1371,-0.0668,0.0680",\ +"-0.2575,-0.2468,-0.2312,-0.2048,-0.1648,-0.0945,0.0403"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1666,-0.1558,-0.1422,-0.1148,-0.0777,-0.0055,0.1244",\ +"-0.1705,-0.1597,-0.1461,-0.1187,-0.0816,-0.0093,0.1205",\ +"-0.1743,-0.1635,-0.1498,-0.1225,-0.0854,-0.0131,0.1167",\ +"-0.1775,-0.1668,-0.1531,-0.1258,-0.0887,-0.0164,0.1135",\ +"-0.1900,-0.1792,-0.1656,-0.1382,-0.1011,-0.0288,0.1011",\ +"-0.2074,-0.1967,-0.1830,-0.1557,-0.1186,-0.0463,0.0836",\ +"-0.2351,-0.2243,-0.2107,-0.1833,-0.1462,-0.0739,0.0559"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2950,0.2833,0.2686,0.2423,0.2022,0.1309,-0.0058",\ +"0.2989,0.2872,0.2725,0.2461,0.2061,0.1348,-0.0019",\ +"0.3027,0.2910,0.2763,0.2499,0.2099,0.1386,0.0019",\ +"0.3059,0.2942,0.2796,0.2532,0.2132,0.1419,0.0052",\ +"0.3184,0.3066,0.2920,0.2656,0.2256,0.1543,0.0176",\ +"0.3358,0.3241,0.3095,0.2831,0.2431,0.1718,0.0351",\ +"0.3635,0.3518,0.3371,0.3108,0.2707,0.1994,0.0627"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2667,0.2569,0.2423,0.2159,0.1788,0.1055,-0.0224",\ +"0.2706,0.2608,0.2461,0.2198,0.1827,0.1094,-0.0185",\ +"0.2744,0.2646,0.2499,0.2236,0.1865,0.1132,-0.0147",\ +"0.2776,0.2678,0.2532,0.2268,0.1897,0.1165,-0.0115",\ +"0.2900,0.2803,0.2656,0.2393,0.2022,0.1289,0.0010",\ +"0.3075,0.2978,0.2831,0.2567,0.2196,0.1464,0.0185",\ +"0.3352,0.3254,0.3108,0.2844,0.2473,0.1740,0.0461"); + } + } +} + pin(A_CLK) { + direction : input; + capacitance : 0.00389386; + max_transition : "0.38"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.004,0.38"); + values("0.12,0.12"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (0.7039); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (40.8199); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (41.5232); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (33.7892); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (0.4120); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (0.9290); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_DIN) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00387207 ; + memory_write() { + address : A_ADDR ; + clocked_on : A_CLK; + } + + max_transition : "0.38" ; + pin(A_DIN[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0783); + } + fall_power("scalar"){ + values (0.0812); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.1034); + } + fall_power("scalar"){ + values (0.0834); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1890,-0.1783,-0.1627,-0.1363,-0.0963,-0.0260,0.1088",\ +"-0.1929,-0.1822,-0.1666,-0.1402,-0.1002,-0.0298,0.1049",\ +"-0.1967,-0.1860,-0.1704,-0.1440,-0.1039,-0.0336,0.1011",\ +"-0.2000,-0.1892,-0.1736,-0.1472,-0.1072,-0.0369,0.0979",\ +"-0.2124,-0.2017,-0.1861,-0.1597,-0.1196,-0.0493,0.0854",\ +"-0.2299,-0.2191,-0.2035,-0.1771,-0.1371,-0.0668,0.0680",\ +"-0.2575,-0.2468,-0.2312,-0.2048,-0.1648,-0.0945,0.0403"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1666,-0.1558,-0.1422,-0.1148,-0.0777,-0.0055,0.1244",\ +"-0.1705,-0.1597,-0.1461,-0.1187,-0.0816,-0.0093,0.1205",\ +"-0.1743,-0.1635,-0.1498,-0.1225,-0.0854,-0.0131,0.1167",\ +"-0.1775,-0.1668,-0.1531,-0.1258,-0.0887,-0.0164,0.1135",\ +"-0.1900,-0.1792,-0.1656,-0.1382,-0.1011,-0.0288,0.1011",\ +"-0.2074,-0.1967,-0.1830,-0.1557,-0.1186,-0.0463,0.0836",\ +"-0.2351,-0.2243,-0.2107,-0.1833,-0.1462,-0.0739,0.0559"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2950,0.2833,0.2686,0.2423,0.2022,0.1309,-0.0058",\ +"0.2989,0.2872,0.2725,0.2461,0.2061,0.1348,-0.0019",\ +"0.3027,0.2910,0.2763,0.2499,0.2099,0.1386,0.0019",\ +"0.3059,0.2942,0.2796,0.2532,0.2132,0.1419,0.0052",\ +"0.3184,0.3066,0.2920,0.2656,0.2256,0.1543,0.0176",\ +"0.3358,0.3241,0.3095,0.2831,0.2431,0.1718,0.0351",\ +"0.3635,0.3518,0.3371,0.3108,0.2707,0.1994,0.0627"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2667,0.2569,0.2423,0.2159,0.1788,0.1055,-0.0224",\ +"0.2706,0.2608,0.2461,0.2198,0.1827,0.1094,-0.0185",\ +"0.2744,0.2646,0.2499,0.2236,0.1865,0.1132,-0.0147",\ +"0.2776,0.2678,0.2532,0.2268,0.1897,0.1165,-0.0115",\ +"0.2900,0.2803,0.2656,0.2393,0.2022,0.1289,0.0010",\ +"0.3075,0.2978,0.2831,0.2567,0.2196,0.1464,0.0185",\ +"0.3352,0.3254,0.3108,0.2844,0.2473,0.1740,0.0461"); + } + } + } + + pin(A_BIST_EN) { + direction : input ; + capacitance : 0.00421562 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_BIST_ADDR) { + bus_type : A_9_0; + direction : input ; + capacitance : 0.00691085 ; + pin(A_BIST_ADDR[0]) { + capacitance : 0.00562034 ; + } + pin(A_BIST_ADDR[1]) { + capacitance : 0.00462655 ; + } + pin(A_BIST_ADDR[2]) { + capacitance : 0.00594295 ; + } + pin(A_BIST_ADDR[3]) { + capacitance : 0.00723434 ; + } + pin(A_BIST_ADDR[4]) { + capacitance : 0.00481603 ; + } + pin(A_BIST_ADDR[5]) { + capacitance : 0.00868123 ; + } + pin(A_BIST_ADDR[6]) { + capacitance : 0.010187 ; + } + pin(A_BIST_ADDR[7]) { + capacitance : 0.00734489 ; + } + pin(A_BIST_ADDR[8]) { + capacitance : 0.00904175 ; + } + max_transition : "0.38" ; + pin(A_BIST_ADDR[9:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.2111); + } + fall_power("scalar"){ + values (0.2703); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0286); + } + fall_power("scalar"){ + values (0.0026); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2371,-0.2215,-0.2098,-0.1824,-0.1434,-0.0691,0.0676",\ +"-0.2449,-0.2332,-0.2176,-0.1902,-0.1551,-0.0770,0.0559",\ +"-0.2605,-0.2488,-0.2332,-0.2059,-0.1707,-0.0965,0.0441",\ +"-0.2879,-0.2723,-0.2605,-0.2332,-0.1941,-0.1199,0.0168",\ +"-0.3230,-0.3113,-0.2996,-0.2723,-0.2332,-0.1590,-0.0184",\ +"-0.4012,-0.3895,-0.3738,-0.3465,-0.3074,-0.2332,-0.0965",\ +"-0.5379,-0.5262,-0.5105,-0.4832,-0.4480,-0.3699,-0.2332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1785,-0.1707,-0.1551,-0.1277,-0.0887,-0.0184,0.1145",\ +"-0.1902,-0.1785,-0.1629,-0.1355,-0.1004,-0.0262,0.1027",\ +"-0.2059,-0.1941,-0.1785,-0.1512,-0.1160,-0.0418,0.0871",\ +"-0.2293,-0.2176,-0.2059,-0.1785,-0.1434,-0.0691,0.0598",\ +"-0.2684,-0.2566,-0.2449,-0.2176,-0.1824,-0.1082,0.0207",\ +"-0.3465,-0.3348,-0.3191,-0.2918,-0.2566,-0.1824,-0.0535",\ +"-0.4832,-0.4715,-0.4559,-0.4324,-0.3934,-0.3191,-0.1902"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3410,0.3293,0.3137,0.2863,0.2473,0.1730,0.0324",\ +"0.3488,0.3371,0.3215,0.2941,0.2590,0.1809,0.0480",\ +"0.3684,0.3527,0.3371,0.3098,0.2746,0.1965,0.0598",\ +"0.3918,0.3762,0.3645,0.3371,0.2980,0.2238,0.0871",\ +"0.4309,0.4152,0.4035,0.3762,0.3371,0.2629,0.1223",\ +"0.5051,0.4934,0.4777,0.4504,0.4113,0.3371,0.1965",\ +"0.6418,0.6262,0.6145,0.5871,0.5520,0.4738,0.3332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2824,0.2707,0.2551,0.2277,0.1926,0.1184,-0.0105",\ +"0.2902,0.2785,0.2668,0.2395,0.2043,0.1301,0.0012",\ +"0.3059,0.2941,0.2824,0.2551,0.2199,0.1457,0.0168",\ +"0.3332,0.3215,0.3059,0.2785,0.2434,0.1691,0.0402",\ +"0.3723,0.3605,0.3449,0.3176,0.2824,0.2121,0.0793",\ +"0.4465,0.4348,0.4230,0.3918,0.3566,0.2824,0.1535",\ +"0.5832,0.5715,0.5598,0.5324,0.4934,0.4191,0.2902"); + } + } +} +pin(A_BIST_WEN) { + direction : input ; + capacitance : 0.00341384 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.4060); + } + fall_power("scalar"){ + values (0.0178); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0063); + } + fall_power("scalar"){ + values (0.0181); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1887,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3527",\ +"-0.0262,-0.0145,0.0012,0.0246,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1418"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2160,0.2316,0.2590,0.2941,0.3684,0.5012",\ +"0.1926,0.2043,0.2199,0.2473,0.2824,0.3566,0.4895",\ +"0.1770,0.1887,0.2043,0.2316,0.2668,0.3410,0.4777",\ +"0.1535,0.1652,0.1770,0.2043,0.2395,0.3137,0.4504",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2746,0.4113",\ +"0.0402,0.0520,0.0676,0.0910,0.1262,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0730,-0.0457,-0.0066,0.0637,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1496,0.1223,0.0793,0.0090,-0.1316",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0168,-0.1199",\ +"0.2004,0.1887,0.1770,0.1496,0.1066,0.0363,-0.1043",\ +"0.2277,0.2160,0.2004,0.1730,0.1340,0.0598,-0.0809",\ +"0.2668,0.2551,0.2395,0.2121,0.1730,0.0988,-0.0418",\ +"0.3410,0.3293,0.3137,0.2863,0.2434,0.1730,0.0324",\ +"0.4816,0.4699,0.4543,0.4230,0.3801,0.3098,0.1730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1066,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1457,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1613,0.1340,0.0988,0.0246,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2512,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0457",\ +"0.3254,0.3176,0.3020,0.2746,0.2355,0.1652,0.0324",\ +"0.4660,0.4543,0.4387,0.4113,0.3723,0.3020,0.1691"); + } + } + } +pin(A_BIST_REN) { + direction : input ; + capacitance : 0.00390661 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0125); + } + fall_power("scalar"){ + values (0.0108); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0263); + } + fall_power("scalar"){ + values (0.0211); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.0027,0.0090,0.0246,0.0520,0.0910,0.1613,0.3020",\ +"-0.0105,0.0012,0.0129,0.0363,0.0793,0.1535,0.2902",\ +"-0.0262,-0.0145,-0.0027,0.0246,0.0637,0.1379,0.2785",\ +"-0.0535,-0.0418,-0.0262,0.0012,0.0363,0.1105,0.2512",\ +"-0.0926,-0.0809,-0.0652,-0.0418,-0.0027,0.0715,0.2121",\ +"-0.1668,-0.1551,-0.1395,-0.1082,-0.0770,-0.0027,0.1379",\ +"-0.3035,-0.2918,-0.2762,-0.2488,-0.2137,-0.1434,-0.0027"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.0832,0.0949,0.1105,0.1379,0.1730,0.2473,0.3801",\ +"0.0754,0.0832,0.0988,0.1223,0.1613,0.2355,0.3684",\ +"0.0598,0.0676,0.0832,0.1066,0.1457,0.2121,0.3527",\ +"0.0324,0.0441,0.0598,0.0871,0.1223,0.1926,0.3293",\ +"-0.0066,0.0051,0.0168,0.0480,0.0832,0.1535,0.2902",\ +"-0.0809,-0.0691,-0.0574,-0.0301,0.0090,0.0832,0.2121",\ +"-0.2176,-0.2059,-0.1941,-0.1668,-0.1277,-0.0574,0.0793"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1160",\ +"0.1965,0.1848,0.1730,0.1457,0.1027,0.0324,-0.1082",\ +"0.2160,0.2004,0.1887,0.1613,0.1184,0.0480,-0.0926",\ +"0.2395,0.2277,0.2121,0.1848,0.1457,0.0715,-0.0652",\ +"0.2785,0.2668,0.2512,0.2238,0.1848,0.1105,-0.0262",\ +"0.3527,0.3410,0.3254,0.2980,0.2551,0.1848,0.0480",\ +"0.4934,0.4816,0.4660,0.4387,0.3957,0.3254,0.1887"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1730,0.1613,0.1496,0.1184,0.0793,0.0129,-0.1238",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0207,-0.1121",\ +"0.2004,0.1887,0.1730,0.1457,0.1066,0.0363,-0.1004",\ +"0.2238,0.2121,0.2004,0.1691,0.1340,0.0598,-0.0730",\ +"0.2629,0.2512,0.2395,0.2121,0.1691,0.0988,-0.0340",\ +"0.3371,0.3254,0.3137,0.2863,0.2434,0.1730,0.0402",\ +"0.4777,0.4660,0.4504,0.4230,0.3840,0.3137,0.1809"); + } + } + } +pin(A_BIST_MEN) { + direction : input ; + capacitance : 0.00326046 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.1484); + } + fall_power("scalar"){ + values (0.2101); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1926,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1418,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3488",\ +"-0.0262,-0.0145,0.0012,0.0285,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1379"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2199,0.2316,0.2590,0.2980,0.3723,0.5051",\ +"0.1965,0.2082,0.2199,0.2473,0.2863,0.3605,0.4934",\ +"0.1809,0.1926,0.2043,0.2316,0.2707,0.3449,0.4777",\ +"0.1574,0.1691,0.1809,0.2082,0.2434,0.3176,0.4543",\ +"0.1145,0.1262,0.1418,0.1691,0.2043,0.2785,0.4113",\ +"0.0441,0.0559,0.0676,0.0949,0.1301,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0691,-0.0418,-0.0066,0.0676,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1535,0.1262,0.0832,0.0129,-0.1277",\ +"0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1199",\ +"0.2043,0.1926,0.1770,0.1496,0.1105,0.0363,-0.1043",\ +"0.2277,0.2160,0.2043,0.1770,0.1379,0.0598,-0.0770",\ +"0.2668,0.2551,0.2434,0.2160,0.1730,0.0988,-0.0379",\ +"0.3449,0.3332,0.3176,0.2902,0.2473,0.1730,0.0363",\ +"0.4816,0.4699,0.4543,0.4270,0.3840,0.3098,0.1770"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1105,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1496,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1652,0.1340,0.0988,0.0285,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2551,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0418",\ +"0.3293,0.3176,0.3020,0.2746,0.2395,0.1652,0.0324",\ +"0.4660,0.4543,0.4426,0.4113,0.3762,0.3020,0.1691"); + } + } + } +bus(A_BIST_BM) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00253457 ; + max_transition : "0.38" ; + pin(A_BIST_BM[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0783); + } + fall_power("scalar"){ + values (0.0812); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.1034); + } + fall_power("scalar"){ + values (0.0834); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1890,-0.1783,-0.1627,-0.1363,-0.0963,-0.0260,0.1088",\ +"-0.1929,-0.1822,-0.1666,-0.1402,-0.1002,-0.0298,0.1049",\ +"-0.1967,-0.1860,-0.1704,-0.1440,-0.1039,-0.0336,0.1011",\ +"-0.2000,-0.1892,-0.1736,-0.1472,-0.1072,-0.0369,0.0979",\ +"-0.2124,-0.2017,-0.1861,-0.1597,-0.1196,-0.0493,0.0854",\ +"-0.2299,-0.2191,-0.2035,-0.1771,-0.1371,-0.0668,0.0680",\ +"-0.2575,-0.2468,-0.2312,-0.2048,-0.1648,-0.0945,0.0403"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1666,-0.1558,-0.1422,-0.1148,-0.0777,-0.0055,0.1244",\ +"-0.1705,-0.1597,-0.1461,-0.1187,-0.0816,-0.0093,0.1205",\ +"-0.1743,-0.1635,-0.1498,-0.1225,-0.0854,-0.0131,0.1167",\ +"-0.1775,-0.1668,-0.1531,-0.1258,-0.0887,-0.0164,0.1135",\ +"-0.1900,-0.1792,-0.1656,-0.1382,-0.1011,-0.0288,0.1011",\ +"-0.2074,-0.1967,-0.1830,-0.1557,-0.1186,-0.0463,0.0836",\ +"-0.2351,-0.2243,-0.2107,-0.1833,-0.1462,-0.0739,0.0559"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2950,0.2833,0.2686,0.2423,0.2022,0.1309,-0.0058",\ +"0.2989,0.2872,0.2725,0.2461,0.2061,0.1348,-0.0019",\ +"0.3027,0.2910,0.2763,0.2499,0.2099,0.1386,0.0019",\ +"0.3059,0.2942,0.2796,0.2532,0.2132,0.1419,0.0052",\ +"0.3184,0.3066,0.2920,0.2656,0.2256,0.1543,0.0176",\ +"0.3358,0.3241,0.3095,0.2831,0.2431,0.1718,0.0351",\ +"0.3635,0.3518,0.3371,0.3108,0.2707,0.1994,0.0627"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2667,0.2569,0.2423,0.2159,0.1788,0.1055,-0.0224",\ +"0.2706,0.2608,0.2461,0.2198,0.1827,0.1094,-0.0185",\ +"0.2744,0.2646,0.2499,0.2236,0.1865,0.1132,-0.0147",\ +"0.2776,0.2678,0.2532,0.2268,0.1897,0.1165,-0.0115",\ +"0.2900,0.2803,0.2656,0.2393,0.2022,0.1289,0.0010",\ +"0.3075,0.2978,0.2831,0.2567,0.2196,0.1464,0.0185",\ +"0.3352,0.3254,0.3108,0.2844,0.2473,0.1740,0.0461"); + } + } +} + pin(A_BIST_CLK) { + direction : input; + capacitance : 0.00389386; + max_transition : "0.38"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.004,0.38"); + values("0.12,0.12"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0.7039); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (40.8199); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (41.5232); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (33.7892); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.4120); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.9290); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_BIST_DIN) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00252927 ; + memory_write() { + address : A_BIST_ADDR ; + clocked_on : A_BIST_CLK; + } + + max_transition : "0.38" ; + pin(A_BIST_DIN[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0783); + } + fall_power("scalar"){ + values (0.0812); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.1034); + } + fall_power("scalar"){ + values (0.0834); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1890,-0.1783,-0.1627,-0.1363,-0.0963,-0.0260,0.1088",\ +"-0.1929,-0.1822,-0.1666,-0.1402,-0.1002,-0.0298,0.1049",\ +"-0.1967,-0.1860,-0.1704,-0.1440,-0.1039,-0.0336,0.1011",\ +"-0.2000,-0.1892,-0.1736,-0.1472,-0.1072,-0.0369,0.0979",\ +"-0.2124,-0.2017,-0.1861,-0.1597,-0.1196,-0.0493,0.0854",\ +"-0.2299,-0.2191,-0.2035,-0.1771,-0.1371,-0.0668,0.0680",\ +"-0.2575,-0.2468,-0.2312,-0.2048,-0.1648,-0.0945,0.0403"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1666,-0.1558,-0.1422,-0.1148,-0.0777,-0.0055,0.1244",\ +"-0.1705,-0.1597,-0.1461,-0.1187,-0.0816,-0.0093,0.1205",\ +"-0.1743,-0.1635,-0.1498,-0.1225,-0.0854,-0.0131,0.1167",\ +"-0.1775,-0.1668,-0.1531,-0.1258,-0.0887,-0.0164,0.1135",\ +"-0.1900,-0.1792,-0.1656,-0.1382,-0.1011,-0.0288,0.1011",\ +"-0.2074,-0.1967,-0.1830,-0.1557,-0.1186,-0.0463,0.0836",\ +"-0.2351,-0.2243,-0.2107,-0.1833,-0.1462,-0.0739,0.0559"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2950,0.2833,0.2686,0.2423,0.2022,0.1309,-0.0058",\ +"0.2989,0.2872,0.2725,0.2461,0.2061,0.1348,-0.0019",\ +"0.3027,0.2910,0.2763,0.2499,0.2099,0.1386,0.0019",\ +"0.3059,0.2942,0.2796,0.2532,0.2132,0.1419,0.0052",\ +"0.3184,0.3066,0.2920,0.2656,0.2256,0.1543,0.0176",\ +"0.3358,0.3241,0.3095,0.2831,0.2431,0.1718,0.0351",\ +"0.3635,0.3518,0.3371,0.3108,0.2707,0.1994,0.0627"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2667,0.2569,0.2423,0.2159,0.1788,0.1055,-0.0224",\ +"0.2706,0.2608,0.2461,0.2198,0.1827,0.1094,-0.0185",\ +"0.2744,0.2646,0.2499,0.2236,0.1865,0.1132,-0.0147",\ +"0.2776,0.2678,0.2532,0.2268,0.1897,0.1165,-0.0115",\ +"0.2900,0.2803,0.2656,0.2393,0.2022,0.1289,0.0010",\ +"0.3075,0.2978,0.2831,0.2567,0.2196,0.1464,0.0185",\ +"0.3352,0.3254,0.3108,0.2844,0.2473,0.1740,0.0461"); + } + } + } + +bus(A_DOUT) { + + bus_type : D_15_0; + direction : output ; + capacitance : 0 ; + max_capacitance : "6.4e-14" ; + memory_read() { + address : A_ADDR ; + } + pin(A_DOUT[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "A_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("2.6175,2.6185,2.6234,2.6289,2.6498,2.6733",\ +"2.6247,2.6258,2.6306,2.6361,2.6570,2.6805",\ +"2.6262,2.6272,2.6320,2.6376,2.6585,2.6820",\ +"2.6296,2.6306,2.6354,2.6409,2.6618,2.6853",\ +"2.6424,2.6434,2.6482,2.6537,2.6746,2.6981",\ +"2.6601,2.6612,2.6660,2.6715,2.6924,2.7159",\ +"2.6855,2.6865,2.6914,2.6969,2.7178,2.7413"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("2.5832,2.5841,2.5881,2.5927,2.6098,2.6265",\ +"2.5905,2.5913,2.5954,2.5999,2.6170,2.6337",\ +"2.5919,2.5928,2.5968,2.6014,2.6185,2.6352",\ +"2.5953,2.5961,2.6002,2.6047,2.6218,2.6385",\ +"2.6081,2.6089,2.6130,2.6175,2.6346,2.6513",\ +"2.6259,2.6267,2.6308,2.6353,2.6524,2.6691",\ +"2.6512,2.6521,2.6561,2.6607,2.6778,2.6945"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0206,0.0210,0.0265,0.0323,0.0606,0.0955"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0170,0.0177,0.0222,0.0270,0.0451,0.0644"); + } + } +} +cell_leakage_power : 469.5941; +} +} diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_1024x16_c2_bm_bist_slow_1p08V_125C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_1024x16_c2_bm_bist_slow_1p08V_125C.lib new file mode 100644 index 0000000000..7f909869ac --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_1024x16_c2_bm_bist_slow_1p08V_125C.lib @@ -0,0 +1,1525 @@ +/* ------------------------------------------------------*/ +/**/ +/* Copyright 2024 IHP PDK Authors*/ +/**/ +/* Licensed under the Apache License, Version 2.0 (the "License");*/ +/* you may not use this file except in compliance with the License.*/ +/* You may obtain a copy of the License at*/ +/* */ +/* https://www.apache.org/licenses/LICENSE-2.0*/ +/* */ +/* Unless required by applicable law or agreed to in writing, software*/ +/* distributed under the License is distributed on an "AS IS" BASIS,*/ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/ +/* See the License for the specific language governing permissions and*/ +/* limitations under the License.*/ +/* */ +/* Generated on Fri Jul 19 08:58:02 2024 */ +/* */ +/* ------------------------------------------------------ */ +library(RM_IHPSG13_1P_1024x16_c2_bm_bist_slow_1p08V_125C) { + technology (cmos) ; + delay_model : table_lookup ; + define ("add_pg_pin_to_lib", "library", "boolean"); + add_pg_pin_to_lib : true; + voltage_map ( VDD, 1.08); + voltage_map ( VDDARRAY, 1.08); + voltage_map ( VSS, 0.000000 ); + + date : "Fri Jul 19 08:58:00 2024" ; + comment : "IHP Microelectronics GmbH, 2024" ; + revision : 1.0.0 ; + simulation : true ; + nom_process : 1 ; + nom_temperature : 125 ; + nom_voltage : 1.08 ; + + operating_conditions("slow_1p08V_125C"){ + process : 1 ; + temperature : 125 ; + voltage : 1.08 ; + tree_type : "balanced_tree" ; + } + + default_operating_conditions : slow_1p08V_125C ; + default_max_transition : 1.0 ; + default_fanout_load : 1.0 ; + default_inout_pin_cap : 0.0 ; + default_input_pin_cap : 0.0 ; + default_output_pin_cap : 0.0 ; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + + slew_lower_threshold_pct_rise : 30 ; + slew_upper_threshold_pct_rise : 70 ; + input_threshold_pct_fall : 50 ; + output_threshold_pct_fall : 50 ; + input_threshold_pct_rise : 50 ; + output_threshold_pct_rise : 50 ; + slew_lower_threshold_pct_fall : 30 ; + slew_upper_threshold_pct_fall : 70 ; + slew_derate_from_library : 0.5; + k_volt_cell_leakage_power : 0.0 ; + k_temp_cell_leakage_power : 0.0 ; + k_process_cell_leakage_power : 0.0 ; + k_volt_internal_power : 0.0 ; + k_temp_internal_power : 0.0 ; + k_process_internal_power : 0.0 ; + + capacitive_load_unit (1,pf) ; + voltage_unit : "1V" ; + current_unit : "1uA" ; + time_unit : "1ns" ; + leakage_power_unit : "1nW" ; + pulling_resistance_unit : "1kohm"; + /* + ------------------------------------------------------------------------------------------ + implicit units overview: + cell_area unit : "um" + internal_power unit : "1e-12 * J/toggle = 1 * uW/MHz" + (capacitive_load_unit * voltage_unit^2) per toggle event + ------------------------------------------------------------------------------------------ + */ + library_features(report_delay_calculation); + define_cell_area (pad_drivers,pad_driver_sites) ; + + lu_table_template(CLKTRAN_constraint_template) { + variable_1 : constrained_pin_transition; + index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" ); + } + lu_table_template(SRAM_load_template) { + variable_1 : total_output_net_capacitance; + index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + lu_table_template(SIG2SRAM_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" ); + index_2 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" ); + } + + lu_table_template(SIG2SRAM_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" ); + index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + + type (D_15_0) { + base_type : array; + data_type : bit; + bit_width : 16; + bit_from : 15; + bit_to : 0; + downto : true; + } + + type (A_9_0) { + base_type : array; + data_type : bit; + bit_width : 10; + bit_from : 9; + bit_to : 0; + downto : true; + } + +cell(RM_IHPSG13_1P_1024x16_c2_bm_bist) { +pg_pin (VDD) { + pg_type : primary_power; + voltage_name : VDD; +} +pg_pin (VDDARRAY) { + pg_type : primary_power; + voltage_name : VDDARRAY; +} +pg_pin (VSS) { + pg_type : primary_ground; + voltage_name : VSS; +} + +memory() { + type : ram; + address_width : 10; + word_width : 16; +} + +interface_timing : false; +bus_naming_style : "%s[%d]" ; +area : 79673.728 ; + + pin(A_DLY) { + direction : input ; + capacitance : 0.00387999 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_ADDR) { + bus_type : A_9_0; + direction : input ; + capacitance : 0.0077013 ; + pin(A_ADDR[0]) { + capacitance : 0.00625349 ; + } + pin(A_ADDR[1]) { + capacitance : 0.00507435 ; + } + pin(A_ADDR[2]) { + capacitance : 0.00656707 ; + } + pin(A_ADDR[3]) { + capacitance : 0.0083133 ; + } + pin(A_ADDR[4]) { + capacitance : 0.00507219 ; + } + pin(A_ADDR[5]) { + capacitance : 0.00964344 ; + } + pin(A_ADDR[6]) { + capacitance : 0.0119653 ; + } + pin(A_ADDR[7]) { + capacitance : 0.00827606 ; + } + pin(A_ADDR[8]) { + capacitance : 0.0110771 ; + } + max_transition : "0.5952" ; + pin(A_ADDR[9:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0011); + } + fall_power("scalar"){ + values (0.0188); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0058); + } + fall_power("scalar"){ + values (0.0107); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7371,-0.7176,-0.6863,-0.6434,-0.5652,-0.4168,-0.1980",\ +"-0.7566,-0.7371,-0.7059,-0.6629,-0.5848,-0.4363,-0.2137",\ +"-0.7879,-0.7645,-0.7332,-0.6902,-0.6121,-0.4637,-0.2449",\ +"-0.8309,-0.8074,-0.7762,-0.7332,-0.6551,-0.5066,-0.2879",\ +"-0.9051,-0.8895,-0.8543,-0.8113,-0.7332,-0.5887,-0.3660",\ +"-1.0418,-1.0262,-0.9949,-0.9480,-0.8699,-0.7293,-0.5027",\ +"-1.2684,-1.2449,-1.2176,-1.1707,-1.0965,-0.9480,-0.7293"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5926,-0.5730,-0.5418,-0.4988,-0.4246,-0.2879,-0.0730",\ +"-0.6121,-0.5926,-0.5613,-0.5223,-0.4441,-0.3074,-0.0887",\ +"-0.6395,-0.6199,-0.5926,-0.5496,-0.4715,-0.3348,-0.1160",\ +"-0.6863,-0.6668,-0.6355,-0.5965,-0.5184,-0.3777,-0.1590",\ +"-0.7605,-0.7410,-0.7137,-0.6746,-0.5926,-0.4559,-0.2410",\ +"-0.9012,-0.8816,-0.8504,-0.8113,-0.7332,-0.5926,-0.3895",\ +"-1.1238,-1.1043,-1.0769,-1.0379,-0.9559,-0.8191,-0.6004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8488,0.8293,0.7980,0.7551,0.6730,0.5285,0.3098",\ +"0.8684,0.8488,0.8176,0.7746,0.6926,0.5480,0.3254",\ +"0.8996,0.8801,0.8449,0.8020,0.7238,0.5754,0.3527",\ +"0.9426,0.9191,0.8918,0.8488,0.7668,0.6223,0.3996",\ +"1.0168,1.0012,0.9699,0.9230,0.8449,0.7004,0.4777",\ +"1.1574,1.1379,1.1105,1.0598,0.9816,0.8371,0.6184",\ +"1.3801,1.3605,1.3254,1.2980,1.2043,1.0637,0.8371"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6965,0.6770,0.6496,0.6066,0.5246,0.3918,0.1730",\ +"0.7160,0.6965,0.6652,0.6262,0.5441,0.4113,0.1965",\ +"0.7473,0.7277,0.6965,0.6535,0.5754,0.4426,0.2238",\ +"0.7863,0.7707,0.7395,0.7004,0.6223,0.4855,0.2629",\ +"0.8684,0.8449,0.8176,0.7785,0.7004,0.5637,0.3449",\ +"1.0051,0.9855,0.9855,0.9113,0.8332,0.7004,0.4895",\ +"1.2277,1.2082,1.1809,1.1379,1.0598,0.9230,0.7004"); + } + } +} +pin(A_WEN) { + direction : input ; + capacitance : 0.00313551 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0065); + } + fall_power("scalar"){ + values (0.0066); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0128); + } + fall_power("scalar"){ + values (0.0293); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3137,0.3332,0.3605,0.4035,0.4816,0.6223,0.8488",\ +"0.2980,0.3176,0.3410,0.3840,0.4660,0.6027,0.8293",\ +"0.2629,0.2824,0.3098,0.3527,0.4348,0.5754,0.7980",\ +"0.2199,0.2395,0.2668,0.3098,0.3918,0.5324,0.7590",\ +"0.1418,0.1613,0.1887,0.2316,0.3137,0.4348,0.6730",\ +"0.0012,0.0207,0.0520,0.0910,0.1730,0.3098,0.5285",\ +"-0.2215,-0.2020,-0.1746,-0.1277,-0.0496,0.0910,0.3098"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4504,0.4699,0.4973,0.5324,0.6027,0.7355,0.9699",\ +"0.4309,0.4504,0.4777,0.5129,0.5910,0.7160,0.9504",\ +"0.3996,0.4191,0.4465,0.4816,0.5520,0.6848,0.9191",\ +"0.3605,0.3762,0.4035,0.4387,0.5168,0.6418,0.8723",\ +"0.2785,0.2980,0.3215,0.3605,0.4348,0.5637,0.7980",\ +"0.1379,0.1574,0.1809,0.2199,0.2980,0.4309,0.6457",\ +"-0.0809,-0.0613,-0.0340,0.0051,0.0832,0.2160,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3723,0.3527,0.3215,0.2785,0.1965,0.0559,-0.1668",\ +"0.3918,0.3723,0.3449,0.2980,0.2160,0.0754,-0.1473",\ +"0.4152,0.3996,0.3684,0.3254,0.2434,0.1066,-0.1199",\ +"0.4621,0.4465,0.4152,0.3723,0.2863,0.1496,-0.0730",\ +"0.5324,0.5207,0.4895,0.4465,0.3645,0.2199,0.0051",\ +"0.6770,0.6535,0.6301,0.5832,0.5090,0.3605,0.1418",\ +"0.9035,0.8879,0.8566,0.8137,0.7316,0.5871,0.3684"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3566,0.3293,0.2863,0.2043,0.0676,-0.1434",\ +"0.3957,0.3762,0.3488,0.3059,0.2238,0.0871,-0.1199",\ +"0.4230,0.4035,0.3723,0.3332,0.2512,0.1184,-0.0965",\ +"0.4660,0.4465,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5324,0.5168,0.4973,0.4543,0.3723,0.2316,0.0285",\ +"0.6809,0.6613,0.6340,0.5910,0.5129,0.3645,0.1652",\ +"0.9113,0.8918,0.8605,0.8176,0.7395,0.5988,0.3879"); + } + } + } +pin(A_REN) { + direction : input ; + capacitance : 0.00381144 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0060); + } + fall_power("scalar"){ + values (0.0027); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0013); + } + fall_power("scalar"){ + values (0.0021); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.0770,-0.0574,-0.0262,0.0168,0.0949,0.2355,0.4582",\ +"-0.0965,-0.0770,-0.0457,-0.0027,0.0754,0.2160,0.4387",\ +"-0.1199,-0.1004,-0.0730,-0.0262,0.0520,0.1887,0.4113",\ +"-0.1590,-0.1434,-0.1160,-0.0730,0.0051,0.1457,0.3645",\ +"-0.2449,-0.2254,-0.1941,-0.1473,-0.0770,0.0676,0.2863",\ +"-0.3816,-0.3699,-0.3387,-0.2801,-0.2215,-0.0770,0.1457",\ +"-0.6121,-0.5926,-0.5613,-0.5145,-0.4363,-0.2996,-0.0730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.1262,0.1457,0.1691,0.2121,0.2824,0.4191,0.6457",\ +"0.1105,0.1262,0.1496,0.1887,0.2629,0.3996,0.6262",\ +"0.0793,0.0949,0.1223,0.1652,0.2395,0.3684,0.5949",\ +"0.0363,0.0559,0.0793,0.1223,0.2004,0.3410,0.5520",\ +"-0.0457,-0.0262,0.0012,0.0441,0.1301,0.2629,0.4738",\ +"-0.1902,-0.1746,-0.1434,-0.1043,-0.0184,0.1223,0.3332",\ +"-0.4129,-0.3934,-0.3660,-0.3230,-0.2449,-0.1043,0.1105"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4113,0.3918,0.3645,0.3176,0.2395,0.0988,-0.1238",\ +"0.4309,0.4113,0.3840,0.3371,0.2590,0.1184,-0.1043",\ +"0.4582,0.4387,0.4113,0.3645,0.2824,0.1457,-0.0770",\ +"0.5051,0.4816,0.4543,0.4074,0.3293,0.1887,-0.0340",\ +"0.5715,0.5598,0.5324,0.4895,0.4035,0.2512,0.0441",\ +"0.7043,0.7004,0.6730,0.6262,0.5402,0.3957,0.1809",\ +"0.9387,0.9270,0.8957,0.8527,0.7746,0.6262,0.4074"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4152,0.3918,0.3645,0.3215,0.2395,0.1027,-0.1082",\ +"0.4309,0.4113,0.3801,0.3410,0.2590,0.1223,-0.0926",\ +"0.4582,0.4387,0.4074,0.3684,0.2863,0.1496,-0.0613",\ +"0.5012,0.4816,0.4504,0.4074,0.3293,0.1887,-0.0145",\ +"0.5715,0.5559,0.5285,0.4816,0.3996,0.2512,0.0598",\ +"0.7160,0.7004,0.6691,0.6262,0.5520,0.4035,0.2004",\ +"0.9387,0.9191,0.8957,0.8488,0.7707,0.6262,0.4113"); + } + } + } +pin(A_MEN) { + direction : input ; + capacitance : 0.00300347 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0060); + } + fall_power("scalar"){ + values (0.0099); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3215,0.3449,0.3684,0.4113,0.4895,0.6301,0.8527",\ +"0.3059,0.3254,0.3527,0.3957,0.4738,0.6145,0.8371",\ +"0.2746,0.2941,0.3215,0.3645,0.4426,0.5871,0.8059",\ +"0.2316,0.2512,0.2785,0.3215,0.3996,0.5402,0.7629",\ +"0.1496,0.1730,0.1965,0.2395,0.3215,0.4660,0.6848",\ +"0.0090,0.0285,0.0598,0.1027,0.1809,0.3176,0.5402",\ +"-0.2098,-0.1902,-0.1668,-0.1199,-0.0418,0.0988,0.3137"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4582,0.4738,0.5012,0.5363,0.6145,0.7395,0.9738",\ +"0.4387,0.4543,0.4816,0.5207,0.5910,0.7199,0.9582",\ +"0.4035,0.4230,0.4504,0.4855,0.5637,0.6887,0.9230",\ +"0.3645,0.3840,0.4074,0.4465,0.5285,0.6496,0.8840",\ +"0.2824,0.3020,0.3254,0.3645,0.4465,0.5715,0.7980",\ +"0.1418,0.1613,0.1887,0.2238,0.3020,0.4309,0.6496",\ +"-0.0770,-0.0574,-0.0301,0.0090,0.0910,0.2238,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3293,0.2863,0.2043,0.0637,-0.1629",\ +"0.3996,0.3801,0.3488,0.3020,0.2238,0.0832,-0.1395",\ +"0.4230,0.4074,0.3723,0.3293,0.2473,0.1105,-0.1121",\ +"0.4621,0.4465,0.4152,0.3762,0.2941,0.1535,-0.0691",\ +"0.5441,0.5285,0.4973,0.4465,0.3684,0.2316,0.0090",\ +"0.6848,0.6652,0.6301,0.5910,0.5129,0.3605,0.1496",\ +"0.9074,0.8918,0.8566,0.8215,0.7395,0.5910,0.3723"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3332,0.2863,0.2043,0.0715,-0.1395",\ +"0.3996,0.3762,0.3488,0.3059,0.2238,0.0910,-0.1199",\ +"0.4270,0.4035,0.3762,0.3332,0.2512,0.1184,-0.0965",\ +"0.4699,0.4504,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5441,0.5285,0.4973,0.4543,0.3762,0.2355,0.0324",\ +"0.6770,0.6613,0.6340,0.5949,0.5207,0.3762,0.1652",\ +"0.9074,0.8918,0.8605,0.8176,0.7395,0.6027,0.3918"); + } + } + } +bus(A_BM) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00263802 ; + max_transition : "0.5952" ; + pin(A_BM[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0368); + } + fall_power("scalar"){ + values (0.0200); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0452); + } + fall_power("scalar"){ + values (0.0145); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.6208,-0.6012,-0.5749,-0.5329,-0.4518,-0.3073,-0.0866",\ +"-0.6288,-0.6093,-0.5829,-0.5409,-0.4599,-0.3153,-0.0946",\ +"-0.6378,-0.6183,-0.5919,-0.5499,-0.4689,-0.3243,-0.1036",\ +"-0.6510,-0.6314,-0.6051,-0.5631,-0.4820,-0.3375,-0.1168",\ +"-0.6752,-0.6557,-0.6293,-0.5874,-0.5063,-0.3618,-0.1411",\ +"-0.7058,-0.6862,-0.6599,-0.6179,-0.5368,-0.3923,-0.1716",\ +"-0.7872,-0.7677,-0.7413,-0.6993,-0.6183,-0.4737,-0.2530"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5651,-0.5495,-0.5212,-0.4821,-0.4011,-0.2634,-0.0514",\ +"-0.5731,-0.5575,-0.5292,-0.4901,-0.4091,-0.2714,-0.0595",\ +"-0.5822,-0.5665,-0.5382,-0.4991,-0.4181,-0.2804,-0.0685",\ +"-0.5953,-0.5797,-0.5514,-0.5123,-0.4312,-0.2936,-0.0816",\ +"-0.6196,-0.6040,-0.5756,-0.5366,-0.4555,-0.3178,-0.1059",\ +"-0.6501,-0.6345,-0.6061,-0.5671,-0.4860,-0.3483,-0.1364",\ +"-0.7315,-0.7159,-0.6876,-0.6485,-0.5675,-0.4298,-0.2179"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.7376,0.7161,0.6897,0.6467,0.5676,0.4221,0.1965",\ +"0.7456,0.7241,0.6977,0.6548,0.5757,0.4302,0.2046",\ +"0.7546,0.7331,0.7067,0.6638,0.5847,0.4392,0.2136",\ +"0.7677,0.7463,0.7199,0.6769,0.5978,0.4523,0.2267",\ +"0.7920,0.7705,0.7442,0.7012,0.6221,0.4766,0.2510",\ +"0.8225,0.8010,0.7747,0.7317,0.6526,0.5071,0.2815",\ +"0.9040,0.8825,0.8561,0.8132,0.7341,0.5886,0.3630"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6692,0.6526,0.6243,0.5803,0.5032,0.3655,0.1555",\ +"0.6772,0.6606,0.6323,0.5884,0.5112,0.3735,0.1636",\ +"0.6862,0.6696,0.6413,0.5974,0.5202,0.3825,0.1726",\ +"0.6994,0.6828,0.6545,0.6105,0.5334,0.3957,0.1857",\ +"0.7237,0.7071,0.6787,0.6348,0.5576,0.4200,0.2100",\ +"0.7542,0.7376,0.7093,0.6653,0.5882,0.4505,0.2405",\ +"0.8356,0.8190,0.7907,0.7468,0.6696,0.5319,0.3220"); + } + } +} + pin(A_CLK) { + direction : input; + capacitance : 0.00378957; + max_transition : "0.5952"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.008,0.5952"); + values("0.4,0.4"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (0.5660); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (25.9369); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (26.9678); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (20.0971); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (0.3586); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (0.7302); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_DIN) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00358485 ; + memory_write() { + address : A_ADDR ; + clocked_on : A_CLK; + } + + max_transition : "0.5952" ; + pin(A_DIN[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0368); + } + fall_power("scalar"){ + values (0.0200); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0452); + } + fall_power("scalar"){ + values (0.0145); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.6208,-0.6012,-0.5749,-0.5329,-0.4518,-0.3073,-0.0866",\ +"-0.6288,-0.6093,-0.5829,-0.5409,-0.4599,-0.3153,-0.0946",\ +"-0.6378,-0.6183,-0.5919,-0.5499,-0.4689,-0.3243,-0.1036",\ +"-0.6510,-0.6314,-0.6051,-0.5631,-0.4820,-0.3375,-0.1168",\ +"-0.6752,-0.6557,-0.6293,-0.5874,-0.5063,-0.3618,-0.1411",\ +"-0.7058,-0.6862,-0.6599,-0.6179,-0.5368,-0.3923,-0.1716",\ +"-0.7872,-0.7677,-0.7413,-0.6993,-0.6183,-0.4737,-0.2530"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5651,-0.5495,-0.5212,-0.4821,-0.4011,-0.2634,-0.0514",\ +"-0.5731,-0.5575,-0.5292,-0.4901,-0.4091,-0.2714,-0.0595",\ +"-0.5822,-0.5665,-0.5382,-0.4991,-0.4181,-0.2804,-0.0685",\ +"-0.5953,-0.5797,-0.5514,-0.5123,-0.4312,-0.2936,-0.0816",\ +"-0.6196,-0.6040,-0.5756,-0.5366,-0.4555,-0.3178,-0.1059",\ +"-0.6501,-0.6345,-0.6061,-0.5671,-0.4860,-0.3483,-0.1364",\ +"-0.7315,-0.7159,-0.6876,-0.6485,-0.5675,-0.4298,-0.2179"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.7376,0.7161,0.6897,0.6467,0.5676,0.4221,0.1965",\ +"0.7456,0.7241,0.6977,0.6548,0.5757,0.4302,0.2046",\ +"0.7546,0.7331,0.7067,0.6638,0.5847,0.4392,0.2136",\ +"0.7677,0.7463,0.7199,0.6769,0.5978,0.4523,0.2267",\ +"0.7920,0.7705,0.7442,0.7012,0.6221,0.4766,0.2510",\ +"0.8225,0.8010,0.7747,0.7317,0.6526,0.5071,0.2815",\ +"0.9040,0.8825,0.8561,0.8132,0.7341,0.5886,0.3630"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6692,0.6526,0.6243,0.5803,0.5032,0.3655,0.1555",\ +"0.6772,0.6606,0.6323,0.5884,0.5112,0.3735,0.1636",\ +"0.6862,0.6696,0.6413,0.5974,0.5202,0.3825,0.1726",\ +"0.6994,0.6828,0.6545,0.6105,0.5334,0.3957,0.1857",\ +"0.7237,0.7071,0.6787,0.6348,0.5576,0.4200,0.2100",\ +"0.7542,0.7376,0.7093,0.6653,0.5882,0.4505,0.2405",\ +"0.8356,0.8190,0.7907,0.7468,0.6696,0.5319,0.3220"); + } + } + } + + pin(A_BIST_EN) { + direction : input ; + capacitance : 0.00387999 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_BIST_ADDR) { + bus_type : A_9_0; + direction : input ; + capacitance : 0.0077013 ; + pin(A_BIST_ADDR[0]) { + capacitance : 0.00625349 ; + } + pin(A_BIST_ADDR[1]) { + capacitance : 0.00507435 ; + } + pin(A_BIST_ADDR[2]) { + capacitance : 0.00656707 ; + } + pin(A_BIST_ADDR[3]) { + capacitance : 0.0083133 ; + } + pin(A_BIST_ADDR[4]) { + capacitance : 0.00507219 ; + } + pin(A_BIST_ADDR[5]) { + capacitance : 0.00964344 ; + } + pin(A_BIST_ADDR[6]) { + capacitance : 0.0119653 ; + } + pin(A_BIST_ADDR[7]) { + capacitance : 0.00827606 ; + } + pin(A_BIST_ADDR[8]) { + capacitance : 0.0110771 ; + } + max_transition : "0.5952" ; + pin(A_BIST_ADDR[9:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0011); + } + fall_power("scalar"){ + values (0.0188); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0058); + } + fall_power("scalar"){ + values (0.0107); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7371,-0.7176,-0.6863,-0.6434,-0.5652,-0.4168,-0.1980",\ +"-0.7566,-0.7371,-0.7059,-0.6629,-0.5848,-0.4363,-0.2137",\ +"-0.7879,-0.7645,-0.7332,-0.6902,-0.6121,-0.4637,-0.2449",\ +"-0.8309,-0.8074,-0.7762,-0.7332,-0.6551,-0.5066,-0.2879",\ +"-0.9051,-0.8895,-0.8543,-0.8113,-0.7332,-0.5887,-0.3660",\ +"-1.0418,-1.0262,-0.9949,-0.9480,-0.8699,-0.7293,-0.5027",\ +"-1.2684,-1.2449,-1.2176,-1.1707,-1.0965,-0.9480,-0.7293"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5926,-0.5730,-0.5418,-0.4988,-0.4246,-0.2879,-0.0730",\ +"-0.6121,-0.5926,-0.5613,-0.5223,-0.4441,-0.3074,-0.0887",\ +"-0.6395,-0.6199,-0.5926,-0.5496,-0.4715,-0.3348,-0.1160",\ +"-0.6863,-0.6668,-0.6355,-0.5965,-0.5184,-0.3777,-0.1590",\ +"-0.7605,-0.7410,-0.7137,-0.6746,-0.5926,-0.4559,-0.2410",\ +"-0.9012,-0.8816,-0.8504,-0.8113,-0.7332,-0.5926,-0.3895",\ +"-1.1238,-1.1043,-1.0769,-1.0379,-0.9559,-0.8191,-0.6004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8488,0.8293,0.7980,0.7551,0.6730,0.5285,0.3098",\ +"0.8684,0.8488,0.8176,0.7746,0.6926,0.5480,0.3254",\ +"0.8996,0.8801,0.8449,0.8020,0.7238,0.5754,0.3527",\ +"0.9426,0.9191,0.8918,0.8488,0.7668,0.6223,0.3996",\ +"1.0168,1.0012,0.9699,0.9230,0.8449,0.7004,0.4777",\ +"1.1574,1.1379,1.1105,1.0598,0.9816,0.8371,0.6184",\ +"1.3801,1.3605,1.3254,1.2980,1.2043,1.0637,0.8371"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6965,0.6770,0.6496,0.6066,0.5246,0.3918,0.1730",\ +"0.7160,0.6965,0.6652,0.6262,0.5441,0.4113,0.1965",\ +"0.7473,0.7277,0.6965,0.6535,0.5754,0.4426,0.2238",\ +"0.7863,0.7707,0.7395,0.7004,0.6223,0.4855,0.2629",\ +"0.8684,0.8449,0.8176,0.7785,0.7004,0.5637,0.3449",\ +"1.0051,0.9855,0.9855,0.9113,0.8332,0.7004,0.4895",\ +"1.2277,1.2082,1.1809,1.1379,1.0598,0.9230,0.7004"); + } + } +} +pin(A_BIST_WEN) { + direction : input ; + capacitance : 0.00313551 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0065); + } + fall_power("scalar"){ + values (0.0066); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0128); + } + fall_power("scalar"){ + values (0.0293); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3137,0.3332,0.3605,0.4035,0.4816,0.6223,0.8488",\ +"0.2980,0.3176,0.3410,0.3840,0.4660,0.6027,0.8293",\ +"0.2629,0.2824,0.3098,0.3527,0.4348,0.5754,0.7980",\ +"0.2199,0.2395,0.2668,0.3098,0.3918,0.5324,0.7590",\ +"0.1418,0.1613,0.1887,0.2316,0.3137,0.4348,0.6730",\ +"0.0012,0.0207,0.0520,0.0910,0.1730,0.3098,0.5285",\ +"-0.2215,-0.2020,-0.1746,-0.1277,-0.0496,0.0910,0.3098"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4504,0.4699,0.4973,0.5324,0.6027,0.7355,0.9699",\ +"0.4309,0.4504,0.4777,0.5129,0.5910,0.7160,0.9504",\ +"0.3996,0.4191,0.4465,0.4816,0.5520,0.6848,0.9191",\ +"0.3605,0.3762,0.4035,0.4387,0.5168,0.6418,0.8723",\ +"0.2785,0.2980,0.3215,0.3605,0.4348,0.5637,0.7980",\ +"0.1379,0.1574,0.1809,0.2199,0.2980,0.4309,0.6457",\ +"-0.0809,-0.0613,-0.0340,0.0051,0.0832,0.2160,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3723,0.3527,0.3215,0.2785,0.1965,0.0559,-0.1668",\ +"0.3918,0.3723,0.3449,0.2980,0.2160,0.0754,-0.1473",\ +"0.4152,0.3996,0.3684,0.3254,0.2434,0.1066,-0.1199",\ +"0.4621,0.4465,0.4152,0.3723,0.2863,0.1496,-0.0730",\ +"0.5324,0.5207,0.4895,0.4465,0.3645,0.2199,0.0051",\ +"0.6770,0.6535,0.6301,0.5832,0.5090,0.3605,0.1418",\ +"0.9035,0.8879,0.8566,0.8137,0.7316,0.5871,0.3684"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3566,0.3293,0.2863,0.2043,0.0676,-0.1434",\ +"0.3957,0.3762,0.3488,0.3059,0.2238,0.0871,-0.1199",\ +"0.4230,0.4035,0.3723,0.3332,0.2512,0.1184,-0.0965",\ +"0.4660,0.4465,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5324,0.5168,0.4973,0.4543,0.3723,0.2316,0.0285",\ +"0.6809,0.6613,0.6340,0.5910,0.5129,0.3645,0.1652",\ +"0.9113,0.8918,0.8605,0.8176,0.7395,0.5988,0.3879"); + } + } + } +pin(A_BIST_REN) { + direction : input ; + capacitance : 0.00381144 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0060); + } + fall_power("scalar"){ + values (0.0027); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0013); + } + fall_power("scalar"){ + values (0.0021); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.0770,-0.0574,-0.0262,0.0168,0.0949,0.2355,0.4582",\ +"-0.0965,-0.0770,-0.0457,-0.0027,0.0754,0.2160,0.4387",\ +"-0.1199,-0.1004,-0.0730,-0.0262,0.0520,0.1887,0.4113",\ +"-0.1590,-0.1434,-0.1160,-0.0730,0.0051,0.1457,0.3645",\ +"-0.2449,-0.2254,-0.1941,-0.1473,-0.0770,0.0676,0.2863",\ +"-0.3816,-0.3699,-0.3387,-0.2801,-0.2215,-0.0770,0.1457",\ +"-0.6121,-0.5926,-0.5613,-0.5145,-0.4363,-0.2996,-0.0730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.1262,0.1457,0.1691,0.2121,0.2824,0.4191,0.6457",\ +"0.1105,0.1262,0.1496,0.1887,0.2629,0.3996,0.6262",\ +"0.0793,0.0949,0.1223,0.1652,0.2395,0.3684,0.5949",\ +"0.0363,0.0559,0.0793,0.1223,0.2004,0.3410,0.5520",\ +"-0.0457,-0.0262,0.0012,0.0441,0.1301,0.2629,0.4738",\ +"-0.1902,-0.1746,-0.1434,-0.1043,-0.0184,0.1223,0.3332",\ +"-0.4129,-0.3934,-0.3660,-0.3230,-0.2449,-0.1043,0.1105"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4113,0.3918,0.3645,0.3176,0.2395,0.0988,-0.1238",\ +"0.4309,0.4113,0.3840,0.3371,0.2590,0.1184,-0.1043",\ +"0.4582,0.4387,0.4113,0.3645,0.2824,0.1457,-0.0770",\ +"0.5051,0.4816,0.4543,0.4074,0.3293,0.1887,-0.0340",\ +"0.5715,0.5598,0.5324,0.4895,0.4035,0.2512,0.0441",\ +"0.7043,0.7004,0.6730,0.6262,0.5402,0.3957,0.1809",\ +"0.9387,0.9270,0.8957,0.8527,0.7746,0.6262,0.4074"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4152,0.3918,0.3645,0.3215,0.2395,0.1027,-0.1082",\ +"0.4309,0.4113,0.3801,0.3410,0.2590,0.1223,-0.0926",\ +"0.4582,0.4387,0.4074,0.3684,0.2863,0.1496,-0.0613",\ +"0.5012,0.4816,0.4504,0.4074,0.3293,0.1887,-0.0145",\ +"0.5715,0.5559,0.5285,0.4816,0.3996,0.2512,0.0598",\ +"0.7160,0.7004,0.6691,0.6262,0.5520,0.4035,0.2004",\ +"0.9387,0.9191,0.8957,0.8488,0.7707,0.6262,0.4113"); + } + } + } +pin(A_BIST_MEN) { + direction : input ; + capacitance : 0.00300347 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0060); + } + fall_power("scalar"){ + values (0.0099); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3215,0.3449,0.3684,0.4113,0.4895,0.6301,0.8527",\ +"0.3059,0.3254,0.3527,0.3957,0.4738,0.6145,0.8371",\ +"0.2746,0.2941,0.3215,0.3645,0.4426,0.5871,0.8059",\ +"0.2316,0.2512,0.2785,0.3215,0.3996,0.5402,0.7629",\ +"0.1496,0.1730,0.1965,0.2395,0.3215,0.4660,0.6848",\ +"0.0090,0.0285,0.0598,0.1027,0.1809,0.3176,0.5402",\ +"-0.2098,-0.1902,-0.1668,-0.1199,-0.0418,0.0988,0.3137"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4582,0.4738,0.5012,0.5363,0.6145,0.7395,0.9738",\ +"0.4387,0.4543,0.4816,0.5207,0.5910,0.7199,0.9582",\ +"0.4035,0.4230,0.4504,0.4855,0.5637,0.6887,0.9230",\ +"0.3645,0.3840,0.4074,0.4465,0.5285,0.6496,0.8840",\ +"0.2824,0.3020,0.3254,0.3645,0.4465,0.5715,0.7980",\ +"0.1418,0.1613,0.1887,0.2238,0.3020,0.4309,0.6496",\ +"-0.0770,-0.0574,-0.0301,0.0090,0.0910,0.2238,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3293,0.2863,0.2043,0.0637,-0.1629",\ +"0.3996,0.3801,0.3488,0.3020,0.2238,0.0832,-0.1395",\ +"0.4230,0.4074,0.3723,0.3293,0.2473,0.1105,-0.1121",\ +"0.4621,0.4465,0.4152,0.3762,0.2941,0.1535,-0.0691",\ +"0.5441,0.5285,0.4973,0.4465,0.3684,0.2316,0.0090",\ +"0.6848,0.6652,0.6301,0.5910,0.5129,0.3605,0.1496",\ +"0.9074,0.8918,0.8566,0.8215,0.7395,0.5910,0.3723"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3332,0.2863,0.2043,0.0715,-0.1395",\ +"0.3996,0.3762,0.3488,0.3059,0.2238,0.0910,-0.1199",\ +"0.4270,0.4035,0.3762,0.3332,0.2512,0.1184,-0.0965",\ +"0.4699,0.4504,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5441,0.5285,0.4973,0.4543,0.3762,0.2355,0.0324",\ +"0.6770,0.6613,0.6340,0.5949,0.5207,0.3762,0.1652",\ +"0.9074,0.8918,0.8605,0.8176,0.7395,0.6027,0.3918"); + } + } + } +bus(A_BIST_BM) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00225269 ; + max_transition : "0.5952" ; + pin(A_BIST_BM[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0368); + } + fall_power("scalar"){ + values (0.0200); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0452); + } + fall_power("scalar"){ + values (0.0145); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.6208,-0.6012,-0.5749,-0.5329,-0.4518,-0.3073,-0.0866",\ +"-0.6288,-0.6093,-0.5829,-0.5409,-0.4599,-0.3153,-0.0946",\ +"-0.6378,-0.6183,-0.5919,-0.5499,-0.4689,-0.3243,-0.1036",\ +"-0.6510,-0.6314,-0.6051,-0.5631,-0.4820,-0.3375,-0.1168",\ +"-0.6752,-0.6557,-0.6293,-0.5874,-0.5063,-0.3618,-0.1411",\ +"-0.7058,-0.6862,-0.6599,-0.6179,-0.5368,-0.3923,-0.1716",\ +"-0.7872,-0.7677,-0.7413,-0.6993,-0.6183,-0.4737,-0.2530"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5651,-0.5495,-0.5212,-0.4821,-0.4011,-0.2634,-0.0514",\ +"-0.5731,-0.5575,-0.5292,-0.4901,-0.4091,-0.2714,-0.0595",\ +"-0.5822,-0.5665,-0.5382,-0.4991,-0.4181,-0.2804,-0.0685",\ +"-0.5953,-0.5797,-0.5514,-0.5123,-0.4312,-0.2936,-0.0816",\ +"-0.6196,-0.6040,-0.5756,-0.5366,-0.4555,-0.3178,-0.1059",\ +"-0.6501,-0.6345,-0.6061,-0.5671,-0.4860,-0.3483,-0.1364",\ +"-0.7315,-0.7159,-0.6876,-0.6485,-0.5675,-0.4298,-0.2179"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.7376,0.7161,0.6897,0.6467,0.5676,0.4221,0.1965",\ +"0.7456,0.7241,0.6977,0.6548,0.5757,0.4302,0.2046",\ +"0.7546,0.7331,0.7067,0.6638,0.5847,0.4392,0.2136",\ +"0.7677,0.7463,0.7199,0.6769,0.5978,0.4523,0.2267",\ +"0.7920,0.7705,0.7442,0.7012,0.6221,0.4766,0.2510",\ +"0.8225,0.8010,0.7747,0.7317,0.6526,0.5071,0.2815",\ +"0.9040,0.8825,0.8561,0.8132,0.7341,0.5886,0.3630"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6692,0.6526,0.6243,0.5803,0.5032,0.3655,0.1555",\ +"0.6772,0.6606,0.6323,0.5884,0.5112,0.3735,0.1636",\ +"0.6862,0.6696,0.6413,0.5974,0.5202,0.3825,0.1726",\ +"0.6994,0.6828,0.6545,0.6105,0.5334,0.3957,0.1857",\ +"0.7237,0.7071,0.6787,0.6348,0.5576,0.4200,0.2100",\ +"0.7542,0.7376,0.7093,0.6653,0.5882,0.4505,0.2405",\ +"0.8356,0.8190,0.7907,0.7468,0.6696,0.5319,0.3220"); + } + } +} + pin(A_BIST_CLK) { + direction : input; + capacitance : 0.00378957; + max_transition : "0.5952"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.008,0.5952"); + values("0.4,0.4"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0.5660); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (25.9369); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (26.9678); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (20.0971); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.3586); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.7302); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_BIST_DIN) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00226348 ; + memory_write() { + address : A_BIST_ADDR ; + clocked_on : A_BIST_CLK; + } + + max_transition : "0.5952" ; + pin(A_BIST_DIN[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0368); + } + fall_power("scalar"){ + values (0.0200); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0452); + } + fall_power("scalar"){ + values (0.0145); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.6208,-0.6012,-0.5749,-0.5329,-0.4518,-0.3073,-0.0866",\ +"-0.6288,-0.6093,-0.5829,-0.5409,-0.4599,-0.3153,-0.0946",\ +"-0.6378,-0.6183,-0.5919,-0.5499,-0.4689,-0.3243,-0.1036",\ +"-0.6510,-0.6314,-0.6051,-0.5631,-0.4820,-0.3375,-0.1168",\ +"-0.6752,-0.6557,-0.6293,-0.5874,-0.5063,-0.3618,-0.1411",\ +"-0.7058,-0.6862,-0.6599,-0.6179,-0.5368,-0.3923,-0.1716",\ +"-0.7872,-0.7677,-0.7413,-0.6993,-0.6183,-0.4737,-0.2530"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5651,-0.5495,-0.5212,-0.4821,-0.4011,-0.2634,-0.0514",\ +"-0.5731,-0.5575,-0.5292,-0.4901,-0.4091,-0.2714,-0.0595",\ +"-0.5822,-0.5665,-0.5382,-0.4991,-0.4181,-0.2804,-0.0685",\ +"-0.5953,-0.5797,-0.5514,-0.5123,-0.4312,-0.2936,-0.0816",\ +"-0.6196,-0.6040,-0.5756,-0.5366,-0.4555,-0.3178,-0.1059",\ +"-0.6501,-0.6345,-0.6061,-0.5671,-0.4860,-0.3483,-0.1364",\ +"-0.7315,-0.7159,-0.6876,-0.6485,-0.5675,-0.4298,-0.2179"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.7376,0.7161,0.6897,0.6467,0.5676,0.4221,0.1965",\ +"0.7456,0.7241,0.6977,0.6548,0.5757,0.4302,0.2046",\ +"0.7546,0.7331,0.7067,0.6638,0.5847,0.4392,0.2136",\ +"0.7677,0.7463,0.7199,0.6769,0.5978,0.4523,0.2267",\ +"0.7920,0.7705,0.7442,0.7012,0.6221,0.4766,0.2510",\ +"0.8225,0.8010,0.7747,0.7317,0.6526,0.5071,0.2815",\ +"0.9040,0.8825,0.8561,0.8132,0.7341,0.5886,0.3630"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6692,0.6526,0.6243,0.5803,0.5032,0.3655,0.1555",\ +"0.6772,0.6606,0.6323,0.5884,0.5112,0.3735,0.1636",\ +"0.6862,0.6696,0.6413,0.5974,0.5202,0.3825,0.1726",\ +"0.6994,0.6828,0.6545,0.6105,0.5334,0.3957,0.1857",\ +"0.7237,0.7071,0.6787,0.6348,0.5576,0.4200,0.2100",\ +"0.7542,0.7376,0.7093,0.6653,0.5882,0.4505,0.2405",\ +"0.8356,0.8190,0.7907,0.7468,0.6696,0.5319,0.3220"); + } + } + } + +bus(A_DOUT) { + + bus_type : D_15_0; + direction : output ; + capacitance : 0 ; + max_capacitance : "6.4e-14" ; + memory_read() { + address : A_ADDR ; + } + pin(A_DOUT[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "A_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("7.1160,7.1187,7.1309,7.1451,7.1977,7.2526",\ +"7.1314,7.1341,7.1463,7.1605,7.2131,7.2680",\ +"7.1377,7.1405,7.1526,7.1668,7.2194,7.2744",\ +"7.1584,7.1611,7.1733,7.1875,7.2401,7.2951",\ +"7.1759,7.1786,7.1907,7.2050,7.2575,7.3125",\ +"7.2116,7.2143,7.2265,7.2407,7.2933,7.3483",\ +"7.2820,7.2847,7.2969,7.3111,7.3637,7.4186"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("7.0058,7.0080,7.0177,7.0296,7.0731,7.1168",\ +"7.0212,7.0234,7.0332,7.0450,7.0886,7.1323",\ +"7.0276,7.0297,7.0395,7.0513,7.0949,7.1386",\ +"7.0482,7.0504,7.0602,7.0720,7.1156,7.1593",\ +"7.0657,7.0679,7.0776,7.0895,7.1330,7.1767",\ +"7.1014,7.1036,7.1134,7.1252,7.1688,7.2125",\ +"7.1718,7.1740,7.1838,7.1956,7.2392,7.2829"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0560,0.0583,0.0696,0.0816,0.1519,0.2335"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0428,0.0445,0.0538,0.0658,0.1181,0.1751"); + } + } +} +cell_leakage_power : 1306.5882; +} +} diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_1024x16_c2_bm_bist_typ_1p20V_25C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_1024x16_c2_bm_bist_typ_1p20V_25C.lib new file mode 100644 index 0000000000..258eea0af1 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_1024x16_c2_bm_bist_typ_1p20V_25C.lib @@ -0,0 +1,1525 @@ +/* ------------------------------------------------------*/ +/**/ +/* Copyright 2024 IHP PDK Authors*/ +/**/ +/* Licensed under the Apache License, Version 2.0 (the "License");*/ +/* you may not use this file except in compliance with the License.*/ +/* You may obtain a copy of the License at*/ +/* */ +/* https://www.apache.org/licenses/LICENSE-2.0*/ +/* */ +/* Unless required by applicable law or agreed to in writing, software*/ +/* distributed under the License is distributed on an "AS IS" BASIS,*/ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/ +/* See the License for the specific language governing permissions and*/ +/* limitations under the License.*/ +/* */ +/* Generated on Fri Jul 19 08:58:03 2024 */ +/* */ +/* ------------------------------------------------------ */ +library(RM_IHPSG13_1P_1024x16_c2_bm_bist_typ_1p20V_25C) { + technology (cmos) ; + delay_model : table_lookup ; + define ("add_pg_pin_to_lib", "library", "boolean"); + add_pg_pin_to_lib : true; + voltage_map ( VDD, 1.20); + voltage_map ( VDDARRAY, 1.20); + voltage_map ( VSS, 0.000000 ); + + date : "Fri Jul 19 08:58:00 2024" ; + comment : "IHP Microelectronics GmbH, 2024" ; + revision : 1.0.0 ; + simulation : true ; + nom_process : 1 ; + nom_temperature : 25 ; + nom_voltage : 1.20 ; + + operating_conditions("typ_1p20V_25C"){ + process : 1 ; + temperature : 25 ; + voltage : 1.20 ; + tree_type : "balanced_tree" ; + } + + default_operating_conditions : typ_1p20V_25C ; + default_max_transition : 1.0 ; + default_fanout_load : 1.0 ; + default_inout_pin_cap : 0.0 ; + default_input_pin_cap : 0.0 ; + default_output_pin_cap : 0.0 ; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + + slew_lower_threshold_pct_rise : 30 ; + slew_upper_threshold_pct_rise : 70 ; + input_threshold_pct_fall : 50 ; + output_threshold_pct_fall : 50 ; + input_threshold_pct_rise : 50 ; + output_threshold_pct_rise : 50 ; + slew_lower_threshold_pct_fall : 30 ; + slew_upper_threshold_pct_fall : 70 ; + slew_derate_from_library : 0.5; + k_volt_cell_leakage_power : 0.0 ; + k_temp_cell_leakage_power : 0.0 ; + k_process_cell_leakage_power : 0.0 ; + k_volt_internal_power : 0.0 ; + k_temp_internal_power : 0.0 ; + k_process_internal_power : 0.0 ; + + capacitive_load_unit (1,pf) ; + voltage_unit : "1V" ; + current_unit : "1uA" ; + time_unit : "1ns" ; + leakage_power_unit : "1nW" ; + pulling_resistance_unit : "1kohm"; + /* + ------------------------------------------------------------------------------------------ + implicit units overview: + cell_area unit : "um" + internal_power unit : "1e-12 * J/toggle = 1 * uW/MHz" + (capacitive_load_unit * voltage_unit^2) per toggle event + ------------------------------------------------------------------------------------------ + */ + library_features(report_delay_calculation); + define_cell_area (pad_drivers,pad_driver_sites) ; + + lu_table_template(CLKTRAN_constraint_template) { + variable_1 : constrained_pin_transition; + index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" ); + } + lu_table_template(SRAM_load_template) { + variable_1 : total_output_net_capacitance; + index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + lu_table_template(SIG2SRAM_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" ); + index_2 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" ); + } + + lu_table_template(SIG2SRAM_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" ); + index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + + type (D_15_0) { + base_type : array; + data_type : bit; + bit_width : 16; + bit_from : 15; + bit_to : 0; + downto : true; + } + + type (A_9_0) { + base_type : array; + data_type : bit; + bit_width : 10; + bit_from : 9; + bit_to : 0; + downto : true; + } + +cell(RM_IHPSG13_1P_1024x16_c2_bm_bist) { +pg_pin (VDD) { + pg_type : primary_power; + voltage_name : VDD; +} +pg_pin (VDDARRAY) { + pg_type : primary_power; + voltage_name : VDDARRAY; +} +pg_pin (VSS) { + pg_type : primary_ground; + voltage_name : VSS; +} + +memory() { + type : ram; + address_width : 10; + word_width : 16; +} + +interface_timing : false; +bus_naming_style : "%s[%d]" ; +area : 79673.728 ; + + pin(A_DLY) { + direction : input ; + capacitance : 0.00401111 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_ADDR) { + bus_type : A_9_0; + direction : input ; + capacitance : 0.00721489 ; + pin(A_ADDR[0]) { + capacitance : 0.00593979 ; + } + pin(A_ADDR[1]) { + capacitance : 0.00483009 ; + } + pin(A_ADDR[2]) { + capacitance : 0.006215 ; + } + pin(A_ADDR[3]) { + capacitance : 0.00766726 ; + } + pin(A_ADDR[4]) { + capacitance : 0.00488951 ; + } + pin(A_ADDR[5]) { + capacitance : 0.0091523 ; + } + pin(A_ADDR[6]) { + capacitance : 0.0109212 ; + } + pin(A_ADDR[7]) { + capacitance : 0.00774122 ; + } + pin(A_ADDR[8]) { + capacitance : 0.0101403 ; + } + max_transition : "0.476" ; + pin(A_ADDR[9:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0120); + } + fall_power("scalar"){ + values (0.0063); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0204); + } + fall_power("scalar"){ + values (0.0012); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4168,-0.3973,-0.3855,-0.3543,-0.3074,-0.2020,-0.0027",\ +"-0.4324,-0.4129,-0.4012,-0.3699,-0.3191,-0.2176,-0.0184",\ +"-0.4441,-0.4285,-0.4129,-0.3816,-0.3309,-0.2293,-0.0301",\ +"-0.4793,-0.4598,-0.4441,-0.4129,-0.3660,-0.2645,-0.0652",\ +"-0.5223,-0.5066,-0.4910,-0.4598,-0.4129,-0.3074,-0.1121",\ +"-0.6199,-0.6082,-0.5926,-0.5613,-0.5145,-0.4129,-0.2137",\ +"-0.8191,-0.8074,-0.7840,-0.7566,-0.7098,-0.6082,-0.4051"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3309,-0.3113,-0.2996,-0.2684,-0.2176,-0.1238,0.0637",\ +"-0.3465,-0.3309,-0.3152,-0.2840,-0.2332,-0.1395,0.0480",\ +"-0.3582,-0.3426,-0.3270,-0.2996,-0.2488,-0.1512,0.0324",\ +"-0.3895,-0.3738,-0.3582,-0.3309,-0.2801,-0.1863,0.0051",\ +"-0.4363,-0.4207,-0.4051,-0.3777,-0.3230,-0.2293,-0.0379",\ +"-0.5379,-0.5223,-0.5066,-0.4793,-0.4285,-0.3309,-0.1434",\ +"-0.7332,-0.7176,-0.7020,-0.6746,-0.6238,-0.5262,-0.3387"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5246,0.5051,0.4895,0.4582,0.4113,0.3059,0.1066",\ +"0.5402,0.5207,0.5051,0.4777,0.4270,0.3215,0.1223",\ +"0.5520,0.5324,0.5168,0.4895,0.4387,0.3371,0.1340",\ +"0.5832,0.5676,0.5520,0.5207,0.4738,0.3684,0.1691",\ +"0.6301,0.6105,0.5949,0.5676,0.5168,0.4113,0.2160",\ +"0.7316,0.7121,0.7004,0.6691,0.6223,0.5168,0.3176",\ +"0.9270,0.9230,0.8957,0.8645,0.8137,0.7121,0.5168"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4309,0.4152,0.4035,0.3684,0.3215,0.2277,0.0363",\ +"0.4465,0.4309,0.4152,0.3879,0.3371,0.2395,0.0559",\ +"0.4582,0.4426,0.4309,0.3996,0.3488,0.2551,0.0715",\ +"0.4934,0.4777,0.4621,0.4348,0.3840,0.2863,0.0988",\ +"0.5363,0.5207,0.5051,0.4777,0.4270,0.3332,0.1418",\ +"0.6379,0.6262,0.6105,0.5793,0.5324,0.4348,0.2434",\ +"0.8332,0.8215,0.8059,0.7707,0.7238,0.6301,0.4387"); + } + } +} +pin(A_WEN) { + direction : input ; + capacitance : 0.00324098 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0046); + } + fall_power("scalar"){ + values (0.0039); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0043); + } + fall_power("scalar"){ + values (0.0040); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2629,0.3059,0.4113,0.6066",\ +"0.1887,0.2043,0.2160,0.2473,0.2941,0.3957,0.5949",\ +"0.1691,0.1848,0.2004,0.2316,0.2785,0.3801,0.5754",\ +"0.1379,0.1574,0.1691,0.2004,0.2473,0.3527,0.5480",\ +"0.0910,0.1066,0.1223,0.1535,0.2004,0.2980,0.4973",\ +"-0.0105,0.0051,0.0207,0.0520,0.0949,0.2004,0.3957",\ +"-0.2059,-0.1902,-0.1746,-0.1473,-0.1004,0.0051,0.2004"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2941,0.3098,0.3215,0.3488,0.4035,0.4973,0.6887",\ +"0.2785,0.2941,0.3059,0.3332,0.3840,0.4816,0.6691",\ +"0.2629,0.2785,0.2902,0.3176,0.3684,0.4660,0.6535",\ +"0.2316,0.2473,0.2590,0.2863,0.3410,0.4348,0.6262",\ +"0.1848,0.2004,0.2121,0.2395,0.2902,0.3879,0.5754",\ +"0.0832,0.0988,0.1105,0.1379,0.1809,0.2746,0.4699",\ +"-0.1121,-0.0965,-0.0848,-0.0535,-0.0066,0.0910,0.2824"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2473,0.2316,0.2160,0.1887,0.1379,0.0363,-0.1629",\ +"0.2629,0.2473,0.2316,0.2043,0.1535,0.0520,-0.1473",\ +"0.2785,0.2590,0.2434,0.2160,0.1652,0.0676,-0.1355",\ +"0.3098,0.2941,0.2785,0.2473,0.1965,0.0910,-0.1043",\ +"0.3527,0.3371,0.3215,0.2941,0.2434,0.1418,-0.0574",\ +"0.4582,0.4426,0.4270,0.3957,0.3488,0.2434,0.0480",\ +"0.6535,0.6379,0.6184,0.5910,0.5402,0.4426,0.2434"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2395,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2668,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2395,0.1887,0.0910,-0.0965",\ +"0.3449,0.3293,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4191,0.3879,0.3371,0.2395,0.0559",\ +"0.6457,0.6301,0.6145,0.5871,0.5324,0.4309,0.2512"); + } + } + } +pin(A_REN) { + direction : input ; + capacitance : 0.00381634 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0061); + } + fall_power("scalar"){ + values (0.0021); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0062); + } + fall_power("scalar"){ + values (0.0025); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.0301,-0.0145,0.0012,0.0324,0.0793,0.1809,0.3762",\ +"-0.0457,-0.0301,-0.0145,0.0168,0.0637,0.1613,0.3605",\ +"-0.0574,-0.0418,-0.0262,0.0051,0.0520,0.1496,0.3449",\ +"-0.0926,-0.0730,-0.0574,-0.0262,0.0207,0.1184,0.3137",\ +"-0.1395,-0.1238,-0.1082,-0.0770,-0.0301,0.0715,0.2707",\ +"-0.2410,-0.2254,-0.2098,-0.1746,-0.1355,-0.0340,0.1652",\ +"-0.4402,-0.4207,-0.4051,-0.3738,-0.3270,-0.2293,-0.0340"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.0988,0.1145,0.1262,0.1535,0.2043,0.3020,0.4855",\ +"0.0832,0.0988,0.1105,0.1418,0.1848,0.2824,0.4738",\ +"0.0676,0.0832,0.0949,0.1262,0.1730,0.2668,0.4621",\ +"0.0402,0.0559,0.0676,0.0988,0.1457,0.2434,0.4191",\ +"-0.0105,0.0012,0.0168,0.0480,0.0988,0.1965,0.3840",\ +"-0.1160,-0.0965,-0.0848,-0.0535,-0.0066,0.0988,0.2824",\ +"-0.3113,-0.2957,-0.2801,-0.2527,-0.2059,-0.1043,0.0832"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2707,0.2551,0.2395,0.2121,0.1613,0.0598,-0.1395",\ +"0.2863,0.2707,0.2551,0.2238,0.1730,0.0715,-0.1238",\ +"0.2980,0.2824,0.2668,0.2395,0.1887,0.0871,-0.1121",\ +"0.3332,0.3176,0.3020,0.2707,0.2199,0.1184,-0.0809",\ +"0.3762,0.3605,0.3449,0.3176,0.2668,0.1613,-0.0340",\ +"0.4816,0.4621,0.4504,0.4191,0.3723,0.2629,0.0715",\ +"0.6770,0.6613,0.6418,0.6184,0.5637,0.4699,0.2629"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2590,0.2434,0.2316,0.2004,0.1457,0.0520,-0.1355",\ +"0.2746,0.2590,0.2434,0.2160,0.1613,0.0676,-0.1199",\ +"0.2863,0.2707,0.2590,0.2277,0.1730,0.0832,-0.1082",\ +"0.3215,0.3059,0.2902,0.2590,0.2082,0.1105,-0.0770",\ +"0.3645,0.3488,0.3332,0.3059,0.2551,0.1535,-0.0340",\ +"0.4699,0.4543,0.4387,0.4074,0.3605,0.2551,0.0715",\ +"0.6652,0.6496,0.6340,0.6027,0.5520,0.4621,0.2707"); + } + } + } +pin(A_MEN) { + direction : input ; + capacitance : 0.00309605 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0448); + } + fall_power("scalar"){ + values (0.0052); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2668,0.3098,0.4152,0.6066",\ +"0.1887,0.2043,0.2199,0.2512,0.2941,0.3996,0.5949",\ +"0.1730,0.1887,0.2043,0.2355,0.2824,0.3840,0.5793",\ +"0.1418,0.1574,0.1730,0.2043,0.2512,0.3566,0.5480",\ +"0.0949,0.1105,0.1262,0.1574,0.2043,0.3020,0.5051",\ +"-0.0066,0.0090,0.0246,0.0520,0.0988,0.2043,0.3996",\ +"-0.2020,-0.1863,-0.1746,-0.1434,-0.0965,0.0090,0.2082"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2980,0.3137,0.3254,0.3527,0.4035,0.5012,0.6887",\ +"0.2824,0.2980,0.3098,0.3371,0.3879,0.4855,0.6730",\ +"0.2668,0.2824,0.2941,0.3215,0.3723,0.4699,0.6574",\ +"0.2355,0.2473,0.2629,0.2902,0.3410,0.4387,0.6262",\ +"0.1887,0.2004,0.2160,0.2395,0.2941,0.3918,0.5793",\ +"0.0871,0.1027,0.1145,0.1418,0.1848,0.2746,0.4816",\ +"-0.1082,-0.0965,-0.0809,-0.0496,-0.0027,0.0949,0.2863"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2512,0.2355,0.2199,0.1926,0.1418,0.0402,-0.1590",\ +"0.2668,0.2512,0.2355,0.2082,0.1574,0.0559,-0.1434",\ +"0.2824,0.2629,0.2512,0.2199,0.1691,0.0715,-0.1316",\ +"0.3137,0.2980,0.2824,0.2512,0.2004,0.0988,-0.0965",\ +"0.3566,0.3410,0.3254,0.2980,0.2473,0.1418,-0.0535",\ +"0.4621,0.4426,0.4309,0.3996,0.3527,0.2473,0.0520",\ +"0.6574,0.6418,0.6262,0.5949,0.5441,0.4465,0.2473"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2434,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2707,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2434,0.1926,0.0910,-0.0965",\ +"0.3449,0.3332,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4230,0.3918,0.3410,0.2434,0.0559",\ +"0.6457,0.6301,0.6145,0.5910,0.5324,0.4387,0.2512"); + } + } + } +bus(A_BM) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00285703 ; + max_transition : "0.476" ; + pin(A_BM[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0592); + } + fall_power("scalar"){ + values (0.0247); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0603); + } + fall_power("scalar"){ + values (0.0245); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3412,-0.3246,-0.3119,-0.2796,-0.2328,-0.1283,0.0641",\ +"-0.3462,-0.3296,-0.3169,-0.2847,-0.2378,-0.1333,0.0591",\ +"-0.3506,-0.3340,-0.3213,-0.2891,-0.2422,-0.1377,0.0547",\ +"-0.3605,-0.3439,-0.3312,-0.2989,-0.2521,-0.1476,0.0448",\ +"-0.3668,-0.3502,-0.3375,-0.3053,-0.2584,-0.1539,0.0385",\ +"-0.4033,-0.3867,-0.3740,-0.3418,-0.2949,-0.1904,0.0020",\ +"-0.4542,-0.4376,-0.4249,-0.3926,-0.3458,-0.2413,-0.0489"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3089,-0.2933,-0.2806,-0.2523,-0.2015,-0.1029,0.0758",\ +"-0.3140,-0.2983,-0.2856,-0.2573,-0.2065,-0.1079,0.0708",\ +"-0.3184,-0.3028,-0.2901,-0.2617,-0.2110,-0.1123,0.0664",\ +"-0.3282,-0.3126,-0.2999,-0.2716,-0.2208,-0.1222,0.0565",\ +"-0.3346,-0.3189,-0.3062,-0.2779,-0.2271,-0.1285,0.0502",\ +"-0.3711,-0.3554,-0.3427,-0.3144,-0.2636,-0.1650,0.0137",\ +"-0.4219,-0.4063,-0.3936,-0.3653,-0.3145,-0.2159,-0.0372"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4501,0.4345,0.4218,0.3895,0.3407,0.2421,0.0458",\ +"0.4551,0.4395,0.4268,0.3946,0.3457,0.2471,0.0508",\ +"0.4595,0.4439,0.4312,0.3990,0.3502,0.2515,0.0552",\ +"0.4694,0.4537,0.4411,0.4088,0.3600,0.2614,0.0651",\ +"0.4757,0.4601,0.4474,0.4152,0.3663,0.2677,0.0714",\ +"0.5122,0.4966,0.4839,0.4517,0.4028,0.3042,0.1079",\ +"0.5631,0.5475,0.5348,0.5025,0.4537,0.3551,0.1588"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4100,0.3954,0.3817,0.3534,0.3026,0.2099,0.0214",\ +"0.4151,0.4004,0.3867,0.3584,0.3076,0.2149,0.0264",\ +"0.4195,0.4048,0.3912,0.3628,0.3121,0.2193,0.0308",\ +"0.4293,0.4147,0.4010,0.3727,0.3219,0.2291,0.0407",\ +"0.4357,0.4210,0.4074,0.3790,0.3283,0.2355,0.0470",\ +"0.4722,0.4575,0.4438,0.4155,0.3647,0.2720,0.0835",\ +"0.5230,0.5084,0.4947,0.4664,0.4156,0.3228,0.1344"); + } + } +} + pin(A_CLK) { + direction : input; + capacitance : 0.00380014; + max_transition : "0.476"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.0056,0.476"); + values("0.21,0.21"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (0.5466); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (32.9180); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (33.7600); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (26.4863); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (0.3253); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (0.7651); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_DIN) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00365723 ; + memory_write() { + address : A_ADDR ; + clocked_on : A_CLK; + } + + max_transition : "0.476" ; + pin(A_DIN[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0592); + } + fall_power("scalar"){ + values (0.0247); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0603); + } + fall_power("scalar"){ + values (0.0245); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3412,-0.3246,-0.3119,-0.2796,-0.2328,-0.1283,0.0641",\ +"-0.3462,-0.3296,-0.3169,-0.2847,-0.2378,-0.1333,0.0591",\ +"-0.3506,-0.3340,-0.3213,-0.2891,-0.2422,-0.1377,0.0547",\ +"-0.3605,-0.3439,-0.3312,-0.2989,-0.2521,-0.1476,0.0448",\ +"-0.3668,-0.3502,-0.3375,-0.3053,-0.2584,-0.1539,0.0385",\ +"-0.4033,-0.3867,-0.3740,-0.3418,-0.2949,-0.1904,0.0020",\ +"-0.4542,-0.4376,-0.4249,-0.3926,-0.3458,-0.2413,-0.0489"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3089,-0.2933,-0.2806,-0.2523,-0.2015,-0.1029,0.0758",\ +"-0.3140,-0.2983,-0.2856,-0.2573,-0.2065,-0.1079,0.0708",\ +"-0.3184,-0.3028,-0.2901,-0.2617,-0.2110,-0.1123,0.0664",\ +"-0.3282,-0.3126,-0.2999,-0.2716,-0.2208,-0.1222,0.0565",\ +"-0.3346,-0.3189,-0.3062,-0.2779,-0.2271,-0.1285,0.0502",\ +"-0.3711,-0.3554,-0.3427,-0.3144,-0.2636,-0.1650,0.0137",\ +"-0.4219,-0.4063,-0.3936,-0.3653,-0.3145,-0.2159,-0.0372"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4501,0.4345,0.4218,0.3895,0.3407,0.2421,0.0458",\ +"0.4551,0.4395,0.4268,0.3946,0.3457,0.2471,0.0508",\ +"0.4595,0.4439,0.4312,0.3990,0.3502,0.2515,0.0552",\ +"0.4694,0.4537,0.4411,0.4088,0.3600,0.2614,0.0651",\ +"0.4757,0.4601,0.4474,0.4152,0.3663,0.2677,0.0714",\ +"0.5122,0.4966,0.4839,0.4517,0.4028,0.3042,0.1079",\ +"0.5631,0.5475,0.5348,0.5025,0.4537,0.3551,0.1588"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4100,0.3954,0.3817,0.3534,0.3026,0.2099,0.0214",\ +"0.4151,0.4004,0.3867,0.3584,0.3076,0.2149,0.0264",\ +"0.4195,0.4048,0.3912,0.3628,0.3121,0.2193,0.0308",\ +"0.4293,0.4147,0.4010,0.3727,0.3219,0.2291,0.0407",\ +"0.4357,0.4210,0.4074,0.3790,0.3283,0.2355,0.0470",\ +"0.4722,0.4575,0.4438,0.4155,0.3647,0.2720,0.0835",\ +"0.5230,0.5084,0.4947,0.4664,0.4156,0.3228,0.1344"); + } + } + } + + pin(A_BIST_EN) { + direction : input ; + capacitance : 0.00401111 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_BIST_ADDR) { + bus_type : A_9_0; + direction : input ; + capacitance : 0.00721489 ; + pin(A_BIST_ADDR[0]) { + capacitance : 0.00593979 ; + } + pin(A_BIST_ADDR[1]) { + capacitance : 0.00483009 ; + } + pin(A_BIST_ADDR[2]) { + capacitance : 0.006215 ; + } + pin(A_BIST_ADDR[3]) { + capacitance : 0.00766726 ; + } + pin(A_BIST_ADDR[4]) { + capacitance : 0.00488951 ; + } + pin(A_BIST_ADDR[5]) { + capacitance : 0.0091523 ; + } + pin(A_BIST_ADDR[6]) { + capacitance : 0.0109212 ; + } + pin(A_BIST_ADDR[7]) { + capacitance : 0.00774122 ; + } + pin(A_BIST_ADDR[8]) { + capacitance : 0.0101403 ; + } + max_transition : "0.476" ; + pin(A_BIST_ADDR[9:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0120); + } + fall_power("scalar"){ + values (0.0063); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0204); + } + fall_power("scalar"){ + values (0.0012); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4168,-0.3973,-0.3855,-0.3543,-0.3074,-0.2020,-0.0027",\ +"-0.4324,-0.4129,-0.4012,-0.3699,-0.3191,-0.2176,-0.0184",\ +"-0.4441,-0.4285,-0.4129,-0.3816,-0.3309,-0.2293,-0.0301",\ +"-0.4793,-0.4598,-0.4441,-0.4129,-0.3660,-0.2645,-0.0652",\ +"-0.5223,-0.5066,-0.4910,-0.4598,-0.4129,-0.3074,-0.1121",\ +"-0.6199,-0.6082,-0.5926,-0.5613,-0.5145,-0.4129,-0.2137",\ +"-0.8191,-0.8074,-0.7840,-0.7566,-0.7098,-0.6082,-0.4051"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3309,-0.3113,-0.2996,-0.2684,-0.2176,-0.1238,0.0637",\ +"-0.3465,-0.3309,-0.3152,-0.2840,-0.2332,-0.1395,0.0480",\ +"-0.3582,-0.3426,-0.3270,-0.2996,-0.2488,-0.1512,0.0324",\ +"-0.3895,-0.3738,-0.3582,-0.3309,-0.2801,-0.1863,0.0051",\ +"-0.4363,-0.4207,-0.4051,-0.3777,-0.3230,-0.2293,-0.0379",\ +"-0.5379,-0.5223,-0.5066,-0.4793,-0.4285,-0.3309,-0.1434",\ +"-0.7332,-0.7176,-0.7020,-0.6746,-0.6238,-0.5262,-0.3387"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5246,0.5051,0.4895,0.4582,0.4113,0.3059,0.1066",\ +"0.5402,0.5207,0.5051,0.4777,0.4270,0.3215,0.1223",\ +"0.5520,0.5324,0.5168,0.4895,0.4387,0.3371,0.1340",\ +"0.5832,0.5676,0.5520,0.5207,0.4738,0.3684,0.1691",\ +"0.6301,0.6105,0.5949,0.5676,0.5168,0.4113,0.2160",\ +"0.7316,0.7121,0.7004,0.6691,0.6223,0.5168,0.3176",\ +"0.9270,0.9230,0.8957,0.8645,0.8137,0.7121,0.5168"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4309,0.4152,0.4035,0.3684,0.3215,0.2277,0.0363",\ +"0.4465,0.4309,0.4152,0.3879,0.3371,0.2395,0.0559",\ +"0.4582,0.4426,0.4309,0.3996,0.3488,0.2551,0.0715",\ +"0.4934,0.4777,0.4621,0.4348,0.3840,0.2863,0.0988",\ +"0.5363,0.5207,0.5051,0.4777,0.4270,0.3332,0.1418",\ +"0.6379,0.6262,0.6105,0.5793,0.5324,0.4348,0.2434",\ +"0.8332,0.8215,0.8059,0.7707,0.7238,0.6301,0.4387"); + } + } +} +pin(A_BIST_WEN) { + direction : input ; + capacitance : 0.00324098 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0046); + } + fall_power("scalar"){ + values (0.0039); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0043); + } + fall_power("scalar"){ + values (0.0040); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2629,0.3059,0.4113,0.6066",\ +"0.1887,0.2043,0.2160,0.2473,0.2941,0.3957,0.5949",\ +"0.1691,0.1848,0.2004,0.2316,0.2785,0.3801,0.5754",\ +"0.1379,0.1574,0.1691,0.2004,0.2473,0.3527,0.5480",\ +"0.0910,0.1066,0.1223,0.1535,0.2004,0.2980,0.4973",\ +"-0.0105,0.0051,0.0207,0.0520,0.0949,0.2004,0.3957",\ +"-0.2059,-0.1902,-0.1746,-0.1473,-0.1004,0.0051,0.2004"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2941,0.3098,0.3215,0.3488,0.4035,0.4973,0.6887",\ +"0.2785,0.2941,0.3059,0.3332,0.3840,0.4816,0.6691",\ +"0.2629,0.2785,0.2902,0.3176,0.3684,0.4660,0.6535",\ +"0.2316,0.2473,0.2590,0.2863,0.3410,0.4348,0.6262",\ +"0.1848,0.2004,0.2121,0.2395,0.2902,0.3879,0.5754",\ +"0.0832,0.0988,0.1105,0.1379,0.1809,0.2746,0.4699",\ +"-0.1121,-0.0965,-0.0848,-0.0535,-0.0066,0.0910,0.2824"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2473,0.2316,0.2160,0.1887,0.1379,0.0363,-0.1629",\ +"0.2629,0.2473,0.2316,0.2043,0.1535,0.0520,-0.1473",\ +"0.2785,0.2590,0.2434,0.2160,0.1652,0.0676,-0.1355",\ +"0.3098,0.2941,0.2785,0.2473,0.1965,0.0910,-0.1043",\ +"0.3527,0.3371,0.3215,0.2941,0.2434,0.1418,-0.0574",\ +"0.4582,0.4426,0.4270,0.3957,0.3488,0.2434,0.0480",\ +"0.6535,0.6379,0.6184,0.5910,0.5402,0.4426,0.2434"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2395,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2668,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2395,0.1887,0.0910,-0.0965",\ +"0.3449,0.3293,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4191,0.3879,0.3371,0.2395,0.0559",\ +"0.6457,0.6301,0.6145,0.5871,0.5324,0.4309,0.2512"); + } + } + } +pin(A_BIST_REN) { + direction : input ; + capacitance : 0.00381634 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0061); + } + fall_power("scalar"){ + values (0.0021); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0062); + } + fall_power("scalar"){ + values (0.0025); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.0301,-0.0145,0.0012,0.0324,0.0793,0.1809,0.3762",\ +"-0.0457,-0.0301,-0.0145,0.0168,0.0637,0.1613,0.3605",\ +"-0.0574,-0.0418,-0.0262,0.0051,0.0520,0.1496,0.3449",\ +"-0.0926,-0.0730,-0.0574,-0.0262,0.0207,0.1184,0.3137",\ +"-0.1395,-0.1238,-0.1082,-0.0770,-0.0301,0.0715,0.2707",\ +"-0.2410,-0.2254,-0.2098,-0.1746,-0.1355,-0.0340,0.1652",\ +"-0.4402,-0.4207,-0.4051,-0.3738,-0.3270,-0.2293,-0.0340"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.0988,0.1145,0.1262,0.1535,0.2043,0.3020,0.4855",\ +"0.0832,0.0988,0.1105,0.1418,0.1848,0.2824,0.4738",\ +"0.0676,0.0832,0.0949,0.1262,0.1730,0.2668,0.4621",\ +"0.0402,0.0559,0.0676,0.0988,0.1457,0.2434,0.4191",\ +"-0.0105,0.0012,0.0168,0.0480,0.0988,0.1965,0.3840",\ +"-0.1160,-0.0965,-0.0848,-0.0535,-0.0066,0.0988,0.2824",\ +"-0.3113,-0.2957,-0.2801,-0.2527,-0.2059,-0.1043,0.0832"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2707,0.2551,0.2395,0.2121,0.1613,0.0598,-0.1395",\ +"0.2863,0.2707,0.2551,0.2238,0.1730,0.0715,-0.1238",\ +"0.2980,0.2824,0.2668,0.2395,0.1887,0.0871,-0.1121",\ +"0.3332,0.3176,0.3020,0.2707,0.2199,0.1184,-0.0809",\ +"0.3762,0.3605,0.3449,0.3176,0.2668,0.1613,-0.0340",\ +"0.4816,0.4621,0.4504,0.4191,0.3723,0.2629,0.0715",\ +"0.6770,0.6613,0.6418,0.6184,0.5637,0.4699,0.2629"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2590,0.2434,0.2316,0.2004,0.1457,0.0520,-0.1355",\ +"0.2746,0.2590,0.2434,0.2160,0.1613,0.0676,-0.1199",\ +"0.2863,0.2707,0.2590,0.2277,0.1730,0.0832,-0.1082",\ +"0.3215,0.3059,0.2902,0.2590,0.2082,0.1105,-0.0770",\ +"0.3645,0.3488,0.3332,0.3059,0.2551,0.1535,-0.0340",\ +"0.4699,0.4543,0.4387,0.4074,0.3605,0.2551,0.0715",\ +"0.6652,0.6496,0.6340,0.6027,0.5520,0.4621,0.2707"); + } + } + } +pin(A_BIST_MEN) { + direction : input ; + capacitance : 0.00309605 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0448); + } + fall_power("scalar"){ + values (0.0052); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2668,0.3098,0.4152,0.6066",\ +"0.1887,0.2043,0.2199,0.2512,0.2941,0.3996,0.5949",\ +"0.1730,0.1887,0.2043,0.2355,0.2824,0.3840,0.5793",\ +"0.1418,0.1574,0.1730,0.2043,0.2512,0.3566,0.5480",\ +"0.0949,0.1105,0.1262,0.1574,0.2043,0.3020,0.5051",\ +"-0.0066,0.0090,0.0246,0.0520,0.0988,0.2043,0.3996",\ +"-0.2020,-0.1863,-0.1746,-0.1434,-0.0965,0.0090,0.2082"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2980,0.3137,0.3254,0.3527,0.4035,0.5012,0.6887",\ +"0.2824,0.2980,0.3098,0.3371,0.3879,0.4855,0.6730",\ +"0.2668,0.2824,0.2941,0.3215,0.3723,0.4699,0.6574",\ +"0.2355,0.2473,0.2629,0.2902,0.3410,0.4387,0.6262",\ +"0.1887,0.2004,0.2160,0.2395,0.2941,0.3918,0.5793",\ +"0.0871,0.1027,0.1145,0.1418,0.1848,0.2746,0.4816",\ +"-0.1082,-0.0965,-0.0809,-0.0496,-0.0027,0.0949,0.2863"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2512,0.2355,0.2199,0.1926,0.1418,0.0402,-0.1590",\ +"0.2668,0.2512,0.2355,0.2082,0.1574,0.0559,-0.1434",\ +"0.2824,0.2629,0.2512,0.2199,0.1691,0.0715,-0.1316",\ +"0.3137,0.2980,0.2824,0.2512,0.2004,0.0988,-0.0965",\ +"0.3566,0.3410,0.3254,0.2980,0.2473,0.1418,-0.0535",\ +"0.4621,0.4426,0.4309,0.3996,0.3527,0.2473,0.0520",\ +"0.6574,0.6418,0.6262,0.5949,0.5441,0.4465,0.2473"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2434,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2707,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2434,0.1926,0.0910,-0.0965",\ +"0.3449,0.3332,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4230,0.3918,0.3410,0.2434,0.0559",\ +"0.6457,0.6301,0.6145,0.5910,0.5324,0.4387,0.2512"); + } + } + } +bus(A_BIST_BM) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00238379 ; + max_transition : "0.476" ; + pin(A_BIST_BM[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0592); + } + fall_power("scalar"){ + values (0.0247); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0603); + } + fall_power("scalar"){ + values (0.0245); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3412,-0.3246,-0.3119,-0.2796,-0.2328,-0.1283,0.0641",\ +"-0.3462,-0.3296,-0.3169,-0.2847,-0.2378,-0.1333,0.0591",\ +"-0.3506,-0.3340,-0.3213,-0.2891,-0.2422,-0.1377,0.0547",\ +"-0.3605,-0.3439,-0.3312,-0.2989,-0.2521,-0.1476,0.0448",\ +"-0.3668,-0.3502,-0.3375,-0.3053,-0.2584,-0.1539,0.0385",\ +"-0.4033,-0.3867,-0.3740,-0.3418,-0.2949,-0.1904,0.0020",\ +"-0.4542,-0.4376,-0.4249,-0.3926,-0.3458,-0.2413,-0.0489"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3089,-0.2933,-0.2806,-0.2523,-0.2015,-0.1029,0.0758",\ +"-0.3140,-0.2983,-0.2856,-0.2573,-0.2065,-0.1079,0.0708",\ +"-0.3184,-0.3028,-0.2901,-0.2617,-0.2110,-0.1123,0.0664",\ +"-0.3282,-0.3126,-0.2999,-0.2716,-0.2208,-0.1222,0.0565",\ +"-0.3346,-0.3189,-0.3062,-0.2779,-0.2271,-0.1285,0.0502",\ +"-0.3711,-0.3554,-0.3427,-0.3144,-0.2636,-0.1650,0.0137",\ +"-0.4219,-0.4063,-0.3936,-0.3653,-0.3145,-0.2159,-0.0372"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4501,0.4345,0.4218,0.3895,0.3407,0.2421,0.0458",\ +"0.4551,0.4395,0.4268,0.3946,0.3457,0.2471,0.0508",\ +"0.4595,0.4439,0.4312,0.3990,0.3502,0.2515,0.0552",\ +"0.4694,0.4537,0.4411,0.4088,0.3600,0.2614,0.0651",\ +"0.4757,0.4601,0.4474,0.4152,0.3663,0.2677,0.0714",\ +"0.5122,0.4966,0.4839,0.4517,0.4028,0.3042,0.1079",\ +"0.5631,0.5475,0.5348,0.5025,0.4537,0.3551,0.1588"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4100,0.3954,0.3817,0.3534,0.3026,0.2099,0.0214",\ +"0.4151,0.4004,0.3867,0.3584,0.3076,0.2149,0.0264",\ +"0.4195,0.4048,0.3912,0.3628,0.3121,0.2193,0.0308",\ +"0.4293,0.4147,0.4010,0.3727,0.3219,0.2291,0.0407",\ +"0.4357,0.4210,0.4074,0.3790,0.3283,0.2355,0.0470",\ +"0.4722,0.4575,0.4438,0.4155,0.3647,0.2720,0.0835",\ +"0.5230,0.5084,0.4947,0.4664,0.4156,0.3228,0.1344"); + } + } +} + pin(A_BIST_CLK) { + direction : input; + capacitance : 0.00380014; + max_transition : "0.476"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.0056,0.476"); + values("0.21,0.21"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0.5466); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (32.9180); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (33.7600); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (26.4863); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.3253); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.7651); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_BIST_DIN) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00233858 ; + memory_write() { + address : A_BIST_ADDR ; + clocked_on : A_BIST_CLK; + } + + max_transition : "0.476" ; + pin(A_BIST_DIN[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0592); + } + fall_power("scalar"){ + values (0.0247); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0603); + } + fall_power("scalar"){ + values (0.0245); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3412,-0.3246,-0.3119,-0.2796,-0.2328,-0.1283,0.0641",\ +"-0.3462,-0.3296,-0.3169,-0.2847,-0.2378,-0.1333,0.0591",\ +"-0.3506,-0.3340,-0.3213,-0.2891,-0.2422,-0.1377,0.0547",\ +"-0.3605,-0.3439,-0.3312,-0.2989,-0.2521,-0.1476,0.0448",\ +"-0.3668,-0.3502,-0.3375,-0.3053,-0.2584,-0.1539,0.0385",\ +"-0.4033,-0.3867,-0.3740,-0.3418,-0.2949,-0.1904,0.0020",\ +"-0.4542,-0.4376,-0.4249,-0.3926,-0.3458,-0.2413,-0.0489"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3089,-0.2933,-0.2806,-0.2523,-0.2015,-0.1029,0.0758",\ +"-0.3140,-0.2983,-0.2856,-0.2573,-0.2065,-0.1079,0.0708",\ +"-0.3184,-0.3028,-0.2901,-0.2617,-0.2110,-0.1123,0.0664",\ +"-0.3282,-0.3126,-0.2999,-0.2716,-0.2208,-0.1222,0.0565",\ +"-0.3346,-0.3189,-0.3062,-0.2779,-0.2271,-0.1285,0.0502",\ +"-0.3711,-0.3554,-0.3427,-0.3144,-0.2636,-0.1650,0.0137",\ +"-0.4219,-0.4063,-0.3936,-0.3653,-0.3145,-0.2159,-0.0372"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4501,0.4345,0.4218,0.3895,0.3407,0.2421,0.0458",\ +"0.4551,0.4395,0.4268,0.3946,0.3457,0.2471,0.0508",\ +"0.4595,0.4439,0.4312,0.3990,0.3502,0.2515,0.0552",\ +"0.4694,0.4537,0.4411,0.4088,0.3600,0.2614,0.0651",\ +"0.4757,0.4601,0.4474,0.4152,0.3663,0.2677,0.0714",\ +"0.5122,0.4966,0.4839,0.4517,0.4028,0.3042,0.1079",\ +"0.5631,0.5475,0.5348,0.5025,0.4537,0.3551,0.1588"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4100,0.3954,0.3817,0.3534,0.3026,0.2099,0.0214",\ +"0.4151,0.4004,0.3867,0.3584,0.3076,0.2149,0.0264",\ +"0.4195,0.4048,0.3912,0.3628,0.3121,0.2193,0.0308",\ +"0.4293,0.4147,0.4010,0.3727,0.3219,0.2291,0.0407",\ +"0.4357,0.4210,0.4074,0.3790,0.3283,0.2355,0.0470",\ +"0.4722,0.4575,0.4438,0.4155,0.3647,0.2720,0.0835",\ +"0.5230,0.5084,0.4947,0.4664,0.4156,0.3228,0.1344"); + } + } + } + +bus(A_DOUT) { + + bus_type : D_15_0; + direction : output ; + capacitance : 0 ; + max_capacitance : "6.4e-14" ; + memory_read() { + address : A_ADDR ; + } + pin(A_DOUT[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "A_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("4.2547,4.2563,4.2639,4.2726,4.3051,4.3409",\ +"4.2648,4.2664,4.2740,4.2828,4.3152,4.3511",\ +"4.2694,4.2710,4.2787,4.2874,4.3198,4.3557",\ +"4.2772,4.2788,4.2865,4.2952,4.3276,4.3635",\ +"4.2847,4.2863,4.2940,4.3027,4.3351,4.3710",\ +"4.3198,4.3214,4.3291,4.3378,4.3702,4.4061",\ +"4.3732,4.3748,4.3824,4.3911,4.4236,4.4594"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("4.1936,4.1949,4.2009,4.2081,4.2346,4.2612",\ +"4.2037,4.2050,4.2110,4.2182,4.2447,4.2713",\ +"4.2083,4.2097,4.2157,4.2228,4.2493,4.2759",\ +"4.2161,4.2175,4.2235,4.2306,4.2571,4.2837",\ +"4.2237,4.2250,4.2310,4.2381,4.2646,4.2913",\ +"4.2587,4.2601,4.2661,4.2732,4.2997,4.3264",\ +"4.3121,4.3134,4.3194,4.3266,4.3531,4.3797"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0326,0.0341,0.0428,0.0518,0.0923,0.1492"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0254,0.0265,0.0335,0.0402,0.0707,0.1039"); + } + } +} +cell_leakage_power : 198.0155; +} +} diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_1024x8_c2_bm_bist_fast_1p32V_m55C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_1024x8_c2_bm_bist_fast_1p32V_m55C.lib new file mode 100644 index 0000000000..1010183c63 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_1024x8_c2_bm_bist_fast_1p32V_m55C.lib @@ -0,0 +1,1525 @@ +/* ------------------------------------------------------*/ +/**/ +/* Copyright 2024 IHP PDK Authors*/ +/**/ +/* Licensed under the Apache License, Version 2.0 (the "License");*/ +/* you may not use this file except in compliance with the License.*/ +/* You may obtain a copy of the License at*/ +/* */ +/* https://www.apache.org/licenses/LICENSE-2.0*/ +/* */ +/* Unless required by applicable law or agreed to in writing, software*/ +/* distributed under the License is distributed on an "AS IS" BASIS,*/ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/ +/* See the License for the specific language governing permissions and*/ +/* limitations under the License.*/ +/* */ +/* Generated on Fri Jul 19 09:01:12 2024 */ +/* */ +/* ------------------------------------------------------ */ +library(RM_IHPSG13_1P_1024x8_c2_bm_bist_fast_1p32V_m55C) { + technology (cmos) ; + delay_model : table_lookup ; + define ("add_pg_pin_to_lib", "library", "boolean"); + add_pg_pin_to_lib : true; + voltage_map ( VDD, 1.32); + voltage_map ( VDDARRAY, 1.32); + voltage_map ( VSS, 0.000000 ); + + date : "Fri Jul 19 09:01:10 2024" ; + comment : "IHP Microelectronics GmbH, 2024" ; + revision : 1.0.0 ; + simulation : true ; + nom_process : 1 ; + nom_temperature : -55 ; + nom_voltage : 1.32 ; + + operating_conditions("fast_1p32V_m55C"){ + process : 1 ; + temperature : -55 ; + voltage : 1.32 ; + tree_type : "balanced_tree" ; + } + + default_operating_conditions : fast_1p32V_m55C ; + default_max_transition : 1.0 ; + default_fanout_load : 1.0 ; + default_inout_pin_cap : 0.0 ; + default_input_pin_cap : 0.0 ; + default_output_pin_cap : 0.0 ; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + + slew_lower_threshold_pct_rise : 30 ; + slew_upper_threshold_pct_rise : 70 ; + input_threshold_pct_fall : 50 ; + output_threshold_pct_fall : 50 ; + input_threshold_pct_rise : 50 ; + output_threshold_pct_rise : 50 ; + slew_lower_threshold_pct_fall : 30 ; + slew_upper_threshold_pct_fall : 70 ; + slew_derate_from_library : 0.5; + k_volt_cell_leakage_power : 0.0 ; + k_temp_cell_leakage_power : 0.0 ; + k_process_cell_leakage_power : 0.0 ; + k_volt_internal_power : 0.0 ; + k_temp_internal_power : 0.0 ; + k_process_internal_power : 0.0 ; + + capacitive_load_unit (1,pf) ; + voltage_unit : "1V" ; + current_unit : "1uA" ; + time_unit : "1ns" ; + leakage_power_unit : "1nW" ; + pulling_resistance_unit : "1kohm"; + /* + ------------------------------------------------------------------------------------------ + implicit units overview: + cell_area unit : "um" + internal_power unit : "1e-12 * J/toggle = 1 * uW/MHz" + (capacitive_load_unit * voltage_unit^2) per toggle event + ------------------------------------------------------------------------------------------ + */ + library_features(report_delay_calculation); + define_cell_area (pad_drivers,pad_driver_sites) ; + + lu_table_template(CLKTRAN_constraint_template) { + variable_1 : constrained_pin_transition; + index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" ); + } + lu_table_template(SRAM_load_template) { + variable_1 : total_output_net_capacitance; + index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + lu_table_template(SIG2SRAM_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" ); + index_2 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" ); + } + + lu_table_template(SIG2SRAM_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" ); + index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + + type (D_7_0) { + base_type : array; + data_type : bit; + bit_width : 8; + bit_from : 7; + bit_to : 0; + downto : true; + } + + type (A_9_0) { + base_type : array; + data_type : bit; + bit_width : 10; + bit_from : 9; + bit_to : 0; + downto : true; + } + +cell(RM_IHPSG13_1P_1024x8_c2_bm_bist) { +pg_pin (VDD) { + pg_type : primary_power; + voltage_name : VDD; +} +pg_pin (VDDARRAY) { + pg_type : primary_power; + voltage_name : VDDARRAY; +} +pg_pin (VSS) { + pg_type : primary_ground; + voltage_name : VSS; +} + +memory() { + type : ram; + address_width : 10; + word_width : 8; +} + +interface_timing : false; +bus_naming_style : "%s[%d]" ; +area : 49419.2448 ; + + pin(A_DLY) { + direction : input ; + capacitance : 0.00421562 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_ADDR) { + bus_type : A_9_0; + direction : input ; + capacitance : 0.00691085 ; + pin(A_ADDR[0]) { + capacitance : 0.00562034 ; + } + pin(A_ADDR[1]) { + capacitance : 0.00462655 ; + } + pin(A_ADDR[2]) { + capacitance : 0.00594295 ; + } + pin(A_ADDR[3]) { + capacitance : 0.00723434 ; + } + pin(A_ADDR[4]) { + capacitance : 0.00481603 ; + } + pin(A_ADDR[5]) { + capacitance : 0.00868123 ; + } + pin(A_ADDR[6]) { + capacitance : 0.010187 ; + } + pin(A_ADDR[7]) { + capacitance : 0.00734489 ; + } + pin(A_ADDR[8]) { + capacitance : 0.00904175 ; + } + max_transition : "0.38" ; + pin(A_ADDR[9:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0799); + } + fall_power("scalar"){ + values (0.0925); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0267); + } + fall_power("scalar"){ + values (0.0027); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2371,-0.2215,-0.2098,-0.1824,-0.1434,-0.0691,0.0676",\ +"-0.2449,-0.2332,-0.2176,-0.1902,-0.1551,-0.0770,0.0559",\ +"-0.2605,-0.2488,-0.2332,-0.2059,-0.1707,-0.0965,0.0441",\ +"-0.2879,-0.2723,-0.2605,-0.2332,-0.1941,-0.1199,0.0168",\ +"-0.3230,-0.3113,-0.2996,-0.2723,-0.2332,-0.1590,-0.0184",\ +"-0.4012,-0.3895,-0.3738,-0.3465,-0.3074,-0.2332,-0.0965",\ +"-0.5379,-0.5262,-0.5105,-0.4832,-0.4480,-0.3699,-0.2332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1785,-0.1707,-0.1551,-0.1277,-0.0887,-0.0184,0.1145",\ +"-0.1902,-0.1785,-0.1629,-0.1355,-0.1004,-0.0262,0.1027",\ +"-0.2059,-0.1941,-0.1785,-0.1512,-0.1160,-0.0418,0.0871",\ +"-0.2293,-0.2176,-0.2059,-0.1785,-0.1434,-0.0691,0.0598",\ +"-0.2684,-0.2566,-0.2449,-0.2176,-0.1824,-0.1082,0.0207",\ +"-0.3465,-0.3348,-0.3191,-0.2918,-0.2566,-0.1824,-0.0535",\ +"-0.4832,-0.4715,-0.4559,-0.4324,-0.3934,-0.3191,-0.1902"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3410,0.3293,0.3137,0.2863,0.2473,0.1730,0.0324",\ +"0.3488,0.3371,0.3215,0.2941,0.2590,0.1809,0.0480",\ +"0.3684,0.3527,0.3371,0.3098,0.2746,0.1965,0.0598",\ +"0.3918,0.3762,0.3645,0.3371,0.2980,0.2238,0.0871",\ +"0.4309,0.4152,0.4035,0.3762,0.3371,0.2629,0.1223",\ +"0.5051,0.4934,0.4777,0.4504,0.4113,0.3371,0.1965",\ +"0.6418,0.6262,0.6145,0.5871,0.5520,0.4738,0.3332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2824,0.2707,0.2551,0.2277,0.1926,0.1184,-0.0105",\ +"0.2902,0.2785,0.2668,0.2395,0.2043,0.1301,0.0012",\ +"0.3059,0.2941,0.2824,0.2551,0.2199,0.1457,0.0168",\ +"0.3332,0.3215,0.3059,0.2785,0.2434,0.1691,0.0402",\ +"0.3723,0.3605,0.3449,0.3176,0.2824,0.2121,0.0793",\ +"0.4465,0.4348,0.4230,0.3918,0.3566,0.2824,0.1535",\ +"0.5832,0.5715,0.5598,0.5324,0.4934,0.4191,0.2902"); + } + } +} +pin(A_WEN) { + direction : input ; + capacitance : 0.00341384 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.1397); + } + fall_power("scalar"){ + values (0.0161); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0060); + } + fall_power("scalar"){ + values (0.0209); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1887,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3527",\ +"-0.0262,-0.0145,0.0012,0.0246,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1418"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2160,0.2316,0.2590,0.2941,0.3684,0.5012",\ +"0.1926,0.2043,0.2199,0.2473,0.2824,0.3566,0.4895",\ +"0.1770,0.1887,0.2043,0.2316,0.2668,0.3410,0.4777",\ +"0.1535,0.1652,0.1770,0.2043,0.2395,0.3137,0.4504",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2746,0.4113",\ +"0.0402,0.0520,0.0676,0.0910,0.1262,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0730,-0.0457,-0.0066,0.0637,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1496,0.1223,0.0793,0.0090,-0.1316",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0168,-0.1199",\ +"0.2004,0.1887,0.1770,0.1496,0.1066,0.0363,-0.1043",\ +"0.2277,0.2160,0.2004,0.1730,0.1340,0.0598,-0.0809",\ +"0.2668,0.2551,0.2395,0.2121,0.1730,0.0988,-0.0418",\ +"0.3410,0.3293,0.3137,0.2863,0.2434,0.1730,0.0324",\ +"0.4816,0.4699,0.4543,0.4230,0.3801,0.3098,0.1730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1066,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1457,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1613,0.1340,0.0988,0.0246,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2512,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0457",\ +"0.3254,0.3176,0.3020,0.2746,0.2355,0.1652,0.0324",\ +"0.4660,0.4543,0.4387,0.4113,0.3723,0.3020,0.1691"); + } + } + } +pin(A_REN) { + direction : input ; + capacitance : 0.00390661 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0111); + } + fall_power("scalar"){ + values (0.0105); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0257); + } + fall_power("scalar"){ + values (0.0199); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.0027,0.0090,0.0246,0.0520,0.0910,0.1613,0.3020",\ +"-0.0105,0.0012,0.0129,0.0363,0.0793,0.1535,0.2902",\ +"-0.0262,-0.0145,-0.0027,0.0246,0.0637,0.1379,0.2785",\ +"-0.0535,-0.0418,-0.0262,0.0012,0.0363,0.1105,0.2512",\ +"-0.0926,-0.0809,-0.0652,-0.0418,-0.0027,0.0715,0.2121",\ +"-0.1668,-0.1551,-0.1395,-0.1082,-0.0770,-0.0027,0.1379",\ +"-0.3035,-0.2918,-0.2762,-0.2488,-0.2137,-0.1434,-0.0027"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.0832,0.0949,0.1105,0.1379,0.1730,0.2473,0.3801",\ +"0.0754,0.0832,0.0988,0.1223,0.1613,0.2355,0.3684",\ +"0.0598,0.0676,0.0832,0.1066,0.1457,0.2121,0.3527",\ +"0.0324,0.0441,0.0598,0.0871,0.1223,0.1926,0.3293",\ +"-0.0066,0.0051,0.0168,0.0480,0.0832,0.1535,0.2902",\ +"-0.0809,-0.0691,-0.0574,-0.0301,0.0090,0.0832,0.2121",\ +"-0.2176,-0.2059,-0.1941,-0.1668,-0.1277,-0.0574,0.0793"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1160",\ +"0.1965,0.1848,0.1730,0.1457,0.1027,0.0324,-0.1082",\ +"0.2160,0.2004,0.1887,0.1613,0.1184,0.0480,-0.0926",\ +"0.2395,0.2277,0.2121,0.1848,0.1457,0.0715,-0.0652",\ +"0.2785,0.2668,0.2512,0.2238,0.1848,0.1105,-0.0262",\ +"0.3527,0.3410,0.3254,0.2980,0.2551,0.1848,0.0480",\ +"0.4934,0.4816,0.4660,0.4387,0.3957,0.3254,0.1887"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1730,0.1613,0.1496,0.1184,0.0793,0.0129,-0.1238",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0207,-0.1121",\ +"0.2004,0.1887,0.1730,0.1457,0.1066,0.0363,-0.1004",\ +"0.2238,0.2121,0.2004,0.1691,0.1340,0.0598,-0.0730",\ +"0.2629,0.2512,0.2395,0.2121,0.1691,0.0988,-0.0340",\ +"0.3371,0.3254,0.3137,0.2863,0.2434,0.1730,0.0402",\ +"0.4777,0.4660,0.4504,0.4230,0.3840,0.3137,0.1809"); + } + } + } +pin(A_MEN) { + direction : input ; + capacitance : 0.00326046 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0783); + } + fall_power("scalar"){ + values (0.0772); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1926,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1418,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3488",\ +"-0.0262,-0.0145,0.0012,0.0285,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1379"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2199,0.2316,0.2590,0.2980,0.3723,0.5051",\ +"0.1965,0.2082,0.2199,0.2473,0.2863,0.3605,0.4934",\ +"0.1809,0.1926,0.2043,0.2316,0.2707,0.3449,0.4777",\ +"0.1574,0.1691,0.1809,0.2082,0.2434,0.3176,0.4543",\ +"0.1145,0.1262,0.1418,0.1691,0.2043,0.2785,0.4113",\ +"0.0441,0.0559,0.0676,0.0949,0.1301,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0691,-0.0418,-0.0066,0.0676,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1535,0.1262,0.0832,0.0129,-0.1277",\ +"0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1199",\ +"0.2043,0.1926,0.1770,0.1496,0.1105,0.0363,-0.1043",\ +"0.2277,0.2160,0.2043,0.1770,0.1379,0.0598,-0.0770",\ +"0.2668,0.2551,0.2434,0.2160,0.1730,0.0988,-0.0379",\ +"0.3449,0.3332,0.3176,0.2902,0.2473,0.1730,0.0363",\ +"0.4816,0.4699,0.4543,0.4270,0.3840,0.3098,0.1770"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1105,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1496,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1652,0.1340,0.0988,0.0285,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2551,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0418",\ +"0.3293,0.3176,0.3020,0.2746,0.2395,0.1652,0.0324",\ +"0.4660,0.4543,0.4426,0.4113,0.3762,0.3020,0.1691"); + } + } + } +bus(A_BM) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00310985 ; + max_transition : "0.38" ; + pin(A_BM[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0418); + } + fall_power("scalar"){ + values (0.0388); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0592); + } + fall_power("scalar"){ + values (0.0451); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1576,-0.1468,-0.1312,-0.1048,-0.0648,0.0055,0.1403",\ +"-0.1615,-0.1507,-0.1351,-0.1087,-0.0687,0.0016,0.1364",\ +"-0.1652,-0.1545,-0.1389,-0.1125,-0.0725,-0.0022,0.1326",\ +"-0.1685,-0.1578,-0.1421,-0.1158,-0.0757,-0.0054,0.1293",\ +"-0.1809,-0.1702,-0.1546,-0.1282,-0.0882,-0.0179,0.1169",\ +"-0.1984,-0.1877,-0.1720,-0.1457,-0.1056,-0.0353,0.0994",\ +"-0.2261,-0.2153,-0.1997,-0.1733,-0.1333,-0.0630,0.0718"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1351,-0.1244,-0.1107,-0.0834,-0.0462,0.0260,0.1559",\ +"-0.1390,-0.1282,-0.1146,-0.0872,-0.0501,0.0221,0.1520",\ +"-0.1428,-0.1320,-0.1184,-0.0910,-0.0539,0.0183,0.1482",\ +"-0.1460,-0.1353,-0.1216,-0.0943,-0.0572,0.0151,0.1450",\ +"-0.1585,-0.1477,-0.1341,-0.1067,-0.0696,0.0026,0.1325",\ +"-0.1759,-0.1652,-0.1515,-0.1242,-0.0871,-0.0148,0.1151",\ +"-0.2036,-0.1929,-0.1792,-0.1518,-0.1147,-0.0425,0.0874"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2635,0.2517,0.2371,0.2107,0.1707,0.0994,-0.0373",\ +"0.2673,0.2556,0.2410,0.2146,0.1746,0.1033,-0.0334",\ +"0.2711,0.2594,0.2448,0.2184,0.1784,0.1071,-0.0296",\ +"0.2744,0.2627,0.2480,0.2217,0.1816,0.1103,-0.0264",\ +"0.2868,0.2751,0.2605,0.2341,0.1941,0.1228,-0.0139",\ +"0.3043,0.2926,0.2779,0.2516,0.2115,0.1402,0.0035",\ +"0.3320,0.3202,0.3056,0.2792,0.2392,0.1679,0.0312"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2351,0.2254,0.2107,0.1844,0.1473,0.0740,-0.0539",\ +"0.2390,0.2293,0.2146,0.1882,0.1511,0.0779,-0.0500",\ +"0.2428,0.2331,0.2184,0.1920,0.1549,0.0817,-0.0462",\ +"0.2461,0.2363,0.2217,0.1953,0.1582,0.0849,-0.0430",\ +"0.2585,0.2488,0.2341,0.2077,0.1706,0.0974,-0.0305",\ +"0.2760,0.2662,0.2516,0.2252,0.1881,0.1149,-0.0131",\ +"0.3036,0.2939,0.2792,0.2529,0.2157,0.1425,0.0146"); + } + } +} + pin(A_CLK) { + direction : input; + capacitance : 0.00389386; + max_transition : "0.38"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.004,0.38"); + values("0.12,0.12"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (0.6944); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (24.3582); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (24.1537); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (19.6992); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (0.4036); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (0.6774); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_DIN) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00387207 ; + memory_write() { + address : A_ADDR ; + clocked_on : A_CLK; + } + + max_transition : "0.38" ; + pin(A_DIN[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0418); + } + fall_power("scalar"){ + values (0.0388); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0592); + } + fall_power("scalar"){ + values (0.0451); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1576,-0.1468,-0.1312,-0.1048,-0.0648,0.0055,0.1403",\ +"-0.1615,-0.1507,-0.1351,-0.1087,-0.0687,0.0016,0.1364",\ +"-0.1652,-0.1545,-0.1389,-0.1125,-0.0725,-0.0022,0.1326",\ +"-0.1685,-0.1578,-0.1421,-0.1158,-0.0757,-0.0054,0.1293",\ +"-0.1809,-0.1702,-0.1546,-0.1282,-0.0882,-0.0179,0.1169",\ +"-0.1984,-0.1877,-0.1720,-0.1457,-0.1056,-0.0353,0.0994",\ +"-0.2261,-0.2153,-0.1997,-0.1733,-0.1333,-0.0630,0.0718"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1351,-0.1244,-0.1107,-0.0834,-0.0462,0.0260,0.1559",\ +"-0.1390,-0.1282,-0.1146,-0.0872,-0.0501,0.0221,0.1520",\ +"-0.1428,-0.1320,-0.1184,-0.0910,-0.0539,0.0183,0.1482",\ +"-0.1460,-0.1353,-0.1216,-0.0943,-0.0572,0.0151,0.1450",\ +"-0.1585,-0.1477,-0.1341,-0.1067,-0.0696,0.0026,0.1325",\ +"-0.1759,-0.1652,-0.1515,-0.1242,-0.0871,-0.0148,0.1151",\ +"-0.2036,-0.1929,-0.1792,-0.1518,-0.1147,-0.0425,0.0874"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2635,0.2517,0.2371,0.2107,0.1707,0.0994,-0.0373",\ +"0.2673,0.2556,0.2410,0.2146,0.1746,0.1033,-0.0334",\ +"0.2711,0.2594,0.2448,0.2184,0.1784,0.1071,-0.0296",\ +"0.2744,0.2627,0.2480,0.2217,0.1816,0.1103,-0.0264",\ +"0.2868,0.2751,0.2605,0.2341,0.1941,0.1228,-0.0139",\ +"0.3043,0.2926,0.2779,0.2516,0.2115,0.1402,0.0035",\ +"0.3320,0.3202,0.3056,0.2792,0.2392,0.1679,0.0312"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2351,0.2254,0.2107,0.1844,0.1473,0.0740,-0.0539",\ +"0.2390,0.2293,0.2146,0.1882,0.1511,0.0779,-0.0500",\ +"0.2428,0.2331,0.2184,0.1920,0.1549,0.0817,-0.0462",\ +"0.2461,0.2363,0.2217,0.1953,0.1582,0.0849,-0.0430",\ +"0.2585,0.2488,0.2341,0.2077,0.1706,0.0974,-0.0305",\ +"0.2760,0.2662,0.2516,0.2252,0.1881,0.1149,-0.0131",\ +"0.3036,0.2939,0.2792,0.2529,0.2157,0.1425,0.0146"); + } + } + } + + pin(A_BIST_EN) { + direction : input ; + capacitance : 0.00421562 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_BIST_ADDR) { + bus_type : A_9_0; + direction : input ; + capacitance : 0.00691085 ; + pin(A_BIST_ADDR[0]) { + capacitance : 0.00562034 ; + } + pin(A_BIST_ADDR[1]) { + capacitance : 0.00462655 ; + } + pin(A_BIST_ADDR[2]) { + capacitance : 0.00594295 ; + } + pin(A_BIST_ADDR[3]) { + capacitance : 0.00723434 ; + } + pin(A_BIST_ADDR[4]) { + capacitance : 0.00481603 ; + } + pin(A_BIST_ADDR[5]) { + capacitance : 0.00868123 ; + } + pin(A_BIST_ADDR[6]) { + capacitance : 0.010187 ; + } + pin(A_BIST_ADDR[7]) { + capacitance : 0.00734489 ; + } + pin(A_BIST_ADDR[8]) { + capacitance : 0.00904175 ; + } + max_transition : "0.38" ; + pin(A_BIST_ADDR[9:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0799); + } + fall_power("scalar"){ + values (0.0925); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0267); + } + fall_power("scalar"){ + values (0.0027); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2371,-0.2215,-0.2098,-0.1824,-0.1434,-0.0691,0.0676",\ +"-0.2449,-0.2332,-0.2176,-0.1902,-0.1551,-0.0770,0.0559",\ +"-0.2605,-0.2488,-0.2332,-0.2059,-0.1707,-0.0965,0.0441",\ +"-0.2879,-0.2723,-0.2605,-0.2332,-0.1941,-0.1199,0.0168",\ +"-0.3230,-0.3113,-0.2996,-0.2723,-0.2332,-0.1590,-0.0184",\ +"-0.4012,-0.3895,-0.3738,-0.3465,-0.3074,-0.2332,-0.0965",\ +"-0.5379,-0.5262,-0.5105,-0.4832,-0.4480,-0.3699,-0.2332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1785,-0.1707,-0.1551,-0.1277,-0.0887,-0.0184,0.1145",\ +"-0.1902,-0.1785,-0.1629,-0.1355,-0.1004,-0.0262,0.1027",\ +"-0.2059,-0.1941,-0.1785,-0.1512,-0.1160,-0.0418,0.0871",\ +"-0.2293,-0.2176,-0.2059,-0.1785,-0.1434,-0.0691,0.0598",\ +"-0.2684,-0.2566,-0.2449,-0.2176,-0.1824,-0.1082,0.0207",\ +"-0.3465,-0.3348,-0.3191,-0.2918,-0.2566,-0.1824,-0.0535",\ +"-0.4832,-0.4715,-0.4559,-0.4324,-0.3934,-0.3191,-0.1902"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3410,0.3293,0.3137,0.2863,0.2473,0.1730,0.0324",\ +"0.3488,0.3371,0.3215,0.2941,0.2590,0.1809,0.0480",\ +"0.3684,0.3527,0.3371,0.3098,0.2746,0.1965,0.0598",\ +"0.3918,0.3762,0.3645,0.3371,0.2980,0.2238,0.0871",\ +"0.4309,0.4152,0.4035,0.3762,0.3371,0.2629,0.1223",\ +"0.5051,0.4934,0.4777,0.4504,0.4113,0.3371,0.1965",\ +"0.6418,0.6262,0.6145,0.5871,0.5520,0.4738,0.3332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2824,0.2707,0.2551,0.2277,0.1926,0.1184,-0.0105",\ +"0.2902,0.2785,0.2668,0.2395,0.2043,0.1301,0.0012",\ +"0.3059,0.2941,0.2824,0.2551,0.2199,0.1457,0.0168",\ +"0.3332,0.3215,0.3059,0.2785,0.2434,0.1691,0.0402",\ +"0.3723,0.3605,0.3449,0.3176,0.2824,0.2121,0.0793",\ +"0.4465,0.4348,0.4230,0.3918,0.3566,0.2824,0.1535",\ +"0.5832,0.5715,0.5598,0.5324,0.4934,0.4191,0.2902"); + } + } +} +pin(A_BIST_WEN) { + direction : input ; + capacitance : 0.00341384 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.1397); + } + fall_power("scalar"){ + values (0.0161); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0060); + } + fall_power("scalar"){ + values (0.0209); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1887,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3527",\ +"-0.0262,-0.0145,0.0012,0.0246,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1418"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2160,0.2316,0.2590,0.2941,0.3684,0.5012",\ +"0.1926,0.2043,0.2199,0.2473,0.2824,0.3566,0.4895",\ +"0.1770,0.1887,0.2043,0.2316,0.2668,0.3410,0.4777",\ +"0.1535,0.1652,0.1770,0.2043,0.2395,0.3137,0.4504",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2746,0.4113",\ +"0.0402,0.0520,0.0676,0.0910,0.1262,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0730,-0.0457,-0.0066,0.0637,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1496,0.1223,0.0793,0.0090,-0.1316",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0168,-0.1199",\ +"0.2004,0.1887,0.1770,0.1496,0.1066,0.0363,-0.1043",\ +"0.2277,0.2160,0.2004,0.1730,0.1340,0.0598,-0.0809",\ +"0.2668,0.2551,0.2395,0.2121,0.1730,0.0988,-0.0418",\ +"0.3410,0.3293,0.3137,0.2863,0.2434,0.1730,0.0324",\ +"0.4816,0.4699,0.4543,0.4230,0.3801,0.3098,0.1730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1066,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1457,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1613,0.1340,0.0988,0.0246,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2512,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0457",\ +"0.3254,0.3176,0.3020,0.2746,0.2355,0.1652,0.0324",\ +"0.4660,0.4543,0.4387,0.4113,0.3723,0.3020,0.1691"); + } + } + } +pin(A_BIST_REN) { + direction : input ; + capacitance : 0.00390661 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0111); + } + fall_power("scalar"){ + values (0.0105); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0257); + } + fall_power("scalar"){ + values (0.0199); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.0027,0.0090,0.0246,0.0520,0.0910,0.1613,0.3020",\ +"-0.0105,0.0012,0.0129,0.0363,0.0793,0.1535,0.2902",\ +"-0.0262,-0.0145,-0.0027,0.0246,0.0637,0.1379,0.2785",\ +"-0.0535,-0.0418,-0.0262,0.0012,0.0363,0.1105,0.2512",\ +"-0.0926,-0.0809,-0.0652,-0.0418,-0.0027,0.0715,0.2121",\ +"-0.1668,-0.1551,-0.1395,-0.1082,-0.0770,-0.0027,0.1379",\ +"-0.3035,-0.2918,-0.2762,-0.2488,-0.2137,-0.1434,-0.0027"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.0832,0.0949,0.1105,0.1379,0.1730,0.2473,0.3801",\ +"0.0754,0.0832,0.0988,0.1223,0.1613,0.2355,0.3684",\ +"0.0598,0.0676,0.0832,0.1066,0.1457,0.2121,0.3527",\ +"0.0324,0.0441,0.0598,0.0871,0.1223,0.1926,0.3293",\ +"-0.0066,0.0051,0.0168,0.0480,0.0832,0.1535,0.2902",\ +"-0.0809,-0.0691,-0.0574,-0.0301,0.0090,0.0832,0.2121",\ +"-0.2176,-0.2059,-0.1941,-0.1668,-0.1277,-0.0574,0.0793"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1160",\ +"0.1965,0.1848,0.1730,0.1457,0.1027,0.0324,-0.1082",\ +"0.2160,0.2004,0.1887,0.1613,0.1184,0.0480,-0.0926",\ +"0.2395,0.2277,0.2121,0.1848,0.1457,0.0715,-0.0652",\ +"0.2785,0.2668,0.2512,0.2238,0.1848,0.1105,-0.0262",\ +"0.3527,0.3410,0.3254,0.2980,0.2551,0.1848,0.0480",\ +"0.4934,0.4816,0.4660,0.4387,0.3957,0.3254,0.1887"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1730,0.1613,0.1496,0.1184,0.0793,0.0129,-0.1238",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0207,-0.1121",\ +"0.2004,0.1887,0.1730,0.1457,0.1066,0.0363,-0.1004",\ +"0.2238,0.2121,0.2004,0.1691,0.1340,0.0598,-0.0730",\ +"0.2629,0.2512,0.2395,0.2121,0.1691,0.0988,-0.0340",\ +"0.3371,0.3254,0.3137,0.2863,0.2434,0.1730,0.0402",\ +"0.4777,0.4660,0.4504,0.4230,0.3840,0.3137,0.1809"); + } + } + } +pin(A_BIST_MEN) { + direction : input ; + capacitance : 0.00326046 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0783); + } + fall_power("scalar"){ + values (0.0772); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1926,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1418,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3488",\ +"-0.0262,-0.0145,0.0012,0.0285,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1379"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2199,0.2316,0.2590,0.2980,0.3723,0.5051",\ +"0.1965,0.2082,0.2199,0.2473,0.2863,0.3605,0.4934",\ +"0.1809,0.1926,0.2043,0.2316,0.2707,0.3449,0.4777",\ +"0.1574,0.1691,0.1809,0.2082,0.2434,0.3176,0.4543",\ +"0.1145,0.1262,0.1418,0.1691,0.2043,0.2785,0.4113",\ +"0.0441,0.0559,0.0676,0.0949,0.1301,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0691,-0.0418,-0.0066,0.0676,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1535,0.1262,0.0832,0.0129,-0.1277",\ +"0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1199",\ +"0.2043,0.1926,0.1770,0.1496,0.1105,0.0363,-0.1043",\ +"0.2277,0.2160,0.2043,0.1770,0.1379,0.0598,-0.0770",\ +"0.2668,0.2551,0.2434,0.2160,0.1730,0.0988,-0.0379",\ +"0.3449,0.3332,0.3176,0.2902,0.2473,0.1730,0.0363",\ +"0.4816,0.4699,0.4543,0.4270,0.3840,0.3098,0.1770"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1105,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1496,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1652,0.1340,0.0988,0.0285,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2551,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0418",\ +"0.3293,0.3176,0.3020,0.2746,0.2395,0.1652,0.0324",\ +"0.4660,0.4543,0.4426,0.4113,0.3762,0.3020,0.1691"); + } + } + } +bus(A_BIST_BM) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00253457 ; + max_transition : "0.38" ; + pin(A_BIST_BM[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0418); + } + fall_power("scalar"){ + values (0.0388); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0592); + } + fall_power("scalar"){ + values (0.0451); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1576,-0.1468,-0.1312,-0.1048,-0.0648,0.0055,0.1403",\ +"-0.1615,-0.1507,-0.1351,-0.1087,-0.0687,0.0016,0.1364",\ +"-0.1652,-0.1545,-0.1389,-0.1125,-0.0725,-0.0022,0.1326",\ +"-0.1685,-0.1578,-0.1421,-0.1158,-0.0757,-0.0054,0.1293",\ +"-0.1809,-0.1702,-0.1546,-0.1282,-0.0882,-0.0179,0.1169",\ +"-0.1984,-0.1877,-0.1720,-0.1457,-0.1056,-0.0353,0.0994",\ +"-0.2261,-0.2153,-0.1997,-0.1733,-0.1333,-0.0630,0.0718"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1351,-0.1244,-0.1107,-0.0834,-0.0462,0.0260,0.1559",\ +"-0.1390,-0.1282,-0.1146,-0.0872,-0.0501,0.0221,0.1520",\ +"-0.1428,-0.1320,-0.1184,-0.0910,-0.0539,0.0183,0.1482",\ +"-0.1460,-0.1353,-0.1216,-0.0943,-0.0572,0.0151,0.1450",\ +"-0.1585,-0.1477,-0.1341,-0.1067,-0.0696,0.0026,0.1325",\ +"-0.1759,-0.1652,-0.1515,-0.1242,-0.0871,-0.0148,0.1151",\ +"-0.2036,-0.1929,-0.1792,-0.1518,-0.1147,-0.0425,0.0874"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2635,0.2517,0.2371,0.2107,0.1707,0.0994,-0.0373",\ +"0.2673,0.2556,0.2410,0.2146,0.1746,0.1033,-0.0334",\ +"0.2711,0.2594,0.2448,0.2184,0.1784,0.1071,-0.0296",\ +"0.2744,0.2627,0.2480,0.2217,0.1816,0.1103,-0.0264",\ +"0.2868,0.2751,0.2605,0.2341,0.1941,0.1228,-0.0139",\ +"0.3043,0.2926,0.2779,0.2516,0.2115,0.1402,0.0035",\ +"0.3320,0.3202,0.3056,0.2792,0.2392,0.1679,0.0312"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2351,0.2254,0.2107,0.1844,0.1473,0.0740,-0.0539",\ +"0.2390,0.2293,0.2146,0.1882,0.1511,0.0779,-0.0500",\ +"0.2428,0.2331,0.2184,0.1920,0.1549,0.0817,-0.0462",\ +"0.2461,0.2363,0.2217,0.1953,0.1582,0.0849,-0.0430",\ +"0.2585,0.2488,0.2341,0.2077,0.1706,0.0974,-0.0305",\ +"0.2760,0.2662,0.2516,0.2252,0.1881,0.1149,-0.0131",\ +"0.3036,0.2939,0.2792,0.2529,0.2157,0.1425,0.0146"); + } + } +} + pin(A_BIST_CLK) { + direction : input; + capacitance : 0.00389386; + max_transition : "0.38"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.004,0.38"); + values("0.12,0.12"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0.6944); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (24.3582); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (24.1537); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (19.6992); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.4036); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.6774); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_BIST_DIN) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00252927 ; + memory_write() { + address : A_BIST_ADDR ; + clocked_on : A_BIST_CLK; + } + + max_transition : "0.38" ; + pin(A_BIST_DIN[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0418); + } + fall_power("scalar"){ + values (0.0388); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0592); + } + fall_power("scalar"){ + values (0.0451); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1576,-0.1468,-0.1312,-0.1048,-0.0648,0.0055,0.1403",\ +"-0.1615,-0.1507,-0.1351,-0.1087,-0.0687,0.0016,0.1364",\ +"-0.1652,-0.1545,-0.1389,-0.1125,-0.0725,-0.0022,0.1326",\ +"-0.1685,-0.1578,-0.1421,-0.1158,-0.0757,-0.0054,0.1293",\ +"-0.1809,-0.1702,-0.1546,-0.1282,-0.0882,-0.0179,0.1169",\ +"-0.1984,-0.1877,-0.1720,-0.1457,-0.1056,-0.0353,0.0994",\ +"-0.2261,-0.2153,-0.1997,-0.1733,-0.1333,-0.0630,0.0718"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1351,-0.1244,-0.1107,-0.0834,-0.0462,0.0260,0.1559",\ +"-0.1390,-0.1282,-0.1146,-0.0872,-0.0501,0.0221,0.1520",\ +"-0.1428,-0.1320,-0.1184,-0.0910,-0.0539,0.0183,0.1482",\ +"-0.1460,-0.1353,-0.1216,-0.0943,-0.0572,0.0151,0.1450",\ +"-0.1585,-0.1477,-0.1341,-0.1067,-0.0696,0.0026,0.1325",\ +"-0.1759,-0.1652,-0.1515,-0.1242,-0.0871,-0.0148,0.1151",\ +"-0.2036,-0.1929,-0.1792,-0.1518,-0.1147,-0.0425,0.0874"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2635,0.2517,0.2371,0.2107,0.1707,0.0994,-0.0373",\ +"0.2673,0.2556,0.2410,0.2146,0.1746,0.1033,-0.0334",\ +"0.2711,0.2594,0.2448,0.2184,0.1784,0.1071,-0.0296",\ +"0.2744,0.2627,0.2480,0.2217,0.1816,0.1103,-0.0264",\ +"0.2868,0.2751,0.2605,0.2341,0.1941,0.1228,-0.0139",\ +"0.3043,0.2926,0.2779,0.2516,0.2115,0.1402,0.0035",\ +"0.3320,0.3202,0.3056,0.2792,0.2392,0.1679,0.0312"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2351,0.2254,0.2107,0.1844,0.1473,0.0740,-0.0539",\ +"0.2390,0.2293,0.2146,0.1882,0.1511,0.0779,-0.0500",\ +"0.2428,0.2331,0.2184,0.1920,0.1549,0.0817,-0.0462",\ +"0.2461,0.2363,0.2217,0.1953,0.1582,0.0849,-0.0430",\ +"0.2585,0.2488,0.2341,0.2077,0.1706,0.0974,-0.0305",\ +"0.2760,0.2662,0.2516,0.2252,0.1881,0.1149,-0.0131",\ +"0.3036,0.2939,0.2792,0.2529,0.2157,0.1425,0.0146"); + } + } + } + +bus(A_DOUT) { + + bus_type : D_7_0; + direction : output ; + capacitance : 0 ; + max_capacitance : "6.4e-14" ; + memory_read() { + address : A_ADDR ; + } + pin(A_DOUT[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "A_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("2.5949,2.5959,2.6007,2.6062,2.6271,2.6506",\ +"2.6021,2.6031,2.6079,2.6134,2.6343,2.6578",\ +"2.6036,2.6046,2.6094,2.6149,2.6358,2.6593",\ +"2.6069,2.6079,2.6127,2.6183,2.6392,2.6627",\ +"2.6197,2.6207,2.6256,2.6311,2.6520,2.6755",\ +"2.6375,2.6385,2.6433,2.6488,2.6697,2.6932",\ +"2.6629,2.6639,2.6687,2.6742,2.6951,2.7186"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("2.5606,2.5614,2.5655,2.5700,2.5871,2.6038",\ +"2.5678,2.5687,2.5727,2.5772,2.5943,2.6111",\ +"2.5693,2.5701,2.5742,2.5787,2.5958,2.6125",\ +"2.5726,2.5735,2.5775,2.5821,2.5992,2.6159",\ +"2.5854,2.5863,2.5903,2.5949,2.6120,2.6287",\ +"2.6032,2.6041,2.6081,2.6126,2.6297,2.6465",\ +"2.6286,2.6294,2.6335,2.6380,2.6551,2.6718"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0206,0.0210,0.0265,0.0323,0.0606,0.0955"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0170,0.0177,0.0222,0.0270,0.0451,0.0644"); + } + } +} +cell_leakage_power : 234.7971; +} +} diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_1024x8_c2_bm_bist_slow_1p08V_125C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_1024x8_c2_bm_bist_slow_1p08V_125C.lib new file mode 100644 index 0000000000..66a85022b1 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_1024x8_c2_bm_bist_slow_1p08V_125C.lib @@ -0,0 +1,1525 @@ +/* ------------------------------------------------------*/ +/**/ +/* Copyright 2024 IHP PDK Authors*/ +/**/ +/* Licensed under the Apache License, Version 2.0 (the "License");*/ +/* you may not use this file except in compliance with the License.*/ +/* You may obtain a copy of the License at*/ +/* */ +/* https://www.apache.org/licenses/LICENSE-2.0*/ +/* */ +/* Unless required by applicable law or agreed to in writing, software*/ +/* distributed under the License is distributed on an "AS IS" BASIS,*/ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/ +/* See the License for the specific language governing permissions and*/ +/* limitations under the License.*/ +/* */ +/* Generated on Fri Jul 19 09:01:11 2024 */ +/* */ +/* ------------------------------------------------------ */ +library(RM_IHPSG13_1P_1024x8_c2_bm_bist_slow_1p08V_125C) { + technology (cmos) ; + delay_model : table_lookup ; + define ("add_pg_pin_to_lib", "library", "boolean"); + add_pg_pin_to_lib : true; + voltage_map ( VDD, 1.08); + voltage_map ( VDDARRAY, 1.08); + voltage_map ( VSS, 0.000000 ); + + date : "Fri Jul 19 09:01:10 2024" ; + comment : "IHP Microelectronics GmbH, 2024" ; + revision : 1.0.0 ; + simulation : true ; + nom_process : 1 ; + nom_temperature : 125 ; + nom_voltage : 1.08 ; + + operating_conditions("slow_1p08V_125C"){ + process : 1 ; + temperature : 125 ; + voltage : 1.08 ; + tree_type : "balanced_tree" ; + } + + default_operating_conditions : slow_1p08V_125C ; + default_max_transition : 1.0 ; + default_fanout_load : 1.0 ; + default_inout_pin_cap : 0.0 ; + default_input_pin_cap : 0.0 ; + default_output_pin_cap : 0.0 ; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + + slew_lower_threshold_pct_rise : 30 ; + slew_upper_threshold_pct_rise : 70 ; + input_threshold_pct_fall : 50 ; + output_threshold_pct_fall : 50 ; + input_threshold_pct_rise : 50 ; + output_threshold_pct_rise : 50 ; + slew_lower_threshold_pct_fall : 30 ; + slew_upper_threshold_pct_fall : 70 ; + slew_derate_from_library : 0.5; + k_volt_cell_leakage_power : 0.0 ; + k_temp_cell_leakage_power : 0.0 ; + k_process_cell_leakage_power : 0.0 ; + k_volt_internal_power : 0.0 ; + k_temp_internal_power : 0.0 ; + k_process_internal_power : 0.0 ; + + capacitive_load_unit (1,pf) ; + voltage_unit : "1V" ; + current_unit : "1uA" ; + time_unit : "1ns" ; + leakage_power_unit : "1nW" ; + pulling_resistance_unit : "1kohm"; + /* + ------------------------------------------------------------------------------------------ + implicit units overview: + cell_area unit : "um" + internal_power unit : "1e-12 * J/toggle = 1 * uW/MHz" + (capacitive_load_unit * voltage_unit^2) per toggle event + ------------------------------------------------------------------------------------------ + */ + library_features(report_delay_calculation); + define_cell_area (pad_drivers,pad_driver_sites) ; + + lu_table_template(CLKTRAN_constraint_template) { + variable_1 : constrained_pin_transition; + index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" ); + } + lu_table_template(SRAM_load_template) { + variable_1 : total_output_net_capacitance; + index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + lu_table_template(SIG2SRAM_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" ); + index_2 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" ); + } + + lu_table_template(SIG2SRAM_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" ); + index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + + type (D_7_0) { + base_type : array; + data_type : bit; + bit_width : 8; + bit_from : 7; + bit_to : 0; + downto : true; + } + + type (A_9_0) { + base_type : array; + data_type : bit; + bit_width : 10; + bit_from : 9; + bit_to : 0; + downto : true; + } + +cell(RM_IHPSG13_1P_1024x8_c2_bm_bist) { +pg_pin (VDD) { + pg_type : primary_power; + voltage_name : VDD; +} +pg_pin (VDDARRAY) { + pg_type : primary_power; + voltage_name : VDDARRAY; +} +pg_pin (VSS) { + pg_type : primary_ground; + voltage_name : VSS; +} + +memory() { + type : ram; + address_width : 10; + word_width : 8; +} + +interface_timing : false; +bus_naming_style : "%s[%d]" ; +area : 49419.2448 ; + + pin(A_DLY) { + direction : input ; + capacitance : 0.00387999 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_ADDR) { + bus_type : A_9_0; + direction : input ; + capacitance : 0.0077013 ; + pin(A_ADDR[0]) { + capacitance : 0.00625349 ; + } + pin(A_ADDR[1]) { + capacitance : 0.00507435 ; + } + pin(A_ADDR[2]) { + capacitance : 0.00656707 ; + } + pin(A_ADDR[3]) { + capacitance : 0.0083133 ; + } + pin(A_ADDR[4]) { + capacitance : 0.00507219 ; + } + pin(A_ADDR[5]) { + capacitance : 0.00964344 ; + } + pin(A_ADDR[6]) { + capacitance : 0.0119653 ; + } + pin(A_ADDR[7]) { + capacitance : 0.00827606 ; + } + pin(A_ADDR[8]) { + capacitance : 0.0110771 ; + } + max_transition : "0.5952" ; + pin(A_ADDR[9:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0113); + } + fall_power("scalar"){ + values (0.0087); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0152); + } + fall_power("scalar"){ + values (0.0041); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7371,-0.7176,-0.6863,-0.6434,-0.5652,-0.4168,-0.1980",\ +"-0.7566,-0.7371,-0.7059,-0.6629,-0.5848,-0.4363,-0.2137",\ +"-0.7879,-0.7645,-0.7332,-0.6902,-0.6121,-0.4637,-0.2449",\ +"-0.8309,-0.8074,-0.7762,-0.7332,-0.6551,-0.5066,-0.2879",\ +"-0.9051,-0.8895,-0.8543,-0.8113,-0.7332,-0.5887,-0.3660",\ +"-1.0418,-1.0262,-0.9949,-0.9480,-0.8699,-0.7293,-0.5027",\ +"-1.2684,-1.2449,-1.2176,-1.1707,-1.0965,-0.9480,-0.7293"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5926,-0.5730,-0.5418,-0.4988,-0.4246,-0.2879,-0.0730",\ +"-0.6121,-0.5926,-0.5613,-0.5223,-0.4441,-0.3074,-0.0887",\ +"-0.6395,-0.6199,-0.5926,-0.5496,-0.4715,-0.3348,-0.1160",\ +"-0.6863,-0.6668,-0.6355,-0.5965,-0.5184,-0.3777,-0.1590",\ +"-0.7605,-0.7410,-0.7137,-0.6746,-0.5926,-0.4559,-0.2410",\ +"-0.9012,-0.8816,-0.8504,-0.8113,-0.7332,-0.5926,-0.3895",\ +"-1.1238,-1.1043,-1.0769,-1.0379,-0.9559,-0.8191,-0.6004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8488,0.8293,0.7980,0.7551,0.6730,0.5285,0.3098",\ +"0.8684,0.8488,0.8176,0.7746,0.6926,0.5480,0.3254",\ +"0.8996,0.8801,0.8449,0.8020,0.7238,0.5754,0.3527",\ +"0.9426,0.9191,0.8918,0.8488,0.7668,0.6223,0.3996",\ +"1.0168,1.0012,0.9699,0.9230,0.8449,0.7004,0.4777",\ +"1.1574,1.1379,1.1105,1.0598,0.9816,0.8371,0.6184",\ +"1.3801,1.3605,1.3254,1.2980,1.2043,1.0637,0.8371"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6965,0.6770,0.6496,0.6066,0.5246,0.3918,0.1730",\ +"0.7160,0.6965,0.6652,0.6262,0.5441,0.4113,0.1965",\ +"0.7473,0.7277,0.6965,0.6535,0.5754,0.4426,0.2238",\ +"0.7863,0.7707,0.7395,0.7004,0.6223,0.4855,0.2629",\ +"0.8684,0.8449,0.8176,0.7785,0.7004,0.5637,0.3449",\ +"1.0051,0.9855,0.9855,0.9113,0.8332,0.7004,0.4895",\ +"1.2277,1.2082,1.1809,1.1379,1.0598,0.9230,0.7004"); + } + } +} +pin(A_WEN) { + direction : input ; + capacitance : 0.00313551 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0036); + } + fall_power("scalar"){ + values (0.0007); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0050); + } + fall_power("scalar"){ + values (0.0003); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3137,0.3332,0.3605,0.4035,0.4816,0.6223,0.8488",\ +"0.2980,0.3176,0.3410,0.3840,0.4660,0.6027,0.8293",\ +"0.2629,0.2824,0.3098,0.3527,0.4348,0.5754,0.7980",\ +"0.2199,0.2395,0.2668,0.3098,0.3918,0.5324,0.7590",\ +"0.1418,0.1613,0.1887,0.2316,0.3137,0.4348,0.6730",\ +"0.0012,0.0207,0.0520,0.0910,0.1730,0.3098,0.5285",\ +"-0.2215,-0.2020,-0.1746,-0.1277,-0.0496,0.0910,0.3098"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4504,0.4699,0.4973,0.5324,0.6027,0.7355,0.9699",\ +"0.4309,0.4504,0.4777,0.5129,0.5910,0.7160,0.9504",\ +"0.3996,0.4191,0.4465,0.4816,0.5520,0.6848,0.9191",\ +"0.3605,0.3762,0.4035,0.4387,0.5168,0.6418,0.8723",\ +"0.2785,0.2980,0.3215,0.3605,0.4348,0.5637,0.7980",\ +"0.1379,0.1574,0.1809,0.2199,0.2980,0.4309,0.6457",\ +"-0.0809,-0.0613,-0.0340,0.0051,0.0832,0.2160,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3723,0.3527,0.3215,0.2785,0.1965,0.0559,-0.1668",\ +"0.3918,0.3723,0.3449,0.2980,0.2160,0.0754,-0.1473",\ +"0.4152,0.3996,0.3684,0.3254,0.2434,0.1066,-0.1199",\ +"0.4621,0.4465,0.4152,0.3723,0.2863,0.1496,-0.0730",\ +"0.5324,0.5207,0.4895,0.4465,0.3645,0.2199,0.0051",\ +"0.6770,0.6535,0.6301,0.5832,0.5090,0.3605,0.1418",\ +"0.9035,0.8879,0.8566,0.8137,0.7316,0.5871,0.3684"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3566,0.3293,0.2863,0.2043,0.0676,-0.1434",\ +"0.3957,0.3762,0.3488,0.3059,0.2238,0.0871,-0.1199",\ +"0.4230,0.4035,0.3723,0.3332,0.2512,0.1184,-0.0965",\ +"0.4660,0.4465,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5324,0.5168,0.4973,0.4543,0.3723,0.2316,0.0285",\ +"0.6809,0.6613,0.6340,0.5910,0.5129,0.3645,0.1652",\ +"0.9113,0.8918,0.8605,0.8176,0.7395,0.5988,0.3879"); + } + } + } +pin(A_REN) { + direction : input ; + capacitance : 0.00381144 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0041); + } + fall_power("scalar"){ + values (0.0015); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0041); + } + fall_power("scalar"){ + values (0.0013); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.0770,-0.0574,-0.0262,0.0168,0.0949,0.2355,0.4582",\ +"-0.0965,-0.0770,-0.0457,-0.0027,0.0754,0.2160,0.4387",\ +"-0.1199,-0.1004,-0.0730,-0.0262,0.0520,0.1887,0.4113",\ +"-0.1590,-0.1434,-0.1160,-0.0730,0.0051,0.1457,0.3645",\ +"-0.2449,-0.2254,-0.1941,-0.1473,-0.0770,0.0676,0.2863",\ +"-0.3816,-0.3699,-0.3387,-0.2801,-0.2215,-0.0770,0.1457",\ +"-0.6121,-0.5926,-0.5613,-0.5145,-0.4363,-0.2996,-0.0730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.1262,0.1457,0.1691,0.2121,0.2824,0.4191,0.6457",\ +"0.1105,0.1262,0.1496,0.1887,0.2629,0.3996,0.6262",\ +"0.0793,0.0949,0.1223,0.1652,0.2395,0.3684,0.5949",\ +"0.0363,0.0559,0.0793,0.1223,0.2004,0.3410,0.5520",\ +"-0.0457,-0.0262,0.0012,0.0441,0.1301,0.2629,0.4738",\ +"-0.1902,-0.1746,-0.1434,-0.1043,-0.0184,0.1223,0.3332",\ +"-0.4129,-0.3934,-0.3660,-0.3230,-0.2449,-0.1043,0.1105"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4113,0.3918,0.3645,0.3176,0.2395,0.0988,-0.1238",\ +"0.4309,0.4113,0.3840,0.3371,0.2590,0.1184,-0.1043",\ +"0.4582,0.4387,0.4113,0.3645,0.2824,0.1457,-0.0770",\ +"0.5051,0.4816,0.4543,0.4074,0.3293,0.1887,-0.0340",\ +"0.5715,0.5598,0.5324,0.4895,0.4035,0.2512,0.0441",\ +"0.7043,0.7004,0.6730,0.6262,0.5402,0.3957,0.1809",\ +"0.9387,0.9270,0.8957,0.8527,0.7746,0.6262,0.4074"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4152,0.3918,0.3645,0.3215,0.2395,0.1027,-0.1082",\ +"0.4309,0.4113,0.3801,0.3410,0.2590,0.1223,-0.0926",\ +"0.4582,0.4387,0.4074,0.3684,0.2863,0.1496,-0.0613",\ +"0.5012,0.4816,0.4504,0.4074,0.3293,0.1887,-0.0145",\ +"0.5715,0.5559,0.5285,0.4816,0.3996,0.2512,0.0598",\ +"0.7160,0.7004,0.6691,0.6262,0.5520,0.4035,0.2004",\ +"0.9387,0.9191,0.8957,0.8488,0.7707,0.6262,0.4113"); + } + } + } +pin(A_MEN) { + direction : input ; + capacitance : 0.00300347 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0092); + } + fall_power("scalar"){ + values (0.0002); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3215,0.3449,0.3684,0.4113,0.4895,0.6301,0.8527",\ +"0.3059,0.3254,0.3527,0.3957,0.4738,0.6145,0.8371",\ +"0.2746,0.2941,0.3215,0.3645,0.4426,0.5871,0.8059",\ +"0.2316,0.2512,0.2785,0.3215,0.3996,0.5402,0.7629",\ +"0.1496,0.1730,0.1965,0.2395,0.3215,0.4660,0.6848",\ +"0.0090,0.0285,0.0598,0.1027,0.1809,0.3176,0.5402",\ +"-0.2098,-0.1902,-0.1668,-0.1199,-0.0418,0.0988,0.3137"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4582,0.4738,0.5012,0.5363,0.6145,0.7395,0.9738",\ +"0.4387,0.4543,0.4816,0.5207,0.5910,0.7199,0.9582",\ +"0.4035,0.4230,0.4504,0.4855,0.5637,0.6887,0.9230",\ +"0.3645,0.3840,0.4074,0.4465,0.5285,0.6496,0.8840",\ +"0.2824,0.3020,0.3254,0.3645,0.4465,0.5715,0.7980",\ +"0.1418,0.1613,0.1887,0.2238,0.3020,0.4309,0.6496",\ +"-0.0770,-0.0574,-0.0301,0.0090,0.0910,0.2238,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3293,0.2863,0.2043,0.0637,-0.1629",\ +"0.3996,0.3801,0.3488,0.3020,0.2238,0.0832,-0.1395",\ +"0.4230,0.4074,0.3723,0.3293,0.2473,0.1105,-0.1121",\ +"0.4621,0.4465,0.4152,0.3762,0.2941,0.1535,-0.0691",\ +"0.5441,0.5285,0.4973,0.4465,0.3684,0.2316,0.0090",\ +"0.6848,0.6652,0.6301,0.5910,0.5129,0.3605,0.1496",\ +"0.9074,0.8918,0.8566,0.8215,0.7395,0.5910,0.3723"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3332,0.2863,0.2043,0.0715,-0.1395",\ +"0.3996,0.3762,0.3488,0.3059,0.2238,0.0910,-0.1199",\ +"0.4270,0.4035,0.3762,0.3332,0.2512,0.1184,-0.0965",\ +"0.4699,0.4504,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5441,0.5285,0.4973,0.4543,0.3762,0.2355,0.0324",\ +"0.6770,0.6613,0.6340,0.5949,0.5207,0.3762,0.1652",\ +"0.9074,0.8918,0.8605,0.8176,0.7395,0.6027,0.3918"); + } + } + } +bus(A_BM) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00263802 ; + max_transition : "0.5952" ; + pin(A_BM[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0236); + } + fall_power("scalar"){ + values (0.0075); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0230); + } + fall_power("scalar"){ + values (0.0072); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5355,-0.5160,-0.4896,-0.4476,-0.3665,-0.2220,-0.0013",\ +"-0.5435,-0.5240,-0.4976,-0.4556,-0.3746,-0.2300,-0.0093",\ +"-0.5525,-0.5330,-0.5066,-0.4646,-0.3836,-0.2390,-0.0183",\ +"-0.5657,-0.5461,-0.5198,-0.4778,-0.3967,-0.2522,-0.0315",\ +"-0.5899,-0.5704,-0.5440,-0.5021,-0.4210,-0.2765,-0.0558",\ +"-0.6205,-0.6009,-0.5746,-0.5326,-0.4515,-0.3070,-0.0863",\ +"-0.7019,-0.6824,-0.6560,-0.6140,-0.5330,-0.3884,-0.1677"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.4798,-0.4642,-0.4359,-0.3968,-0.3158,-0.1781,0.0339",\ +"-0.4878,-0.4722,-0.4439,-0.4048,-0.3238,-0.1861,0.0258",\ +"-0.4968,-0.4812,-0.4529,-0.4138,-0.3328,-0.1951,0.0168",\ +"-0.5100,-0.4944,-0.4661,-0.4270,-0.3459,-0.2082,0.0037",\ +"-0.5343,-0.5187,-0.4903,-0.4513,-0.3702,-0.2325,-0.0206",\ +"-0.5648,-0.5492,-0.5208,-0.4818,-0.4007,-0.2630,-0.0511",\ +"-0.6462,-0.6306,-0.6023,-0.5632,-0.4822,-0.3445,-0.1326"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6521,0.6307,0.6043,0.5613,0.4822,0.3367,0.1111",\ +"0.6602,0.6387,0.6123,0.5693,0.4902,0.3447,0.1192",\ +"0.6692,0.6477,0.6213,0.5784,0.4993,0.3537,0.1282",\ +"0.6823,0.6608,0.6345,0.5915,0.5124,0.3669,0.1413",\ +"0.7066,0.6851,0.6588,0.6158,0.5367,0.3912,0.1656",\ +"0.7371,0.7156,0.6893,0.6463,0.5672,0.4217,0.1961",\ +"0.8186,0.7971,0.7707,0.7278,0.6487,0.5031,0.2776"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.5838,0.5672,0.5389,0.4949,0.4178,0.2801,0.0701",\ +"0.5918,0.5752,0.5469,0.5029,0.4258,0.2881,0.0781",\ +"0.6008,0.5842,0.5559,0.5120,0.4348,0.2971,0.0871",\ +"0.6140,0.5974,0.5690,0.5251,0.4480,0.3103,0.1003",\ +"0.6382,0.6216,0.5933,0.5494,0.4722,0.3345,0.1246",\ +"0.6688,0.6522,0.6238,0.5799,0.5028,0.3650,0.1551",\ +"0.7502,0.7336,0.7053,0.6613,0.5842,0.4465,0.2366"); + } + } +} + pin(A_CLK) { + direction : input; + capacitance : 0.00378957; + max_transition : "0.5952"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.008,0.5952"); + values("0.4,0.4"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (0.5206); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (15.8889); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (15.7957); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (12.1067); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (0.3170); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (0.5148); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_DIN) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00358485 ; + memory_write() { + address : A_ADDR ; + clocked_on : A_CLK; + } + + max_transition : "0.5952" ; + pin(A_DIN[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0236); + } + fall_power("scalar"){ + values (0.0075); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0230); + } + fall_power("scalar"){ + values (0.0072); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5355,-0.5160,-0.4896,-0.4476,-0.3665,-0.2220,-0.0013",\ +"-0.5435,-0.5240,-0.4976,-0.4556,-0.3746,-0.2300,-0.0093",\ +"-0.5525,-0.5330,-0.5066,-0.4646,-0.3836,-0.2390,-0.0183",\ +"-0.5657,-0.5461,-0.5198,-0.4778,-0.3967,-0.2522,-0.0315",\ +"-0.5899,-0.5704,-0.5440,-0.5021,-0.4210,-0.2765,-0.0558",\ +"-0.6205,-0.6009,-0.5746,-0.5326,-0.4515,-0.3070,-0.0863",\ +"-0.7019,-0.6824,-0.6560,-0.6140,-0.5330,-0.3884,-0.1677"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.4798,-0.4642,-0.4359,-0.3968,-0.3158,-0.1781,0.0339",\ +"-0.4878,-0.4722,-0.4439,-0.4048,-0.3238,-0.1861,0.0258",\ +"-0.4968,-0.4812,-0.4529,-0.4138,-0.3328,-0.1951,0.0168",\ +"-0.5100,-0.4944,-0.4661,-0.4270,-0.3459,-0.2082,0.0037",\ +"-0.5343,-0.5187,-0.4903,-0.4513,-0.3702,-0.2325,-0.0206",\ +"-0.5648,-0.5492,-0.5208,-0.4818,-0.4007,-0.2630,-0.0511",\ +"-0.6462,-0.6306,-0.6023,-0.5632,-0.4822,-0.3445,-0.1326"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6521,0.6307,0.6043,0.5613,0.4822,0.3367,0.1111",\ +"0.6602,0.6387,0.6123,0.5693,0.4902,0.3447,0.1192",\ +"0.6692,0.6477,0.6213,0.5784,0.4993,0.3537,0.1282",\ +"0.6823,0.6608,0.6345,0.5915,0.5124,0.3669,0.1413",\ +"0.7066,0.6851,0.6588,0.6158,0.5367,0.3912,0.1656",\ +"0.7371,0.7156,0.6893,0.6463,0.5672,0.4217,0.1961",\ +"0.8186,0.7971,0.7707,0.7278,0.6487,0.5031,0.2776"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.5838,0.5672,0.5389,0.4949,0.4178,0.2801,0.0701",\ +"0.5918,0.5752,0.5469,0.5029,0.4258,0.2881,0.0781",\ +"0.6008,0.5842,0.5559,0.5120,0.4348,0.2971,0.0871",\ +"0.6140,0.5974,0.5690,0.5251,0.4480,0.3103,0.1003",\ +"0.6382,0.6216,0.5933,0.5494,0.4722,0.3345,0.1246",\ +"0.6688,0.6522,0.6238,0.5799,0.5028,0.3650,0.1551",\ +"0.7502,0.7336,0.7053,0.6613,0.5842,0.4465,0.2366"); + } + } + } + + pin(A_BIST_EN) { + direction : input ; + capacitance : 0.00387999 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_BIST_ADDR) { + bus_type : A_9_0; + direction : input ; + capacitance : 0.0077013 ; + pin(A_BIST_ADDR[0]) { + capacitance : 0.00625349 ; + } + pin(A_BIST_ADDR[1]) { + capacitance : 0.00507435 ; + } + pin(A_BIST_ADDR[2]) { + capacitance : 0.00656707 ; + } + pin(A_BIST_ADDR[3]) { + capacitance : 0.0083133 ; + } + pin(A_BIST_ADDR[4]) { + capacitance : 0.00507219 ; + } + pin(A_BIST_ADDR[5]) { + capacitance : 0.00964344 ; + } + pin(A_BIST_ADDR[6]) { + capacitance : 0.0119653 ; + } + pin(A_BIST_ADDR[7]) { + capacitance : 0.00827606 ; + } + pin(A_BIST_ADDR[8]) { + capacitance : 0.0110771 ; + } + max_transition : "0.5952" ; + pin(A_BIST_ADDR[9:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0113); + } + fall_power("scalar"){ + values (0.0087); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0152); + } + fall_power("scalar"){ + values (0.0041); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7371,-0.7176,-0.6863,-0.6434,-0.5652,-0.4168,-0.1980",\ +"-0.7566,-0.7371,-0.7059,-0.6629,-0.5848,-0.4363,-0.2137",\ +"-0.7879,-0.7645,-0.7332,-0.6902,-0.6121,-0.4637,-0.2449",\ +"-0.8309,-0.8074,-0.7762,-0.7332,-0.6551,-0.5066,-0.2879",\ +"-0.9051,-0.8895,-0.8543,-0.8113,-0.7332,-0.5887,-0.3660",\ +"-1.0418,-1.0262,-0.9949,-0.9480,-0.8699,-0.7293,-0.5027",\ +"-1.2684,-1.2449,-1.2176,-1.1707,-1.0965,-0.9480,-0.7293"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5926,-0.5730,-0.5418,-0.4988,-0.4246,-0.2879,-0.0730",\ +"-0.6121,-0.5926,-0.5613,-0.5223,-0.4441,-0.3074,-0.0887",\ +"-0.6395,-0.6199,-0.5926,-0.5496,-0.4715,-0.3348,-0.1160",\ +"-0.6863,-0.6668,-0.6355,-0.5965,-0.5184,-0.3777,-0.1590",\ +"-0.7605,-0.7410,-0.7137,-0.6746,-0.5926,-0.4559,-0.2410",\ +"-0.9012,-0.8816,-0.8504,-0.8113,-0.7332,-0.5926,-0.3895",\ +"-1.1238,-1.1043,-1.0769,-1.0379,-0.9559,-0.8191,-0.6004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8488,0.8293,0.7980,0.7551,0.6730,0.5285,0.3098",\ +"0.8684,0.8488,0.8176,0.7746,0.6926,0.5480,0.3254",\ +"0.8996,0.8801,0.8449,0.8020,0.7238,0.5754,0.3527",\ +"0.9426,0.9191,0.8918,0.8488,0.7668,0.6223,0.3996",\ +"1.0168,1.0012,0.9699,0.9230,0.8449,0.7004,0.4777",\ +"1.1574,1.1379,1.1105,1.0598,0.9816,0.8371,0.6184",\ +"1.3801,1.3605,1.3254,1.2980,1.2043,1.0637,0.8371"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6965,0.6770,0.6496,0.6066,0.5246,0.3918,0.1730",\ +"0.7160,0.6965,0.6652,0.6262,0.5441,0.4113,0.1965",\ +"0.7473,0.7277,0.6965,0.6535,0.5754,0.4426,0.2238",\ +"0.7863,0.7707,0.7395,0.7004,0.6223,0.4855,0.2629",\ +"0.8684,0.8449,0.8176,0.7785,0.7004,0.5637,0.3449",\ +"1.0051,0.9855,0.9855,0.9113,0.8332,0.7004,0.4895",\ +"1.2277,1.2082,1.1809,1.1379,1.0598,0.9230,0.7004"); + } + } +} +pin(A_BIST_WEN) { + direction : input ; + capacitance : 0.00313551 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0036); + } + fall_power("scalar"){ + values (0.0007); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0050); + } + fall_power("scalar"){ + values (0.0003); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3137,0.3332,0.3605,0.4035,0.4816,0.6223,0.8488",\ +"0.2980,0.3176,0.3410,0.3840,0.4660,0.6027,0.8293",\ +"0.2629,0.2824,0.3098,0.3527,0.4348,0.5754,0.7980",\ +"0.2199,0.2395,0.2668,0.3098,0.3918,0.5324,0.7590",\ +"0.1418,0.1613,0.1887,0.2316,0.3137,0.4348,0.6730",\ +"0.0012,0.0207,0.0520,0.0910,0.1730,0.3098,0.5285",\ +"-0.2215,-0.2020,-0.1746,-0.1277,-0.0496,0.0910,0.3098"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4504,0.4699,0.4973,0.5324,0.6027,0.7355,0.9699",\ +"0.4309,0.4504,0.4777,0.5129,0.5910,0.7160,0.9504",\ +"0.3996,0.4191,0.4465,0.4816,0.5520,0.6848,0.9191",\ +"0.3605,0.3762,0.4035,0.4387,0.5168,0.6418,0.8723",\ +"0.2785,0.2980,0.3215,0.3605,0.4348,0.5637,0.7980",\ +"0.1379,0.1574,0.1809,0.2199,0.2980,0.4309,0.6457",\ +"-0.0809,-0.0613,-0.0340,0.0051,0.0832,0.2160,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3723,0.3527,0.3215,0.2785,0.1965,0.0559,-0.1668",\ +"0.3918,0.3723,0.3449,0.2980,0.2160,0.0754,-0.1473",\ +"0.4152,0.3996,0.3684,0.3254,0.2434,0.1066,-0.1199",\ +"0.4621,0.4465,0.4152,0.3723,0.2863,0.1496,-0.0730",\ +"0.5324,0.5207,0.4895,0.4465,0.3645,0.2199,0.0051",\ +"0.6770,0.6535,0.6301,0.5832,0.5090,0.3605,0.1418",\ +"0.9035,0.8879,0.8566,0.8137,0.7316,0.5871,0.3684"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3566,0.3293,0.2863,0.2043,0.0676,-0.1434",\ +"0.3957,0.3762,0.3488,0.3059,0.2238,0.0871,-0.1199",\ +"0.4230,0.4035,0.3723,0.3332,0.2512,0.1184,-0.0965",\ +"0.4660,0.4465,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5324,0.5168,0.4973,0.4543,0.3723,0.2316,0.0285",\ +"0.6809,0.6613,0.6340,0.5910,0.5129,0.3645,0.1652",\ +"0.9113,0.8918,0.8605,0.8176,0.7395,0.5988,0.3879"); + } + } + } +pin(A_BIST_REN) { + direction : input ; + capacitance : 0.00381144 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0041); + } + fall_power("scalar"){ + values (0.0015); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0041); + } + fall_power("scalar"){ + values (0.0013); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.0770,-0.0574,-0.0262,0.0168,0.0949,0.2355,0.4582",\ +"-0.0965,-0.0770,-0.0457,-0.0027,0.0754,0.2160,0.4387",\ +"-0.1199,-0.1004,-0.0730,-0.0262,0.0520,0.1887,0.4113",\ +"-0.1590,-0.1434,-0.1160,-0.0730,0.0051,0.1457,0.3645",\ +"-0.2449,-0.2254,-0.1941,-0.1473,-0.0770,0.0676,0.2863",\ +"-0.3816,-0.3699,-0.3387,-0.2801,-0.2215,-0.0770,0.1457",\ +"-0.6121,-0.5926,-0.5613,-0.5145,-0.4363,-0.2996,-0.0730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.1262,0.1457,0.1691,0.2121,0.2824,0.4191,0.6457",\ +"0.1105,0.1262,0.1496,0.1887,0.2629,0.3996,0.6262",\ +"0.0793,0.0949,0.1223,0.1652,0.2395,0.3684,0.5949",\ +"0.0363,0.0559,0.0793,0.1223,0.2004,0.3410,0.5520",\ +"-0.0457,-0.0262,0.0012,0.0441,0.1301,0.2629,0.4738",\ +"-0.1902,-0.1746,-0.1434,-0.1043,-0.0184,0.1223,0.3332",\ +"-0.4129,-0.3934,-0.3660,-0.3230,-0.2449,-0.1043,0.1105"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4113,0.3918,0.3645,0.3176,0.2395,0.0988,-0.1238",\ +"0.4309,0.4113,0.3840,0.3371,0.2590,0.1184,-0.1043",\ +"0.4582,0.4387,0.4113,0.3645,0.2824,0.1457,-0.0770",\ +"0.5051,0.4816,0.4543,0.4074,0.3293,0.1887,-0.0340",\ +"0.5715,0.5598,0.5324,0.4895,0.4035,0.2512,0.0441",\ +"0.7043,0.7004,0.6730,0.6262,0.5402,0.3957,0.1809",\ +"0.9387,0.9270,0.8957,0.8527,0.7746,0.6262,0.4074"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4152,0.3918,0.3645,0.3215,0.2395,0.1027,-0.1082",\ +"0.4309,0.4113,0.3801,0.3410,0.2590,0.1223,-0.0926",\ +"0.4582,0.4387,0.4074,0.3684,0.2863,0.1496,-0.0613",\ +"0.5012,0.4816,0.4504,0.4074,0.3293,0.1887,-0.0145",\ +"0.5715,0.5559,0.5285,0.4816,0.3996,0.2512,0.0598",\ +"0.7160,0.7004,0.6691,0.6262,0.5520,0.4035,0.2004",\ +"0.9387,0.9191,0.8957,0.8488,0.7707,0.6262,0.4113"); + } + } + } +pin(A_BIST_MEN) { + direction : input ; + capacitance : 0.00300347 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0092); + } + fall_power("scalar"){ + values (0.0002); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3215,0.3449,0.3684,0.4113,0.4895,0.6301,0.8527",\ +"0.3059,0.3254,0.3527,0.3957,0.4738,0.6145,0.8371",\ +"0.2746,0.2941,0.3215,0.3645,0.4426,0.5871,0.8059",\ +"0.2316,0.2512,0.2785,0.3215,0.3996,0.5402,0.7629",\ +"0.1496,0.1730,0.1965,0.2395,0.3215,0.4660,0.6848",\ +"0.0090,0.0285,0.0598,0.1027,0.1809,0.3176,0.5402",\ +"-0.2098,-0.1902,-0.1668,-0.1199,-0.0418,0.0988,0.3137"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4582,0.4738,0.5012,0.5363,0.6145,0.7395,0.9738",\ +"0.4387,0.4543,0.4816,0.5207,0.5910,0.7199,0.9582",\ +"0.4035,0.4230,0.4504,0.4855,0.5637,0.6887,0.9230",\ +"0.3645,0.3840,0.4074,0.4465,0.5285,0.6496,0.8840",\ +"0.2824,0.3020,0.3254,0.3645,0.4465,0.5715,0.7980",\ +"0.1418,0.1613,0.1887,0.2238,0.3020,0.4309,0.6496",\ +"-0.0770,-0.0574,-0.0301,0.0090,0.0910,0.2238,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3293,0.2863,0.2043,0.0637,-0.1629",\ +"0.3996,0.3801,0.3488,0.3020,0.2238,0.0832,-0.1395",\ +"0.4230,0.4074,0.3723,0.3293,0.2473,0.1105,-0.1121",\ +"0.4621,0.4465,0.4152,0.3762,0.2941,0.1535,-0.0691",\ +"0.5441,0.5285,0.4973,0.4465,0.3684,0.2316,0.0090",\ +"0.6848,0.6652,0.6301,0.5910,0.5129,0.3605,0.1496",\ +"0.9074,0.8918,0.8566,0.8215,0.7395,0.5910,0.3723"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3332,0.2863,0.2043,0.0715,-0.1395",\ +"0.3996,0.3762,0.3488,0.3059,0.2238,0.0910,-0.1199",\ +"0.4270,0.4035,0.3762,0.3332,0.2512,0.1184,-0.0965",\ +"0.4699,0.4504,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5441,0.5285,0.4973,0.4543,0.3762,0.2355,0.0324",\ +"0.6770,0.6613,0.6340,0.5949,0.5207,0.3762,0.1652",\ +"0.9074,0.8918,0.8605,0.8176,0.7395,0.6027,0.3918"); + } + } + } +bus(A_BIST_BM) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00225269 ; + max_transition : "0.5952" ; + pin(A_BIST_BM[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0236); + } + fall_power("scalar"){ + values (0.0075); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0230); + } + fall_power("scalar"){ + values (0.0072); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5355,-0.5160,-0.4896,-0.4476,-0.3665,-0.2220,-0.0013",\ +"-0.5435,-0.5240,-0.4976,-0.4556,-0.3746,-0.2300,-0.0093",\ +"-0.5525,-0.5330,-0.5066,-0.4646,-0.3836,-0.2390,-0.0183",\ +"-0.5657,-0.5461,-0.5198,-0.4778,-0.3967,-0.2522,-0.0315",\ +"-0.5899,-0.5704,-0.5440,-0.5021,-0.4210,-0.2765,-0.0558",\ +"-0.6205,-0.6009,-0.5746,-0.5326,-0.4515,-0.3070,-0.0863",\ +"-0.7019,-0.6824,-0.6560,-0.6140,-0.5330,-0.3884,-0.1677"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.4798,-0.4642,-0.4359,-0.3968,-0.3158,-0.1781,0.0339",\ +"-0.4878,-0.4722,-0.4439,-0.4048,-0.3238,-0.1861,0.0258",\ +"-0.4968,-0.4812,-0.4529,-0.4138,-0.3328,-0.1951,0.0168",\ +"-0.5100,-0.4944,-0.4661,-0.4270,-0.3459,-0.2082,0.0037",\ +"-0.5343,-0.5187,-0.4903,-0.4513,-0.3702,-0.2325,-0.0206",\ +"-0.5648,-0.5492,-0.5208,-0.4818,-0.4007,-0.2630,-0.0511",\ +"-0.6462,-0.6306,-0.6023,-0.5632,-0.4822,-0.3445,-0.1326"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6521,0.6307,0.6043,0.5613,0.4822,0.3367,0.1111",\ +"0.6602,0.6387,0.6123,0.5693,0.4902,0.3447,0.1192",\ +"0.6692,0.6477,0.6213,0.5784,0.4993,0.3537,0.1282",\ +"0.6823,0.6608,0.6345,0.5915,0.5124,0.3669,0.1413",\ +"0.7066,0.6851,0.6588,0.6158,0.5367,0.3912,0.1656",\ +"0.7371,0.7156,0.6893,0.6463,0.5672,0.4217,0.1961",\ +"0.8186,0.7971,0.7707,0.7278,0.6487,0.5031,0.2776"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.5838,0.5672,0.5389,0.4949,0.4178,0.2801,0.0701",\ +"0.5918,0.5752,0.5469,0.5029,0.4258,0.2881,0.0781",\ +"0.6008,0.5842,0.5559,0.5120,0.4348,0.2971,0.0871",\ +"0.6140,0.5974,0.5690,0.5251,0.4480,0.3103,0.1003",\ +"0.6382,0.6216,0.5933,0.5494,0.4722,0.3345,0.1246",\ +"0.6688,0.6522,0.6238,0.5799,0.5028,0.3650,0.1551",\ +"0.7502,0.7336,0.7053,0.6613,0.5842,0.4465,0.2366"); + } + } +} + pin(A_BIST_CLK) { + direction : input; + capacitance : 0.00378957; + max_transition : "0.5952"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.008,0.5952"); + values("0.4,0.4"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0.5206); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (15.8889); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (15.7957); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (12.1067); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.3170); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.5148); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_BIST_DIN) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00226348 ; + memory_write() { + address : A_BIST_ADDR ; + clocked_on : A_BIST_CLK; + } + + max_transition : "0.5952" ; + pin(A_BIST_DIN[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0236); + } + fall_power("scalar"){ + values (0.0075); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0230); + } + fall_power("scalar"){ + values (0.0072); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5355,-0.5160,-0.4896,-0.4476,-0.3665,-0.2220,-0.0013",\ +"-0.5435,-0.5240,-0.4976,-0.4556,-0.3746,-0.2300,-0.0093",\ +"-0.5525,-0.5330,-0.5066,-0.4646,-0.3836,-0.2390,-0.0183",\ +"-0.5657,-0.5461,-0.5198,-0.4778,-0.3967,-0.2522,-0.0315",\ +"-0.5899,-0.5704,-0.5440,-0.5021,-0.4210,-0.2765,-0.0558",\ +"-0.6205,-0.6009,-0.5746,-0.5326,-0.4515,-0.3070,-0.0863",\ +"-0.7019,-0.6824,-0.6560,-0.6140,-0.5330,-0.3884,-0.1677"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.4798,-0.4642,-0.4359,-0.3968,-0.3158,-0.1781,0.0339",\ +"-0.4878,-0.4722,-0.4439,-0.4048,-0.3238,-0.1861,0.0258",\ +"-0.4968,-0.4812,-0.4529,-0.4138,-0.3328,-0.1951,0.0168",\ +"-0.5100,-0.4944,-0.4661,-0.4270,-0.3459,-0.2082,0.0037",\ +"-0.5343,-0.5187,-0.4903,-0.4513,-0.3702,-0.2325,-0.0206",\ +"-0.5648,-0.5492,-0.5208,-0.4818,-0.4007,-0.2630,-0.0511",\ +"-0.6462,-0.6306,-0.6023,-0.5632,-0.4822,-0.3445,-0.1326"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6521,0.6307,0.6043,0.5613,0.4822,0.3367,0.1111",\ +"0.6602,0.6387,0.6123,0.5693,0.4902,0.3447,0.1192",\ +"0.6692,0.6477,0.6213,0.5784,0.4993,0.3537,0.1282",\ +"0.6823,0.6608,0.6345,0.5915,0.5124,0.3669,0.1413",\ +"0.7066,0.6851,0.6588,0.6158,0.5367,0.3912,0.1656",\ +"0.7371,0.7156,0.6893,0.6463,0.5672,0.4217,0.1961",\ +"0.8186,0.7971,0.7707,0.7278,0.6487,0.5031,0.2776"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.5838,0.5672,0.5389,0.4949,0.4178,0.2801,0.0701",\ +"0.5918,0.5752,0.5469,0.5029,0.4258,0.2881,0.0781",\ +"0.6008,0.5842,0.5559,0.5120,0.4348,0.2971,0.0871",\ +"0.6140,0.5974,0.5690,0.5251,0.4480,0.3103,0.1003",\ +"0.6382,0.6216,0.5933,0.5494,0.4722,0.3345,0.1246",\ +"0.6688,0.6522,0.6238,0.5799,0.5028,0.3650,0.1551",\ +"0.7502,0.7336,0.7053,0.6613,0.5842,0.4465,0.2366"); + } + } + } + +bus(A_DOUT) { + + bus_type : D_7_0; + direction : output ; + capacitance : 0 ; + max_capacitance : "6.4e-14" ; + memory_read() { + address : A_ADDR ; + } + pin(A_DOUT[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "A_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("7.0497,7.0524,7.0646,7.0788,7.1314,7.1863",\ +"7.0651,7.0678,7.0800,7.0942,7.1468,7.2018",\ +"7.0715,7.0742,7.0863,7.1006,7.1531,7.2081",\ +"7.0921,7.0949,7.1070,7.1212,7.1738,7.2288",\ +"7.1096,7.1123,7.1245,7.1387,7.1913,7.2462",\ +"7.1454,7.1481,7.1602,7.1744,7.2270,7.2820",\ +"7.2157,7.2184,7.2306,7.2448,7.2974,7.3524"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("6.9395,6.9417,6.9515,6.9633,7.0068,7.0506",\ +"6.9549,6.9571,6.9669,6.9787,7.0223,7.0660",\ +"6.9613,6.9634,6.9732,6.9850,7.0286,7.0723",\ +"6.9820,6.9841,6.9939,7.0057,7.0493,7.0930",\ +"6.9994,7.0016,7.0113,7.0232,7.0667,7.1105",\ +"7.0352,7.0373,7.0471,7.0589,7.1025,7.1462",\ +"7.1055,7.1077,7.1175,7.1293,7.1729,7.2166"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0560,0.0583,0.0696,0.0816,0.1519,0.2335"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0428,0.0445,0.0538,0.0658,0.1181,0.1751"); + } + } +} +cell_leakage_power : 653.2941; +} +} diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_1024x8_c2_bm_bist_typ_1p20V_25C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_1024x8_c2_bm_bist_typ_1p20V_25C.lib new file mode 100644 index 0000000000..2f551b9b5e --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_1024x8_c2_bm_bist_typ_1p20V_25C.lib @@ -0,0 +1,1525 @@ +/* ------------------------------------------------------*/ +/**/ +/* Copyright 2024 IHP PDK Authors*/ +/**/ +/* Licensed under the Apache License, Version 2.0 (the "License");*/ +/* you may not use this file except in compliance with the License.*/ +/* You may obtain a copy of the License at*/ +/* */ +/* https://www.apache.org/licenses/LICENSE-2.0*/ +/* */ +/* Unless required by applicable law or agreed to in writing, software*/ +/* distributed under the License is distributed on an "AS IS" BASIS,*/ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/ +/* See the License for the specific language governing permissions and*/ +/* limitations under the License.*/ +/* */ +/* Generated on Fri Jul 19 09:01:13 2024 */ +/* */ +/* ------------------------------------------------------ */ +library(RM_IHPSG13_1P_1024x8_c2_bm_bist_typ_1p20V_25C) { + technology (cmos) ; + delay_model : table_lookup ; + define ("add_pg_pin_to_lib", "library", "boolean"); + add_pg_pin_to_lib : true; + voltage_map ( VDD, 1.20); + voltage_map ( VDDARRAY, 1.20); + voltage_map ( VSS, 0.000000 ); + + date : "Fri Jul 19 09:01:10 2024" ; + comment : "IHP Microelectronics GmbH, 2024" ; + revision : 1.0.0 ; + simulation : true ; + nom_process : 1 ; + nom_temperature : 25 ; + nom_voltage : 1.20 ; + + operating_conditions("typ_1p20V_25C"){ + process : 1 ; + temperature : 25 ; + voltage : 1.20 ; + tree_type : "balanced_tree" ; + } + + default_operating_conditions : typ_1p20V_25C ; + default_max_transition : 1.0 ; + default_fanout_load : 1.0 ; + default_inout_pin_cap : 0.0 ; + default_input_pin_cap : 0.0 ; + default_output_pin_cap : 0.0 ; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + + slew_lower_threshold_pct_rise : 30 ; + slew_upper_threshold_pct_rise : 70 ; + input_threshold_pct_fall : 50 ; + output_threshold_pct_fall : 50 ; + input_threshold_pct_rise : 50 ; + output_threshold_pct_rise : 50 ; + slew_lower_threshold_pct_fall : 30 ; + slew_upper_threshold_pct_fall : 70 ; + slew_derate_from_library : 0.5; + k_volt_cell_leakage_power : 0.0 ; + k_temp_cell_leakage_power : 0.0 ; + k_process_cell_leakage_power : 0.0 ; + k_volt_internal_power : 0.0 ; + k_temp_internal_power : 0.0 ; + k_process_internal_power : 0.0 ; + + capacitive_load_unit (1,pf) ; + voltage_unit : "1V" ; + current_unit : "1uA" ; + time_unit : "1ns" ; + leakage_power_unit : "1nW" ; + pulling_resistance_unit : "1kohm"; + /* + ------------------------------------------------------------------------------------------ + implicit units overview: + cell_area unit : "um" + internal_power unit : "1e-12 * J/toggle = 1 * uW/MHz" + (capacitive_load_unit * voltage_unit^2) per toggle event + ------------------------------------------------------------------------------------------ + */ + library_features(report_delay_calculation); + define_cell_area (pad_drivers,pad_driver_sites) ; + + lu_table_template(CLKTRAN_constraint_template) { + variable_1 : constrained_pin_transition; + index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" ); + } + lu_table_template(SRAM_load_template) { + variable_1 : total_output_net_capacitance; + index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + lu_table_template(SIG2SRAM_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" ); + index_2 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" ); + } + + lu_table_template(SIG2SRAM_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" ); + index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + + type (D_7_0) { + base_type : array; + data_type : bit; + bit_width : 8; + bit_from : 7; + bit_to : 0; + downto : true; + } + + type (A_9_0) { + base_type : array; + data_type : bit; + bit_width : 10; + bit_from : 9; + bit_to : 0; + downto : true; + } + +cell(RM_IHPSG13_1P_1024x8_c2_bm_bist) { +pg_pin (VDD) { + pg_type : primary_power; + voltage_name : VDD; +} +pg_pin (VDDARRAY) { + pg_type : primary_power; + voltage_name : VDDARRAY; +} +pg_pin (VSS) { + pg_type : primary_ground; + voltage_name : VSS; +} + +memory() { + type : ram; + address_width : 10; + word_width : 8; +} + +interface_timing : false; +bus_naming_style : "%s[%d]" ; +area : 49419.2448 ; + + pin(A_DLY) { + direction : input ; + capacitance : 0.00401111 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_ADDR) { + bus_type : A_9_0; + direction : input ; + capacitance : 0.00721489 ; + pin(A_ADDR[0]) { + capacitance : 0.00593979 ; + } + pin(A_ADDR[1]) { + capacitance : 0.00483009 ; + } + pin(A_ADDR[2]) { + capacitance : 0.006215 ; + } + pin(A_ADDR[3]) { + capacitance : 0.00766726 ; + } + pin(A_ADDR[4]) { + capacitance : 0.00488951 ; + } + pin(A_ADDR[5]) { + capacitance : 0.0091523 ; + } + pin(A_ADDR[6]) { + capacitance : 0.0109212 ; + } + pin(A_ADDR[7]) { + capacitance : 0.00774122 ; + } + pin(A_ADDR[8]) { + capacitance : 0.0101403 ; + } + max_transition : "0.476" ; + pin(A_ADDR[9:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0122); + } + fall_power("scalar"){ + values (0.0064); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0205); + } + fall_power("scalar"){ + values (0.0016); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4168,-0.3973,-0.3855,-0.3543,-0.3074,-0.2020,-0.0027",\ +"-0.4324,-0.4129,-0.4012,-0.3699,-0.3191,-0.2176,-0.0184",\ +"-0.4441,-0.4285,-0.4129,-0.3816,-0.3309,-0.2293,-0.0301",\ +"-0.4793,-0.4598,-0.4441,-0.4129,-0.3660,-0.2645,-0.0652",\ +"-0.5223,-0.5066,-0.4910,-0.4598,-0.4129,-0.3074,-0.1121",\ +"-0.6199,-0.6082,-0.5926,-0.5613,-0.5145,-0.4129,-0.2137",\ +"-0.8191,-0.8074,-0.7840,-0.7566,-0.7098,-0.6082,-0.4051"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3309,-0.3113,-0.2996,-0.2684,-0.2176,-0.1238,0.0637",\ +"-0.3465,-0.3309,-0.3152,-0.2840,-0.2332,-0.1395,0.0480",\ +"-0.3582,-0.3426,-0.3270,-0.2996,-0.2488,-0.1512,0.0324",\ +"-0.3895,-0.3738,-0.3582,-0.3309,-0.2801,-0.1863,0.0051",\ +"-0.4363,-0.4207,-0.4051,-0.3777,-0.3230,-0.2293,-0.0379",\ +"-0.5379,-0.5223,-0.5066,-0.4793,-0.4285,-0.3309,-0.1434",\ +"-0.7332,-0.7176,-0.7020,-0.6746,-0.6238,-0.5262,-0.3387"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5246,0.5051,0.4895,0.4582,0.4113,0.3059,0.1066",\ +"0.5402,0.5207,0.5051,0.4777,0.4270,0.3215,0.1223",\ +"0.5520,0.5324,0.5168,0.4895,0.4387,0.3371,0.1340",\ +"0.5832,0.5676,0.5520,0.5207,0.4738,0.3684,0.1691",\ +"0.6301,0.6105,0.5949,0.5676,0.5168,0.4113,0.2160",\ +"0.7316,0.7121,0.7004,0.6691,0.6223,0.5168,0.3176",\ +"0.9270,0.9230,0.8957,0.8645,0.8137,0.7121,0.5168"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4309,0.4152,0.4035,0.3684,0.3215,0.2277,0.0363",\ +"0.4465,0.4309,0.4152,0.3879,0.3371,0.2395,0.0559",\ +"0.4582,0.4426,0.4309,0.3996,0.3488,0.2551,0.0715",\ +"0.4934,0.4777,0.4621,0.4348,0.3840,0.2863,0.0988",\ +"0.5363,0.5207,0.5051,0.4777,0.4270,0.3332,0.1418",\ +"0.6379,0.6262,0.6105,0.5793,0.5324,0.4348,0.2434",\ +"0.8332,0.8215,0.8059,0.7707,0.7238,0.6301,0.4387"); + } + } +} +pin(A_WEN) { + direction : input ; + capacitance : 0.00324098 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0046); + } + fall_power("scalar"){ + values (0.0038); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0042); + } + fall_power("scalar"){ + values (0.0038); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2629,0.3059,0.4113,0.6066",\ +"0.1887,0.2043,0.2160,0.2473,0.2941,0.3957,0.5949",\ +"0.1691,0.1848,0.2004,0.2316,0.2785,0.3801,0.5754",\ +"0.1379,0.1574,0.1691,0.2004,0.2473,0.3527,0.5480",\ +"0.0910,0.1066,0.1223,0.1535,0.2004,0.2980,0.4973",\ +"-0.0105,0.0051,0.0207,0.0520,0.0949,0.2004,0.3957",\ +"-0.2059,-0.1902,-0.1746,-0.1473,-0.1004,0.0051,0.2004"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2941,0.3098,0.3215,0.3488,0.4035,0.4973,0.6887",\ +"0.2785,0.2941,0.3059,0.3332,0.3840,0.4816,0.6691",\ +"0.2629,0.2785,0.2902,0.3176,0.3684,0.4660,0.6535",\ +"0.2316,0.2473,0.2590,0.2863,0.3410,0.4348,0.6262",\ +"0.1848,0.2004,0.2121,0.2395,0.2902,0.3879,0.5754",\ +"0.0832,0.0988,0.1105,0.1379,0.1809,0.2746,0.4699",\ +"-0.1121,-0.0965,-0.0848,-0.0535,-0.0066,0.0910,0.2824"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2473,0.2316,0.2160,0.1887,0.1379,0.0363,-0.1629",\ +"0.2629,0.2473,0.2316,0.2043,0.1535,0.0520,-0.1473",\ +"0.2785,0.2590,0.2434,0.2160,0.1652,0.0676,-0.1355",\ +"0.3098,0.2941,0.2785,0.2473,0.1965,0.0910,-0.1043",\ +"0.3527,0.3371,0.3215,0.2941,0.2434,0.1418,-0.0574",\ +"0.4582,0.4426,0.4270,0.3957,0.3488,0.2434,0.0480",\ +"0.6535,0.6379,0.6184,0.5910,0.5402,0.4426,0.2434"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2395,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2668,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2395,0.1887,0.0910,-0.0965",\ +"0.3449,0.3293,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4191,0.3879,0.3371,0.2395,0.0559",\ +"0.6457,0.6301,0.6145,0.5871,0.5324,0.4309,0.2512"); + } + } + } +pin(A_REN) { + direction : input ; + capacitance : 0.00381634 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0061); + } + fall_power("scalar"){ + values (0.0020); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0062); + } + fall_power("scalar"){ + values (0.0024); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.0301,-0.0145,0.0012,0.0324,0.0793,0.1809,0.3762",\ +"-0.0457,-0.0301,-0.0145,0.0168,0.0637,0.1613,0.3605",\ +"-0.0574,-0.0418,-0.0262,0.0051,0.0520,0.1496,0.3449",\ +"-0.0926,-0.0730,-0.0574,-0.0262,0.0207,0.1184,0.3137",\ +"-0.1395,-0.1238,-0.1082,-0.0770,-0.0301,0.0715,0.2707",\ +"-0.2410,-0.2254,-0.2098,-0.1746,-0.1355,-0.0340,0.1652",\ +"-0.4402,-0.4207,-0.4051,-0.3738,-0.3270,-0.2293,-0.0340"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.0988,0.1145,0.1262,0.1535,0.2043,0.3020,0.4855",\ +"0.0832,0.0988,0.1105,0.1418,0.1848,0.2824,0.4738",\ +"0.0676,0.0832,0.0949,0.1262,0.1730,0.2668,0.4621",\ +"0.0402,0.0559,0.0676,0.0988,0.1457,0.2434,0.4191",\ +"-0.0105,0.0012,0.0168,0.0480,0.0988,0.1965,0.3840",\ +"-0.1160,-0.0965,-0.0848,-0.0535,-0.0066,0.0988,0.2824",\ +"-0.3113,-0.2957,-0.2801,-0.2527,-0.2059,-0.1043,0.0832"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2707,0.2551,0.2395,0.2121,0.1613,0.0598,-0.1395",\ +"0.2863,0.2707,0.2551,0.2238,0.1730,0.0715,-0.1238",\ +"0.2980,0.2824,0.2668,0.2395,0.1887,0.0871,-0.1121",\ +"0.3332,0.3176,0.3020,0.2707,0.2199,0.1184,-0.0809",\ +"0.3762,0.3605,0.3449,0.3176,0.2668,0.1613,-0.0340",\ +"0.4816,0.4621,0.4504,0.4191,0.3723,0.2629,0.0715",\ +"0.6770,0.6613,0.6418,0.6184,0.5637,0.4699,0.2629"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2590,0.2434,0.2316,0.2004,0.1457,0.0520,-0.1355",\ +"0.2746,0.2590,0.2434,0.2160,0.1613,0.0676,-0.1199",\ +"0.2863,0.2707,0.2590,0.2277,0.1730,0.0832,-0.1082",\ +"0.3215,0.3059,0.2902,0.2590,0.2082,0.1105,-0.0770",\ +"0.3645,0.3488,0.3332,0.3059,0.2551,0.1535,-0.0340",\ +"0.4699,0.4543,0.4387,0.4074,0.3605,0.2551,0.0715",\ +"0.6652,0.6496,0.6340,0.6027,0.5520,0.4621,0.2707"); + } + } + } +pin(A_MEN) { + direction : input ; + capacitance : 0.00309605 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0236); + } + fall_power("scalar"){ + values (0.0052); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2668,0.3098,0.4152,0.6066",\ +"0.1887,0.2043,0.2199,0.2512,0.2941,0.3996,0.5949",\ +"0.1730,0.1887,0.2043,0.2355,0.2824,0.3840,0.5793",\ +"0.1418,0.1574,0.1730,0.2043,0.2512,0.3566,0.5480",\ +"0.0949,0.1105,0.1262,0.1574,0.2043,0.3020,0.5051",\ +"-0.0066,0.0090,0.0246,0.0520,0.0988,0.2043,0.3996",\ +"-0.2020,-0.1863,-0.1746,-0.1434,-0.0965,0.0090,0.2082"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2980,0.3137,0.3254,0.3527,0.4035,0.5012,0.6887",\ +"0.2824,0.2980,0.3098,0.3371,0.3879,0.4855,0.6730",\ +"0.2668,0.2824,0.2941,0.3215,0.3723,0.4699,0.6574",\ +"0.2355,0.2473,0.2629,0.2902,0.3410,0.4387,0.6262",\ +"0.1887,0.2004,0.2160,0.2395,0.2941,0.3918,0.5793",\ +"0.0871,0.1027,0.1145,0.1418,0.1848,0.2746,0.4816",\ +"-0.1082,-0.0965,-0.0809,-0.0496,-0.0027,0.0949,0.2863"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2512,0.2355,0.2199,0.1926,0.1418,0.0402,-0.1590",\ +"0.2668,0.2512,0.2355,0.2082,0.1574,0.0559,-0.1434",\ +"0.2824,0.2629,0.2512,0.2199,0.1691,0.0715,-0.1316",\ +"0.3137,0.2980,0.2824,0.2512,0.2004,0.0988,-0.0965",\ +"0.3566,0.3410,0.3254,0.2980,0.2473,0.1418,-0.0535",\ +"0.4621,0.4426,0.4309,0.3996,0.3527,0.2473,0.0520",\ +"0.6574,0.6418,0.6262,0.5949,0.5441,0.4465,0.2473"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2434,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2707,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2434,0.1926,0.0910,-0.0965",\ +"0.3449,0.3332,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4230,0.3918,0.3410,0.2434,0.0559",\ +"0.6457,0.6301,0.6145,0.5910,0.5324,0.4387,0.2512"); + } + } + } +bus(A_BM) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00285703 ; + max_transition : "0.476" ; + pin(A_BM[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0299); + } + fall_power("scalar"){ + values (0.0123); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0317); + } + fall_power("scalar"){ + values (0.0122); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.2903,-0.2736,-0.2610,-0.2287,-0.1819,-0.0774,0.1150",\ +"-0.2953,-0.2787,-0.2660,-0.2337,-0.1869,-0.0824,0.1100",\ +"-0.2997,-0.2831,-0.2704,-0.2382,-0.1913,-0.0868,0.1056",\ +"-0.3095,-0.2929,-0.2802,-0.2480,-0.2011,-0.0966,0.0957",\ +"-0.3159,-0.2993,-0.2866,-0.2544,-0.2075,-0.1030,0.0894",\ +"-0.3524,-0.3358,-0.3231,-0.2909,-0.2440,-0.1395,0.0529",\ +"-0.4032,-0.3866,-0.3739,-0.3417,-0.2949,-0.1904,0.0020"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.2580,-0.2424,-0.2297,-0.2014,-0.1506,-0.0520,0.1267",\ +"-0.2630,-0.2474,-0.2347,-0.2064,-0.1556,-0.0570,0.1217",\ +"-0.2675,-0.2518,-0.2391,-0.2108,-0.1600,-0.0614,0.1173",\ +"-0.2773,-0.2617,-0.2490,-0.2207,-0.1699,-0.0713,0.1074",\ +"-0.2837,-0.2680,-0.2553,-0.2270,-0.1762,-0.0776,0.1011",\ +"-0.3201,-0.3045,-0.2918,-0.2635,-0.2127,-0.1141,0.0646",\ +"-0.3710,-0.3554,-0.3427,-0.3144,-0.2636,-0.1650,0.0137"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.3991,0.3835,0.3708,0.3385,0.2897,0.1911,-0.0052",\ +"0.4041,0.3885,0.3758,0.3435,0.2947,0.1961,-0.0002",\ +"0.4085,0.3929,0.3802,0.3480,0.2992,0.2005,0.0042",\ +"0.4184,0.4027,0.3901,0.3578,0.3090,0.2104,0.0141",\ +"0.4247,0.4091,0.3964,0.3642,0.3153,0.2167,0.0204",\ +"0.4612,0.4456,0.4329,0.4007,0.3518,0.2532,0.0569",\ +"0.5121,0.4965,0.4838,0.4515,0.4027,0.3041,0.1078"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.3590,0.3444,0.3307,0.3024,0.2516,0.1588,-0.0296",\ +"0.3641,0.3494,0.3357,0.3074,0.2566,0.1639,-0.0246",\ +"0.3685,0.3538,0.3402,0.3118,0.2611,0.1683,-0.0202",\ +"0.3783,0.3637,0.3500,0.3217,0.2709,0.1781,-0.0103",\ +"0.3847,0.3700,0.3564,0.3280,0.2773,0.1845,-0.0040",\ +"0.4212,0.4065,0.3928,0.3645,0.3137,0.2210,0.0325",\ +"0.4720,0.4574,0.4437,0.4154,0.3646,0.2718,0.0834"); + } + } +} + pin(A_CLK) { + direction : input; + capacitance : 0.00380014; + max_transition : "0.476"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.0056,0.476"); + values("0.21,0.21"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (0.5550); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (19.9179); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (19.7017); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (15.5961); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (0.3069); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (0.5410); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_DIN) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00365723 ; + memory_write() { + address : A_ADDR ; + clocked_on : A_CLK; + } + + max_transition : "0.476" ; + pin(A_DIN[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0299); + } + fall_power("scalar"){ + values (0.0123); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0317); + } + fall_power("scalar"){ + values (0.0122); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.2903,-0.2736,-0.2610,-0.2287,-0.1819,-0.0774,0.1150",\ +"-0.2953,-0.2787,-0.2660,-0.2337,-0.1869,-0.0824,0.1100",\ +"-0.2997,-0.2831,-0.2704,-0.2382,-0.1913,-0.0868,0.1056",\ +"-0.3095,-0.2929,-0.2802,-0.2480,-0.2011,-0.0966,0.0957",\ +"-0.3159,-0.2993,-0.2866,-0.2544,-0.2075,-0.1030,0.0894",\ +"-0.3524,-0.3358,-0.3231,-0.2909,-0.2440,-0.1395,0.0529",\ +"-0.4032,-0.3866,-0.3739,-0.3417,-0.2949,-0.1904,0.0020"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.2580,-0.2424,-0.2297,-0.2014,-0.1506,-0.0520,0.1267",\ +"-0.2630,-0.2474,-0.2347,-0.2064,-0.1556,-0.0570,0.1217",\ +"-0.2675,-0.2518,-0.2391,-0.2108,-0.1600,-0.0614,0.1173",\ +"-0.2773,-0.2617,-0.2490,-0.2207,-0.1699,-0.0713,0.1074",\ +"-0.2837,-0.2680,-0.2553,-0.2270,-0.1762,-0.0776,0.1011",\ +"-0.3201,-0.3045,-0.2918,-0.2635,-0.2127,-0.1141,0.0646",\ +"-0.3710,-0.3554,-0.3427,-0.3144,-0.2636,-0.1650,0.0137"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.3991,0.3835,0.3708,0.3385,0.2897,0.1911,-0.0052",\ +"0.4041,0.3885,0.3758,0.3435,0.2947,0.1961,-0.0002",\ +"0.4085,0.3929,0.3802,0.3480,0.2992,0.2005,0.0042",\ +"0.4184,0.4027,0.3901,0.3578,0.3090,0.2104,0.0141",\ +"0.4247,0.4091,0.3964,0.3642,0.3153,0.2167,0.0204",\ +"0.4612,0.4456,0.4329,0.4007,0.3518,0.2532,0.0569",\ +"0.5121,0.4965,0.4838,0.4515,0.4027,0.3041,0.1078"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.3590,0.3444,0.3307,0.3024,0.2516,0.1588,-0.0296",\ +"0.3641,0.3494,0.3357,0.3074,0.2566,0.1639,-0.0246",\ +"0.3685,0.3538,0.3402,0.3118,0.2611,0.1683,-0.0202",\ +"0.3783,0.3637,0.3500,0.3217,0.2709,0.1781,-0.0103",\ +"0.3847,0.3700,0.3564,0.3280,0.2773,0.1845,-0.0040",\ +"0.4212,0.4065,0.3928,0.3645,0.3137,0.2210,0.0325",\ +"0.4720,0.4574,0.4437,0.4154,0.3646,0.2718,0.0834"); + } + } + } + + pin(A_BIST_EN) { + direction : input ; + capacitance : 0.00401111 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_BIST_ADDR) { + bus_type : A_9_0; + direction : input ; + capacitance : 0.00721489 ; + pin(A_BIST_ADDR[0]) { + capacitance : 0.00593979 ; + } + pin(A_BIST_ADDR[1]) { + capacitance : 0.00483009 ; + } + pin(A_BIST_ADDR[2]) { + capacitance : 0.006215 ; + } + pin(A_BIST_ADDR[3]) { + capacitance : 0.00766726 ; + } + pin(A_BIST_ADDR[4]) { + capacitance : 0.00488951 ; + } + pin(A_BIST_ADDR[5]) { + capacitance : 0.0091523 ; + } + pin(A_BIST_ADDR[6]) { + capacitance : 0.0109212 ; + } + pin(A_BIST_ADDR[7]) { + capacitance : 0.00774122 ; + } + pin(A_BIST_ADDR[8]) { + capacitance : 0.0101403 ; + } + max_transition : "0.476" ; + pin(A_BIST_ADDR[9:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0122); + } + fall_power("scalar"){ + values (0.0064); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0205); + } + fall_power("scalar"){ + values (0.0016); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4168,-0.3973,-0.3855,-0.3543,-0.3074,-0.2020,-0.0027",\ +"-0.4324,-0.4129,-0.4012,-0.3699,-0.3191,-0.2176,-0.0184",\ +"-0.4441,-0.4285,-0.4129,-0.3816,-0.3309,-0.2293,-0.0301",\ +"-0.4793,-0.4598,-0.4441,-0.4129,-0.3660,-0.2645,-0.0652",\ +"-0.5223,-0.5066,-0.4910,-0.4598,-0.4129,-0.3074,-0.1121",\ +"-0.6199,-0.6082,-0.5926,-0.5613,-0.5145,-0.4129,-0.2137",\ +"-0.8191,-0.8074,-0.7840,-0.7566,-0.7098,-0.6082,-0.4051"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3309,-0.3113,-0.2996,-0.2684,-0.2176,-0.1238,0.0637",\ +"-0.3465,-0.3309,-0.3152,-0.2840,-0.2332,-0.1395,0.0480",\ +"-0.3582,-0.3426,-0.3270,-0.2996,-0.2488,-0.1512,0.0324",\ +"-0.3895,-0.3738,-0.3582,-0.3309,-0.2801,-0.1863,0.0051",\ +"-0.4363,-0.4207,-0.4051,-0.3777,-0.3230,-0.2293,-0.0379",\ +"-0.5379,-0.5223,-0.5066,-0.4793,-0.4285,-0.3309,-0.1434",\ +"-0.7332,-0.7176,-0.7020,-0.6746,-0.6238,-0.5262,-0.3387"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5246,0.5051,0.4895,0.4582,0.4113,0.3059,0.1066",\ +"0.5402,0.5207,0.5051,0.4777,0.4270,0.3215,0.1223",\ +"0.5520,0.5324,0.5168,0.4895,0.4387,0.3371,0.1340",\ +"0.5832,0.5676,0.5520,0.5207,0.4738,0.3684,0.1691",\ +"0.6301,0.6105,0.5949,0.5676,0.5168,0.4113,0.2160",\ +"0.7316,0.7121,0.7004,0.6691,0.6223,0.5168,0.3176",\ +"0.9270,0.9230,0.8957,0.8645,0.8137,0.7121,0.5168"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4309,0.4152,0.4035,0.3684,0.3215,0.2277,0.0363",\ +"0.4465,0.4309,0.4152,0.3879,0.3371,0.2395,0.0559",\ +"0.4582,0.4426,0.4309,0.3996,0.3488,0.2551,0.0715",\ +"0.4934,0.4777,0.4621,0.4348,0.3840,0.2863,0.0988",\ +"0.5363,0.5207,0.5051,0.4777,0.4270,0.3332,0.1418",\ +"0.6379,0.6262,0.6105,0.5793,0.5324,0.4348,0.2434",\ +"0.8332,0.8215,0.8059,0.7707,0.7238,0.6301,0.4387"); + } + } +} +pin(A_BIST_WEN) { + direction : input ; + capacitance : 0.00324098 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0046); + } + fall_power("scalar"){ + values (0.0038); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0042); + } + fall_power("scalar"){ + values (0.0038); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2629,0.3059,0.4113,0.6066",\ +"0.1887,0.2043,0.2160,0.2473,0.2941,0.3957,0.5949",\ +"0.1691,0.1848,0.2004,0.2316,0.2785,0.3801,0.5754",\ +"0.1379,0.1574,0.1691,0.2004,0.2473,0.3527,0.5480",\ +"0.0910,0.1066,0.1223,0.1535,0.2004,0.2980,0.4973",\ +"-0.0105,0.0051,0.0207,0.0520,0.0949,0.2004,0.3957",\ +"-0.2059,-0.1902,-0.1746,-0.1473,-0.1004,0.0051,0.2004"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2941,0.3098,0.3215,0.3488,0.4035,0.4973,0.6887",\ +"0.2785,0.2941,0.3059,0.3332,0.3840,0.4816,0.6691",\ +"0.2629,0.2785,0.2902,0.3176,0.3684,0.4660,0.6535",\ +"0.2316,0.2473,0.2590,0.2863,0.3410,0.4348,0.6262",\ +"0.1848,0.2004,0.2121,0.2395,0.2902,0.3879,0.5754",\ +"0.0832,0.0988,0.1105,0.1379,0.1809,0.2746,0.4699",\ +"-0.1121,-0.0965,-0.0848,-0.0535,-0.0066,0.0910,0.2824"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2473,0.2316,0.2160,0.1887,0.1379,0.0363,-0.1629",\ +"0.2629,0.2473,0.2316,0.2043,0.1535,0.0520,-0.1473",\ +"0.2785,0.2590,0.2434,0.2160,0.1652,0.0676,-0.1355",\ +"0.3098,0.2941,0.2785,0.2473,0.1965,0.0910,-0.1043",\ +"0.3527,0.3371,0.3215,0.2941,0.2434,0.1418,-0.0574",\ +"0.4582,0.4426,0.4270,0.3957,0.3488,0.2434,0.0480",\ +"0.6535,0.6379,0.6184,0.5910,0.5402,0.4426,0.2434"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2395,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2668,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2395,0.1887,0.0910,-0.0965",\ +"0.3449,0.3293,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4191,0.3879,0.3371,0.2395,0.0559",\ +"0.6457,0.6301,0.6145,0.5871,0.5324,0.4309,0.2512"); + } + } + } +pin(A_BIST_REN) { + direction : input ; + capacitance : 0.00381634 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0061); + } + fall_power("scalar"){ + values (0.0020); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0062); + } + fall_power("scalar"){ + values (0.0024); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.0301,-0.0145,0.0012,0.0324,0.0793,0.1809,0.3762",\ +"-0.0457,-0.0301,-0.0145,0.0168,0.0637,0.1613,0.3605",\ +"-0.0574,-0.0418,-0.0262,0.0051,0.0520,0.1496,0.3449",\ +"-0.0926,-0.0730,-0.0574,-0.0262,0.0207,0.1184,0.3137",\ +"-0.1395,-0.1238,-0.1082,-0.0770,-0.0301,0.0715,0.2707",\ +"-0.2410,-0.2254,-0.2098,-0.1746,-0.1355,-0.0340,0.1652",\ +"-0.4402,-0.4207,-0.4051,-0.3738,-0.3270,-0.2293,-0.0340"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.0988,0.1145,0.1262,0.1535,0.2043,0.3020,0.4855",\ +"0.0832,0.0988,0.1105,0.1418,0.1848,0.2824,0.4738",\ +"0.0676,0.0832,0.0949,0.1262,0.1730,0.2668,0.4621",\ +"0.0402,0.0559,0.0676,0.0988,0.1457,0.2434,0.4191",\ +"-0.0105,0.0012,0.0168,0.0480,0.0988,0.1965,0.3840",\ +"-0.1160,-0.0965,-0.0848,-0.0535,-0.0066,0.0988,0.2824",\ +"-0.3113,-0.2957,-0.2801,-0.2527,-0.2059,-0.1043,0.0832"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2707,0.2551,0.2395,0.2121,0.1613,0.0598,-0.1395",\ +"0.2863,0.2707,0.2551,0.2238,0.1730,0.0715,-0.1238",\ +"0.2980,0.2824,0.2668,0.2395,0.1887,0.0871,-0.1121",\ +"0.3332,0.3176,0.3020,0.2707,0.2199,0.1184,-0.0809",\ +"0.3762,0.3605,0.3449,0.3176,0.2668,0.1613,-0.0340",\ +"0.4816,0.4621,0.4504,0.4191,0.3723,0.2629,0.0715",\ +"0.6770,0.6613,0.6418,0.6184,0.5637,0.4699,0.2629"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2590,0.2434,0.2316,0.2004,0.1457,0.0520,-0.1355",\ +"0.2746,0.2590,0.2434,0.2160,0.1613,0.0676,-0.1199",\ +"0.2863,0.2707,0.2590,0.2277,0.1730,0.0832,-0.1082",\ +"0.3215,0.3059,0.2902,0.2590,0.2082,0.1105,-0.0770",\ +"0.3645,0.3488,0.3332,0.3059,0.2551,0.1535,-0.0340",\ +"0.4699,0.4543,0.4387,0.4074,0.3605,0.2551,0.0715",\ +"0.6652,0.6496,0.6340,0.6027,0.5520,0.4621,0.2707"); + } + } + } +pin(A_BIST_MEN) { + direction : input ; + capacitance : 0.00309605 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0236); + } + fall_power("scalar"){ + values (0.0052); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2668,0.3098,0.4152,0.6066",\ +"0.1887,0.2043,0.2199,0.2512,0.2941,0.3996,0.5949",\ +"0.1730,0.1887,0.2043,0.2355,0.2824,0.3840,0.5793",\ +"0.1418,0.1574,0.1730,0.2043,0.2512,0.3566,0.5480",\ +"0.0949,0.1105,0.1262,0.1574,0.2043,0.3020,0.5051",\ +"-0.0066,0.0090,0.0246,0.0520,0.0988,0.2043,0.3996",\ +"-0.2020,-0.1863,-0.1746,-0.1434,-0.0965,0.0090,0.2082"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2980,0.3137,0.3254,0.3527,0.4035,0.5012,0.6887",\ +"0.2824,0.2980,0.3098,0.3371,0.3879,0.4855,0.6730",\ +"0.2668,0.2824,0.2941,0.3215,0.3723,0.4699,0.6574",\ +"0.2355,0.2473,0.2629,0.2902,0.3410,0.4387,0.6262",\ +"0.1887,0.2004,0.2160,0.2395,0.2941,0.3918,0.5793",\ +"0.0871,0.1027,0.1145,0.1418,0.1848,0.2746,0.4816",\ +"-0.1082,-0.0965,-0.0809,-0.0496,-0.0027,0.0949,0.2863"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2512,0.2355,0.2199,0.1926,0.1418,0.0402,-0.1590",\ +"0.2668,0.2512,0.2355,0.2082,0.1574,0.0559,-0.1434",\ +"0.2824,0.2629,0.2512,0.2199,0.1691,0.0715,-0.1316",\ +"0.3137,0.2980,0.2824,0.2512,0.2004,0.0988,-0.0965",\ +"0.3566,0.3410,0.3254,0.2980,0.2473,0.1418,-0.0535",\ +"0.4621,0.4426,0.4309,0.3996,0.3527,0.2473,0.0520",\ +"0.6574,0.6418,0.6262,0.5949,0.5441,0.4465,0.2473"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2434,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2707,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2434,0.1926,0.0910,-0.0965",\ +"0.3449,0.3332,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4230,0.3918,0.3410,0.2434,0.0559",\ +"0.6457,0.6301,0.6145,0.5910,0.5324,0.4387,0.2512"); + } + } + } +bus(A_BIST_BM) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00238379 ; + max_transition : "0.476" ; + pin(A_BIST_BM[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0299); + } + fall_power("scalar"){ + values (0.0123); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0317); + } + fall_power("scalar"){ + values (0.0122); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.2903,-0.2736,-0.2610,-0.2287,-0.1819,-0.0774,0.1150",\ +"-0.2953,-0.2787,-0.2660,-0.2337,-0.1869,-0.0824,0.1100",\ +"-0.2997,-0.2831,-0.2704,-0.2382,-0.1913,-0.0868,0.1056",\ +"-0.3095,-0.2929,-0.2802,-0.2480,-0.2011,-0.0966,0.0957",\ +"-0.3159,-0.2993,-0.2866,-0.2544,-0.2075,-0.1030,0.0894",\ +"-0.3524,-0.3358,-0.3231,-0.2909,-0.2440,-0.1395,0.0529",\ +"-0.4032,-0.3866,-0.3739,-0.3417,-0.2949,-0.1904,0.0020"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.2580,-0.2424,-0.2297,-0.2014,-0.1506,-0.0520,0.1267",\ +"-0.2630,-0.2474,-0.2347,-0.2064,-0.1556,-0.0570,0.1217",\ +"-0.2675,-0.2518,-0.2391,-0.2108,-0.1600,-0.0614,0.1173",\ +"-0.2773,-0.2617,-0.2490,-0.2207,-0.1699,-0.0713,0.1074",\ +"-0.2837,-0.2680,-0.2553,-0.2270,-0.1762,-0.0776,0.1011",\ +"-0.3201,-0.3045,-0.2918,-0.2635,-0.2127,-0.1141,0.0646",\ +"-0.3710,-0.3554,-0.3427,-0.3144,-0.2636,-0.1650,0.0137"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.3991,0.3835,0.3708,0.3385,0.2897,0.1911,-0.0052",\ +"0.4041,0.3885,0.3758,0.3435,0.2947,0.1961,-0.0002",\ +"0.4085,0.3929,0.3802,0.3480,0.2992,0.2005,0.0042",\ +"0.4184,0.4027,0.3901,0.3578,0.3090,0.2104,0.0141",\ +"0.4247,0.4091,0.3964,0.3642,0.3153,0.2167,0.0204",\ +"0.4612,0.4456,0.4329,0.4007,0.3518,0.2532,0.0569",\ +"0.5121,0.4965,0.4838,0.4515,0.4027,0.3041,0.1078"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.3590,0.3444,0.3307,0.3024,0.2516,0.1588,-0.0296",\ +"0.3641,0.3494,0.3357,0.3074,0.2566,0.1639,-0.0246",\ +"0.3685,0.3538,0.3402,0.3118,0.2611,0.1683,-0.0202",\ +"0.3783,0.3637,0.3500,0.3217,0.2709,0.1781,-0.0103",\ +"0.3847,0.3700,0.3564,0.3280,0.2773,0.1845,-0.0040",\ +"0.4212,0.4065,0.3928,0.3645,0.3137,0.2210,0.0325",\ +"0.4720,0.4574,0.4437,0.4154,0.3646,0.2718,0.0834"); + } + } +} + pin(A_BIST_CLK) { + direction : input; + capacitance : 0.00380014; + max_transition : "0.476"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.0056,0.476"); + values("0.21,0.21"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0.5550); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (19.9179); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (19.7017); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (15.5961); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.3069); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.5410); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_BIST_DIN) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00233858 ; + memory_write() { + address : A_BIST_ADDR ; + clocked_on : A_BIST_CLK; + } + + max_transition : "0.476" ; + pin(A_BIST_DIN[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0299); + } + fall_power("scalar"){ + values (0.0123); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0317); + } + fall_power("scalar"){ + values (0.0122); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.2903,-0.2736,-0.2610,-0.2287,-0.1819,-0.0774,0.1150",\ +"-0.2953,-0.2787,-0.2660,-0.2337,-0.1869,-0.0824,0.1100",\ +"-0.2997,-0.2831,-0.2704,-0.2382,-0.1913,-0.0868,0.1056",\ +"-0.3095,-0.2929,-0.2802,-0.2480,-0.2011,-0.0966,0.0957",\ +"-0.3159,-0.2993,-0.2866,-0.2544,-0.2075,-0.1030,0.0894",\ +"-0.3524,-0.3358,-0.3231,-0.2909,-0.2440,-0.1395,0.0529",\ +"-0.4032,-0.3866,-0.3739,-0.3417,-0.2949,-0.1904,0.0020"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.2580,-0.2424,-0.2297,-0.2014,-0.1506,-0.0520,0.1267",\ +"-0.2630,-0.2474,-0.2347,-0.2064,-0.1556,-0.0570,0.1217",\ +"-0.2675,-0.2518,-0.2391,-0.2108,-0.1600,-0.0614,0.1173",\ +"-0.2773,-0.2617,-0.2490,-0.2207,-0.1699,-0.0713,0.1074",\ +"-0.2837,-0.2680,-0.2553,-0.2270,-0.1762,-0.0776,0.1011",\ +"-0.3201,-0.3045,-0.2918,-0.2635,-0.2127,-0.1141,0.0646",\ +"-0.3710,-0.3554,-0.3427,-0.3144,-0.2636,-0.1650,0.0137"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.3991,0.3835,0.3708,0.3385,0.2897,0.1911,-0.0052",\ +"0.4041,0.3885,0.3758,0.3435,0.2947,0.1961,-0.0002",\ +"0.4085,0.3929,0.3802,0.3480,0.2992,0.2005,0.0042",\ +"0.4184,0.4027,0.3901,0.3578,0.3090,0.2104,0.0141",\ +"0.4247,0.4091,0.3964,0.3642,0.3153,0.2167,0.0204",\ +"0.4612,0.4456,0.4329,0.4007,0.3518,0.2532,0.0569",\ +"0.5121,0.4965,0.4838,0.4515,0.4027,0.3041,0.1078"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.3590,0.3444,0.3307,0.3024,0.2516,0.1588,-0.0296",\ +"0.3641,0.3494,0.3357,0.3074,0.2566,0.1639,-0.0246",\ +"0.3685,0.3538,0.3402,0.3118,0.2611,0.1683,-0.0202",\ +"0.3783,0.3637,0.3500,0.3217,0.2709,0.1781,-0.0103",\ +"0.3847,0.3700,0.3564,0.3280,0.2773,0.1845,-0.0040",\ +"0.4212,0.4065,0.3928,0.3645,0.3137,0.2210,0.0325",\ +"0.4720,0.4574,0.4437,0.4154,0.3646,0.2718,0.0834"); + } + } + } + +bus(A_DOUT) { + + bus_type : D_7_0; + direction : output ; + capacitance : 0 ; + max_capacitance : "6.4e-14" ; + memory_read() { + address : A_ADDR ; + } + pin(A_DOUT[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "A_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("4.2177,4.2193,4.2270,4.2357,4.2681,4.3040",\ +"4.2278,4.2294,4.2371,4.2458,4.2782,4.3141",\ +"4.2324,4.2340,4.2417,4.2504,4.2828,4.3187",\ +"4.2402,4.2418,4.2495,4.2582,4.2906,4.3265",\ +"4.2478,4.2494,4.2570,4.2657,4.2982,4.3340",\ +"4.2828,4.2844,4.2921,4.3008,4.3332,4.3691",\ +"4.3362,4.3378,4.3455,4.3542,4.3866,4.4225"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("4.1566,4.1579,4.1639,4.1711,4.1976,4.2242",\ +"4.1667,4.1681,4.1741,4.1812,4.2077,4.2343",\ +"4.1714,4.1727,4.1787,4.1858,4.2123,4.2390",\ +"4.1792,4.1805,4.1865,4.1936,4.2201,4.2468",\ +"4.1867,4.1880,4.1940,4.2012,4.2277,4.2543",\ +"4.2218,4.2231,4.2291,4.2362,4.2627,4.2894",\ +"4.2751,4.2764,4.2824,4.2896,4.3161,4.3427"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0326,0.0341,0.0428,0.0518,0.0923,0.1492"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0254,0.0265,0.0335,0.0402,0.0707,0.1039"); + } + } +} +cell_leakage_power : 99.0077; +} +} diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_4096x16_c3_bm_bist_fast_1p32V_m55C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_4096x16_c3_bm_bist_fast_1p32V_m55C.lib new file mode 100644 index 0000000000..aafc0b323c --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_4096x16_c3_bm_bist_fast_1p32V_m55C.lib @@ -0,0 +1,1537 @@ +/* ------------------------------------------------------*/ +/**/ +/* Copyright 2024 IHP PDK Authors*/ +/**/ +/* Licensed under the Apache License, Version 2.0 (the "License");*/ +/* you may not use this file except in compliance with the License.*/ +/* You may obtain a copy of the License at*/ +/* */ +/* https://www.apache.org/licenses/LICENSE-2.0*/ +/* */ +/* Unless required by applicable law or agreed to in writing, software*/ +/* distributed under the License is distributed on an "AS IS" BASIS,*/ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/ +/* See the License for the specific language governing permissions and*/ +/* limitations under the License.*/ +/* */ +/* Generated on Fri Jul 12 17:37:33 2024 */ +/* */ +/* ------------------------------------------------------ */ +library(RM_IHPSG13_1P_4096x16_c3_bm_bist_fast_1p32V_m55C) { + technology (cmos) ; + delay_model : table_lookup ; + define ("add_pg_pin_to_lib", "library", "boolean"); + add_pg_pin_to_lib : true; + voltage_map ( VDD, 1.32); + voltage_map ( VDDARRAY, 1.32); + voltage_map ( VSS, 0.000000 ); + + date : "Fri Jul 12 17:37:29 2024" ; + comment : "IHP Microelectronics GmbH, 2024" ; + revision : 1.0.0 ; + simulation : true ; + nom_process : 1 ; + nom_temperature : -55 ; + nom_voltage : 1.32 ; + + operating_conditions("fast_1p32V_m55C"){ + process : 1 ; + temperature : -55 ; + voltage : 1.32 ; + tree_type : "balanced_tree" ; + } + + default_operating_conditions : fast_1p32V_m55C ; + default_max_transition : 1.0 ; + default_fanout_load : 1.0 ; + default_inout_pin_cap : 0.0 ; + default_input_pin_cap : 0.0 ; + default_output_pin_cap : 0.0 ; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + + slew_lower_threshold_pct_rise : 30 ; + slew_upper_threshold_pct_rise : 70 ; + input_threshold_pct_fall : 50 ; + output_threshold_pct_fall : 50 ; + input_threshold_pct_rise : 50 ; + output_threshold_pct_rise : 50 ; + slew_lower_threshold_pct_fall : 30 ; + slew_upper_threshold_pct_fall : 70 ; + slew_derate_from_library : 0.5; + k_volt_cell_leakage_power : 0.0 ; + k_temp_cell_leakage_power : 0.0 ; + k_process_cell_leakage_power : 0.0 ; + k_volt_internal_power : 0.0 ; + k_temp_internal_power : 0.0 ; + k_process_internal_power : 0.0 ; + + capacitive_load_unit (1,pf) ; + voltage_unit : "1V" ; + current_unit : "1uA" ; + time_unit : "1ns" ; + leakage_power_unit : "1nW" ; + pulling_resistance_unit : "1kohm"; + /* + ------------------------------------------------------------------------------------------ + implicit units overview: + cell_area unit : "um" + internal_power unit : "1e-12 * J/toggle = 1 * uW/MHz" + (capacitive_load_unit * voltage_unit^2) per toggle event + ------------------------------------------------------------------------------------------ + */ + library_features(report_delay_calculation); + define_cell_area (pad_drivers,pad_driver_sites) ; + + lu_table_template(CLKTRAN_constraint_template) { + variable_1 : constrained_pin_transition; + index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" ); + } + lu_table_template(SRAM_load_template) { + variable_1 : total_output_net_capacitance; + index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + lu_table_template(SIG2SRAM_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" ); + index_2 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" ); + } + + lu_table_template(SIG2SRAM_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" ); + index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + + type (D_15_0) { + base_type : array; + data_type : bit; + bit_width : 16; + bit_from : 15; + bit_to : 0; + downto : true; + } + + type (A_11_0) { + base_type : array; + data_type : bit; + bit_width : 12; + bit_from : 11; + bit_to : 0; + downto : true; + } + +cell(RM_IHPSG13_1P_4096x16_c3_bm_bist) { +pg_pin (VDD) { + pg_type : primary_power; + voltage_name : VDD; +} +pg_pin (VDDARRAY) { + pg_type : primary_power; + voltage_name : VDDARRAY; +} +pg_pin (VSS) { + pg_type : primary_ground; + voltage_name : VSS; +} + +memory() { + type : ram; + address_width : 12; + word_width : 16; +} + +interface_timing : false; +bus_naming_style : "%s[%d]" ; +area : 257608.512 ; + + pin(A_DLY) { + direction : input ; + capacitance : 0.00421562 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_ADDR) { + bus_type : A_11_0; + direction : input ; + capacitance : 0.00691085 ; + pin(A_ADDR[0]) { + capacitance : 0.00562034 ; + } + pin(A_ADDR[1]) { + capacitance : 0.00462655 ; + } + pin(A_ADDR[2]) { + capacitance : 0.00594295 ; + } + pin(A_ADDR[3]) { + capacitance : 0.00723434 ; + } + pin(A_ADDR[4]) { + capacitance : 0.00481603 ; + } + pin(A_ADDR[5]) { + capacitance : 0.00868123 ; + } + pin(A_ADDR[6]) { + capacitance : 0.010187 ; + } + pin(A_ADDR[7]) { + capacitance : 0.00734489 ; + } + pin(A_ADDR[8]) { + capacitance : 0.00904175 ; + } + pin(A_ADDR[9]) { + capacitance : 0.0074973 ; + } + pin(A_ADDR[10]) { + capacitance : 0.00825659 ; + } + max_transition : "0.38" ; + pin(A_ADDR[11:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0094); + } + fall_power("scalar"){ + values (0.0008); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0200); + } + fall_power("scalar"){ + values (0.0016); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2371,-0.2215,-0.2098,-0.1824,-0.1434,-0.0691,0.0676",\ +"-0.2449,-0.2332,-0.2176,-0.1902,-0.1551,-0.0770,0.0559",\ +"-0.2605,-0.2488,-0.2332,-0.2059,-0.1707,-0.0965,0.0441",\ +"-0.2879,-0.2723,-0.2605,-0.2332,-0.1941,-0.1199,0.0168",\ +"-0.3230,-0.3113,-0.2996,-0.2723,-0.2332,-0.1590,-0.0184",\ +"-0.4012,-0.3895,-0.3738,-0.3465,-0.3074,-0.2332,-0.0965",\ +"-0.5379,-0.5262,-0.5105,-0.4832,-0.4480,-0.3699,-0.2332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1785,-0.1707,-0.1551,-0.1277,-0.0887,-0.0184,0.1145",\ +"-0.1902,-0.1785,-0.1629,-0.1355,-0.1004,-0.0262,0.1027",\ +"-0.2059,-0.1941,-0.1785,-0.1512,-0.1160,-0.0418,0.0871",\ +"-0.2293,-0.2176,-0.2059,-0.1785,-0.1434,-0.0691,0.0598",\ +"-0.2684,-0.2566,-0.2449,-0.2176,-0.1824,-0.1082,0.0207",\ +"-0.3465,-0.3348,-0.3191,-0.2918,-0.2566,-0.1824,-0.0535",\ +"-0.4832,-0.4715,-0.4559,-0.4324,-0.3934,-0.3191,-0.1902"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3410,0.3293,0.3137,0.2863,0.2473,0.1730,0.0324",\ +"0.3488,0.3371,0.3215,0.2941,0.2590,0.1809,0.0480",\ +"0.3684,0.3527,0.3371,0.3098,0.2746,0.1965,0.0598",\ +"0.3918,0.3762,0.3645,0.3371,0.2980,0.2238,0.0871",\ +"0.4309,0.4152,0.4035,0.3762,0.3371,0.2629,0.1223",\ +"0.5051,0.4934,0.4777,0.4504,0.4113,0.3371,0.1965",\ +"0.6418,0.6262,0.6145,0.5871,0.5520,0.4738,0.3332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2824,0.2707,0.2551,0.2277,0.1926,0.1184,-0.0105",\ +"0.2902,0.2785,0.2668,0.2395,0.2043,0.1301,0.0012",\ +"0.3059,0.2941,0.2824,0.2551,0.2199,0.1457,0.0168",\ +"0.3332,0.3215,0.3059,0.2785,0.2434,0.1691,0.0402",\ +"0.3723,0.3605,0.3449,0.3176,0.2824,0.2121,0.0793",\ +"0.4465,0.4348,0.4230,0.3918,0.3566,0.2824,0.1535",\ +"0.5832,0.5715,0.5598,0.5324,0.4934,0.4191,0.2902"); + } + } +} +pin(A_WEN) { + direction : input ; + capacitance : 0.00341384 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0068); + } + fall_power("scalar"){ + values (0.0168); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0045); + } + fall_power("scalar"){ + values (0.0208); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1887,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3527",\ +"-0.0262,-0.0145,0.0012,0.0246,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1418"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2160,0.2316,0.2590,0.2941,0.3684,0.5012",\ +"0.1926,0.2043,0.2199,0.2473,0.2824,0.3566,0.4895",\ +"0.1770,0.1887,0.2043,0.2316,0.2668,0.3410,0.4777",\ +"0.1535,0.1652,0.1770,0.2043,0.2395,0.3137,0.4504",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2746,0.4113",\ +"0.0402,0.0520,0.0676,0.0910,0.1262,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0730,-0.0457,-0.0066,0.0637,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1496,0.1223,0.0793,0.0090,-0.1316",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0168,-0.1199",\ +"0.2004,0.1887,0.1770,0.1496,0.1066,0.0363,-0.1043",\ +"0.2277,0.2160,0.2004,0.1730,0.1340,0.0598,-0.0809",\ +"0.2668,0.2551,0.2395,0.2121,0.1730,0.0988,-0.0418",\ +"0.3410,0.3293,0.3137,0.2863,0.2434,0.1730,0.0324",\ +"0.4816,0.4699,0.4543,0.4230,0.3801,0.3098,0.1730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1066,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1457,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1613,0.1340,0.0988,0.0246,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2512,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0457",\ +"0.3254,0.3176,0.3020,0.2746,0.2355,0.1652,0.0324",\ +"0.4660,0.4543,0.4387,0.4113,0.3723,0.3020,0.1691"); + } + } + } +pin(A_REN) { + direction : input ; + capacitance : 0.00390661 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0070); + } + fall_power("scalar"){ + values (0.0134); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0242); + } + fall_power("scalar"){ + values (0.0209); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.0027,0.0090,0.0246,0.0520,0.0910,0.1613,0.3020",\ +"-0.0105,0.0012,0.0129,0.0363,0.0793,0.1535,0.2902",\ +"-0.0262,-0.0145,-0.0027,0.0246,0.0637,0.1379,0.2785",\ +"-0.0535,-0.0418,-0.0262,0.0012,0.0363,0.1105,0.2512",\ +"-0.0926,-0.0809,-0.0652,-0.0418,-0.0027,0.0715,0.2121",\ +"-0.1668,-0.1551,-0.1395,-0.1082,-0.0770,-0.0027,0.1379",\ +"-0.3035,-0.2918,-0.2762,-0.2488,-0.2137,-0.1434,-0.0027"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.0832,0.0949,0.1105,0.1379,0.1730,0.2473,0.3801",\ +"0.0754,0.0832,0.0988,0.1223,0.1613,0.2355,0.3684",\ +"0.0598,0.0676,0.0832,0.1066,0.1457,0.2121,0.3527",\ +"0.0324,0.0441,0.0598,0.0871,0.1223,0.1926,0.3293",\ +"-0.0066,0.0051,0.0168,0.0480,0.0832,0.1535,0.2902",\ +"-0.0809,-0.0691,-0.0574,-0.0301,0.0090,0.0832,0.2121",\ +"-0.2176,-0.2059,-0.1941,-0.1668,-0.1277,-0.0574,0.0793"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1160",\ +"0.1965,0.1848,0.1730,0.1457,0.1027,0.0324,-0.1082",\ +"0.2160,0.2004,0.1887,0.1613,0.1184,0.0480,-0.0926",\ +"0.2395,0.2277,0.2121,0.1848,0.1457,0.0715,-0.0652",\ +"0.2785,0.2668,0.2512,0.2238,0.1848,0.1105,-0.0262",\ +"0.3527,0.3410,0.3254,0.2980,0.2551,0.1848,0.0480",\ +"0.4934,0.4816,0.4660,0.4387,0.3957,0.3254,0.1887"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1730,0.1613,0.1496,0.1184,0.0793,0.0129,-0.1238",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0207,-0.1121",\ +"0.2004,0.1887,0.1730,0.1457,0.1066,0.0363,-0.1004",\ +"0.2238,0.2121,0.2004,0.1691,0.1340,0.0598,-0.0730",\ +"0.2629,0.2512,0.2395,0.2121,0.1691,0.0988,-0.0340",\ +"0.3371,0.3254,0.3137,0.2863,0.2434,0.1730,0.0402",\ +"0.4777,0.4660,0.4504,0.4230,0.3840,0.3137,0.1809"); + } + } + } +pin(A_MEN) { + direction : input ; + capacitance : 0.00326046 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.1478); + } + fall_power("scalar"){ + values (0.0124); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1926,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1418,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3488",\ +"-0.0262,-0.0145,0.0012,0.0285,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1379"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2199,0.2316,0.2590,0.2980,0.3723,0.5051",\ +"0.1965,0.2082,0.2199,0.2473,0.2863,0.3605,0.4934",\ +"0.1809,0.1926,0.2043,0.2316,0.2707,0.3449,0.4777",\ +"0.1574,0.1691,0.1809,0.2082,0.2434,0.3176,0.4543",\ +"0.1145,0.1262,0.1418,0.1691,0.2043,0.2785,0.4113",\ +"0.0441,0.0559,0.0676,0.0949,0.1301,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0691,-0.0418,-0.0066,0.0676,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1535,0.1262,0.0832,0.0129,-0.1277",\ +"0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1199",\ +"0.2043,0.1926,0.1770,0.1496,0.1105,0.0363,-0.1043",\ +"0.2277,0.2160,0.2043,0.1770,0.1379,0.0598,-0.0770",\ +"0.2668,0.2551,0.2434,0.2160,0.1730,0.0988,-0.0379",\ +"0.3449,0.3332,0.3176,0.2902,0.2473,0.1730,0.0363",\ +"0.4816,0.4699,0.4543,0.4270,0.3840,0.3098,0.1770"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1105,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1496,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1652,0.1340,0.0988,0.0285,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2551,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0418",\ +"0.3293,0.3176,0.3020,0.2746,0.2395,0.1652,0.0324",\ +"0.4660,0.4543,0.4426,0.4113,0.3762,0.3020,0.1691"); + } + } + } +bus(A_BM) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00318267 ; + max_transition : "0.38" ; + pin(A_BM[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0726); + } + fall_power("scalar"){ + values (0.0881); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0856); + } + fall_power("scalar"){ + values (0.0958); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2152,-0.2044,-0.1888,-0.1634,-0.1224,-0.0492,0.0856",\ +"-0.2191,-0.2083,-0.1927,-0.1673,-0.1263,-0.0531,0.0817",\ +"-0.2230,-0.2122,-0.1966,-0.1712,-0.1302,-0.0570,0.0778",\ +"-0.2261,-0.2154,-0.1998,-0.1744,-0.1333,-0.0601,0.0747",\ +"-0.2386,-0.2278,-0.2122,-0.1868,-0.1458,-0.0725,0.0622",\ +"-0.2560,-0.2453,-0.2297,-0.2043,-0.1633,-0.0900,0.0447",\ +"-0.2837,-0.2729,-0.2573,-0.2319,-0.1909,-0.1177,0.0171"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1917,-0.1800,-0.1673,-0.1400,-0.1029,-0.0296,0.0983",\ +"-0.1956,-0.1839,-0.1712,-0.1439,-0.1068,-0.0335,0.0944",\ +"-0.1995,-0.1878,-0.1751,-0.1478,-0.1107,-0.0374,0.0905",\ +"-0.2027,-0.1910,-0.1783,-0.1509,-0.1138,-0.0406,0.0873",\ +"-0.2151,-0.2034,-0.1907,-0.1634,-0.1263,-0.0530,0.0749",\ +"-0.2326,-0.2209,-0.2082,-0.1808,-0.1437,-0.0705,0.0574",\ +"-0.2602,-0.2485,-0.2358,-0.2085,-0.1714,-0.0981,0.0298"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3203,0.3105,0.2949,0.2685,0.2314,0.1572,0.0224",\ +"0.3242,0.3144,0.2988,0.2724,0.2353,0.1611,0.0263",\ +"0.3281,0.3183,0.3027,0.2763,0.2392,0.1650,0.0302",\ +"0.3312,0.3215,0.3058,0.2795,0.2424,0.1681,0.0334",\ +"0.3437,0.3339,0.3183,0.2919,0.2548,0.1806,0.0458",\ +"0.3611,0.3514,0.3357,0.3094,0.2723,0.1980,0.0633",\ +"0.3888,0.3790,0.3634,0.3370,0.2999,0.2257,0.0909"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2920,0.2812,0.2676,0.2402,0.2041,0.1318,0.0019",\ +"0.2959,0.2851,0.2715,0.2441,0.2080,0.1357,0.0058",\ +"0.2998,0.2890,0.2754,0.2480,0.2119,0.1396,0.0097",\ +"0.3029,0.2922,0.2785,0.2512,0.2150,0.1428,0.0129",\ +"0.3154,0.3046,0.2909,0.2636,0.2275,0.1552,0.0253",\ +"0.3328,0.3221,0.3084,0.2811,0.2449,0.1727,0.0428",\ +"0.3605,0.3497,0.3361,0.3087,0.2726,0.2003,0.0704"); + } + } +} + pin(A_CLK) { + direction : input; + capacitance : 0.00389386; + max_transition : "0.38"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.004,0.38"); + values("0.12,0.12"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (0.2437); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (92.9376); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (89.8350); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (72.7475); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (0.5007); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (1.0180); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_DIN) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00332733 ; + memory_write() { + address : A_ADDR ; + clocked_on : A_CLK; + } + + max_transition : "0.38" ; + pin(A_DIN[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0726); + } + fall_power("scalar"){ + values (0.0881); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0856); + } + fall_power("scalar"){ + values (0.0958); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2152,-0.2044,-0.1888,-0.1634,-0.1224,-0.0492,0.0856",\ +"-0.2191,-0.2083,-0.1927,-0.1673,-0.1263,-0.0531,0.0817",\ +"-0.2230,-0.2122,-0.1966,-0.1712,-0.1302,-0.0570,0.0778",\ +"-0.2261,-0.2154,-0.1998,-0.1744,-0.1333,-0.0601,0.0747",\ +"-0.2386,-0.2278,-0.2122,-0.1868,-0.1458,-0.0725,0.0622",\ +"-0.2560,-0.2453,-0.2297,-0.2043,-0.1633,-0.0900,0.0447",\ +"-0.2837,-0.2729,-0.2573,-0.2319,-0.1909,-0.1177,0.0171"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1917,-0.1800,-0.1673,-0.1400,-0.1029,-0.0296,0.0983",\ +"-0.1956,-0.1839,-0.1712,-0.1439,-0.1068,-0.0335,0.0944",\ +"-0.1995,-0.1878,-0.1751,-0.1478,-0.1107,-0.0374,0.0905",\ +"-0.2027,-0.1910,-0.1783,-0.1509,-0.1138,-0.0406,0.0873",\ +"-0.2151,-0.2034,-0.1907,-0.1634,-0.1263,-0.0530,0.0749",\ +"-0.2326,-0.2209,-0.2082,-0.1808,-0.1437,-0.0705,0.0574",\ +"-0.2602,-0.2485,-0.2358,-0.2085,-0.1714,-0.0981,0.0298"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3203,0.3105,0.2949,0.2685,0.2314,0.1572,0.0224",\ +"0.3242,0.3144,0.2988,0.2724,0.2353,0.1611,0.0263",\ +"0.3281,0.3183,0.3027,0.2763,0.2392,0.1650,0.0302",\ +"0.3312,0.3215,0.3058,0.2795,0.2424,0.1681,0.0334",\ +"0.3437,0.3339,0.3183,0.2919,0.2548,0.1806,0.0458",\ +"0.3611,0.3514,0.3357,0.3094,0.2723,0.1980,0.0633",\ +"0.3888,0.3790,0.3634,0.3370,0.2999,0.2257,0.0909"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2920,0.2812,0.2676,0.2402,0.2041,0.1318,0.0019",\ +"0.2959,0.2851,0.2715,0.2441,0.2080,0.1357,0.0058",\ +"0.2998,0.2890,0.2754,0.2480,0.2119,0.1396,0.0097",\ +"0.3029,0.2922,0.2785,0.2512,0.2150,0.1428,0.0129",\ +"0.3154,0.3046,0.2909,0.2636,0.2275,0.1552,0.0253",\ +"0.3328,0.3221,0.3084,0.2811,0.2449,0.1727,0.0428",\ +"0.3605,0.3497,0.3361,0.3087,0.2726,0.2003,0.0704"); + } + } + } + + pin(A_BIST_EN) { + direction : input ; + capacitance : 0.00421562 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_BIST_ADDR) { + bus_type : A_11_0; + direction : input ; + capacitance : 0.00691085 ; + pin(A_BIST_ADDR[0]) { + capacitance : 0.00562034 ; + } + pin(A_BIST_ADDR[1]) { + capacitance : 0.00462655 ; + } + pin(A_BIST_ADDR[2]) { + capacitance : 0.00594295 ; + } + pin(A_BIST_ADDR[3]) { + capacitance : 0.00723434 ; + } + pin(A_BIST_ADDR[4]) { + capacitance : 0.00481603 ; + } + pin(A_BIST_ADDR[5]) { + capacitance : 0.00868123 ; + } + pin(A_BIST_ADDR[6]) { + capacitance : 0.010187 ; + } + pin(A_BIST_ADDR[7]) { + capacitance : 0.00734489 ; + } + pin(A_BIST_ADDR[8]) { + capacitance : 0.00904175 ; + } + pin(A_BIST_ADDR[9]) { + capacitance : 0.0074973 ; + } + pin(A_BIST_ADDR[10]) { + capacitance : 0.00825659 ; + } + max_transition : "0.38" ; + pin(A_BIST_ADDR[11:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0094); + } + fall_power("scalar"){ + values (0.0008); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0200); + } + fall_power("scalar"){ + values (0.0016); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2371,-0.2215,-0.2098,-0.1824,-0.1434,-0.0691,0.0676",\ +"-0.2449,-0.2332,-0.2176,-0.1902,-0.1551,-0.0770,0.0559",\ +"-0.2605,-0.2488,-0.2332,-0.2059,-0.1707,-0.0965,0.0441",\ +"-0.2879,-0.2723,-0.2605,-0.2332,-0.1941,-0.1199,0.0168",\ +"-0.3230,-0.3113,-0.2996,-0.2723,-0.2332,-0.1590,-0.0184",\ +"-0.4012,-0.3895,-0.3738,-0.3465,-0.3074,-0.2332,-0.0965",\ +"-0.5379,-0.5262,-0.5105,-0.4832,-0.4480,-0.3699,-0.2332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1785,-0.1707,-0.1551,-0.1277,-0.0887,-0.0184,0.1145",\ +"-0.1902,-0.1785,-0.1629,-0.1355,-0.1004,-0.0262,0.1027",\ +"-0.2059,-0.1941,-0.1785,-0.1512,-0.1160,-0.0418,0.0871",\ +"-0.2293,-0.2176,-0.2059,-0.1785,-0.1434,-0.0691,0.0598",\ +"-0.2684,-0.2566,-0.2449,-0.2176,-0.1824,-0.1082,0.0207",\ +"-0.3465,-0.3348,-0.3191,-0.2918,-0.2566,-0.1824,-0.0535",\ +"-0.4832,-0.4715,-0.4559,-0.4324,-0.3934,-0.3191,-0.1902"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3410,0.3293,0.3137,0.2863,0.2473,0.1730,0.0324",\ +"0.3488,0.3371,0.3215,0.2941,0.2590,0.1809,0.0480",\ +"0.3684,0.3527,0.3371,0.3098,0.2746,0.1965,0.0598",\ +"0.3918,0.3762,0.3645,0.3371,0.2980,0.2238,0.0871",\ +"0.4309,0.4152,0.4035,0.3762,0.3371,0.2629,0.1223",\ +"0.5051,0.4934,0.4777,0.4504,0.4113,0.3371,0.1965",\ +"0.6418,0.6262,0.6145,0.5871,0.5520,0.4738,0.3332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2824,0.2707,0.2551,0.2277,0.1926,0.1184,-0.0105",\ +"0.2902,0.2785,0.2668,0.2395,0.2043,0.1301,0.0012",\ +"0.3059,0.2941,0.2824,0.2551,0.2199,0.1457,0.0168",\ +"0.3332,0.3215,0.3059,0.2785,0.2434,0.1691,0.0402",\ +"0.3723,0.3605,0.3449,0.3176,0.2824,0.2121,0.0793",\ +"0.4465,0.4348,0.4230,0.3918,0.3566,0.2824,0.1535",\ +"0.5832,0.5715,0.5598,0.5324,0.4934,0.4191,0.2902"); + } + } +} +pin(A_BIST_WEN) { + direction : input ; + capacitance : 0.00341384 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0068); + } + fall_power("scalar"){ + values (0.0168); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0045); + } + fall_power("scalar"){ + values (0.0208); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1887,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3527",\ +"-0.0262,-0.0145,0.0012,0.0246,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1418"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2160,0.2316,0.2590,0.2941,0.3684,0.5012",\ +"0.1926,0.2043,0.2199,0.2473,0.2824,0.3566,0.4895",\ +"0.1770,0.1887,0.2043,0.2316,0.2668,0.3410,0.4777",\ +"0.1535,0.1652,0.1770,0.2043,0.2395,0.3137,0.4504",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2746,0.4113",\ +"0.0402,0.0520,0.0676,0.0910,0.1262,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0730,-0.0457,-0.0066,0.0637,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1496,0.1223,0.0793,0.0090,-0.1316",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0168,-0.1199",\ +"0.2004,0.1887,0.1770,0.1496,0.1066,0.0363,-0.1043",\ +"0.2277,0.2160,0.2004,0.1730,0.1340,0.0598,-0.0809",\ +"0.2668,0.2551,0.2395,0.2121,0.1730,0.0988,-0.0418",\ +"0.3410,0.3293,0.3137,0.2863,0.2434,0.1730,0.0324",\ +"0.4816,0.4699,0.4543,0.4230,0.3801,0.3098,0.1730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1066,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1457,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1613,0.1340,0.0988,0.0246,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2512,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0457",\ +"0.3254,0.3176,0.3020,0.2746,0.2355,0.1652,0.0324",\ +"0.4660,0.4543,0.4387,0.4113,0.3723,0.3020,0.1691"); + } + } + } +pin(A_BIST_REN) { + direction : input ; + capacitance : 0.00390661 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0070); + } + fall_power("scalar"){ + values (0.0134); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0242); + } + fall_power("scalar"){ + values (0.0209); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.0027,0.0090,0.0246,0.0520,0.0910,0.1613,0.3020",\ +"-0.0105,0.0012,0.0129,0.0363,0.0793,0.1535,0.2902",\ +"-0.0262,-0.0145,-0.0027,0.0246,0.0637,0.1379,0.2785",\ +"-0.0535,-0.0418,-0.0262,0.0012,0.0363,0.1105,0.2512",\ +"-0.0926,-0.0809,-0.0652,-0.0418,-0.0027,0.0715,0.2121",\ +"-0.1668,-0.1551,-0.1395,-0.1082,-0.0770,-0.0027,0.1379",\ +"-0.3035,-0.2918,-0.2762,-0.2488,-0.2137,-0.1434,-0.0027"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.0832,0.0949,0.1105,0.1379,0.1730,0.2473,0.3801",\ +"0.0754,0.0832,0.0988,0.1223,0.1613,0.2355,0.3684",\ +"0.0598,0.0676,0.0832,0.1066,0.1457,0.2121,0.3527",\ +"0.0324,0.0441,0.0598,0.0871,0.1223,0.1926,0.3293",\ +"-0.0066,0.0051,0.0168,0.0480,0.0832,0.1535,0.2902",\ +"-0.0809,-0.0691,-0.0574,-0.0301,0.0090,0.0832,0.2121",\ +"-0.2176,-0.2059,-0.1941,-0.1668,-0.1277,-0.0574,0.0793"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1160",\ +"0.1965,0.1848,0.1730,0.1457,0.1027,0.0324,-0.1082",\ +"0.2160,0.2004,0.1887,0.1613,0.1184,0.0480,-0.0926",\ +"0.2395,0.2277,0.2121,0.1848,0.1457,0.0715,-0.0652",\ +"0.2785,0.2668,0.2512,0.2238,0.1848,0.1105,-0.0262",\ +"0.3527,0.3410,0.3254,0.2980,0.2551,0.1848,0.0480",\ +"0.4934,0.4816,0.4660,0.4387,0.3957,0.3254,0.1887"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1730,0.1613,0.1496,0.1184,0.0793,0.0129,-0.1238",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0207,-0.1121",\ +"0.2004,0.1887,0.1730,0.1457,0.1066,0.0363,-0.1004",\ +"0.2238,0.2121,0.2004,0.1691,0.1340,0.0598,-0.0730",\ +"0.2629,0.2512,0.2395,0.2121,0.1691,0.0988,-0.0340",\ +"0.3371,0.3254,0.3137,0.2863,0.2434,0.1730,0.0402",\ +"0.4777,0.4660,0.4504,0.4230,0.3840,0.3137,0.1809"); + } + } + } +pin(A_BIST_MEN) { + direction : input ; + capacitance : 0.00326046 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.1478); + } + fall_power("scalar"){ + values (0.0124); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1926,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1418,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3488",\ +"-0.0262,-0.0145,0.0012,0.0285,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1379"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2199,0.2316,0.2590,0.2980,0.3723,0.5051",\ +"0.1965,0.2082,0.2199,0.2473,0.2863,0.3605,0.4934",\ +"0.1809,0.1926,0.2043,0.2316,0.2707,0.3449,0.4777",\ +"0.1574,0.1691,0.1809,0.2082,0.2434,0.3176,0.4543",\ +"0.1145,0.1262,0.1418,0.1691,0.2043,0.2785,0.4113",\ +"0.0441,0.0559,0.0676,0.0949,0.1301,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0691,-0.0418,-0.0066,0.0676,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1535,0.1262,0.0832,0.0129,-0.1277",\ +"0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1199",\ +"0.2043,0.1926,0.1770,0.1496,0.1105,0.0363,-0.1043",\ +"0.2277,0.2160,0.2043,0.1770,0.1379,0.0598,-0.0770",\ +"0.2668,0.2551,0.2434,0.2160,0.1730,0.0988,-0.0379",\ +"0.3449,0.3332,0.3176,0.2902,0.2473,0.1730,0.0363",\ +"0.4816,0.4699,0.4543,0.4270,0.3840,0.3098,0.1770"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1105,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1496,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1652,0.1340,0.0988,0.0285,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2551,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0418",\ +"0.3293,0.3176,0.3020,0.2746,0.2395,0.1652,0.0324",\ +"0.4660,0.4543,0.4426,0.4113,0.3762,0.3020,0.1691"); + } + } + } +bus(A_BIST_BM) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00252172 ; + max_transition : "0.38" ; + pin(A_BIST_BM[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0726); + } + fall_power("scalar"){ + values (0.0881); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0856); + } + fall_power("scalar"){ + values (0.0958); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2152,-0.2044,-0.1888,-0.1634,-0.1224,-0.0492,0.0856",\ +"-0.2191,-0.2083,-0.1927,-0.1673,-0.1263,-0.0531,0.0817",\ +"-0.2230,-0.2122,-0.1966,-0.1712,-0.1302,-0.0570,0.0778",\ +"-0.2261,-0.2154,-0.1998,-0.1744,-0.1333,-0.0601,0.0747",\ +"-0.2386,-0.2278,-0.2122,-0.1868,-0.1458,-0.0725,0.0622",\ +"-0.2560,-0.2453,-0.2297,-0.2043,-0.1633,-0.0900,0.0447",\ +"-0.2837,-0.2729,-0.2573,-0.2319,-0.1909,-0.1177,0.0171"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1917,-0.1800,-0.1673,-0.1400,-0.1029,-0.0296,0.0983",\ +"-0.1956,-0.1839,-0.1712,-0.1439,-0.1068,-0.0335,0.0944",\ +"-0.1995,-0.1878,-0.1751,-0.1478,-0.1107,-0.0374,0.0905",\ +"-0.2027,-0.1910,-0.1783,-0.1509,-0.1138,-0.0406,0.0873",\ +"-0.2151,-0.2034,-0.1907,-0.1634,-0.1263,-0.0530,0.0749",\ +"-0.2326,-0.2209,-0.2082,-0.1808,-0.1437,-0.0705,0.0574",\ +"-0.2602,-0.2485,-0.2358,-0.2085,-0.1714,-0.0981,0.0298"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3203,0.3105,0.2949,0.2685,0.2314,0.1572,0.0224",\ +"0.3242,0.3144,0.2988,0.2724,0.2353,0.1611,0.0263",\ +"0.3281,0.3183,0.3027,0.2763,0.2392,0.1650,0.0302",\ +"0.3312,0.3215,0.3058,0.2795,0.2424,0.1681,0.0334",\ +"0.3437,0.3339,0.3183,0.2919,0.2548,0.1806,0.0458",\ +"0.3611,0.3514,0.3357,0.3094,0.2723,0.1980,0.0633",\ +"0.3888,0.3790,0.3634,0.3370,0.2999,0.2257,0.0909"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2920,0.2812,0.2676,0.2402,0.2041,0.1318,0.0019",\ +"0.2959,0.2851,0.2715,0.2441,0.2080,0.1357,0.0058",\ +"0.2998,0.2890,0.2754,0.2480,0.2119,0.1396,0.0097",\ +"0.3029,0.2922,0.2785,0.2512,0.2150,0.1428,0.0129",\ +"0.3154,0.3046,0.2909,0.2636,0.2275,0.1552,0.0253",\ +"0.3328,0.3221,0.3084,0.2811,0.2449,0.1727,0.0428",\ +"0.3605,0.3497,0.3361,0.3087,0.2726,0.2003,0.0704"); + } + } +} + pin(A_BIST_CLK) { + direction : input; + capacitance : 0.00389386; + max_transition : "0.38"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.004,0.38"); + values("0.12,0.12"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0.2437); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (92.9376); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (89.8350); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (72.7475); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.5007); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (1.0180); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_BIST_DIN) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00252023 ; + memory_write() { + address : A_BIST_ADDR ; + clocked_on : A_BIST_CLK; + } + + max_transition : "0.38" ; + pin(A_BIST_DIN[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0726); + } + fall_power("scalar"){ + values (0.0881); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0856); + } + fall_power("scalar"){ + values (0.0958); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2152,-0.2044,-0.1888,-0.1634,-0.1224,-0.0492,0.0856",\ +"-0.2191,-0.2083,-0.1927,-0.1673,-0.1263,-0.0531,0.0817",\ +"-0.2230,-0.2122,-0.1966,-0.1712,-0.1302,-0.0570,0.0778",\ +"-0.2261,-0.2154,-0.1998,-0.1744,-0.1333,-0.0601,0.0747",\ +"-0.2386,-0.2278,-0.2122,-0.1868,-0.1458,-0.0725,0.0622",\ +"-0.2560,-0.2453,-0.2297,-0.2043,-0.1633,-0.0900,0.0447",\ +"-0.2837,-0.2729,-0.2573,-0.2319,-0.1909,-0.1177,0.0171"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1917,-0.1800,-0.1673,-0.1400,-0.1029,-0.0296,0.0983",\ +"-0.1956,-0.1839,-0.1712,-0.1439,-0.1068,-0.0335,0.0944",\ +"-0.1995,-0.1878,-0.1751,-0.1478,-0.1107,-0.0374,0.0905",\ +"-0.2027,-0.1910,-0.1783,-0.1509,-0.1138,-0.0406,0.0873",\ +"-0.2151,-0.2034,-0.1907,-0.1634,-0.1263,-0.0530,0.0749",\ +"-0.2326,-0.2209,-0.2082,-0.1808,-0.1437,-0.0705,0.0574",\ +"-0.2602,-0.2485,-0.2358,-0.2085,-0.1714,-0.0981,0.0298"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3203,0.3105,0.2949,0.2685,0.2314,0.1572,0.0224",\ +"0.3242,0.3144,0.2988,0.2724,0.2353,0.1611,0.0263",\ +"0.3281,0.3183,0.3027,0.2763,0.2392,0.1650,0.0302",\ +"0.3312,0.3215,0.3058,0.2795,0.2424,0.1681,0.0334",\ +"0.3437,0.3339,0.3183,0.2919,0.2548,0.1806,0.0458",\ +"0.3611,0.3514,0.3357,0.3094,0.2723,0.1980,0.0633",\ +"0.3888,0.3790,0.3634,0.3370,0.2999,0.2257,0.0909"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2920,0.2812,0.2676,0.2402,0.2041,0.1318,0.0019",\ +"0.2959,0.2851,0.2715,0.2441,0.2080,0.1357,0.0058",\ +"0.2998,0.2890,0.2754,0.2480,0.2119,0.1396,0.0097",\ +"0.3029,0.2922,0.2785,0.2512,0.2150,0.1428,0.0129",\ +"0.3154,0.3046,0.2909,0.2636,0.2275,0.1552,0.0253",\ +"0.3328,0.3221,0.3084,0.2811,0.2449,0.1727,0.0428",\ +"0.3605,0.3497,0.3361,0.3087,0.2726,0.2003,0.0704"); + } + } + } + +bus(A_DOUT) { + + bus_type : D_15_0; + direction : output ; + capacitance : 0 ; + max_capacitance : "6.4e-14" ; + memory_read() { + address : A_ADDR ; + } + pin(A_DOUT[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "A_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("3.2854,3.2864,3.2912,3.2967,3.3176,3.3411",\ +"3.2918,3.2928,3.2976,3.3032,3.3241,3.3476",\ +"3.2958,3.2968,3.3016,3.3071,3.3280,3.3515",\ +"3.2991,3.3001,3.3049,3.3104,3.3313,3.3548",\ +"3.3077,3.3087,3.3136,3.3191,3.3400,3.3635",\ +"3.3298,3.3309,3.3357,3.3412,3.3621,3.3856",\ +"3.3553,3.3563,3.3612,3.3667,3.3876,3.4111"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("3.2511,3.2520,3.2560,3.2605,3.2776,3.2944",\ +"3.2575,3.2584,3.2624,3.2670,3.2841,3.3008",\ +"3.2615,3.2623,3.2664,3.2709,3.2880,3.3047",\ +"3.2648,3.2657,3.2697,3.2742,3.2913,3.3081",\ +"3.2734,3.2743,3.2783,3.2829,3.3000,3.3167",\ +"3.2956,3.2964,3.3005,3.3050,3.3221,3.3388",\ +"3.3210,3.3219,3.3259,3.3305,3.3476,3.3643"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0206,0.0210,0.0265,0.0323,0.0606,0.0955"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0170,0.0177,0.0222,0.0270,0.0451,0.0644"); + } + } +} +cell_leakage_power : 1878.3764; +} +} diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_4096x16_c3_bm_bist_slow_1p08V_125C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_4096x16_c3_bm_bist_slow_1p08V_125C.lib new file mode 100644 index 0000000000..acf9678138 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_4096x16_c3_bm_bist_slow_1p08V_125C.lib @@ -0,0 +1,1537 @@ +/* ------------------------------------------------------*/ +/**/ +/* Copyright 2024 IHP PDK Authors*/ +/**/ +/* Licensed under the Apache License, Version 2.0 (the "License");*/ +/* you may not use this file except in compliance with the License.*/ +/* You may obtain a copy of the License at*/ +/* */ +/* https://www.apache.org/licenses/LICENSE-2.0*/ +/* */ +/* Unless required by applicable law or agreed to in writing, software*/ +/* distributed under the License is distributed on an "AS IS" BASIS,*/ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/ +/* See the License for the specific language governing permissions and*/ +/* limitations under the License.*/ +/* */ +/* Generated on Fri Jul 12 17:37:31 2024 */ +/* */ +/* ------------------------------------------------------ */ +library(RM_IHPSG13_1P_4096x16_c3_bm_bist_slow_1p08V_125C) { + technology (cmos) ; + delay_model : table_lookup ; + define ("add_pg_pin_to_lib", "library", "boolean"); + add_pg_pin_to_lib : true; + voltage_map ( VDD, 1.08); + voltage_map ( VDDARRAY, 1.08); + voltage_map ( VSS, 0.000000 ); + + date : "Fri Jul 12 17:37:29 2024" ; + comment : "IHP Microelectronics GmbH, 2024" ; + revision : 1.0.0 ; + simulation : true ; + nom_process : 1 ; + nom_temperature : 125 ; + nom_voltage : 1.08 ; + + operating_conditions("slow_1p08V_125C"){ + process : 1 ; + temperature : 125 ; + voltage : 1.08 ; + tree_type : "balanced_tree" ; + } + + default_operating_conditions : slow_1p08V_125C ; + default_max_transition : 1.0 ; + default_fanout_load : 1.0 ; + default_inout_pin_cap : 0.0 ; + default_input_pin_cap : 0.0 ; + default_output_pin_cap : 0.0 ; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + + slew_lower_threshold_pct_rise : 30 ; + slew_upper_threshold_pct_rise : 70 ; + input_threshold_pct_fall : 50 ; + output_threshold_pct_fall : 50 ; + input_threshold_pct_rise : 50 ; + output_threshold_pct_rise : 50 ; + slew_lower_threshold_pct_fall : 30 ; + slew_upper_threshold_pct_fall : 70 ; + slew_derate_from_library : 0.5; + k_volt_cell_leakage_power : 0.0 ; + k_temp_cell_leakage_power : 0.0 ; + k_process_cell_leakage_power : 0.0 ; + k_volt_internal_power : 0.0 ; + k_temp_internal_power : 0.0 ; + k_process_internal_power : 0.0 ; + + capacitive_load_unit (1,pf) ; + voltage_unit : "1V" ; + current_unit : "1uA" ; + time_unit : "1ns" ; + leakage_power_unit : "1nW" ; + pulling_resistance_unit : "1kohm"; + /* + ------------------------------------------------------------------------------------------ + implicit units overview: + cell_area unit : "um" + internal_power unit : "1e-12 * J/toggle = 1 * uW/MHz" + (capacitive_load_unit * voltage_unit^2) per toggle event + ------------------------------------------------------------------------------------------ + */ + library_features(report_delay_calculation); + define_cell_area (pad_drivers,pad_driver_sites) ; + + lu_table_template(CLKTRAN_constraint_template) { + variable_1 : constrained_pin_transition; + index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" ); + } + lu_table_template(SRAM_load_template) { + variable_1 : total_output_net_capacitance; + index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + lu_table_template(SIG2SRAM_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" ); + index_2 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" ); + } + + lu_table_template(SIG2SRAM_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" ); + index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + + type (D_15_0) { + base_type : array; + data_type : bit; + bit_width : 16; + bit_from : 15; + bit_to : 0; + downto : true; + } + + type (A_11_0) { + base_type : array; + data_type : bit; + bit_width : 12; + bit_from : 11; + bit_to : 0; + downto : true; + } + +cell(RM_IHPSG13_1P_4096x16_c3_bm_bist) { +pg_pin (VDD) { + pg_type : primary_power; + voltage_name : VDD; +} +pg_pin (VDDARRAY) { + pg_type : primary_power; + voltage_name : VDDARRAY; +} +pg_pin (VSS) { + pg_type : primary_ground; + voltage_name : VSS; +} + +memory() { + type : ram; + address_width : 12; + word_width : 16; +} + +interface_timing : false; +bus_naming_style : "%s[%d]" ; +area : 257608.512 ; + + pin(A_DLY) { + direction : input ; + capacitance : 0.00387999 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_ADDR) { + bus_type : A_11_0; + direction : input ; + capacitance : 0.0077013 ; + pin(A_ADDR[0]) { + capacitance : 0.00625349 ; + } + pin(A_ADDR[1]) { + capacitance : 0.00507435 ; + } + pin(A_ADDR[2]) { + capacitance : 0.00656707 ; + } + pin(A_ADDR[3]) { + capacitance : 0.0083133 ; + } + pin(A_ADDR[4]) { + capacitance : 0.00507219 ; + } + pin(A_ADDR[5]) { + capacitance : 0.00964344 ; + } + pin(A_ADDR[6]) { + capacitance : 0.0119653 ; + } + pin(A_ADDR[7]) { + capacitance : 0.00827606 ; + } + pin(A_ADDR[8]) { + capacitance : 0.0110771 ; + } + pin(A_ADDR[9]) { + capacitance : 0.00811634 ; + } + pin(A_ADDR[10]) { + capacitance : 0.00916579 ; + } + max_transition : "0.5952" ; + pin(A_ADDR[11:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0276); + } + fall_power("scalar"){ + values (0.0166); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0210); + } + fall_power("scalar"){ + values (0.0037); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7371,-0.7176,-0.6863,-0.6434,-0.5652,-0.4168,-0.1980",\ +"-0.7566,-0.7371,-0.7059,-0.6629,-0.5848,-0.4363,-0.2137",\ +"-0.7879,-0.7645,-0.7332,-0.6902,-0.6121,-0.4637,-0.2449",\ +"-0.8309,-0.8074,-0.7762,-0.7332,-0.6551,-0.5066,-0.2879",\ +"-0.9051,-0.8895,-0.8543,-0.8113,-0.7332,-0.5887,-0.3660",\ +"-1.0418,-1.0262,-0.9949,-0.9480,-0.8699,-0.7293,-0.5027",\ +"-1.2684,-1.2449,-1.2176,-1.1707,-1.0965,-0.9480,-0.7293"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5926,-0.5730,-0.5418,-0.4988,-0.4246,-0.2879,-0.0730",\ +"-0.6121,-0.5926,-0.5613,-0.5223,-0.4441,-0.3074,-0.0887",\ +"-0.6395,-0.6199,-0.5926,-0.5496,-0.4715,-0.3348,-0.1160",\ +"-0.6863,-0.6668,-0.6355,-0.5965,-0.5184,-0.3777,-0.1590",\ +"-0.7605,-0.7410,-0.7137,-0.6746,-0.5926,-0.4559,-0.2410",\ +"-0.9012,-0.8816,-0.8504,-0.8113,-0.7332,-0.5926,-0.3895",\ +"-1.1238,-1.1043,-1.0769,-1.0379,-0.9559,-0.8191,-0.6004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8488,0.8293,0.7980,0.7551,0.6730,0.5285,0.3098",\ +"0.8684,0.8488,0.8176,0.7746,0.6926,0.5480,0.3254",\ +"0.8996,0.8801,0.8449,0.8020,0.7238,0.5754,0.3527",\ +"0.9426,0.9191,0.8918,0.8488,0.7668,0.6223,0.3996",\ +"1.0168,1.0012,0.9699,0.9230,0.8449,0.7004,0.4777",\ +"1.1574,1.1379,1.1105,1.0598,0.9816,0.8371,0.6184",\ +"1.3801,1.3605,1.3254,1.2980,1.2043,1.0637,0.8371"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6965,0.6770,0.6496,0.6066,0.5246,0.3918,0.1730",\ +"0.7160,0.6965,0.6652,0.6262,0.5441,0.4113,0.1965",\ +"0.7473,0.7277,0.6965,0.6535,0.5754,0.4426,0.2238",\ +"0.7863,0.7707,0.7395,0.7004,0.6223,0.4855,0.2629",\ +"0.8684,0.8449,0.8176,0.7785,0.7004,0.5637,0.3449",\ +"1.0051,0.9855,0.9855,0.9113,0.8332,0.7004,0.4895",\ +"1.2277,1.2082,1.1809,1.1379,1.0598,0.9230,0.7004"); + } + } +} +pin(A_WEN) { + direction : input ; + capacitance : 0.00313551 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0235); + } + fall_power("scalar"){ + values (0.0210); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0049); + } + fall_power("scalar"){ + values (0.0013); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3137,0.3332,0.3605,0.4035,0.4816,0.6223,0.8488",\ +"0.2980,0.3176,0.3410,0.3840,0.4660,0.6027,0.8293",\ +"0.2629,0.2824,0.3098,0.3527,0.4348,0.5754,0.7980",\ +"0.2199,0.2395,0.2668,0.3098,0.3918,0.5324,0.7590",\ +"0.1418,0.1613,0.1887,0.2316,0.3137,0.4348,0.6730",\ +"0.0012,0.0207,0.0520,0.0910,0.1730,0.3098,0.5285",\ +"-0.2215,-0.2020,-0.1746,-0.1277,-0.0496,0.0910,0.3098"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4504,0.4699,0.4973,0.5324,0.6027,0.7355,0.9699",\ +"0.4309,0.4504,0.4777,0.5129,0.5910,0.7160,0.9504",\ +"0.3996,0.4191,0.4465,0.4816,0.5520,0.6848,0.9191",\ +"0.3605,0.3762,0.4035,0.4387,0.5168,0.6418,0.8723",\ +"0.2785,0.2980,0.3215,0.3605,0.4348,0.5637,0.7980",\ +"0.1379,0.1574,0.1809,0.2199,0.2980,0.4309,0.6457",\ +"-0.0809,-0.0613,-0.0340,0.0051,0.0832,0.2160,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3723,0.3527,0.3215,0.2785,0.1965,0.0559,-0.1668",\ +"0.3918,0.3723,0.3449,0.2980,0.2160,0.0754,-0.1473",\ +"0.4152,0.3996,0.3684,0.3254,0.2434,0.1066,-0.1199",\ +"0.4621,0.4465,0.4152,0.3723,0.2863,0.1496,-0.0730",\ +"0.5324,0.5207,0.4895,0.4465,0.3645,0.2199,0.0051",\ +"0.6770,0.6535,0.6301,0.5832,0.5090,0.3605,0.1418",\ +"0.9035,0.8879,0.8566,0.8137,0.7316,0.5871,0.3684"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3566,0.3293,0.2863,0.2043,0.0676,-0.1434",\ +"0.3957,0.3762,0.3488,0.3059,0.2238,0.0871,-0.1199",\ +"0.4230,0.4035,0.3723,0.3332,0.2512,0.1184,-0.0965",\ +"0.4660,0.4465,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5324,0.5168,0.4973,0.4543,0.3723,0.2316,0.0285",\ +"0.6809,0.6613,0.6340,0.5910,0.5129,0.3645,0.1652",\ +"0.9113,0.8918,0.8605,0.8176,0.7395,0.5988,0.3879"); + } + } + } +pin(A_REN) { + direction : input ; + capacitance : 0.00381144 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0239); + } + fall_power("scalar"){ + values (0.0205); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0037); + } + fall_power("scalar"){ + values (0.0003); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.0770,-0.0574,-0.0262,0.0168,0.0949,0.2355,0.4582",\ +"-0.0965,-0.0770,-0.0457,-0.0027,0.0754,0.2160,0.4387",\ +"-0.1199,-0.1004,-0.0730,-0.0262,0.0520,0.1887,0.4113",\ +"-0.1590,-0.1434,-0.1160,-0.0730,0.0051,0.1457,0.3645",\ +"-0.2449,-0.2254,-0.1941,-0.1473,-0.0770,0.0676,0.2863",\ +"-0.3816,-0.3699,-0.3387,-0.2801,-0.2215,-0.0770,0.1457",\ +"-0.6121,-0.5926,-0.5613,-0.5145,-0.4363,-0.2996,-0.0730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.1262,0.1457,0.1691,0.2121,0.2824,0.4191,0.6457",\ +"0.1105,0.1262,0.1496,0.1887,0.2629,0.3996,0.6262",\ +"0.0793,0.0949,0.1223,0.1652,0.2395,0.3684,0.5949",\ +"0.0363,0.0559,0.0793,0.1223,0.2004,0.3410,0.5520",\ +"-0.0457,-0.0262,0.0012,0.0441,0.1301,0.2629,0.4738",\ +"-0.1902,-0.1746,-0.1434,-0.1043,-0.0184,0.1223,0.3332",\ +"-0.4129,-0.3934,-0.3660,-0.3230,-0.2449,-0.1043,0.1105"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4113,0.3918,0.3645,0.3176,0.2395,0.0988,-0.1238",\ +"0.4309,0.4113,0.3840,0.3371,0.2590,0.1184,-0.1043",\ +"0.4582,0.4387,0.4113,0.3645,0.2824,0.1457,-0.0770",\ +"0.5051,0.4816,0.4543,0.4074,0.3293,0.1887,-0.0340",\ +"0.5715,0.5598,0.5324,0.4895,0.4035,0.2512,0.0441",\ +"0.7043,0.7004,0.6730,0.6262,0.5402,0.3957,0.1809",\ +"0.9387,0.9270,0.8957,0.8527,0.7746,0.6262,0.4074"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4152,0.3918,0.3645,0.3215,0.2395,0.1027,-0.1082",\ +"0.4309,0.4113,0.3801,0.3410,0.2590,0.1223,-0.0926",\ +"0.4582,0.4387,0.4074,0.3684,0.2863,0.1496,-0.0613",\ +"0.5012,0.4816,0.4504,0.4074,0.3293,0.1887,-0.0145",\ +"0.5715,0.5559,0.5285,0.4816,0.3996,0.2512,0.0598",\ +"0.7160,0.7004,0.6691,0.6262,0.5520,0.4035,0.2004",\ +"0.9387,0.9191,0.8957,0.8488,0.7707,0.6262,0.4113"); + } + } + } +pin(A_MEN) { + direction : input ; + capacitance : 0.00300347 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0853); + } + fall_power("scalar"){ + values (0.0218); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3215,0.3449,0.3684,0.4113,0.4895,0.6301,0.8527",\ +"0.3059,0.3254,0.3527,0.3957,0.4738,0.6145,0.8371",\ +"0.2746,0.2941,0.3215,0.3645,0.4426,0.5871,0.8059",\ +"0.2316,0.2512,0.2785,0.3215,0.3996,0.5402,0.7629",\ +"0.1496,0.1730,0.1965,0.2395,0.3215,0.4660,0.6848",\ +"0.0090,0.0285,0.0598,0.1027,0.1809,0.3176,0.5402",\ +"-0.2098,-0.1902,-0.1668,-0.1199,-0.0418,0.0988,0.3137"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4582,0.4738,0.5012,0.5363,0.6145,0.7395,0.9738",\ +"0.4387,0.4543,0.4816,0.5207,0.5910,0.7199,0.9582",\ +"0.4035,0.4230,0.4504,0.4855,0.5637,0.6887,0.9230",\ +"0.3645,0.3840,0.4074,0.4465,0.5285,0.6496,0.8840",\ +"0.2824,0.3020,0.3254,0.3645,0.4465,0.5715,0.7980",\ +"0.1418,0.1613,0.1887,0.2238,0.3020,0.4309,0.6496",\ +"-0.0770,-0.0574,-0.0301,0.0090,0.0910,0.2238,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3293,0.2863,0.2043,0.0637,-0.1629",\ +"0.3996,0.3801,0.3488,0.3020,0.2238,0.0832,-0.1395",\ +"0.4230,0.4074,0.3723,0.3293,0.2473,0.1105,-0.1121",\ +"0.4621,0.4465,0.4152,0.3762,0.2941,0.1535,-0.0691",\ +"0.5441,0.5285,0.4973,0.4465,0.3684,0.2316,0.0090",\ +"0.6848,0.6652,0.6301,0.5910,0.5129,0.3605,0.1496",\ +"0.9074,0.8918,0.8566,0.8215,0.7395,0.5910,0.3723"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3332,0.2863,0.2043,0.0715,-0.1395",\ +"0.3996,0.3762,0.3488,0.3059,0.2238,0.0910,-0.1199",\ +"0.4270,0.4035,0.3762,0.3332,0.2512,0.1184,-0.0965",\ +"0.4699,0.4504,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5441,0.5285,0.4973,0.4543,0.3762,0.2355,0.0324",\ +"0.6770,0.6613,0.6340,0.5949,0.5207,0.3762,0.1652",\ +"0.9074,0.8918,0.8605,0.8176,0.7395,0.6027,0.3918"); + } + } + } +bus(A_BM) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00272583 ; + max_transition : "0.5952" ; + pin(A_BM[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0645); + } + fall_power("scalar"){ + values (0.0555); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0341); + } + fall_power("scalar"){ + values (0.0017); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7140,-0.6945,-0.6681,-0.6252,-0.5451,-0.3976,-0.1769",\ +"-0.7220,-0.7025,-0.6761,-0.6332,-0.5531,-0.4056,-0.1849",\ +"-0.7321,-0.7126,-0.6862,-0.6433,-0.5632,-0.4157,-0.1950",\ +"-0.7451,-0.7255,-0.6992,-0.6562,-0.5761,-0.4286,-0.2079",\ +"-0.7704,-0.7509,-0.7245,-0.6815,-0.6015,-0.4540,-0.2333",\ +"-0.8126,-0.7931,-0.7667,-0.7237,-0.6437,-0.4962,-0.2755",\ +"-0.8770,-0.8575,-0.8311,-0.7882,-0.7081,-0.5606,-0.3399"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.6496,-0.6301,-0.6037,-0.5656,-0.4826,-0.3459,-0.1340",\ +"-0.6576,-0.6381,-0.6117,-0.5736,-0.4906,-0.3539,-0.1420",\ +"-0.6677,-0.6481,-0.6218,-0.5837,-0.5007,-0.3640,-0.1521",\ +"-0.6806,-0.6611,-0.6347,-0.5966,-0.5136,-0.3769,-0.1650",\ +"-0.7059,-0.6864,-0.6600,-0.6220,-0.5390,-0.4022,-0.1903",\ +"-0.7481,-0.7286,-0.7022,-0.6642,-0.5812,-0.4444,-0.2325",\ +"-0.8126,-0.7930,-0.7667,-0.7286,-0.6456,-0.5089,-0.2969"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8263,0.8058,0.7804,0.7374,0.6593,0.5128,0.2901",\ +"0.8343,0.8138,0.7884,0.7454,0.6673,0.5208,0.2981",\ +"0.8444,0.8239,0.7985,0.7555,0.6774,0.5309,0.3082",\ +"0.8573,0.8368,0.8114,0.7684,0.6903,0.5438,0.3211",\ +"0.8826,0.8621,0.8367,0.7938,0.7156,0.5691,0.3465",\ +"0.9248,0.9043,0.8789,0.8360,0.7578,0.6113,0.3887",\ +"0.9892,0.9687,0.9433,0.9004,0.8223,0.6758,0.4531"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.7530,0.7355,0.7071,0.6661,0.5860,0.4483,0.2374",\ +"0.7610,0.7435,0.7151,0.6741,0.5940,0.4563,0.2454",\ +"0.7711,0.7535,0.7252,0.6842,0.6041,0.4664,0.2555",\ +"0.7841,0.7665,0.7381,0.6971,0.6170,0.4794,0.2684",\ +"0.8094,0.7918,0.7635,0.7225,0.6424,0.5047,0.2938",\ +"0.8516,0.8340,0.8057,0.7647,0.6846,0.5469,0.3360",\ +"0.9160,0.8984,0.8701,0.8291,0.7490,0.6113,0.4004"); + } + } +} + pin(A_CLK) { + direction : input; + capacitance : 0.00378957; + max_transition : "0.5952"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.008,0.5952"); + values("0.4,0.4"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (2.4669); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (60.0756); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (56.8329); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (47.0671); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (0.5979); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (0.9552); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_DIN) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00290547 ; + memory_write() { + address : A_ADDR ; + clocked_on : A_CLK; + } + + max_transition : "0.5952" ; + pin(A_DIN[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0645); + } + fall_power("scalar"){ + values (0.0555); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0341); + } + fall_power("scalar"){ + values (0.0017); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7140,-0.6945,-0.6681,-0.6252,-0.5451,-0.3976,-0.1769",\ +"-0.7220,-0.7025,-0.6761,-0.6332,-0.5531,-0.4056,-0.1849",\ +"-0.7321,-0.7126,-0.6862,-0.6433,-0.5632,-0.4157,-0.1950",\ +"-0.7451,-0.7255,-0.6992,-0.6562,-0.5761,-0.4286,-0.2079",\ +"-0.7704,-0.7509,-0.7245,-0.6815,-0.6015,-0.4540,-0.2333",\ +"-0.8126,-0.7931,-0.7667,-0.7237,-0.6437,-0.4962,-0.2755",\ +"-0.8770,-0.8575,-0.8311,-0.7882,-0.7081,-0.5606,-0.3399"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.6496,-0.6301,-0.6037,-0.5656,-0.4826,-0.3459,-0.1340",\ +"-0.6576,-0.6381,-0.6117,-0.5736,-0.4906,-0.3539,-0.1420",\ +"-0.6677,-0.6481,-0.6218,-0.5837,-0.5007,-0.3640,-0.1521",\ +"-0.6806,-0.6611,-0.6347,-0.5966,-0.5136,-0.3769,-0.1650",\ +"-0.7059,-0.6864,-0.6600,-0.6220,-0.5390,-0.4022,-0.1903",\ +"-0.7481,-0.7286,-0.7022,-0.6642,-0.5812,-0.4444,-0.2325",\ +"-0.8126,-0.7930,-0.7667,-0.7286,-0.6456,-0.5089,-0.2969"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8263,0.8058,0.7804,0.7374,0.6593,0.5128,0.2901",\ +"0.8343,0.8138,0.7884,0.7454,0.6673,0.5208,0.2981",\ +"0.8444,0.8239,0.7985,0.7555,0.6774,0.5309,0.3082",\ +"0.8573,0.8368,0.8114,0.7684,0.6903,0.5438,0.3211",\ +"0.8826,0.8621,0.8367,0.7938,0.7156,0.5691,0.3465",\ +"0.9248,0.9043,0.8789,0.8360,0.7578,0.6113,0.3887",\ +"0.9892,0.9687,0.9433,0.9004,0.8223,0.6758,0.4531"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.7530,0.7355,0.7071,0.6661,0.5860,0.4483,0.2374",\ +"0.7610,0.7435,0.7151,0.6741,0.5940,0.4563,0.2454",\ +"0.7711,0.7535,0.7252,0.6842,0.6041,0.4664,0.2555",\ +"0.7841,0.7665,0.7381,0.6971,0.6170,0.4794,0.2684",\ +"0.8094,0.7918,0.7635,0.7225,0.6424,0.5047,0.2938",\ +"0.8516,0.8340,0.8057,0.7647,0.6846,0.5469,0.3360",\ +"0.9160,0.8984,0.8701,0.8291,0.7490,0.6113,0.4004"); + } + } + } + + pin(A_BIST_EN) { + direction : input ; + capacitance : 0.00387999 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_BIST_ADDR) { + bus_type : A_11_0; + direction : input ; + capacitance : 0.0077013 ; + pin(A_BIST_ADDR[0]) { + capacitance : 0.00625349 ; + } + pin(A_BIST_ADDR[1]) { + capacitance : 0.00507435 ; + } + pin(A_BIST_ADDR[2]) { + capacitance : 0.00656707 ; + } + pin(A_BIST_ADDR[3]) { + capacitance : 0.0083133 ; + } + pin(A_BIST_ADDR[4]) { + capacitance : 0.00507219 ; + } + pin(A_BIST_ADDR[5]) { + capacitance : 0.00964344 ; + } + pin(A_BIST_ADDR[6]) { + capacitance : 0.0119653 ; + } + pin(A_BIST_ADDR[7]) { + capacitance : 0.00827606 ; + } + pin(A_BIST_ADDR[8]) { + capacitance : 0.0110771 ; + } + pin(A_BIST_ADDR[9]) { + capacitance : 0.00811634 ; + } + pin(A_BIST_ADDR[10]) { + capacitance : 0.00916579 ; + } + max_transition : "0.5952" ; + pin(A_BIST_ADDR[11:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0276); + } + fall_power("scalar"){ + values (0.0166); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0210); + } + fall_power("scalar"){ + values (0.0037); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7371,-0.7176,-0.6863,-0.6434,-0.5652,-0.4168,-0.1980",\ +"-0.7566,-0.7371,-0.7059,-0.6629,-0.5848,-0.4363,-0.2137",\ +"-0.7879,-0.7645,-0.7332,-0.6902,-0.6121,-0.4637,-0.2449",\ +"-0.8309,-0.8074,-0.7762,-0.7332,-0.6551,-0.5066,-0.2879",\ +"-0.9051,-0.8895,-0.8543,-0.8113,-0.7332,-0.5887,-0.3660",\ +"-1.0418,-1.0262,-0.9949,-0.9480,-0.8699,-0.7293,-0.5027",\ +"-1.2684,-1.2449,-1.2176,-1.1707,-1.0965,-0.9480,-0.7293"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5926,-0.5730,-0.5418,-0.4988,-0.4246,-0.2879,-0.0730",\ +"-0.6121,-0.5926,-0.5613,-0.5223,-0.4441,-0.3074,-0.0887",\ +"-0.6395,-0.6199,-0.5926,-0.5496,-0.4715,-0.3348,-0.1160",\ +"-0.6863,-0.6668,-0.6355,-0.5965,-0.5184,-0.3777,-0.1590",\ +"-0.7605,-0.7410,-0.7137,-0.6746,-0.5926,-0.4559,-0.2410",\ +"-0.9012,-0.8816,-0.8504,-0.8113,-0.7332,-0.5926,-0.3895",\ +"-1.1238,-1.1043,-1.0769,-1.0379,-0.9559,-0.8191,-0.6004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8488,0.8293,0.7980,0.7551,0.6730,0.5285,0.3098",\ +"0.8684,0.8488,0.8176,0.7746,0.6926,0.5480,0.3254",\ +"0.8996,0.8801,0.8449,0.8020,0.7238,0.5754,0.3527",\ +"0.9426,0.9191,0.8918,0.8488,0.7668,0.6223,0.3996",\ +"1.0168,1.0012,0.9699,0.9230,0.8449,0.7004,0.4777",\ +"1.1574,1.1379,1.1105,1.0598,0.9816,0.8371,0.6184",\ +"1.3801,1.3605,1.3254,1.2980,1.2043,1.0637,0.8371"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6965,0.6770,0.6496,0.6066,0.5246,0.3918,0.1730",\ +"0.7160,0.6965,0.6652,0.6262,0.5441,0.4113,0.1965",\ +"0.7473,0.7277,0.6965,0.6535,0.5754,0.4426,0.2238",\ +"0.7863,0.7707,0.7395,0.7004,0.6223,0.4855,0.2629",\ +"0.8684,0.8449,0.8176,0.7785,0.7004,0.5637,0.3449",\ +"1.0051,0.9855,0.9855,0.9113,0.8332,0.7004,0.4895",\ +"1.2277,1.2082,1.1809,1.1379,1.0598,0.9230,0.7004"); + } + } +} +pin(A_BIST_WEN) { + direction : input ; + capacitance : 0.00313551 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0235); + } + fall_power("scalar"){ + values (0.0210); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0049); + } + fall_power("scalar"){ + values (0.0013); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3137,0.3332,0.3605,0.4035,0.4816,0.6223,0.8488",\ +"0.2980,0.3176,0.3410,0.3840,0.4660,0.6027,0.8293",\ +"0.2629,0.2824,0.3098,0.3527,0.4348,0.5754,0.7980",\ +"0.2199,0.2395,0.2668,0.3098,0.3918,0.5324,0.7590",\ +"0.1418,0.1613,0.1887,0.2316,0.3137,0.4348,0.6730",\ +"0.0012,0.0207,0.0520,0.0910,0.1730,0.3098,0.5285",\ +"-0.2215,-0.2020,-0.1746,-0.1277,-0.0496,0.0910,0.3098"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4504,0.4699,0.4973,0.5324,0.6027,0.7355,0.9699",\ +"0.4309,0.4504,0.4777,0.5129,0.5910,0.7160,0.9504",\ +"0.3996,0.4191,0.4465,0.4816,0.5520,0.6848,0.9191",\ +"0.3605,0.3762,0.4035,0.4387,0.5168,0.6418,0.8723",\ +"0.2785,0.2980,0.3215,0.3605,0.4348,0.5637,0.7980",\ +"0.1379,0.1574,0.1809,0.2199,0.2980,0.4309,0.6457",\ +"-0.0809,-0.0613,-0.0340,0.0051,0.0832,0.2160,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3723,0.3527,0.3215,0.2785,0.1965,0.0559,-0.1668",\ +"0.3918,0.3723,0.3449,0.2980,0.2160,0.0754,-0.1473",\ +"0.4152,0.3996,0.3684,0.3254,0.2434,0.1066,-0.1199",\ +"0.4621,0.4465,0.4152,0.3723,0.2863,0.1496,-0.0730",\ +"0.5324,0.5207,0.4895,0.4465,0.3645,0.2199,0.0051",\ +"0.6770,0.6535,0.6301,0.5832,0.5090,0.3605,0.1418",\ +"0.9035,0.8879,0.8566,0.8137,0.7316,0.5871,0.3684"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3566,0.3293,0.2863,0.2043,0.0676,-0.1434",\ +"0.3957,0.3762,0.3488,0.3059,0.2238,0.0871,-0.1199",\ +"0.4230,0.4035,0.3723,0.3332,0.2512,0.1184,-0.0965",\ +"0.4660,0.4465,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5324,0.5168,0.4973,0.4543,0.3723,0.2316,0.0285",\ +"0.6809,0.6613,0.6340,0.5910,0.5129,0.3645,0.1652",\ +"0.9113,0.8918,0.8605,0.8176,0.7395,0.5988,0.3879"); + } + } + } +pin(A_BIST_REN) { + direction : input ; + capacitance : 0.00381144 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0239); + } + fall_power("scalar"){ + values (0.0205); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0037); + } + fall_power("scalar"){ + values (0.0003); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.0770,-0.0574,-0.0262,0.0168,0.0949,0.2355,0.4582",\ +"-0.0965,-0.0770,-0.0457,-0.0027,0.0754,0.2160,0.4387",\ +"-0.1199,-0.1004,-0.0730,-0.0262,0.0520,0.1887,0.4113",\ +"-0.1590,-0.1434,-0.1160,-0.0730,0.0051,0.1457,0.3645",\ +"-0.2449,-0.2254,-0.1941,-0.1473,-0.0770,0.0676,0.2863",\ +"-0.3816,-0.3699,-0.3387,-0.2801,-0.2215,-0.0770,0.1457",\ +"-0.6121,-0.5926,-0.5613,-0.5145,-0.4363,-0.2996,-0.0730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.1262,0.1457,0.1691,0.2121,0.2824,0.4191,0.6457",\ +"0.1105,0.1262,0.1496,0.1887,0.2629,0.3996,0.6262",\ +"0.0793,0.0949,0.1223,0.1652,0.2395,0.3684,0.5949",\ +"0.0363,0.0559,0.0793,0.1223,0.2004,0.3410,0.5520",\ +"-0.0457,-0.0262,0.0012,0.0441,0.1301,0.2629,0.4738",\ +"-0.1902,-0.1746,-0.1434,-0.1043,-0.0184,0.1223,0.3332",\ +"-0.4129,-0.3934,-0.3660,-0.3230,-0.2449,-0.1043,0.1105"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4113,0.3918,0.3645,0.3176,0.2395,0.0988,-0.1238",\ +"0.4309,0.4113,0.3840,0.3371,0.2590,0.1184,-0.1043",\ +"0.4582,0.4387,0.4113,0.3645,0.2824,0.1457,-0.0770",\ +"0.5051,0.4816,0.4543,0.4074,0.3293,0.1887,-0.0340",\ +"0.5715,0.5598,0.5324,0.4895,0.4035,0.2512,0.0441",\ +"0.7043,0.7004,0.6730,0.6262,0.5402,0.3957,0.1809",\ +"0.9387,0.9270,0.8957,0.8527,0.7746,0.6262,0.4074"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4152,0.3918,0.3645,0.3215,0.2395,0.1027,-0.1082",\ +"0.4309,0.4113,0.3801,0.3410,0.2590,0.1223,-0.0926",\ +"0.4582,0.4387,0.4074,0.3684,0.2863,0.1496,-0.0613",\ +"0.5012,0.4816,0.4504,0.4074,0.3293,0.1887,-0.0145",\ +"0.5715,0.5559,0.5285,0.4816,0.3996,0.2512,0.0598",\ +"0.7160,0.7004,0.6691,0.6262,0.5520,0.4035,0.2004",\ +"0.9387,0.9191,0.8957,0.8488,0.7707,0.6262,0.4113"); + } + } + } +pin(A_BIST_MEN) { + direction : input ; + capacitance : 0.00300347 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0853); + } + fall_power("scalar"){ + values (0.0218); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3215,0.3449,0.3684,0.4113,0.4895,0.6301,0.8527",\ +"0.3059,0.3254,0.3527,0.3957,0.4738,0.6145,0.8371",\ +"0.2746,0.2941,0.3215,0.3645,0.4426,0.5871,0.8059",\ +"0.2316,0.2512,0.2785,0.3215,0.3996,0.5402,0.7629",\ +"0.1496,0.1730,0.1965,0.2395,0.3215,0.4660,0.6848",\ +"0.0090,0.0285,0.0598,0.1027,0.1809,0.3176,0.5402",\ +"-0.2098,-0.1902,-0.1668,-0.1199,-0.0418,0.0988,0.3137"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4582,0.4738,0.5012,0.5363,0.6145,0.7395,0.9738",\ +"0.4387,0.4543,0.4816,0.5207,0.5910,0.7199,0.9582",\ +"0.4035,0.4230,0.4504,0.4855,0.5637,0.6887,0.9230",\ +"0.3645,0.3840,0.4074,0.4465,0.5285,0.6496,0.8840",\ +"0.2824,0.3020,0.3254,0.3645,0.4465,0.5715,0.7980",\ +"0.1418,0.1613,0.1887,0.2238,0.3020,0.4309,0.6496",\ +"-0.0770,-0.0574,-0.0301,0.0090,0.0910,0.2238,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3293,0.2863,0.2043,0.0637,-0.1629",\ +"0.3996,0.3801,0.3488,0.3020,0.2238,0.0832,-0.1395",\ +"0.4230,0.4074,0.3723,0.3293,0.2473,0.1105,-0.1121",\ +"0.4621,0.4465,0.4152,0.3762,0.2941,0.1535,-0.0691",\ +"0.5441,0.5285,0.4973,0.4465,0.3684,0.2316,0.0090",\ +"0.6848,0.6652,0.6301,0.5910,0.5129,0.3605,0.1496",\ +"0.9074,0.8918,0.8566,0.8215,0.7395,0.5910,0.3723"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3332,0.2863,0.2043,0.0715,-0.1395",\ +"0.3996,0.3762,0.3488,0.3059,0.2238,0.0910,-0.1199",\ +"0.4270,0.4035,0.3762,0.3332,0.2512,0.1184,-0.0965",\ +"0.4699,0.4504,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5441,0.5285,0.4973,0.4543,0.3762,0.2355,0.0324",\ +"0.6770,0.6613,0.6340,0.5949,0.5207,0.3762,0.1652",\ +"0.9074,0.8918,0.8605,0.8176,0.7395,0.6027,0.3918"); + } + } + } +bus(A_BIST_BM) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00223339 ; + max_transition : "0.5952" ; + pin(A_BIST_BM[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0645); + } + fall_power("scalar"){ + values (0.0555); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0341); + } + fall_power("scalar"){ + values (0.0017); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7140,-0.6945,-0.6681,-0.6252,-0.5451,-0.3976,-0.1769",\ +"-0.7220,-0.7025,-0.6761,-0.6332,-0.5531,-0.4056,-0.1849",\ +"-0.7321,-0.7126,-0.6862,-0.6433,-0.5632,-0.4157,-0.1950",\ +"-0.7451,-0.7255,-0.6992,-0.6562,-0.5761,-0.4286,-0.2079",\ +"-0.7704,-0.7509,-0.7245,-0.6815,-0.6015,-0.4540,-0.2333",\ +"-0.8126,-0.7931,-0.7667,-0.7237,-0.6437,-0.4962,-0.2755",\ +"-0.8770,-0.8575,-0.8311,-0.7882,-0.7081,-0.5606,-0.3399"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.6496,-0.6301,-0.6037,-0.5656,-0.4826,-0.3459,-0.1340",\ +"-0.6576,-0.6381,-0.6117,-0.5736,-0.4906,-0.3539,-0.1420",\ +"-0.6677,-0.6481,-0.6218,-0.5837,-0.5007,-0.3640,-0.1521",\ +"-0.6806,-0.6611,-0.6347,-0.5966,-0.5136,-0.3769,-0.1650",\ +"-0.7059,-0.6864,-0.6600,-0.6220,-0.5390,-0.4022,-0.1903",\ +"-0.7481,-0.7286,-0.7022,-0.6642,-0.5812,-0.4444,-0.2325",\ +"-0.8126,-0.7930,-0.7667,-0.7286,-0.6456,-0.5089,-0.2969"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8263,0.8058,0.7804,0.7374,0.6593,0.5128,0.2901",\ +"0.8343,0.8138,0.7884,0.7454,0.6673,0.5208,0.2981",\ +"0.8444,0.8239,0.7985,0.7555,0.6774,0.5309,0.3082",\ +"0.8573,0.8368,0.8114,0.7684,0.6903,0.5438,0.3211",\ +"0.8826,0.8621,0.8367,0.7938,0.7156,0.5691,0.3465",\ +"0.9248,0.9043,0.8789,0.8360,0.7578,0.6113,0.3887",\ +"0.9892,0.9687,0.9433,0.9004,0.8223,0.6758,0.4531"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.7530,0.7355,0.7071,0.6661,0.5860,0.4483,0.2374",\ +"0.7610,0.7435,0.7151,0.6741,0.5940,0.4563,0.2454",\ +"0.7711,0.7535,0.7252,0.6842,0.6041,0.4664,0.2555",\ +"0.7841,0.7665,0.7381,0.6971,0.6170,0.4794,0.2684",\ +"0.8094,0.7918,0.7635,0.7225,0.6424,0.5047,0.2938",\ +"0.8516,0.8340,0.8057,0.7647,0.6846,0.5469,0.3360",\ +"0.9160,0.8984,0.8701,0.8291,0.7490,0.6113,0.4004"); + } + } +} + pin(A_BIST_CLK) { + direction : input; + capacitance : 0.00378957; + max_transition : "0.5952"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.008,0.5952"); + values("0.4,0.4"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (2.4669); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (60.0756); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (56.8329); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (47.0671); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.5979); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.9552); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_BIST_DIN) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00223473 ; + memory_write() { + address : A_BIST_ADDR ; + clocked_on : A_BIST_CLK; + } + + max_transition : "0.5952" ; + pin(A_BIST_DIN[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0645); + } + fall_power("scalar"){ + values (0.0555); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0341); + } + fall_power("scalar"){ + values (0.0017); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7140,-0.6945,-0.6681,-0.6252,-0.5451,-0.3976,-0.1769",\ +"-0.7220,-0.7025,-0.6761,-0.6332,-0.5531,-0.4056,-0.1849",\ +"-0.7321,-0.7126,-0.6862,-0.6433,-0.5632,-0.4157,-0.1950",\ +"-0.7451,-0.7255,-0.6992,-0.6562,-0.5761,-0.4286,-0.2079",\ +"-0.7704,-0.7509,-0.7245,-0.6815,-0.6015,-0.4540,-0.2333",\ +"-0.8126,-0.7931,-0.7667,-0.7237,-0.6437,-0.4962,-0.2755",\ +"-0.8770,-0.8575,-0.8311,-0.7882,-0.7081,-0.5606,-0.3399"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.6496,-0.6301,-0.6037,-0.5656,-0.4826,-0.3459,-0.1340",\ +"-0.6576,-0.6381,-0.6117,-0.5736,-0.4906,-0.3539,-0.1420",\ +"-0.6677,-0.6481,-0.6218,-0.5837,-0.5007,-0.3640,-0.1521",\ +"-0.6806,-0.6611,-0.6347,-0.5966,-0.5136,-0.3769,-0.1650",\ +"-0.7059,-0.6864,-0.6600,-0.6220,-0.5390,-0.4022,-0.1903",\ +"-0.7481,-0.7286,-0.7022,-0.6642,-0.5812,-0.4444,-0.2325",\ +"-0.8126,-0.7930,-0.7667,-0.7286,-0.6456,-0.5089,-0.2969"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8263,0.8058,0.7804,0.7374,0.6593,0.5128,0.2901",\ +"0.8343,0.8138,0.7884,0.7454,0.6673,0.5208,0.2981",\ +"0.8444,0.8239,0.7985,0.7555,0.6774,0.5309,0.3082",\ +"0.8573,0.8368,0.8114,0.7684,0.6903,0.5438,0.3211",\ +"0.8826,0.8621,0.8367,0.7938,0.7156,0.5691,0.3465",\ +"0.9248,0.9043,0.8789,0.8360,0.7578,0.6113,0.3887",\ +"0.9892,0.9687,0.9433,0.9004,0.8223,0.6758,0.4531"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.7530,0.7355,0.7071,0.6661,0.5860,0.4483,0.2374",\ +"0.7610,0.7435,0.7151,0.6741,0.5940,0.4563,0.2454",\ +"0.7711,0.7535,0.7252,0.6842,0.6041,0.4664,0.2555",\ +"0.7841,0.7665,0.7381,0.6971,0.6170,0.4794,0.2684",\ +"0.8094,0.7918,0.7635,0.7225,0.6424,0.5047,0.2938",\ +"0.8516,0.8340,0.8057,0.7647,0.6846,0.5469,0.3360",\ +"0.9160,0.8984,0.8701,0.8291,0.7490,0.6113,0.4004"); + } + } + } + +bus(A_DOUT) { + + bus_type : D_15_0; + direction : output ; + capacitance : 0 ; + max_capacitance : "6.4e-14" ; + memory_read() { + address : A_ADDR ; + } + pin(A_DOUT[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "A_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("8.8937,8.8964,8.9086,8.9228,8.9749,9.0329",\ +"8.9058,8.9085,8.9207,8.9349,8.9870,9.0450",\ +"8.9177,8.9205,8.9327,8.9469,8.9989,9.0569",\ +"8.9199,8.9226,8.9348,8.9490,9.0011,9.0591",\ +"8.9457,8.9484,8.9606,8.9748,9.0269,9.0849",\ +"8.9971,8.9998,9.0120,9.0262,9.0783,9.1363",\ +"9.0539,9.0566,9.0688,9.0830,9.1351,9.1931"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("8.7838,8.7860,8.7956,8.8074,8.8510,8.8947",\ +"8.7959,8.7981,8.8077,8.8195,8.8631,8.9068",\ +"8.8078,8.8100,8.8196,8.8314,8.8750,8.9187",\ +"8.8100,8.8121,8.8217,8.8336,8.8771,8.9209",\ +"8.8358,8.8380,8.8476,8.8594,8.9030,8.9467",\ +"8.8872,8.8893,8.8990,8.9108,8.9543,8.9981",\ +"8.9440,8.9462,8.9558,8.9676,9.0112,9.0549"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0560,0.0583,0.0696,0.0816,0.1519,0.2335"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0428,0.0445,0.0538,0.0658,0.1181,0.1751"); + } + } +} +cell_leakage_power : 5226.3526; +} +} diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_4096x16_c3_bm_bist_typ_1p20V_25C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_4096x16_c3_bm_bist_typ_1p20V_25C.lib new file mode 100644 index 0000000000..86dafef075 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_4096x16_c3_bm_bist_typ_1p20V_25C.lib @@ -0,0 +1,1537 @@ +/* ------------------------------------------------------*/ +/**/ +/* Copyright 2024 IHP PDK Authors*/ +/**/ +/* Licensed under the Apache License, Version 2.0 (the "License");*/ +/* you may not use this file except in compliance with the License.*/ +/* You may obtain a copy of the License at*/ +/* */ +/* https://www.apache.org/licenses/LICENSE-2.0*/ +/* */ +/* Unless required by applicable law or agreed to in writing, software*/ +/* distributed under the License is distributed on an "AS IS" BASIS,*/ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/ +/* See the License for the specific language governing permissions and*/ +/* limitations under the License.*/ +/* */ +/* Generated on Fri Jul 12 17:37:35 2024 */ +/* */ +/* ------------------------------------------------------ */ +library(RM_IHPSG13_1P_4096x16_c3_bm_bist_typ_1p20V_25C) { + technology (cmos) ; + delay_model : table_lookup ; + define ("add_pg_pin_to_lib", "library", "boolean"); + add_pg_pin_to_lib : true; + voltage_map ( VDD, 1.20); + voltage_map ( VDDARRAY, 1.20); + voltage_map ( VSS, 0.000000 ); + + date : "Fri Jul 12 17:37:29 2024" ; + comment : "IHP Microelectronics GmbH, 2024" ; + revision : 1.0.0 ; + simulation : true ; + nom_process : 1 ; + nom_temperature : 25 ; + nom_voltage : 1.20 ; + + operating_conditions("typ_1p20V_25C"){ + process : 1 ; + temperature : 25 ; + voltage : 1.20 ; + tree_type : "balanced_tree" ; + } + + default_operating_conditions : typ_1p20V_25C ; + default_max_transition : 1.0 ; + default_fanout_load : 1.0 ; + default_inout_pin_cap : 0.0 ; + default_input_pin_cap : 0.0 ; + default_output_pin_cap : 0.0 ; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + + slew_lower_threshold_pct_rise : 30 ; + slew_upper_threshold_pct_rise : 70 ; + input_threshold_pct_fall : 50 ; + output_threshold_pct_fall : 50 ; + input_threshold_pct_rise : 50 ; + output_threshold_pct_rise : 50 ; + slew_lower_threshold_pct_fall : 30 ; + slew_upper_threshold_pct_fall : 70 ; + slew_derate_from_library : 0.5; + k_volt_cell_leakage_power : 0.0 ; + k_temp_cell_leakage_power : 0.0 ; + k_process_cell_leakage_power : 0.0 ; + k_volt_internal_power : 0.0 ; + k_temp_internal_power : 0.0 ; + k_process_internal_power : 0.0 ; + + capacitive_load_unit (1,pf) ; + voltage_unit : "1V" ; + current_unit : "1uA" ; + time_unit : "1ns" ; + leakage_power_unit : "1nW" ; + pulling_resistance_unit : "1kohm"; + /* + ------------------------------------------------------------------------------------------ + implicit units overview: + cell_area unit : "um" + internal_power unit : "1e-12 * J/toggle = 1 * uW/MHz" + (capacitive_load_unit * voltage_unit^2) per toggle event + ------------------------------------------------------------------------------------------ + */ + library_features(report_delay_calculation); + define_cell_area (pad_drivers,pad_driver_sites) ; + + lu_table_template(CLKTRAN_constraint_template) { + variable_1 : constrained_pin_transition; + index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" ); + } + lu_table_template(SRAM_load_template) { + variable_1 : total_output_net_capacitance; + index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + lu_table_template(SIG2SRAM_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" ); + index_2 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" ); + } + + lu_table_template(SIG2SRAM_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" ); + index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + + type (D_15_0) { + base_type : array; + data_type : bit; + bit_width : 16; + bit_from : 15; + bit_to : 0; + downto : true; + } + + type (A_11_0) { + base_type : array; + data_type : bit; + bit_width : 12; + bit_from : 11; + bit_to : 0; + downto : true; + } + +cell(RM_IHPSG13_1P_4096x16_c3_bm_bist) { +pg_pin (VDD) { + pg_type : primary_power; + voltage_name : VDD; +} +pg_pin (VDDARRAY) { + pg_type : primary_power; + voltage_name : VDDARRAY; +} +pg_pin (VSS) { + pg_type : primary_ground; + voltage_name : VSS; +} + +memory() { + type : ram; + address_width : 12; + word_width : 16; +} + +interface_timing : false; +bus_naming_style : "%s[%d]" ; +area : 257608.512 ; + + pin(A_DLY) { + direction : input ; + capacitance : 0.00401111 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_ADDR) { + bus_type : A_11_0; + direction : input ; + capacitance : 0.00721489 ; + pin(A_ADDR[0]) { + capacitance : 0.00593979 ; + } + pin(A_ADDR[1]) { + capacitance : 0.00483009 ; + } + pin(A_ADDR[2]) { + capacitance : 0.006215 ; + } + pin(A_ADDR[3]) { + capacitance : 0.00766726 ; + } + pin(A_ADDR[4]) { + capacitance : 0.00488951 ; + } + pin(A_ADDR[5]) { + capacitance : 0.0091523 ; + } + pin(A_ADDR[6]) { + capacitance : 0.0109212 ; + } + pin(A_ADDR[7]) { + capacitance : 0.00774122 ; + } + pin(A_ADDR[8]) { + capacitance : 0.0101403 ; + } + pin(A_ADDR[9]) { + capacitance : 0.00771605 ; + } + pin(A_ADDR[10]) { + capacitance : 0.00860549 ; + } + max_transition : "0.476" ; + pin(A_ADDR[11:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0076); + } + fall_power("scalar"){ + values (0.0017); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0180); + } + fall_power("scalar"){ + values (0.0031); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4168,-0.3973,-0.3855,-0.3543,-0.3074,-0.2020,-0.0027",\ +"-0.4324,-0.4129,-0.4012,-0.3699,-0.3191,-0.2176,-0.0184",\ +"-0.4441,-0.4285,-0.4129,-0.3816,-0.3309,-0.2293,-0.0301",\ +"-0.4793,-0.4598,-0.4441,-0.4129,-0.3660,-0.2645,-0.0652",\ +"-0.5223,-0.5066,-0.4910,-0.4598,-0.4129,-0.3074,-0.1121",\ +"-0.6199,-0.6082,-0.5926,-0.5613,-0.5145,-0.4129,-0.2137",\ +"-0.8191,-0.8074,-0.7840,-0.7566,-0.7098,-0.6082,-0.4051"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3309,-0.3113,-0.2996,-0.2684,-0.2176,-0.1238,0.0637",\ +"-0.3465,-0.3309,-0.3152,-0.2840,-0.2332,-0.1395,0.0480",\ +"-0.3582,-0.3426,-0.3270,-0.2996,-0.2488,-0.1512,0.0324",\ +"-0.3895,-0.3738,-0.3582,-0.3309,-0.2801,-0.1863,0.0051",\ +"-0.4363,-0.4207,-0.4051,-0.3777,-0.3230,-0.2293,-0.0379",\ +"-0.5379,-0.5223,-0.5066,-0.4793,-0.4285,-0.3309,-0.1434",\ +"-0.7332,-0.7176,-0.7020,-0.6746,-0.6238,-0.5262,-0.3387"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5246,0.5051,0.4895,0.4582,0.4113,0.3059,0.1066",\ +"0.5402,0.5207,0.5051,0.4777,0.4270,0.3215,0.1223",\ +"0.5520,0.5324,0.5168,0.4895,0.4387,0.3371,0.1340",\ +"0.5832,0.5676,0.5520,0.5207,0.4738,0.3684,0.1691",\ +"0.6301,0.6105,0.5949,0.5676,0.5168,0.4113,0.2160",\ +"0.7316,0.7121,0.7004,0.6691,0.6223,0.5168,0.3176",\ +"0.9270,0.9230,0.8957,0.8645,0.8137,0.7121,0.5168"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4309,0.4152,0.4035,0.3684,0.3215,0.2277,0.0363",\ +"0.4465,0.4309,0.4152,0.3879,0.3371,0.2395,0.0559",\ +"0.4582,0.4426,0.4309,0.3996,0.3488,0.2551,0.0715",\ +"0.4934,0.4777,0.4621,0.4348,0.3840,0.2863,0.0988",\ +"0.5363,0.5207,0.5051,0.4777,0.4270,0.3332,0.1418",\ +"0.6379,0.6262,0.6105,0.5793,0.5324,0.4348,0.2434",\ +"0.8332,0.8215,0.8059,0.7707,0.7238,0.6301,0.4387"); + } + } +} +pin(A_WEN) { + direction : input ; + capacitance : 0.00324098 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0038); + } + fall_power("scalar"){ + values (0.0050); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0034); + } + fall_power("scalar"){ + values (0.0050); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2629,0.3059,0.4113,0.6066",\ +"0.1887,0.2043,0.2160,0.2473,0.2941,0.3957,0.5949",\ +"0.1691,0.1848,0.2004,0.2316,0.2785,0.3801,0.5754",\ +"0.1379,0.1574,0.1691,0.2004,0.2473,0.3527,0.5480",\ +"0.0910,0.1066,0.1223,0.1535,0.2004,0.2980,0.4973",\ +"-0.0105,0.0051,0.0207,0.0520,0.0949,0.2004,0.3957",\ +"-0.2059,-0.1902,-0.1746,-0.1473,-0.1004,0.0051,0.2004"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2941,0.3098,0.3215,0.3488,0.4035,0.4973,0.6887",\ +"0.2785,0.2941,0.3059,0.3332,0.3840,0.4816,0.6691",\ +"0.2629,0.2785,0.2902,0.3176,0.3684,0.4660,0.6535",\ +"0.2316,0.2473,0.2590,0.2863,0.3410,0.4348,0.6262",\ +"0.1848,0.2004,0.2121,0.2395,0.2902,0.3879,0.5754",\ +"0.0832,0.0988,0.1105,0.1379,0.1809,0.2746,0.4699",\ +"-0.1121,-0.0965,-0.0848,-0.0535,-0.0066,0.0910,0.2824"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2473,0.2316,0.2160,0.1887,0.1379,0.0363,-0.1629",\ +"0.2629,0.2473,0.2316,0.2043,0.1535,0.0520,-0.1473",\ +"0.2785,0.2590,0.2434,0.2160,0.1652,0.0676,-0.1355",\ +"0.3098,0.2941,0.2785,0.2473,0.1965,0.0910,-0.1043",\ +"0.3527,0.3371,0.3215,0.2941,0.2434,0.1418,-0.0574",\ +"0.4582,0.4426,0.4270,0.3957,0.3488,0.2434,0.0480",\ +"0.6535,0.6379,0.6184,0.5910,0.5402,0.4426,0.2434"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2395,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2668,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2395,0.1887,0.0910,-0.0965",\ +"0.3449,0.3293,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4191,0.3879,0.3371,0.2395,0.0559",\ +"0.6457,0.6301,0.6145,0.5871,0.5324,0.4309,0.2512"); + } + } + } +pin(A_REN) { + direction : input ; + capacitance : 0.00381634 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0054); + } + fall_power("scalar"){ + values (0.0036); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0053); + } + fall_power("scalar"){ + values (0.0036); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.0301,-0.0145,0.0012,0.0324,0.0793,0.1809,0.3762",\ +"-0.0457,-0.0301,-0.0145,0.0168,0.0637,0.1613,0.3605",\ +"-0.0574,-0.0418,-0.0262,0.0051,0.0520,0.1496,0.3449",\ +"-0.0926,-0.0730,-0.0574,-0.0262,0.0207,0.1184,0.3137",\ +"-0.1395,-0.1238,-0.1082,-0.0770,-0.0301,0.0715,0.2707",\ +"-0.2410,-0.2254,-0.2098,-0.1746,-0.1355,-0.0340,0.1652",\ +"-0.4402,-0.4207,-0.4051,-0.3738,-0.3270,-0.2293,-0.0340"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.0988,0.1145,0.1262,0.1535,0.2043,0.3020,0.4855",\ +"0.0832,0.0988,0.1105,0.1418,0.1848,0.2824,0.4738",\ +"0.0676,0.0832,0.0949,0.1262,0.1730,0.2668,0.4621",\ +"0.0402,0.0559,0.0676,0.0988,0.1457,0.2434,0.4191",\ +"-0.0105,0.0012,0.0168,0.0480,0.0988,0.1965,0.3840",\ +"-0.1160,-0.0965,-0.0848,-0.0535,-0.0066,0.0988,0.2824",\ +"-0.3113,-0.2957,-0.2801,-0.2527,-0.2059,-0.1043,0.0832"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2707,0.2551,0.2395,0.2121,0.1613,0.0598,-0.1395",\ +"0.2863,0.2707,0.2551,0.2238,0.1730,0.0715,-0.1238",\ +"0.2980,0.2824,0.2668,0.2395,0.1887,0.0871,-0.1121",\ +"0.3332,0.3176,0.3020,0.2707,0.2199,0.1184,-0.0809",\ +"0.3762,0.3605,0.3449,0.3176,0.2668,0.1613,-0.0340",\ +"0.4816,0.4621,0.4504,0.4191,0.3723,0.2629,0.0715",\ +"0.6770,0.6613,0.6418,0.6184,0.5637,0.4699,0.2629"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2590,0.2434,0.2316,0.2004,0.1457,0.0520,-0.1355",\ +"0.2746,0.2590,0.2434,0.2160,0.1613,0.0676,-0.1199",\ +"0.2863,0.2707,0.2590,0.2277,0.1730,0.0832,-0.1082",\ +"0.3215,0.3059,0.2902,0.2590,0.2082,0.1105,-0.0770",\ +"0.3645,0.3488,0.3332,0.3059,0.2551,0.1535,-0.0340",\ +"0.4699,0.4543,0.4387,0.4074,0.3605,0.2551,0.0715",\ +"0.6652,0.6496,0.6340,0.6027,0.5520,0.4621,0.2707"); + } + } + } +pin(A_MEN) { + direction : input ; + capacitance : 0.00309605 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0457); + } + fall_power("scalar"){ + values (0.0060); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2668,0.3098,0.4152,0.6066",\ +"0.1887,0.2043,0.2199,0.2512,0.2941,0.3996,0.5949",\ +"0.1730,0.1887,0.2043,0.2355,0.2824,0.3840,0.5793",\ +"0.1418,0.1574,0.1730,0.2043,0.2512,0.3566,0.5480",\ +"0.0949,0.1105,0.1262,0.1574,0.2043,0.3020,0.5051",\ +"-0.0066,0.0090,0.0246,0.0520,0.0988,0.2043,0.3996",\ +"-0.2020,-0.1863,-0.1746,-0.1434,-0.0965,0.0090,0.2082"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2980,0.3137,0.3254,0.3527,0.4035,0.5012,0.6887",\ +"0.2824,0.2980,0.3098,0.3371,0.3879,0.4855,0.6730",\ +"0.2668,0.2824,0.2941,0.3215,0.3723,0.4699,0.6574",\ +"0.2355,0.2473,0.2629,0.2902,0.3410,0.4387,0.6262",\ +"0.1887,0.2004,0.2160,0.2395,0.2941,0.3918,0.5793",\ +"0.0871,0.1027,0.1145,0.1418,0.1848,0.2746,0.4816",\ +"-0.1082,-0.0965,-0.0809,-0.0496,-0.0027,0.0949,0.2863"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2512,0.2355,0.2199,0.1926,0.1418,0.0402,-0.1590",\ +"0.2668,0.2512,0.2355,0.2082,0.1574,0.0559,-0.1434",\ +"0.2824,0.2629,0.2512,0.2199,0.1691,0.0715,-0.1316",\ +"0.3137,0.2980,0.2824,0.2512,0.2004,0.0988,-0.0965",\ +"0.3566,0.3410,0.3254,0.2980,0.2473,0.1418,-0.0535",\ +"0.4621,0.4426,0.4309,0.3996,0.3527,0.2473,0.0520",\ +"0.6574,0.6418,0.6262,0.5949,0.5441,0.4465,0.2473"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2434,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2707,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2434,0.1926,0.0910,-0.0965",\ +"0.3449,0.3332,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4230,0.3918,0.3410,0.2434,0.0559",\ +"0.6457,0.6301,0.6145,0.5910,0.5324,0.4387,0.2512"); + } + } + } +bus(A_BM) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00293842 ; + max_transition : "0.476" ; + pin(A_BM[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0486); + } + fall_power("scalar"){ + values (0.0390); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0482); + } + fall_power("scalar"){ + values (0.0381); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3928,-0.3771,-0.3635,-0.3312,-0.2844,-0.1799,0.0115",\ +"-0.3978,-0.3821,-0.3685,-0.3362,-0.2894,-0.1849,0.0065",\ +"-0.4022,-0.3866,-0.3729,-0.3407,-0.2939,-0.1894,0.0020",\ +"-0.4120,-0.3964,-0.3827,-0.3505,-0.3036,-0.1991,-0.0077",\ +"-0.4186,-0.4029,-0.3893,-0.3570,-0.3102,-0.2057,-0.0143",\ +"-0.4495,-0.4339,-0.4203,-0.3880,-0.3411,-0.2367,-0.0453",\ +"-0.5056,-0.4899,-0.4762,-0.4440,-0.3971,-0.2927,-0.1012"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3547,-0.3400,-0.3264,-0.2980,-0.2473,-0.1496,0.0330",\ +"-0.3597,-0.3450,-0.3314,-0.3030,-0.2523,-0.1546,0.0280",\ +"-0.3642,-0.3495,-0.3358,-0.3075,-0.2567,-0.1591,0.0235",\ +"-0.3739,-0.3593,-0.3456,-0.3173,-0.2665,-0.1688,0.0138",\ +"-0.3805,-0.3658,-0.3522,-0.3238,-0.2731,-0.1754,0.0072",\ +"-0.4115,-0.3968,-0.3831,-0.3548,-0.3040,-0.2064,-0.0238",\ +"-0.4675,-0.4528,-0.4391,-0.4108,-0.3600,-0.2624,-0.0798"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5019,0.4853,0.4726,0.4404,0.3925,0.2890,0.0966",\ +"0.5069,0.4903,0.4776,0.4454,0.3975,0.2940,0.1016",\ +"0.5114,0.4948,0.4821,0.4499,0.4020,0.2985,0.1061",\ +"0.5211,0.5046,0.4919,0.4596,0.4118,0.3083,0.1159",\ +"0.5277,0.5111,0.4984,0.4662,0.4183,0.3148,0.1224",\ +"0.5587,0.5421,0.5294,0.4972,0.4493,0.3458,0.1534",\ +"0.6147,0.5981,0.5854,0.5532,0.5053,0.4018,0.2094"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4560,0.4414,0.4277,0.3994,0.3496,0.2568,0.0722",\ +"0.4610,0.4464,0.4327,0.4044,0.3546,0.2618,0.0772",\ +"0.4655,0.4508,0.4372,0.4088,0.3590,0.2663,0.0817",\ +"0.4753,0.4606,0.4469,0.4186,0.3688,0.2760,0.0915",\ +"0.4818,0.4672,0.4535,0.4252,0.3754,0.2826,0.0980",\ +"0.5128,0.4981,0.4845,0.4561,0.4063,0.3136,0.1290",\ +"0.5688,0.5541,0.5405,0.5121,0.4623,0.3696,0.1850"); + } + } +} + pin(A_CLK) { + direction : input; + capacitance : 0.00380014; + max_transition : "0.476"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.0056,0.476"); + values("0.21,0.21"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (1.6932); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (72.4898); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (73.1657); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (58.6440); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (0.3446); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (0.7709); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_DIN) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.0030602 ; + memory_write() { + address : A_ADDR ; + clocked_on : A_CLK; + } + + max_transition : "0.476" ; + pin(A_DIN[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0486); + } + fall_power("scalar"){ + values (0.0390); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0482); + } + fall_power("scalar"){ + values (0.0381); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3928,-0.3771,-0.3635,-0.3312,-0.2844,-0.1799,0.0115",\ +"-0.3978,-0.3821,-0.3685,-0.3362,-0.2894,-0.1849,0.0065",\ +"-0.4022,-0.3866,-0.3729,-0.3407,-0.2939,-0.1894,0.0020",\ +"-0.4120,-0.3964,-0.3827,-0.3505,-0.3036,-0.1991,-0.0077",\ +"-0.4186,-0.4029,-0.3893,-0.3570,-0.3102,-0.2057,-0.0143",\ +"-0.4495,-0.4339,-0.4203,-0.3880,-0.3411,-0.2367,-0.0453",\ +"-0.5056,-0.4899,-0.4762,-0.4440,-0.3971,-0.2927,-0.1012"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3547,-0.3400,-0.3264,-0.2980,-0.2473,-0.1496,0.0330",\ +"-0.3597,-0.3450,-0.3314,-0.3030,-0.2523,-0.1546,0.0280",\ +"-0.3642,-0.3495,-0.3358,-0.3075,-0.2567,-0.1591,0.0235",\ +"-0.3739,-0.3593,-0.3456,-0.3173,-0.2665,-0.1688,0.0138",\ +"-0.3805,-0.3658,-0.3522,-0.3238,-0.2731,-0.1754,0.0072",\ +"-0.4115,-0.3968,-0.3831,-0.3548,-0.3040,-0.2064,-0.0238",\ +"-0.4675,-0.4528,-0.4391,-0.4108,-0.3600,-0.2624,-0.0798"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5019,0.4853,0.4726,0.4404,0.3925,0.2890,0.0966",\ +"0.5069,0.4903,0.4776,0.4454,0.3975,0.2940,0.1016",\ +"0.5114,0.4948,0.4821,0.4499,0.4020,0.2985,0.1061",\ +"0.5211,0.5046,0.4919,0.4596,0.4118,0.3083,0.1159",\ +"0.5277,0.5111,0.4984,0.4662,0.4183,0.3148,0.1224",\ +"0.5587,0.5421,0.5294,0.4972,0.4493,0.3458,0.1534",\ +"0.6147,0.5981,0.5854,0.5532,0.5053,0.4018,0.2094"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4560,0.4414,0.4277,0.3994,0.3496,0.2568,0.0722",\ +"0.4610,0.4464,0.4327,0.4044,0.3546,0.2618,0.0772",\ +"0.4655,0.4508,0.4372,0.4088,0.3590,0.2663,0.0817",\ +"0.4753,0.4606,0.4469,0.4186,0.3688,0.2760,0.0915",\ +"0.4818,0.4672,0.4535,0.4252,0.3754,0.2826,0.0980",\ +"0.5128,0.4981,0.4845,0.4561,0.4063,0.3136,0.1290",\ +"0.5688,0.5541,0.5405,0.5121,0.4623,0.3696,0.1850"); + } + } + } + + pin(A_BIST_EN) { + direction : input ; + capacitance : 0.00401111 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_BIST_ADDR) { + bus_type : A_11_0; + direction : input ; + capacitance : 0.00721489 ; + pin(A_BIST_ADDR[0]) { + capacitance : 0.00593979 ; + } + pin(A_BIST_ADDR[1]) { + capacitance : 0.00483009 ; + } + pin(A_BIST_ADDR[2]) { + capacitance : 0.006215 ; + } + pin(A_BIST_ADDR[3]) { + capacitance : 0.00766726 ; + } + pin(A_BIST_ADDR[4]) { + capacitance : 0.00488951 ; + } + pin(A_BIST_ADDR[5]) { + capacitance : 0.0091523 ; + } + pin(A_BIST_ADDR[6]) { + capacitance : 0.0109212 ; + } + pin(A_BIST_ADDR[7]) { + capacitance : 0.00774122 ; + } + pin(A_BIST_ADDR[8]) { + capacitance : 0.0101403 ; + } + pin(A_BIST_ADDR[9]) { + capacitance : 0.00771605 ; + } + pin(A_BIST_ADDR[10]) { + capacitance : 0.00860549 ; + } + max_transition : "0.476" ; + pin(A_BIST_ADDR[11:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0076); + } + fall_power("scalar"){ + values (0.0017); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0180); + } + fall_power("scalar"){ + values (0.0031); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4168,-0.3973,-0.3855,-0.3543,-0.3074,-0.2020,-0.0027",\ +"-0.4324,-0.4129,-0.4012,-0.3699,-0.3191,-0.2176,-0.0184",\ +"-0.4441,-0.4285,-0.4129,-0.3816,-0.3309,-0.2293,-0.0301",\ +"-0.4793,-0.4598,-0.4441,-0.4129,-0.3660,-0.2645,-0.0652",\ +"-0.5223,-0.5066,-0.4910,-0.4598,-0.4129,-0.3074,-0.1121",\ +"-0.6199,-0.6082,-0.5926,-0.5613,-0.5145,-0.4129,-0.2137",\ +"-0.8191,-0.8074,-0.7840,-0.7566,-0.7098,-0.6082,-0.4051"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3309,-0.3113,-0.2996,-0.2684,-0.2176,-0.1238,0.0637",\ +"-0.3465,-0.3309,-0.3152,-0.2840,-0.2332,-0.1395,0.0480",\ +"-0.3582,-0.3426,-0.3270,-0.2996,-0.2488,-0.1512,0.0324",\ +"-0.3895,-0.3738,-0.3582,-0.3309,-0.2801,-0.1863,0.0051",\ +"-0.4363,-0.4207,-0.4051,-0.3777,-0.3230,-0.2293,-0.0379",\ +"-0.5379,-0.5223,-0.5066,-0.4793,-0.4285,-0.3309,-0.1434",\ +"-0.7332,-0.7176,-0.7020,-0.6746,-0.6238,-0.5262,-0.3387"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5246,0.5051,0.4895,0.4582,0.4113,0.3059,0.1066",\ +"0.5402,0.5207,0.5051,0.4777,0.4270,0.3215,0.1223",\ +"0.5520,0.5324,0.5168,0.4895,0.4387,0.3371,0.1340",\ +"0.5832,0.5676,0.5520,0.5207,0.4738,0.3684,0.1691",\ +"0.6301,0.6105,0.5949,0.5676,0.5168,0.4113,0.2160",\ +"0.7316,0.7121,0.7004,0.6691,0.6223,0.5168,0.3176",\ +"0.9270,0.9230,0.8957,0.8645,0.8137,0.7121,0.5168"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4309,0.4152,0.4035,0.3684,0.3215,0.2277,0.0363",\ +"0.4465,0.4309,0.4152,0.3879,0.3371,0.2395,0.0559",\ +"0.4582,0.4426,0.4309,0.3996,0.3488,0.2551,0.0715",\ +"0.4934,0.4777,0.4621,0.4348,0.3840,0.2863,0.0988",\ +"0.5363,0.5207,0.5051,0.4777,0.4270,0.3332,0.1418",\ +"0.6379,0.6262,0.6105,0.5793,0.5324,0.4348,0.2434",\ +"0.8332,0.8215,0.8059,0.7707,0.7238,0.6301,0.4387"); + } + } +} +pin(A_BIST_WEN) { + direction : input ; + capacitance : 0.00324098 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0038); + } + fall_power("scalar"){ + values (0.0050); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0034); + } + fall_power("scalar"){ + values (0.0050); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2629,0.3059,0.4113,0.6066",\ +"0.1887,0.2043,0.2160,0.2473,0.2941,0.3957,0.5949",\ +"0.1691,0.1848,0.2004,0.2316,0.2785,0.3801,0.5754",\ +"0.1379,0.1574,0.1691,0.2004,0.2473,0.3527,0.5480",\ +"0.0910,0.1066,0.1223,0.1535,0.2004,0.2980,0.4973",\ +"-0.0105,0.0051,0.0207,0.0520,0.0949,0.2004,0.3957",\ +"-0.2059,-0.1902,-0.1746,-0.1473,-0.1004,0.0051,0.2004"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2941,0.3098,0.3215,0.3488,0.4035,0.4973,0.6887",\ +"0.2785,0.2941,0.3059,0.3332,0.3840,0.4816,0.6691",\ +"0.2629,0.2785,0.2902,0.3176,0.3684,0.4660,0.6535",\ +"0.2316,0.2473,0.2590,0.2863,0.3410,0.4348,0.6262",\ +"0.1848,0.2004,0.2121,0.2395,0.2902,0.3879,0.5754",\ +"0.0832,0.0988,0.1105,0.1379,0.1809,0.2746,0.4699",\ +"-0.1121,-0.0965,-0.0848,-0.0535,-0.0066,0.0910,0.2824"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2473,0.2316,0.2160,0.1887,0.1379,0.0363,-0.1629",\ +"0.2629,0.2473,0.2316,0.2043,0.1535,0.0520,-0.1473",\ +"0.2785,0.2590,0.2434,0.2160,0.1652,0.0676,-0.1355",\ +"0.3098,0.2941,0.2785,0.2473,0.1965,0.0910,-0.1043",\ +"0.3527,0.3371,0.3215,0.2941,0.2434,0.1418,-0.0574",\ +"0.4582,0.4426,0.4270,0.3957,0.3488,0.2434,0.0480",\ +"0.6535,0.6379,0.6184,0.5910,0.5402,0.4426,0.2434"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2395,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2668,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2395,0.1887,0.0910,-0.0965",\ +"0.3449,0.3293,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4191,0.3879,0.3371,0.2395,0.0559",\ +"0.6457,0.6301,0.6145,0.5871,0.5324,0.4309,0.2512"); + } + } + } +pin(A_BIST_REN) { + direction : input ; + capacitance : 0.00381634 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0054); + } + fall_power("scalar"){ + values (0.0036); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0053); + } + fall_power("scalar"){ + values (0.0036); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.0301,-0.0145,0.0012,0.0324,0.0793,0.1809,0.3762",\ +"-0.0457,-0.0301,-0.0145,0.0168,0.0637,0.1613,0.3605",\ +"-0.0574,-0.0418,-0.0262,0.0051,0.0520,0.1496,0.3449",\ +"-0.0926,-0.0730,-0.0574,-0.0262,0.0207,0.1184,0.3137",\ +"-0.1395,-0.1238,-0.1082,-0.0770,-0.0301,0.0715,0.2707",\ +"-0.2410,-0.2254,-0.2098,-0.1746,-0.1355,-0.0340,0.1652",\ +"-0.4402,-0.4207,-0.4051,-0.3738,-0.3270,-0.2293,-0.0340"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.0988,0.1145,0.1262,0.1535,0.2043,0.3020,0.4855",\ +"0.0832,0.0988,0.1105,0.1418,0.1848,0.2824,0.4738",\ +"0.0676,0.0832,0.0949,0.1262,0.1730,0.2668,0.4621",\ +"0.0402,0.0559,0.0676,0.0988,0.1457,0.2434,0.4191",\ +"-0.0105,0.0012,0.0168,0.0480,0.0988,0.1965,0.3840",\ +"-0.1160,-0.0965,-0.0848,-0.0535,-0.0066,0.0988,0.2824",\ +"-0.3113,-0.2957,-0.2801,-0.2527,-0.2059,-0.1043,0.0832"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2707,0.2551,0.2395,0.2121,0.1613,0.0598,-0.1395",\ +"0.2863,0.2707,0.2551,0.2238,0.1730,0.0715,-0.1238",\ +"0.2980,0.2824,0.2668,0.2395,0.1887,0.0871,-0.1121",\ +"0.3332,0.3176,0.3020,0.2707,0.2199,0.1184,-0.0809",\ +"0.3762,0.3605,0.3449,0.3176,0.2668,0.1613,-0.0340",\ +"0.4816,0.4621,0.4504,0.4191,0.3723,0.2629,0.0715",\ +"0.6770,0.6613,0.6418,0.6184,0.5637,0.4699,0.2629"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2590,0.2434,0.2316,0.2004,0.1457,0.0520,-0.1355",\ +"0.2746,0.2590,0.2434,0.2160,0.1613,0.0676,-0.1199",\ +"0.2863,0.2707,0.2590,0.2277,0.1730,0.0832,-0.1082",\ +"0.3215,0.3059,0.2902,0.2590,0.2082,0.1105,-0.0770",\ +"0.3645,0.3488,0.3332,0.3059,0.2551,0.1535,-0.0340",\ +"0.4699,0.4543,0.4387,0.4074,0.3605,0.2551,0.0715",\ +"0.6652,0.6496,0.6340,0.6027,0.5520,0.4621,0.2707"); + } + } + } +pin(A_BIST_MEN) { + direction : input ; + capacitance : 0.00309605 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0457); + } + fall_power("scalar"){ + values (0.0060); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2668,0.3098,0.4152,0.6066",\ +"0.1887,0.2043,0.2199,0.2512,0.2941,0.3996,0.5949",\ +"0.1730,0.1887,0.2043,0.2355,0.2824,0.3840,0.5793",\ +"0.1418,0.1574,0.1730,0.2043,0.2512,0.3566,0.5480",\ +"0.0949,0.1105,0.1262,0.1574,0.2043,0.3020,0.5051",\ +"-0.0066,0.0090,0.0246,0.0520,0.0988,0.2043,0.3996",\ +"-0.2020,-0.1863,-0.1746,-0.1434,-0.0965,0.0090,0.2082"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2980,0.3137,0.3254,0.3527,0.4035,0.5012,0.6887",\ +"0.2824,0.2980,0.3098,0.3371,0.3879,0.4855,0.6730",\ +"0.2668,0.2824,0.2941,0.3215,0.3723,0.4699,0.6574",\ +"0.2355,0.2473,0.2629,0.2902,0.3410,0.4387,0.6262",\ +"0.1887,0.2004,0.2160,0.2395,0.2941,0.3918,0.5793",\ +"0.0871,0.1027,0.1145,0.1418,0.1848,0.2746,0.4816",\ +"-0.1082,-0.0965,-0.0809,-0.0496,-0.0027,0.0949,0.2863"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2512,0.2355,0.2199,0.1926,0.1418,0.0402,-0.1590",\ +"0.2668,0.2512,0.2355,0.2082,0.1574,0.0559,-0.1434",\ +"0.2824,0.2629,0.2512,0.2199,0.1691,0.0715,-0.1316",\ +"0.3137,0.2980,0.2824,0.2512,0.2004,0.0988,-0.0965",\ +"0.3566,0.3410,0.3254,0.2980,0.2473,0.1418,-0.0535",\ +"0.4621,0.4426,0.4309,0.3996,0.3527,0.2473,0.0520",\ +"0.6574,0.6418,0.6262,0.5949,0.5441,0.4465,0.2473"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2434,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2707,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2434,0.1926,0.0910,-0.0965",\ +"0.3449,0.3332,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4230,0.3918,0.3410,0.2434,0.0559",\ +"0.6457,0.6301,0.6145,0.5910,0.5324,0.4387,0.2512"); + } + } + } +bus(A_BIST_BM) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00236845 ; + max_transition : "0.476" ; + pin(A_BIST_BM[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0486); + } + fall_power("scalar"){ + values (0.0390); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0482); + } + fall_power("scalar"){ + values (0.0381); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3928,-0.3771,-0.3635,-0.3312,-0.2844,-0.1799,0.0115",\ +"-0.3978,-0.3821,-0.3685,-0.3362,-0.2894,-0.1849,0.0065",\ +"-0.4022,-0.3866,-0.3729,-0.3407,-0.2939,-0.1894,0.0020",\ +"-0.4120,-0.3964,-0.3827,-0.3505,-0.3036,-0.1991,-0.0077",\ +"-0.4186,-0.4029,-0.3893,-0.3570,-0.3102,-0.2057,-0.0143",\ +"-0.4495,-0.4339,-0.4203,-0.3880,-0.3411,-0.2367,-0.0453",\ +"-0.5056,-0.4899,-0.4762,-0.4440,-0.3971,-0.2927,-0.1012"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3547,-0.3400,-0.3264,-0.2980,-0.2473,-0.1496,0.0330",\ +"-0.3597,-0.3450,-0.3314,-0.3030,-0.2523,-0.1546,0.0280",\ +"-0.3642,-0.3495,-0.3358,-0.3075,-0.2567,-0.1591,0.0235",\ +"-0.3739,-0.3593,-0.3456,-0.3173,-0.2665,-0.1688,0.0138",\ +"-0.3805,-0.3658,-0.3522,-0.3238,-0.2731,-0.1754,0.0072",\ +"-0.4115,-0.3968,-0.3831,-0.3548,-0.3040,-0.2064,-0.0238",\ +"-0.4675,-0.4528,-0.4391,-0.4108,-0.3600,-0.2624,-0.0798"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5019,0.4853,0.4726,0.4404,0.3925,0.2890,0.0966",\ +"0.5069,0.4903,0.4776,0.4454,0.3975,0.2940,0.1016",\ +"0.5114,0.4948,0.4821,0.4499,0.4020,0.2985,0.1061",\ +"0.5211,0.5046,0.4919,0.4596,0.4118,0.3083,0.1159",\ +"0.5277,0.5111,0.4984,0.4662,0.4183,0.3148,0.1224",\ +"0.5587,0.5421,0.5294,0.4972,0.4493,0.3458,0.1534",\ +"0.6147,0.5981,0.5854,0.5532,0.5053,0.4018,0.2094"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4560,0.4414,0.4277,0.3994,0.3496,0.2568,0.0722",\ +"0.4610,0.4464,0.4327,0.4044,0.3546,0.2618,0.0772",\ +"0.4655,0.4508,0.4372,0.4088,0.3590,0.2663,0.0817",\ +"0.4753,0.4606,0.4469,0.4186,0.3688,0.2760,0.0915",\ +"0.4818,0.4672,0.4535,0.4252,0.3754,0.2826,0.0980",\ +"0.5128,0.4981,0.4845,0.4561,0.4063,0.3136,0.1290",\ +"0.5688,0.5541,0.5405,0.5121,0.4623,0.3696,0.1850"); + } + } +} + pin(A_BIST_CLK) { + direction : input; + capacitance : 0.00380014; + max_transition : "0.476"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.0056,0.476"); + values("0.21,0.21"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (1.6932); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (72.4898); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (73.1657); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (58.6440); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.3446); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.7709); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_BIST_DIN) { + bus_type : D_15_0; + direction : input ; + capacitance : 0.00232602 ; + memory_write() { + address : A_BIST_ADDR ; + clocked_on : A_BIST_CLK; + } + + max_transition : "0.476" ; + pin(A_BIST_DIN[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0486); + } + fall_power("scalar"){ + values (0.0390); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0482); + } + fall_power("scalar"){ + values (0.0381); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3928,-0.3771,-0.3635,-0.3312,-0.2844,-0.1799,0.0115",\ +"-0.3978,-0.3821,-0.3685,-0.3362,-0.2894,-0.1849,0.0065",\ +"-0.4022,-0.3866,-0.3729,-0.3407,-0.2939,-0.1894,0.0020",\ +"-0.4120,-0.3964,-0.3827,-0.3505,-0.3036,-0.1991,-0.0077",\ +"-0.4186,-0.4029,-0.3893,-0.3570,-0.3102,-0.2057,-0.0143",\ +"-0.4495,-0.4339,-0.4203,-0.3880,-0.3411,-0.2367,-0.0453",\ +"-0.5056,-0.4899,-0.4762,-0.4440,-0.3971,-0.2927,-0.1012"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3547,-0.3400,-0.3264,-0.2980,-0.2473,-0.1496,0.0330",\ +"-0.3597,-0.3450,-0.3314,-0.3030,-0.2523,-0.1546,0.0280",\ +"-0.3642,-0.3495,-0.3358,-0.3075,-0.2567,-0.1591,0.0235",\ +"-0.3739,-0.3593,-0.3456,-0.3173,-0.2665,-0.1688,0.0138",\ +"-0.3805,-0.3658,-0.3522,-0.3238,-0.2731,-0.1754,0.0072",\ +"-0.4115,-0.3968,-0.3831,-0.3548,-0.3040,-0.2064,-0.0238",\ +"-0.4675,-0.4528,-0.4391,-0.4108,-0.3600,-0.2624,-0.0798"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5019,0.4853,0.4726,0.4404,0.3925,0.2890,0.0966",\ +"0.5069,0.4903,0.4776,0.4454,0.3975,0.2940,0.1016",\ +"0.5114,0.4948,0.4821,0.4499,0.4020,0.2985,0.1061",\ +"0.5211,0.5046,0.4919,0.4596,0.4118,0.3083,0.1159",\ +"0.5277,0.5111,0.4984,0.4662,0.4183,0.3148,0.1224",\ +"0.5587,0.5421,0.5294,0.4972,0.4493,0.3458,0.1534",\ +"0.6147,0.5981,0.5854,0.5532,0.5053,0.4018,0.2094"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4560,0.4414,0.4277,0.3994,0.3496,0.2568,0.0722",\ +"0.4610,0.4464,0.4327,0.4044,0.3546,0.2618,0.0772",\ +"0.4655,0.4508,0.4372,0.4088,0.3590,0.2663,0.0817",\ +"0.4753,0.4606,0.4469,0.4186,0.3688,0.2760,0.0915",\ +"0.4818,0.4672,0.4535,0.4252,0.3754,0.2826,0.0980",\ +"0.5128,0.4981,0.4845,0.4561,0.4063,0.3136,0.1290",\ +"0.5688,0.5541,0.5405,0.5121,0.4623,0.3696,0.1850"); + } + } + } + +bus(A_DOUT) { + + bus_type : D_15_0; + direction : output ; + capacitance : 0 ; + max_capacitance : "6.4e-14" ; + memory_read() { + address : A_ADDR ; + } + pin(A_DOUT[15:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "A_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("5.3293,5.3309,5.3386,5.3473,5.3797,5.4156",\ +"5.3405,5.3421,5.3498,5.3585,5.3909,5.4268",\ +"5.3392,5.3408,5.3484,5.3571,5.3896,5.4254",\ +"5.3522,5.3538,5.3615,5.3702,5.4026,5.4385",\ +"5.3600,5.3616,5.3693,5.3780,5.4104,5.4463",\ +"5.3926,5.3942,5.4018,5.4105,5.4430,5.4788",\ +"5.4465,5.4481,5.4558,5.4645,5.4969,5.5328"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("5.2683,5.2696,5.2756,5.2827,5.3092,5.3359",\ +"5.2794,5.2808,5.2868,5.2939,5.3204,5.3471",\ +"5.2781,5.2794,5.2854,5.2926,5.3191,5.3457",\ +"5.2912,5.2925,5.2985,5.3056,5.3321,5.3588",\ +"5.2989,5.3002,5.3062,5.3134,5.3399,5.3665",\ +"5.3315,5.3328,5.3388,5.3460,5.3725,5.3991",\ +"5.3854,5.3868,5.3928,5.3999,5.4264,5.4530"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0326,0.0341,0.0428,0.0518,0.0923,0.1492"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0254,0.0265,0.0335,0.0402,0.0707,0.1039"); + } + } +} +cell_leakage_power : 792.0620; +} +} diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_4096x8_c3_bm_bist_fast_1p32V_m55C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_4096x8_c3_bm_bist_fast_1p32V_m55C.lib new file mode 100644 index 0000000000..4aff53a01f --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_4096x8_c3_bm_bist_fast_1p32V_m55C.lib @@ -0,0 +1,1537 @@ +/* ------------------------------------------------------*/ +/**/ +/* Copyright 2024 IHP PDK Authors*/ +/**/ +/* Licensed under the Apache License, Version 2.0 (the "License");*/ +/* you may not use this file except in compliance with the License.*/ +/* You may obtain a copy of the License at*/ +/* */ +/* https://www.apache.org/licenses/LICENSE-2.0*/ +/* */ +/* Unless required by applicable law or agreed to in writing, software*/ +/* distributed under the License is distributed on an "AS IS" BASIS,*/ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/ +/* See the License for the specific language governing permissions and*/ +/* limitations under the License.*/ +/* */ +/* Generated on Fri Jul 19 08:59:21 2024 */ +/* */ +/* ------------------------------------------------------ */ +library(RM_IHPSG13_1P_4096x8_c3_bm_bist_fast_1p32V_m55C) { + technology (cmos) ; + delay_model : table_lookup ; + define ("add_pg_pin_to_lib", "library", "boolean"); + add_pg_pin_to_lib : true; + voltage_map ( VDD, 1.32); + voltage_map ( VDDARRAY, 1.32); + voltage_map ( VSS, 0.000000 ); + + date : "Fri Jul 19 08:59:19 2024" ; + comment : "IHP Microelectronics GmbH, 2024" ; + revision : 1.0.0 ; + simulation : true ; + nom_process : 1 ; + nom_temperature : -55 ; + nom_voltage : 1.32 ; + + operating_conditions("fast_1p32V_m55C"){ + process : 1 ; + temperature : -55 ; + voltage : 1.32 ; + tree_type : "balanced_tree" ; + } + + default_operating_conditions : fast_1p32V_m55C ; + default_max_transition : 1.0 ; + default_fanout_load : 1.0 ; + default_inout_pin_cap : 0.0 ; + default_input_pin_cap : 0.0 ; + default_output_pin_cap : 0.0 ; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + + slew_lower_threshold_pct_rise : 30 ; + slew_upper_threshold_pct_rise : 70 ; + input_threshold_pct_fall : 50 ; + output_threshold_pct_fall : 50 ; + input_threshold_pct_rise : 50 ; + output_threshold_pct_rise : 50 ; + slew_lower_threshold_pct_fall : 30 ; + slew_upper_threshold_pct_fall : 70 ; + slew_derate_from_library : 0.5; + k_volt_cell_leakage_power : 0.0 ; + k_temp_cell_leakage_power : 0.0 ; + k_process_cell_leakage_power : 0.0 ; + k_volt_internal_power : 0.0 ; + k_temp_internal_power : 0.0 ; + k_process_internal_power : 0.0 ; + + capacitive_load_unit (1,pf) ; + voltage_unit : "1V" ; + current_unit : "1uA" ; + time_unit : "1ns" ; + leakage_power_unit : "1nW" ; + pulling_resistance_unit : "1kohm"; + /* + ------------------------------------------------------------------------------------------ + implicit units overview: + cell_area unit : "um" + internal_power unit : "1e-12 * J/toggle = 1 * uW/MHz" + (capacitive_load_unit * voltage_unit^2) per toggle event + ------------------------------------------------------------------------------------------ + */ + library_features(report_delay_calculation); + define_cell_area (pad_drivers,pad_driver_sites) ; + + lu_table_template(CLKTRAN_constraint_template) { + variable_1 : constrained_pin_transition; + index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" ); + } + lu_table_template(SRAM_load_template) { + variable_1 : total_output_net_capacitance; + index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + lu_table_template(SIG2SRAM_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" ); + index_2 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" ); + } + + lu_table_template(SIG2SRAM_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" ); + index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + + type (D_7_0) { + base_type : array; + data_type : bit; + bit_width : 8; + bit_from : 7; + bit_to : 0; + downto : true; + } + + type (A_11_0) { + base_type : array; + data_type : bit; + bit_width : 12; + bit_from : 11; + bit_to : 0; + downto : true; + } + +cell(RM_IHPSG13_1P_4096x8_c3_bm_bist) { +pg_pin (VDD) { + pg_type : primary_power; + voltage_name : VDD; +} +pg_pin (VDDARRAY) { + pg_type : primary_power; + voltage_name : VDDARRAY; +} +pg_pin (VSS) { + pg_type : primary_ground; + voltage_name : VSS; +} + +memory() { + type : ram; + address_width : 12; + word_width : 8; +} + +interface_timing : false; +bus_naming_style : "%s[%d]" ; +area : 146413.44 ; + + pin(A_DLY) { + direction : input ; + capacitance : 0.00421562 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_ADDR) { + bus_type : A_11_0; + direction : input ; + capacitance : 0.00691085 ; + pin(A_ADDR[0]) { + capacitance : 0.00562034 ; + } + pin(A_ADDR[1]) { + capacitance : 0.00462655 ; + } + pin(A_ADDR[2]) { + capacitance : 0.00594295 ; + } + pin(A_ADDR[3]) { + capacitance : 0.00723434 ; + } + pin(A_ADDR[4]) { + capacitance : 0.00481603 ; + } + pin(A_ADDR[5]) { + capacitance : 0.00868123 ; + } + pin(A_ADDR[6]) { + capacitance : 0.010187 ; + } + pin(A_ADDR[7]) { + capacitance : 0.00734489 ; + } + pin(A_ADDR[8]) { + capacitance : 0.00904175 ; + } + pin(A_ADDR[9]) { + capacitance : 0.0074973 ; + } + pin(A_ADDR[10]) { + capacitance : 0.00825659 ; + } + max_transition : "0.38" ; + pin(A_ADDR[11:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0093); + } + fall_power("scalar"){ + values (0.0011); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0215); + } + fall_power("scalar"){ + values (0.0018); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2371,-0.2215,-0.2098,-0.1824,-0.1434,-0.0691,0.0676",\ +"-0.2449,-0.2332,-0.2176,-0.1902,-0.1551,-0.0770,0.0559",\ +"-0.2605,-0.2488,-0.2332,-0.2059,-0.1707,-0.0965,0.0441",\ +"-0.2879,-0.2723,-0.2605,-0.2332,-0.1941,-0.1199,0.0168",\ +"-0.3230,-0.3113,-0.2996,-0.2723,-0.2332,-0.1590,-0.0184",\ +"-0.4012,-0.3895,-0.3738,-0.3465,-0.3074,-0.2332,-0.0965",\ +"-0.5379,-0.5262,-0.5105,-0.4832,-0.4480,-0.3699,-0.2332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1785,-0.1707,-0.1551,-0.1277,-0.0887,-0.0184,0.1145",\ +"-0.1902,-0.1785,-0.1629,-0.1355,-0.1004,-0.0262,0.1027",\ +"-0.2059,-0.1941,-0.1785,-0.1512,-0.1160,-0.0418,0.0871",\ +"-0.2293,-0.2176,-0.2059,-0.1785,-0.1434,-0.0691,0.0598",\ +"-0.2684,-0.2566,-0.2449,-0.2176,-0.1824,-0.1082,0.0207",\ +"-0.3465,-0.3348,-0.3191,-0.2918,-0.2566,-0.1824,-0.0535",\ +"-0.4832,-0.4715,-0.4559,-0.4324,-0.3934,-0.3191,-0.1902"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3410,0.3293,0.3137,0.2863,0.2473,0.1730,0.0324",\ +"0.3488,0.3371,0.3215,0.2941,0.2590,0.1809,0.0480",\ +"0.3684,0.3527,0.3371,0.3098,0.2746,0.1965,0.0598",\ +"0.3918,0.3762,0.3645,0.3371,0.2980,0.2238,0.0871",\ +"0.4309,0.4152,0.4035,0.3762,0.3371,0.2629,0.1223",\ +"0.5051,0.4934,0.4777,0.4504,0.4113,0.3371,0.1965",\ +"0.6418,0.6262,0.6145,0.5871,0.5520,0.4738,0.3332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2824,0.2707,0.2551,0.2277,0.1926,0.1184,-0.0105",\ +"0.2902,0.2785,0.2668,0.2395,0.2043,0.1301,0.0012",\ +"0.3059,0.2941,0.2824,0.2551,0.2199,0.1457,0.0168",\ +"0.3332,0.3215,0.3059,0.2785,0.2434,0.1691,0.0402",\ +"0.3723,0.3605,0.3449,0.3176,0.2824,0.2121,0.0793",\ +"0.4465,0.4348,0.4230,0.3918,0.3566,0.2824,0.1535",\ +"0.5832,0.5715,0.5598,0.5324,0.4934,0.4191,0.2902"); + } + } +} +pin(A_WEN) { + direction : input ; + capacitance : 0.00341384 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0072); + } + fall_power("scalar"){ + values (0.0165); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0048); + } + fall_power("scalar"){ + values (0.0225); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1887,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3527",\ +"-0.0262,-0.0145,0.0012,0.0246,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1418"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2160,0.2316,0.2590,0.2941,0.3684,0.5012",\ +"0.1926,0.2043,0.2199,0.2473,0.2824,0.3566,0.4895",\ +"0.1770,0.1887,0.2043,0.2316,0.2668,0.3410,0.4777",\ +"0.1535,0.1652,0.1770,0.2043,0.2395,0.3137,0.4504",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2746,0.4113",\ +"0.0402,0.0520,0.0676,0.0910,0.1262,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0730,-0.0457,-0.0066,0.0637,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1496,0.1223,0.0793,0.0090,-0.1316",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0168,-0.1199",\ +"0.2004,0.1887,0.1770,0.1496,0.1066,0.0363,-0.1043",\ +"0.2277,0.2160,0.2004,0.1730,0.1340,0.0598,-0.0809",\ +"0.2668,0.2551,0.2395,0.2121,0.1730,0.0988,-0.0418",\ +"0.3410,0.3293,0.3137,0.2863,0.2434,0.1730,0.0324",\ +"0.4816,0.4699,0.4543,0.4230,0.3801,0.3098,0.1730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1066,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1457,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1613,0.1340,0.0988,0.0246,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2512,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0457",\ +"0.3254,0.3176,0.3020,0.2746,0.2355,0.1652,0.0324",\ +"0.4660,0.4543,0.4387,0.4113,0.3723,0.3020,0.1691"); + } + } + } +pin(A_REN) { + direction : input ; + capacitance : 0.00390661 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0093); + } + fall_power("scalar"){ + values (0.0121); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0244); + } + fall_power("scalar"){ + values (0.0205); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.0027,0.0090,0.0246,0.0520,0.0910,0.1613,0.3020",\ +"-0.0105,0.0012,0.0129,0.0363,0.0793,0.1535,0.2902",\ +"-0.0262,-0.0145,-0.0027,0.0246,0.0637,0.1379,0.2785",\ +"-0.0535,-0.0418,-0.0262,0.0012,0.0363,0.1105,0.2512",\ +"-0.0926,-0.0809,-0.0652,-0.0418,-0.0027,0.0715,0.2121",\ +"-0.1668,-0.1551,-0.1395,-0.1082,-0.0770,-0.0027,0.1379",\ +"-0.3035,-0.2918,-0.2762,-0.2488,-0.2137,-0.1434,-0.0027"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.0832,0.0949,0.1105,0.1379,0.1730,0.2473,0.3801",\ +"0.0754,0.0832,0.0988,0.1223,0.1613,0.2355,0.3684",\ +"0.0598,0.0676,0.0832,0.1066,0.1457,0.2121,0.3527",\ +"0.0324,0.0441,0.0598,0.0871,0.1223,0.1926,0.3293",\ +"-0.0066,0.0051,0.0168,0.0480,0.0832,0.1535,0.2902",\ +"-0.0809,-0.0691,-0.0574,-0.0301,0.0090,0.0832,0.2121",\ +"-0.2176,-0.2059,-0.1941,-0.1668,-0.1277,-0.0574,0.0793"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1160",\ +"0.1965,0.1848,0.1730,0.1457,0.1027,0.0324,-0.1082",\ +"0.2160,0.2004,0.1887,0.1613,0.1184,0.0480,-0.0926",\ +"0.2395,0.2277,0.2121,0.1848,0.1457,0.0715,-0.0652",\ +"0.2785,0.2668,0.2512,0.2238,0.1848,0.1105,-0.0262",\ +"0.3527,0.3410,0.3254,0.2980,0.2551,0.1848,0.0480",\ +"0.4934,0.4816,0.4660,0.4387,0.3957,0.3254,0.1887"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1730,0.1613,0.1496,0.1184,0.0793,0.0129,-0.1238",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0207,-0.1121",\ +"0.2004,0.1887,0.1730,0.1457,0.1066,0.0363,-0.1004",\ +"0.2238,0.2121,0.2004,0.1691,0.1340,0.0598,-0.0730",\ +"0.2629,0.2512,0.2395,0.2121,0.1691,0.0988,-0.0340",\ +"0.3371,0.3254,0.3137,0.2863,0.2434,0.1730,0.0402",\ +"0.4777,0.4660,0.4504,0.4230,0.3840,0.3137,0.1809"); + } + } + } +pin(A_MEN) { + direction : input ; + capacitance : 0.00326046 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0754); + } + fall_power("scalar"){ + values (0.0123); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1926,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1418,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3488",\ +"-0.0262,-0.0145,0.0012,0.0285,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1379"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2199,0.2316,0.2590,0.2980,0.3723,0.5051",\ +"0.1965,0.2082,0.2199,0.2473,0.2863,0.3605,0.4934",\ +"0.1809,0.1926,0.2043,0.2316,0.2707,0.3449,0.4777",\ +"0.1574,0.1691,0.1809,0.2082,0.2434,0.3176,0.4543",\ +"0.1145,0.1262,0.1418,0.1691,0.2043,0.2785,0.4113",\ +"0.0441,0.0559,0.0676,0.0949,0.1301,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0691,-0.0418,-0.0066,0.0676,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1535,0.1262,0.0832,0.0129,-0.1277",\ +"0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1199",\ +"0.2043,0.1926,0.1770,0.1496,0.1105,0.0363,-0.1043",\ +"0.2277,0.2160,0.2043,0.1770,0.1379,0.0598,-0.0770",\ +"0.2668,0.2551,0.2434,0.2160,0.1730,0.0988,-0.0379",\ +"0.3449,0.3332,0.3176,0.2902,0.2473,0.1730,0.0363",\ +"0.4816,0.4699,0.4543,0.4270,0.3840,0.3098,0.1770"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1105,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1496,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1652,0.1340,0.0988,0.0285,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2551,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0418",\ +"0.3293,0.3176,0.3020,0.2746,0.2395,0.1652,0.0324",\ +"0.4660,0.4543,0.4426,0.4113,0.3762,0.3020,0.1691"); + } + } + } +bus(A_BM) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00318267 ; + max_transition : "0.38" ; + pin(A_BM[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0378); + } + fall_power("scalar"){ + values (0.0440); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0522); + } + fall_power("scalar"){ + values (0.0514); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1741,-0.1633,-0.1477,-0.1223,-0.0813,-0.0080,0.1267",\ +"-0.1779,-0.1672,-0.1516,-0.1262,-0.0852,-0.0119,0.1228",\ +"-0.1818,-0.1711,-0.1555,-0.1301,-0.0891,-0.0158,0.1189",\ +"-0.1850,-0.1742,-0.1586,-0.1332,-0.0922,-0.0190,0.1158",\ +"-0.1974,-0.1867,-0.1711,-0.1457,-0.1047,-0.0314,0.1033",\ +"-0.2149,-0.2041,-0.1885,-0.1631,-0.1221,-0.0489,0.0859",\ +"-0.2425,-0.2318,-0.2162,-0.1908,-0.1498,-0.0765,0.0582"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1506,-0.1389,-0.1262,-0.0989,-0.0617,0.0115,0.1394",\ +"-0.1545,-0.1428,-0.1301,-0.1027,-0.0656,0.0076,0.1355",\ +"-0.1584,-0.1467,-0.1340,-0.1067,-0.0695,0.0037,0.1316",\ +"-0.1615,-0.1498,-0.1371,-0.1098,-0.0727,0.0006,0.1285",\ +"-0.1740,-0.1623,-0.1496,-0.1222,-0.0851,-0.0119,0.1160",\ +"-0.1915,-0.1797,-0.1670,-0.1397,-0.1026,-0.0293,0.0986",\ +"-0.2191,-0.2074,-0.1947,-0.1673,-0.1302,-0.0570,0.0709"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2790,0.2693,0.2536,0.2273,0.1902,0.1160,-0.0188",\ +"0.2829,0.2732,0.2575,0.2312,0.1941,0.1198,-0.0149",\ +"0.2868,0.2771,0.2614,0.2351,0.1980,0.1237,-0.0110",\ +"0.2900,0.2802,0.2646,0.2382,0.2011,0.1269,-0.0079",\ +"0.3024,0.2926,0.2770,0.2507,0.2135,0.1393,0.0046",\ +"0.3199,0.3101,0.2945,0.2681,0.2310,0.1568,0.0220",\ +"0.3475,0.3378,0.3221,0.2958,0.2587,0.1845,0.0497"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2507,0.2400,0.2263,0.1990,0.1628,0.0906,-0.0393",\ +"0.2546,0.2439,0.2302,0.2028,0.1667,0.0944,-0.0354",\ +"0.2585,0.2478,0.2341,0.2068,0.1706,0.0984,-0.0315",\ +"0.2617,0.2509,0.2372,0.2099,0.1738,0.1015,-0.0284",\ +"0.2741,0.2633,0.2497,0.2223,0.1862,0.1139,-0.0159",\ +"0.2916,0.2808,0.2671,0.2398,0.2037,0.1314,0.0015",\ +"0.3192,0.3085,0.2948,0.2675,0.2313,0.1591,0.0292"); + } + } +} + pin(A_CLK) { + direction : input; + capacitance : 0.00389386; + max_transition : "0.38"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.004,0.38"); + values("0.12,0.12"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (0.8242); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (53.0853); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (50.8144); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (42.3390); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (0.4507); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (0.7118); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_DIN) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00332733 ; + memory_write() { + address : A_ADDR ; + clocked_on : A_CLK; + } + + max_transition : "0.38" ; + pin(A_DIN[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0378); + } + fall_power("scalar"){ + values (0.0440); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0522); + } + fall_power("scalar"){ + values (0.0514); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1741,-0.1633,-0.1477,-0.1223,-0.0813,-0.0080,0.1267",\ +"-0.1779,-0.1672,-0.1516,-0.1262,-0.0852,-0.0119,0.1228",\ +"-0.1818,-0.1711,-0.1555,-0.1301,-0.0891,-0.0158,0.1189",\ +"-0.1850,-0.1742,-0.1586,-0.1332,-0.0922,-0.0190,0.1158",\ +"-0.1974,-0.1867,-0.1711,-0.1457,-0.1047,-0.0314,0.1033",\ +"-0.2149,-0.2041,-0.1885,-0.1631,-0.1221,-0.0489,0.0859",\ +"-0.2425,-0.2318,-0.2162,-0.1908,-0.1498,-0.0765,0.0582"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1506,-0.1389,-0.1262,-0.0989,-0.0617,0.0115,0.1394",\ +"-0.1545,-0.1428,-0.1301,-0.1027,-0.0656,0.0076,0.1355",\ +"-0.1584,-0.1467,-0.1340,-0.1067,-0.0695,0.0037,0.1316",\ +"-0.1615,-0.1498,-0.1371,-0.1098,-0.0727,0.0006,0.1285",\ +"-0.1740,-0.1623,-0.1496,-0.1222,-0.0851,-0.0119,0.1160",\ +"-0.1915,-0.1797,-0.1670,-0.1397,-0.1026,-0.0293,0.0986",\ +"-0.2191,-0.2074,-0.1947,-0.1673,-0.1302,-0.0570,0.0709"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2790,0.2693,0.2536,0.2273,0.1902,0.1160,-0.0188",\ +"0.2829,0.2732,0.2575,0.2312,0.1941,0.1198,-0.0149",\ +"0.2868,0.2771,0.2614,0.2351,0.1980,0.1237,-0.0110",\ +"0.2900,0.2802,0.2646,0.2382,0.2011,0.1269,-0.0079",\ +"0.3024,0.2926,0.2770,0.2507,0.2135,0.1393,0.0046",\ +"0.3199,0.3101,0.2945,0.2681,0.2310,0.1568,0.0220",\ +"0.3475,0.3378,0.3221,0.2958,0.2587,0.1845,0.0497"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2507,0.2400,0.2263,0.1990,0.1628,0.0906,-0.0393",\ +"0.2546,0.2439,0.2302,0.2028,0.1667,0.0944,-0.0354",\ +"0.2585,0.2478,0.2341,0.2068,0.1706,0.0984,-0.0315",\ +"0.2617,0.2509,0.2372,0.2099,0.1738,0.1015,-0.0284",\ +"0.2741,0.2633,0.2497,0.2223,0.1862,0.1139,-0.0159",\ +"0.2916,0.2808,0.2671,0.2398,0.2037,0.1314,0.0015",\ +"0.3192,0.3085,0.2948,0.2675,0.2313,0.1591,0.0292"); + } + } + } + + pin(A_BIST_EN) { + direction : input ; + capacitance : 0.00421562 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_BIST_ADDR) { + bus_type : A_11_0; + direction : input ; + capacitance : 0.00691085 ; + pin(A_BIST_ADDR[0]) { + capacitance : 0.00562034 ; + } + pin(A_BIST_ADDR[1]) { + capacitance : 0.00462655 ; + } + pin(A_BIST_ADDR[2]) { + capacitance : 0.00594295 ; + } + pin(A_BIST_ADDR[3]) { + capacitance : 0.00723434 ; + } + pin(A_BIST_ADDR[4]) { + capacitance : 0.00481603 ; + } + pin(A_BIST_ADDR[5]) { + capacitance : 0.00868123 ; + } + pin(A_BIST_ADDR[6]) { + capacitance : 0.010187 ; + } + pin(A_BIST_ADDR[7]) { + capacitance : 0.00734489 ; + } + pin(A_BIST_ADDR[8]) { + capacitance : 0.00904175 ; + } + pin(A_BIST_ADDR[9]) { + capacitance : 0.0074973 ; + } + pin(A_BIST_ADDR[10]) { + capacitance : 0.00825659 ; + } + max_transition : "0.38" ; + pin(A_BIST_ADDR[11:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0093); + } + fall_power("scalar"){ + values (0.0011); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0215); + } + fall_power("scalar"){ + values (0.0018); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.2371,-0.2215,-0.2098,-0.1824,-0.1434,-0.0691,0.0676",\ +"-0.2449,-0.2332,-0.2176,-0.1902,-0.1551,-0.0770,0.0559",\ +"-0.2605,-0.2488,-0.2332,-0.2059,-0.1707,-0.0965,0.0441",\ +"-0.2879,-0.2723,-0.2605,-0.2332,-0.1941,-0.1199,0.0168",\ +"-0.3230,-0.3113,-0.2996,-0.2723,-0.2332,-0.1590,-0.0184",\ +"-0.4012,-0.3895,-0.3738,-0.3465,-0.3074,-0.2332,-0.0965",\ +"-0.5379,-0.5262,-0.5105,-0.4832,-0.4480,-0.3699,-0.2332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1785,-0.1707,-0.1551,-0.1277,-0.0887,-0.0184,0.1145",\ +"-0.1902,-0.1785,-0.1629,-0.1355,-0.1004,-0.0262,0.1027",\ +"-0.2059,-0.1941,-0.1785,-0.1512,-0.1160,-0.0418,0.0871",\ +"-0.2293,-0.2176,-0.2059,-0.1785,-0.1434,-0.0691,0.0598",\ +"-0.2684,-0.2566,-0.2449,-0.2176,-0.1824,-0.1082,0.0207",\ +"-0.3465,-0.3348,-0.3191,-0.2918,-0.2566,-0.1824,-0.0535",\ +"-0.4832,-0.4715,-0.4559,-0.4324,-0.3934,-0.3191,-0.1902"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.3410,0.3293,0.3137,0.2863,0.2473,0.1730,0.0324",\ +"0.3488,0.3371,0.3215,0.2941,0.2590,0.1809,0.0480",\ +"0.3684,0.3527,0.3371,0.3098,0.2746,0.1965,0.0598",\ +"0.3918,0.3762,0.3645,0.3371,0.2980,0.2238,0.0871",\ +"0.4309,0.4152,0.4035,0.3762,0.3371,0.2629,0.1223",\ +"0.5051,0.4934,0.4777,0.4504,0.4113,0.3371,0.1965",\ +"0.6418,0.6262,0.6145,0.5871,0.5520,0.4738,0.3332"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2824,0.2707,0.2551,0.2277,0.1926,0.1184,-0.0105",\ +"0.2902,0.2785,0.2668,0.2395,0.2043,0.1301,0.0012",\ +"0.3059,0.2941,0.2824,0.2551,0.2199,0.1457,0.0168",\ +"0.3332,0.3215,0.3059,0.2785,0.2434,0.1691,0.0402",\ +"0.3723,0.3605,0.3449,0.3176,0.2824,0.2121,0.0793",\ +"0.4465,0.4348,0.4230,0.3918,0.3566,0.2824,0.1535",\ +"0.5832,0.5715,0.5598,0.5324,0.4934,0.4191,0.2902"); + } + } +} +pin(A_BIST_WEN) { + direction : input ; + capacitance : 0.00341384 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0072); + } + fall_power("scalar"){ + values (0.0165); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0048); + } + fall_power("scalar"){ + values (0.0225); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1887,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3527",\ +"-0.0262,-0.0145,0.0012,0.0246,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1418"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2160,0.2316,0.2590,0.2941,0.3684,0.5012",\ +"0.1926,0.2043,0.2199,0.2473,0.2824,0.3566,0.4895",\ +"0.1770,0.1887,0.2043,0.2316,0.2668,0.3410,0.4777",\ +"0.1535,0.1652,0.1770,0.2043,0.2395,0.3137,0.4504",\ +"0.1145,0.1262,0.1379,0.1652,0.2043,0.2746,0.4113",\ +"0.0402,0.0520,0.0676,0.0910,0.1262,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0730,-0.0457,-0.0066,0.0637,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1496,0.1223,0.0793,0.0090,-0.1316",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0168,-0.1199",\ +"0.2004,0.1887,0.1770,0.1496,0.1066,0.0363,-0.1043",\ +"0.2277,0.2160,0.2004,0.1730,0.1340,0.0598,-0.0809",\ +"0.2668,0.2551,0.2395,0.2121,0.1730,0.0988,-0.0418",\ +"0.3410,0.3293,0.3137,0.2863,0.2434,0.1730,0.0324",\ +"0.4816,0.4699,0.4543,0.4230,0.3801,0.3098,0.1730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1066,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1457,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1613,0.1340,0.0988,0.0246,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2512,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0457",\ +"0.3254,0.3176,0.3020,0.2746,0.2355,0.1652,0.0324",\ +"0.4660,0.4543,0.4387,0.4113,0.3723,0.3020,0.1691"); + } + } + } +pin(A_BIST_REN) { + direction : input ; + capacitance : 0.00390661 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0093); + } + fall_power("scalar"){ + values (0.0121); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0244); + } + fall_power("scalar"){ + values (0.0205); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.0027,0.0090,0.0246,0.0520,0.0910,0.1613,0.3020",\ +"-0.0105,0.0012,0.0129,0.0363,0.0793,0.1535,0.2902",\ +"-0.0262,-0.0145,-0.0027,0.0246,0.0637,0.1379,0.2785",\ +"-0.0535,-0.0418,-0.0262,0.0012,0.0363,0.1105,0.2512",\ +"-0.0926,-0.0809,-0.0652,-0.0418,-0.0027,0.0715,0.2121",\ +"-0.1668,-0.1551,-0.1395,-0.1082,-0.0770,-0.0027,0.1379",\ +"-0.3035,-0.2918,-0.2762,-0.2488,-0.2137,-0.1434,-0.0027"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.0832,0.0949,0.1105,0.1379,0.1730,0.2473,0.3801",\ +"0.0754,0.0832,0.0988,0.1223,0.1613,0.2355,0.3684",\ +"0.0598,0.0676,0.0832,0.1066,0.1457,0.2121,0.3527",\ +"0.0324,0.0441,0.0598,0.0871,0.1223,0.1926,0.3293",\ +"-0.0066,0.0051,0.0168,0.0480,0.0832,0.1535,0.2902",\ +"-0.0809,-0.0691,-0.0574,-0.0301,0.0090,0.0832,0.2121",\ +"-0.2176,-0.2059,-0.1941,-0.1668,-0.1277,-0.0574,0.0793"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1160",\ +"0.1965,0.1848,0.1730,0.1457,0.1027,0.0324,-0.1082",\ +"0.2160,0.2004,0.1887,0.1613,0.1184,0.0480,-0.0926",\ +"0.2395,0.2277,0.2121,0.1848,0.1457,0.0715,-0.0652",\ +"0.2785,0.2668,0.2512,0.2238,0.1848,0.1105,-0.0262",\ +"0.3527,0.3410,0.3254,0.2980,0.2551,0.1848,0.0480",\ +"0.4934,0.4816,0.4660,0.4387,0.3957,0.3254,0.1887"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1730,0.1613,0.1496,0.1184,0.0793,0.0129,-0.1238",\ +"0.1848,0.1730,0.1574,0.1301,0.0910,0.0207,-0.1121",\ +"0.2004,0.1887,0.1730,0.1457,0.1066,0.0363,-0.1004",\ +"0.2238,0.2121,0.2004,0.1691,0.1340,0.0598,-0.0730",\ +"0.2629,0.2512,0.2395,0.2121,0.1691,0.0988,-0.0340",\ +"0.3371,0.3254,0.3137,0.2863,0.2434,0.1730,0.0402",\ +"0.4777,0.4660,0.4504,0.4230,0.3840,0.3137,0.1809"); + } + } + } +pin(A_BIST_MEN) { + direction : input ; + capacitance : 0.00326046 ; + max_transition : "0.38" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0754); + } + fall_power("scalar"){ + values (0.0123); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1418,0.1496,0.1652,0.1926,0.2316,0.3059,0.4465",\ +"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\ +"0.1145,0.1262,0.1418,0.1652,0.2043,0.2785,0.4191",\ +"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\ +"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3488",\ +"-0.0262,-0.0145,0.0012,0.0285,0.0676,0.1379,0.2785",\ +"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1379"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2082,0.2199,0.2316,0.2590,0.2980,0.3723,0.5051",\ +"0.1965,0.2082,0.2199,0.2473,0.2863,0.3605,0.4934",\ +"0.1809,0.1926,0.2043,0.2316,0.2707,0.3449,0.4777",\ +"0.1574,0.1691,0.1809,0.2082,0.2434,0.3176,0.4543",\ +"0.1145,0.1262,0.1418,0.1691,0.2043,0.2785,0.4113",\ +"0.0441,0.0559,0.0676,0.0949,0.1301,0.2004,0.3332",\ +"-0.0965,-0.0848,-0.0691,-0.0418,-0.0066,0.0676,0.2004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1770,0.1652,0.1535,0.1262,0.0832,0.0129,-0.1277",\ +"0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1199",\ +"0.2043,0.1926,0.1770,0.1496,0.1105,0.0363,-0.1043",\ +"0.2277,0.2160,0.2043,0.1770,0.1379,0.0598,-0.0770",\ +"0.2668,0.2551,0.2434,0.2160,0.1730,0.0988,-0.0379",\ +"0.3449,0.3332,0.3176,0.2902,0.2473,0.1730,0.0363",\ +"0.4816,0.4699,0.4543,0.4270,0.3840,0.3098,0.1770"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.1613,0.1496,0.1379,0.1105,0.0715,0.0012,-0.1355",\ +"0.1730,0.1613,0.1496,0.1184,0.0832,0.0129,-0.1238",\ +"0.1887,0.1770,0.1652,0.1340,0.0988,0.0285,-0.1121",\ +"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\ +"0.2551,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0418",\ +"0.3293,0.3176,0.3020,0.2746,0.2395,0.1652,0.0324",\ +"0.4660,0.4543,0.4426,0.4113,0.3762,0.3020,0.1691"); + } + } + } +bus(A_BIST_BM) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00252172 ; + max_transition : "0.38" ; + pin(A_BIST_BM[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0378); + } + fall_power("scalar"){ + values (0.0440); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0522); + } + fall_power("scalar"){ + values (0.0514); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1741,-0.1633,-0.1477,-0.1223,-0.0813,-0.0080,0.1267",\ +"-0.1779,-0.1672,-0.1516,-0.1262,-0.0852,-0.0119,0.1228",\ +"-0.1818,-0.1711,-0.1555,-0.1301,-0.0891,-0.0158,0.1189",\ +"-0.1850,-0.1742,-0.1586,-0.1332,-0.0922,-0.0190,0.1158",\ +"-0.1974,-0.1867,-0.1711,-0.1457,-0.1047,-0.0314,0.1033",\ +"-0.2149,-0.2041,-0.1885,-0.1631,-0.1221,-0.0489,0.0859",\ +"-0.2425,-0.2318,-0.2162,-0.1908,-0.1498,-0.0765,0.0582"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1506,-0.1389,-0.1262,-0.0989,-0.0617,0.0115,0.1394",\ +"-0.1545,-0.1428,-0.1301,-0.1027,-0.0656,0.0076,0.1355",\ +"-0.1584,-0.1467,-0.1340,-0.1067,-0.0695,0.0037,0.1316",\ +"-0.1615,-0.1498,-0.1371,-0.1098,-0.0727,0.0006,0.1285",\ +"-0.1740,-0.1623,-0.1496,-0.1222,-0.0851,-0.0119,0.1160",\ +"-0.1915,-0.1797,-0.1670,-0.1397,-0.1026,-0.0293,0.0986",\ +"-0.2191,-0.2074,-0.1947,-0.1673,-0.1302,-0.0570,0.0709"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2790,0.2693,0.2536,0.2273,0.1902,0.1160,-0.0188",\ +"0.2829,0.2732,0.2575,0.2312,0.1941,0.1198,-0.0149",\ +"0.2868,0.2771,0.2614,0.2351,0.1980,0.1237,-0.0110",\ +"0.2900,0.2802,0.2646,0.2382,0.2011,0.1269,-0.0079",\ +"0.3024,0.2926,0.2770,0.2507,0.2135,0.1393,0.0046",\ +"0.3199,0.3101,0.2945,0.2681,0.2310,0.1568,0.0220",\ +"0.3475,0.3378,0.3221,0.2958,0.2587,0.1845,0.0497"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2507,0.2400,0.2263,0.1990,0.1628,0.0906,-0.0393",\ +"0.2546,0.2439,0.2302,0.2028,0.1667,0.0944,-0.0354",\ +"0.2585,0.2478,0.2341,0.2068,0.1706,0.0984,-0.0315",\ +"0.2617,0.2509,0.2372,0.2099,0.1738,0.1015,-0.0284",\ +"0.2741,0.2633,0.2497,0.2223,0.1862,0.1139,-0.0159",\ +"0.2916,0.2808,0.2671,0.2398,0.2037,0.1314,0.0015",\ +"0.3192,0.3085,0.2948,0.2675,0.2313,0.1591,0.0292"); + } + } +} + pin(A_BIST_CLK) { + direction : input; + capacitance : 0.00389386; + max_transition : "0.38"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.004,0.38"); + values("0.12,0.12"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0.8242); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (53.0853); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (50.8144); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (42.3390); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.4507); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.7118); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_BIST_DIN) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00252023 ; + memory_write() { + address : A_BIST_ADDR ; + clocked_on : A_BIST_CLK; + } + + max_transition : "0.38" ; + pin(A_BIST_DIN[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0378); + } + fall_power("scalar"){ + values (0.0440); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0522); + } + fall_power("scalar"){ + values (0.0514); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1741,-0.1633,-0.1477,-0.1223,-0.0813,-0.0080,0.1267",\ +"-0.1779,-0.1672,-0.1516,-0.1262,-0.0852,-0.0119,0.1228",\ +"-0.1818,-0.1711,-0.1555,-0.1301,-0.0891,-0.0158,0.1189",\ +"-0.1850,-0.1742,-0.1586,-0.1332,-0.0922,-0.0190,0.1158",\ +"-0.1974,-0.1867,-0.1711,-0.1457,-0.1047,-0.0314,0.1033",\ +"-0.2149,-0.2041,-0.1885,-0.1631,-0.1221,-0.0489,0.0859",\ +"-0.2425,-0.2318,-0.2162,-0.1908,-0.1498,-0.0765,0.0582"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("-0.1506,-0.1389,-0.1262,-0.0989,-0.0617,0.0115,0.1394",\ +"-0.1545,-0.1428,-0.1301,-0.1027,-0.0656,0.0076,0.1355",\ +"-0.1584,-0.1467,-0.1340,-0.1067,-0.0695,0.0037,0.1316",\ +"-0.1615,-0.1498,-0.1371,-0.1098,-0.0727,0.0006,0.1285",\ +"-0.1740,-0.1623,-0.1496,-0.1222,-0.0851,-0.0119,0.1160",\ +"-0.1915,-0.1797,-0.1670,-0.1397,-0.1026,-0.0293,0.0986",\ +"-0.2191,-0.2074,-0.1947,-0.1673,-0.1302,-0.0570,0.0709"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2790,0.2693,0.2536,0.2273,0.1902,0.1160,-0.0188",\ +"0.2829,0.2732,0.2575,0.2312,0.1941,0.1198,-0.0149",\ +"0.2868,0.2771,0.2614,0.2351,0.1980,0.1237,-0.0110",\ +"0.2900,0.2802,0.2646,0.2382,0.2011,0.1269,-0.0079",\ +"0.3024,0.2926,0.2770,0.2507,0.2135,0.1393,0.0046",\ +"0.3199,0.3101,0.2945,0.2681,0.2310,0.1568,0.0220",\ +"0.3475,0.3378,0.3221,0.2958,0.2587,0.1845,0.0497"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + values ("0.2507,0.2400,0.2263,0.1990,0.1628,0.0906,-0.0393",\ +"0.2546,0.2439,0.2302,0.2028,0.1667,0.0944,-0.0354",\ +"0.2585,0.2478,0.2341,0.2068,0.1706,0.0984,-0.0315",\ +"0.2617,0.2509,0.2372,0.2099,0.1738,0.1015,-0.0284",\ +"0.2741,0.2633,0.2497,0.2223,0.1862,0.1139,-0.0159",\ +"0.2916,0.2808,0.2671,0.2398,0.2037,0.1314,0.0015",\ +"0.3192,0.3085,0.2948,0.2675,0.2313,0.1591,0.0292"); + } + } + } + +bus(A_DOUT) { + + bus_type : D_7_0; + direction : output ; + capacitance : 0 ; + max_capacitance : "6.4e-14" ; + memory_read() { + address : A_ADDR ; + } + pin(A_DOUT[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "A_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("3.2551,3.2561,3.2609,3.2664,3.2873,3.3108",\ +"3.2615,3.2625,3.2673,3.2729,3.2938,3.3173",\ +"3.2655,3.2665,3.2713,3.2768,3.2977,3.3212",\ +"3.2688,3.2698,3.2746,3.2801,3.3010,3.3245",\ +"3.2774,3.2784,3.2832,3.2888,3.3097,3.3332",\ +"3.2995,3.3005,3.3054,3.3109,3.3318,3.3553",\ +"3.3250,3.3260,3.3308,3.3364,3.3573,3.3808"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("3.2208,3.2216,3.2257,3.2302,3.2473,3.2640",\ +"3.2272,3.2281,3.2321,3.2367,3.2538,3.2705",\ +"3.2312,3.2320,3.2361,3.2406,3.2577,3.2744",\ +"3.2345,3.2353,3.2394,3.2439,3.2610,3.2777",\ +"3.2431,3.2440,3.2480,3.2526,3.2697,3.2864",\ +"3.2652,3.2661,3.2701,3.2747,3.2918,3.3085",\ +"3.2907,3.2916,3.2956,3.3002,3.3173,3.3340"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0206,0.0210,0.0265,0.0323,0.0606,0.0955"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0170,0.0177,0.0222,0.0270,0.0451,0.0644"); + } + } +} +cell_leakage_power : 939.1882; +} +} diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_4096x8_c3_bm_bist_slow_1p08V_125C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_4096x8_c3_bm_bist_slow_1p08V_125C.lib new file mode 100644 index 0000000000..236e4866c9 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_4096x8_c3_bm_bist_slow_1p08V_125C.lib @@ -0,0 +1,1537 @@ +/* ------------------------------------------------------*/ +/**/ +/* Copyright 2024 IHP PDK Authors*/ +/**/ +/* Licensed under the Apache License, Version 2.0 (the "License");*/ +/* you may not use this file except in compliance with the License.*/ +/* You may obtain a copy of the License at*/ +/* */ +/* https://www.apache.org/licenses/LICENSE-2.0*/ +/* */ +/* Unless required by applicable law or agreed to in writing, software*/ +/* distributed under the License is distributed on an "AS IS" BASIS,*/ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/ +/* See the License for the specific language governing permissions and*/ +/* limitations under the License.*/ +/* */ +/* Generated on Fri Jul 19 08:59:20 2024 */ +/* */ +/* ------------------------------------------------------ */ +library(RM_IHPSG13_1P_4096x8_c3_bm_bist_slow_1p08V_125C) { + technology (cmos) ; + delay_model : table_lookup ; + define ("add_pg_pin_to_lib", "library", "boolean"); + add_pg_pin_to_lib : true; + voltage_map ( VDD, 1.08); + voltage_map ( VDDARRAY, 1.08); + voltage_map ( VSS, 0.000000 ); + + date : "Fri Jul 19 08:59:19 2024" ; + comment : "IHP Microelectronics GmbH, 2024" ; + revision : 1.0.0 ; + simulation : true ; + nom_process : 1 ; + nom_temperature : 125 ; + nom_voltage : 1.08 ; + + operating_conditions("slow_1p08V_125C"){ + process : 1 ; + temperature : 125 ; + voltage : 1.08 ; + tree_type : "balanced_tree" ; + } + + default_operating_conditions : slow_1p08V_125C ; + default_max_transition : 1.0 ; + default_fanout_load : 1.0 ; + default_inout_pin_cap : 0.0 ; + default_input_pin_cap : 0.0 ; + default_output_pin_cap : 0.0 ; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + + slew_lower_threshold_pct_rise : 30 ; + slew_upper_threshold_pct_rise : 70 ; + input_threshold_pct_fall : 50 ; + output_threshold_pct_fall : 50 ; + input_threshold_pct_rise : 50 ; + output_threshold_pct_rise : 50 ; + slew_lower_threshold_pct_fall : 30 ; + slew_upper_threshold_pct_fall : 70 ; + slew_derate_from_library : 0.5; + k_volt_cell_leakage_power : 0.0 ; + k_temp_cell_leakage_power : 0.0 ; + k_process_cell_leakage_power : 0.0 ; + k_volt_internal_power : 0.0 ; + k_temp_internal_power : 0.0 ; + k_process_internal_power : 0.0 ; + + capacitive_load_unit (1,pf) ; + voltage_unit : "1V" ; + current_unit : "1uA" ; + time_unit : "1ns" ; + leakage_power_unit : "1nW" ; + pulling_resistance_unit : "1kohm"; + /* + ------------------------------------------------------------------------------------------ + implicit units overview: + cell_area unit : "um" + internal_power unit : "1e-12 * J/toggle = 1 * uW/MHz" + (capacitive_load_unit * voltage_unit^2) per toggle event + ------------------------------------------------------------------------------------------ + */ + library_features(report_delay_calculation); + define_cell_area (pad_drivers,pad_driver_sites) ; + + lu_table_template(CLKTRAN_constraint_template) { + variable_1 : constrained_pin_transition; + index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" ); + } + lu_table_template(SRAM_load_template) { + variable_1 : total_output_net_capacitance; + index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + lu_table_template(SIG2SRAM_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" ); + index_2 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" ); + } + + lu_table_template(SIG2SRAM_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" ); + index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + + type (D_7_0) { + base_type : array; + data_type : bit; + bit_width : 8; + bit_from : 7; + bit_to : 0; + downto : true; + } + + type (A_11_0) { + base_type : array; + data_type : bit; + bit_width : 12; + bit_from : 11; + bit_to : 0; + downto : true; + } + +cell(RM_IHPSG13_1P_4096x8_c3_bm_bist) { +pg_pin (VDD) { + pg_type : primary_power; + voltage_name : VDD; +} +pg_pin (VDDARRAY) { + pg_type : primary_power; + voltage_name : VDDARRAY; +} +pg_pin (VSS) { + pg_type : primary_ground; + voltage_name : VSS; +} + +memory() { + type : ram; + address_width : 12; + word_width : 8; +} + +interface_timing : false; +bus_naming_style : "%s[%d]" ; +area : 146413.44 ; + + pin(A_DLY) { + direction : input ; + capacitance : 0.00387999 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_ADDR) { + bus_type : A_11_0; + direction : input ; + capacitance : 0.0077013 ; + pin(A_ADDR[0]) { + capacitance : 0.00625349 ; + } + pin(A_ADDR[1]) { + capacitance : 0.00507435 ; + } + pin(A_ADDR[2]) { + capacitance : 0.00656707 ; + } + pin(A_ADDR[3]) { + capacitance : 0.0083133 ; + } + pin(A_ADDR[4]) { + capacitance : 0.00507219 ; + } + pin(A_ADDR[5]) { + capacitance : 0.00964344 ; + } + pin(A_ADDR[6]) { + capacitance : 0.0119653 ; + } + pin(A_ADDR[7]) { + capacitance : 0.00827606 ; + } + pin(A_ADDR[8]) { + capacitance : 0.0110771 ; + } + pin(A_ADDR[9]) { + capacitance : 0.00811634 ; + } + pin(A_ADDR[10]) { + capacitance : 0.00916579 ; + } + max_transition : "0.5952" ; + pin(A_ADDR[11:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0172); + } + fall_power("scalar"){ + values (0.0062); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0149); + } + fall_power("scalar"){ + values (0.0018); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7371,-0.7176,-0.6863,-0.6434,-0.5652,-0.4168,-0.1980",\ +"-0.7566,-0.7371,-0.7059,-0.6629,-0.5848,-0.4363,-0.2137",\ +"-0.7879,-0.7645,-0.7332,-0.6902,-0.6121,-0.4637,-0.2449",\ +"-0.8309,-0.8074,-0.7762,-0.7332,-0.6551,-0.5066,-0.2879",\ +"-0.9051,-0.8895,-0.8543,-0.8113,-0.7332,-0.5887,-0.3660",\ +"-1.0418,-1.0262,-0.9949,-0.9480,-0.8699,-0.7293,-0.5027",\ +"-1.2684,-1.2449,-1.2176,-1.1707,-1.0965,-0.9480,-0.7293"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5926,-0.5730,-0.5418,-0.4988,-0.4246,-0.2879,-0.0730",\ +"-0.6121,-0.5926,-0.5613,-0.5223,-0.4441,-0.3074,-0.0887",\ +"-0.6395,-0.6199,-0.5926,-0.5496,-0.4715,-0.3348,-0.1160",\ +"-0.6863,-0.6668,-0.6355,-0.5965,-0.5184,-0.3777,-0.1590",\ +"-0.7605,-0.7410,-0.7137,-0.6746,-0.5926,-0.4559,-0.2410",\ +"-0.9012,-0.8816,-0.8504,-0.8113,-0.7332,-0.5926,-0.3895",\ +"-1.1238,-1.1043,-1.0769,-1.0379,-0.9559,-0.8191,-0.6004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8488,0.8293,0.7980,0.7551,0.6730,0.5285,0.3098",\ +"0.8684,0.8488,0.8176,0.7746,0.6926,0.5480,0.3254",\ +"0.8996,0.8801,0.8449,0.8020,0.7238,0.5754,0.3527",\ +"0.9426,0.9191,0.8918,0.8488,0.7668,0.6223,0.3996",\ +"1.0168,1.0012,0.9699,0.9230,0.8449,0.7004,0.4777",\ +"1.1574,1.1379,1.1105,1.0598,0.9816,0.8371,0.6184",\ +"1.3801,1.3605,1.3254,1.2980,1.2043,1.0637,0.8371"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6965,0.6770,0.6496,0.6066,0.5246,0.3918,0.1730",\ +"0.7160,0.6965,0.6652,0.6262,0.5441,0.4113,0.1965",\ +"0.7473,0.7277,0.6965,0.6535,0.5754,0.4426,0.2238",\ +"0.7863,0.7707,0.7395,0.7004,0.6223,0.4855,0.2629",\ +"0.8684,0.8449,0.8176,0.7785,0.7004,0.5637,0.3449",\ +"1.0051,0.9855,0.9855,0.9113,0.8332,0.7004,0.4895",\ +"1.2277,1.2082,1.1809,1.1379,1.0598,0.9230,0.7004"); + } + } +} +pin(A_WEN) { + direction : input ; + capacitance : 0.00313551 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0130); + } + fall_power("scalar"){ + values (0.0107); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0044); + } + fall_power("scalar"){ + values (0.0010); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3137,0.3332,0.3605,0.4035,0.4816,0.6223,0.8488",\ +"0.2980,0.3176,0.3410,0.3840,0.4660,0.6027,0.8293",\ +"0.2629,0.2824,0.3098,0.3527,0.4348,0.5754,0.7980",\ +"0.2199,0.2395,0.2668,0.3098,0.3918,0.5324,0.7590",\ +"0.1418,0.1613,0.1887,0.2316,0.3137,0.4348,0.6730",\ +"0.0012,0.0207,0.0520,0.0910,0.1730,0.3098,0.5285",\ +"-0.2215,-0.2020,-0.1746,-0.1277,-0.0496,0.0910,0.3098"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4504,0.4699,0.4973,0.5324,0.6027,0.7355,0.9699",\ +"0.4309,0.4504,0.4777,0.5129,0.5910,0.7160,0.9504",\ +"0.3996,0.4191,0.4465,0.4816,0.5520,0.6848,0.9191",\ +"0.3605,0.3762,0.4035,0.4387,0.5168,0.6418,0.8723",\ +"0.2785,0.2980,0.3215,0.3605,0.4348,0.5637,0.7980",\ +"0.1379,0.1574,0.1809,0.2199,0.2980,0.4309,0.6457",\ +"-0.0809,-0.0613,-0.0340,0.0051,0.0832,0.2160,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3723,0.3527,0.3215,0.2785,0.1965,0.0559,-0.1668",\ +"0.3918,0.3723,0.3449,0.2980,0.2160,0.0754,-0.1473",\ +"0.4152,0.3996,0.3684,0.3254,0.2434,0.1066,-0.1199",\ +"0.4621,0.4465,0.4152,0.3723,0.2863,0.1496,-0.0730",\ +"0.5324,0.5207,0.4895,0.4465,0.3645,0.2199,0.0051",\ +"0.6770,0.6535,0.6301,0.5832,0.5090,0.3605,0.1418",\ +"0.9035,0.8879,0.8566,0.8137,0.7316,0.5871,0.3684"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3566,0.3293,0.2863,0.2043,0.0676,-0.1434",\ +"0.3957,0.3762,0.3488,0.3059,0.2238,0.0871,-0.1199",\ +"0.4230,0.4035,0.3723,0.3332,0.2512,0.1184,-0.0965",\ +"0.4660,0.4465,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5324,0.5168,0.4973,0.4543,0.3723,0.2316,0.0285",\ +"0.6809,0.6613,0.6340,0.5910,0.5129,0.3645,0.1652",\ +"0.9113,0.8918,0.8605,0.8176,0.7395,0.5988,0.3879"); + } + } + } +pin(A_REN) { + direction : input ; + capacitance : 0.00381144 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0135); + } + fall_power("scalar"){ + values (0.0100); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0034); + } + fall_power("scalar"){ + values (0.0000); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.0770,-0.0574,-0.0262,0.0168,0.0949,0.2355,0.4582",\ +"-0.0965,-0.0770,-0.0457,-0.0027,0.0754,0.2160,0.4387",\ +"-0.1199,-0.1004,-0.0730,-0.0262,0.0520,0.1887,0.4113",\ +"-0.1590,-0.1434,-0.1160,-0.0730,0.0051,0.1457,0.3645",\ +"-0.2449,-0.2254,-0.1941,-0.1473,-0.0770,0.0676,0.2863",\ +"-0.3816,-0.3699,-0.3387,-0.2801,-0.2215,-0.0770,0.1457",\ +"-0.6121,-0.5926,-0.5613,-0.5145,-0.4363,-0.2996,-0.0730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.1262,0.1457,0.1691,0.2121,0.2824,0.4191,0.6457",\ +"0.1105,0.1262,0.1496,0.1887,0.2629,0.3996,0.6262",\ +"0.0793,0.0949,0.1223,0.1652,0.2395,0.3684,0.5949",\ +"0.0363,0.0559,0.0793,0.1223,0.2004,0.3410,0.5520",\ +"-0.0457,-0.0262,0.0012,0.0441,0.1301,0.2629,0.4738",\ +"-0.1902,-0.1746,-0.1434,-0.1043,-0.0184,0.1223,0.3332",\ +"-0.4129,-0.3934,-0.3660,-0.3230,-0.2449,-0.1043,0.1105"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4113,0.3918,0.3645,0.3176,0.2395,0.0988,-0.1238",\ +"0.4309,0.4113,0.3840,0.3371,0.2590,0.1184,-0.1043",\ +"0.4582,0.4387,0.4113,0.3645,0.2824,0.1457,-0.0770",\ +"0.5051,0.4816,0.4543,0.4074,0.3293,0.1887,-0.0340",\ +"0.5715,0.5598,0.5324,0.4895,0.4035,0.2512,0.0441",\ +"0.7043,0.7004,0.6730,0.6262,0.5402,0.3957,0.1809",\ +"0.9387,0.9270,0.8957,0.8527,0.7746,0.6262,0.4074"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4152,0.3918,0.3645,0.3215,0.2395,0.1027,-0.1082",\ +"0.4309,0.4113,0.3801,0.3410,0.2590,0.1223,-0.0926",\ +"0.4582,0.4387,0.4074,0.3684,0.2863,0.1496,-0.0613",\ +"0.5012,0.4816,0.4504,0.4074,0.3293,0.1887,-0.0145",\ +"0.5715,0.5559,0.5285,0.4816,0.3996,0.2512,0.0598",\ +"0.7160,0.7004,0.6691,0.6262,0.5520,0.4035,0.2004",\ +"0.9387,0.9191,0.8957,0.8488,0.7707,0.6262,0.4113"); + } + } + } +pin(A_MEN) { + direction : input ; + capacitance : 0.00300347 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0422); + } + fall_power("scalar"){ + values (0.0114); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3215,0.3449,0.3684,0.4113,0.4895,0.6301,0.8527",\ +"0.3059,0.3254,0.3527,0.3957,0.4738,0.6145,0.8371",\ +"0.2746,0.2941,0.3215,0.3645,0.4426,0.5871,0.8059",\ +"0.2316,0.2512,0.2785,0.3215,0.3996,0.5402,0.7629",\ +"0.1496,0.1730,0.1965,0.2395,0.3215,0.4660,0.6848",\ +"0.0090,0.0285,0.0598,0.1027,0.1809,0.3176,0.5402",\ +"-0.2098,-0.1902,-0.1668,-0.1199,-0.0418,0.0988,0.3137"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4582,0.4738,0.5012,0.5363,0.6145,0.7395,0.9738",\ +"0.4387,0.4543,0.4816,0.5207,0.5910,0.7199,0.9582",\ +"0.4035,0.4230,0.4504,0.4855,0.5637,0.6887,0.9230",\ +"0.3645,0.3840,0.4074,0.4465,0.5285,0.6496,0.8840",\ +"0.2824,0.3020,0.3254,0.3645,0.4465,0.5715,0.7980",\ +"0.1418,0.1613,0.1887,0.2238,0.3020,0.4309,0.6496",\ +"-0.0770,-0.0574,-0.0301,0.0090,0.0910,0.2238,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3293,0.2863,0.2043,0.0637,-0.1629",\ +"0.3996,0.3801,0.3488,0.3020,0.2238,0.0832,-0.1395",\ +"0.4230,0.4074,0.3723,0.3293,0.2473,0.1105,-0.1121",\ +"0.4621,0.4465,0.4152,0.3762,0.2941,0.1535,-0.0691",\ +"0.5441,0.5285,0.4973,0.4465,0.3684,0.2316,0.0090",\ +"0.6848,0.6652,0.6301,0.5910,0.5129,0.3605,0.1496",\ +"0.9074,0.8918,0.8566,0.8215,0.7395,0.5910,0.3723"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3332,0.2863,0.2043,0.0715,-0.1395",\ +"0.3996,0.3762,0.3488,0.3059,0.2238,0.0910,-0.1199",\ +"0.4270,0.4035,0.3762,0.3332,0.2512,0.1184,-0.0965",\ +"0.4699,0.4504,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5441,0.5285,0.4973,0.4543,0.3762,0.2355,0.0324",\ +"0.6770,0.6613,0.6340,0.5949,0.5207,0.3762,0.1652",\ +"0.9074,0.8918,0.8605,0.8176,0.7395,0.6027,0.3918"); + } + } + } +bus(A_BM) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00272583 ; + max_transition : "0.5952" ; + pin(A_BM[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0335); + } + fall_power("scalar"){ + values (0.0287); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0174); + } + fall_power("scalar"){ + values (0.0008); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5971,-0.5776,-0.5512,-0.5083,-0.4282,-0.2807,-0.0600",\ +"-0.6051,-0.5856,-0.5592,-0.5163,-0.4362,-0.2887,-0.0680",\ +"-0.6152,-0.5957,-0.5693,-0.5263,-0.4463,-0.2988,-0.0781",\ +"-0.6281,-0.6086,-0.5822,-0.5393,-0.4592,-0.3117,-0.0910",\ +"-0.6535,-0.6339,-0.6076,-0.5646,-0.4845,-0.3371,-0.1164",\ +"-0.6957,-0.6761,-0.6498,-0.6068,-0.5267,-0.3793,-0.1586",\ +"-0.7601,-0.7406,-0.7142,-0.6712,-0.5911,-0.4437,-0.2230"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5327,-0.5131,-0.4868,-0.4487,-0.3657,-0.2290,-0.0170",\ +"-0.5407,-0.5211,-0.4948,-0.4567,-0.3737,-0.2370,-0.0250",\ +"-0.5508,-0.5312,-0.5049,-0.4668,-0.3838,-0.2470,-0.0351",\ +"-0.5637,-0.5441,-0.5178,-0.4797,-0.3967,-0.2600,-0.0481",\ +"-0.5890,-0.5695,-0.5431,-0.5050,-0.4220,-0.2853,-0.0734",\ +"-0.6312,-0.6117,-0.5853,-0.5472,-0.4642,-0.3275,-0.1156",\ +"-0.6956,-0.6761,-0.6497,-0.6117,-0.5286,-0.3919,-0.1800"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.7091,0.6886,0.6632,0.6202,0.5421,0.3956,0.1729",\ +"0.7171,0.6966,0.6712,0.6282,0.5501,0.4036,0.1809",\ +"0.7272,0.7067,0.6813,0.6383,0.5602,0.4137,0.1910",\ +"0.7401,0.7196,0.6942,0.6512,0.5731,0.4266,0.2039",\ +"0.7654,0.7449,0.7195,0.6766,0.5984,0.4519,0.2293",\ +"0.8076,0.7871,0.7617,0.7188,0.6406,0.4941,0.2715",\ +"0.8720,0.8515,0.8261,0.7832,0.7050,0.5586,0.3359"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6358,0.6182,0.5899,0.5489,0.4688,0.3311,0.1202",\ +"0.6438,0.6262,0.5979,0.5569,0.4768,0.3391,0.1282",\ +"0.6539,0.6363,0.6080,0.5670,0.4869,0.3492,0.1383",\ +"0.6668,0.6493,0.6209,0.5799,0.4998,0.3621,0.1512",\ +"0.6922,0.6746,0.6463,0.6053,0.5252,0.3875,0.1766",\ +"0.7344,0.7168,0.6885,0.6475,0.5674,0.4297,0.2188",\ +"0.7988,0.7812,0.7529,0.7119,0.6318,0.4941,0.2832"); + } + } +} + pin(A_CLK) { + direction : input; + capacitance : 0.00378957; + max_transition : "0.5952"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.008,0.5952"); + values("0.4,0.4"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (1.5263); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (34.4339); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (32.2541); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (26.8612); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (0.4582); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (0.6428); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_DIN) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00290547 ; + memory_write() { + address : A_ADDR ; + clocked_on : A_CLK; + } + + max_transition : "0.5952" ; + pin(A_DIN[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0335); + } + fall_power("scalar"){ + values (0.0287); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0174); + } + fall_power("scalar"){ + values (0.0008); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5971,-0.5776,-0.5512,-0.5083,-0.4282,-0.2807,-0.0600",\ +"-0.6051,-0.5856,-0.5592,-0.5163,-0.4362,-0.2887,-0.0680",\ +"-0.6152,-0.5957,-0.5693,-0.5263,-0.4463,-0.2988,-0.0781",\ +"-0.6281,-0.6086,-0.5822,-0.5393,-0.4592,-0.3117,-0.0910",\ +"-0.6535,-0.6339,-0.6076,-0.5646,-0.4845,-0.3371,-0.1164",\ +"-0.6957,-0.6761,-0.6498,-0.6068,-0.5267,-0.3793,-0.1586",\ +"-0.7601,-0.7406,-0.7142,-0.6712,-0.5911,-0.4437,-0.2230"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5327,-0.5131,-0.4868,-0.4487,-0.3657,-0.2290,-0.0170",\ +"-0.5407,-0.5211,-0.4948,-0.4567,-0.3737,-0.2370,-0.0250",\ +"-0.5508,-0.5312,-0.5049,-0.4668,-0.3838,-0.2470,-0.0351",\ +"-0.5637,-0.5441,-0.5178,-0.4797,-0.3967,-0.2600,-0.0481",\ +"-0.5890,-0.5695,-0.5431,-0.5050,-0.4220,-0.2853,-0.0734",\ +"-0.6312,-0.6117,-0.5853,-0.5472,-0.4642,-0.3275,-0.1156",\ +"-0.6956,-0.6761,-0.6497,-0.6117,-0.5286,-0.3919,-0.1800"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.7091,0.6886,0.6632,0.6202,0.5421,0.3956,0.1729",\ +"0.7171,0.6966,0.6712,0.6282,0.5501,0.4036,0.1809",\ +"0.7272,0.7067,0.6813,0.6383,0.5602,0.4137,0.1910",\ +"0.7401,0.7196,0.6942,0.6512,0.5731,0.4266,0.2039",\ +"0.7654,0.7449,0.7195,0.6766,0.5984,0.4519,0.2293",\ +"0.8076,0.7871,0.7617,0.7188,0.6406,0.4941,0.2715",\ +"0.8720,0.8515,0.8261,0.7832,0.7050,0.5586,0.3359"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6358,0.6182,0.5899,0.5489,0.4688,0.3311,0.1202",\ +"0.6438,0.6262,0.5979,0.5569,0.4768,0.3391,0.1282",\ +"0.6539,0.6363,0.6080,0.5670,0.4869,0.3492,0.1383",\ +"0.6668,0.6493,0.6209,0.5799,0.4998,0.3621,0.1512",\ +"0.6922,0.6746,0.6463,0.6053,0.5252,0.3875,0.1766",\ +"0.7344,0.7168,0.6885,0.6475,0.5674,0.4297,0.2188",\ +"0.7988,0.7812,0.7529,0.7119,0.6318,0.4941,0.2832"); + } + } + } + + pin(A_BIST_EN) { + direction : input ; + capacitance : 0.00387999 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_BIST_ADDR) { + bus_type : A_11_0; + direction : input ; + capacitance : 0.0077013 ; + pin(A_BIST_ADDR[0]) { + capacitance : 0.00625349 ; + } + pin(A_BIST_ADDR[1]) { + capacitance : 0.00507435 ; + } + pin(A_BIST_ADDR[2]) { + capacitance : 0.00656707 ; + } + pin(A_BIST_ADDR[3]) { + capacitance : 0.0083133 ; + } + pin(A_BIST_ADDR[4]) { + capacitance : 0.00507219 ; + } + pin(A_BIST_ADDR[5]) { + capacitance : 0.00964344 ; + } + pin(A_BIST_ADDR[6]) { + capacitance : 0.0119653 ; + } + pin(A_BIST_ADDR[7]) { + capacitance : 0.00827606 ; + } + pin(A_BIST_ADDR[8]) { + capacitance : 0.0110771 ; + } + pin(A_BIST_ADDR[9]) { + capacitance : 0.00811634 ; + } + pin(A_BIST_ADDR[10]) { + capacitance : 0.00916579 ; + } + max_transition : "0.5952" ; + pin(A_BIST_ADDR[11:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0172); + } + fall_power("scalar"){ + values (0.0062); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0149); + } + fall_power("scalar"){ + values (0.0018); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.7371,-0.7176,-0.6863,-0.6434,-0.5652,-0.4168,-0.1980",\ +"-0.7566,-0.7371,-0.7059,-0.6629,-0.5848,-0.4363,-0.2137",\ +"-0.7879,-0.7645,-0.7332,-0.6902,-0.6121,-0.4637,-0.2449",\ +"-0.8309,-0.8074,-0.7762,-0.7332,-0.6551,-0.5066,-0.2879",\ +"-0.9051,-0.8895,-0.8543,-0.8113,-0.7332,-0.5887,-0.3660",\ +"-1.0418,-1.0262,-0.9949,-0.9480,-0.8699,-0.7293,-0.5027",\ +"-1.2684,-1.2449,-1.2176,-1.1707,-1.0965,-0.9480,-0.7293"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5926,-0.5730,-0.5418,-0.4988,-0.4246,-0.2879,-0.0730",\ +"-0.6121,-0.5926,-0.5613,-0.5223,-0.4441,-0.3074,-0.0887",\ +"-0.6395,-0.6199,-0.5926,-0.5496,-0.4715,-0.3348,-0.1160",\ +"-0.6863,-0.6668,-0.6355,-0.5965,-0.5184,-0.3777,-0.1590",\ +"-0.7605,-0.7410,-0.7137,-0.6746,-0.5926,-0.4559,-0.2410",\ +"-0.9012,-0.8816,-0.8504,-0.8113,-0.7332,-0.5926,-0.3895",\ +"-1.1238,-1.1043,-1.0769,-1.0379,-0.9559,-0.8191,-0.6004"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.8488,0.8293,0.7980,0.7551,0.6730,0.5285,0.3098",\ +"0.8684,0.8488,0.8176,0.7746,0.6926,0.5480,0.3254",\ +"0.8996,0.8801,0.8449,0.8020,0.7238,0.5754,0.3527",\ +"0.9426,0.9191,0.8918,0.8488,0.7668,0.6223,0.3996",\ +"1.0168,1.0012,0.9699,0.9230,0.8449,0.7004,0.4777",\ +"1.1574,1.1379,1.1105,1.0598,0.9816,0.8371,0.6184",\ +"1.3801,1.3605,1.3254,1.2980,1.2043,1.0637,0.8371"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6965,0.6770,0.6496,0.6066,0.5246,0.3918,0.1730",\ +"0.7160,0.6965,0.6652,0.6262,0.5441,0.4113,0.1965",\ +"0.7473,0.7277,0.6965,0.6535,0.5754,0.4426,0.2238",\ +"0.7863,0.7707,0.7395,0.7004,0.6223,0.4855,0.2629",\ +"0.8684,0.8449,0.8176,0.7785,0.7004,0.5637,0.3449",\ +"1.0051,0.9855,0.9855,0.9113,0.8332,0.7004,0.4895",\ +"1.2277,1.2082,1.1809,1.1379,1.0598,0.9230,0.7004"); + } + } +} +pin(A_BIST_WEN) { + direction : input ; + capacitance : 0.00313551 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0130); + } + fall_power("scalar"){ + values (0.0107); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0044); + } + fall_power("scalar"){ + values (0.0010); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3137,0.3332,0.3605,0.4035,0.4816,0.6223,0.8488",\ +"0.2980,0.3176,0.3410,0.3840,0.4660,0.6027,0.8293",\ +"0.2629,0.2824,0.3098,0.3527,0.4348,0.5754,0.7980",\ +"0.2199,0.2395,0.2668,0.3098,0.3918,0.5324,0.7590",\ +"0.1418,0.1613,0.1887,0.2316,0.3137,0.4348,0.6730",\ +"0.0012,0.0207,0.0520,0.0910,0.1730,0.3098,0.5285",\ +"-0.2215,-0.2020,-0.1746,-0.1277,-0.0496,0.0910,0.3098"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4504,0.4699,0.4973,0.5324,0.6027,0.7355,0.9699",\ +"0.4309,0.4504,0.4777,0.5129,0.5910,0.7160,0.9504",\ +"0.3996,0.4191,0.4465,0.4816,0.5520,0.6848,0.9191",\ +"0.3605,0.3762,0.4035,0.4387,0.5168,0.6418,0.8723",\ +"0.2785,0.2980,0.3215,0.3605,0.4348,0.5637,0.7980",\ +"0.1379,0.1574,0.1809,0.2199,0.2980,0.4309,0.6457",\ +"-0.0809,-0.0613,-0.0340,0.0051,0.0832,0.2160,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3723,0.3527,0.3215,0.2785,0.1965,0.0559,-0.1668",\ +"0.3918,0.3723,0.3449,0.2980,0.2160,0.0754,-0.1473",\ +"0.4152,0.3996,0.3684,0.3254,0.2434,0.1066,-0.1199",\ +"0.4621,0.4465,0.4152,0.3723,0.2863,0.1496,-0.0730",\ +"0.5324,0.5207,0.4895,0.4465,0.3645,0.2199,0.0051",\ +"0.6770,0.6535,0.6301,0.5832,0.5090,0.3605,0.1418",\ +"0.9035,0.8879,0.8566,0.8137,0.7316,0.5871,0.3684"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3566,0.3293,0.2863,0.2043,0.0676,-0.1434",\ +"0.3957,0.3762,0.3488,0.3059,0.2238,0.0871,-0.1199",\ +"0.4230,0.4035,0.3723,0.3332,0.2512,0.1184,-0.0965",\ +"0.4660,0.4465,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5324,0.5168,0.4973,0.4543,0.3723,0.2316,0.0285",\ +"0.6809,0.6613,0.6340,0.5910,0.5129,0.3645,0.1652",\ +"0.9113,0.8918,0.8605,0.8176,0.7395,0.5988,0.3879"); + } + } + } +pin(A_BIST_REN) { + direction : input ; + capacitance : 0.00381144 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0135); + } + fall_power("scalar"){ + values (0.0100); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0034); + } + fall_power("scalar"){ + values (0.0000); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.0770,-0.0574,-0.0262,0.0168,0.0949,0.2355,0.4582",\ +"-0.0965,-0.0770,-0.0457,-0.0027,0.0754,0.2160,0.4387",\ +"-0.1199,-0.1004,-0.0730,-0.0262,0.0520,0.1887,0.4113",\ +"-0.1590,-0.1434,-0.1160,-0.0730,0.0051,0.1457,0.3645",\ +"-0.2449,-0.2254,-0.1941,-0.1473,-0.0770,0.0676,0.2863",\ +"-0.3816,-0.3699,-0.3387,-0.2801,-0.2215,-0.0770,0.1457",\ +"-0.6121,-0.5926,-0.5613,-0.5145,-0.4363,-0.2996,-0.0730"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.1262,0.1457,0.1691,0.2121,0.2824,0.4191,0.6457",\ +"0.1105,0.1262,0.1496,0.1887,0.2629,0.3996,0.6262",\ +"0.0793,0.0949,0.1223,0.1652,0.2395,0.3684,0.5949",\ +"0.0363,0.0559,0.0793,0.1223,0.2004,0.3410,0.5520",\ +"-0.0457,-0.0262,0.0012,0.0441,0.1301,0.2629,0.4738",\ +"-0.1902,-0.1746,-0.1434,-0.1043,-0.0184,0.1223,0.3332",\ +"-0.4129,-0.3934,-0.3660,-0.3230,-0.2449,-0.1043,0.1105"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4113,0.3918,0.3645,0.3176,0.2395,0.0988,-0.1238",\ +"0.4309,0.4113,0.3840,0.3371,0.2590,0.1184,-0.1043",\ +"0.4582,0.4387,0.4113,0.3645,0.2824,0.1457,-0.0770",\ +"0.5051,0.4816,0.4543,0.4074,0.3293,0.1887,-0.0340",\ +"0.5715,0.5598,0.5324,0.4895,0.4035,0.2512,0.0441",\ +"0.7043,0.7004,0.6730,0.6262,0.5402,0.3957,0.1809",\ +"0.9387,0.9270,0.8957,0.8527,0.7746,0.6262,0.4074"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4152,0.3918,0.3645,0.3215,0.2395,0.1027,-0.1082",\ +"0.4309,0.4113,0.3801,0.3410,0.2590,0.1223,-0.0926",\ +"0.4582,0.4387,0.4074,0.3684,0.2863,0.1496,-0.0613",\ +"0.5012,0.4816,0.4504,0.4074,0.3293,0.1887,-0.0145",\ +"0.5715,0.5559,0.5285,0.4816,0.3996,0.2512,0.0598",\ +"0.7160,0.7004,0.6691,0.6262,0.5520,0.4035,0.2004",\ +"0.9387,0.9191,0.8957,0.8488,0.7707,0.6262,0.4113"); + } + } + } +pin(A_BIST_MEN) { + direction : input ; + capacitance : 0.00300347 ; + max_transition : "0.5952" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0422); + } + fall_power("scalar"){ + values (0.0114); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3215,0.3449,0.3684,0.4113,0.4895,0.6301,0.8527",\ +"0.3059,0.3254,0.3527,0.3957,0.4738,0.6145,0.8371",\ +"0.2746,0.2941,0.3215,0.3645,0.4426,0.5871,0.8059",\ +"0.2316,0.2512,0.2785,0.3215,0.3996,0.5402,0.7629",\ +"0.1496,0.1730,0.1965,0.2395,0.3215,0.4660,0.6848",\ +"0.0090,0.0285,0.0598,0.1027,0.1809,0.3176,0.5402",\ +"-0.2098,-0.1902,-0.1668,-0.1199,-0.0418,0.0988,0.3137"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.4582,0.4738,0.5012,0.5363,0.6145,0.7395,0.9738",\ +"0.4387,0.4543,0.4816,0.5207,0.5910,0.7199,0.9582",\ +"0.4035,0.4230,0.4504,0.4855,0.5637,0.6887,0.9230",\ +"0.3645,0.3840,0.4074,0.4465,0.5285,0.6496,0.8840",\ +"0.2824,0.3020,0.3254,0.3645,0.4465,0.5715,0.7980",\ +"0.1418,0.1613,0.1887,0.2238,0.3020,0.4309,0.6496",\ +"-0.0770,-0.0574,-0.0301,0.0090,0.0910,0.2238,0.4191"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3293,0.2863,0.2043,0.0637,-0.1629",\ +"0.3996,0.3801,0.3488,0.3020,0.2238,0.0832,-0.1395",\ +"0.4230,0.4074,0.3723,0.3293,0.2473,0.1105,-0.1121",\ +"0.4621,0.4465,0.4152,0.3762,0.2941,0.1535,-0.0691",\ +"0.5441,0.5285,0.4973,0.4465,0.3684,0.2316,0.0090",\ +"0.6848,0.6652,0.6301,0.5910,0.5129,0.3605,0.1496",\ +"0.9074,0.8918,0.8566,0.8215,0.7395,0.5910,0.3723"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.3762,0.3605,0.3332,0.2863,0.2043,0.0715,-0.1395",\ +"0.3996,0.3762,0.3488,0.3059,0.2238,0.0910,-0.1199",\ +"0.4270,0.4035,0.3762,0.3332,0.2512,0.1184,-0.0965",\ +"0.4699,0.4504,0.4191,0.3762,0.2941,0.1613,-0.0496",\ +"0.5441,0.5285,0.4973,0.4543,0.3762,0.2355,0.0324",\ +"0.6770,0.6613,0.6340,0.5949,0.5207,0.3762,0.1652",\ +"0.9074,0.8918,0.8605,0.8176,0.7395,0.6027,0.3918"); + } + } + } +bus(A_BIST_BM) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00223339 ; + max_transition : "0.5952" ; + pin(A_BIST_BM[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0335); + } + fall_power("scalar"){ + values (0.0287); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0174); + } + fall_power("scalar"){ + values (0.0008); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5971,-0.5776,-0.5512,-0.5083,-0.4282,-0.2807,-0.0600",\ +"-0.6051,-0.5856,-0.5592,-0.5163,-0.4362,-0.2887,-0.0680",\ +"-0.6152,-0.5957,-0.5693,-0.5263,-0.4463,-0.2988,-0.0781",\ +"-0.6281,-0.6086,-0.5822,-0.5393,-0.4592,-0.3117,-0.0910",\ +"-0.6535,-0.6339,-0.6076,-0.5646,-0.4845,-0.3371,-0.1164",\ +"-0.6957,-0.6761,-0.6498,-0.6068,-0.5267,-0.3793,-0.1586",\ +"-0.7601,-0.7406,-0.7142,-0.6712,-0.5911,-0.4437,-0.2230"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5327,-0.5131,-0.4868,-0.4487,-0.3657,-0.2290,-0.0170",\ +"-0.5407,-0.5211,-0.4948,-0.4567,-0.3737,-0.2370,-0.0250",\ +"-0.5508,-0.5312,-0.5049,-0.4668,-0.3838,-0.2470,-0.0351",\ +"-0.5637,-0.5441,-0.5178,-0.4797,-0.3967,-0.2600,-0.0481",\ +"-0.5890,-0.5695,-0.5431,-0.5050,-0.4220,-0.2853,-0.0734",\ +"-0.6312,-0.6117,-0.5853,-0.5472,-0.4642,-0.3275,-0.1156",\ +"-0.6956,-0.6761,-0.6497,-0.6117,-0.5286,-0.3919,-0.1800"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.7091,0.6886,0.6632,0.6202,0.5421,0.3956,0.1729",\ +"0.7171,0.6966,0.6712,0.6282,0.5501,0.4036,0.1809",\ +"0.7272,0.7067,0.6813,0.6383,0.5602,0.4137,0.1910",\ +"0.7401,0.7196,0.6942,0.6512,0.5731,0.4266,0.2039",\ +"0.7654,0.7449,0.7195,0.6766,0.5984,0.4519,0.2293",\ +"0.8076,0.7871,0.7617,0.7188,0.6406,0.4941,0.2715",\ +"0.8720,0.8515,0.8261,0.7832,0.7050,0.5586,0.3359"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6358,0.6182,0.5899,0.5489,0.4688,0.3311,0.1202",\ +"0.6438,0.6262,0.5979,0.5569,0.4768,0.3391,0.1282",\ +"0.6539,0.6363,0.6080,0.5670,0.4869,0.3492,0.1383",\ +"0.6668,0.6493,0.6209,0.5799,0.4998,0.3621,0.1512",\ +"0.6922,0.6746,0.6463,0.6053,0.5252,0.3875,0.1766",\ +"0.7344,0.7168,0.6885,0.6475,0.5674,0.4297,0.2188",\ +"0.7988,0.7812,0.7529,0.7119,0.6318,0.4941,0.2832"); + } + } +} + pin(A_BIST_CLK) { + direction : input; + capacitance : 0.00378957; + max_transition : "0.5952"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.008,0.5952"); + values("0.4,0.4"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (1.5263); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (34.4339); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (32.2541); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (26.8612); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.4582); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.6428); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_BIST_DIN) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00223473 ; + memory_write() { + address : A_BIST_ADDR ; + clocked_on : A_BIST_CLK; + } + + max_transition : "0.5952" ; + pin(A_BIST_DIN[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0335); + } + fall_power("scalar"){ + values (0.0287); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0174); + } + fall_power("scalar"){ + values (0.0008); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5971,-0.5776,-0.5512,-0.5083,-0.4282,-0.2807,-0.0600",\ +"-0.6051,-0.5856,-0.5592,-0.5163,-0.4362,-0.2887,-0.0680",\ +"-0.6152,-0.5957,-0.5693,-0.5263,-0.4463,-0.2988,-0.0781",\ +"-0.6281,-0.6086,-0.5822,-0.5393,-0.4592,-0.3117,-0.0910",\ +"-0.6535,-0.6339,-0.6076,-0.5646,-0.4845,-0.3371,-0.1164",\ +"-0.6957,-0.6761,-0.6498,-0.6068,-0.5267,-0.3793,-0.1586",\ +"-0.7601,-0.7406,-0.7142,-0.6712,-0.5911,-0.4437,-0.2230"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("-0.5327,-0.5131,-0.4868,-0.4487,-0.3657,-0.2290,-0.0170",\ +"-0.5407,-0.5211,-0.4948,-0.4567,-0.3737,-0.2370,-0.0250",\ +"-0.5508,-0.5312,-0.5049,-0.4668,-0.3838,-0.2470,-0.0351",\ +"-0.5637,-0.5441,-0.5178,-0.4797,-0.3967,-0.2600,-0.0481",\ +"-0.5890,-0.5695,-0.5431,-0.5050,-0.4220,-0.2853,-0.0734",\ +"-0.6312,-0.6117,-0.5853,-0.5472,-0.4642,-0.3275,-0.1156",\ +"-0.6956,-0.6761,-0.6497,-0.6117,-0.5286,-0.3919,-0.1800"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.7091,0.6886,0.6632,0.6202,0.5421,0.3956,0.1729",\ +"0.7171,0.6966,0.6712,0.6282,0.5501,0.4036,0.1809",\ +"0.7272,0.7067,0.6813,0.6383,0.5602,0.4137,0.1910",\ +"0.7401,0.7196,0.6942,0.6512,0.5731,0.4266,0.2039",\ +"0.7654,0.7449,0.7195,0.6766,0.5984,0.4519,0.2293",\ +"0.8076,0.7871,0.7617,0.7188,0.6406,0.4941,0.2715",\ +"0.8720,0.8515,0.8261,0.7832,0.7050,0.5586,0.3359"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + values ("0.6358,0.6182,0.5899,0.5489,0.4688,0.3311,0.1202",\ +"0.6438,0.6262,0.5979,0.5569,0.4768,0.3391,0.1282",\ +"0.6539,0.6363,0.6080,0.5670,0.4869,0.3492,0.1383",\ +"0.6668,0.6493,0.6209,0.5799,0.4998,0.3621,0.1512",\ +"0.6922,0.6746,0.6463,0.6053,0.5252,0.3875,0.1766",\ +"0.7344,0.7168,0.6885,0.6475,0.5674,0.4297,0.2188",\ +"0.7988,0.7812,0.7529,0.7119,0.6318,0.4941,0.2832"); + } + } + } + +bus(A_DOUT) { + + bus_type : D_7_0; + direction : output ; + capacitance : 0 ; + max_capacitance : "6.4e-14" ; + memory_read() { + address : A_ADDR ; + } + pin(A_DOUT[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "A_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("8.8071,8.8098,8.8220,8.8362,8.8882,8.9463",\ +"8.8192,8.8219,8.8341,8.8483,8.9004,8.9584",\ +"8.8311,8.8338,8.8460,8.8602,8.9123,8.9703",\ +"8.8332,8.8360,8.8482,8.8624,8.9144,8.9724",\ +"8.8591,8.8618,8.8740,8.8882,8.9402,8.9983",\ +"8.9105,8.9132,8.9254,8.9396,8.9916,9.0497",\ +"8.9673,8.9700,8.9822,8.9964,9.0485,9.1065"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("8.6972,8.6993,8.7089,8.7207,8.7643,8.8081",\ +"8.7093,8.7114,8.7210,8.7328,8.7764,8.8202",\ +"8.7212,8.7233,8.7330,8.7448,8.7883,8.8321",\ +"8.7233,8.7255,8.7351,8.7469,8.7905,8.8342",\ +"8.7491,8.7513,8.7609,8.7727,8.8163,8.8600",\ +"8.8005,8.8027,8.8123,8.8241,8.8677,8.9114",\ +"8.8574,8.8595,8.8691,8.8809,8.9245,8.9683"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0560,0.0583,0.0696,0.0816,0.1519,0.2335"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0428,0.0445,0.0538,0.0658,0.1181,0.1751"); + } + } +} +cell_leakage_power : 2613.1763; +} +} diff --git a/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_4096x8_c3_bm_bist_typ_1p20V_25C.lib b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_4096x8_c3_bm_bist_typ_1p20V_25C.lib new file mode 100644 index 0000000000..0dd7037c33 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lib/RM_IHPSG13_1P_4096x8_c3_bm_bist_typ_1p20V_25C.lib @@ -0,0 +1,1537 @@ +/* ------------------------------------------------------*/ +/**/ +/* Copyright 2024 IHP PDK Authors*/ +/**/ +/* Licensed under the Apache License, Version 2.0 (the "License");*/ +/* you may not use this file except in compliance with the License.*/ +/* You may obtain a copy of the License at*/ +/* */ +/* https://www.apache.org/licenses/LICENSE-2.0*/ +/* */ +/* Unless required by applicable law or agreed to in writing, software*/ +/* distributed under the License is distributed on an "AS IS" BASIS,*/ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/ +/* See the License for the specific language governing permissions and*/ +/* limitations under the License.*/ +/* */ +/* Generated on Fri Jul 19 08:59:22 2024 */ +/* */ +/* ------------------------------------------------------ */ +library(RM_IHPSG13_1P_4096x8_c3_bm_bist_typ_1p20V_25C) { + technology (cmos) ; + delay_model : table_lookup ; + define ("add_pg_pin_to_lib", "library", "boolean"); + add_pg_pin_to_lib : true; + voltage_map ( VDD, 1.20); + voltage_map ( VDDARRAY, 1.20); + voltage_map ( VSS, 0.000000 ); + + date : "Fri Jul 19 08:59:19 2024" ; + comment : "IHP Microelectronics GmbH, 2024" ; + revision : 1.0.0 ; + simulation : true ; + nom_process : 1 ; + nom_temperature : 25 ; + nom_voltage : 1.20 ; + + operating_conditions("typ_1p20V_25C"){ + process : 1 ; + temperature : 25 ; + voltage : 1.20 ; + tree_type : "balanced_tree" ; + } + + default_operating_conditions : typ_1p20V_25C ; + default_max_transition : 1.0 ; + default_fanout_load : 1.0 ; + default_inout_pin_cap : 0.0 ; + default_input_pin_cap : 0.0 ; + default_output_pin_cap : 0.0 ; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + + slew_lower_threshold_pct_rise : 30 ; + slew_upper_threshold_pct_rise : 70 ; + input_threshold_pct_fall : 50 ; + output_threshold_pct_fall : 50 ; + input_threshold_pct_rise : 50 ; + output_threshold_pct_rise : 50 ; + slew_lower_threshold_pct_fall : 30 ; + slew_upper_threshold_pct_fall : 70 ; + slew_derate_from_library : 0.5; + k_volt_cell_leakage_power : 0.0 ; + k_temp_cell_leakage_power : 0.0 ; + k_process_cell_leakage_power : 0.0 ; + k_volt_internal_power : 0.0 ; + k_temp_internal_power : 0.0 ; + k_process_internal_power : 0.0 ; + + capacitive_load_unit (1,pf) ; + voltage_unit : "1V" ; + current_unit : "1uA" ; + time_unit : "1ns" ; + leakage_power_unit : "1nW" ; + pulling_resistance_unit : "1kohm"; + /* + ------------------------------------------------------------------------------------------ + implicit units overview: + cell_area unit : "um" + internal_power unit : "1e-12 * J/toggle = 1 * uW/MHz" + (capacitive_load_unit * voltage_unit^2) per toggle event + ------------------------------------------------------------------------------------------ + */ + library_features(report_delay_calculation); + define_cell_area (pad_drivers,pad_driver_sites) ; + + lu_table_template(CLKTRAN_constraint_template) { + variable_1 : constrained_pin_transition; + index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" ); + } + lu_table_template(SRAM_load_template) { + variable_1 : total_output_net_capacitance; + index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + lu_table_template(SIG2SRAM_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" ); + index_2 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" ); + } + + lu_table_template(SIG2SRAM_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" ); + index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" ); + } + + type (D_7_0) { + base_type : array; + data_type : bit; + bit_width : 8; + bit_from : 7; + bit_to : 0; + downto : true; + } + + type (A_11_0) { + base_type : array; + data_type : bit; + bit_width : 12; + bit_from : 11; + bit_to : 0; + downto : true; + } + +cell(RM_IHPSG13_1P_4096x8_c3_bm_bist) { +pg_pin (VDD) { + pg_type : primary_power; + voltage_name : VDD; +} +pg_pin (VDDARRAY) { + pg_type : primary_power; + voltage_name : VDDARRAY; +} +pg_pin (VSS) { + pg_type : primary_ground; + voltage_name : VSS; +} + +memory() { + type : ram; + address_width : 12; + word_width : 8; +} + +interface_timing : false; +bus_naming_style : "%s[%d]" ; +area : 146413.44 ; + + pin(A_DLY) { + direction : input ; + capacitance : 0.00401111 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_ADDR) { + bus_type : A_11_0; + direction : input ; + capacitance : 0.00721489 ; + pin(A_ADDR[0]) { + capacitance : 0.00593979 ; + } + pin(A_ADDR[1]) { + capacitance : 0.00483009 ; + } + pin(A_ADDR[2]) { + capacitance : 0.006215 ; + } + pin(A_ADDR[3]) { + capacitance : 0.00766726 ; + } + pin(A_ADDR[4]) { + capacitance : 0.00488951 ; + } + pin(A_ADDR[5]) { + capacitance : 0.0091523 ; + } + pin(A_ADDR[6]) { + capacitance : 0.0109212 ; + } + pin(A_ADDR[7]) { + capacitance : 0.00774122 ; + } + pin(A_ADDR[8]) { + capacitance : 0.0101403 ; + } + pin(A_ADDR[9]) { + capacitance : 0.00771605 ; + } + pin(A_ADDR[10]) { + capacitance : 0.00860549 ; + } + max_transition : "0.476" ; + pin(A_ADDR[11:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0077); + } + fall_power("scalar"){ + values (0.0018); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0163); + } + fall_power("scalar"){ + values (0.0029); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4168,-0.3973,-0.3855,-0.3543,-0.3074,-0.2020,-0.0027",\ +"-0.4324,-0.4129,-0.4012,-0.3699,-0.3191,-0.2176,-0.0184",\ +"-0.4441,-0.4285,-0.4129,-0.3816,-0.3309,-0.2293,-0.0301",\ +"-0.4793,-0.4598,-0.4441,-0.4129,-0.3660,-0.2645,-0.0652",\ +"-0.5223,-0.5066,-0.4910,-0.4598,-0.4129,-0.3074,-0.1121",\ +"-0.6199,-0.6082,-0.5926,-0.5613,-0.5145,-0.4129,-0.2137",\ +"-0.8191,-0.8074,-0.7840,-0.7566,-0.7098,-0.6082,-0.4051"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3309,-0.3113,-0.2996,-0.2684,-0.2176,-0.1238,0.0637",\ +"-0.3465,-0.3309,-0.3152,-0.2840,-0.2332,-0.1395,0.0480",\ +"-0.3582,-0.3426,-0.3270,-0.2996,-0.2488,-0.1512,0.0324",\ +"-0.3895,-0.3738,-0.3582,-0.3309,-0.2801,-0.1863,0.0051",\ +"-0.4363,-0.4207,-0.4051,-0.3777,-0.3230,-0.2293,-0.0379",\ +"-0.5379,-0.5223,-0.5066,-0.4793,-0.4285,-0.3309,-0.1434",\ +"-0.7332,-0.7176,-0.7020,-0.6746,-0.6238,-0.5262,-0.3387"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "((A_WEN | A_REN)& A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5246,0.5051,0.4895,0.4582,0.4113,0.3059,0.1066",\ +"0.5402,0.5207,0.5051,0.4777,0.4270,0.3215,0.1223",\ +"0.5520,0.5324,0.5168,0.4895,0.4387,0.3371,0.1340",\ +"0.5832,0.5676,0.5520,0.5207,0.4738,0.3684,0.1691",\ +"0.6301,0.6105,0.5949,0.5676,0.5168,0.4113,0.2160",\ +"0.7316,0.7121,0.7004,0.6691,0.6223,0.5168,0.3176",\ +"0.9270,0.9230,0.8957,0.8645,0.8137,0.7121,0.5168"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4309,0.4152,0.4035,0.3684,0.3215,0.2277,0.0363",\ +"0.4465,0.4309,0.4152,0.3879,0.3371,0.2395,0.0559",\ +"0.4582,0.4426,0.4309,0.3996,0.3488,0.2551,0.0715",\ +"0.4934,0.4777,0.4621,0.4348,0.3840,0.2863,0.0988",\ +"0.5363,0.5207,0.5051,0.4777,0.4270,0.3332,0.1418",\ +"0.6379,0.6262,0.6105,0.5793,0.5324,0.4348,0.2434",\ +"0.8332,0.8215,0.8059,0.7707,0.7238,0.6301,0.4387"); + } + } +} +pin(A_WEN) { + direction : input ; + capacitance : 0.00324098 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0038); + } + fall_power("scalar"){ + values (0.0049); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0032); + } + fall_power("scalar"){ + values (0.0048); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2629,0.3059,0.4113,0.6066",\ +"0.1887,0.2043,0.2160,0.2473,0.2941,0.3957,0.5949",\ +"0.1691,0.1848,0.2004,0.2316,0.2785,0.3801,0.5754",\ +"0.1379,0.1574,0.1691,0.2004,0.2473,0.3527,0.5480",\ +"0.0910,0.1066,0.1223,0.1535,0.2004,0.2980,0.4973",\ +"-0.0105,0.0051,0.0207,0.0520,0.0949,0.2004,0.3957",\ +"-0.2059,-0.1902,-0.1746,-0.1473,-0.1004,0.0051,0.2004"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2941,0.3098,0.3215,0.3488,0.4035,0.4973,0.6887",\ +"0.2785,0.2941,0.3059,0.3332,0.3840,0.4816,0.6691",\ +"0.2629,0.2785,0.2902,0.3176,0.3684,0.4660,0.6535",\ +"0.2316,0.2473,0.2590,0.2863,0.3410,0.4348,0.6262",\ +"0.1848,0.2004,0.2121,0.2395,0.2902,0.3879,0.5754",\ +"0.0832,0.0988,0.1105,0.1379,0.1809,0.2746,0.4699",\ +"-0.1121,-0.0965,-0.0848,-0.0535,-0.0066,0.0910,0.2824"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2473,0.2316,0.2160,0.1887,0.1379,0.0363,-0.1629",\ +"0.2629,0.2473,0.2316,0.2043,0.1535,0.0520,-0.1473",\ +"0.2785,0.2590,0.2434,0.2160,0.1652,0.0676,-0.1355",\ +"0.3098,0.2941,0.2785,0.2473,0.1965,0.0910,-0.1043",\ +"0.3527,0.3371,0.3215,0.2941,0.2434,0.1418,-0.0574",\ +"0.4582,0.4426,0.4270,0.3957,0.3488,0.2434,0.0480",\ +"0.6535,0.6379,0.6184,0.5910,0.5402,0.4426,0.2434"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2395,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2668,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2395,0.1887,0.0910,-0.0965",\ +"0.3449,0.3293,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4191,0.3879,0.3371,0.2395,0.0559",\ +"0.6457,0.6301,0.6145,0.5871,0.5324,0.4309,0.2512"); + } + } + } +pin(A_REN) { + direction : input ; + capacitance : 0.00381634 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0055); + } + fall_power("scalar"){ + values (0.0032); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0052); + } + fall_power("scalar"){ + values (0.0035); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.0301,-0.0145,0.0012,0.0324,0.0793,0.1809,0.3762",\ +"-0.0457,-0.0301,-0.0145,0.0168,0.0637,0.1613,0.3605",\ +"-0.0574,-0.0418,-0.0262,0.0051,0.0520,0.1496,0.3449",\ +"-0.0926,-0.0730,-0.0574,-0.0262,0.0207,0.1184,0.3137",\ +"-0.1395,-0.1238,-0.1082,-0.0770,-0.0301,0.0715,0.2707",\ +"-0.2410,-0.2254,-0.2098,-0.1746,-0.1355,-0.0340,0.1652",\ +"-0.4402,-0.4207,-0.4051,-0.3738,-0.3270,-0.2293,-0.0340"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.0988,0.1145,0.1262,0.1535,0.2043,0.3020,0.4855",\ +"0.0832,0.0988,0.1105,0.1418,0.1848,0.2824,0.4738",\ +"0.0676,0.0832,0.0949,0.1262,0.1730,0.2668,0.4621",\ +"0.0402,0.0559,0.0676,0.0988,0.1457,0.2434,0.4191",\ +"-0.0105,0.0012,0.0168,0.0480,0.0988,0.1965,0.3840",\ +"-0.1160,-0.0965,-0.0848,-0.0535,-0.0066,0.0988,0.2824",\ +"-0.3113,-0.2957,-0.2801,-0.2527,-0.2059,-0.1043,0.0832"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "A_MEN" + sdf_cond : "A_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2707,0.2551,0.2395,0.2121,0.1613,0.0598,-0.1395",\ +"0.2863,0.2707,0.2551,0.2238,0.1730,0.0715,-0.1238",\ +"0.2980,0.2824,0.2668,0.2395,0.1887,0.0871,-0.1121",\ +"0.3332,0.3176,0.3020,0.2707,0.2199,0.1184,-0.0809",\ +"0.3762,0.3605,0.3449,0.3176,0.2668,0.1613,-0.0340",\ +"0.4816,0.4621,0.4504,0.4191,0.3723,0.2629,0.0715",\ +"0.6770,0.6613,0.6418,0.6184,0.5637,0.4699,0.2629"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2590,0.2434,0.2316,0.2004,0.1457,0.0520,-0.1355",\ +"0.2746,0.2590,0.2434,0.2160,0.1613,0.0676,-0.1199",\ +"0.2863,0.2707,0.2590,0.2277,0.1730,0.0832,-0.1082",\ +"0.3215,0.3059,0.2902,0.2590,0.2082,0.1105,-0.0770",\ +"0.3645,0.3488,0.3332,0.3059,0.2551,0.1535,-0.0340",\ +"0.4699,0.4543,0.4387,0.4074,0.3605,0.2551,0.0715",\ +"0.6652,0.6496,0.6340,0.6027,0.5520,0.4621,0.2707"); + } + } + } +pin(A_MEN) { + direction : input ; + capacitance : 0.00309605 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0234); + } + fall_power("scalar"){ + values (0.0060); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2668,0.3098,0.4152,0.6066",\ +"0.1887,0.2043,0.2199,0.2512,0.2941,0.3996,0.5949",\ +"0.1730,0.1887,0.2043,0.2355,0.2824,0.3840,0.5793",\ +"0.1418,0.1574,0.1730,0.2043,0.2512,0.3566,0.5480",\ +"0.0949,0.1105,0.1262,0.1574,0.2043,0.3020,0.5051",\ +"-0.0066,0.0090,0.0246,0.0520,0.0988,0.2043,0.3996",\ +"-0.2020,-0.1863,-0.1746,-0.1434,-0.0965,0.0090,0.2082"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2980,0.3137,0.3254,0.3527,0.4035,0.5012,0.6887",\ +"0.2824,0.2980,0.3098,0.3371,0.3879,0.4855,0.6730",\ +"0.2668,0.2824,0.2941,0.3215,0.3723,0.4699,0.6574",\ +"0.2355,0.2473,0.2629,0.2902,0.3410,0.4387,0.6262",\ +"0.1887,0.2004,0.2160,0.2395,0.2941,0.3918,0.5793",\ +"0.0871,0.1027,0.1145,0.1418,0.1848,0.2746,0.4816",\ +"-0.1082,-0.0965,-0.0809,-0.0496,-0.0027,0.0949,0.2863"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2512,0.2355,0.2199,0.1926,0.1418,0.0402,-0.1590",\ +"0.2668,0.2512,0.2355,0.2082,0.1574,0.0559,-0.1434",\ +"0.2824,0.2629,0.2512,0.2199,0.1691,0.0715,-0.1316",\ +"0.3137,0.2980,0.2824,0.2512,0.2004,0.0988,-0.0965",\ +"0.3566,0.3410,0.3254,0.2980,0.2473,0.1418,-0.0535",\ +"0.4621,0.4426,0.4309,0.3996,0.3527,0.2473,0.0520",\ +"0.6574,0.6418,0.6262,0.5949,0.5441,0.4465,0.2473"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2434,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2707,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2434,0.1926,0.0910,-0.0965",\ +"0.3449,0.3332,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4230,0.3918,0.3410,0.2434,0.0559",\ +"0.6457,0.6301,0.6145,0.5910,0.5324,0.4387,0.2512"); + } + } + } +bus(A_BM) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00293842 ; + max_transition : "0.476" ; + pin(A_BM[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0242); + } + fall_power("scalar"){ + values (0.0193); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0257); + } + fall_power("scalar"){ + values (0.0191); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3243,-0.3086,-0.2950,-0.2627,-0.2159,-0.1114,0.0800",\ +"-0.3293,-0.3136,-0.3000,-0.2677,-0.2209,-0.1164,0.0750",\ +"-0.3338,-0.3181,-0.3045,-0.2722,-0.2254,-0.1209,0.0705",\ +"-0.3435,-0.3279,-0.3142,-0.2820,-0.2351,-0.1306,0.0608",\ +"-0.3501,-0.3345,-0.3208,-0.2886,-0.2417,-0.1372,0.0542",\ +"-0.3811,-0.3654,-0.3518,-0.3195,-0.2727,-0.1682,0.0232",\ +"-0.4371,-0.4214,-0.4078,-0.3755,-0.3287,-0.2242,-0.0328"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.2862,-0.2715,-0.2579,-0.2295,-0.1788,-0.0811,0.1015",\ +"-0.2912,-0.2765,-0.2629,-0.2345,-0.1838,-0.0861,0.0965",\ +"-0.2957,-0.2810,-0.2673,-0.2390,-0.1882,-0.0906,0.0920",\ +"-0.3054,-0.2908,-0.2771,-0.2488,-0.1980,-0.1004,0.0823",\ +"-0.3120,-0.2974,-0.2837,-0.2554,-0.2046,-0.1069,0.0757",\ +"-0.3430,-0.3283,-0.3147,-0.2863,-0.2356,-0.1379,0.0447",\ +"-0.3990,-0.3843,-0.3706,-0.3423,-0.2915,-0.1939,-0.0113"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)" + sdf_cond : "A_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4332,0.4166,0.4039,0.3717,0.3238,0.2203,0.0279",\ +"0.4382,0.4216,0.4089,0.3767,0.3288,0.2253,0.0330",\ +"0.4427,0.4261,0.4134,0.3812,0.3333,0.2298,0.0374",\ +"0.4525,0.4359,0.4232,0.3909,0.3431,0.2396,0.0472",\ +"0.4590,0.4424,0.4297,0.3975,0.3496,0.2461,0.0538",\ +"0.4900,0.4734,0.4607,0.4285,0.3806,0.2771,0.0847",\ +"0.5460,0.5294,0.5167,0.4845,0.4366,0.3331,0.1407"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.3873,0.3727,0.3590,0.3307,0.2809,0.1881,0.0035",\ +"0.3923,0.3777,0.3640,0.3357,0.2859,0.1931,0.0085",\ +"0.3968,0.3822,0.3685,0.3402,0.2904,0.1976,0.0130",\ +"0.4066,0.3919,0.3782,0.3499,0.3001,0.2073,0.0228",\ +"0.4131,0.3985,0.3848,0.3565,0.3067,0.2139,0.0293",\ +"0.4441,0.4295,0.4158,0.3875,0.3377,0.2449,0.0603",\ +"0.5001,0.4855,0.4718,0.4435,0.3937,0.3009,0.1163"); + } + } +} + pin(A_CLK) { + direction : input; + capacitance : 0.00380014; + max_transition : "0.476"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.0056,0.476"); + values("0.21,0.21"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (1.1525); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & !A_REN"; + rise_power("scalar"){ + values (42.2119); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (41.0961); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (33.7167); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & !A_WEN & A_REN"; + rise_power("scalar"){ + values (0.3256); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_MEN & A_WEN & A_REN"; + rise_power("scalar"){ + values (0.5445); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_MEN & !A_WEN & !A_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_DIN) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.0030602 ; + memory_write() { + address : A_ADDR ; + clocked_on : A_CLK; + } + + max_transition : "0.476" ; + pin(A_DIN[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_MEN"; + rise_power("scalar"){ + values (0.0242); + } + fall_power("scalar"){ + values (0.0193); + } + } + internal_power() { + when : "!A_MEN"; + rise_power("scalar"){ + values (0.0257); + } + fall_power("scalar"){ + values (0.0191); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3243,-0.3086,-0.2950,-0.2627,-0.2159,-0.1114,0.0800",\ +"-0.3293,-0.3136,-0.3000,-0.2677,-0.2209,-0.1164,0.0750",\ +"-0.3338,-0.3181,-0.3045,-0.2722,-0.2254,-0.1209,0.0705",\ +"-0.3435,-0.3279,-0.3142,-0.2820,-0.2351,-0.1306,0.0608",\ +"-0.3501,-0.3345,-0.3208,-0.2886,-0.2417,-0.1372,0.0542",\ +"-0.3811,-0.3654,-0.3518,-0.3195,-0.2727,-0.1682,0.0232",\ +"-0.4371,-0.4214,-0.4078,-0.3755,-0.3287,-0.2242,-0.0328"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.2862,-0.2715,-0.2579,-0.2295,-0.1788,-0.0811,0.1015",\ +"-0.2912,-0.2765,-0.2629,-0.2345,-0.1838,-0.0861,0.0965",\ +"-0.2957,-0.2810,-0.2673,-0.2390,-0.1882,-0.0906,0.0920",\ +"-0.3054,-0.2908,-0.2771,-0.2488,-0.1980,-0.1004,0.0823",\ +"-0.3120,-0.2974,-0.2837,-0.2554,-0.2046,-0.1069,0.0757",\ +"-0.3430,-0.3283,-0.3147,-0.2863,-0.2356,-0.1379,0.0447",\ +"-0.3990,-0.3843,-0.3706,-0.3423,-0.2915,-0.1939,-0.0113"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_CLK"; + when : "(A_WEN & A_MEN)"; + sdf_cond : "A_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4332,0.4166,0.4039,0.3717,0.3238,0.2203,0.0279",\ +"0.4382,0.4216,0.4089,0.3767,0.3288,0.2253,0.0330",\ +"0.4427,0.4261,0.4134,0.3812,0.3333,0.2298,0.0374",\ +"0.4525,0.4359,0.4232,0.3909,0.3431,0.2396,0.0472",\ +"0.4590,0.4424,0.4297,0.3975,0.3496,0.2461,0.0538",\ +"0.4900,0.4734,0.4607,0.4285,0.3806,0.2771,0.0847",\ +"0.5460,0.5294,0.5167,0.4845,0.4366,0.3331,0.1407"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.3873,0.3727,0.3590,0.3307,0.2809,0.1881,0.0035",\ +"0.3923,0.3777,0.3640,0.3357,0.2859,0.1931,0.0085",\ +"0.3968,0.3822,0.3685,0.3402,0.2904,0.1976,0.0130",\ +"0.4066,0.3919,0.3782,0.3499,0.3001,0.2073,0.0228",\ +"0.4131,0.3985,0.3848,0.3565,0.3067,0.2139,0.0293",\ +"0.4441,0.4295,0.4158,0.3875,0.3377,0.2449,0.0603",\ +"0.5001,0.4855,0.4718,0.4435,0.3937,0.3009,0.1163"); + } + } + } + + pin(A_BIST_EN) { + direction : input ; + capacitance : 0.00401111 ; + max_transition : "1" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + +bus(A_BIST_ADDR) { + bus_type : A_11_0; + direction : input ; + capacitance : 0.00721489 ; + pin(A_BIST_ADDR[0]) { + capacitance : 0.00593979 ; + } + pin(A_BIST_ADDR[1]) { + capacitance : 0.00483009 ; + } + pin(A_BIST_ADDR[2]) { + capacitance : 0.006215 ; + } + pin(A_BIST_ADDR[3]) { + capacitance : 0.00766726 ; + } + pin(A_BIST_ADDR[4]) { + capacitance : 0.00488951 ; + } + pin(A_BIST_ADDR[5]) { + capacitance : 0.0091523 ; + } + pin(A_BIST_ADDR[6]) { + capacitance : 0.0109212 ; + } + pin(A_BIST_ADDR[7]) { + capacitance : 0.00774122 ; + } + pin(A_BIST_ADDR[8]) { + capacitance : 0.0101403 ; + } + pin(A_BIST_ADDR[9]) { + capacitance : 0.00771605 ; + } + pin(A_BIST_ADDR[10]) { + capacitance : 0.00860549 ; + } + max_transition : "0.476" ; + pin(A_BIST_ADDR[11:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0077); + } + fall_power("scalar"){ + values (0.0018); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0163); + } + fall_power("scalar"){ + values (0.0029); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.4168,-0.3973,-0.3855,-0.3543,-0.3074,-0.2020,-0.0027",\ +"-0.4324,-0.4129,-0.4012,-0.3699,-0.3191,-0.2176,-0.0184",\ +"-0.4441,-0.4285,-0.4129,-0.3816,-0.3309,-0.2293,-0.0301",\ +"-0.4793,-0.4598,-0.4441,-0.4129,-0.3660,-0.2645,-0.0652",\ +"-0.5223,-0.5066,-0.4910,-0.4598,-0.4129,-0.3074,-0.1121",\ +"-0.6199,-0.6082,-0.5926,-0.5613,-0.5145,-0.4129,-0.2137",\ +"-0.8191,-0.8074,-0.7840,-0.7566,-0.7098,-0.6082,-0.4051"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3309,-0.3113,-0.2996,-0.2684,-0.2176,-0.1238,0.0637",\ +"-0.3465,-0.3309,-0.3152,-0.2840,-0.2332,-0.1395,0.0480",\ +"-0.3582,-0.3426,-0.3270,-0.2996,-0.2488,-0.1512,0.0324",\ +"-0.3895,-0.3738,-0.3582,-0.3309,-0.2801,-0.1863,0.0051",\ +"-0.4363,-0.4207,-0.4051,-0.3777,-0.3230,-0.2293,-0.0379",\ +"-0.5379,-0.5223,-0.5066,-0.4793,-0.4285,-0.3309,-0.1434",\ +"-0.7332,-0.7176,-0.7020,-0.6746,-0.6238,-0.5262,-0.3387"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.5246,0.5051,0.4895,0.4582,0.4113,0.3059,0.1066",\ +"0.5402,0.5207,0.5051,0.4777,0.4270,0.3215,0.1223",\ +"0.5520,0.5324,0.5168,0.4895,0.4387,0.3371,0.1340",\ +"0.5832,0.5676,0.5520,0.5207,0.4738,0.3684,0.1691",\ +"0.6301,0.6105,0.5949,0.5676,0.5168,0.4113,0.2160",\ +"0.7316,0.7121,0.7004,0.6691,0.6223,0.5168,0.3176",\ +"0.9270,0.9230,0.8957,0.8645,0.8137,0.7121,0.5168"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4309,0.4152,0.4035,0.3684,0.3215,0.2277,0.0363",\ +"0.4465,0.4309,0.4152,0.3879,0.3371,0.2395,0.0559",\ +"0.4582,0.4426,0.4309,0.3996,0.3488,0.2551,0.0715",\ +"0.4934,0.4777,0.4621,0.4348,0.3840,0.2863,0.0988",\ +"0.5363,0.5207,0.5051,0.4777,0.4270,0.3332,0.1418",\ +"0.6379,0.6262,0.6105,0.5793,0.5324,0.4348,0.2434",\ +"0.8332,0.8215,0.8059,0.7707,0.7238,0.6301,0.4387"); + } + } +} +pin(A_BIST_WEN) { + direction : input ; + capacitance : 0.00324098 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0038); + } + fall_power("scalar"){ + values (0.0049); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0032); + } + fall_power("scalar"){ + values (0.0048); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2629,0.3059,0.4113,0.6066",\ +"0.1887,0.2043,0.2160,0.2473,0.2941,0.3957,0.5949",\ +"0.1691,0.1848,0.2004,0.2316,0.2785,0.3801,0.5754",\ +"0.1379,0.1574,0.1691,0.2004,0.2473,0.3527,0.5480",\ +"0.0910,0.1066,0.1223,0.1535,0.2004,0.2980,0.4973",\ +"-0.0105,0.0051,0.0207,0.0520,0.0949,0.2004,0.3957",\ +"-0.2059,-0.1902,-0.1746,-0.1473,-0.1004,0.0051,0.2004"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2941,0.3098,0.3215,0.3488,0.4035,0.4973,0.6887",\ +"0.2785,0.2941,0.3059,0.3332,0.3840,0.4816,0.6691",\ +"0.2629,0.2785,0.2902,0.3176,0.3684,0.4660,0.6535",\ +"0.2316,0.2473,0.2590,0.2863,0.3410,0.4348,0.6262",\ +"0.1848,0.2004,0.2121,0.2395,0.2902,0.3879,0.5754",\ +"0.0832,0.0988,0.1105,0.1379,0.1809,0.2746,0.4699",\ +"-0.1121,-0.0965,-0.0848,-0.0535,-0.0066,0.0910,0.2824"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2473,0.2316,0.2160,0.1887,0.1379,0.0363,-0.1629",\ +"0.2629,0.2473,0.2316,0.2043,0.1535,0.0520,-0.1473",\ +"0.2785,0.2590,0.2434,0.2160,0.1652,0.0676,-0.1355",\ +"0.3098,0.2941,0.2785,0.2473,0.1965,0.0910,-0.1043",\ +"0.3527,0.3371,0.3215,0.2941,0.2434,0.1418,-0.0574",\ +"0.4582,0.4426,0.4270,0.3957,0.3488,0.2434,0.0480",\ +"0.6535,0.6379,0.6184,0.5910,0.5402,0.4426,0.2434"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2395,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2668,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2395,0.1887,0.0910,-0.0965",\ +"0.3449,0.3293,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4191,0.3879,0.3371,0.2395,0.0559",\ +"0.6457,0.6301,0.6145,0.5871,0.5324,0.4309,0.2512"); + } + } + } +pin(A_BIST_REN) { + direction : input ; + capacitance : 0.00381634 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0055); + } + fall_power("scalar"){ + values (0.0032); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0052); + } + fall_power("scalar"){ + values (0.0035); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.0301,-0.0145,0.0012,0.0324,0.0793,0.1809,0.3762",\ +"-0.0457,-0.0301,-0.0145,0.0168,0.0637,0.1613,0.3605",\ +"-0.0574,-0.0418,-0.0262,0.0051,0.0520,0.1496,0.3449",\ +"-0.0926,-0.0730,-0.0574,-0.0262,0.0207,0.1184,0.3137",\ +"-0.1395,-0.1238,-0.1082,-0.0770,-0.0301,0.0715,0.2707",\ +"-0.2410,-0.2254,-0.2098,-0.1746,-0.1355,-0.0340,0.1652",\ +"-0.4402,-0.4207,-0.4051,-0.3738,-0.3270,-0.2293,-0.0340"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.0988,0.1145,0.1262,0.1535,0.2043,0.3020,0.4855",\ +"0.0832,0.0988,0.1105,0.1418,0.1848,0.2824,0.4738",\ +"0.0676,0.0832,0.0949,0.1262,0.1730,0.2668,0.4621",\ +"0.0402,0.0559,0.0676,0.0988,0.1457,0.2434,0.4191",\ +"-0.0105,0.0012,0.0168,0.0480,0.0988,0.1965,0.3840",\ +"-0.1160,-0.0965,-0.0848,-0.0535,-0.0066,0.0988,0.2824",\ +"-0.3113,-0.2957,-0.2801,-0.2527,-0.2059,-0.1043,0.0832"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "A_BIST_MEN" + sdf_cond : "A_BIST_MEN" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2707,0.2551,0.2395,0.2121,0.1613,0.0598,-0.1395",\ +"0.2863,0.2707,0.2551,0.2238,0.1730,0.0715,-0.1238",\ +"0.2980,0.2824,0.2668,0.2395,0.1887,0.0871,-0.1121",\ +"0.3332,0.3176,0.3020,0.2707,0.2199,0.1184,-0.0809",\ +"0.3762,0.3605,0.3449,0.3176,0.2668,0.1613,-0.0340",\ +"0.4816,0.4621,0.4504,0.4191,0.3723,0.2629,0.0715",\ +"0.6770,0.6613,0.6418,0.6184,0.5637,0.4699,0.2629"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2590,0.2434,0.2316,0.2004,0.1457,0.0520,-0.1355",\ +"0.2746,0.2590,0.2434,0.2160,0.1613,0.0676,-0.1199",\ +"0.2863,0.2707,0.2590,0.2277,0.1730,0.0832,-0.1082",\ +"0.3215,0.3059,0.2902,0.2590,0.2082,0.1105,-0.0770",\ +"0.3645,0.3488,0.3332,0.3059,0.2551,0.1535,-0.0340",\ +"0.4699,0.4543,0.4387,0.4074,0.3605,0.2551,0.0715",\ +"0.6652,0.6496,0.6340,0.6027,0.5520,0.4621,0.2707"); + } + } + } +pin(A_BIST_MEN) { + direction : input ; + capacitance : 0.00309605 ; + max_transition : "0.476" ; + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar"){ + values (0.0234); + } + fall_power("scalar"){ + values (0.0060); + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2043,0.2199,0.2316,0.2668,0.3098,0.4152,0.6066",\ +"0.1887,0.2043,0.2199,0.2512,0.2941,0.3996,0.5949",\ +"0.1730,0.1887,0.2043,0.2355,0.2824,0.3840,0.5793",\ +"0.1418,0.1574,0.1730,0.2043,0.2512,0.3566,0.5480",\ +"0.0949,0.1105,0.1262,0.1574,0.2043,0.3020,0.5051",\ +"-0.0066,0.0090,0.0246,0.0520,0.0988,0.2043,0.3996",\ +"-0.2020,-0.1863,-0.1746,-0.1434,-0.0965,0.0090,0.2082"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2980,0.3137,0.3254,0.3527,0.4035,0.5012,0.6887",\ +"0.2824,0.2980,0.3098,0.3371,0.3879,0.4855,0.6730",\ +"0.2668,0.2824,0.2941,0.3215,0.3723,0.4699,0.6574",\ +"0.2355,0.2473,0.2629,0.2902,0.3410,0.4387,0.6262",\ +"0.1887,0.2004,0.2160,0.2395,0.2941,0.3918,0.5793",\ +"0.0871,0.1027,0.1145,0.1418,0.1848,0.2746,0.4816",\ +"-0.1082,-0.0965,-0.0809,-0.0496,-0.0027,0.0949,0.2863"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2512,0.2355,0.2199,0.1926,0.1418,0.0402,-0.1590",\ +"0.2668,0.2512,0.2355,0.2082,0.1574,0.0559,-0.1434",\ +"0.2824,0.2629,0.2512,0.2199,0.1691,0.0715,-0.1316",\ +"0.3137,0.2980,0.2824,0.2512,0.2004,0.0988,-0.0965",\ +"0.3566,0.3410,0.3254,0.2980,0.2473,0.1418,-0.0535",\ +"0.4621,0.4426,0.4309,0.3996,0.3527,0.2473,0.0520",\ +"0.6574,0.6418,0.6262,0.5949,0.5441,0.4465,0.2473"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\ +"0.2551,0.2434,0.2277,0.1965,0.1457,0.0480,-0.1395",\ +"0.2707,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\ +"0.3020,0.2863,0.2707,0.2434,0.1926,0.0910,-0.0965",\ +"0.3449,0.3332,0.3176,0.2863,0.2355,0.1379,-0.0496",\ +"0.4504,0.4348,0.4230,0.3918,0.3410,0.2434,0.0559",\ +"0.6457,0.6301,0.6145,0.5910,0.5324,0.4387,0.2512"); + } + } + } +bus(A_BIST_BM) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00236845 ; + max_transition : "0.476" ; + pin(A_BIST_BM[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0242); + } + fall_power("scalar"){ + values (0.0193); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0257); + } + fall_power("scalar"){ + values (0.0191); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3243,-0.3086,-0.2950,-0.2627,-0.2159,-0.1114,0.0800",\ +"-0.3293,-0.3136,-0.3000,-0.2677,-0.2209,-0.1164,0.0750",\ +"-0.3338,-0.3181,-0.3045,-0.2722,-0.2254,-0.1209,0.0705",\ +"-0.3435,-0.3279,-0.3142,-0.2820,-0.2351,-0.1306,0.0608",\ +"-0.3501,-0.3345,-0.3208,-0.2886,-0.2417,-0.1372,0.0542",\ +"-0.3811,-0.3654,-0.3518,-0.3195,-0.2727,-0.1682,0.0232",\ +"-0.4371,-0.4214,-0.4078,-0.3755,-0.3287,-0.2242,-0.0328"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.2862,-0.2715,-0.2579,-0.2295,-0.1788,-0.0811,0.1015",\ +"-0.2912,-0.2765,-0.2629,-0.2345,-0.1838,-0.0861,0.0965",\ +"-0.2957,-0.2810,-0.2673,-0.2390,-0.1882,-0.0906,0.0920",\ +"-0.3054,-0.2908,-0.2771,-0.2488,-0.1980,-0.1004,0.0823",\ +"-0.3120,-0.2974,-0.2837,-0.2554,-0.2046,-0.1069,0.0757",\ +"-0.3430,-0.3283,-0.3147,-0.2863,-0.2356,-0.1379,0.0447",\ +"-0.3990,-0.3843,-0.3706,-0.3423,-0.2915,-0.1939,-0.0113"); + } + } + + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)" + sdf_cond : "A_BIST_RW_ACCESS" + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4332,0.4166,0.4039,0.3717,0.3238,0.2203,0.0279",\ +"0.4382,0.4216,0.4089,0.3767,0.3288,0.2253,0.0330",\ +"0.4427,0.4261,0.4134,0.3812,0.3333,0.2298,0.0374",\ +"0.4525,0.4359,0.4232,0.3909,0.3431,0.2396,0.0472",\ +"0.4590,0.4424,0.4297,0.3975,0.3496,0.2461,0.0538",\ +"0.4900,0.4734,0.4607,0.4285,0.3806,0.2771,0.0847",\ +"0.5460,0.5294,0.5167,0.4845,0.4366,0.3331,0.1407"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.3873,0.3727,0.3590,0.3307,0.2809,0.1881,0.0035",\ +"0.3923,0.3777,0.3640,0.3357,0.2859,0.1931,0.0085",\ +"0.3968,0.3822,0.3685,0.3402,0.2904,0.1976,0.0130",\ +"0.4066,0.3919,0.3782,0.3499,0.3001,0.2073,0.0228",\ +"0.4131,0.3985,0.3848,0.3565,0.3067,0.2139,0.0293",\ +"0.4441,0.4295,0.4158,0.3875,0.3377,0.2449,0.0603",\ +"0.5001,0.4855,0.4718,0.4435,0.3937,0.3009,0.1163"); + } + } +} + pin(A_BIST_CLK) { + direction : input; + capacitance : 0.00380014; + max_transition : "0.476"; + clock : "true" ; + pin_func_type : active_rising ; + + timing () { + timing_type : "min_pulse_width"; + related_pin : "A_BIST_CLK"; + rise_constraint("CLKTRAN_constraint_template") { + index_1("0.0056,0.476"); + values("0.21,0.21"); + } + } + + related_power_pin : VDD; + related_ground_pin : VSS; + + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (1.1525); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (42.2119); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (41.0961); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (33.7167); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & !A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.3256); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "!A_BIST_MEN & A_BIST_WEN & A_BIST_REN"; + rise_power("scalar"){ + values (0.5445); + } + fall_power("scalar"){ + values (0); + } + } + internal_power() { + when : "A_BIST_MEN & !A_BIST_WEN & !A_BIST_REN"; + rise_power("scalar"){ + values (0); + } + fall_power("scalar"){ + values (0); + } + } + } + bus(A_BIST_DIN) { + bus_type : D_7_0; + direction : input ; + capacitance : 0.00232602 ; + memory_write() { + address : A_BIST_ADDR ; + clocked_on : A_BIST_CLK; + } + + max_transition : "0.476" ; + pin(A_BIST_DIN[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + when : "A_BIST_MEN"; + rise_power("scalar"){ + values (0.0242); + } + fall_power("scalar"){ + values (0.0193); + } + } + internal_power() { + when : "!A_BIST_MEN"; + rise_power("scalar"){ + values (0.0257); + } + fall_power("scalar"){ + values (0.0191); + } + } + } + timing() { + timing_type : setup_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.3243,-0.3086,-0.2950,-0.2627,-0.2159,-0.1114,0.0800",\ +"-0.3293,-0.3136,-0.3000,-0.2677,-0.2209,-0.1164,0.0750",\ +"-0.3338,-0.3181,-0.3045,-0.2722,-0.2254,-0.1209,0.0705",\ +"-0.3435,-0.3279,-0.3142,-0.2820,-0.2351,-0.1306,0.0608",\ +"-0.3501,-0.3345,-0.3208,-0.2886,-0.2417,-0.1372,0.0542",\ +"-0.3811,-0.3654,-0.3518,-0.3195,-0.2727,-0.1682,0.0232",\ +"-0.4371,-0.4214,-0.4078,-0.3755,-0.3287,-0.2242,-0.0328"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("-0.2862,-0.2715,-0.2579,-0.2295,-0.1788,-0.0811,0.1015",\ +"-0.2912,-0.2765,-0.2629,-0.2345,-0.1838,-0.0861,0.0965",\ +"-0.2957,-0.2810,-0.2673,-0.2390,-0.1882,-0.0906,0.0920",\ +"-0.3054,-0.2908,-0.2771,-0.2488,-0.1980,-0.1004,0.0823",\ +"-0.3120,-0.2974,-0.2837,-0.2554,-0.2046,-0.1069,0.0757",\ +"-0.3430,-0.3283,-0.3147,-0.2863,-0.2356,-0.1379,0.0447",\ +"-0.3990,-0.3843,-0.3706,-0.3423,-0.2915,-0.1939,-0.0113"); + } + } + + timing() { + timing_type : hold_rising; + related_pin : "A_BIST_CLK"; + when : "(A_BIST_WEN & A_BIST_MEN)"; + sdf_cond : "A_BIST_W_ACCESS"; + + rise_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.4332,0.4166,0.4039,0.3717,0.3238,0.2203,0.0279",\ +"0.4382,0.4216,0.4089,0.3767,0.3288,0.2253,0.0330",\ +"0.4427,0.4261,0.4134,0.3812,0.3333,0.2298,0.0374",\ +"0.4525,0.4359,0.4232,0.3909,0.3431,0.2396,0.0472",\ +"0.4590,0.4424,0.4297,0.3975,0.3496,0.2461,0.0538",\ +"0.4900,0.4734,0.4607,0.4285,0.3806,0.2771,0.0847",\ +"0.5460,0.5294,0.5167,0.4845,0.4366,0.3331,0.1407"); + } + + fall_constraint("SIG2SRAM_constraint_template") { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + values ("0.3873,0.3727,0.3590,0.3307,0.2809,0.1881,0.0035",\ +"0.3923,0.3777,0.3640,0.3357,0.2859,0.1931,0.0085",\ +"0.3968,0.3822,0.3685,0.3402,0.2904,0.1976,0.0130",\ +"0.4066,0.3919,0.3782,0.3499,0.3001,0.2073,0.0228",\ +"0.4131,0.3985,0.3848,0.3565,0.3067,0.2139,0.0293",\ +"0.4441,0.4295,0.4158,0.3875,0.3377,0.2449,0.0603",\ +"0.5001,0.4855,0.4718,0.4435,0.3937,0.3009,0.1163"); + } + } + } + +bus(A_DOUT) { + + bus_type : D_7_0; + direction : output ; + capacitance : 0 ; + max_capacitance : "6.4e-14" ; + memory_read() { + address : A_ADDR ; + } + pin(A_DOUT[7:0]) { + related_power_pin : VDD; + related_ground_pin : VSS; + internal_power() { + rise_power("scalar") { + values (0); + } + fall_power("scalar") { + values (0); + } + } + } + timing() { + related_pin : "A_CLK"; + timing_type : rising_edge ; + timing_sense : non_unate ; + + cell_rise(SIG2SRAM_delay_template) { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("5.2741,5.2757,5.2834,5.2921,5.3245,5.3604",\ +"5.2853,5.2869,5.2946,5.3033,5.3357,5.3716",\ +"5.2840,5.2856,5.2932,5.3019,5.3344,5.3702",\ +"5.2970,5.2986,5.3063,5.3150,5.3474,5.3833",\ +"5.3048,5.3064,5.3141,5.3228,5.3552,5.3911",\ +"5.3374,5.3390,5.3466,5.3553,5.3878,5.4236",\ +"5.3913,5.3929,5.4006,5.4093,5.4417,5.4776"); + } + cell_fall(SIG2SRAM_delay_template) { + index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760"); + index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("5.2131,5.2144,5.2204,5.2275,5.2540,5.2807",\ +"5.2242,5.2256,5.2316,5.2387,5.2652,5.2918",\ +"5.2229,5.2242,5.2302,5.2374,5.2639,5.2905",\ +"5.2359,5.2373,5.2433,5.2504,5.2769,5.3036",\ +"5.2437,5.2450,5.2510,5.2582,5.2847,5.3113",\ +"5.2763,5.2776,5.2836,5.2908,5.3173,5.3439",\ +"5.3302,5.3315,5.3375,5.3447,5.3712,5.3978"); + } + + rise_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0326,0.0341,0.0428,0.0518,0.0923,0.1492"); + } + fall_transition(SRAM_load_template) { + index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640"); + values ("0.0254,0.0265,0.0335,0.0402,0.0707,0.1039"); + } + } +} +cell_leakage_power : 396.0310; +} +} diff --git a/flow/platforms/ihp-sg13g2/lib/sg13g2_io_dummy.lib b/flow/platforms/ihp-sg13g2/lib/sg13g2_io_dummy.lib index f985659464..57efb7f778 100644 --- a/flow/platforms/ihp-sg13g2/lib/sg13g2_io_dummy.lib +++ b/flow/platforms/ihp-sg13g2/lib/sg13g2_io_dummy.lib @@ -1540,4 +1540,78 @@ library (sg13g2_io_dummy) { voltage_name : "iovdd"; } } + cell (sg13g2_IOPadAnalog) { + area: 14400; + dont_touch : true; + dont_use : true; + timing_model_type : abstracted; + pad_cell : true; + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pin (pad) { + direction : inout; + function : "(pad)"; + output_voltage : core_output; + related_ground_pin : vss; + related_power_pin : vdd; + max_capacitance : 500; + max_transition : 200; + timing () { + related_pin : "pad"; + timing_type : combinational; + cell_rise (delay_template_2x2) { + values ( \ + "1000, 1000", \ + "1000, 1000" \ + ); + } + rise_transition (delay_template_2x2) { + values ( \ + "200, 200", \ + "200, 200" \ + ); + } + cell_fall (delay_template_2x2) { + values ( \ + "1000, 1000", \ + "1000, 1000" \ + ); + } + fall_transition (delay_template_2x2) { + values ( \ + "200, 200", \ + "200, 200" \ + ); + } + } + } + pin (padres) { + direction : inout; + is_pad : false; + input_voltage : io_input; + related_ground_pin : iovss; + related_power_pin : iovdd; + max_transition : 200; + capacitance : 15.0; + rise_capacitance : 15.0; + rise_capacitance_range (12.0, 15.0); + fall_capacitance : 15.0; + fall_capacitance_range (12.0, 15.0); + } + } + } diff --git a/flow/platforms/ihp-sg13g2/lib/sg13g2_io_fast_1p32V_3p6V_m40C.lib b/flow/platforms/ihp-sg13g2/lib/sg13g2_io_fast_1p32V_3p6V_m40C.lib new file mode 100644 index 0000000000..c42ff8c075 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lib/sg13g2_io_fast_1p32V_3p6V_m40C.lib @@ -0,0 +1,4599 @@ +/************************************************************************ + + Copyright 2024 IHP PDK Authors + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + https://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +************************************************************************/ + +library (sg13g2_io_fast_1p32V_3p6V_m40C) { + comment : "IHP Microelectronics GmbH, 2024"; + date : "$Date: Wed May 8 12:23:04 2024 $"; + revision : "$Revision: 0.0.1 $"; + delay_model : table_lookup; + capacitive_load_unit (1,pf); + current_unit : "1uA"; + leakage_power_unit : "1pW"; + pulling_resistance_unit : "1kohm"; + time_unit : "1ns"; + voltage_unit : "1V"; + voltage_map (vdd, 1.32); + voltage_map (iovdd, 3.6); + voltage_map (iovss, 0); + voltage_map (vss, 0); + voltage_map (GND, 0); + define_cell_area (pad_drivers, pad_driver_sites); + define_cell_area (bond_pads, pad_slots); + default_output_pin_cap : 0; + default_inout_pin_cap : 1; + default_input_pin_cap : 1; + default_fanout_load : 1; + default_cell_leakage_power : 0; + default_max_transition : 1.2; + default_leakage_power_density : 0; + default_max_capacitance : 0.3; + default_max_fanout : 8; + default_wire_load_area : 0.29; + default_wire_load_capacitance : 0.0003; + default_wire_load_mode : "enclosed"; + default_wire_load_resistance : 0.0057; + in_place_swap_mode : match_footprint; + input_threshold_pct_fall : 50; + input_threshold_pct_rise : 50; + nom_process : 1; + nom_temperature : -40; + nom_voltage : 1.32; + output_threshold_pct_fall : 50; + output_threshold_pct_rise : 50; + slew_derate_from_library : 1; + slew_lower_threshold_pct_fall : 10; + slew_lower_threshold_pct_rise : 10; + slew_upper_threshold_pct_fall : 90; + slew_upper_threshold_pct_rise : 90; + operating_conditions (sg13g2_io_fast_1p32V_3p6V_m40C) { + process : 1; + temperature : -40; + voltage : 1.32; + } + input_voltage (pad) { + vih : 3.3; + vil : 0; + vimax : 3.3; + vimin : 0; + } + input_voltage (core) { + vih : 1.2; + vil : 0; + vimax : 1.2; + vimin : 0; + } + output_voltage (pad) { + voh : 3.3; + vol : 0; + vomax : 3.3; + vomin : 0; + } + output_voltage (core) { + voh : 1.2; + vol : 0; + vomax : 1.2; + vomin : 0; + } + wire_load (Zero) { + area : 0.01; + capacitance : 0.0001; + resistance : 0.0001; + slope : 1; + fanout_length (1, 0.01); + fanout_length (5, 0.01); + fanout_length (20, 0.01); + } + wire_load ("0_1k") { + area : 0.36; + capacitance : 0.0001; + resistance : 0.0035; + slope : 7.387; + fanout_length (1, 6.43); + fanout_length (5, 38.56); + fanout_length (20, 146.8); + } + wire_load ("0_5k") { + area : 0.36; + capacitance : 0.0001; + resistance : 0.0042; + slope : 10.99; + fanout_length (1, 7.89); + fanout_length (5, 47.32); + fanout_length (20, 169.4); + } + wire_load ("1k") { + area : 0.36; + capacitance : 0.0002; + resistance : 0.0053; + slope : 10.9; + fanout_length (1, 9.93); + fanout_length (5, 59.59); + fanout_length (20, 215.6); + } + wire_load ("2k") { + area : 0.36; + capacitance : 0.0002; + resistance : 0.0063; + slope : 16.87; + fanout_length (1, 11.68); + fanout_length (5, 70.11); + fanout_length (20, 239.5); + } + wire_load ("5k") { + area : 0.36; + capacitance : 0.0003; + resistance : 0.0072; + slope : 14.58; + fanout_length (1, 13.44); + fanout_length (5, 80.62); + fanout_length (20, 287.1); + } + wire_load ("10k") { + area : 0.37; + capacitance : 0.0003; + resistance : 0.008; + slope : 18.94; + fanout_length (1, 14.9); + fanout_length (5, 89.39); + fanout_length (20, 381.6); + } + wire_load ("30k") { + area : 0.37; + capacitance : 0.0003; + resistance : 0.0094; + slope : 24.61; + fanout_length (1, 17.53); + fanout_length (5, 105.2); + fanout_length (20, 515.5); + } + wire_load ("50k") { + area : 0.37; + capacitance : 0.0005; + resistance : 0.0152; + slope : 31.81; + fanout_length (1, 28.33); + fanout_length (5, 170); + fanout_length (20, 607.6); + } + wire_load ("100k") { + area : 0.39; + capacitance : 0.0009; + resistance : 0.0265; + slope : 40.22; + fanout_length (1, 49.37); + fanout_length (5, 296.2); + fanout_length (20, 812.1); + } + wire_load ("200k") { + area : 0.41; + capacitance : 0.0016; + resistance : 0.0456; + slope : 52.68; + fanout_length (1, 84.71); + fanout_length (5, 508.3); + fanout_length (20, 1051.7); + } + wire_load ("500k") { + area : 0.45; + capacitance : 0.0027; + resistance : 0.076; + slope : 67.44; + fanout_length (1, 141.4); + fanout_length (5, 848.3); + fanout_length (20, 1527.1); + } + wire_load_selection ("4_metls_routing") { + wire_load_from_area (0, 635, 0_1k); + wire_load_from_area (635, 3175, 0_5k); + wire_load_from_area (3175, 6350, 1k); + wire_load_from_area (6350, 12701, 2k); + wire_load_from_area (12701, 31752, 5k); + wire_load_from_area (31752, 63504, 10k); + wire_load_from_area (63504, 190512, 30k); + wire_load_from_area (190512, 317520, 50k); + wire_load_from_area (317520, 635040, 100k); + wire_load_from_area (635040, 1.27008e+06, 200k); + wire_load_from_area (1.27008e+06, 3.1752e+06, 500k); + } + default_wire_load : "1k"; + default_operating_conditions : sg13g2_io_fast_1p32V_3p6V_m40C; + default_wire_load_selection : "4_metls_routing"; + lu_table_template (delay_template_7x6_16) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 3, 7, 9, 12, 15"); + } + power_lut_template (passive_power_template_7x1_16) { + variable_1 : input_transition_time; + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + } + power_lut_template (power_template_7x6_16) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 3, 7, 9, 12, 15"); + } + cell (sg13g2_IOPadIOVdd) { + area : 14400; + pad_cell : true; + bond_pads : 1; + dont_touch : true; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + is_pad : true; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 7677.59; + related_pg_pin : iovdd; + } + leakage_power () { + value : 0; + related_pg_pin : vdd; + } + } + cell (sg13g2_IOPadIOVss) { + area : 14400; + pad_cell : true; + bond_pads : 1; + dont_touch : true; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + is_pad : true; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 0; + related_pg_pin : iovdd; + } + leakage_power () { + value : 1.83299; + related_pg_pin : vdd; + } + } + cell (sg13g2_IOPadIn) { + pad_cell : true; + area : 14400; + cell_footprint : "input"; + pad_drivers : 1; + bond_pads : 1; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 0; + when : "pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 354.116; + when : "pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 0; + when : "!pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 670.739; + when : "!pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 0; + related_pg_pin : iovdd; + } + leakage_power () { + value : 512.427; + related_pg_pin : vdd; + } + pin (p2c) { + direction : "output"; + output_voltage : "core"; + function : "pad"; + related_ground_pin : vss; + related_power_pin : vdd; + max_capacitance : 1.28354; + timing () { + related_pin : "pad"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0523039, 0.0646799, 0.087623, 0.109319, 0.13033, 0.151196", \ + "0.0523049, 0.0646809, 0.087624, 0.10932, 0.130331, 0.151197", \ + "0.0523059, 0.0646819, 0.087625, 0.109321, 0.130332, 0.151198", \ + "0.0523069, 0.0646829, 0.087626, 0.109322, 0.130333, 0.151199", \ + "0.0523079, 0.0646839, 0.087627, 0.109323, 0.130334, 0.1512", \ + "0.0523089, 0.0646849, 0.087628, 0.109324, 0.130335, 0.151201", \ + "0.0523099, 0.0646859, 0.087629, 0.109325, 0.130336, 0.151202" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0428437, 0.0653179, 0.109366, 0.153753, 0.198558, 0.243442", \ + "0.0456388, 0.067037, 0.111483, 0.156944, 0.201663, 0.246552", \ + "0.0508324, 0.0713752, 0.114082, 0.158033, 0.202811, 0.248058", \ + "0.0534639, 0.073691, 0.115793, 0.15919, 0.203617, 0.24829", \ + "0.0657121, 0.0850862, 0.125061, 0.166125, 0.208858, 0.252443", \ + "0.0862891, 0.10512, 0.142109, 0.181709, 0.222366, 0.263495", \ + "0.102899, 0.122236, 0.157721, 0.194267, 0.233121, 0.273106" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.299572, 0.317477, 0.345389, 0.368863, 0.390036, 0.410337", \ + "0.354454, 0.372294, 0.400331, 0.42368, 0.444424, 0.465138", \ + "0.475665, 0.493405, 0.521478, 0.544476, 0.566031, 0.586205", \ + "0.53895, 0.556871, 0.584526, 0.607573, 0.629295, 0.649423", \ + "0.855057, 0.872865, 0.900428, 0.923611, 0.94469, 0.965375", \ + "1.4969, 1.51561, 1.54385, 1.56724, 1.58852, 1.60764", \ + "2.05897, 2.07932, 2.11055, 2.13577, 2.15781, 2.17829" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0852423, 0.103765, 0.137116, 0.169592, 0.201984, 0.235388", \ + "0.0853015, 0.103766, 0.137117, 0.169593, 0.201985, 0.235389", \ + "0.0853025, 0.103767, 0.137118, 0.169594, 0.201986, 0.23539", \ + "0.0853035, 0.103768, 0.137119, 0.169595, 0.202057, 0.235391", \ + "0.0853045, 0.103898, 0.13712, 0.169596, 0.202058, 0.235438", \ + "0.098857, 0.11625, 0.14692, 0.17785, 0.209811, 0.241414", \ + "0.120292, 0.137979, 0.168987, 0.19889, 0.228172, 0.258693" \ + ); + } + } + internal_power () { + related_pin : "pad"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "9.24581e-09, 9.24676e-09, 9.24651e-09, 9.24644e-09, 9.24643e-09, 9.24596e-09", \ + "1.79958e-08, 1.79943e-08, 1.79941e-08, 1.79941e-08, 1.79945e-08, 1.79945e-08", \ + "3.5493e-08, 3.54928e-08, 3.54911e-08, 3.5491e-08, 3.54907e-08, 3.54909e-08", \ + "4.42416e-08, 4.42413e-08, 4.42409e-08, 4.42374e-08, 4.42392e-08, 4.42392e-08", \ + "8.79826e-08, 8.79837e-08, 8.79816e-08, 8.79812e-08, 8.79817e-08, 8.79821e-08", \ + "1.75465e-07, 1.75464e-07, 1.75466e-07, 1.75462e-07, 1.75466e-07, 1.75464e-07", \ + "2.54676e-07, 2.54676e-07, 2.54676e-07, 2.5468e-07, 2.54678e-07, 2.54681e-07" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "-9.24581e-09, -9.24639e-09, -9.24645e-09, -9.24644e-09, -9.24643e-09, -9.24596e-09", \ + "-1.79951e-08, -1.79943e-08, -1.79941e-08, -1.79941e-08, -1.79945e-08, -1.79945e-08", \ + "-3.54918e-08, -3.54917e-08, -3.54911e-08, -3.5491e-08, -3.54907e-08, -3.54909e-08", \ + "-4.424e-08, -4.424e-08, -4.424e-08, -4.42374e-08, -4.42392e-08, -4.42392e-08", \ + "-8.79786e-08, -8.79786e-08, -8.79786e-08, -8.79786e-08, -8.79787e-08, -8.79787e-08", \ + "-1.75458e-07, -1.75458e-07, -1.75458e-07, -1.75458e-07, -1.75459e-07, -1.75459e-07", \ + "-2.54676e-07, -2.54676e-07, -2.54676e-07, -2.5468e-07, -2.54678e-07, -2.54681e-07" \ + ); + } + } + internal_power () { + related_pin : "pad"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "-0.000947443, -0.000697383, -0.000788833, -0.000724008, -0.000882686, -0.00109453", \ + "-0.00194729, -0.00154423, -0.00137465, -0.00165184, -0.00195796, -0.00223237", \ + "-0.00252829, -0.00247062, -0.0023195, -0.00209377, -0.00213048, -0.00254297", \ + "-0.00266262, -0.00267658, -0.00273134, -0.00269965, -0.00237693, -0.00265886", \ + "-0.00232712, -0.00261495, -0.00262601, -0.00377677, -0.00415101, -0.00491026", \ + "-0.000360651, -0.00134872, -0.00206606, -0.00203094, -0.00213695, -0.00356901", \ + "0.0526746, 0.0505981, 0.0492084, 0.0469091, 0.0468558, 0.04505" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0675601, 0.0664679, 0.066242, 0.0663827, 0.0665253, 0.0666468", \ + "0.0667947, 0.0656519, 0.0653503, 0.0654599, 0.0655764, 0.065692", \ + "0.0663483, 0.0652505, 0.0649197, 0.0649653, 0.065068, 0.0651515", \ + "0.0659144, 0.06481, 0.0644553, 0.0645035, 0.0646019, 0.0646759", \ + "0.0663483, 0.0651383, 0.0645445, 0.0644442, 0.0644579, 0.0644801", \ + "0.0689082, 0.0670994, 0.0656158, 0.0651657, 0.0650151, 0.0649601", \ + "0.074507, 0.070866, 0.0683193, 0.0673413, 0.0667181, 0.066293" \ + ); + } + } + } + pin (pad) { + direction : "input"; + is_pad : true; + input_voltage : "pad"; + fanout_load : 1; + related_ground_pin : iovss; + related_power_pin : iovdd; + max_transition : 3.5; + capacitance : 0.220548; + rise_capacitance : 0.222529; + rise_capacitance_range (0.196262, 0.239896); + fall_capacitance : 0.218566; + fall_capacitance_range (0.198739, 0.231212); + } + } + cell (sg13g2_IOPadInOut16mA) { + pad_cell : true; + area : 14400; + cell_footprint : "inout"; + pad_drivers : 1; + bond_pads : 1; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 1244.94; + when : "!c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 3844.11; + when : "!c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 1244.94; + when : "!c2p_en&c2p&!pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 4913; + when : "!c2p_en&c2p&!pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 27.4413; + when : "!c2p_en&!c2p&pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 3526.99; + when : "!c2p_en&!c2p&pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 27.4413; + when : "!c2p_en&c2p&pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 4595.94; + when : "!c2p_en&c2p&pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 54.3465; + when : "c2p_en&c2p&pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 4743.21; + when : "c2p_en&c2p&pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 54.3465; + when : "c2p_en&c2p&pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 4743.16; + when : "c2p_en&c2p&pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 1220.31; + when : "c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 3965.07; + when : "c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 1220.31; + when : "c2p_en&!c2p&!pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 3965.08; + when : "c2p_en&!c2p&!pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 636.76; + related_pg_pin : iovdd; + } + leakage_power () { + value : 4287.07; + related_pg_pin : vdd; + } + pin (pad) { + direction : "inout"; + is_pad : true; + function : "c2p"; + three_state : "c2p_en'"; + drive_current : 16; + output_voltage : "pad"; + input_voltage : "pad"; + related_ground_pin : iovss; + related_power_pin : iovdd; + max_capacitance : 6.47325; + capacitance : 0.260161; + rise_capacitance : 0.259789; + rise_capacitance_range (0.231825, 0.278191); + fall_capacitance : 0.260533; + fall_capacitance_range (0.239067, 0.274174); + timing () { + related_pin : "c2p"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.07349, 1.1888, 1.28513, 1.37296, 1.61565, 1.84783", \ + "1.08928, 1.20437, 1.30083, 1.38842, 1.63113, 1.86319", \ + "1.09889, 1.21401, 1.31046, 1.39806, 1.64106, 1.87278", \ + "1.11354, 1.22858, 1.32489, 1.41252, 1.65544, 1.88718", \ + "1.13158, 1.24658, 1.34288, 1.43051, 1.67316, 1.90518", \ + "1.15249, 1.26746, 1.3638, 1.45144, 1.69418, 1.92626", \ + "1.17094, 1.28661, 1.38305, 1.47094, 1.71422, 1.94585" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.381481, 0.537776, 0.685625, 0.832073, 1.27845, 1.73393", \ + "0.381482, 0.537777, 0.685626, 0.832074, 1.27846, 1.73394", \ + "0.381483, 0.537778, 0.685627, 0.832075, 1.27873, 1.73395", \ + "0.381484, 0.537779, 0.685628, 0.832076, 1.27874, 1.7354", \ + "0.381485, 0.53778, 0.685629, 0.832077, 1.27875, 1.73541", \ + "0.381486, 0.537781, 0.68563, 0.832078, 1.27876, 1.7355", \ + "0.382352, 0.53836, 0.686806, 0.833134, 1.27898, 1.73551" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.851984, 0.941528, 1.02216, 1.09847, 1.31919, 1.5392", \ + "0.870278, 0.960186, 1.04057, 1.11696, 1.33671, 1.55736", \ + "0.885063, 0.974565, 1.05525, 1.13171, 1.35109, 1.57139", \ + "0.91476, 1.00419, 1.08489, 1.16082, 1.38041, 1.60073", \ + "0.959751, 1.04959, 1.12996, 1.20624, 1.42581, 1.64616", \ + "1.028, 1.11687, 1.19743, 1.27326, 1.49306, 1.71302", \ + "1.14669, 1.23637, 1.31739, 1.39356, 1.6141, 1.83482" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.436875, 0.549465, 0.669105, 0.793587, 1.19363, 1.61117", \ + "0.441306, 0.552294, 0.672064, 0.795192, 1.19507, 1.61274", \ + "0.44369, 0.554294, 0.673703, 0.797439, 1.19612, 1.61376", \ + "0.444648, 0.556701, 0.675791, 0.79904, 1.19771, 1.61467", \ + "0.445777, 0.556702, 0.675792, 0.799041, 1.19772, 1.61468", \ + "0.445778, 0.556703, 0.675793, 0.799042, 1.19773, 1.61469", \ + "0.445779, 0.556704, 0.675794, 0.799043, 1.19774, 1.6147" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : negative_unate; + timing_type : three_state_disable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.788371, 0.788372, 0.788373, 0.788374, 0.788375, 0.788376", \ + "0.807984, 0.807985, 0.807986, 0.807987, 0.807988, 0.807989", \ + "0.819297, 0.819299, 0.8193, 0.819301, 0.819302, 0.819303", \ + "0.838509, 0.83851, 0.838511, 0.838515, 0.838516, 0.838517", \ + "0.865805, 0.865806, 0.865807, 0.865808, 0.865809, 0.86581", \ + "0.909502, 0.909503, 0.909504, 0.909505, 0.909506, 0.909507", \ + "0.98087, 0.980871, 0.980872, 0.980873, 0.980874, 0.980875" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.788371, 0.788372, 0.788373, 0.788374, 0.788375, 0.788376", \ + "0.807984, 0.807985, 0.807986, 0.807987, 0.807988, 0.807989", \ + "0.819297, 0.819299, 0.8193, 0.819301, 0.819302, 0.819303", \ + "0.838509, 0.83851, 0.838511, 0.838515, 0.838516, 0.838517", \ + "0.865805, 0.865806, 0.865807, 0.865808, 0.865809, 0.86581", \ + "0.909502, 0.909503, 0.909504, 0.909505, 0.909506, 0.909507", \ + "0.98087, 0.980871, 0.980872, 0.980873, 0.980874, 0.980875" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.851468, 0.851469, 0.85147, 0.851471, 0.851472, 0.851473", \ + "0.874056, 0.874057, 0.874058, 0.874059, 0.87406, 0.874061", \ + "0.890629, 0.89063, 0.890631, 0.890632, 0.890633, 0.890634", \ + "0.92, 0.920001, 0.920002, 0.920003, 0.920004, 0.920005", \ + "0.960562, 0.961449, 0.961453, 0.961454, 0.961455, 0.961456", \ + "1.0185, 1.01851, 1.01852, 1.01853, 1.01854, 1.01855", \ + "1.1161, 1.11611, 1.11612, 1.11613, 1.11614, 1.11615" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.851468, 0.851469, 0.85147, 0.851471, 0.851472, 0.851473", \ + "0.874056, 0.874057, 0.874058, 0.874059, 0.87406, 0.874061", \ + "0.890629, 0.89063, 0.890631, 0.890632, 0.890633, 0.890634", \ + "0.92, 0.920001, 0.920002, 0.920003, 0.920004, 0.920005", \ + "0.960562, 0.961449, 0.961453, 0.961454, 0.961455, 0.961456", \ + "1.0185, 1.01851, 1.01852, 1.01853, 1.01854, 1.01855", \ + "1.1161, 1.11611, 1.11612, 1.11613, 1.11614, 1.11615" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : positive_unate; + timing_type : three_state_enable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.06441, 1.18602, 1.28649, 1.37825, 1.63254, 1.87571", \ + "1.08109, 1.20254, 1.30317, 1.39456, 1.64865, 1.89184", \ + "1.09215, 1.2135, 1.3142, 1.4058, 1.65961, 1.9028", \ + "1.10877, 1.22991, 1.33064, 1.42262, 1.676, 1.91929", \ + "1.13046, 1.25183, 1.3524, 1.44416, 1.69838, 1.94161", \ + "1.15605, 1.2774, 1.37796, 1.46958, 1.72381, 1.96705", \ + "1.18378, 1.30516, 1.40566, 1.49718, 1.75128, 1.99542" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.385054, 0.533176, 0.67715, 0.821634, 1.26647, 1.72287", \ + "0.385055, 0.533177, 0.677161, 0.821635, 1.26648, 1.72403", \ + "0.385056, 0.533178, 0.677162, 0.821636, 1.26649, 1.72404", \ + "0.385057, 0.533179, 0.677163, 0.821942, 1.2665, 1.72405", \ + "0.385058, 0.53318, 0.677164, 0.821943, 1.26651, 1.7244", \ + "0.385059, 0.533181, 0.677165, 0.821944, 1.26658, 1.72441", \ + "0.38506, 0.534022, 0.67861, 0.821945, 1.26659, 1.72447" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.725354, 0.832222, 0.926798, 1.01715, 1.27468, 1.52826", \ + "0.741185, 0.848201, 0.942495, 1.03308, 1.29062, 1.54417", \ + "0.749565, 0.857023, 0.950663, 1.04139, 1.29938, 1.55273", \ + "0.762148, 0.869412, 0.963985, 1.05426, 1.31175, 1.5651", \ + "0.777726, 0.884691, 0.978916, 1.06951, 1.32709, 1.58071", \ + "0.794241, 0.898874, 0.993962, 1.08381, 1.34157, 1.59484", \ + "0.807676, 0.914545, 1.00988, 1.09877, 1.35659, 1.61039" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.281953, 0.422772, 0.560079, 0.701393, 1.13031, 1.56641", \ + "0.281954, 0.422807, 0.560866, 0.701394, 1.13032, 1.56832", \ + "0.281961, 0.422808, 0.561085, 0.701395, 1.13043, 1.56833", \ + "0.281962, 0.422809, 0.56216, 0.70169, 1.13044, 1.56834", \ + "0.281963, 0.42281, 0.562161, 0.701691, 1.13045, 1.56835", \ + "0.281964, 0.422811, 0.562162, 0.701692, 1.13054, 1.56963", \ + "0.281965, 0.422812, 0.562192, 0.701693, 1.13055, 1.56964" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "7.95486, 7.85643, 7.82262, 7.77244, 7.62556, 7.43688", \ + "7.97618, 7.8704, 7.83943, 7.77049, 7.63571, 7.44055", \ + "7.97485, 7.8783, 7.839, 7.78086, 7.65853, 7.4493", \ + "7.98282, 7.88521, 7.83972, 7.78468, 7.64946, 7.49707", \ + "7.98581, 7.88573, 7.84289, 7.78424, 7.63776, 7.50341", \ + "7.96932, 7.86901, 7.82939, 7.77031, 7.6279, 7.50388", \ + "7.92175, 7.82421, 7.82417, 7.83133, 7.64737, 7.4102" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "17.7836, 15.7534, 14.3935, 13.3833, 11.5087, 10.3839", \ + "18.0905, 16.0092, 14.622, 13.5839, 11.6653, 10.5301", \ + "18.2861, 16.2011, 14.7746, 13.7262, 11.7717, 10.628", \ + "18.4645, 16.355, 14.9397, 13.8719, 11.895, 10.7239", \ + "18.4265, 16.3126, 14.8947, 13.8331, 11.8678, 10.7018", \ + "18.1914, 16.1001, 14.7, 13.6809, 11.7439, 10.599", \ + "17.2633, 15.2977, 13.9645, 13.0198, 11.18, 10.1559" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.77158, 3.48583, 5.20333, 6.89762, 12.0249, 15.9422", \ + "1.76981, 3.48434, 5.20107, 6.90782, 12.0208, 15.925", \ + "1.77278, 3.48706, 5.20036, 6.91123, 12.0389, 15.9368", \ + "1.77891, 3.49403, 5.20981, 6.9331, 12.0172, 15.8323", \ + "1.80204, 3.51643, 5.23366, 6.9393, 12.0638, 15.685", \ + "1.8535, 3.5692, 5.28374, 6.99425, 12.088, 15.3636", \ + "1.96487, 3.68408, 5.38888, 7.12126, 12.1151, 14.8404" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.214751, 0.214405, 0.214124, 0.213957, 0.213626, 0.212819", \ + "0.213155, 0.212924, 0.21259, 0.212518, 0.211954, 0.21152", \ + "0.215757, 0.215386, 0.215162, 0.21506, 0.214519, 0.214036", \ + "0.224653, 0.22427, 0.224011, 0.22386, 0.223511, 0.222863", \ + "0.248008, 0.247718, 0.247311, 0.247282, 0.246855, 0.245841", \ + "0.300161, 0.299846, 0.299427, 0.29924, 0.298828, 0.297479", \ + "0.409831, 0.409515, 0.409449, 0.409051, 0.408704, 0.406675" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "7.4611, 7.74812, 8.05172, 8.33058, 9.1975, 10.0558", \ + "7.47342, 7.76541, 8.06792, 8.33936, 9.17957, 10.1162", \ + "7.47379, 7.76215, 8.05583, 8.35754, 9.20682, 10.1151", \ + "7.47198, 7.76029, 8.05601, 8.35844, 9.22763, 10.0928", \ + "7.47303, 7.7683, 8.07808, 8.37144, 9.23018, 10.1835", \ + "7.46643, 7.75156, 8.06166, 8.34581, 9.21902, 10.0735", \ + "7.50648, 7.76809, 8.14349, 8.28644, 9.2218, 10.1409" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.98754, 2.9875, 2.98546, 2.98349, 2.97868, 2.98082", \ + "2.98741, 2.98774, 2.98503, 2.98384, 2.97904, 2.98085", \ + "2.98777, 2.9888, 2.98456, 2.98401, 2.97846, 2.97837", \ + "2.98745, 2.98861, 2.98315, 2.98384, 2.97807, 2.978", \ + "2.98886, 2.98904, 2.98603, 2.98503, 2.98037, 2.98201", \ + "2.98806, 2.99018, 2.99019, 2.98699, 2.98491, 2.98321", \ + "2.99094, 2.98933, 2.98964, 2.98367, 2.9802, 2.98266" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.73615, 3.45815, 5.16194, 6.89537, 12.0159, 16.0155", \ + "1.73702, 3.4578, 5.17074, 6.87879, 12.0093, 15.9332", \ + "1.74167, 3.45527, 5.17018, 6.88137, 12.0107, 15.8965", \ + "1.75177, 3.46726, 5.18311, 6.89516, 12.001, 15.8124", \ + "1.77836, 3.49159, 5.19921, 6.91969, 12.0411, 15.8672", \ + "1.83353, 3.54761, 5.26316, 6.97518, 12.0699, 15.3536", \ + "1.95139, 3.66454, 5.38376, 7.0917, 12.1111, 14.8537" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.112217, 0.111785, 0.111529, 0.111446, 0.110851, 0.109917", \ + "0.111908, 0.111514, 0.111245, 0.111233, 0.110575, 0.109506", \ + "0.113833, 0.113639, 0.113055, 0.113125, 0.112648, 0.111677", \ + "0.120166, 0.119811, 0.11942, 0.119467, 0.118873, 0.117807", \ + "0.133369, 0.132939, 0.132603, 0.132598, 0.131952, 0.130571", \ + "0.162843, 0.16186, 0.16154, 0.161413, 0.160966, 0.159336", \ + "0.223835, 0.223566, 0.223094, 0.222788, 0.222311, 0.21968" \ + ); + } + } + } + pin (p2c) { + direction : "output"; + output_voltage : "core"; + function : "pad"; + related_ground_pin : vss; + related_power_pin : vdd; + max_capacitance : 1.27738; + timing () { + related_pin : "pad"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0525178, 0.0647662, 0.0878011, 0.10949, 0.130581, 0.151437", \ + "0.0525188, 0.0647672, 0.0878021, 0.109491, 0.130582, 0.151438", \ + "0.0525198, 0.0647682, 0.0878031, 0.109492, 0.130583, 0.151439", \ + "0.0525208, 0.0647692, 0.0878041, 0.109493, 0.130584, 0.15144", \ + "0.0525218, 0.0647702, 0.0878051, 0.109494, 0.130585, 0.151441", \ + "0.0525228, 0.0647712, 0.0878061, 0.109495, 0.130586, 0.151442", \ + "0.0525238, 0.0647722, 0.0878071, 0.109496, 0.130587, 0.151443" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0428776, 0.0652529, 0.109341, 0.153788, 0.198556, 0.243446", \ + "0.0456634, 0.067104, 0.111442, 0.156899, 0.201625, 0.246515", \ + "0.0507684, 0.0713047, 0.113908, 0.157873, 0.20273, 0.247936", \ + "0.05348, 0.0736078, 0.115651, 0.158968, 0.203438, 0.24821", \ + "0.0656314, 0.0848857, 0.124968, 0.16655, 0.208803, 0.252638", \ + "0.0863222, 0.105036, 0.142349, 0.181744, 0.2222, 0.263611", \ + "0.102752, 0.122174, 0.157497, 0.194492, 0.233546, 0.27411" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.299806, 0.317616, 0.345423, 0.368693, 0.389274, 0.409759", \ + "0.354133, 0.371973, 0.399704, 0.422727, 0.444064, 0.463459", \ + "0.476433, 0.494265, 0.522063, 0.545002, 0.566303, 0.586188", \ + "0.537112, 0.554926, 0.582593, 0.605445, 0.626777, 0.646257", \ + "0.855219, 0.872785, 0.900325, 0.923634, 0.944245, 0.964742", \ + "1.49723, 1.51534, 1.54281, 1.56603, 1.58706, 1.6058", \ + "2.05912, 2.07924, 2.11018, 2.13514, 2.15708, 2.17756" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0850931, 0.103406, 0.136334, 0.168469, 0.200247, 0.233512", \ + "0.0850941, 0.103407, 0.136335, 0.16847, 0.200653, 0.233513", \ + "0.0850951, 0.103408, 0.136336, 0.168471, 0.200654, 0.233514", \ + "0.0850961, 0.103409, 0.136337, 0.168472, 0.200655, 0.233515", \ + "0.0850971, 0.10341, 0.136338, 0.168473, 0.200656, 0.233522", \ + "0.098665, 0.116297, 0.147045, 0.177029, 0.208535, 0.239982", \ + "0.120057, 0.137684, 0.168617, 0.197608, 0.226783, 0.256901" \ + ); + } + } + internal_power () { + related_pin : "pad"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "-0.696083, -0.696081, -0.695761, -0.696091, -0.696124, -0.696136", \ + "-0.696794, -0.696804, -0.696822, -0.696419, -0.696867, -0.696902", \ + "-0.696691, -0.696693, -0.696702, -0.696713, -0.696729, -0.696744", \ + "-0.696307, -0.69573, -0.69632, -0.696337, -0.696349, -0.696401", \ + "-0.696274, -0.695969, -0.696222, -0.69621, -0.69621, -0.696211", \ + "-0.693954, -0.693593, -0.693744, -0.693578, -0.694415, -0.695328", \ + "-0.307937, -0.308426, -0.308189, -0.308528, -0.312327, -0.306482" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.696083, 0.696081, 0.696079, 0.696091, 0.696124, 0.696136", \ + "0.696794, 0.696804, 0.696823, 0.696843, 0.696867, 0.696902", \ + "0.696691, 0.696693, 0.696702, 0.696713, 0.696729, 0.696744", \ + "0.696307, 0.69631, 0.69632, 0.696337, 0.696349, 0.696401", \ + "0.696274, 0.69625, 0.696222, 0.69621, 0.69621, 0.696211", \ + "0.693954, 0.693593, 0.693744, 0.693578, 0.694415, 0.695328", \ + "0.695005, 0.694358, 0.693515, 0.693063, 0.694242, 0.693029" \ + ); + } + } + internal_power () { + related_pin : "pad"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "-0.000837553, -0.000733155, -0.000763621, -0.000872112, -0.000835298, -0.00111275", \ + "-0.00179659, -0.0012922, -0.00139062, -0.00168708, -0.00216929, -0.0022993", \ + "-0.0022667, -0.0022508, -0.00235831, -0.00221455, -0.00234802, -0.002758", \ + "-0.00226639, -0.00231972, -0.00258588, -0.00299652, -0.00253519, -0.00242787", \ + "-0.00196103, -0.00229428, -0.00247064, -0.00291877, -0.00389427, -0.00452719", \ + "0.000183506, -0.00118556, -0.000888625, -0.0011439, -0.00148329, -0.00251327", \ + "0.0468397, 0.0449674, 0.0432474, 0.042692, 0.0437882, 0.0412237" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0675916, 0.0664836, 0.0662619, 0.0663988, 0.0665479, 0.0666604", \ + "0.0666562, 0.0655369, 0.0652573, 0.0653704, 0.0655118, 0.0656186", \ + "0.0660687, 0.0649275, 0.0646004, 0.0646644, 0.0647692, 0.0648502", \ + "0.066105, 0.0650316, 0.0646434, 0.0646697, 0.0647602, 0.0648664", \ + "0.0663404, 0.0650966, 0.0645183, 0.064426, 0.0644338, 0.0644526", \ + "0.0692452, 0.067964, 0.0656612, 0.0648731, 0.0648982, 0.0650302", \ + "0.0742733, 0.071081, 0.0684508, 0.0673765, 0.0668071, 0.0663362" \ + ); + } + } + } + pin (c2p) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.016; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0299879; + rise_capacitance : 0.0300679; + rise_capacitance_range (0.0240635, 0.0340879); + fall_capacitance : 0.0299078; + fall_capacitance_range (0.0246689, 0.0330278); + internal_power () { + when : "(!c2p_en * pad * p2c)"; + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-1.0595e-05, -4.72573e-06, -6.17116e-06, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "1.0595e-05, 4.72573e-06, 6.17116e-06, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + when : "(!c2p_en * pad * p2c)"; + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0215189, -0.0224595, -0.0225904, -0.0225479, -0.0228347, -0.0227621, -0.0228348" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0286057, 0.0281311, 0.0284957, 0.0283702, 0.0282106, 0.0279653, 0.027811" \ + ); + } + } + internal_power () { + when : "(!c2p_en * !pad * !p2c)"; + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-1.05147e-05, -4.72445e-06, -6.18168e-06, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "1.05147e-05, 4.72445e-06, 6.18168e-06, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + when : "(!c2p_en * !pad * !p2c)"; + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0215165, -0.0224586, -0.0225893, -0.0225472, -0.0228346, -0.0227622, -0.0228349" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0286039, 0.02813, 0.0284951, 0.02837, 0.0282104, 0.0279652, 0.0278109" \ + ); + } + } + internal_power () { + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-1.05147e-05, -4.72445e-06, -6.18168e-06, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "1.05147e-05, 4.72445e-06, 6.18168e-06, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0215165, -0.0224586, -0.0225893, -0.0225472, -0.0228346, -0.0227622, -0.0228349" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0286039, 0.02813, 0.0284951, 0.02837, 0.0282104, 0.0279652, 0.0278109" \ + ); + } + } + } + pin (c2p_en) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.011; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0269153; + rise_capacitance : 0.0277693; + rise_capacitance_range (0.023155, 0.0335066); + fall_capacitance : 0.0260612; + fall_capacitance_range (0.022145, 0.0296985); + internal_power () { + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "2.07018, 2.0702, 2.0735, 2.07491, 2.07102, 2.08049, 2.07712" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.351858, 0.351235, 0.350431, 0.350044, 0.349117, 0.348846, 0.347964" \ + ); + } + } + internal_power () { + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0402604, 0.0397503, 0.0417318, 0.0480681, 0.0612338, 0.0910797, 0.156348" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.101475, 0.102542, 0.105062, 0.110746, 0.124548, 0.154403, 0.219086" \ + ); + } + } + } + } + cell (sg13g2_IOPadInOut30mA) { + pad_cell : true; + area : 14400; + cell_footprint : "inout"; + pad_drivers : 1; + bond_pads : 1; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 2119.76; + when : "!c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 3843.65; + when : "!c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 2119.76; + when : "!c2p_en&c2p&!pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 4912.45; + when : "!c2p_en&c2p&!pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 0; + when : "!c2p_en&!c2p&pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 3526.63; + when : "!c2p_en&!c2p&pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 0; + when : "!c2p_en&c2p&pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 4595.59; + when : "!c2p_en&c2p&pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 0; + when : "c2p_en&c2p&pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 4742.76; + when : "c2p_en&c2p&pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 0; + when : "c2p_en&c2p&pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 4742.81; + when : "c2p_en&c2p&pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 2095.16; + when : "c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 3964.62; + when : "c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 2095.16; + when : "c2p_en&!c2p&!pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 3964.61; + when : "c2p_en&!c2p&!pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 1053.73; + related_pg_pin : iovdd; + } + leakage_power () { + value : 4286.64; + related_pg_pin : vdd; + } + pin (pad) { + direction : "inout"; + is_pad : true; + function : "c2p"; + three_state : "c2p_en'"; + drive_current : 30; + output_voltage : "pad"; + input_voltage : "pad"; + related_ground_pin : iovss; + related_power_pin : iovdd; + max_capacitance : 9.99915; + capacitance : 0.344807; + rise_capacitance : 0.3422; + rise_capacitance_range (0.312154, 0.362295); + fall_capacitance : 0.347414; + fall_capacitance_range (0.323933, 0.362627); + timing () { + related_pin : "c2p"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.24498, 1.34771, 1.43209, 1.50564, 1.69033, 1.84711", \ + "1.25847, 1.36076, 1.445, 1.51848, 1.70311, 1.85982", \ + "1.27069, 1.37256, 1.45681, 1.52948, 1.714, 1.87078", \ + "1.28432, 1.38639, 1.47033, 1.54368, 1.7283, 1.88491", \ + "1.30132, 1.4031, 1.487, 1.5604, 1.74487, 1.90153", \ + "1.32223, 1.42395, 1.50859, 1.5821, 1.76678, 1.92348", \ + "1.33904, 1.44226, 1.52709, 1.60077, 1.7857, 1.94247" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.366058, 0.492082, 0.597318, 0.69119, 0.943224, 1.18335", \ + "0.366059, 0.492083, 0.597319, 0.691191, 0.94338, 1.18336", \ + "0.36606, 0.492084, 0.59732, 0.691192, 0.943381, 1.18337", \ + "0.366061, 0.492085, 0.597321, 0.691193, 0.943646, 1.18338", \ + "0.366062, 0.492086, 0.597322, 0.691194, 0.943647, 1.18339", \ + "0.366063, 0.492205, 0.597323, 0.691195, 0.943751, 1.1834", \ + "0.367108, 0.494516, 0.597898, 0.691828, 0.944408, 1.18341" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.05455, 1.11567, 1.17172, 1.22419, 1.36627, 1.49708", \ + "1.07318, 1.13427, 1.1903, 1.24142, 1.38495, 1.51582", \ + "1.08792, 1.14813, 1.20466, 1.25709, 1.39875, 1.52957", \ + "1.11742, 1.1788, 1.23473, 1.28556, 1.42922, 1.56004", \ + "1.1624, 1.22383, 1.27981, 1.3309, 1.47439, 1.60529", \ + "1.23033, 1.29115, 1.34685, 1.399, 1.54115, 1.6717", \ + "1.34796, 1.40959, 1.46573, 1.51819, 1.6586, 1.78985" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.688101, 0.726369, 0.779665, 0.837845, 1.01174, 1.19409", \ + "0.692845, 0.730565, 0.783477, 0.841263, 1.01518, 1.19697", \ + "0.695684, 0.733089, 0.786998, 0.844648, 1.01644, 1.19698", \ + "0.699671, 0.736694, 0.789186, 0.844649, 1.0199, 1.20142", \ + "0.699672, 0.736695, 0.789187, 0.845831, 1.01991, 1.20143", \ + "0.699673, 0.736696, 0.789188, 0.845832, 1.01992, 1.20144", \ + "0.699674, 0.736697, 0.789189, 0.845833, 1.01993, 1.20145" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : negative_unate; + timing_type : three_state_disable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.950233, 0.950234, 0.950235, 0.950236, 0.950237, 0.950238", \ + "0.970383, 0.970384, 0.970385, 0.970386, 0.970387, 0.970388", \ + "0.979081, 0.979082, 0.979083, 0.979084, 0.979085, 0.979086", \ + "0.999339, 0.999343, 0.999344, 0.999345, 0.999346, 0.999347", \ + "1.0277, 1.02771, 1.02772, 1.02773, 1.02774, 1.02775", \ + "1.07051, 1.07052, 1.07053, 1.07054, 1.07055, 1.07056", \ + "1.1429, 1.14291, 1.14292, 1.14293, 1.14294, 1.14295" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.950233, 0.950234, 0.950235, 0.950236, 0.950237, 0.950238", \ + "0.970383, 0.970384, 0.970385, 0.970386, 0.970387, 0.970388", \ + "0.979081, 0.979082, 0.979083, 0.979084, 0.979085, 0.979086", \ + "0.999339, 0.999343, 0.999344, 0.999345, 0.999346, 0.999347", \ + "1.0277, 1.02771, 1.02772, 1.02773, 1.02774, 1.02775", \ + "1.07051, 1.07052, 1.07053, 1.07054, 1.07055, 1.07056", \ + "1.1429, 1.14291, 1.14292, 1.14293, 1.14294, 1.14295" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.27373, 1.27374, 1.27375, 1.27376, 1.27377, 1.27378", \ + "1.28774, 1.28775, 1.28776, 1.28777, 1.28778, 1.28779", \ + "1.30306, 1.32133, 1.32134, 1.32135, 1.32136, 1.32137", \ + "1.3343, 1.35124, 1.35125, 1.35126, 1.35127, 1.35128", \ + "1.38336, 1.38544, 1.38545, 1.38546, 1.38547, 1.38548", \ + "1.44688, 1.44689, 1.4469, 1.44691, 1.44692, 1.44693", \ + "1.5367, 1.53671, 1.53672, 1.53673, 1.53674, 1.53675" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.27373, 1.27374, 1.27375, 1.27376, 1.27377, 1.27378", \ + "1.28774, 1.28775, 1.28776, 1.28777, 1.28778, 1.28779", \ + "1.30306, 1.32133, 1.32134, 1.32135, 1.32136, 1.32137", \ + "1.3343, 1.35124, 1.35125, 1.35126, 1.35127, 1.35128", \ + "1.38336, 1.38544, 1.38545, 1.38546, 1.38547, 1.38548", \ + "1.44688, 1.44689, 1.4469, 1.44691, 1.44692, 1.44693", \ + "1.5367, 1.53671, 1.53672, 1.53673, 1.53674, 1.53675" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : positive_unate; + timing_type : three_state_enable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.2093, 1.32777, 1.41986, 1.49833, 1.69198, 1.85536", \ + "1.22593, 1.34431, 1.43652, 1.51489, 1.70863, 1.87214", \ + "1.23574, 1.35434, 1.44646, 1.52477, 1.71844, 1.88181", \ + "1.25217, 1.37071, 1.46293, 1.5413, 1.73505, 1.89859", \ + "1.27402, 1.39246, 1.48459, 1.56297, 1.75662, 1.92054", \ + "1.29994, 1.41826, 1.51048, 1.58884, 1.78261, 1.94585", \ + "1.32922, 1.4477, 1.53993, 1.61821, 1.81184, 1.97474" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.397225, 0.50701, 0.601175, 0.687804, 0.929253, 1.16315", \ + "0.39731, 0.50736, 0.601485, 0.688305, 0.929254, 1.16328", \ + "0.397341, 0.507361, 0.601486, 0.688306, 0.929255, 1.16329", \ + "0.397743, 0.507454, 0.601487, 0.688307, 0.929256, 1.16332", \ + "0.397744, 0.507455, 0.601488, 0.688308, 0.929257, 1.16366", \ + "0.397745, 0.507456, 0.601489, 0.688309, 0.929258, 1.16367", \ + "0.397746, 0.50884, 0.60149, 0.68831, 0.929259, 1.16368" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.75858, 0.843905, 0.915343, 0.978017, 1.14477, 1.29416", \ + "0.774265, 0.859951, 0.930447, 0.993437, 1.15974, 1.31098", \ + "0.782773, 0.868625, 0.938972, 1.00214, 1.16903, 1.31929", \ + "0.795346, 0.880906, 0.952418, 1.01495, 1.18182, 1.33114", \ + "0.810986, 0.896123, 0.967655, 1.03014, 1.19714, 1.34679", \ + "0.825253, 0.910978, 0.980911, 1.04485, 1.21024, 1.36067", \ + "0.840202, 0.925799, 0.996827, 1.06064, 1.22655, 1.37814" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.259579, 0.347553, 0.424801, 0.505057, 0.727076, 0.948921", \ + "0.25958, 0.347554, 0.428072, 0.505058, 0.727077, 0.948922", \ + "0.259581, 0.348083, 0.428073, 0.505059, 0.727701, 0.948923", \ + "0.259582, 0.348084, 0.428074, 0.50506, 0.727702, 0.948924", \ + "0.259583, 0.348085, 0.428596, 0.505061, 0.727703, 0.948925", \ + "0.259584, 0.348086, 0.428597, 0.505062, 0.727704, 0.949087", \ + "0.259585, 0.348087, 0.428598, 0.505428, 0.729932, 0.949998" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "13.2866, 12.9093, 12.7024, 12.5789, 12.2466, 12.1378", \ + "13.3232, 12.922, 12.7111, 12.5853, 12.3243, 12.1734", \ + "13.3588, 12.9424, 12.7209, 12.6137, 12.2852, 12.171", \ + "13.3619, 12.9644, 12.739, 12.6126, 12.3691, 12.0354", \ + "13.3896, 12.9819, 12.7423, 12.6159, 12.2729, 12.1222", \ + "13.3087, 12.8997, 12.686, 12.5616, 12.3143, 12.129", \ + "13.216, 12.8271, 12.5456, 12.4654, 12.2556, 12.01" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "71.2329, 67.0105, 63.4667, 60.4042, 53.3443, 48.2074", \ + "71.8631, 67.6161, 64.045, 61.0216, 53.8464, 48.6514", \ + "72.3102, 68.0909, 64.5331, 61.4438, 54.267, 49.0578", \ + "72.7538, 68.5034, 64.9071, 61.8335, 54.5969, 49.3516", \ + "72.6379, 68.3906, 64.7913, 61.746, 54.4984, 49.2479", \ + "72.0314, 67.882, 64.3299, 61.2598, 54.1739, 48.9971", \ + "69.9477, 65.8342, 62.3361, 59.3632, 52.408, 47.3788" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.77008, 3.49101, 5.21874, 6.92314, 11.8577, 12.8561", \ + "1.76777, 3.48914, 5.2155, 6.93754, 11.8195, 12.8425", \ + "1.77033, 3.49211, 5.21936, 6.91436, 11.7748, 12.7071", \ + "1.77718, 3.50095, 5.22723, 6.92502, 11.767, 12.4658", \ + "1.79971, 3.52488, 5.24144, 6.96245, 11.803, 12.1373", \ + "1.85126, 3.57659, 5.30262, 7.01989, 11.6195, 11.4605", \ + "1.96394, 3.68573, 5.40527, 7.12234, 11.268, 9.76035" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.21459, 0.214267, 0.214187, 0.214151, 0.21371, 0.21211", \ + "0.213071, 0.212727, 0.21265, 0.212563, 0.212171, 0.210515", \ + "0.215518, 0.215361, 0.215157, 0.215138, 0.214761, 0.21297", \ + "0.224441, 0.224157, 0.224023, 0.22389, 0.223596, 0.221631", \ + "0.247784, 0.247511, 0.24742, 0.247289, 0.246878, 0.244635", \ + "0.30019, 0.299799, 0.299643, 0.299521, 0.298975, 0.296024", \ + "0.410056, 0.409674, 0.409144, 0.409371, 0.408769, 0.403935" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "11.3954, 11.708, 12.013, 12.3342, 13.2561, 14.1276", \ + "11.3879, 11.6945, 12.0185, 12.3418, 13.173, 14.135", \ + "11.382, 11.6817, 11.9963, 12.3074, 13.1931, 14.1104", \ + "11.3725, 11.6802, 11.994, 12.3213, 13.1848, 14.1219", \ + "11.3926, 11.6974, 12.0178, 12.3408, 13.2663, 14.1459", \ + "11.385, 11.6787, 12.0076, 12.3121, 13.1847, 14.014", \ + "11.4162, 11.8018, 11.9814, 12.3089, 13.1863, 13.9543" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "4.99672, 4.99671, 4.99634, 5.00142, 5.00028, 4.99404", \ + "4.98985, 4.99326, 4.99969, 4.99974, 4.99861, 4.99744", \ + "4.99299, 5.00415, 4.99936, 5.00018, 4.99864, 4.99755", \ + "4.99422, 4.99716, 4.9985, 5.00174, 5.00144, 4.99519", \ + "4.99213, 4.99776, 5.00422, 5.00232, 5.0026, 4.99694", \ + "4.9893, 4.98901, 4.99663, 4.99783, 4.998, 4.99548", \ + "5.0039, 5.0026, 5.0008, 5.01263, 5.00304, 5.00366" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.7367, 3.4622, 5.18716, 6.9095, 11.7663, 12.7184", \ + "1.73627, 3.46031, 5.1798, 6.9134, 11.8059, 12.8156", \ + "1.74083, 3.46443, 5.18431, 6.9098, 11.7577, 12.6568", \ + "1.75252, 3.47619, 5.19687, 6.92217, 11.7349, 12.4989", \ + "1.77769, 3.50352, 5.22956, 6.94402, 11.6622, 12.1555", \ + "1.83475, 3.5605, 5.27888, 6.99446, 11.6684, 11.2305", \ + "1.94882, 3.67714, 5.39981, 7.10637, 11.2228, 9.53586" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.112372, 0.111952, 0.111947, 0.111574, 0.111064, 0.106684", \ + "0.112077, 0.111727, 0.111492, 0.111253, 0.110671, 0.106633", \ + "0.114133, 0.113784, 0.113407, 0.113225, 0.112668, 0.108375", \ + "0.1202, 0.119896, 0.119781, 0.119508, 0.118806, 0.114202", \ + "0.133514, 0.133068, 0.133039, 0.132664, 0.131857, 0.127078", \ + "0.163153, 0.162795, 0.162204, 0.162504, 0.161142, 0.1558", \ + "0.224876, 0.224645, 0.224613, 0.224436, 0.221941, 0.215247" \ + ); + } + } + } + pin (p2c) { + direction : "output"; + output_voltage : "core"; + function : "pad"; + related_ground_pin : vss; + related_power_pin : vdd; + max_capacitance : 1.2785; + timing () { + related_pin : "pad"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0525071, 0.0648283, 0.0878589, 0.109624, 0.130626, 0.151511", \ + "0.0525081, 0.0648293, 0.0878599, 0.109625, 0.130627, 0.151512", \ + "0.0525091, 0.0648303, 0.0878609, 0.109626, 0.130628, 0.151513", \ + "0.0525101, 0.0648313, 0.0878619, 0.109627, 0.130629, 0.151514", \ + "0.0525111, 0.0648323, 0.0878629, 0.109628, 0.13063, 0.151515", \ + "0.0525121, 0.0648333, 0.0878639, 0.109629, 0.130631, 0.151516", \ + "0.0525131, 0.0648343, 0.0878649, 0.10963, 0.130632, 0.151517" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.042848, 0.0652991, 0.109404, 0.153768, 0.198612, 0.243616", \ + "0.0456753, 0.0669385, 0.111351, 0.156901, 0.201644, 0.246459", \ + "0.0507853, 0.0712618, 0.113948, 0.157946, 0.20283, 0.247858", \ + "0.053502, 0.0736067, 0.115587, 0.159027, 0.203468, 0.248346", \ + "0.0656324, 0.0848908, 0.125081, 0.166485, 0.208772, 0.252563", \ + "0.0862527, 0.105213, 0.142577, 0.181686, 0.221267, 0.263516", \ + "0.102848, 0.122266, 0.157679, 0.194192, 0.233014, 0.274181" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.299816, 0.317589, 0.345405, 0.368696, 0.389213, 0.409299", \ + "0.354193, 0.371996, 0.400293, 0.423389, 0.444119, 0.464551", \ + "0.476354, 0.494109, 0.521824, 0.545023, 0.565596, 0.586132", \ + "0.527152, 0.544944, 0.572519, 0.595849, 0.616932, 0.636727", \ + "0.847297, 0.864994, 0.892602, 0.915755, 0.936748, 0.95673", \ + "1.49737, 1.51579, 1.54392, 1.56702, 1.58817, 1.60723", \ + "2.05943, 2.07939, 2.11013, 2.13509, 2.15709, 2.17754" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0851105, 0.103595, 0.136267, 0.168402, 0.200169, 0.23311", \ + "0.0851115, 0.103596, 0.136268, 0.168403, 0.200312, 0.233387", \ + "0.0851125, 0.103597, 0.136269, 0.168404, 0.200313, 0.233477", \ + "0.0851135, 0.103598, 0.13627, 0.168405, 0.200518, 0.233478", \ + "0.085156, 0.103654, 0.136671, 0.168922, 0.201083, 0.233888", \ + "0.098662, 0.11586, 0.146245, 0.176856, 0.208316, 0.23946", \ + "0.119939, 0.137551, 0.168789, 0.197714, 0.226865, 0.256946" \ + ); + } + } + internal_power () { + related_pin : "pad"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "-1.32371, -1.32368, -1.32095, -1.32371, -1.32377, -1.32383", \ + "-1.32645, -1.32649, -1.32434, -1.32418, -1.32373, -1.31855", \ + "-1.32479, -1.32475, -1.32479, -1.32481, -1.32486, -1.32491", \ + "-1.32437, -1.32435, -1.3244, -1.32441, -1.32446, -1.32451", \ + "-1.32333, -1.32379, -1.32447, -1.32501, -1.32547, -1.32554", \ + "-1.31934, -1.31908, -1.31974, -1.31874, -1.32023, -1.32158", \ + "-0.592167, -0.593345, -0.593014, -0.591661, -0.590571, -0.590444" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "1.32371, 1.32368, 1.32367, 1.32371, 1.32377, 1.32383", \ + "1.32645, 1.32649, 1.32704, 1.32707, 1.32712, 1.32715", \ + "1.32479, 1.32475, 1.32479, 1.32481, 1.32486, 1.32491", \ + "1.32437, 1.32435, 1.3244, 1.32441, 1.32446, 1.32451", \ + "1.32333, 1.32379, 1.32447, 1.32501, 1.32547, 1.32554", \ + "1.31934, 1.31908, 1.31974, 1.31874, 1.32023, 1.32158", \ + "1.32134, 1.32033, 1.31852, 1.31763, 1.31989, 1.31754" \ + ); + } + } + internal_power () { + related_pin : "pad"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "-0.00091806, -0.000777639, -0.000825793, -0.000739056, -0.000881366, -0.00117162", \ + "-0.00180563, -0.00115165, -0.00118853, -0.00149053, -0.00188549, -0.00183334", \ + "-0.00227847, -0.00221005, -0.00226288, -0.00223871, -0.00228835, -0.00284235", \ + "-0.00227736, -0.00238207, -0.00258562, -0.00297883, -0.00252807, -0.00242879", \ + "-0.00196895, -0.00232981, -0.00207372, -0.00293527, -0.00427139, -0.00444021", \ + "0.00030162, -0.000984641, -0.000781705, -0.00141542, -0.00274864, -0.00137807", \ + "0.0463354, 0.0444606, 0.0428718, 0.0416118, 0.0404202, 0.0406053" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0704139, 0.0693572, 0.0690701, 0.0692101, 0.0693486, 0.0694601", \ + "0.0696314, 0.0684831, 0.0682583, 0.0683578, 0.0684904, 0.0686003", \ + "0.0690308, 0.0679825, 0.0676328, 0.0676912, 0.0677916, 0.0678851", \ + "0.0682652, 0.0671019, 0.0666951, 0.0667106, 0.0667703, 0.0668191", \ + "0.0693605, 0.0681328, 0.0675695, 0.0674664, 0.0674599, 0.0674526", \ + "0.0721149, 0.0700468, 0.0686103, 0.0680854, 0.06787, 0.0677704", \ + "0.0761963, 0.0734664, 0.0713199, 0.0701914, 0.0695827, 0.0691152" \ + ); + } + } + } + pin (c2p) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.016; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.029988; + rise_capacitance : 0.0300681; + rise_capacitance_range (0.0240636, 0.0340916); + fall_capacitance : 0.0299078; + fall_capacitance_range (0.024669, 0.0330278); + internal_power () { + when : "(!c2p_en * pad * p2c)"; + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-9.5169e-06, -4.13135e-06, -6.01105e-06, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "9.5169e-06, 4.13135e-06, 6.01105e-06, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + when : "(!c2p_en * pad * p2c)"; + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0215188, -0.0224595, -0.0225904, -0.0225476, -0.0228347, -0.0227621, -0.0228348" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0286056, 0.0281312, 0.0284957, 0.0283703, 0.0282106, 0.0279654, 0.027811" \ + ); + } + } + internal_power () { + when : "(!c2p_en * !pad * !p2c)"; + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-9.42452e-06, -4.09958e-06, -6.01012e-06, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "9.42452e-06, 4.09958e-06, 6.01012e-06, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + when : "(!c2p_en * !pad * !p2c)"; + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0215165, -0.0224586, -0.0225893, -0.0225469, -0.0228345, -0.0227622, -0.0228349" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0286038, 0.0281301, 0.0284951, 0.02837, 0.0282104, 0.0279652, 0.0278109" \ + ); + } + } + internal_power () { + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-9.42452e-06, -4.09958e-06, -6.01012e-06, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "9.42452e-06, 4.09958e-06, 6.01012e-06, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0215165, -0.0224586, -0.0225893, -0.0225469, -0.0228345, -0.0227622, -0.0228349" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0286038, 0.0281301, 0.0284951, 0.02837, 0.0282104, 0.0279652, 0.0278109" \ + ); + } + } + } + pin (c2p_en) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.011; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0269102; + rise_capacitance : 0.0277591; + rise_capacitance_range (0.023155, 0.0335044); + fall_capacitance : 0.0260613; + fall_capacitance_range (0.0221451, 0.0296416); + internal_power () { + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "3.2791, 3.27884, 3.27863, 3.27952, 3.27865, 3.27359, 3.29028" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.334507, 0.333787, 0.333639, 0.332725, 0.332561, 0.33132, 0.330624" \ + ); + } + } + internal_power () { + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0402581, 0.0397475, 0.0417297, 0.0480681, 0.0612353, 0.0909499, 0.156315" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.101471, 0.102534, 0.105058, 0.110742, 0.124499, 0.154339, 0.219104" \ + ); + } + } + } + } + cell (sg13g2_IOPadInOut4mA) { + pad_cell : true; + area : 14400; + cell_footprint : "inout"; + pad_drivers : 1; + bond_pads : 1; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 396.411; + when : "!c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 3844.58; + when : "!c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 396.113; + when : "!c2p_en&c2p&!pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 4913.42; + when : "!c2p_en&c2p&!pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 7.07672; + when : "!c2p_en&!c2p&pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 3527.98; + when : "!c2p_en&!c2p&pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 7.12881; + when : "!c2p_en&c2p&pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 4596.94; + when : "!c2p_en&c2p&pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 32.7753; + when : "c2p_en&c2p&pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 4744.15; + when : "c2p_en&c2p&pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 32.624; + when : "c2p_en&c2p&pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 4744.15; + when : "c2p_en&c2p&pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 371.516; + when : "c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 3965.55; + when : "c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 371.5; + when : "c2p_en&!c2p&!pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 3965.55; + when : "c2p_en&!c2p&!pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 201.893; + related_pg_pin : iovdd; + } + leakage_power () { + value : 4287.79; + related_pg_pin : vdd; + } + pin (pad) { + direction : "inout"; + is_pad : true; + function : "c2p"; + three_state : "c2p_en'"; + drive_current : 4; + output_voltage : "pad"; + input_voltage : "pad"; + related_ground_pin : iovss; + related_power_pin : iovdd; + max_capacitance : 1.65074; + capacitance : 0.187243; + rise_capacitance : 0.188648; + rise_capacitance_range (0.162168, 0.206099); + fall_capacitance : 0.185839; + fall_capacitance_range (0.16571, 0.198556); + timing () { + related_pin : "c2p"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.05733, 1.36151, 1.66373, 1.96535, 2.86901, 3.77236", \ + "1.07278, 1.37692, 1.67913, 1.98075, 2.88436, 3.7878", \ + "1.08211, 1.38629, 1.68851, 1.99013, 2.8938, 3.79707", \ + "1.09675, 1.4009, 1.70312, 2.00477, 2.90837, 3.8119", \ + "1.11557, 1.41984, 1.72205, 2.02371, 2.92727, 3.83095", \ + "1.13589, 1.44021, 1.74245, 2.04411, 2.94769, 3.85115", \ + "1.156, 1.46029, 1.76258, 2.06427, 2.96801, 3.87108" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.795011, 1.4171, 2.04666, 2.67907, 4.56845, 6.45816", \ + "0.795012, 1.41746, 2.04769, 2.67908, 4.5717, 6.45817", \ + "0.795013, 1.41747, 2.0477, 2.67909, 4.57171, 6.45915", \ + "0.795014, 1.41748, 2.04771, 2.6791, 4.57184, 6.45916", \ + "0.795015, 1.41749, 2.04772, 2.67911, 4.57185, 6.4597", \ + "0.795016, 1.4175, 2.04773, 2.67912, 4.57282, 6.45971", \ + "0.802156, 1.41751, 2.04774, 2.67913, 4.57283, 6.45972" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.890894, 1.19918, 1.5068, 1.81386, 2.73587, 3.65871", \ + "0.906886, 1.21477, 1.52223, 1.82947, 2.75128, 3.6737", \ + "0.921317, 1.22898, 1.53639, 1.8435, 2.76542, 3.68771", \ + "0.9492, 1.25664, 1.56413, 1.87113, 2.79296, 3.71517", \ + "0.994752, 1.30244, 1.60991, 1.91693, 2.83841, 3.76346", \ + "1.06362, 1.37142, 1.67888, 1.98608, 2.9079, 3.82951", \ + "1.18823, 1.49684, 1.80434, 2.11127, 3.033, 3.95398" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.729846, 1.31741, 1.90854, 2.50115, 4.27153, 6.05691", \ + "0.730099, 1.31781, 1.90867, 2.50116, 4.27154, 6.05719", \ + "0.730291, 1.31861, 1.90868, 2.50117, 4.27184, 6.0572", \ + "0.730489, 1.32029, 1.90869, 2.50118, 4.27197, 6.05721", \ + "0.73049, 1.3203, 1.9087, 2.50119, 4.28022, 6.05722", \ + "0.730491, 1.32031, 1.90871, 2.5012, 4.28023, 6.05723", \ + "0.733056, 1.32032, 1.91035, 2.50688, 4.28024, 6.05724" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : negative_unate; + timing_type : three_state_disable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.630659, 0.63066, 0.630661, 0.630662, 0.630663, 0.630664", \ + "0.651345, 0.651346, 0.651347, 0.651348, 0.651349, 0.65135", \ + "0.663346, 0.663357, 0.66336, 0.663363, 0.663366, 0.663367", \ + "0.682244, 0.682245, 0.682246, 0.682247, 0.682248, 0.682249", \ + "0.712698, 0.712699, 0.7127, 0.712701, 0.712702, 0.712703", \ + "0.755432, 0.755441, 0.755445, 0.755446, 0.755447, 0.755448", \ + "0.825725, 0.825726, 0.825727, 0.825728, 0.825729, 0.82573" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.630659, 0.63066, 0.630661, 0.630662, 0.630663, 0.630664", \ + "0.651345, 0.651346, 0.651347, 0.651348, 0.651349, 0.65135", \ + "0.663346, 0.663357, 0.66336, 0.663363, 0.663366, 0.663367", \ + "0.682244, 0.682245, 0.682246, 0.682247, 0.682248, 0.682249", \ + "0.712698, 0.712699, 0.7127, 0.712701, 0.712702, 0.712703", \ + "0.755432, 0.755441, 0.755445, 0.755446, 0.755447, 0.755448", \ + "0.825725, 0.825726, 0.825727, 0.825728, 0.825729, 0.82573" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.488887, 0.488888, 0.488889, 0.48889, 0.488891, 0.488892", \ + "0.51021, 0.510211, 0.510212, 0.510213, 0.510214, 0.510215", \ + "0.526899, 0.526977, 0.526978, 0.526979, 0.52698, 0.526981", \ + "0.555973, 0.555976, 0.555977, 0.555978, 0.555979, 0.55598", \ + "0.597018, 0.597019, 0.59702, 0.597021, 0.597022, 0.597023", \ + "0.658881, 0.658882, 0.658883, 0.658884, 0.658885, 0.658886", \ + "0.761103, 0.761104, 0.761105, 0.761106, 0.761107, 0.761108" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.488887, 0.488888, 0.488889, 0.48889, 0.488891, 0.488892", \ + "0.51021, 0.510211, 0.510212, 0.510213, 0.510214, 0.510215", \ + "0.526899, 0.526977, 0.526978, 0.526979, 0.52698, 0.526981", \ + "0.555973, 0.555976, 0.555977, 0.555978, 0.555979, 0.55598", \ + "0.597018, 0.597019, 0.59702, 0.597021, 0.597022, 0.597023", \ + "0.658881, 0.658882, 0.658883, 0.658884, 0.658885, 0.658886", \ + "0.761103, 0.761104, 0.761105, 0.761106, 0.761107, 0.761108" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : positive_unate; + timing_type : three_state_enable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.0588, 1.37407, 1.68742, 2.00019, 2.93752, 3.8746", \ + "1.07615, 1.39113, 1.70444, 2.01724, 2.95462, 3.89186", \ + "1.08503, 1.40223, 1.71327, 2.02606, 2.96329, 3.90254", \ + "1.10162, 1.41658, 1.72986, 2.04265, 2.98018, 3.91685", \ + "1.12563, 1.44098, 1.75432, 2.06712, 3.00442, 3.94133", \ + "1.15048, 1.4656, 1.77889, 2.09168, 3.02899, 3.96639", \ + "1.17816, 1.49346, 1.80697, 2.11976, 3.057, 3.99439" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.79403, 1.41733, 2.04642, 2.67904, 4.56695, 6.45813", \ + "0.794031, 1.41734, 2.04736, 2.67905, 4.56894, 6.45977", \ + "0.794528, 1.41737, 2.0474, 2.67906, 4.57196, 6.46961", \ + "0.794537, 1.41738, 2.04741, 2.67907, 4.57197, 6.46962", \ + "0.794538, 1.41739, 2.04742, 2.67914, 4.57198, 6.46963", \ + "0.794539, 1.4174, 2.04743, 2.67915, 4.57199, 6.46964", \ + "0.798545, 1.41741, 2.04744, 2.67916, 4.572, 6.46965" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.907432, 1.24704, 1.58575, 1.92432, 2.93887, 3.95689", \ + "0.923483, 1.26308, 1.602, 1.94039, 2.95521, 3.96863", \ + "0.931631, 1.27124, 1.61038, 1.94846, 2.96357, 3.98106", \ + "0.944633, 1.28432, 1.62293, 1.96128, 2.97637, 3.99308", \ + "0.959328, 1.29909, 1.63765, 1.97642, 2.9922, 4.00756", \ + "0.975558, 1.31529, 1.65371, 1.99215, 3.00658, 4.0213", \ + "0.988473, 1.32823, 1.66714, 2.00477, 3.01787, 4.03098" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.725662, 1.31561, 1.90832, 2.49662, 4.27304, 6.05241", \ + "0.72569, 1.31562, 1.90834, 2.49701, 4.28243, 6.05242", \ + "0.725691, 1.31562, 1.90841, 2.49793, 4.28244, 6.05243", \ + "0.725692, 1.31563, 1.90842, 2.50804, 4.28245, 6.05356", \ + "0.726271, 1.31564, 1.91264, 2.50805, 4.28246, 6.05433", \ + "0.726272, 1.31565, 1.91331, 2.50806, 4.29145, 6.06244", \ + "0.726322, 1.31566, 1.91332, 2.50807, 4.29146, 6.06245" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "4.2718, 4.22929, 4.18694, 4.17326, 3.96536, 3.75833", \ + "4.27095, 4.23941, 4.20098, 4.17042, 3.97627, 3.74998", \ + "4.2695, 4.23572, 4.18522, 4.1319, 3.97753, 3.75894", \ + "4.26941, 4.24181, 4.20077, 4.10479, 3.98362, 3.74587", \ + "4.27069, 4.23888, 4.20674, 4.10918, 3.94258, 3.7517", \ + "4.25331, 4.22397, 4.18993, 4.09673, 4.00381, 3.753", \ + "4.31297, 4.22276, 4.19526, 4.11556, 3.92688, 3.73993" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.25203, 2.23809, 2.23175, 2.22814, 2.22158, 2.21946", \ + "2.26262, 2.24305, 2.23391, 2.22871, 2.22174, 2.2184", \ + "2.27581, 2.25265, 2.24173, 2.23605, 2.22696, 2.22291", \ + "2.28417, 2.25754, 2.24502, 2.23778, 2.22739, 2.22273", \ + "2.2961, 2.26919, 2.25548, 2.24833, 2.23929, 2.23412", \ + "2.27728, 2.2592, 2.25034, 2.24821, 2.2369, 2.23344", \ + "2.2519, 2.24474, 2.24333, 2.24187, 2.23961, 2.23759" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.78054, 3.50932, 5.23643, 6.96709, 12.1521, 17.3581", \ + "1.7787, 3.51019, 5.23446, 6.96527, 12.1538, 17.3431", \ + "1.78071, 3.50716, 5.23638, 6.96233, 12.1627, 17.3451", \ + "1.78816, 3.51922, 5.24456, 6.97189, 12.1649, 17.3492", \ + "1.81086, 3.5425, 5.26824, 6.99433, 12.1861, 17.3699", \ + "1.8623, 3.5942, 5.31865, 7.04029, 12.242, 17.4262", \ + "1.97688, 3.69943, 5.43148, 7.16174, 12.3418, 17.5255" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.214353, 0.214054, 0.213981, 0.213449, 0.213688, 0.214247", \ + "0.212829, 0.212528, 0.212342, 0.21229, 0.212125, 0.212654", \ + "0.215437, 0.214879, 0.21495, 0.214086, 0.214801, 0.215359", \ + "0.224329, 0.223891, 0.223876, 0.223646, 0.223679, 0.22423", \ + "0.247521, 0.247214, 0.247205, 0.246869, 0.247367, 0.247416", \ + "0.299724, 0.29962, 0.298972, 0.299233, 0.299182, 0.299766", \ + "0.409505, 0.409342, 0.409431, 0.409048, 0.408702, 0.409728" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "4.05886, 4.27528, 4.47606, 4.71409, 5.23328, 5.79157", \ + "4.07151, 4.27467, 4.49582, 4.68331, 5.27569, 5.79694", \ + "4.04665, 4.28923, 4.47152, 4.65995, 5.26655, 5.92481", \ + "4.04682, 4.25685, 4.47124, 4.6957, 5.20736, 5.77138", \ + "4.06298, 4.28097, 4.49586, 4.7232, 5.23958, 5.79802", \ + "4.05018, 4.27002, 4.48063, 4.64472, 5.22396, 5.79452", \ + "4.09355, 4.29991, 4.4986, 4.66538, 5.28887, 5.81047" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.28607, 1.2855, 1.28486, 1.28464, 1.28399, 1.28364", \ + "1.28687, 1.28637, 1.28692, 1.28577, 1.28548, 1.28481", \ + "1.28642, 1.28585, 1.28559, 1.28516, 1.28472, 1.28397", \ + "1.28678, 1.28627, 1.28537, 1.28578, 1.28446, 1.28408", \ + "1.28671, 1.28475, 1.28521, 1.28409, 1.28368, 1.28338", \ + "1.28806, 1.28526, 1.28509, 1.28541, 1.28468, 1.28424", \ + "1.28628, 1.28334, 1.2842, 1.28329, 1.28258, 1.28233" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.74534, 3.47579, 5.20346, 6.93027, 12.1327, 17.303", \ + "1.74554, 3.47458, 5.20305, 6.93204, 12.1297, 17.2962", \ + "1.74926, 3.48179, 5.20689, 6.93657, 12.1235, 17.2999", \ + "1.76052, 3.49302, 5.21879, 6.94886, 12.1331, 17.315", \ + "1.78395, 3.51592, 5.24319, 6.97438, 12.167, 17.3409", \ + "1.84304, 3.57561, 5.30113, 7.02838, 12.2255, 17.4", \ + "1.96377, 3.69474, 5.419, 7.14428, 12.3324, 17.5178" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.111715, 0.111312, 0.111319, 0.111183, 0.110994, 0.111962", \ + "0.111451, 0.11108, 0.110544, 0.110702, 0.111088, 0.111525", \ + "0.113347, 0.112941, 0.112899, 0.112706, 0.112872, 0.113587", \ + "0.119519, 0.118768, 0.118875, 0.118876, 0.118983, 0.119663", \ + "0.132883, 0.1326, 0.132222, 0.132061, 0.132294, 0.133194", \ + "0.162542, 0.162093, 0.161843, 0.16158, 0.162063, 0.162952", \ + "0.22649, 0.226672, 0.226905, 0.2262, 0.22632, 0.226871" \ + ); + } + } + } + pin (p2c) { + direction : "output"; + output_voltage : "core"; + function : "pad"; + related_ground_pin : vss; + related_power_pin : vdd; + max_capacitance : 1.28078; + timing () { + related_pin : "pad"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0524929, 0.0647372, 0.0877582, 0.10947, 0.13051, 0.151378", \ + "0.0524939, 0.0647382, 0.0877592, 0.109471, 0.130511, 0.151379", \ + "0.0524949, 0.0647392, 0.0877602, 0.109472, 0.130512, 0.15138", \ + "0.0524959, 0.0647402, 0.0877612, 0.109473, 0.130513, 0.151381", \ + "0.0524969, 0.0647412, 0.0877622, 0.109474, 0.130514, 0.151382", \ + "0.0524979, 0.0647422, 0.0877632, 0.109475, 0.130515, 0.151383", \ + "0.0524989, 0.0647432, 0.0877642, 0.109476, 0.130516, 0.151384" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0428345, 0.0651842, 0.109287, 0.153736, 0.198431, 0.24338", \ + "0.0455957, 0.0670648, 0.111396, 0.156843, 0.201556, 0.246451", \ + "0.0507598, 0.0713056, 0.113949, 0.157845, 0.202642, 0.24789", \ + "0.0534761, 0.0735664, 0.115382, 0.158956, 0.203405, 0.248173", \ + "0.0656726, 0.0849303, 0.125176, 0.166418, 0.208866, 0.252561", \ + "0.0863317, 0.105233, 0.141897, 0.181649, 0.221064, 0.26348", \ + "0.102798, 0.12201, 0.15763, 0.193677, 0.232754, 0.273796" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.299798, 0.317463, 0.3451, 0.368557, 0.389727, 0.409705", \ + "0.354194, 0.371933, 0.399555, 0.422792, 0.443988, 0.463866", \ + "0.476254, 0.494128, 0.521705, 0.544888, 0.566081, 0.585427", \ + "0.527077, 0.544869, 0.572441, 0.59579, 0.616894, 0.636661", \ + "0.847275, 0.864972, 0.892584, 0.915736, 0.936732, 0.95671", \ + "1.49735, 1.51577, 1.54391, 1.56693, 1.58816, 1.60722", \ + "2.05934, 2.07929, 2.11008, 2.13511, 2.15717, 2.17769" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0851423, 0.103088, 0.13617, 0.168484, 0.20066, 0.233487", \ + "0.0851433, 0.103289, 0.136171, 0.168488, 0.200661, 0.233488", \ + "0.0851443, 0.10329, 0.13623, 0.168489, 0.200662, 0.233489", \ + "0.0851453, 0.103291, 0.136231, 0.16849, 0.200663, 0.23349", \ + "0.085159, 0.103657, 0.13668, 0.16893, 0.201094, 0.233896", \ + "0.09867, 0.115867, 0.146334, 0.176562, 0.208328, 0.239478", \ + "0.119994, 0.137657, 0.168662, 0.197666, 0.22717, 0.257043" \ + ); + } + } + internal_power () { + related_pin : "pad"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "-0.174111, -0.174094, -0.174018, -0.174082, -0.174079, -0.174075", \ + "-0.174275, -0.174248, -0.174229, -0.174199, -0.174258, -0.174271", \ + "-0.173539, -0.173536, -0.173522, -0.173512, -0.173503, -0.173498", \ + "-0.1742, -0.173991, -0.174192, -0.173883, -0.174144, -0.174185", \ + "-0.174006, -0.174009, -0.174145, -0.17421, -0.174267, -0.174276", \ + "-0.17346, -0.173426, -0.173505, -0.173454, -0.173558, -0.173737", \ + "-0.0448015, -0.0441731, -0.0446462, -0.0441549, -0.0441392, -0.0435873" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.174111, 0.174104, 0.174091, 0.174082, 0.174079, 0.174075", \ + "0.174275, 0.174272, 0.174266, 0.174259, 0.174258, 0.174271", \ + "0.173539, 0.173536, 0.173522, 0.173512, 0.173503, 0.173498", \ + "0.1742, 0.174197, 0.174192, 0.174188, 0.174184, 0.174185", \ + "0.174006, 0.17406, 0.174145, 0.17421, 0.174267, 0.174276", \ + "0.17346, 0.173426, 0.173505, 0.173454, 0.173558, 0.173737", \ + "0.173681, 0.173544, 0.173324, 0.173219, 0.1735, 0.173208" \ + ); + } + } + internal_power () { + related_pin : "pad"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "-0.00081378, -0.000696472, -0.000738013, -0.000581448, -0.000736694, -0.000946297", \ + "-0.00178248, -0.00118438, -0.00134825, -0.00162253, -0.00189645, -0.00222775", \ + "-0.00224667, -0.00222523, -0.00219146, -0.00231144, -0.0023001, -0.00270955", \ + "-0.00227023, -0.0023262, -0.00298782, -0.00287231, -0.00232017, -0.00243275", \ + "-0.00192716, -0.00207281, -0.00216044, -0.0028496, -0.00376728, -0.0043849", \ + "0.000238603, -0.000939444, -0.00175916, -0.00118561, -0.00304801, -0.00234325", \ + "0.0498843, 0.0471836, 0.0464905, 0.0444609, 0.0437404, 0.0437506" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0703765, 0.0692796, 0.0690439, 0.0691947, 0.0693472, 0.0694573", \ + "0.0695551, 0.0684312, 0.0681407, 0.0682603, 0.0684002, 0.0685847", \ + "0.0689408, 0.0678407, 0.0675407, 0.0676054, 0.0677114, 0.0678151", \ + "0.0682589, 0.0670945, 0.0666868, 0.0667042, 0.0667703, 0.0668111", \ + "0.0693553, 0.0681283, 0.0675659, 0.0674626, 0.0674567, 0.0674495", \ + "0.0721066, 0.0700398, 0.0686053, 0.0680767, 0.0678665, 0.0677663", \ + "0.0762865, 0.0736545, 0.0712805, 0.070161, 0.0696017, 0.0691351" \ + ); + } + } + } + pin (c2p) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.016; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0299877; + rise_capacitance : 0.0300677; + rise_capacitance_range (0.0240633, 0.0340854); + fall_capacitance : 0.0299078; + fall_capacitance_range (0.0246685, 0.0330278); + internal_power () { + when : "(!c2p_en * pad * p2c)"; + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-1.3586e-05, -5.42498e-06, -6.13275e-06, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "1.3586e-05, 5.42498e-06, 6.13275e-06, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + when : "(!c2p_en * pad * p2c)"; + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.021519, -0.0224595, -0.0225905, -0.0225481, -0.0228347, -0.022762, -0.0228348" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0286058, 0.028131, 0.0284957, 0.0283702, 0.0282106, 0.0279653, 0.027811" \ + ); + } + } + internal_power () { + when : "(!c2p_en * !pad * !p2c)"; + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-1.35733e-05, -5.437e-06, -6.13866e-06, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "1.35733e-05, 5.437e-06, 6.13866e-06, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + when : "(!c2p_en * !pad * !p2c)"; + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0215166, -0.0224586, -0.0225893, -0.0225475, -0.0228346, -0.0227622, -0.0228349" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.028604, 0.0281298, 0.0284951, 0.02837, 0.0282104, 0.0279652, 0.0278109" \ + ); + } + } + internal_power () { + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-1.35733e-05, -5.437e-06, -6.13866e-06, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "1.35733e-05, 5.437e-06, 6.13866e-06, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0215166, -0.0224586, -0.0225893, -0.0225475, -0.0228346, -0.0227622, -0.0228349" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.028604, 0.0281298, 0.0284951, 0.02837, 0.0282104, 0.0279652, 0.0278109" \ + ); + } + } + } + pin (c2p_en) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.011; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0269094; + rise_capacitance : 0.0277574; + rise_capacitance_range (0.0231549, 0.0334327); + fall_capacitance : 0.0260614; + fall_capacitance_range (0.0221449, 0.0296327); + internal_power () { + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "1.05787, 1.05802, 1.05798, 1.0583, 1.05658, 1.06089, 1.05634" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.387719, 0.386783, 0.386769, 0.385912, 0.385659, 0.384371, 0.383716" \ + ); + } + } + internal_power () { + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0402722, 0.0397633, 0.0417451, 0.0480841, 0.0612821, 0.0910429, 0.156113" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.101475, 0.102535, 0.105059, 0.110747, 0.124619, 0.154252, 0.219089" \ + ); + } + } + } + } + cell (sg13g2_IOPadOut16mA) { + pad_cell : true; + area : 14400; + cell_footprint : "inout"; + pad_drivers : 1; + bond_pads : 1; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 1116.98; + when : "!c2p&!pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 696.611; + when : "!c2p&!pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 282.332; + when : "c2p&pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 1335.85; + when : "c2p&pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 699.654; + related_pg_pin : iovdd; + } + leakage_power () { + value : 1016.23; + related_pg_pin : vdd; + } + pin (pad) { + direction : "output"; + is_pad : true; + function : "c2p"; + drive_current : 16; + output_voltage : "pad"; + related_ground_pin : iovss; + related_power_pin : iovdd; + max_capacitance : 6.49552; + timing () { + related_pin : "c2p"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 3, 7, 9, 12, 15"); + values ( \ + "1.03594, 1.24912, 1.58116, 1.73613, 1.96493, 2.19364", \ + "1.06454, 1.27775, 1.60974, 1.76456, 1.99439, 2.22215", \ + "1.09303, 1.30564, 1.63785, 1.79245, 2.02269, 2.25031", \ + "1.15855, 1.37182, 1.70376, 1.85831, 2.08849, 2.31626", \ + "1.28442, 1.49711, 1.82903, 1.98435, 2.21438, 2.44174", \ + "1.51513, 1.72796, 2.06037, 2.2152, 2.44467, 2.67264", \ + "1.94658, 2.15949, 2.49192, 2.64726, 2.87643, 3.10419" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 3, 7, 9, 12, 15"); + values ( \ + "0.373035, 0.681582, 1.27524, 1.57731, 2.03653, 2.5005", \ + "0.373049, 0.681583, 1.27525, 1.57732, 2.03654, 2.50051", \ + "0.37305, 0.681584, 1.27526, 1.57733, 2.03676, 2.50052", \ + "0.374059, 0.681585, 1.27527, 1.57751, 2.03677, 2.50053", \ + "0.37406, 0.681586, 1.27528, 1.57752, 2.03677, 2.50079", \ + "0.374061, 0.681587, 1.27529, 1.57753, 2.0368, 2.5008", \ + "0.374062, 0.681588, 1.2753, 1.57777, 2.03681, 2.50081" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 3, 7, 9, 12, 15"); + values ( \ + "0.802918, 0.973107, 1.26722, 1.41225, 1.63226, 1.85613", \ + "0.815135, 0.985506, 1.27957, 1.42418, 1.64445, 1.86836", \ + "0.822802, 0.992981, 1.28674, 1.4319, 1.65276, 1.87516", \ + "0.835293, 1.00585, 1.30007, 1.44383, 1.66564, 1.88779", \ + "0.849891, 1.02029, 1.31474, 1.45843, 1.68025, 1.9024", \ + "0.878335, 1.04928, 1.34282, 1.48744, 1.70774, 1.93173", \ + "0.929305, 1.09908, 1.39331, 1.53861, 1.75856, 1.98261" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 3, 7, 9, 12, 15"); + values ( \ + "0.456241, 0.679532, 1.19877, 1.4729, 1.89507, 2.32423", \ + "0.456242, 0.681161, 1.19941, 1.47291, 1.89508, 2.32424", \ + "0.456365, 0.681162, 1.19942, 1.47292, 1.89509, 2.32472", \ + "0.456366, 0.681333, 1.19943, 1.47349, 1.8951, 2.32473", \ + "0.456918, 0.681446, 1.19944, 1.47387, 1.89511, 2.32474", \ + "0.456919, 0.682267, 1.2001, 1.47403, 1.89614, 2.32601", \ + "0.45692, 0.682268, 1.20011, 1.47404, 1.89615, 2.32602" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 3, 7, 9, 12, 15"); + values ( \ + "7.72377, 7.57591, 7.4713, 7.39098, 7.21372, 7.20691", \ + "7.72511, 7.58527, 7.4849, 7.34144, 7.33309, 7.2103", \ + "7.72901, 7.56025, 7.48555, 7.35329, 7.34562, 7.22192", \ + "7.74759, 7.61555, 7.50946, 7.40333, 7.37662, 7.24662", \ + "7.8093, 7.64183, 7.53923, 7.45124, 7.41647, 7.2846", \ + "7.90221, 7.71404, 7.64644, 7.52584, 7.43335, 7.38115", \ + "8.04137, 7.85995, 7.80001, 7.76254, 7.62548, 7.51964" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 3, 7, 9, 12, 15"); + values ( \ + "19.734, 15.9465, 12.683, 11.7341, 10.7774, 10.0544", \ + "19.7174, 15.9385, 12.6589, 11.7139, 10.7608, 10.0381", \ + "19.7232, 15.9353, 12.6532, 11.7145, 10.7413, 10.0597", \ + "19.725, 15.945, 12.6437, 11.7381, 10.739, 10.0477", \ + "19.7486, 15.9507, 12.6447, 11.7475, 10.7356, 10.043", \ + "19.7606, 15.9976, 12.6892, 11.7514, 10.7781, 10.0857", \ + "19.7493, 15.9439, 12.6679, 11.7387, 10.7693, 10.0491" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 3, 7, 9, 12, 15"); + values ( \ + "-0.0146871, -0.0146869, -0.0146868, -0.0146873, -0.0146878, -0.0146878", \ + "-0.0130704, -0.0130702, -0.0130701, -0.0130705, -0.0130715, -0.013071", \ + "-0.00936959, -0.00936989, -0.00936971, -0.00936982, -0.00937009, -0.0093703", \ + "0.00188957, 0.00188921, 0.00169101, 0.00169053, 0.00168983, 0.00168995", \ + "0.0264835, 0.0262177, 0.0262178, 0.0264835, 0.0264834, 0.0262173", \ + "0.0778245, 0.0778247, 0.0777762, 0.0777758, 0.0778237, 0.0778243", \ + "0.185463, 0.185463, 0.185463, 0.185559, 0.185462, 0.185559" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 3, 7, 9, 12, 15"); + values ( \ + "0.0701465, 0.0701445, 0.0701417, 0.0701386, 0.070141, 0.0701433", \ + "0.0742085, 0.0742073, 0.0742075, 0.0741991, 0.0742044, 0.0742069", \ + "0.0797051, 0.0797002, 0.0795852, 0.079581, 0.079695, 0.0796935", \ + "0.0912998, 0.0912874, 0.0908188, 0.0908203, 0.0908188, 0.090822", \ + "0.116466, 0.116461, 0.116498, 0.116455, 0.116499, 0.116503", \ + "0.16799, 0.167954, 0.168065, 0.168167, 0.168701, 0.168273", \ + "0.271847, 0.271618, 0.271844, 0.271685, 0.271624, 0.271896" \ + ); + } + } + } + pin (c2p) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.016; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0418272; + rise_capacitance : 0.0401402; + rise_capacitance_range (0.0358148, 0.0427779); + fall_capacitance : 0.0435141; + fall_capacitance_range (0.0383863, 0.0469537); + } + } + cell (sg13g2_IOPadOut30mA) { + pad_cell : true; + area : 14400; + cell_footprint : "inout"; + pad_drivers : 1; + bond_pads : 1; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 2129.07; + when : "!c2p&!pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 695.81; + when : "!c2p&!pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 524.869; + when : "c2p&pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 1335.76; + when : "c2p&pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 1326.97; + related_pg_pin : iovdd; + } + leakage_power () { + value : 1015.79; + related_pg_pin : vdd; + } + pin (pad) { + direction : "output"; + is_pad : true; + function : "c2p"; + drive_current : 30; + output_voltage : "pad"; + related_ground_pin : iovss; + related_power_pin : iovdd; + max_capacitance : 9.69355; + timing () { + related_pin : "c2p"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("2, 6, 14, 18, 24, 30"); + values ( \ + "1.31313, 1.59911, 2.00632, 2.18226, 2.43817, 2.68727", \ + "1.34184, 1.62819, 2.03273, 2.21137, 2.46786, 2.71586", \ + "1.36979, 1.65583, 2.05984, 2.23943, 2.49435, 2.74404", \ + "1.43638, 1.72249, 2.12693, 2.30568, 2.56216, 2.80991", \ + "1.56135, 1.84785, 2.25226, 2.43093, 2.6869, 2.93574", \ + "1.79324, 2.07942, 2.4835, 2.66268, 2.91863, 3.16711", \ + "2.22468, 2.51107, 2.91571, 3.09442, 3.35071, 3.5993" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("2, 6, 14, 18, 24, 30"); + values ( \ + "0.48413, 0.860225, 1.50092, 1.81667, 2.3003, 2.78692", \ + "0.484131, 0.860226, 1.50093, 1.81697, 2.30031, 2.78693", \ + "0.484132, 0.860227, 1.50094, 1.81699, 2.30032, 2.78754", \ + "0.484133, 0.860228, 1.50095, 1.81702, 2.30033, 2.7877", \ + "0.484134, 0.860267, 1.50096, 1.81703, 2.30034, 2.78771", \ + "0.484135, 0.860268, 1.50097, 1.81704, 2.30035, 2.78772", \ + "0.484136, 0.860645, 1.50098, 1.81732, 2.30036, 2.78773" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("2, 6, 14, 18, 24, 30"); + values ( \ + "1.07059, 1.27561, 1.61292, 1.76821, 1.99671, 2.2258", \ + "1.08308, 1.2874, 1.6252, 1.78106, 2.00939, 2.23594", \ + "1.09083, 1.29575, 1.63296, 1.7876, 2.01779, 2.24629", \ + "1.10332, 1.30795, 1.64545, 1.80008, 2.0297, 2.25627", \ + "1.118, 1.32304, 1.66015, 1.81638, 2.04403, 2.27311", \ + "1.14648, 1.35069, 1.68877, 1.84352, 2.07162, 2.29862", \ + "1.19677, 1.40132, 1.73886, 1.89192, 2.12133, 2.35141" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("2, 6, 14, 18, 24, 30"); + values ( \ + "0.752057, 0.970826, 1.46584, 1.73584, 2.16335, 2.60216", \ + "0.752348, 0.973725, 1.46585, 1.73648, 2.1637, 2.60217", \ + "0.752506, 0.973726, 1.4659, 1.73674, 2.16371, 2.60218", \ + "0.752507, 0.974297, 1.46596, 1.73689, 2.16387, 2.60219", \ + "0.752749, 0.974298, 1.46623, 1.7369, 2.16388, 2.60245", \ + "0.753254, 0.974299, 1.46624, 1.73776, 2.16466, 2.60246", \ + "0.753255, 0.9743, 1.46625, 1.73777, 2.16467, 2.60247" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("2, 6, 14, 18, 24, 30"); + values ( \ + "12.902, 12.406, 12.2023, 11.7803, 11.6843, 11.4293", \ + "12.8529, 12.4209, 11.8158, 11.7852, 11.6362, 11.2727", \ + "12.8777, 12.4246, 11.8349, 11.7884, 11.6652, 11.4775", \ + "12.9342, 12.4541, 11.8595, 11.8192, 11.6465, 11.3591", \ + "12.9414, 12.4944, 11.9141, 11.8003, 11.7786, 11.4656", \ + "13.0317, 12.5821, 11.9861, 11.8865, 11.7832, 11.6287", \ + "13.1778, 12.7345, 12.1401, 12.11, 11.9628, 11.7626" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("2, 6, 14, 18, 24, 30"); + values ( \ + "71.0851, 59.0036, 46.2492, 42.2831, 38.0132, 34.8529", \ + "71.046, 59.0016, 46.2274, 42.2784, 38.0054, 34.7951", \ + "71.0672, 58.9917, 46.24, 42.2737, 37.973, 34.8457", \ + "71.0882, 59.0279, 46.2469, 42.367, 38.0252, 34.8149", \ + "71.1444, 59.0451, 46.2682, 42.3261, 38.0324, 34.8668", \ + "71.1528, 59.0936, 46.252, 42.4092, 38.1225, 34.8866", \ + "71.0817, 58.9972, 46.1425, 42.3538, 38.0115, 34.8892" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("2, 6, 14, 18, 24, 30"); + values ( \ + "-0.014686, -0.0146858, -0.0146857, -0.0146854, -0.0146857, -0.0146861", \ + "-0.0130857, -0.0130857, -0.0130858, -0.0130856, -0.0130858, -0.0130862", \ + "-0.00938393, -0.00938386, -0.00971518, -0.00962531, -0.00971501, -0.00971574", \ + "0.00186263, 0.00186278, 0.00166143, 0.00186293, 0.0018627, 0.00186227", \ + "0.0264337, 0.0261659, 0.0264336, 0.0264339, 0.026166, 0.0264329", \ + "0.0785553, 0.0785553, 0.0784692, 0.0785555, 0.0784693, 0.0784691", \ + "0.185394, 0.185394, 0.185394, 0.185332, 0.185332, 0.185394" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("2, 6, 14, 18, 24, 30"); + values ( \ + "0.0701494, 0.0701487, 0.0701468, 0.0701481, 0.0701526, 0.0701544", \ + "0.0742019, 0.0742019, 0.0742, 0.0742013, 0.0742063, 0.0742042", \ + "0.0795637, 0.07967, 0.0795615, 0.0796719, 0.0796745, 0.079676", \ + "0.091244, 0.0912426, 0.091241, 0.0907731, 0.0912473, 0.0912466", \ + "0.116467, 0.116421, 0.11642, 0.11642, 0.116426, 0.116471", \ + "0.168987, 0.167999, 0.168034, 0.168726, 0.168859, 0.168421", \ + "0.271978, 0.271947, 0.271925, 0.272327, 0.272246, 0.272234" \ + ); + } + } + } + pin (c2p) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.016; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0418259; + rise_capacitance : 0.0401445; + rise_capacitance_range (0.0358067, 0.0427549); + fall_capacitance : 0.0435073; + fall_capacitance_range (0.038367, 0.0469494); + } + } + cell (sg13g2_IOPadOut4mA) { + pad_cell : true; + area : 14400; + cell_footprint : "inout"; + pad_drivers : 1; + bond_pads : 1; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 354.02; + when : "!c2p&!pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 695.76; + when : "!c2p&!pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 184.993; + when : "c2p&pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 1335.87; + when : "c2p&pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 269.507; + related_pg_pin : iovdd; + } + leakage_power () { + value : 1015.81; + related_pg_pin : vdd; + } + pin (pad) { + direction : "output"; + is_pad : true; + function : "c2p"; + drive_current : 4; + output_voltage : "pad"; + related_ground_pin : iovss; + related_power_pin : iovdd; + max_capacitance : 1.6895; + timing () { + related_pin : "c2p"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.01179, 1.31593, 1.61818, 1.92027, 2.82379, 3.72684", \ + "1.0404, 1.34439, 1.64718, 1.94881, 2.85236, 3.75539", \ + "1.06854, 1.37254, 1.67547, 1.97681, 2.88065, 3.78362", \ + "1.13447, 1.43859, 1.74132, 2.04294, 2.94651, 3.84953", \ + "1.26011, 1.56415, 1.86704, 2.16838, 3.07209, 3.97519", \ + "1.49267, 1.79858, 2.09956, 2.40098, 3.3046, 4.20934", \ + "1.92553, 2.22973, 2.53241, 2.83381, 3.73745, 4.64039" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.772138, 1.39264, 2.01982, 2.64793, 4.5403, 6.42993", \ + "0.772327, 1.39265, 2.01983, 2.64888, 4.54031, 6.42994", \ + "0.772328, 1.39266, 2.01984, 2.64889, 4.54032, 6.42995", \ + "0.772329, 1.3928, 2.01985, 2.6489, 4.54033, 6.42996", \ + "0.77233, 1.39281, 2.01986, 2.64893, 4.54034, 6.42997", \ + "0.772388, 1.39282, 2.01987, 2.64898, 4.54035, 6.42998", \ + "0.772469, 1.39283, 2.01988, 2.64917, 4.54036, 6.42999" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.823104, 1.12936, 1.43575, 1.74213, 2.66207, 3.58275", \ + "0.835022, 1.14118, 1.44773, 1.75408, 2.67394, 3.5947", \ + "0.84245, 1.14877, 1.45518, 1.76155, 2.68173, 3.60227", \ + "0.855434, 1.16136, 1.46768, 1.77485, 2.69398, 3.61483", \ + "0.869133, 1.17523, 1.48177, 1.78835, 2.70802, 3.62873", \ + "0.897929, 1.2041, 1.51078, 1.817, 2.73736, 3.65643", \ + "0.94894, 1.255, 1.56154, 1.8677, 2.7885, 3.70824" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.708721, 1.29099, 1.87883, 2.46822, 4.23785, 6.00896", \ + "0.708722, 1.291, 1.87884, 2.46825, 4.23786, 6.00897", \ + "0.708723, 1.29101, 1.87885, 2.46827, 4.23787, 6.00898", \ + "0.708724, 1.29161, 1.87885, 2.46828, 4.23864, 6.00899", \ + "0.708992, 1.29162, 1.87894, 2.46942, 4.23865, 6.00899", \ + "0.709066, 1.29163, 1.87895, 2.46983, 4.23866, 6.009", \ + "0.709067, 1.29164, 1.87896, 2.46984, 4.23873, 6.00901" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "3.84845, 3.81205, 3.78256, 3.73421, 3.65069, 3.52253", \ + "3.85154, 3.81414, 3.78194, 3.74864, 3.6544, 3.50323", \ + "3.86288, 3.82347, 3.79044, 3.75376, 3.66642, 3.52426", \ + "3.88405, 3.84899, 3.8173, 3.78173, 3.68766, 3.54614", \ + "3.93854, 3.90099, 3.86626, 3.83094, 3.7427, 3.59374", \ + "4.0319, 3.99666, 3.96335, 3.92908, 3.83872, 3.68352", \ + "4.19189, 4.15798, 4.12729, 4.09464, 4.00216, 3.85819" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.45117, 2.39606, 2.37206, 2.3589, 2.33803, 2.32872", \ + "2.43101, 2.37763, 2.35263, 2.34005, 2.319, 2.30963", \ + "2.4258, 2.37185, 2.34691, 2.33486, 2.31349, 2.3043", \ + "2.42593, 2.37186, 2.34592, 2.3335, 2.31348, 2.30294", \ + "2.40923, 2.35398, 2.3282, 2.31457, 2.29401, 2.28415", \ + "2.41188, 2.35693, 2.33196, 2.31696, 2.29691, 2.28734", \ + "2.43132, 2.37459, 2.34886, 2.33491, 2.31489, 2.30478" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "-0.0146871, -0.0146882, -0.0146886, -0.0146884, -0.0146884, -0.0146884", \ + "-0.0130841, -0.013085, -0.0130859, -0.0130855, -0.0130851, -0.0130854", \ + "-0.00938279, -0.00938372, -0.00938395, -0.00938415, -0.0093834, -0.00938315", \ + "0.00186267, 0.00186199, 0.00186128, 0.00186166, 0.00186204, 0.00186172", \ + "0.0264334, 0.0264327, 0.0264323, 0.0264322, 0.0264325, 0.0264331", \ + "0.0787085, 0.0786671, 0.0787071, 0.0787074, 0.0787073, 0.0786667", \ + "0.185529, 0.185532, 0.185532, 0.185533, 0.185533, 0.185534" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.0701631, 0.0701705, 0.0701627, 0.0701564, 0.0701475, 0.070154", \ + "0.0742291, 0.0742174, 0.0742105, 0.0742089, 0.0741971, 0.0742014", \ + "0.079712, 0.0797006, 0.0797044, 0.0795713, 0.0796903, 0.0795639", \ + "0.0912796, 0.0907818, 0.0907848, 0.0912562, 0.0907756, 0.090779", \ + "0.116507, 0.116471, 0.116462, 0.116497, 0.116447, 0.116451", \ + "0.168319, 0.168233, 0.168328, 0.168127, 0.168256, 0.168284", \ + "0.276194, 0.275854, 0.275833, 0.275885, 0.276312, 0.276406" \ + ); + } + } + } + pin (c2p) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.016; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0418143; + rise_capacitance : 0.0401233; + rise_capacitance_range (0.0358063, 0.0427017); + fall_capacitance : 0.0435054; + fall_capacitance_range (0.0383654, 0.0468359); + } + } + cell (sg13g2_IOPadTriOut16mA) { + pad_cell : true; + area : 14400; + cell_footprint : "tri_out"; + pad_drivers : 1; + bond_pads : 1; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 224.199; + when : "!c2p_en&!c2p"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 3171.23; + when : "!c2p_en&!c2p"; + related_pg_pin : vdd; + } + leakage_power () { + value : 224.199; + when : "!c2p_en&c2p"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 4240.17; + when : "!c2p_en&c2p"; + related_pg_pin : vdd; + } + leakage_power () { + value : 354.364; + when : "c2p_en&c2p&pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 4387.39; + when : "c2p_en&c2p&pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 1165.17; + when : "c2p_en&!c2p&!pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 3292.18; + when : "c2p_en&!c2p&!pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 491.983; + related_pg_pin : iovdd; + } + leakage_power () { + value : 3772.74; + related_pg_pin : vdd; + } + pin (pad) { + direction : "output"; + is_pad : true; + function : "c2p"; + three_state : "c2p_en'"; + drive_current : 16; + output_voltage : "pad"; + related_ground_pin : iovss; + related_power_pin : iovdd; + max_capacitance : 6.49603; + capacitance : 0.234686; + rise_capacitance : 0.236873; + rise_capacitance_range (0.236873, 0.236873); + fall_capacitance : 0.2325; + fall_capacitance_range (0.2325, 0.2325); + timing () { + related_pin : "c2p"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.08412, 1.20061, 1.29817, 1.38775, 1.63041, 1.8625", \ + "1.09976, 1.21613, 1.31328, 1.40207, 1.64542, 1.87803", \ + "1.10975, 1.22627, 1.32324, 1.41289, 1.65545, 1.88802", \ + "1.12488, 1.24104, 1.33855, 1.42786, 1.67105, 1.90318", \ + "1.14297, 1.25941, 1.35626, 1.44587, 1.68891, 1.92088", \ + "1.16379, 1.28014, 1.37755, 1.46611, 1.70994, 1.94222", \ + "1.18244, 1.29964, 1.39698, 1.48586, 1.72947, 1.96147" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.375267, 0.533686, 0.681992, 0.830367, 1.27506, 1.72964", \ + "0.375268, 0.533687, 0.681993, 0.830368, 1.27507, 1.72996", \ + "0.375269, 0.534427, 0.681994, 0.830369, 1.27508, 1.73016", \ + "0.37527, 0.534428, 0.681995, 0.83037, 1.27525, 1.73026", \ + "0.375271, 0.534429, 0.681996, 0.830371, 1.27526, 1.73027", \ + "0.375272, 0.53443, 0.681997, 0.830372, 1.27527, 1.73028", \ + "0.376588, 0.535834, 0.683324, 0.830373, 1.27528, 1.73029" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.862896, 0.95336, 1.03352, 1.11006, 1.33099, 1.54947", \ + "0.881408, 0.971654, 1.05172, 1.12831, 1.34881, 1.56703", \ + "0.896358, 0.986424, 1.0665, 1.14316, 1.36272, 1.58215", \ + "0.925978, 1.01599, 1.09605, 1.17251, 1.39224, 1.61132", \ + "0.971098, 1.06121, 1.14175, 1.21791, 1.43782, 1.65577", \ + "1.03838, 1.12903, 1.20942, 1.2852, 1.50527, 1.72428", \ + "1.15773, 1.24779, 1.32881, 1.40533, 1.62612, 1.84626" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.434713, 0.546978, 0.664367, 0.789624, 1.188, 1.60459", \ + "0.438793, 0.550142, 0.665906, 0.792102, 1.18987, 1.60645", \ + "0.441156, 0.552291, 0.668035, 0.793678, 1.19181, 1.60694", \ + "0.4433, 0.554183, 0.669791, 0.795083, 1.19301, 1.60767", \ + "0.443301, 0.554184, 0.670443, 0.795084, 1.19302, 1.60774", \ + "0.443302, 0.554185, 0.670444, 0.795085, 1.19303, 1.60775", \ + "0.443303, 0.554186, 0.670445, 0.795086, 1.19304, 1.60776" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : negative_unate; + timing_type : three_state_disable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.801469, 0.80147, 0.801471, 0.801472, 0.801473, 0.801474", \ + "0.82328, 0.823281, 0.823282, 0.823283, 0.823284, 0.823285", \ + "0.834025, 0.834026, 0.834027, 0.834028, 0.834029, 0.83403", \ + "0.855508, 0.855509, 0.85551, 0.855511, 0.855512, 0.855513", \ + "0.88093, 0.880931, 0.880932, 0.880933, 0.880934, 0.880935", \ + "0.922405, 0.922406, 0.922407, 0.922408, 0.922409, 0.92241", \ + "0.994613, 0.994614, 0.994615, 0.994616, 0.994617, 0.994618" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.801469, 0.80147, 0.801471, 0.801472, 0.801473, 0.801474", \ + "0.82328, 0.823281, 0.823282, 0.823283, 0.823284, 0.823285", \ + "0.834025, 0.834026, 0.834027, 0.834028, 0.834029, 0.83403", \ + "0.855508, 0.855509, 0.85551, 0.855511, 0.855512, 0.855513", \ + "0.88093, 0.880931, 0.880932, 0.880933, 0.880934, 0.880935", \ + "0.922405, 0.922406, 0.922407, 0.922408, 0.922409, 0.92241", \ + "0.994613, 0.994614, 0.994615, 0.994616, 0.994617, 0.994618" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.864764, 0.864765, 0.864766, 0.864767, 0.864768, 0.864769", \ + "0.880024, 0.880025, 0.880026, 0.880027, 0.880028, 0.880029", \ + "0.903523, 0.903524, 0.903525, 0.903526, 0.903527, 0.903528", \ + "0.933144, 0.933145, 0.933146, 0.933147, 0.933148, 0.933149", \ + "0.97388, 0.973881, 0.973882, 0.973883, 0.973884, 0.973885", \ + "1.0299, 1.02991, 1.02992, 1.02993, 1.02994, 1.02995", \ + "1.12898, 1.12899, 1.129, 1.12901, 1.12902, 1.12903" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.864764, 0.864765, 0.864766, 0.864767, 0.864768, 0.864769", \ + "0.880024, 0.880025, 0.880026, 0.880027, 0.880028, 0.880029", \ + "0.903523, 0.903524, 0.903525, 0.903526, 0.903527, 0.903528", \ + "0.933144, 0.933145, 0.933146, 0.933147, 0.933148, 0.933149", \ + "0.97388, 0.973881, 0.973882, 0.973883, 0.973884, 0.973885", \ + "1.0299, 1.02991, 1.02992, 1.02993, 1.02994, 1.02995", \ + "1.12898, 1.12899, 1.129, 1.12901, 1.12902, 1.12903" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : positive_unate; + timing_type : three_state_enable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.07386, 1.19826, 1.29899, 1.39251, 1.64643, 1.8906", \ + "1.09014, 1.21487, 1.3174, 1.40842, 1.66327, 1.90774", \ + "1.10205, 1.22569, 1.32866, 1.42199, 1.67542, 1.91875", \ + "1.11844, 1.24311, 1.34561, 1.43902, 1.69204, 1.93591", \ + "1.14037, 1.26463, 1.36594, 1.46033, 1.71375, 1.95641", \ + "1.16638, 1.29024, 1.39368, 1.48694, 1.73979, 1.9835", \ + "1.19413, 1.3176, 1.41972, 1.51225, 1.76662, 2.01143" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.380236, 0.530632, 0.672991, 0.819037, 1.26106, 1.71776", \ + "0.380237, 0.530633, 0.674616, 0.819038, 1.26173, 1.7186", \ + "0.380238, 0.530634, 0.674617, 0.820112, 1.26213, 1.71861", \ + "0.380249, 0.530949, 0.675004, 0.820547, 1.26219, 1.71862", \ + "0.380257, 0.53095, 0.675005, 0.820548, 1.2622, 1.71863", \ + "0.380258, 0.530951, 0.675006, 0.820549, 1.26221, 1.71864", \ + "0.380525, 0.532565, 0.675007, 0.82055, 1.26222, 1.71865" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.734101, 0.843602, 0.940183, 1.0286, 1.29036, 1.54652", \ + "0.750139, 0.859637, 0.956218, 1.04485, 1.3064, 1.56256", \ + "0.758648, 0.867505, 0.964627, 1.0547, 1.3148, 1.57086", \ + "0.771656, 0.881159, 0.977742, 1.06637, 1.32793, 1.58409", \ + "0.787339, 0.896839, 0.993411, 1.08211, 1.34292, 1.59966", \ + "0.80293, 0.910965, 1.00655, 1.09719, 1.35846, 1.61427", \ + "0.817008, 0.926507, 1.02309, 1.11147, 1.37327, 1.62949" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.27658, 0.416945, 0.555142, 0.692874, 1.11902, 1.55248", \ + "0.276581, 0.416946, 0.555143, 0.692875, 1.11903, 1.55249", \ + "0.276582, 0.416947, 0.555144, 0.693768, 1.11904, 1.5525", \ + "0.276583, 0.416948, 0.555145, 0.693769, 1.11905, 1.55251", \ + "0.276584, 0.416949, 0.555146, 0.69377, 1.11906, 1.55252", \ + "0.276585, 0.41695, 0.555147, 0.693771, 1.11907, 1.55305", \ + "0.276586, 0.416951, 0.555148, 0.693772, 1.11925, 1.55329" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "7.63818, 7.53184, 7.50798, 7.57436, 7.4264, 7.28302", \ + "7.655, 7.54513, 7.48984, 7.51399, 7.37762, 7.3184", \ + "7.66921, 7.61754, 7.50769, 7.5767, 7.41524, 7.35358", \ + "7.67249, 7.55341, 7.54697, 7.58329, 7.4471, 7.35034", \ + "7.67901, 7.62792, 7.51288, 7.5807, 7.43224, 7.33424", \ + "7.62211, 7.53034, 7.5056, 7.48148, 7.44379, 7.34936", \ + "7.58416, 7.55956, 7.50236, 7.47562, 7.36963, 7.2355" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "17.9788, 15.9349, 14.5459, 13.5707, 11.6465, 10.5362", \ + "18.2851, 16.203, 14.7794, 13.794, 11.8209, 10.6864", \ + "18.483, 16.3804, 14.939, 13.9169, 11.9399, 10.7721", \ + "18.662, 16.5403, 15.0817, 14.052, 12.0687, 10.8584", \ + "18.6226, 16.5036, 15.0705, 14.0162, 12.0133, 10.8603", \ + "18.3873, 16.3148, 14.8671, 13.8543, 11.9224, 10.7271", \ + "17.4663, 15.4801, 14.1495, 13.1874, 11.3524, 10.2789" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.0602245, 0.0602198, 0.0602252, 0.0602279, 0.0602245, 0.0602188", \ + "0.0583184, 0.0583215, 0.0583189, 0.0583149, 0.058318, 0.0583132", \ + "0.0602094, 0.0602115, 0.060211, 0.0602131, 0.0602086, 0.0602079", \ + "0.0680799, 0.0680782, 0.068081, 0.0680823, 0.0680827, 0.0680763", \ + "0.0903912, 0.0903943, 0.0903922, 0.0903943, 0.0903948, 0.0903913", \ + "0.141606, 0.141599, 0.141601, 0.141598, 0.141601, 0.141595", \ + "0.252135, 0.252129, 0.252119, 0.252141, 0.252156, 0.252091" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.149702, 0.149703, 0.149695, 0.149696, 0.149692, 0.149692", \ + "0.148111, 0.148108, 0.148096, 0.148102, 0.148093, 0.148095", \ + "0.150632, 0.150639, 0.150639, 0.150639, 0.150632, 0.150619", \ + "0.159732, 0.159735, 0.159736, 0.159737, 0.159731, 0.159719", \ + "0.182745, 0.182749, 0.182749, 0.182739, 0.182736, 0.182736", \ + "0.234617, 0.234893, 0.23463, 0.234628, 0.234945, 0.234577", \ + "0.344139, 0.344087, 0.344185, 0.344091, 0.344371, 0.344075" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "7.12147, 7.52797, 7.75786, 8.13784, 9.00461, 10.0692", \ + "7.10625, 7.52651, 7.86733, 8.07228, 9.04054, 10.1153", \ + "7.12002, 7.4989, 7.8642, 8.25206, 9.09943, 10.0582", \ + "7.1005, 7.51238, 7.8412, 8.25181, 9.0716, 10.095", \ + "7.11766, 7.51925, 7.78097, 8.25109, 9.09637, 9.98816", \ + "7.09156, 7.46759, 7.85966, 8.26182, 9.07888, 10.0669", \ + "7.12638, 7.52151, 7.77136, 8.08146, 8.98434, 9.99511" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "3.04504, 3.04819, 3.04651, 3.04609, 3.04232, 3.04378", \ + "3.04508, 3.04822, 3.04654, 3.04688, 3.04235, 3.04398", \ + "3.04536, 3.0467, 3.047, 3.04628, 3.04281, 3.04427", \ + "3.04561, 3.04877, 3.04709, 3.0475, 3.0429, 3.04464", \ + "3.04828, 3.05147, 3.04976, 3.05025, 3.04675, 3.04662", \ + "3.04466, 3.05002, 3.04922, 3.0499, 3.04623, 3.04422", \ + "3.04864, 3.05279, 3.04878, 3.04993, 3.04313, 3.04468" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.0250466, 0.0250508, 0.0250492, 0.0250511, 0.0250507, 0.0250499", \ + "0.0247598, 0.0247641, 0.0247684, 0.0247652, 0.0247642, 0.0247662", \ + "0.0286392, 0.0285437, 0.0285487, 0.0286489, 0.0286474, 0.0286425", \ + "0.0403106, 0.0403142, 0.0403188, 0.0403211, 0.0403193, 0.0403168", \ + "0.0651677, 0.0651712, 0.0651715, 0.0651772, 0.0651756, 0.0651694", \ + "0.120938, 0.120937, 0.120941, 0.120943, 0.120938, 0.120935", \ + "0.237351, 0.237338, 0.237385, 0.237401, 0.237299, 0.237299" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.0441749, 0.0441633, 0.0441658, 0.0441633, 0.0441629, 0.0441515", \ + "0.0439176, 0.0439059, 0.0439085, 0.0439079, 0.0439057, 0.0438943", \ + "0.0458766, 0.0458823, 0.0457708, 0.0458741, 0.0457676, 0.0458637", \ + "0.0519618, 0.05195, 0.0519526, 0.0519507, 0.0519497, 0.0519383", \ + "0.0652679, 0.0652569, 0.0652588, 0.0652571, 0.0652543, 0.0652428", \ + "0.0946015, 0.09443, 0.0944554, 0.094588, 0.0945708, 0.0945759", \ + "0.15548, 0.155525, 0.155607, 0.155565, 0.15566, 0.155593" \ + ); + } + } + } + pin (c2p) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.016; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0297152; + rise_capacitance : 0.0298031; + rise_capacitance_range (0.0242945, 0.0343204); + fall_capacitance : 0.0296273; + fall_capacitance_range (0.0248974, 0.0317572); + internal_power () { + when : "!c2p_en"; + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "5.46686e-05, 7.68948e-05, 8.16041e-05, 8.55607e-05, 8.89343e-05, 9.15928e-05, 9.14849e-05" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-5.46686e-05, -7.68948e-05, -8.16041e-05, -8.55607e-05, -8.89343e-05, -9.15928e-05, -9.14849e-05" \ + ); + } + } + internal_power () { + when : "!c2p_en"; + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0214862, -0.0221601, -0.0223643, -0.0224852, -0.0228157, -0.0229528, -0.0230855" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0273005, 0.0271122, 0.0269564, 0.0268388, 0.0270428, 0.026966, 0.0263145" \ + ); + } + } + internal_power () { + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "5.46686e-05, 7.68948e-05, 8.16041e-05, 8.55607e-05, 8.89343e-05, 9.15928e-05, 9.14849e-05" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-5.46686e-05, -7.68948e-05, -8.16041e-05, -8.55607e-05, -8.89343e-05, -9.15928e-05, -9.14849e-05" \ + ); + } + } + internal_power () { + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0214862, -0.0221601, -0.0223643, -0.0224852, -0.0228157, -0.0229528, -0.0230855" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0273005, 0.0271122, 0.0269564, 0.0268388, 0.0270428, 0.026966, 0.0263145" \ + ); + } + } + } + pin (c2p_en) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.011; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.027662; + rise_capacitance : 0.0283908; + rise_capacitance_range (0.024257, 0.033727); + fall_capacitance : 0.0269331; + fall_capacitance_range (0.0235252, 0.0299325); + } + } + cell (sg13g2_IOPadTriOut30mA) { + pad_cell : true; + area : 14400; + cell_footprint : "tri_out"; + pad_drivers : 1; + bond_pads : 1; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 349.682; + when : "!c2p_en&!c2p"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 3171.59; + when : "!c2p_en&!c2p"; + related_pg_pin : vdd; + } + leakage_power () { + value : 349.682; + when : "!c2p_en&c2p"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 4240.54; + when : "!c2p_en&c2p"; + related_pg_pin : vdd; + } + leakage_power () { + value : 540.674; + when : "c2p_en&c2p&pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 4387.79; + when : "c2p_en&c2p&pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 2144.88; + when : "c2p_en&!c2p&!pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 3292.78; + when : "c2p_en&!c2p&!pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 846.231; + related_pg_pin : iovdd; + } + leakage_power () { + value : 3773.18; + related_pg_pin : vdd; + } + pin (pad) { + direction : "output"; + is_pad : true; + function : "c2p"; + three_state : "c2p_en'"; + drive_current : 30; + output_voltage : "pad"; + related_ground_pin : iovss; + related_power_pin : iovdd; + max_capacitance : 10.0761; + capacitance : 0.320954; + rise_capacitance : 0.320969; + rise_capacitance_range (0.320969, 0.320969); + fall_capacitance : 0.32094; + fall_capacitance_range (0.32094, 0.32094); + timing () { + related_pin : "c2p"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.25698, 1.36069, 1.44594, 1.51893, 1.70493, 1.86259", \ + "1.27161, 1.37507, 1.45991, 1.53392, 1.71953, 1.87726", \ + "1.2822, 1.38548, 1.47039, 1.54436, 1.73005, 1.88817", \ + "1.29798, 1.40102, 1.48588, 1.55973, 1.74532, 1.90354", \ + "1.31631, 1.41968, 1.5028, 1.57712, 1.76251, 1.9207", \ + "1.3357, 1.43899, 1.52381, 1.59805, 1.78386, 1.94209", \ + "1.3528, 1.4573, 1.54249, 1.61629, 1.80328, 1.96139" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.358696, 0.486295, 0.59277, 0.687374, 0.941419, 1.18122", \ + "0.358697, 0.486296, 0.592771, 0.687375, 0.94142, 1.18123", \ + "0.358698, 0.486297, 0.592772, 0.687376, 0.941421, 1.18214", \ + "0.358699, 0.486298, 0.592773, 0.687377, 0.941422, 1.18215", \ + "0.3587, 0.486299, 0.592774, 0.687378, 0.941423, 1.18216", \ + "0.358701, 0.4863, 0.592775, 0.687448, 0.941424, 1.18218", \ + "0.360107, 0.487436, 0.593497, 0.687449, 0.944038, 1.18237" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.06784, 1.12985, 1.18581, 1.23822, 1.38097, 1.51149", \ + "1.08638, 1.14833, 1.20296, 1.25663, 1.39945, 1.52946", \ + "1.10151, 1.16329, 1.21936, 1.27089, 1.41472, 1.54426", \ + "1.13116, 1.19301, 1.24758, 1.30125, 1.44418, 1.57399", \ + "1.17608, 1.23734, 1.29392, 1.34619, 1.48872, 1.61837", \ + "1.2433, 1.30526, 1.36163, 1.41356, 1.55638, 1.68665", \ + "1.36178, 1.42351, 1.48008, 1.53121, 1.67507, 1.80449" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.68725, 0.72606, 0.779143, 0.836343, 1.00773, 1.19037", \ + "0.692105, 0.730307, 0.783362, 0.839894, 1.01115, 1.19346", \ + "0.695874, 0.733449, 0.786842, 0.842213, 1.01501, 1.19458", \ + "0.698931, 0.736329, 0.788934, 0.845288, 1.01577, 1.19775", \ + "0.698932, 0.73633, 0.788935, 0.845289, 1.01578, 1.19776", \ + "0.698933, 0.736331, 0.788936, 0.84529, 1.01579, 1.19777", \ + "0.698934, 0.736332, 0.788937, 0.845291, 1.0158, 1.19778" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : negative_unate; + timing_type : three_state_disable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.966732, 0.966733, 0.966734, 0.966735, 0.966736, 0.966737", \ + "0.985837, 0.985838, 0.985839, 0.98584, 0.985841, 0.985842", \ + "0.995347, 0.995348, 0.995349, 0.99535, 0.995351, 0.995352", \ + "1.01872, 1.01873, 1.01874, 1.01875, 1.01876, 1.01877", \ + "1.04525, 1.04526, 1.04527, 1.04528, 1.04529, 1.0453", \ + "1.08815, 1.08816, 1.08817, 1.08818, 1.08819, 1.0882", \ + "1.15938, 1.15939, 1.1594, 1.15941, 1.15942, 1.15943" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.966732, 0.966733, 0.966734, 0.966735, 0.966736, 0.966737", \ + "0.985837, 0.985838, 0.985839, 0.98584, 0.985841, 0.985842", \ + "0.995347, 0.995348, 0.995349, 0.99535, 0.995351, 0.995352", \ + "1.01872, 1.01873, 1.01874, 1.01875, 1.01876, 1.01877", \ + "1.04525, 1.04526, 1.04527, 1.04528, 1.04529, 1.0453", \ + "1.08815, 1.08816, 1.08817, 1.08818, 1.08819, 1.0882", \ + "1.15938, 1.15939, 1.1594, 1.15941, 1.15942, 1.15943" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.28636, 1.28637, 1.28638, 1.28639, 1.2864, 1.28641", \ + "1.31441, 1.31442, 1.31443, 1.31444, 1.31445, 1.31446", \ + "1.32136, 1.32137, 1.32138, 1.32139, 1.3214, 1.32141", \ + "1.35091, 1.35092, 1.35093, 1.35094, 1.35095, 1.35096", \ + "1.39549, 1.3955, 1.39551, 1.39552, 1.39553, 1.39554", \ + "1.46626, 1.46627, 1.46628, 1.46629, 1.4663, 1.46631", \ + "1.54886, 1.54887, 1.54888, 1.54889, 1.5489, 1.54891" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.28636, 1.28637, 1.28638, 1.28639, 1.2864, 1.28641", \ + "1.31441, 1.31442, 1.31443, 1.31444, 1.31445, 1.31446", \ + "1.32136, 1.32137, 1.32138, 1.32139, 1.3214, 1.32141", \ + "1.35091, 1.35092, 1.35093, 1.35094, 1.35095, 1.35096", \ + "1.39549, 1.3955, 1.39551, 1.39552, 1.39553, 1.39554", \ + "1.46626, 1.46627, 1.46628, 1.46629, 1.4663, 1.46631", \ + "1.54886, 1.54887, 1.54888, 1.54889, 1.5489, 1.54891" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : positive_unate; + timing_type : three_state_enable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.21816, 1.33889, 1.43283, 1.51181, 1.70957, 1.87557", \ + "1.23495, 1.35567, 1.44957, 1.52933, 1.72624, 1.88981", \ + "1.24508, 1.3657, 1.45918, 1.53946, 1.73627, 1.89966", \ + "1.26172, 1.38231, 1.47642, 1.55557, 1.7531, 1.91587", \ + "1.28361, 1.40429, 1.49825, 1.57737, 1.77493, 1.94077", \ + "1.30993, 1.43053, 1.52411, 1.60416, 1.80113, 1.96737", \ + "1.33883, 1.45948, 1.55348, 1.63105, 1.82752, 1.99312" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.394377, 0.504373, 0.599623, 0.684318, 0.930617, 1.16444", \ + "0.394378, 0.504502, 0.599624, 0.686784, 0.930618, 1.16445", \ + "0.394649, 0.505002, 0.599625, 0.687291, 0.930619, 1.16446", \ + "0.39465, 0.505003, 0.599633, 0.687292, 0.93062, 1.16447", \ + "0.394651, 0.505004, 0.599635, 0.687293, 0.930621, 1.16448", \ + "0.394652, 0.505005, 0.599636, 0.687294, 0.930622, 1.1645", \ + "0.394653, 0.505006, 0.599637, 0.687295, 0.930623, 1.16451" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.765881, 0.852779, 0.924041, 0.988418, 1.15612, 1.30723", \ + "0.782157, 0.869053, 0.940993, 1.00428, 1.17237, 1.32205", \ + "0.790321, 0.877523, 0.948718, 1.01286, 1.18056, 1.33209", \ + "0.803457, 0.89066, 0.961854, 1.02599, 1.19369, 1.3448", \ + "0.819316, 0.906326, 0.977658, 1.04166, 1.20922, 1.3605", \ + "0.834275, 0.921036, 0.991835, 1.05679, 1.22417, 1.37566", \ + "0.84869, 0.935631, 1.00702, 1.07074, 1.23883, 1.38999" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.255713, 0.342926, 0.421822, 0.499214, 0.722081, 0.943038", \ + "0.255717, 0.342927, 0.423032, 0.499215, 0.722082, 0.943039", \ + "0.255718, 0.343095, 0.423033, 0.499216, 0.722083, 0.943067", \ + "0.255719, 0.343096, 0.423034, 0.499217, 0.722084, 0.943068", \ + "0.25583, 0.343097, 0.423035, 0.499218, 0.722085, 0.943069", \ + "0.255831, 0.343098, 0.423036, 0.499219, 0.722777, 0.94307", \ + "0.255832, 0.343099, 0.423037, 0.49922, 0.726385, 0.943363" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "13.0488, 12.6743, 12.531, 12.3696, 12.0575, 11.8903", \ + "13.0801, 12.7092, 12.5345, 12.4003, 12.0472, 11.8927", \ + "13.1019, 12.7149, 12.4926, 12.3655, 12.0694, 12.0269", \ + "13.13, 12.7451, 12.5828, 12.3853, 12.0839, 12.049", \ + "13.151, 12.7813, 12.5481, 12.4838, 12.0992, 12.0502", \ + "13.0694, 12.6801, 12.5156, 12.4241, 12.0424, 12.0174", \ + "12.9108, 12.5594, 12.3616, 12.1728, 12.1733, 11.9509" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "71.4519, 67.2434, 63.7137, 60.6912, 53.5782, 48.4935", \ + "72.0733, 67.8667, 64.3248, 61.2744, 54.0691, 48.9834", \ + "72.5849, 68.3733, 64.844, 61.7442, 54.54, 49.4011", \ + "72.9835, 68.7346, 65.164, 62.0815, 54.8214, 49.6546", \ + "72.876, 68.6863, 65.1016, 62.0014, 54.7623, 49.5854", \ + "72.3688, 68.1809, 64.5551, 61.5782, 54.3093, 49.2119", \ + "70.2288, 66.1407, 62.6453, 59.6122, 52.6206, 47.6219" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.0602048, 0.0602052, 0.0602039, 0.0602144, 0.0602124, 0.0602116", \ + "0.0583108, 0.0583103, 0.0583075, 0.0583149, 0.0583092, 0.0583087", \ + "0.0601979, 0.0601975, 0.060196, 0.0602023, 0.060196, 0.0601956", \ + "0.0680632, 0.0680645, 0.0680621, 0.0680685, 0.0680627, 0.0680626", \ + "0.0903565, 0.0903559, 0.0903647, 0.0903663, 0.0903638, 0.0903659", \ + "0.141566, 0.141625, 0.141621, 0.141624, 0.141564, 0.141563", \ + "0.252369, 0.252369, 0.2524, 0.252326, 0.252338, 0.252385" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.149663, 0.149662, 0.149662, 0.149663, 0.149656, 0.149652", \ + "0.148072, 0.148062, 0.148067, 0.148067, 0.148066, 0.148064", \ + "0.150593, 0.150591, 0.150595, 0.150595, 0.150593, 0.15059", \ + "0.159702, 0.159695, 0.159695, 0.159692, 0.159694, 0.159692", \ + "0.1827, 0.182702, 0.182697, 0.182704, 0.1827, 0.182698", \ + "0.234589, 0.23459, 0.234575, 0.234759, 0.234579, 0.23477", \ + "0.344193, 0.344189, 0.344179, 0.344153, 0.344055, 0.344254" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "11.0289, 11.3562, 11.7482, 11.9479, 13.3292, 14.3398", \ + "11.0295, 11.3541, 11.7476, 12.1371, 13.32, 14.0727", \ + "11.0115, 11.3261, 11.7142, 12.109, 13.321, 13.9383", \ + "11.0135, 11.3264, 11.734, 12.0817, 13.3086, 13.9117", \ + "11.0236, 11.3488, 11.7417, 12.0868, 13.316, 14.3214", \ + "11.0308, 11.3549, 11.7274, 12.1347, 13.3298, 14.3616", \ + "11.0257, 11.3473, 11.6393, 11.8621, 13.0468, 14.0545" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "5.04922, 5.05131, 5.05243, 5.05743, 5.05903, 5.05707", \ + "5.04982, 5.0519, 5.05618, 5.05697, 5.05963, 5.05999", \ + "5.04965, 5.0529, 5.05461, 5.05787, 5.05947, 5.05784", \ + "5.0498, 5.05305, 5.05476, 5.05802, 5.05961, 5.05763", \ + "5.05353, 5.05573, 5.05764, 5.06069, 5.06184, 5.0603", \ + "5.04845, 5.05094, 5.05558, 5.05774, 5.05965, 5.05739", \ + "5.05509, 5.06758, 5.06259, 5.06426, 5.06464, 5.05912" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.0250352, 0.0250348, 0.0250355, 0.0250353, 0.0250389, 0.0250417", \ + "0.0247481, 0.0247479, 0.0247483, 0.0247492, 0.0247523, 0.0247515", \ + "0.0286291, 0.0286295, 0.0285304, 0.0286299, 0.028534, 0.0285322", \ + "0.0403021, 0.0403023, 0.040302, 0.0403025, 0.0403054, 0.0403038", \ + "0.0651553, 0.0651551, 0.0651556, 0.065156, 0.065159, 0.0651618", \ + "0.122176, 0.122177, 0.122178, 0.122179, 0.122182, 0.122185", \ + "0.237636, 0.237632, 0.237605, 0.237624, 0.237569, 0.237603" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.0441164, 0.0441141, 0.0441123, 0.0441062, 0.0441056, 0.0441042", \ + "0.0438554, 0.0438533, 0.0438492, 0.0438425, 0.0438426, 0.0438382", \ + "0.0457166, 0.0457126, 0.0457095, 0.0457064, 0.0457058, 0.0458119", \ + "0.0518913, 0.0518873, 0.0518842, 0.0518812, 0.0518805, 0.0518788", \ + "0.0651971, 0.0651904, 0.0651905, 0.0651841, 0.0651832, 0.0651816", \ + "0.0951244, 0.0950953, 0.0949884, 0.0951062, 0.0949642, 0.0951036", \ + "0.156587, 0.156377, 0.156473, 0.156488, 0.156492, 0.156516" \ + ); + } + } + } + pin (c2p) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.016; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0297153; + rise_capacitance : 0.0298035; + rise_capacitance_range (0.0242949, 0.0343239); + fall_capacitance : 0.0296272; + fall_capacitance_range (0.0248976, 0.0317563); + internal_power () { + when : "!c2p_en"; + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.000175573, 0.000196651, 0.000201937, 0.000207166, 0.000211544, 0.000214563, 0.000214657" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.000175573, -0.000196651, -0.000201937, -0.000207166, -0.000211544, -0.000214563, -0.000214657" \ + ); + } + } + internal_power () { + when : "!c2p_en"; + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0214863, -0.0221594, -0.0223753, -0.0224852, -0.0228153, -0.0229528, -0.0230855" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0273008, 0.0269573, 0.0269648, 0.0268445, 0.027037, 0.0269621, 0.0263593" \ + ); + } + } + internal_power () { + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.000175573, 0.000196651, 0.000201937, 0.000207166, 0.000211544, 0.000214563, 0.000214657" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.000175573, -0.000196651, -0.000201937, -0.000207166, -0.000211544, -0.000214563, -0.000214657" \ + ); + } + } + internal_power () { + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0214863, -0.0221594, -0.0223753, -0.0224852, -0.0228153, -0.0229528, -0.0230855" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0273008, 0.0269573, 0.0269648, 0.0268445, 0.027037, 0.0269621, 0.0263593" \ + ); + } + } + } + pin (c2p_en) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.011; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0276544; + rise_capacitance : 0.0283756; + rise_capacitance_range (0.0242571, 0.0337233); + fall_capacitance : 0.0269332; + fall_capacitance_range (0.0235246, 0.0298754); + } + } + cell (sg13g2_IOPadTriOut4mA) { + pad_cell : true; + area : 14400; + cell_footprint : "tri_out"; + pad_drivers : 1; + bond_pads : 1; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 37.1844; + when : "!c2p_en&!c2p"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 3171.5; + when : "!c2p_en&!c2p"; + related_pg_pin : vdd; + } + leakage_power () { + value : 37.1844; + when : "!c2p_en&c2p"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 4240.44; + when : "!c2p_en&c2p"; + related_pg_pin : vdd; + } + leakage_power () { + value : 118.253; + when : "c2p_en&c2p&pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 4387.67; + when : "c2p_en&c2p&pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 288.414; + when : "c2p_en&!c2p&!pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 3292.48; + when : "c2p_en&!c2p&!pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 120.259; + related_pg_pin : iovdd; + } + leakage_power () { + value : 3773.02; + related_pg_pin : vdd; + } + pin (pad) { + direction : "output"; + is_pad : true; + function : "c2p"; + three_state : "c2p_en'"; + drive_current : 4; + output_voltage : "pad"; + related_ground_pin : iovss; + related_power_pin : iovdd; + max_capacitance : 1.68907; + capacitance : 0.160427; + rise_capacitance : 0.164378; + rise_capacitance_range (0.164378, 0.164378); + fall_capacitance : 0.156476; + fall_capacitance_range (0.156476, 0.156476); + timing () { + related_pin : "c2p"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.06088, 1.36519, 1.66756, 1.96959, 2.87299, 3.77588", \ + "1.07685, 1.38101, 1.68332, 1.98556, 2.88908, 3.79216", \ + "1.08696, 1.39111, 1.69339, 1.99543, 2.89889, 3.80208", \ + "1.10101, 1.40512, 1.70746, 2.0095, 2.91327, 3.81625", \ + "1.11984, 1.42402, 1.72626, 2.02839, 2.93186, 3.83488", \ + "1.14082, 1.44489, 1.74739, 2.04912, 2.95263, 3.85715", \ + "1.16079, 1.46507, 1.76769, 2.06926, 2.97293, 3.87628" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.772808, 1.39311, 2.01975, 2.64848, 4.54029, 6.42914", \ + "0.772873, 1.39312, 2.01976, 2.6485, 4.5403, 6.42992", \ + "0.772874, 1.39313, 2.01977, 2.64851, 4.5403, 6.42993", \ + "0.772875, 1.39314, 2.01978, 2.64887, 4.54031, 6.42994", \ + "0.772876, 1.39315, 2.01979, 2.64888, 4.54032, 6.42995", \ + "0.772877, 1.39316, 2.0198, 2.64947, 4.54033, 6.42996", \ + "0.777656, 1.39322, 2.01981, 2.64948, 4.54034, 6.42997" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.892687, 1.20085, 1.50765, 1.81486, 2.7352, 3.65539", \ + "0.908971, 1.21686, 1.52391, 1.83083, 2.75124, 3.67147", \ + "0.922834, 1.23069, 1.53752, 1.84434, 2.76524, 3.68556", \ + "0.951341, 1.25887, 1.56578, 1.87283, 2.7927, 3.71371", \ + "0.996931, 1.30428, 1.61133, 1.9181, 2.83852, 3.75926", \ + "1.06561, 1.37358, 1.6805, 1.98737, 2.90813, 3.82872", \ + "1.19042, 1.49894, 1.80603, 2.11305, 3.03399, 3.95425" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.706803, 1.29069, 1.87902, 2.4679, 4.23785, 6.00938", \ + "0.706804, 1.29071, 1.87903, 2.46929, 4.23786, 6.01152", \ + "0.706977, 1.29072, 1.87904, 2.46932, 4.23823, 6.01153", \ + "0.707012, 1.29073, 1.87905, 2.46933, 4.23824, 6.01154", \ + "0.707317, 1.29074, 1.87906, 2.46977, 4.23825, 6.01155", \ + "0.707318, 1.2909, 1.87907, 2.46978, 4.23826, 6.01156", \ + "0.708663, 1.29091, 1.87908, 2.46979, 4.24021, 6.01157" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : negative_unate; + timing_type : three_state_disable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.644849, 0.64485, 0.644851, 0.644852, 0.644853, 0.644854", \ + "0.666656, 0.666657, 0.666658, 0.666659, 0.66666, 0.666661", \ + "0.677918, 0.677919, 0.67792, 0.677921, 0.677922, 0.677923", \ + "0.699274, 0.699275, 0.699276, 0.699277, 0.699278, 0.699279", \ + "0.72864, 0.728641, 0.728642, 0.728643, 0.728644, 0.728645", \ + "0.770678, 0.770679, 0.77068, 0.770681, 0.770682, 0.770683", \ + "0.842347, 0.842348, 0.842349, 0.84235, 0.842351, 0.842352" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.644849, 0.64485, 0.644851, 0.644852, 0.644853, 0.644854", \ + "0.666656, 0.666657, 0.666658, 0.666659, 0.66666, 0.666661", \ + "0.677918, 0.677919, 0.67792, 0.677921, 0.677922, 0.677923", \ + "0.699274, 0.699275, 0.699276, 0.699277, 0.699278, 0.699279", \ + "0.72864, 0.728641, 0.728642, 0.728643, 0.728644, 0.728645", \ + "0.770678, 0.770679, 0.77068, 0.770681, 0.770682, 0.770683", \ + "0.842347, 0.842348, 0.842349, 0.84235, 0.842351, 0.842352" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.499289, 0.49929, 0.499291, 0.499292, 0.499293, 0.499294", \ + "0.520756, 0.520757, 0.520758, 0.520759, 0.52076, 0.520761", \ + "0.537342, 0.537343, 0.537344, 0.537345, 0.537346, 0.537347", \ + "0.567044, 0.567045, 0.567046, 0.567047, 0.567048, 0.567049", \ + "0.608342, 0.608343, 0.608344, 0.608345, 0.608346, 0.608347", \ + "0.669482, 0.669483, 0.669484, 0.669485, 0.669486, 0.669487", \ + "0.772345, 0.772346, 0.772347, 0.772348, 0.772349, 0.77235" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.499289, 0.49929, 0.499291, 0.499292, 0.499293, 0.499294", \ + "0.520756, 0.520757, 0.520758, 0.520759, 0.52076, 0.520761", \ + "0.537342, 0.537343, 0.537344, 0.537345, 0.537346, 0.537347", \ + "0.567044, 0.567045, 0.567046, 0.567047, 0.567048, 0.567049", \ + "0.608342, 0.608343, 0.608344, 0.608345, 0.608346, 0.608347", \ + "0.669482, 0.669483, 0.669484, 0.669485, 0.669486, 0.669487", \ + "0.772345, 0.772346, 0.772347, 0.772348, 0.772349, 0.77235" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : positive_unate; + timing_type : three_state_enable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.06285, 1.37931, 1.69373, 2.00729, 2.94726, 3.88794", \ + "1.07928, 1.39531, 1.70983, 2.02368, 2.96459, 3.90435", \ + "1.09079, 1.40724, 1.72181, 2.03523, 2.97309, 3.91339", \ + "1.10738, 1.42383, 1.73841, 2.05165, 2.99202, 3.93246", \ + "1.12963, 1.44564, 1.76086, 2.07414, 3.01434, 3.9549", \ + "1.15531, 1.47109, 1.78553, 2.09845, 3.03878, 3.97933", \ + "1.18269, 1.49885, 1.8132, 2.12782, 3.06715, 4.0066" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.771337, 1.39198, 2.01962, 2.64862, 4.53886, 6.42849", \ + "0.771338, 1.39202, 2.01969, 2.64863, 4.53887, 6.4285", \ + "0.771339, 1.39203, 2.01974, 2.64886, 4.54042, 6.42851", \ + "0.77134, 1.39204, 2.01975, 2.64887, 4.54043, 6.42852", \ + "0.771341, 1.39205, 2.01976, 2.64888, 4.54044, 6.42853", \ + "0.771391, 1.39206, 2.01977, 2.64889, 4.54045, 6.42904", \ + "0.774918, 1.39376, 2.0201, 2.6489, 4.54046, 6.42947" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.909767, 1.25096, 1.59107, 1.93082, 2.94946, 3.9676", \ + "0.925059, 1.26635, 1.60648, 1.94651, 2.96482, 3.98296", \ + "0.933643, 1.27491, 1.6156, 1.95562, 2.97393, 3.9915", \ + "0.947185, 1.28854, 1.62897, 1.96842, 2.98732, 4.00517", \ + "0.962376, 1.30374, 1.6438, 1.98383, 3.00213, 4.02027", \ + "0.978211, 1.31951, 1.65963, 1.99934, 3.01796, 4.03609", \ + "0.991483, 1.33285, 1.67292, 2.01278, 3.03108, 4.04899" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.702142, 1.28817, 1.87743, 2.46789, 4.23778, 6.00774", \ + "0.702143, 1.28837, 1.87744, 2.4679, 4.23779, 6.00775", \ + "0.702155, 1.28891, 1.87745, 2.46791, 4.2378, 6.00778", \ + "0.702167, 1.28892, 1.87787, 2.46792, 4.23824, 6.00779", \ + "0.702168, 1.28893, 1.87788, 2.46793, 4.23825, 6.0078", \ + "0.702592, 1.28894, 1.87789, 2.46794, 4.23826, 6.00781", \ + "0.702593, 1.28895, 1.8779, 2.46806, 4.23852, 6.00844" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "3.83829, 3.81155, 3.77338, 3.74263, 3.64766, 3.51191", \ + "3.83918, 3.80373, 3.77071, 3.73342, 3.64489, 3.51454", \ + "3.84205, 3.80713, 3.77269, 3.73144, 3.64511, 3.50392", \ + "3.8375, 3.80265, 3.76956, 3.73597, 3.64529, 3.48689", \ + "3.83766, 3.80425, 3.7688, 3.73291, 3.64568, 3.49448", \ + "3.82882, 3.79136, 3.75937, 3.73352, 3.63409, 3.49506", \ + "3.86529, 3.80649, 3.76726, 3.73835, 3.61724, 3.52696" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.35388, 2.33823, 2.33215, 2.32589, 2.32135, 2.31971", \ + "2.36804, 2.34582, 2.33598, 2.33129, 2.32309, 2.32056", \ + "2.37829, 2.35248, 2.33962, 2.33536, 2.3255, 2.32185", \ + "2.38876, 2.35975, 2.34485, 2.34017, 2.32848, 2.32378", \ + "2.39573, 2.36808, 2.35363, 2.34657, 2.33712, 2.3331", \ + "2.38449, 2.36077, 2.34519, 2.34459, 2.33206, 2.3293", \ + "2.35302, 2.34463, 2.34314, 2.34062, 2.33788, 2.33966" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.0602633, 0.0602576, 0.0602535, 0.0602534, 0.0602558, 0.0602569", \ + "0.0583623, 0.0583535, 0.0583465, 0.0583532, 0.058356, 0.058356", \ + "0.0604252, 0.0604176, 0.0604107, 0.0604119, 0.0604167, 0.0604146", \ + "0.0680963, 0.0680855, 0.0680797, 0.0680892, 0.0680901, 0.0680899", \ + "0.0904834, 0.0904756, 0.0904672, 0.0904704, 0.0904732, 0.0904751", \ + "0.141719, 0.141668, 0.141712, 0.14167, 0.14167, 0.141672", \ + "0.25205, 0.252061, 0.252122, 0.252071, 0.252023, 0.251999" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.149889, 0.149889, 0.14989, 0.149886, 0.149881, 0.149893", \ + "0.148297, 0.148299, 0.148289, 0.1483, 0.148285, 0.148293", \ + "0.150828, 0.150837, 0.150826, 0.150837, 0.150823, 0.15083", \ + "0.159935, 0.159938, 0.159924, 0.15994, 0.159922, 0.159929", \ + "0.182999, 0.183006, 0.182992, 0.182998, 0.182996, 0.182997", \ + "0.234983, 0.234989, 0.234833, 0.234993, 0.234873, 0.234897", \ + "0.344403, 0.344456, 0.344305, 0.344295, 0.344553, 0.344514" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "3.64209, 3.88402, 4.11689, 4.34506, 5.05717, 5.76184", \ + "3.63493, 3.86492, 4.09914, 4.33177, 5.04508, 5.75435", \ + "3.64061, 3.8809, 4.12103, 4.34837, 5.04803, 5.71842", \ + "3.63977, 3.88064, 4.11613, 4.34642, 5.07362, 5.76076", \ + "3.64501, 3.87217, 4.11869, 4.34999, 5.07704, 5.73926", \ + "3.62602, 3.85515, 4.08132, 4.30564, 5.04248, 5.70694", \ + "3.66981, 3.91198, 4.10292, 4.34902, 5.05595, 5.76256" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.33772, 1.33806, 1.33613, 1.33633, 1.33481, 1.33436", \ + "1.33617, 1.33559, 1.3348, 1.33332, 1.33212, 1.33196", \ + "1.33578, 1.33466, 1.33752, 1.33675, 1.33562, 1.33216", \ + "1.33885, 1.3387, 1.33673, 1.33599, 1.33554, 1.33497", \ + "1.33884, 1.33801, 1.33724, 1.33672, 1.33559, 1.33547", \ + "1.33664, 1.33619, 1.33599, 1.33541, 1.33393, 1.33331", \ + "1.33615, 1.33503, 1.33429, 1.33376, 1.33262, 1.33251" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.0250939, 0.0250875, 0.025084, 0.0250833, 0.0250884, 0.0250906", \ + "0.0248071, 0.0247946, 0.0247923, 0.024792, 0.0248043, 0.0248001", \ + "0.0286894, 0.0286831, 0.0286801, 0.0286799, 0.0285788, 0.0285786", \ + "0.0403612, 0.040355, 0.0403524, 0.0403516, 0.0403552, 0.0403533", \ + "0.0652253, 0.065216, 0.0652166, 0.065218, 0.0652185, 0.0652186", \ + "0.122551, 0.122545, 0.122541, 0.122542, 0.122543, 0.122542", \ + "0.241689, 0.241607, 0.241725, 0.241724, 0.241701, 0.241637" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.0443727, 0.0443736, 0.0443736, 0.0443732, 0.044373, 0.0443706", \ + "0.0441152, 0.0441133, 0.0441107, 0.0441129, 0.0441117, 0.0441107", \ + "0.0460811, 0.0460786, 0.0459781, 0.0459824, 0.0459805, 0.0460761", \ + "0.05218, 0.0521756, 0.0521754, 0.0521714, 0.0521756, 0.052172", \ + "0.0655177, 0.0655114, 0.0655108, 0.0655149, 0.065512, 0.0655107", \ + "0.0950557, 0.0951181, 0.0950897, 0.0949691, 0.0951248, 0.0951167", \ + "0.159656, 0.159718, 0.159687, 0.159536, 0.159558, 0.15959" \ + ); + } + } + } + pin (c2p) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.016; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0297151; + rise_capacitance : 0.0298029; + rise_capacitance_range (0.0242946, 0.0343179); + fall_capacitance : 0.0296273; + fall_capacitance_range (0.0248972, 0.0317574); + internal_power () { + when : "!c2p_en"; + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0, 0, 0, 3.65218e-06, 6.44846e-06, 8.66516e-06, 8.5694e-06" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0, 0, 0, -3.65218e-06, -6.44846e-06, -8.66516e-06, -8.5694e-06" \ + ); + } + } + internal_power () { + when : "!c2p_en"; + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0214866, -0.02216, -0.022376, -0.0224851, -0.0228165, -0.0229528, -0.0230851" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0273012, 0.0271121, 0.0269545, 0.0268374, 0.0270443, 0.026967, 0.0263061" \ + ); + } + } + internal_power () { + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0, 0, 0, 3.65218e-06, 6.44846e-06, 8.66516e-06, 8.5694e-06" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0, 0, 0, -3.65218e-06, -6.44846e-06, -8.66516e-06, -8.5694e-06" \ + ); + } + } + internal_power () { + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0214866, -0.02216, -0.022376, -0.0224851, -0.0228165, -0.0229528, -0.0230851" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0273012, 0.0271121, 0.0269545, 0.0268374, 0.0270443, 0.026967, 0.0263061" \ + ); + } + } + } + pin (c2p_en) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.011; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0276546; + rise_capacitance : 0.0283744; + rise_capacitance_range (0.0242582, 0.033655); + fall_capacitance : 0.0269348; + fall_capacitance_range (0.0235268, 0.0298685); + } + } + cell (sg13g2_IOPadVdd) { + area : 14400; + pad_cell : true; + bond_pads : 1; + dont_touch : true; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + is_pad : true; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 0; + related_pg_pin : iovdd; + } + leakage_power () { + value : 0; + related_pg_pin : vdd; + } + } + cell (sg13g2_IOPadVss) { + area : 14400; + pad_cell : true; + bond_pads : 1; + dont_touch : true; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + is_pad : true; + } + leakage_power () { + value : 0; + related_pg_pin : iovdd; + } + leakage_power () { + value : 1.15235; + related_pg_pin : vdd; + } + } +} diff --git a/flow/platforms/ihp-sg13g2/lib/sg13g2_io_fast_1p65V_3p6V_m40C.lib b/flow/platforms/ihp-sg13g2/lib/sg13g2_io_fast_1p65V_3p6V_m40C.lib new file mode 100644 index 0000000000..a8d38e287c --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lib/sg13g2_io_fast_1p65V_3p6V_m40C.lib @@ -0,0 +1,4599 @@ +/************************************************************************ + + Copyright 2024 IHP PDK Authors + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + https://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +************************************************************************/ + +library (sg13g2_io_fast_1p65V_3p6V_m40C) { + comment : "IHP Microelectronics GmbH, 2024"; + date : "$Date: Wed May 8 12:28:37 2024 $"; + revision : "$Revision: 0.0.1 $"; + delay_model : table_lookup; + capacitive_load_unit (1,pf); + current_unit : "1uA"; + leakage_power_unit : "1pW"; + pulling_resistance_unit : "1kohm"; + time_unit : "1ns"; + voltage_unit : "1V"; + voltage_map (vdd, 1.65); + voltage_map (iovdd, 3.6); + voltage_map (iovss, 0); + voltage_map (vss, 0); + voltage_map (GND, 0); + define_cell_area (pad_drivers, pad_driver_sites); + define_cell_area (bond_pads, pad_slots); + default_output_pin_cap : 0; + default_inout_pin_cap : 1; + default_input_pin_cap : 1; + default_fanout_load : 1; + default_cell_leakage_power : 0; + default_max_transition : 1.2; + default_leakage_power_density : 0; + default_max_capacitance : 0.3; + default_max_fanout : 8; + default_wire_load_area : 0.29; + default_wire_load_capacitance : 0.0003; + default_wire_load_mode : "enclosed"; + default_wire_load_resistance : 0.0057; + in_place_swap_mode : match_footprint; + input_threshold_pct_fall : 50; + input_threshold_pct_rise : 50; + nom_process : 1; + nom_temperature : -40; + nom_voltage : 1.65; + output_threshold_pct_fall : 50; + output_threshold_pct_rise : 50; + slew_derate_from_library : 1; + slew_lower_threshold_pct_fall : 10; + slew_lower_threshold_pct_rise : 10; + slew_upper_threshold_pct_fall : 90; + slew_upper_threshold_pct_rise : 90; + operating_conditions (sg13g2_io_fast_1p65V_3p6V_m40C) { + process : 1; + temperature : -40; + voltage : 1.65; + } + input_voltage (pad) { + vih : 3.3; + vil : 0; + vimax : 3.3; + vimin : 0; + } + input_voltage (core) { + vih : 1.2; + vil : 0; + vimax : 1.2; + vimin : 0; + } + output_voltage (pad) { + voh : 3.3; + vol : 0; + vomax : 3.3; + vomin : 0; + } + output_voltage (core) { + voh : 1.2; + vol : 0; + vomax : 1.2; + vomin : 0; + } + wire_load (Zero) { + area : 0.01; + capacitance : 0.0001; + resistance : 0.0001; + slope : 1; + fanout_length (1, 0.01); + fanout_length (5, 0.01); + fanout_length (20, 0.01); + } + wire_load ("0_1k") { + area : 0.36; + capacitance : 0.0001; + resistance : 0.0035; + slope : 7.387; + fanout_length (1, 6.43); + fanout_length (5, 38.56); + fanout_length (20, 146.8); + } + wire_load ("0_5k") { + area : 0.36; + capacitance : 0.0001; + resistance : 0.0042; + slope : 10.99; + fanout_length (1, 7.89); + fanout_length (5, 47.32); + fanout_length (20, 169.4); + } + wire_load ("1k") { + area : 0.36; + capacitance : 0.0002; + resistance : 0.0053; + slope : 10.9; + fanout_length (1, 9.93); + fanout_length (5, 59.59); + fanout_length (20, 215.6); + } + wire_load ("2k") { + area : 0.36; + capacitance : 0.0002; + resistance : 0.0063; + slope : 16.87; + fanout_length (1, 11.68); + fanout_length (5, 70.11); + fanout_length (20, 239.5); + } + wire_load ("5k") { + area : 0.36; + capacitance : 0.0003; + resistance : 0.0072; + slope : 14.58; + fanout_length (1, 13.44); + fanout_length (5, 80.62); + fanout_length (20, 287.1); + } + wire_load ("10k") { + area : 0.37; + capacitance : 0.0003; + resistance : 0.008; + slope : 18.94; + fanout_length (1, 14.9); + fanout_length (5, 89.39); + fanout_length (20, 381.6); + } + wire_load ("30k") { + area : 0.37; + capacitance : 0.0003; + resistance : 0.0094; + slope : 24.61; + fanout_length (1, 17.53); + fanout_length (5, 105.2); + fanout_length (20, 515.5); + } + wire_load ("50k") { + area : 0.37; + capacitance : 0.0005; + resistance : 0.0152; + slope : 31.81; + fanout_length (1, 28.33); + fanout_length (5, 170); + fanout_length (20, 607.6); + } + wire_load ("100k") { + area : 0.39; + capacitance : 0.0009; + resistance : 0.0265; + slope : 40.22; + fanout_length (1, 49.37); + fanout_length (5, 296.2); + fanout_length (20, 812.1); + } + wire_load ("200k") { + area : 0.41; + capacitance : 0.0016; + resistance : 0.0456; + slope : 52.68; + fanout_length (1, 84.71); + fanout_length (5, 508.3); + fanout_length (20, 1051.7); + } + wire_load ("500k") { + area : 0.45; + capacitance : 0.0027; + resistance : 0.076; + slope : 67.44; + fanout_length (1, 141.4); + fanout_length (5, 848.3); + fanout_length (20, 1527.1); + } + wire_load_selection ("4_metls_routing") { + wire_load_from_area (0, 635, 0_1k); + wire_load_from_area (635, 3175, 0_5k); + wire_load_from_area (3175, 6350, 1k); + wire_load_from_area (6350, 12701, 2k); + wire_load_from_area (12701, 31752, 5k); + wire_load_from_area (31752, 63504, 10k); + wire_load_from_area (63504, 190512, 30k); + wire_load_from_area (190512, 317520, 50k); + wire_load_from_area (317520, 635040, 100k); + wire_load_from_area (635040, 1.27008e+06, 200k); + wire_load_from_area (1.27008e+06, 3.1752e+06, 500k); + } + default_wire_load : "1k"; + default_operating_conditions : sg13g2_io_fast_1p65V_3p6V_m40C; + default_wire_load_selection : "4_metls_routing"; + lu_table_template (delay_template_7x6_16) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 3, 7, 9, 12, 15"); + } + power_lut_template (passive_power_template_7x1_16) { + variable_1 : input_transition_time; + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + } + power_lut_template (power_template_7x6_16) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 3, 7, 9, 12, 15"); + } + cell (sg13g2_IOPadIOVdd) { + area : 14400; + pad_cell : true; + bond_pads : 1; + dont_touch : true; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + is_pad : true; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 7677.59; + related_pg_pin : iovdd; + } + leakage_power () { + value : 0; + related_pg_pin : vdd; + } + } + cell (sg13g2_IOPadIOVss) { + area : 14400; + pad_cell : true; + bond_pads : 1; + dont_touch : true; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + is_pad : true; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 0; + related_pg_pin : iovdd; + } + leakage_power () { + value : 2.86405; + related_pg_pin : vdd; + } + } + cell (sg13g2_IOPadIn) { + pad_cell : true; + area : 14400; + cell_footprint : "input"; + pad_drivers : 1; + bond_pads : 1; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 0; + when : "pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 922.445; + when : "pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 0; + when : "!pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 3192.46; + when : "!pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 0; + related_pg_pin : iovdd; + } + leakage_power () { + value : 2057.45; + related_pg_pin : vdd; + } + pin (p2c) { + direction : "output"; + output_voltage : "core"; + function : "pad"; + related_ground_pin : vss; + related_power_pin : vdd; + max_capacitance : 1.71416; + timing () { + related_pin : "pad"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0493016, 0.058503, 0.0757703, 0.0919474, 0.107867, 0.123564", \ + "0.0493026, 0.058504, 0.0757713, 0.0919484, 0.107868, 0.123565", \ + "0.0493036, 0.058505, 0.0757723, 0.0919494, 0.107869, 0.123566", \ + "0.0493046, 0.058506, 0.0757733, 0.0919504, 0.10787, 0.123567", \ + "0.0493056, 0.058507, 0.0757743, 0.0919514, 0.107871, 0.123568", \ + "0.0493066, 0.058508, 0.0757753, 0.0919524, 0.107872, 0.123569", \ + "0.0493076, 0.058509, 0.0757763, 0.0919534, 0.107873, 0.12357" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0351829, 0.0520313, 0.086066, 0.120071, 0.154469, 0.189216", \ + "0.0388672, 0.0548156, 0.088168, 0.122189, 0.157127, 0.191602", \ + "0.0457502, 0.0611199, 0.0927111, 0.125556, 0.15926, 0.193704", \ + "0.0487259, 0.0641572, 0.0950036, 0.127549, 0.160742, 0.194705", \ + "0.0614145, 0.0765083, 0.105884, 0.13687, 0.168894, 0.201409", \ + "0.0823411, 0.0972964, 0.125943, 0.154633, 0.184725, 0.215817", \ + "0.097491, 0.112485, 0.141502, 0.169413, 0.197627, 0.228027" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.202854, 0.214687, 0.234343, 0.251552, 0.267083, 0.282595", \ + "0.256781, 0.268691, 0.288413, 0.305196, 0.321346, 0.336511", \ + "0.375112, 0.386894, 0.406676, 0.423698, 0.439187, 0.454294", \ + "0.431721, 0.443503, 0.462817, 0.47996, 0.495585, 0.510584", \ + "0.724361, 0.736656, 0.756905, 0.773992, 0.789873, 0.804525", \ + "1.25661, 1.27038, 1.29311, 1.31209, 1.32926, 1.34525", \ + "1.72191, 1.73663, 1.76061, 1.78101, 1.799, 1.81577" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0573324, 0.070862, 0.0974163, 0.123521, 0.149566, 0.176558", \ + "0.0573334, 0.070863, 0.0974173, 0.123522, 0.149816, 0.176607", \ + "0.0573344, 0.070864, 0.0975316, 0.123557, 0.149817, 0.176608", \ + "0.0578739, 0.0716363, 0.098352, 0.124531, 0.150682, 0.177256", \ + "0.071745, 0.084168, 0.109042, 0.133422, 0.158383, 0.183947", \ + "0.099268, 0.111414, 0.135365, 0.158708, 0.18262, 0.206984", \ + "0.118717, 0.130819, 0.154075, 0.17753, 0.200158, 0.223951" \ + ); + } + } + internal_power () { + related_pin : "pad"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "9.24818e-09, 9.2497e-09, 9.24959e-09, 9.25019e-09, 9.24968e-09, 9.25012e-09", \ + "1.79976e-08, 1.79985e-08, 1.79964e-08, 1.79974e-08, 1.79974e-08, 1.79974e-08", \ + "3.54943e-08, 3.54944e-08, 3.54954e-08, 3.54947e-08, 3.54947e-08, 3.54932e-08", \ + "4.42435e-08, 4.42447e-08, 4.42441e-08, 4.42424e-08, 4.42422e-08, 4.42433e-08", \ + "8.79846e-08, 8.79852e-08, 8.79857e-08, 8.79861e-08, 8.79862e-08, 8.79821e-08", \ + "1.7546e-07, 1.75465e-07, 1.75466e-07, 1.75464e-07, 1.75465e-07, 1.75463e-07", \ + "2.33236e-07, 2.33235e-07, 2.33238e-07, 2.33235e-07, 2.33236e-07, 2.33235e-07" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "-9.24818e-09, -9.2497e-09, -9.24959e-09, -9.25e-09, -9.24968e-09, -9.25012e-09", \ + "-1.79976e-08, -1.79975e-08, -1.79964e-08, -1.79974e-08, -1.79974e-08, -1.79974e-08", \ + "-3.54943e-08, -3.54944e-08, -3.54953e-08, -3.54947e-08, -3.54947e-08, -3.54932e-08", \ + "-4.42406e-08, -4.42408e-08, -4.42416e-08, -4.42417e-08, -4.42422e-08, -4.42423e-08", \ + "-8.79811e-08, -8.79811e-08, -8.79811e-08, -8.79816e-08, -8.79813e-08, -8.79819e-08", \ + "-1.7546e-07, -1.75462e-07, -1.75462e-07, -1.75462e-07, -1.75462e-07, -1.75461e-07", \ + "-2.33236e-07, -2.33235e-07, -2.33238e-07, -2.33235e-07, -2.33236e-07, -2.33235e-07" \ + ); + } + } + internal_power () { + related_pin : "pad"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0103788, 0.00976643, 0.00997524, 0.00886332, 0.0085767, 0.00809822", \ + "0.0102518, 0.00940589, 0.010246, 0.0088097, 0.00868576, 0.00772647", \ + "0.0130891, 0.0113023, 0.00932679, 0.00836964, 0.00827541, 0.00813336", \ + "0.0143981, 0.0123289, 0.00959887, 0.00881102, 0.00785004, 0.0081756", \ + "0.0224718, 0.0184402, 0.0146598, 0.0127354, 0.0103269, 0.00912452", \ + "0.0415466, 0.032745, 0.025803, 0.0224494, 0.0201031, 0.0189569", \ + "0.115412, 0.104694, 0.0943411, 0.0902959, 0.0859539, 0.0842406" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.102141, 0.0977675, 0.0953841, 0.0947242, 0.0944339, 0.0942051", \ + "0.100999, 0.0965269, 0.0940085, 0.0932392, 0.0929348, 0.0927299", \ + "0.10082, 0.0962556, 0.0935485, 0.0926481, 0.0922075, 0.0920285", \ + "0.104066, 0.0993228, 0.0962382, 0.0949555, 0.0943512, 0.0939655", \ + "0.113025, 0.105976, 0.100616, 0.0982951, 0.0971489, 0.0967678", \ + "0.138346, 0.126485, 0.115134, 0.110402, 0.107572, 0.105596", \ + "0.158833, 0.144415, 0.128698, 0.121181, 0.116907, 0.114647" \ + ); + } + } + } + pin (pad) { + direction : "input"; + is_pad : true; + input_voltage : "pad"; + fanout_load : 1; + related_ground_pin : iovss; + related_power_pin : iovdd; + max_transition : 3.5; + capacitance : 0.220662; + rise_capacitance : 0.223725; + rise_capacitance_range (0.197141, 0.241203); + fall_capacitance : 0.217598; + fall_capacitance_range (0.198068, 0.230121); + } + } + cell (sg13g2_IOPadInOut16mA) { + pad_cell : true; + area : 14400; + cell_footprint : "inout"; + pad_drivers : 1; + bond_pads : 1; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 1244.94; + when : "!c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 15094.6; + when : "!c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 1244.94; + when : "!c2p_en&c2p&!pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 22149.8; + when : "!c2p_en&c2p&!pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 27.4413; + when : "!c2p_en&!c2p&pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 12823.9; + when : "!c2p_en&!c2p&pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 27.4413; + when : "!c2p_en&c2p&pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 19879.8; + when : "!c2p_en&c2p&pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 54.3465; + when : "c2p_en&c2p&pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 20819.6; + when : "c2p_en&c2p&pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 54.3465; + when : "c2p_en&c2p&pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 20819.5; + when : "c2p_en&c2p&pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 1220.31; + when : "c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 16760.6; + when : "c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 1220.31; + when : "c2p_en&!c2p&!pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 16760.6; + when : "c2p_en&!c2p&!pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 636.76; + related_pg_pin : iovdd; + } + leakage_power () { + value : 18138.5; + related_pg_pin : vdd; + } + pin (pad) { + direction : "inout"; + is_pad : true; + function : "c2p"; + three_state : "c2p_en'"; + drive_current : 16; + output_voltage : "pad"; + input_voltage : "pad"; + related_ground_pin : iovss; + related_power_pin : iovdd; + max_capacitance : 6.47213; + capacitance : 0.260317; + rise_capacitance : 0.261064; + rise_capacitance_range (0.232676, 0.279544); + fall_capacitance : 0.259569; + fall_capacitance_range (0.238412, 0.273083); + timing () { + related_pin : "c2p"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.03218, 1.14733, 1.24366, 1.33145, 1.57384, 1.80592", \ + "1.04054, 1.15548, 1.25179, 1.33948, 1.58198, 1.81391", \ + "1.04411, 1.159, 1.25528, 1.34301, 1.58553, 1.81731", \ + "1.05018, 1.16506, 1.26132, 1.34907, 1.5915, 1.82346", \ + "1.05486, 1.16979, 1.26619, 1.35398, 1.59654, 1.82845", \ + "1.05487, 1.1698, 1.2662, 1.35399, 1.59655, 1.82846", \ + "1.05488, 1.16981, 1.26621, 1.354, 1.59656, 1.82847" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.380404, 0.537177, 0.684937, 0.832041, 1.27827, 1.73558", \ + "0.380405, 0.537178, 0.684938, 0.832042, 1.27842, 1.73559", \ + "0.380406, 0.537179, 0.684939, 0.832043, 1.27843, 1.7356", \ + "0.380407, 0.53718, 0.68494, 0.832044, 1.27844, 1.73561", \ + "0.380408, 0.537181, 0.684943, 0.832045, 1.27844, 1.73562", \ + "0.38104, 0.537432, 0.684944, 0.832046, 1.27866, 1.73563", \ + "0.383015, 0.538545, 0.690525, 0.835424, 1.27867, 1.73564" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.704356, 0.793704, 0.874271, 0.950212, 1.1701, 1.38998", \ + "0.719104, 0.808823, 0.889166, 0.965355, 1.18441, 1.40394", \ + "0.731816, 0.821043, 0.901524, 0.977397, 1.19704, 1.41602", \ + "0.756343, 0.845685, 0.926093, 1.00215, 1.22126, 1.44073", \ + "0.795626, 0.884915, 0.965685, 1.04135, 1.26086, 1.48026", \ + "0.866162, 0.95657, 1.03784, 1.1141, 1.33294, 1.55205", \ + "0.985558, 1.07574, 1.15628, 1.2328, 1.45323, 1.67449" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.447284, 0.557942, 0.675056, 0.799709, 1.19797, 1.61398", \ + "0.450913, 0.560574, 0.678573, 0.801774, 1.20033, 1.61539", \ + "0.452882, 0.562834, 0.679275, 0.803371, 1.20113, 1.61568", \ + "0.452883, 0.562835, 0.679488, 0.803372, 1.20114, 1.6157", \ + "0.452884, 0.562836, 0.679489, 0.803373, 1.20115, 1.61571", \ + "0.452885, 0.562837, 0.67949, 0.803374, 1.20116, 1.61572", \ + "0.452886, 0.562838, 0.679491, 0.803375, 1.20117, 1.61573" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : negative_unate; + timing_type : three_state_disable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.747248, 0.747249, 0.74725, 0.747251, 0.747252, 0.747253", \ + "0.762003, 0.762004, 0.762005, 0.762006, 0.762007, 0.762008", \ + "0.770705, 0.770706, 0.770707, 0.770708, 0.770709, 0.77071", \ + "0.787143, 0.787144, 0.787147, 0.787148, 0.787149, 0.78715", \ + "0.81313, 0.813131, 0.813132, 0.813133, 0.813134, 0.813135", \ + "0.849551, 0.849552, 0.849553, 0.849554, 0.849555, 0.849556", \ + "0.925219, 0.92522, 0.925221, 0.925222, 0.925223, 0.925224" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.747248, 0.747249, 0.74725, 0.747251, 0.747252, 0.747253", \ + "0.762003, 0.762004, 0.762005, 0.762006, 0.762007, 0.762008", \ + "0.770705, 0.770706, 0.770707, 0.770708, 0.770709, 0.77071", \ + "0.787143, 0.787144, 0.787147, 0.787148, 0.787149, 0.78715", \ + "0.81313, 0.813131, 0.813132, 0.813133, 0.813134, 0.813135", \ + "0.849551, 0.849552, 0.849553, 0.849554, 0.849555, 0.849556", \ + "0.925219, 0.92522, 0.925221, 0.925222, 0.925223, 0.925224" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.714864, 0.714865, 0.714866, 0.714867, 0.714868, 0.714869", \ + "0.728762, 0.728763, 0.728764, 0.728765, 0.728766, 0.728767", \ + "0.744941, 0.744942, 0.744943, 0.744944, 0.744945, 0.744946", \ + "0.759228, 0.759235, 0.759238, 0.75924, 0.759242, 0.759243", \ + "0.794612, 0.794619, 0.79462, 0.794621, 0.794623, 0.794624", \ + "0.851261, 0.851262, 0.851263, 0.851264, 0.851265, 0.851266", \ + "0.942832, 0.94284, 0.942841, 0.942842, 0.942843, 0.942844" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.714864, 0.714865, 0.714866, 0.714867, 0.714868, 0.714869", \ + "0.728762, 0.728763, 0.728764, 0.728765, 0.728766, 0.728767", \ + "0.744941, 0.744942, 0.744943, 0.744944, 0.744945, 0.744946", \ + "0.759228, 0.759235, 0.759238, 0.75924, 0.759242, 0.759243", \ + "0.794612, 0.794619, 0.79462, 0.794621, 0.794623, 0.794624", \ + "0.851261, 0.851262, 0.851263, 0.851264, 0.851265, 0.851266", \ + "0.942832, 0.94284, 0.942841, 0.942842, 0.942843, 0.942844" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : positive_unate; + timing_type : three_state_enable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.02429, 1.14572, 1.24655, 1.33796, 1.59206, 1.83538", \ + "1.03497, 1.15643, 1.25708, 1.34928, 1.60271, 1.84731", \ + "1.04084, 1.16232, 1.26314, 1.35452, 1.60865, 1.85194", \ + "1.05063, 1.17222, 1.27274, 1.36442, 1.61888, 1.86203", \ + "1.06197, 1.18334, 1.28418, 1.37556, 1.62964, 1.87294", \ + "1.07211, 1.19325, 1.29413, 1.38565, 1.64094, 1.88427", \ + "1.07769, 1.19918, 1.29974, 1.39138, 1.6457, 1.88891" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.38392, 0.532216, 0.676371, 0.820975, 1.26632, 1.72257", \ + "0.383921, 0.532288, 0.676372, 0.821857, 1.26633, 1.7246", \ + "0.383922, 0.532289, 0.676374, 0.821858, 1.26635, 1.72461", \ + "0.38405, 0.53229, 0.676375, 0.821859, 1.26664, 1.72462", \ + "0.384051, 0.532291, 0.676376, 0.82186, 1.26665, 1.72463", \ + "0.384257, 0.532638, 0.676839, 0.821861, 1.26699, 1.72464", \ + "0.384258, 0.532639, 0.678837, 0.822447, 1.267, 1.72465" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.57203, 0.679347, 0.774545, 0.864913, 1.12348, 1.37797", \ + "0.582258, 0.688741, 0.783545, 0.874307, 1.13294, 1.38771", \ + "0.586683, 0.693441, 0.787963, 0.878758, 1.13743, 1.39218", \ + "0.591864, 0.699184, 0.793774, 0.884673, 1.14331, 1.39809", \ + "0.596331, 0.70281, 0.798489, 0.889387, 1.14701, 1.40204", \ + "0.596332, 0.702811, 0.79849, 0.889388, 1.14702, 1.40205", \ + "0.596333, 0.702812, 0.798491, 0.889389, 1.14703, 1.40206" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.280763, 0.420793, 0.560106, 0.698873, 1.128, 1.56139", \ + "0.280764, 0.420794, 0.560107, 0.698874, 1.12801, 1.5614", \ + "0.280889, 0.420827, 0.560108, 0.698875, 1.12802, 1.56334", \ + "0.28089, 0.420828, 0.560109, 0.698876, 1.12803, 1.56335", \ + "0.281294, 0.421325, 0.560317, 0.699496, 1.12804, 1.56336", \ + "0.281295, 0.421326, 0.560318, 0.699497, 1.12805, 1.56337", \ + "0.281296, 0.421327, 0.560319, 0.699498, 1.12877, 1.56338" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "7.96958, 7.86972, 7.80577, 7.77809, 7.60792, 7.4979", \ + "7.98747, 7.8802, 7.81232, 7.78428, 7.61951, 7.49466", \ + "7.99229, 7.88251, 7.8133, 7.77161, 7.61576, 7.49401", \ + "7.98877, 7.87763, 7.80872, 7.7638, 7.61576, 7.49369", \ + "7.96965, 7.86132, 7.79512, 7.75422, 7.61094, 7.46402", \ + "7.92186, 7.826, 7.77683, 7.72308, 7.61778, 7.42086", \ + "7.85946, 7.8824, 7.85365, 7.85578, 7.56068, 7.46111" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "18.4798, 16.3596, 14.9248, 13.862, 11.864, 10.6818", \ + "18.8361, 16.6597, 15.1958, 14.1006, 12.0556, 10.8369", \ + "18.9407, 16.7691, 15.2925, 14.1957, 12.1326, 10.8896", \ + "18.9208, 16.74, 15.2698, 14.1673, 12.1136, 10.8869", \ + "18.778, 16.6262, 15.1419, 14.0826, 12.0005, 10.8171", \ + "18.2881, 16.204, 14.8036, 13.7544, 11.7669, 10.598", \ + "17.2806, 15.2883, 13.9711, 12.9875, 11.1782, 10.1076" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.78764, 5.46434, 8.13957, 10.8188, 18.8612, 26.6596", \ + "2.79589, 5.47363, 8.14819, 10.8216, 18.8604, 26.65", \ + "2.81178, 5.48276, 8.16511, 10.851, 18.8796, 26.6551", \ + "2.86047, 5.54065, 8.21396, 10.8966, 18.9286, 26.6606", \ + "2.96803, 5.63664, 8.3213, 11.0057, 19.025, 26.6185", \ + "3.19299, 5.86079, 8.54809, 11.2325, 19.2352, 26.6964", \ + "3.63733, 6.32074, 8.9962, 11.6732, 19.6828, 26.7927" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.330267, 0.329529, 0.329207, 0.329134, 0.329371, 0.330188", \ + "0.339978, 0.339487, 0.33909, 0.338885, 0.339326, 0.340179", \ + "0.35911, 0.358352, 0.358008, 0.357855, 0.358264, 0.359076", \ + "0.409455, 0.408718, 0.408359, 0.408168, 0.408495, 0.409095", \ + "0.515037, 0.514183, 0.513846, 0.513519, 0.513743, 0.514473", \ + "0.734568, 0.733673, 0.73302, 0.732819, 0.73256, 0.73334", \ + "1.17599, 1.17552, 1.17422, 1.17404, 1.17334, 1.17397" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "7.47006, 7.75675, 8.05453, 8.34854, 9.23494, 10.1028", \ + "7.46392, 7.75159, 8.04578, 8.35304, 9.22824, 10.2077", \ + "7.46641, 7.75692, 8.0527, 8.35722, 9.23594, 10.1392", \ + "7.46398, 7.75935, 8.05748, 8.36003, 9.27295, 10.133", \ + "7.47086, 7.75932, 8.05712, 8.36456, 9.24509, 10.1311", \ + "7.44344, 7.70932, 8.00204, 8.31546, 9.21478, 10.159", \ + "7.48501, 7.85222, 8.13118, 8.43408, 9.23429, 10.0956" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.92914, 2.92858, 2.92364, 2.92348, 2.91696, 2.91691", \ + "2.92875, 2.92681, 2.92206, 2.92164, 2.91575, 2.91649", \ + "2.93014, 2.92837, 2.92471, 2.92322, 2.91748, 2.91869", \ + "2.9297, 2.92913, 2.92576, 2.92408, 2.91827, 2.91945", \ + "2.92798, 2.92745, 2.9246, 2.92389, 2.92017, 2.91739", \ + "2.93186, 2.92992, 2.92458, 2.92671, 2.9244, 2.91947", \ + "2.92979, 2.93099, 2.92537, 2.92363, 2.91693, 2.91766" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.73279, 5.4125, 8.09774, 10.7663, 18.8107, 26.5378", \ + "2.74824, 5.42729, 8.10668, 10.7829, 18.8208, 26.6107", \ + "2.76804, 5.44723, 8.13187, 10.8021, 18.8407, 26.6169", \ + "2.82125, 5.49201, 8.1774, 10.8576, 18.9084, 26.566", \ + "2.93085, 5.60163, 8.28634, 10.9673, 19.0058, 26.637", \ + "3.16093, 5.84138, 8.51727, 11.1946, 19.2316, 26.6919", \ + "3.61191, 6.28783, 8.96282, 11.6496, 19.6793, 26.7913" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.166061, 0.165636, 0.165404, 0.16564, 0.16596, 0.167017", \ + "0.174366, 0.173548, 0.173187, 0.173362, 0.173804, 0.174775", \ + "0.18503, 0.184215, 0.183918, 0.184212, 0.184493, 0.185554", \ + "0.213366, 0.212903, 0.21257, 0.212754, 0.213134, 0.21415", \ + "0.271992, 0.271068, 0.270941, 0.271105, 0.271394, 0.272364", \ + "0.393923, 0.393486, 0.393272, 0.39312, 0.393276, 0.394443", \ + "0.639916, 0.639198, 0.638688, 0.639072, 0.638908, 0.639056" \ + ); + } + } + } + pin (p2c) { + direction : "output"; + output_voltage : "core"; + function : "pad"; + related_ground_pin : vss; + related_power_pin : vdd; + max_capacitance : 1.70416; + timing () { + related_pin : "pad"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0494336, 0.0587738, 0.0756572, 0.0920902, 0.107961, 0.123735", \ + "0.0494346, 0.0587748, 0.0756582, 0.0920912, 0.107962, 0.123736", \ + "0.0494356, 0.0587758, 0.0756592, 0.0920922, 0.107963, 0.123737", \ + "0.0494366, 0.0587768, 0.0756602, 0.0920932, 0.107964, 0.123738", \ + "0.0494376, 0.0587778, 0.0756612, 0.0920942, 0.107965, 0.123739", \ + "0.0494386, 0.0587788, 0.0756622, 0.0920952, 0.107966, 0.12374", \ + "0.0494396, 0.0587798, 0.0756632, 0.0920962, 0.107967, 0.123741" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0351286, 0.0520144, 0.0857716, 0.120002, 0.154452, 0.189169", \ + "0.0387735, 0.0548375, 0.0880618, 0.12215, 0.156959, 0.191489", \ + "0.0455394, 0.0608352, 0.0924502, 0.125313, 0.159081, 0.193353", \ + "0.0487158, 0.0640857, 0.0948149, 0.127271, 0.160623, 0.194682", \ + "0.0613766, 0.0764041, 0.105499, 0.136704, 0.168452, 0.201196", \ + "0.0819738, 0.0970146, 0.125648, 0.154214, 0.184014, 0.215315", \ + "0.097241, 0.112355, 0.141356, 0.169462, 0.197748, 0.226861" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.203053, 0.214897, 0.234467, 0.25143, 0.266752, 0.28214", \ + "0.257049, 0.268882, 0.288423, 0.30533, 0.321089, 0.335633", \ + "0.37295, 0.384686, 0.404231, 0.421173, 0.436478, 0.45142", \ + "0.434404, 0.446078, 0.465354, 0.482195, 0.498007, 0.51295", \ + "0.724417, 0.736684, 0.756727, 0.773657, 0.789433, 0.803942", \ + "1.25556, 1.26931, 1.29165, 1.31052, 1.32735, 1.34329", \ + "1.72385, 1.73859, 1.76252, 1.78267, 1.80051, 1.81708" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0571429, 0.0706507, 0.0968625, 0.12262, 0.148258, 0.174872", \ + "0.0571439, 0.0706517, 0.0968635, 0.122621, 0.148468, 0.174873", \ + "0.0571889, 0.0706666, 0.0969204, 0.122622, 0.148469, 0.174874", \ + "0.0575879, 0.0711012, 0.0971785, 0.122752, 0.148865, 0.175037", \ + "0.071605, 0.083954, 0.108435, 0.132232, 0.157109, 0.182392", \ + "0.09945, 0.111563, 0.135462, 0.158611, 0.181981, 0.205874", \ + "0.118099, 0.130004, 0.153231, 0.176227, 0.198439, 0.221605" \ + ); + } + } + internal_power () { + related_pin : "pad"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "-0.692731, -0.693869, -0.693427, -0.697262, -0.697369, -0.69734", \ + "-0.69715, -0.697143, -0.695431, -0.693677, -0.69619, -0.695288", \ + "-0.697323, -0.697771, -0.697779, -0.697789, -0.69782, -0.696045", \ + "-0.695584, -0.695561, -0.695493, -0.69545, -0.69548, -0.695421", \ + "-0.693627, -0.693352, -0.69318, -0.695057, -0.693977, -0.69519", \ + "-0.695765, -0.695959, -0.694176, -0.696069, -0.695478, -0.694651", \ + "0.147274, 0.149066, 0.147181, 0.143011, 0.149961, 0.148776" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.697214, 0.697223, 0.697238, 0.697262, 0.697369, 0.69734", \ + "0.69715, 0.697143, 0.69714, 0.697154, 0.69719, 0.697229", \ + "0.697377, 0.697786, 0.697779, 0.697789, 0.69782, 0.697898", \ + "0.695584, 0.695561, 0.695493, 0.69545, 0.69548, 0.695421", \ + "0.693627, 0.693352, 0.69318, 0.695057, 0.693977, 0.69519", \ + "0.695765, 0.695959, 0.694176, 0.696069, 0.695478, 0.694651", \ + "0.694256, 0.694482, 0.693749, 0.694317, 0.694969, 0.694019" \ + ); + } + } + internal_power () { + related_pin : "pad"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0109412, 0.0106223, 0.00965299, 0.00923078, 0.00878955, 0.00862325", \ + "0.0109339, 0.0104509, 0.0109052, 0.0097101, 0.009157, 0.00872456", \ + "0.0132747, 0.011242, 0.00933999, 0.00856022, 0.00895587, 0.00888824", \ + "0.0150043, 0.0129404, 0.0100693, 0.00873297, 0.00805101, 0.00777597", \ + "0.0238607, 0.0195938, 0.0148792, 0.0135741, 0.0108344, 0.00929744", \ + "0.0418073, 0.033744, 0.0272064, 0.0229865, 0.0204072, 0.0190156", \ + "0.116304, 0.105638, 0.095978, 0.0920266, 0.0870847, 0.0827137" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.102272, 0.0979028, 0.0954645, 0.0947521, 0.0944525, 0.0942106", \ + "0.101096, 0.0966182, 0.0940654, 0.093312, 0.0929736, 0.0928142", \ + "0.101444, 0.0968802, 0.0940626, 0.0931127, 0.0926793, 0.0924284", \ + "0.102816, 0.0980171, 0.0947952, 0.0936453, 0.0929948, 0.0925781", \ + "0.113204, 0.106117, 0.100703, 0.0983726, 0.0972151, 0.0968287", \ + "0.140038, 0.128658, 0.11857, 0.114016, 0.110649, 0.108258", \ + "0.166962, 0.152889, 0.137317, 0.130174, 0.126194, 0.123494" \ + ); + } + } + } + pin (c2p) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.016; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0314981; + rise_capacitance : 0.0317462; + rise_capacitance_range (0.0245489, 0.0372822); + fall_capacitance : 0.0312499; + fall_capacitance_range (0.0252988, 0.0337121); + internal_power () { + when : "(!c2p_en * pad * p2c)"; + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-1.33856e-05, -1.24899e-05, -6.25697e-06, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "1.33856e-05, 1.24899e-05, 6.25697e-06, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + when : "(!c2p_en * pad * p2c)"; + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0345903, -0.0357941, -0.0361564, -0.0365757, -0.0367368, -0.0369406, -0.0368259" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0450126, 0.0443943, 0.0441665, 0.0441, 0.0441325, 0.0442615, 0.0440573" \ + ); + } + } + internal_power () { + when : "(!c2p_en * !pad * !p2c)"; + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-1.32669e-05, -1.24849e-05, -6.27457e-06, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "1.32669e-05, 1.24849e-05, 6.27457e-06, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + when : "(!c2p_en * !pad * !p2c)"; + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0345873, -0.035792, -0.0361543, -0.0365748, -0.0367364, -0.0369406, -0.0368261" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0450094, 0.0443927, 0.0441658, 0.0440994, 0.044132, 0.0442614, 0.0440572" \ + ); + } + } + internal_power () { + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-1.32669e-05, -1.24849e-05, -6.27457e-06, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "1.32669e-05, 1.24849e-05, 6.27457e-06, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0345873, -0.035792, -0.0361543, -0.0365748, -0.0367364, -0.0369406, -0.0368261" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0450094, 0.0443927, 0.0441658, 0.0440994, 0.044132, 0.0442614, 0.0440572" \ + ); + } + } + } + pin (c2p_en) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.011; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0280703; + rise_capacitance : 0.0293254; + rise_capacitance_range (0.0234223, 0.0373491); + fall_capacitance : 0.0268152; + fall_capacitance_range (0.0227688, 0.0321876); + internal_power () { + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "2.01075, 2.01101, 2.01081, 2.01329, 2.0118, 2.02263, 2.01015" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.348109, 0.345127, 0.345633, 0.343656, 0.344536, 0.34241, 0.340173" \ + ); + } + } + internal_power () { + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.065218, 0.0727405, 0.0837335, 0.111103, 0.170391, 0.293159, 0.55277" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.16025, 0.17146, 0.183068, 0.212803, 0.272343, 0.396486, 0.651602" \ + ); + } + } + } + } + cell (sg13g2_IOPadInOut30mA) { + pad_cell : true; + area : 14400; + cell_footprint : "inout"; + pad_drivers : 1; + bond_pads : 1; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 2119.76; + when : "!c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 15093.9; + when : "!c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 2119.76; + when : "!c2p_en&c2p&!pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 22149; + when : "!c2p_en&c2p&!pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 0; + when : "!c2p_en&!c2p&pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 12823.3; + when : "!c2p_en&!c2p&pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 0; + when : "!c2p_en&c2p&pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 19879.3; + when : "!c2p_en&c2p&pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 0; + when : "c2p_en&c2p&pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 20818.9; + when : "c2p_en&c2p&pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 0; + when : "c2p_en&c2p&pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 20818.9; + when : "c2p_en&c2p&pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 2095.16; + when : "c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 16759.9; + when : "c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 2095.16; + when : "c2p_en&!c2p&!pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 16759.8; + when : "c2p_en&!c2p&!pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 1053.73; + related_pg_pin : iovdd; + } + leakage_power () { + value : 18137.9; + related_pg_pin : vdd; + } + pin (pad) { + direction : "inout"; + is_pad : true; + function : "c2p"; + three_state : "c2p_en'"; + drive_current : 30; + output_voltage : "pad"; + input_voltage : "pad"; + related_ground_pin : iovss; + related_power_pin : iovdd; + max_capacitance : 10.0022; + capacitance : 0.344961; + rise_capacitance : 0.343521; + rise_capacitance_range (0.31299, 0.363677); + fall_capacitance : 0.346401; + fall_capacitance_range (0.323393, 0.361524); + timing () { + related_pin : "c2p"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.20298, 1.30459, 1.38869, 1.46222, 1.64676, 1.80332", \ + "1.21099, 1.31307, 1.39694, 1.4703, 1.65468, 1.81123", \ + "1.21551, 1.31673, 1.40064, 1.47396, 1.6583, 1.81495", \ + "1.22118, 1.32255, 1.4062, 1.47953, 1.66392, 1.82048", \ + "1.22375, 1.32561, 1.40955, 1.48288, 1.66742, 1.82403", \ + "1.22439, 1.32668, 1.41086, 1.48354, 1.66839, 1.82522", \ + "1.2244, 1.32669, 1.41087, 1.48355, 1.6684, 1.82523" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.364042, 0.491164, 0.596119, 0.689747, 0.942931, 1.18166", \ + "0.364702, 0.491165, 0.59612, 0.689748, 0.942932, 1.18179", \ + "0.364703, 0.491166, 0.596121, 0.689862, 0.942933, 1.18186", \ + "0.364704, 0.491167, 0.596122, 0.689916, 0.942934, 1.18187", \ + "0.364705, 0.491168, 0.596123, 0.689958, 0.942935, 1.18188", \ + "0.364906, 0.492423, 0.597273, 0.691693, 0.943876, 1.18273", \ + "0.369398, 0.49493, 0.599299, 0.694755, 0.944469, 1.18335" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.908881, 0.970137, 1.02601, 1.07837, 1.22011, 1.35083", \ + "0.924724, 0.986034, 1.0408, 1.09322, 1.23648, 1.36587", \ + "0.93692, 0.998127, 1.05394, 1.10628, 1.24825, 1.37912", \ + "0.961379, 1.02266, 1.07695, 1.12984, 1.27312, 1.40246", \ + "1.00027, 1.06187, 1.1177, 1.17004, 1.31204, 1.44289", \ + "1.07212, 1.1337, 1.18846, 1.23987, 1.38163, 1.51174", \ + "1.18947, 1.25072, 1.30606, 1.35839, 1.50197, 1.6308" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.701244, 0.73841, 0.790631, 0.847803, 1.01601, 1.19598", \ + "0.707495, 0.743781, 0.795213, 0.850885, 1.02411, 1.2032", \ + "0.709252, 0.745326, 0.797005, 0.853823, 1.02512, 1.20535", \ + "0.709253, 0.745327, 0.797006, 0.853824, 1.02513, 1.20536", \ + "0.709254, 0.745328, 0.797007, 0.853825, 1.02514, 1.20537", \ + "0.709255, 0.745329, 0.797008, 0.853826, 1.02515, 1.20538", \ + "0.709256, 0.74533, 0.797009, 0.853827, 1.02516, 1.20539" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : negative_unate; + timing_type : three_state_disable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.908276, 0.908277, 0.908278, 0.908279, 0.90828, 0.908281", \ + "0.923912, 0.923913, 0.923914, 0.923915, 0.923916, 0.923917", \ + "0.933115, 0.933118, 0.933119, 0.93312, 0.933121, 0.933122", \ + "0.947032, 0.947039, 0.94704, 0.947041, 0.947042, 0.947045", \ + "0.973852, 0.973856, 0.973857, 0.973858, 0.973859, 0.97386", \ + "1.01357, 1.01358, 1.01359, 1.0136, 1.01361, 1.01362", \ + "1.08849, 1.0885, 1.08851, 1.08852, 1.08853, 1.08854" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.908276, 0.908277, 0.908278, 0.908279, 0.90828, 0.908281", \ + "0.923912, 0.923913, 0.923914, 0.923915, 0.923916, 0.923917", \ + "0.933115, 0.933118, 0.933119, 0.93312, 0.933121, 0.933122", \ + "0.947032, 0.947039, 0.94704, 0.947041, 0.947042, 0.947045", \ + "0.973852, 0.973856, 0.973857, 0.973858, 0.973859, 0.97386", \ + "1.01357, 1.01358, 1.01359, 1.0136, 1.01361, 1.01362", \ + "1.08849, 1.0885, 1.08851, 1.08852, 1.08853, 1.08854" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.1476, 1.14761, 1.14762, 1.14763, 1.14764, 1.14765", \ + "1.16964, 1.16965, 1.16966, 1.16967, 1.16968, 1.16969", \ + "1.17535, 1.17536, 1.17537, 1.17538, 1.17539, 1.1754", \ + "1.20392, 1.20393, 1.20394, 1.20395, 1.20396, 1.20397", \ + "1.23778, 1.23779, 1.2378, 1.23781, 1.23782, 1.23783", \ + "1.28878, 1.28879, 1.2888, 1.28881, 1.28882, 1.28883", \ + "1.38031, 1.38032, 1.38033, 1.38034, 1.38035, 1.38036" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.1476, 1.14761, 1.14762, 1.14763, 1.14764, 1.14765", \ + "1.16964, 1.16965, 1.16966, 1.16967, 1.16968, 1.16969", \ + "1.17535, 1.17536, 1.17537, 1.17538, 1.17539, 1.1754", \ + "1.20392, 1.20393, 1.20394, 1.20395, 1.20396, 1.20397", \ + "1.23778, 1.23779, 1.2378, 1.23781, 1.23782, 1.23783", \ + "1.28878, 1.28879, 1.2888, 1.28881, 1.28882, 1.28883", \ + "1.38031, 1.38032, 1.38033, 1.38034, 1.38035, 1.38036" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : positive_unate; + timing_type : three_state_enable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.1689, 1.28731, 1.37937, 1.45777, 1.6515, 1.81475", \ + "1.17963, 1.29804, 1.39008, 1.46851, 1.66213, 1.82545", \ + "1.1855, 1.30394, 1.39611, 1.47442, 1.66811, 1.83134", \ + "1.19607, 1.31448, 1.40654, 1.48497, 1.67854, 1.84179", \ + "1.20546, 1.32385, 1.4159, 1.49432, 1.68788, 1.85112", \ + "1.21646, 1.33468, 1.42681, 1.50509, 1.69874, 1.86197", \ + "1.22278, 1.34121, 1.43327, 1.51168, 1.70538, 1.86835" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.397285, 0.507227, 0.601163, 0.687995, 0.928999, 1.16313", \ + "0.397286, 0.507228, 0.601164, 0.687996, 0.929, 1.16371", \ + "0.397402, 0.507384, 0.601231, 0.688276, 0.929288, 1.16372", \ + "0.397403, 0.507385, 0.601232, 0.688277, 0.929289, 1.16373", \ + "0.397404, 0.507386, 0.601233, 0.688278, 0.92929, 1.16374", \ + "0.397405, 0.507387, 0.601234, 0.688279, 0.929291, 1.16375", \ + "0.397406, 0.507608, 0.601739, 0.68828, 0.929407, 1.16376" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.604184, 0.689075, 0.759391, 0.821722, 0.986868, 1.13438", \ + "0.61404, 0.698922, 0.769266, 0.831616, 0.996713, 1.14423", \ + "0.618289, 0.703225, 0.773131, 0.836773, 1.00092, 1.15063", \ + "0.624285, 0.70914, 0.779998, 0.841957, 1.00708, 1.15464", \ + "0.628837, 0.713961, 0.784075, 0.84637, 1.01049, 1.16011", \ + "0.628838, 0.713962, 0.784076, 0.846371, 1.0105, 1.16012", \ + "0.628839, 0.713963, 0.784077, 0.846372, 1.01051, 1.16013" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.261557, 0.350422, 0.429068, 0.503895, 0.729919, 0.95149", \ + "0.261558, 0.350423, 0.429072, 0.505183, 0.72992, 0.951491", \ + "0.261559, 0.350424, 0.430089, 0.505184, 0.729943, 0.953071", \ + "0.26156, 0.350425, 0.43009, 0.505185, 0.729944, 0.953072", \ + "0.261561, 0.350426, 0.430091, 0.506345, 0.729945, 0.953073", \ + "0.261687, 0.350427, 0.430092, 0.506346, 0.729946, 0.953074", \ + "0.261688, 0.350428, 0.431518, 0.506347, 0.729947, 0.953075" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "13.3644, 12.9252, 12.7104, 12.5699, 12.3015, 12.0606", \ + "13.3744, 12.9827, 12.7326, 12.6173, 12.2705, 12.0646", \ + "13.4295, 12.9885, 12.7513, 12.6343, 12.3198, 12.0743", \ + "13.4246, 12.9996, 12.7333, 12.6273, 12.3184, 12.0523", \ + "13.3556, 12.9486, 12.6991, 12.5679, 12.2573, 12.0096", \ + "13.2623, 12.8562, 12.6101, 12.4652, 12.1913, 11.9765", \ + "13.0407, 12.7148, 12.5177, 12.606, 12.1427, 12.0028" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "72.863, 68.6552, 65.0485, 61.9234, 54.6632, 49.418", \ + "73.7048, 69.4363, 65.8175, 62.678, 55.31, 50.0908", \ + "73.9319, 69.6599, 66.0002, 62.8308, 55.5115, 50.1855", \ + "73.8759, 69.6016, 65.9391, 62.8318, 55.446, 50.227", \ + "73.5758, 69.3087, 65.6632, 62.5075, 55.2184, 49.9184", \ + "72.448, 68.2067, 64.6461, 61.5415, 54.3259, 49.217", \ + "70.1722, 65.9657, 62.4761, 59.4826, 52.3929, 47.3864" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.7845, 5.45848, 8.15834, 10.8568, 18.7638, 24.804", \ + "2.79407, 5.46659, 8.16803, 10.8661, 18.7647, 24.8302", \ + "2.80968, 5.48286, 8.18481, 10.883, 18.7756, 24.6923", \ + "2.85862, 5.53313, 8.23653, 10.923, 18.8119, 24.5907", \ + "2.96635, 5.63996, 8.3443, 11.0343, 18.9997, 24.3934", \ + "3.19049, 5.86395, 8.5692, 11.2635, 19.1217, 23.9628", \ + "3.63967, 6.30965, 9.01623, 11.7079, 19.4952, 22.9407" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.331217, 0.329697, 0.329425, 0.329254, 0.32888, 0.328772", \ + "0.340976, 0.339585, 0.339188, 0.339036, 0.338794, 0.338389", \ + "0.36002, 0.358588, 0.358252, 0.358102, 0.357728, 0.357438", \ + "0.410284, 0.408934, 0.408546, 0.408262, 0.408009, 0.407445", \ + "0.515693, 0.514428, 0.514024, 0.513784, 0.513273, 0.51263", \ + "0.735445, 0.734236, 0.733393, 0.732676, 0.732269, 0.731474", \ + "1.17742, 1.1756, 1.17463, 1.17399, 1.17338, 1.17055" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "11.3787, 11.676, 11.9639, 12.2912, 13.1303, 14.0252", \ + "11.3724, 11.6692, 11.9548, 12.2957, 13.1448, 14.0631", \ + "11.3713, 11.6673, 11.9621, 12.294, 13.162, 13.9401", \ + "11.3763, 11.6708, 11.961, 12.2909, 13.1207, 14.0188", \ + "11.3753, 11.6608, 11.9614, 12.2904, 13.1233, 14.02", \ + "11.374, 11.6551, 11.961, 12.2999, 13.1558, 13.9388", \ + "11.4091, 11.6798, 12.0365, 12.2815, 13.1548, 13.9955" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "4.92533, 4.92746, 4.92635, 4.9252, 4.92663, 4.91979", \ + "4.92493, 4.92702, 4.9262, 4.92622, 4.92662, 4.91981", \ + "4.92489, 4.92198, 4.92731, 4.92798, 4.92627, 4.92304", \ + "4.92533, 4.9276, 4.92709, 4.92695, 4.92919, 4.92211", \ + "4.92529, 4.92332, 4.92383, 4.92904, 4.92574, 4.92389", \ + "4.93064, 4.93021, 4.92418, 4.92922, 4.93028, 4.93062", \ + "4.92854, 4.93384, 4.93878, 4.93192, 4.92946, 4.92148" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.73295, 5.4085, 8.11224, 10.8022, 18.7371, 24.7759", \ + "2.74727, 5.4237, 8.12562, 10.8132, 18.7342, 24.7996", \ + "2.76747, 5.44392, 8.14641, 10.8417, 18.7408, 24.6496", \ + "2.82133, 5.49551, 8.20012, 10.8988, 18.8787, 24.5756", \ + "2.92966, 5.60578, 8.30912, 10.9975, 18.8645, 24.3801", \ + "3.15875, 5.832, 8.5402, 11.2214, 19.1343, 23.912", \ + "3.60796, 6.2805, 8.98325, 11.676, 19.3379, 22.8325" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.16548, 0.164862, 0.164744, 0.164537, 0.164627, 0.16257", \ + "0.173379, 0.17275, 0.172633, 0.172375, 0.172492, 0.170342", \ + "0.184071, 0.183542, 0.183124, 0.183339, 0.183153, 0.181138", \ + "0.212817, 0.212136, 0.212135, 0.211791, 0.211793, 0.209367", \ + "0.271378, 0.270951, 0.270444, 0.270141, 0.270101, 0.267488", \ + "0.392908, 0.392044, 0.391754, 0.391365, 0.390785, 0.38734", \ + "0.638373, 0.637201, 0.636778, 0.63635, 0.636397, 0.630161" \ + ); + } + } + } + pin (p2c) { + direction : "output"; + output_voltage : "core"; + function : "pad"; + related_ground_pin : vss; + related_power_pin : vdd; + max_capacitance : 1.70082; + timing () { + related_pin : "pad"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0494793, 0.0587558, 0.0757058, 0.0921054, 0.108018, 0.123811", \ + "0.0494803, 0.0587568, 0.0757068, 0.0921064, 0.108019, 0.123812", \ + "0.0494813, 0.0587578, 0.0757078, 0.0921074, 0.10802, 0.123813", \ + "0.0494823, 0.0587588, 0.0757088, 0.0921084, 0.108021, 0.123814", \ + "0.0494833, 0.0587598, 0.0757098, 0.0921094, 0.108022, 0.123815", \ + "0.0494843, 0.0587608, 0.0757108, 0.0921104, 0.108023, 0.123816", \ + "0.0494853, 0.0587618, 0.0757118, 0.0921114, 0.108024, 0.123817" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0351445, 0.0520259, 0.0858011, 0.120007, 0.154498, 0.189233", \ + "0.0387865, 0.0548609, 0.0879408, 0.122134, 0.157032, 0.191546", \ + "0.0455513, 0.0609921, 0.0924827, 0.125346, 0.159073, 0.193383", \ + "0.0487316, 0.0638548, 0.0948292, 0.12734, 0.160651, 0.194652", \ + "0.0613836, 0.0764122, 0.105805, 0.136703, 0.168441, 0.201258", \ + "0.0818836, 0.0969576, 0.12569, 0.154218, 0.18402, 0.215322", \ + "0.09716, 0.112366, 0.141367, 0.16947, 0.197477, 0.227738" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.203687, 0.215468, 0.235108, 0.251771, 0.267783, 0.282765", \ + "0.257172, 0.269002, 0.288571, 0.305212, 0.321213, 0.336184", \ + "0.372347, 0.38407, 0.403475, 0.420561, 0.436313, 0.451288", \ + "0.434582, 0.44633, 0.465546, 0.482153, 0.497811, 0.512881", \ + "0.724414, 0.736694, 0.75684, 0.773659, 0.789435, 0.803945", \ + "1.25754, 1.27126, 1.29363, 1.31266, 1.32964, 1.34576", \ + "1.72395, 1.73867, 1.76259, 1.78273, 1.80072, 1.81716" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0571449, 0.0705701, 0.0968367, 0.122248, 0.148564, 0.174881", \ + "0.0571459, 0.0705711, 0.0968377, 0.122249, 0.148565, 0.174882", \ + "0.0571469, 0.0705721, 0.0968387, 0.122518, 0.148619, 0.174883", \ + "0.0575923, 0.0712176, 0.0976167, 0.12332, 0.149184, 0.175578", \ + "0.071615, 0.083951, 0.108505, 0.132213, 0.157107, 0.182394", \ + "0.098908, 0.110952, 0.134714, 0.157783, 0.181418, 0.205944", \ + "0.117993, 0.130011, 0.153249, 0.17625, 0.19863, 0.221578" \ + ); + } + } + internal_power () { + related_pin : "pad"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "-1.31839, -1.3238, -1.31869, -1.32603, -1.32587, -1.32615", \ + "-1.32547, -1.32539, -1.32173, -1.32033, -1.32542, -1.32094", \ + "-1.32479, -1.32542, -1.32556, -1.32552, -1.32558, -1.32324", \ + "-1.32179, -1.32306, -1.32466, -1.32545, -1.32596, -1.32641", \ + "-1.3187, -1.31818, -1.31783, -1.3214, -1.31931, -1.3216", \ + "-1.32313, -1.32315, -1.32029, -1.32294, -1.3233, -1.32042", \ + "0.283339, 0.278639, 0.283524, 0.275418, 0.291407, 0.290467" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "1.32603, 1.32601, 1.32604, 1.32603, 1.3261, 1.32615", \ + "1.32547, 1.32539, 1.32536, 1.32538, 1.32542, 1.32547", \ + "1.32479, 1.32542, 1.32556, 1.32552, 1.32558, 1.32563", \ + "1.32179, 1.32306, 1.32466, 1.32545, 1.32596, 1.32641", \ + "1.3187, 1.31818, 1.31783, 1.3214, 1.31931, 1.3216", \ + "1.32313, 1.32315, 1.32029, 1.32294, 1.3233, 1.32042", \ + "1.32088, 1.32042, 1.32027, 1.32207, 1.3201, 1.32205" \ + ); + } + } + internal_power () { + related_pin : "pad"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0109237, 0.0104399, 0.00961603, 0.00912815, 0.00858775, 0.00851336", \ + "0.0110123, 0.0104244, 0.0102698, 0.00952448, 0.00905272, 0.00880458", \ + "0.0132385, 0.0113628, 0.00919198, 0.00854537, 0.00896214, 0.00883016", \ + "0.0150001, 0.0125179, 0.0100058, 0.00878561, 0.00809539, 0.00782976", \ + "0.0238619, 0.0196268, 0.0160613, 0.0135662, 0.0106357, 0.00893246", \ + "0.0418093, 0.0339249, 0.0269387, 0.0229682, 0.0203785, 0.0190054", \ + "0.11629, 0.105982, 0.0959949, 0.0920402, 0.0863046, 0.0846891" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.102547, 0.0980788, 0.0957284, 0.0949871, 0.0947111, 0.0944945", \ + "0.101142, 0.0966368, 0.0940733, 0.0932936, 0.0929891, 0.0927746", \ + "0.101341, 0.0967485, 0.0938927, 0.0929897, 0.0925489, 0.0922557", \ + "0.103272, 0.0985916, 0.0954313, 0.0942302, 0.09365, 0.0932078", \ + "0.113197, 0.106118, 0.100762, 0.0983863, 0.0972334, 0.0968522", \ + "0.140179, 0.12847, 0.116829, 0.111795, 0.108754, 0.106722", \ + "0.16684, 0.15255, 0.137067, 0.129981, 0.125847, 0.123379" \ + ); + } + } + } + pin (c2p) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.016; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.031498; + rise_capacitance : 0.0317461; + rise_capacitance_range (0.024549, 0.0372825); + fall_capacitance : 0.0312499; + fall_capacitance_range (0.025299, 0.0337121); + internal_power () { + when : "(!c2p_en * pad * p2c)"; + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-1.22207e-05, -1.18018e-05, -6.05288e-06, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "1.22207e-05, 1.18018e-05, 6.05288e-06, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + when : "(!c2p_en * pad * p2c)"; + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0345905, -0.0357941, -0.0361564, -0.0365756, -0.0367366, -0.0369406, -0.0368259" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0450125, 0.0443943, 0.0441664, 0.0441001, 0.0441325, 0.0442615, 0.0440573" \ + ); + } + } + internal_power () { + when : "(!c2p_en * !pad * !p2c)"; + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-1.21112e-05, -1.17525e-05, -6.05397e-06, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "1.21112e-05, 1.17525e-05, 6.05397e-06, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + when : "(!c2p_en * !pad * !p2c)"; + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0345874, -0.035792, -0.0361543, -0.0365747, -0.0367362, -0.0369406, -0.0368261" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0450094, 0.0443927, 0.0441658, 0.0440996, 0.044132, 0.0442614, 0.0440572" \ + ); + } + } + internal_power () { + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-1.21112e-05, -1.17525e-05, -6.05397e-06, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "1.21112e-05, 1.17525e-05, 6.05397e-06, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0345874, -0.035792, -0.0361543, -0.0365747, -0.0367362, -0.0369406, -0.0368261" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0450094, 0.0443927, 0.0441658, 0.0440996, 0.044132, 0.0442614, 0.0440572" \ + ); + } + } + } + pin (c2p_en) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.011; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0280746; + rise_capacitance : 0.029334; + rise_capacitance_range (0.0234223, 0.0374029); + fall_capacitance : 0.0268151; + fall_capacitance_range (0.0227688, 0.0321782); + internal_power () { + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "3.22292, 3.21837, 3.2187, 3.21956, 3.21813, 3.22666, 3.22677" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.330827, 0.331694, 0.328272, 0.325957, 0.328742, 0.32518, 0.324286" \ + ); + } + } + internal_power () { + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0652165, 0.0727334, 0.0837314, 0.111088, 0.170349, 0.293192, 0.553406" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.160256, 0.171467, 0.183062, 0.212809, 0.272296, 0.396483, 0.651934" \ + ); + } + } + } + } + cell (sg13g2_IOPadInOut4mA) { + pad_cell : true; + area : 14400; + cell_footprint : "inout"; + pad_drivers : 1; + bond_pads : 1; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 396.411; + when : "!c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 15095.4; + when : "!c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 396.113; + when : "!c2p_en&c2p&!pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 22150.5; + when : "!c2p_en&c2p&!pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 7.07672; + when : "!c2p_en&!c2p&pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 12825.4; + when : "!c2p_en&!c2p&pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 7.1288; + when : "!c2p_en&c2p&pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 19881.4; + when : "!c2p_en&c2p&pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 32.7753; + when : "c2p_en&c2p&pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 20821; + when : "c2p_en&c2p&pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 32.624; + when : "c2p_en&c2p&pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 20821; + when : "c2p_en&c2p&pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 371.516; + when : "c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 16761.3; + when : "c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 371.5; + when : "c2p_en&!c2p&!pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 16761.3; + when : "c2p_en&!c2p&!pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 201.893; + related_pg_pin : iovdd; + } + leakage_power () { + value : 18139.7; + related_pg_pin : vdd; + } + pin (pad) { + direction : "inout"; + is_pad : true; + function : "c2p"; + three_state : "c2p_en'"; + drive_current : 4; + output_voltage : "pad"; + input_voltage : "pad"; + related_ground_pin : iovss; + related_power_pin : iovdd; + max_capacitance : 1.65137; + capacitance : 0.18739; + rise_capacitance : 0.189886; + rise_capacitance_range (0.163006, 0.207436); + fall_capacitance : 0.184894; + fall_capacitance_range (0.165144, 0.197488); + timing () { + related_pin : "c2p"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.01629, 1.3204, 1.62261, 1.92417, 2.82789, 3.73101", \ + "1.02388, 1.32801, 1.6302, 1.93177, 2.8353, 3.73862", \ + "1.02776, 1.33188, 1.63407, 1.93564, 2.83917, 3.74249", \ + "1.03352, 1.33777, 1.63999, 1.94151, 2.84502, 3.74818", \ + "1.03883, 1.34305, 1.64529, 1.94688, 2.85041, 3.75391", \ + "1.03884, 1.34306, 1.6453, 1.94689, 2.85042, 3.75392", \ + "1.03885, 1.34307, 1.64531, 1.9469, 2.85043, 3.75393" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.794795, 1.41692, 2.04753, 2.67867, 4.56673, 6.46705", \ + "0.794796, 1.41729, 2.04756, 2.67868, 4.57125, 6.46706", \ + "0.794797, 1.4173, 2.04757, 2.67869, 4.57178, 6.46707", \ + "0.794798, 1.41731, 2.04758, 2.6787, 4.57179, 6.46708", \ + "0.794799, 1.41732, 2.04759, 2.67871, 4.5743, 6.46709", \ + "0.7948, 1.41733, 2.04784, 2.67879, 4.57431, 6.46723", \ + "0.794801, 1.41734, 2.04785, 2.6788, 4.57432, 6.46724" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.735329, 1.04286, 1.3503, 1.65732, 2.57916, 3.50259", \ + "0.748234, 1.05546, 1.36281, 1.67018, 2.5915, 3.51342", \ + "0.760502, 1.06749, 1.37484, 1.68181, 2.6034, 3.52517", \ + "0.785054, 1.09224, 1.39943, 1.70636, 2.62818, 3.54974", \ + "0.825152, 1.13248, 1.43961, 1.74677, 2.66875, 3.58963", \ + "0.899313, 1.20696, 1.51438, 1.82146, 2.74296, 3.66372", \ + "1.02495, 1.33353, 1.64152, 1.94833, 2.86904, 3.79013" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.728666, 1.31675, 1.90602, 2.49674, 4.27212, 6.05241", \ + "0.728866, 1.31676, 1.90603, 2.49715, 4.27252, 6.05822", \ + "0.729063, 1.31677, 1.90604, 2.49716, 4.27254, 6.05823", \ + "0.729064, 1.31678, 1.90704, 2.49717, 4.27255, 6.05824", \ + "0.729065, 1.31679, 1.90705, 2.49718, 4.27371, 6.05825", \ + "0.729066, 1.3168, 1.90706, 2.49906, 4.27372, 6.05826", \ + "0.729067, 1.31681, 1.90707, 2.50053, 4.27373, 6.05827" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : negative_unate; + timing_type : three_state_disable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.589415, 0.589416, 0.589417, 0.589418, 0.589419, 0.58942", \ + "0.606144, 0.606145, 0.606146, 0.606147, 0.606148, 0.606149", \ + "0.615547, 0.615548, 0.615549, 0.61555, 0.615551, 0.615552", \ + "0.630534, 0.630535, 0.630536, 0.630537, 0.630538, 0.630539", \ + "0.656278, 0.656279, 0.65628, 0.656281, 0.656282, 0.656283", \ + "0.69886, 0.698861, 0.698862, 0.698863, 0.698864, 0.698865", \ + "0.769914, 0.769915, 0.769916, 0.769917, 0.769918, 0.769919" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.589415, 0.589416, 0.589417, 0.589418, 0.589419, 0.58942", \ + "0.606144, 0.606145, 0.606146, 0.606147, 0.606148, 0.606149", \ + "0.615547, 0.615548, 0.615549, 0.61555, 0.615551, 0.615552", \ + "0.630534, 0.630535, 0.630536, 0.630537, 0.630538, 0.630539", \ + "0.656278, 0.656279, 0.65628, 0.656281, 0.656282, 0.656283", \ + "0.69886, 0.698861, 0.698862, 0.698863, 0.698864, 0.698865", \ + "0.769914, 0.769915, 0.769916, 0.769917, 0.769918, 0.769919" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.348876, 0.348877, 0.348878, 0.348879, 0.34888, 0.348881", \ + "0.366761, 0.366762, 0.366763, 0.366764, 0.366765, 0.366766", \ + "0.379733, 0.379734, 0.379735, 0.379736, 0.379737, 0.379738", \ + "0.402008, 0.402009, 0.40201, 0.402011, 0.402012, 0.402013", \ + "0.436528, 0.436529, 0.43653, 0.436531, 0.436532, 0.436533", \ + "0.492592, 0.492593, 0.492594, 0.492595, 0.492596, 0.492597", \ + "0.581213, 0.581214, 0.581215, 0.581216, 0.581217, 0.581218" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.348876, 0.348877, 0.348878, 0.348879, 0.34888, 0.348881", \ + "0.366761, 0.366762, 0.366763, 0.366764, 0.366765, 0.366766", \ + "0.379733, 0.379734, 0.379735, 0.379736, 0.379737, 0.379738", \ + "0.402008, 0.402009, 0.40201, 0.402011, 0.402012, 0.402013", \ + "0.436528, 0.436529, 0.43653, 0.436531, 0.436532, 0.436533", \ + "0.492592, 0.492593, 0.492594, 0.492595, 0.492596, 0.492597", \ + "0.581213, 0.581214, 0.581215, 0.581216, 0.581217, 0.581218" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : positive_unate; + timing_type : three_state_enable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.01908, 1.33455, 1.64793, 1.96067, 2.89816, 3.8355", \ + "1.02994, 1.34524, 1.65864, 1.97145, 2.90907, 3.84607", \ + "1.03433, 1.34946, 1.6629, 1.97567, 2.91304, 3.85028", \ + "1.04536, 1.36069, 1.67412, 1.98689, 2.92436, 3.86181", \ + "1.05786, 1.37318, 1.68659, 1.99938, 2.93693, 3.87464", \ + "1.06511, 1.38039, 1.69372, 2.00647, 2.94396, 3.88103", \ + "1.0698, 1.38525, 1.69904, 2.01146, 2.94892, 3.88588" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.793413, 1.41703, 2.04726, 2.67842, 4.565, 6.46252", \ + "0.793713, 1.41713, 2.04727, 2.67843, 4.56675, 6.46253", \ + "0.793982, 1.41714, 2.04728, 2.67844, 4.57427, 6.46853", \ + "0.793983, 1.41715, 2.04729, 2.67867, 4.57428, 6.46854", \ + "0.793984, 1.41716, 2.0473, 2.6787, 4.57429, 6.46855", \ + "0.793985, 1.41755, 2.04731, 2.67871, 4.5743, 6.46928", \ + "0.794035, 1.41756, 2.04732, 2.67872, 4.57431, 6.46929" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.750263, 1.09034, 1.42949, 1.76884, 2.78481, 3.8026", \ + "0.760316, 1.10048, 1.43953, 1.77888, 2.79493, 3.81133", \ + "0.764364, 1.10455, 1.44357, 1.7829, 2.79904, 3.81508", \ + "0.770381, 1.11045, 1.44957, 1.78869, 2.80556, 3.82011", \ + "0.774855, 1.11506, 1.45424, 1.79323, 2.80922, 3.82419", \ + "0.774856, 1.11507, 1.45425, 1.79324, 2.80923, 3.8242", \ + "0.774857, 1.11508, 1.45426, 1.79325, 2.80924, 3.82421" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.725255, 1.31238, 1.90513, 2.49482, 4.2691, 6.05464", \ + "0.725256, 1.31293, 1.90514, 2.49616, 4.26962, 6.05465", \ + "0.725257, 1.31319, 1.90515, 2.49617, 4.27015, 6.05622", \ + "0.725258, 1.3132, 1.90516, 2.49731, 4.2742, 6.05623", \ + "0.725259, 1.31321, 1.90517, 2.49732, 4.27421, 6.05624", \ + "0.72526, 1.31455, 1.90518, 2.49733, 4.28085, 6.05625", \ + "0.725261, 1.31456, 1.90519, 2.49734, 4.28086, 6.05626" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "4.26685, 4.21488, 4.2102, 4.1688, 3.97814, 3.85798", \ + "4.2634, 4.21975, 4.20469, 4.15451, 4.01612, 3.86327", \ + "4.26319, 4.21746, 4.20286, 4.14504, 3.99794, 3.86244", \ + "4.25619, 4.2045, 4.19656, 4.14054, 3.99204, 3.77946", \ + "4.2564, 4.21273, 4.20026, 4.14101, 4.0631, 3.83782", \ + "4.23786, 4.19607, 4.18277, 4.14839, 3.93581, 3.85247", \ + "4.28384, 4.19921, 4.16509, 4.15051, 3.94826, 3.86064" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.14328, 2.11784, 2.10594, 2.09907, 2.08893, 2.08383", \ + "2.16262, 2.12937, 2.11451, 2.10584, 2.09282, 2.08693", \ + "2.16902, 2.13538, 2.11753, 2.10897, 2.09537, 2.08914", \ + "2.17203, 2.13786, 2.1206, 2.11204, 2.09839, 2.09228", \ + "2.16609, 2.13334, 2.11977, 2.11113, 2.09867, 2.09319", \ + "2.15106, 2.12902, 2.11881, 2.11281, 2.10427, 2.10061", \ + "2.12664, 2.12249, 2.1196, 2.11873, 2.11705, 2.11609" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.79539, 5.49049, 8.20635, 10.9082, 19.0152, 27.1303", \ + "2.80489, 5.49581, 8.20682, 10.9188, 19.0316, 27.1313", \ + "2.82218, 5.51236, 8.22338, 10.9344, 19.0393, 27.148", \ + "2.87134, 5.56368, 8.26941, 10.982, 19.0894, 27.2114", \ + "2.97758, 5.66869, 8.37792, 11.0865, 19.2041, 27.3143", \ + "3.20321, 5.89223, 8.60943, 11.3144, 19.4171, 27.533", \ + "3.65799, 6.33638, 9.05004, 11.7532, 19.8546, 27.9875" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.330791, 0.332688, 0.333865, 0.335481, 0.341791, 0.34636", \ + "0.340675, 0.341989, 0.343443, 0.345289, 0.350415, 0.355645", \ + "0.3598, 0.361501, 0.362405, 0.363986, 0.369428, 0.373161", \ + "0.410096, 0.411526, 0.413005, 0.414537, 0.421167, 0.425949", \ + "0.5157, 0.517299, 0.518315, 0.519841, 0.525876, 0.531948", \ + "0.735355, 0.736576, 0.737645, 0.739937, 0.744296, 0.748255", \ + "1.17713, 1.17806, 1.18012, 1.18229, 1.18548, 1.19324" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "4.05897, 4.27337, 4.50824, 4.71488, 5.27818, 5.9206", \ + "4.06655, 4.27661, 4.50745, 4.68306, 5.25953, 5.86883", \ + "4.05369, 4.25998, 4.49561, 4.69199, 5.36976, 5.97427", \ + "4.06139, 4.2732, 4.5054, 4.72637, 5.25686, 5.86922", \ + "4.06907, 4.28086, 4.51328, 4.73519, 5.28905, 5.86861", \ + "4.02644, 4.23715, 4.44092, 4.6701, 5.23742, 5.9638", \ + "4.03931, 4.27067, 4.47538, 4.66664, 5.26547, 5.94893" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.20846, 1.20718, 1.20669, 1.20664, 1.2057, 1.20556", \ + "1.20904, 1.208, 1.20726, 1.20656, 1.20626, 1.20595", \ + "1.20857, 1.20755, 1.20675, 1.20602, 1.20573, 1.20544", \ + "1.20848, 1.20749, 1.20803, 1.20721, 1.20666, 1.2063", \ + "1.21321, 1.2112, 1.21042, 1.21066, 1.21007, 1.20973", \ + "1.20885, 1.20835, 1.20789, 1.20743, 1.20704, 1.20677", \ + "1.21002, 1.20869, 1.20798, 1.20813, 1.20737, 1.20713" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.74067, 5.43453, 8.14637, 10.8524, 18.9635, 27.0815", \ + "2.75367, 5.45169, 8.16366, 10.8653, 18.978, 27.0885", \ + "2.77301, 5.47217, 8.18262, 10.8936, 19.0083, 27.1242", \ + "2.82928, 5.52581, 8.23824, 10.9451, 19.0292, 27.17", \ + "2.93755, 5.63409, 8.34667, 11.0544, 19.1537, 27.2664", \ + "3.16697, 5.86202, 8.56785, 11.2832, 19.3783, 27.5191", \ + "3.62694, 6.31688, 9.02809, 11.738, 19.8438, 27.9573" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.166762, 0.1686, 0.169893, 0.171231, 0.175323, 0.182352", \ + "0.174821, 0.176411, 0.177664, 0.180583, 0.183916, 0.187621", \ + "0.185499, 0.187291, 0.188368, 0.190174, 0.194699, 0.198956", \ + "0.214136, 0.216569, 0.217063, 0.21899, 0.224451, 0.226984", \ + "0.27172, 0.274234, 0.275118, 0.276497, 0.282346, 0.28594", \ + "0.396242, 0.397384, 0.398854, 0.400605, 0.40491, 0.410642", \ + "0.646773, 0.649496, 0.650391, 0.652329, 0.657174, 0.660315" \ + ); + } + } + } + pin (p2c) { + direction : "output"; + output_voltage : "core"; + function : "pad"; + related_ground_pin : vss; + related_power_pin : vdd; + max_capacitance : 1.70927; + timing () { + related_pin : "pad"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0494206, 0.0587623, 0.0756481, 0.0920541, 0.108008, 0.123704", \ + "0.0494216, 0.0587633, 0.0756491, 0.0920551, 0.108009, 0.123705", \ + "0.0494226, 0.0587643, 0.0756501, 0.0920561, 0.10801, 0.123706", \ + "0.0494236, 0.0587653, 0.0756511, 0.0920571, 0.108011, 0.123707", \ + "0.0494246, 0.0587663, 0.0756521, 0.0920581, 0.108012, 0.123708", \ + "0.0494256, 0.0587673, 0.0756531, 0.0920591, 0.108013, 0.123709", \ + "0.0494266, 0.0587683, 0.0756541, 0.0920601, 0.108014, 0.12371" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0351131, 0.0520245, 0.0857493, 0.119935, 0.154392, 0.189098", \ + "0.0387187, 0.0548122, 0.0878816, 0.122087, 0.156906, 0.191474", \ + "0.045545, 0.0609624, 0.0923723, 0.125272, 0.159074, 0.193352", \ + "0.0487742, 0.0638268, 0.0948019, 0.127402, 0.160633, 0.194635", \ + "0.061352, 0.0763967, 0.105657, 0.136742, 0.168506, 0.201138", \ + "0.081968, 0.0970098, 0.125645, 0.154208, 0.184013, 0.215312", \ + "0.097279, 0.112291, 0.141344, 0.169455, 0.197801, 0.227551" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.203051, 0.214823, 0.234434, 0.251133, 0.267111, 0.282148", \ + "0.257015, 0.268848, 0.28839, 0.3053, 0.321057, 0.335881", \ + "0.373223, 0.384988, 0.40453, 0.421504, 0.437197, 0.452177", \ + "0.434377, 0.446043, 0.465303, 0.482356, 0.497541, 0.513014", \ + "0.724425, 0.736737, 0.756738, 0.773672, 0.789449, 0.80395", \ + "1.25489, 1.26855, 1.29106, 1.30998, 1.32734, 1.34331", \ + "1.72163, 1.73638, 1.76038, 1.78051, 1.79854, 1.81512" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0571529, 0.0706179, 0.0968246, 0.12227, 0.148578, 0.174864", \ + "0.0571539, 0.0706189, 0.0968256, 0.122472, 0.148579, 0.174865", \ + "0.0572009, 0.0707008, 0.0968662, 0.12263, 0.14858, 0.174895", \ + "0.0575786, 0.0710905, 0.0970075, 0.1231, 0.148581, 0.175138", \ + "0.071608, 0.084046, 0.108293, 0.132242, 0.157118, 0.182313", \ + "0.099657, 0.111693, 0.135622, 0.158414, 0.182272, 0.206389", \ + "0.118704, 0.130632, 0.153731, 0.176683, 0.199018, 0.222167" \ + ); + } + } + internal_power () { + related_pin : "pad"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "-0.173127, -0.173982, -0.173285, -0.174167, -0.174158, -0.174156", \ + "-0.174367, -0.174365, -0.173346, -0.173747, -0.174033, -0.173867", \ + "-0.174516, -0.174631, -0.174261, -0.174258, -0.174258, -0.174255", \ + "-0.173887, -0.173882, -0.173867, -0.173849, -0.173846, -0.173829", \ + "-0.173436, -0.173374, -0.173486, -0.173782, -0.173523, -0.17381", \ + "-0.173761, -0.173531, -0.173504, -0.173647, -0.173496, -0.173558", \ + "0.0366241, 0.0366118, 0.0365922, 0.0355722, 0.0371308, 0.0353475" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.174168, 0.174167, 0.174164, 0.174167, 0.174158, 0.174156", \ + "0.174367, 0.174365, 0.174356, 0.174354, 0.174351, 0.174349", \ + "0.174543, 0.174631, 0.174261, 0.174258, 0.174258, 0.174255", \ + "0.173887, 0.173882, 0.173867, 0.173849, 0.173846, 0.173829", \ + "0.173436, 0.173374, 0.173486, 0.173782, 0.173523, 0.17381", \ + "0.173761, 0.173531, 0.173504, 0.173647, 0.173496, 0.173558", \ + "0.173623, 0.173569, 0.173477, 0.173362, 0.173435, 0.173558" \ + ); + } + } + internal_power () { + related_pin : "pad"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0109527, 0.0107032, 0.00972262, 0.0093966, 0.00925089, 0.00866598", \ + "0.010865, 0.0104708, 0.0103189, 0.00968733, 0.00923802, 0.00874386", \ + "0.0133313, 0.0115248, 0.00943767, 0.00875805, 0.00907054, 0.00866252", \ + "0.0152625, 0.0124663, 0.010079, 0.00920289, 0.00835296, 0.00815663", \ + "0.0238695, 0.0195242, 0.0156281, 0.0135965, 0.0109591, 0.00946013", \ + "0.0417995, 0.0337486, 0.0270277, 0.0229916, 0.0204478, 0.0190323", \ + "0.116245, 0.105698, 0.0959361, 0.0919969, 0.0870091, 0.0847072" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.102279, 0.0979112, 0.0954079, 0.0946871, 0.0944253, 0.0941901", \ + "0.101076, 0.0966028, 0.094041, 0.0933031, 0.0929646, 0.092736", \ + "0.101499, 0.0969551, 0.0938357, 0.0929183, 0.0924937, 0.092219", \ + "0.10284, 0.0980399, 0.0947984, 0.0936465, 0.0929944, 0.0926078", \ + "0.113196, 0.106155, 0.10069, 0.0983679, 0.0972096, 0.0968226", \ + "0.140729, 0.129855, 0.118196, 0.112825, 0.109634, 0.107528", \ + "0.157956, 0.143437, 0.127507, 0.11996, 0.115757, 0.113277" \ + ); + } + } + } + pin (c2p) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.016; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.031498; + rise_capacitance : 0.031746; + rise_capacitance_range (0.0245486, 0.0372814); + fall_capacitance : 0.03125; + fall_capacitance_range (0.0252984, 0.0337121); + internal_power () { + when : "(!c2p_en * pad * p2c)"; + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-1.75371e-05, -1.29722e-05, -6.2825e-06, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "1.75371e-05, 1.29722e-05, 6.2825e-06, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + when : "(!c2p_en * pad * p2c)"; + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0345885, -0.0357936, -0.0361564, -0.0365758, -0.036737, -0.0369406, -0.0368259" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0450127, 0.0443943, 0.0441665, 0.0440997, 0.0441325, 0.0442615, 0.0440573" \ + ); + } + } + internal_power () { + when : "(!c2p_en * !pad * !p2c)"; + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-1.74914e-05, -1.2984e-05, -6.2943e-06, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "1.74914e-05, 1.2984e-05, 6.2943e-06, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + when : "(!c2p_en * !pad * !p2c)"; + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0345857, -0.0357916, -0.0361543, -0.0365749, -0.0367367, -0.0369406, -0.0368261" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0450096, 0.0443927, 0.0441658, 0.0440992, 0.044132, 0.0442614, 0.0440572" \ + ); + } + } + internal_power () { + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-1.74914e-05, -1.2984e-05, -6.2943e-06, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "1.74914e-05, 1.2984e-05, 6.2943e-06, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0345857, -0.0357916, -0.0361543, -0.0365749, -0.0367367, -0.0369406, -0.0368261" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0450096, 0.0443927, 0.0441658, 0.0440992, 0.044132, 0.0442614, 0.0440572" \ + ); + } + } + } + pin (c2p_en) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.011; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0280667; + rise_capacitance : 0.0293182; + rise_capacitance_range (0.0234222, 0.0371855); + fall_capacitance : 0.0268152; + fall_capacitance_range (0.0227686, 0.0320786); + internal_power () { + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.979721, 0.979978, 0.979863, 0.980265, 0.980365, 0.981087, 0.981469" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.383971, 0.381634, 0.380361, 0.378775, 0.380175, 0.376881, 0.375967" \ + ); + } + } + internal_power () { + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0652314, 0.0727543, 0.0837524, 0.111066, 0.170357, 0.293502, 0.552503" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.160237, 0.171461, 0.183055, 0.212778, 0.272206, 0.396243, 0.651737" \ + ); + } + } + } + } + cell (sg13g2_IOPadOut16mA) { + pad_cell : true; + area : 14400; + cell_footprint : "inout"; + pad_drivers : 1; + bond_pads : 1; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 1116.98; + when : "!c2p&!pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 1826.61; + when : "!c2p&!pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 282.332; + when : "c2p&pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 6376.16; + when : "c2p&pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 699.654; + related_pg_pin : iovdd; + } + leakage_power () { + value : 4101.39; + related_pg_pin : vdd; + } + pin (pad) { + direction : "output"; + is_pad : true; + function : "c2p"; + drive_current : 16; + output_voltage : "pad"; + related_ground_pin : iovss; + related_power_pin : iovdd; + max_capacitance : 6.49658; + timing () { + related_pin : "c2p"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 3, 7, 9, 12, 15"); + values ( \ + "1.00861, 1.22141, 1.55354, 1.7086, 1.93785, 2.16594", \ + "1.0306, 1.24334, 1.57533, 1.72991, 1.95982, 2.18795", \ + "1.05009, 1.26294, 1.59484, 1.75004, 1.97941, 2.20755", \ + "1.08937, 1.30186, 1.63401, 1.78936, 2.01886, 2.24674", \ + "1.15488, 1.368, 1.69999, 1.85482, 2.08494, 2.31246", \ + "1.27085, 1.4846, 1.81579, 1.97143, 2.20041, 2.42856", \ + "1.47787, 1.69028, 2.02148, 2.17757, 2.40743, 2.63486" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 3, 7, 9, 12, 15"); + values ( \ + "0.37306, 0.680981, 1.27503, 1.57726, 2.03611, 2.50114", \ + "0.373094, 0.680982, 1.27504, 1.57727, 2.03663, 2.50115", \ + "0.373095, 0.680998, 1.27505, 1.5775, 2.03664, 2.50116", \ + "0.373096, 0.680999, 1.27506, 1.57751, 2.03665, 2.50117", \ + "0.373097, 0.681409, 1.27507, 1.57752, 2.03677, 2.50118", \ + "0.373534, 0.682177, 1.27508, 1.57757, 2.03678, 2.50119", \ + "0.374103, 0.682178, 1.27509, 1.57758, 2.03679, 2.50229" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 3, 7, 9, 12, 15"); + values ( \ + "0.670514, 0.841174, 1.13496, 1.27891, 1.49925, 1.72302", \ + "0.68081, 0.851377, 1.14497, 1.28944, 1.51055, 1.7332", \ + "0.686502, 0.857099, 1.15075, 1.29521, 1.51629, 1.73896", \ + "0.695375, 0.866018, 1.15962, 1.30408, 1.52411, 1.74779", \ + "0.713109, 0.882982, 1.17769, 1.32152, 1.5418, 1.76547", \ + "0.742553, 0.912185, 1.20723, 1.35203, 1.57195, 1.79569", \ + "0.786821, 0.95745, 1.25132, 1.3959, 1.61632, 1.83952" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 3, 7, 9, 12, 15"); + values ( \ + "0.459001, 0.683451, 1.201, 1.47476, 1.89581, 2.32504", \ + "0.459438, 0.68351, 1.20109, 1.47477, 1.89582, 2.32508", \ + "0.459439, 0.683511, 1.20112, 1.47478, 1.89583, 2.32509", \ + "0.45944, 0.683561, 1.20113, 1.47479, 1.89596, 2.32511", \ + "0.459441, 0.683562, 1.20114, 1.4748, 1.89597, 2.32512", \ + "0.459442, 0.683563, 1.2013, 1.47481, 1.89654, 2.32513", \ + "0.459443, 0.683564, 1.20131, 1.47482, 1.89655, 2.32514" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 3, 7, 9, 12, 15"); + values ( \ + "7.73342, 7.54765, 7.4664, 7.38248, 7.22837, 7.18322", \ + "7.7397, 7.55384, 7.46834, 7.34098, 7.27844, 7.1815", \ + "7.72092, 7.56144, 7.47065, 7.38086, 7.26548, 7.2009", \ + "7.74535, 7.56245, 7.4741, 7.40696, 7.33043, 7.20997", \ + "7.77318, 7.64726, 7.54132, 7.41874, 7.41888, 7.25645", \ + "7.86646, 7.75444, 7.60241, 7.57804, 7.40801, 7.36063", \ + "8.03058, 7.79746, 7.57382, 7.63171, 7.55554, 7.38454" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 3, 7, 9, 12, 15"); + values ( \ + "19.897, 16.0611, 12.7075, 11.7952, 10.7911, 10.0533", \ + "19.8871, 16.0548, 12.7097, 11.7561, 10.7586, 10.0457", \ + "19.8808, 16.0478, 12.7019, 11.7492, 10.7474, 10.0396", \ + "19.8787, 16.0398, 12.693, 11.7388, 10.7657, 10.0289", \ + "19.8581, 16.0236, 12.6818, 11.7545, 10.7615, 10.0278", \ + "19.8345, 16.0104, 12.6842, 11.7502, 10.779, 10.0314", \ + "19.8191, 16.004, 12.6652, 11.7405, 10.766, 10.0292" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 3, 7, 9, 12, 15"); + values ( \ + "-0.0232037, -0.0232035, -0.0232031, -0.0232039, -0.0232046, -0.023204", \ + "-0.00666839, -0.00666824, -0.00666807, -0.00666845, -0.00666915, -0.00666916", \ + "0.0146588, 0.0146589, 0.0146593, 0.0146585, 0.0146578, 0.0146585", \ + "0.0660763, 0.0660759, 0.0660763, 0.0660755, 0.0660744, 0.0660755", \ + "0.171125, 0.17103, 0.17103, 0.17103, 0.171029, 0.171029", \ + "0.383078, 0.383079, 0.383104, 0.383103, 0.383102, 0.383103", \ + "0.807961, 0.80795, 0.807892, 0.807985, 0.807943, 0.807895" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 3, 7, 9, 12, 15"); + values ( \ + "0.111462, 0.111462, 0.111463, 0.11146, 0.111461, 0.111465", \ + "0.133658, 0.133658, 0.133657, 0.133651, 0.133651, 0.13366", \ + "0.156325, 0.156327, 0.156326, 0.156324, 0.156325, 0.156329", \ + "0.208564, 0.208565, 0.208565, 0.208563, 0.208563, 0.208568", \ + "0.31613, 0.316487, 0.316404, 0.316208, 0.316407, 0.316408", \ + "0.52423, 0.524573, 0.524385, 0.524643, 0.524675, 0.524187", \ + "0.950187, 0.950266, 0.950402, 0.950115, 0.950299, 0.950125" \ + ); + } + } + } + pin (c2p) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.016; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0436858; + rise_capacitance : 0.0423121; + rise_capacitance_range (0.0369655, 0.0458742); + fall_capacitance : 0.0450594; + fall_capacitance_range (0.0398753, 0.0481484); + } + } + cell (sg13g2_IOPadOut30mA) { + pad_cell : true; + area : 14400; + cell_footprint : "inout"; + pad_drivers : 1; + bond_pads : 1; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 2129.07; + when : "!c2p&!pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 1825.36; + when : "!c2p&!pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 524.869; + when : "c2p&pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 6376.03; + when : "c2p&pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 1326.97; + related_pg_pin : iovdd; + } + leakage_power () { + value : 4100.69; + related_pg_pin : vdd; + } + pin (pad) { + direction : "output"; + is_pad : true; + function : "c2p"; + drive_current : 30; + output_voltage : "pad"; + related_ground_pin : iovss; + related_power_pin : iovdd; + max_capacitance : 9.66853; + timing () { + related_pin : "c2p"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("2, 6, 14, 18, 24, 30"); + values ( \ + "1.28565, 1.57262, 1.98017, 2.15608, 2.41259, 2.66101", \ + "1.30945, 1.59547, 2.00097, 2.1793, 2.43306, 2.68249", \ + "1.32704, 1.6134, 2.02014, 2.19656, 2.45234, 2.70232", \ + "1.36571, 1.65173, 2.05839, 2.23489, 2.49136, 2.73917", \ + "1.43326, 1.71906, 2.12357, 2.30225, 2.5585, 2.80644", \ + "1.5473, 1.83326, 2.23832, 2.41697, 2.67346, 2.92149", \ + "1.75486, 2.04052, 2.44766, 2.62406, 2.88057, 3.12983" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("2, 6, 14, 18, 24, 30"); + values ( \ + "0.482808, 0.859201, 1.50096, 1.81702, 2.29945, 2.787", \ + "0.482809, 0.860084, 1.50097, 1.8194, 2.2998, 2.78731", \ + "0.483694, 0.860085, 1.50098, 1.81941, 2.29981, 2.7883", \ + "0.483695, 0.860086, 1.50099, 1.81942, 2.29982, 2.78831", \ + "0.483696, 0.860308, 1.501, 1.81943, 2.29983, 2.78832", \ + "0.483974, 0.860309, 1.50101, 1.81944, 2.29984, 2.78833", \ + "0.483975, 0.861476, 1.50212, 1.81945, 2.29985, 2.78834" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("2, 6, 14, 18, 24, 30"); + values ( \ + "0.940409, 1.14488, 1.48248, 1.6379, 1.86542, 2.09382", \ + "0.950951, 1.15519, 1.49396, 1.64884, 1.87732, 2.10335", \ + "0.9566, 1.16152, 1.49867, 1.65358, 1.88327, 2.11155", \ + "0.965127, 1.16959, 1.50786, 1.66293, 1.89106, 2.11748", \ + "0.982969, 1.1878, 1.52513, 1.67947, 1.90958, 2.13784", \ + "1.01158, 1.21716, 1.55347, 1.7081, 1.93737, 2.16408", \ + "1.05543, 1.26012, 1.59762, 1.75121, 1.97972, 2.20906" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("2, 6, 14, 18, 24, 30"); + values ( \ + "0.755997, 0.975225, 1.46438, 1.73858, 2.16521, 2.60108", \ + "0.756029, 0.975226, 1.4652, 1.73859, 2.16522, 2.6018", \ + "0.756128, 0.97583, 1.46521, 1.7386, 2.16523, 2.60329", \ + "0.756129, 0.976958, 1.46528, 1.73861, 2.16547, 2.6033", \ + "0.75613, 0.976959, 1.46529, 1.73862, 2.16548, 2.60357", \ + "0.756131, 0.97696, 1.4653, 1.73925, 2.16627, 2.60358", \ + "0.756132, 0.976961, 1.46531, 1.73926, 2.16628, 2.60359" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("2, 6, 14, 18, 24, 30"); + values ( \ + "12.8574, 12.3418, 12.2045, 11.7416, 11.5716, 11.4102", \ + "12.8746, 12.4327, 12.1932, 12.188, 11.6585, 11.4307", \ + "12.8897, 12.4318, 12.1919, 11.7325, 11.6614, 11.5567", \ + "12.8918, 12.4405, 12.194, 11.8124, 11.6284, 11.3594", \ + "12.9656, 12.4874, 11.9034, 11.8369, 11.6664, 11.2007", \ + "13.0001, 12.4611, 11.964, 11.9159, 11.7404, 11.38", \ + "13.1188, 12.5759, 12.3341, 11.8573, 11.8121, 11.6885" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("2, 6, 14, 18, 24, 30"); + values ( \ + "71.5119, 59.3996, 46.4346, 42.5643, 38.2531, 34.9269", \ + "71.5065, 59.3699, 46.4793, 42.5604, 38.1496, 34.9777", \ + "71.5045, 59.3728, 46.4437, 42.4796, 38.1754, 35.0172", \ + "71.4955, 59.3627, 46.4589, 42.5174, 38.1996, 34.9593", \ + "71.4462, 59.3059, 46.3568, 42.4789, 38.1462, 34.9849", \ + "71.4122, 59.3421, 46.4229, 42.5456, 38.1815, 34.9475", \ + "71.2549, 59.1172, 46.274, 42.3308, 38.0261, 34.8684" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("2, 6, 14, 18, 24, 30"); + values ( \ + "-0.0232329, -0.0232327, -0.0232332, -0.0232331, -0.0232333, -0.0232336", \ + "-0.00672926, -0.00672898, -0.00672819, -0.00672836, -0.00672848, -0.00672942", \ + "0.014567, 0.0145666, 0.0145673, 0.0145672, 0.0145671, 0.0145665", \ + "0.0659146, 0.0659147, 0.0659148, 0.0659149, 0.0659146, 0.0659141", \ + "0.170603, 0.170603, 0.170603, 0.170604, 0.170603, 0.170603", \ + "0.3863, 0.3863, 0.3863, 0.3863, 0.3863, 0.3863", \ + "0.808597, 0.808502, 0.808476, 0.808471, 0.80858, 0.808549" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("2, 6, 14, 18, 24, 30"); + values ( \ + "0.11148, 0.11148, 0.11148, 0.111479, 0.111484, 0.111483", \ + "0.133601, 0.133601, 0.1336, 0.133599, 0.133606, 0.133604", \ + "0.156249, 0.156248, 0.156247, 0.156249, 0.156252, 0.156254", \ + "0.208652, 0.208651, 0.208651, 0.208651, 0.208656, 0.208653", \ + "0.315769, 0.31575, 0.315749, 0.315883, 0.315886, 0.315888", \ + "0.524067, 0.524025, 0.523598, 0.523979, 0.524198, 0.523909", \ + "0.949522, 0.949681, 0.949606, 0.949477, 0.949998, 0.949932" \ + ); + } + } + } + pin (c2p) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.016; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0436819; + rise_capacitance : 0.0422883; + rise_capacitance_range (0.0369505, 0.045777); + fall_capacitance : 0.0450755; + fall_capacitance_range (0.0398526, 0.0481717); + } + } + cell (sg13g2_IOPadOut4mA) { + pad_cell : true; + area : 14400; + cell_footprint : "inout"; + pad_drivers : 1; + bond_pads : 1; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 354.02; + when : "!c2p&!pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 1825.28; + when : "!c2p&!pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 184.993; + when : "c2p&pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 6376.19; + when : "c2p&pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 269.507; + related_pg_pin : iovdd; + } + leakage_power () { + value : 4100.73; + related_pg_pin : vdd; + } + pin (pad) { + direction : "output"; + is_pad : true; + function : "c2p"; + drive_current : 4; + output_voltage : "pad"; + related_ground_pin : iovss; + related_power_pin : iovdd; + max_capacitance : 1.68968; + timing () { + related_pin : "c2p"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.984383, 1.28831, 1.59048, 1.89272, 2.79613, 3.69929", \ + "1.00607, 1.31003, 1.61291, 1.9143, 2.81795, 3.72109", \ + "1.02573, 1.32966, 1.6327, 1.93395, 2.83701, 3.74064", \ + "1.06477, 1.36883, 1.67143, 1.97285, 2.87654, 3.7803", \ + "1.13121, 1.43521, 1.73798, 2.0397, 2.94309, 3.84602", \ + "1.24813, 1.55213, 1.85506, 2.15643, 3.05999, 3.96301", \ + "1.45321, 1.75832, 2.0604, 2.36249, 3.26589, 4.17015" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.772504, 1.39233, 2.01993, 2.64852, 4.54032, 6.42992", \ + "0.772505, 1.39256, 2.01994, 2.64902, 4.54033, 6.42993", \ + "0.772506, 1.39306, 2.01995, 2.64903, 4.54034, 6.42994", \ + "0.772507, 1.39307, 2.01996, 2.64904, 4.54035, 6.42995", \ + "0.772508, 1.39308, 2.01997, 2.64905, 4.54036, 6.42996", \ + "0.772509, 1.39309, 2.01998, 2.64906, 4.54037, 6.42997", \ + "0.773164, 1.39327, 2.01999, 2.64907, 4.54037, 6.42998" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.686111, 0.992308, 1.29874, 1.60511, 2.52546, 3.44567", \ + "0.696243, 1.00232, 1.3087, 1.61547, 2.5349, 3.45567", \ + "0.70213, 1.00823, 1.31493, 1.62092, 2.54148, 3.46168", \ + "0.711372, 1.01755, 1.3238, 1.63007, 2.55062, 3.47083", \ + "0.728961, 1.03525, 1.34157, 1.64788, 2.56791, 3.4884", \ + "0.758642, 1.06466, 1.371, 1.67767, 2.59811, 3.51806", \ + "0.803405, 1.10952, 1.41589, 1.7227, 2.64195, 3.56209" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.708862, 1.29046, 1.87879, 2.46821, 4.23823, 6.00909", \ + "0.708863, 1.29161, 1.8788, 2.46842, 4.23824, 6.0091", \ + "0.708864, 1.29162, 1.87887, 2.46843, 4.23825, 6.00911", \ + "0.708865, 1.29171, 1.87888, 2.46853, 4.23826, 6.00912", \ + "0.708866, 1.29172, 1.87889, 2.46854, 4.23869, 6.00979", \ + "0.708867, 1.29173, 1.8789, 2.46855, 4.23874, 6.0098", \ + "0.708868, 1.29174, 1.87891, 2.46945, 4.23875, 6.00981" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "3.83833, 3.79612, 3.76985, 3.72877, 3.63229, 3.50788", \ + "3.84605, 3.8065, 3.7737, 3.74328, 3.64709, 3.48898", \ + "3.85417, 3.81524, 3.78349, 3.74706, 3.61112, 3.5051", \ + "3.87602, 3.83617, 3.8003, 3.76132, 3.67733, 3.51464", \ + "3.92018, 3.88053, 3.84484, 3.80999, 3.72294, 3.56483", \ + "3.99896, 3.96407, 3.93329, 3.89444, 3.80459, 3.64468", \ + "4.14311, 4.10871, 4.06764, 4.03042, 3.94121, 3.8065" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.31467, 2.26098, 2.23452, 2.22047, 2.20002, 2.18926", \ + "2.30121, 2.24757, 2.21999, 2.20674, 2.18656, 2.17581", \ + "2.29798, 2.24418, 2.21748, 2.20395, 2.18301, 2.1728", \ + "2.28584, 2.2313, 2.20573, 2.19251, 2.17115, 2.16099", \ + "2.28805, 2.23493, 2.20878, 2.1929, 2.17458, 2.16505", \ + "2.29615, 2.24151, 2.21655, 2.20387, 2.18239, 2.17296", \ + "2.33858, 2.28509, 2.25867, 2.24532, 2.22495, 2.21476" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "-0.0232351, -0.0232361, -0.0232369, -0.0232369, -0.0232361, -0.0232365", \ + "-0.00672668, -0.00672789, -0.00672812, -0.00672835, -0.00672788, -0.00672693", \ + "0.0145704, 0.0145694, 0.0145689, 0.0145684, 0.0145692, 0.0145688", \ + "0.0659123, 0.0659118, 0.065911, 0.0659112, 0.0659111, 0.0659115", \ + "0.170739, 0.170738, 0.170738, 0.170738, 0.170738, 0.170738", \ + "0.386259, 0.386259, 0.38626, 0.38626, 0.386261, 0.38626", \ + "0.812084, 0.812014, 0.812097, 0.812135, 0.81202, 0.812013" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.111535, 0.111522, 0.111518, 0.111517, 0.111513, 0.111518", \ + "0.133636, 0.133633, 0.133631, 0.133628, 0.133627, 0.133632", \ + "0.156281, 0.156274, 0.156263, 0.156266, 0.156261, 0.156268", \ + "0.208621, 0.208617, 0.208617, 0.208619, 0.20861, 0.208617", \ + "0.315834, 0.316125, 0.316085, 0.315725, 0.316083, 0.315971", \ + "0.531865, 0.531522, 0.531745, 0.531984, 0.53159, 0.531525", \ + "0.952786, 0.952822, 0.952711, 0.953172, 0.953229, 0.952998" \ + ); + } + } + } + pin (c2p) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.016; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0436669; + rise_capacitance : 0.0422708; + rise_capacitance_range (0.0369502, 0.0456785); + fall_capacitance : 0.045063; + fall_capacitance_range (0.0398508, 0.0481448); + } + } + cell (sg13g2_IOPadTriOut16mA) { + pad_cell : true; + area : 14400; + cell_footprint : "tri_out"; + pad_drivers : 1; + bond_pads : 1; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 224.199; + when : "!c2p_en&!c2p"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 11898.9; + when : "!c2p_en&!c2p"; + related_pg_pin : vdd; + } + leakage_power () { + value : 224.199; + when : "!c2p_en&c2p"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 18954.8; + when : "!c2p_en&c2p"; + related_pg_pin : vdd; + } + leakage_power () { + value : 354.364; + when : "c2p_en&c2p&pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 19894.5; + when : "c2p_en&c2p&pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 1165.17; + when : "c2p_en&!c2p&!pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 13564.8; + when : "c2p_en&!c2p&!pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 491.983; + related_pg_pin : iovdd; + } + leakage_power () { + value : 16078.2; + related_pg_pin : vdd; + } + pin (pad) { + direction : "output"; + is_pad : true; + function : "c2p"; + three_state : "c2p_en'"; + drive_current : 16; + output_voltage : "pad"; + related_ground_pin : iovss; + related_power_pin : iovdd; + max_capacitance : 6.49315; + capacitance : 0.234686; + rise_capacitance : 0.236873; + rise_capacitance_range (0.236873, 0.236873); + fall_capacitance : 0.2325; + fall_capacitance_range (0.2325, 0.2325); + timing () { + related_pin : "c2p"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.04212, 1.15836, 1.2554, 1.34516, 1.58709, 1.82024", \ + "1.05075, 1.16673, 1.26488, 1.35341, 1.59589, 1.82839", \ + "1.05453, 1.17055, 1.26761, 1.35594, 1.60027, 1.83203", \ + "1.06042, 1.17647, 1.27347, 1.36184, 1.60578, 1.83786", \ + "1.06509, 1.18147, 1.27831, 1.36786, 1.61063, 1.84326", \ + "1.0651, 1.18148, 1.27832, 1.36787, 1.61064, 1.84327", \ + "1.06511, 1.18149, 1.27833, 1.36788, 1.61065, 1.84328" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.374284, 0.532906, 0.681287, 0.830064, 1.27474, 1.73012", \ + "0.374285, 0.532907, 0.682644, 0.830065, 1.27475, 1.73013", \ + "0.374286, 0.532908, 0.682645, 0.830066, 1.27493, 1.73014", \ + "0.374287, 0.532909, 0.682646, 0.830067, 1.27531, 1.73015", \ + "0.374335, 0.534123, 0.682647, 0.830069, 1.27532, 1.73029", \ + "0.375068, 0.534124, 0.682648, 0.830495, 1.27533, 1.7303", \ + "0.37742, 0.534824, 0.685239, 0.832746, 1.27534, 1.73031" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.713429, 0.803588, 0.884126, 0.960195, 1.17995, 1.39772", \ + "0.728394, 0.818503, 0.898975, 0.974835, 1.19422, 1.41331", \ + "0.741117, 0.831274, 0.911725, 0.987742, 1.20663, 1.42572", \ + "0.765418, 0.85548, 0.935935, 1.01207, 1.23084, 1.45003", \ + "0.804681, 0.89486, 0.975371, 1.05139, 1.27091, 1.48975", \ + "0.875239, 0.965617, 1.04651, 1.1227, 1.3418, 1.56131", \ + "0.994724, 1.08508, 1.16575, 1.24183, 1.46189, 1.6823" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.444894, 0.55546, 0.671985, 0.796051, 1.19289, 1.60896", \ + "0.448869, 0.559015, 0.674284, 0.798737, 1.19471, 1.61045", \ + "0.44995, 0.560305, 0.67516, 0.799679, 1.19597, 1.61064", \ + "0.449991, 0.560306, 0.675161, 0.79968, 1.19598, 1.61065", \ + "0.449992, 0.560307, 0.675162, 0.799681, 1.19599, 1.61066", \ + "0.449993, 0.560308, 0.675163, 0.799682, 1.196, 1.61067", \ + "0.449994, 0.560309, 0.675164, 0.799683, 1.19601, 1.61068" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : negative_unate; + timing_type : three_state_disable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.759799, 0.7598, 0.759801, 0.759802, 0.759803, 0.759804", \ + "0.775605, 0.775606, 0.775607, 0.775608, 0.775609, 0.77561", \ + "0.783394, 0.783395, 0.783396, 0.783397, 0.783398, 0.783399", \ + "0.802313, 0.802314, 0.802315, 0.802316, 0.802317, 0.802318", \ + "0.826263, 0.826264, 0.826265, 0.826266, 0.826267, 0.826268", \ + "0.863161, 0.863162, 0.863163, 0.863164, 0.863165, 0.863166", \ + "0.93939, 0.939391, 0.939392, 0.939393, 0.939394, 0.939395" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.759799, 0.7598, 0.759801, 0.759802, 0.759803, 0.759804", \ + "0.775605, 0.775606, 0.775607, 0.775608, 0.775609, 0.77561", \ + "0.783394, 0.783395, 0.783396, 0.783397, 0.783398, 0.783399", \ + "0.802313, 0.802314, 0.802315, 0.802316, 0.802317, 0.802318", \ + "0.826263, 0.826264, 0.826265, 0.826266, 0.826267, 0.826268", \ + "0.863161, 0.863162, 0.863163, 0.863164, 0.863165, 0.863166", \ + "0.93939, 0.939391, 0.939392, 0.939393, 0.939394, 0.939395" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.72561, 0.725611, 0.725612, 0.725613, 0.725614, 0.725615", \ + "0.745571, 0.745572, 0.745573, 0.745574, 0.745575, 0.745576", \ + "0.757899, 0.7579, 0.757901, 0.757902, 0.757903, 0.757904", \ + "0.779746, 0.779747, 0.779748, 0.779749, 0.77975, 0.779751", \ + "0.815345, 0.815346, 0.815347, 0.815348, 0.815349, 0.81535", \ + "0.861824, 0.861825, 0.861826, 0.861827, 0.861828, 0.861829", \ + "0.954411, 0.954412, 0.954413, 0.954414, 0.954415, 0.954416" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.72561, 0.725611, 0.725612, 0.725613, 0.725614, 0.725615", \ + "0.745571, 0.745572, 0.745573, 0.745574, 0.745575, 0.745576", \ + "0.757899, 0.7579, 0.757901, 0.757902, 0.757903, 0.757904", \ + "0.779746, 0.779747, 0.779748, 0.779749, 0.77975, 0.779751", \ + "0.815345, 0.815346, 0.815347, 0.815348, 0.815349, 0.81535", \ + "0.861824, 0.861825, 0.861826, 0.861827, 0.861828, 0.861829", \ + "0.954411, 0.954412, 0.954413, 0.954414, 0.954415, 0.954416" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : positive_unate; + timing_type : three_state_enable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.03218, 1.15599, 1.25948, 1.35252, 1.60604, 1.84926", \ + "1.04392, 1.16739, 1.27082, 1.36364, 1.6171, 1.85985", \ + "1.04925, 1.17363, 1.27619, 1.36793, 1.62278, 1.86508", \ + "1.05936, 1.18366, 1.28639, 1.37925, 1.63269, 1.87599", \ + "1.07114, 1.19544, 1.29666, 1.38927, 1.64442, 1.88809", \ + "1.08104, 1.20516, 1.30643, 1.40077, 1.65424, 1.89802", \ + "1.08708, 1.21139, 1.31412, 1.40698, 1.6605, 1.90371" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.380222, 0.530227, 0.67457, 0.820076, 1.26244, 1.7176", \ + "0.380292, 0.530228, 0.67459, 0.820077, 1.26245, 1.71761", \ + "0.380444, 0.530648, 0.67465, 0.820078, 1.26246, 1.71765", \ + "0.380445, 0.530649, 0.674798, 0.820165, 1.26266, 1.71779", \ + "0.380446, 0.53065, 0.674799, 0.820166, 1.26267, 1.7178", \ + "0.380447, 0.531097, 0.6748, 0.820167, 1.26268, 1.71781", \ + "0.380448, 0.531098, 0.676252, 0.820168, 1.26295, 1.71782" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.577965, 0.686804, 0.782786, 0.873932, 1.13345, 1.39006", \ + "0.588259, 0.696631, 0.793229, 0.884246, 1.14353, 1.40033", \ + "0.592403, 0.700927, 0.796984, 0.888077, 1.14865, 1.40413", \ + "0.598295, 0.707655, 0.804176, 0.892794, 1.15432, 1.40947", \ + "0.602356, 0.710884, 0.808118, 0.896754, 1.15867, 1.41419", \ + "0.602357, 0.710885, 0.808119, 0.896755, 1.15868, 1.4142", \ + "0.602358, 0.710886, 0.80812, 0.896756, 1.15869, 1.41421" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.27566, 0.415885, 0.553811, 0.693463, 1.11878, 1.55239", \ + "0.275703, 0.415886, 0.553946, 0.693481, 1.11879, 1.5524", \ + "0.275877, 0.415887, 0.553947, 0.693482, 1.11884, 1.55241", \ + "0.275879, 0.416427, 0.554736, 0.693483, 1.11885, 1.55286", \ + "0.276204, 0.416428, 0.555036, 0.693484, 1.11895, 1.55287", \ + "0.276205, 0.416429, 0.555037, 0.693485, 1.11924, 1.55288", \ + "0.276206, 0.416471, 0.555038, 0.693486, 1.11925, 1.55289" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "7.66479, 7.55135, 7.50215, 7.57976, 7.36078, 7.35124", \ + "7.6868, 7.5577, 7.58797, 7.58106, 7.37791, 7.33486", \ + "7.68298, 7.56108, 7.50863, 7.46114, 7.44221, 7.33943", \ + "7.68829, 7.56125, 7.50557, 7.46989, 7.43771, 7.33334", \ + "7.66614, 7.61217, 7.49434, 7.55701, 7.40765, 7.32503", \ + "7.58263, 7.50964, 7.45542, 7.52972, 7.40254, 7.32755", \ + "7.54436, 7.45507, 7.48642, 7.60108, 7.35764, 7.26635" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "18.6912, 16.5544, 15.1047, 14.0414, 12.0124, 10.8356", \ + "19.0241, 16.8506, 15.365, 14.2879, 12.2104, 10.9702", \ + "19.1471, 16.9568, 15.4592, 14.3693, 12.2986, 11.0269", \ + "19.116, 16.9309, 15.436, 14.3571, 12.2694, 11.0164", \ + "18.9747, 16.8049, 15.3221, 14.2446, 12.1766, 10.9459", \ + "18.4671, 16.3828, 14.9255, 13.8986, 11.9096, 10.7392", \ + "17.4887, 15.489, 14.1395, 13.1812, 11.3389, 10.2719" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.0940077, 0.0940042, 0.094008, 0.0940058, 0.094008, 0.0940046", \ + "0.102241, 0.102239, 0.102246, 0.10224, 0.102244, 0.102237", \ + "0.118722, 0.118725, 0.118724, 0.11872, 0.118731, 0.118721", \ + "0.167163, 0.167165, 0.167165, 0.167162, 0.167167, 0.167161", \ + "0.273728, 0.273731, 0.273731, 0.273732, 0.273731, 0.273725", \ + "0.497514, 0.497524, 0.497443, 0.497449, 0.497445, 0.497442", \ + "0.942577, 0.942695, 0.944187, 0.944188, 0.944196, 0.94417" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.239024, 0.239022, 0.239024, 0.239018, 0.239017, 0.239018", \ + "0.248758, 0.248761, 0.248759, 0.248756, 0.248756, 0.248747", \ + "0.267495, 0.267497, 0.267499, 0.267494, 0.267495, 0.267487", \ + "0.317621, 0.317624, 0.317625, 0.317624, 0.317622, 0.317611", \ + "0.422531, 0.422539, 0.422532, 0.422539, 0.422528, 0.422521", \ + "0.640885, 0.641186, 0.640803, 0.641188, 0.640726, 0.64117", \ + "1.0812, 1.0812, 1.081, 1.08126, 1.08088, 1.08122" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "7.09714, 7.45838, 7.85812, 8.24656, 9.10984, 10.0611", \ + "7.11187, 7.4664, 7.8547, 8.23165, 9.04698, 9.97265", \ + "7.10614, 7.51334, 7.85012, 8.12333, 9.06538, 9.99587", \ + "7.10855, 7.50987, 7.85686, 8.23543, 9.08215, 10.0433", \ + "7.11197, 7.51566, 7.77676, 8.07786, 9.08226, 10.0857", \ + "7.09436, 7.48077, 7.74353, 8.21869, 9.07585, 10.0876", \ + "7.13288, 7.52297, 7.90452, 8.23439, 9.09961, 9.95796" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.98171, 2.98345, 2.9819, 2.98302, 2.97999, 2.98095", \ + "2.98271, 2.98397, 2.98334, 2.9841, 2.98305, 2.98347", \ + "2.9823, 2.9832, 2.98191, 2.98297, 2.97981, 2.98109", \ + "2.98339, 2.98637, 2.98461, 2.98509, 2.98047, 2.98219", \ + "2.98087, 2.98231, 2.98249, 2.98299, 2.97954, 2.98095", \ + "2.98227, 2.98193, 2.98473, 2.98606, 2.98235, 2.98262", \ + "2.98367, 2.98685, 2.98756, 2.98531, 2.97879, 2.97984" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.039636, 0.039638, 0.0396456, 0.039648, 0.0396465, 0.0396397", \ + "0.0536612, 0.0536641, 0.0536712, 0.0536731, 0.0536693, 0.053667", \ + "0.0735373, 0.0735428, 0.0735473, 0.0735431, 0.0735458, 0.0735433", \ + "0.127143, 0.127147, 0.127153, 0.127155, 0.127154, 0.127147", \ + "0.236075, 0.236081, 0.23608, 0.236081, 0.236086, 0.236083", \ + "0.465486, 0.465412, 0.465411, 0.465416, 0.465413, 0.465407", \ + "0.910554, 0.910646, 0.91069, 0.910787, 0.910697, 0.910792" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.0714824, 0.0714786, 0.0714843, 0.0714732, 0.0714741, 0.0714694", \ + "0.0792813, 0.0792774, 0.0792823, 0.0792787, 0.0792742, 0.0792689", \ + "0.0899897, 0.0899851, 0.0899907, 0.0899799, 0.0899808, 0.0899756", \ + "0.118602, 0.118593, 0.118599, 0.118594, 0.118592, 0.118593", \ + "0.177008, 0.176958, 0.176952, 0.176966, 0.176951, 0.176943", \ + "0.299091, 0.299149, 0.299059, 0.299012, 0.299172, 0.298944", \ + "0.544353, 0.544423, 0.544538, 0.544565, 0.5448, 0.544874" \ + ); + } + } + } + pin (c2p) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.016; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0311375; + rise_capacitance : 0.0314761; + rise_capacitance_range (0.0247745, 0.0374792); + fall_capacitance : 0.030799; + fall_capacitance_range (0.025523, 0.0325351); + internal_power () { + when : "!c2p_en"; + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "5.16164e-05, 6.98342e-05, 7.399e-05, 8.03321e-05, 8.7444e-05, 9.06281e-05, 9.14924e-05" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-5.16164e-05, -6.98342e-05, -7.399e-05, -8.03321e-05, -8.7444e-05, -9.06281e-05, -9.14924e-05" \ + ); + } + } + internal_power () { + when : "!c2p_en"; + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0347575, -0.0360391, -0.0363823, -0.0365755, -0.0367439, -0.0369023, -0.036963" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0430085, 0.0426212, 0.04232, 0.042071, 0.0417322, 0.0422942, 0.041893" \ + ); + } + } + internal_power () { + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "5.16164e-05, 6.98342e-05, 7.399e-05, 8.03321e-05, 8.7444e-05, 9.06281e-05, 9.14924e-05" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-5.16164e-05, -6.98342e-05, -7.399e-05, -8.03321e-05, -8.7444e-05, -9.06281e-05, -9.14924e-05" \ + ); + } + } + internal_power () { + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0347575, -0.0360391, -0.0363823, -0.0365755, -0.0367439, -0.0369023, -0.036963" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0430085, 0.0426212, 0.04232, 0.042071, 0.0417322, 0.0422942, 0.041893" \ + ); + } + } + } + pin (c2p_en) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.011; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.028895; + rise_capacitance : 0.0300448; + rise_capacitance_range (0.0247594, 0.037547); + fall_capacitance : 0.0277453; + fall_capacitance_range (0.0238186, 0.0324167); + } + } + cell (sg13g2_IOPadTriOut30mA) { + pad_cell : true; + area : 14400; + cell_footprint : "tri_out"; + pad_drivers : 1; + bond_pads : 1; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 349.682; + when : "!c2p_en&!c2p"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 11899.4; + when : "!c2p_en&!c2p"; + related_pg_pin : vdd; + } + leakage_power () { + value : 349.682; + when : "!c2p_en&c2p"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 18955.4; + when : "!c2p_en&c2p"; + related_pg_pin : vdd; + } + leakage_power () { + value : 540.674; + when : "c2p_en&c2p&pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 19895.1; + when : "c2p_en&c2p&pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 2144.88; + when : "c2p_en&!c2p&!pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 13565.7; + when : "c2p_en&!c2p&!pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 846.231; + related_pg_pin : iovdd; + } + leakage_power () { + value : 16078.9; + related_pg_pin : vdd; + } + pin (pad) { + direction : "output"; + is_pad : true; + function : "c2p"; + three_state : "c2p_en'"; + drive_current : 30; + output_voltage : "pad"; + related_ground_pin : iovss; + related_power_pin : iovdd; + max_capacitance : 10.0496; + capacitance : 0.320954; + rise_capacitance : 0.320969; + rise_capacitance_range (0.320969, 0.320969); + fall_capacitance : 0.32094; + fall_capacitance_range (0.32094, 0.32094); + timing () { + related_pin : "c2p"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.21488, 1.31803, 1.40306, 1.47637, 1.66223, 1.81975", \ + "1.22363, 1.32627, 1.41131, 1.48471, 1.67025, 1.82837", \ + "1.22799, 1.33072, 1.41552, 1.48911, 1.67464, 1.83276", \ + "1.23288, 1.33569, 1.4201, 1.49434, 1.67943, 1.83896", \ + "1.2367, 1.33978, 1.42431, 1.49828, 1.68347, 1.84322", \ + "1.23671, 1.33979, 1.42452, 1.49863, 1.6843, 1.84394", \ + "1.23672, 1.3398, 1.42453, 1.49864, 1.68431, 1.84395" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.357137, 0.484555, 0.591532, 0.686635, 0.94084, 1.18092", \ + "0.357138, 0.484556, 0.591533, 0.686636, 0.940841, 1.18178", \ + "0.357139, 0.484557, 0.591534, 0.686637, 0.940842, 1.1818", \ + "0.35714, 0.484558, 0.591535, 0.686638, 0.940843, 1.1827", \ + "0.357141, 0.485065, 0.591536, 0.686639, 0.940844, 1.18271", \ + "0.358899, 0.486125, 0.592506, 0.687987, 0.941566, 1.1833", \ + "0.362182, 0.488259, 0.596633, 0.68893, 0.942074, 1.18331" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.920766, 0.98241, 1.03856, 1.0907, 1.23335, 1.36353", \ + "0.936016, 0.997501, 1.05342, 1.10575, 1.24856, 1.37843", \ + "0.948272, 1.00995, 1.066, 1.11695, 1.26071, 1.39091", \ + "0.972901, 1.03447, 1.08911, 1.14271, 1.28578, 1.41538", \ + "1.01232, 1.07398, 1.12974, 1.18208, 1.32456, 1.45477", \ + "1.08225, 1.14419, 1.19986, 1.25174, 1.39517, 1.52446", \ + "1.20031, 1.26231, 1.31837, 1.37083, 1.51408, 1.64288" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.700609, 0.737064, 0.790404, 0.844865, 1.01656, 1.19675", \ + "0.706682, 0.742893, 0.793304, 0.849438, 1.02061, 1.20206", \ + "0.708629, 0.745072, 0.796826, 0.852381, 1.02272, 1.20207", \ + "0.70863, 0.745073, 0.796827, 0.852382, 1.02462, 1.20293", \ + "0.708631, 0.745074, 0.796828, 0.852383, 1.02463, 1.20294", \ + "0.708632, 0.745075, 0.796829, 0.852384, 1.02464, 1.20295", \ + "0.708633, 0.745076, 0.79683, 0.852385, 1.02465, 1.20296" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : negative_unate; + timing_type : three_state_disable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.922217, 0.922218, 0.922219, 0.92222, 0.922221, 0.922222", \ + "0.938636, 0.938637, 0.938638, 0.938639, 0.93864, 0.938641", \ + "0.946974, 0.946975, 0.946976, 0.946977, 0.946978, 0.946979", \ + "0.962706, 0.962707, 0.962708, 0.962709, 0.96271, 0.962711", \ + "0.988714, 0.988715, 0.988716, 0.988717, 0.988718, 0.988719", \ + "1.02715, 1.02716, 1.02717, 1.02718, 1.02719, 1.0272", \ + "1.10375, 1.10376, 1.10377, 1.10378, 1.10379, 1.1038" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.922217, 0.922218, 0.922219, 0.92222, 0.922221, 0.922222", \ + "0.938636, 0.938637, 0.938638, 0.938639, 0.93864, 0.938641", \ + "0.946974, 0.946975, 0.946976, 0.946977, 0.946978, 0.946979", \ + "0.962706, 0.962707, 0.962708, 0.962709, 0.96271, 0.962711", \ + "0.988714, 0.988715, 0.988716, 0.988717, 0.988718, 0.988719", \ + "1.02715, 1.02716, 1.02717, 1.02718, 1.02719, 1.0272", \ + "1.10375, 1.10376, 1.10377, 1.10378, 1.10379, 1.1038" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.16216, 1.16217, 1.16218, 1.16219, 1.1622, 1.16221", \ + "1.17831, 1.17832, 1.17833, 1.17834, 1.17835, 1.17836", \ + "1.18945, 1.18946, 1.18947, 1.18948, 1.18949, 1.1895", \ + "1.21178, 1.21179, 1.2118, 1.21181, 1.21182, 1.21183", \ + "1.23054, 1.23055, 1.23056, 1.23057, 1.23058, 1.23059", \ + "1.30108, 1.30109, 1.3011, 1.30111, 1.30112, 1.30113", \ + "1.39358, 1.39359, 1.3936, 1.39361, 1.39362, 1.39363" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.16216, 1.16217, 1.16218, 1.16219, 1.1622, 1.16221", \ + "1.17831, 1.17832, 1.17833, 1.17834, 1.17835, 1.17836", \ + "1.18945, 1.18946, 1.18947, 1.18948, 1.18949, 1.1895", \ + "1.21178, 1.21179, 1.2118, 1.21181, 1.21182, 1.21183", \ + "1.23054, 1.23055, 1.23056, 1.23057, 1.23058, 1.23059", \ + "1.30108, 1.30109, 1.3011, 1.30111, 1.30112, 1.30113", \ + "1.39358, 1.39359, 1.3936, 1.39361, 1.39362, 1.39363" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : positive_unate; + timing_type : three_state_enable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.17694, 1.29767, 1.39102, 1.47101, 1.66838, 1.83418", \ + "1.18686, 1.3076, 1.40115, 1.48127, 1.67832, 1.84411", \ + "1.1934, 1.31404, 1.40797, 1.48706, 1.68455, 1.84894", \ + "1.20442, 1.32513, 1.41901, 1.49879, 1.69563, 1.86142", \ + "1.21352, 1.33416, 1.42804, 1.5078, 1.70325, 1.87061", \ + "1.22547, 1.34621, 1.43971, 1.51918, 1.71733, 1.8843", \ + "1.23176, 1.35246, 1.44637, 1.52615, 1.72078, 1.88546" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.394602, 0.504436, 0.598464, 0.686785, 0.930854, 1.16465", \ + "0.394614, 0.50448, 0.599278, 0.687134, 0.930872, 1.16466", \ + "0.394615, 0.504481, 0.599581, 0.687135, 0.930873, 1.16467", \ + "0.394616, 0.504679, 0.599756, 0.687136, 0.930874, 1.16468", \ + "0.394617, 0.50468, 0.599757, 0.687137, 0.930875, 1.16469", \ + "0.394618, 0.504681, 0.599758, 0.687138, 0.931723, 1.16641", \ + "0.394619, 0.505555, 0.599759, 0.687139, 0.931724, 1.16642" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.610853, 0.697379, 0.768108, 0.831551, 0.99764, 1.14672", \ + "0.62042, 0.70675, 0.777279, 0.840813, 1.0054, 1.15644", \ + "0.624478, 0.710785, 0.781839, 0.844372, 1.00981, 1.16057", \ + "0.630303, 0.716619, 0.787779, 0.850906, 1.01619, 1.16681", \ + "0.634563, 0.720626, 0.792019, 0.855193, 1.0213, 1.17014", \ + "0.634564, 0.720627, 0.79202, 0.855194, 1.02131, 1.17015", \ + "0.634565, 0.720628, 0.792021, 0.855195, 1.02132, 1.17016" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.257487, 0.345438, 0.425453, 0.502153, 0.725453, 0.945553", \ + "0.257613, 0.345439, 0.425454, 0.502154, 0.725454, 0.946386", \ + "0.257614, 0.34544, 0.425719, 0.502155, 0.725455, 0.946577", \ + "0.257615, 0.345441, 0.42572, 0.502156, 0.725456, 0.946591", \ + "0.258199, 0.345731, 0.426064, 0.50246, 0.725646, 0.946592", \ + "0.2582, 0.345732, 0.426065, 0.502461, 0.725647, 0.946593", \ + "0.258201, 0.345733, 0.426066, 0.502462, 0.725648, 0.94968" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "13.127, 12.7412, 12.5766, 12.3992, 12.0709, 11.8974", \ + "13.163, 12.752, 12.6053, 12.442, 12.0815, 12.0528", \ + "13.1711, 12.7795, 12.6191, 12.4822, 12.0993, 12.0577", \ + "13.1632, 12.77, 12.5606, 12.4926, 12.0762, 12.1566", \ + "13.1242, 12.7714, 12.537, 12.3663, 12.0356, 12.1441", \ + "12.9859, 12.6156, 12.4577, 12.3696, 11.9857, 12.1025", \ + "12.8399, 12.4472, 12.4159, 12.1798, 11.871, 11.7384" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "73.1369, 68.8957, 65.3146, 62.2054, 54.9321, 49.7485", \ + "73.9434, 69.6723, 66.0465, 62.9173, 55.6402, 50.3217", \ + "74.1926, 69.8778, 66.2861, 63.1382, 55.7873, 50.532", \ + "74.1165, 69.8598, 66.2082, 63.0951, 55.7618, 50.4669", \ + "73.8108, 69.5107, 65.9289, 62.8068, 55.4548, 50.2314", \ + "72.6612, 68.4369, 64.8469, 61.7968, 54.5566, 49.4739", \ + "70.3615, 66.24, 62.7295, 59.7313, 52.7087, 47.6767" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.093996, 0.0939958, 0.0939969, 0.093993, 0.0939923, 0.0939933", \ + "0.102229, 0.10223, 0.10223, 0.102233, 0.102226, 0.102227", \ + "0.118713, 0.118713, 0.118708, 0.11871, 0.11871, 0.118712", \ + "0.167161, 0.167159, 0.167159, 0.167161, 0.167161, 0.167162", \ + "0.273719, 0.273716, 0.273718, 0.273722, 0.273718, 0.273719", \ + "0.498055, 0.498052, 0.498048, 0.498054, 0.498038, 0.498038", \ + "0.942995, 0.943052, 0.944482, 0.944506, 0.94454, 0.944606" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.238875, 0.238875, 0.238874, 0.238874, 0.238874, 0.23887", \ + "0.248673, 0.248672, 0.248667, 0.248669, 0.24867, 0.24867", \ + "0.267443, 0.267442, 0.267439, 0.267437, 0.267439, 0.267437", \ + "0.317579, 0.317581, 0.317576, 0.317576, 0.317581, 0.317577", \ + "0.422443, 0.42244, 0.422443, 0.422437, 0.422438, 0.422438", \ + "0.640986, 0.641292, 0.641164, 0.640883, 0.641109, 0.64114", \ + "1.08112, 1.08103, 1.08116, 1.08132, 1.08109, 1.08129" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "11.012, 11.3376, 11.6274, 12.0936, 13.305, 14.2954", \ + "11.0036, 11.3291, 11.6951, 12.1062, 13.2965, 14.2852", \ + "11.0133, 11.3372, 11.7278, 12.0698, 13.2902, 14.153", \ + "11.0159, 11.3375, 11.728, 12.1174, 13.2903, 14.2838", \ + "11.0145, 11.3393, 11.7269, 12.1147, 13.1606, 14.2986", \ + "11.0014, 11.3307, 11.6958, 12.0651, 13.3031, 14.3779", \ + "11.0322, 11.3682, 11.7194, 11.9928, 12.8736, 13.8561" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "4.98095, 4.9839, 4.98574, 4.98882, 4.99021, 4.99364", \ + "4.98002, 4.98193, 4.98321, 4.98628, 4.98806, 4.98578", \ + "4.97998, 4.9817, 4.98482, 4.988, 4.98783, 4.9861", \ + "4.98017, 4.98222, 4.98572, 4.9876, 4.9886, 4.98833", \ + "4.97729, 4.97915, 4.98391, 4.98596, 4.98778, 4.99222", \ + "4.97938, 4.98233, 4.9841, 4.98502, 4.98981, 4.98741", \ + "4.99126, 4.98855, 4.993, 4.99554, 4.99285, 4.98929" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.0396243, 0.0396229, 0.0396234, 0.0396244, 0.0396276, 0.039631", \ + "0.0536504, 0.05365, 0.0536501, 0.0536516, 0.0536547, 0.053658", \ + "0.0735251, 0.0735244, 0.0735253, 0.0735258, 0.0735296, 0.0735311", \ + "0.127128, 0.127128, 0.127128, 0.12713, 0.127133, 0.127136", \ + "0.235752, 0.235751, 0.235752, 0.235753, 0.235755, 0.235759", \ + "0.46382, 0.463818, 0.463818, 0.463818, 0.463822, 0.463826", \ + "0.909551, 0.909597, 0.909652, 0.909688, 0.90958, 0.909557" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.0714164, 0.0714203, 0.0714198, 0.0714165, 0.0714193, 0.0714106", \ + "0.0791473, 0.0791495, 0.0791496, 0.079147, 0.079147, 0.0791442", \ + "0.0898746, 0.0898725, 0.089878, 0.0898739, 0.0898698, 0.0898714", \ + "0.118534, 0.118537, 0.118538, 0.118534, 0.118532, 0.11853", \ + "0.176697, 0.176708, 0.176703, 0.176707, 0.176705, 0.176687", \ + "0.298374, 0.298383, 0.298409, 0.29842, 0.2982, 0.298306", \ + "0.543756, 0.543806, 0.543952, 0.543969, 0.544013, 0.544112" \ + ); + } + } + } + pin (c2p) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.016; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0311373; + rise_capacitance : 0.0314763; + rise_capacitance_range (0.0247749, 0.0374796); + fall_capacitance : 0.0307983; + fall_capacitance_range (0.0255232, 0.0325333); + internal_power () { + when : "!c2p_en"; + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.000172062, 0.0001875, 0.000192727, 0.000200812, 0.000209253, 0.000213107, 0.000214309" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-3.68012e-05, -4.04648e-05, -4.94974e-05, -6.35698e-05, -6.56173e-05, -6.50405e-05, -6.47275e-05" \ + ); + } + } + internal_power () { + when : "!c2p_en"; + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0347575, -0.0360474, -0.0363822, -0.0365754, -0.0367438, -0.0369021, -0.036963" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.043018, 0.0425123, 0.0426688, 0.0421789, 0.0424553, 0.0423033, 0.042188" \ + ); + } + } + internal_power () { + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.000172062, 0.0001875, 0.000192727, 0.000200812, 0.000209253, 0.000213107, 0.000214309" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-3.68012e-05, -4.04648e-05, -4.94974e-05, -6.35698e-05, -6.56173e-05, -6.50405e-05, -6.47275e-05" \ + ); + } + } + internal_power () { + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0347575, -0.0360474, -0.0363822, -0.0365754, -0.0367438, -0.0369021, -0.036963" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.043018, 0.0425123, 0.0426688, 0.0421789, 0.0424553, 0.0423033, 0.042188" \ + ); + } + } + } + pin (c2p_en) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.011; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0289015; + rise_capacitance : 0.0300576; + rise_capacitance_range (0.0247595, 0.0376008); + fall_capacitance : 0.0277453; + fall_capacitance_range (0.0238177, 0.0324078); + } + } + cell (sg13g2_IOPadTriOut4mA) { + pad_cell : true; + area : 14400; + cell_footprint : "tri_out"; + pad_drivers : 1; + bond_pads : 1; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 37.1844; + when : "!c2p_en&!c2p"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 11899.3; + when : "!c2p_en&!c2p"; + related_pg_pin : vdd; + } + leakage_power () { + value : 37.1844; + when : "!c2p_en&c2p"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 18955.2; + when : "!c2p_en&c2p"; + related_pg_pin : vdd; + } + leakage_power () { + value : 118.253; + when : "c2p_en&c2p&pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 19894.9; + when : "c2p_en&c2p&pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 288.414; + when : "c2p_en&!c2p&!pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 13565.2; + when : "c2p_en&!c2p&!pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 120.259; + related_pg_pin : iovdd; + } + leakage_power () { + value : 16078.7; + related_pg_pin : vdd; + } + pin (pad) { + direction : "output"; + is_pad : true; + function : "c2p"; + three_state : "c2p_en'"; + drive_current : 4; + output_voltage : "pad"; + related_ground_pin : iovss; + related_power_pin : iovdd; + max_capacitance : 1.6893; + capacitance : 0.160427; + rise_capacitance : 0.164378; + rise_capacitance_range (0.164378, 0.164378); + fall_capacitance : 0.156476; + fall_capacitance_range (0.156476, 0.156476); + timing () { + related_pin : "c2p"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.01868, 1.32281, 1.6251, 1.92732, 2.83085, 3.73376", \ + "1.02671, 1.33056, 1.6331, 1.93516, 2.83845, 3.74132", \ + "1.03071, 1.33472, 1.63722, 1.93928, 2.84258, 3.74547", \ + "1.03639, 1.34045, 1.64295, 1.94488, 2.84829, 3.75139", \ + "1.04203, 1.34628, 1.64851, 1.95066, 2.85414, 3.75734", \ + "1.04204, 1.34629, 1.64852, 1.95067, 2.85415, 3.75735", \ + "1.04205, 1.3463, 1.64853, 1.95068, 2.85416, 3.75736" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.772643, 1.39277, 2.0198, 2.64857, 4.54029, 6.43136", \ + "0.772644, 1.39278, 2.01981, 2.64858, 4.5403, 6.43137", \ + "0.772645, 1.39279, 2.01982, 2.64859, 4.54031, 6.43138", \ + "0.772646, 1.39304, 2.01983, 2.6486, 4.54032, 6.43139", \ + "0.772647, 1.39305, 2.01984, 2.64861, 4.54033, 6.4314", \ + "0.772748, 1.39306, 2.01985, 2.64862, 4.54034, 6.43141", \ + "0.772783, 1.39307, 2.01986, 2.64863, 4.54035, 6.43142" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.735753, 1.04322, 1.35018, 1.65693, 2.57759, 3.49802", \ + "0.748707, 1.05593, 1.36273, 1.66951, 2.59016, 3.51046", \ + "0.760552, 1.06771, 1.37438, 1.68107, 2.60122, 3.52147", \ + "0.785405, 1.0925, 1.3993, 1.70597, 2.62611, 3.54693", \ + "0.825561, 1.13265, 1.43938, 1.74618, 2.66684, 3.58713", \ + "0.899401, 1.20702, 1.51401, 1.82123, 2.74122, 3.66141", \ + "1.02501, 1.33375, 1.64111, 1.948, 2.86864, 3.7887" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.706873, 1.29072, 1.87864, 2.46931, 4.23888, 6.00877", \ + "0.706983, 1.29143, 1.87899, 2.46933, 4.23889, 6.00878", \ + "0.707517, 1.29144, 1.879, 2.46934, 4.2389, 6.00879", \ + "0.707518, 1.29145, 1.87901, 2.46935, 4.23891, 6.0088", \ + "0.707519, 1.29145, 1.87902, 2.46936, 4.23892, 6.00881", \ + "0.70752, 1.29146, 1.87903, 2.46937, 4.24019, 6.01151", \ + "0.707521, 1.29147, 1.87969, 2.46938, 4.2402, 6.01152" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : negative_unate; + timing_type : three_state_disable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.605008, 0.605009, 0.60501, 0.605011, 0.605012, 0.605013", \ + "0.619158, 0.619159, 0.61916, 0.619161, 0.619162, 0.619163", \ + "0.629322, 0.629323, 0.629324, 0.629325, 0.629326, 0.629327", \ + "0.645229, 0.64523, 0.645231, 0.645232, 0.645233, 0.645234", \ + "0.669644, 0.669645, 0.669646, 0.669647, 0.669648, 0.669649", \ + "0.711127, 0.711128, 0.711129, 0.71113, 0.711131, 0.711132", \ + "0.78349, 0.783491, 0.783492, 0.783493, 0.783494, 0.783495" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.605008, 0.605009, 0.60501, 0.605011, 0.605012, 0.605013", \ + "0.619158, 0.619159, 0.61916, 0.619161, 0.619162, 0.619163", \ + "0.629322, 0.629323, 0.629324, 0.629325, 0.629326, 0.629327", \ + "0.645229, 0.64523, 0.645231, 0.645232, 0.645233, 0.645234", \ + "0.669644, 0.669645, 0.669646, 0.669647, 0.669648, 0.669649", \ + "0.711127, 0.711128, 0.711129, 0.71113, 0.711131, 0.711132", \ + "0.78349, 0.783491, 0.783492, 0.783493, 0.783494, 0.783495" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.357051, 0.357052, 0.357053, 0.357054, 0.357055, 0.357056", \ + "0.37545, 0.375451, 0.375452, 0.375453, 0.375454, 0.375455", \ + "0.388304, 0.388305, 0.388306, 0.388307, 0.388308, 0.388309", \ + "0.41107, 0.411071, 0.411072, 0.411073, 0.411074, 0.411075", \ + "0.445159, 0.44516, 0.445161, 0.445162, 0.445163, 0.445164", \ + "0.501867, 0.501868, 0.501869, 0.50187, 0.501871, 0.501872", \ + "0.590123, 0.590124, 0.590125, 0.590126, 0.590127, 0.590128" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.357051, 0.357052, 0.357053, 0.357054, 0.357055, 0.357056", \ + "0.37545, 0.375451, 0.375452, 0.375453, 0.375454, 0.375455", \ + "0.388304, 0.388305, 0.388306, 0.388307, 0.388308, 0.388309", \ + "0.41107, 0.411071, 0.411072, 0.411073, 0.411074, 0.411075", \ + "0.445159, 0.44516, 0.445161, 0.445162, 0.445163, 0.445164", \ + "0.501867, 0.501868, 0.501869, 0.50187, 0.501871, 0.501872", \ + "0.590123, 0.590124, 0.590125, 0.590126, 0.590127, 0.590128" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : positive_unate; + timing_type : three_state_enable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.02112, 1.33744, 1.65258, 1.96618, 2.90593, 3.8463", \ + "1.03071, 1.34705, 1.66216, 1.97555, 2.91558, 3.85599", \ + "1.03746, 1.35371, 1.66883, 1.98218, 2.92219, 3.86149", \ + "1.04773, 1.36421, 1.67886, 1.99234, 2.93297, 3.87332", \ + "1.06053, 1.37686, 1.69119, 2.00484, 2.94471, 3.88528", \ + "1.06774, 1.38394, 1.69931, 2.01284, 2.9522, 3.89261", \ + "1.0752, 1.39146, 1.70619, 2.01946, 2.95948, 3.89879" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.770927, 1.39193, 2.01937, 2.64912, 4.54042, 6.42849", \ + "0.771079, 1.39194, 2.0195, 2.64913, 4.54043, 6.4285", \ + "0.77108, 1.39195, 2.01962, 2.64914, 4.54044, 6.4315", \ + "0.771081, 1.39203, 2.01973, 2.64924, 4.54045, 6.43151", \ + "0.771082, 1.39204, 2.01974, 2.64925, 4.54046, 6.43152", \ + "0.771083, 1.39253, 2.01975, 2.64926, 4.54047, 6.43153", \ + "0.77132, 1.39254, 2.01984, 2.64955, 4.54048, 6.43154" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.75064, 1.09192, 1.43206, 1.77212, 2.79041, 3.80887", \ + "0.760436, 1.10171, 1.44208, 1.78177, 2.80022, 3.8184", \ + "0.7648, 1.10608, 1.44622, 1.78593, 2.80457, 3.82275", \ + "0.770902, 1.11217, 1.45254, 1.79201, 2.81069, 3.82887", \ + "0.775475, 1.11654, 1.45668, 1.79674, 2.8151, 3.83328", \ + "0.775476, 1.11655, 1.45669, 1.79675, 2.81511, 3.83329", \ + "0.775477, 1.11656, 1.4567, 1.79676, 2.81512, 3.8333" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.701826, 1.28845, 1.8786, 2.46831, 4.23778, 6.01167", \ + "0.701827, 1.28846, 1.87861, 2.46894, 4.23779, 6.01168", \ + "0.701828, 1.28847, 1.87862, 2.46895, 4.2378, 6.01169", \ + "0.701829, 1.28848, 1.87863, 2.46896, 4.23781, 6.0117", \ + "0.701843, 1.28913, 1.87864, 2.46897, 4.23782, 6.01171", \ + "0.702238, 1.28914, 1.87865, 2.46898, 4.24046, 6.01172", \ + "0.702239, 1.28915, 1.87866, 2.46899, 4.24047, 6.01173" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "3.82991, 3.79444, 3.75581, 3.71812, 3.63107, 3.51637", \ + "3.83078, 3.79428, 3.76333, 3.72427, 3.62855, 3.52051", \ + "3.82941, 3.795, 3.75854, 3.72262, 3.62772, 3.49524", \ + "3.82159, 3.78752, 3.74936, 3.70732, 3.62286, 3.47368", \ + "3.82236, 3.79349, 3.75703, 3.7102, 3.63128, 3.4938", \ + "3.80742, 3.7693, 3.73223, 3.70102, 3.61498, 3.50233", \ + "3.81884, 3.7764, 3.75851, 3.7098, 3.60547, 3.46864" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.24806, 2.21895, 2.20673, 2.20137, 2.1908, 2.18581", \ + "2.26793, 2.23177, 2.21652, 2.20901, 2.19358, 2.18797", \ + "2.27246, 2.23678, 2.2184, 2.20901, 2.19434, 2.18962", \ + "2.27751, 2.23901, 2.22354, 2.2146, 2.1987, 2.19263", \ + "2.27129, 2.23593, 2.2217, 2.21444, 2.1994, 2.19387", \ + "2.2558, 2.2313, 2.21923, 2.2149, 2.2046, 2.20315", \ + "2.22851, 2.22206, 2.22033, 2.21802, 2.21653, 2.21555" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.0940494, 0.0940428, 0.0940353, 0.0940411, 0.0940447, 0.0940452", \ + "0.102292, 0.102279, 0.102276, 0.102278, 0.10228, 0.102276", \ + "0.118638, 0.11863, 0.118628, 0.118629, 0.118631, 0.118628", \ + "0.167219, 0.167208, 0.167207, 0.167202, 0.167205, 0.167209", \ + "0.27378, 0.273769, 0.273759, 0.273769, 0.273766, 0.273768", \ + "0.497481, 0.497391, 0.497403, 0.497474, 0.497468, 0.497479", \ + "0.942623, 0.942688, 0.94254, 0.94265, 0.942572, 0.942684" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.239153, 0.23915, 0.239146, 0.239161, 0.239152, 0.239155", \ + "0.248978, 0.248963, 0.248963, 0.248971, 0.248965, 0.248967", \ + "0.267737, 0.267735, 0.267735, 0.267733, 0.267729, 0.267733", \ + "0.317883, 0.317868, 0.317863, 0.317876, 0.31787, 0.317871", \ + "0.422836, 0.422838, 0.422833, 0.422838, 0.422828, 0.422829", \ + "0.641373, 0.641164, 0.641203, 0.640967, 0.641024, 0.641399", \ + "1.08094, 1.08129, 1.08131, 1.08139, 1.08123, 1.08155" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "3.63393, 3.86771, 4.11296, 4.34664, 5.063, 5.74708", \ + "3.61212, 3.83887, 4.08679, 4.31921, 5.04036, 5.72602", \ + "3.62877, 3.86121, 4.10566, 4.33642, 5.05735, 5.76367", \ + "3.62105, 3.85682, 4.10123, 4.33001, 5.06124, 5.74564", \ + "3.63789, 3.87928, 4.10753, 4.33973, 5.04731, 5.75021", \ + "3.59877, 3.82717, 4.06886, 4.30531, 5.02027, 5.70118", \ + "3.63146, 3.86792, 4.09925, 4.33573, 5.04547, 5.70751" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.26066, 1.25895, 1.25913, 1.25919, 1.25791, 1.25751", \ + "1.25979, 1.25846, 1.25837, 1.25708, 1.25612, 1.2562", \ + "1.26035, 1.25866, 1.25879, 1.25824, 1.25759, 1.25714", \ + "1.26143, 1.26017, 1.26005, 1.25877, 1.25781, 1.25788", \ + "1.2609, 1.26361, 1.26343, 1.26168, 1.26037, 1.26032", \ + "1.2608, 1.25972, 1.25946, 1.25786, 1.25755, 1.25748", \ + "1.26234, 1.26008, 1.2603, 1.25967, 1.25911, 1.25865" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.0396914, 0.0396806, 0.0396844, 0.0396862, 0.0396867, 0.0396858", \ + "0.0537111, 0.0537054, 0.0537039, 0.0537049, 0.0537063, 0.0537071", \ + "0.0735935, 0.073582, 0.073585, 0.0735868, 0.0735874, 0.073588", \ + "0.127193, 0.127181, 0.127185, 0.127184, 0.127191, 0.127189", \ + "0.235328, 0.235322, 0.235311, 0.235311, 0.235325, 0.235321", \ + "0.462086, 0.462067, 0.462076, 0.462143, 0.46207, 0.462068", \ + "0.921214, 0.921224, 0.921083, 0.921077, 0.921084, 0.921042" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.0717391, 0.0717404, 0.071747, 0.0717473, 0.0717466, 0.0717456", \ + "0.0795236, 0.0795242, 0.0795307, 0.0795322, 0.0795279, 0.0795266", \ + "0.0902563, 0.0902577, 0.0902643, 0.0902625, 0.0902635, 0.0902608", \ + "0.118834, 0.118834, 0.118841, 0.118842, 0.118836, 0.118835", \ + "0.176518, 0.176397, 0.176406, 0.176405, 0.176397, 0.176396", \ + "0.300064, 0.300083, 0.3, 0.300093, 0.300078, 0.300081", \ + "0.550609, 0.550998, 0.550804, 0.550896, 0.550775, 0.550534" \ + ); + } + } + } + pin (c2p) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.016; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0311377; + rise_capacitance : 0.0314763; + rise_capacitance_range (0.0247746, 0.0374785); + fall_capacitance : 0.0307991; + fall_capacitance_range (0.0255227, 0.0325354); + internal_power () { + when : "!c2p_en"; + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0, 0, 0, 0, 4.94431e-06, 7.9244e-06, 8.56027e-06" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0, 0, 0, 0, -4.94431e-06, -7.9244e-06, -8.56027e-06" \ + ); + } + } + internal_power () { + when : "!c2p_en"; + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0347579, -0.0360502, -0.0363822, -0.0365755, -0.0367439, -0.0369023, -0.036963" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0430082, 0.0426501, 0.0423189, 0.0420443, 0.0419276, 0.0422944, 0.0422754" \ + ); + } + } + internal_power () { + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0, 0, 0, 0, 4.94431e-06, 7.9244e-06, 8.56027e-06" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0, 0, 0, 0, -4.94431e-06, -7.9244e-06, -8.56027e-06" \ + ); + } + } + internal_power () { + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0347579, -0.0360502, -0.0363822, -0.0365755, -0.0367439, -0.0369023, -0.036963" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0430082, 0.0426501, 0.0423189, 0.0420443, 0.0419276, 0.0422944, 0.0422754" \ + ); + } + } + } + pin (c2p_en) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.011; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0288912; + rise_capacitance : 0.0300357; + rise_capacitance_range (0.0247606, 0.0373877); + fall_capacitance : 0.0277468; + fall_capacitance_range (0.0238201, 0.0323106); + } + } + cell (sg13g2_IOPadVdd) { + area : 14400; + pad_cell : true; + bond_pads : 1; + dont_touch : true; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + is_pad : true; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 0; + related_pg_pin : iovdd; + } + leakage_power () { + value : 0; + related_pg_pin : vdd; + } + } + cell (sg13g2_IOPadVss) { + area : 14400; + pad_cell : true; + bond_pads : 1; + dont_touch : true; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + is_pad : true; + } + leakage_power () { + value : 0; + related_pg_pin : iovdd; + } + leakage_power () { + value : 1.80055; + related_pg_pin : vdd; + } + } +} diff --git a/flow/platforms/ihp-sg13g2/lib/sg13g2_io_slow_1p08V_3p0V_125C.lib b/flow/platforms/ihp-sg13g2/lib/sg13g2_io_slow_1p08V_3p0V_125C.lib new file mode 100644 index 0000000000..64cb1db0bb --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lib/sg13g2_io_slow_1p08V_3p0V_125C.lib @@ -0,0 +1,4599 @@ +/************************************************************************ + + Copyright 2024 IHP PDK Authors + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + https://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +************************************************************************/ + +library (sg13g2_io_slow_1p08V_3p0V_125C) { + comment : "IHP Microelectronics GmbH, 2024"; + date : "$Date: Wed May 8 12:21:14 2024 $"; + revision : "$Revision: 0.0.1 $"; + delay_model : table_lookup; + capacitive_load_unit (1,pf); + current_unit : "1uA"; + leakage_power_unit : "1pW"; + pulling_resistance_unit : "1kohm"; + time_unit : "1ns"; + voltage_unit : "1V"; + voltage_map (vdd, 1.08); + voltage_map (iovdd, 3); + voltage_map (iovss, 0); + voltage_map (vss, 0); + voltage_map (GND, 0); + define_cell_area (pad_drivers, pad_driver_sites); + define_cell_area (bond_pads, pad_slots); + default_output_pin_cap : 0; + default_inout_pin_cap : 1; + default_input_pin_cap : 1; + default_fanout_load : 1; + default_cell_leakage_power : 0; + default_max_transition : 1.2; + default_leakage_power_density : 0; + default_max_capacitance : 0.3; + default_max_fanout : 8; + default_wire_load_area : 0.29; + default_wire_load_capacitance : 0.0003; + default_wire_load_mode : "enclosed"; + default_wire_load_resistance : 0.0057; + in_place_swap_mode : match_footprint; + input_threshold_pct_fall : 50; + input_threshold_pct_rise : 50; + nom_process : 1; + nom_temperature : 125; + nom_voltage : 1.08; + output_threshold_pct_fall : 50; + output_threshold_pct_rise : 50; + slew_derate_from_library : 1; + slew_lower_threshold_pct_fall : 10; + slew_lower_threshold_pct_rise : 10; + slew_upper_threshold_pct_fall : 90; + slew_upper_threshold_pct_rise : 90; + operating_conditions (sg13g2_io_slow_1p08V_3p0V_125C) { + process : 1; + temperature : 125; + voltage : 1.08; + } + input_voltage (pad) { + vih : 3.3; + vil : 0; + vimax : 3.3; + vimin : 0; + } + input_voltage (core) { + vih : 1.2; + vil : 0; + vimax : 1.2; + vimin : 0; + } + output_voltage (pad) { + voh : 3.3; + vol : 0; + vomax : 3.3; + vomin : 0; + } + output_voltage (core) { + voh : 1.2; + vol : 0; + vomax : 1.2; + vomin : 0; + } + wire_load (Zero) { + area : 0.01; + capacitance : 0.0001; + resistance : 0.0001; + slope : 1; + fanout_length (1, 0.01); + fanout_length (5, 0.01); + fanout_length (20, 0.01); + } + wire_load ("0_1k") { + area : 0.36; + capacitance : 0.0001; + resistance : 0.0035; + slope : 7.387; + fanout_length (1, 6.43); + fanout_length (5, 38.56); + fanout_length (20, 146.8); + } + wire_load ("0_5k") { + area : 0.36; + capacitance : 0.0001; + resistance : 0.0042; + slope : 10.99; + fanout_length (1, 7.89); + fanout_length (5, 47.32); + fanout_length (20, 169.4); + } + wire_load ("1k") { + area : 0.36; + capacitance : 0.0002; + resistance : 0.0053; + slope : 10.9; + fanout_length (1, 9.93); + fanout_length (5, 59.59); + fanout_length (20, 215.6); + } + wire_load ("2k") { + area : 0.36; + capacitance : 0.0002; + resistance : 0.0063; + slope : 16.87; + fanout_length (1, 11.68); + fanout_length (5, 70.11); + fanout_length (20, 239.5); + } + wire_load ("5k") { + area : 0.36; + capacitance : 0.0003; + resistance : 0.0072; + slope : 14.58; + fanout_length (1, 13.44); + fanout_length (5, 80.62); + fanout_length (20, 287.1); + } + wire_load ("10k") { + area : 0.37; + capacitance : 0.0003; + resistance : 0.008; + slope : 18.94; + fanout_length (1, 14.9); + fanout_length (5, 89.39); + fanout_length (20, 381.6); + } + wire_load ("30k") { + area : 0.37; + capacitance : 0.0003; + resistance : 0.0094; + slope : 24.61; + fanout_length (1, 17.53); + fanout_length (5, 105.2); + fanout_length (20, 515.5); + } + wire_load ("50k") { + area : 0.37; + capacitance : 0.0005; + resistance : 0.0152; + slope : 31.81; + fanout_length (1, 28.33); + fanout_length (5, 170); + fanout_length (20, 607.6); + } + wire_load ("100k") { + area : 0.39; + capacitance : 0.0009; + resistance : 0.0265; + slope : 40.22; + fanout_length (1, 49.37); + fanout_length (5, 296.2); + fanout_length (20, 812.1); + } + wire_load ("200k") { + area : 0.41; + capacitance : 0.0016; + resistance : 0.0456; + slope : 52.68; + fanout_length (1, 84.71); + fanout_length (5, 508.3); + fanout_length (20, 1051.7); + } + wire_load ("500k") { + area : 0.45; + capacitance : 0.0027; + resistance : 0.076; + slope : 67.44; + fanout_length (1, 141.4); + fanout_length (5, 848.3); + fanout_length (20, 1527.1); + } + wire_load_selection ("4_metls_routing") { + wire_load_from_area (0, 635, 0_1k); + wire_load_from_area (635, 3175, 0_5k); + wire_load_from_area (3175, 6350, 1k); + wire_load_from_area (6350, 12701, 2k); + wire_load_from_area (12701, 31752, 5k); + wire_load_from_area (31752, 63504, 10k); + wire_load_from_area (63504, 190512, 30k); + wire_load_from_area (190512, 317520, 50k); + wire_load_from_area (317520, 635040, 100k); + wire_load_from_area (635040, 1.27008e+06, 200k); + wire_load_from_area (1.27008e+06, 3.1752e+06, 500k); + } + default_wire_load : "1k"; + default_operating_conditions : sg13g2_io_slow_1p08V_3p0V_125C; + default_wire_load_selection : "4_metls_routing"; + lu_table_template (delay_template_7x6_16) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 3, 7, 9, 12, 15"); + } + power_lut_template (passive_power_template_7x1_16) { + variable_1 : input_transition_time; + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + } + power_lut_template (power_template_7x6_16) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 3, 7, 9, 12, 15"); + } + cell (sg13g2_IOPadIOVdd) { + area : 14400; + pad_cell : true; + bond_pads : 1; + dont_touch : true; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + is_pad : true; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 26693.5; + related_pg_pin : iovdd; + } + leakage_power () { + value : 0; + related_pg_pin : vdd; + } + } + cell (sg13g2_IOPadIOVss) { + area : 14400; + pad_cell : true; + bond_pads : 1; + dont_touch : true; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + is_pad : true; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 0; + related_pg_pin : iovdd; + } + leakage_power () { + value : 1.22704; + related_pg_pin : vdd; + } + } + cell (sg13g2_IOPadIn) { + pad_cell : true; + area : 14400; + cell_footprint : "input"; + pad_drivers : 1; + bond_pads : 1; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 0; + when : "pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 788.379; + when : "pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 0; + when : "!pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 1939.34; + when : "!pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 0; + related_pg_pin : iovdd; + } + leakage_power () { + value : 1363.86; + related_pg_pin : vdd; + } + pin (p2c) { + direction : "output"; + output_voltage : "core"; + function : "pad"; + related_ground_pin : vss; + related_power_pin : vdd; + max_capacitance : 0.511894; + timing () { + related_pin : "pad"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.128437, 0.156341, 0.209301, 0.26138, 0.313254, 0.365086", \ + "0.129921, 0.160277, 0.21527, 0.267605, 0.319621, 0.37152", \ + "0.129922, 0.160278, 0.215271, 0.267606, 0.319622, 0.371521", \ + "0.129923, 0.160279, 0.215272, 0.267607, 0.319623, 0.371522", \ + "0.129924, 0.16028, 0.215273, 0.267608, 0.319624, 0.371523", \ + "0.129925, 0.160281, 0.215274, 0.267609, 0.319625, 0.371524", \ + "0.129926, 0.160282, 0.215275, 0.26761, 0.319626, 0.371525" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0911138, 0.143001, 0.248865, 0.355819, 0.46337, 0.571267", \ + "0.0999905, 0.151349, 0.255684, 0.361392, 0.467915, 0.57451", \ + "0.10577, 0.158143, 0.265081, 0.370243, 0.476096, 0.582889", \ + "0.108195, 0.160115, 0.265944, 0.37306, 0.478736, 0.585597", \ + "0.123053, 0.173733, 0.274489, 0.378895, 0.485283, 0.592526", \ + "0.149693, 0.198494, 0.294069, 0.394742, 0.497169, 0.602121", \ + "0.174458, 0.219473, 0.312041, 0.409583, 0.509136, 0.612736" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.678008, 0.721423, 0.788094, 0.843279, 0.893033, 0.939333", \ + "0.705159, 0.748768, 0.815031, 0.869284, 0.918991, 0.965964", \ + "0.80875, 0.852382, 0.918738, 0.972477, 1.02234, 1.06954", \ + "0.856371, 0.89997, 0.966223, 1.02116, 1.06995, 1.11843", \ + "1.18068, 1.22379, 1.29027, 1.34545, 1.39446, 1.44269", \ + "1.82065, 1.86421, 1.9298, 1.98501, 2.03523, 2.08221", \ + "2.38962, 2.43241, 2.49779, 2.55238, 2.603, 2.64892" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.20776, 0.248023, 0.318782, 0.388945, 0.460265, 0.532073", \ + "0.208018, 0.248024, 0.318783, 0.388946, 0.460266, 0.532447", \ + "0.208019, 0.248025, 0.318818, 0.388947, 0.460267, 0.532448", \ + "0.20802, 0.248026, 0.318819, 0.389062, 0.460268, 0.533031", \ + "0.208021, 0.248027, 0.31882, 0.389063, 0.460269, 0.533032", \ + "0.208022, 0.248028, 0.318821, 0.389064, 0.460561, 0.533033", \ + "0.209537, 0.249985, 0.3218, 0.391184, 0.463249, 0.534278" \ + ); + } + } + internal_power () { + related_pin : "pad"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "6.48615e-09, 6.48635e-09, 6.48586e-09, 6.48589e-09, 6.48539e-09, 6.48601e-09", \ + "1.2568e-08, 1.25683e-08, 1.25686e-08, 1.25681e-08, 1.25688e-08, 1.25678e-08", \ + "2.47336e-08, 2.47325e-08, 2.47332e-08, 2.47334e-08, 2.47321e-08, 2.47329e-08", \ + "3.08162e-08, 3.08168e-08, 3.08161e-08, 3.08154e-08, 3.08163e-08, 3.0817e-08", \ + "6.1233e-08, 6.12329e-08, 6.1233e-08, 6.12332e-08, 6.12316e-08, 6.12327e-08", \ + "1.22061e-07, 1.22063e-07, 1.22064e-07, 1.22067e-07, 1.22069e-07, 1.22067e-07", \ + "1.7782e-07, 1.77831e-07, 1.77823e-07, 1.77827e-07, 1.7783e-07, 1.77829e-07" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "-6.47214e-09, -6.47213e-09, -6.47219e-09, -6.47224e-09, -6.47225e-09, -6.4723e-09", \ + "-1.25473e-08, -1.25473e-08, -1.25473e-08, -1.25474e-08, -1.25474e-08, -1.25475e-08", \ + "-2.46978e-08, -2.46978e-08, -2.46979e-08, -2.46979e-08, -2.4698e-08, -2.4698e-08", \ + "-3.07727e-08, -3.07727e-08, -3.07728e-08, -3.07728e-08, -3.07728e-08, -3.07729e-08", \ + "-6.11476e-08, -6.11476e-08, -6.11477e-08, -6.11477e-08, -6.11477e-08, -6.11477e-08", \ + "-1.21898e-07, -1.21898e-07, -1.21898e-07, -1.21898e-07, -1.21898e-07, -1.21898e-07", \ + "-1.77583e-07, -1.77583e-07, -1.77584e-07, -1.77584e-07, -1.77584e-07, -1.77584e-07" \ + ); + } + } + internal_power () { + related_pin : "pad"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.00074628, 0.0010612, 0.00126846, 0.00101035, 0.000860111, 0.000447451", \ + "0.000343645, 0.000529653, 0.000698435, 0.000632456, 0.000380591, 0.000243655", \ + "-0.000300165, 0.000205459, 0.000223559, 5.23879e-05, -0.000184465, -0.000319889", \ + "-0.000266793, 0.000110009, 0.000292679, 0.000261152, -9.57971e-05, -0.000420977", \ + "-0.00126965, -0.00135154, -0.00125971, -0.000960004, -0.000746821, -0.00111131", \ + "-0.00174019, -0.00143301, -0.00184118, -0.00166416, -0.00222361, -0.00221691", \ + "-0.001408, -0.0014408, -0.00171914, -0.00197661, -0.00299473, -0.00318124" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0428208, 0.0426887, 0.0428407, 0.0430691, 0.0432502, 0.0434055", \ + "0.0416674, 0.0415058, 0.0416367, 0.0418299, 0.0420153, 0.0421414", \ + "0.041024, 0.0408597, 0.0409803, 0.0411418, 0.0413056, 0.041434", \ + "0.0406117, 0.0404405, 0.0405405, 0.0407108, 0.0408462, 0.0409532", \ + "0.0403456, 0.0401975, 0.0403046, 0.0404725, 0.0405976, 0.0407119", \ + "0.039926, 0.0397557, 0.0397974, 0.0399282, 0.040049, 0.0401386", \ + "0.0408194, 0.0405311, 0.0404295, 0.0404332, 0.0404826, 0.0405242" \ + ); + } + } + } + pin (pad) { + direction : "input"; + is_pad : true; + input_voltage : "pad"; + fanout_load : 1; + related_ground_pin : iovss; + related_power_pin : iovdd; + max_transition : 3.5; + capacitance : 0.22094; + rise_capacitance : 0.223351; + rise_capacitance_range (0.194715, 0.244025); + fall_capacitance : 0.218529; + fall_capacitance_range (0.196944, 0.232784); + } + } + cell (sg13g2_IOPadInOut16mA) { + pad_cell : true; + area : 14400; + cell_footprint : "inout"; + pad_drivers : 1; + bond_pads : 1; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 5141.58; + when : "!c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 8044; + when : "!c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 5141.58; + when : "!c2p_en&c2p&!pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 8127.75; + when : "!c2p_en&c2p&!pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 398.079; + when : "!c2p_en&!c2p&pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 6893.14; + when : "!c2p_en&!c2p&pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 398.078; + when : "!c2p_en&c2p&pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 6976.39; + when : "!c2p_en&c2p&pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 550.826; + when : "c2p_en&c2p&pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 10163.1; + when : "c2p_en&c2p&pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 550.826; + when : "c2p_en&c2p&pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 10163.1; + when : "c2p_en&c2p&pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 4990.01; + when : "c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 11192.5; + when : "c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 4990.01; + when : "c2p_en&!c2p&!pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 11192.6; + when : "c2p_en&!c2p&!pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 2770.12; + related_pg_pin : iovdd; + } + leakage_power () { + value : 9094.07; + related_pg_pin : vdd; + } + pin (pad) { + direction : "inout"; + is_pad : true; + function : "c2p"; + three_state : "c2p_en'"; + drive_current : 16; + output_voltage : "pad"; + input_voltage : "pad"; + related_ground_pin : iovss; + related_power_pin : iovdd; + max_capacitance : 2.19096; + capacitance : 0.271577; + rise_capacitance : 0.270244; + rise_capacitance_range (0.240067, 0.292156); + fall_capacitance : 0.272909; + fall_capacitance_range (0.249869, 0.288338); + timing () { + related_pin : "c2p"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.65508, 2.89262, 3.09547, 3.28207, 3.80742, 4.31449", \ + "2.67687, 2.91463, 3.11727, 3.30396, 3.82922, 4.33596", \ + "2.69426, 2.93194, 3.13447, 3.32107, 3.84632, 4.35341", \ + "2.72609, 2.9637, 3.1662, 3.35279, 3.87802, 4.38512", \ + "2.76972, 3.0075, 3.20954, 3.39674, 3.92176, 4.42877", \ + "2.82258, 3.06018, 3.26278, 3.44939, 3.97467, 4.48182", \ + "2.88679, 3.12466, 3.32735, 3.51399, 4.03939, 4.54663" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.783142, 1.11253, 1.43467, 1.75854, 2.74893, 3.76022", \ + "0.783143, 1.1129, 1.43505, 1.75867, 2.74894, 3.76023", \ + "0.783144, 1.11291, 1.43506, 1.75868, 2.74895, 3.76024", \ + "0.783145, 1.11292, 1.43507, 1.75869, 2.74896, 3.76025", \ + "0.783146, 1.11297, 1.43508, 1.7587, 2.74904, 3.76026", \ + "0.783147, 1.11298, 1.43509, 1.75871, 2.7494, 3.76027", \ + "0.783196, 1.11299, 1.4351, 1.75872, 2.74941, 3.76028" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.6727, 2.86286, 3.03466, 3.19742, 3.67559, 4.15509", \ + "2.69451, 2.88504, 3.05681, 3.21931, 3.69771, 4.17752", \ + "2.71347, 2.90342, 3.07509, 3.23782, 3.71662, 4.19444", \ + "2.75418, 2.94403, 3.11555, 3.27821, 3.75625, 4.23417", \ + "2.82493, 3.01457, 3.18609, 3.34861, 3.82575, 4.3052", \ + "2.9395, 3.12946, 3.3016, 3.46374, 3.94119, 4.41951", \ + "3.12026, 3.31032, 3.48251, 3.64469, 4.12245, 4.60124" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.881889, 1.1419, 1.41633, 1.70357, 2.60651, 3.54279", \ + "0.882891, 1.14334, 1.418, 1.70503, 2.60777, 3.54419", \ + "0.886155, 1.14526, 1.41801, 1.7061, 2.60845, 3.54476", \ + "0.889996, 1.14848, 1.41841, 1.70841, 2.60984, 3.54601", \ + "0.894076, 1.15179, 1.42504, 1.71109, 2.61343, 3.5478", \ + "0.894077, 1.1518, 1.42505, 1.7111, 2.61344, 3.54781", \ + "0.894078, 1.15181, 1.42506, 1.71111, 2.61345, 3.54782" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : negative_unate; + timing_type : three_state_disable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.00669, 2.0067, 2.00671, 2.00672, 2.00673, 2.00674", \ + "2.03138, 2.03139, 2.0314, 2.03141, 2.03142, 2.03143", \ + "2.05141, 2.05142, 2.05143, 2.05144, 2.05145, 2.05146", \ + "2.09417, 2.09418, 2.09419, 2.0942, 2.09421, 2.09422", \ + "2.14785, 2.14786, 2.14787, 2.14788, 2.14789, 2.1479", \ + "2.22482, 2.22483, 2.22484, 2.22485, 2.22486, 2.22487", \ + "2.33338, 2.33339, 2.3334, 2.33341, 2.33342, 2.33343" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.00669, 2.0067, 2.00671, 2.00672, 2.00673, 2.00674", \ + "2.03138, 2.03139, 2.0314, 2.03141, 2.03142, 2.03143", \ + "2.05141, 2.05142, 2.05143, 2.05144, 2.05145, 2.05146", \ + "2.09417, 2.09418, 2.09419, 2.0942, 2.09421, 2.09422", \ + "2.14785, 2.14786, 2.14787, 2.14788, 2.14789, 2.1479", \ + "2.22482, 2.22483, 2.22484, 2.22485, 2.22486, 2.22487", \ + "2.33338, 2.33339, 2.3334, 2.33341, 2.33342, 2.33343" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.58314, 2.58315, 2.58316, 2.58317, 2.58318, 2.58319", \ + "2.61157, 2.61158, 2.61159, 2.6116, 2.61161, 2.61162", \ + "2.62009, 2.6201, 2.62011, 2.62012, 2.62013, 2.62014", \ + "2.67273, 2.67551, 2.67552, 2.67553, 2.67554, 2.67555", \ + "2.74272, 2.74273, 2.74274, 2.74275, 2.74276, 2.74277", \ + "2.84409, 2.84415, 2.84417, 2.84418, 2.84419, 2.8442", \ + "3.02033, 3.02034, 3.02035, 3.02036, 3.02037, 3.02038" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.58314, 2.58315, 2.58316, 2.58317, 2.58318, 2.58319", \ + "2.61157, 2.61158, 2.61159, 2.6116, 2.61161, 2.61162", \ + "2.62009, 2.6201, 2.62011, 2.62012, 2.62013, 2.62014", \ + "2.67273, 2.67551, 2.67552, 2.67553, 2.67554, 2.67555", \ + "2.74272, 2.74273, 2.74274, 2.74275, 2.74276, 2.74277", \ + "2.84409, 2.84415, 2.84417, 2.84418, 2.84419, 2.8442", \ + "3.02033, 3.02034, 3.02035, 3.02036, 3.02037, 3.02038" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : positive_unate; + timing_type : three_state_enable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.63805, 2.88141, 3.08782, 3.27914, 3.81598, 4.33344", \ + "2.65528, 2.89839, 3.10445, 3.29582, 3.83246, 4.34962", \ + "2.67209, 2.91538, 3.12186, 3.31316, 3.84997, 4.36746", \ + "2.70357, 2.94811, 3.15451, 3.34425, 3.88271, 4.40011", \ + "2.74628, 2.9892, 3.19441, 3.38623, 3.92266, 4.44005", \ + "2.7992, 3.04245, 3.24894, 3.44024, 3.9771, 4.4945", \ + "2.85887, 3.10159, 3.30847, 3.50192, 4.03572, 4.5561" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.79266, 1.11591, 1.43464, 1.75718, 2.74514, 3.7545", \ + "0.792661, 1.11601, 1.43465, 1.75719, 2.74515, 3.75451", \ + "0.792662, 1.11602, 1.43466, 1.7572, 2.74516, 3.75452", \ + "0.792663, 1.11603, 1.43467, 1.75721, 2.74518, 3.75453", \ + "0.792664, 1.11695, 1.43468, 1.75722, 2.74519, 3.75454", \ + "0.792665, 1.11696, 1.43469, 1.75723, 2.7452, 3.75455", \ + "0.792666, 1.11697, 1.4347, 1.75914, 2.74521, 3.75456" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.43577, 2.65306, 2.84509, 3.02564, 3.54018, 4.04611", \ + "2.45722, 2.67479, 2.867, 3.0465, 3.56268, 4.06812", \ + "2.47395, 2.69125, 2.88222, 3.06384, 3.57838, 4.08425", \ + "2.49848, 2.71605, 2.90823, 3.08768, 3.60392, 4.10929", \ + "2.53466, 2.75224, 2.94392, 3.12389, 3.63967, 4.14507", \ + "2.58036, 2.7979, 2.98958, 3.16967, 3.68564, 4.19096", \ + "2.6269, 2.84424, 3.03619, 3.21694, 3.7317, 4.23734" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.670859, 0.980181, 1.2851, 1.59501, 2.53973, 3.49456", \ + "0.67086, 0.980182, 1.2878, 1.59502, 2.54091, 3.50245", \ + "0.670861, 0.980183, 1.28781, 1.59503, 2.54092, 3.50246", \ + "0.670862, 0.980184, 1.28781, 1.59504, 2.54093, 3.50247", \ + "0.670863, 0.980185, 1.28782, 1.59505, 2.54094, 3.50248", \ + "0.670864, 0.981012, 1.28783, 1.59506, 2.54112, 3.50257", \ + "0.670865, 0.981013, 1.28784, 1.59507, 2.54113, 3.50258" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "5.18851, 5.15879, 5.13426, 5.10999, 5.03817, 4.96731", \ + "5.1911, 5.16087, 5.13933, 5.11146, 5.03664, 4.97148", \ + "5.19129, 5.16203, 5.14149, 5.11146, 5.04333, 4.9518", \ + "5.19246, 5.16279, 5.14089, 5.11074, 5.04234, 4.95423", \ + "5.18781, 5.16013, 5.13123, 5.11035, 5.02854, 4.94901", \ + "5.18693, 5.15856, 5.13636, 5.10711, 5.0424, 4.95489", \ + "5.17435, 5.15213, 5.13225, 5.10399, 5.0238, 4.95138" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "10.094, 8.99074, 8.26721, 7.73843, 6.76473, 6.20294", \ + "10.1323, 9.02716, 8.29953, 7.77082, 6.79572, 6.22564", \ + "10.2017, 9.08439, 8.34417, 7.81393, 6.83893, 6.25027", \ + "10.3019, 9.17202, 8.42299, 7.88423, 6.89306, 6.29666", \ + "10.3986, 9.25581, 8.50253, 7.96062, 6.93862, 6.34138", \ + "10.3631, 9.22281, 8.47151, 7.92971, 6.917, 6.32789", \ + "10.2597, 9.13608, 8.39222, 7.85653, 6.86124, 6.28133" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.19355, 2.35808, 3.51599, 4.66396, 7.94064, 8.69593", \ + "1.19205, 2.35647, 3.51675, 4.66235, 8.0007, 8.62304", \ + "1.19117, 2.35519, 3.49894, 4.66167, 8.06083, 8.59795", \ + "1.19134, 2.35607, 3.51503, 4.66195, 8.05122, 8.49833", \ + "1.1925, 2.34714, 3.50432, 4.66155, 7.96847, 8.37478", \ + "1.19805, 2.35417, 3.52179, 4.66918, 8.00716, 8.21555", \ + "1.2128, 2.36635, 3.53739, 4.68708, 7.85365, 7.66348" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.135404, 0.135209, 0.135049, 0.134889, 0.134542, 0.133287", \ + "0.133462, 0.133258, 0.133108, 0.132945, 0.132579, 0.13131", \ + "0.132807, 0.132627, 0.132463, 0.132309, 0.132087, 0.130458", \ + "0.132943, 0.132763, 0.132596, 0.132444, 0.132092, 0.130503", \ + "0.134569, 0.134377, 0.134225, 0.13405, 0.133715, 0.132232", \ + "0.13959, 0.139393, 0.139225, 0.139076, 0.138749, 0.136801", \ + "0.153993, 0.153822, 0.153654, 0.153494, 0.153129, 0.150759" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "4.81725, 4.8708, 4.9224, 4.98273, 5.217, 5.44155", \ + "4.82416, 4.86467, 4.91985, 4.9851, 5.20572, 5.40123", \ + "4.81662, 4.86952, 4.92099, 4.98246, 5.21595, 5.44116", \ + "4.81851, 4.86981, 4.92192, 4.98003, 5.21856, 5.41344", \ + "4.81614, 4.86175, 4.9083, 4.97352, 5.20332, 5.38602", \ + "4.81768, 4.8691, 4.92372, 4.98315, 5.22189, 5.41725", \ + "4.82131, 4.86565, 4.92351, 5.01024, 5.1999, 5.48673" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.11183, 2.11073, 2.10951, 2.10885, 2.10772, 2.10742", \ + "2.11131, 2.11076, 2.10868, 2.1083, 2.10634, 2.10568", \ + "2.11189, 2.11081, 2.10907, 2.10893, 2.10786, 2.10751", \ + "2.11093, 2.11038, 2.10828, 2.10785, 2.10598, 2.10539", \ + "2.11124, 2.11071, 2.10869, 2.10791, 2.10628, 2.10559", \ + "2.11022, 2.11014, 2.10901, 2.10831, 2.10606, 2.10491", \ + "2.11473, 2.11392, 2.11156, 2.11205, 2.1098, 2.1107" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.17221, 2.33669, 3.4838, 4.64907, 7.98713, 8.65055", \ + "1.16973, 2.3241, 3.4823, 4.65081, 7.98414, 8.6021", \ + "1.16906, 2.32623, 3.48695, 4.64722, 7.97704, 8.57939", \ + "1.17067, 2.33544, 3.49526, 4.65029, 7.96723, 8.45415", \ + "1.17266, 2.33835, 3.4727, 4.65241, 7.9542, 8.43464", \ + "1.18032, 2.33796, 3.49, 4.65881, 7.99328, 8.13764", \ + "1.20022, 2.35655, 3.50177, 4.66336, 7.95109, 7.66202" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.0720004, 0.0716841, 0.0715044, 0.0713806, 0.0708744, 0.0694592", \ + "0.0704751, 0.0702174, 0.0700565, 0.069942, 0.0694183, 0.0679191", \ + "0.0702721, 0.0699573, 0.0697526, 0.0696547, 0.069139, 0.0676199", \ + "0.070355, 0.0700973, 0.0699191, 0.0698015, 0.0692939, 0.0676908", \ + "0.0721436, 0.0718858, 0.0716423, 0.0715203, 0.0709967, 0.0693057", \ + "0.0760181, 0.0757734, 0.0755409, 0.0754133, 0.0749289, 0.0729884", \ + "0.0852793, 0.0849903, 0.0848146, 0.0847032, 0.0841389, 0.0815922" \ + ); + } + } + } + pin (p2c) { + direction : "output"; + output_voltage : "core"; + function : "pad"; + related_ground_pin : vss; + related_power_pin : vdd; + max_capacitance : 0.511993; + timing () { + related_pin : "pad"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.128901, 0.156733, 0.209709, 0.261836, 0.313689, 0.365509", \ + "0.130184, 0.160693, 0.215549, 0.26782, 0.319871, 0.371746", \ + "0.130185, 0.160694, 0.21555, 0.267821, 0.319872, 0.371747", \ + "0.130186, 0.160695, 0.215551, 0.267822, 0.319873, 0.371748", \ + "0.130187, 0.160696, 0.215552, 0.267823, 0.319874, 0.371749", \ + "0.130188, 0.160697, 0.215553, 0.267824, 0.319875, 0.37175", \ + "0.130189, 0.160698, 0.215554, 0.267825, 0.319876, 0.371751" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0911905, 0.143106, 0.248972, 0.355953, 0.463323, 0.571232", \ + "0.10005, 0.151576, 0.255813, 0.361557, 0.467812, 0.574741", \ + "0.105934, 0.158009, 0.265058, 0.370413, 0.476351, 0.582958", \ + "0.108329, 0.16017, 0.26609, 0.373284, 0.479228, 0.585659", \ + "0.123201, 0.173109, 0.274692, 0.37913, 0.485349, 0.592549", \ + "0.150163, 0.197791, 0.294749, 0.394871, 0.497365, 0.60193", \ + "0.174604, 0.219554, 0.312365, 0.408387, 0.509237, 0.612041" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.678208, 0.721776, 0.787694, 0.843008, 0.891933, 0.938931", \ + "0.704973, 0.748608, 0.814864, 0.86944, 0.918439, 0.965957", \ + "0.80293, 0.846025, 0.911613, 0.966986, 1.01685, 1.064", \ + "0.868304, 0.911358, 0.977486, 1.0325, 1.08207, 1.12934", \ + "1.18079, 1.22402, 1.29021, 1.34391, 1.39411, 1.44027", \ + "1.82059, 1.8639, 1.93024, 1.98481, 2.03457, 2.0802", \ + "2.41888, 2.46205, 2.52818, 2.58229, 2.63264, 2.6795" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.207488, 0.247837, 0.317888, 0.387837, 0.458303, 0.530063", \ + "0.207551, 0.247838, 0.317889, 0.38793, 0.458304, 0.531543", \ + "0.207552, 0.247839, 0.318531, 0.388415, 0.459394, 0.531544", \ + "0.207553, 0.24784, 0.318532, 0.388416, 0.459395, 0.531545", \ + "0.207554, 0.247841, 0.318533, 0.388417, 0.459396, 0.531546", \ + "0.207555, 0.247842, 0.318534, 0.388418, 0.459397, 0.531547", \ + "0.208153, 0.247843, 0.318942, 0.388419, 0.459541, 0.531548" \ + ); + } + } + internal_power () { + related_pin : "pad"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "-0.555387, -0.555398, -0.555418, -0.555473, -0.555519, -0.555559", \ + "-0.558364, -0.559777, -0.559198, -0.559937, -0.560671, -0.559918", \ + "-0.559383, -0.558254, -0.557865, -0.559355, -0.556754, -0.557852", \ + "-0.559084, -0.559098, -0.559107, -0.557128, -0.559187, -0.559217", \ + "-0.557978, -0.557972, -0.558001, -0.558025, -0.55806, -0.558088", \ + "-0.557862, -0.557968, -0.557786, -0.558012, -0.558029, -0.558052", \ + "-0.556903, -0.556931, -0.556946, -0.556956, -0.556969, -0.556984" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.555387, 0.555398, 0.555418, 0.555473, 0.555519, 0.555559", \ + "0.560519, 0.560541, 0.560582, 0.560615, 0.560671, 0.560699", \ + "0.559383, 0.559402, 0.559428, 0.559448, 0.559495, 0.559534", \ + "0.559084, 0.559098, 0.559107, 0.559154, 0.559187, 0.559217", \ + "0.557978, 0.557972, 0.558001, 0.558025, 0.55806, 0.558088", \ + "0.557954, 0.557968, 0.557986, 0.558012, 0.558029, 0.558052", \ + "0.556903, 0.556931, 0.556946, 0.556956, 0.556969, 0.556984" \ + ); + } + } + internal_power () { + related_pin : "pad"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.000912967, 0.00121108, 0.00141275, 0.00111824, 0.000903527, 0.000610963", \ + "0.000398995, 0.000664362, 0.000850391, 0.000585692, 0.000303803, 0.000257047", \ + "-0.000219618, 0.000149558, 0.000262763, 0.000168488, -0.000225181, -0.000312113", \ + "-0.000299895, 0.000133455, 0.000322811, 0.000310724, -3.19691e-05, -0.000367625", \ + "-0.00103113, -0.00104673, -0.00117688, -0.0009046, -0.000755137, -0.00107438", \ + "-0.00131707, -0.00107432, -0.00135432, -0.00151566, -0.00213009, -0.0020886", \ + "-0.00102171, -0.00131638, -0.00120744, -0.00249998, -0.00268769, -0.00306384" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0427678, 0.0426472, 0.0427907, 0.0430223, 0.0431998, 0.0433415", \ + "0.0416511, 0.0414992, 0.0416346, 0.0418346, 0.0420143, 0.0421235", \ + "0.0408049, 0.0406513, 0.0407664, 0.0409599, 0.0411117, 0.0412251", \ + "0.0407178, 0.040587, 0.0407056, 0.0408935, 0.0410399, 0.0411566", \ + "0.0402995, 0.0401412, 0.0402513, 0.0404014, 0.0405334, 0.0406621", \ + "0.0398559, 0.0396867, 0.0397535, 0.0398801, 0.0399926, 0.0400892", \ + "0.0398837, 0.0396583, 0.039645, 0.0397187, 0.0398034, 0.0398736" \ + ); + } + } + } + pin (c2p) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.016; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0252022; + rise_capacitance : 0.025323; + rise_capacitance_range (0.0220222, 0.0288318); + fall_capacitance : 0.0250814; + fall_capacitance_range (0.0223271, 0.0272541); + internal_power () { + when : "(!c2p_en * pad * p2c)"; + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-1.02215e-05, 0, 0, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "1.02215e-05, 0, 0, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + when : "(!c2p_en * pad * p2c)"; + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0124555, -0.0129151, -0.0131625, -0.0133357, -0.0133487, -0.0134639, -0.0135316" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0156797, 0.0154411, 0.015492, 0.0153677, 0.0154467, 0.0154114, 0.0153378" \ + ); + } + } + internal_power () { + when : "(!c2p_en * !pad * !p2c)"; + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-1.02002e-05, 0, 0, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "1.02002e-05, 0, 0, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + when : "(!c2p_en * !pad * !p2c)"; + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0124549, -0.0129147, -0.0131622, -0.0133355, -0.0133485, -0.0134638, -0.0135316" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0156792, 0.0154408, 0.0154918, 0.0153675, 0.0154466, 0.0154114, 0.0153378" \ + ); + } + } + internal_power () { + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-1.02002e-05, 0, 0, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "1.02002e-05, 0, 0, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0124549, -0.0129147, -0.0131622, -0.0133355, -0.0133485, -0.0134638, -0.0135316" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0156792, 0.0154408, 0.0154918, 0.0153675, 0.0154466, 0.0154114, 0.0153378" \ + ); + } + } + } + pin (c2p_en) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.011; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0238583; + rise_capacitance : 0.0246362; + rise_capacitance_range (0.0213425, 0.0285532); + fall_capacitance : 0.0230804; + fall_capacitance_range (0.0199991, 0.0261443); + internal_power () { + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "1.43341, 1.43329, 1.43327, 1.43272, 1.4329, 1.43327, 1.43645" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.244515, 0.244863, 0.244183, 0.244202, 0.24406, 0.242962, 0.243059" \ + ); + } + } + internal_power () { + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0300283, 0.0285753, 0.0284124, 0.0284394, 0.0303103, 0.0340618, 0.0433855" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0624462, 0.0616579, 0.0613785, 0.0616813, 0.0632286, 0.0677119, 0.0755756" \ + ); + } + } + } + } + cell (sg13g2_IOPadInOut30mA) { + pad_cell : true; + area : 14400; + cell_footprint : "inout"; + pad_drivers : 1; + bond_pads : 1; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 9164.97; + when : "!c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 8043.7; + when : "!c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 9164.97; + when : "!c2p_en&c2p&!pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 8127.38; + when : "!c2p_en&c2p&!pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 355.716; + when : "!c2p_en&!c2p&pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 6892.9; + when : "!c2p_en&!c2p&pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 355.715; + when : "!c2p_en&c2p&pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 6976.16; + when : "!c2p_en&c2p&pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 511.094; + when : "c2p_en&c2p&pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 10162.8; + when : "c2p_en&c2p&pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 511.094; + when : "c2p_en&c2p&pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 10162.8; + when : "c2p_en&c2p&pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 9013.42; + when : "c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 11192.2; + when : "c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 9013.42; + when : "c2p_en&!c2p&!pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 11192.2; + when : "c2p_en&!c2p&!pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 4761.3; + related_pg_pin : iovdd; + } + leakage_power () { + value : 9093.78; + related_pg_pin : vdd; + } + pin (pad) { + direction : "inout"; + is_pad : true; + function : "c2p"; + three_state : "c2p_en'"; + drive_current : 30; + output_voltage : "pad"; + input_voltage : "pad"; + related_ground_pin : iovss; + related_power_pin : iovdd; + max_capacitance : 0.668662; + capacitance : 0.36632; + rise_capacitance : 0.361502; + rise_capacitance_range (0.329622, 0.385076); + fall_capacitance : 0.371139; + fall_capacitance_range (0.346734, 0.38807); + timing () { + related_pin : "c2p"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.9367, 3.14743, 3.31835, 3.46688, 3.84362, 4.16974", \ + "2.95788, 3.16833, 3.33918, 3.48783, 3.86443, 4.19061", \ + "2.97627, 3.18662, 3.35745, 3.50478, 3.88142, 4.20754", \ + "3.00923, 3.21956, 3.39037, 3.53872, 3.91568, 4.24149", \ + "3.05085, 3.26126, 3.432, 3.58062, 3.95753, 4.28343", \ + "3.10549, 3.31602, 3.48684, 3.63539, 4.01197, 4.33802", \ + "3.16655, 3.37756, 3.54858, 3.69729, 4.07412, 4.40027" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.751558, 0.990952, 1.1959, 1.38537, 1.92014, 2.44219", \ + "0.751559, 0.991043, 1.19607, 1.38568, 1.92015, 2.4422", \ + "0.75156, 0.991044, 1.19608, 1.38569, 1.92016, 2.44221", \ + "0.751561, 0.991045, 1.19609, 1.3857, 1.92017, 2.44222", \ + "0.751562, 0.991046, 1.1961, 1.38571, 1.92052, 2.44223", \ + "0.751563, 0.991047, 1.19611, 1.38572, 1.92053, 2.44224", \ + "0.752638, 0.991928, 1.19675, 1.38603, 1.92209, 2.44225" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "3.07597, 3.20563, 3.32459, 3.43607, 3.73596, 4.01197", \ + "3.09799, 3.22802, 3.34634, 3.45674, 3.75818, 4.03329", \ + "3.11705, 3.2463, 3.36599, 3.4754, 3.77695, 4.05135", \ + "3.15815, 3.28758, 3.40688, 3.51622, 3.81774, 4.09209", \ + "3.22758, 3.35855, 3.47666, 3.58705, 3.8889, 4.16305", \ + "3.34429, 3.47414, 3.59214, 3.70266, 4.00321, 4.27873", \ + "3.52442, 3.65447, 3.77248, 3.88324, 4.18373, 4.45931" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.31851, 1.42363, 1.54608, 1.68276, 2.0768, 2.4985", \ + "1.32119, 1.42852, 1.55183, 1.68277, 2.07681, 2.50051", \ + "1.32394, 1.42853, 1.55496, 1.6839, 2.08078, 2.50052", \ + "1.32971, 1.43386, 1.55964, 1.68951, 2.08463, 2.50053", \ + "1.33505, 1.4416, 1.56391, 1.69291, 2.08837, 2.50308", \ + "1.33506, 1.44161, 1.56392, 1.69292, 2.08838, 2.50784", \ + "1.33507, 1.44162, 1.56393, 1.69293, 2.08839, 2.50785" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : negative_unate; + timing_type : three_state_disable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.26155, 2.26156, 2.26157, 2.26158, 2.26159, 2.2616", \ + "2.29374, 2.29375, 2.29376, 2.29377, 2.29378, 2.29379", \ + "2.30632, 2.30633, 2.30634, 2.30635, 2.30636, 2.30637", \ + "2.35434, 2.35435, 2.35436, 2.35437, 2.35438, 2.35439", \ + "2.41051, 2.41052, 2.41053, 2.41054, 2.41055, 2.41056", \ + "2.48589, 2.4859, 2.48591, 2.48592, 2.48593, 2.48594", \ + "2.59867, 2.59868, 2.59869, 2.5987, 2.59871, 2.59872" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.26155, 2.26156, 2.26157, 2.26158, 2.26159, 2.2616", \ + "2.29374, 2.29375, 2.29376, 2.29377, 2.29378, 2.29379", \ + "2.30632, 2.30633, 2.30634, 2.30635, 2.30636, 2.30637", \ + "2.35434, 2.35435, 2.35436, 2.35437, 2.35438, 2.35439", \ + "2.41051, 2.41052, 2.41053, 2.41054, 2.41055, 2.41056", \ + "2.48589, 2.4859, 2.48591, 2.48592, 2.48593, 2.48594", \ + "2.59867, 2.59868, 2.59869, 2.5987, 2.59871, 2.59872" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "3.40017, 3.40018, 3.40019, 3.4002, 3.40021, 3.40022", \ + "3.47284, 3.47285, 3.47286, 3.47287, 3.47288, 3.47289", \ + "3.47285, 3.47286, 3.47287, 3.47288, 3.47289, 3.4729", \ + "3.48529, 3.49189, 3.4919, 3.49191, 3.49192, 3.49193", \ + "3.6083, 3.60831, 3.60832, 3.60833, 3.60834, 3.60835", \ + "3.7028, 3.70295, 3.703, 3.70302, 3.70305, 3.70306", \ + "3.84481, 3.84482, 3.84483, 3.84484, 3.84485, 3.84486" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "3.40017, 3.40018, 3.40019, 3.4002, 3.40021, 3.40022", \ + "3.47284, 3.47285, 3.47286, 3.47287, 3.47288, 3.47289", \ + "3.47285, 3.47286, 3.47287, 3.47288, 3.47289, 3.4729", \ + "3.48529, 3.49189, 3.4919, 3.49191, 3.49192, 3.49193", \ + "3.6083, 3.60831, 3.60832, 3.60833, 3.60834, 3.60835", \ + "3.7028, 3.70295, 3.703, 3.70302, 3.70305, 3.70306", \ + "3.84481, 3.84482, 3.84483, 3.84484, 3.84485, 3.84486" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : positive_unate; + timing_type : three_state_enable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.89325, 3.11595, 3.29183, 3.44335, 3.82524, 4.15375", \ + "2.91262, 3.13555, 3.31156, 3.46285, 3.84498, 4.17454", \ + "2.92742, 3.15005, 3.32599, 3.47752, 3.85979, 4.18811", \ + "2.96095, 3.18384, 3.35858, 3.5101, 3.89199, 4.22051", \ + "3.00231, 3.22539, 3.40113, 3.55242, 3.93471, 4.26326", \ + "3.05286, 3.27578, 3.45149, 3.60276, 3.98504, 4.31366", \ + "3.11202, 3.33509, 3.51082, 3.662, 4.04398, 4.37335" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.799262, 1.02248, 1.21862, 1.40261, 1.93002, 2.44609", \ + "0.80114, 1.02336, 1.21864, 1.40369, 1.93003, 2.44863", \ + "0.801141, 1.02337, 1.21865, 1.4037, 1.93013, 2.44864", \ + "0.801142, 1.02381, 1.21866, 1.40371, 1.93014, 2.44865", \ + "0.801143, 1.02382, 1.21867, 1.40372, 1.93015, 2.44866", \ + "0.801144, 1.02383, 1.21868, 1.40373, 1.93016, 2.44867", \ + "0.801145, 1.02384, 1.21869, 1.40374, 1.93017, 2.44868" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.52138, 2.69746, 2.84177, 2.97006, 3.30801, 3.60802", \ + "2.54345, 2.71895, 2.86414, 2.99124, 3.33056, 3.63213", \ + "2.55972, 2.73579, 2.88015, 3.00838, 3.34636, 3.64636", \ + "2.58452, 2.76022, 2.90547, 3.03258, 3.3718, 3.6725", \ + "2.62035, 2.79646, 2.94107, 3.06964, 3.40755, 3.70998", \ + "2.6667, 2.84204, 2.98603, 3.11525, 3.45102, 3.75208", \ + "2.71387, 2.88992, 3.03389, 3.16266, 3.50039, 3.80033" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.625595, 0.82257, 0.997822, 1.17138, 1.67118, 2.16345", \ + "0.625596, 0.822571, 1.00068, 1.17139, 1.67124, 2.16346", \ + "0.625597, 0.822572, 1.00069, 1.1714, 1.67125, 2.16347", \ + "0.625598, 0.822573, 1.00085, 1.17141, 1.67126, 2.16348", \ + "0.625599, 0.822574, 1.00086, 1.17142, 1.67127, 2.16349", \ + "0.6256, 0.822575, 1.00087, 1.17143, 1.67128, 2.1635", \ + "0.625601, 0.822576, 1.00088, 1.1715, 1.67134, 2.16351" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "8.11007, 7.9776, 7.91433, 7.87107, 7.75563, 7.6818", \ + "8.11159, 7.97609, 7.91118, 7.86831, 7.77006, 7.69053", \ + "8.12057, 7.98932, 7.92084, 7.86981, 7.77624, 7.67778", \ + "8.13, 7.99699, 7.92954, 7.87239, 7.79265, 7.69812", \ + "8.11268, 7.97494, 7.91307, 7.8651, 7.77885, 7.67955", \ + "8.12046, 7.9853, 7.91115, 7.87815, 7.78005, 7.67676", \ + "8.08408, 7.95608, 7.89594, 7.84962, 7.80117, 7.66539" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "40.0312, 37.5226, 35.4481, 33.6831, 29.6967, 26.8632", \ + "40.1357, 37.5928, 35.5641, 33.797, 29.7906, 26.9596", \ + "40.2969, 37.7625, 35.6748, 33.9482, 29.8854, 27.0717", \ + "40.5391, 38.0007, 35.8987, 34.1567, 30.0785, 27.2472", \ + "40.7672, 38.2022, 36.1304, 34.3578, 30.257, 27.4058", \ + "40.6966, 38.1335, 36.0707, 34.2952, 30.2346, 27.3512", \ + "40.4384, 37.8857, 35.8334, 34.0518, 30.0234, 27.1649" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.19413, 2.34768, 3.4993, 4.65213, 6.67089, 4.29747", \ + "1.19029, 2.34645, 3.50514, 4.64876, 6.66512, 4.23111", \ + "1.18853, 2.34969, 3.50342, 4.64255, 6.64077, 4.18403", \ + "1.18905, 2.34833, 3.49949, 4.64006, 6.57288, 4.0626", \ + "1.19062, 2.34585, 3.50543, 4.65844, 6.5362, 3.85009", \ + "1.1986, 2.35159, 3.51075, 4.64987, 6.25652, 3.4509", \ + "1.21104, 2.36855, 3.5131, 4.6686, 5.92528, 2.67353" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.135005, 0.135099, 0.135009, 0.135109, 0.134632, 0.131131", \ + "0.133149, 0.133257, 0.133055, 0.133046, 0.132822, 0.129099", \ + "0.132438, 0.132477, 0.132482, 0.132403, 0.132183, 0.128427", \ + "0.132575, 0.132656, 0.132616, 0.132583, 0.132285, 0.128486", \ + "0.134177, 0.134345, 0.13421, 0.134166, 0.133842, 0.13002", \ + "0.139181, 0.139363, 0.139211, 0.139186, 0.138589, 0.134465", \ + "0.153593, 0.153778, 0.153633, 0.153577, 0.152764, 0.148059" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "7.24673, 7.22736, 7.23723, 7.22394, 7.27077, 7.24509", \ + "7.23968, 7.22666, 7.22634, 7.21611, 7.25748, 7.28526", \ + "7.24269, 7.22551, 7.22385, 7.2231, 7.22175, 7.25265", \ + "7.23662, 7.22645, 7.23492, 7.22328, 7.26849, 7.24578", \ + "7.24079, 7.23505, 7.22556, 7.22745, 7.23147, 7.26447", \ + "7.24317, 7.24195, 7.22766, 7.23, 7.25847, 7.27416", \ + "7.23787, 7.2322, 7.22259, 7.22427, 7.25544, 7.26264" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "3.45374, 3.45295, 3.45092, 3.45351, 3.45177, 3.44725", \ + "3.45196, 3.45147, 3.45308, 3.45168, 3.45243, 3.44878", \ + "3.45384, 3.45305, 3.45085, 3.45361, 3.4519, 3.44736", \ + "3.4517, 3.4511, 3.45286, 3.45138, 3.45203, 3.44766", \ + "3.45182, 3.45163, 3.45296, 3.45358, 3.4524, 3.44893", \ + "3.44869, 3.44942, 3.4525, 3.45085, 3.45051, 3.4469", \ + "3.45652, 3.45576, 3.45596, 3.45614, 3.45412, 3.4498" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.17383, 2.32553, 3.478, 4.62137, 6.7443, 4.2715", \ + "1.16853, 2.32798, 3.48431, 4.62288, 6.62964, 4.20417", \ + "1.16832, 2.3239, 3.47787, 4.61897, 6.59329, 4.15364", \ + "1.16914, 2.32668, 3.47224, 4.61972, 6.50406, 4.03821", \ + "1.17212, 2.32659, 3.48708, 4.6385, 6.43309, 3.78641", \ + "1.17903, 2.33475, 3.49398, 4.64569, 6.24907, 3.39053", \ + "1.19873, 2.3539, 3.5123, 4.66856, 5.78751, 2.65975" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.0720579, 0.0718393, 0.0716089, 0.0716003, 0.0705565, 0.0658581", \ + "0.0705771, 0.0703506, 0.0702548, 0.0701192, 0.0690656, 0.0642341", \ + "0.0703325, 0.0701138, 0.0699294, 0.0698757, 0.0687689, 0.0640299", \ + "0.0704354, 0.0702293, 0.0701211, 0.0700026, 0.0688539, 0.0640206", \ + "0.0721622, 0.0720202, 0.0718403, 0.0718141, 0.0704471, 0.0655661", \ + "0.0759779, 0.0757908, 0.0756627, 0.075605, 0.074134, 0.0689985", \ + "0.085335, 0.0851138, 0.0849405, 0.0848953, 0.0828153, 0.0777316" \ + ); + } + } + } + pin (p2c) { + direction : "output"; + output_voltage : "core"; + function : "pad"; + related_ground_pin : vss; + related_power_pin : vdd; + max_capacitance : 0.511982; + timing () { + related_pin : "pad"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.129142, 0.15699, 0.209984, 0.262082, 0.313977, 0.365738", \ + "0.130319, 0.160759, 0.21546, 0.267815, 0.319895, 0.371736", \ + "0.13032, 0.16076, 0.215461, 0.267816, 0.319896, 0.371737", \ + "0.130321, 0.160761, 0.215462, 0.267817, 0.319897, 0.371738", \ + "0.130322, 0.160762, 0.215463, 0.267818, 0.319898, 0.371739", \ + "0.130323, 0.160763, 0.215464, 0.267819, 0.319899, 0.37174", \ + "0.130324, 0.160764, 0.215465, 0.26782, 0.3199, 0.371741" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0911876, 0.143094, 0.249024, 0.355948, 0.463506, 0.571503", \ + "0.100288, 0.151905, 0.255961, 0.361637, 0.468127, 0.574895", \ + "0.105906, 0.158132, 0.265133, 0.370556, 0.476527, 0.583094", \ + "0.10867, 0.160612, 0.266342, 0.373269, 0.479443, 0.585713", \ + "0.123954, 0.173374, 0.27463, 0.379312, 0.485381, 0.59258", \ + "0.149836, 0.197097, 0.29485, 0.395027, 0.497844, 0.602256", \ + "0.173951, 0.219286, 0.312369, 0.410313, 0.511001, 0.612615" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.678428, 0.721929, 0.787777, 0.842576, 0.89273, 0.938697", \ + "0.705112, 0.748823, 0.814878, 0.868939, 0.919262, 0.965193", \ + "0.803617, 0.846913, 0.912926, 0.967821, 1.01764, 1.06344", \ + "0.866983, 0.910021, 0.976461, 1.03129, 1.08109, 1.12813", \ + "1.18083, 1.22406, 1.29024, 1.34486, 1.39438, 1.4412", \ + "1.82101, 1.86431, 1.93054, 1.98515, 2.03502, 2.08211", \ + "2.4164, 2.45935, 2.52524, 2.58022, 2.6302, 2.67736" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.207535, 0.247047, 0.31833, 0.388163, 0.459195, 0.529985", \ + "0.207726, 0.247144, 0.318331, 0.388164, 0.459196, 0.530286", \ + "0.207727, 0.247633, 0.318492, 0.388165, 0.459197, 0.530287", \ + "0.207728, 0.247634, 0.318493, 0.388166, 0.459198, 0.53119", \ + "0.207729, 0.247635, 0.318494, 0.388167, 0.459604, 0.531191", \ + "0.20773, 0.247636, 0.318495, 0.388168, 0.459605, 0.531192", \ + "0.207876, 0.247637, 0.318496, 0.388169, 0.459606, 0.531193" \ + ); + } + } + internal_power () { + related_pin : "pad"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "-1.06281, -1.06273, -1.06276, -1.0628, -1.06297, -1.06307", \ + "-1.06353, -1.06598, -1.06488, -1.06613, -1.06635, -1.06623", \ + "-1.0616, -1.05987, -1.06151, -1.06474, -1.06034, -1.06254", \ + "-1.06403, -1.06409, -1.06417, -1.06015, -1.06428, -1.06432", \ + "-1.06202, -1.06207, -1.06207, -1.06218, -1.06225, -1.06229", \ + "-1.06219, -1.06221, -1.06228, -1.06235, -1.06241, -1.06248", \ + "-1.05939, -1.05943, -1.05947, -1.05951, -1.05953, -1.05964" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "1.06281, 1.06273, 1.06283, 1.06292, 1.06302, 1.06307", \ + "1.06724, 1.06721, 1.06734, 1.06744, 1.06754, 1.06759", \ + "1.06458, 1.06465, 1.06468, 1.06474, 1.06485, 1.06497", \ + "1.06403, 1.06409, 1.06417, 1.06425, 1.06428, 1.06432", \ + "1.06202, 1.06207, 1.06207, 1.06218, 1.06225, 1.06229", \ + "1.06219, 1.06221, 1.06228, 1.06235, 1.06241, 1.06248", \ + "1.05939, 1.05943, 1.05947, 1.05951, 1.05953, 1.05964" \ + ); + } + } + internal_power () { + related_pin : "pad"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.000962291, 0.00127424, 0.00142798, 0.00113887, 0.000935495, 0.000561391", \ + "0.000484887, 0.000609444, 0.000856655, 0.00064898, 0.000211787, -7.82926e-05", \ + "-0.000161287, 0.000210168, 0.000282959, 0.000185336, -0.000340525, -0.000338141", \ + "-0.000447412, 5.55765e-05, 0.000114479, -6.70601e-05, -0.000480385, -0.000730073", \ + "-0.000817269, -0.00103296, -0.00110819, -0.0006157, -0.000719497, -0.0010882", \ + "-0.00130179, -0.00128286, -0.00189853, -0.00182627, -0.00190933, -0.00199918", \ + "-0.00127221, -0.00132866, -0.00159916, -0.00171449, -0.00220072, -0.00328816" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0428018, 0.0426598, 0.0427994, 0.0430228, 0.0432198, 0.0433758", \ + "0.0416617, 0.0415051, 0.0416358, 0.0418275, 0.0420067, 0.04214", \ + "0.0408134, 0.0406764, 0.0407948, 0.0409771, 0.041128, 0.0412517", \ + "0.0406817, 0.0405415, 0.0406683, 0.0408513, 0.0409988, 0.0411098", \ + "0.0402953, 0.0401363, 0.0402453, 0.0404059, 0.0405326, 0.0406388", \ + "0.0398625, 0.0396882, 0.039754, 0.0398812, 0.0399983, 0.0400929", \ + "0.0397753, 0.0395403, 0.0395176, 0.0396006, 0.0396902, 0.0397653" \ + ); + } + } + } + pin (c2p) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.016; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0252022; + rise_capacitance : 0.0253231; + rise_capacitance_range (0.0220223, 0.0288318); + fall_capacitance : 0.0250814; + fall_capacitance_range (0.0223272, 0.0272541); + internal_power () { + when : "(!c2p_en * pad * p2c)"; + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-9.93776e-06, 0, 0, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "9.93776e-06, 0, 0, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + when : "(!c2p_en * pad * p2c)"; + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0124555, -0.0129151, -0.0131625, -0.0133357, -0.0133486, -0.0134639, -0.0135316" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0156797, 0.0154412, 0.015492, 0.0153677, 0.0154467, 0.0154115, 0.0153378" \ + ); + } + } + internal_power () { + when : "(!c2p_en * !pad * !p2c)"; + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-9.90739e-06, 0, 0, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "9.90739e-06, 0, 0, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + when : "(!c2p_en * !pad * !p2c)"; + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0124549, -0.0129147, -0.0131622, -0.0133355, -0.0133485, -0.0134638, -0.0135316" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0156792, 0.0154409, 0.0154918, 0.0153675, 0.0154466, 0.0154114, 0.0153378" \ + ); + } + } + internal_power () { + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-9.90739e-06, 0, 0, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "9.90739e-06, 0, 0, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0124549, -0.0129147, -0.0131622, -0.0133355, -0.0133485, -0.0134638, -0.0135316" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0156792, 0.0154409, 0.0154918, 0.0153675, 0.0154466, 0.0154114, 0.0153378" \ + ); + } + } + } + pin (c2p_en) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.011; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0238589; + rise_capacitance : 0.0246374; + rise_capacitance_range (0.0213426, 0.0285629); + fall_capacitance : 0.0230804; + fall_capacitance_range (0.0199992, 0.0261453); + internal_power () { + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "2.17129, 2.16793, 2.16761, 2.17105, 2.16747, 2.1678, 2.17461" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.236474, 0.236865, 0.236084, 0.235809, 0.236069, 0.234611, 0.234705" \ + ); + } + } + internal_power () { + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0300342, 0.0285828, 0.0284198, 0.0284454, 0.0303178, 0.0340689, 0.0433936" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0624454, 0.0616575, 0.061378, 0.0616825, 0.0632276, 0.0677134, 0.0755754" \ + ); + } + } + } + } + cell (sg13g2_IOPadInOut4mA) { + pad_cell : true; + area : 14400; + cell_footprint : "inout"; + pad_drivers : 1; + bond_pads : 1; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 1628.85; + when : "!c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 8044.32; + when : "!c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 1628.65; + when : "!c2p_en&c2p&!pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 8128.02; + when : "!c2p_en&c2p&!pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 383.936; + when : "!c2p_en&!c2p&pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 6893.8; + when : "!c2p_en&!c2p&pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 383.972; + when : "!c2p_en&c2p&pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 6977.06; + when : "!c2p_en&c2p&pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 535.914; + when : "c2p_en&c2p&pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 10163.7; + when : "c2p_en&c2p&pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 535.808; + when : "c2p_en&c2p&pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 10163.7; + when : "c2p_en&c2p&pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 1477.11; + when : "c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 11192.9; + when : "c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 1477.1; + when : "c2p_en&!c2p&!pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 11192.9; + when : "c2p_en&!c2p&!pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 1006.42; + related_pg_pin : iovdd; + } + leakage_power () { + value : 9094.56; + related_pg_pin : vdd; + } + pin (pad) { + direction : "inout"; + is_pad : true; + function : "c2p"; + three_state : "c2p_en'"; + drive_current : 4; + output_voltage : "pad"; + input_voltage : "pad"; + related_ground_pin : iovss; + related_power_pin : iovdd; + max_capacitance : 0.599774; + capacitance : 0.190423; + rise_capacitance : 0.191911; + rise_capacitance_range (0.162998, 0.212716); + fall_capacitance : 0.188935; + fall_capacitance_range (0.167113, 0.203301); + timing () { + related_pin : "c2p"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.71105, 3.37998, 4.04582, 4.71091, 6.70449, 8.69771", \ + "2.73237, 3.40158, 4.06729, 4.7323, 6.72598, 8.71968", \ + "2.75004, 3.41898, 4.08485, 4.7499, 6.74348, 8.73644", \ + "2.78083, 3.44973, 4.11587, 4.78085, 6.77472, 8.76768", \ + "2.82515, 3.49414, 4.16001, 4.82503, 6.81864, 8.81227", \ + "2.87761, 3.54691, 4.2126, 4.8776, 6.87125, 8.86465", \ + "2.94497, 3.61401, 4.27989, 4.94488, 6.93854, 8.93163" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.7451, 3.11803, 4.50581, 5.89091, 10.0734, 14.2522", \ + "1.74511, 3.11925, 4.50609, 5.89289, 10.0736, 14.2523", \ + "1.74512, 3.11926, 4.5061, 5.8929, 10.0737, 14.2524", \ + "1.74518, 3.11927, 4.50619, 5.89685, 10.0738, 14.2525", \ + "1.74519, 3.11928, 4.50635, 5.89686, 10.0739, 14.2526", \ + "1.7452, 3.11929, 4.50636, 5.89687, 10.074, 14.2527", \ + "1.74521, 3.1193, 4.50637, 5.89688, 10.0741, 14.2528" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.79174, 3.45418, 4.11611, 4.77821, 6.76551, 8.74673", \ + "2.81272, 3.47491, 4.13691, 4.79905, 6.78445, 8.77044", \ + "2.83029, 3.49229, 4.15408, 4.81658, 6.80199, 8.78531", \ + "2.86933, 3.53073, 4.19204, 4.85481, 6.83816, 8.82317", \ + "2.9368, 3.59914, 4.2604, 4.92135, 6.90606, 8.89078", \ + "3.05274, 3.71491, 4.37613, 5.03825, 7.02219, 9.00704", \ + "3.23656, 3.89846, 4.56005, 5.22284, 7.2071, 9.19395" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.63423, 2.93109, 4.23454, 5.5523, 9.48952, 13.4138", \ + "1.63428, 2.9311, 4.24036, 5.55231, 9.48953, 13.4364", \ + "1.63432, 2.93111, 4.24205, 5.55232, 9.49059, 13.4365", \ + "1.63474, 2.93112, 4.24206, 5.55233, 9.4906, 13.4366", \ + "1.63475, 2.93113, 4.24207, 5.55582, 9.49061, 13.4367", \ + "1.63476, 2.93363, 4.24208, 5.55583, 9.49062, 13.4368", \ + "1.63477, 2.93364, 4.24349, 5.55584, 9.50132, 13.4369" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : negative_unate; + timing_type : three_state_disable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.73402, 1.73403, 1.73404, 1.73405, 1.73406, 1.73407", \ + "1.76693, 1.76694, 1.76695, 1.76696, 1.76697, 1.76698", \ + "1.78653, 1.78654, 1.78655, 1.78656, 1.78657, 1.78658", \ + "1.81879, 1.8188, 1.81881, 1.81882, 1.81883, 1.81884", \ + "1.87733, 1.87734, 1.87735, 1.87736, 1.87737, 1.87738", \ + "1.958, 1.95801, 1.95802, 1.95803, 1.95804, 1.95805", \ + "2.07363, 2.07364, 2.07365, 2.07366, 2.07367, 2.07368" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.73402, 1.73403, 1.73404, 1.73405, 1.73406, 1.73407", \ + "1.76693, 1.76694, 1.76695, 1.76696, 1.76697, 1.76698", \ + "1.78653, 1.78654, 1.78655, 1.78656, 1.78657, 1.78658", \ + "1.81879, 1.8188, 1.81881, 1.81882, 1.81883, 1.81884", \ + "1.87733, 1.87734, 1.87735, 1.87736, 1.87737, 1.87738", \ + "1.958, 1.95801, 1.95802, 1.95803, 1.95804, 1.95805", \ + "2.07363, 2.07364, 2.07365, 2.07366, 2.07367, 2.07368" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.88995, 1.88996, 1.88997, 1.88998, 1.88999, 1.89", \ + "1.91307, 1.91308, 1.91309, 1.9131, 1.91311, 1.91312", \ + "1.93291, 1.93292, 1.93293, 1.93294, 1.93295, 1.93296", \ + "1.9758, 1.9782, 1.97821, 1.97822, 1.97823, 1.97824", \ + "2.04955, 2.04956, 2.04957, 2.04958, 2.04959, 2.0496", \ + "2.15634, 2.15635, 2.15636, 2.15637, 2.15638, 2.15639", \ + "2.32548, 2.32549, 2.3255, 2.32551, 2.32552, 2.32553" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.88995, 1.88996, 1.88997, 1.88998, 1.88999, 1.89", \ + "1.91307, 1.91308, 1.91309, 1.9131, 1.91311, 1.91312", \ + "1.93291, 1.93292, 1.93293, 1.93294, 1.93295, 1.93296", \ + "1.9758, 1.9782, 1.97821, 1.97822, 1.97823, 1.97824", \ + "2.04955, 2.04956, 2.04957, 2.04958, 2.04959, 2.0496", \ + "2.15634, 2.15635, 2.15636, 2.15637, 2.15638, 2.15639", \ + "2.32548, 2.32549, 2.3255, 2.32551, 2.32552, 2.32553" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : positive_unate; + timing_type : three_state_enable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.7137, 3.39943, 4.0826, 4.76511, 6.81177, 8.85881", \ + "2.7308, 3.41682, 4.10007, 4.78266, 6.8292, 8.87567", \ + "2.74738, 3.43314, 4.11642, 4.79898, 6.84556, 8.8919", \ + "2.78025, 3.46598, 4.14915, 4.83166, 6.87835, 8.92369", \ + "2.82082, 3.50673, 4.19011, 4.87268, 6.91922, 8.96569", \ + "2.87382, 3.55989, 4.24309, 4.9256, 6.97229, 9.01941", \ + "2.93491, 3.61994, 4.30332, 4.98587, 7.03246, 9.07903" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.74463, 3.11827, 4.5034, 5.89277, 10.0735, 14.2275", \ + "1.74464, 3.11843, 4.50579, 5.89783, 10.0736, 14.2333", \ + "1.74465, 3.11844, 4.50582, 5.89784, 10.0737, 14.2334", \ + "1.74475, 3.11845, 4.50583, 5.89785, 10.0738, 14.2335", \ + "1.74476, 3.11846, 4.50584, 5.89786, 10.0739, 14.2518", \ + "1.74477, 3.11847, 4.50585, 5.89787, 10.074, 14.2519", \ + "1.74478, 3.11848, 4.50586, 5.89788, 10.0741, 14.252" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.78275, 3.46635, 4.14912, 4.83171, 6.87682, 8.92086", \ + "2.80466, 3.48788, 4.17103, 4.85366, 6.90158, 8.9425", \ + "2.82103, 3.50466, 4.18739, 4.86855, 6.91366, 8.96083", \ + "2.84577, 3.52937, 4.21213, 4.89472, 6.94267, 8.98384", \ + "2.88234, 3.56541, 4.24746, 4.93139, 6.97915, 9.0203", \ + "2.92654, 3.61031, 4.29243, 4.97643, 7.02132, 9.06541", \ + "2.97478, 3.65851, 4.34119, 5.02468, 7.06872, 9.11091" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.6346, 2.93018, 4.2388, 5.54645, 9.48032, 13.4164", \ + "1.63464, 2.93019, 4.23881, 5.5467, 9.49016, 13.4165", \ + "1.63465, 2.93019, 4.23922, 5.55478, 9.49017, 13.4207", \ + "1.63466, 2.9302, 4.23923, 5.55479, 9.49124, 13.4208", \ + "1.63473, 2.93244, 4.23924, 5.5548, 9.49129, 13.4209", \ + "1.63474, 2.93245, 4.24141, 5.55481, 9.49927, 13.421", \ + "1.63475, 2.93246, 4.24142, 5.55482, 9.50407, 13.4211" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.92209, 2.88786, 2.85858, 2.80545, 2.7402, 2.66181", \ + "2.92027, 2.89247, 2.86386, 2.81193, 2.74425, 2.54769", \ + "2.92234, 2.88863, 2.86357, 2.80515, 2.73897, 2.6415", \ + "2.91742, 2.88284, 2.85448, 2.82429, 2.66805, 2.54085", \ + "2.91702, 2.88393, 2.85845, 2.80677, 2.74056, 2.54454", \ + "2.91404, 2.88568, 2.85335, 2.81112, 2.73849, 2.56917", \ + "2.91757, 2.88777, 2.85951, 2.81601, 2.74098, 2.58906" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.70883, 1.70383, 1.70126, 1.69971, 1.6985, 1.69787", \ + "1.71273, 1.70638, 1.70268, 1.70144, 1.69968, 1.69904", \ + "1.71425, 1.70722, 1.70299, 1.70147, 1.69953, 1.69865", \ + "1.71912, 1.70973, 1.7051, 1.70289, 1.69889, 1.69761", \ + "1.71959, 1.70825, 1.70248, 1.69975, 1.69561, 1.69384", \ + "1.71452, 1.70397, 1.69826, 1.6959, 1.6918, 1.69119", \ + "1.71388, 1.70607, 1.70168, 1.69983, 1.69767, 1.69664" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.19592, 2.35404, 3.50909, 4.66826, 8.14334, 11.611", \ + "1.19387, 2.35193, 3.51443, 4.66557, 8.13814, 11.6079", \ + "1.19402, 2.35177, 3.50906, 4.66581, 8.1407, 11.6133", \ + "1.19412, 2.35249, 3.50742, 4.6674, 8.13543, 11.6119", \ + "1.19494, 2.35388, 3.50925, 4.66903, 8.14192, 11.613", \ + "1.20085, 2.3596, 3.515, 4.67435, 8.14522, 11.6173", \ + "1.21528, 2.37286, 3.52972, 4.68649, 8.15942, 11.6304" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.134951, 0.134437, 0.134508, 0.134029, 0.134217, 0.134185", \ + "0.132955, 0.132867, 0.132271, 0.132026, 0.13225, 0.132422", \ + "0.132323, 0.132036, 0.131797, 0.131789, 0.131672, 0.13164", \ + "0.132453, 0.132073, 0.131976, 0.131711, 0.131832, 0.131868", \ + "0.134062, 0.133731, 0.133489, 0.133527, 0.133345, 0.133367", \ + "0.139081, 0.138702, 0.138729, 0.138449, 0.138474, 0.138485", \ + "0.153533, 0.153458, 0.152848, 0.152921, 0.152923, 0.152953" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.73665, 2.82587, 2.91561, 2.99469, 3.2997, 3.48666", \ + "2.73069, 2.82167, 2.9126, 3.01362, 3.29409, 3.50244", \ + "2.734, 2.82337, 2.91566, 2.98767, 3.29748, 3.52104", \ + "2.73526, 2.82437, 2.91527, 2.99109, 3.30093, 3.51705", \ + "2.72834, 2.8182, 2.9141, 3.01725, 3.24753, 3.58953", \ + "2.73375, 2.82534, 2.91758, 3.0111, 3.25488, 3.48846", \ + "2.73798, 2.82905, 2.92175, 2.99886, 3.30909, 3.51291" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.981031, 0.980664, 0.98049, 0.980434, 0.980039, 0.979721", \ + "0.980863, 0.981526, 0.980292, 0.980268, 0.979908, 0.979536", \ + "0.981265, 0.980975, 0.980765, 0.980729, 0.980154, 0.979843", \ + "0.980535, 0.980165, 0.979993, 0.979937, 0.979536, 0.979172", \ + "0.980715, 0.981318, 0.980821, 0.980143, 0.979807, 0.979406", \ + "0.981286, 0.981121, 0.980928, 0.980365, 0.979999, 0.979742", \ + "0.984532, 0.984253, 0.984104, 0.98336, 0.983178, 0.9829" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.17486, 2.33124, 3.48716, 4.64662, 8.119, 11.5993", \ + "1.17268, 2.3293, 3.48617, 4.64264, 8.12148, 11.5872", \ + "1.17237, 2.32885, 3.48601, 4.64278, 8.12137, 11.5869", \ + "1.17294, 2.32981, 3.48689, 4.64436, 8.11786, 11.5889", \ + "1.17589, 2.33541, 3.49175, 4.6536, 8.12576, 11.5938", \ + "1.18518, 2.34254, 3.50028, 4.65775, 8.13844, 11.6003", \ + "1.20161, 2.36027, 3.51548, 4.67343, 8.15219, 11.6175" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.0716932, 0.0712267, 0.0710114, 0.0709402, 0.0709915, 0.0710068", \ + "0.0701879, 0.069684, 0.0694856, 0.0694017, 0.069478, 0.0695748", \ + "0.0699012, 0.0694941, 0.0691085, 0.0692781, 0.0693152, 0.0692431", \ + "0.0700688, 0.0696028, 0.0693878, 0.0693165, 0.069336, 0.0694324", \ + "0.0719233, 0.0713275, 0.0712192, 0.0711825, 0.0711185, 0.0712275", \ + "0.0756795, 0.0754799, 0.0751821, 0.0748279, 0.0750189, 0.0749553", \ + "0.0849702, 0.0847825, 0.0842604, 0.0842833, 0.0843601, 0.0842668" \ + ); + } + } + } + pin (p2c) { + direction : "output"; + output_voltage : "core"; + function : "pad"; + related_ground_pin : vss; + related_power_pin : vdd; + max_capacitance : 0.511631; + timing () { + related_pin : "pad"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.128583, 0.156548, 0.20953, 0.261674, 0.313582, 0.365357", \ + "0.130188, 0.160633, 0.215494, 0.267762, 0.319727, 0.371574", \ + "0.130189, 0.160634, 0.215495, 0.267763, 0.319728, 0.371575", \ + "0.13019, 0.160635, 0.215496, 0.267764, 0.319729, 0.371576", \ + "0.130191, 0.160636, 0.215497, 0.267765, 0.31973, 0.371577", \ + "0.130192, 0.160637, 0.215498, 0.267766, 0.319731, 0.371578", \ + "0.130193, 0.160638, 0.215499, 0.267767, 0.319732, 0.371579" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0911387, 0.143095, 0.248955, 0.35592, 0.463428, 0.571185", \ + "0.100137, 0.151743, 0.255901, 0.361504, 0.467931, 0.574491", \ + "0.105968, 0.158248, 0.264831, 0.370307, 0.476251, 0.582911", \ + "0.10862, 0.160541, 0.266214, 0.373253, 0.47886, 0.585666", \ + "0.124538, 0.173065, 0.274274, 0.379125, 0.485186, 0.592532", \ + "0.149698, 0.196827, 0.295246, 0.394537, 0.497295, 0.602208", \ + "0.173834, 0.218938, 0.312148, 0.409703, 0.510835, 0.613464" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.678211, 0.721939, 0.788064, 0.842839, 0.89273, 0.939967", \ + "0.70439, 0.747676, 0.81388, 0.867965, 0.917393, 0.964559", \ + "0.810119, 0.853541, 0.919617, 0.973604, 1.02437, 1.07014", \ + "0.864598, 0.907789, 0.96497, 1.01936, 1.06893, 1.11637", \ + "1.18033, 1.22357, 1.28989, 1.34437, 1.39444, 1.44118", \ + "1.82519, 1.86857, 1.93422, 1.98878, 2.03825, 2.08545", \ + "2.40223, 2.44567, 2.51097, 2.56535, 2.61599, 2.6633" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.207334, 0.247134, 0.317869, 0.388227, 0.45913, 0.531035", \ + "0.208013, 0.247278, 0.317882, 0.388228, 0.459131, 0.531036", \ + "0.208014, 0.247307, 0.318676, 0.388229, 0.459215, 0.531037", \ + "0.208015, 0.247308, 0.318677, 0.388447, 0.459652, 0.5319", \ + "0.208016, 0.247309, 0.318678, 0.388448, 0.459653, 0.531901", \ + "0.208017, 0.24731, 0.318679, 0.388449, 0.459654, 0.531902", \ + "0.208394, 0.248233, 0.318887, 0.38845, 0.459655, 0.531903" \ + ); + } + } + internal_power () { + related_pin : "pad"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "-0.138883, -0.138879, -0.138874, -0.138868, -0.138866, -0.138865", \ + "-0.139674, -0.139668, -0.139928, -0.139682, -0.140115, -0.13969", \ + "-0.139894, -0.139722, -0.139089, -0.139255, -0.139477, -0.139635", \ + "-0.139605, -0.139753, -0.139753, -0.139282, -0.13984, -0.139839", \ + "-0.139531, -0.13953, -0.139519, -0.139525, -0.139523, -0.139521", \ + "-0.138934, -0.139069, -0.139067, -0.139065, -0.139064, -0.139063", \ + "-0.139289, -0.139314, -0.139377, -0.139413, -0.139104, -0.139104" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.138883, 0.138879, 0.138874, 0.138868, 0.138866, 0.138865", \ + "0.140171, 0.14017, 0.140166, 0.140163, 0.140158, 0.140159", \ + "0.139894, 0.139889, 0.139883, 0.139882, 0.13988, 0.139878", \ + "0.139754, 0.139753, 0.139848, 0.139843, 0.13984, 0.139839", \ + "0.139531, 0.13953, 0.139527, 0.139525, 0.139523, 0.139521", \ + "0.139071, 0.139069, 0.139067, 0.139065, 0.139064, 0.139063", \ + "0.139289, 0.139314, 0.139377, 0.139413, 0.139104, 0.139104" \ + ); + } + } + internal_power () { + related_pin : "pad"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0008316, 0.00117758, 0.00139774, 0.00117051, 0.00101747, 0.000699307", \ + "0.000512481, 0.000645818, 0.000752975, 0.000503612, 0.000364499, 3.61874e-05", \ + "-0.000188017, 0.000302443, 0.000266867, 0.000290852, -0.000217081, -0.000204221", \ + "-0.000297983, 5.50905e-05, 0.000140939, 8.78119e-05, -0.000331885, -0.000582869", \ + "-0.000881788, -0.000964354, -0.000958069, -0.000785044, -0.000724249, -0.00105278", \ + "-0.001182, -0.00116199, -0.00157432, -0.00199745, -0.00196171, -0.00192293", \ + "-0.00111628, -0.00140388, -0.00157453, -0.00182422, -0.00214596, -0.00275972" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0429223, 0.0427915, 0.0429413, 0.0431652, 0.043358, 0.0435004", \ + "0.041837, 0.0416689, 0.0418011, 0.0419967, 0.0421692, 0.0423135", \ + "0.0410832, 0.0409475, 0.0410761, 0.0412536, 0.0414194, 0.0415458", \ + "0.0407481, 0.0405916, 0.0405598, 0.0407183, 0.0408518, 0.0409688", \ + "0.0404239, 0.0402678, 0.0403795, 0.0405375, 0.0406825, 0.0407789", \ + "0.0398975, 0.0397354, 0.0398027, 0.0399459, 0.0400795, 0.0401704", \ + "0.0402264, 0.0399891, 0.0399431, 0.0400039, 0.0400021, 0.0400682" \ + ); + } + } + } + pin (c2p) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.016; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0252022; + rise_capacitance : 0.025323; + rise_capacitance_range (0.0220221, 0.0288318); + fall_capacitance : 0.0250813; + fall_capacitance_range (0.0223269, 0.0272541); + internal_power () { + when : "(!c2p_en * pad * p2c)"; + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-1.13982e-05, 0, 0, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "1.13982e-05, 0, 0, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + when : "(!c2p_en * pad * p2c)"; + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0124555, -0.012915, -0.0131625, -0.0133357, -0.0133487, -0.0134639, -0.0135316" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0156797, 0.0154411, 0.015492, 0.0153676, 0.0154464, 0.0154114, 0.0153378" \ + ); + } + } + internal_power () { + when : "(!c2p_en * !pad * !p2c)"; + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-1.13928e-05, 0, 0, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "1.13928e-05, 0, 0, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + when : "(!c2p_en * !pad * !p2c)"; + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.012455, -0.0129146, -0.0131622, -0.0133355, -0.0133486, -0.0134639, -0.0135316" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0156792, 0.0154408, 0.0154917, 0.0153675, 0.0154466, 0.0154114, 0.0153378" \ + ); + } + } + internal_power () { + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-1.13928e-05, 0, 0, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "1.13928e-05, 0, 0, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.012455, -0.0129146, -0.0131622, -0.0133355, -0.0133486, -0.0134639, -0.0135316" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0156792, 0.0154408, 0.0154917, 0.0153675, 0.0154466, 0.0154114, 0.0153378" \ + ); + } + } + } + pin (c2p_en) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.011; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0238583; + rise_capacitance : 0.0246361; + rise_capacitance_range (0.0213424, 0.0285887); + fall_capacitance : 0.0230804; + fall_capacitance_range (0.019999, 0.0261246); + internal_power () { + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.810952, 0.810357, 0.810328, 0.810164, 0.810456, 0.810533, 0.814415" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.263376, 0.263744, 0.263013, 0.26307, 0.262925, 0.261866, 0.261955" \ + ); + } + } + internal_power () { + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0300235, 0.0285711, 0.0284082, 0.0284344, 0.0303054, 0.0340561, 0.0433771" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0624483, 0.0616598, 0.0613807, 0.0616824, 0.0632319, 0.0677129, 0.0755781" \ + ); + } + } + } + } + cell (sg13g2_IOPadOut16mA) { + pad_cell : true; + area : 14400; + cell_footprint : "inout"; + pad_drivers : 1; + bond_pads : 1; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 4918.23; + when : "!c2p&!pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 1545.81; + when : "!c2p&!pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 1041.68; + when : "c2p&pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 3850.98; + when : "c2p&pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 2979.96; + related_pg_pin : iovdd; + } + leakage_power () { + value : 2698.39; + related_pg_pin : vdd; + } + pin (pad) { + direction : "output"; + is_pad : true; + function : "c2p"; + drive_current : 16; + output_voltage : "pad"; + related_ground_pin : iovss; + related_power_pin : iovdd; + max_capacitance : 2.09528; + timing () { + related_pin : "c2p"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 3, 7, 9, 12, 15"); + values ( \ + "2.57522, 3.01834, 3.73282, 4.07227, 4.5757, 5.07593", \ + "2.60331, 3.04664, 3.7612, 4.10066, 4.60361, 5.10423", \ + "2.62966, 3.07263, 3.78734, 4.1268, 4.62949, 5.13015", \ + "2.70036, 3.14356, 3.85811, 4.19752, 4.69975, 5.20202", \ + "2.85276, 3.29575, 4.0102, 4.34989, 4.85242, 5.3532", \ + "3.17268, 3.61298, 4.32799, 4.66684, 5.17004, 5.67037", \ + "3.83444, 4.27759, 4.99199, 5.33136, 5.834, 6.33486" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 3, 7, 9, 12, 15"); + values ( \ + "0.770616, 1.42646, 2.74073, 3.40973, 4.42522, 5.44922", \ + "0.770617, 1.42708, 2.74076, 3.40974, 4.42523, 5.4508", \ + "0.770618, 1.42714, 2.74077, 3.40977, 4.42586, 5.45081", \ + "0.770619, 1.42779, 2.74078, 3.41008, 4.42587, 5.45082", \ + "0.77062, 1.4278, 2.74079, 3.41009, 4.42588, 5.45083", \ + "0.770621, 1.42781, 2.7408, 3.4101, 4.42589, 5.45084", \ + "0.770622, 1.42782, 2.74081, 3.41011, 4.4259, 5.45085" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 3, 7, 9, 12, 15"); + values ( \ + "2.57131, 2.9333, 3.57091, 3.88762, 4.36771, 4.85138", \ + "2.57132, 2.93331, 3.57092, 3.88763, 4.36772, 4.85139", \ + "2.57133, 2.93332, 3.57093, 3.88764, 4.36773, 4.8514", \ + "2.58318, 2.94555, 3.58259, 3.89959, 4.37851, 4.86335", \ + "2.61365, 2.97615, 3.61337, 3.93085, 4.40956, 4.8938", \ + "2.66226, 3.02525, 3.66172, 3.97831, 4.4591, 4.94313", \ + "2.72307, 3.08477, 3.72229, 4.03872, 4.51889, 5.00212" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 3, 7, 9, 12, 15"); + values ( \ + "0.912932, 1.43491, 2.61225, 3.23075, 4.17367, 5.12807", \ + "0.912933, 1.43492, 2.61226, 3.23076, 4.17368, 5.12808", \ + "0.913274, 1.43493, 2.61227, 3.23077, 4.17369, 5.12836", \ + "0.913803, 1.43494, 2.61234, 3.23078, 4.1737, 5.12938", \ + "0.913804, 1.43513, 2.61242, 3.23079, 4.17371, 5.13053", \ + "0.914791, 1.43578, 2.61303, 3.23099, 4.17387, 5.13054", \ + "0.916407, 1.43687, 2.61369, 3.23154, 4.17528, 5.13055" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 3, 7, 9, 12, 15"); + values ( \ + "5.00582, 4.93902, 4.90929, 4.88181, 4.81203, 4.74153", \ + "4.99679, 4.9371, 4.91124, 4.88226, 4.79049, 4.75347", \ + "4.99998, 4.93446, 4.91205, 4.88238, 4.8036, 4.74783", \ + "4.9892, 4.94514, 4.91343, 4.88085, 4.78686, 4.71606", \ + "4.99849, 4.95213, 4.9236, 4.89108, 4.80483, 4.74117", \ + "5.02872, 4.97649, 4.93851, 4.90602, 4.82262, 4.7682", \ + "5.07559, 5.00706, 4.98768, 4.95138, 4.86429, 4.79895" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 3, 7, 9, 12, 15"); + values ( \ + "11.2655, 9.19558, 7.45485, 6.98119, 6.47469, 6.11168", \ + "11.2265, 9.16522, 7.42641, 6.95419, 6.4494, 6.08784", \ + "11.2216, 9.15732, 7.42008, 6.94823, 6.44313, 6.0846", \ + "11.2248, 9.15447, 7.41742, 6.94345, 6.43473, 6.07433", \ + "11.2315, 9.16008, 7.41849, 6.94273, 6.43351, 6.07088", \ + "11.2492, 9.17351, 7.42486, 6.95057, 6.44154, 6.08038", \ + "11.2787, 9.19099, 7.43952, 6.95728, 6.45241, 6.07842" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 3, 7, 9, 12, 15"); + values ( \ + "-0.0063267, -0.00632683, -0.00632701, -0.00632689, -0.00632687, -0.00632678", \ + "-0.00796772, -0.00796775, -0.00796798, -0.00796807, -0.0079678, -0.00796781", \ + "-0.00787172, -0.00787173, -0.00787194, -0.00787203, -0.00787177, -0.00787177", \ + "-0.00683557, -0.00683571, -0.00683582, -0.00683589, -0.00683563, -0.00717173", \ + "-0.00412822, -0.00409879, -0.00409901, -0.00412848, -0.00412835, -0.0040987", \ + "0.00306213, 0.00282723, 0.00283827, 0.00282706, 0.00283824, 0.0028273", \ + "0.019111, 0.0191109, 0.0191107, 0.0191107, 0.0191109, 0.0191112" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 3, 7, 9, 12, 15"); + values ( \ + "0.0445352, 0.0445598, 0.0445599, 0.0445565, 0.0445438, 0.0445481", \ + "0.0435012, 0.0435269, 0.0435254, 0.0435217, 0.043509, 0.0435132", \ + "0.0440257, 0.0440415, 0.044056, 0.0440476, 0.044037, 0.0440398", \ + "0.0451641, 0.0451599, 0.0451728, 0.0451642, 0.0451695, 0.0451557", \ + "0.0481635, 0.0481802, 0.0482783, 0.0482771, 0.048268, 0.048183", \ + "0.0550331, 0.0554315, 0.0550516, 0.0550517, 0.0554863, 0.0554292", \ + "0.0704638, 0.0704872, 0.0704906, 0.0704206, 0.0704222, 0.0704723" \ + ); + } + } + } + pin (c2p) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.016; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0371182; + rise_capacitance : 0.0365248; + rise_capacitance_range (0.0330214, 0.0388706); + fall_capacitance : 0.0377115; + fall_capacitance_range (0.0341496, 0.0399949); + } + } + cell (sg13g2_IOPadOut30mA) { + pad_cell : true; + area : 14400; + cell_footprint : "inout"; + pad_drivers : 1; + bond_pads : 1; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 9036.95; + when : "!c2p&!pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 1545.27; + when : "!c2p&!pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 1485.88; + when : "c2p&pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 3850.92; + when : "c2p&pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 5261.41; + related_pg_pin : iovdd; + } + leakage_power () { + value : 2698.09; + related_pg_pin : vdd; + } + pin (pad) { + direction : "output"; + is_pad : true; + function : "c2p"; + drive_current : 30; + output_voltage : "pad"; + related_ground_pin : iovss; + related_power_pin : iovdd; + max_capacitance : 2.62768; + timing () { + related_pin : "c2p"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("2, 6, 14, 18, 24, 30"); + values ( \ + "3.07452, 3.65528, 4.50278, 4.88382, 5.43734, 5.97921", \ + "3.10641, 3.68656, 4.53397, 4.91458, 5.46849, 6.01187", \ + "3.13042, 3.70998, 4.55748, 4.93818, 5.49194, 6.03536", \ + "3.20287, 3.78336, 4.63083, 5.01294, 5.56656, 6.10999", \ + "3.35527, 3.93598, 4.78318, 5.16414, 5.71785, 6.26102", \ + "3.67354, 4.25378, 5.1014, 5.48249, 6.03652, 6.57941", \ + "4.33547, 4.91574, 5.76314, 6.14419, 6.69768, 7.24047" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("2, 6, 14, 18, 24, 30"); + values ( \ + "0.977452, 1.74011, 3.13708, 3.83946, 4.90743, 5.98339", \ + "0.978292, 1.74081, 3.13731, 3.84002, 4.90759, 5.9834", \ + "0.978293, 1.74082, 3.13732, 3.84003, 4.9076, 5.98341", \ + "0.978294, 1.74083, 3.13733, 3.84017, 4.90761, 5.98342", \ + "0.978295, 1.74084, 3.13734, 3.84018, 4.90762, 5.98343", \ + "0.978296, 1.74085, 3.13735, 3.84019, 4.90763, 5.98344", \ + "0.978297, 1.74086, 3.13736, 3.8402, 4.90764, 5.98345" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("2, 6, 14, 18, 24, 30"); + values ( \ + "3.11567, 3.54865, 4.26475, 4.5993, 5.09844, 5.59726", \ + "3.11568, 3.54866, 4.26476, 4.59931, 5.09845, 5.59727", \ + "3.11569, 3.54867, 4.26477, 4.59932, 5.09846, 5.59728", \ + "3.12857, 3.56321, 4.2791, 4.61249, 5.11243, 5.60645", \ + "3.15984, 3.59436, 4.3095, 4.64338, 5.14226, 5.63883", \ + "3.20841, 3.64259, 4.35958, 4.6944, 5.19189, 5.68543", \ + "3.27026, 3.70473, 4.41635, 4.75382, 5.25343, 5.74932" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("2, 6, 14, 18, 24, 30"); + values ( \ + "1.47215, 1.97804, 3.11069, 3.73516, 4.69878, 5.68782", \ + "1.47216, 1.97805, 3.1107, 3.73663, 4.69899, 5.68783", \ + "1.47217, 1.97808, 3.11071, 3.73664, 4.69964, 5.68784", \ + "1.47218, 1.97853, 3.11072, 3.73665, 4.69965, 5.68785", \ + "1.47299, 1.97925, 3.11104, 3.73666, 4.70004, 5.68786", \ + "1.47486, 1.97926, 3.1144, 3.73667, 4.70088, 5.68787", \ + "1.47621, 1.98181, 3.11441, 3.73668, 4.70125, 5.68788" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("2, 6, 14, 18, 24, 30"); + values ( \ + "7.89091, 7.71501, 7.58553, 7.53549, 7.46694, 7.25973", \ + "7.94055, 7.73646, 7.5906, 7.55607, 7.47765, 7.38759", \ + "7.91609, 7.68243, 7.5957, 7.51335, 7.4751, 7.37718", \ + "7.92691, 7.74003, 7.60665, 7.57392, 7.49103, 7.37019", \ + "7.93604, 7.74822, 7.61553, 7.54125, 7.49988, 7.38276", \ + "7.94799, 7.75155, 7.62951, 7.56522, 7.53726, 7.39104", \ + "7.98183, 7.80981, 7.67769, 7.59729, 7.56279, 7.38228" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("2, 6, 14, 18, 24, 30"); + values ( \ + "40.0558, 33.0277, 25.9196, 23.7946, 21.4592, 19.7692", \ + "40.0031, 32.9753, 25.8714, 23.7819, 21.4312, 19.6883", \ + "40.0103, 32.9954, 25.8847, 23.7418, 21.4397, 19.6963", \ + "40.0303, 33.0096, 25.8892, 23.7635, 21.4281, 19.6902", \ + "40.0616, 33.0379, 25.9069, 23.7953, 21.4448, 19.6892", \ + "40.1094, 33.0645, 25.9324, 23.8028, 21.4656, 19.739", \ + "40.192, 33.1478, 25.9851, 23.8508, 21.5, 19.7509" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("2, 6, 14, 18, 24, 30"); + values ( \ + "-0.00632822, -0.00632839, -0.00632831, -0.00632851, -0.0063284, -0.00632824", \ + "-0.00796855, -0.00796862, -0.00796863, -0.00796873, -0.0079687, -0.00796863", \ + "-0.00786991, -0.00786988, -0.0078698, -0.00786992, -0.00786977, -0.00786979", \ + "-0.00683566, -0.00683587, -0.0068357, -0.00717344, -0.00710646, -0.00710625", \ + "-0.00410121, -0.00413146, -0.00410122, -0.00410135, -0.00413144, -0.00410124", \ + "0.00305725, 0.00305707, 0.00305715, 0.00305702, 0.0030571, 0.00305721", \ + "0.0191038, 0.0191036, 0.0191037, 0.0191035, 0.0191036, 0.0191039" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("2, 6, 14, 18, 24, 30"); + values ( \ + "0.0445616, 0.0445554, 0.0445512, 0.044547, 0.0445455, 0.0445419", \ + "0.0435227, 0.043517, 0.0435118, 0.0435079, 0.0435072, 0.0435034", \ + "0.0440497, 0.0440416, 0.0440357, 0.0440331, 0.044029, 0.0440289", \ + "0.0451718, 0.0451663, 0.0451535, 0.045148, 0.045152, 0.0451502", \ + "0.0482758, 0.0482709, 0.0482582, 0.0482609, 0.0481701, 0.0482525", \ + "0.05505, 0.0554797, 0.0554793, 0.0550322, 0.055475, 0.0551045", \ + "0.0704838, 0.0704788, 0.0704639, 0.0704683, 0.0704639, 0.0704624" \ + ); + } + } + } + pin (c2p) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.016; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0371156; + rise_capacitance : 0.0365214; + rise_capacitance_range (0.0330181, 0.038865); + fall_capacitance : 0.0377098; + fall_capacitance_range (0.0341408, 0.0399916); + } + } + cell (sg13g2_IOPadOut4mA) { + pad_cell : true; + area : 14400; + cell_footprint : "inout"; + pad_drivers : 1; + bond_pads : 1; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 1464.94; + when : "!c2p&!pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 1545.24; + when : "!c2p&!pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 738.345; + when : "c2p&pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 3850.99; + when : "c2p&pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 1101.64; + related_pg_pin : iovdd; + } + leakage_power () { + value : 2698.11; + related_pg_pin : vdd; + } + pin (pad) { + direction : "output"; + is_pad : true; + function : "c2p"; + drive_current : 4; + output_voltage : "pad"; + related_ground_pin : iovss; + related_power_pin : iovdd; + max_capacitance : 0.661248; + timing () { + related_pin : "c2p"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.61645, 3.28573, 3.95177, 4.61735, 6.61195, 8.60557", \ + "2.6449, 3.31394, 3.98057, 4.64585, 6.64021, 8.63365", \ + "2.67124, 3.34031, 4.00681, 4.67219, 6.66679, 8.66044", \ + "2.74155, 3.41069, 4.07717, 4.74257, 6.73694, 8.73037", \ + "2.89386, 3.56274, 4.22937, 4.89451, 6.8889, 8.88234", \ + "3.21385, 3.88303, 4.55091, 5.21212, 7.20926, 9.20268", \ + "3.87483, 4.54373, 5.21013, 5.87597, 7.87032, 9.8637" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.69834, 3.06716, 4.44736, 5.83532, 10.0003, 14.1653", \ + "1.69835, 3.06717, 4.44786, 5.83533, 10.0004, 14.1654", \ + "1.69836, 3.06718, 4.44865, 5.83534, 10.0005, 14.1655", \ + "1.69853, 3.06719, 4.44866, 5.83535, 10.0006, 14.1656", \ + "1.69854, 3.0672, 4.44867, 5.83536, 10.0007, 14.1657", \ + "1.69855, 3.06721, 4.44868, 5.83537, 10.0008, 14.1658", \ + "1.69856, 3.06722, 4.44869, 5.83538, 10.0009, 14.1659" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.65641, 3.3159, 3.97513, 4.63437, 6.61451, 8.59604", \ + "2.65642, 3.31591, 3.97514, 4.63438, 6.61452, 8.59605", \ + "2.65643, 3.31592, 3.97515, 4.63439, 6.61453, 8.59606", \ + "2.66724, 3.32661, 3.98702, 4.646, 6.62596, 8.6075", \ + "2.69755, 3.35706, 4.01653, 4.67636, 6.65635, 8.63788", \ + "2.74634, 3.40552, 4.06516, 4.72465, 6.70501, 8.68627", \ + "2.80674, 3.4661, 4.1258, 4.78556, 6.76466, 8.74583" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.58851, 2.87613, 4.17826, 5.48347, 9.40622, 13.3279", \ + "1.58852, 2.8762, 4.17827, 5.48348, 9.40623, 13.328", \ + "1.58853, 2.87621, 4.17828, 5.48349, 9.40624, 13.3281", \ + "1.58854, 2.87633, 4.17829, 5.48366, 9.40625, 13.3282", \ + "1.58855, 2.87634, 4.17895, 5.48367, 9.40626, 13.3283", \ + "1.58856, 2.87635, 4.17896, 5.48369, 9.40627, 13.3284", \ + "1.58857, 2.87636, 4.17897, 5.4837, 9.40628, 13.3285" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.63443, 2.60954, 2.58072, 2.55615, 2.48907, 2.45004", \ + "2.63261, 2.60999, 2.5831, 2.56155, 2.49057, 2.44872", \ + "2.63424, 2.61027, 2.58454, 2.5566, 2.4897, 2.45262", \ + "2.63425, 2.61055, 2.58497, 2.5617, 2.49189, 2.45118", \ + "2.63859, 2.61626, 2.59037, 2.56647, 2.49729, 2.45646", \ + "2.6604, 2.63675, 2.61042, 2.58501, 2.51841, 2.47758", \ + "2.70223, 2.67665, 2.65247, 2.62881, 2.55996, 2.51904" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.84183, 1.81319, 1.8001, 1.79279, 1.78333, 1.77901", \ + "1.82162, 1.79415, 1.78153, 1.7744, 1.76514, 1.76099", \ + "1.81201, 1.78436, 1.77175, 1.76531, 1.75544, 1.75113", \ + "1.80055, 1.77373, 1.76036, 1.75363, 1.7444, 1.74015", \ + "1.79229, 1.76512, 1.75251, 1.74525, 1.73573, 1.73142", \ + "1.78738, 1.76051, 1.74711, 1.7397, 1.73018, 1.72695", \ + "1.7757, 1.74714, 1.73546, 1.72789, 1.71684, 1.71404" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "-0.00632879, -0.00632912, -0.00632916, -0.00632905, -0.00632887, -0.00632889", \ + "-0.00796834, -0.00796877, -0.00796878, -0.00796874, -0.00796872, -0.0079686", \ + "-0.00786948, -0.00786978, -0.00786979, -0.00786975, -0.00786944, -0.00786955", \ + "-0.00683549, -0.00683576, -0.00683575, -0.00683572, -0.00683573, -0.00683571", \ + "-0.0041305, -0.00410127, -0.00413096, -0.00410125, -0.00410124, -0.00410121", \ + "0.00305761, 0.00305734, 0.00286017, 0.00283391, 0.00305737, 0.00305739", \ + "0.0189654, 0.0189651, 0.0191112, 0.0191115, 0.0191114, 0.0191115" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.0445574, 0.0445616, 0.0445483, 0.0445483, 0.0445475, 0.0445539", \ + "0.0435173, 0.0435232, 0.0435108, 0.0435105, 0.0435086, 0.043515", \ + "0.0440427, 0.044045, 0.044034, 0.0440367, 0.0440335, 0.0440393", \ + "0.0451647, 0.0451692, 0.0451541, 0.0451544, 0.0451533, 0.0451586", \ + "0.0481829, 0.0482759, 0.0482647, 0.0481737, 0.0482598, 0.048265", \ + "0.0554855, 0.0554367, 0.0551142, 0.0551117, 0.0554745, 0.0554908", \ + "0.0737095, 0.073601, 0.073706, 0.0737032, 0.0735852, 0.0736026" \ + ); + } + } + } + pin (c2p) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.016; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0371154; + rise_capacitance : 0.0365246; + rise_capacitance_range (0.0330175, 0.0388976); + fall_capacitance : 0.0377062; + fall_capacitance_range (0.0341402, 0.0399804); + } + } + cell (sg13g2_IOPadTriOut16mA) { + pad_cell : true; + area : 14400; + cell_footprint : "tri_out"; + pad_drivers : 1; + bond_pads : 1; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 937.301; + when : "!c2p_en&!c2p"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 6103.66; + when : "!c2p_en&!c2p"; + related_pg_pin : vdd; + } + leakage_power () { + value : 937.3; + when : "!c2p_en&c2p"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 6186.91; + when : "!c2p_en&c2p"; + related_pg_pin : vdd; + } + leakage_power () { + value : 1091.71; + when : "c2p_en&c2p&pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 9373.6; + when : "c2p_en&c2p&pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 4951.7; + when : "c2p_en&!c2p&!pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 9251.78; + when : "c2p_en&!c2p&!pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 1979.5; + related_pg_pin : iovdd; + } + leakage_power () { + value : 7728.99; + related_pg_pin : vdd; + } + pin (pad) { + direction : "output"; + is_pad : true; + function : "c2p"; + three_state : "c2p_en'"; + drive_current : 16; + output_voltage : "pad"; + related_ground_pin : iovss; + related_power_pin : iovdd; + max_capacitance : 2.21523; + capacitance : 0.248764; + rise_capacitance : 0.2505; + rise_capacitance_range (0.2505, 0.2505); + fall_capacitance : 0.247028; + fall_capacitance_range (0.247028, 0.247028); + timing () { + related_pin : "c2p"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.68401, 2.9243, 3.13029, 3.31894, 3.84349, 4.35125", \ + "2.70689, 2.94701, 3.15292, 3.34163, 3.86609, 4.37342", \ + "2.72348, 2.96371, 3.16964, 3.35813, 3.88275, 4.39051", \ + "2.75539, 2.99554, 3.2014, 3.38994, 3.91456, 4.42232", \ + "2.80006, 3.03981, 3.24623, 3.43474, 3.95918, 4.467", \ + "2.85276, 3.09311, 3.29919, 3.48765, 4.01217, 4.51958", \ + "2.9186, 3.15901, 3.36511, 3.55367, 4.07824, 4.58613" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.772759, 1.10544, 1.43081, 1.75499, 2.741, 3.74714", \ + "0.77276, 1.10545, 1.43082, 1.755, 2.74101, 3.74715", \ + "0.772761, 1.10546, 1.43083, 1.75501, 2.74102, 3.74716", \ + "0.772762, 1.10547, 1.43084, 1.75502, 2.74103, 3.74717", \ + "0.772763, 1.10548, 1.43085, 1.75503, 2.74104, 3.74718", \ + "0.772818, 1.10549, 1.43086, 1.75504, 2.74105, 3.74719", \ + "0.773061, 1.1055, 1.43087, 1.75505, 2.74106, 3.7472" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.70681, 2.89914, 3.07179, 3.23519, 3.71425, 4.19518", \ + "2.72956, 2.92069, 3.09432, 3.25743, 3.73656, 4.21699", \ + "2.74827, 2.93968, 3.11305, 3.27581, 3.75386, 4.2352", \ + "2.78908, 2.97982, 3.15265, 3.31678, 3.79252, 4.27226", \ + "2.85897, 3.04953, 3.22204, 3.38581, 3.86339, 4.34082", \ + "2.97405, 3.16663, 3.33754, 3.50161, 3.97902, 4.45659", \ + "3.156, 3.34799, 3.52038, 3.68365, 4.16214, 4.64057" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.872421, 1.13311, 1.40594, 1.69015, 2.59399, 3.52999", \ + "0.875061, 1.13351, 1.40718, 1.69115, 2.59557, 3.53093", \ + "0.876995, 1.13383, 1.4087, 1.69261, 2.59558, 3.53183", \ + "0.880969, 1.1368, 1.40871, 1.69467, 2.59656, 3.53184", \ + "0.885011, 1.14134, 1.41104, 1.6969, 2.5994, 3.5322", \ + "0.885012, 1.14242, 1.41105, 1.69691, 2.59941, 3.53221", \ + "0.885013, 1.14243, 1.41106, 1.69692, 2.59942, 3.53222" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : negative_unate; + timing_type : three_state_disable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.04309, 2.0431, 2.04311, 2.04312, 2.04313, 2.04314", \ + "2.06877, 2.06878, 2.06879, 2.0688, 2.06881, 2.06882", \ + "2.08875, 2.08876, 2.08877, 2.08878, 2.08879, 2.0888", \ + "2.1291, 2.12911, 2.12912, 2.12913, 2.12914, 2.12915", \ + "2.18728, 2.18729, 2.1873, 2.18731, 2.18732, 2.18733", \ + "2.26294, 2.26295, 2.26296, 2.26297, 2.26298, 2.26299", \ + "2.36619, 2.3662, 2.36621, 2.36622, 2.36623, 2.36624" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.04309, 2.0431, 2.04311, 2.04312, 2.04313, 2.04314", \ + "2.06877, 2.06878, 2.06879, 2.0688, 2.06881, 2.06882", \ + "2.08875, 2.08876, 2.08877, 2.08878, 2.08879, 2.0888", \ + "2.1291, 2.12911, 2.12912, 2.12913, 2.12914, 2.12915", \ + "2.18728, 2.18729, 2.1873, 2.18731, 2.18732, 2.18733", \ + "2.26294, 2.26295, 2.26296, 2.26297, 2.26298, 2.26299", \ + "2.36619, 2.3662, 2.36621, 2.36622, 2.36623, 2.36624" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.61841, 2.61842, 2.61843, 2.61844, 2.61845, 2.61846", \ + "2.651, 2.65101, 2.65102, 2.65103, 2.65104, 2.65105", \ + "2.65512, 2.65513, 2.65514, 2.65515, 2.65516, 2.65517", \ + "2.69999, 2.7, 2.70001, 2.70002, 2.70003, 2.70004", \ + "2.78321, 2.78322, 2.78323, 2.78324, 2.78325, 2.78326", \ + "2.89054, 2.89055, 2.89056, 2.89057, 2.89058, 2.89059", \ + "3.06532, 3.06533, 3.06534, 3.06535, 3.06536, 3.06537" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.61841, 2.61842, 2.61843, 2.61844, 2.61845, 2.61846", \ + "2.651, 2.65101, 2.65102, 2.65103, 2.65104, 2.65105", \ + "2.65512, 2.65513, 2.65514, 2.65515, 2.65516, 2.65517", \ + "2.69999, 2.7, 2.70001, 2.70002, 2.70003, 2.70004", \ + "2.78321, 2.78322, 2.78323, 2.78324, 2.78325, 2.78326", \ + "2.89054, 2.89055, 2.89056, 2.89057, 2.89058, 2.89059", \ + "3.06532, 3.06533, 3.06534, 3.06535, 3.06536, 3.06537" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : positive_unate; + timing_type : three_state_enable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.66434, 2.90964, 3.12158, 3.31401, 3.84599, 4.36288", \ + "2.68142, 2.92733, 3.13916, 3.3322, 3.86419, 4.38046", \ + "2.69732, 2.94321, 3.15506, 3.34745, 3.87947, 4.39637", \ + "2.73144, 2.98066, 3.18933, 3.38176, 3.91446, 4.4313", \ + "2.77408, 3.02192, 3.22857, 3.41918, 3.95492, 4.47218", \ + "2.82337, 3.06826, 3.28034, 3.47255, 4.00553, 4.52011", \ + "2.88687, 3.13451, 3.34359, 3.53616, 4.06813, 4.5841" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.786801, 1.1084, 1.43207, 1.75501, 2.73548, 3.74204", \ + "0.786802, 1.10841, 1.43208, 1.75507, 2.73549, 3.74205", \ + "0.786803, 1.10842, 1.43209, 1.75508, 2.7355, 3.74206", \ + "0.786804, 1.11317, 1.43268, 1.75525, 2.7365, 3.74224", \ + "0.786805, 1.11318, 1.43269, 1.75526, 2.73651, 3.74225", \ + "0.786806, 1.11319, 1.4327, 1.75527, 2.73692, 3.74226", \ + "0.786807, 1.1132, 1.43271, 1.75528, 2.73693, 3.74227" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.46513, 2.6859, 2.8766, 3.05825, 3.57607, 4.08077", \ + "2.48722, 2.70797, 2.89871, 3.08034, 3.59887, 4.10288", \ + "2.50345, 2.72421, 2.91763, 3.09658, 3.61327, 4.11901", \ + "2.52758, 2.74917, 2.94288, 3.12227, 3.63949, 4.14462", \ + "2.56305, 2.78509, 2.979, 3.15767, 3.67491, 4.18107", \ + "2.6076, 2.8284, 3.01909, 3.20073, 3.71855, 4.22325", \ + "2.65659, 2.87847, 3.07201, 3.25105, 3.76775, 4.27309" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.662329, 0.971467, 1.27613, 1.58343, 2.5235, 3.47947", \ + "0.66233, 0.971468, 1.27614, 1.58344, 2.52354, 3.47948", \ + "0.662512, 0.971477, 1.27791, 1.58363, 2.52355, 3.47949", \ + "0.662513, 0.971478, 1.278, 1.58461, 2.52356, 3.4795", \ + "0.662514, 0.971479, 1.27801, 1.58462, 2.52357, 3.47951", \ + "0.662515, 0.97148, 1.27802, 1.58463, 2.52358, 3.47952", \ + "0.662516, 0.971481, 1.27803, 1.58464, 2.52359, 3.47953" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "4.96808, 4.94249, 4.97277, 4.98804, 4.90191, 4.86177", \ + "4.97318, 4.92837, 4.97712, 4.99071, 4.90515, 4.82124", \ + "4.97214, 4.93416, 4.97529, 4.98921, 4.90344, 4.86264", \ + "4.97266, 4.9327, 4.97523, 4.98861, 4.90332, 4.86174", \ + "4.97097, 4.92987, 4.97745, 4.9884, 4.90314, 4.85577", \ + "4.96207, 4.92828, 4.97502, 4.983, 4.90182, 4.84467", \ + "4.95733, 4.93593, 4.9716, 4.98207, 4.90296, 4.85781" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "10.193, 9.0844, 8.35361, 7.829, 6.85503, 6.29512", \ + "10.2425, 9.12453, 8.39137, 7.86506, 6.88007, 6.31999", \ + "10.2972, 9.16918, 8.43454, 7.90258, 6.9104, 6.34391", \ + "10.4015, 9.26298, 8.51582, 7.97648, 6.95916, 6.38162", \ + "10.4881, 9.33924, 8.58222, 8.03757, 7.01761, 6.41985", \ + "10.4567, 9.32384, 8.55645, 8.0133, 6.99964, 6.40351", \ + "10.3547, 9.22575, 8.47988, 7.94265, 6.94302, 6.35755" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.0401776, 0.0401773, 0.0401777, 0.0401775, 0.0401755, 0.0401758", \ + "0.0385373, 0.0385378, 0.0385381, 0.0385372, 0.0385354, 0.0385372", \ + "0.0378763, 0.0378763, 0.037876, 0.0378755, 0.0378735, 0.0378737", \ + "0.0379992, 0.0379992, 0.0379993, 0.037999, 0.0379971, 0.0379972", \ + "0.0391813, 0.0391812, 0.0391814, 0.0391813, 0.0391794, 0.0391803", \ + "0.0446474, 0.0446469, 0.0446473, 0.0446466, 0.0446451, 0.0446455", \ + "0.0592706, 0.0592702, 0.0592702, 0.0592694, 0.0592674, 0.0592687" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.0942392, 0.0942397, 0.0942338, 0.0942386, 0.0942451, 0.0942306", \ + "0.092277, 0.0922796, 0.0922752, 0.0922832, 0.0922859, 0.0922792", \ + "0.0916395, 0.0916393, 0.091639, 0.0916531, 0.0916523, 0.0916374", \ + "0.0917725, 0.0917847, 0.0917795, 0.0917734, 0.0917824, 0.0917831", \ + "0.0933614, 0.0933621, 0.0933672, 0.0933669, 0.0933728, 0.0933704", \ + "0.0983747, 0.0983907, 0.0983812, 0.0983749, 0.0983877, 0.0983843", \ + "0.112728, 0.112729, 0.112724, 0.112729, 0.112731, 0.112727" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "4.57991, 4.62197, 4.78479, 4.90077, 5.03019, 5.20935", \ + "4.57217, 4.62271, 4.79181, 4.90899, 5.03502, 5.2077", \ + "4.57307, 4.62105, 4.79259, 4.90332, 5.03133, 5.20857", \ + "4.56938, 4.7011, 4.77798, 4.89399, 5.01078, 5.25081", \ + "4.5802, 4.70025, 4.73469, 4.76994, 5.01399, 5.17509", \ + "4.58048, 4.61294, 4.78281, 4.89291, 5.01042, 5.17659", \ + "4.58231, 4.70225, 4.78116, 4.90242, 5.00754, 5.1783" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.14708, 2.14806, 2.14834, 2.14835, 2.14504, 2.14501", \ + "2.14703, 2.148, 2.14833, 2.14822, 2.14598, 2.14488", \ + "2.14722, 2.14809, 2.14696, 2.14843, 2.148, 2.14506", \ + "2.14586, 2.14745, 2.14648, 2.14839, 2.14474, 2.14396", \ + "2.14545, 2.14792, 2.14664, 2.14767, 2.14495, 2.14416", \ + "2.14688, 2.14793, 2.14825, 2.14819, 2.14502, 2.14494", \ + "2.1494, 2.15168, 2.15077, 2.15227, 2.15079, 2.14849" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.0185986, 0.0185987, 0.018601, 0.0186013, 0.0186002, 0.0186002", \ + "0.0167099, 0.01671, 0.0167122, 0.0167127, 0.0167118, 0.0167115", \ + "0.0162322, 0.0162323, 0.0162345, 0.0162348, 0.016234, 0.0162339", \ + "0.017138, 0.0171181, 0.0171398, 0.0171403, 0.0171395, 0.0171386", \ + "0.0198807, 0.0198818, 0.0198814, 0.0198816, 0.0198614, 0.0198823", \ + "0.0275548, 0.0275543, 0.0275564, 0.0275566, 0.027556, 0.0275558", \ + "0.0463659, 0.0463668, 0.0463674, 0.046368, 0.0463668, 0.0463669" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.0302377, 0.0302403, 0.0302435, 0.030241, 0.0302466, 0.0302448", \ + "0.0287626, 0.0287657, 0.0287693, 0.0287662, 0.0287647, 0.0287696", \ + "0.0284954, 0.0284967, 0.0285024, 0.0284974, 0.0285019, 0.0285021", \ + "0.0286516, 0.0286267, 0.0286524, 0.0286496, 0.0286349, 0.0286521", \ + "0.0303636, 0.0303574, 0.0304421, 0.030367, 0.030369, 0.030444", \ + "0.0342611, 0.0342605, 0.0342626, 0.0342602, 0.0342651, 0.0342635", \ + "0.0434857, 0.0434791, 0.0434816, 0.0434823, 0.0434837, 0.0434855" \ + ); + } + } + } + pin (c2p) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.016; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.025391; + rise_capacitance : 0.0254596; + rise_capacitance_range (0.022261, 0.029073); + fall_capacitance : 0.0253224; + fall_capacitance_range (0.0225646, 0.0275037); + internal_power () { + when : "!c2p_en"; + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0, 0, 0, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0, 0, 0, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + when : "!c2p_en"; + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0124355, -0.0130287, -0.0131357, -0.0133419, -0.0133855, -0.0132293, -0.0135195" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0156047, 0.0155275, 0.0153809, 0.0152937, 0.0154073, 0.0152875, 0.0153112" \ + ); + } + } + internal_power () { + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0, 0, 0, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0, 0, 0, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0124355, -0.0130287, -0.0131357, -0.0133419, -0.0133855, -0.0132293, -0.0135195" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0156047, 0.0155275, 0.0153809, 0.0152937, 0.0154073, 0.0152875, 0.0153112" \ + ); + } + } + } + pin (c2p_en) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.011; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0244494; + rise_capacitance : 0.0250958; + rise_capacitance_range (0.0220979, 0.0287841); + fall_capacitance : 0.0238029; + fall_capacitance_range (0.021611, 0.0263823); + } + } + cell (sg13g2_IOPadTriOut30mA) { + pad_cell : true; + area : 14400; + cell_footprint : "tri_out"; + pad_drivers : 1; + bond_pads : 1; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 1341.23; + when : "!c2p_en&!c2p"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 6103.9; + when : "!c2p_en&!c2p"; + related_pg_pin : vdd; + } + leakage_power () { + value : 1341.23; + when : "!c2p_en&c2p"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 6187.15; + when : "!c2p_en&c2p"; + related_pg_pin : vdd; + } + leakage_power () { + value : 1496.85; + when : "c2p_en&c2p&pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 9373.87; + when : "c2p_en&c2p&pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 9047.94; + when : "c2p_en&!c2p&!pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 9252.18; + when : "c2p_en&!c2p&!pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 3306.81; + related_pg_pin : iovdd; + } + leakage_power () { + value : 7729.27; + related_pg_pin : vdd; + } + pin (pad) { + direction : "output"; + is_pad : true; + function : "c2p"; + three_state : "c2p_en'"; + drive_current : 30; + output_voltage : "pad"; + related_ground_pin : iovss; + related_power_pin : iovdd; + max_capacitance : 0.698507; + capacitance : 0.344907; + rise_capacitance : 0.343194; + rise_capacitance_range (0.343194, 0.343194); + fall_capacitance : 0.346619; + fall_capacitance_range (0.346619, 0.346619); + timing () { + related_pin : "c2p"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.96941, 3.18241, 3.35436, 3.50383, 3.88294, 4.21444", \ + "2.99096, 3.20377, 3.3756, 3.52526, 3.90394, 4.23575", \ + "3.00955, 3.2217, 3.39253, 3.54176, 3.92122, 4.25239", \ + "3.04034, 3.25266, 3.42465, 3.5738, 3.95313, 4.28427", \ + "3.08462, 3.29736, 3.46888, 3.61844, 3.99981, 4.32889", \ + "3.13771, 3.3507, 3.52226, 3.67184, 4.05098, 4.38228", \ + "3.20321, 3.41623, 3.58838, 3.73793, 4.11714, 4.44866" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.739014, 0.982088, 1.19025, 1.38185, 1.91725, 2.4439", \ + "0.739365, 0.982089, 1.19026, 1.38186, 1.91726, 2.44391", \ + "0.739366, 0.98209, 1.19027, 1.38221, 1.91727, 2.44421", \ + "0.739367, 0.982091, 1.19028, 1.38222, 1.91728, 2.44422", \ + "0.739368, 0.982092, 1.19029, 1.38223, 1.92322, 2.44423", \ + "0.739369, 0.982093, 1.1903, 1.38224, 1.92323, 2.44424", \ + "0.740247, 0.982692, 1.19066, 1.38225, 1.92324, 2.44425" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "3.11612, 3.249, 3.36833, 3.47847, 3.78126, 4.0546", \ + "3.13854, 3.27136, 3.39067, 3.50203, 3.80357, 4.07722", \ + "3.15757, 3.29016, 3.40948, 3.52035, 3.82231, 4.09598", \ + "3.19841, 3.33079, 3.45041, 3.56132, 3.86317, 4.13677", \ + "3.26861, 3.40123, 3.5199, 3.63162, 3.93283, 4.2062", \ + "3.38411, 3.51673, 3.63564, 3.74674, 4.04744, 4.32153", \ + "3.56582, 3.69867, 3.81764, 3.92851, 4.23042, 4.50377" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.31586, 1.41981, 1.54358, 1.67064, 2.07095, 2.48303", \ + "1.3181, 1.42158, 1.54568, 1.67616, 2.07276, 2.48523", \ + "1.32115, 1.42433, 1.54771, 1.67821, 2.074, 2.48864", \ + "1.32718, 1.42967, 1.55297, 1.68234, 2.07869, 2.4897", \ + "1.33271, 1.43475, 1.55804, 1.68727, 2.08172, 2.49994", \ + "1.33272, 1.43476, 1.55805, 1.68728, 2.08173, 2.49995", \ + "1.33273, 1.43477, 1.55806, 1.68729, 2.08174, 2.49996" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : negative_unate; + timing_type : three_state_disable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.2982, 2.29821, 2.29822, 2.29823, 2.29824, 2.29825", \ + "2.32445, 2.32446, 2.32447, 2.32448, 2.32449, 2.3245", \ + "2.34365, 2.34366, 2.34367, 2.34368, 2.34369, 2.3437", \ + "2.39265, 2.39266, 2.39267, 2.39268, 2.39269, 2.3927", \ + "2.44126, 2.44127, 2.44128, 2.44129, 2.4413, 2.44131", \ + "2.52498, 2.52499, 2.525, 2.52501, 2.52502, 2.52503", \ + "2.63603, 2.63604, 2.63605, 2.63606, 2.63607, 2.63608" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.2982, 2.29821, 2.29822, 2.29823, 2.29824, 2.29825", \ + "2.32445, 2.32446, 2.32447, 2.32448, 2.32449, 2.3245", \ + "2.34365, 2.34366, 2.34367, 2.34368, 2.34369, 2.3437", \ + "2.39265, 2.39266, 2.39267, 2.39268, 2.39269, 2.3927", \ + "2.44126, 2.44127, 2.44128, 2.44129, 2.4413, 2.44131", \ + "2.52498, 2.52499, 2.525, 2.52501, 2.52502, 2.52503", \ + "2.63603, 2.63604, 2.63605, 2.63606, 2.63607, 2.63608" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "3.44942, 3.44943, 3.44944, 3.44945, 3.44946, 3.44947", \ + "3.51214, 3.51215, 3.51216, 3.51217, 3.51218, 3.51219", \ + "3.51215, 3.51216, 3.51217, 3.51218, 3.51219, 3.5122", \ + "3.54212, 3.54213, 3.54214, 3.54215, 3.54216, 3.54217", \ + "3.60199, 3.602, 3.60201, 3.60202, 3.60203, 3.60204", \ + "3.71507, 3.71508, 3.71509, 3.7151, 3.71511, 3.71512", \ + "3.90153, 3.90154, 3.90155, 3.90156, 3.90157, 3.90158" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "3.44942, 3.44943, 3.44944, 3.44945, 3.44946, 3.44947", \ + "3.51214, 3.51215, 3.51216, 3.51217, 3.51218, 3.51219", \ + "3.51215, 3.51216, 3.51217, 3.51218, 3.51219, 3.5122", \ + "3.54212, 3.54213, 3.54214, 3.54215, 3.54216, 3.54217", \ + "3.60199, 3.602, 3.60201, 3.60202, 3.60203, 3.60204", \ + "3.71507, 3.71508, 3.71509, 3.7151, 3.71511, 3.71512", \ + "3.90153, 3.90154, 3.90155, 3.90156, 3.90157, 3.90158" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : positive_unate; + timing_type : three_state_enable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.92013, 3.1471, 3.32439, 3.47723, 3.86095, 4.19407", \ + "2.93912, 3.16576, 3.34375, 3.49764, 3.88525, 4.21791", \ + "2.95485, 3.18203, 3.36023, 3.51348, 3.90112, 4.23425", \ + "2.98657, 3.21343, 3.39129, 3.54459, 3.93219, 4.26404", \ + "3.0279, 3.2552, 3.4337, 3.58597, 3.97124, 4.30548", \ + "3.07755, 3.30386, 3.48178, 3.63625, 4.01869, 4.35603", \ + "3.13954, 3.36548, 3.54435, 3.6964, 4.08484, 4.41255" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.79615, 1.01907, 1.21806, 1.4047, 1.9305, 2.45092", \ + "0.797561, 1.02002, 1.21826, 1.40482, 1.93759, 2.45396", \ + "0.797894, 1.0204, 1.21887, 1.40483, 1.9376, 2.45462", \ + "0.797895, 1.02041, 1.21888, 1.40484, 1.93761, 2.45463", \ + "0.797896, 1.02042, 1.21889, 1.40485, 1.93762, 2.45464", \ + "0.797897, 1.02043, 1.2189, 1.40486, 1.93763, 2.45465", \ + "0.797898, 1.02044, 1.21891, 1.40487, 1.93764, 2.45466" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.551, 2.72836, 2.87582, 3.00291, 3.34449, 3.64843", \ + "2.57347, 2.75083, 2.89829, 3.02538, 3.36697, 3.6709", \ + "2.5897, 2.76832, 2.91441, 3.04395, 3.38312, 3.68228", \ + "2.61445, 2.79325, 2.93941, 3.06668, 3.40452, 3.70809", \ + "2.65055, 2.82956, 2.97438, 3.10298, 3.44082, 3.74402", \ + "2.69699, 2.87551, 3.02179, 3.14889, 3.49046, 3.78983", \ + "2.74452, 2.9222, 3.0696, 3.19897, 3.53815, 3.84224" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.619064, 0.814027, 0.994236, 1.16337, 1.6617, 2.1554", \ + "0.619065, 0.814028, 0.994237, 1.16338, 1.66171, 2.15541", \ + "0.619066, 0.814997, 0.994242, 1.16581, 1.66174, 2.15542", \ + "0.619067, 0.814998, 0.994243, 1.16582, 1.66175, 2.15543", \ + "0.619068, 0.814999, 0.994244, 1.16583, 1.66176, 2.15544", \ + "0.61907, 0.815, 0.994344, 1.16584, 1.66177, 2.15545", \ + "0.619071, 0.815001, 0.994345, 1.16585, 1.66178, 2.15546" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "7.96381, 7.84037, 7.79607, 7.77405, 7.64415, 7.78038", \ + "7.97128, 7.84341, 7.79571, 7.77867, 7.64736, 7.77282", \ + "7.98278, 7.84508, 7.76946, 7.76718, 7.65378, 7.77855", \ + "7.98241, 7.84615, 7.80501, 7.77108, 7.65816, 7.77888", \ + "7.94917, 7.85565, 7.79493, 7.77723, 7.85658, 7.77297", \ + "7.9682, 7.84989, 7.78974, 7.77273, 7.65069, 7.75971", \ + "7.95245, 7.82504, 7.78437, 7.76103, 7.63128, 7.78092" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "40.13, 37.622, 35.5634, 33.7912, 29.7944, 26.9695", \ + "40.2503, 37.7301, 35.6683, 33.8954, 29.8844, 27.0449", \ + "40.3809, 37.8767, 35.7818, 34.0164, 29.9757, 27.1516", \ + "40.6228, 38.0984, 36.0146, 34.2203, 30.181, 27.311", \ + "40.8568, 38.3176, 36.2174, 34.4368, 30.352, 27.5026", \ + "40.7885, 38.2522, 36.1493, 34.37, 30.2875, 27.4495", \ + "40.5245, 38.0062, 35.9313, 34.1401, 30.0886, 27.2512" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.0401582, 0.0401592, 0.0401583, 0.0401583, 0.0401572, 0.040159", \ + "0.0385226, 0.0385232, 0.0385232, 0.0385229, 0.0385225, 0.0385229", \ + "0.0378566, 0.0378572, 0.0378605, 0.0378605, 0.0378605, 0.0378614", \ + "0.0379835, 0.0379843, 0.0379829, 0.0379838, 0.0379836, 0.0379842", \ + "0.0391664, 0.0391666, 0.0391664, 0.0391662, 0.0391659, 0.0391662", \ + "0.0446293, 0.0446304, 0.0446296, 0.0446296, 0.0446291, 0.0446304", \ + "0.0592486, 0.0592494, 0.0592486, 0.0592485, 0.0592483, 0.0592493" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.0941932, 0.0941953, 0.0941961, 0.0941883, 0.0941949, 0.0941936", \ + "0.0922391, 0.0922307, 0.0922424, 0.0922411, 0.0922427, 0.0922297", \ + "0.0915944, 0.0916059, 0.0915972, 0.0916065, 0.0915969, 0.0916009", \ + "0.0917387, 0.0917361, 0.0917379, 0.0917268, 0.0917351, 0.0917206", \ + "0.0933217, 0.0933255, 0.0933271, 0.0933287, 0.0933267, 0.0933191", \ + "0.0983329, 0.0983374, 0.098339, 0.0983217, 0.0983381, 0.0983311", \ + "0.112662, 0.11266, 0.112676, 0.112675, 0.112667, 0.112669" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "7.01835, 7.03278, 7.05213, 7.08279, 7.05378, 7.1799", \ + "7.0115, 7.01632, 7.04709, 7.11627, 7.31274, 7.34277", \ + "7.00917, 7.02673, 7.06524, 7.11606, 7.31322, 7.37004", \ + "7.01472, 7.0273, 7.06491, 7.11696, 7.31301, 7.33416", \ + "7.01248, 7.02013, 7.0719, 7.08795, 7.24035, 7.33074", \ + "7.01436, 7.01652, 7.05339, 7.1343, 7.05624, 7.35507", \ + "7.01456, 6.98136, 7.06884, 7.07928, 7.30353, 7.15986" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "3.4863, 3.48596, 3.4902, 3.48955, 3.4917, 3.48913", \ + "3.48635, 3.48601, 3.49026, 3.4896, 3.49175, 3.48918", \ + "3.48651, 3.48842, 3.49017, 3.4917, 3.49168, 3.49088", \ + "3.48513, 3.48743, 3.48963, 3.49034, 3.49112, 3.49153", \ + "3.48519, 3.48775, 3.48857, 3.48886, 3.49097, 3.49181", \ + "3.48634, 3.48787, 3.49033, 3.48957, 3.49169, 3.49163", \ + "3.48868, 3.48941, 3.49339, 3.49462, 3.49463, 3.49218" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.01858, 0.0185801, 0.0185803, 0.0185806, 0.018581, 0.0185817", \ + "0.0166881, 0.0166881, 0.0166883, 0.0166889, 0.01669, 0.0166907", \ + "0.0162104, 0.0162103, 0.0162107, 0.0162112, 0.0162123, 0.0162131", \ + "0.0171224, 0.0171224, 0.017104, 0.0171231, 0.0171243, 0.0171062", \ + "0.0198431, 0.0198637, 0.019864, 0.0198644, 0.0198448, 0.0198457", \ + "0.0274303, 0.0274303, 0.0274305, 0.027431, 0.0274311, 0.0274332", \ + "0.0463151, 0.0463149, 0.0463154, 0.0463156, 0.0463173, 0.0463166" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.0302271, 0.0302261, 0.0302291, 0.0302285, 0.0302289, 0.0302259", \ + "0.0287078, 0.0287068, 0.0287097, 0.0287091, 0.0287095, 0.0287066", \ + "0.0284393, 0.0284371, 0.028442, 0.0284408, 0.0284427, 0.0284369", \ + "0.0285898, 0.0285896, 0.0285901, 0.0285901, 0.0285713, 0.0285681", \ + "0.0303809, 0.0303819, 0.0303819, 0.0303825, 0.0303052, 0.0303787", \ + "0.0341207, 0.0341222, 0.0341216, 0.0341214, 0.0341228, 0.0341173", \ + "0.0433994, 0.0433979, 0.0434022, 0.0433993, 0.0434013, 0.0433965" \ + ); + } + } + } + pin (c2p) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.016; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0253911; + rise_capacitance : 0.0254597; + rise_capacitance_range (0.0222614, 0.029073); + fall_capacitance : 0.0253224; + fall_capacitance_range (0.0225648, 0.0275037); + internal_power () { + when : "!c2p_en"; + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0, 0, 0, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0, 0, 0, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + when : "!c2p_en"; + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0124354, -0.0130287, -0.0131357, -0.0133419, -0.0133856, -0.0132292, -0.0135195" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0156077, 0.0155256, 0.0153824, 0.0152939, 0.0154056, 0.0152868, 0.0153104" \ + ); + } + } + internal_power () { + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0, 0, 0, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0, 0, 0, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0124354, -0.0130287, -0.0131357, -0.0133419, -0.0133856, -0.0132292, -0.0135195" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0156077, 0.0155256, 0.0153824, 0.0152939, 0.0154056, 0.0152868, 0.0153104" \ + ); + } + } + } + pin (c2p_en) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.011; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0244489; + rise_capacitance : 0.025095; + rise_capacitance_range (0.022098, 0.0287935); + fall_capacitance : 0.0238029; + fall_capacitance_range (0.0216107, 0.0263835); + } + } + cell (sg13g2_IOPadTriOut4mA) { + pad_cell : true; + area : 14400; + cell_footprint : "tri_out"; + pad_drivers : 1; + bond_pads : 1; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 536.306; + when : "!c2p_en&!c2p"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 6103.84; + when : "!c2p_en&!c2p"; + related_pg_pin : vdd; + } + leakage_power () { + value : 536.306; + when : "!c2p_en&c2p"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 6187.09; + when : "!c2p_en&c2p"; + related_pg_pin : vdd; + } + leakage_power () { + value : 691.999; + when : "c2p_en&c2p&pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 9373.78; + when : "c2p_en&c2p&pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 1419.38; + when : "c2p_en&!c2p&!pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 9251.98; + when : "c2p_en&!c2p&!pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 795.997; + related_pg_pin : iovdd; + } + leakage_power () { + value : 7729.17; + related_pg_pin : vdd; + } + pin (pad) { + direction : "output"; + is_pad : true; + function : "c2p"; + three_state : "c2p_en'"; + drive_current : 4; + output_voltage : "pad"; + related_ground_pin : iovss; + related_power_pin : iovdd; + max_capacitance : 0.661248; + capacitance : 0.166368; + rise_capacitance : 0.170905; + rise_capacitance_range (0.170905, 0.170905); + fall_capacitance : 0.161831; + fall_capacitance_range (0.161831, 0.161831); + timing () { + related_pin : "c2p"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.72623, 3.39616, 4.06281, 4.72771, 6.72219, 8.71562", \ + "2.74802, 3.41761, 4.0843, 4.74908, 6.74357, 8.73722", \ + "2.76544, 3.43503, 4.10185, 4.76696, 6.76145, 8.75509", \ + "2.79718, 3.46686, 4.13336, 4.79866, 6.79318, 8.78682", \ + "2.84107, 3.51048, 4.17665, 4.84214, 6.83661, 8.83003", \ + "2.89459, 3.56424, 4.23028, 4.89577, 6.89026, 8.88365", \ + "2.96208, 3.63173, 4.29801, 4.96338, 6.95783, 8.95119" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.69851, 3.06626, 4.44975, 5.83335, 10.0003, 14.1653", \ + "1.69852, 3.06649, 4.44977, 5.83336, 10.0004, 14.1654", \ + "1.69853, 3.0665, 4.44978, 5.83337, 10.0005, 14.1655", \ + "1.69854, 3.06651, 4.44979, 5.83338, 10.0006, 14.1656", \ + "1.69855, 3.06652, 4.4498, 5.83339, 10.0007, 14.1657", \ + "1.69856, 3.06706, 4.44981, 5.8334, 10.0008, 14.1658", \ + "1.69857, 3.06707, 4.44982, 5.83341, 10.0009, 14.1659" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.81181, 3.47429, 4.13544, 4.79656, 6.77614, 8.75699", \ + "2.83263, 3.49528, 4.15642, 4.81629, 6.79695, 8.77941", \ + "2.85049, 3.51303, 4.17413, 4.83394, 6.81496, 8.79505", \ + "2.88897, 3.55079, 4.21178, 4.87153, 6.85243, 8.83445", \ + "2.9567, 3.61876, 4.27964, 4.93953, 6.9201, 8.90201", \ + "3.07323, 3.73474, 4.39567, 5.05548, 7.03627, 9.01813", \ + "3.25814, 3.9199, 4.58096, 5.24091, 7.22248, 9.2037" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.5863, 2.87595, 4.17886, 5.48335, 9.40553, 13.3332", \ + "1.58632, 2.876, 4.17887, 5.48336, 9.40609, 13.3333", \ + "1.58635, 2.87781, 4.17888, 5.48532, 9.4069, 13.3334", \ + "1.58664, 2.87782, 4.17889, 5.48533, 9.40691, 13.3335", \ + "1.58667, 2.87783, 4.1789, 5.48534, 9.40692, 13.3336", \ + "1.5868, 2.87784, 4.17891, 5.48535, 9.40693, 13.3337", \ + "1.58681, 2.87785, 4.17892, 5.48536, 9.40694, 13.3338" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : negative_unate; + timing_type : three_state_disable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.77767, 1.77768, 1.77769, 1.7777, 1.77771, 1.77772", \ + "1.80361, 1.80362, 1.80363, 1.80364, 1.80365, 1.80366", \ + "1.82332, 1.82333, 1.82334, 1.82335, 1.82336, 1.82337", \ + "1.85903, 1.85904, 1.85905, 1.85906, 1.85907, 1.85908", \ + "1.91347, 1.91348, 1.91349, 1.9135, 1.91351, 1.91352", \ + "1.98692, 1.98693, 1.98694, 1.98695, 1.98696, 1.98697", \ + "2.11098, 2.11099, 2.111, 2.11101, 2.11102, 2.11103" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.77767, 1.77768, 1.77769, 1.7777, 1.77771, 1.77772", \ + "1.80361, 1.80362, 1.80363, 1.80364, 1.80365, 1.80366", \ + "1.82332, 1.82333, 1.82334, 1.82335, 1.82336, 1.82337", \ + "1.85903, 1.85904, 1.85905, 1.85906, 1.85907, 1.85908", \ + "1.91347, 1.91348, 1.91349, 1.9135, 1.91351, 1.91352", \ + "1.98692, 1.98693, 1.98694, 1.98695, 1.98696, 1.98697", \ + "2.11098, 2.11099, 2.111, 2.11101, 2.11102, 2.11103" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.92455, 1.92456, 1.92457, 1.92458, 1.92459, 1.9246", \ + "1.94847, 1.94848, 1.94849, 1.9485, 1.94851, 1.94852", \ + "1.96745, 1.96746, 1.96747, 1.96748, 1.96749, 1.9675", \ + "2.01099, 2.011, 2.01101, 2.01102, 2.01103, 2.01104", \ + "2.08427, 2.08428, 2.08429, 2.0843, 2.08431, 2.08432", \ + "2.19166, 2.19167, 2.19168, 2.19169, 2.1917, 2.19171", \ + "2.36059, 2.3606, 2.36061, 2.36062, 2.36063, 2.36064" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.92455, 1.92456, 1.92457, 1.92458, 1.92459, 1.9246", \ + "1.94847, 1.94848, 1.94849, 1.9485, 1.94851, 1.94852", \ + "1.96745, 1.96746, 1.96747, 1.96748, 1.96749, 1.9675", \ + "2.01099, 2.011, 2.01101, 2.01102, 2.01103, 2.01104", \ + "2.08427, 2.08428, 2.08429, 2.0843, 2.08431, 2.08432", \ + "2.19166, 2.19167, 2.19168, 2.19169, 2.1917, 2.19171", \ + "2.36059, 2.3606, 2.36061, 2.36062, 2.36063, 2.36064" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : positive_unate; + timing_type : three_state_enable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.72534, 3.41282, 4.09793, 4.78011, 6.82982, 8.87788", \ + "2.7441, 3.43155, 4.11651, 4.79934, 6.84966, 8.8965", \ + "2.75995, 3.44742, 4.1324, 4.81521, 6.86611, 8.91225", \ + "2.79391, 3.48109, 4.16747, 4.84982, 6.89672, 8.94641", \ + "2.83582, 3.52236, 4.20763, 4.89044, 6.93845, 8.99081", \ + "2.88545, 3.57255, 4.25809, 4.9414, 6.98954, 9.03823", \ + "2.94883, 3.63567, 4.32184, 5.00439, 7.05365, 9.1019" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.69755, 3.06551, 4.44746, 5.83261, 9.99601, 14.165", \ + "1.69756, 3.06552, 4.44747, 5.8343, 9.99602, 14.1651", \ + "1.69757, 3.06579, 4.44748, 5.83431, 9.99684, 14.1652", \ + "1.69758, 3.0658, 4.44749, 5.83465, 9.99685, 14.1653", \ + "1.69759, 3.06581, 4.44812, 5.83466, 9.99686, 14.1654", \ + "1.6976, 3.06582, 4.44867, 5.83469, 10.0002, 14.1655", \ + "1.69761, 3.06583, 4.44868, 5.8347, 10.0003, 14.1656" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.7979, 3.4796, 4.15733, 4.83675, 6.8707, 8.90438", \ + "2.81988, 3.50098, 4.17968, 4.85857, 6.89251, 8.92619", \ + "2.83601, 3.51736, 4.19659, 4.87458, 6.90862, 8.94238", \ + "2.86072, 3.54137, 4.22075, 4.89948, 6.93382, 8.96748", \ + "2.89667, 3.57823, 4.25737, 4.93556, 6.97188, 9.00409", \ + "2.94197, 3.62269, 4.30168, 4.98078, 7.01472, 9.04841", \ + "2.99116, 3.67273, 4.3514, 5.02984, 7.06389, 9.09729" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.58688, 2.87528, 4.17844, 5.48329, 9.40612, 13.3304", \ + "1.58705, 2.87529, 4.17845, 5.48332, 9.40613, 13.3305", \ + "1.58729, 2.87544, 4.17846, 5.48333, 9.40614, 13.3306", \ + "1.5873, 2.87545, 4.17847, 5.48334, 9.40615, 13.3307", \ + "1.58731, 2.87593, 4.17848, 5.48335, 9.40616, 13.3308", \ + "1.58769, 2.87594, 4.17849, 5.48336, 9.40617, 13.3309", \ + "1.5877, 2.87595, 4.1785, 5.48337, 9.40622, 13.331" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.63263, 2.61221, 2.58796, 2.55846, 2.4912, 2.44923", \ + "2.63088, 2.6076, 2.58675, 2.5575, 2.49003, 2.45226", \ + "2.63231, 2.61037, 2.58015, 2.55834, 2.49102, 2.45316", \ + "2.62858, 2.60966, 2.58231, 2.56026, 2.48958, 2.45163", \ + "2.62627, 2.60422, 2.58248, 2.55684, 2.48712, 2.44569", \ + "2.62332, 2.60313, 2.58071, 2.55594, 2.48574, 2.44413", \ + "2.62549, 2.60956, 2.58241, 2.55909, 2.48952, 2.44905" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.77959, 1.77331, 1.77127, 1.77208, 1.77062, 1.77051", \ + "1.78216, 1.77514, 1.77276, 1.77229, 1.77039, 1.76934", \ + "1.78628, 1.7783, 1.77503, 1.77474, 1.77165, 1.77231", \ + "1.78787, 1.77789, 1.77375, 1.77224, 1.76979, 1.76864", \ + "1.78941, 1.77752, 1.77273, 1.77026, 1.76754, 1.76609", \ + "1.78476, 1.77301, 1.76856, 1.76648, 1.76379, 1.76249", \ + "1.78693, 1.77703, 1.77343, 1.77154, 1.76975, 1.76818" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.0402398, 0.0402389, 0.0402397, 0.0402404, 0.0402407, 0.0402416", \ + "0.0386022, 0.0386011, 0.0386011, 0.0386012, 0.0386014, 0.0386011", \ + "0.0379387, 0.0379366, 0.0379391, 0.0379389, 0.0379394, 0.0379391", \ + "0.0380636, 0.0380608, 0.0380621, 0.0380628, 0.0380634, 0.0380632", \ + "0.0392475, 0.039246, 0.0392464, 0.0392466, 0.0392468, 0.0392474", \ + "0.0447134, 0.044712, 0.0447121, 0.0447124, 0.0447124, 0.0447131", \ + "0.0593354, 0.0593346, 0.0593352, 0.0593366, 0.0593363, 0.0593361" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.0944579, 0.0944662, 0.0944667, 0.0944686, 0.0944688, 0.0944687", \ + "0.0925046, 0.092513, 0.0925116, 0.0925153, 0.0925125, 0.0925086", \ + "0.0918721, 0.0918813, 0.0918783, 0.0918828, 0.0918755, 0.0918839", \ + "0.0920033, 0.0920108, 0.0920095, 0.0920134, 0.0920127, 0.0920109", \ + "0.0935972, 0.0936042, 0.0936016, 0.0936013, 0.093602, 0.0936032", \ + "0.098618, 0.0986244, 0.0986221, 0.0986244, 0.0986226, 0.0986238", \ + "0.11298, 0.112987, 0.112986, 0.112985, 0.112987, 0.112982" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.43918, 2.5418, 2.64408, 2.73585, 3.05817, 3.39054", \ + "2.43927, 2.53848, 2.63265, 2.73735, 3.05223, 3.37944", \ + "2.43852, 2.53872, 2.63087, 2.7381, 3.04905, 3.37941", \ + "2.4386, 2.53706, 2.64641, 2.74746, 3.04587, 3.4068", \ + "2.4379, 2.53675, 2.63843, 2.74152, 3.05712, 3.3783", \ + "2.43667, 2.53425, 2.6531, 2.74395, 3.06855, 3.41703", \ + "2.43993, 2.53646, 2.64885, 2.7462, 3.06393, 3.39708" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.01642, 1.01616, 1.01673, 1.0158, 1.01528, 1.01504", \ + "1.01626, 1.01486, 1.01511, 1.01567, 1.01511, 1.01489", \ + "1.01616, 1.01664, 1.01505, 1.0159, 1.01558, 1.01522", \ + "1.01501, 1.01567, 1.01583, 1.01635, 1.01449, 1.01433", \ + "1.01561, 1.01599, 1.01618, 1.01609, 1.01561, 1.01443", \ + "1.01619, 1.01544, 1.01651, 1.01556, 1.01503, 1.01479", \ + "1.01972, 1.01889, 1.01999, 1.01959, 1.01947, 1.01939" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.0186615, 0.0186598, 0.0186591, 0.0186594, 0.0186607, 0.0186603", \ + "0.0167717, 0.01677, 0.0167687, 0.0167687, 0.0167704, 0.0167708", \ + "0.0162943, 0.0162925, 0.0162913, 0.0162913, 0.0162933, 0.0162929", \ + "0.0171994, 0.0171781, 0.0171981, 0.0171795, 0.0171993, 0.0171987", \ + "0.0199207, 0.0199424, 0.019919, 0.0199193, 0.0199206, 0.019921", \ + "0.0298395, 0.0298048, 0.029839, 0.0298067, 0.0298389, 0.02984", \ + "0.0457974, 0.0457959, 0.0457958, 0.0457959, 0.0457961, 0.0457964" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.030485, 0.0304818, 0.0304817, 0.0304843, 0.0304871, 0.0304842", \ + "0.0290061, 0.029007, 0.0290041, 0.0290057, 0.0290085, 0.0290055", \ + "0.0287367, 0.0287395, 0.0287378, 0.0287374, 0.0287404, 0.0287384", \ + "0.028889, 0.0288856, 0.0288873, 0.02889, 0.0288746, 0.0288711", \ + "0.0305877, 0.03067, 0.0306688, 0.0305905, 0.0306696, 0.0306711", \ + "0.0345388, 0.0345351, 0.0345364, 0.0345388, 0.0345414, 0.034538", \ + "0.0437683, 0.0437727, 0.0437687, 0.0437701, 0.0437729, 0.0437758" \ + ); + } + } + } + pin (c2p) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.016; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0253911; + rise_capacitance : 0.0254596; + rise_capacitance_range (0.022261, 0.029073); + fall_capacitance : 0.0253226; + fall_capacitance_range (0.0225645, 0.0275038); + internal_power () { + when : "!c2p_en"; + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0, 0, 0, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0, 0, 0, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + when : "!c2p_en"; + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0124355, -0.0130287, -0.0131357, -0.0133419, -0.0133857, -0.0132291, -0.0135195" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0155916, 0.0155349, 0.0153769, 0.0152926, 0.0154084, 0.0152901, 0.0153151" \ + ); + } + } + internal_power () { + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0, 0, 0, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0, 0, 0, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0124355, -0.0130287, -0.0131357, -0.0133419, -0.0133857, -0.0132291, -0.0135195" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0155916, 0.0155349, 0.0153769, 0.0152926, 0.0154084, 0.0152901, 0.0153151" \ + ); + } + } + } + pin (c2p_en) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.011; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0244495; + rise_capacitance : 0.0250947; + rise_capacitance_range (0.0220993, 0.0288207); + fall_capacitance : 0.0238043; + fall_capacitance_range (0.0216132, 0.026365); + } + } + cell (sg13g2_IOPadVdd) { + area : 14400; + pad_cell : true; + bond_pads : 1; + dont_touch : true; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + is_pad : true; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 0; + related_pg_pin : iovdd; + } + leakage_power () { + value : 1.01727; + related_pg_pin : vdd; + } + } + cell (sg13g2_IOPadVss) { + area : 14400; + pad_cell : true; + bond_pads : 1; + dont_touch : true; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + is_pad : true; + } + leakage_power () { + value : 0; + related_pg_pin : iovdd; + } + leakage_power () { + value : 0.77141; + related_pg_pin : vdd; + } + } +} diff --git a/flow/platforms/ihp-sg13g2/lib/sg13g2_io_slow_1p35V_3p0V_125C.lib b/flow/platforms/ihp-sg13g2/lib/sg13g2_io_slow_1p35V_3p0V_125C.lib new file mode 100644 index 0000000000..4f59f148b4 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lib/sg13g2_io_slow_1p35V_3p0V_125C.lib @@ -0,0 +1,4599 @@ +/************************************************************************ + + Copyright 2024 IHP PDK Authors + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + https://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +************************************************************************/ + +library (sg13g2_io_slow_1p35V_3p0V_125C) { + comment : "IHP Microelectronics GmbH, 2024"; + date : "$Date: Wed May 8 12:26:45 2024 $"; + revision : "$Revision: 0.0.1 $"; + delay_model : table_lookup; + capacitive_load_unit (1,pf); + current_unit : "1uA"; + leakage_power_unit : "1pW"; + pulling_resistance_unit : "1kohm"; + time_unit : "1ns"; + voltage_unit : "1V"; + voltage_map (vdd, 1.35); + voltage_map (iovdd, 3); + voltage_map (iovss, 0); + voltage_map (vss, 0); + voltage_map (GND, 0); + define_cell_area (pad_drivers, pad_driver_sites); + define_cell_area (bond_pads, pad_slots); + default_output_pin_cap : 0; + default_inout_pin_cap : 1; + default_input_pin_cap : 1; + default_fanout_load : 1; + default_cell_leakage_power : 0; + default_max_transition : 1.2; + default_leakage_power_density : 0; + default_max_capacitance : 0.3; + default_max_fanout : 8; + default_wire_load_area : 0.29; + default_wire_load_capacitance : 0.0003; + default_wire_load_mode : "enclosed"; + default_wire_load_resistance : 0.0057; + in_place_swap_mode : match_footprint; + input_threshold_pct_fall : 50; + input_threshold_pct_rise : 50; + nom_process : 1; + nom_temperature : 125; + nom_voltage : 1.35; + output_threshold_pct_fall : 50; + output_threshold_pct_rise : 50; + slew_derate_from_library : 1; + slew_lower_threshold_pct_fall : 10; + slew_lower_threshold_pct_rise : 10; + slew_upper_threshold_pct_fall : 90; + slew_upper_threshold_pct_rise : 90; + operating_conditions (sg13g2_io_slow_1p35V_3p0V_125C) { + process : 1; + temperature : 125; + voltage : 1.35; + } + input_voltage (pad) { + vih : 3.3; + vil : 0; + vimax : 3.3; + vimin : 0; + } + input_voltage (core) { + vih : 1.2; + vil : 0; + vimax : 1.2; + vimin : 0; + } + output_voltage (pad) { + voh : 3.3; + vol : 0; + vomax : 3.3; + vomin : 0; + } + output_voltage (core) { + voh : 1.2; + vol : 0; + vomax : 1.2; + vomin : 0; + } + wire_load (Zero) { + area : 0.01; + capacitance : 0.0001; + resistance : 0.0001; + slope : 1; + fanout_length (1, 0.01); + fanout_length (5, 0.01); + fanout_length (20, 0.01); + } + wire_load ("0_1k") { + area : 0.36; + capacitance : 0.0001; + resistance : 0.0035; + slope : 7.387; + fanout_length (1, 6.43); + fanout_length (5, 38.56); + fanout_length (20, 146.8); + } + wire_load ("0_5k") { + area : 0.36; + capacitance : 0.0001; + resistance : 0.0042; + slope : 10.99; + fanout_length (1, 7.89); + fanout_length (5, 47.32); + fanout_length (20, 169.4); + } + wire_load ("1k") { + area : 0.36; + capacitance : 0.0002; + resistance : 0.0053; + slope : 10.9; + fanout_length (1, 9.93); + fanout_length (5, 59.59); + fanout_length (20, 215.6); + } + wire_load ("2k") { + area : 0.36; + capacitance : 0.0002; + resistance : 0.0063; + slope : 16.87; + fanout_length (1, 11.68); + fanout_length (5, 70.11); + fanout_length (20, 239.5); + } + wire_load ("5k") { + area : 0.36; + capacitance : 0.0003; + resistance : 0.0072; + slope : 14.58; + fanout_length (1, 13.44); + fanout_length (5, 80.62); + fanout_length (20, 287.1); + } + wire_load ("10k") { + area : 0.37; + capacitance : 0.0003; + resistance : 0.008; + slope : 18.94; + fanout_length (1, 14.9); + fanout_length (5, 89.39); + fanout_length (20, 381.6); + } + wire_load ("30k") { + area : 0.37; + capacitance : 0.0003; + resistance : 0.0094; + slope : 24.61; + fanout_length (1, 17.53); + fanout_length (5, 105.2); + fanout_length (20, 515.5); + } + wire_load ("50k") { + area : 0.37; + capacitance : 0.0005; + resistance : 0.0152; + slope : 31.81; + fanout_length (1, 28.33); + fanout_length (5, 170); + fanout_length (20, 607.6); + } + wire_load ("100k") { + area : 0.39; + capacitance : 0.0009; + resistance : 0.0265; + slope : 40.22; + fanout_length (1, 49.37); + fanout_length (5, 296.2); + fanout_length (20, 812.1); + } + wire_load ("200k") { + area : 0.41; + capacitance : 0.0016; + resistance : 0.0456; + slope : 52.68; + fanout_length (1, 84.71); + fanout_length (5, 508.3); + fanout_length (20, 1051.7); + } + wire_load ("500k") { + area : 0.45; + capacitance : 0.0027; + resistance : 0.076; + slope : 67.44; + fanout_length (1, 141.4); + fanout_length (5, 848.3); + fanout_length (20, 1527.1); + } + wire_load_selection ("4_metls_routing") { + wire_load_from_area (0, 635, 0_1k); + wire_load_from_area (635, 3175, 0_5k); + wire_load_from_area (3175, 6350, 1k); + wire_load_from_area (6350, 12701, 2k); + wire_load_from_area (12701, 31752, 5k); + wire_load_from_area (31752, 63504, 10k); + wire_load_from_area (63504, 190512, 30k); + wire_load_from_area (190512, 317520, 50k); + wire_load_from_area (317520, 635040, 100k); + wire_load_from_area (635040, 1.27008e+06, 200k); + wire_load_from_area (1.27008e+06, 3.1752e+06, 500k); + } + default_wire_load : "1k"; + default_operating_conditions : sg13g2_io_slow_1p35V_3p0V_125C; + default_wire_load_selection : "4_metls_routing"; + lu_table_template (delay_template_7x6_16) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 3, 7, 9, 12, 15"); + } + power_lut_template (passive_power_template_7x1_16) { + variable_1 : input_transition_time; + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + } + power_lut_template (power_template_7x6_16) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 3, 7, 9, 12, 15"); + } + cell (sg13g2_IOPadIOVdd) { + area : 14400; + pad_cell : true; + bond_pads : 1; + dont_touch : true; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + is_pad : true; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 26693.5; + related_pg_pin : iovdd; + } + leakage_power () { + value : 0; + related_pg_pin : vdd; + } + } + cell (sg13g2_IOPadIOVss) { + area : 14400; + pad_cell : true; + bond_pads : 1; + dont_touch : true; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + is_pad : true; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 0; + related_pg_pin : iovdd; + } + leakage_power () { + value : 1.91726; + related_pg_pin : vdd; + } + } + cell (sg13g2_IOPadIn) { + pad_cell : true; + area : 14400; + cell_footprint : "input"; + pad_drivers : 1; + bond_pads : 1; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 0; + when : "pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 1193.75; + when : "pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 0; + when : "!pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 3108.07; + when : "!pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 0; + related_pg_pin : iovdd; + } + leakage_power () { + value : 2150.91; + related_pg_pin : vdd; + } + pin (p2c) { + direction : "output"; + output_voltage : "core"; + function : "pad"; + related_ground_pin : vss; + related_power_pin : vdd; + max_capacitance : 0.737156; + timing () { + related_pin : "pad"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.112045, 0.132047, 0.169539, 0.205934, 0.24215, 0.278233", \ + "0.113801, 0.135509, 0.174739, 0.211717, 0.24802, 0.284249", \ + "0.113802, 0.13551, 0.17474, 0.211718, 0.248021, 0.28425", \ + "0.113803, 0.135511, 0.174741, 0.211719, 0.248022, 0.284251", \ + "0.113804, 0.135512, 0.174742, 0.21172, 0.248023, 0.284252", \ + "0.113805, 0.135513, 0.174743, 0.211721, 0.248024, 0.284253", \ + "0.113806, 0.135514, 0.174744, 0.211722, 0.248025, 0.284254" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0696241, 0.105977, 0.180816, 0.256652, 0.333246, 0.410119", \ + "0.0762027, 0.113269, 0.186784, 0.26182, 0.337477, 0.413739", \ + "0.0836911, 0.119689, 0.193531, 0.268876, 0.344227, 0.420147", \ + "0.0876734, 0.123387, 0.195962, 0.271066, 0.347322, 0.422882", \ + "0.104556, 0.138772, 0.208501, 0.280657, 0.354588, 0.429025", \ + "0.13425, 0.16893, 0.234804, 0.30297, 0.373689, 0.447904", \ + "0.1585, 0.192905, 0.257919, 0.323361, 0.390833, 0.460161" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.40026, 0.42796, 0.472656, 0.51058, 0.545503, 0.578831", \ + "0.440804, 0.468552, 0.513352, 0.551313, 0.586208, 0.618636", \ + "0.552035, 0.580045, 0.624603, 0.662077, 0.696856, 0.730012", \ + "0.612513, 0.640362, 0.684626, 0.72225, 0.757775, 0.791013", \ + "0.910488, 0.938377, 0.982884, 1.0207, 1.05503, 1.08897", \ + "1.50905, 1.53736, 1.58182, 1.6191, 1.65333, 1.68662", \ + "2.02542, 2.05645, 2.10492, 2.14464, 2.18123, 2.21409" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.126586, 0.155301, 0.20781, 0.259253, 0.311527, 0.363777", \ + "0.126587, 0.155324, 0.207811, 0.259282, 0.311528, 0.363778", \ + "0.126588, 0.155325, 0.207812, 0.259283, 0.311529, 0.363779", \ + "0.126589, 0.155326, 0.207813, 0.259284, 0.31153, 0.36378", \ + "0.12659, 0.155327, 0.207814, 0.259285, 0.311531, 0.363781", \ + "0.144293, 0.171451, 0.221638, 0.270417, 0.320604, 0.371992", \ + "0.174663, 0.201923, 0.251563, 0.297563, 0.345965, 0.393535" \ + ); + } + } + internal_power () { + related_pin : "pad"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "6.48775e-09, 6.48829e-09, 6.48839e-09, 6.4885e-09, 6.48804e-09, 6.4881e-09", \ + "1.25709e-08, 1.25712e-08, 1.25713e-08, 1.25713e-08, 1.25707e-08, 1.25716e-08", \ + "2.4736e-08, 2.47361e-08, 2.47361e-08, 2.47357e-08, 2.47363e-08, 2.47364e-08", \ + "3.08189e-08, 3.08189e-08, 3.08184e-08, 3.08196e-08, 3.08189e-08, 3.08198e-08", \ + "6.12365e-08, 6.12356e-08, 6.12356e-08, 6.12357e-08, 6.12358e-08, 6.12364e-08", \ + "1.22069e-07, 1.22065e-07, 1.22071e-07, 1.2207e-07, 1.2207e-07, 1.22069e-07", \ + "1.77834e-07, 1.77829e-07, 1.77834e-07, 1.77828e-07, 1.77831e-07, 1.77834e-07" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "-6.47357e-09, -6.47356e-09, -6.47362e-09, -6.4737e-09, -6.47375e-09, -6.47377e-09", \ + "-1.25498e-08, -1.25498e-08, -1.25499e-08, -1.25499e-08, -1.255e-08, -1.255e-08", \ + "-2.47e-08, -2.47e-08, -2.47001e-08, -2.47002e-08, -2.47003e-08, -2.47003e-08", \ + "-3.07752e-08, -3.07752e-08, -3.07753e-08, -3.07753e-08, -3.07754e-08, -3.07754e-08", \ + "-6.11499e-08, -6.11503e-08, -6.11503e-08, -6.11504e-08, -6.11504e-08, -6.11504e-08", \ + "-1.21899e-07, -1.21899e-07, -1.21899e-07, -1.21899e-07, -1.219e-07, -1.21899e-07", \ + "-1.77587e-07, -1.77586e-07, -1.77586e-07, -1.77586e-07, -1.77586e-07, -1.77587e-07" \ + ); + } + } + internal_power () { + related_pin : "pad"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.00763375, 0.0078481, 0.00819126, 0.00800821, 0.0077922, 0.00748117", \ + "0.00686586, 0.00705798, 0.00709465, 0.00707536, 0.00667588, 0.00635878", \ + "0.00643072, 0.00643081, 0.00662593, 0.00619962, 0.00603652, 0.00542013", \ + "0.00634061, 0.00632707, 0.00645178, 0.00586549, 0.00548383, 0.00491982", \ + "0.00676704, 0.00583938, 0.00568485, 0.00529444, 0.005584, 0.00526191", \ + "0.00951462, 0.0078862, 0.00695763, 0.00582877, 0.00499851, 0.00555648", \ + "0.0127998, 0.0111404, 0.00972108, 0.00826984, 0.00690957, 0.00539515" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0623421, 0.061092, 0.0606589, 0.0606842, 0.0607514, 0.0608053", \ + "0.0608285, 0.0596308, 0.0591578, 0.0591421, 0.0591787, 0.0592473", \ + "0.0601077, 0.0588744, 0.0583887, 0.0583458, 0.0583854, 0.0584302", \ + "0.0599303, 0.0586767, 0.0581558, 0.0580943, 0.058128, 0.0581526", \ + "0.0593151, 0.0581018, 0.0574379, 0.0572922, 0.0572865, 0.057266", \ + "0.0630082, 0.0609257, 0.0594702, 0.058871, 0.0585627, 0.058281", \ + "0.0687022, 0.0651496, 0.062646, 0.0614855, 0.0608868, 0.0603429" \ + ); + } + } + } + pin (pad) { + direction : "input"; + is_pad : true; + input_voltage : "pad"; + fanout_load : 1; + related_ground_pin : iovss; + related_power_pin : iovdd; + max_transition : 3.5; + capacitance : 0.221024; + rise_capacitance : 0.224216; + rise_capacitance_range (0.195327, 0.245091); + fall_capacitance : 0.217833; + fall_capacitance_range (0.196481, 0.232002); + } + } + cell (sg13g2_IOPadInOut16mA) { + pad_cell : true; + area : 14400; + cell_footprint : "inout"; + pad_drivers : 1; + bond_pads : 1; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 5141.58; + when : "!c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 12749.1; + when : "!c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 5141.58; + when : "!c2p_en&c2p&!pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 12932.2; + when : "!c2p_en&c2p&!pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 398.078; + when : "!c2p_en&!c2p&pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 10834.7; + when : "!c2p_en&!c2p&pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 398.078; + when : "!c2p_en&c2p&pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 11017.3; + when : "!c2p_en&c2p&pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 550.826; + when : "c2p_en&c2p&pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 16170.1; + when : "c2p_en&c2p&pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 550.826; + when : "c2p_en&c2p&pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 16170; + when : "c2p_en&c2p&pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 4990.01; + when : "c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 17607.9; + when : "c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 4990.01; + when : "c2p_en&!c2p&!pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 17607.9; + when : "c2p_en&!c2p&!pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 2770.12; + related_pg_pin : iovdd; + } + leakage_power () { + value : 14386.2; + related_pg_pin : vdd; + } + pin (pad) { + direction : "inout"; + is_pad : true; + function : "c2p"; + three_state : "c2p_en'"; + drive_current : 16; + output_voltage : "pad"; + input_voltage : "pad"; + related_ground_pin : iovss; + related_power_pin : iovdd; + max_capacitance : 2.12219; + capacitance : 0.271651; + rise_capacitance : 0.271108; + rise_capacitance_range (0.240674, 0.293218); + fall_capacitance : 0.272193; + fall_capacitance_range (0.249412, 0.287527); + timing () { + related_pin : "c2p"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.21678, 2.454, 2.65611, 2.84304, 3.36767, 3.87395", \ + "2.23262, 2.46955, 2.67172, 2.85865, 3.38309, 3.89019", \ + "2.24239, 2.47912, 2.68128, 2.86788, 3.39277, 3.89985", \ + "2.25722, 2.49387, 2.69619, 2.88309, 3.40767, 3.91436", \ + "2.27527, 2.51203, 2.71427, 2.9008, 3.42561, 3.93268", \ + "2.2925, 2.5294, 2.73169, 2.91857, 3.44315, 3.95033", \ + "2.2988, 2.53588, 2.73806, 2.92486, 3.44955, 3.95578" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.780855, 1.11193, 1.4341, 1.75803, 2.74767, 3.75865", \ + "0.780887, 1.11194, 1.43411, 1.75819, 2.74787, 3.75993", \ + "0.780888, 1.11195, 1.43412, 1.7582, 2.74788, 3.75994", \ + "0.780889, 1.11196, 1.43413, 1.75821, 2.74904, 3.75995", \ + "0.78089, 1.11197, 1.43414, 1.75822, 2.74905, 3.76", \ + "0.780891, 1.11198, 1.43415, 1.75823, 2.74906, 3.76003", \ + "0.780892, 1.11199, 1.43453, 1.75831, 2.74907, 3.76004" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.63567, 1.82498, 1.99716, 2.15977, 2.63586, 3.11376", \ + "1.65376, 1.84306, 2.01518, 2.1777, 2.65369, 3.13156", \ + "1.66853, 1.8579, 2.02983, 2.19242, 2.66826, 3.14631", \ + "1.70226, 1.89143, 2.06329, 2.22564, 2.70119, 3.17877", \ + "1.76005, 1.9491, 2.12096, 2.28333, 2.75823, 3.2351", \ + "1.84627, 2.03547, 2.20708, 2.37046, 2.84489, 3.32196", \ + "2.003, 2.19046, 2.36239, 2.52566, 3.00077, 3.47863" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.904206, 1.15922, 1.4306, 1.71372, 2.61657, 3.5494", \ + "0.90723, 1.16178, 1.43241, 1.71589, 2.61827, 3.54949", \ + "0.909576, 1.16407, 1.43402, 1.71962, 2.61988, 3.5509", \ + "0.914611, 1.16794, 1.43738, 1.72215, 2.62181, 3.55323", \ + "0.916141, 1.1693, 1.43909, 1.72216, 2.62182, 3.55324", \ + "0.916142, 1.16931, 1.4391, 1.72217, 2.62183, 3.55325", \ + "0.916143, 1.16932, 1.43911, 1.72218, 2.62184, 3.55326" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : negative_unate; + timing_type : three_state_disable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.56677, 1.56678, 1.56679, 1.5668, 1.56681, 1.56682", \ + "1.59036, 1.59037, 1.59038, 1.59039, 1.5904, 1.59041", \ + "1.60924, 1.60925, 1.60926, 1.60927, 1.60928, 1.60929", \ + "1.63496, 1.63497, 1.63498, 1.63499, 1.635, 1.63501", \ + "1.67256, 1.67257, 1.67258, 1.67259, 1.6726, 1.67261", \ + "1.73315, 1.73316, 1.73317, 1.73318, 1.73319, 1.7332", \ + "1.81955, 1.81956, 1.81957, 1.81958, 1.81959, 1.8196" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.56677, 1.56678, 1.56679, 1.5668, 1.56681, 1.56682", \ + "1.59036, 1.59037, 1.59038, 1.59039, 1.5904, 1.59041", \ + "1.60924, 1.60925, 1.60926, 1.60927, 1.60928, 1.60929", \ + "1.63496, 1.63497, 1.63498, 1.63499, 1.635, 1.63501", \ + "1.67256, 1.67257, 1.67258, 1.67259, 1.6726, 1.67261", \ + "1.73315, 1.73316, 1.73317, 1.73318, 1.73319, 1.7332", \ + "1.81955, 1.81956, 1.81957, 1.81958, 1.81959, 1.8196" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.584, 1.58401, 1.58402, 1.58403, 1.58404, 1.58405", \ + "1.6057, 1.60571, 1.60572, 1.60573, 1.60574, 1.60575", \ + "1.62225, 1.62244, 1.62245, 1.62246, 1.62247, 1.62248", \ + "1.66157, 1.66158, 1.66159, 1.6616, 1.66161, 1.66162", \ + "1.73049, 1.7305, 1.73051, 1.73052, 1.73053, 1.73054", \ + "1.81053, 1.81054, 1.81055, 1.81056, 1.81057, 1.81058", \ + "1.93914, 1.93915, 1.93916, 1.93917, 1.93918, 1.93919" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.584, 1.58401, 1.58402, 1.58403, 1.58404, 1.58405", \ + "1.6057, 1.60571, 1.60572, 1.60573, 1.60574, 1.60575", \ + "1.62225, 1.62244, 1.62245, 1.62246, 1.62247, 1.62248", \ + "1.66157, 1.66158, 1.66159, 1.6616, 1.66161, 1.66162", \ + "1.73049, 1.7305, 1.73051, 1.73052, 1.73053, 1.73054", \ + "1.81053, 1.81054, 1.81055, 1.81056, 1.81057, 1.81058", \ + "1.93914, 1.93915, 1.93916, 1.93917, 1.93918, 1.93919" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : positive_unate; + timing_type : three_state_enable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.20115, 2.44405, 2.65071, 2.84281, 3.37994, 3.89654", \ + "2.21659, 2.45928, 2.66599, 2.85727, 3.39456, 3.91156", \ + "2.22672, 2.46964, 2.67693, 2.86837, 3.40501, 3.92286", \ + "2.24313, 2.48586, 2.69223, 2.88342, 3.42014, 3.93756", \ + "2.26441, 2.50729, 2.71281, 2.9041, 3.44072, 3.95805", \ + "2.28522, 2.52792, 2.73471, 2.92577, 3.46249, 3.98047", \ + "2.29859, 2.54141, 2.74942, 2.93826, 3.47765, 3.99464" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.793084, 1.11639, 1.43572, 1.75857, 2.74628, 3.75403", \ + "0.793429, 1.1164, 1.43595, 1.75858, 2.74629, 3.75436", \ + "0.79343, 1.11647, 1.43596, 1.75859, 2.7463, 3.75437", \ + "0.793431, 1.11648, 1.43597, 1.7586, 2.74631, 3.75438", \ + "0.793432, 1.11648, 1.43598, 1.75861, 2.74632, 3.75439", \ + "0.793433, 1.11649, 1.43599, 1.75862, 2.74633, 3.75441", \ + "0.793434, 1.1165, 1.436, 1.75863, 2.74634, 3.75442" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.38411, 1.60081, 1.7914, 1.97208, 2.48735, 2.99215", \ + "1.40047, 1.61709, 1.80871, 1.9884, 2.50365, 3.00848", \ + "1.40949, 1.62627, 1.81787, 1.99744, 2.51283, 3.01764", \ + "1.42185, 1.63852, 1.82992, 2.00943, 2.52452, 3.02953", \ + "1.43835, 1.65438, 1.84579, 2.02645, 2.54186, 3.04652", \ + "1.44879, 1.66544, 1.85705, 2.03674, 2.55199, 3.05682", \ + "1.45216, 1.66687, 1.85706, 2.03675, 2.55363, 3.05902" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.660085, 0.970295, 1.27963, 1.59168, 2.53524, 3.49477", \ + "0.660086, 0.970364, 1.28083, 1.59169, 2.53525, 3.49478", \ + "0.660087, 0.970365, 1.28084, 1.5917, 2.53526, 3.49479", \ + "0.660088, 0.971326, 1.28085, 1.59171, 2.53527, 3.4948", \ + "0.660089, 0.972914, 1.28163, 1.59175, 2.5353, 3.49482", \ + "0.660098, 0.972915, 1.28164, 1.59176, 2.53531, 3.49483", \ + "0.660099, 0.972916, 1.28165, 1.59177, 2.53532, 3.49484" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "5.15034, 5.10337, 5.07702, 5.05107, 4.95834, 4.85109", \ + "5.15458, 5.10983, 5.07771, 5.04495, 4.96053, 4.88373", \ + "5.15342, 5.10647, 5.07927, 5.0466, 4.9599, 4.88262", \ + "5.15048, 5.10674, 5.07789, 5.04639, 4.9608, 4.85592", \ + "5.15255, 5.10465, 5.07774, 5.04003, 4.95219, 4.88283", \ + "5.14346, 5.09779, 5.07381, 5.04228, 4.95066, 4.88718", \ + "5.13185, 5.08628, 5.05872, 5.03688, 4.95069, 4.83744" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "10.4729, 9.29049, 8.51345, 7.94018, 6.88167, 6.26136", \ + "10.5525, 9.36073, 8.5794, 7.99976, 6.93, 6.29755", \ + "10.6263, 9.42911, 8.62905, 8.05976, 6.97326, 6.33425", \ + "10.7417, 9.52703, 8.72867, 8.14068, 7.03741, 6.38574", \ + "10.7882, 9.56805, 8.76126, 8.16467, 7.05859, 6.40873", \ + "10.7054, 9.49483, 8.6926, 8.12191, 7.00699, 6.3668", \ + "10.4818, 9.29073, 8.51467, 7.96085, 6.89579, 6.27296" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.86475, 3.66268, 5.45556, 7.27169, 12.6337, 17.4074", \ + "1.86236, 3.66493, 5.46738, 7.25383, 12.6421, 17.3877", \ + "1.86567, 3.66429, 5.46856, 7.27303, 12.6321, 17.3777", \ + "1.87127, 3.66815, 5.4743, 7.26271, 12.6374, 17.3546", \ + "1.88605, 3.68655, 5.483, 7.27714, 12.654, 17.3142", \ + "1.92494, 3.72571, 5.52179, 7.319, 12.703, 17.4112", \ + "2.01219, 3.81148, 5.60316, 7.40383, 12.7829, 17.1719" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.206736, 0.206294, 0.206167, 0.205951, 0.205452, 0.205685", \ + "0.204453, 0.204012, 0.203869, 0.203651, 0.203171, 0.203453", \ + "0.205582, 0.205222, 0.20506, 0.204873, 0.204336, 0.204655", \ + "0.211652, 0.211267, 0.211053, 0.2109, 0.210366, 0.2105", \ + "0.228433, 0.228048, 0.227855, 0.227635, 0.227153, 0.227417", \ + "0.268136, 0.267743, 0.267535, 0.267275, 0.26684, 0.266859", \ + "0.353318, 0.352653, 0.352662, 0.352425, 0.351997, 0.351871" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "4.78062, 4.81891, 4.85943, 4.92435, 5.15304, 5.34195", \ + "4.77866, 4.8211, 4.86198, 4.91013, 5.14071, 5.33976", \ + "4.78056, 4.81663, 4.87575, 4.93512, 5.15112, 5.38899", \ + "4.77949, 4.82628, 4.87038, 4.91871, 5.1285, 5.31855", \ + "4.78044, 4.82828, 4.87509, 4.92492, 5.14317, 5.33481", \ + "4.7804, 4.82641, 4.87335, 4.91808, 5.13672, 5.37612", \ + "4.77814, 4.83223, 4.90266, 4.94136, 5.21787, 5.41014" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.9788, 1.97693, 1.97496, 1.97252, 1.97013, 1.96893", \ + "1.97886, 1.97704, 1.97546, 1.97253, 1.97023, 1.96904", \ + "1.97888, 1.97704, 1.97548, 1.97258, 1.97024, 1.96904", \ + "1.97856, 1.97726, 1.97528, 1.97361, 1.9703, 1.96917", \ + "1.97902, 1.97705, 1.97407, 1.97285, 1.9703, 1.96894", \ + "1.97718, 1.97537, 1.97383, 1.97091, 1.96861, 1.96743", \ + "1.98044, 1.97875, 1.97791, 1.97711, 1.97499, 1.97114" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.8312, 3.63334, 5.43599, 7.24194, 12.6024, 17.3774", \ + "1.82983, 3.63187, 5.41598, 7.20499, 12.6011, 17.3592", \ + "1.83278, 3.63478, 5.42273, 7.21467, 12.628, 17.43", \ + "1.84231, 3.64409, 5.44217, 7.25336, 12.6125, 17.4927", \ + "1.8613, 3.6606, 5.46674, 7.27064, 12.6332, 17.3066", \ + "1.9085, 3.7096, 5.50615, 7.30301, 12.6905, 17.2808", \ + "2.00011, 3.79697, 5.59104, 7.39198, 12.7722, 17.1061" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.105399, 0.105011, 0.104716, 0.104573, 0.104203, 0.10439", \ + "0.104306, 0.103907, 0.103606, 0.103478, 0.103138, 0.103287", \ + "0.105412, 0.105128, 0.104799, 0.104585, 0.10433, 0.104474", \ + "0.109963, 0.10959, 0.109263, 0.109118, 0.108804, 0.108897", \ + "0.120612, 0.120066, 0.119898, 0.119781, 0.119429, 0.119541", \ + "0.144593, 0.144192, 0.14387, 0.143734, 0.143386, 0.14359", \ + "0.191827, 0.191313, 0.190885, 0.19068, 0.190365, 0.190354" \ + ); + } + } + } + pin (p2c) { + direction : "output"; + output_voltage : "core"; + function : "pad"; + related_ground_pin : vss; + related_power_pin : vdd; + max_capacitance : 0.734601; + timing () { + related_pin : "pad"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.112376, 0.132329, 0.169867, 0.206269, 0.242446, 0.278543", \ + "0.11418, 0.135713, 0.174915, 0.211975, 0.248242, 0.284325", \ + "0.114181, 0.135714, 0.174916, 0.211976, 0.248243, 0.284326", \ + "0.114182, 0.135715, 0.174917, 0.211977, 0.248244, 0.284327", \ + "0.114183, 0.135716, 0.174918, 0.211978, 0.248245, 0.284328", \ + "0.114184, 0.135717, 0.174919, 0.211979, 0.248246, 0.284329", \ + "0.114185, 0.135718, 0.17492, 0.21198, 0.248247, 0.28433" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0696225, 0.106124, 0.180907, 0.256765, 0.333282, 0.410258", \ + "0.0763506, 0.113334, 0.18684, 0.261931, 0.337549, 0.413787", \ + "0.0838534, 0.119916, 0.193638, 0.269289, 0.344428, 0.420126", \ + "0.0875028, 0.122994, 0.195874, 0.271015, 0.347482, 0.422441", \ + "0.104503, 0.138778, 0.208718, 0.280394, 0.354209, 0.42903", \ + "0.134222, 0.168918, 0.234776, 0.302934, 0.374637, 0.446135", \ + "0.158429, 0.192669, 0.257684, 0.322756, 0.391788, 0.46015" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.400266, 0.428043, 0.472473, 0.510257, 0.544835, 0.578149", \ + "0.440919, 0.468965, 0.513153, 0.550543, 0.585731, 0.618737", \ + "0.547752, 0.575741, 0.619883, 0.657763, 0.691725, 0.724792", \ + "0.609147, 0.636998, 0.681378, 0.719086, 0.753848, 0.786132", \ + "0.910646, 0.938322, 0.982721, 1.01995, 1.05444, 1.08745", \ + "1.50942, 1.53732, 1.5817, 1.61857, 1.65321, 1.68593", \ + "2.02905, 2.06011, 2.10848, 2.14818, 2.18358, 2.21645" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.126229, 0.154959, 0.207221, 0.258696, 0.310011, 0.362267", \ + "0.126357, 0.155117, 0.207222, 0.258697, 0.310012, 0.362278", \ + "0.126358, 0.155118, 0.207223, 0.258698, 0.310013, 0.362279", \ + "0.126359, 0.155119, 0.207224, 0.258699, 0.310014, 0.36228", \ + "0.12636, 0.15512, 0.207284, 0.2587, 0.310015, 0.362281", \ + "0.144064, 0.170945, 0.220799, 0.269194, 0.31869, 0.370227", \ + "0.173232, 0.200297, 0.248545, 0.294422, 0.343371, 0.391132" \ + ); + } + } + internal_power () { + related_pin : "pad"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "-0.555709, -0.557118, -0.557147, -0.557162, -0.557184, -0.557198", \ + "-0.558318, -0.558423, -0.558868, -0.558238, -0.555732, -0.559125", \ + "-0.558649, -0.558631, -0.558658, -0.556973, -0.558695, -0.558716", \ + "-0.558603, -0.558592, -0.558588, -0.556129, -0.558193, -0.558591", \ + "-0.55897, -0.558915, -0.558835, -0.558251, -0.558827, -0.558826", \ + "-0.55556, -0.556072, -0.555864, -0.557266, -0.557022, -0.555977", \ + "-0.556987, -0.555768, -0.555751, -0.556051, -0.555981, -0.556225" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.557145, 0.557152, 0.557147, 0.557162, 0.557184, 0.557198", \ + "0.559024, 0.55904, 0.559057, 0.559085, 0.559109, 0.559125", \ + "0.558649, 0.558631, 0.558658, 0.558688, 0.558695, 0.558716", \ + "0.558603, 0.558592, 0.558588, 0.558609, 0.558635, 0.558662", \ + "0.55897, 0.558915, 0.558835, 0.558829, 0.558827, 0.558826", \ + "0.55556, 0.556072, 0.555864, 0.557266, 0.557022, 0.555977", \ + "0.556987, 0.555768, 0.555751, 0.556051, 0.555981, 0.556225" \ + ); + } + } + internal_power () { + related_pin : "pad"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0078322, 0.00787005, 0.00831937, 0.00819289, 0.00789115, 0.00748509", \ + "0.00709908, 0.00714296, 0.00716944, 0.00724276, 0.00667413, 0.00621001", \ + "0.00655204, 0.0069022, 0.00636012, 0.0064819, 0.00623889, 0.00534736", \ + "0.00632089, 0.00608538, 0.00649606, 0.00603276, 0.00555201, 0.00543066", \ + "0.00684486, 0.0061793, 0.00580999, 0.0052102, 0.00529618, 0.00548668", \ + "0.00981999, 0.00813946, 0.00704241, 0.00606651, 0.00651294, 0.00417448", \ + "0.0128923, 0.0110895, 0.00989644, 0.00878784, 0.0079245, 0.0053965" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0624906, 0.0612648, 0.060852, 0.060898, 0.0609522, 0.0610116", \ + "0.0610536, 0.0598201, 0.0593151, 0.059293, 0.0593525, 0.0593884", \ + "0.0599115, 0.0586969, 0.0581567, 0.0581056, 0.0581046, 0.0581689", \ + "0.0600354, 0.0587978, 0.0582632, 0.0582114, 0.0582222, 0.0582732", \ + "0.0597826, 0.0584436, 0.0577657, 0.0575982, 0.0575792, 0.0575981", \ + "0.062575, 0.0606733, 0.059325, 0.0588866, 0.0584911, 0.0584078", \ + "0.0677941, 0.0642586, 0.0618091, 0.060744, 0.0605362, 0.0601573" \ + ); + } + } + } + pin (c2p) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.016; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0266293; + rise_capacitance : 0.0268779; + rise_capacitance_range (0.0224464, 0.0317239); + fall_capacitance : 0.0263806; + fall_capacitance_range (0.0229772, 0.0284049); + internal_power () { + when : "(!c2p_en * pad * p2c)"; + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-1.1772e-05, -3.30965e-08, -3.1608e-07, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "1.1772e-05, 3.30965e-08, 3.1608e-07, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + when : "(!c2p_en * pad * p2c)"; + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0201437, -0.0212464, -0.0213443, -0.0213888, -0.0217584, -0.021855, -0.0216817" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0251577, 0.024708, 0.0247034, 0.0245273, 0.0246058, 0.0245069, 0.0244758" \ + ); + } + } + internal_power () { + when : "(!c2p_en * !pad * !p2c)"; + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-1.17475e-05, -1.12543e-08, -3.10495e-07, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "1.17475e-05, 1.12543e-08, 3.10495e-07, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + when : "(!c2p_en * !pad * !p2c)"; + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.020143, -0.0212459, -0.0213437, -0.0213883, -0.021758, -0.0218549, -0.0216817" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.025157, 0.0247071, 0.0247029, 0.024527, 0.0246057, 0.0245068, 0.0244758" \ + ); + } + } + internal_power () { + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-1.17475e-05, -1.12543e-08, -3.10495e-07, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "1.17475e-05, 1.12543e-08, 3.10495e-07, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.020143, -0.0212459, -0.0213437, -0.0213883, -0.021758, -0.0218549, -0.0216817" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.025157, 0.0247071, 0.0247029, 0.024527, 0.0246057, 0.0245068, 0.0244758" \ + ); + } + } + } + pin (c2p_en) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.011; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0249992; + rise_capacitance : 0.0260044; + rise_capacitance_range (0.0216574, 0.0320201); + fall_capacitance : 0.023994; + fall_capacitance_range (0.0206001, 0.0281688); + internal_power () { + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "1.29844, 1.29831, 1.29895, 1.2997, 1.29918, 1.29736, 1.30505" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.214585, 0.214202, 0.214106, 0.213919, 0.213357, 0.211437, 0.212075" \ + ); + } + } + internal_power () { + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0461541, 0.0454655, 0.0462313, 0.0507188, 0.0613582, 0.0854665, 0.133411" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.098293, 0.0975189, 0.0994431, 0.103454, 0.11414, 0.139852, 0.18681" \ + ); + } + } + } + } + cell (sg13g2_IOPadInOut30mA) { + pad_cell : true; + area : 14400; + cell_footprint : "inout"; + pad_drivers : 1; + bond_pads : 1; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 9164.97; + when : "!c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 12748.7; + when : "!c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 9164.97; + when : "!c2p_en&c2p&!pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 12931.7; + when : "!c2p_en&c2p&!pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 355.716; + when : "!c2p_en&!c2p&pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 10834.4; + when : "!c2p_en&!c2p&pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 355.715; + when : "!c2p_en&c2p&pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 11016.9; + when : "!c2p_en&c2p&pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 511.094; + when : "c2p_en&c2p&pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 16169.6; + when : "c2p_en&c2p&pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 511.094; + when : "c2p_en&c2p&pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 16169.6; + when : "c2p_en&c2p&pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 9013.42; + when : "c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 17607.4; + when : "c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 9013.42; + when : "c2p_en&!c2p&!pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 17607.4; + when : "c2p_en&!c2p&!pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 4761.3; + related_pg_pin : iovdd; + } + leakage_power () { + value : 14385.7; + related_pg_pin : vdd; + } + pin (pad) { + direction : "inout"; + is_pad : true; + function : "c2p"; + three_state : "c2p_en'"; + drive_current : 30; + output_voltage : "pad"; + input_voltage : "pad"; + related_ground_pin : iovss; + related_power_pin : iovdd; + max_capacitance : 0.454808; + capacitance : 0.366392; + rise_capacitance : 0.362351; + rise_capacitance_range (0.330303, 0.386121); + fall_capacitance : 0.370432; + fall_capacitance_range (0.346295, 0.387266); + timing () { + related_pin : "c2p"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.50015, 2.7092, 2.87938, 3.02747, 3.40368, 3.72997", \ + "2.51843, 2.72711, 2.89717, 3.04537, 3.42146, 3.7475", \ + "2.52762, 2.73576, 2.90565, 3.05384, 3.43004, 3.75565", \ + "2.54099, 2.7497, 2.91961, 3.06781, 3.44393, 3.77", \ + "2.56013, 2.76834, 2.93824, 3.08578, 3.46192, 3.78788", \ + "2.57756, 2.78653, 2.95671, 3.10491, 3.4811, 3.80711", \ + "2.58106, 2.79097, 2.96171, 3.11003, 3.48673, 3.81314" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.746966, 0.987594, 1.19296, 1.38368, 1.91914, 2.4427", \ + "0.746967, 0.987595, 1.19297, 1.38381, 1.91929, 2.44271", \ + "0.746968, 0.987596, 1.19298, 1.38382, 1.9194, 2.44272", \ + "0.746969, 0.987597, 1.19299, 1.38383, 1.91941, 2.44273", \ + "0.74697, 0.987598, 1.193, 1.38384, 1.91942, 2.44274", \ + "0.746971, 0.987599, 1.19342, 1.38385, 1.91943, 2.44275", \ + "0.749588, 0.989691, 1.19468, 1.38501, 1.91944, 2.44306" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.05482, 2.18334, 2.30252, 2.41357, 2.71315, 2.98927", \ + "2.07371, 2.20323, 2.32089, 2.43155, 2.73172, 3.00758", \ + "2.0889, 2.21801, 2.33553, 2.44607, 2.74787, 3.02179", \ + "2.12286, 2.25201, 2.36911, 2.47992, 2.78187, 3.05562", \ + "2.18077, 2.30931, 2.42792, 2.53887, 2.83826, 3.1144", \ + "2.26514, 2.39506, 2.51422, 2.62344, 2.92462, 3.20101", \ + "2.41883, 2.54882, 2.66716, 2.77727, 3.07767, 3.35301" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.35966, 1.45713, 1.5822, 1.71155, 2.09981, 2.5175", \ + "1.36442, 1.4657, 1.58517, 1.71156, 2.10193, 2.51751", \ + "1.36814, 1.4694, 1.58894, 1.71536, 2.10568, 2.5178", \ + "1.37467, 1.4749, 1.59148, 1.72017, 2.10989, 2.52093", \ + "1.37688, 1.47491, 1.5963, 1.72477, 2.11141, 2.52773", \ + "1.37689, 1.47492, 1.59631, 1.72478, 2.11142, 2.52774", \ + "1.3769, 1.47493, 1.59632, 1.72479, 2.11143, 2.52775" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : negative_unate; + timing_type : three_state_disable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.83824, 1.83825, 1.83826, 1.83827, 1.83828, 1.83829", \ + "1.85888, 1.85889, 1.8589, 1.85891, 1.85892, 1.85893", \ + "1.87164, 1.87165, 1.87166, 1.87167, 1.87168, 1.87169", \ + "1.8986, 1.89861, 1.89862, 1.89863, 1.89864, 1.89865", \ + "1.93642, 1.93643, 1.93644, 1.93645, 1.93646, 1.93647", \ + "1.99555, 1.99556, 1.99557, 1.99558, 1.99559, 1.9956", \ + "2.08382, 2.08383, 2.08384, 2.08385, 2.08386, 2.08387" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.83824, 1.83825, 1.83826, 1.83827, 1.83828, 1.83829", \ + "1.85888, 1.85889, 1.8589, 1.85891, 1.85892, 1.85893", \ + "1.87164, 1.87165, 1.87166, 1.87167, 1.87168, 1.87169", \ + "1.8986, 1.89861, 1.89862, 1.89863, 1.89864, 1.89865", \ + "1.93642, 1.93643, 1.93644, 1.93645, 1.93646, 1.93647", \ + "1.99555, 1.99556, 1.99557, 1.99558, 1.99559, 1.9956", \ + "2.08382, 2.08383, 2.08384, 2.08385, 2.08386, 2.08387" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.46431, 2.46432, 2.46433, 2.46434, 2.46435, 2.46436", \ + "2.48572, 2.48573, 2.48574, 2.48575, 2.48576, 2.48577", \ + "2.50314, 2.50443, 2.50444, 2.50445, 2.50446, 2.50447", \ + "2.5414, 2.54141, 2.54141, 2.54142, 2.54143, 2.54144", \ + "2.57833, 2.59919, 2.5992, 2.59921, 2.59922, 2.59923", \ + "2.66143, 2.66144, 2.66145, 2.66146, 2.66147, 2.66148", \ + "2.8165, 2.81651, 2.81652, 2.81653, 2.81654, 2.81655" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.46431, 2.46432, 2.46433, 2.46434, 2.46435, 2.46436", \ + "2.48572, 2.48573, 2.48574, 2.48575, 2.48576, 2.48577", \ + "2.50314, 2.50443, 2.50444, 2.50445, 2.50446, 2.50447", \ + "2.5414, 2.54141, 2.54141, 2.54142, 2.54143, 2.54144", \ + "2.57833, 2.59919, 2.5992, 2.59921, 2.59922, 2.59923", \ + "2.66143, 2.66144, 2.66145, 2.66146, 2.66147, 2.66148", \ + "2.8165, 2.81651, 2.81652, 2.81653, 2.81654, 2.81655" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : positive_unate; + timing_type : three_state_enable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.45662, 2.67973, 2.85543, 3.00713, 3.38959, 3.71826", \ + "2.47221, 2.69502, 2.87101, 3.02252, 3.40454, 3.73398", \ + "2.4839, 2.7071, 2.88125, 3.03265, 3.41535, 3.74567", \ + "2.49845, 2.72168, 2.89735, 3.04905, 3.43111, 3.76201", \ + "2.52111, 2.74417, 2.92049, 3.07187, 3.45364, 3.78352", \ + "2.54243, 2.76544, 2.94145, 3.09308, 3.47499, 3.80553", \ + "2.55598, 2.77881, 2.95465, 3.106, 3.48841, 3.81886" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.798432, 1.02066, 1.21645, 1.4021, 1.92842, 2.44612", \ + "0.798433, 1.02124, 1.2171, 1.40211, 1.92843, 2.44613", \ + "0.799156, 1.02129, 1.21711, 1.40212, 1.92848, 2.4463", \ + "0.799157, 1.0213, 1.21712, 1.40213, 1.92849, 2.44784", \ + "0.800155, 1.02219, 1.21779, 1.40214, 1.9285, 2.44785", \ + "0.800156, 1.0222, 1.2178, 1.40215, 1.92851, 2.44786", \ + "0.800157, 1.02221, 1.21781, 1.40216, 1.92852, 2.44787" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.48037, 1.65539, 1.79968, 1.92779, 2.26397, 2.56465", \ + "1.4968, 1.67182, 1.81582, 1.94424, 2.28028, 2.58095", \ + "1.50591, 1.68079, 1.82507, 1.95336, 2.28933, 2.59", \ + "1.51851, 1.69309, 1.83846, 1.96829, 2.30049, 2.60283", \ + "1.53454, 1.70956, 1.85588, 1.98195, 2.31828, 2.61902", \ + "1.54608, 1.71967, 1.86434, 1.99135, 2.32827, 2.63006", \ + "1.54609, 1.71968, 1.86435, 1.99136, 2.32897, 2.6314" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.618317, 0.816909, 0.991736, 1.16662, 1.66177, 2.15491", \ + "0.618329, 0.816945, 0.993554, 1.16712, 1.66206, 2.15586", \ + "0.61833, 0.816946, 0.993555, 1.16713, 1.66207, 2.15587", \ + "0.618331, 0.816947, 0.993556, 1.17076, 1.66457, 2.15877", \ + "0.618332, 0.816948, 0.993557, 1.17077, 1.66458, 2.15878", \ + "0.618333, 0.816949, 0.994625, 1.17078, 1.66543, 2.1588", \ + "0.618334, 0.81695, 0.994626, 1.17079, 1.66544, 2.16015" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "8.11869, 7.96559, 7.8789, 7.83642, 7.71156, 7.65423", \ + "8.14203, 7.97941, 7.89402, 7.84929, 7.72998, 7.65576", \ + "8.14982, 7.98, 7.88808, 7.84512, 7.72083, 7.64175", \ + "8.13297, 7.97571, 7.89444, 7.83213, 7.72059, 7.64724", \ + "8.14256, 7.97465, 7.88511, 7.84314, 7.71255, 7.66308", \ + "8.12326, 7.96856, 7.89318, 7.82826, 7.71054, 7.6641", \ + "8.06918, 7.92539, 7.84911, 7.80951, 7.69374, 7.63047" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "41.5016, 38.9145, 36.7673, 34.9366, 30.7979, 27.8472", \ + "41.697, 39.0764, 36.9666, 35.1193, 30.971, 27.9854", \ + "41.8823, 39.2477, 37.1256, 35.2978, 31.0708, 28.1321", \ + "42.1481, 39.5032, 37.3761, 35.5343, 31.2786, 28.3189", \ + "42.2324, 39.6269, 37.4427, 35.5849, 31.3804, 28.3772", \ + "42.0629, 39.4441, 37.2721, 35.4599, 31.224, 28.2353", \ + "41.4841, 38.9006, 36.7816, 34.9558, 30.8305, 27.877" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.85967, 3.67195, 5.46978, 7.26592, 12.4481, 13.6689", \ + "1.85983, 3.67128, 5.46982, 7.26574, 12.4446, 13.5762", \ + "1.85935, 3.67124, 5.47056, 7.27447, 12.4295, 13.5792", \ + "1.86412, 3.67658, 5.47678, 7.26554, 12.4131, 13.4015", \ + "1.88081, 3.69373, 5.49294, 7.2869, 12.4679, 13.283", \ + "1.9198, 3.73311, 5.53191, 7.3225, 12.3898, 12.8337", \ + "2.006, 3.81858, 5.61837, 7.41201, 12.2698, 11.8706" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.206712, 0.206291, 0.206073, 0.206109, 0.205844, 0.204779", \ + "0.204298, 0.204039, 0.20379, 0.203652, 0.203538, 0.202316", \ + "0.205558, 0.205198, 0.204891, 0.204847, 0.204767, 0.203657", \ + "0.211611, 0.211234, 0.210922, 0.210874, 0.210799, 0.209767", \ + "0.228407, 0.228024, 0.227772, 0.227691, 0.227538, 0.226539", \ + "0.268018, 0.267645, 0.26746, 0.267301, 0.267247, 0.265863", \ + "0.353205, 0.352776, 0.352623, 0.352427, 0.35229, 0.350138" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "7.21427, 7.21239, 7.20339, 7.21491, 7.25175, 7.29588", \ + "7.21241, 7.20382, 7.21314, 7.21419, 7.22046, 7.29228", \ + "7.21356, 7.21032, 7.2024, 7.21092, 7.24935, 7.29087", \ + "7.21142, 7.2094, 7.20108, 7.21002, 7.22655, 7.30632", \ + "7.2098, 7.20218, 7.21263, 7.21752, 7.2246, 7.29273", \ + "7.21328, 7.20262, 7.20519, 7.22118, 7.23123, 7.30629", \ + "7.21917, 7.21799, 7.20573, 7.2246, 7.25901, 7.32363" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "3.33233, 3.33331, 3.33072, 3.33312, 3.33026, 3.3264", \ + "3.33247, 3.33345, 3.33138, 3.33334, 3.33031, 3.32641", \ + "3.33245, 3.33342, 3.33144, 3.33326, 3.33034, 3.32649", \ + "3.3284, 3.32968, 3.33241, 3.33698, 3.32901, 3.32617", \ + "3.33234, 3.33344, 3.33321, 3.33323, 3.33046, 3.32661", \ + "3.32802, 3.33113, 3.33158, 3.33009, 3.32758, 3.32454", \ + "3.32375, 3.32772, 3.3297, 3.32917, 3.32834, 3.32419" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.82767, 3.63905, 5.44072, 7.24566, 12.472, 13.7226", \ + "1.82612, 3.63764, 5.43719, 7.23151, 12.4236, 13.5829", \ + "1.83046, 3.64057, 5.44241, 7.23483, 12.4545, 13.5337", \ + "1.83878, 3.64896, 5.45075, 7.24285, 12.4641, 13.4006", \ + "1.85726, 3.67073, 5.4694, 7.27744, 12.4507, 13.2861", \ + "1.90134, 3.71308, 5.51507, 7.30958, 12.375, 12.8457", \ + "1.99163, 3.80579, 5.61289, 7.39817, 12.2519, 11.8478" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.105315, 0.104987, 0.104868, 0.104686, 0.104381, 0.101439", \ + "0.104223, 0.103895, 0.103628, 0.103575, 0.103267, 0.10018", \ + "0.105416, 0.104999, 0.104864, 0.10478, 0.104377, 0.101291", \ + "0.109856, 0.109576, 0.109404, 0.109424, 0.108877, 0.105789", \ + "0.120529, 0.120191, 0.120184, 0.119891, 0.119542, 0.11613", \ + "0.143655, 0.143237, 0.143144, 0.142884, 0.14256, 0.138704", \ + "0.191607, 0.191219, 0.190803, 0.190729, 0.190318, 0.185381" \ + ); + } + } + } + pin (p2c) { + direction : "output"; + output_voltage : "core"; + function : "pad"; + related_ground_pin : vss; + related_power_pin : vdd; + max_capacitance : 0.734132; + timing () { + related_pin : "pad"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.112227, 0.132287, 0.169796, 0.206216, 0.242408, 0.278562", \ + "0.114287, 0.135814, 0.174984, 0.212089, 0.248321, 0.284502", \ + "0.114288, 0.135815, 0.174985, 0.21209, 0.248322, 0.284503", \ + "0.114289, 0.135816, 0.174986, 0.212091, 0.248323, 0.284504", \ + "0.11429, 0.135817, 0.174987, 0.212092, 0.248324, 0.284505", \ + "0.114291, 0.135818, 0.174988, 0.212093, 0.248325, 0.284506", \ + "0.114292, 0.135819, 0.174989, 0.212094, 0.248326, 0.284507" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0696547, 0.106106, 0.180878, 0.25691, 0.333345, 0.410361", \ + "0.0763819, 0.113247, 0.186816, 0.261996, 0.337672, 0.413808", \ + "0.0840152, 0.120039, 0.193755, 0.26943, 0.344459, 0.42018", \ + "0.0875126, 0.123088, 0.196498, 0.27113, 0.346882, 0.422489", \ + "0.104662, 0.138838, 0.208199, 0.280561, 0.354183, 0.429071", \ + "0.134238, 0.168088, 0.23482, 0.304024, 0.374824, 0.446177", \ + "0.158422, 0.192624, 0.257779, 0.322823, 0.390825, 0.460226" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.400321, 0.428252, 0.47216, 0.510165, 0.545058, 0.578147", \ + "0.441077, 0.468758, 0.512857, 0.550878, 0.585808, 0.618618", \ + "0.547817, 0.575678, 0.620049, 0.657805, 0.691785, 0.724849", \ + "0.608941, 0.636671, 0.680676, 0.718887, 0.753596, 0.785919", \ + "0.910683, 0.938359, 0.982757, 1.01998, 1.05448, 1.08749", \ + "1.50936, 1.53737, 1.58172, 1.61938, 1.65327, 1.68599", \ + "2.02942, 2.06033, 2.10827, 2.14785, 2.18337, 2.21747" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.126223, 0.155046, 0.206998, 0.258551, 0.310136, 0.362187", \ + "0.126265, 0.155047, 0.206999, 0.258552, 0.310137, 0.362188", \ + "0.126266, 0.155048, 0.207061, 0.258553, 0.310138, 0.362189", \ + "0.126267, 0.155049, 0.207062, 0.258554, 0.310139, 0.36219", \ + "0.126268, 0.15505, 0.207277, 0.258555, 0.31014, 0.362191", \ + "0.143931, 0.170744, 0.220772, 0.269684, 0.318661, 0.370181", \ + "0.173268, 0.200193, 0.248923, 0.295172, 0.342879, 0.390986" \ + ); + } + } + internal_power () { + related_pin : "pad"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "-1.05869, -1.061, -1.06098, -1.06096, -1.061, -1.06106", \ + "-1.06364, -1.06359, -1.06444, -1.06346, -1.05829, -1.06441", \ + "-1.06343, -1.06347, -1.06346, -1.06349, -1.06344, -1.06345", \ + "-1.06331, -1.06334, -1.0633, -1.06335, -1.06227, -1.06332", \ + "-1.06406, -1.06395, -1.05978, -1.06377, -1.06371, -1.06373", \ + "-1.05797, -1.05875, -1.05835, -1.05973, -1.06053, -1.05854", \ + "-1.05931, -1.05854, -1.05848, -1.05917, -1.05857, -1.05928" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "1.06111, 1.06102, 1.06098, 1.06096, 1.061, 1.06106", \ + "1.06442, 1.06441, 1.06444, 1.06444, 1.06448, 1.06441", \ + "1.06343, 1.06347, 1.06346, 1.06349, 1.06344, 1.06345", \ + "1.06331, 1.06334, 1.0633, 1.06335, 1.06329, 1.06332", \ + "1.06406, 1.06395, 1.06384, 1.06377, 1.06371, 1.06373", \ + "1.05797, 1.05875, 1.05835, 1.05973, 1.06053, 1.05854", \ + "1.06098, 1.05854, 1.05848, 1.05917, 1.05857, 1.05928" \ + ); + } + } + internal_power () { + related_pin : "pad"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.00769042, 0.00787775, 0.00832396, 0.00826971, 0.00784147, 0.00761428", \ + "0.00709457, 0.00722458, 0.00726286, 0.00726058, 0.00665955, 0.00635176", \ + "0.00652682, 0.00679972, 0.00642559, 0.0063546, 0.00614331, 0.00532063", \ + "0.00632057, 0.00611968, 0.00678766, 0.00611565, 0.00583173, 0.00529417", \ + "0.00692264, 0.00613277, 0.00546588, 0.00535411, 0.00522544, 0.00541311", \ + "0.00982005, 0.00826979, 0.00704308, 0.00654441, 0.00653953, 0.00433324", \ + "0.0128403, 0.0110496, 0.00974578, 0.00846613, 0.00728271, 0.00566367" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0624957, 0.0612838, 0.0608508, 0.0608988, 0.0609733, 0.0610226", \ + "0.0610688, 0.0597991, 0.0593076, 0.0593104, 0.0593593, 0.0593854", \ + "0.0599177, 0.0586851, 0.0581682, 0.0581098, 0.0581092, 0.0581729", \ + "0.0600226, 0.0587754, 0.0582498, 0.0581993, 0.0582068, 0.0582586", \ + "0.059784, 0.0584445, 0.0577668, 0.057599, 0.0575789, 0.0575954", \ + "0.0625727, 0.0606631, 0.0593266, 0.0588869, 0.0584844, 0.0584006", \ + "0.0672391, 0.0637501, 0.0616943, 0.0607931, 0.0602847, 0.0597709" \ + ); + } + } + } + pin (c2p) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.016; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0266293; + rise_capacitance : 0.0268779; + rise_capacitance_range (0.0224465, 0.031724); + fall_capacitance : 0.0263806; + fall_capacitance_range (0.0229773, 0.0284048); + internal_power () { + when : "(!c2p_en * pad * p2c)"; + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-1.15239e-05, 0, 0, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "1.15239e-05, 0, 0, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + when : "(!c2p_en * pad * p2c)"; + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0201437, -0.0212464, -0.0213441, -0.0213888, -0.0217584, -0.021855, -0.0216817" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0251577, 0.0247079, 0.0247034, 0.0245273, 0.0246058, 0.0245069, 0.0244758" \ + ); + } + } + internal_power () { + when : "(!c2p_en * !pad * !p2c)"; + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-1.14948e-05, 0, 0, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "1.14948e-05, 0, 0, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + when : "(!c2p_en * !pad * !p2c)"; + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.020143, -0.0212459, -0.0213436, -0.0213883, -0.021758, -0.0218549, -0.0216817" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.025157, 0.0247071, 0.0247029, 0.024527, 0.0246057, 0.0245068, 0.0244758" \ + ); + } + } + internal_power () { + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-1.14948e-05, 0, 0, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "1.14948e-05, 0, 0, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.020143, -0.0212459, -0.0213436, -0.0213883, -0.021758, -0.0218549, -0.0216817" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.025157, 0.0247071, 0.0247029, 0.024527, 0.0246057, 0.0245068, 0.0244758" \ + ); + } + } + } + pin (c2p_en) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.011; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0249966; + rise_capacitance : 0.0259992; + rise_capacitance_range (0.0216574, 0.0319883); + fall_capacitance : 0.023994; + fall_capacitance_range (0.0206002, 0.0281567); + internal_power () { + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "2.04899, 2.05281, 2.04971, 2.04899, 2.04985, 2.04809, 2.05404" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.206963, 0.206576, 0.206522, 0.206307, 0.205823, 0.203664, 0.204294" \ + ); + } + } + internal_power () { + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0461632, 0.0454731, 0.0462396, 0.0507269, 0.061366, 0.085475, 0.133318" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0982906, 0.09752, 0.0994445, 0.103452, 0.11414, 0.139847, 0.186706" \ + ); + } + } + } + } + cell (sg13g2_IOPadInOut4mA) { + pad_cell : true; + area : 14400; + cell_footprint : "inout"; + pad_drivers : 1; + bond_pads : 1; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 1628.85; + when : "!c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 12749.6; + when : "!c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 1628.65; + when : "!c2p_en&c2p&!pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 12932.7; + when : "!c2p_en&c2p&!pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 383.936; + when : "!c2p_en&!c2p&pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 10835.8; + when : "!c2p_en&!c2p&pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 383.972; + when : "!c2p_en&c2p&pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 11018.3; + when : "!c2p_en&c2p&pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 535.914; + when : "c2p_en&c2p&pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 16171.1; + when : "c2p_en&c2p&pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 535.808; + when : "c2p_en&c2p&pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 16171.1; + when : "c2p_en&c2p&pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 1477.11; + when : "c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 17608.4; + when : "c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 1477.1; + when : "c2p_en&!c2p&!pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 17608.4; + when : "c2p_en&!c2p&!pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 1006.42; + related_pg_pin : iovdd; + } + leakage_power () { + value : 14386.9; + related_pg_pin : vdd; + } + pin (pad) { + direction : "inout"; + is_pad : true; + function : "c2p"; + three_state : "c2p_en'"; + drive_current : 4; + output_voltage : "pad"; + input_voltage : "pad"; + related_ground_pin : iovss; + related_power_pin : iovdd; + max_capacitance : 0.635156; + capacitance : 0.190513; + rise_capacitance : 0.192788; + rise_capacitance_range (0.163654, 0.213783); + fall_capacitance : 0.188238; + fall_capacitance_range (0.166647, 0.202518); + timing () { + related_pin : "c2p"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.27181, 2.94125, 3.6069, 4.27185, 6.26549, 8.25854", \ + "2.2871, 2.9562, 3.6218, 4.28671, 6.2804, 8.27338", \ + "2.29684, 2.96618, 3.6319, 4.29685, 6.29049, 8.28361", \ + "2.31248, 2.98125, 3.64688, 4.31182, 6.30542, 8.2985", \ + "2.33022, 2.99899, 3.66464, 4.32958, 6.32318, 8.31587", \ + "2.34901, 3.01791, 3.68362, 4.34862, 6.34212, 8.33521", \ + "2.35439, 3.02344, 3.68907, 4.35404, 6.3481, 8.34096" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.74459, 3.11765, 4.5059, 5.89537, 10.0752, 14.2327", \ + "1.7446, 3.11766, 4.50591, 5.89629, 10.0753, 14.2518", \ + "1.74461, 3.11767, 4.50592, 5.8963, 10.0754, 14.2519", \ + "1.74462, 3.1177, 4.50593, 5.89656, 10.0755, 14.252", \ + "1.74463, 3.11771, 4.50594, 5.89657, 10.0756, 14.2521", \ + "1.74464, 3.11772, 4.50595, 5.89687, 10.0757, 14.2522", \ + "1.74505, 3.11773, 4.50596, 5.89688, 10.0758, 14.2523" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.73858, 2.40099, 3.06251, 3.72461, 5.71035, 7.69453", \ + "1.7551, 2.41715, 3.07853, 3.74099, 5.72842, 7.70788", \ + "1.76897, 2.43088, 3.09212, 3.75296, 5.74235, 7.72133", \ + "1.80074, 2.46222, 3.12313, 3.78511, 5.76923, 7.75214", \ + "1.85641, 2.51782, 3.17879, 3.84052, 5.82468, 7.80701", \ + "1.9446, 2.60625, 3.26742, 3.92845, 5.91458, 7.89604", \ + "2.104, 2.76647, 3.42831, 4.08959, 6.07312, 8.05742" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.62734, 2.92597, 4.2294, 5.54341, 9.46822, 13.4005", \ + "1.62735, 2.92598, 4.23601, 5.54342, 9.48165, 13.4056", \ + "1.62736, 2.92599, 4.23602, 5.54343, 9.48293, 13.4057", \ + "1.62737, 2.926, 4.23603, 5.54344, 9.48294, 13.4064", \ + "1.62738, 2.92601, 4.23604, 5.54555, 9.48295, 13.4065", \ + "1.62739, 2.92892, 4.23605, 5.54556, 9.48296, 13.4082", \ + "1.62823, 2.92893, 4.23606, 5.54557, 9.48297, 13.4131" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : negative_unate; + timing_type : three_state_disable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.30357, 1.30358, 1.30359, 1.3036, 1.30361, 1.30362", \ + "1.32474, 1.32475, 1.32476, 1.32477, 1.32478, 1.32479", \ + "1.33831, 1.33832, 1.33833, 1.33834, 1.33835, 1.33836", \ + "1.36505, 1.36506, 1.36507, 1.36508, 1.36509, 1.3651", \ + "1.40181, 1.40182, 1.40183, 1.40184, 1.40185, 1.40186", \ + "1.46152, 1.46153, 1.46154, 1.46155, 1.46156, 1.46157", \ + "1.55503, 1.55504, 1.55505, 1.55506, 1.55507, 1.55508" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.30357, 1.30358, 1.30359, 1.3036, 1.30361, 1.30362", \ + "1.32474, 1.32475, 1.32476, 1.32477, 1.32478, 1.32479", \ + "1.33831, 1.33832, 1.33833, 1.33834, 1.33835, 1.33836", \ + "1.36505, 1.36506, 1.36507, 1.36508, 1.36509, 1.3651", \ + "1.40181, 1.40182, 1.40183, 1.40184, 1.40185, 1.40186", \ + "1.46152, 1.46153, 1.46154, 1.46155, 1.46156, 1.46157", \ + "1.55503, 1.55504, 1.55505, 1.55506, 1.55507, 1.55508" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.862948, 0.862949, 0.86295, 0.862951, 0.862952, 0.862953", \ + "0.884583, 0.884584, 0.884585, 0.884586, 0.884587, 0.884588", \ + "0.903566, 0.903682, 0.903683, 0.903684, 0.903685, 0.903686", \ + "0.939685, 0.939686, 0.939687, 0.939688, 0.93969, 0.939691", \ + "0.997272, 0.997273, 0.997274, 0.997275, 0.997276, 0.997277", \ + "1.07353, 1.07354, 1.07355, 1.07356, 1.07357, 1.07358", \ + "1.21265, 1.21266, 1.21267, 1.21268, 1.21269, 1.2127" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.862948, 0.862949, 0.86295, 0.862951, 0.862952, 0.862953", \ + "0.884583, 0.884584, 0.884585, 0.884586, 0.884587, 0.884588", \ + "0.903566, 0.903682, 0.903683, 0.903684, 0.903685, 0.903686", \ + "0.939685, 0.939686, 0.939687, 0.939688, 0.93969, 0.939691", \ + "0.997272, 0.997273, 0.997274, 0.997275, 0.997276, 0.997277", \ + "1.07353, 1.07354, 1.07355, 1.07356, 1.07357, 1.07358", \ + "1.21265, 1.21266, 1.21267, 1.21268, 1.21269, 1.2127" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : positive_unate; + timing_type : three_state_enable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.27714, 2.96336, 3.64666, 4.32929, 6.3764, 8.4231", \ + "2.29327, 2.9785, 3.66172, 4.34437, 6.3915, 8.43803", \ + "2.30275, 2.98923, 3.67252, 4.3552, 6.4023, 8.44892", \ + "2.31907, 3.00522, 3.68851, 4.37116, 6.41842, 8.46516", \ + "2.33972, 3.02626, 3.70954, 4.39221, 6.43948, 8.48585", \ + "2.36286, 3.04906, 3.73247, 4.41515, 6.46214, 8.50888", \ + "2.37446, 3.06014, 3.74344, 4.4261, 6.4731, 8.5198" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.74374, 3.11591, 4.50122, 5.89245, 10.062, 14.2522", \ + "1.74439, 3.11592, 4.5019, 5.89655, 10.0741, 14.2523", \ + "1.7444, 3.11602, 4.50355, 5.89656, 10.0742, 14.2524", \ + "1.74441, 3.11649, 4.50356, 5.89657, 10.0753, 14.2525", \ + "1.74442, 3.1165, 4.50357, 5.89658, 10.0754, 14.2526", \ + "1.74443, 3.11662, 4.50358, 5.89659, 10.0755, 14.2527", \ + "1.74444, 3.11663, 4.50359, 5.89685, 10.0756, 14.2528" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.72816, 2.41179, 3.09476, 3.77708, 5.82517, 7.86694", \ + "1.74441, 2.42786, 3.11029, 3.79348, 5.84076, 7.88245", \ + "1.75353, 2.43698, 3.11942, 3.80274, 5.84942, 7.89298", \ + "1.76608, 2.44953, 3.13197, 3.81526, 5.86118, 7.9032", \ + "1.78294, 2.46639, 3.14888, 3.83042, 5.87652, 7.91999", \ + "1.79236, 2.47597, 3.15886, 3.84131, 5.88493, 7.93214", \ + "1.79682, 2.48009, 3.16199, 3.84418, 5.88641, 7.93334" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.62652, 2.92165, 4.23241, 5.54448, 9.47537, 13.4021", \ + "1.62656, 2.92438, 4.23277, 5.54449, 9.47925, 13.4218", \ + "1.62657, 2.92439, 4.23282, 5.54493, 9.48628, 13.4219", \ + "1.62658, 2.9244, 4.23284, 5.54494, 9.49334, 13.422", \ + "1.62666, 2.92441, 4.23315, 5.54495, 9.49335, 13.4221", \ + "1.62667, 2.92523, 4.23316, 5.54496, 9.49336, 13.4222", \ + "1.62846, 2.92524, 4.23566, 5.54497, 9.49337, 13.4223" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.85209, 2.83454, 2.80538, 2.77764, 2.71962, 2.55084", \ + "2.85312, 2.83588, 2.7996, 2.781, 2.7114, 2.63793", \ + "2.85247, 2.83605, 2.80592, 2.77755, 2.71965, 2.62533", \ + "2.85096, 2.83009, 2.80269, 2.78796, 2.65128, 2.54844", \ + "2.85032, 2.83063, 2.80239, 2.77905, 2.63604, 2.62443", \ + "2.84999, 2.82757, 2.79903, 2.7777, 2.65101, 2.55114", \ + "2.83959, 2.82366, 2.79499, 2.76936, 2.66031, 2.6145" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.42701, 1.42026, 1.41628, 1.41455, 1.41192, 1.4106", \ + "1.43052, 1.42252, 1.41803, 1.41585, 1.4128, 1.41099", \ + "1.43278, 1.4229, 1.4191, 1.4166, 1.41293, 1.41091", \ + "1.44081, 1.42915, 1.42283, 1.41995, 1.41464, 1.41244", \ + "1.44195, 1.42919, 1.42281, 1.42039, 1.41483, 1.41266", \ + "1.4342, 1.42391, 1.41804, 1.41521, 1.41104, 1.40877", \ + "1.43024, 1.42229, 1.42049, 1.41909, 1.416, 1.41495" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.86799, 3.67911, 5.48853, 7.29285, 12.7231, 18.1469", \ + "1.86392, 3.67572, 5.48426, 7.29697, 12.7201, 18.1508", \ + "1.86479, 3.68183, 5.48784, 7.29236, 12.7224, 18.1309", \ + "1.87061, 3.68411, 5.49354, 7.30115, 12.7325, 18.152", \ + "1.88707, 3.69923, 5.50987, 7.31718, 12.7462, 18.1847", \ + "1.92594, 3.73777, 5.54814, 7.34919, 12.7848, 18.2185", \ + "2.01273, 3.82617, 5.63521, 7.44579, 12.8716, 18.3093" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.206481, 0.206474, 0.206782, 0.206974, 0.208546, 0.208209", \ + "0.204335, 0.204367, 0.204581, 0.205411, 0.205653, 0.207582", \ + "0.205541, 0.205372, 0.206011, 0.206197, 0.207211, 0.208333", \ + "0.211416, 0.211548, 0.211676, 0.212253, 0.213267, 0.214888", \ + "0.228269, 0.228291, 0.228332, 0.229004, 0.229851, 0.23084", \ + "0.26789, 0.267677, 0.268141, 0.268615, 0.270339, 0.271647", \ + "0.352945, 0.353081, 0.353345, 0.353916, 0.354976, 0.356958" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.69481, 2.79448, 2.8916, 2.98569, 3.25203, 3.61293", \ + "2.69817, 2.78893, 2.88602, 2.99604, 3.29904, 3.60903", \ + "2.68783, 2.79153, 2.8916, 2.99919, 3.24477, 3.60774", \ + "2.69423, 2.79601, 2.88264, 2.99493, 3.31383, 3.52068", \ + "2.69209, 2.80237, 2.89487, 3.00399, 3.25152, 3.55884", \ + "2.69745, 2.79861, 2.90007, 2.98332, 3.28914, 3.62922", \ + "2.68551, 2.78197, 2.87888, 2.98482, 3.23805, 3.50976" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.831437, 0.831042, 0.830742, 0.830261, 0.829878, 0.829705", \ + "0.831316, 0.830799, 0.830536, 0.82997, 0.829823, 0.829639", \ + "0.831218, 0.83069, 0.830431, 0.830367, 0.82979, 0.829527", \ + "0.830937, 0.830377, 0.830116, 0.829577, 0.829493, 0.829271", \ + "0.832069, 0.831532, 0.831318, 0.831384, 0.830548, 0.830553", \ + "0.829594, 0.829272, 0.828942, 0.828432, 0.828143, 0.827887", \ + "0.831557, 0.831272, 0.830903, 0.830317, 0.830443, 0.830274" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.8319, 3.6432, 5.45777, 7.2607, 12.6859, 18.1142", \ + "1.83273, 3.64276, 5.45295, 7.26696, 12.6837, 18.1174", \ + "1.83328, 3.64483, 5.45414, 7.26824, 12.6916, 18.1146", \ + "1.84166, 3.65381, 5.46482, 7.27584, 12.6991, 18.1323", \ + "1.86196, 3.66987, 5.48397, 7.29657, 12.7212, 18.1611", \ + "1.90766, 3.72422, 5.52896, 7.33739, 12.7731, 18.1984", \ + "2.00189, 3.81432, 5.62599, 7.43276, 12.8547, 18.2862" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.105235, 0.105539, 0.105749, 0.105937, 0.107344, 0.108292", \ + "0.104311, 0.104393, 0.104581, 0.10474, 0.106662, 0.107264", \ + "0.105309, 0.105401, 0.105564, 0.106223, 0.107943, 0.10726", \ + "0.109826, 0.109913, 0.110056, 0.110215, 0.112533, 0.112906", \ + "0.120424, 0.120681, 0.120977, 0.121413, 0.122392, 0.124309", \ + "0.144314, 0.144347, 0.144883, 0.145005, 0.146816, 0.147192", \ + "0.193752, 0.193839, 0.19433, 0.194509, 0.195509, 0.196603" \ + ); + } + } + } + pin (p2c) { + direction : "output"; + output_voltage : "core"; + function : "pad"; + related_ground_pin : vss; + related_power_pin : vdd; + max_capacitance : 0.736815; + timing () { + related_pin : "pad"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.11233, 0.132354, 0.169862, 0.20626, 0.242439, 0.278569", \ + "0.114357, 0.135735, 0.174883, 0.211944, 0.248218, 0.284437", \ + "0.114358, 0.135736, 0.174884, 0.211945, 0.248219, 0.284438", \ + "0.114359, 0.135737, 0.174885, 0.211946, 0.24822, 0.284439", \ + "0.11436, 0.135738, 0.174886, 0.211947, 0.248221, 0.28444", \ + "0.114361, 0.135739, 0.174887, 0.211948, 0.248222, 0.284441", \ + "0.114362, 0.13574, 0.174888, 0.211949, 0.248223, 0.284442" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0696141, 0.106041, 0.180759, 0.256781, 0.333227, 0.41008", \ + "0.076501, 0.113278, 0.186811, 0.26189, 0.337496, 0.413709", \ + "0.0838518, 0.11992, 0.193625, 0.269325, 0.344402, 0.419987", \ + "0.0876346, 0.123108, 0.195778, 0.270896, 0.347279, 0.422837", \ + "0.104675, 0.138875, 0.208579, 0.280268, 0.354526, 0.429015", \ + "0.135146, 0.168905, 0.234104, 0.302947, 0.373753, 0.447924", \ + "0.158498, 0.192968, 0.257844, 0.322696, 0.390793, 0.462136" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.400555, 0.428453, 0.472826, 0.510332, 0.544762, 0.577773", \ + "0.440865, 0.468822, 0.513265, 0.550894, 0.585727, 0.618849", \ + "0.547742, 0.575732, 0.619874, 0.657755, 0.691718, 0.724786", \ + "0.609215, 0.637068, 0.68145, 0.71917, 0.753847, 0.786205", \ + "0.91058, 0.938411, 0.982739, 1.0205, 1.05522, 1.08836", \ + "1.50942, 1.53733, 1.58171, 1.61905, 1.65321, 1.68593", \ + "2.02919, 2.06013, 2.10847, 2.14841, 2.18337, 2.21648" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.126254, 0.155343, 0.207198, 0.257969, 0.309071, 0.361544", \ + "0.126255, 0.155344, 0.207199, 0.258243, 0.309866, 0.362402", \ + "0.126256, 0.155345, 0.2072, 0.258244, 0.309867, 0.362403", \ + "0.126257, 0.155346, 0.207201, 0.258245, 0.309868, 0.362404", \ + "0.126258, 0.155347, 0.207202, 0.258246, 0.309871, 0.362405", \ + "0.144068, 0.170948, 0.220807, 0.269518, 0.318706, 0.370248", \ + "0.173416, 0.20028, 0.248592, 0.294692, 0.342783, 0.391481" \ + ); + } + } + internal_power () { + related_pin : "pad"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "-0.139219, -0.138832, -0.13908, -0.138966, -0.138891, -0.139805", \ + "-0.139689, -0.139691, -0.139842, -0.139703, -0.139114, -0.139653", \ + "-0.139775, -0.139701, -0.139773, -0.139724, -0.139774, -0.139614", \ + "-0.139565, -0.139749, -0.139748, -0.139704, -0.139261, -0.139747", \ + "-0.139211, -0.139206, -0.139073, -0.139198, -0.13917, -0.139194", \ + "-0.138938, -0.139059, -0.139011, -0.139126, -0.139287, -0.139034", \ + "-0.139254, -0.13895, -0.138949, -0.139009, -0.138965, -0.139067" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.139806, 0.139805, 0.139807, 0.139808, 0.139808, 0.139805", \ + "0.139849, 0.139849, 0.13985, 0.139849, 0.139848, 0.139842", \ + "0.139775, 0.139772, 0.139773, 0.139771, 0.139774, 0.139773", \ + "0.13975, 0.139749, 0.139748, 0.139746, 0.139745, 0.139747", \ + "0.139211, 0.139206, 0.139201, 0.139198, 0.139196, 0.139194", \ + "0.138938, 0.139059, 0.139011, 0.139126, 0.139287, 0.139034", \ + "0.139254, 0.13895, 0.138949, 0.139009, 0.138965, 0.139067" \ + ); + } + } + internal_power () { + related_pin : "pad"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.00783589, 0.00802576, 0.00847138, 0.00841119, 0.00802345, 0.00767152", \ + "0.00722708, 0.00721479, 0.00720184, 0.00730108, 0.00683167, 0.00665754", \ + "0.00651145, 0.00695474, 0.00646758, 0.00651916, 0.00635782, 0.00548223", \ + "0.00655422, 0.006246, 0.00646218, 0.00589074, 0.00528822, 0.00492549", \ + "0.00694398, 0.00638785, 0.00584226, 0.0052372, 0.00585603, 0.00545523", \ + "0.00943851, 0.00815422, 0.00659097, 0.00611011, 0.00518076, 0.00596809", \ + "0.0130739, 0.0115377, 0.00999459, 0.00876232, 0.007236, 0.00748536" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0625753, 0.0614179, 0.0609507, 0.060973, 0.0610603, 0.0611222", \ + "0.0610524, 0.0598009, 0.0593176, 0.0593017, 0.0593475, 0.0593837", \ + "0.0599084, 0.0586938, 0.0581534, 0.0581029, 0.058102, 0.0581664", \ + "0.0600374, 0.0587999, 0.0582657, 0.0582143, 0.0582203, 0.0582761", \ + "0.059467, 0.0581623, 0.0575082, 0.0573813, 0.0573546, 0.0573745", \ + "0.0625728, 0.0606715, 0.0593234, 0.0588413, 0.0584926, 0.05841", \ + "0.0677025, 0.0641935, 0.0617493, 0.0607121, 0.0604487, 0.060121" \ + ); + } + } + } + pin (c2p) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.016; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0266292; + rise_capacitance : 0.0268778; + rise_capacitance_range (0.0224462, 0.0317237); + fall_capacitance : 0.0263806; + fall_capacitance_range (0.022977, 0.028405); + internal_power () { + when : "(!c2p_en * pad * p2c)"; + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-1.28884e-05, -1.55373e-06, -1.01383e-06, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "1.28884e-05, 1.55373e-06, 1.01383e-06, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + when : "(!c2p_en * pad * p2c)"; + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0201435, -0.0212465, -0.0213445, -0.0213888, -0.0217585, -0.021855, -0.0216817" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0251578, 0.024708, 0.0247034, 0.0245272, 0.0246058, 0.0245068, 0.0244758" \ + ); + } + } + internal_power () { + when : "(!c2p_en * !pad * !p2c)"; + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-1.28778e-05, -1.55503e-06, -1.01763e-06, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "1.28778e-05, 1.55503e-06, 1.01763e-06, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + when : "(!c2p_en * !pad * !p2c)"; + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0201429, -0.0212459, -0.0213439, -0.0213883, -0.0217581, -0.0218549, -0.0216817" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0251571, 0.0247071, 0.0247029, 0.024527, 0.0246057, 0.0245067, 0.0244758" \ + ); + } + } + internal_power () { + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-1.28778e-05, -1.55503e-06, -1.01763e-06, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "1.28778e-05, 1.55503e-06, 1.01763e-06, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0201429, -0.0212459, -0.0213439, -0.0213883, -0.0217581, -0.0218549, -0.0216817" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0251571, 0.0247071, 0.0247029, 0.024527, 0.0246057, 0.0245067, 0.0244758" \ + ); + } + } + } + pin (c2p_en) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.011; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0249918; + rise_capacitance : 0.0259897; + rise_capacitance_range (0.0216573, 0.031848); + fall_capacitance : 0.023994; + fall_capacitance_range (0.0206, 0.0280959); + internal_power () { + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.661032, 0.660322, 0.660776, 0.66112, 0.661146, 0.658943, 0.662086" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.232659, 0.232286, 0.232299, 0.231978, 0.231295, 0.230033, 0.230113" \ + ); + } + } + internal_power () { + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0461392, 0.0454534, 0.0462197, 0.050699, 0.0613509, 0.0854494, 0.133315" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.098288, 0.0975148, 0.0994388, 0.103449, 0.114136, 0.139853, 0.186745" \ + ); + } + } + } + } + cell (sg13g2_IOPadOut16mA) { + pad_cell : true; + area : 14400; + cell_footprint : "inout"; + pad_drivers : 1; + bond_pads : 1; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 4918.23; + when : "!c2p&!pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 2341.43; + when : "!c2p&!pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 1041.68; + when : "c2p&pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 6177.33; + when : "c2p&pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 2979.96; + related_pg_pin : iovdd; + } + leakage_power () { + value : 4259.38; + related_pg_pin : vdd; + } + pin (pad) { + direction : "output"; + is_pad : true; + function : "c2p"; + drive_current : 16; + output_voltage : "pad"; + related_ground_pin : iovss; + related_power_pin : iovdd; + max_capacitance : 2.06464; + timing () { + related_pin : "c2p"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 3, 7, 9, 12, 15"); + values ( \ + "2.16764, 2.61018, 3.32433, 3.66376, 4.16728, 4.66749", \ + "2.19351, 2.63623, 3.35035, 3.68943, 4.19276, 4.69328", \ + "2.22123, 2.66366, 3.37788, 3.7173, 4.22017, 4.72039", \ + "2.28417, 2.7269, 3.44075, 3.78039, 4.28306, 4.78429", \ + "2.41115, 2.85349, 3.56774, 3.90715, 4.40963, 4.91048", \ + "2.65562, 3.09842, 3.81271, 4.15211, 4.65459, 5.15558", \ + "3.11376, 3.55663, 4.27081, 4.61019, 5.1127, 5.61349" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 3, 7, 9, 12, 15"); + values ( \ + "0.76837, 1.42757, 2.74078, 3.40974, 4.42518, 5.44941", \ + "0.768799, 1.42758, 2.74079, 3.40975, 4.42519, 5.4508", \ + "0.7688, 1.42759, 2.7408, 3.40976, 4.42637, 5.45081", \ + "0.768801, 1.4276, 2.74081, 3.41005, 4.42638, 5.45082", \ + "0.768802, 1.42772, 2.74082, 3.41019, 4.42639, 5.45083", \ + "0.768803, 1.42776, 2.74083, 3.41022, 4.4264, 5.45084", \ + "0.768804, 1.42777, 2.74084, 3.41023, 4.42641, 5.45085" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 3, 7, 9, 12, 15"); + values ( \ + "1.56417, 1.92599, 2.56206, 2.87822, 3.35607, 3.83853", \ + "1.57985, 1.94168, 2.57769, 2.89383, 3.37081, 3.85597", \ + "1.59011, 1.95151, 2.58744, 2.90352, 3.3828, 3.86537", \ + "1.60858, 1.97002, 2.60575, 2.92209, 3.40081, 3.88304", \ + "1.63663, 1.9984, 2.63444, 2.95048, 3.42917, 3.91172", \ + "1.67677, 2.03856, 2.67336, 2.9906, 3.46804, 3.95113", \ + "1.75742, 2.1213, 2.75575, 3.07119, 3.55014, 4.03135" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 3, 7, 9, 12, 15"); + values ( \ + "0.925738, 1.44139, 2.61749, 3.23444, 4.17686, 5.13255", \ + "0.925882, 1.4414, 2.6175, 3.23451, 4.17687, 5.13256", \ + "0.926356, 1.44141, 2.61759, 3.23452, 4.17782, 5.13257", \ + "0.926527, 1.44142, 2.6177, 3.23459, 4.17783, 5.13258", \ + "0.926528, 1.44143, 2.61771, 3.2346, 4.17784, 5.13259", \ + "0.926576, 1.44144, 2.61773, 3.23476, 4.17785, 5.1326", \ + "0.926577, 1.44482, 2.61963, 3.23679, 4.17786, 5.13261" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 3, 7, 9, 12, 15"); + values ( \ + "4.95659, 4.89093, 4.84557, 4.82169, 4.75374, 4.66764", \ + "4.95252, 4.8981, 4.85172, 4.80927, 4.73964, 4.68936", \ + "4.95689, 4.8993, 4.8519, 4.82259, 4.74612, 4.67265", \ + "4.95883, 4.90527, 4.85595, 4.82775, 4.75443, 4.66962", \ + "4.97255, 4.90998, 4.86972, 4.83483, 4.74726, 4.68852", \ + "4.9917, 4.93482, 4.89597, 4.85802, 4.77387, 4.7037", \ + "5.04174, 4.99038, 4.94811, 4.91106, 4.82565, 4.752" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 3, 7, 9, 12, 15"); + values ( \ + "11.3659, 9.22498, 7.4156, 6.91714, 6.38979, 6.00616", \ + "11.357, 9.21361, 7.40707, 6.91202, 6.37231, 6.00181", \ + "11.3574, 9.21306, 7.40726, 6.90742, 6.3835, 5.99875", \ + "11.3552, 9.21349, 7.40661, 6.90731, 6.37824, 5.99448", \ + "11.3578, 9.21038, 7.40601, 6.90623, 6.37766, 5.99092", \ + "11.3665, 9.21565, 7.4012, 6.90576, 6.37601, 5.99084", \ + "11.3548, 9.22888, 7.41311, 6.91362, 6.38687, 5.98958" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 3, 7, 9, 12, 15"); + values ( \ + "-0.0114481, -0.0114484, -0.0114484, -0.0114487, -0.0114486, -0.0114482", \ + "-0.011785, -0.0117853, -0.0117854, -0.0117853, -0.0117853, -0.0117852", \ + "-0.00920842, -0.00922948, -0.00920869, -0.00920893, -0.00920872, -0.00920844", \ + "-0.000787183, -0.000787372, -0.000787409, -0.000787526, -0.000787293, -0.000802197", \ + "0.0178684, 0.017798, 0.0177977, 0.0177976, 0.0177979, 0.0177979", \ + "0.0567698, 0.0567698, 0.0567695, 0.0567696, 0.0567697, 0.0567698", \ + "0.142418, 0.142418, 0.142418, 0.142418, 0.142418, 0.142418" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 3, 7, 9, 12, 15"); + values ( \ + "0.06901, 0.0689995, 0.0690007, 0.0689983, 0.0689962, 0.0689933", \ + "0.0710267, 0.0710185, 0.0710208, 0.071019, 0.0710197, 0.071016", \ + "0.0738162, 0.0738115, 0.0738127, 0.0736611, 0.073809, 0.0736594", \ + "0.0827838, 0.0827799, 0.0826426, 0.0827787, 0.0827766, 0.0827732", \ + "0.101514, 0.10151, 0.101511, 0.101509, 0.101507, 0.101506", \ + "0.141059, 0.141058, 0.140862, 0.141058, 0.140857, 0.141055", \ + "0.2232, 0.223472, 0.223233, 0.223495, 0.223491, 0.223175" \ + ); + } + } + } + pin (c2p) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.016; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0389999; + rise_capacitance : 0.0381972; + rise_capacitance_range (0.0338184, 0.0413843); + fall_capacitance : 0.0398026; + fall_capacitance_range (0.0356268, 0.0421723); + } + } + cell (sg13g2_IOPadOut30mA) { + pad_cell : true; + area : 14400; + cell_footprint : "inout"; + pad_drivers : 1; + bond_pads : 1; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 9036.95; + when : "!c2p&!pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 2340.59; + when : "!c2p&!pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 1485.88; + when : "c2p&pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 6177.24; + when : "c2p&pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 5261.41; + related_pg_pin : iovdd; + } + leakage_power () { + value : 4258.92; + related_pg_pin : vdd; + } + pin (pad) { + direction : "output"; + is_pad : true; + function : "c2p"; + drive_current : 30; + output_voltage : "pad"; + related_ground_pin : iovss; + related_power_pin : iovdd; + max_capacitance : 2.56963; + timing () { + related_pin : "c2p"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("2, 6, 14, 18, 24, 30"); + values ( \ + "2.66791, 3.2476, 4.09859, 4.47574, 5.02915, 5.57102", \ + "2.69339, 3.27316, 4.12389, 4.50139, 5.05491, 5.59727", \ + "2.72289, 3.30253, 4.14974, 4.53054, 5.08404, 5.62754", \ + "2.78514, 3.36367, 4.21357, 4.59447, 5.14799, 5.69117", \ + "2.91274, 3.48989, 4.33719, 4.71814, 5.27166, 5.81504", \ + "3.15565, 3.73511, 4.58238, 4.96336, 5.51683, 6.06023", \ + "3.61397, 4.19331, 5.04078, 5.42176, 5.9752, 6.51871" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("2, 6, 14, 18, 24, 30"); + values ( \ + "0.975198, 1.74027, 3.14156, 3.83976, 4.90745, 5.98257", \ + "0.975557, 1.74028, 3.14157, 3.84009, 4.90746, 5.98263", \ + "0.975558, 1.74029, 3.14158, 3.84018, 4.90746, 5.9828", \ + "0.975695, 1.7403, 3.14159, 3.84019, 4.90747, 5.98281", \ + "0.975696, 1.74031, 3.1416, 3.8402, 4.90748, 5.98286", \ + "0.976631, 1.74032, 3.14161, 3.84021, 4.90749, 5.98322", \ + "0.976632, 1.74033, 3.14162, 3.84022, 4.9075, 5.98339" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("2, 6, 14, 18, 24, 30"); + values ( \ + "2.12227, 2.55507, 3.26938, 3.60531, 4.10218, 4.60077", \ + "2.13772, 2.57172, 3.28729, 3.62118, 4.1162, 4.61738", \ + "2.14787, 2.5806, 3.29774, 3.62908, 4.12657, 4.62628", \ + "2.16649, 2.59895, 3.31578, 3.64733, 4.14506, 4.64162", \ + "2.19479, 2.62646, 3.34501, 3.6778, 4.17203, 4.66842", \ + "2.23409, 2.66752, 3.38459, 3.71784, 4.21355, 4.71517", \ + "2.31557, 2.74852, 3.46343, 3.79735, 4.2925, 4.78893" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("2, 6, 14, 18, 24, 30"); + values ( \ + "1.49264, 1.99229, 3.12258, 3.743, 4.7079, 5.69503", \ + "1.49265, 1.99437, 3.12259, 3.74535, 4.70925, 5.69504", \ + "1.49297, 1.99438, 3.1226, 3.74767, 4.70926, 5.69517", \ + "1.49379, 1.99439, 3.1254, 3.74768, 4.70927, 5.69518", \ + "1.4938, 1.9944, 3.134, 3.74769, 4.70928, 5.69519", \ + "1.49381, 1.99441, 3.13401, 3.7477, 4.70929, 5.6952", \ + "1.49424, 1.99652, 3.13402, 3.74876, 4.70943, 5.69521" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("2, 6, 14, 18, 24, 30"); + values ( \ + "7.86985, 7.6821, 7.75974, 7.4748, 7.40406, 7.19094", \ + "7.86609, 7.67328, 7.75896, 7.50552, 7.42308, 7.15539", \ + "7.88091, 7.68396, 7.54896, 7.51203, 7.42686, 7.3362", \ + "7.89378, 7.68, 7.55565, 7.51998, 7.43514, 7.31925", \ + "7.88498, 7.69104, 7.56495, 7.49079, 7.44429, 7.34172", \ + "7.9373, 7.71507, 7.58964, 7.51767, 7.46859, 7.3608", \ + "7.95917, 7.75401, 7.63653, 7.56666, 7.52106, 7.38687" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("2, 6, 14, 18, 24, 30"); + values ( \ + "40.7951, 33.6265, 26.3313, 24.1675, 21.7696, 20.0223", \ + "40.8016, 33.6399, 26.3354, 24.146, 21.7941, 19.9556", \ + "40.791, 33.6218, 26.3136, 24.1757, 21.7781, 20.0146", \ + "40.7979, 33.6166, 26.3424, 24.2099, 21.7791, 19.9461", \ + "40.7809, 33.6273, 26.4014, 24.1488, 21.7813, 19.9589", \ + "40.8166, 33.6378, 26.3515, 24.1592, 21.783, 19.9337", \ + "40.8147, 33.6526, 26.3733, 24.2181, 21.7809, 19.987" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("2, 6, 14, 18, 24, 30"); + values ( \ + "-0.0114525, -0.0114526, -0.0114525, -0.0114529, -0.0114529, -0.0114524", \ + "-0.0117847, -0.0117851, -0.0117847, -0.0117849, -0.0117851, -0.0117848", \ + "-0.00921643, -0.00921647, -0.00921652, -0.00923654, -0.00923667, -0.00921657", \ + "-0.000816139, -0.000816103, -0.000814955, -0.000815069, -0.000815201, -0.000814925", \ + "0.0178437, 0.0177737, 0.0177738, 0.0177737, 0.0177738, 0.0177738", \ + "0.0567247, 0.0567248, 0.0567247, 0.0567245, 0.0567247, 0.0567247", \ + "0.14239, 0.14239, 0.14239, 0.14239, 0.142389, 0.14239" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("2, 6, 14, 18, 24, 30"); + values ( \ + "0.0690078, 0.0690084, 0.0690092, 0.0690069, 0.0690082, 0.0690061", \ + "0.0710151, 0.0710159, 0.0710147, 0.071016, 0.0710153, 0.0710137", \ + "0.0738041, 0.073655, 0.0738043, 0.073805, 0.0736551, 0.0736524", \ + "0.0826274, 0.0827665, 0.0827665, 0.0827657, 0.0826283, 0.0827646", \ + "0.101481, 0.101331, 0.101331, 0.101483, 0.101331, 0.101481", \ + "0.140811, 0.140771, 0.14077, 0.14077, 0.140771, 0.140769", \ + "0.223499, 0.223297, 0.223391, 0.223581, 0.222985, 0.223014" \ + ); + } + } + } + pin (c2p) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.016; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0389979; + rise_capacitance : 0.038194; + rise_capacitance_range (0.0338126, 0.0413615); + fall_capacitance : 0.0398017; + fall_capacitance_range (0.0356136, 0.0421731); + } + } + cell (sg13g2_IOPadOut4mA) { + pad_cell : true; + area : 14400; + cell_footprint : "inout"; + pad_drivers : 1; + bond_pads : 1; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 1464.94; + when : "!c2p&!pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 2340.54; + when : "!c2p&!pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 738.344; + when : "c2p&pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 6177.35; + when : "c2p&pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 1101.64; + related_pg_pin : iovdd; + } + leakage_power () { + value : 4258.94; + related_pg_pin : vdd; + } + pin (pad) { + direction : "output"; + is_pad : true; + function : "c2p"; + drive_current : 4; + output_voltage : "pad"; + related_ground_pin : iovss; + related_power_pin : iovdd; + max_capacitance : 0.661248; + timing () { + related_pin : "c2p"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.20736, 2.87691, 3.54309, 4.20776, 6.20279, 8.19615", \ + "2.23328, 2.90248, 3.56889, 4.23435, 6.22878, 8.22261", \ + "2.26081, 2.93038, 3.59609, 4.26155, 6.25613, 8.24982", \ + "2.3236, 2.99296, 3.65897, 4.32425, 6.31941, 8.31325", \ + "2.45069, 3.11978, 3.78594, 4.45158, 6.44592, 8.43929", \ + "2.69535, 3.36454, 4.03073, 4.69617, 6.69056, 8.68404", \ + "3.15398, 3.82312, 4.4894, 5.15495, 7.14929, 9.14272" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.6985, 3.06749, 4.44897, 5.83487, 10.0003, 14.1653", \ + "1.69851, 3.0675, 4.44898, 5.83488, 10.0004, 14.1654", \ + "1.69852, 3.06751, 4.44899, 5.83489, 10.0005, 14.1655", \ + "1.69853, 3.06752, 4.44925, 5.8349, 10.0006, 14.1656", \ + "1.69854, 3.06753, 4.44926, 5.83491, 10.0007, 14.1657", \ + "1.69855, 3.06754, 4.44927, 5.83492, 10.0008, 14.1658", \ + "1.69856, 3.06755, 4.44928, 5.83493, 10.0009, 14.1659" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.63618, 2.29585, 2.95574, 3.61621, 5.59642, 7.57672", \ + "1.6511, 2.31117, 2.97089, 3.63029, 5.61147, 7.59182", \ + "1.66145, 2.32113, 2.98054, 3.63998, 5.62142, 7.60163", \ + "1.67908, 2.33935, 2.99892, 3.65919, 5.63894, 7.61984", \ + "1.7079, 2.36733, 3.02701, 3.68631, 5.66589, 7.64805", \ + "1.74671, 2.40632, 3.06631, 3.72576, 5.70568, 7.68718", \ + "1.82952, 2.48958, 3.14948, 3.80868, 5.78844, 7.76791" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.58341, 2.87489, 4.17742, 5.48315, 9.40483, 13.328", \ + "1.58342, 2.8749, 4.17743, 5.48342, 9.40484, 13.3293", \ + "1.58343, 2.87491, 4.17773, 5.48493, 9.40585, 13.3294", \ + "1.58344, 2.87492, 4.17774, 5.48494, 9.40982, 13.3295", \ + "1.58345, 2.87601, 4.17775, 5.48495, 9.40983, 13.3296", \ + "1.58346, 2.87602, 4.17776, 5.48496, 9.40984, 13.3297", \ + "1.58347, 2.87603, 4.17777, 5.48497, 9.40985, 13.3299" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.56939, 2.54736, 2.51869, 2.49168, 2.42352, 2.38218", \ + "2.56598, 2.54136, 2.5173, 2.49381, 2.42214, 2.38293", \ + "2.57108, 2.5458, 2.52522, 2.48916, 2.42571, 2.38644", \ + "2.57179, 2.55166, 2.52707, 2.50011, 2.43105, 2.38812", \ + "2.58329, 2.56244, 2.53113, 2.51073, 2.44125, 2.40027", \ + "2.61049, 2.587, 2.56104, 2.53482, 2.46504, 2.42361", \ + "2.6607, 2.63866, 2.60528, 2.58756, 2.51796, 2.47593" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.53875, 1.51533, 1.50456, 1.49985, 1.48973, 1.48529", \ + "1.5302, 1.50655, 1.49623, 1.49028, 1.4814, 1.47793", \ + "1.52611, 1.50233, 1.49258, 1.48617, 1.47721, 1.4735", \ + "1.52209, 1.49843, 1.48807, 1.48274, 1.47385, 1.46941", \ + "1.52252, 1.49895, 1.4877, 1.48192, 1.47368, 1.46955", \ + "1.5147, 1.49137, 1.47971, 1.47373, 1.46466, 1.45997", \ + "1.51683, 1.49218, 1.48262, 1.47652, 1.46809, 1.4626" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "-0.0114529, -0.0114532, -0.0114536, -0.0114533, -0.0114531, -0.0114531", \ + "-0.0117845, -0.0117848, -0.011785, -0.011785, -0.0117848, -0.0117846", \ + "-0.00921506, -0.00923525, -0.00921567, -0.00921562, -0.00923521, -0.00921528", \ + "-0.000798894, -0.000799251, -0.000799344, -0.000799301, -0.000798932, -0.000812822", \ + "0.0177752, 0.0177747, 0.0177747, 0.0177747, 0.0177747, 0.0177747", \ + "0.0567254, 0.0567248, 0.0567247, 0.0567247, 0.0567248, 0.056725", \ + "0.142486, 0.142486, 0.142486, 0.142486, 0.142486, 0.142486" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.0690501, 0.0690446, 0.0690321, 0.0690389, 0.0690302, 0.06903", \ + "0.0710545, 0.0710474, 0.0710287, 0.0710329, 0.0710326, 0.0710368", \ + "0.0738233, 0.0738362, 0.0738225, 0.0736773, 0.0738206, 0.0738256", \ + "0.0826682, 0.0827983, 0.082785, 0.0827892, 0.0827832, 0.0826505", \ + "0.101473, 0.10135, 0.101335, 0.101338, 0.101465, 0.101468", \ + "0.140821, 0.140819, 0.140941, 0.140945, 0.140943, 0.140943", \ + "0.223243, 0.223203, 0.22324, 0.223228, 0.223588, 0.223251" \ + ); + } + } + } + pin (c2p) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.016; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0389963; + rise_capacitance : 0.0381863; + rise_capacitance_range (0.0338121, 0.0413372); + fall_capacitance : 0.0398062; + fall_capacitance_range (0.035613, 0.0422132); + } + } + cell (sg13g2_IOPadTriOut16mA) { + pad_cell : true; + area : 14400; + cell_footprint : "tri_out"; + pad_drivers : 1; + bond_pads : 1; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 937.301; + when : "!c2p_en&!c2p"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 9639.27; + when : "!c2p_en&!c2p"; + related_pg_pin : vdd; + } + leakage_power () { + value : 937.3; + when : "!c2p_en&c2p"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 9821.81; + when : "!c2p_en&c2p"; + related_pg_pin : vdd; + } + leakage_power () { + value : 1091.71; + when : "c2p_en&c2p&pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 14974.6; + when : "c2p_en&c2p&pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 4951.7; + when : "c2p_en&!c2p&!pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 14497.5; + when : "c2p_en&!c2p&!pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 1979.5; + related_pg_pin : iovdd; + } + leakage_power () { + value : 12233.3; + related_pg_pin : vdd; + } + pin (pad) { + direction : "output"; + is_pad : true; + function : "c2p"; + three_state : "c2p_en'"; + drive_current : 16; + output_voltage : "pad"; + related_ground_pin : iovss; + related_power_pin : iovdd; + max_capacitance : 2.15294; + capacitance : 0.248764; + rise_capacitance : 0.2505; + rise_capacitance_range (0.2505, 0.2505); + fall_capacitance : 0.247028; + fall_capacitance_range (0.247028, 0.247028); + timing () { + related_pin : "c2p"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.23807, 2.47768, 2.68148, 2.87177, 3.39614, 3.90392", \ + "2.25402, 2.49338, 2.69722, 2.88751, 3.41072, 3.91949", \ + "2.26381, 2.50328, 2.70691, 2.89726, 3.42144, 3.92924", \ + "2.27972, 2.51871, 2.72277, 2.91304, 3.43715, 3.94496", \ + "2.29671, 2.53618, 2.73996, 2.93028, 3.45458, 3.96184", \ + "2.315, 2.55419, 2.75802, 2.94824, 3.47265, 3.98043", \ + "2.32063, 2.56044, 2.76453, 2.9548, 3.47923, 3.98707" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.770929, 1.10411, 1.42771, 1.75491, 2.74096, 3.74729", \ + "0.77093, 1.10412, 1.42772, 1.75492, 2.74097, 3.7473", \ + "0.770931, 1.10413, 1.42773, 1.75493, 2.74098, 3.74731", \ + "0.770932, 1.10414, 1.42774, 1.75494, 2.741, 3.74732", \ + "0.770933, 1.10415, 1.42775, 1.75495, 2.74101, 3.74733", \ + "0.770934, 1.10416, 1.42776, 1.75496, 2.74102, 3.74734", \ + "0.772262, 1.10461, 1.42794, 1.75497, 2.74103, 3.74735" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.65636, 1.8481, 2.02017, 2.18302, 2.65961, 3.13843", \ + "1.67517, 1.86675, 2.03836, 2.20149, 2.67773, 3.15626", \ + "1.69018, 1.88177, 2.05327, 2.21638, 2.69211, 3.16806", \ + "1.7245, 1.91589, 2.08727, 2.25026, 2.72557, 3.20104", \ + "1.78145, 1.97222, 2.14363, 2.30653, 2.78188, 3.25962", \ + "1.86858, 2.05928, 2.23067, 2.39367, 2.86928, 3.34464", \ + "2.02285, 2.21397, 2.38597, 2.54923, 3.02307, 3.50108" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.895681, 1.15122, 1.42096, 1.70304, 2.60379, 3.5385", \ + "0.898279, 1.15395, 1.42228, 1.70509, 2.60511, 3.53873", \ + "0.901519, 1.15617, 1.42416, 1.7068, 2.60631, 3.53874", \ + "0.90576, 1.16013, 1.42751, 1.70979, 2.60834, 3.53897", \ + "0.907644, 1.16138, 1.42852, 1.71079, 2.60924, 3.54107", \ + "0.907645, 1.16139, 1.42853, 1.7108, 2.60925, 3.54108", \ + "0.907646, 1.1614, 1.42854, 1.71081, 2.60926, 3.54109" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : negative_unate; + timing_type : three_state_disable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.59749, 1.5975, 1.59751, 1.59752, 1.59753, 1.59754", \ + "1.62065, 1.62066, 1.62067, 1.62068, 1.62069, 1.6207", \ + "1.63665, 1.63666, 1.63667, 1.63668, 1.63669, 1.6367", \ + "1.66792, 1.66793, 1.66794, 1.66795, 1.66796, 1.66797", \ + "1.70314, 1.70315, 1.70316, 1.70317, 1.70318, 1.70319", \ + "1.75786, 1.75787, 1.75788, 1.75789, 1.7579, 1.75791", \ + "1.85042, 1.85043, 1.85044, 1.85045, 1.85046, 1.85047" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.59749, 1.5975, 1.59751, 1.59752, 1.59753, 1.59754", \ + "1.62065, 1.62066, 1.62067, 1.62068, 1.62069, 1.6207", \ + "1.63665, 1.63666, 1.63667, 1.63668, 1.63669, 1.6367", \ + "1.66792, 1.66793, 1.66794, 1.66795, 1.66796, 1.66797", \ + "1.70314, 1.70315, 1.70316, 1.70317, 1.70318, 1.70319", \ + "1.75786, 1.75787, 1.75788, 1.75789, 1.7579, 1.75791", \ + "1.85042, 1.85043, 1.85044, 1.85045, 1.85046, 1.85047" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.60845, 1.60846, 1.60847, 1.60848, 1.60849, 1.6085", \ + "1.62812, 1.62813, 1.62814, 1.62815, 1.62816, 1.62817", \ + "1.66107, 1.66108, 1.66109, 1.6611, 1.66111, 1.66112", \ + "1.69875, 1.69876, 1.69877, 1.69878, 1.69879, 1.6988", \ + "1.75684, 1.75685, 1.75686, 1.75687, 1.75688, 1.75689", \ + "1.81735, 1.81736, 1.81737, 1.81738, 1.81739, 1.8174", \ + "1.95839, 1.9584, 1.95841, 1.95842, 1.95843, 1.95844" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.60845, 1.60846, 1.60847, 1.60848, 1.60849, 1.6085", \ + "1.62812, 1.62813, 1.62814, 1.62815, 1.62816, 1.62817", \ + "1.66107, 1.66108, 1.66109, 1.6611, 1.66111, 1.66112", \ + "1.69875, 1.69876, 1.69877, 1.69878, 1.69879, 1.6988", \ + "1.75684, 1.75685, 1.75686, 1.75687, 1.75688, 1.75689", \ + "1.81735, 1.81736, 1.81737, 1.81738, 1.81739, 1.8174", \ + "1.95839, 1.9584, 1.95841, 1.95842, 1.95843, 1.95844" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : positive_unate; + timing_type : three_state_enable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.22088, 2.4682, 2.67827, 2.86574, 3.40247, 3.91758", \ + "2.2354, 2.48384, 2.69357, 2.88103, 3.41825, 3.93387", \ + "2.24554, 2.49125, 2.70331, 2.89588, 3.42899, 3.94503", \ + "2.26322, 2.50881, 2.72066, 2.91332, 3.44579, 3.96209", \ + "2.28426, 2.5319, 2.74102, 2.92897, 3.46626, 3.98107", \ + "2.30517, 2.55058, 2.76243, 2.95455, 3.48667, 4.00127", \ + "2.31931, 2.56757, 2.77679, 2.96453, 3.50165, 4.0164" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.786738, 1.11415, 1.43351, 1.75089, 2.73653, 3.74241", \ + "0.786739, 1.11447, 1.43352, 1.7509, 2.73654, 3.74242", \ + "0.78674, 1.11448, 1.43353, 1.75505, 2.73655, 3.74243", \ + "0.786741, 1.11449, 1.43354, 1.75508, 2.73656, 3.74244", \ + "0.786742, 1.1145, 1.43355, 1.75509, 2.73657, 3.74245", \ + "0.786743, 1.11451, 1.43356, 1.7551, 2.73658, 3.74246", \ + "0.786744, 1.11452, 1.43357, 1.75511, 2.73659, 3.74247" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.39938, 1.61956, 1.80981, 1.99084, 2.50778, 3.01363", \ + "1.41561, 1.63579, 1.82602, 2.00674, 2.52385, 3.02996", \ + "1.42496, 1.64539, 1.83545, 2.01646, 2.53339, 3.03863", \ + "1.43753, 1.65771, 1.84795, 2.02866, 2.54578, 3.05188", \ + "1.45502, 1.67433, 1.86457, 2.04555, 2.56166, 3.06838", \ + "1.46551, 1.68472, 1.87497, 2.05571, 2.57181, 3.0788", \ + "1.46885, 1.68767, 1.87845, 2.05901, 2.57598, 3.08159" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.652026, 0.964639, 1.27107, 1.57904, 2.52108, 3.47717", \ + "0.652027, 0.96464, 1.27108, 1.57962, 2.52109, 3.47718", \ + "0.652028, 0.964641, 1.27109, 1.57967, 2.5211, 3.47756", \ + "0.652029, 0.964642, 1.2711, 1.57968, 2.52111, 3.47757", \ + "0.652752, 0.964649, 1.27111, 1.57969, 2.52112, 3.47758", \ + "0.652845, 0.96465, 1.27112, 1.5797, 2.52113, 3.47759", \ + "0.652846, 0.964651, 1.27113, 1.57971, 2.52114, 3.4776" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "4.93064, 4.8914, 4.87986, 4.92984, 4.84194, 4.79214", \ + "4.9371, 4.89187, 4.87098, 4.93428, 4.80654, 4.79418", \ + "4.93631, 4.8955, 4.86558, 4.93281, 4.83726, 4.79724", \ + "4.93882, 4.88719, 4.87011, 4.93359, 4.83699, 4.79661", \ + "4.91893, 4.88964, 4.86534, 4.93059, 4.83912, 4.78491", \ + "4.93382, 4.88415, 4.86552, 4.92936, 4.84248, 4.79208", \ + "4.89524, 4.85929, 4.85037, 4.90887, 4.82643, 4.77522" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "10.5674, 9.38282, 8.59717, 8.02711, 6.96451, 6.35333", \ + "10.6524, 9.45834, 8.66582, 8.08813, 7.01297, 6.39448", \ + "10.7208, 9.51754, 8.71965, 8.13615, 7.05223, 6.41492", \ + "10.8489, 9.62733, 8.81779, 8.22515, 7.12302, 6.47455", \ + "10.885, 9.65929, 8.84573, 8.25129, 7.142, 6.50207", \ + "10.8116, 9.58806, 8.78191, 8.19318, 7.09579, 6.45009", \ + "10.5657, 9.38341, 8.60316, 8.03049, 6.96373, 6.35357" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.061694, 0.0616923, 0.0616915, 0.0616924, 0.0616891, 0.0616909", \ + "0.0595515, 0.0595498, 0.0595504, 0.0595503, 0.0595501, 0.0595476", \ + "0.0608164, 0.0608159, 0.0608138, 0.0608156, 0.0608143, 0.0608122", \ + "0.0662984, 0.066297, 0.0662967, 0.0662967, 0.0662964, 0.0662939", \ + "0.0826066, 0.0826061, 0.082606, 0.0826056, 0.0826034, 0.0826027", \ + "0.121263, 0.121262, 0.121262, 0.121262, 0.121259, 0.121259", \ + "0.207474, 0.207473, 0.207473, 0.207472, 0.207469, 0.207469" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.1492, 0.149198, 0.149198, 0.149196, 0.149198, 0.149191", \ + "0.146768, 0.146766, 0.146761, 0.146765, 0.146764, 0.146758", \ + "0.147958, 0.147956, 0.147954, 0.147954, 0.147955, 0.147949", \ + "0.153857, 0.153854, 0.153852, 0.153852, 0.153852, 0.153847", \ + "0.170698, 0.170688, 0.170681, 0.170683, 0.170684, 0.170678", \ + "0.210259, 0.210257, 0.210255, 0.210257, 0.210257, 0.210252", \ + "0.295191, 0.295142, 0.295292, 0.295077, 0.295209, 0.295311" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "4.5454, 4.65436, 4.74201, 4.731, 4.96131, 5.12895", \ + "4.53441, 4.65649, 4.74294, 4.72974, 4.96626, 5.14434", \ + "4.53609, 4.5802, 4.74729, 4.86081, 4.97871, 5.21334", \ + "4.53919, 4.5806, 4.75008, 4.8597, 4.98888, 5.13381", \ + "4.54654, 4.6634, 4.74576, 4.73787, 4.96947, 5.11725", \ + "4.54411, 4.58465, 4.74858, 4.84719, 4.99371, 5.11017", \ + "4.53183, 4.66462, 4.74849, 4.73955, 5.0067, 5.15625" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.01232, 2.01373, 2.01404, 2.0136, 2.01011, 2.00924", \ + "2.01228, 2.01369, 2.01394, 2.01369, 2.01255, 2.00931", \ + "2.01243, 2.01373, 2.01418, 2.01405, 2.0103, 2.00933", \ + "2.01238, 2.0138, 2.01406, 2.01381, 2.01256, 2.00944", \ + "2.01328, 2.01405, 2.01432, 2.014, 2.01245, 2.00972", \ + "2.01125, 2.01191, 2.01225, 2.0121, 2.01057, 2.00758", \ + "2.01301, 2.01366, 2.0139, 2.01478, 2.01442, 2.01055" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.0277638, 0.0277647, 0.0277661, 0.0277645, 0.027765, 0.0277653", \ + "0.0264857, 0.0264873, 0.0264886, 0.0264871, 0.026488, 0.0264871", \ + "0.0289421, 0.028942, 0.0289447, 0.0289451, 0.029261, 0.0289431", \ + "0.0372677, 0.0372678, 0.0372706, 0.037271, 0.0372702, 0.0372701", \ + "0.0576424, 0.0576436, 0.0576447, 0.0576434, 0.0576442, 0.0576442", \ + "0.102986, 0.102986, 0.102989, 0.102989, 0.102988, 0.102987", \ + "0.194235, 0.194236, 0.194236, 0.194235, 0.194235, 0.194235" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.0469917, 0.0469905, 0.0469877, 0.0469879, 0.0469852, 0.0469818", \ + "0.0459049, 0.0459019, 0.0458968, 0.0458977, 0.0458962, 0.0458918", \ + "0.0469839, 0.0470775, 0.0469777, 0.0470712, 0.0469752, 0.0470667", \ + "0.0515204, 0.0515173, 0.0515129, 0.0515133, 0.0515112, 0.0515072", \ + "0.0621613, 0.0621581, 0.0621568, 0.0621563, 0.0621522, 0.0621504", \ + "0.0860795, 0.0860753, 0.0860751, 0.0860709, 0.0860692, 0.0860654", \ + "0.13373, 0.133811, 0.133764, 0.133811, 0.133673, 0.133707" \ + ); + } + } + } + pin (c2p) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.016; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0268082; + rise_capacitance : 0.0269943; + rise_capacitance_range (0.0226816, 0.0319488); + fall_capacitance : 0.0266221; + fall_capacitance_range (0.0232107, 0.0286557); + internal_power () { + when : "!c2p_en"; + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0, 0, 0, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0, 0, 0, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + when : "!c2p_en"; + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0201738, -0.0212732, -0.0214401, -0.0214293, -0.0217521, -0.02178, -0.0219522" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0249864, 0.0245475, 0.0244909, 0.0243853, 0.0244903, 0.0240938, 0.0243234" \ + ); + } + } + internal_power () { + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0, 0, 0, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0, 0, 0, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0201738, -0.0212732, -0.0214401, -0.0214293, -0.0217521, -0.02178, -0.0219522" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0249864, 0.0245475, 0.0244909, 0.0243853, 0.0244903, 0.0240938, 0.0243234" \ + ); + } + } + } + pin (c2p_en) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.011; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0256701; + rise_capacitance : 0.0265642; + rise_capacitance_range (0.0225486, 0.0322363); + fall_capacitance : 0.024776; + fall_capacitance_range (0.0219391, 0.0283998); + } + } + cell (sg13g2_IOPadTriOut30mA) { + pad_cell : true; + area : 14400; + cell_footprint : "tri_out"; + pad_drivers : 1; + bond_pads : 1; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 1341.23; + when : "!c2p_en&!c2p"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 9639.64; + when : "!c2p_en&!c2p"; + related_pg_pin : vdd; + } + leakage_power () { + value : 1341.23; + when : "!c2p_en&c2p"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 9822.19; + when : "!c2p_en&c2p"; + related_pg_pin : vdd; + } + leakage_power () { + value : 1496.85; + when : "c2p_en&c2p&pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 14975; + when : "c2p_en&c2p&pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 9047.94; + when : "c2p_en&!c2p&!pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 14498.2; + when : "c2p_en&!c2p&!pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 3306.81; + related_pg_pin : iovdd; + } + leakage_power () { + value : 12233.7; + related_pg_pin : vdd; + } + pin (pad) { + direction : "output"; + is_pad : true; + function : "c2p"; + three_state : "c2p_en'"; + drive_current : 30; + output_voltage : "pad"; + related_ground_pin : iovss; + related_power_pin : iovdd; + max_capacitance : 0.370793; + capacitance : 0.344907; + rise_capacitance : 0.343194; + rise_capacitance_range (0.343194, 0.343194); + fall_capacitance : 0.346619; + fall_capacitance_range (0.346619, 0.346619); + timing () { + related_pin : "c2p"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.52507, 2.73633, 2.90777, 3.05702, 3.43538, 3.76666", \ + "2.54285, 2.75351, 2.92461, 3.07359, 3.45223, 3.78331", \ + "2.55198, 2.76307, 2.93401, 3.08302, 3.46138, 3.79265", \ + "2.56662, 2.77757, 2.94865, 3.09767, 3.47621, 3.80728", \ + "2.58432, 2.79497, 2.96607, 3.11457, 3.49363, 3.82456", \ + "2.60382, 2.81506, 2.98604, 3.1353, 3.51389, 3.84497", \ + "2.60694, 2.81877, 2.99029, 3.13979, 3.51886, 3.84987" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.734802, 0.978895, 1.18768, 1.38077, 1.91761, 2.44339", \ + "0.734803, 0.978896, 1.18769, 1.38078, 1.91762, 2.44342", \ + "0.734804, 0.978897, 1.1877, 1.38079, 1.91763, 2.44343", \ + "0.734805, 0.978898, 1.18771, 1.3808, 1.91764, 2.44344", \ + "0.734806, 0.978899, 1.18772, 1.38081, 1.91765, 2.44351", \ + "0.734807, 0.9789, 1.18808, 1.38082, 1.91766, 2.44354", \ + "0.734824, 0.980045, 1.18961, 1.38108, 1.91767, 2.44402" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.08108, 2.2131, 2.33199, 2.4429, 2.74431, 3.01782", \ + "2.10029, 2.23189, 2.35084, 2.46121, 2.76273, 3.03673", \ + "2.11524, 2.24694, 2.36584, 2.47659, 2.77616, 3.05142", \ + "2.15005, 2.2814, 2.40029, 2.51096, 2.81285, 3.08569", \ + "2.20653, 2.33781, 2.45678, 2.56732, 2.86675, 3.14204", \ + "2.29326, 2.42485, 2.54317, 2.65108, 2.95547, 3.22964", \ + "2.44604, 2.57819, 2.69648, 2.80772, 3.10928, 3.38318" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.3565, 1.45478, 1.57645, 1.70421, 2.09572, 2.50435", \ + "1.36152, 1.4595, 1.58031, 1.70777, 2.09985, 2.50743", \ + "1.36511, 1.46294, 1.58299, 1.71016, 2.09986, 2.51583", \ + "1.37213, 1.46884, 1.58836, 1.71528, 2.10585, 2.52037", \ + "1.37425, 1.47068, 1.58987, 1.71683, 2.10586, 2.52079", \ + "1.37426, 1.47069, 1.58988, 1.71684, 2.10587, 2.5208", \ + "1.37427, 1.4707, 1.58989, 1.71685, 2.10588, 2.52081" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : negative_unate; + timing_type : three_state_disable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.86845, 1.86846, 1.86847, 1.86848, 1.86849, 1.8685", \ + "1.88882, 1.88883, 1.88884, 1.88885, 1.88886, 1.88887", \ + "1.90532, 1.90533, 1.90534, 1.90535, 1.90536, 1.90537", \ + "1.92892, 1.92893, 1.92894, 1.92895, 1.92896, 1.92897", \ + "1.96384, 1.96385, 1.96386, 1.96387, 1.96388, 1.96389", \ + "2.02876, 2.02877, 2.02878, 2.02879, 2.0288, 2.02881", \ + "2.11602, 2.11603, 2.11604, 2.11605, 2.11606, 2.11607" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.86845, 1.86846, 1.86847, 1.86848, 1.86849, 1.8685", \ + "1.88882, 1.88883, 1.88884, 1.88885, 1.88886, 1.88887", \ + "1.90532, 1.90533, 1.90534, 1.90535, 1.90536, 1.90537", \ + "1.92892, 1.92893, 1.92894, 1.92895, 1.92896, 1.92897", \ + "1.96384, 1.96385, 1.96386, 1.96387, 1.96388, 1.96389", \ + "2.02876, 2.02877, 2.02878, 2.02879, 2.0288, 2.02881", \ + "2.11602, 2.11603, 2.11604, 2.11605, 2.11606, 2.11607" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.49341, 2.49342, 2.49343, 2.49344, 2.49345, 2.49346", \ + "2.51583, 2.51584, 2.51585, 2.51586, 2.51587, 2.51588", \ + "2.53994, 2.53995, 2.53996, 2.53997, 2.53998, 2.53999", \ + "2.5733, 2.57331, 2.57332, 2.57333, 2.57334, 2.57335", \ + "2.59995, 2.59996, 2.59997, 2.59998, 2.59999, 2.6", \ + "2.70329, 2.7033, 2.70331, 2.70332, 2.70333, 2.70334", \ + "2.83514, 2.83515, 2.83516, 2.83517, 2.83518, 2.83519" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.49341, 2.49342, 2.49343, 2.49344, 2.49345, 2.49346", \ + "2.51583, 2.51584, 2.51585, 2.51586, 2.51587, 2.51588", \ + "2.53994, 2.53995, 2.53996, 2.53997, 2.53998, 2.53999", \ + "2.5733, 2.57331, 2.57332, 2.57333, 2.57334, 2.57335", \ + "2.59995, 2.59996, 2.59997, 2.59998, 2.59999, 2.6", \ + "2.70329, 2.7033, 2.70331, 2.70332, 2.70333, 2.70334", \ + "2.83514, 2.83515, 2.83516, 2.83517, 2.83518, 2.83519" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : positive_unate; + timing_type : three_state_enable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.4757, 2.70202, 2.88038, 3.03469, 3.42164, 3.75462", \ + "2.49134, 2.7179, 2.89648, 3.0502, 3.43731, 3.7694", \ + "2.50178, 2.72852, 2.90667, 3.0599, 3.44492, 3.78027", \ + "2.51921, 2.74637, 2.92335, 3.07818, 3.4648, 3.79393", \ + "2.53913, 2.76635, 2.9439, 3.09782, 3.4854, 3.81886", \ + "2.56024, 2.7863, 2.96431, 3.11738, 3.50591, 3.83925", \ + "2.57563, 2.80272, 2.98099, 3.13472, 3.51816, 3.85505" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.794896, 1.01764, 1.21673, 1.40483, 1.93651, 2.45309", \ + "0.795271, 1.01815, 1.21692, 1.40484, 1.93656, 2.4531", \ + "0.795272, 1.01914, 1.21702, 1.40485, 1.93657, 2.45311", \ + "0.795328, 1.01915, 1.21703, 1.40514, 1.93658, 2.45312", \ + "0.795671, 1.01916, 1.21704, 1.40515, 1.93659, 2.4534", \ + "0.795672, 1.01917, 1.21705, 1.40516, 1.9366, 2.45341", \ + "0.795673, 1.01918, 1.21706, 1.40517, 1.93661, 2.45342" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.49542, 1.674, 1.81859, 1.94881, 2.2876, 2.58646", \ + "1.51229, 1.69009, 1.83573, 1.96212, 2.30298, 2.60331", \ + "1.52247, 1.70059, 1.84518, 1.97533, 2.31423, 2.61787", \ + "1.53419, 1.71198, 1.85763, 1.98365, 2.32485, 2.62508", \ + "1.55059, 1.7287, 1.87326, 2.00343, 2.34233, 2.64215", \ + "1.56194, 1.73971, 1.88544, 2.01463, 2.35332, 2.65263", \ + "1.56455, 1.74161, 1.887, 2.0171, 2.35607, 2.65667" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.610561, 0.810264, 0.989253, 1.16207, 1.65881, 2.14949", \ + "0.613093, 0.810265, 0.990145, 1.16208, 1.65882, 2.14973", \ + "0.613094, 0.810334, 0.990146, 1.16209, 1.65898, 2.15283", \ + "0.613101, 0.810335, 0.990155, 1.1621, 1.65899, 2.15284", \ + "0.613102, 0.810336, 0.990156, 1.16211, 1.659, 2.15285", \ + "0.613103, 0.810337, 0.990157, 1.16219, 1.65901, 2.15286", \ + "0.613104, 0.810338, 0.990158, 1.1622, 1.65998, 2.15287" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "7.98034, 7.83259, 7.77864, 7.77312, 7.61841, 7.73232", \ + "8.00323, 7.85027, 7.79094, 7.7565, 7.63701, 7.73103", \ + "7.99775, 7.85903, 7.7913, 7.75821, 7.63461, 7.73424", \ + "7.99528, 7.85003, 7.78836, 7.75644, 7.64322, 7.73232", \ + "7.9976, 7.85029, 7.78665, 7.68723, 7.64025, 7.7205", \ + "7.98607, 7.84197, 7.77681, 7.75275, 7.64193, 7.72584", \ + "7.89015, 7.77813, 7.73427, 7.7148, 7.59255, 7.71147" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "41.5995, 39.0255, 36.8768, 35.0742, 30.8937, 27.9478", \ + "41.791, 39.2232, 37.0673, 35.2777, 31.0929, 28.1156", \ + "41.966, 39.3793, 37.2404, 35.3846, 31.186, 28.2559", \ + "42.2303, 39.6493, 37.5015, 35.6354, 31.4301, 28.4619", \ + "42.3222, 39.7347, 37.5824, 35.7113, 31.4798, 28.52", \ + "42.1388, 39.5575, 37.3929, 35.5532, 31.3416, 28.3695", \ + "41.5923, 39.0172, 36.8899, 35.0946, 30.8941, 27.9855" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.0616719, 0.0616727, 0.0616733, 0.0616721, 0.0616721, 0.0616725", \ + "0.0595265, 0.0595268, 0.0595269, 0.0595266, 0.0595262, 0.0595275", \ + "0.0607912, 0.0607914, 0.0607916, 0.0607914, 0.0607908, 0.0607916", \ + "0.0662775, 0.0662776, 0.0662772, 0.0662773, 0.0662763, 0.0662776", \ + "0.0825851, 0.082585, 0.0825847, 0.0825855, 0.0825847, 0.0825857", \ + "0.121234, 0.121235, 0.121234, 0.121234, 0.121234, 0.121235", \ + "0.207465, 0.207465, 0.207463, 0.207465, 0.207463, 0.207464" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.149147, 0.149146, 0.149145, 0.149146, 0.149146, 0.149144", \ + "0.146701, 0.146702, 0.146701, 0.146703, 0.146704, 0.146701", \ + "0.147897, 0.147895, 0.147896, 0.147895, 0.147897, 0.147895", \ + "0.153791, 0.153789, 0.153789, 0.153789, 0.153791, 0.153788", \ + "0.17062, 0.170618, 0.17062, 0.170618, 0.170619, 0.170618", \ + "0.210191, 0.210188, 0.210188, 0.210189, 0.21019, 0.210189", \ + "0.294964, 0.295063, 0.295162, 0.295195, 0.294947, 0.295081" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "6.98408, 6.98102, 7.03149, 7.11057, 7.29063, 7.34253", \ + "6.98712, 6.99434, 7.04979, 7.1067, 7.2972, 7.33665", \ + "6.98978, 7.00156, 7.04955, 7.09902, 7.23024, 7.35429", \ + "6.9842, 7.00537, 6.97896, 7.10799, 7.28742, 7.18422", \ + "6.97908, 6.9987, 7.02498, 7.09761, 7.29732, 7.35777", \ + "6.98915, 6.98846, 7.02813, 7.07103, 7.30326, 7.36671", \ + "6.98406, 7.00652, 7.05591, 7.1205, 7.10574, 7.38165" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "3.36232, 3.36759, 3.36794, 3.37063, 3.3706, 3.37058", \ + "3.36619, 3.36747, 3.36932, 3.36765, 3.36967, 3.37059", \ + "3.36615, 3.36844, 3.36958, 3.3714, 3.37164, 3.36874", \ + "3.36627, 3.36756, 3.36941, 3.36698, 3.36974, 3.3706", \ + "3.36554, 3.3678, 3.36803, 3.37074, 3.37097, 3.37101", \ + "3.36528, 3.3665, 3.36851, 3.36985, 3.36937, 3.36935", \ + "3.36214, 3.36481, 3.36756, 3.36934, 3.37025, 3.3691" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.0277427, 0.0277426, 0.0277431, 0.0277438, 0.0277455, 0.0277463", \ + "0.0264647, 0.0264647, 0.0264652, 0.0264659, 0.0264675, 0.0264681", \ + "0.029237, 0.029237, 0.0292375, 0.0292381, 0.0292392, 0.0289238", \ + "0.037245, 0.0372451, 0.0372454, 0.0372461, 0.0372476, 0.0372471", \ + "0.0576207, 0.0576207, 0.0576209, 0.0576216, 0.0576233, 0.0576246", \ + "0.101229, 0.101229, 0.10123, 0.101231, 0.101232, 0.101233", \ + "0.19274, 0.19274, 0.19274, 0.19274, 0.192741, 0.192743" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.0468991, 0.0468959, 0.0468978, 0.0468948, 0.0468937, 0.0468914", \ + "0.0458088, 0.0458052, 0.0458063, 0.0458061, 0.0458024, 0.0458022", \ + "0.0469908, 0.0469871, 0.046887, 0.0469862, 0.0469838, 0.0469835", \ + "0.0514206, 0.051417, 0.051418, 0.0514174, 0.0514141, 0.0514141", \ + "0.0620626, 0.0620589, 0.0620616, 0.0620579, 0.0620555, 0.0620543", \ + "0.0851435, 0.0851378, 0.085142, 0.0851368, 0.0851354, 0.0851359", \ + "0.133084, 0.133073, 0.132974, 0.133, 0.133069, 0.132932" \ + ); + } + } + } + pin (c2p) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.016; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0268083; + rise_capacitance : 0.0269944; + rise_capacitance_range (0.0226819, 0.0319489); + fall_capacitance : 0.0266221; + fall_capacitance_range (0.0232108, 0.0286556); + internal_power () { + when : "!c2p_en"; + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0, 0, 0, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0, 0, 0, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + when : "!c2p_en"; + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0201755, -0.0212757, -0.0214403, -0.0214293, -0.0217521, -0.0217799, -0.0219522" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0249844, 0.0245476, 0.024488, 0.0243576, 0.024489, 0.024026, 0.0243078" \ + ); + } + } + internal_power () { + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0, 0, 0, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0, 0, 0, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0201755, -0.0212757, -0.0214403, -0.0214293, -0.0217521, -0.0217799, -0.0219522" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0249844, 0.0245476, 0.024488, 0.0243576, 0.024489, 0.024026, 0.0243078" \ + ); + } + } + } + pin (c2p_en) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.011; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0256659; + rise_capacitance : 0.0265558; + rise_capacitance_range (0.0225487, 0.0322016); + fall_capacitance : 0.024776; + fall_capacitance_range (0.0219389, 0.0283874); + } + } + cell (sg13g2_IOPadTriOut4mA) { + pad_cell : true; + area : 14400; + cell_footprint : "tri_out"; + pad_drivers : 1; + bond_pads : 1; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 536.306; + when : "!c2p_en&!c2p"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 9639.55; + when : "!c2p_en&!c2p"; + related_pg_pin : vdd; + } + leakage_power () { + value : 536.306; + when : "!c2p_en&c2p"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 9822.09; + when : "!c2p_en&c2p"; + related_pg_pin : vdd; + } + leakage_power () { + value : 691.998; + when : "c2p_en&c2p&pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 14974.9; + when : "c2p_en&c2p&pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 1419.38; + when : "c2p_en&!c2p&!pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 14497.9; + when : "c2p_en&!c2p&!pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 795.997; + related_pg_pin : iovdd; + } + leakage_power () { + value : 12233.6; + related_pg_pin : vdd; + } + pin (pad) { + direction : "output"; + is_pad : true; + function : "c2p"; + three_state : "c2p_en'"; + drive_current : 4; + output_voltage : "pad"; + related_ground_pin : iovss; + related_power_pin : iovdd; + max_capacitance : 0.661248; + capacitance : 0.166368; + rise_capacitance : 0.170905; + rise_capacitance_range (0.170905, 0.170905); + fall_capacitance : 0.161831; + fall_capacitance_range (0.161831, 0.161831); + timing () { + related_pin : "c2p"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.27879, 2.94793, 3.61407, 4.27952, 6.2742, 8.26782", \ + "2.29422, 2.96385, 3.62946, 4.29513, 6.28967, 8.28327", \ + "2.30444, 2.97378, 3.63945, 4.30508, 6.29949, 8.29309", \ + "2.3192, 2.98854, 3.65437, 4.32006, 6.31475, 8.30838", \ + "2.33722, 3.0063, 3.67304, 4.33821, 6.33249, 8.32591", \ + "2.35655, 3.02571, 3.69242, 4.35762, 6.35191, 8.34531", \ + "2.36365, 3.03283, 3.69842, 4.36376, 6.3582, 8.35182" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.69854, 3.06618, 4.44873, 5.83349, 10.0003, 14.1653", \ + "1.69855, 3.0665, 4.44874, 5.8335, 10.0004, 14.1654", \ + "1.69873, 3.06719, 4.44875, 5.83351, 10.0005, 14.1655", \ + "1.69874, 3.0672, 4.44876, 5.83352, 10.0006, 14.1656", \ + "1.69875, 3.06721, 4.44877, 5.83353, 10.0007, 14.1657", \ + "1.69876, 3.06722, 4.44878, 5.83354, 10.0008, 14.1658", \ + "1.69926, 3.06723, 4.44879, 5.83355, 10.0009, 14.1659" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.74319, 2.40614, 3.06696, 3.72687, 5.70847, 7.68696", \ + "1.76015, 2.42202, 3.08322, 3.74314, 5.72278, 7.70527", \ + "1.7742, 2.43615, 3.09711, 3.75692, 5.73714, 7.71894", \ + "1.80545, 2.46705, 3.12732, 3.78734, 5.76771, 7.74753", \ + "1.86154, 2.52313, 3.18329, 3.84352, 5.82377, 7.80217", \ + "1.9498, 2.61161, 3.27197, 3.9323, 5.91247, 7.89398", \ + "2.10919, 2.77182, 3.43277, 4.09247, 6.07307, 8.05284" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.58123, 2.87466, 4.17774, 5.48502, 9.40482, 13.3297", \ + "1.5818, 2.87467, 4.17775, 5.48503, 9.40565, 13.3298", \ + "1.58196, 2.87488, 4.17776, 5.48503, 9.40621, 13.3299", \ + "1.58214, 2.87489, 4.17777, 5.48504, 9.40622, 13.333", \ + "1.58215, 2.8749, 4.17795, 5.48505, 9.40623, 13.3331", \ + "1.58216, 2.87491, 4.17796, 5.48506, 9.40624, 13.3332", \ + "1.58217, 2.8763, 4.17797, 5.48507, 9.40625, 13.3333" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : negative_unate; + timing_type : three_state_disable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.33247, 1.33248, 1.33249, 1.3325, 1.33251, 1.33252", \ + "1.35402, 1.35403, 1.35404, 1.35405, 1.35406, 1.35407", \ + "1.37018, 1.37019, 1.3702, 1.37021, 1.37022, 1.37023", \ + "1.39796, 1.39797, 1.39798, 1.39799, 1.398, 1.39801", \ + "1.42963, 1.42964, 1.42965, 1.42966, 1.42967, 1.42968", \ + "1.49661, 1.49662, 1.49663, 1.49664, 1.49665, 1.49666", \ + "1.5854, 1.58541, 1.58542, 1.58543, 1.58544, 1.58545" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.33247, 1.33248, 1.33249, 1.3325, 1.33251, 1.33252", \ + "1.35402, 1.35403, 1.35404, 1.35405, 1.35406, 1.35407", \ + "1.37018, 1.37019, 1.3702, 1.37021, 1.37022, 1.37023", \ + "1.39796, 1.39797, 1.39798, 1.39799, 1.398, 1.39801", \ + "1.42963, 1.42964, 1.42965, 1.42966, 1.42967, 1.42968", \ + "1.49661, 1.49662, 1.49663, 1.49664, 1.49665, 1.49666", \ + "1.5854, 1.58541, 1.58542, 1.58543, 1.58544, 1.58545" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.885671, 0.885672, 0.885673, 0.885674, 0.885675, 0.885676", \ + "0.909177, 0.909178, 0.909179, 0.90918, 0.909181, 0.909182", \ + "0.925583, 0.925584, 0.925585, 0.925586, 0.925587, 0.925588", \ + "0.962949, 0.96295, 0.962951, 0.962952, 0.962953, 0.962954", \ + "1.01826, 1.01827, 1.01828, 1.01829, 1.0183, 1.01831", \ + "1.09664, 1.09665, 1.09666, 1.09667, 1.09668, 1.09669", \ + "1.2354, 1.23541, 1.23542, 1.23543, 1.23544, 1.23545" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.885671, 0.885672, 0.885673, 0.885674, 0.885675, 0.885676", \ + "0.909177, 0.909178, 0.909179, 0.90918, 0.909181, 0.909182", \ + "0.925583, 0.925584, 0.925585, 0.925586, 0.925587, 0.925588", \ + "0.962949, 0.96295, 0.962951, 0.962952, 0.962953, 0.962954", \ + "1.01826, 1.01827, 1.01828, 1.01829, 1.0183, 1.01831", \ + "1.09664, 1.09665, 1.09666, 1.09667, 1.09668, 1.09669", \ + "1.2354, 1.23541, 1.23542, 1.23543, 1.23544, 1.23545" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : positive_unate; + timing_type : three_state_enable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.28268, 2.97035, 3.6549, 4.33822, 6.38897, 8.43642", \ + "2.29796, 2.98498, 3.66998, 4.35255, 6.40219, 8.45162", \ + "2.30814, 2.99554, 3.68204, 4.36486, 6.41285, 8.46291", \ + "2.32519, 3.01207, 3.69708, 4.37963, 6.43021, 8.47877", \ + "2.34576, 3.03317, 3.71802, 4.40131, 6.44977, 8.49963", \ + "2.3682, 3.05548, 3.74202, 4.42564, 6.47378, 8.52256", \ + "2.3812, 3.06802, 3.75202, 4.43491, 6.48415, 8.533" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.69716, 3.06536, 4.44764, 5.83186, 9.99419, 14.1652", \ + "1.69739, 3.06622, 4.4483, 5.83246, 9.99636, 14.1653", \ + "1.6974, 3.06623, 4.4487, 5.83314, 9.99637, 14.1654", \ + "1.6975, 3.06624, 4.44871, 5.83315, 10.0003, 14.1655", \ + "1.69751, 3.06625, 4.44872, 5.83468, 10.0004, 14.1656", \ + "1.69752, 3.06626, 4.44873, 5.83469, 10.0005, 14.1657", \ + "1.69753, 3.06627, 4.44874, 5.8347, 10.0006, 14.1658" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.72899, 2.40992, 3.08905, 3.76813, 5.803, 7.83554", \ + "1.74542, 2.42642, 3.10534, 3.78386, 5.81948, 7.85201", \ + "1.75482, 2.43575, 3.11489, 3.79397, 5.82885, 7.86138", \ + "1.76739, 2.44861, 3.1276, 3.80674, 5.84057, 7.87413", \ + "1.78396, 2.46511, 3.14426, 3.82265, 5.85713, 7.89067", \ + "1.7936, 2.47482, 3.15358, 3.83293, 5.86679, 7.90035", \ + "1.7985, 2.47992, 3.15833, 3.83655, 5.8727, 7.90497" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.58143, 2.87384, 4.17579, 5.482, 9.40478, 13.3306", \ + "1.58144, 2.87385, 4.17667, 5.48298, 9.40479, 13.3307", \ + "1.58145, 2.87386, 4.17668, 5.48299, 9.4048, 13.3308", \ + "1.58151, 2.87408, 4.17672, 5.483, 9.40634, 13.3309", \ + "1.58152, 2.87409, 4.17673, 5.48301, 9.4068, 13.331", \ + "1.58153, 2.8741, 4.17674, 5.48302, 9.40681, 13.3311", \ + "1.58154, 2.87411, 4.17675, 5.48466, 9.40682, 13.3312" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.56528, 2.53928, 2.51653, 2.47725, 2.4192, 2.38032", \ + "2.56688, 2.54149, 2.51816, 2.49114, 2.4213, 2.38203", \ + "2.56515, 2.54153, 2.5122, 2.48721, 2.42091, 2.38188", \ + "2.56291, 2.53669, 2.51401, 2.48394, 2.41575, 2.37852", \ + "2.56104, 2.53581, 2.51035, 2.48199, 2.41701, 2.37621", \ + "2.56019, 2.53783, 2.50758, 2.48811, 2.41761, 2.37681", \ + "2.55401, 2.53331, 2.50607, 2.47911, 2.4087, 2.37018" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.49763, 1.48883, 1.48588, 1.48417, 1.48202, 1.48", \ + "1.49997, 1.49117, 1.48713, 1.48533, 1.48166, 1.48145", \ + "1.50573, 1.49505, 1.49006, 1.48773, 1.48435, 1.48164", \ + "1.51026, 1.49728, 1.49152, 1.48864, 1.48329, 1.48215", \ + "1.51306, 1.49997, 1.49358, 1.49053, 1.48467, 1.48304", \ + "1.50495, 1.49307, 1.48785, 1.48526, 1.48124, 1.47862", \ + "1.50098, 1.49244, 1.49022, 1.48788, 1.48582, 1.48372" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.0617664, 0.0617641, 0.0617639, 0.0617652, 0.061766, 0.0617658", \ + "0.0596269, 0.0596258, 0.0596242, 0.0596243, 0.0596262, 0.0596262", \ + "0.0608907, 0.0608883, 0.0608879, 0.0608877, 0.0608886, 0.0608885", \ + "0.0663747, 0.0663718, 0.0663718, 0.0663729, 0.0663747, 0.0663738", \ + "0.0826837, 0.0826811, 0.0826798, 0.082682, 0.0826819, 0.082682", \ + "0.121339, 0.121337, 0.121336, 0.121339, 0.121338, 0.121338", \ + "0.207607, 0.207609, 0.2076, 0.207603, 0.2076, 0.2076" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.14951, 0.149509, 0.149508, 0.149505, 0.149501, 0.149503", \ + "0.147052, 0.147053, 0.147052, 0.147052, 0.147051, 0.147054", \ + "0.148267, 0.148266, 0.148261, 0.148263, 0.148258, 0.14826", \ + "0.154149, 0.154147, 0.154144, 0.154148, 0.154143, 0.154151", \ + "0.171001, 0.171001, 0.170997, 0.170996, 0.17099, 0.170996", \ + "0.210567, 0.210565, 0.210561, 0.210563, 0.210557, 0.210561", \ + "0.295509, 0.295434, 0.295463, 0.295361, 0.295447, 0.295371" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.40587, 2.50737, 2.6037, 2.70456, 3.0153, 3.37335", \ + "2.40333, 2.49954, 2.6022, 2.70288, 3.01404, 3.37062", \ + "2.40289, 2.50186, 2.61631, 2.70399, 3.02532, 3.3771", \ + "2.40258, 2.49881, 2.59838, 2.69817, 3.02637, 3.36654", \ + "2.40484, 2.49447, 2.60191, 2.70528, 3.01044, 3.36516", \ + "2.40449, 2.50123, 2.61544, 2.71092, 3.01782, 3.37659", \ + "2.38996, 2.4899, 2.58702, 2.68965, 3.00786, 3.35763" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.864872, 0.864865, 0.864512, 0.864034, 0.864668, 0.864562", \ + "0.864581, 0.864426, 0.864223, 0.86377, 0.864249, 0.863717", \ + "0.864988, 0.865022, 0.864623, 0.864143, 0.864752, 0.864167", \ + "0.865425, 0.865829, 0.866003, 0.864787, 0.865072, 0.864938", \ + "0.86556, 0.865881, 0.865196, 0.866266, 0.865517, 0.865353", \ + "0.862765, 0.863058, 0.86271, 0.862219, 0.862547, 0.862415", \ + "0.865354, 0.865155, 0.865649, 0.865683, 0.864792, 0.865315" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.0278378, 0.0278359, 0.0278343, 0.0278346, 0.0278366, 0.0278356", \ + "0.0265601, 0.0265561, 0.0265565, 0.0265572, 0.0265588, 0.0265583", \ + "0.0292842, 0.0292841, 0.0292845, 0.0292847, 0.0292851, 0.0292848", \ + "0.0373438, 0.0373404, 0.0373399, 0.0373402, 0.037343, 0.0373419", \ + "0.0577167, 0.0577127, 0.0577129, 0.057713, 0.0577162, 0.0577148", \ + "0.103071, 0.103069, 0.10307, 0.103071, 0.10307, 0.103072", \ + "0.196818, 0.196814, 0.1968, 0.196802, 0.1968, 0.196801" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.0472905, 0.0472952, 0.0472926, 0.0472909, 0.0472899, 0.0472882", \ + "0.0462019, 0.0462057, 0.0462032, 0.0462016, 0.0461996, 0.0461989", \ + "0.0473697, 0.0473746, 0.0473718, 0.0473703, 0.0474249, 0.0474239", \ + "0.0518357, 0.0518335, 0.0518334, 0.0518324, 0.051833, 0.0518291", \ + "0.062472, 0.0624724, 0.0624695, 0.0624701, 0.0624693, 0.0624653", \ + "0.0862549, 0.0862533, 0.0862533, 0.0862509, 0.0862496, 0.0862431", \ + "0.13567, 0.135687, 0.135703, 0.135676, 0.135687, 0.135551" \ + ); + } + } + } + pin (c2p) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.016; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.026807; + rise_capacitance : 0.0269943; + rise_capacitance_range (0.0226816, 0.0319487); + fall_capacitance : 0.0266197; + fall_capacitance_range (0.0232105, 0.0286558); + internal_power () { + when : "!c2p_en"; + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0, 0, 0, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0, 0, 0, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + when : "!c2p_en"; + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0201757, -0.021276, -0.0214403, -0.0214293, -0.0217521, -0.02178, -0.0219522" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0249923, 0.0245498, 0.0245079, 0.024285, 0.0244947, 0.024091, 0.024012" \ + ); + } + } + internal_power () { + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0, 0, 0, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0, 0, 0, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0201757, -0.021276, -0.0214403, -0.0214293, -0.0217521, -0.02178, -0.0219522" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0249923, 0.0245498, 0.0245079, 0.024285, 0.0244947, 0.024091, 0.024012" \ + ); + } + } + } + pin (c2p_en) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.011; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0256606; + rise_capacitance : 0.0265437; + rise_capacitance_range (0.0225499, 0.0320677); + fall_capacitance : 0.0247774; + fall_capacitance_range (0.0219411, 0.0283296); + } + } + cell (sg13g2_IOPadVdd) { + area : 14400; + pad_cell : true; + bond_pads : 1; + dont_touch : true; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + is_pad : true; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 0; + related_pg_pin : iovdd; + } + leakage_power () { + value : 5.66442; + related_pg_pin : vdd; + } + } + cell (sg13g2_IOPadVss) { + area : 14400; + pad_cell : true; + bond_pads : 1; + dont_touch : true; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + is_pad : true; + } + leakage_power () { + value : 0; + related_pg_pin : iovdd; + } + leakage_power () { + value : 1.20533; + related_pg_pin : vdd; + } + } +} diff --git a/flow/platforms/ihp-sg13g2/lib/sg13g2_io_typ_1p2V_3p3V_25C.lib b/flow/platforms/ihp-sg13g2/lib/sg13g2_io_typ_1p2V_3p3V_25C.lib new file mode 100644 index 0000000000..ba6b43f67a --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lib/sg13g2_io_typ_1p2V_3p3V_25C.lib @@ -0,0 +1,4599 @@ +/************************************************************************ + + Copyright 2024 IHP PDK Authors + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + https://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +************************************************************************/ + +library (sg13g2_io_typ_1p2V_3p3V_25C) { + comment : "IHP Microelectronics GmbH, 2024"; + date : "$Date: Wed May 8 12:19:26 2024 $"; + revision : "$Revision: 0.0.1 $"; + delay_model : table_lookup; + capacitive_load_unit (1,pf); + current_unit : "1uA"; + leakage_power_unit : "1pW"; + pulling_resistance_unit : "1kohm"; + time_unit : "1ns"; + voltage_unit : "1V"; + voltage_map (vdd, 1.2); + voltage_map (iovdd, 3.3); + voltage_map (iovss, 0); + voltage_map (vss, 0); + voltage_map (GND, 0); + define_cell_area (pad_drivers, pad_driver_sites); + define_cell_area (bond_pads, pad_slots); + default_output_pin_cap : 0; + default_inout_pin_cap : 1; + default_input_pin_cap : 1; + default_fanout_load : 1; + default_cell_leakage_power : 0; + default_max_transition : 1.2; + default_leakage_power_density : 0; + default_max_capacitance : 0.3; + default_max_fanout : 8; + default_wire_load_area : 0.29; + default_wire_load_capacitance : 0.0003; + default_wire_load_mode : "enclosed"; + default_wire_load_resistance : 0.0057; + in_place_swap_mode : match_footprint; + input_threshold_pct_fall : 50; + input_threshold_pct_rise : 50; + nom_process : 1; + nom_temperature : 25; + nom_voltage : 1.2; + output_threshold_pct_fall : 50; + output_threshold_pct_rise : 50; + slew_derate_from_library : 1; + slew_lower_threshold_pct_fall : 10; + slew_lower_threshold_pct_rise : 10; + slew_upper_threshold_pct_fall : 90; + slew_upper_threshold_pct_rise : 90; + operating_conditions (sg13g2_io_typ_1p2V_3p3V_25C) { + process : 1; + temperature : 25; + voltage : 1.2; + } + input_voltage (pad) { + vih : 3.3; + vil : 0; + vimax : 3.3; + vimin : 0; + } + input_voltage (core) { + vih : 1.2; + vil : 0; + vimax : 1.2; + vimin : 0; + } + output_voltage (pad) { + voh : 3.3; + vol : 0; + vomax : 3.3; + vomin : 0; + } + output_voltage (core) { + voh : 1.2; + vol : 0; + vomax : 1.2; + vomin : 0; + } + wire_load (Zero) { + area : 0.01; + capacitance : 0.0001; + resistance : 0.0001; + slope : 1; + fanout_length (1, 0.01); + fanout_length (5, 0.01); + fanout_length (20, 0.01); + } + wire_load ("0_1k") { + area : 0.36; + capacitance : 0.0001; + resistance : 0.0035; + slope : 7.387; + fanout_length (1, 6.43); + fanout_length (5, 38.56); + fanout_length (20, 146.8); + } + wire_load ("0_5k") { + area : 0.36; + capacitance : 0.0001; + resistance : 0.0042; + slope : 10.99; + fanout_length (1, 7.89); + fanout_length (5, 47.32); + fanout_length (20, 169.4); + } + wire_load ("1k") { + area : 0.36; + capacitance : 0.0002; + resistance : 0.0053; + slope : 10.9; + fanout_length (1, 9.93); + fanout_length (5, 59.59); + fanout_length (20, 215.6); + } + wire_load ("2k") { + area : 0.36; + capacitance : 0.0002; + resistance : 0.0063; + slope : 16.87; + fanout_length (1, 11.68); + fanout_length (5, 70.11); + fanout_length (20, 239.5); + } + wire_load ("5k") { + area : 0.36; + capacitance : 0.0003; + resistance : 0.0072; + slope : 14.58; + fanout_length (1, 13.44); + fanout_length (5, 80.62); + fanout_length (20, 287.1); + } + wire_load ("10k") { + area : 0.37; + capacitance : 0.0003; + resistance : 0.008; + slope : 18.94; + fanout_length (1, 14.9); + fanout_length (5, 89.39); + fanout_length (20, 381.6); + } + wire_load ("30k") { + area : 0.37; + capacitance : 0.0003; + resistance : 0.0094; + slope : 24.61; + fanout_length (1, 17.53); + fanout_length (5, 105.2); + fanout_length (20, 515.5); + } + wire_load ("50k") { + area : 0.37; + capacitance : 0.0005; + resistance : 0.0152; + slope : 31.81; + fanout_length (1, 28.33); + fanout_length (5, 170); + fanout_length (20, 607.6); + } + wire_load ("100k") { + area : 0.39; + capacitance : 0.0009; + resistance : 0.0265; + slope : 40.22; + fanout_length (1, 49.37); + fanout_length (5, 296.2); + fanout_length (20, 812.1); + } + wire_load ("200k") { + area : 0.41; + capacitance : 0.0016; + resistance : 0.0456; + slope : 52.68; + fanout_length (1, 84.71); + fanout_length (5, 508.3); + fanout_length (20, 1051.7); + } + wire_load ("500k") { + area : 0.45; + capacitance : 0.0027; + resistance : 0.076; + slope : 67.44; + fanout_length (1, 141.4); + fanout_length (5, 848.3); + fanout_length (20, 1527.1); + } + wire_load_selection ("4_metls_routing") { + wire_load_from_area (0, 635, 0_1k); + wire_load_from_area (635, 3175, 0_5k); + wire_load_from_area (3175, 6350, 1k); + wire_load_from_area (6350, 12701, 2k); + wire_load_from_area (12701, 31752, 5k); + wire_load_from_area (31752, 63504, 10k); + wire_load_from_area (63504, 190512, 30k); + wire_load_from_area (190512, 317520, 50k); + wire_load_from_area (317520, 635040, 100k); + wire_load_from_area (635040, 1.27008e+06, 200k); + wire_load_from_area (1.27008e+06, 3.1752e+06, 500k); + } + default_wire_load : "1k"; + default_operating_conditions : sg13g2_io_typ_1p2V_3p3V_25C; + default_wire_load_selection : "4_metls_routing"; + lu_table_template (delay_template_7x6_16) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 3, 7, 9, 12, 15"); + } + power_lut_template (passive_power_template_7x1_16) { + variable_1 : input_transition_time; + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + } + power_lut_template (power_template_7x6_16) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 3, 7, 9, 12, 15"); + } + cell (sg13g2_IOPadIOVdd) { + area : 14400; + pad_cell : true; + bond_pads : 1; + dont_touch : true; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + is_pad : true; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 4853.24; + related_pg_pin : iovdd; + } + leakage_power () { + value : 0; + related_pg_pin : vdd; + } + } + cell (sg13g2_IOPadIOVss) { + area : 14400; + pad_cell : true; + bond_pads : 1; + dont_touch : true; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + is_pad : true; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 0; + related_pg_pin : iovdd; + } + leakage_power () { + value : 1.51487; + related_pg_pin : vdd; + } + } + cell (sg13g2_IOPadIn) { + pad_cell : true; + area : 14400; + cell_footprint : "input"; + pad_drivers : 1; + bond_pads : 1; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 0; + when : "pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 209.155; + when : "pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 0; + when : "!pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 306.047; + when : "!pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 0; + related_pg_pin : iovdd; + } + leakage_power () { + value : 257.601; + related_pg_pin : vdd; + } + pin (p2c) { + direction : "output"; + output_voltage : "core"; + function : "pad"; + related_ground_pin : vss; + related_power_pin : vdd; + max_capacitance : 0.813522; + timing () { + related_pin : "pad"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0829273, 0.101695, 0.13584, 0.168766, 0.201454, 0.234094", \ + "0.0829283, 0.101696, 0.135841, 0.168767, 0.201455, 0.234095", \ + "0.0829293, 0.101697, 0.135842, 0.168768, 0.201456, 0.234096", \ + "0.0829303, 0.101698, 0.135843, 0.168769, 0.201457, 0.234097", \ + "0.0829313, 0.101699, 0.135844, 0.16877, 0.201458, 0.234098", \ + "0.0829323, 0.1017, 0.135845, 0.168771, 0.201459, 0.234099", \ + "0.0829333, 0.101701, 0.135846, 0.168772, 0.20146, 0.2341" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0627496, 0.0960629, 0.163818, 0.23243, 0.301399, 0.370782", \ + "0.0659365, 0.100241, 0.169105, 0.237391, 0.306332, 0.375597", \ + "0.0712358, 0.104239, 0.171815, 0.241049, 0.311013, 0.38026", \ + "0.0739275, 0.106289, 0.17363, 0.241928, 0.311263, 0.381601", \ + "0.0865204, 0.116934, 0.181456, 0.248389, 0.315962, 0.384236", \ + "0.109874, 0.13904, 0.198839, 0.262058, 0.326825, 0.392622", \ + "0.129222, 0.157402, 0.214295, 0.274662, 0.337776, 0.403138" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.449604, 0.477094, 0.518977, 0.552833, 0.583909, 0.614134", \ + "0.492961, 0.520273, 0.56209, 0.596678, 0.627309, 0.657611", \ + "0.615137, 0.642508, 0.684446, 0.718973, 0.749963, 0.779167", \ + "0.658122, 0.685687, 0.727514, 0.761964, 0.79337, 0.821863", \ + "0.992682, 1.02037, 1.06208, 1.09646, 1.1276, 1.15725", \ + "1.63254, 1.65994, 1.70145, 1.73556, 1.76719, 1.79685", \ + "2.22332, 2.25073, 2.29188, 2.32647, 2.35748, 2.38737" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.13202, 0.157585, 0.202799, 0.24694, 0.291822, 0.337534", \ + "0.132021, 0.157586, 0.203179, 0.247356, 0.291823, 0.337535", \ + "0.132022, 0.157587, 0.20318, 0.247357, 0.291824, 0.337536", \ + "0.132023, 0.157588, 0.203181, 0.247358, 0.291825, 0.337537", \ + "0.132024, 0.157589, 0.203182, 0.247359, 0.291826, 0.337538", \ + "0.132686, 0.158385, 0.203403, 0.24736, 0.292332, 0.337745", \ + "0.145177, 0.168636, 0.212183, 0.255025, 0.29814, 0.343628" \ + ); + } + } + internal_power () { + related_pin : "pad"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "7.79824e-09, 7.79829e-09, 7.79837e-09, 7.79789e-09, 7.79797e-09, 7.7971e-09", \ + "1.51474e-08, 1.51485e-08, 1.51484e-08, 1.51484e-08, 1.51488e-08, 1.5148e-08", \ + "2.9851e-08, 2.98512e-08, 2.985e-08, 2.985e-08, 2.98493e-08, 2.98495e-08", \ + "3.7203e-08, 3.72023e-08, 3.7203e-08, 3.72006e-08, 3.72006e-08, 3.72004e-08", \ + "7.39566e-08, 7.39582e-08, 7.39568e-08, 7.39537e-08, 7.39556e-08, 7.39555e-08", \ + "1.47464e-07, 1.47466e-07, 1.47465e-07, 1.47468e-07, 1.47465e-07, 1.47464e-07", \ + "2.14849e-07, 2.14846e-07, 2.14847e-07, 2.14853e-07, 2.14853e-07, 2.14847e-07" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "-7.79784e-09, -7.79781e-09, -7.79785e-09, -7.79789e-09, -7.79792e-09, -7.7971e-09", \ + "-1.51474e-08, -1.51485e-08, -1.51484e-08, -1.51484e-08, -1.51488e-08, -1.5148e-08", \ + "-2.9851e-08, -2.98512e-08, -2.985e-08, -2.985e-08, -2.98493e-08, -2.98495e-08", \ + "-3.72023e-08, -3.72023e-08, -3.72023e-08, -3.72006e-08, -3.72006e-08, -3.72004e-08", \ + "-7.39554e-08, -7.39554e-08, -7.39554e-08, -7.39537e-08, -7.39555e-08, -7.39555e-08", \ + "-1.47462e-07, -1.47462e-07, -1.47462e-07, -1.47462e-07, -1.47462e-07, -1.47462e-07", \ + "-2.14842e-07, -2.14841e-07, -2.14842e-07, -2.14842e-07, -2.14842e-07, -2.14842e-07" \ + ); + } + } + internal_power () { + related_pin : "pad"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "1.18318e-05, 0.000299688, 0.000553319, 0.00059101, 0.000269279, -0.000121671", \ + "-0.000282504, -0.00017142, -0.000161881, -0.00016955, -0.000346681, -0.000603351", \ + "-0.00123846, -0.00121745, -0.000548881, -0.00054815, -0.000828961, -0.00120935", \ + "-0.00136244, -0.00138007, -0.00127164, -0.00107975, -0.00148392, -0.00184187", \ + "-0.00192428, -0.00237772, -0.00206616, -0.00279551, -0.00262188, -0.00221555", \ + "-0.00187183, -0.00232244, -0.00211992, -0.00292007, -0.00274644, -0.00420335", \ + "-0.00153923, -0.00185651, -0.00257868, -0.00354743, -0.00457524, -0.00384227" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0533388, 0.0529775, 0.0530701, 0.0532902, 0.0534913, 0.0536627", \ + "0.052193, 0.0518383, 0.051934, 0.0521529, 0.0523288, 0.0524867", \ + "0.0518106, 0.0514234, 0.0514885, 0.0516938, 0.0518567, 0.0519733", \ + "0.0510166, 0.050624, 0.0506358, 0.050791, 0.0509417, 0.0510443", \ + "0.0508556, 0.0504956, 0.0505065, 0.0506659, 0.0508037, 0.0509258", \ + "0.0513875, 0.0508272, 0.0505433, 0.0504994, 0.0505228, 0.0505632", \ + "0.0528457, 0.0520097, 0.0516669, 0.0515274, 0.0514654, 0.0514455" \ + ); + } + } + } + pin (pad) { + direction : "input"; + is_pad : true; + input_voltage : "pad"; + fanout_load : 1; + related_ground_pin : iovss; + related_power_pin : iovdd; + max_transition : 3.5; + capacitance : 0.220657; + rise_capacitance : 0.222681; + rise_capacitance_range (0.195297, 0.241559); + fall_capacitance : 0.218632; + fall_capacitance_range (0.197848, 0.232141); + } + } + cell (sg13g2_IOPadInOut16mA) { + pad_cell : true; + area : 14400; + cell_footprint : "inout"; + pad_drivers : 1; + bond_pads : 1; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 527.669; + when : "!c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 1735.07; + when : "!c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 527.669; + when : "!c2p_en&c2p&!pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 1889.28; + when : "!c2p_en&c2p&!pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 4.74047; + when : "!c2p_en&!c2p&pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 1637.78; + when : "!c2p_en&!c2p&pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 4.74047; + when : "!c2p_en&c2p&pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 1792.35; + when : "!c2p_en&c2p&pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 8.09409; + when : "c2p_en&c2p&pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 1965.76; + when : "c2p_en&c2p&pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 8.09409; + when : "c2p_en&c2p&pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 1965.72; + when : "c2p_en&c2p&pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 525.668; + when : "c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 2042.39; + when : "c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 525.668; + when : "c2p_en&!c2p&!pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 2042.4; + when : "c2p_en&!c2p&!pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 266.543; + related_pg_pin : iovdd; + } + leakage_power () { + value : 1883.84; + related_pg_pin : vdd; + } + pin (pad) { + direction : "inout"; + is_pad : true; + function : "c2p"; + three_state : "c2p_en'"; + drive_current : 16; + output_voltage : "pad"; + input_voltage : "pad"; + related_ground_pin : iovss; + related_power_pin : iovdd; + max_capacitance : 4.19976; + capacitance : 0.26512; + rise_capacitance : 0.264234; + rise_capacitance_range (0.235193, 0.284242); + fall_capacitance : 0.266006; + fall_capacitance_range (0.24364, 0.280606); + timing () { + related_pin : "c2p"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.53598, 1.69422, 1.82784, 1.95066, 2.29415, 2.62498", \ + "1.55631, 1.71433, 1.84796, 1.9707, 2.31384, 2.64487", \ + "1.56975, 1.72786, 1.86137, 1.98429, 2.32791, 2.65841", \ + "1.59416, 1.75227, 1.88551, 2.00851, 2.35207, 2.68258", \ + "1.62254, 1.78057, 1.91427, 2.03685, 2.38071, 2.71112", \ + "1.65929, 1.81742, 1.95099, 2.0738, 2.41719, 2.74804", \ + "1.6982, 1.85531, 1.99045, 2.11332, 2.45655, 2.7868" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.520952, 0.737812, 0.94722, 1.15712, 1.7986, 2.45491", \ + "0.520953, 0.737933, 0.947313, 1.15735, 1.79861, 2.45494", \ + "0.520954, 0.737934, 0.947314, 1.15736, 1.79896, 2.45495", \ + "0.520955, 0.737935, 0.947315, 1.15756, 1.79897, 2.45496", \ + "0.520956, 0.737936, 0.947366, 1.15757, 1.79898, 2.45497", \ + "0.520957, 0.737937, 0.947367, 1.15758, 1.79899, 2.45498", \ + "0.520958, 0.737938, 0.947368, 1.15759, 1.79974, 2.45499" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.36944, 1.49438, 1.60631, 1.71275, 2.02084, 2.33066", \ + "1.39002, 1.51496, 1.6268, 1.73327, 2.04105, 2.35019", \ + "1.40725, 1.53143, 1.64362, 1.74983, 2.05788, 2.36753", \ + "1.44326, 1.56738, 1.67972, 1.78554, 2.09369, 2.40251", \ + "1.50247, 1.62739, 1.73908, 1.84548, 2.1525, 2.46088", \ + "1.59149, 1.71604, 1.82802, 1.93417, 2.24164, 2.55039", \ + "1.72579, 1.85123, 1.9635, 2.0698, 2.3766, 2.6854" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.585678, 0.746891, 0.919723, 1.10073, 1.66787, 2.26247", \ + "0.588333, 0.749072, 0.921468, 1.10237, 1.669, 2.26265", \ + "0.590621, 0.752225, 0.922793, 1.10238, 1.67053, 2.26394", \ + "0.595017, 0.756013, 0.926088, 1.10429, 1.67231, 2.26537", \ + "0.595204, 0.75606, 0.927348, 1.10761, 1.67281, 2.26569", \ + "0.595205, 0.756061, 0.927349, 1.10762, 1.67282, 2.2657", \ + "0.595206, 0.756062, 0.92735, 1.10763, 1.67283, 2.26571" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : negative_unate; + timing_type : three_state_disable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.1263, 1.12631, 1.12632, 1.12633, 1.12634, 1.12635", \ + "1.1438, 1.14381, 1.14382, 1.14383, 1.14384, 1.14385", \ + "1.1641, 1.16411, 1.16412, 1.16413, 1.16414, 1.16415", \ + "1.19689, 1.1969, 1.19691, 1.19692, 1.19693, 1.19694", \ + "1.2356, 1.23561, 1.23562, 1.23563, 1.23564, 1.23565", \ + "1.28754, 1.28755, 1.28756, 1.28757, 1.28758, 1.28759", \ + "1.37848, 1.37849, 1.3785, 1.37851, 1.37852, 1.37853" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.1263, 1.12631, 1.12632, 1.12633, 1.12634, 1.12635", \ + "1.1438, 1.14381, 1.14382, 1.14383, 1.14384, 1.14385", \ + "1.1641, 1.16411, 1.16412, 1.16413, 1.16414, 1.16415", \ + "1.19689, 1.1969, 1.19691, 1.19692, 1.19693, 1.19694", \ + "1.2356, 1.23561, 1.23562, 1.23563, 1.23564, 1.23565", \ + "1.28754, 1.28755, 1.28756, 1.28757, 1.28758, 1.28759", \ + "1.37848, 1.37849, 1.3785, 1.37851, 1.37852, 1.37853" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.33973, 1.33974, 1.33975, 1.33976, 1.33977, 1.33978", \ + "1.36717, 1.36718, 1.36719, 1.3672, 1.36721, 1.36722", \ + "1.38242, 1.38243, 1.38244, 1.38245, 1.38246, 1.38247", \ + "1.42574, 1.42575, 1.42576, 1.42577, 1.42578, 1.42579", \ + "1.47719, 1.4772, 1.47721, 1.47722, 1.47723, 1.47724", \ + "1.5554, 1.55541, 1.55542, 1.55543, 1.55544, 1.55545", \ + "1.673, 1.67301, 1.67302, 1.67303, 1.67304, 1.67305" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.33973, 1.33974, 1.33975, 1.33976, 1.33977, 1.33978", \ + "1.36717, 1.36718, 1.36719, 1.3672, 1.36721, 1.36722", \ + "1.38242, 1.38243, 1.38244, 1.38245, 1.38246, 1.38247", \ + "1.42574, 1.42575, 1.42576, 1.42577, 1.42578, 1.42579", \ + "1.47719, 1.4772, 1.47721, 1.47722, 1.47723, 1.47724", \ + "1.5554, 1.55541, 1.55542, 1.55543, 1.55544, 1.55545", \ + "1.673, 1.67301, 1.67302, 1.67303, 1.67304, 1.67305" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : positive_unate; + timing_type : three_state_enable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.53119, 1.69672, 1.83711, 1.96566, 2.32765, 2.67684", \ + "1.54919, 1.715, 1.8549, 1.98356, 2.34484, 2.69427", \ + "1.5649, 1.73042, 1.87071, 1.99952, 2.36152, 2.71071", \ + "1.58914, 1.75517, 1.89449, 2.02427, 2.38542, 2.7349", \ + "1.61772, 1.78346, 1.92314, 2.05212, 2.41416, 2.76349", \ + "1.65511, 1.82035, 1.96016, 2.08915, 2.45056, 2.80126", \ + "1.69442, 1.8593, 1.99965, 2.12739, 2.487, 2.83587" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.516443, 0.726109, 0.933178, 1.14125, 1.78181, 2.43931", \ + "0.516444, 0.72611, 0.933179, 1.14126, 1.78182, 2.43932", \ + "0.516445, 0.726111, 0.93318, 1.14127, 1.78199, 2.43933", \ + "0.516712, 0.726112, 0.933181, 1.14162, 1.782, 2.43934", \ + "0.516713, 0.726237, 0.933182, 1.14163, 1.78201, 2.43935", \ + "0.516714, 0.726238, 0.933183, 1.14164, 1.78202, 2.43936", \ + "0.516715, 0.726239, 0.933184, 1.14241, 1.78287, 2.43937" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.21273, 1.36046, 1.48966, 1.61413, 1.96701, 2.31389", \ + "1.23266, 1.37979, 1.51035, 1.63225, 1.98545, 2.33277", \ + "1.2439, 1.3916, 1.52083, 1.64526, 1.99815, 2.34504", \ + "1.26353, 1.4095, 1.54149, 1.66304, 2.01647, 2.36357", \ + "1.28909, 1.43514, 1.56506, 1.68879, 2.04218, 2.38945", \ + "1.31163, 1.45891, 1.58923, 1.71302, 2.06588, 2.41253", \ + "1.34185, 1.48912, 1.61869, 1.74153, 2.0951, 2.44213" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.407429, 0.605561, 0.800167, 0.997209, 1.59903, 2.21509", \ + "0.40743, 0.605562, 0.801592, 0.997882, 1.60057, 2.2151", \ + "0.407483, 0.605563, 0.801593, 0.997883, 1.60058, 2.21511", \ + "0.407484, 0.605564, 0.801764, 0.9979, 1.60059, 2.21807", \ + "0.407485, 0.605565, 0.801765, 0.997908, 1.6006, 2.21808", \ + "0.407703, 0.605566, 0.801766, 0.997909, 1.60175, 2.21809", \ + "0.407804, 0.608588, 0.801767, 0.99791, 1.60176, 2.2181" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "6.38413, 6.34024, 6.31524, 6.29112, 6.19968, 6.12599", \ + "6.40005, 6.34899, 6.3224, 6.29871, 6.18522, 6.12394", \ + "6.39349, 6.34174, 6.31825, 6.2927, 6.21779, 6.12506", \ + "6.39561, 6.34705, 6.31811, 6.30303, 6.21717, 6.0427", \ + "6.39473, 6.3469, 6.32042, 6.29191, 6.17051, 6.1016", \ + "6.38933, 6.34417, 6.3158, 6.29508, 6.19268, 6.04247", \ + "6.35961, 6.25577, 6.30033, 6.27403, 6.14741, 5.99105" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "13.2515, 11.7458, 10.7599, 10.0314, 8.69098, 7.91138", \ + "13.3836, 11.8585, 10.859, 10.1219, 8.76071, 7.97794", \ + "13.4771, 11.9572, 10.9508, 10.2028, 8.82977, 8.02784", \ + "13.6951, 12.1498, 11.1019, 10.3605, 8.95889, 8.13186", \ + "13.7827, 12.2122, 11.1736, 10.4084, 8.98637, 8.16587", \ + "13.7033, 12.1544, 11.1068, 10.3765, 8.93535, 8.13028", \ + "13.4061, 11.9021, 10.8967, 10.1679, 8.78005, 7.99736" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.46845, 2.89002, 4.32584, 5.73547, 9.85946, 11.637", \ + "1.46224, 2.88329, 4.32353, 5.73675, 9.85073, 11.6085", \ + "1.46283, 2.88041, 4.30703, 5.71516, 9.92397, 11.5697", \ + "1.46333, 2.88571, 4.3071, 5.74498, 9.91741, 11.5218", \ + "1.4692, 2.89044, 4.31396, 5.75182, 9.85149, 11.4145", \ + "1.48499, 2.90425, 4.33047, 5.76796, 9.87909, 11.0096", \ + "1.52307, 2.94359, 4.36892, 5.80086, 9.89742, 10.3404" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.171359, 0.17117, 0.170937, 0.170808, 0.17051, 0.169441", \ + "0.168918, 0.16871, 0.16857, 0.168441, 0.168071, 0.167282", \ + "0.168957, 0.168627, 0.16847, 0.168286, 0.167922, 0.167089", \ + "0.170403, 0.170085, 0.169941, 0.169803, 0.169359, 0.168477", \ + "0.176334, 0.176186, 0.175997, 0.175868, 0.175367, 0.174361", \ + "0.192174, 0.191971, 0.191775, 0.191609, 0.191175, 0.189832", \ + "0.229971, 0.229802, 0.22967, 0.229558, 0.229265, 0.226999" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "6.18034, 6.43801, 6.73009, 7.0223, 7.90433, 8.81717", \ + "6.17661, 6.45678, 6.73589, 7.02629, 7.87753, 8.76315", \ + "6.17993, 6.4479, 6.74672, 7.03748, 7.93379, 8.83618", \ + "6.1728, 6.44594, 6.72771, 7.02428, 7.89413, 8.82476", \ + "6.17312, 6.44639, 6.73342, 7.02844, 7.92069, 8.82856", \ + "6.18256, 6.44351, 6.72656, 7.01791, 7.89334, 8.80856", \ + "6.16537, 6.41134, 6.72009, 6.93502, 7.69006, 8.54261" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.51155, 2.51136, 2.50867, 2.50817, 2.50588, 2.50644", \ + "2.51212, 2.51226, 2.50892, 2.50683, 2.50635, 2.50653", \ + "2.51179, 2.51156, 2.50882, 2.50837, 2.50611, 2.50663", \ + "2.51205, 2.51082, 2.50945, 2.507, 2.50619, 2.50624", \ + "2.51283, 2.5114, 2.50996, 2.50782, 2.50666, 2.50747", \ + "2.51097, 2.51054, 2.5085, 2.50698, 2.50257, 2.50335", \ + "2.51373, 2.51799, 2.50898, 2.5135, 2.51223, 2.51016" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.43686, 2.8547, 4.29073, 5.70415, 9.84077, 11.5707", \ + "1.4358, 2.85542, 4.28935, 5.71073, 9.82834, 11.6281", \ + "1.43625, 2.85521, 4.26586, 5.6968, 9.89429, 11.4733", \ + "1.43903, 2.86044, 4.27113, 5.71923, 9.81898, 11.5773", \ + "1.44688, 2.86785, 4.27833, 5.73048, 9.87657, 11.2354", \ + "1.46615, 2.88306, 4.29807, 5.73479, 9.85223, 11.0822", \ + "1.5092, 2.93113, 4.34268, 5.77753, 9.77013, 10.2137" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.0903609, 0.0900959, 0.0897079, 0.0896193, 0.0893516, 0.0878243", \ + "0.0890482, 0.0886438, 0.0884537, 0.0881447, 0.0876328, 0.0867564", \ + "0.0890474, 0.0887761, 0.0883906, 0.0882984, 0.0879602, 0.0864165", \ + "0.0908631, 0.0902903, 0.0902293, 0.0898751, 0.089699, 0.088152", \ + "0.0949325, 0.0943745, 0.0942757, 0.0939755, 0.0936965, 0.0918938", \ + "0.105279, 0.104845, 0.104656, 0.104527, 0.103922, 0.102204", \ + "0.127903, 0.127653, 0.127291, 0.127068, 0.12625, 0.12397" \ + ); + } + } + } + pin (p2c) { + direction : "output"; + output_voltage : "core"; + function : "pad"; + related_ground_pin : vss; + related_power_pin : vdd; + max_capacitance : 0.815063; + timing () { + related_pin : "pad"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0832234, 0.101979, 0.136167, 0.168976, 0.201703, 0.234298", \ + "0.0832244, 0.10198, 0.136168, 0.168977, 0.201704, 0.234299", \ + "0.0832254, 0.101981, 0.136169, 0.168978, 0.201705, 0.2343", \ + "0.0832264, 0.101982, 0.13617, 0.168979, 0.201706, 0.234301", \ + "0.0832274, 0.101983, 0.136171, 0.16898, 0.201707, 0.234302", \ + "0.0832284, 0.101984, 0.136172, 0.168981, 0.201708, 0.234303", \ + "0.0832294, 0.101985, 0.136173, 0.168982, 0.201709, 0.234304" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0627683, 0.0961025, 0.163776, 0.232509, 0.301504, 0.370795", \ + "0.0660042, 0.100337, 0.169172, 0.237493, 0.306389, 0.375506", \ + "0.0711561, 0.104127, 0.17168, 0.241066, 0.311485, 0.380309", \ + "0.0739606, 0.106413, 0.173371, 0.241845, 0.311486, 0.381813", \ + "0.0863838, 0.116984, 0.180785, 0.247828, 0.315913, 0.384022", \ + "0.109928, 0.139172, 0.198709, 0.261285, 0.326685, 0.392638", \ + "0.129264, 0.157385, 0.214108, 0.274663, 0.337776, 0.403432" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.450015, 0.477231, 0.518976, 0.552739, 0.583553, 0.613645", \ + "0.493043, 0.520231, 0.562072, 0.596407, 0.627509, 0.656766", \ + "0.602505, 0.629789, 0.671374, 0.705836, 0.736897, 0.765911", \ + "0.675588, 0.702944, 0.744069, 0.77868, 0.80978, 0.838244", \ + "0.992811, 1.02028, 1.06143, 1.09592, 1.12679, 1.1564", \ + "1.63347, 1.66081, 1.70154, 1.73561, 1.76636, 1.79628", \ + "2.23932, 2.26689, 2.30804, 2.34165, 2.37277, 2.40259" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.13188, 0.157123, 0.202209, 0.246226, 0.289783, 0.335361", \ + "0.131989, 0.157435, 0.20221, 0.246227, 0.290412, 0.335658", \ + "0.13199, 0.157436, 0.202211, 0.246228, 0.290413, 0.335659", \ + "0.131991, 0.157437, 0.202212, 0.246229, 0.290414, 0.33566", \ + "0.131992, 0.157438, 0.202213, 0.24623, 0.290415, 0.335661", \ + "0.132164, 0.157797, 0.202997, 0.246793, 0.290419, 0.335929", \ + "0.141029, 0.165464, 0.208577, 0.252394, 0.296283, 0.33968" \ + ); + } + } + internal_power () { + related_pin : "pad"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "-0.623209, -0.623466, -0.623455, -0.623459, -0.623477, -0.623484", \ + "-0.624669, -0.624261, -0.62416, -0.626321, -0.625263, -0.622276", \ + "-0.625198, -0.625205, -0.623042, -0.625232, -0.62525, -0.625268", \ + "-0.624561, -0.624566, -0.624574, -0.624586, -0.624599, -0.624619", \ + "-0.624377, -0.624377, -0.624377, -0.624382, -0.624384, -0.624393", \ + "-0.622462, -0.622522, -0.623877, -0.623876, -0.623882, -0.623879", \ + "-0.621883, -0.62207, -0.621641, -0.622408, -0.622064, -0.621975" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.623475, 0.623466, 0.623455, 0.623459, 0.623477, 0.623484", \ + "0.626259, 0.626279, 0.626299, 0.626321, 0.626334, 0.626355", \ + "0.625198, 0.625205, 0.62522, 0.625232, 0.62525, 0.625268", \ + "0.624561, 0.624566, 0.624574, 0.624586, 0.624599, 0.624619", \ + "0.624377, 0.624377, 0.624377, 0.624382, 0.624384, 0.624393", \ + "0.622462, 0.622522, 0.623877, 0.623876, 0.623882, 0.623879", \ + "0.621883, 0.62207, 0.621641, 0.622408, 0.622064, 0.621975" \ + ); + } + } + internal_power () { + related_pin : "pad"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.000102036, 0.000399312, 0.000823919, 0.00066817, 0.000424319, -6.88709e-05", \ + "-0.000217464, -6.99603e-05, -2.17206e-05, -8.15902e-05, -0.000370921, -0.000841431", \ + "-0.00135485, -0.000913188, -0.000526921, -0.00100031, -0.000800521, -0.00127619", \ + "-0.00107173, -0.00115386, -0.000822601, -0.00084983, -0.00100692, -0.00180791", \ + "-0.00189862, -0.0020515, -0.00235032, -0.00286235, -0.00264444, -0.00253835", \ + "-0.0016363, -0.00190835, -0.00220824, -0.00346199, -0.00382956, -0.00384611", \ + "-0.00110262, -0.00186593, -0.00267264, -0.00302759, -0.003759, -0.00306287" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.053361, 0.0529871, 0.0530924, 0.0533105, 0.053525, 0.0536901", \ + "0.0522049, 0.0518503, 0.0519123, 0.0521242, 0.0523106, 0.0524486", \ + "0.0512592, 0.0509087, 0.0509397, 0.0511251, 0.0512854, 0.0514025", \ + "0.0514743, 0.051108, 0.051165, 0.0513697, 0.0515467, 0.0516798", \ + "0.0508552, 0.0504875, 0.0504894, 0.0506499, 0.0507978, 0.0509183", \ + "0.0512603, 0.0507386, 0.050544, 0.0505237, 0.0505555, 0.0505922", \ + "0.0519695, 0.0512763, 0.0508388, 0.0507359, 0.0506916, 0.0506562" \ + ); + } + } + } + pin (c2p) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.016; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0275776; + rise_capacitance : 0.0276797; + rise_capacitance_range (0.022992, 0.031206); + fall_capacitance : 0.0274755; + fall_capacitance_range (0.0234413, 0.0309533); + internal_power () { + when : "(!c2p_en * pad * p2c)"; + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-4.01346e-07, -1.93071e-06, -2.2869e-08, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "4.01346e-07, 1.93071e-06, 2.2869e-08, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + when : "(!c2p_en * pad * p2c)"; + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0164272, -0.0172187, -0.017344, -0.0174193, -0.0173032, -0.0176487, -0.0176347" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0224792, 0.0222596, 0.0221874, 0.0221378, 0.0219568, 0.0217808, 0.0221616" \ + ); + } + } + internal_power () { + when : "(!c2p_en * !pad * !p2c)"; + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-3.67695e-07, -1.92219e-06, -2.66555e-08, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "3.67695e-07, 1.92219e-06, 2.66555e-08, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + when : "(!c2p_en * !pad * !p2c)"; + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0164257, -0.0172183, -0.0173434, -0.0174188, -0.017303, -0.0176487, -0.0176347" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0224782, 0.0222585, 0.0221869, 0.0221376, 0.0219569, 0.0217807, 0.0221616" \ + ); + } + } + internal_power () { + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-3.67695e-07, -1.92219e-06, -2.66555e-08, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "3.67695e-07, 1.92219e-06, 2.66555e-08, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0164257, -0.0172183, -0.0173434, -0.0174188, -0.017303, -0.0176487, -0.0176347" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0224782, 0.0222585, 0.0221869, 0.0221376, 0.0219569, 0.0217807, 0.0221616" \ + ); + } + } + } + pin (c2p_en) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.011; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0252767; + rise_capacitance : 0.0260894; + rise_capacitance_range (0.0221884, 0.0307568); + fall_capacitance : 0.024464; + fall_capacitance_range (0.0209977, 0.0277632); + internal_power () { + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "1.71151, 1.71181, 1.71179, 1.70911, 1.71038, 1.70961, 1.72074" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.280068, 0.280157, 0.279536, 0.279581, 0.278461, 0.279732, 0.277147" \ + ); + } + } + internal_power () { + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0336521, 0.0323305, 0.0322863, 0.0340077, 0.0379637, 0.0487118, 0.0706333" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0813462, 0.0803897, 0.0808792, 0.0822559, 0.0863897, 0.0964075, 0.118522" \ + ); + } + } + } + } + cell (sg13g2_IOPadInOut30mA) { + pad_cell : true; + area : 14400; + cell_footprint : "inout"; + pad_drivers : 1; + bond_pads : 1; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 825.168; + when : "!c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 1734.69; + when : "!c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 825.168; + when : "!c2p_en&c2p&!pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 1888.82; + when : "!c2p_en&c2p&!pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 0; + when : "!c2p_en&!c2p&pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 1637.48; + when : "!c2p_en&!c2p&pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 0; + when : "!c2p_en&c2p&pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 1792.06; + when : "!c2p_en&c2p&pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 0; + when : "c2p_en&c2p&pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 1965.39; + when : "c2p_en&c2p&pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 0; + when : "c2p_en&c2p&pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 1965.43; + when : "c2p_en&c2p&pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 823.195; + when : "c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 2042.02; + when : "c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 823.195; + when : "c2p_en&!c2p&!pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 2042.01; + when : "c2p_en&!c2p&!pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 412.091; + related_pg_pin : iovdd; + } + leakage_power () { + value : 1883.49; + related_pg_pin : vdd; + } + pin (pad) { + direction : "inout"; + is_pad : true; + function : "c2p"; + three_state : "c2p_en'"; + drive_current : 30; + output_voltage : "pad"; + input_voltage : "pad"; + related_ground_pin : iovss; + related_power_pin : iovdd; + max_capacitance : 4.83452; + capacitance : 0.354236; + rise_capacitance : 0.35065; + rise_capacitance_range (0.319563, 0.372349); + fall_capacitance : 0.357822; + fall_capacitance_range (0.333658, 0.374009); + timing () { + related_pin : "c2p"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.74247, 1.88405, 1.99905, 2.09897, 2.35077, 2.56696", \ + "1.76315, 1.90427, 2.01922, 2.11902, 2.37074, 2.58687", \ + "1.77717, 1.91813, 2.03305, 2.13292, 2.38451, 2.60078", \ + "1.80197, 1.94253, 2.05731, 2.1572, 2.40881, 2.62506", \ + "1.82989, 1.97076, 2.08566, 2.18545, 2.43698, 2.65308", \ + "1.86615, 2.00722, 2.12204, 2.22179, 2.47355, 2.68956", \ + "1.90564, 2.04681, 2.16132, 2.26088, 2.51255, 2.72911" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.50136, 0.666867, 0.80584, 0.93275, 1.2844, 1.62302", \ + "0.501361, 0.666868, 0.805841, 0.932751, 1.28441, 1.62303", \ + "0.501362, 0.666869, 0.805842, 0.932752, 1.28442, 1.62304", \ + "0.501363, 0.66687, 0.805843, 0.932753, 1.28443, 1.62305", \ + "0.501364, 0.666871, 0.805844, 0.932754, 1.28444, 1.62306", \ + "0.501365, 0.666872, 0.805845, 0.932755, 1.28445, 1.62307", \ + "0.501366, 0.667613, 0.807207, 0.93421, 1.28602, 1.6241" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.64263, 1.72668, 1.80527, 1.87797, 2.07538, 2.25589", \ + "1.66357, 1.7482, 1.82596, 1.89893, 2.09595, 2.27672", \ + "1.68045, 1.76555, 1.84239, 1.91544, 2.11398, 2.2938", \ + "1.71685, 1.80178, 1.87989, 1.95158, 2.14993, 2.33108", \ + "1.7768, 1.86052, 1.93903, 2.01167, 2.20899, 2.38944", \ + "1.86551, 1.94956, 2.02775, 2.10042, 2.29763, 2.47826", \ + "2.00055, 2.08368, 2.16097, 2.23398, 2.43123, 2.6107" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.900114, 0.961777, 1.0413, 1.12096, 1.37214, 1.63418", \ + "0.903842, 0.966338, 1.04173, 1.12277, 1.37454, 1.63644", \ + "0.90707, 0.968259, 1.04816, 1.12838, 1.37669, 1.63685", \ + "0.913493, 0.972618, 1.04946, 1.13348, 1.38104, 1.6421", \ + "0.915727, 0.975443, 1.0541, 1.13349, 1.38289, 1.64369", \ + "0.915728, 0.975444, 1.05411, 1.1335, 1.3829, 1.6437", \ + "0.915729, 0.975445, 1.05412, 1.13351, 1.38291, 1.64371" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : negative_unate; + timing_type : three_state_disable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.31961, 1.31962, 1.31963, 1.31964, 1.31965, 1.31966", \ + "1.34443, 1.34444, 1.34445, 1.34446, 1.34447, 1.34448", \ + "1.35714, 1.35715, 1.35716, 1.35717, 1.35718, 1.35719", \ + "1.3871, 1.38711, 1.38712, 1.38713, 1.38714, 1.38715", \ + "1.42829, 1.4283, 1.42831, 1.42832, 1.42833, 1.42834", \ + "1.47838, 1.47839, 1.4784, 1.47841, 1.47842, 1.47843", \ + "1.57068, 1.57069, 1.5707, 1.57071, 1.57072, 1.57073" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.31961, 1.31962, 1.31963, 1.31964, 1.31965, 1.31966", \ + "1.34443, 1.34444, 1.34445, 1.34446, 1.34447, 1.34448", \ + "1.35714, 1.35715, 1.35716, 1.35717, 1.35718, 1.35719", \ + "1.3871, 1.38711, 1.38712, 1.38713, 1.38714, 1.38715", \ + "1.42829, 1.4283, 1.42831, 1.42832, 1.42833, 1.42834", \ + "1.47838, 1.47839, 1.4784, 1.47841, 1.47842, 1.47843", \ + "1.57068, 1.57069, 1.5707, 1.57071, 1.57072, 1.57073" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.91034, 1.91035, 1.91036, 1.91037, 1.91038, 1.91039", \ + "1.92283, 1.94769, 1.9477, 1.94771, 1.94772, 1.94773", \ + "1.94944, 1.94945, 1.94946, 1.94947, 1.94948, 1.94949", \ + "1.98275, 1.98276, 1.98277, 1.98278, 1.98279, 1.9828", \ + "2.06409, 2.0641, 2.06411, 2.06412, 2.06413, 2.06414", \ + "2.12042, 2.12043, 2.12044, 2.12045, 2.12046, 2.12047", \ + "2.24669, 2.2467, 2.24671, 2.24672, 2.24673, 2.24674" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.91034, 1.91035, 1.91036, 1.91037, 1.91038, 1.91039", \ + "1.92283, 1.94769, 1.9477, 1.94771, 1.94772, 1.94773", \ + "1.94944, 1.94945, 1.94946, 1.94947, 1.94948, 1.94949", \ + "1.98275, 1.98276, 1.98277, 1.98278, 1.98279, 1.9828", \ + "2.06409, 2.0641, 2.06411, 2.06412, 2.06413, 2.06414", \ + "2.12042, 2.12043, 2.12044, 2.12045, 2.12046, 2.12047", \ + "2.24669, 2.2467, 2.24671, 2.24672, 2.24673, 2.24674" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : positive_unate; + timing_type : three_state_enable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.71898, 1.87498, 1.99753, 2.10251, 2.36573, 2.59173", \ + "1.73653, 1.89246, 2.01505, 2.11997, 2.38321, 2.60926", \ + "1.7521, 1.908, 2.0306, 2.13556, 2.39882, 2.62479", \ + "1.7768, 1.93351, 2.05615, 2.1611, 2.42436, 2.64955", \ + "1.80567, 1.96174, 2.08409, 2.18927, 2.45248, 2.67836", \ + "1.84104, 1.99695, 2.11953, 2.22446, 2.4877, 2.71373", \ + "1.88303, 2.03926, 2.16184, 2.26686, 2.53006, 2.75581" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.522218, 0.668852, 0.796911, 0.916443, 1.25745, 1.5909", \ + "0.522219, 0.668956, 0.796912, 0.916444, 1.25746, 1.59093", \ + "0.52224, 0.669269, 0.797226, 0.916636, 1.25751, 1.59094", \ + "0.522241, 0.66927, 0.797227, 0.916637, 1.25752, 1.59127", \ + "0.522242, 0.669271, 0.797228, 0.916638, 1.25753, 1.59135", \ + "0.522243, 0.669272, 0.797229, 0.916639, 1.25754, 1.59136", \ + "0.522244, 0.669273, 0.79723, 0.91664, 1.25755, 1.59137" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.26481, 1.38293, 1.47999, 1.56687, 1.7958, 2.00004", \ + "1.28459, 1.40198, 1.49977, 1.58822, 1.81363, 2.02084", \ + "1.29596, 1.41409, 1.51114, 1.59803, 1.82695, 2.03119", \ + "1.31505, 1.43316, 1.53014, 1.61729, 1.84608, 2.05031", \ + "1.34073, 1.45811, 1.5559, 1.64435, 1.86977, 2.07698", \ + "1.36522, 1.48354, 1.58044, 1.66698, 1.89527, 2.10234", \ + "1.39335, 1.51151, 1.60774, 1.69291, 1.91967, 2.12639" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.376716, 0.498564, 0.614548, 0.720805, 1.03893, 1.35168", \ + "0.376717, 0.500353, 0.614549, 0.725255, 1.03894, 1.35169", \ + "0.376718, 0.500354, 0.61455, 0.725256, 1.03895, 1.3517", \ + "0.376719, 0.500899, 0.614557, 0.725257, 1.03896, 1.35171", \ + "0.37672, 0.5009, 0.614558, 0.725258, 1.03897, 1.35172", \ + "0.376721, 0.500901, 0.616251, 0.725259, 1.03898, 1.35173", \ + "0.376813, 0.500902, 0.616252, 0.72526, 1.03899, 1.35174" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "10.2191, 10.022, 9.91789, 9.86525, 9.73223, 9.59795", \ + "10.2481, 10.0318, 9.93343, 9.85641, 9.74823, 9.60442", \ + "10.2584, 10.0334, 9.92637, 9.85799, 9.74384, 9.61439", \ + "10.2703, 10.0458, 9.93231, 9.85601, 9.74269, 9.60267", \ + "10.2643, 10.048, 9.94481, 9.86502, 9.7546, 9.58871", \ + "10.2541, 10.0471, 9.9366, 9.85944, 9.74464, 9.60392", \ + "10.2166, 9.99626, 9.86208, 9.7615, 9.63346, 9.50502" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "53.4525, 50.1523, 47.4614, 45.1149, 39.7795, 35.925", \ + "53.75, 50.4693, 47.721, 45.3655, 40.0029, 36.1364", \ + "54.0061, 50.6669, 47.9472, 45.6247, 40.1683, 36.3654", \ + "54.5143, 51.1764, 48.3991, 46.0794, 40.5822, 36.6464", \ + "54.6925, 51.3461, 48.6116, 46.2104, 40.7704, 36.8297", \ + "54.4992, 51.1782, 48.4336, 46.0403, 40.6152, 36.6765", \ + "53.7527, 50.468, 47.7288, 45.4308, 40.0583, 36.2197" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.46519, 2.8934, 4.31436, 5.72939, 8.9664, 7.44515", \ + "1.46332, 2.88881, 4.31178, 5.71978, 9.02448, 7.34225", \ + "1.46349, 2.89029, 4.31064, 5.71881, 8.89807, 7.26031", \ + "1.46372, 2.89137, 4.31269, 5.72088, 8.81996, 7.11144", \ + "1.46988, 2.89643, 4.32186, 5.72547, 8.82864, 6.77959", \ + "1.48525, 2.91425, 4.32727, 5.73671, 8.49371, 6.11839", \ + "1.52271, 2.94846, 4.36913, 5.77839, 7.89901, 4.82154" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.170956, 0.171046, 0.17093, 0.170827, 0.170653, 0.167757", \ + "0.1686, 0.16863, 0.168554, 0.168509, 0.168277, 0.165323", \ + "0.168482, 0.168657, 0.168559, 0.168449, 0.168228, 0.165141", \ + "0.169943, 0.169988, 0.169876, 0.169888, 0.169635, 0.166522", \ + "0.176016, 0.176073, 0.175987, 0.175923, 0.175778, 0.172229", \ + "0.191824, 0.191839, 0.191691, 0.191735, 0.191446, 0.187503", \ + "0.229787, 0.22971, 0.229667, 0.229594, 0.229126, 0.224015" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "9.31797, 9.59766, 9.89927, 10.1728, 11.074, 11.8915", \ + "9.32029, 9.60496, 9.8903, 10.1703, 11.0711, 11.8908", \ + "9.31195, 9.59647, 9.88878, 10.1633, 11.0639, 11.8586", \ + "9.32197, 9.59423, 9.89677, 10.1701, 11.0571, 11.9081", \ + "9.32143, 9.61205, 9.88304, 10.1805, 11.0742, 11.9101", \ + "9.31357, 9.60247, 9.88436, 10.1677, 11.0689, 11.8994", \ + "9.3121, 9.61244, 9.90845, 10.2008, 11.1041, 11.912" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "4.1659, 4.16205, 4.16759, 4.1664, 4.16808, 4.16297", \ + "4.16427, 4.16499, 4.16566, 4.17404, 4.16671, 4.16539", \ + "4.16609, 4.16224, 4.16777, 4.16653, 4.16826, 4.16314", \ + "4.16553, 4.16591, 4.16767, 4.16626, 4.1687, 4.1634", \ + "4.165, 4.16571, 4.16514, 4.17476, 4.1674, 4.16608", \ + "4.16316, 4.16377, 4.16798, 4.16762, 4.16649, 4.16502", \ + "4.16538, 4.16342, 4.16466, 4.16498, 4.16902, 4.16693" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.438, 2.86754, 4.28396, 5.70474, 8.85841, 7.2288", \ + "1.43577, 2.86528, 4.2869, 5.70214, 8.82291, 7.12855", \ + "1.43641, 2.86614, 4.28774, 5.69994, 8.78242, 7.066", \ + "1.44023, 2.86975, 4.29318, 5.70582, 8.7045, 6.88027", \ + "1.44808, 2.87625, 4.29374, 5.71238, 8.78653, 6.53289", \ + "1.46726, 2.89651, 4.31872, 5.72676, 8.52432, 5.89083", \ + "1.51015, 2.93855, 4.35605, 5.77654, 7.82678, 4.5374" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.0904749, 0.0901327, 0.0899149, 0.0897952, 0.0892426, 0.0841027", \ + "0.0890099, 0.0886602, 0.0885143, 0.0885779, 0.0877079, 0.0828025", \ + "0.0891571, 0.0888167, 0.0885981, 0.0884842, 0.0878495, 0.0826034", \ + "0.0908224, 0.090504, 0.0902548, 0.0902424, 0.0891551, 0.0841841", \ + "0.0948723, 0.0945198, 0.0943932, 0.0944341, 0.0932643, 0.0880546", \ + "0.105321, 0.105088, 0.104873, 0.104674, 0.103414, 0.0977553", \ + "0.127821, 0.127406, 0.12711, 0.126926, 0.124577, 0.118448" \ + ); + } + } + } + pin (p2c) { + direction : "output"; + output_voltage : "core"; + function : "pad"; + related_ground_pin : vss; + related_power_pin : vdd; + max_capacitance : 0.80964; + timing () { + related_pin : "pad"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0831252, 0.101898, 0.135971, 0.16892, 0.201666, 0.234313", \ + "0.0831262, 0.101899, 0.135972, 0.168921, 0.201667, 0.234314", \ + "0.0831272, 0.1019, 0.135973, 0.168922, 0.201668, 0.234315", \ + "0.0831282, 0.101901, 0.135974, 0.168923, 0.201669, 0.234316", \ + "0.0831292, 0.101902, 0.135975, 0.168924, 0.20167, 0.234317", \ + "0.0831302, 0.101903, 0.135976, 0.168925, 0.201671, 0.234318", \ + "0.0831312, 0.101904, 0.135977, 0.168926, 0.201672, 0.234319" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0628501, 0.0962365, 0.164003, 0.232625, 0.301671, 0.370896", \ + "0.0659295, 0.1004, 0.169221, 0.23767, 0.306429, 0.375615", \ + "0.0713318, 0.104286, 0.171863, 0.24114, 0.311354, 0.380293", \ + "0.0739647, 0.106812, 0.173464, 0.241945, 0.311415, 0.381919", \ + "0.0865974, 0.118069, 0.181349, 0.247835, 0.315333, 0.384085", \ + "0.109274, 0.13853, 0.197909, 0.260902, 0.326318, 0.393573", \ + "0.129195, 0.157324, 0.214537, 0.274529, 0.337808, 0.403488" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.451151, 0.478531, 0.52013, 0.554488, 0.585747, 0.614846", \ + "0.493191, 0.520477, 0.561975, 0.59661, 0.627594, 0.656965", \ + "0.608505, 0.635915, 0.677114, 0.711792, 0.742129, 0.772145", \ + "0.663981, 0.691351, 0.733149, 0.767485, 0.797731, 0.827776", \ + "0.98738, 1.0146, 1.05612, 1.09006, 1.12159, 1.15086", \ + "1.64404, 1.67126, 1.71264, 1.747, 1.77722, 1.80713", \ + "2.24003, 2.26694, 2.30856, 2.3424, 2.37348, 2.40238" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.131639, 0.157207, 0.202684, 0.246258, 0.2907, 0.335294", \ + "0.131801, 0.157654, 0.202685, 0.246259, 0.290701, 0.335625", \ + "0.131802, 0.157655, 0.202686, 0.24626, 0.290702, 0.335626", \ + "0.131803, 0.157656, 0.202687, 0.246261, 0.290703, 0.335627", \ + "0.131804, 0.157657, 0.202688, 0.246262, 0.290704, 0.335628", \ + "0.132017, 0.157658, 0.202689, 0.246865, 0.290705, 0.335731", \ + "0.140847, 0.165854, 0.208823, 0.251346, 0.295462, 0.33958" \ + ); + } + } + internal_power () { + related_pin : "pad"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "-1.1854, -1.19072, -1.18993, -1.18988, -1.1908, -1.18784", \ + "-1.18948, -1.18477, -1.18746, -1.18951, -1.18952, -1.18406", \ + "-1.18891, -1.18892, -1.18896, -1.18894, -1.18903, -1.185", \ + "-1.18866, -1.18867, -1.18364, -1.18875, -1.18879, -1.18882", \ + "-1.18715, -1.1871, -1.18714, -1.18709, -1.18713, -1.18721", \ + "-1.18636, -1.18673, -1.18714, -1.18757, -1.1879, -1.18816", \ + "-1.1827, -1.18386, -1.18273, -1.18334, -1.18282, -1.18313" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "1.19073, 1.19072, 1.19077, 1.19081, 1.1908, 1.1909", \ + "1.18948, 1.18948, 1.18951, 1.18951, 1.18952, 1.18961", \ + "1.18891, 1.18892, 1.18896, 1.18894, 1.18903, 1.18908", \ + "1.18866, 1.18867, 1.1887, 1.18875, 1.18879, 1.18882", \ + "1.18715, 1.1871, 1.18714, 1.18709, 1.18713, 1.18721", \ + "1.18636, 1.18673, 1.18714, 1.18757, 1.1879, 1.18816", \ + "1.1827, 1.18386, 1.18273, 1.18334, 1.18282, 1.18313" \ + ); + } + } + internal_power () { + related_pin : "pad"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.000226908, 0.0005226, 0.000830519, 0.00078649, 0.000408479, 2.08891e-05", \ + "-4.22042e-05, 5.23077e-05, 0.000203999, 8.67698e-05, -0.000158161, -0.000632991", \ + "-0.000964764, -0.000666096, -0.000377641, -0.00089219, -0.00131856, -0.00150359", \ + "-0.00144732, -0.00152201, -0.00100824, -0.00104279, -0.00130428, -0.00154583", \ + "-0.00173515, -0.00155575, -0.00203412, -0.00218051, -0.00241596, -0.00208487", \ + "-0.00179693, -0.00186281, -0.00244968, -0.00274895, -0.0026796, -0.00302495", \ + "-0.000990792, -0.00174462, -0.00214752, -0.00304535, -0.00376956, -0.00308423" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0554316, 0.0550879, 0.0551951, 0.0554327, 0.0556461, 0.0557958", \ + "0.0542153, 0.0538966, 0.053952, 0.0541773, 0.0543601, 0.0545055", \ + "0.0534856, 0.0531027, 0.0531415, 0.0533494, 0.0535116, 0.0536523", \ + "0.0530989, 0.0527154, 0.0527717, 0.0529476, 0.0530869, 0.0532266", \ + "0.0528382, 0.0524572, 0.0524632, 0.0526046, 0.0527513, 0.0528633", \ + "0.0529779, 0.052513, 0.0523789, 0.05246, 0.052545, 0.0526376", \ + "0.0536196, 0.0531371, 0.0526889, 0.0525855, 0.0525338, 0.0525134" \ + ); + } + } + } + pin (c2p) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.016; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0275776; + rise_capacitance : 0.0276798; + rise_capacitance_range (0.0229921, 0.0312061); + fall_capacitance : 0.0274755; + fall_capacitance_range (0.0234414, 0.0309533); + internal_power () { + when : "(!c2p_en * pad * p2c)"; + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0, -1.37939e-06, 0, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0, 1.37939e-06, 0, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + when : "(!c2p_en * pad * p2c)"; + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0164272, -0.0172187, -0.017344, -0.0174193, -0.0173028, -0.0176487, -0.0176347" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0224792, 0.0222596, 0.0221874, 0.0221378, 0.0219567, 0.0217808, 0.0221616" \ + ); + } + } + internal_power () { + when : "(!c2p_en * !pad * !p2c)"; + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0, -1.34685e-06, 0, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0, 1.34685e-06, 0, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + when : "(!c2p_en * !pad * !p2c)"; + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0164257, -0.0172183, -0.0173434, -0.0174188, -0.0173026, -0.0176487, -0.0176347" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0224782, 0.0222585, 0.0221869, 0.0221376, 0.0219568, 0.0217807, 0.0221616" \ + ); + } + } + internal_power () { + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0, -1.34685e-06, 0, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0, 1.34685e-06, 0, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0164257, -0.0172183, -0.0173434, -0.0174188, -0.0173026, -0.0176487, -0.0176347" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0224782, 0.0222585, 0.0221869, 0.0221376, 0.0219568, 0.0217807, 0.0221616" \ + ); + } + } + } + pin (c2p_en) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.011; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0252782; + rise_capacitance : 0.0260925; + rise_capacitance_range (0.0221885, 0.0308132); + fall_capacitance : 0.024464; + fall_capacitance_range (0.0209978, 0.0277746); + internal_power () { + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "2.663, 2.65815, 2.66306, 2.65803, 2.66193, 2.65852, 2.66328" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.269915, 0.269769, 0.269332, 0.269387, 0.267915, 0.269439, 0.26744" \ + ); + } + } + internal_power () { + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0336515, 0.0323304, 0.0322854, 0.034006, 0.0379632, 0.0486941, 0.0706621" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0813506, 0.0803875, 0.0808783, 0.0822552, 0.0863923, 0.0963572, 0.118846" \ + ); + } + } + } + } + cell (sg13g2_IOPadInOut4mA) { + pad_cell : true; + area : 14400; + cell_footprint : "inout"; + pad_drivers : 1; + bond_pads : 1; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 189.75; + when : "!c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 1735.46; + when : "!c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 189.499; + when : "!c2p_en&c2p&!pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 1889.62; + when : "!c2p_en&c2p&!pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 0; + when : "!c2p_en&!c2p&pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 1638.6; + when : "!c2p_en&!c2p&pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 0; + when : "!c2p_en&c2p&pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 1793.18; + when : "!c2p_en&c2p&pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 0; + when : "c2p_en&c2p&pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 1966.54; + when : "c2p_en&c2p&pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 0; + when : "c2p_en&c2p&pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 1966.54; + when : "c2p_en&c2p&pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 187.53; + when : "c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 2042.79; + when : "c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 187.516; + when : "c2p_en&!c2p&!pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 2042.79; + when : "c2p_en&!c2p&!pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 94.2869; + related_pg_pin : iovdd; + } + leakage_power () { + value : 1884.44; + related_pg_pin : vdd; + } + pin (pad) { + direction : "inout"; + is_pad : true; + function : "c2p"; + three_state : "c2p_en'"; + drive_current : 4; + output_voltage : "pad"; + input_voltage : "pad"; + related_ground_pin : iovss; + related_power_pin : iovdd; + max_capacitance : 1.07593; + capacitance : 0.188577; + rise_capacitance : 0.189895; + rise_capacitance_range (0.162282, 0.208866); + fall_capacitance : 0.187258; + fall_capacitance_range (0.166164, 0.200869); + timing () { + related_pin : "c2p"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.54948, 1.98537, 2.41868, 2.85128, 4.1479, 5.44429", \ + "1.56845, 2.00432, 2.43764, 2.87024, 4.16695, 5.4629", \ + "1.58291, 2.01883, 2.45217, 2.88478, 4.18153, 5.47811", \ + "1.60745, 2.04325, 2.47656, 2.90912, 4.20581, 5.50245", \ + "1.63562, 2.07151, 2.50485, 2.9375, 4.23404, 5.53004", \ + "1.6732, 2.10917, 2.54258, 2.9752, 4.27173, 5.56774", \ + "1.71191, 2.14777, 2.58125, 3.01361, 4.31037, 5.60624" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.13236, 2.02275, 2.92166, 3.82574, 6.53448, 9.2269", \ + "1.13246, 2.02281, 2.92378, 3.82575, 6.53449, 9.23126", \ + "1.13247, 2.02282, 2.92416, 3.82576, 6.5345, 9.23127", \ + "1.13282, 2.02297, 2.9242, 3.82577, 6.53451, 9.23128", \ + "1.13283, 2.02298, 2.92421, 3.82618, 6.53456, 9.23592", \ + "1.13284, 2.02375, 2.92422, 3.82631, 6.53457, 9.23593", \ + "1.13291, 2.02408, 2.92424, 3.82632, 6.53458, 9.2428" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.43677, 1.86654, 2.29554, 2.72391, 4.01033, 5.29434", \ + "1.45624, 1.88536, 2.31404, 2.74281, 4.02874, 5.31236", \ + "1.47243, 1.90157, 2.3299, 2.75885, 4.04345, 5.32765", \ + "1.50613, 1.93476, 2.36296, 2.79226, 4.07634, 5.36061", \ + "1.56466, 1.99356, 2.42162, 2.84972, 4.13614, 5.42275", \ + "1.65511, 2.08392, 2.51213, 2.94146, 4.22563, 5.51105", \ + "1.79186, 2.221, 2.64952, 3.07855, 4.36335, 5.64667" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.03378, 1.86387, 2.69407, 3.52668, 6.03783, 8.54573", \ + "1.03379, 1.86388, 2.69535, 3.53107, 6.04636, 8.55837", \ + "1.0338, 1.86389, 2.69811, 3.53117, 6.05584, 8.55838", \ + "1.03463, 1.86674, 2.69812, 3.53118, 6.05585, 8.57099", \ + "1.03464, 1.86675, 2.69813, 3.53119, 6.05586, 8.571", \ + "1.03465, 1.86676, 2.69814, 3.53139, 6.05587, 8.57101", \ + "1.03466, 1.86677, 2.69815, 3.5314, 6.05588, 8.57102" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : negative_unate; + timing_type : three_state_disable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.932447, 0.932448, 0.932449, 0.93245, 0.932451, 0.932452", \ + "0.952078, 0.952079, 0.95208, 0.952081, 0.952082, 0.952083", \ + "0.970039, 0.97004, 0.970041, 0.970042, 0.970043, 0.970044", \ + "1.00251, 1.00252, 1.00253, 1.00254, 1.00255, 1.00256", \ + "1.04116, 1.04117, 1.04118, 1.04119, 1.0412, 1.04121", \ + "1.09709, 1.0971, 1.09711, 1.09712, 1.09713, 1.09714", \ + "1.18612, 1.18613, 1.18614, 1.18615, 1.18616, 1.18617" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.932447, 0.932448, 0.932449, 0.93245, 0.932451, 0.932452", \ + "0.952078, 0.952079, 0.95208, 0.952081, 0.952082, 0.952083", \ + "0.970039, 0.97004, 0.970041, 0.970042, 0.970043, 0.970044", \ + "1.00251, 1.00252, 1.00253, 1.00254, 1.00255, 1.00256", \ + "1.04116, 1.04117, 1.04118, 1.04119, 1.0412, 1.04121", \ + "1.09709, 1.0971, 1.09711, 1.09712, 1.09713, 1.09714", \ + "1.18612, 1.18613, 1.18614, 1.18615, 1.18616, 1.18617" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.858056, 0.858057, 0.858058, 0.858059, 0.85806, 0.858061", \ + "0.881395, 0.881396, 0.881397, 0.881398, 0.881399, 0.8814", \ + "0.901056, 0.901057, 0.901058, 0.901059, 0.90106, 0.901061", \ + "0.939794, 0.939795, 0.939796, 0.939797, 0.939798, 0.939799", \ + "0.996358, 0.996359, 0.99636, 0.996361, 0.996362, 0.996363", \ + "1.07591, 1.07592, 1.07593, 1.07594, 1.07595, 1.07596", \ + "1.19972, 1.19973, 1.19974, 1.19975, 1.19976, 1.19977" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.858056, 0.858057, 0.858058, 0.858059, 0.85806, 0.858061", \ + "0.881395, 0.881396, 0.881397, 0.881398, 0.881399, 0.8814", \ + "0.901056, 0.901057, 0.901058, 0.901059, 0.90106, 0.901061", \ + "0.939794, 0.939795, 0.939796, 0.939797, 0.939798, 0.939799", \ + "0.996358, 0.996359, 0.99636, 0.996361, 0.996362, 0.996363", \ + "1.07591, 1.07592, 1.07593, 1.07594, 1.07595, 1.07596", \ + "1.19972, 1.19973, 1.19974, 1.19975, 1.19976, 1.19977" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : positive_unate; + timing_type : three_state_enable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.55588, 2.00785, 2.45782, 2.90728, 4.25471, 5.60147", \ + "1.57265, 2.0253, 2.47517, 2.92447, 4.27197, 5.61856", \ + "1.5896, 2.0418, 2.49176, 2.94115, 4.28838, 5.63498", \ + "1.61458, 2.06649, 2.51653, 2.96596, 4.31321, 5.65932", \ + "1.64225, 2.0949, 2.54492, 2.99435, 4.34173, 5.68828", \ + "1.68132, 2.1334, 2.58346, 3.03284, 4.38001, 5.72676", \ + "1.72041, 2.17304, 2.62324, 3.07255, 4.41998, 5.76737" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.13135, 2.02284, 2.92319, 3.82618, 6.52359, 9.22329", \ + "1.13136, 2.02285, 2.9232, 3.82619, 6.5236, 9.24351", \ + "1.13137, 2.02286, 2.92375, 3.8262, 6.5312, 9.24352", \ + "1.13138, 2.02287, 2.92376, 3.82622, 6.53121, 9.24353", \ + "1.13139, 2.02288, 2.92377, 3.82623, 6.53122, 9.24354", \ + "1.1314, 2.02289, 2.92378, 3.82624, 6.53383, 9.24355", \ + "1.13141, 2.0229, 2.92379, 3.82625, 6.53384, 9.24356" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.4591, 1.92759, 2.39454, 2.86203, 4.26208, 5.66135", \ + "1.47847, 1.94697, 2.41392, 2.8814, 4.28127, 5.68077", \ + "1.49015, 1.95864, 2.4256, 2.89308, 4.29296, 5.69244", \ + "1.51042, 1.97892, 2.44588, 2.91305, 4.3138, 5.71262", \ + "1.53457, 2.00337, 2.47045, 2.93749, 4.3376, 5.73681", \ + "1.55717, 2.0257, 2.49287, 2.96008, 4.35927, 5.75795", \ + "1.58795, 2.05603, 2.52371, 2.9894, 4.38845, 5.78643" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.02981, 1.85961, 2.70138, 3.53181, 6.03488, 8.53589", \ + "1.02982, 1.85962, 2.70139, 3.53182, 6.03538, 8.5429", \ + "1.02983, 1.85963, 2.7014, 3.53183, 6.03539, 8.54291", \ + "1.02984, 1.85963, 2.70141, 3.53184, 6.0354, 8.54292", \ + "1.02985, 1.85964, 2.70142, 3.53185, 6.04357, 8.54293", \ + "1.02986, 1.85965, 2.70143, 3.53193, 6.04358, 8.54294", \ + "1.02987, 1.85966, 2.70144, 3.53194, 6.04359, 8.54295" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "3.5241, 3.49142, 3.45117, 3.42405, 3.3202, 3.10302", \ + "3.51861, 3.48507, 3.45936, 3.41956, 3.25096, 3.11329", \ + "3.52299, 3.49004, 3.46444, 3.42524, 3.26591, 3.07669", \ + "3.5276, 3.49284, 3.46497, 3.40243, 3.23763, 3.08072", \ + "3.52489, 3.48896, 3.4618, 3.43481, 3.32063, 3.13371", \ + "3.52074, 3.49115, 3.44378, 3.43939, 3.27799, 3.09236", \ + "3.5153, 3.48637, 3.45781, 3.39715, 3.25918, 3.1974" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.91385, 1.90815, 1.90679, 1.90527, 1.9043, 1.90343", \ + "1.91906, 1.91285, 1.91046, 1.90836, 1.9061, 1.90466", \ + "1.92089, 1.91331, 1.90919, 1.90747, 1.90512, 1.90369", \ + "1.92955, 1.91878, 1.91241, 1.90929, 1.90575, 1.90384", \ + "1.93385, 1.92079, 1.9145, 1.91067, 1.90628, 1.90412", \ + "1.93979, 1.92811, 1.92226, 1.91893, 1.915, 1.9127", \ + "1.91902, 1.91302, 1.90968, 1.90761, 1.90546, 1.90322" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.47173, 2.90051, 4.33261, 5.75467, 10.0432, 14.3311", \ + "1.46943, 2.89793, 4.33143, 5.75614, 10.0406, 14.324", \ + "1.46945, 2.8981, 4.32864, 5.75617, 10.0522, 14.3284", \ + "1.47441, 2.90142, 4.32961, 5.75484, 10.0461, 14.3333", \ + "1.48025, 2.90758, 4.33566, 5.768, 10.0483, 14.3385", \ + "1.49159, 2.92375, 4.35021, 5.78604, 10.0736, 14.3589", \ + "1.5308, 2.96166, 4.38939, 5.8175, 10.099, 14.3848" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.170859, 0.170227, 0.170049, 0.170168, 0.16994, 0.170061", \ + "0.168451, 0.167946, 0.167899, 0.167817, 0.167481, 0.167671", \ + "0.168427, 0.167971, 0.167721, 0.167974, 0.167601, 0.167434", \ + "0.169863, 0.169244, 0.169435, 0.169354, 0.169056, 0.16909", \ + "0.175942, 0.175323, 0.175243, 0.175049, 0.174938, 0.17505", \ + "0.191737, 0.191111, 0.191135, 0.19133, 0.190919, 0.190713", \ + "0.229763, 0.229166, 0.229246, 0.228846, 0.228724, 0.228668" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "3.40015, 3.57786, 3.76622, 3.96488, 4.42804, 4.94944", \ + "3.38595, 3.57608, 3.74534, 3.95284, 4.43804, 5.07352", \ + "3.39609, 3.57994, 3.7715, 3.96281, 4.48958, 5.06263", \ + "3.39978, 3.57138, 3.76903, 3.96492, 4.43032, 4.93716", \ + "3.38353, 3.57547, 3.75507, 3.96096, 4.4257, 4.98986", \ + "3.39868, 3.58416, 3.77385, 3.96201, 4.52447, 5.07213", \ + "3.39084, 3.57882, 3.7619, 3.96561, 4.42801, 4.94244" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.11032, 1.10891, 1.10941, 1.10877, 1.10825, 1.10777", \ + "1.11023, 1.10881, 1.10932, 1.10868, 1.10817, 1.10782", \ + "1.11043, 1.10902, 1.10952, 1.10889, 1.10837, 1.10803", \ + "1.11211, 1.11071, 1.11095, 1.11163, 1.11, 1.10954", \ + "1.11083, 1.11053, 1.11001, 1.10928, 1.10937, 1.10827", \ + "1.1073, 1.10713, 1.10665, 1.10601, 1.10554, 1.10522", \ + "1.11133, 1.11185, 1.11113, 1.11068, 1.11056, 1.11007" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.44709, 2.87557, 4.30725, 5.73655, 10.0166, 14.3067", \ + "1.44191, 2.87342, 4.30134, 5.73046, 10.0171, 14.3048", \ + "1.4431, 2.87562, 4.30316, 5.7346, 10.0207, 14.2941", \ + "1.44879, 2.87576, 4.30518, 5.73834, 10.0187, 14.3077", \ + "1.45359, 2.88546, 4.31352, 5.74172, 10.0238, 14.3175", \ + "1.47245, 2.90256, 4.3319, 5.7601, 10.0515, 14.3266", \ + "1.5173, 2.94778, 4.37418, 5.80407, 10.0889, 14.3728" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.0899352, 0.0894049, 0.0894117, 0.0894182, 0.0891092, 0.089132", \ + "0.088566, 0.0880602, 0.0880633, 0.0880697, 0.087641, 0.0878705", \ + "0.0885873, 0.0880817, 0.0880804, 0.088091, 0.0876619, 0.0878925", \ + "0.0903723, 0.0897807, 0.0901016, 0.0895518, 0.0895047, 0.0895717", \ + "0.0944217, 0.0939999, 0.0937443, 0.0939093, 0.093256, 0.093583", \ + "0.104779, 0.104642, 0.104098, 0.103968, 0.103929, 0.103859", \ + "0.12785, 0.127404, 0.127237, 0.127232, 0.126554, 0.126934" \ + ); + } + } + } + pin (p2c) { + direction : "output"; + output_voltage : "core"; + function : "pad"; + related_ground_pin : vss; + related_power_pin : vdd; + max_capacitance : 0.812356; + timing () { + related_pin : "pad"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.083135, 0.101906, 0.135997, 0.168912, 0.201587, 0.234197", \ + "0.083136, 0.101907, 0.135998, 0.168913, 0.201588, 0.234198", \ + "0.083137, 0.101908, 0.135999, 0.168914, 0.201589, 0.234199", \ + "0.083138, 0.101909, 0.136, 0.168915, 0.20159, 0.2342", \ + "0.083139, 0.10191, 0.136001, 0.168916, 0.201591, 0.234201", \ + "0.08314, 0.101911, 0.136002, 0.168917, 0.201592, 0.234202", \ + "0.083141, 0.101912, 0.136003, 0.168918, 0.201593, 0.234203" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0627305, 0.0960899, 0.163886, 0.232432, 0.301491, 0.37082", \ + "0.0659578, 0.10023, 0.169128, 0.237451, 0.306242, 0.37542", \ + "0.0711406, 0.104106, 0.17164, 0.241016, 0.311128, 0.380191", \ + "0.0739344, 0.10623, 0.173213, 0.241798, 0.31143, 0.381805", \ + "0.08652, 0.116985, 0.181532, 0.248097, 0.315514, 0.383951", \ + "0.109916, 0.138904, 0.198704, 0.261372, 0.326372, 0.392627", \ + "0.129196, 0.157307, 0.214063, 0.27461, 0.337758, 0.402749" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.451091, 0.478481, 0.519999, 0.553829, 0.585546, 0.614002", \ + "0.493021, 0.520487, 0.561779, 0.596509, 0.627595, 0.655985", \ + "0.608404, 0.635804, 0.677352, 0.711677, 0.741974, 0.771585", \ + "0.663957, 0.691385, 0.733091, 0.767428, 0.797677, 0.827724", \ + "0.987065, 1.0145, 1.05601, 1.0904, 1.12075, 1.15076", \ + "1.644, 1.67123, 1.71261, 1.7469, 1.7782, 1.80742", \ + "2.23853, 2.26609, 2.30759, 2.341, 2.37123, 2.40075" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.131757, 0.157198, 0.202496, 0.245657, 0.290688, 0.334719", \ + "0.131758, 0.157623, 0.202497, 0.246025, 0.290689, 0.33472", \ + "0.131759, 0.157624, 0.202498, 0.246026, 0.29069, 0.335202", \ + "0.13176, 0.157625, 0.202499, 0.246027, 0.290691, 0.335203", \ + "0.131761, 0.157626, 0.2025, 0.246028, 0.290692, 0.335204", \ + "0.132016, 0.157637, 0.202501, 0.246744, 0.290827, 0.335205", \ + "0.141725, 0.16589, 0.208878, 0.252128, 0.294924, 0.339689" \ + ); + } + } + internal_power () { + related_pin : "pad"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "-0.155842, -0.156461, -0.156447, -0.156443, -0.156438, -0.156225", \ + "-0.156086, -0.15608, -0.156144, -0.156366, -0.156364, -0.155807", \ + "-0.15629, -0.156305, -0.156301, -0.156298, -0.156296, -0.156292", \ + "-0.156274, -0.156272, -0.156269, -0.156266, -0.156264, -0.156262", \ + "-0.155922, -0.156053, -0.156046, -0.156043, -0.156043, -0.156039", \ + "-0.155881, -0.155926, -0.155985, -0.156032, -0.156063, -0.155645", \ + "-0.155412, -0.15542, -0.155328, -0.155517, -0.155388, -0.155341" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.156466, 0.156461, 0.156447, 0.156443, 0.156438, 0.156438", \ + "0.156377, 0.156371, 0.156369, 0.156366, 0.156364, 0.156363", \ + "0.156307, 0.156305, 0.156301, 0.156298, 0.156296, 0.156292", \ + "0.156274, 0.156272, 0.156269, 0.156266, 0.156264, 0.156262", \ + "0.156056, 0.156053, 0.156046, 0.156043, 0.156043, 0.156039", \ + "0.155881, 0.155926, 0.155985, 0.156032, 0.156063, 0.155645", \ + "0.155412, 0.15542, 0.155328, 0.155517, 0.155388, 0.155341" \ + ); + } + } + internal_power () { + related_pin : "pad"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.000115128, 0.000424092, 0.000837599, 0.00076093, 0.000386519, -0.000151191", \ + "-0.000192528, -7.27083e-05, -2.76006e-05, -4.41502e-05, -0.000370201, -0.000717591", \ + "-0.0012164, -0.000917664, -0.000550441, -0.00094859, -0.0010086, -0.00118379", \ + "-0.001079, -0.00119947, -0.00103356, -0.00086087, -0.000969361, -0.00172955", \ + "-0.00167749, -0.00219592, -0.00192228, -0.00288839, -0.00282336, -0.00247247", \ + "-0.00164306, -0.0020824, -0.00196296, -0.00323495, -0.00274716, -0.00387539", \ + "-0.00111991, -0.00151602, -0.00246636, -0.00276731, -0.00351156, -0.00369719" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0554261, 0.0550733, 0.055173, 0.0554033, 0.0556271, 0.0557816", \ + "0.0541929, 0.0538863, 0.053949, 0.0541744, 0.0543622, 0.0544998", \ + "0.053481, 0.0530974, 0.0531486, 0.0533435, 0.0535063, 0.0536181", \ + "0.0530997, 0.0527263, 0.0527684, 0.0529443, 0.0530835, 0.0532237", \ + "0.0528259, 0.0524559, 0.0524646, 0.052611, 0.0527384, 0.0528613", \ + "0.0529766, 0.0525122, 0.0523788, 0.0524531, 0.0525373, 0.0524902", \ + "0.0538962, 0.0531365, 0.0526504, 0.0525274, 0.0524226, 0.0524242" \ + ); + } + } + } + pin (c2p) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.016; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0275776; + rise_capacitance : 0.0276797; + rise_capacitance_range (0.0229918, 0.031206); + fall_capacitance : 0.0274755; + fall_capacitance_range (0.023441, 0.0309533); + internal_power () { + when : "(!c2p_en * pad * p2c)"; + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-2.4092e-06, -2.86858e-06, -4.09611e-07, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "2.4092e-06, 2.86858e-06, 4.09611e-07, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + when : "(!c2p_en * pad * p2c)"; + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0164274, -0.0172188, -0.017344, -0.0174193, -0.0173012, -0.0176487, -0.0176347" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0224793, 0.0222596, 0.0221874, 0.0221378, 0.0219571, 0.0217808, 0.0221616" \ + ); + } + } + internal_power () { + when : "(!c2p_en * !pad * !p2c)"; + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-2.41063e-06, -2.87211e-06, -4.14762e-07, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "2.41063e-06, 2.87211e-06, 4.14762e-07, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + when : "(!c2p_en * !pad * !p2c)"; + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0164258, -0.0172183, -0.0173434, -0.0174189, -0.0173034, -0.0176487, -0.0176347" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0224783, 0.0222585, 0.0221869, 0.0221375, 0.0219572, 0.0217806, 0.0221616" \ + ); + } + } + internal_power () { + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-2.41063e-06, -2.87211e-06, -4.14762e-07, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "2.41063e-06, 2.87211e-06, 4.14762e-07, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0164258, -0.0172183, -0.0173434, -0.0174189, -0.0173034, -0.0176487, -0.0176347" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0224783, 0.0222585, 0.0221869, 0.0221375, 0.0219572, 0.0217806, 0.0221616" \ + ); + } + } + } + pin (c2p_en) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.011; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0252808; + rise_capacitance : 0.0260999; + rise_capacitance_range (0.0221883, 0.0308705); + fall_capacitance : 0.0244616; + fall_capacitance_range (0.0209976, 0.0278104); + internal_power () { + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.909065, 0.908883, 0.909248, 0.909041, 0.909423, 0.907505, 0.908591" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.305067, 0.304736, 0.304846, 0.303703, 0.303348, 0.303951, 0.30294" \ + ); + } + } + internal_power () { + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0336586, 0.0323363, 0.032293, 0.0340124, 0.0379721, 0.0486711, 0.0707421" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0813504, 0.0803938, 0.0808797, 0.0822601, 0.0863942, 0.0962996, 0.118723" \ + ); + } + } + } + } + cell (sg13g2_IOPadOut16mA) { + pad_cell : true; + area : 14400; + cell_footprint : "inout"; + pad_drivers : 1; + bond_pads : 1; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 438.841; + when : "!c2p&!pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 413.931; + when : "!c2p&!pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 201.682; + when : "c2p&pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 607.193; + when : "c2p&pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 320.261; + related_pg_pin : iovdd; + } + leakage_power () { + value : 510.562; + related_pg_pin : vdd; + } + pin (pad) { + direction : "output"; + is_pad : true; + function : "c2p"; + drive_current : 16; + output_voltage : "pad"; + related_ground_pin : iovss; + related_power_pin : iovdd; + max_capacitance : 4.21305; + timing () { + related_pin : "c2p"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 3, 7, 9, 12, 15"); + values ( \ + "1.48219, 1.77613, 2.24432, 2.46584, 2.79385, 3.11961", \ + "1.511, 1.80572, 2.2727, 2.49458, 2.82273, 3.14837", \ + "1.54096, 1.83495, 2.30311, 2.52448, 2.85267, 3.17826", \ + "1.61473, 1.90906, 2.37648, 2.59688, 2.92579, 3.25162", \ + "1.7655, 2.05921, 2.52665, 2.74854, 3.07666, 3.40194", \ + "2.06865, 2.36182, 2.83046, 3.051, 3.37953, 3.70515", \ + "2.66358, 2.95742, 3.42554, 3.6472, 3.97417, 4.30039" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 3, 7, 9, 12, 15"); + values ( \ + "0.510924, 0.942338, 1.79281, 2.22632, 2.8848, 3.54848", \ + "0.510928, 0.94337, 1.79282, 2.22655, 2.88481, 3.5495", \ + "0.510978, 0.943371, 1.79283, 2.22656, 2.88482, 3.54951", \ + "0.510979, 0.943372, 1.79284, 2.22657, 2.88483, 3.54952", \ + "0.51098, 0.943373, 1.79285, 2.22678, 2.88484, 3.54953", \ + "0.510981, 0.943374, 1.79286, 2.22679, 2.88513, 3.54954", \ + "0.510982, 0.943375, 1.79287, 2.22685, 2.88514, 3.54955" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 3, 7, 9, 12, 15"); + values ( \ + "1.29542, 1.53108, 1.94428, 2.14631, 2.45665, 2.76747", \ + "1.3045, 1.54025, 1.95144, 2.15735, 2.4659, 2.77768", \ + "1.31407, 1.54993, 1.96231, 2.1667, 2.47544, 2.78714", \ + "1.33224, 1.5689, 1.97923, 2.1846, 2.49352, 2.80529", \ + "1.35863, 1.59515, 2.00656, 2.21089, 2.51868, 2.83149", \ + "1.38952, 1.62602, 2.03718, 2.242, 2.54927, 2.86236", \ + "1.4554, 1.69147, 2.10455, 2.30661, 2.61659, 2.92889" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 3, 7, 9, 12, 15"); + values ( \ + "0.61148, 0.933952, 1.67559, 2.06517, 2.66226, 3.26846", \ + "0.611481, 0.934998, 1.6756, 2.06615, 2.66231, 3.26847", \ + "0.611482, 0.935161, 1.67656, 2.06616, 2.66232, 3.26848", \ + "0.611483, 0.936469, 1.67657, 2.06617, 2.66233, 3.26849", \ + "0.611601, 0.936577, 1.67658, 2.06618, 2.66321, 3.26908", \ + "0.612518, 0.937195, 1.67659, 2.06651, 2.66383, 3.26909", \ + "0.612931, 0.937196, 1.67678, 2.06706, 2.66384, 3.26909" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 3, 7, 9, 12, 15"); + values ( \ + "6.17145, 6.09388, 6.04247, 6.01244, 5.95762, 5.8439", \ + "6.17286, 6.12965, 6.03468, 6.01663, 5.95752, 5.85397", \ + "6.16892, 6.09744, 6.02088, 6.00725, 5.95983, 5.8607", \ + "6.18489, 6.1088, 6.05883, 5.95191, 5.94459, 5.84899", \ + "6.19645, 6.12655, 6.07094, 6.06095, 5.95254, 5.8806", \ + "6.243, 6.18394, 6.13434, 6.08929, 6.00273, 5.93215", \ + "6.34891, 6.28594, 6.24113, 6.21608, 6.12018, 5.99069" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 3, 7, 9, 12, 15"); + values ( \ + "14.9186, 12.0703, 9.67442, 9.01185, 8.2847, 7.79305", \ + "14.895, 12.0542, 9.65441, 8.98499, 8.26318, 7.76672", \ + "14.8989, 12.0571, 9.67291, 8.97539, 8.26055, 7.76469", \ + "14.9105, 12.074, 9.65839, 8.97641, 8.26204, 7.76461", \ + "14.9222, 12.0793, 9.67908, 8.98285, 8.29739, 7.76934", \ + "14.9505, 12.0955, 9.65775, 8.99492, 8.29423, 7.76934", \ + "14.9716, 12.1069, 9.6866, 9.03338, 8.2935, 7.79409" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 3, 7, 9, 12, 15"); + values ( \ + "-0.0100958, -0.0100958, -0.0100962, -0.0100962, -0.0100963, -0.0100958", \ + "-0.0113445, -0.0113446, -0.0113449, -0.0113454, -0.0113453, -0.0113448", \ + "-0.0105443, -0.0105443, -0.0105446, -0.0105448, -0.0105447, -0.0105443", \ + "-0.00723627, -0.00725203, -0.00730723, -0.00730731, -0.00722371, -0.00730694", \ + "0.000793376, 0.000793131, 0.000793205, 0.000792619, 0.000792941, 0.000793345", \ + "0.0184921, 0.0188254, 0.0184543, 0.018825, 0.018825, 0.0188253", \ + "0.0567026, 0.0567027, 0.0567023, 0.0567023, 0.0567024, 0.0567027" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 3, 7, 9, 12, 15"); + values ( \ + "0.0560928, 0.0560837, 0.0560829, 0.0560816, 0.0560806, 0.0560807", \ + "0.0564502, 0.0564416, 0.0564432, 0.0564286, 0.0564386, 0.0564339", \ + "0.0575592, 0.0575802, 0.0575486, 0.057568, 0.057548, 0.0575433", \ + "0.0612522, 0.0613101, 0.0612428, 0.0612994, 0.0612397, 0.061303", \ + "0.0700145, 0.0700059, 0.0700048, 0.0699949, 0.0699966, 0.069998", \ + "0.0879647, 0.0880457, 0.0879479, 0.0880355, 0.0880348, 0.0880383", \ + "0.125612, 0.125589, 0.1256, 0.125818, 0.125712, 0.125702" \ + ); + } + } + } + pin (c2p) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.016; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0392194; + rise_capacitance : 0.0380695; + rise_capacitance_range (0.034176, 0.0406024); + fall_capacitance : 0.0403692; + fall_capacitance_range (0.0360909, 0.0430839); + } + } + cell (sg13g2_IOPadOut30mA) { + pad_cell : true; + area : 14400; + cell_footprint : "inout"; + pad_drivers : 1; + bond_pads : 1; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 851.687; + when : "!c2p&!pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 413.269; + when : "!c2p&!pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 406.782; + when : "c2p&pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 607.122; + when : "c2p&pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 629.234; + related_pg_pin : iovdd; + } + leakage_power () { + value : 510.196; + related_pg_pin : vdd; + } + pin (pad) { + direction : "output"; + is_pad : true; + function : "c2p"; + drive_current : 30; + output_voltage : "pad"; + related_ground_pin : iovss; + related_power_pin : iovdd; + max_capacitance : 4.53171; + timing () { + related_pin : "c2p"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("2, 6, 14, 18, 24, 30"); + values ( \ + "1.83605, 2.22672, 2.78965, 3.03862, 3.39854, 3.75349", \ + "1.86498, 2.25586, 2.81856, 3.0651, 3.42883, 3.78182", \ + "1.89882, 2.28895, 2.85175, 3.09917, 3.46038, 3.8156", \ + "1.96876, 2.35866, 2.91951, 3.16989, 3.53223, 3.88651", \ + "2.12212, 2.5127, 3.07023, 3.32318, 3.67957, 4.04002", \ + "2.42212, 2.81291, 3.37664, 3.6244, 3.98591, 4.33945", \ + "3.01845, 3.40888, 3.97331, 4.22104, 4.58414, 4.93804" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("2, 6, 14, 18, 24, 30"); + values ( \ + "0.657208, 1.16926, 2.07708, 2.53014, 3.2195, 3.92074", \ + "0.657209, 1.16929, 2.07709, 2.53015, 3.22164, 3.92075", \ + "0.65721, 1.16976, 2.07725, 2.53038, 3.22165, 3.92076", \ + "0.657211, 1.16977, 2.07726, 2.53039, 3.22166, 3.92077", \ + "0.657212, 1.16978, 2.07727, 2.5304, 3.22167, 3.92078", \ + "0.657213, 1.16979, 2.07728, 2.53041, 3.22168, 3.92079", \ + "0.657214, 1.1698, 2.07729, 2.53051, 3.22169, 3.9208" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("2, 6, 14, 18, 24, 30"); + values ( \ + "1.66, 1.94387, 2.41265, 2.63031, 2.94885, 3.26808", \ + "1.66857, 1.95425, 2.42111, 2.6388, 2.9577, 3.278", \ + "1.67853, 1.96274, 2.4313, 2.64827, 2.96755, 3.28692", \ + "1.69715, 1.98339, 2.44956, 2.66629, 2.98577, 3.3105", \ + "1.72286, 2.00769, 2.47602, 2.69139, 3.0131, 3.3308", \ + "1.75459, 2.0389, 2.50686, 2.72488, 3.04395, 3.36347", \ + "1.82046, 2.1047, 2.57192, 2.78841, 3.10899, 3.42772" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("2, 6, 14, 18, 24, 30"); + values ( \ + "0.998532, 1.31503, 2.02311, 2.41117, 3.01959, 3.64267", \ + "0.998533, 1.31504, 2.02312, 2.41425, 3.01987, 3.64268", \ + "0.998534, 1.31505, 2.02596, 2.41426, 3.01988, 3.64269", \ + "0.999427, 1.3152, 2.02597, 2.41427, 3.02025, 3.64361", \ + "0.999491, 1.31636, 2.02598, 2.41428, 3.02109, 3.64362", \ + "1.00099, 1.31637, 2.02599, 2.41484, 3.0211, 3.64363", \ + "1.00132, 1.31759, 2.02631, 2.41485, 3.02318, 3.64364" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("2, 6, 14, 18, 24, 30"); + values ( \ + "9.96903, 9.83582, 9.74394, 9.41734, 9.16215, 9.15288", \ + "9.93248, 9.84241, 9.75328, 9.27293, 9.3264, 9.04002", \ + "9.98888, 9.84727, 9.75021, 9.41658, 9.16285, 9.12021", \ + "9.95636, 9.64712, 9.43982, 9.44028, 9.30079, 9.1773", \ + "10.0305, 9.89327, 9.77609, 9.41262, 9.19423, 9.2301", \ + "10.0341, 9.93135, 9.8475, 9.44856, 9.40203, 9.12912", \ + "10.1424, 9.91069, 9.93498, 9.61901, 9.52789, 9.33438" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("2, 6, 14, 18, 24, 30"); + values ( \ + "53.6991, 44.4388, 34.7535, 31.8284, 28.6587, 26.2815", \ + "53.7534, 44.3996, 34.6981, 31.8265, 28.6599, 26.2063", \ + "53.7249, 44.4377, 34.7866, 31.8259, 28.6473, 26.2734", \ + "53.7493, 44.3653, 34.7407, 31.8567, 28.6973, 26.2405", \ + "53.7863, 44.4405, 34.777, 31.8609, 28.6438, 26.2938", \ + "53.8412, 44.5235, 34.826, 31.884, 28.6388, 26.2959", \ + "53.9317, 44.6099, 34.9382, 31.9539, 28.8009, 26.3489" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("2, 6, 14, 18, 24, 30"); + values ( \ + "-0.0100998, -0.0100998, -0.0100996, -0.0100998, -0.0101, -0.0100998", \ + "-0.0113461, -0.0113464, -0.0113461, -0.0113463, -0.0113465, -0.0113465", \ + "-0.0105776, -0.0105778, -0.0105777, -0.0105778, -0.010578, -0.0105779", \ + "-0.00724316, -0.00725765, -0.00722862, -0.00722885, -0.00722904, -0.00731315", \ + "0.000783257, 0.000783372, 0.000570847, 0.000783186, 0.000570004, 0.000783062", \ + "0.0188044, 0.0188043, 0.0184715, 0.0184713, 0.0184335, 0.0188042", \ + "0.0566427, 0.0566424, 0.0566426, 0.0566422, 0.0566423, 0.0566424" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("2, 6, 14, 18, 24, 30"); + values ( \ + "0.056088, 0.0560899, 0.056087, 0.0560873, 0.0560867, 0.0560863", \ + "0.0564432, 0.0564361, 0.0564342, 0.0564358, 0.0564328, 0.0564335", \ + "0.0575514, 0.0575719, 0.0575682, 0.0575684, 0.0575408, 0.0575678", \ + "0.0612386, 0.0612328, 0.0612299, 0.0612303, 0.0612965, 0.0612981", \ + "0.0695863, 0.0699865, 0.0695852, 0.0695862, 0.069586, 0.0695845", \ + "0.0879223, 0.0879385, 0.0879145, 0.0879371, 0.0879124, 0.0879138", \ + "0.125623, 0.125595, 0.125664, 0.125792, 0.125867, 0.125607" \ + ); + } + } + } + pin (c2p) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.016; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0392183; + rise_capacitance : 0.0380654; + rise_capacitance_range (0.0341714, 0.0405906); + fall_capacitance : 0.0403712; + fall_capacitance_range (0.0360774, 0.0430673); + } + } + cell (sg13g2_IOPadOut4mA) { + pad_cell : true; + area : 14400; + cell_footprint : "inout"; + pad_drivers : 1; + bond_pads : 1; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 172.828; + when : "!c2p&!pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 413.228; + when : "!c2p&!pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 118.795; + when : "c2p&pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 607.207; + when : "c2p&pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 145.811; + related_pg_pin : iovdd; + } + leakage_power () { + value : 510.217; + related_pg_pin : vdd; + } + pin (pad) { + direction : "output"; + is_pad : true; + function : "c2p"; + drive_current : 4; + output_voltage : "pad"; + related_ground_pin : iovss; + related_power_pin : iovdd; + max_capacitance : 1.11146; + timing () { + related_pin : "c2p"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.48454, 1.92055, 2.35449, 2.78678, 4.08373, 5.37987", \ + "1.51342, 1.94973, 2.38305, 2.81598, 4.11293, 5.40925", \ + "1.54356, 1.97984, 2.4137, 2.84599, 4.143, 5.4394", \ + "1.61772, 2.05383, 2.48775, 2.91962, 4.21701, 5.51289", \ + "1.76747, 2.20328, 2.63714, 3.06944, 4.36644, 5.66283", \ + "2.07059, 2.50668, 2.9414, 3.37394, 4.66987, 5.96618", \ + "2.66774, 3.10168, 3.53569, 3.97001, 5.26698, 6.5631" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.10093, 1.98802, 2.88417, 3.78209, 6.48436, 9.18199", \ + "1.10094, 1.98803, 2.88426, 3.78234, 6.48437, 9.18319", \ + "1.10095, 1.98818, 2.88427, 3.7834, 6.48438, 9.18534", \ + "1.10107, 1.98819, 2.88428, 3.78353, 6.48439, 9.18535", \ + "1.10108, 1.9882, 2.88436, 3.78354, 6.4844, 9.18536", \ + "1.10114, 1.98821, 2.88437, 3.78355, 6.48441, 9.18537", \ + "1.10115, 1.98822, 2.88438, 3.78356, 6.48442, 9.18538" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.33709, 1.76438, 2.19139, 2.61878, 3.90079, 5.18261", \ + "1.34619, 1.77327, 2.20051, 2.62779, 3.9099, 5.19172", \ + "1.35519, 1.7826, 2.20966, 2.63662, 3.91794, 5.20078", \ + "1.37323, 1.80077, 2.22781, 2.65501, 3.93699, 5.21889", \ + "1.39895, 1.82604, 2.25424, 2.68086, 3.96189, 5.24515", \ + "1.42956, 1.85683, 2.28365, 2.71066, 3.99219, 5.27493", \ + "1.49486, 1.922, 2.34922, 2.77615, 4.05748, 5.34014" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.0044, 1.82514, 2.65446, 3.48561, 5.98221, 8.47946", \ + "1.00441, 1.82535, 2.65447, 3.48562, 5.98222, 8.47948", \ + "1.00442, 1.82536, 2.65448, 3.48591, 5.98459, 8.47949", \ + "1.00443, 1.82537, 2.65449, 3.48592, 5.9846, 8.4795", \ + "1.00444, 1.82538, 2.6545, 3.48593, 5.98461, 8.47951", \ + "1.00446, 1.82559, 2.65458, 3.48594, 5.98462, 8.47952", \ + "1.00501, 1.8256, 2.65459, 3.48724, 5.98463, 8.47953" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "3.16849, 3.14189, 3.10857, 3.07524, 2.99221, 2.88017", \ + "3.16719, 3.14376, 3.10959, 3.08359, 2.99848, 2.91832", \ + "3.16794, 3.14138, 3.10873, 3.08352, 2.99762, 2.90601", \ + "3.18079, 3.15258, 3.12345, 3.09834, 3.01026, 2.91621", \ + "3.20388, 3.17631, 3.14328, 3.11728, 3.0299, 2.93954", \ + "3.25705, 3.22832, 3.20153, 3.17011, 3.08718, 2.99218", \ + "3.36009, 3.33079, 3.30135, 3.277, 3.19262, 3.10085" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.07826, 2.04322, 2.02619, 2.01901, 2.00462, 1.99915", \ + "2.05778, 2.02316, 2.00593, 1.99889, 1.98434, 1.97886", \ + "2.05017, 2.01477, 1.99773, 1.99041, 1.97721, 1.9703", \ + "2.0417, 2.0068, 1.98984, 1.98251, 1.96886, 1.96259", \ + "2.04182, 2.00564, 1.99028, 1.98275, 1.969, 1.96302", \ + "2.02731, 1.9908, 1.97267, 1.96507, 1.95097, 1.94517", \ + "2.0265, 1.99041, 1.97257, 1.96368, 1.95012, 1.94503" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "-0.0101002, -0.0101008, -0.010101, -0.010101, -0.0101007, -0.0101009", \ + "-0.0113461, -0.0113466, -0.0113469, -0.0113469, -0.0113467, -0.0113466", \ + "-0.0105765, -0.010577, -0.0105775, -0.0105773, -0.0105771, -0.0105772", \ + "-0.0072566, -0.00725739, -0.00725783, -0.00724264, -0.00725747, -0.00724231", \ + "0.000593564, 0.000784031, 0.000783557, 0.000783734, 0.000784144, 0.000783906", \ + "0.0188051, 0.0188043, 0.0184713, 0.0184338, 0.0188043, 0.0188044", \ + "0.0564691, 0.0566446, 0.0566444, 0.0564684, 0.0564685, 0.0564687" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.0561003, 0.0560997, 0.0560932, 0.0561053, 0.0560917, 0.0560928", \ + "0.0564487, 0.0564501, 0.0564363, 0.0564526, 0.0564393, 0.0564406", \ + "0.0575855, 0.0575541, 0.0575397, 0.0575851, 0.0575473, 0.0575488", \ + "0.061314, 0.0613077, 0.0612924, 0.0613095, 0.0612981, 0.0612342", \ + "0.0695964, 0.0696031, 0.0699922, 0.0699997, 0.0695828, 0.0699878", \ + "0.0877965, 0.0877857, 0.0880155, 0.0880214, 0.0879411, 0.0877795", \ + "0.125641, 0.125653, 0.12547, 0.125863, 0.125569, 0.125533" \ + ); + } + } + } + pin (c2p) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.016; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0392157; + rise_capacitance : 0.0380628; + rise_capacitance_range (0.0341708, 0.0406205); + fall_capacitance : 0.0403686; + fall_capacitance_range (0.0360764, 0.0430814); + } + } + cell (sg13g2_IOPadTriOut16mA) { + pad_cell : true; + area : 14400; + cell_footprint : "tri_out"; + pad_drivers : 1; + bond_pads : 1; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 173.446; + when : "!c2p_en&!c2p"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 1427.27; + when : "!c2p_en&!c2p"; + related_pg_pin : vdd; + } + leakage_power () { + value : 173.446; + when : "!c2p_en&c2p"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 1581.83; + when : "!c2p_en&c2p"; + related_pg_pin : vdd; + } + leakage_power () { + value : 262.209; + when : "c2p_en&c2p&pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 1755.2; + when : "c2p_en&c2p&pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 479.337; + when : "c2p_en&!c2p&!pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 1734.57; + when : "c2p_en&!c2p&!pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 272.109; + related_pg_pin : iovdd; + } + leakage_power () { + value : 1624.72; + related_pg_pin : vdd; + } + pin (pad) { + direction : "output"; + is_pad : true; + function : "c2p"; + three_state : "c2p_en'"; + drive_current : 16; + output_voltage : "pad"; + related_ground_pin : iovss; + related_power_pin : iovdd; + max_capacitance : 4.21412; + capacitance : 0.24106; + rise_capacitance : 0.24299; + rise_capacitance_range (0.24299, 0.24299); + fall_capacitance : 0.239129; + fall_capacitance_range (0.239129, 0.239129); + timing () { + related_pin : "c2p"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.55181, 1.71179, 1.84668, 1.97205, 2.31546, 2.64676", \ + "1.57169, 1.73149, 1.8664, 1.99174, 2.33512, 2.66636", \ + "1.58577, 1.74561, 1.88032, 2.00577, 2.34909, 2.68033", \ + "1.61023, 1.76997, 1.90492, 2.03028, 2.37343, 2.70486", \ + "1.63893, 1.79864, 1.93333, 2.05884, 2.40216, 2.73336", \ + "1.67679, 1.83662, 1.9726, 2.09676, 2.44017, 2.77139", \ + "1.71547, 1.876, 2.0123, 2.1358, 2.47976, 2.81045" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.513216, 0.732503, 0.94266, 1.1547, 1.7929, 2.44498", \ + "0.513217, 0.732504, 0.942931, 1.15471, 1.79303, 2.44502", \ + "0.513218, 0.732505, 0.942932, 1.15472, 1.79309, 2.44507", \ + "0.513219, 0.732506, 0.942933, 1.15473, 1.7931, 2.44523", \ + "0.51322, 0.732507, 0.942934, 1.15474, 1.79311, 2.44544", \ + "0.513221, 0.732508, 0.943702, 1.15475, 1.79312, 2.44545", \ + "0.513222, 0.732509, 0.944322, 1.15557, 1.79318, 2.44596" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.38738, 1.51221, 1.62539, 1.73162, 2.04014, 2.34814", \ + "1.40796, 1.53346, 1.64602, 1.75179, 2.05919, 2.36842", \ + "1.42479, 1.55052, 1.66295, 1.76858, 2.07699, 2.38549", \ + "1.46061, 1.58641, 1.69878, 1.80448, 2.11265, 2.42032", \ + "1.52055, 1.64528, 1.7578, 1.86397, 2.17244, 2.47863", \ + "1.60873, 1.73409, 1.84655, 1.95217, 2.26022, 2.56822", \ + "1.74366, 1.86916, 1.98286, 2.08852, 2.39662, 2.7037" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.580395, 0.742624, 0.913386, 1.09123, 1.66102, 2.25247", \ + "0.582995, 0.74551, 0.91515, 1.09329, 1.6622, 2.25316", \ + "0.585582, 0.746946, 0.916605, 1.09449, 1.66378, 2.25367", \ + "0.589181, 0.750746, 0.919864, 1.09664, 1.6657, 2.255", \ + "0.591457, 0.751579, 0.921312, 1.09756, 1.66616, 2.25603", \ + "0.591458, 0.75158, 0.921313, 1.09757, 1.66617, 2.25604", \ + "0.591459, 0.751581, 0.921314, 1.09758, 1.66618, 2.25605" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : negative_unate; + timing_type : three_state_disable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.14816, 1.14817, 1.14818, 1.14819, 1.1482, 1.14821", \ + "1.16427, 1.16428, 1.16429, 1.1643, 1.16431, 1.16432", \ + "1.1836, 1.18361, 1.18362, 1.18363, 1.18364, 1.18365", \ + "1.21636, 1.21637, 1.21638, 1.21639, 1.2164, 1.21641", \ + "1.25281, 1.25282, 1.25283, 1.25284, 1.25285, 1.25286", \ + "1.3134, 1.31341, 1.31342, 1.31343, 1.31344, 1.31345", \ + "1.39983, 1.39984, 1.39985, 1.39986, 1.39987, 1.39988" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.14816, 1.14817, 1.14818, 1.14819, 1.1482, 1.14821", \ + "1.16427, 1.16428, 1.16429, 1.1643, 1.16431, 1.16432", \ + "1.1836, 1.18361, 1.18362, 1.18363, 1.18364, 1.18365", \ + "1.21636, 1.21637, 1.21638, 1.21639, 1.2164, 1.21641", \ + "1.25281, 1.25282, 1.25283, 1.25284, 1.25285, 1.25286", \ + "1.3134, 1.31341, 1.31342, 1.31343, 1.31344, 1.31345", \ + "1.39983, 1.39984, 1.39985, 1.39986, 1.39987, 1.39988" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.3591, 1.35911, 1.35912, 1.35913, 1.35914, 1.35915", \ + "1.38189, 1.3819, 1.38191, 1.38192, 1.38193, 1.38194", \ + "1.40159, 1.4016, 1.40161, 1.40162, 1.40163, 1.40164", \ + "1.44015, 1.44016, 1.44017, 1.44018, 1.44019, 1.4402", \ + "1.49683, 1.49684, 1.49685, 1.49686, 1.49687, 1.49688", \ + "1.58235, 1.58236, 1.58237, 1.58238, 1.58239, 1.5824", \ + "1.69248, 1.69249, 1.6925, 1.69251, 1.69252, 1.69253" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.3591, 1.35911, 1.35912, 1.35913, 1.35914, 1.35915", \ + "1.38189, 1.3819, 1.38191, 1.38192, 1.38193, 1.38194", \ + "1.40159, 1.4016, 1.40161, 1.40162, 1.40163, 1.40164", \ + "1.44015, 1.44016, 1.44017, 1.44018, 1.44019, 1.4402", \ + "1.49683, 1.49684, 1.49685, 1.49686, 1.49687, 1.49688", \ + "1.58235, 1.58236, 1.58237, 1.58238, 1.58239, 1.5824", \ + "1.69248, 1.69249, 1.6925, 1.69251, 1.69252, 1.69253" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : positive_unate; + timing_type : three_state_enable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.54568, 1.71543, 1.85753, 1.98809, 2.34799, 2.69903", \ + "1.56554, 1.7349, 1.87708, 2.00648, 2.36675, 2.71775", \ + "1.57967, 1.74931, 1.89155, 2.02196, 2.38184, 2.7315", \ + "1.60373, 1.77338, 1.91558, 2.04601, 2.40704, 2.75679", \ + "1.63284, 1.80252, 1.94456, 2.07525, 2.4355, 2.78645", \ + "1.67136, 1.84056, 1.98094, 2.11322, 2.47416, 2.82472", \ + "1.71023, 1.87806, 2.02059, 2.15281, 2.51367, 2.86352" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.510697, 0.721968, 0.928898, 1.13767, 1.77403, 2.42799", \ + "0.511788, 0.721969, 0.928943, 1.13768, 1.77404, 2.428", \ + "0.511789, 0.72197, 0.928944, 1.13769, 1.77405, 2.42801", \ + "0.51179, 0.721971, 0.928945, 1.1377, 1.77406, 2.42802", \ + "0.511791, 0.721972, 0.928946, 1.13771, 1.77407, 2.42812", \ + "0.511792, 0.721973, 0.928947, 1.13772, 1.7741, 2.42813", \ + "0.511793, 0.721974, 0.928948, 1.13818, 1.77411, 2.42814" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.22722, 1.37698, 1.50878, 1.63239, 1.98893, 2.33691", \ + "1.2464, 1.39516, 1.52755, 1.65087, 2.00782, 2.35489", \ + "1.25897, 1.40799, 1.53842, 1.66334, 2.01978, 2.36692", \ + "1.27727, 1.42703, 1.55904, 1.68247, 2.03768, 2.3874", \ + "1.30307, 1.45243, 1.58497, 1.70946, 2.06518, 2.41281", \ + "1.32702, 1.47578, 1.60817, 1.73144, 2.08842, 2.43552", \ + "1.35656, 1.50634, 1.63728, 1.76143, 2.11761, 2.46511" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.40051, 0.597895, 0.791989, 0.987324, 1.58716, 2.19733", \ + "0.400511, 0.597896, 0.79199, 0.987325, 1.58717, 2.19735", \ + "0.401046, 0.597897, 0.791991, 0.987643, 1.58718, 2.19814", \ + "0.401047, 0.597898, 0.791994, 0.987665, 1.58719, 2.19815", \ + "0.401048, 0.597899, 0.791995, 0.988507, 1.5872, 2.19816", \ + "0.401049, 0.5979, 0.791996, 0.988508, 1.58721, 2.1983", \ + "0.40105, 0.597901, 0.791997, 0.988509, 1.58722, 2.19831" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "6.11675, 6.06803, 6.05514, 6.12767, 6.03537, 5.97429", \ + "6.12733, 6.0756, 6.05956, 6.13589, 6.03587, 5.97148", \ + "6.13022, 6.08178, 6.05916, 6.13619, 6.0354, 5.97534", \ + "6.12552, 6.07084, 6.04784, 6.13589, 6.029, 5.96277", \ + "6.12939, 6.07636, 6.0555, 6.13368, 6.03458, 5.96614", \ + "6.12425, 6.07705, 6.11879, 6.13549, 6.04352, 5.97307", \ + "6.06802, 6.05339, 6.10553, 6.08517, 6.01095, 5.92845" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "13.399, 11.8866, 10.8863, 10.1629, 8.8045, 8.03324", \ + "13.5285, 12.001, 10.9844, 10.2571, 8.88818, 8.08931", \ + "13.6226, 12.0815, 11.0601, 10.329, 8.94407, 8.12979", \ + "13.8412, 12.2743, 11.232, 10.4809, 9.06327, 8.23116", \ + "13.9176, 12.3441, 11.2996, 10.5339, 9.10856, 8.27854", \ + "13.8383, 12.274, 11.2281, 10.4793, 9.08285, 8.23117", \ + "13.5382, 12.007, 11.0102, 10.271, 8.90622, 8.09065" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.049282, 0.0492811, 0.0492807, 0.0492825, 0.0492772, 0.049279", \ + "0.0469305, 0.046929, 0.0469302, 0.0469301, 0.0469275, 0.0469254", \ + "0.0468747, 0.0468755, 0.0468753, 0.0468753, 0.0468723, 0.0468696", \ + "0.0478909, 0.04789, 0.0478887, 0.0478904, 0.0478872, 0.0478861", \ + "0.0536495, 0.0536487, 0.05365, 0.0536487, 0.0536462, 0.0536439", \ + "0.0696638, 0.0696626, 0.0696648, 0.0696636, 0.0696588, 0.0696573", \ + "0.107218, 0.107236, 0.107249, 0.107213, 0.107209, 0.107206" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.1194, 0.119411, 0.119401, 0.119394, 0.119392, 0.119395", \ + "0.117026, 0.117033, 0.117016, 0.117031, 0.117022, 0.117024", \ + "0.116954, 0.116937, 0.116934, 0.116948, 0.116946, 0.116928", \ + "0.118232, 0.118223, 0.118222, 0.118235, 0.118233, 0.118215", \ + "0.12439, 0.124398, 0.124404, 0.12439, 0.124385, 0.124388", \ + "0.140228, 0.140237, 0.140218, 0.140234, 0.140229, 0.140211", \ + "0.178014, 0.177981, 0.178039, 0.177985, 0.178019, 0.177917" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "5.88778, 6.23875, 6.60205, 6.96373, 7.7914, 8.80374", \ + "5.8927, 6.23625, 6.60112, 6.94663, 7.78602, 8.7981", \ + "5.88955, 6.23587, 6.61096, 6.96646, 7.79282, 8.66534", \ + "5.8888, 6.23748, 6.61013, 6.9666, 7.80678, 8.79071", \ + "5.88446, 6.2328, 6.59901, 6.96422, 7.7884, 8.81694", \ + "5.89946, 6.24107, 6.51123, 6.96732, 7.83519, 8.81651", \ + "5.86404, 6.12661, 6.51268, 6.93541, 7.82044, 8.78648" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.55722, 2.55901, 2.55796, 2.56073, 2.55616, 2.55713", \ + "2.55685, 2.55832, 2.5602, 2.55906, 2.55541, 2.55763", \ + "2.55881, 2.55898, 2.55886, 2.56041, 2.55593, 2.55756", \ + "2.55699, 2.55879, 2.55779, 2.56063, 2.55594, 2.55655", \ + "2.55772, 2.55907, 2.55849, 2.55952, 2.55674, 2.55654", \ + "2.55722, 2.55874, 2.56045, 2.55937, 2.55584, 2.55821", \ + "2.55633, 2.5581, 2.5588, 2.56055, 2.55905, 2.56021" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.0215397, 0.0215426, 0.0215441, 0.0215445, 0.0215413, 0.021541", \ + "0.0195966, 0.019599, 0.0196011, 0.0196034, 0.0196011, 0.0196004", \ + "0.0201299, 0.0201322, 0.0201344, 0.0201348, 0.0201319, 0.0201321", \ + "0.023067, 0.0230692, 0.0230715, 0.0230719, 0.0230183, 0.023068", \ + "0.0311358, 0.0311381, 0.0311399, 0.0311407, 0.0311378, 0.0311376", \ + "0.0500791, 0.0500812, 0.0500803, 0.0500839, 0.0500827, 0.0500809", \ + "0.0932504, 0.09322, 0.093257, 0.0932836, 0.093294, 0.093256" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.0364528, 0.0364543, 0.0364524, 0.0364389, 0.0364347, 0.0364304", \ + "0.0350904, 0.0350914, 0.0350758, 0.0350836, 0.0350748, 0.0350695", \ + "0.0350857, 0.0350984, 0.0350952, 0.0350832, 0.0350805, 0.0350758", \ + "0.0367524, 0.0367536, 0.036777, 0.0367366, 0.036766, 0.0367558", \ + "0.0409024, 0.0407877, 0.0407847, 0.0407691, 0.0407661, 0.0408791", \ + "0.0512301, 0.0512317, 0.0512183, 0.0512284, 0.0512144, 0.0512116", \ + "0.0738906, 0.0738946, 0.0738743, 0.0738629, 0.0738293, 0.0738102" \ + ); + } + } + } + pin (c2p) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.016; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0274344; + rise_capacitance : 0.0275056; + rise_capacitance_range (0.0232275, 0.0314441); + fall_capacitance : 0.0273632; + fall_capacitance_range (0.0236743, 0.0295816); + internal_power () { + when : "!c2p_en"; + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0, 0, 0, 0, 3.59294e-07, 4.62804e-07, 2.04987e-06" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0, 0, 0, 0, -3.59294e-07, -4.62804e-07, -2.04987e-06" \ + ); + } + } + internal_power () { + when : "!c2p_en"; + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0164259, -0.0171879, -0.017311, -0.0174895, -0.0175626, -0.0176614, -0.0177364" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0214913, 0.02117, 0.0211933, 0.0209076, 0.0211403, 0.0207638, 0.0208256" \ + ); + } + } + internal_power () { + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0, 0, 0, 0, 3.59294e-07, 4.62804e-07, 2.04987e-06" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0, 0, 0, 0, -3.59294e-07, -4.62804e-07, -2.04987e-06" \ + ); + } + } + internal_power () { + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0164259, -0.0171879, -0.017311, -0.0174895, -0.0175626, -0.0176614, -0.0177364" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0214913, 0.02117, 0.0211933, 0.0209076, 0.0211403, 0.0207638, 0.0208256" \ + ); + } + } + } + pin (c2p_en) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.011; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0259441; + rise_capacitance : 0.0266339; + rise_capacitance_range (0.0231191, 0.0309839); + fall_capacitance : 0.0252542; + fall_capacitance_range (0.0225286, 0.0279998); + } + } + cell (sg13g2_IOPadTriOut30mA) { + pad_cell : true; + area : 14400; + cell_footprint : "tri_out"; + pad_drivers : 1; + bond_pads : 1; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 281.639; + when : "!c2p_en&!c2p"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 1427.56; + when : "!c2p_en&!c2p"; + related_pg_pin : vdd; + } + leakage_power () { + value : 281.639; + when : "!c2p_en&c2p"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 1582.13; + when : "!c2p_en&c2p"; + related_pg_pin : vdd; + } + leakage_power () { + value : 420.062; + when : "c2p_en&c2p&pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 1755.53; + when : "c2p_en&c2p&pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 864.978; + when : "c2p_en&!c2p&!pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 1735.07; + when : "c2p_en&!c2p&!pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 462.08; + related_pg_pin : iovdd; + } + leakage_power () { + value : 1625.07; + related_pg_pin : vdd; + } + pin (pad) { + direction : "output"; + is_pad : true; + function : "c2p"; + three_state : "c2p_en'"; + drive_current : 30; + output_voltage : "pad"; + related_ground_pin : iovss; + related_power_pin : iovdd; + max_capacitance : 4.86346; + capacitance : 0.331669; + rise_capacitance : 0.33092; + rise_capacitance_range (0.33092, 0.33092); + fall_capacitance : 0.332418; + fall_capacitance_range (0.332418, 0.332418); + timing () { + related_pin : "c2p"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.76117, 1.90386, 2.0196, 2.12026, 2.37403, 2.59382", \ + "1.7818, 1.92424, 2.03995, 2.14051, 2.39424, 2.61408", \ + "1.79628, 1.93859, 2.05396, 2.15455, 2.4082, 2.62813", \ + "1.82046, 1.96314, 2.07827, 2.17873, 2.43246, 2.65228", \ + "1.84912, 1.99151, 2.10683, 2.20726, 2.46105, 2.67802", \ + "1.88522, 2.02747, 2.14286, 2.24323, 2.49668, 2.71404", \ + "1.92551, 2.0677, 2.18418, 2.28495, 2.53813, 2.75815" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.492622, 0.660172, 0.801621, 0.929583, 1.28203, 1.62405", \ + "0.492623, 0.660173, 0.801622, 0.929584, 1.28204, 1.62421", \ + "0.492624, 0.660174, 0.801623, 0.929585, 1.28205, 1.62424", \ + "0.492625, 0.660175, 0.801624, 0.929586, 1.28206, 1.62425", \ + "0.492626, 0.660176, 0.801625, 0.929587, 1.28207, 1.62426", \ + "0.492627, 0.660177, 0.801626, 0.929588, 1.28207, 1.62427", \ + "0.492628, 0.661817, 0.801885, 0.92982, 1.28235, 1.62472" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.66341, 1.7498, 1.82824, 1.90105, 2.09816, 2.27858", \ + "1.68412, 1.77053, 1.84894, 1.91982, 2.11965, 2.2989", \ + "1.70119, 1.78796, 1.86671, 1.9388, 2.13611, 2.31673", \ + "1.7377, 1.82425, 1.90194, 1.97338, 2.17277, 2.35281", \ + "1.79729, 1.88297, 1.96182, 2.03425, 2.2324, 2.41161", \ + "1.88506, 1.97176, 2.05041, 2.1223, 2.32205, 2.50032", \ + "2.02022, 2.10624, 2.18407, 2.25651, 2.45506, 2.63449" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.899354, 0.959727, 1.03778, 1.11888, 1.3666, 1.62895", \ + "0.903478, 0.962844, 1.04128, 1.12151, 1.37125, 1.63157", \ + "0.906117, 0.966019, 1.04129, 1.12408, 1.37262, 1.63299", \ + "0.912722, 0.971566, 1.04881, 1.12757, 1.37724, 1.636", \ + "0.914883, 0.972742, 1.05041, 1.13109, 1.37852, 1.63836", \ + "0.914884, 0.972743, 1.05042, 1.1311, 1.37853, 1.63837", \ + "0.914885, 0.972744, 1.05043, 1.13111, 1.37854, 1.63838" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : negative_unate; + timing_type : three_state_disable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.33963, 1.33964, 1.33965, 1.33966, 1.33967, 1.33968", \ + "1.36497, 1.36498, 1.36499, 1.365, 1.36501, 1.36502", \ + "1.37774, 1.37775, 1.37776, 1.37777, 1.37778, 1.37779", \ + "1.40981, 1.40982, 1.40983, 1.40984, 1.40985, 1.40986", \ + "1.44787, 1.44788, 1.44789, 1.4479, 1.44791, 1.44792", \ + "1.50822, 1.50823, 1.50824, 1.50825, 1.50826, 1.50827", \ + "1.59418, 1.59419, 1.5942, 1.59421, 1.59422, 1.59423" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.33963, 1.33964, 1.33965, 1.33966, 1.33967, 1.33968", \ + "1.36497, 1.36498, 1.36499, 1.365, 1.36501, 1.36502", \ + "1.37774, 1.37775, 1.37776, 1.37777, 1.37778, 1.37779", \ + "1.40981, 1.40982, 1.40983, 1.40984, 1.40985, 1.40986", \ + "1.44787, 1.44788, 1.44789, 1.4479, 1.44791, 1.44792", \ + "1.50822, 1.50823, 1.50824, 1.50825, 1.50826, 1.50827", \ + "1.59418, 1.59419, 1.5942, 1.59421, 1.59422, 1.59423" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.94579, 1.9458, 1.94581, 1.94582, 1.94583, 1.94584", \ + "1.96956, 1.96957, 1.96958, 1.96959, 1.9696, 1.96961", \ + "1.98985, 1.98986, 1.98987, 1.98988, 1.98989, 1.9899", \ + "2.028, 2.02801, 2.02802, 2.02803, 2.02804, 2.02805", \ + "2.08575, 2.08576, 2.08577, 2.08578, 2.08579, 2.0858", \ + "2.16255, 2.16256, 2.16257, 2.16258, 2.16259, 2.1626", \ + "2.25419, 2.2542, 2.25421, 2.25422, 2.25423, 2.25424" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.94579, 1.9458, 1.94581, 1.94582, 1.94583, 1.94584", \ + "1.96956, 1.96957, 1.96958, 1.96959, 1.9696, 1.96961", \ + "1.98985, 1.98986, 1.98987, 1.98988, 1.98989, 1.9899", \ + "2.028, 2.02801, 2.02802, 2.02803, 2.02804, 2.02805", \ + "2.08575, 2.08576, 2.08577, 2.08578, 2.08579, 2.0858", \ + "2.16255, 2.16256, 2.16257, 2.16258, 2.16259, 2.1626", \ + "2.25419, 2.2542, 2.25421, 2.25422, 2.25423, 2.25424" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : positive_unate; + timing_type : three_state_enable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.73374, 1.89317, 2.01708, 2.12456, 2.39218, 2.62127", \ + "1.75311, 1.91202, 2.0364, 2.14383, 2.40993, 2.64045", \ + "1.76705, 1.92571, 2.05024, 2.15767, 2.42499, 2.65442", \ + "1.79204, 1.95111, 2.07545, 2.18174, 2.44913, 2.67955", \ + "1.82048, 1.97944, 2.10376, 2.21118, 2.47727, 2.7078", \ + "1.85726, 2.0165, 2.1405, 2.24791, 2.51415, 2.7445", \ + "1.89857, 2.05852, 2.18323, 2.28865, 2.55584, 2.7852" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.518186, 0.665186, 0.794091, 0.915345, 1.256, 1.59197", \ + "0.518187, 0.665187, 0.794092, 0.915346, 1.25601, 1.59198", \ + "0.518188, 0.665188, 0.794212, 0.915415, 1.25602, 1.59215", \ + "0.518189, 0.665189, 0.794213, 0.915419, 1.25603, 1.59216", \ + "0.51819, 0.66519, 0.794214, 0.91542, 1.25604, 1.59217", \ + "0.518191, 0.665191, 0.794215, 0.915421, 1.25605, 1.59218", \ + "0.518727, 0.665192, 0.794216, 0.917387, 1.25822, 1.59342" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.28022, 1.4005, 1.4997, 1.5875, 1.81853, 2.02632", \ + "1.29954, 1.41982, 1.51902, 1.60618, 1.83785, 2.04564", \ + "1.31126, 1.43155, 1.53075, 1.61768, 1.84956, 2.05735", \ + "1.33028, 1.45056, 1.54906, 1.63754, 1.86855, 2.07392", \ + "1.35641, 1.4767, 1.5759, 1.66258, 1.89448, 2.10225", \ + "1.38197, 1.50264, 1.60161, 1.68842, 1.91914, 2.12847", \ + "1.4094, 1.52981, 1.62708, 1.71397, 1.94545, 2.15309" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.371943, 0.494963, 0.607716, 0.715625, 1.0291, 1.34138", \ + "0.371944, 0.494964, 0.607717, 0.715626, 1.02911, 1.34139", \ + "0.371945, 0.494971, 0.607718, 0.715627, 1.02912, 1.3414", \ + "0.371946, 0.494972, 0.607719, 0.715628, 1.02913, 1.34141", \ + "0.371947, 0.494973, 0.60772, 0.715629, 1.02917, 1.34142", \ + "0.371948, 0.495139, 0.607732, 0.71563, 1.02918, 1.34142", \ + "0.373074, 0.49514, 0.607733, 0.715631, 1.02919, 1.34143" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "10.0559, 9.83937, 9.75005, 9.7055, 9.54202, 9.66712", \ + "10.0813, 9.86111, 9.7718, 9.7283, 9.56182, 9.68048", \ + "10.0932, 9.88517, 9.77371, 9.73368, 9.56274, 9.68454", \ + "10.0952, 9.87214, 9.77813, 9.7312, 9.56178, 9.68184", \ + "10.0985, 9.88167, 9.77648, 9.66689, 9.56812, 9.45229", \ + "10.0968, 9.88798, 9.77935, 9.72833, 9.56168, 9.43975", \ + "9.99753, 9.78939, 9.73299, 9.69339, 9.46866, 9.6228" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "53.604, 50.3665, 47.6091, 45.2784, 39.8933, 36.1779", \ + "53.9332, 50.7079, 47.9484, 45.5829, 40.1788, 36.35", \ + "54.1596, 50.8515, 48.0913, 45.7533, 40.3391, 36.4967", \ + "54.654, 51.3365, 48.582, 46.2084, 40.7906, 36.8613", \ + "54.8331, 51.5397, 48.7827, 46.4168, 40.8942, 37.0052", \ + "54.6558, 51.3183, 48.5441, 46.2009, 40.6839, 36.8581", \ + "53.9171, 50.6269, 47.9171, 45.5531, 40.1872, 36.3205" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.0492659, 0.0492667, 0.0492656, 0.0492646, 0.0492628, 0.0492684", \ + "0.0469157, 0.0469158, 0.0469175, 0.0469165, 0.0469126, 0.0469163", \ + "0.0468615, 0.0468592, 0.0468597, 0.0468609, 0.0468578, 0.0468608", \ + "0.0478743, 0.047876, 0.0478741, 0.0478753, 0.0478747, 0.0478751", \ + "0.053634, 0.053634, 0.0536352, 0.0536321, 0.0536334, 0.0536331", \ + "0.0695579, 0.0695567, 0.0695581, 0.069555, 0.0695563, 0.0695563", \ + "0.107219, 0.107178, 0.10722, 0.107215, 0.107169, 0.107171" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.119353, 0.119361, 0.119353, 0.119347, 0.119358, 0.119352", \ + "0.116976, 0.116977, 0.116982, 0.116981, 0.116979, 0.116974", \ + "0.116907, 0.116904, 0.116899, 0.116896, 0.116896, 0.116895", \ + "0.118193, 0.118181, 0.118187, 0.118181, 0.118182, 0.118182", \ + "0.124348, 0.124351, 0.124357, 0.124352, 0.124351, 0.124345", \ + "0.140183, 0.14017, 0.140175, 0.140179, 0.140174, 0.140173", \ + "0.178019, 0.177828, 0.177852, 0.178031, 0.177834, 0.177911" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "9.05155, 9.38697, 9.72002, 10.1302, 11.154, 12.2556", \ + "9.05879, 9.37575, 9.72345, 10.135, 11.0805, 12.258", \ + "9.05322, 9.36001, 9.71335, 10.1236, 11.1362, 12.2569", \ + "9.0512, 9.37288, 9.72444, 10.1228, 11.1346, 12.2565", \ + "9.05383, 9.37335, 9.71883, 10.1297, 11.081, 12.2559", \ + "9.05694, 9.38795, 9.72183, 10.1324, 11.0918, 12.2558", \ + "9.03155, 9.3861, 9.75546, 10.0355, 11.0102, 12.1146" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "4.2171, 4.21877, 4.22212, 4.22335, 4.2247, 4.22259", \ + "4.21691, 4.21863, 4.22193, 4.22219, 4.22449, 4.22239", \ + "4.2172, 4.21889, 4.22211, 4.22246, 4.22459, 4.22253", \ + "4.21688, 4.21855, 4.22047, 4.22311, 4.22422, 4.22408", \ + "4.21757, 4.21928, 4.22244, 4.22294, 4.22508, 4.22304", \ + "4.21795, 4.22094, 4.22336, 4.22354, 4.22507, 4.22466", \ + "4.21898, 4.21807, 4.21824, 4.22062, 4.22279, 4.22415" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.0215251, 0.0215247, 0.0215253, 0.0215259, 0.0215282, 0.0215295", \ + "0.0195826, 0.0195823, 0.0195827, 0.0195834, 0.0195851, 0.019587", \ + "0.020115, 0.0201148, 0.0201151, 0.0201158, 0.0201177, 0.0201195", \ + "0.023001, 0.0230005, 0.023001, 0.0230527, 0.023055, 0.0230052", \ + "0.0311211, 0.0311213, 0.0311211, 0.0311221, 0.0311235, 0.0311254", \ + "0.0508398, 0.0508401, 0.05084, 0.050841, 0.0508426, 0.0508448", \ + "0.0931218, 0.0931525, 0.0931243, 0.0930792, 0.0930728, 0.0930738" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.0363954, 0.0363908, 0.0363817, 0.0363829, 0.0363768, 0.0363717", \ + "0.0350129, 0.0350076, 0.0349994, 0.0349976, 0.0349943, 0.0349892", \ + "0.0350345, 0.0350297, 0.0350245, 0.0350235, 0.0350191, 0.0350141", \ + "0.036691, 0.0366862, 0.0367008, 0.0366788, 0.036696, 0.0366898", \ + "0.0407208, 0.0407155, 0.0407119, 0.0408084, 0.0408007, 0.0407984", \ + "0.0512926, 0.0512862, 0.0512823, 0.0512768, 0.0512745, 0.0512646", \ + "0.073617, 0.0736526, 0.0736475, 0.0736312, 0.0736503, 0.0735361" \ + ); + } + } + } + pin (c2p) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.016; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0274344; + rise_capacitance : 0.0275057; + rise_capacitance_range (0.0232278, 0.0314441); + fall_capacitance : 0.0273632; + fall_capacitance_range (0.0236745, 0.0295816); + internal_power () { + when : "!c2p_en"; + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0, 0, 0.00030268, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0, 0, -0.00030268, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + when : "!c2p_en"; + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0164258, -0.0171878, -0.0173124, -0.0174894, -0.0175627, -0.0176614, -0.0177364" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0214916, 0.0211701, 0.021191, 0.0209197, 0.0211399, 0.0207635, 0.0207834" \ + ); + } + } + internal_power () { + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0, 0, 0.00030268, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0, 0, -0.00030268, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0164258, -0.0171878, -0.0173124, -0.0174894, -0.0175627, -0.0176614, -0.0177364" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0214916, 0.0211701, 0.021191, 0.0209197, 0.0211399, 0.0207635, 0.0207834" \ + ); + } + } + } + pin (c2p_en) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.011; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0259423; + rise_capacitance : 0.0266304; + rise_capacitance_range (0.0231191, 0.0310366); + fall_capacitance : 0.0252543; + fall_capacitance_range (0.0225284, 0.0280111); + } + } + cell (sg13g2_IOPadTriOut4mA) { + pad_cell : true; + area : 14400; + cell_footprint : "tri_out"; + pad_drivers : 1; + bond_pads : 1; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 13.8342; + when : "!c2p_en&!c2p"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 1427.49; + when : "!c2p_en&!c2p"; + related_pg_pin : vdd; + } + leakage_power () { + value : 13.8342; + when : "!c2p_en&c2p"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 1582.05; + when : "!c2p_en&c2p"; + related_pg_pin : vdd; + } + leakage_power () { + value : 62.7147; + when : "c2p_en&c2p&pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 1755.43; + when : "c2p_en&c2p&pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 117.701; + when : "c2p_en&!c2p&!pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 1734.81; + when : "c2p_en&!c2p&!pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 52.021; + related_pg_pin : iovdd; + } + leakage_power () { + value : 1624.95; + related_pg_pin : vdd; + } + pin (pad) { + direction : "output"; + is_pad : true; + function : "c2p"; + three_state : "c2p_en'"; + drive_current : 4; + output_voltage : "pad"; + related_ground_pin : iovss; + related_power_pin : iovdd; + max_capacitance : 1.11181; + capacitance : 0.163207; + rise_capacitance : 0.167318; + rise_capacitance_range (0.167318, 0.167318); + fall_capacitance : 0.159097; + fall_capacitance_range (0.159097, 0.159097); + timing () { + related_pin : "c2p"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.55578, 1.99204, 2.4254, 2.85835, 4.15527, 5.45129", \ + "1.57494, 2.01108, 2.44449, 2.87731, 4.17422, 5.47059", \ + "1.58907, 2.02518, 2.45867, 2.89152, 4.18838, 5.48478", \ + "1.61354, 2.04969, 2.48348, 2.91632, 4.21324, 5.51044", \ + "1.64245, 2.07831, 2.51196, 2.94491, 4.24184, 5.53698", \ + "1.68073, 2.11699, 2.5504, 2.98328, 4.28017, 5.57498", \ + "1.71888, 2.1552, 2.58873, 3.02204, 4.31853, 5.61473" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.10131, 1.98794, 2.88458, 3.78205, 6.48434, 9.18015", \ + "1.10132, 1.98836, 2.88459, 3.78294, 6.48435, 9.1804", \ + "1.10133, 1.98887, 2.8846, 3.78295, 6.48436, 9.18377", \ + "1.10134, 1.98888, 2.88461, 3.78296, 6.48437, 9.18378", \ + "1.10135, 1.98889, 2.88462, 3.78297, 6.48438, 9.18379", \ + "1.10136, 1.9889, 2.88463, 3.78298, 6.48439, 9.1838", \ + "1.10165, 1.98891, 2.88464, 3.78299, 6.48441, 9.18495" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.44376, 1.87326, 2.30154, 2.72884, 4.01143, 5.29447", \ + "1.46274, 1.89213, 2.32028, 2.74764, 4.03043, 5.31292", \ + "1.47884, 1.90803, 2.33618, 2.76381, 4.04572, 5.32894", \ + "1.51234, 1.94126, 2.3692, 2.7968, 4.07871, 5.36071", \ + "1.57106, 1.99991, 2.42746, 2.85515, 4.13702, 5.42017", \ + "1.66069, 2.08973, 2.51735, 2.94503, 4.22771, 5.509", \ + "1.79854, 2.22777, 2.65567, 3.08379, 4.36548, 5.64887" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.00252, 1.82529, 2.6544, 3.48459, 5.98214, 8.47953", \ + "1.00275, 1.8253, 2.65441, 3.48552, 5.98215, 8.47954", \ + "1.00276, 1.8263, 2.65442, 3.48553, 5.9823, 8.47955", \ + "1.00311, 1.82631, 2.65444, 3.48554, 5.98231, 8.47956", \ + "1.00312, 1.82632, 2.65447, 3.48555, 5.98232, 8.47957", \ + "1.00313, 1.82633, 2.65448, 3.48556, 5.98233, 8.47958", \ + "1.00314, 1.82634, 2.65454, 3.48561, 5.98234, 8.47959" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : negative_unate; + timing_type : three_state_disable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.952844, 0.952845, 0.952846, 0.952847, 0.952848, 0.952849", \ + "0.972317, 0.972318, 0.972319, 0.97232, 0.972321, 0.972322", \ + "0.991611, 0.991612, 0.991613, 0.991614, 0.991615, 0.991616", \ + "1.02356, 1.02357, 1.02358, 1.02359, 1.0236, 1.02361", \ + "1.05823, 1.05824, 1.05825, 1.05826, 1.05827, 1.05828", \ + "1.1193, 1.11931, 1.11932, 1.11933, 1.11934, 1.11935", \ + "1.20627, 1.20628, 1.20629, 1.2063, 1.20631, 1.20632" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.952844, 0.952845, 0.952846, 0.952847, 0.952848, 0.952849", \ + "0.972317, 0.972318, 0.972319, 0.97232, 0.972321, 0.972322", \ + "0.991611, 0.991612, 0.991613, 0.991614, 0.991615, 0.991616", \ + "1.02356, 1.02357, 1.02358, 1.02359, 1.0236, 1.02361", \ + "1.05823, 1.05824, 1.05825, 1.05826, 1.05827, 1.05828", \ + "1.1193, 1.11931, 1.11932, 1.11933, 1.11934, 1.11935", \ + "1.20627, 1.20628, 1.20629, 1.2063, 1.20631, 1.20632" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.874453, 0.874454, 0.874455, 0.874456, 0.874457, 0.874458", \ + "0.898612, 0.898613, 0.898614, 0.898615, 0.898616, 0.898617", \ + "0.918907, 0.918908, 0.918909, 0.91891, 0.918911, 0.918912", \ + "0.956781, 0.956782, 0.956783, 0.956784, 0.956785, 0.956786", \ + "1.01381, 1.01382, 1.01383, 1.01384, 1.01385, 1.01386", \ + "1.09375, 1.09376, 1.09377, 1.09378, 1.09379, 1.0938", \ + "1.21674, 1.21675, 1.21676, 1.21677, 1.21678, 1.21679" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.874453, 0.874454, 0.874455, 0.874456, 0.874457, 0.874458", \ + "0.898612, 0.898613, 0.898614, 0.898615, 0.898616, 0.898617", \ + "0.918907, 0.918908, 0.918909, 0.91891, 0.918911, 0.918912", \ + "0.956781, 0.956782, 0.956783, 0.956784, 0.956785, 0.956786", \ + "1.01381, 1.01382, 1.01383, 1.01384, 1.01385, 1.01386", \ + "1.09375, 1.09376, 1.09377, 1.09378, 1.09379, 1.0938", \ + "1.21674, 1.21675, 1.21676, 1.21677, 1.21678, 1.21679" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : positive_unate; + timing_type : three_state_enable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.56138, 2.01554, 2.46787, 2.91831, 4.26981, 5.62209", \ + "1.57906, 2.03373, 2.48525, 2.9361, 4.28848, 5.64014", \ + "1.59535, 2.04957, 2.50091, 2.95186, 4.3047, 5.65613", \ + "1.6194, 2.07361, 2.52622, 2.97624, 4.32774, 5.68015", \ + "1.64904, 2.10329, 2.55489, 3.00557, 4.35651, 5.7098", \ + "1.6874, 2.14186, 2.59412, 3.04435, 4.39595, 5.74834", \ + "1.72797, 2.18225, 2.634, 3.08486, 4.43507, 5.78864" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.09934, 1.98693, 2.88363, 3.78313, 6.48442, 9.18144", \ + "1.09935, 1.98722, 2.88447, 3.78345, 6.48443, 9.18182", \ + "1.09936, 1.98779, 2.88448, 3.78346, 6.48444, 9.18183", \ + "1.09937, 1.9878, 2.88449, 3.78359, 6.48445, 9.18184", \ + "1.09938, 1.98781, 2.8845, 3.7836, 6.48446, 9.18185", \ + "1.09939, 1.98782, 2.88451, 3.78361, 6.48447, 9.18186", \ + "1.0994, 1.98783, 2.88452, 3.78368, 6.48448, 9.18191" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.46421, 1.93325, 2.40088, 2.86744, 4.2672, 5.6665", \ + "1.48346, 1.9525, 2.42014, 2.8867, 4.28646, 5.68576", \ + "1.49522, 1.96428, 2.43156, 2.8984, 4.29813, 5.69745", \ + "1.51394, 1.98317, 2.4505, 2.91799, 4.31715, 5.71646", \ + "1.54045, 2.00881, 2.47645, 2.94301, 4.34341, 5.74206", \ + "1.56336, 2.03237, 2.49964, 2.96657, 4.36633, 5.76552", \ + "1.5923, 2.06138, 2.52874, 2.99552, 4.3953, 5.79463" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.997332, 1.82255, 2.65295, 3.48377, 5.98542, 8.48408", \ + "0.997333, 1.82256, 2.65296, 3.48378, 5.98543, 8.48409", \ + "0.997349, 1.82257, 2.65297, 3.48379, 5.98544, 8.4841", \ + "0.99735, 1.82258, 2.65303, 3.48496, 5.98545, 8.48411", \ + "0.997352, 1.82259, 2.65304, 3.48497, 5.98546, 8.48412", \ + "0.997353, 1.8226, 2.65305, 3.48498, 5.98547, 8.48413", \ + "0.997354, 1.82261, 2.65306, 3.48506, 5.98548, 8.48414" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "3.16644, 3.1443, 3.11365, 3.08035, 2.99736, 2.89925", \ + "3.16196, 3.13573, 3.10698, 3.07454, 2.98868, 2.891", \ + "3.16241, 3.13528, 3.10906, 3.07666, 2.9934, 2.89621", \ + "3.15996, 3.13835, 3.11147, 3.0785, 2.99475, 2.89014", \ + "3.16257, 3.13645, 3.10484, 3.08131, 2.99379, 2.89667", \ + "3.16272, 3.13674, 3.10791, 3.08362, 2.99736, 2.881", \ + "3.15336, 3.13238, 3.10078, 3.07055, 2.98574, 2.89717" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.99739, 1.99219, 1.99062, 1.99069, 1.98949, 1.9887", \ + "2.00307, 1.99572, 1.99281, 1.99272, 1.99007, 1.98937", \ + "2.00669, 1.99684, 1.99313, 1.99181, 1.98979, 1.98878", \ + "2.0161, 2.00208, 1.99778, 1.99406, 1.99031, 1.98869", \ + "2.01894, 2.0037, 1.99829, 1.99449, 1.99035, 1.98902", \ + "2.02215, 2.00821, 2.00365, 1.99999, 1.99692, 1.99531", \ + "2.00258, 1.99527, 1.99187, 1.9934, 1.98912, 1.98992" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.0493334, 0.0493289, 0.0493311, 0.0493302, 0.049331, 0.0493306", \ + "0.0469859, 0.0469821, 0.0469804, 0.0469805, 0.0469822, 0.0469817", \ + "0.0469292, 0.0469256, 0.0469266, 0.0469265, 0.0469271, 0.046927", \ + "0.0479455, 0.0479417, 0.0479406, 0.0479406, 0.0479416, 0.0479414", \ + "0.0537047, 0.0537017, 0.053699, 0.0536996, 0.0537007, 0.0537012", \ + "0.0696885, 0.069685, 0.0696836, 0.0696846, 0.0696847, 0.0696846", \ + "0.107292, 0.107286, 0.107282, 0.107291, 0.107215, 0.107212" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.119602, 0.119612, 0.11961, 0.119615, 0.119606, 0.119606", \ + "0.117233, 0.117236, 0.117232, 0.117237, 0.117237, 0.117235", \ + "0.117151, 0.117161, 0.117158, 0.117149, 0.117155, 0.117154", \ + "0.118437, 0.11845, 0.118447, 0.118439, 0.118437, 0.118443", \ + "0.124613, 0.124617, 0.124611, 0.124616, 0.124615, 0.124617", \ + "0.140457, 0.140456, 0.140449, 0.140455, 0.140456, 0.140455", \ + "0.178195, 0.178196, 0.178138, 0.178293, 0.17817, 0.178292" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "3.03984, 3.24345, 3.45216, 3.65501, 4.29624, 4.9201", \ + "3.03793, 3.25751, 3.45444, 3.66363, 4.28984, 4.91311", \ + "3.04029, 3.25154, 3.44867, 3.65963, 4.28766, 4.90849", \ + "3.03898, 3.24774, 3.45441, 3.65871, 4.28881, 4.90868", \ + "3.04394, 3.25072, 3.45325, 3.64799, 4.27964, 4.91426", \ + "3.04346, 3.24787, 3.45751, 3.66244, 4.30152, 4.92815", \ + "3.04146, 3.25105, 3.45982, 3.66541, 4.28838, 4.92921" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.15253, 1.15179, 1.1523, 1.15149, 1.15025, 1.14993", \ + "1.15235, 1.15162, 1.15211, 1.15132, 1.15007, 1.14975", \ + "1.15271, 1.15198, 1.15187, 1.15077, 1.14995, 1.14996", \ + "1.15369, 1.15108, 1.15146, 1.15014, 1.14954, 1.14968", \ + "1.15291, 1.15224, 1.15275, 1.15193, 1.15078, 1.15037", \ + "1.15061, 1.15005, 1.15104, 1.14962, 1.14844, 1.14816", \ + "1.1515, 1.15119, 1.15171, 1.14998, 1.1495, 1.1492" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.0215954, 0.0215927, 0.0215901, 0.0215909, 0.021594, 0.0215929", \ + "0.0196512, 0.0196497, 0.0196486, 0.0196501, 0.0196532, 0.0196529", \ + "0.0201831, 0.0201805, 0.0201786, 0.0201778, 0.0201841, 0.0201827", \ + "0.0231205, 0.023118, 0.0230679, 0.0231171, 0.0231202, 0.02312", \ + "0.0311913, 0.0311879, 0.0311857, 0.0311871, 0.0311902, 0.0311898", \ + "0.0505037, 0.0505028, 0.0505003, 0.0505012, 0.0505037, 0.050503", \ + "0.0936068, 0.0936596, 0.0935878, 0.093636, 0.0936455, 0.0936481" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.0366594, 0.0366588, 0.0366606, 0.0366593, 0.036658, 0.0366573", \ + "0.0353141, 0.0353135, 0.0353154, 0.035314, 0.0353127, 0.0353119", \ + "0.0352985, 0.035296, 0.0353004, 0.0352983, 0.0352955, 0.0352957", \ + "0.0370015, 0.0369966, 0.0369971, 0.0369949, 0.036992, 0.0369921", \ + "0.041006, 0.0411933, 0.0411952, 0.0411939, 0.0410045, 0.0411914", \ + "0.0514388, 0.051439, 0.0514413, 0.0514391, 0.0514364, 0.0514378", \ + "0.0744967, 0.0743744, 0.0743458, 0.0744705, 0.0743537, 0.0743615" \ + ); + } + } + } + pin (c2p) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.016; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0274345; + rise_capacitance : 0.0275056; + rise_capacitance_range (0.0232275, 0.031444); + fall_capacitance : 0.0273633; + fall_capacitance_range (0.0236742, 0.0295819); + internal_power () { + when : "!c2p_en"; + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0, 0, 0, 0, 0, 0, 3.6554e-07" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0, 0, 0, 0, 0, 0, -3.6554e-07" \ + ); + } + } + internal_power () { + when : "!c2p_en"; + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0164258, -0.0171878, -0.0173125, -0.0174888, -0.0174919, -0.0176614, -0.0177364" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0214919, 0.0211705, 0.021092, 0.0212474, 0.0211413, 0.0207645, 0.0209009" \ + ); + } + } + internal_power () { + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0, 0, 0, 0, 0, 0, 3.6554e-07" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0, 0, 0, 0, 0, 0, -3.6554e-07" \ + ); + } + } + internal_power () { + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0164258, -0.0171878, -0.0173125, -0.0174888, -0.0174919, -0.0176614, -0.0177364" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0214919, 0.0211705, 0.021092, 0.0212474, 0.0211413, 0.0207645, 0.0209009" \ + ); + } + } + } + pin (c2p_en) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.011; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0259476; + rise_capacitance : 0.0266431; + rise_capacitance_range (0.0231204, 0.0310979); + fall_capacitance : 0.0252521; + fall_capacitance_range (0.0225309, 0.0280484); + } + } + cell (sg13g2_IOPadVdd) { + area : 14400; + pad_cell : true; + bond_pads : 1; + dont_touch : true; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + is_pad : true; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 0; + related_pg_pin : iovdd; + } + leakage_power () { + value : 0; + related_pg_pin : vdd; + } + } + cell (sg13g2_IOPadVss) { + area : 14400; + pad_cell : true; + bond_pads : 1; + dont_touch : true; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + is_pad : true; + } + leakage_power () { + value : 0; + related_pg_pin : iovdd; + } + leakage_power () { + value : 0.952358; + related_pg_pin : vdd; + } + } +} diff --git a/flow/platforms/ihp-sg13g2/lib/sg13g2_io_typ_1p5V_3p3V_25C.lib b/flow/platforms/ihp-sg13g2/lib/sg13g2_io_typ_1p5V_3p3V_25C.lib new file mode 100644 index 0000000000..73e301b713 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/lib/sg13g2_io_typ_1p5V_3p3V_25C.lib @@ -0,0 +1,4599 @@ +/************************************************************************ + + Copyright 2024 IHP PDK Authors + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + https://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +************************************************************************/ + +library (sg13g2_io_typ_1p5V_3p3V_25C) { + comment : "IHP Microelectronics GmbH, 2024"; + date : "$Date: Wed May 8 12:24:55 2024 $"; + revision : "$Revision: 0.0.1 $"; + delay_model : table_lookup; + capacitive_load_unit (1,pf); + current_unit : "1uA"; + leakage_power_unit : "1pW"; + pulling_resistance_unit : "1kohm"; + time_unit : "1ns"; + voltage_unit : "1V"; + voltage_map (vdd, 1.5); + voltage_map (iovdd, 3.3); + voltage_map (iovss, 0); + voltage_map (vss, 0); + voltage_map (GND, 0); + define_cell_area (pad_drivers, pad_driver_sites); + define_cell_area (bond_pads, pad_slots); + default_output_pin_cap : 0; + default_inout_pin_cap : 1; + default_input_pin_cap : 1; + default_fanout_load : 1; + default_cell_leakage_power : 0; + default_max_transition : 1.2; + default_leakage_power_density : 0; + default_max_capacitance : 0.3; + default_max_fanout : 8; + default_wire_load_area : 0.29; + default_wire_load_capacitance : 0.0003; + default_wire_load_mode : "enclosed"; + default_wire_load_resistance : 0.0057; + in_place_swap_mode : match_footprint; + input_threshold_pct_fall : 50; + input_threshold_pct_rise : 50; + nom_process : 1; + nom_temperature : 25; + nom_voltage : 1.5; + output_threshold_pct_fall : 50; + output_threshold_pct_rise : 50; + slew_derate_from_library : 1; + slew_lower_threshold_pct_fall : 10; + slew_lower_threshold_pct_rise : 10; + slew_upper_threshold_pct_fall : 90; + slew_upper_threshold_pct_rise : 90; + operating_conditions (sg13g2_io_typ_1p5V_3p3V_25C) { + process : 1; + temperature : 25; + voltage : 1.5; + } + input_voltage (pad) { + vih : 3.3; + vil : 0; + vimax : 3.3; + vimin : 0; + } + input_voltage (core) { + vih : 1.2; + vil : 0; + vimax : 1.2; + vimin : 0; + } + output_voltage (pad) { + voh : 3.3; + vol : 0; + vomax : 3.3; + vomin : 0; + } + output_voltage (core) { + voh : 1.2; + vol : 0; + vomax : 1.2; + vomin : 0; + } + wire_load (Zero) { + area : 0.01; + capacitance : 0.0001; + resistance : 0.0001; + slope : 1; + fanout_length (1, 0.01); + fanout_length (5, 0.01); + fanout_length (20, 0.01); + } + wire_load ("0_1k") { + area : 0.36; + capacitance : 0.0001; + resistance : 0.0035; + slope : 7.387; + fanout_length (1, 6.43); + fanout_length (5, 38.56); + fanout_length (20, 146.8); + } + wire_load ("0_5k") { + area : 0.36; + capacitance : 0.0001; + resistance : 0.0042; + slope : 10.99; + fanout_length (1, 7.89); + fanout_length (5, 47.32); + fanout_length (20, 169.4); + } + wire_load ("1k") { + area : 0.36; + capacitance : 0.0002; + resistance : 0.0053; + slope : 10.9; + fanout_length (1, 9.93); + fanout_length (5, 59.59); + fanout_length (20, 215.6); + } + wire_load ("2k") { + area : 0.36; + capacitance : 0.0002; + resistance : 0.0063; + slope : 16.87; + fanout_length (1, 11.68); + fanout_length (5, 70.11); + fanout_length (20, 239.5); + } + wire_load ("5k") { + area : 0.36; + capacitance : 0.0003; + resistance : 0.0072; + slope : 14.58; + fanout_length (1, 13.44); + fanout_length (5, 80.62); + fanout_length (20, 287.1); + } + wire_load ("10k") { + area : 0.37; + capacitance : 0.0003; + resistance : 0.008; + slope : 18.94; + fanout_length (1, 14.9); + fanout_length (5, 89.39); + fanout_length (20, 381.6); + } + wire_load ("30k") { + area : 0.37; + capacitance : 0.0003; + resistance : 0.0094; + slope : 24.61; + fanout_length (1, 17.53); + fanout_length (5, 105.2); + fanout_length (20, 515.5); + } + wire_load ("50k") { + area : 0.37; + capacitance : 0.0005; + resistance : 0.0152; + slope : 31.81; + fanout_length (1, 28.33); + fanout_length (5, 170); + fanout_length (20, 607.6); + } + wire_load ("100k") { + area : 0.39; + capacitance : 0.0009; + resistance : 0.0265; + slope : 40.22; + fanout_length (1, 49.37); + fanout_length (5, 296.2); + fanout_length (20, 812.1); + } + wire_load ("200k") { + area : 0.41; + capacitance : 0.0016; + resistance : 0.0456; + slope : 52.68; + fanout_length (1, 84.71); + fanout_length (5, 508.3); + fanout_length (20, 1051.7); + } + wire_load ("500k") { + area : 0.45; + capacitance : 0.0027; + resistance : 0.076; + slope : 67.44; + fanout_length (1, 141.4); + fanout_length (5, 848.3); + fanout_length (20, 1527.1); + } + wire_load_selection ("4_metls_routing") { + wire_load_from_area (0, 635, 0_1k); + wire_load_from_area (635, 3175, 0_5k); + wire_load_from_area (3175, 6350, 1k); + wire_load_from_area (6350, 12701, 2k); + wire_load_from_area (12701, 31752, 5k); + wire_load_from_area (31752, 63504, 10k); + wire_load_from_area (63504, 190512, 30k); + wire_load_from_area (190512, 317520, 50k); + wire_load_from_area (317520, 635040, 100k); + wire_load_from_area (635040, 1.27008e+06, 200k); + wire_load_from_area (1.27008e+06, 3.1752e+06, 500k); + } + default_wire_load : "1k"; + default_operating_conditions : sg13g2_io_typ_1p5V_3p3V_25C; + default_wire_load_selection : "4_metls_routing"; + lu_table_template (delay_template_7x6_16) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 3, 7, 9, 12, 15"); + } + power_lut_template (passive_power_template_7x1_16) { + variable_1 : input_transition_time; + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + } + power_lut_template (power_template_7x6_16) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 3, 7, 9, 12, 15"); + } + cell (sg13g2_IOPadIOVdd) { + area : 14400; + pad_cell : true; + bond_pads : 1; + dont_touch : true; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + is_pad : true; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 4853.24; + related_pg_pin : iovdd; + } + leakage_power () { + value : 0; + related_pg_pin : vdd; + } + } + cell (sg13g2_IOPadIOVss) { + area : 14400; + pad_cell : true; + bond_pads : 1; + dont_touch : true; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + is_pad : true; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 0; + related_pg_pin : iovdd; + } + leakage_power () { + value : 2.36698; + related_pg_pin : vdd; + } + } + cell (sg13g2_IOPadIn) { + pad_cell : true; + area : 14400; + cell_footprint : "input"; + pad_drivers : 1; + bond_pads : 1; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 0; + when : "pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 438.851; + when : "pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 0; + when : "!pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 970.853; + when : "!pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 0; + related_pg_pin : iovdd; + } + leakage_power () { + value : 704.852; + related_pg_pin : vdd; + } + pin (p2c) { + direction : "output"; + output_voltage : "core"; + function : "pad"; + related_ground_pin : vss; + related_power_pin : vdd; + max_capacitance : 1.12616; + timing () { + related_pin : "pad"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0743031, 0.0881505, 0.113154, 0.137112, 0.160716, 0.18431", \ + "0.0743041, 0.0881515, 0.113155, 0.137113, 0.160717, 0.184311", \ + "0.0743051, 0.0881525, 0.113156, 0.137114, 0.160718, 0.184312", \ + "0.0743061, 0.0881535, 0.113157, 0.137115, 0.160719, 0.184313", \ + "0.0743071, 0.0881545, 0.113158, 0.137116, 0.16072, 0.184314", \ + "0.0743081, 0.0881555, 0.113159, 0.137117, 0.160721, 0.184315", \ + "0.0743091, 0.0881565, 0.11316, 0.137118, 0.160722, 0.184316" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0493227, 0.074015, 0.12398, 0.17487, 0.226149, 0.277749", \ + "0.0530089, 0.0776562, 0.128131, 0.178856, 0.229789, 0.281202", \ + "0.0600543, 0.0838391, 0.132178, 0.182391, 0.233466, 0.285341", \ + "0.0632836, 0.0865556, 0.134638, 0.18391, 0.23456, 0.285862", \ + "0.078088, 0.100898, 0.146529, 0.193463, 0.24311, 0.292278", \ + "0.101867, 0.124933, 0.168215, 0.212886, 0.258324, 0.306096", \ + "0.120601, 0.143864, 0.186884, 0.229659, 0.273972, 0.320252" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.277841, 0.295545, 0.324105, 0.348353, 0.370372, 0.392183", \ + "0.32762, 0.34537, 0.37388, 0.398207, 0.420596, 0.441328", \ + "0.445042, 0.462635, 0.491271, 0.515572, 0.537954, 0.558695", \ + "0.504037, 0.521589, 0.550134, 0.574375, 0.596875, 0.618174", \ + "0.803972, 0.821222, 0.849637, 0.87363, 0.893796, 0.914307", \ + "1.37905, 1.39855, 1.42959, 1.45518, 1.47846, 1.49968", \ + "1.87311, 1.89418, 1.9276, 1.95515, 1.97952, 2.00204" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0822259, 0.101112, 0.135707, 0.169761, 0.203442, 0.238604", \ + "0.0822269, 0.101113, 0.135708, 0.169809, 0.203979, 0.238605", \ + "0.0822279, 0.101114, 0.135709, 0.16981, 0.20398, 0.238606", \ + "0.0822289, 0.101115, 0.13571, 0.169811, 0.203981, 0.238607", \ + "0.085223, 0.104198, 0.138162, 0.171823, 0.206242, 0.240212", \ + "0.115475, 0.13309, 0.165545, 0.196723, 0.22812, 0.260102", \ + "0.139961, 0.157332, 0.189456, 0.220135, 0.250238, 0.28159" \ + ); + } + } + internal_power () { + related_pin : "pad"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "7.80105e-09, 7.80118e-09, 7.80067e-09, 7.80079e-09, 7.8004e-09, 7.80109e-09", \ + "1.5152e-08, 1.51512e-08, 1.51516e-08, 1.51518e-08, 1.51513e-08, 1.51512e-08", \ + "2.98543e-08, 2.98544e-08, 2.9855e-08, 2.98525e-08, 2.98537e-08, 2.98536e-08", \ + "3.72057e-08, 3.72044e-08, 3.72049e-08, 3.72045e-08, 3.72035e-08, 3.72039e-08", \ + "7.39611e-08, 7.39609e-08, 7.39587e-08, 7.39606e-08, 7.39599e-08, 7.39597e-08", \ + "1.47469e-07, 1.47469e-07, 1.4747e-07, 1.4747e-07, 1.47469e-07, 1.47469e-07", \ + "2.14849e-07, 2.14852e-07, 2.14851e-07, 2.14851e-07, 2.14851e-07, 2.14847e-07" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "-7.80094e-09, -7.80092e-09, -7.80067e-09, -7.80079e-09, -7.8004e-09, -7.80109e-09", \ + "-1.5152e-08, -1.51512e-08, -1.51516e-08, -1.51518e-08, -1.51513e-08, -1.51512e-08", \ + "-2.98543e-08, -2.98543e-08, -2.98543e-08, -2.98525e-08, -2.98537e-08, -2.98536e-08", \ + "-3.72042e-08, -3.72041e-08, -3.72041e-08, -3.72041e-08, -3.72035e-08, -3.72039e-08", \ + "-7.3957e-08, -7.39573e-08, -7.3957e-08, -7.39573e-08, -7.39573e-08, -7.3957e-08", \ + "-1.47466e-07, -1.47465e-07, -1.47464e-07, -1.47465e-07, -1.47465e-07, -1.47465e-07", \ + "-2.14847e-07, -2.14847e-07, -2.14847e-07, -2.14847e-07, -2.14846e-07, -2.14846e-07" \ + ); + } + } + internal_power () { + related_pin : "pad"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.00854409, 0.0086649, 0.0087816, 0.00871847, 0.00831465, 0.00788056", \ + "0.00827277, 0.00856692, 0.00790425, 0.00774767, 0.00778335, 0.00718801", \ + "0.00812786, 0.00790936, 0.00741525, 0.00759137, 0.00697485, 0.00562531", \ + "0.0083658, 0.00744033, 0.0069156, 0.00698627, 0.00653085, 0.00547321", \ + "0.0106141, 0.0094087, 0.008088, 0.00615482, 0.0075633, 0.00627226", \ + "0.0171257, 0.0138553, 0.0115023, 0.0108144, 0.0078474, 0.00695206", \ + "0.0253885, 0.0200624, 0.0159117, 0.0137996, 0.0118915, 0.011994" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0790913, 0.0767583, 0.0757582, 0.0756418, 0.0756468, 0.0756288", \ + "0.0778027, 0.0754286, 0.0743639, 0.0741714, 0.0741093, 0.0741176", \ + "0.0771104, 0.0746989, 0.0735911, 0.0733404, 0.0732564, 0.0732622", \ + "0.0768612, 0.0744441, 0.0733151, 0.0730538, 0.0729879, 0.0729609", \ + "0.078927, 0.0761771, 0.0744785, 0.0736113, 0.0732115, 0.0729922", \ + "0.090442, 0.0846935, 0.0801309, 0.0784945, 0.0774758, 0.0767218", \ + "0.0994141, 0.0917749, 0.0853448, 0.0827356, 0.0812005, 0.0802106" \ + ); + } + } + } + pin (pad) { + direction : "input"; + is_pad : true; + input_voltage : "pad"; + fanout_load : 1; + related_ground_pin : iovss; + related_power_pin : iovdd; + max_transition : 3.5; + capacitance : 0.22075; + rise_capacitance : 0.223707; + rise_capacitance_range (0.196054, 0.242764); + fall_capacitance : 0.217793; + fall_capacitance_range (0.197273, 0.2312); + } + } + cell (sg13g2_IOPadInOut16mA) { + pad_cell : true; + area : 14400; + cell_footprint : "inout"; + pad_drivers : 1; + bond_pads : 1; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 527.669; + when : "!c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 4917.81; + when : "!c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 527.669; + when : "!c2p_en&c2p&!pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 6204.4; + when : "!c2p_en&c2p&!pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 4.74047; + when : "!c2p_en&!c2p&pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 4385.16; + when : "!c2p_en&!c2p&pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 4.74047; + when : "!c2p_en&c2p&pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 5672.74; + when : "!c2p_en&c2p&pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 8.09409; + when : "c2p_en&c2p&pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 6137.78; + when : "c2p_en&c2p&pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 8.09409; + when : "c2p_en&c2p&pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 6137.71; + when : "c2p_en&c2p&pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 525.668; + when : "c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 5663.37; + when : "c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 525.668; + when : "c2p_en&!c2p&!pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 5663.39; + when : "c2p_en&!c2p&!pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 266.543; + related_pg_pin : iovdd; + } + leakage_power () { + value : 5597.79; + related_pg_pin : vdd; + } + pin (pad) { + direction : "inout"; + is_pad : true; + function : "c2p"; + three_state : "c2p_en'"; + drive_current : 16; + output_voltage : "pad"; + input_voltage : "pad"; + related_ground_pin : iovss; + related_power_pin : iovdd; + max_capacitance : 4.2026; + capacitance : 0.265223; + rise_capacitance : 0.265258; + rise_capacitance_range (0.23594, 0.28545); + fall_capacitance : 0.265188; + fall_capacitance_range (0.242988, 0.279673); + timing () { + related_pin : "c2p"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.42673, 1.58441, 1.71807, 1.84111, 2.18443, 2.5151", \ + "1.43846, 1.5962, 1.72975, 1.85272, 2.19608, 2.52683", \ + "1.4453, 1.60295, 1.73648, 1.8595, 2.20279, 2.53304", \ + "1.45398, 1.61173, 1.74523, 1.8682, 2.21144, 2.54212", \ + "1.46431, 1.62186, 1.75548, 1.87848, 2.22175, 2.5524", \ + "1.47012, 1.62793, 1.76169, 1.88429, 2.22792, 2.55884", \ + "1.47013, 1.62794, 1.7617, 1.8843, 2.22793, 2.55885" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.519559, 0.737029, 0.946793, 1.15719, 1.79882, 2.45461", \ + "0.51956, 0.73703, 0.946794, 1.1572, 1.79883, 2.45462", \ + "0.519561, 0.737031, 0.946795, 1.15721, 1.79884, 2.45463", \ + "0.519562, 0.737032, 0.946796, 1.15722, 1.79885, 2.45464", \ + "0.519563, 0.737033, 0.946797, 1.1573, 1.79886, 2.45465", \ + "0.519916, 0.73715, 0.946798, 1.15731, 1.79887, 2.45466", \ + "0.521444, 0.737751, 0.94702, 1.15732, 1.79888, 2.45467" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.01423, 1.13834, 1.25075, 1.35637, 1.66357, 1.97213", \ + "1.03037, 1.15444, 1.26661, 1.37205, 1.67954, 1.98739", \ + "1.04455, 1.16877, 1.28057, 1.38667, 1.69288, 2.00027", \ + "1.07377, 1.19786, 1.30972, 1.41553, 1.72198, 2.02982", \ + "1.11904, 1.243, 1.35502, 1.46082, 1.76738, 2.07524", \ + "1.19669, 1.3209, 1.43253, 1.53848, 1.84493, 2.15311", \ + "1.33259, 1.45725, 1.56905, 1.67376, 1.98225, 2.29042" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.601891, 0.76173, 0.9282, 1.10742, 1.67501, 2.26617", \ + "0.60568, 0.764967, 0.931952, 1.11084, 1.67672, 2.2677", \ + "0.608218, 0.767242, 0.933991, 1.11168, 1.6776, 2.26771", \ + "0.610135, 0.767273, 0.935898, 1.11211, 1.6795, 2.26906", \ + "0.610136, 0.768016, 0.935899, 1.11212, 1.67951, 2.26907", \ + "0.610137, 0.768017, 0.9359, 1.11213, 1.67952, 2.26908", \ + "0.610138, 0.768018, 0.935901, 1.11214, 1.67953, 2.26909" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : negative_unate; + timing_type : three_state_disable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.00927, 1.00928, 1.00929, 1.0093, 1.00931, 1.00932", \ + "1.03638, 1.03639, 1.0364, 1.03641, 1.03642, 1.03643", \ + "1.04622, 1.04623, 1.04624, 1.04625, 1.04626, 1.04627", \ + "1.06721, 1.06722, 1.06723, 1.06724, 1.06725, 1.06726", \ + "1.09507, 1.09508, 1.09509, 1.0951, 1.09511, 1.09512", \ + "1.14565, 1.14566, 1.14567, 1.14568, 1.14569, 1.1457", \ + "1.2225, 1.22251, 1.22252, 1.22253, 1.22254, 1.22255" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.00927, 1.00928, 1.00929, 1.0093, 1.00931, 1.00932", \ + "1.03638, 1.03639, 1.0364, 1.03641, 1.03642, 1.03643", \ + "1.04622, 1.04623, 1.04624, 1.04625, 1.04626, 1.04627", \ + "1.06721, 1.06722, 1.06723, 1.06724, 1.06725, 1.06726", \ + "1.09507, 1.09508, 1.09509, 1.0951, 1.09511, 1.09512", \ + "1.14565, 1.14566, 1.14567, 1.14568, 1.14569, 1.1457", \ + "1.2225, 1.22251, 1.22252, 1.22253, 1.22254, 1.22255" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.00731, 1.00732, 1.00733, 1.00734, 1.00735, 1.00736", \ + "1.02487, 1.02488, 1.02489, 1.0249, 1.02491, 1.02492", \ + "1.0353, 1.03531, 1.03532, 1.03533, 1.03534, 1.03535", \ + "1.06606, 1.06607, 1.06608, 1.06609, 1.0661, 1.06611", \ + "1.11525, 1.11526, 1.11527, 1.11528, 1.11529, 1.1153", \ + "1.1749, 1.17491, 1.17492, 1.17493, 1.17494, 1.17495", \ + "1.28817, 1.28818, 1.28819, 1.2882, 1.28821, 1.28822" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.00731, 1.00732, 1.00733, 1.00734, 1.00735, 1.00736", \ + "1.02487, 1.02488, 1.02489, 1.0249, 1.02491, 1.02492", \ + "1.0353, 1.03531, 1.03532, 1.03533, 1.03534, 1.03535", \ + "1.06606, 1.06607, 1.06608, 1.06609, 1.0661, 1.06611", \ + "1.11525, 1.11526, 1.11527, 1.11528, 1.11529, 1.1153", \ + "1.1749, 1.17491, 1.17492, 1.17493, 1.17494, 1.17495", \ + "1.28817, 1.28818, 1.28819, 1.2882, 1.28821, 1.28822" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : positive_unate; + timing_type : three_state_enable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.42241, 1.58815, 1.72769, 1.85719, 2.21846, 2.56743", \ + "1.43485, 1.60019, 1.74046, 1.86846, 2.23121, 2.5808", \ + "1.44325, 1.6086, 1.74855, 1.87756, 2.23935, 2.58894", \ + "1.45502, 1.6203, 1.76065, 1.88879, 2.2517, 2.60104", \ + "1.46934, 1.63462, 1.77509, 1.90316, 2.2645, 2.61552", \ + "1.48104, 1.64662, 1.78682, 1.91553, 2.27757, 2.6269", \ + "1.48793, 1.65353, 1.79305, 1.92158, 2.28197, 2.63066" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.516521, 0.726142, 0.932003, 1.1412, 1.78208, 2.43918", \ + "0.516522, 0.726143, 0.932384, 1.14121, 1.78209, 2.43958", \ + "0.516523, 0.726144, 0.932385, 1.14122, 1.7821, 2.43985", \ + "0.516524, 0.726145, 0.932386, 1.14123, 1.7826, 2.43993", \ + "0.516525, 0.726146, 0.932387, 1.14124, 1.78261, 2.43994", \ + "0.516526, 0.726147, 0.932388, 1.14125, 1.78262, 2.43995", \ + "0.516613, 0.726407, 0.932389, 1.14126, 1.78263, 2.43996" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.846163, 0.992337, 1.12365, 1.24534, 1.59826, 1.94518", \ + "0.859589, 1.00666, 1.13693, 1.25862, 1.61142, 1.95844", \ + "0.864792, 1.01108, 1.14233, 1.26401, 1.61695, 1.96377", \ + "0.874493, 1.02104, 1.1516, 1.27336, 1.62623, 1.97333", \ + "0.881336, 1.02828, 1.15867, 1.28042, 1.6333, 1.98031", \ + "0.884805, 1.03127, 1.16191, 1.28425, 1.63683, 1.98269", \ + "0.884806, 1.03128, 1.16192, 1.28426, 1.63684, 1.9827" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.405703, 0.602439, 0.799512, 0.996226, 1.59705, 2.20943", \ + "0.405704, 0.603066, 0.799513, 0.996227, 1.59796, 2.21034", \ + "0.405705, 0.603067, 0.799536, 0.996229, 1.59797, 2.21035", \ + "0.405706, 0.603068, 0.799537, 0.99623, 1.59798, 2.21036", \ + "0.405731, 0.603069, 0.799538, 0.996231, 1.59799, 2.21037", \ + "0.405732, 0.60307, 0.799539, 0.996232, 1.60016, 2.21038", \ + "0.405808, 0.603077, 0.800678, 0.998368, 1.60017, 2.21059" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "6.38991, 6.33054, 6.29353, 6.27059, 6.17423, 6.08794", \ + "6.39246, 6.33438, 6.29693, 6.27182, 6.15351, 6.0987", \ + "6.39525, 6.33309, 6.29142, 6.27106, 6.16876, 6.00511", \ + "6.38895, 6.32931, 6.28475, 6.27386, 6.1775, 6.08989", \ + "6.38579, 6.32393, 6.28508, 6.27168, 6.16932, 6.07771", \ + "6.36459, 6.31033, 6.28086, 6.2506, 6.15717, 6.09576", \ + "6.34863, 6.28356, 6.25347, 6.21624, 6.07877, 5.99419" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "13.9064, 12.3121, 11.2503, 10.4653, 9.01147, 8.15256", \ + "14.0895, 12.4745, 11.38, 10.6053, 9.12083, 8.2461", \ + "14.2181, 12.588, 11.4888, 10.7075, 9.1767, 8.30023", \ + "14.3177, 12.6705, 11.5712, 10.7513, 9.24396, 8.34292", \ + "14.2687, 12.6314, 11.5322, 10.7171, 9.21609, 8.31698", \ + "14.0835, 12.4718, 11.3969, 10.6016, 9.12073, 8.24409", \ + "13.5032, 11.9627, 10.9197, 10.175, 8.77514, 7.96851" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.30044, 4.52128, 6.73072, 8.9339, 15.5531, 21.6286", \ + "2.30068, 4.5164, 6.7269, 8.93517, 15.57, 21.4973", \ + "2.30497, 4.52056, 6.73674, 8.9428, 15.5618, 21.593", \ + "2.32364, 4.53815, 6.75332, 8.96233, 15.5791, 21.5645", \ + "2.36368, 4.58026, 6.78556, 8.99644, 15.6316, 21.5195", \ + "2.45835, 4.67426, 6.87808, 9.09883, 15.7169, 21.33", \ + "2.65227, 4.86927, 7.07418, 9.28533, 15.8973, 21.1857" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.262183, 0.261625, 0.261269, 0.261148, 0.26075, 0.260859", \ + "0.261879, 0.26136, 0.261157, 0.260927, 0.260706, 0.260668", \ + "0.267981, 0.267485, 0.267254, 0.266942, 0.266614, 0.266775", \ + "0.286868, 0.286418, 0.286128, 0.285771, 0.285332, 0.285742", \ + "0.329355, 0.328786, 0.328576, 0.32815, 0.32775, 0.327876", \ + "0.421972, 0.421534, 0.421127, 0.420916, 0.420369, 0.420328", \ + "0.61495, 0.614893, 0.613757, 0.613878, 0.613009, 0.613174" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "6.15738, 6.42235, 6.69603, 6.98983, 7.86083, 8.75856", \ + "6.15728, 6.42214, 6.6928, 6.9695, 7.85918, 8.8114", \ + "6.1557, 6.4163, 6.69019, 6.97178, 7.85232, 8.80793", \ + "6.1547, 6.4178, 6.6925, 6.98168, 7.89179, 8.83202", \ + "6.15335, 6.41727, 6.69656, 6.97947, 7.83582, 8.82922", \ + "6.15585, 6.422, 6.70352, 6.98891, 7.89667, 8.83163", \ + "6.15606, 6.4089, 6.6788, 6.93944, 7.73962, 8.57746" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.42454, 2.42216, 2.42024, 2.4175, 2.41539, 2.4151", \ + "2.42591, 2.42491, 2.42291, 2.42054, 2.41832, 2.41641", \ + "2.42463, 2.42196, 2.42037, 2.41764, 2.41549, 2.41457", \ + "2.42552, 2.4235, 2.42037, 2.41779, 2.41584, 2.4157", \ + "2.42303, 2.4218, 2.41852, 2.41592, 2.41384, 2.41345", \ + "2.42357, 2.42313, 2.41973, 2.4204, 2.41659, 2.41939", \ + "2.4253, 2.4243, 2.4209, 2.41941, 2.41671, 2.41841" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.25851, 4.47972, 6.68733, 8.89958, 15.528, 21.6434", \ + "2.26069, 4.46671, 6.69385, 8.90254, 15.5624, 21.4975", \ + "2.26821, 4.47567, 6.69846, 8.91982, 15.5355, 21.6097", \ + "2.28925, 4.50538, 6.72421, 8.92114, 15.5645, 21.5884", \ + "2.33765, 4.55333, 6.77121, 8.98003, 15.5931, 21.4212", \ + "2.43933, 4.65453, 6.87287, 9.08043, 15.7054, 21.4652", \ + "2.63591, 4.85545, 7.07214, 9.282, 15.8965, 21.1868" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.132531, 0.132077, 0.1319, 0.131535, 0.131102, 0.131294", \ + "0.133476, 0.133187, 0.132692, 0.132516, 0.132238, 0.132434", \ + "0.137319, 0.136785, 0.136684, 0.136319, 0.135884, 0.136215", \ + "0.148879, 0.148401, 0.148213, 0.147854, 0.147415, 0.148", \ + "0.172972, 0.172618, 0.172286, 0.171919, 0.171528, 0.171889", \ + "0.22506, 0.224392, 0.22426, 0.223924, 0.22361, 0.223667", \ + "0.332368, 0.331652, 0.331382, 0.330932, 0.330645, 0.330533" \ + ); + } + } + } + pin (p2c) { + direction : "output"; + output_voltage : "core"; + function : "pad"; + related_ground_pin : vss; + related_power_pin : vdd; + max_capacitance : 1.12021; + timing () { + related_pin : "pad"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0744964, 0.0882772, 0.113327, 0.137238, 0.160877, 0.184405", \ + "0.0744974, 0.0882782, 0.113328, 0.137239, 0.160878, 0.184406", \ + "0.0744984, 0.0882792, 0.113329, 0.13724, 0.160879, 0.184407", \ + "0.0744994, 0.0882802, 0.11333, 0.137241, 0.16088, 0.184408", \ + "0.0745004, 0.0882812, 0.113331, 0.137242, 0.160881, 0.184409", \ + "0.0745014, 0.0882822, 0.113332, 0.137243, 0.160882, 0.18441", \ + "0.0745024, 0.0882832, 0.113333, 0.137244, 0.160883, 0.184411" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0492924, 0.0740448, 0.124053, 0.174952, 0.226261, 0.277826", \ + "0.0530835, 0.0774355, 0.128053, 0.178668, 0.229784, 0.281211", \ + "0.060171, 0.0838215, 0.132305, 0.182191, 0.233292, 0.285241", \ + "0.0633475, 0.0864245, 0.134316, 0.183858, 0.234442, 0.28565", \ + "0.0780477, 0.100637, 0.146471, 0.193723, 0.24214, 0.291673", \ + "0.101788, 0.124854, 0.168313, 0.212384, 0.259223, 0.305631", \ + "0.120544, 0.143698, 0.186648, 0.229586, 0.273936, 0.318745" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.278055, 0.295587, 0.324085, 0.34826, 0.370521, 0.391135", \ + "0.328421, 0.345903, 0.374333, 0.398534, 0.420284, 0.441877", \ + "0.445192, 0.462738, 0.491093, 0.515169, 0.537494, 0.558024", \ + "0.50446, 0.521966, 0.55032, 0.574563, 0.596747, 0.617872", \ + "0.805081, 0.82196, 0.850289, 0.87367, 0.895523, 0.917012", \ + "1.37593, 1.39528, 1.42605, 1.45171, 1.47489, 1.49694", \ + "1.87129, 1.89221, 1.9256, 1.95303, 1.97752, 2.00009" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0820322, 0.100704, 0.135065, 0.16883, 0.202724, 0.236292", \ + "0.0820332, 0.100705, 0.135156, 0.168831, 0.202725, 0.23673", \ + "0.0820342, 0.100706, 0.135157, 0.168832, 0.202726, 0.236731", \ + "0.0820352, 0.100707, 0.135158, 0.168833, 0.202727, 0.236732", \ + "0.084845, 0.103285, 0.137267, 0.171689, 0.205082, 0.239063", \ + "0.116342, 0.13387, 0.166053, 0.196741, 0.227803, 0.259842", \ + "0.140295, 0.157552, 0.189414, 0.21976, 0.249827, 0.280899" \ + ); + } + } + internal_power () { + related_pin : "pad"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "-0.621895, -0.624691, -0.624184, -0.625104, -0.623071, -0.624616", \ + "-0.625187, -0.625191, -0.621999, -0.621871, -0.621458, -0.625059", \ + "-0.624784, -0.623747, -0.624831, -0.62303, -0.624786, -0.62481", \ + "-0.625228, -0.625239, -0.625312, -0.625269, -0.622292, -0.625202", \ + "-0.622472, -0.622848, -0.622541, -0.623624, -0.622782, -0.622518", \ + "-0.623376, -0.623657, -0.622363, -0.622607, -0.622415, -0.622626", \ + "-0.62377, -0.623538, -0.623803, -0.623542, -0.622135, -0.622699" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.625066, 0.625072, 0.625087, 0.625104, 0.625129, 0.625172", \ + "0.625187, 0.625191, 0.625208, 0.625229, 0.625257, 0.625286", \ + "0.624784, 0.624775, 0.624831, 0.624775, 0.624786, 0.62481", \ + "0.625228, 0.625239, 0.625312, 0.625269, 0.625287, 0.625311", \ + "0.622472, 0.622848, 0.622541, 0.623624, 0.622782, 0.622518", \ + "0.623376, 0.623657, 0.622363, 0.622607, 0.622415, 0.622626", \ + "0.62377, 0.623538, 0.623803, 0.623542, 0.623069, 0.622699" \ + ); + } + } + internal_power () { + related_pin : "pad"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.00873471, 0.00862741, 0.0086679, 0.00840857, 0.00829815, 0.00773896", \ + "0.00842443, 0.00823078, 0.0078282, 0.00765662, 0.00753405, 0.00724426", \ + "0.00848385, 0.0081496, 0.00821235, 0.00754112, 0.00669855, 0.00570166", \ + "0.008673, 0.00755296, 0.0068355, 0.00702617, 0.0063318, 0.00547471", \ + "0.0111104, 0.00960726, 0.0082371, 0.00720407, 0.0059187, 0.00555871", \ + "0.0174496, 0.0141407, 0.0120484, 0.0107234, 0.0099753, 0.00678541", \ + "0.0258166, 0.0205507, 0.0163371, 0.0145187, 0.0127819, 0.0108659" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0824702, 0.0801208, 0.0791405, 0.0790244, 0.078999, 0.0790107", \ + "0.0812974, 0.0788977, 0.0778335, 0.0776488, 0.0775835, 0.0775861", \ + "0.0803242, 0.07799, 0.0768467, 0.0766007, 0.0765383, 0.0765307", \ + "0.0802357, 0.0778104, 0.0766423, 0.0763878, 0.0763058, 0.0762684", \ + "0.0820423, 0.0793056, 0.0778572, 0.0778116, 0.0775747, 0.0772455", \ + "0.0944156, 0.0893156, 0.0844365, 0.0824708, 0.0812852, 0.0805545", \ + "0.102313, 0.094603, 0.0880789, 0.0854516, 0.0839526, 0.0829617" \ + ); + } + } + } + pin (c2p) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.016; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0293079; + rise_capacitance : 0.0295257; + rise_capacitance_range (0.0234308, 0.0344181); + fall_capacitance : 0.0290901; + fall_capacitance_range (0.024094, 0.0317942); + internal_power () { + when : "(!c2p_en * pad * p2c)"; + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-8.03063e-06, -7.08716e-06, -4.07263e-06, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "8.03063e-06, 7.08716e-06, 4.07263e-06, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + when : "(!c2p_en * pad * p2c)"; + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0267609, -0.0277021, -0.0279364, -0.0282798, -0.0283341, -0.0285762, -0.0286453" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0356071, 0.0352665, 0.0349902, 0.0350389, 0.0347358, 0.0349056, 0.0349557" \ + ); + } + } + internal_power () { + when : "(!c2p_en * !pad * !p2c)"; + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-7.97995e-06, -7.07224e-06, -4.078e-06, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "7.97995e-06, 7.07224e-06, 4.078e-06, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + when : "(!c2p_en * !pad * !p2c)"; + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0267589, -0.0277011, -0.027935, -0.0282789, -0.028334, -0.0285763, -0.0286453" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0356053, 0.035265, 0.0349896, 0.0350386, 0.0347354, 0.0349054, 0.0349557" \ + ); + } + } + internal_power () { + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-7.97995e-06, -7.07224e-06, -4.078e-06, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "7.97995e-06, 7.07224e-06, 4.078e-06, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0267589, -0.0277011, -0.027935, -0.0282789, -0.028334, -0.0285763, -0.0286453" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0356053, 0.035265, 0.0349896, 0.0350386, 0.0347354, 0.0349054, 0.0349557" \ + ); + } + } + } + pin (c2p_en) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.011; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0264717; + rise_capacitance : 0.0276329; + rise_capacitance_range (0.0224667, 0.0347968); + fall_capacitance : 0.0253104; + fall_capacitance_range (0.0216284, 0.0302295); + internal_power () { + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "1.62267, 1.6222, 1.62242, 1.6234, 1.61947, 1.62721, 1.62467" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.269432, 0.269004, 0.268404, 0.267374, 0.264914, 0.265183, 0.265175" \ + ); + } + } + internal_power () { + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0527279, 0.0540193, 0.0577159, 0.0689297, 0.09362, 0.145685, 0.25642" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.127561, 0.130667, 0.135508, 0.146199, 0.171527, 0.223577, 0.335977" \ + ); + } + } + } + } + cell (sg13g2_IOPadInOut30mA) { + pad_cell : true; + area : 14400; + cell_footprint : "inout"; + pad_drivers : 1; + bond_pads : 1; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 825.168; + when : "!c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 4917.22; + when : "!c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 825.168; + when : "!c2p_en&c2p&!pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 6203.7; + when : "!c2p_en&c2p&!pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 0; + when : "!c2p_en&!c2p&pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 4384.7; + when : "!c2p_en&!c2p&pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 0; + when : "!c2p_en&c2p&pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 5672.29; + when : "!c2p_en&c2p&pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 0; + when : "c2p_en&c2p&pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 6137.2; + when : "c2p_en&c2p&pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 0; + when : "c2p_en&c2p&pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 6137.26; + when : "c2p_en&c2p&pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 823.195; + when : "c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 5662.79; + when : "c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 823.195; + when : "c2p_en&!c2p&!pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 5662.78; + when : "c2p_en&!c2p&!pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 412.091; + related_pg_pin : iovdd; + } + leakage_power () { + value : 5597.24; + related_pg_pin : vdd; + } + pin (pad) { + direction : "inout"; + is_pad : true; + function : "c2p"; + three_state : "c2p_en'"; + drive_current : 30; + output_voltage : "pad"; + input_voltage : "pad"; + related_ground_pin : iovss; + related_power_pin : iovdd; + max_capacitance : 4.70188; + capacitance : 0.354281; + rise_capacitance : 0.351601; + rise_capacitance_range (0.320385, 0.373507); + fall_capacitance : 0.356961; + fall_capacitance_range (0.333218, 0.373057); + timing () { + related_pin : "c2p"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.63474, 1.77529, 1.88989, 1.98943, 2.24106, 2.45708", \ + "1.64976, 1.78945, 1.90381, 2.0035, 2.25495, 2.47119", \ + "1.65411, 1.79419, 1.90872, 2.00838, 2.25969, 2.47581", \ + "1.6639, 1.80404, 1.91845, 2.01808, 2.26934, 2.48565", \ + "1.67368, 1.81378, 1.92835, 2.02797, 2.27936, 2.49559", \ + "1.67579, 1.81629, 1.93099, 2.03059, 2.28238, 2.49832", \ + "1.6758, 1.8163, 1.931, 2.0306, 2.28239, 2.49833" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.498929, 0.664607, 0.804588, 0.93111, 1.28353, 1.62262", \ + "0.49893, 0.664608, 0.804589, 0.931307, 1.28378, 1.62267", \ + "0.498931, 0.664609, 0.80459, 0.931308, 1.28379, 1.62268", \ + "0.498932, 0.66461, 0.804591, 0.931309, 1.2838, 1.62271", \ + "0.498933, 0.664611, 0.804592, 0.93131, 1.28381, 1.62297", \ + "0.498934, 0.664958, 0.804593, 0.931548, 1.28399, 1.62298", \ + "0.501744, 0.666223, 0.806003, 0.934129, 1.28528, 1.62347" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.2936, 1.37831, 1.45503, 1.52799, 1.72635, 1.90631", \ + "1.30994, 1.39447, 1.47238, 1.54356, 1.74225, 1.92326", \ + "1.32459, 1.4087, 1.48636, 1.55881, 1.75551, 1.93655", \ + "1.35365, 1.4382, 1.51472, 1.58772, 1.78622, 1.96545", \ + "1.39882, 1.48336, 1.56048, 1.63302, 1.83151, 2.01047", \ + "1.47645, 1.56059, 1.63789, 1.71071, 1.9077, 2.08854", \ + "1.61119, 1.6959, 1.77423, 1.84814, 2.04639, 2.22706" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.924807, 0.983333, 1.06162, 1.14066, 1.38625, 1.64496", \ + "0.930081, 0.986618, 1.06194, 1.14528, 1.38981, 1.64904", \ + "0.933772, 0.990708, 1.068, 1.14529, 1.39147, 1.65137", \ + "0.936563, 0.992628, 1.07091, 1.14965, 1.39424, 1.65138", \ + "0.936564, 0.992629, 1.07092, 1.14966, 1.39425, 1.65139", \ + "0.936565, 0.99263, 1.07093, 1.14967, 1.39426, 1.6514", \ + "0.936566, 0.992631, 1.07094, 1.14968, 1.39427, 1.65141" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : negative_unate; + timing_type : three_state_disable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.20519, 1.2052, 1.20521, 1.20522, 1.20523, 1.20524", \ + "1.22731, 1.22732, 1.22733, 1.22734, 1.22735, 1.22736", \ + "1.23622, 1.23623, 1.23624, 1.23625, 1.23626, 1.23627", \ + "1.25781, 1.25782, 1.25782, 1.25783, 1.25784, 1.25785", \ + "1.28987, 1.28988, 1.28989, 1.2899, 1.28991, 1.28992", \ + "1.33417, 1.33418, 1.33419, 1.3342, 1.33421, 1.33422", \ + "1.42208, 1.42209, 1.4221, 1.42211, 1.42212, 1.42213" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.20519, 1.2052, 1.20521, 1.20522, 1.20523, 1.20524", \ + "1.22731, 1.22732, 1.22733, 1.22734, 1.22735, 1.22736", \ + "1.23622, 1.23623, 1.23624, 1.23625, 1.23626, 1.23627", \ + "1.25781, 1.25782, 1.25782, 1.25783, 1.25784, 1.25785", \ + "1.28987, 1.28988, 1.28989, 1.2899, 1.28991, 1.28992", \ + "1.33417, 1.33418, 1.33419, 1.3342, 1.33421, 1.33422", \ + "1.42208, 1.42209, 1.4221, 1.42211, 1.42212, 1.42213" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.59956, 1.59957, 1.59958, 1.59959, 1.5996, 1.59961", \ + "1.6207, 1.62071, 1.62072, 1.62073, 1.62074, 1.62075", \ + "1.63565, 1.63566, 1.63567, 1.63568, 1.63569, 1.6357", \ + "1.65705, 1.65706, 1.65707, 1.65708, 1.65709, 1.6571", \ + "1.69885, 1.69886, 1.69887, 1.69888, 1.69889, 1.6989", \ + "1.77534, 1.77535, 1.77536, 1.77537, 1.77538, 1.77539", \ + "1.85609, 1.8561, 1.85611, 1.85612, 1.85613, 1.85614" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.59956, 1.59957, 1.59958, 1.59959, 1.5996, 1.59961", \ + "1.6207, 1.62071, 1.62072, 1.62073, 1.62074, 1.62075", \ + "1.63565, 1.63566, 1.63567, 1.63568, 1.63569, 1.6357", \ + "1.65705, 1.65706, 1.65707, 1.65708, 1.65709, 1.6571", \ + "1.69885, 1.69886, 1.69887, 1.69888, 1.69889, 1.6989", \ + "1.77534, 1.77535, 1.77536, 1.77537, 1.77538, 1.77539", \ + "1.85609, 1.8561, 1.85611, 1.85612, 1.85613, 1.85614" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : positive_unate; + timing_type : three_state_enable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.61077, 1.76695, 1.88959, 1.99468, 2.25846, 2.48669", \ + "1.62386, 1.78005, 1.90269, 2.00783, 2.27152, 2.4998", \ + "1.63169, 1.78787, 1.91063, 2.01568, 2.27941, 2.50588", \ + "1.64414, 1.80034, 1.92292, 2.02816, 2.29186, 2.51865", \ + "1.65761, 1.8137, 1.93645, 2.04162, 2.3052, 2.53167", \ + "1.6686, 1.82477, 1.94732, 2.05254, 2.31634, 2.54233", \ + "1.67677, 1.83226, 1.95466, 2.06097, 2.32413, 2.55087" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.520486, 0.666842, 0.795015, 0.914486, 1.25538, 1.59116", \ + "0.520487, 0.666843, 0.795016, 0.914487, 1.25548, 1.59117", \ + "0.520519, 0.666844, 0.795017, 0.914662, 1.25577, 1.59118", \ + "0.52052, 0.666845, 0.795018, 0.914663, 1.25578, 1.59119", \ + "0.520521, 0.666905, 0.795019, 0.914664, 1.25579, 1.5912", \ + "0.520522, 0.666906, 0.79502, 0.914665, 1.2558, 1.59121", \ + "0.520523, 0.666907, 0.795021, 0.914666, 1.25581, 1.59122" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.904037, 1.02217, 1.11916, 1.20614, 1.43539, 1.64015", \ + "0.916746, 1.03483, 1.13188, 1.21861, 1.44824, 1.65305", \ + "0.922676, 1.04085, 1.13783, 1.22485, 1.45407, 1.65882", \ + "0.932223, 1.05038, 1.14745, 1.23447, 1.46376, 1.66852", \ + "0.939137, 1.05726, 1.1558, 1.24164, 1.47082, 1.67552", \ + "0.942639, 1.06154, 1.15883, 1.24517, 1.47426, 1.67905", \ + "0.94264, 1.06155, 1.15884, 1.24518, 1.47427, 1.67906" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.373891, 0.498091, 0.612257, 0.718143, 1.03561, 1.34815", \ + "0.374617, 0.498092, 0.612304, 0.719572, 1.03586, 1.34842", \ + "0.374618, 0.498093, 0.612305, 0.719573, 1.03587, 1.34843", \ + "0.374619, 0.498094, 0.612306, 0.719574, 1.03588, 1.34844", \ + "0.376246, 0.500904, 0.612307, 0.719575, 1.03589, 1.34845", \ + "0.376247, 0.500905, 0.612308, 0.721697, 1.03736, 1.34961", \ + "0.376511, 0.500906, 0.615386, 0.721698, 1.03737, 1.34962" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "10.2855, 10.0496, 9.93947, 9.85624, 9.71012, 9.57667", \ + "10.3381, 10.0764, 9.95587, 9.88277, 9.75322, 9.61016", \ + "10.312, 10.0651, 9.95075, 9.87878, 9.7487, 9.60095", \ + "10.3198, 10.0766, 9.94752, 9.88307, 9.74378, 9.60478", \ + "10.3097, 10.0632, 9.94089, 9.87538, 9.74203, 9.61937", \ + "10.2521, 10.015, 9.8965, 9.82978, 9.70923, 9.52238", \ + "10.1524, 9.89678, 9.84974, 9.68213, 9.62999, 9.49106" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "55.221, 51.8326, 49.0509, 46.6784, 41.0975, 37.2036", \ + "55.6378, 52.2547, 49.4258, 47.0286, 41.4414, 37.4296", \ + "55.9207, 52.5604, 49.7352, 47.2785, 41.7014, 37.6807", \ + "56.1508, 52.747, 49.9094, 47.5116, 41.839, 37.8855", \ + "56.0346, 52.6341, 49.8352, 47.407, 41.7406, 37.7648", \ + "55.5871, 52.2469, 49.4272, 46.9998, 41.4674, 37.476", \ + "54.2595, 50.97, 48.2524, 45.872, 40.4765, 36.5505" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.29806, 4.51335, 6.74148, 8.97362, 15.4305, 18.2858", \ + "2.29861, 4.51477, 6.7412, 8.96847, 15.3875, 18.2186", \ + "2.30357, 4.51794, 6.74859, 8.97988, 15.3909, 18.1806", \ + "2.32025, 4.53638, 6.76292, 8.99923, 15.406, 17.9912", \ + "2.36275, 4.57866, 6.80603, 9.04268, 15.3894, 17.8245", \ + "2.45702, 4.6725, 6.90409, 9.12679, 15.3863, 17.1068", \ + "2.65031, 4.86736, 7.0981, 9.32315, 15.4574, 16.0135" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.262411, 0.261779, 0.261446, 0.261128, 0.261018, 0.260223", \ + "0.262118, 0.261332, 0.26113, 0.260968, 0.260734, 0.260309", \ + "0.268243, 0.267463, 0.267081, 0.267013, 0.266811, 0.26609", \ + "0.287046, 0.286317, 0.286113, 0.285808, 0.285651, 0.284795", \ + "0.329609, 0.328809, 0.328546, 0.328281, 0.328071, 0.327143", \ + "0.422316, 0.421575, 0.421134, 0.420934, 0.420502, 0.419237", \ + "0.615182, 0.614424, 0.614317, 0.613726, 0.613539, 0.611148" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "9.33515, 9.62747, 9.93656, 10.2427, 11.1681, 12.1016", \ + "9.3342, 9.62808, 9.93683, 10.2304, 11.1855, 12.1023", \ + "9.33387, 9.62244, 9.93538, 10.2331, 11.1864, 12.0573", \ + "9.33194, 9.62695, 9.92422, 10.2399, 11.1872, 12.0459", \ + "9.32941, 9.61483, 9.9299, 10.2172, 11.1774, 12.0775", \ + "9.32684, 9.62218, 9.93029, 10.2243, 11.1757, 12.08", \ + "9.32387, 9.5794, 9.86419, 10.2275, 11.1356, 12.0499" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "4.08812, 4.08984, 4.09417, 4.09257, 4.09332, 4.0877", \ + "4.0894, 4.09021, 4.09455, 4.09362, 4.09326, 4.08764", \ + "4.08914, 4.09012, 4.09433, 4.09264, 4.09364, 4.08793", \ + "4.08915, 4.08993, 4.09495, 4.09329, 4.09398, 4.08842", \ + "4.09244, 4.09355, 4.09261, 4.09213, 4.09335, 4.08732", \ + "4.08798, 4.09188, 4.08954, 4.09272, 4.09089, 4.08532", \ + "4.09681, 4.0956, 4.10607, 4.09405, 4.09581, 4.09288" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.25597, 4.47407, 6.70505, 8.93902, 15.3651, 18.0961", \ + "2.25836, 4.47462, 6.70823, 8.92699, 15.3364, 17.989", \ + "2.26556, 4.48371, 6.71651, 8.93667, 15.3435, 17.8367", \ + "2.28733, 4.50567, 6.7344, 8.96481, 15.288, 17.8088", \ + "2.33513, 4.55351, 6.78326, 9.00179, 15.3363, 17.6308", \ + "2.43293, 4.65111, 6.88547, 9.1208, 15.3303, 17.068", \ + "2.63141, 4.84674, 7.08238, 9.31798, 15.3762, 15.525" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.132534, 0.132092, 0.131783, 0.131654, 0.131525, 0.128953", \ + "0.133543, 0.133053, 0.132771, 0.132443, 0.132385, 0.129849", \ + "0.137314, 0.136843, 0.136562, 0.136419, 0.136301, 0.133563", \ + "0.14885, 0.148389, 0.148098, 0.147952, 0.14781, 0.144914", \ + "0.172994, 0.172519, 0.172447, 0.172045, 0.171988, 0.168912", \ + "0.224905, 0.224719, 0.224243, 0.224083, 0.223651, 0.220025", \ + "0.332904, 0.332226, 0.331652, 0.331628, 0.33102, 0.325555" \ + ); + } + } + } + pin (p2c) { + direction : "output"; + output_voltage : "core"; + function : "pad"; + related_ground_pin : vss; + related_power_pin : vdd; + max_capacitance : 1.12098; + timing () { + related_pin : "pad"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0745593, 0.0883715, 0.113468, 0.13741, 0.161091, 0.184632", \ + "0.0745603, 0.0883725, 0.113469, 0.137411, 0.161092, 0.184633", \ + "0.0745613, 0.0883735, 0.11347, 0.137412, 0.161093, 0.184634", \ + "0.0745623, 0.0883745, 0.113471, 0.137413, 0.161094, 0.184635", \ + "0.0745633, 0.0883755, 0.113472, 0.137414, 0.161095, 0.184636", \ + "0.0745643, 0.0883765, 0.113473, 0.137415, 0.161096, 0.184637", \ + "0.0745653, 0.0883775, 0.113474, 0.137416, 0.161097, 0.184638" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0493024, 0.0739504, 0.124008, 0.174893, 0.226287, 0.277794", \ + "0.0529649, 0.0776723, 0.128166, 0.178863, 0.229869, 0.281289", \ + "0.0602382, 0.0837364, 0.132319, 0.182215, 0.233336, 0.285302", \ + "0.0633293, 0.0865874, 0.134395, 0.183898, 0.234569, 0.285748", \ + "0.0780577, 0.10092, 0.146465, 0.193823, 0.242178, 0.291668", \ + "0.101791, 0.124858, 0.168317, 0.212846, 0.25923, 0.305642", \ + "0.120553, 0.143708, 0.187113, 0.229125, 0.273946, 0.319073" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.277678, 0.295317, 0.323704, 0.347873, 0.370132, 0.391302", \ + "0.328252, 0.345883, 0.374008, 0.398107, 0.420633, 0.441797", \ + "0.444074, 0.461597, 0.489712, 0.51379, 0.535892, 0.557538", \ + "0.50495, 0.52246, 0.550718, 0.574964, 0.596805, 0.617895", \ + "0.804509, 0.821509, 0.849793, 0.873094, 0.895103, 0.915936", \ + "1.37799, 1.3974, 1.42825, 1.45388, 1.47694, 1.49857", \ + "1.87199, 1.89299, 1.92626, 1.95382, 1.97818, 2.00076" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0820997, 0.100782, 0.135085, 0.168791, 0.202765, 0.236694", \ + "0.0821007, 0.100783, 0.135086, 0.168792, 0.202766, 0.236743", \ + "0.0821017, 0.100784, 0.135087, 0.168793, 0.202767, 0.236744", \ + "0.0821027, 0.100785, 0.135088, 0.168794, 0.202768, 0.236745", \ + "0.085278, 0.103811, 0.137282, 0.171493, 0.206375, 0.238956", \ + "0.115813, 0.133196, 0.165428, 0.196382, 0.227921, 0.259046", \ + "0.140176, 0.157433, 0.189239, 0.219563, 0.249189, 0.279953" \ + ); + } + } + internal_power () { + related_pin : "pad"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "-1.18392, -1.18803, -1.18797, -1.18795, -1.18601, -1.18564", \ + "-1.18897, -1.18872, -1.18406, -1.18897, -1.18585, -1.18911", \ + "-1.18872, -1.18873, -1.18871, -1.18471, -1.18874, -1.18876", \ + "-1.18848, -1.18848, -1.18855, -1.18851, -1.18855, -1.18853", \ + "-1.18432, -1.18453, -1.18349, -1.1856, -1.18691, -1.18299", \ + "-1.18398, -1.18383, -1.18347, -1.184, -1.18711, -1.18393", \ + "-1.17542, -1.17763, -1.17724, -1.17752, -1.18509, -1.17794" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "1.18806, 1.18803, 1.18797, 1.18802, 1.18804, 1.18807", \ + "1.18897, 1.18891, 1.18902, 1.18897, 1.18902, 1.18911", \ + "1.18872, 1.18873, 1.18871, 1.18875, 1.18874, 1.18876", \ + "1.18848, 1.18848, 1.18855, 1.18851, 1.18855, 1.18853", \ + "1.18432, 1.18453, 1.18349, 1.1856, 1.18691, 1.18299", \ + "1.18398, 1.18383, 1.18347, 1.184, 1.18711, 1.18393", \ + "1.18581, 1.18608, 1.18623, 1.18572, 1.18509, 1.1833" \ + ); + } + } + internal_power () { + related_pin : "pad"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.00850803, 0.00860116, 0.00878595, 0.00857657, 0.00863025, 0.00805531", \ + "0.00842793, 0.0086457, 0.0075726, 0.00769757, 0.007398, 0.00691606", \ + "0.00853384, 0.00785398, 0.00796365, 0.00749882, 0.00659355, 0.00558001", \ + "0.00865426, 0.00773883, 0.0068784, 0.00698537, 0.00621345, 0.00589216", \ + "0.0111027, 0.00969895, 0.0081786, 0.00729392, 0.00595365, 0.00546556", \ + "0.0175181, 0.0144199, 0.0122503, 0.0112614, 0.0102168, 0.00695611", \ + "0.0258639, 0.0205028, 0.0165133, 0.0135741, 0.012331, 0.0104072" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0791894, 0.076842, 0.0758108, 0.0756669, 0.0756389, 0.0756288", \ + "0.0778493, 0.0754622, 0.0743793, 0.0741822, 0.074156, 0.0741393", \ + "0.0771776, 0.0747697, 0.0736494, 0.0733891, 0.0733221, 0.0732999", \ + "0.0767291, 0.0743158, 0.0731752, 0.0729047, 0.0728454, 0.0728308", \ + "0.0785583, 0.0758051, 0.0742508, 0.0739426, 0.0741148, 0.0737463", \ + "0.0910535, 0.0853391, 0.0807846, 0.0788802, 0.0780073, 0.0770683", \ + "0.100416, 0.0926077, 0.0858973, 0.0829836, 0.0811304, 0.0797547" \ + ); + } + } + } + pin (c2p) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.016; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0293079; + rise_capacitance : 0.0295258; + rise_capacitance_range (0.0234309, 0.0344183); + fall_capacitance : 0.0290901; + fall_capacitance_range (0.0240941, 0.0317942); + internal_power () { + when : "(!c2p_en * pad * p2c)"; + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-7.33044e-06, -6.39316e-06, -3.78327e-06, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "7.33044e-06, 6.39316e-06, 3.78327e-06, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + when : "(!c2p_en * pad * p2c)"; + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0267608, -0.0277021, -0.0279363, -0.0282798, -0.0283342, -0.0285762, -0.0286452" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.035607, 0.0352665, 0.0349902, 0.0350389, 0.0347358, 0.0349056, 0.0349557" \ + ); + } + } + internal_power () { + when : "(!c2p_en * !pad * !p2c)"; + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-7.2752e-06, -6.34408e-06, -3.77286e-06, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "7.2752e-06, 6.34408e-06, 3.77286e-06, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + when : "(!c2p_en * !pad * !p2c)"; + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0267588, -0.0277011, -0.027935, -0.0282789, -0.028334, -0.0285763, -0.0286452" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0356053, 0.0352649, 0.0349895, 0.0350386, 0.0347355, 0.0349054, 0.0349557" \ + ); + } + } + internal_power () { + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-7.2752e-06, -6.34408e-06, -3.77286e-06, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "7.2752e-06, 6.34408e-06, 3.77286e-06, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0267588, -0.0277011, -0.027935, -0.0282789, -0.028334, -0.0285763, -0.0286452" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0356053, 0.0352649, 0.0349895, 0.0350386, 0.0347355, 0.0349054, 0.0349557" \ + ); + } + } + } + pin (c2p_en) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.011; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0264696; + rise_capacitance : 0.0276288; + rise_capacitance_range (0.0224667, 0.0348234); + fall_capacitance : 0.0253104; + fall_capacitance_range (0.0216285, 0.0302098); + internal_power () { + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "2.58273, 2.58599, 2.58252, 2.58307, 2.57978, 2.58363, 2.60303" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.258946, 0.258323, 0.258052, 0.256793, 0.25579, 0.255171, 0.254286" \ + ); + } + } + internal_power () { + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0527226, 0.0540186, 0.0577114, 0.0688665, 0.0936221, 0.145699, 0.256139" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.127563, 0.130668, 0.135509, 0.146202, 0.171527, 0.223911, 0.336118" \ + ); + } + } + } + } + cell (sg13g2_IOPadInOut4mA) { + pad_cell : true; + area : 14400; + cell_footprint : "inout"; + pad_drivers : 1; + bond_pads : 1; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 189.75; + when : "!c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 4918.42; + when : "!c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 189.499; + when : "!c2p_en&c2p&!pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 6204.94; + when : "!c2p_en&c2p&!pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 0; + when : "!c2p_en&!c2p&pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 4386.44; + when : "!c2p_en&!c2p&pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 0; + when : "!c2p_en&c2p&pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 5674.03; + when : "!c2p_en&c2p&pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 0; + when : "c2p_en&c2p&pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 6138.99; + when : "c2p_en&c2p&pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 0; + when : "c2p_en&c2p&pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 6138.99; + when : "c2p_en&c2p&pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 187.53; + when : "c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 5664; + when : "c2p_en&!c2p&!pad&!p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 187.516; + when : "c2p_en&!c2p&!pad&p2c"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 5664; + when : "c2p_en&!c2p&!pad&p2c"; + related_pg_pin : vdd; + } + leakage_power () { + value : 94.2869; + related_pg_pin : iovdd; + } + leakage_power () { + value : 5598.72; + related_pg_pin : vdd; + } + pin (pad) { + direction : "inout"; + is_pad : true; + function : "c2p"; + three_state : "c2p_en'"; + drive_current : 4; + output_voltage : "pad"; + input_voltage : "pad"; + related_ground_pin : iovss; + related_power_pin : iovdd; + max_capacitance : 1.07635; + capacitance : 0.188688; + rise_capacitance : 0.190919; + rise_capacitance_range (0.163029, 0.210073); + fall_capacitance : 0.186457; + fall_capacitance_range (0.1657, 0.199955); + timing () { + related_pin : "c2p"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.4397, 1.87568, 2.30913, 2.74172, 4.0382, 5.33421", \ + "1.45038, 1.88653, 2.31974, 2.75232, 4.04881, 5.34516", \ + "1.45793, 1.89383, 2.32705, 2.75966, 4.05617, 5.35234", \ + "1.46668, 1.90251, 2.33575, 2.76834, 4.06478, 5.36134", \ + "1.47646, 1.91232, 2.34556, 2.77819, 4.07469, 5.37126", \ + "1.48286, 1.91836, 2.35166, 2.7842, 4.08067, 5.37735", \ + "1.48287, 1.91837, 2.35167, 2.78421, 4.08068, 5.37736" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.13182, 2.02325, 2.9234, 3.82553, 6.52644, 9.23573", \ + "1.13183, 2.02326, 2.92343, 3.82554, 6.53393, 9.23574", \ + "1.13184, 2.02334, 2.92344, 3.826, 6.53394, 9.23575", \ + "1.13189, 2.02335, 2.92345, 3.82601, 6.53395, 9.23576", \ + "1.13194, 2.02342, 2.92346, 3.82602, 6.53481, 9.23577", \ + "1.13195, 2.02343, 2.92347, 3.82603, 6.53482, 9.23578", \ + "1.13196, 2.02344, 2.92348, 3.82604, 6.53483, 9.23579" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.06863, 1.49748, 1.92564, 2.35407, 3.63846, 4.92287", \ + "1.08333, 1.51209, 1.94009, 2.36834, 3.65413, 4.93716", \ + "1.09629, 1.52466, 1.95277, 2.38096, 3.66544, 4.94904", \ + "1.12445, 1.55286, 1.98062, 2.4085, 3.69302, 4.97685", \ + "1.17013, 1.59864, 2.02644, 2.45442, 3.73892, 5.02237", \ + "1.24929, 1.67801, 2.10615, 2.5343, 3.81859, 5.10212", \ + "1.39225, 1.82172, 2.24978, 2.67785, 3.96084, 5.24545" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.03162, 1.85957, 2.68986, 3.52459, 6.02138, 8.54467", \ + "1.03174, 1.85958, 2.69, 3.52966, 6.03144, 8.54468", \ + "1.03191, 1.85959, 2.69094, 3.52967, 6.03145, 8.54469", \ + "1.03204, 1.8596, 2.69095, 3.52968, 6.03146, 8.5447", \ + "1.03205, 1.85961, 2.6964, 3.52969, 6.03147, 8.54471", \ + "1.03216, 1.85962, 2.69641, 3.5297, 6.03148, 8.54472", \ + "1.03217, 1.86073, 2.69642, 3.5301, 6.03149, 8.54473" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : negative_unate; + timing_type : three_state_disable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.819976, 0.819977, 0.819978, 0.819979, 0.81998, 0.819981", \ + "0.840574, 0.840575, 0.840576, 0.840577, 0.840578, 0.840579", \ + "0.85008, 0.850081, 0.850082, 0.850083, 0.850084, 0.850085", \ + "0.873789, 0.873796, 0.873797, 0.873798, 0.873799, 0.8738", \ + "0.90535, 0.905351, 0.905352, 0.905353, 0.905354, 0.905355", \ + "0.948139, 0.94814, 0.948141, 0.948142, 0.948143, 0.948144", \ + "1.0307, 1.03071, 1.03072, 1.03073, 1.03074, 1.03075" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.819976, 0.819977, 0.819978, 0.819979, 0.81998, 0.819981", \ + "0.840574, 0.840575, 0.840576, 0.840577, 0.840578, 0.840579", \ + "0.85008, 0.850081, 0.850082, 0.850083, 0.850084, 0.850085", \ + "0.873789, 0.873796, 0.873797, 0.873798, 0.873799, 0.8738", \ + "0.90535, 0.905351, 0.905352, 0.905353, 0.905354, 0.905355", \ + "0.948139, 0.94814, 0.948141, 0.948142, 0.948143, 0.948144", \ + "1.0307, 1.03071, 1.03072, 1.03073, 1.03074, 1.03075" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.51171, 0.511711, 0.511712, 0.511713, 0.511714, 0.511715", \ + "0.532552, 0.532553, 0.532554, 0.532555, 0.532556, 0.532557", \ + "0.548416, 0.548417, 0.548418, 0.548419, 0.54842, 0.548421", \ + "0.578085, 0.578086, 0.578087, 0.578088, 0.578089, 0.57809", \ + "0.618568, 0.618569, 0.61857, 0.618571, 0.618572, 0.618573", \ + "0.688576, 0.688577, 0.688578, 0.688579, 0.68858, 0.688581", \ + "0.803483, 0.803484, 0.803485, 0.803486, 0.803487, 0.803488" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.51171, 0.511711, 0.511712, 0.511713, 0.511714, 0.511715", \ + "0.532552, 0.532553, 0.532554, 0.532555, 0.532556, 0.532557", \ + "0.548416, 0.548417, 0.548418, 0.548419, 0.54842, 0.548421", \ + "0.578085, 0.578086, 0.578087, 0.578088, 0.578089, 0.57809", \ + "0.618568, 0.618569, 0.61857, 0.618571, 0.618572, 0.618573", \ + "0.688576, 0.688577, 0.688578, 0.688579, 0.68858, 0.688581", \ + "0.803483, 0.803484, 0.803485, 0.803486, 0.803487, 0.803488" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : positive_unate; + timing_type : three_state_enable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.4479, 1.89976, 2.34978, 2.79908, 4.14596, 5.49281", \ + "1.45963, 1.91192, 2.36189, 2.81122, 4.1581, 5.5054", \ + "1.46839, 1.92079, 2.37077, 2.82012, 4.16724, 5.51376", \ + "1.47962, 1.93185, 2.38184, 2.83119, 4.17808, 5.52492", \ + "1.49479, 1.94736, 2.39732, 2.84664, 4.1937, 5.54083", \ + "1.5059, 1.95781, 2.40784, 2.85709, 4.20416, 5.55065", \ + "1.51385, 1.96598, 2.416, 2.86527, 4.21212, 5.55877" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.1306, 2.02156, 2.92324, 3.82583, 6.53327, 9.23797", \ + "1.13061, 2.02167, 2.92325, 3.82584, 6.53328, 9.23798", \ + "1.13062, 2.0222, 2.92326, 3.82595, 6.53329, 9.24345", \ + "1.13063, 2.02221, 2.92327, 3.82596, 6.5333, 9.24346", \ + "1.13064, 2.02222, 2.92328, 3.82597, 6.53409, 9.24347", \ + "1.13065, 2.02223, 2.92329, 3.82598, 6.5341, 9.24348", \ + "1.13066, 2.02224, 2.9233, 3.82599, 6.53411, 9.24349" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.08935, 1.55823, 2.0261, 2.4937, 3.89623, 5.30192", \ + "1.10173, 1.57061, 2.0385, 2.50693, 3.90915, 5.31346", \ + "1.10842, 1.5773, 2.04521, 2.51289, 3.91536, 5.31477", \ + "1.11694, 1.58582, 2.05371, 2.52139, 3.92376, 5.32868", \ + "1.12406, 1.59293, 2.06084, 2.52851, 3.93024, 5.33268", \ + "1.12991, 1.59879, 2.06672, 2.535, 3.93515, 5.33552", \ + "1.12992, 1.5988, 2.06673, 2.53501, 3.93516, 5.33553" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.02604, 1.85581, 2.6895, 3.52991, 6.03124, 8.53818", \ + "1.02605, 1.85582, 2.68951, 3.52992, 6.03908, 8.53819", \ + "1.02609, 1.85587, 2.68954, 3.52993, 6.03909, 8.5382", \ + "1.0261, 1.85588, 2.68955, 3.52994, 6.0391, 8.53821", \ + "1.02611, 1.85589, 2.68956, 3.52995, 6.03911, 8.53822", \ + "1.0267, 1.8559, 2.69065, 3.52996, 6.03912, 8.53823", \ + "1.02883, 1.85594, 2.69443, 3.52997, 6.03913, 8.54141" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "3.49929, 3.46627, 3.44388, 3.42576, 3.27878, 3.16407", \ + "3.49429, 3.46333, 3.43857, 3.42042, 3.32135, 3.07299", \ + "3.49557, 3.46381, 3.42497, 3.41322, 3.21813, 3.09616", \ + "3.49247, 3.45608, 3.43599, 3.41771, 3.31389, 3.10345", \ + "3.48725, 3.45416, 3.42989, 3.40705, 3.33336, 3.09098", \ + "3.48699, 3.45188, 3.40761, 3.39893, 3.31746, 3.10269", \ + "3.48365, 3.46841, 3.42431, 3.40639, 3.32221, 3.07484" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.74488, 1.73289, 1.72644, 1.72389, 1.71849, 1.71642", \ + "1.75348, 1.73772, 1.73075, 1.72671, 1.72032, 1.71738", \ + "1.76035, 1.74264, 1.73349, 1.72918, 1.7216, 1.71855", \ + "1.76639, 1.74602, 1.73658, 1.73141, 1.72361, 1.72", \ + "1.76292, 1.7437, 1.73491, 1.73011, 1.72262, 1.71933", \ + "1.76249, 1.74736, 1.74008, 1.73574, 1.72972, 1.72696", \ + "1.74078, 1.73574, 1.73366, 1.73233, 1.72922, 1.72804" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.30563, 4.53189, 6.77322, 9.0078, 15.7073, 22.4095", \ + "2.3053, 4.53072, 6.77337, 9.00819, 15.7085, 22.389", \ + "2.30962, 4.53609, 6.78041, 9.0094, 15.7012, 22.4082", \ + "2.32786, 4.55308, 6.79563, 9.03058, 15.7305, 22.4245", \ + "2.37009, 4.59499, 6.83669, 9.06781, 15.7796, 22.4601", \ + "2.46372, 4.68848, 6.92456, 9.15978, 15.8688, 22.5625", \ + "2.65772, 4.8988, 7.12178, 9.35433, 16.0588, 22.7388" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.261964, 0.262148, 0.262819, 0.263397, 0.265512, 0.266401", \ + "0.261707, 0.261978, 0.262622, 0.262248, 0.264495, 0.266898", \ + "0.267864, 0.268284, 0.2689, 0.268781, 0.269735, 0.274022", \ + "0.286702, 0.286748, 0.287545, 0.287461, 0.290521, 0.29131", \ + "0.329162, 0.32918, 0.32992, 0.329857, 0.331775, 0.334148", \ + "0.421758, 0.422012, 0.422704, 0.42254, 0.425984, 0.426321", \ + "0.614987, 0.615404, 0.616193, 0.615812, 0.619034, 0.618264" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "3.38301, 3.55242, 3.77157, 3.95482, 4.51011, 5.02831", \ + "3.37548, 3.5607, 3.75966, 3.95855, 4.51384, 4.9835", \ + "3.37598, 3.55943, 3.75527, 3.9531, 4.43738, 5.11335", \ + "3.3736, 3.55935, 3.75728, 3.95423, 4.51499, 5.05431", \ + "3.37408, 3.55714, 3.76157, 3.94291, 4.53664, 4.9727", \ + "3.3781, 3.55507, 3.76992, 3.93862, 4.53156, 5.0322", \ + "3.3805, 3.56081, 3.75755, 3.93278, 4.51202, 5.09573" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.00758, 1.00705, 1.00654, 1.0066, 1.00586, 1.00557", \ + "1.00672, 1.00623, 1.00567, 1.00586, 1.00504, 1.00483", \ + "1.00761, 1.00709, 1.0066, 1.00654, 1.00605, 1.00585", \ + "1.00684, 1.00631, 1.0058, 1.00591, 1.00524, 1.00504", \ + "1.00448, 1.00393, 1.00343, 1.00336, 1.00277, 1.0026", \ + "1.0098, 1.00818, 1.00892, 1.00852, 1.00785, 1.00763", \ + "1.00838, 1.00766, 1.00736, 1.00748, 1.00651, 1.00627" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.26139, 4.48482, 6.73257, 8.96195, 15.6592, 22.3544", \ + "2.26486, 4.48593, 6.72969, 8.96415, 15.6615, 22.3691", \ + "2.27242, 4.49758, 6.73798, 8.97138, 15.6642, 22.3805", \ + "2.29388, 4.51949, 6.76008, 8.99394, 15.6916, 22.3914", \ + "2.34187, 4.564, 6.81102, 9.04519, 15.7448, 22.4409", \ + "2.44215, 4.66885, 6.91305, 9.14736, 15.8463, 22.5486", \ + "2.65103, 4.88017, 7.11683, 9.35181, 16.047, 22.7635" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.132788, 0.133042, 0.133414, 0.133549, 0.135693, 0.137348", \ + "0.133843, 0.134052, 0.134476, 0.135063, 0.136761, 0.13884", \ + "0.13793, 0.138024, 0.138576, 0.138393, 0.142054, 0.142244", \ + "0.149326, 0.149451, 0.149966, 0.150651, 0.153954, 0.155194", \ + "0.173291, 0.173424, 0.173939, 0.174765, 0.176039, 0.175917", \ + "0.225943, 0.225782, 0.227007, 0.225955, 0.230252, 0.231827", \ + "0.337565, 0.337572, 0.338362, 0.338768, 0.341952, 0.341715" \ + ); + } + } + } + pin (p2c) { + direction : "output"; + output_voltage : "core"; + function : "pad"; + related_ground_pin : vss; + related_power_pin : vdd; + max_capacitance : 1.12076; + timing () { + related_pin : "pad"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0745136, 0.088253, 0.113294, 0.137189, 0.160857, 0.18439", \ + "0.0745146, 0.088254, 0.113295, 0.13719, 0.160858, 0.184391", \ + "0.0745156, 0.088255, 0.113296, 0.137191, 0.160859, 0.184392", \ + "0.0745166, 0.088256, 0.113297, 0.137192, 0.16086, 0.184393", \ + "0.0745176, 0.088257, 0.113298, 0.137193, 0.160861, 0.184394", \ + "0.0745186, 0.088258, 0.113299, 0.137194, 0.160862, 0.184395", \ + "0.0745196, 0.088259, 0.1133, 0.137195, 0.160863, 0.184396" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0492954, 0.0739631, 0.123952, 0.174819, 0.226132, 0.277751", \ + "0.053031, 0.0775882, 0.128007, 0.178703, 0.229715, 0.281111", \ + "0.0601586, 0.0838072, 0.132286, 0.182164, 0.23326, 0.285205", \ + "0.0632681, 0.086426, 0.134296, 0.183803, 0.234481, 0.285684", \ + "0.0780409, 0.100728, 0.146496, 0.193781, 0.242294, 0.29179", \ + "0.10183, 0.124845, 0.16831, 0.212777, 0.258652, 0.305638", \ + "0.120412, 0.143677, 0.186927, 0.228663, 0.274017, 0.319106" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.278044, 0.29568, 0.324004, 0.34826, 0.370044, 0.391128", \ + "0.328007, 0.345476, 0.373853, 0.398106, 0.420311, 0.441477", \ + "0.444966, 0.462436, 0.490806, 0.514592, 0.537219, 0.558392", \ + "0.504771, 0.522362, 0.550686, 0.574878, 0.596629, 0.618268", \ + "0.804278, 0.821217, 0.849483, 0.872644, 0.892885, 0.913348", \ + "1.37828, 1.39773, 1.4287, 1.45444, 1.47757, 1.49886", \ + "1.87189, 1.89287, 1.92611, 1.95372, 1.97813, 2.00114" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0820295, 0.100787, 0.13518, 0.16882, 0.201995, 0.23629", \ + "0.0820305, 0.100788, 0.135181, 0.168821, 0.202806, 0.236768", \ + "0.0820315, 0.100789, 0.135182, 0.168822, 0.202807, 0.236769", \ + "0.0820325, 0.10079, 0.135183, 0.168823, 0.202808, 0.23677", \ + "0.085069, 0.104139, 0.137537, 0.171294, 0.204491, 0.238301", \ + "0.115634, 0.132919, 0.164886, 0.195686, 0.227305, 0.258812", \ + "0.1403, 0.157423, 0.188998, 0.219144, 0.249068, 0.280256" \ + ); + } + } + internal_power () { + related_pin : "pad"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "-0.155945, -0.156193, -0.156157, -0.156163, -0.155911, -0.15619", \ + "-0.156372, -0.156203, -0.155707, -0.156354, -0.155929, -0.156165", \ + "-0.156318, -0.156188, -0.155545, -0.15633, -0.156368, -0.156367", \ + "-0.156261, -0.156259, -0.156093, -0.156251, -0.156253, -0.156148", \ + "-0.155594, -0.155772, -0.155613, -0.155895, -0.155753, -0.155639", \ + "-0.15566, -0.155581, -0.155528, -0.155566, -0.15554, -0.15558", \ + "-0.155593, -0.15559, -0.155601, -0.155579, -0.155715, -0.155634" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.156194, 0.156193, 0.15619, 0.156188, 0.156191, 0.15619", \ + "0.156372, 0.156371, 0.156368, 0.156365, 0.156361, 0.156361", \ + "0.156377, 0.156377, 0.156372, 0.156373, 0.156368, 0.156367", \ + "0.156261, 0.156259, 0.156255, 0.156251, 0.156253, 0.156245", \ + "0.155594, 0.155772, 0.155613, 0.155895, 0.155753, 0.155639", \ + "0.15566, 0.155581, 0.155528, 0.155566, 0.15554, 0.15558", \ + "0.155593, 0.15559, 0.155601, 0.155579, 0.155715, 0.155634" \ + ); + } + } + internal_power () { + related_pin : "pad"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.00877155, 0.00869905, 0.0089061, 0.00874426, 0.00841485, 0.00781711", \ + "0.00839229, 0.00864667, 0.0079422, 0.00771407, 0.0073863, 0.00722566", \ + "0.00865597, 0.00814417, 0.00833535, 0.00752762, 0.0067227, 0.00573841", \ + "0.00859512, 0.00763122, 0.0069207, 0.00699602, 0.00626055, 0.00596581", \ + "0.011151, 0.00962193, 0.0081477, 0.00720287, 0.00710415, 0.00595921", \ + "0.0176105, 0.0143967, 0.012255, 0.0111279, 0.00958215, 0.00710926", \ + "0.0255921, 0.0204274, 0.0165649, 0.0131139, 0.0128274, 0.0103466" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.12, 0.24, 0.48, 0.6, 1.2, 2.4, 3.5"); + index_2 ("0.024, 0.048, 0.096, 0.144, 0.192, 0.24"); + values ( \ + "0.0790877, 0.0767663, 0.0757957, 0.0756429, 0.0756304, 0.0756299", \ + "0.0778281, 0.0754194, 0.0743501, 0.0741628, 0.0741207, 0.0740905", \ + "0.0771733, 0.0747632, 0.0736475, 0.0733994, 0.0733238, 0.0732847", \ + "0.0767172, 0.0743285, 0.0731765, 0.0729132, 0.0728393, 0.0727899", \ + "0.0788033, 0.076057, 0.07435, 0.073556, 0.0731505, 0.0729071", \ + "0.089635, 0.0839172, 0.0794664, 0.0777148, 0.0771199, 0.0764564", \ + "0.0996415, 0.0918216, 0.084941, 0.082027, 0.080422, 0.0792477" \ + ); + } + } + } + pin (c2p) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.016; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0293078; + rise_capacitance : 0.0295256; + rise_capacitance_range (0.0234306, 0.0344178); + fall_capacitance : 0.02909; + fall_capacitance_range (0.0240937, 0.0317942); + internal_power () { + when : "(!c2p_en * pad * p2c)"; + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-1.04323e-05, -8.00036e-06, -4.30042e-06, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "1.04323e-05, 8.00036e-06, 4.30042e-06, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + when : "(!c2p_en * pad * p2c)"; + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0267611, -0.027702, -0.0279364, -0.0282799, -0.028334, -0.0285762, -0.0286455" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0356072, 0.0352665, 0.0349902, 0.0350389, 0.0347356, 0.0349056, 0.0349557" \ + ); + } + } + internal_power () { + when : "(!c2p_en * !pad * !p2c)"; + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-1.04194e-05, -8.0064e-06, -4.30687e-06, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "1.04194e-05, 8.0064e-06, 4.30687e-06, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + when : "(!c2p_en * !pad * !p2c)"; + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.026759, -0.0277011, -0.0279351, -0.028279, -0.0283339, -0.0285763, -0.0286455" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0356054, 0.035265, 0.0349896, 0.0350385, 0.0347352, 0.0349054, 0.0349557" \ + ); + } + } + internal_power () { + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-1.04194e-05, -8.0064e-06, -4.30687e-06, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "1.04194e-05, 8.0064e-06, 4.30687e-06, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.026759, -0.0277011, -0.0279351, -0.028279, -0.0283339, -0.0285763, -0.0286455" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0356054, 0.035265, 0.0349896, 0.0350385, 0.0347352, 0.0349054, 0.0349557" \ + ); + } + } + } + pin (c2p_en) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.011; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0264634; + rise_capacitance : 0.0276157; + rise_capacitance_range (0.0224665, 0.0345746); + fall_capacitance : 0.0253111; + fall_capacitance_range (0.0216283, 0.0301574); + internal_power () { + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.806038, 0.80631, 0.806088, 0.806634, 0.804839, 0.809079, 0.806553" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.293533, 0.293209, 0.293292, 0.292204, 0.29045, 0.290223, 0.289659" \ + ); + } + } + internal_power () { + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0527255, 0.0540234, 0.0576236, 0.0689266, 0.0936793, 0.145731, 0.255997" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.127561, 0.130666, 0.135505, 0.146198, 0.171522, 0.223575, 0.335997" \ + ); + } + } + } + } + cell (sg13g2_IOPadOut16mA) { + pad_cell : true; + area : 14400; + cell_footprint : "inout"; + pad_drivers : 1; + bond_pads : 1; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 438.841; + when : "!c2p&!pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 870.847; + when : "!c2p&!pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 201.682; + when : "c2p&pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 1934.07; + when : "c2p&pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 320.261; + related_pg_pin : iovdd; + } + leakage_power () { + value : 1402.46; + related_pg_pin : vdd; + } + pin (pad) { + direction : "output"; + is_pad : true; + function : "c2p"; + drive_current : 16; + output_voltage : "pad"; + related_ground_pin : iovss; + related_power_pin : iovdd; + max_capacitance : 4.21526; + timing () { + related_pin : "c2p"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 3, 7, 9, 12, 15"); + values ( \ + "1.39325, 1.68662, 2.15498, 2.3759, 2.70447, 3.02978", \ + "1.41933, 1.71249, 2.17998, 2.40219, 2.73042, 3.05581", \ + "1.44331, 1.73693, 2.20509, 2.42552, 2.75467, 3.08014", \ + "1.49946, 1.7931, 2.26127, 2.48275, 2.81036, 3.13634", \ + "1.60146, 1.89483, 2.36255, 2.58391, 2.91145, 3.23811", \ + "1.7838, 2.07704, 2.54551, 2.76705, 3.09529, 3.42098", \ + "2.11646, 2.4102, 2.87862, 3.10012, 3.42707, 3.75372" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 3, 7, 9, 12, 15"); + values ( \ + "0.511069, 0.941613, 1.79265, 2.2258, 2.8848, 3.54864", \ + "0.51107, 0.941614, 1.79266, 2.22665, 2.88481, 3.54892", \ + "0.511071, 0.941997, 1.79267, 2.22666, 2.88482, 3.54929", \ + "0.511072, 0.941998, 1.79268, 2.22667, 2.88483, 3.5493", \ + "0.511073, 0.942081, 1.79269, 2.22668, 2.88535, 3.54931", \ + "0.511074, 0.942082, 1.7927, 2.22675, 2.88536, 3.54932", \ + "0.511075, 0.942083, 1.79271, 2.22678, 2.88537, 3.54933" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 3, 7, 9, 12, 15"); + values ( \ + "0.963508, 1.20021, 1.61126, 1.8131, 2.1217, 2.43492", \ + "0.97714, 1.21375, 1.62415, 1.8266, 2.13567, 2.44853", \ + "0.984778, 1.22127, 1.6333, 1.83409, 2.14365, 2.45598", \ + "0.998801, 1.23547, 1.64675, 1.84949, 2.15774, 2.47022", \ + "1.01857, 1.25489, 1.6659, 1.86796, 2.1768, 2.48977", \ + "1.0567, 1.29253, 1.70368, 1.90677, 2.21422, 2.52617", \ + "1.12032, 1.35675, 1.76643, 1.96937, 2.27767, 2.59009" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 3, 7, 9, 12, 15"); + values ( \ + "0.617851, 0.940021, 1.67875, 2.06824, 2.66418, 3.26955", \ + "0.617852, 0.940022, 1.67876, 2.06884, 2.66496, 3.26959", \ + "0.61819, 0.940161, 1.67879, 2.06899, 2.66644, 3.26962", \ + "0.618191, 0.940162, 1.6788, 2.069, 2.66645, 3.26963", \ + "0.618331, 0.940221, 1.67891, 2.06901, 2.66646, 3.26964", \ + "0.618503, 0.940398, 1.67997, 2.0704, 2.66647, 3.27065", \ + "0.618504, 0.940399, 1.67998, 2.07041, 2.66648, 3.27066" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 3, 7, 9, 12, 15"); + values ( \ + "6.1661, 6.05893, 6.01112, 5.96294, 5.93703, 5.77939", \ + "6.164, 6.0622, 5.9767, 5.99313, 5.94861, 5.79747", \ + "6.16514, 6.08154, 6.04174, 5.94261, 5.93726, 5.83358", \ + "6.15264, 6.07999, 6.0425, 6.01663, 5.92056, 5.80295", \ + "6.21311, 6.11807, 6.05233, 6.01564, 5.91858, 5.87067", \ + "6.22861, 6.14605, 6.11507, 6.0914, 5.98778, 5.89241", \ + "6.29104, 6.21977, 6.20067, 6.17219, 6.06068, 5.97432" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 3, 7, 9, 12, 15"); + values ( \ + "15.102, 12.2062, 9.71937, 9.03556, 8.29977, 7.76949", \ + "15.0901, 12.1971, 9.70928, 9.03143, 8.30151, 7.75989", \ + "15.0921, 12.1991, 9.71494, 9.0321, 8.30843, 7.75854", \ + "15.0844, 12.1895, 9.70682, 9.01564, 8.2974, 7.75283", \ + "15.0839, 12.1912, 9.70987, 9.01984, 8.29135, 7.74581", \ + "15.0943, 12.2033, 9.72997, 9.03208, 8.29746, 7.77271", \ + "15.0681, 12.172, 9.68511, 9.00695, 8.26593, 7.74988" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 3, 7, 9, 12, 15"); + values ( \ + "-0.0169284, -0.0169287, -0.0169284, -0.0169289, -0.0169291, -0.0169284", \ + "-0.0129106, -0.012911, -0.0129108, -0.0129112, -0.0129114, -0.0129107", \ + "-0.00525433, -0.00525488, -0.00525499, -0.00525521, -0.00525507, -0.00525485", \ + "0.0152513, 0.0152512, 0.0152512, 0.015251, 0.0152509, 0.0152515", \ + "0.0584194, 0.058419, 0.0584186, 0.0584186, 0.0584188, 0.058419", \ + "0.150444, 0.150445, 0.150444, 0.150444, 0.150444, 0.150444", \ + "0.333724, 0.333724, 0.333724, 0.333724, 0.333724, 0.333724" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 3, 7, 9, 12, 15"); + values ( \ + "0.0876125, 0.0876096, 0.0876116, 0.08761, 0.0876103, 0.0876136", \ + "0.0957992, 0.0957965, 0.0958002, 0.0957949, 0.0957926, 0.0957994", \ + "0.103818, 0.103816, 0.103814, 0.103814, 0.103815, 0.103819", \ + "0.125488, 0.125487, 0.125487, 0.125445, 0.125445, 0.12549", \ + "0.170657, 0.171137, 0.17114, 0.170651, 0.171133, 0.170658", \ + "0.261364, 0.260964, 0.260964, 0.261346, 0.261261, 0.261378", \ + "0.442869, 0.442478, 0.442428, 0.442543, 0.442748, 0.442704" \ + ); + } + } + } + pin (c2p) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.016; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0411573; + rise_capacitance : 0.0400578; + rise_capacitance_range (0.0351473, 0.0435194); + fall_capacitance : 0.0422567; + fall_capacitance_range (0.0376588, 0.0448325); + } + } + cell (sg13g2_IOPadOut30mA) { + pad_cell : true; + area : 14400; + cell_footprint : "inout"; + pad_drivers : 1; + bond_pads : 1; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 851.687; + when : "!c2p&!pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 869.813; + when : "!c2p&!pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 406.782; + when : "c2p&pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 1933.96; + when : "c2p&pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 629.234; + related_pg_pin : iovdd; + } + leakage_power () { + value : 1401.89; + related_pg_pin : vdd; + } + pin (pad) { + direction : "output"; + is_pad : true; + function : "c2p"; + drive_current : 30; + output_voltage : "pad"; + related_ground_pin : iovss; + related_power_pin : iovdd; + max_capacitance : 4.43775; + timing () { + related_pin : "c2p"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("2, 6, 14, 18, 24, 30"); + values ( \ + "1.74656, 2.13551, 2.69948, 2.94654, 3.30863, 3.6634", \ + "1.77295, 2.16172, 2.72567, 2.97333, 3.33642, 3.68906", \ + "1.79685, 2.1874, 2.74978, 2.99768, 3.35962, 3.71431", \ + "1.8555, 2.24346, 2.80737, 3.05503, 3.41789, 3.77087", \ + "1.95683, 2.34709, 2.90701, 3.15689, 3.51996, 3.87436", \ + "2.13668, 2.52571, 3.09005, 3.33838, 3.70047, 4.05326", \ + "2.47194, 2.86131, 3.42476, 3.67351, 4.0349, 4.3898" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("2, 6, 14, 18, 24, 30"); + values ( \ + "0.656556, 1.16488, 2.07673, 2.52915, 3.22108, 3.92059", \ + "0.656619, 1.16568, 2.07674, 2.52916, 3.22191, 3.9206", \ + "0.65662, 1.16902, 2.07675, 2.52917, 3.22192, 3.92061", \ + "0.656621, 1.16903, 2.07676, 2.53022, 3.22193, 3.92062", \ + "0.656622, 1.1693, 2.07677, 2.53023, 3.22194, 3.92063", \ + "0.656861, 1.16931, 2.07693, 2.53024, 3.22195, 3.92064", \ + "0.657045, 1.16932, 2.07694, 2.53025, 3.22195, 3.92065" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("2, 6, 14, 18, 24, 30"); + values ( \ + "1.33307, 1.61788, 2.08599, 2.30143, 2.62071, 2.94514", \ + "1.34688, 1.63077, 2.09832, 2.3159, 2.63434, 2.95533", \ + "1.35451, 1.63859, 2.10664, 2.32349, 2.64398, 2.96095", \ + "1.36872, 1.65305, 2.11946, 2.33801, 2.65657, 2.97501", \ + "1.38795, 1.67287, 2.14094, 2.35599, 2.6777, 2.99911", \ + "1.42551, 1.71, 2.17614, 2.3925, 2.71327, 3.03463", \ + "1.48842, 1.77161, 2.24238, 2.45772, 2.77975, 3.09804" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("2, 6, 14, 18, 24, 30"); + values ( \ + "1.0074, 1.32231, 2.02609, 2.41631, 3.02375, 3.64627", \ + "1.00741, 1.32232, 2.0261, 2.41833, 3.02376, 3.64628", \ + "1.00742, 1.32233, 2.03048, 2.41834, 3.02377, 3.64629", \ + "1.00754, 1.32234, 2.03049, 2.41835, 3.02378, 3.6463", \ + "1.00755, 1.32235, 2.0305, 2.41836, 3.02379, 3.6471", \ + "1.008, 1.32324, 2.03051, 2.41837, 3.0238, 3.64711", \ + "1.00801, 1.32325, 2.03052, 2.41841, 3.02381, 3.64712" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("2, 6, 14, 18, 24, 30"); + values ( \ + "9.96652, 9.60482, 9.71847, 9.31768, 9.22799, 9.11031", \ + "9.97722, 9.63207, 9.72576, 9.32923, 9.30993, 9.02418", \ + "9.93237, 9.8344, 9.72447, 9.35293, 9.30026, 9.14991", \ + "9.98405, 9.62937, 9.74516, 9.41906, 9.31715, 9.04959", \ + "9.99936, 9.8805, 9.48938, 9.42104, 9.34742, 9.21954", \ + "10.0487, 9.71834, 9.82658, 9.45618, 9.41091, 9.09282", \ + "10.1177, 9.93363, 9.87456, 9.50991, 9.47252, 9.32712" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("2, 6, 14, 18, 24, 30"); + values ( \ + "54.3171, 44.9114, 35.1121, 32.1656, 28.9612, 26.4677", \ + "54.2976, 44.8944, 35.08, 32.1597, 28.9419, 26.4607", \ + "54.3051, 44.9098, 35.1488, 32.1513, 28.8983, 26.4881", \ + "54.3115, 44.8908, 35.1366, 32.1368, 28.9133, 26.4799", \ + "54.3203, 44.9074, 35.1238, 32.1075, 28.8776, 26.491", \ + "54.3286, 44.9149, 35.0993, 32.124, 28.9063, 26.414", \ + "54.2614, 44.8526, 35.0621, 32.1679, 28.8996, 26.4628" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("2, 6, 14, 18, 24, 30"); + values ( \ + "-0.0169349, -0.0169347, -0.0169344, -0.0169347, -0.0169348, -0.016935", \ + "-0.0129283, -0.0129285, -0.0129281, -0.0129283, -0.0129284, -0.0129286", \ + "-0.00529122, -0.00529128, -0.00529098, -0.00529115, -0.00529185, -0.0052918", \ + "0.015208, 0.0152082, 0.0152086, 0.0152085, 0.0152084, 0.0152081", \ + "0.0584604, 0.0584601, 0.05846, 0.0584599, 0.0584599, 0.0584598", \ + "0.150258, 0.150258, 0.150258, 0.150258, 0.150258, 0.150258", \ + "0.338671, 0.33867, 0.338671, 0.33867, 0.33867, 0.33867" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("2, 6, 14, 18, 24, 30"); + values ( \ + "0.0876192, 0.0876201, 0.0876205, 0.0876218, 0.0876192, 0.087621", \ + "0.0957843, 0.0957854, 0.0957864, 0.0957885, 0.0957856, 0.095786", \ + "0.103788, 0.103789, 0.103789, 0.103788, 0.103791, 0.103789", \ + "0.1254, 0.125401, 0.125402, 0.125435, 0.125433, 0.125432", \ + "0.170769, 0.17077, 0.17077, 0.170774, 0.17077, 0.170773", \ + "0.261157, 0.26116, 0.260701, 0.260824, 0.260813, 0.260812", \ + "0.445458, 0.445454, 0.445396, 0.44579, 0.445967, 0.445578" \ + ); + } + } + } + pin (c2p) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.016; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0411496; + rise_capacitance : 0.0400495; + rise_capacitance_range (0.0351387, 0.0435201); + fall_capacitance : 0.0422497; + fall_capacitance_range (0.0376405, 0.0447817); + } + } + cell (sg13g2_IOPadOut4mA) { + pad_cell : true; + area : 14400; + cell_footprint : "inout"; + pad_drivers : 1; + bond_pads : 1; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 172.828; + when : "!c2p&!pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 869.749; + when : "!c2p&!pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 118.795; + when : "c2p&pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 1934.09; + when : "c2p&pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 145.811; + related_pg_pin : iovdd; + } + leakage_power () { + value : 1401.92; + related_pg_pin : vdd; + } + pin (pad) { + direction : "output"; + is_pad : true; + function : "c2p"; + drive_current : 4; + output_voltage : "pad"; + related_ground_pin : iovss; + related_power_pin : iovdd; + max_capacitance : 1.1116; + timing () { + related_pin : "c2p"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.39454, 1.83059, 2.26375, 2.69712, 3.99407, 5.28998", \ + "1.42135, 1.85746, 2.29139, 2.72402, 4.02063, 5.31697", \ + "1.44555, 1.88159, 2.31551, 2.74814, 4.04476, 5.34114", \ + "1.5011, 1.93737, 2.37144, 2.80381, 4.10062, 5.3969", \ + "1.60172, 2.03779, 2.47164, 2.9043, 4.20093, 5.49732", \ + "1.7863, 2.22267, 2.65671, 3.08889, 4.38585, 5.68119", \ + "2.12129, 2.55731, 2.99107, 3.4233, 4.72034, 6.01662" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.10091, 1.98784, 2.88475, 3.78323, 6.48435, 9.18083", \ + "1.10103, 1.98787, 2.88476, 3.78324, 6.48436, 9.18272", \ + "1.10104, 1.98826, 2.88477, 3.78325, 6.48437, 9.1833", \ + "1.10122, 1.98827, 2.88478, 3.78326, 6.48438, 9.18534", \ + "1.10123, 1.98828, 2.88479, 3.78351, 6.48439, 9.18535", \ + "1.10124, 1.98829, 2.8848, 3.78352, 6.4844, 9.18536", \ + "1.10125, 1.9883, 2.88481, 3.78356, 6.48441, 9.18537" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.996337, 1.42332, 1.85066, 2.27742, 3.55962, 4.84153", \ + "1.00994, 1.43701, 1.86422, 2.29097, 3.57238, 4.8551", \ + "1.01756, 1.44462, 1.87206, 2.29865, 3.58098, 4.86286", \ + "1.03231, 1.45951, 1.88633, 2.3138, 3.59577, 4.87758", \ + "1.05091, 1.47783, 1.90472, 2.33181, 3.61381, 4.89576", \ + "1.0892, 1.51664, 1.94334, 2.37043, 3.65203, 4.93476", \ + "1.15363, 1.58088, 2.00773, 2.43448, 3.71631, 4.99779" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.00325, 1.82555, 2.65422, 3.48521, 5.98222, 8.47947", \ + "1.00327, 1.82556, 2.6544, 3.48578, 5.98223, 8.47948", \ + "1.00328, 1.82557, 2.65441, 3.48583, 5.98224, 8.47949", \ + "1.00363, 1.82558, 2.65445, 3.48584, 5.98225, 8.4795", \ + "1.00376, 1.82559, 2.65446, 3.48673, 5.98226, 8.47951", \ + "1.00377, 1.8256, 2.65457, 3.48674, 5.98227, 8.47952", \ + "1.00584, 1.82598, 2.65458, 3.48675, 5.98228, 8.483" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "3.14078, 3.11334, 3.08774, 3.05164, 2.96766, 2.85777", \ + "3.14778, 3.11842, 3.09062, 3.06293, 2.97525, 2.87041", \ + "3.14848, 3.12286, 3.09289, 3.05897, 2.97911, 2.90258", \ + "3.16283, 3.13276, 3.10487, 3.07134, 2.99132, 2.89737", \ + "3.18296, 3.15876, 3.12527, 3.10283, 3.01178, 2.92116", \ + "3.23412, 3.21024, 3.18206, 3.14582, 3.06785, 2.96023", \ + "3.32032, 3.29359, 3.26717, 3.23915, 3.15391, 3.05986" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.88419, 1.84853, 1.83262, 1.82353, 1.81035, 1.80406", \ + "1.87472, 1.83971, 1.82288, 1.81385, 1.80092, 1.79464", \ + "1.8701, 1.83353, 1.81818, 1.81007, 1.79554, 1.78971", \ + "1.86831, 1.83373, 1.81698, 1.80866, 1.79403, 1.78877", \ + "1.86127, 1.82437, 1.80824, 1.80001, 1.7858, 1.78003", \ + "1.86159, 1.8271, 1.81009, 1.80147, 1.78761, 1.7801", \ + "1.86927, 1.83293, 1.81737, 1.80918, 1.79462, 1.78886" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "-0.0169355, -0.0169363, -0.016937, -0.0169361, -0.0169358, -0.0169358", \ + "-0.0129271, -0.012928, -0.0129286, -0.0129281, -0.0129282, -0.0129282", \ + "-0.00528896, -0.00528995, -0.00529057, -0.00529005, -0.00529009, -0.00529014", \ + "0.0152079, 0.0152073, 0.015207, 0.0152072, 0.0152071, 0.0152072", \ + "0.0584618, 0.0584608, 0.0584602, 0.0584607, 0.0584608, 0.0584606", \ + "0.148612, 0.148611, 0.148611, 0.148611, 0.148611, 0.148611", \ + "0.338848, 0.338838, 0.33884, 0.338841, 0.338842, 0.338843" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.0876411, 0.0876283, 0.0876307, 0.0876296, 0.087624, 0.0876316", \ + "0.0958343, 0.0958308, 0.0958171, 0.0958231, 0.0958195, 0.0958267", \ + "0.103809, 0.103807, 0.103807, 0.103808, 0.103802, 0.103807", \ + "0.125363, 0.125357, 0.12535, 0.125355, 0.125349, 0.125355", \ + "0.170957, 0.170951, 0.17094, 0.170953, 0.171101, 0.171111", \ + "0.263714, 0.263882, 0.263717, 0.263743, 0.263724, 0.263663", \ + "0.448059, 0.447885, 0.448315, 0.448222, 0.448267, 0.448253" \ + ); + } + } + } + pin (c2p) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.016; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0411635; + rise_capacitance : 0.0400666; + rise_capacitance_range (0.0351382, 0.0435042); + fall_capacitance : 0.0422604; + fall_capacitance_range (0.0376394, 0.0448089); + } + } + cell (sg13g2_IOPadTriOut16mA) { + pad_cell : true; + area : 14400; + cell_footprint : "tri_out"; + pad_drivers : 1; + bond_pads : 1; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 173.446; + when : "!c2p_en&!c2p"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 3944.2; + when : "!c2p_en&!c2p"; + related_pg_pin : vdd; + } + leakage_power () { + value : 173.446; + when : "!c2p_en&c2p"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 5231.75; + when : "!c2p_en&c2p"; + related_pg_pin : vdd; + } + leakage_power () { + value : 262.209; + when : "c2p_en&c2p&pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 5696.72; + when : "c2p_en&c2p&pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 479.337; + when : "c2p_en&!c2p&!pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 4689.75; + when : "c2p_en&!c2p&!pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 272.109; + related_pg_pin : iovdd; + } + leakage_power () { + value : 4890.6; + related_pg_pin : vdd; + } + pin (pad) { + direction : "output"; + is_pad : true; + function : "c2p"; + three_state : "c2p_en'"; + drive_current : 16; + output_voltage : "pad"; + related_ground_pin : iovss; + related_power_pin : iovdd; + max_capacitance : 4.21412; + capacitance : 0.24106; + rise_capacitance : 0.24299; + rise_capacitance_range (0.24299, 0.24299); + fall_capacitance : 0.239129; + fall_capacitance_range (0.239129, 0.239129); + timing () { + related_pin : "c2p"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.4403, 1.59972, 1.73444, 1.85989, 2.20311, 2.53431", \ + "1.45223, 1.61161, 1.74741, 1.87169, 2.21467, 2.5461", \ + "1.45924, 1.6186, 1.75321, 1.87839, 2.22107, 2.55281", \ + "1.46845, 1.62845, 1.76248, 1.8877, 2.23079, 2.56209", \ + "1.47916, 1.63851, 1.77335, 1.89816, 2.24169, 2.57285", \ + "1.48312, 1.64277, 1.77751, 1.903, 2.24625, 2.57754", \ + "1.48313, 1.64278, 1.77752, 1.90301, 2.24626, 2.57755" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.512044, 0.731884, 0.942278, 1.15448, 1.79287, 2.44501", \ + "0.512045, 0.731885, 0.943501, 1.15449, 1.79288, 2.44502", \ + "0.512046, 0.731886, 0.943502, 1.1545, 1.79289, 2.44503", \ + "0.512047, 0.733741, 0.943503, 1.15451, 1.7929, 2.44504", \ + "0.512048, 0.733742, 0.943504, 1.15452, 1.79291, 2.44524", \ + "0.512527, 0.733743, 0.943505, 1.15453, 1.79292, 2.4454", \ + "0.513636, 0.733744, 0.943506, 1.15454, 1.79293, 2.44541" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.02748, 1.15296, 1.26487, 1.37095, 1.67692, 1.98648", \ + "1.04392, 1.16917, 1.28103, 1.38699, 1.69321, 1.99998", \ + "1.05775, 1.18318, 1.295, 1.40093, 1.70781, 2.01517", \ + "1.08694, 1.21234, 1.32414, 1.43002, 1.73664, 2.04324", \ + "1.13226, 1.25745, 1.36926, 1.47516, 1.78226, 2.08937", \ + "1.20938, 1.33477, 1.44692, 1.55286, 1.8599, 2.16578", \ + "1.3459, 1.47143, 1.58345, 1.68942, 1.99621, 2.30511" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.59618, 0.756689, 0.924914, 1.10105, 1.66831, 2.25812", \ + "0.600605, 0.759881, 0.925299, 1.10371, 1.66999, 2.25913", \ + "0.602904, 0.762146, 0.927774, 1.10545, 1.67198, 2.26004", \ + "0.604318, 0.76384, 0.928684, 1.10622, 1.67321, 2.26027", \ + "0.604319, 0.763841, 0.928685, 1.10623, 1.67322, 2.26111", \ + "0.60432, 0.763842, 0.928686, 1.10624, 1.67323, 2.26112", \ + "0.604321, 0.763843, 0.928687, 1.10625, 1.67324, 2.26113" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : negative_unate; + timing_type : three_state_disable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.03068, 1.03069, 1.0307, 1.03071, 1.03072, 1.03073", \ + "1.04742, 1.04743, 1.04744, 1.04745, 1.04746, 1.04747", \ + "1.06681, 1.06682, 1.06683, 1.06684, 1.06685, 1.06686", \ + "1.08693, 1.08694, 1.08695, 1.08696, 1.08697, 1.08698", \ + "1.11655, 1.11656, 1.11657, 1.11658, 1.11659, 1.1166", \ + "1.16487, 1.16488, 1.16489, 1.1649, 1.16491, 1.16492", \ + "1.24176, 1.24177, 1.24178, 1.24179, 1.2418, 1.24181" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.03068, 1.03069, 1.0307, 1.03071, 1.03072, 1.03073", \ + "1.04742, 1.04743, 1.04744, 1.04745, 1.04746, 1.04747", \ + "1.06681, 1.06682, 1.06683, 1.06684, 1.06685, 1.06686", \ + "1.08693, 1.08694, 1.08695, 1.08696, 1.08697, 1.08698", \ + "1.11655, 1.11656, 1.11657, 1.11658, 1.11659, 1.1166", \ + "1.16487, 1.16488, 1.16489, 1.1649, 1.16491, 1.16492", \ + "1.24176, 1.24177, 1.24178, 1.24179, 1.2418, 1.24181" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.01482, 1.01483, 1.01484, 1.01485, 1.01486, 1.01487", \ + "1.03531, 1.03532, 1.03533, 1.03534, 1.03535, 1.03536", \ + "1.05191, 1.05192, 1.05193, 1.05194, 1.05195, 1.05196", \ + "1.09128, 1.09129, 1.0913, 1.09131, 1.09132, 1.09133", \ + "1.12046, 1.12047, 1.12048, 1.12049, 1.1205, 1.12051", \ + "1.19796, 1.19797, 1.19798, 1.19799, 1.198, 1.19801", \ + "1.30367, 1.30368, 1.30369, 1.3037, 1.30371, 1.30372" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.01482, 1.01483, 1.01484, 1.01485, 1.01486, 1.01487", \ + "1.03531, 1.03532, 1.03533, 1.03534, 1.03535, 1.03536", \ + "1.05191, 1.05192, 1.05193, 1.05194, 1.05195, 1.05196", \ + "1.09128, 1.09129, 1.0913, 1.09131, 1.09132, 1.09133", \ + "1.12046, 1.12047, 1.12048, 1.12049, 1.1205, 1.12051", \ + "1.19796, 1.19797, 1.19798, 1.19799, 1.198, 1.19801", \ + "1.30367, 1.30368, 1.30369, 1.3037, 1.30371, 1.30372" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : positive_unate; + timing_type : three_state_enable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.43559, 1.60491, 1.74707, 1.87604, 2.23705, 2.58834", \ + "1.44828, 1.61749, 1.75964, 1.88813, 2.25064, 2.60095", \ + "1.45682, 1.62615, 1.76648, 1.89877, 2.25975, 2.60832", \ + "1.46871, 1.63668, 1.78007, 1.90854, 2.2714, 2.61941", \ + "1.48229, 1.65068, 1.79431, 1.92451, 2.28447, 2.63529", \ + "1.49481, 1.66397, 1.8056, 1.93659, 2.29652, 2.64752", \ + "1.50206, 1.67008, 1.8107, 1.94166, 2.30342, 2.65336" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.511714, 0.721606, 0.928949, 1.13621, 1.77345, 2.42808", \ + "0.511715, 0.721615, 0.92895, 1.13622, 1.77406, 2.42809", \ + "0.511716, 0.721616, 0.928951, 1.13758, 1.77428, 2.4281", \ + "0.511717, 0.721617, 0.928952, 1.13759, 1.77429, 2.42811", \ + "0.511718, 0.721618, 0.928953, 1.1376, 1.7743, 2.42812", \ + "0.511719, 0.721619, 0.928954, 1.13761, 1.77431, 2.42813", \ + "0.51172, 0.72162, 0.928955, 1.13762, 1.77432, 2.42861" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.855922, 1.00479, 1.13624, 1.25836, 1.61483, 1.96144", \ + "0.868843, 1.01774, 1.14721, 1.27127, 1.6261, 1.97388", \ + "0.874791, 1.02367, 1.15511, 1.27723, 1.63373, 1.97989", \ + "0.88403, 1.03291, 1.16435, 1.28647, 1.64297, 1.98918", \ + "0.891106, 1.03998, 1.17143, 1.29354, 1.65004, 1.99624", \ + "0.895452, 1.04326, 1.17615, 1.29889, 1.65366, 2.00106", \ + "0.895453, 1.04327, 1.17616, 1.2989, 1.65367, 2.00107" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.399103, 0.596419, 0.791354, 0.986477, 1.58709, 2.19815", \ + "0.399133, 0.596446, 0.791355, 0.986488, 1.5871, 2.19816", \ + "0.399134, 0.596447, 0.791356, 0.986489, 1.58711, 2.19879", \ + "0.399135, 0.596448, 0.791357, 0.98649, 1.58712, 2.1988", \ + "0.399136, 0.596449, 0.791358, 0.986491, 1.58713, 2.19881", \ + "0.399137, 0.59645, 0.791359, 0.98676, 1.58714, 2.19882", \ + "0.399138, 0.596451, 0.793118, 0.987927, 1.58761, 2.19883" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "6.12555, 6.06468, 6.04501, 6.12266, 6.01989, 5.95274", \ + "6.13093, 6.06614, 6.10388, 6.12394, 6.01517, 5.94416", \ + "6.13196, 6.06335, 6.04916, 6.12124, 5.99881, 5.94531", \ + "6.13611, 6.14127, 6.05055, 6.11615, 5.99333, 5.94802", \ + "6.129, 6.06541, 6.04233, 6.1054, 6.01247, 5.93766", \ + "6.10038, 6.04253, 6.02851, 6.10563, 6.00316, 5.933", \ + "6.04965, 5.95983, 6.00174, 5.94178, 5.88139, 5.92588" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "14.0451, 12.4413, 11.3669, 10.5855, 9.11265, 8.24689", \ + "14.2249, 12.6016, 11.5054, 10.7171, 9.21592, 8.34452", \ + "14.3571, 12.7165, 11.6105, 10.8092, 9.29768, 8.39629", \ + "14.4561, 12.8034, 11.6858, 10.8786, 9.36229, 8.43499", \ + "14.3998, 12.7575, 11.6433, 10.8428, 9.32729, 8.41091", \ + "14.2226, 12.6047, 11.5031, 10.7127, 9.23347, 8.35559", \ + "13.6419, 12.0856, 11.0467, 10.2926, 8.89376, 8.06673" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.0760516, 0.0760496, 0.0760509, 0.0760508, 0.0760473, 0.0760413", \ + "0.0757339, 0.0757323, 0.0757347, 0.0757336, 0.0757302, 0.0757265", \ + "0.0804744, 0.0804738, 0.0804731, 0.0804757, 0.0804744, 0.0804687", \ + "0.0969984, 0.0969992, 0.096999, 0.0969974, 0.0969968, 0.0969901", \ + "0.139086, 0.139085, 0.139086, 0.139087, 0.139081, 0.139083", \ + "0.232372, 0.23237, 0.232373, 0.232372, 0.232367, 0.232366", \ + "0.426471, 0.426447, 0.426468, 0.42638, 0.426345, 0.426465" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.189418, 0.189422, 0.18942, 0.189418, 0.189412, 0.189411", \ + "0.189107, 0.189111, 0.189106, 0.189109, 0.189111, 0.189105", \ + "0.194875, 0.194875, 0.194875, 0.194875, 0.194874, 0.194865", \ + "0.213935, 0.213941, 0.213936, 0.213936, 0.213936, 0.213927", \ + "0.256282, 0.256283, 0.256276, 0.25628, 0.256279, 0.256267", \ + "0.348375, 0.348658, 0.348329, 0.348338, 0.348632, 0.348623", \ + "0.540978, 0.541007, 0.540883, 0.540873, 0.541058, 0.540819" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "5.88109, 6.22534, 6.58634, 6.86651, 7.74497, 8.77955", \ + "5.88517, 6.22316, 6.58284, 6.87113, 7.81051, 8.76869", \ + "5.87821, 6.22284, 6.4982, 6.95435, 7.81282, 8.69804", \ + "5.88411, 6.18907, 6.58984, 6.86912, 7.80856, 8.6853", \ + "5.87284, 6.18651, 6.59515, 6.94838, 7.78048, 8.77028", \ + "5.88364, 6.21863, 6.54529, 6.94828, 7.77493, 8.77899", \ + "5.8695, 6.1759, 6.47711, 6.86182, 7.75041, 8.65488" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "2.46806, 2.4692, 2.46808, 2.46958, 2.46546, 2.46625", \ + "2.46857, 2.46978, 2.4699, 2.47009, 2.46877, 2.46854", \ + "2.46832, 2.46947, 2.46835, 2.46984, 2.46577, 2.46828", \ + "2.46827, 2.46942, 2.46831, 2.4698, 2.46572, 2.46783", \ + "2.46585, 2.467, 2.46589, 2.46738, 2.46329, 2.46561", \ + "2.46836, 2.47019, 2.46818, 2.46961, 2.46618, 2.46909", \ + "2.47107, 2.4695, 2.47052, 2.47047, 2.46611, 2.46821" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.0327046, 0.0327073, 0.0327104, 0.0327079, 0.0327057, 0.0327063", \ + "0.034939, 0.0349418, 0.0349448, 0.0349414, 0.0349427, 0.0349408", \ + "0.042263, 0.0422658, 0.0422651, 0.0422694, 0.0422675, 0.0422645", \ + "0.0638735, 0.0638751, 0.0638788, 0.0638756, 0.063878, 0.0638756", \ + "0.111307, 0.111309, 0.111313, 0.111313, 0.111309, 0.111308", \ + "0.212613, 0.212616, 0.212616, 0.212619, 0.212615, 0.212614", \ + "0.41109, 0.411132, 0.411088, 0.411151, 0.411144, 0.41106" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.057439, 0.0574367, 0.0574353, 0.0574386, 0.0574323, 0.0574271", \ + "0.0584189, 0.058415, 0.0584136, 0.0584177, 0.0584137, 0.0584072", \ + "0.0621469, 0.0621448, 0.0621435, 0.0621468, 0.0621403, 0.0621361", \ + "0.0737419, 0.0737398, 0.0737384, 0.0737419, 0.0737351, 0.0737333", \ + "0.0977139, 0.0977119, 0.0977145, 0.0977141, 0.0977057, 0.0977023", \ + "0.149923, 0.149795, 0.14991, 0.149964, 0.149967, 0.149768", \ + "0.256746, 0.256888, 0.256851, 0.256796, 0.256936, 0.256721" \ + ); + } + } + } + pin (c2p) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.016; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0290076; + rise_capacitance : 0.0292587; + rise_capacitance_range (0.0236619, 0.0346386); + fall_capacitance : 0.0287565; + fall_capacitance_range (0.0243228, 0.0305278); + internal_power () { + when : "!c2p_en"; + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0, 0, 0, 0, 0, 8.23238e-07, 8.31392e-07" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0, 0, 0, 0, 0, -8.23238e-07, -8.31392e-07" \ + ); + } + } + internal_power () { + when : "!c2p_en"; + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0267582, -0.0276741, -0.0279762, -0.0282985, -0.0283981, -0.0283991, -0.0287077" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0338101, 0.0335328, 0.0334616, 0.0334599, 0.0334557, 0.0331343, 0.0332226" \ + ); + } + } + internal_power () { + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0, 0, 0, 0, 0, 8.23238e-07, 8.31392e-07" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0, 0, 0, 0, 0, -8.23238e-07, -8.31392e-07" \ + ); + } + } + internal_power () { + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0267582, -0.0276741, -0.0279762, -0.0282985, -0.0283981, -0.0283991, -0.0287077" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0338101, 0.0335328, 0.0334616, 0.0334599, 0.0334557, 0.0331343, 0.0332226" \ + ); + } + } + } + pin (c2p_en) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.011; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0272264; + rise_capacitance : 0.028292; + rise_capacitance_range (0.0235885, 0.0350038); + fall_capacitance : 0.0261608; + fall_capacitance_range (0.0228294, 0.0304588); + } + } + cell (sg13g2_IOPadTriOut30mA) { + pad_cell : true; + area : 14400; + cell_footprint : "tri_out"; + pad_drivers : 1; + bond_pads : 1; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 281.639; + when : "!c2p_en&!c2p"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 3944.65; + when : "!c2p_en&!c2p"; + related_pg_pin : vdd; + } + leakage_power () { + value : 281.639; + when : "!c2p_en&c2p"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 5232.23; + when : "!c2p_en&c2p"; + related_pg_pin : vdd; + } + leakage_power () { + value : 420.062; + when : "c2p_en&c2p&pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 5697.24; + when : "c2p_en&c2p&pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 864.978; + when : "c2p_en&!c2p&!pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 4690.53; + when : "c2p_en&!c2p&!pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 462.08; + related_pg_pin : iovdd; + } + leakage_power () { + value : 4891.16; + related_pg_pin : vdd; + } + pin (pad) { + direction : "output"; + is_pad : true; + function : "c2p"; + three_state : "c2p_en'"; + drive_current : 30; + output_voltage : "pad"; + related_ground_pin : iovss; + related_power_pin : iovdd; + max_capacitance : 4.71391; + capacitance : 0.331669; + rise_capacitance : 0.33092; + rise_capacitance_range (0.33092, 0.33092); + fall_capacitance : 0.332418; + fall_capacitance_range (0.332418, 0.332418); + timing () { + related_pin : "c2p"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.65136, 1.79285, 1.90823, 2.00857, 2.26213, 2.48191", \ + "1.66305, 1.80475, 1.9202, 2.02064, 2.2738, 2.49356", \ + "1.67009, 1.8117, 1.92696, 2.02724, 2.28058, 2.50007", \ + "1.68201, 1.82366, 1.93883, 2.03887, 2.2921, 2.51198", \ + "1.68982, 1.83134, 1.94666, 2.04682, 2.30159, 2.51999", \ + "1.693, 1.83508, 1.95035, 2.05064, 2.30415, 2.52122", \ + "1.69301, 1.83509, 1.95036, 2.05065, 2.30416, 2.52218" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.490431, 0.657569, 0.800318, 0.928399, 1.28129, 1.624", \ + "0.490432, 0.65757, 0.800319, 0.928943, 1.2813, 1.62401", \ + "0.490433, 0.657571, 0.80032, 0.928944, 1.28131, 1.62402", \ + "0.490434, 0.657572, 0.800321, 0.928945, 1.28132, 1.6241", \ + "0.490435, 0.657683, 0.800322, 0.928946, 1.28514, 1.62411", \ + "0.490938, 0.658888, 0.800323, 0.928947, 1.28515, 1.62412", \ + "0.493341, 0.661157, 0.802115, 0.930807, 1.28516, 1.62464" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.30984, 1.39597, 1.47426, 1.5478, 1.74479, 1.92472", \ + "1.32633, 1.41241, 1.49005, 1.56306, 1.76105, 1.94008", \ + "1.34057, 1.42676, 1.50306, 1.57718, 1.77409, 1.95484", \ + "1.36984, 1.45598, 1.53226, 1.60637, 1.80327, 1.984", \ + "1.41459, 1.50091, 1.57719, 1.65129, 1.85081, 2.02897", \ + "1.49201, 1.57827, 1.65631, 1.72884, 1.92709, 2.10649", \ + "1.62596, 1.71295, 1.79347, 1.86494, 2.0638, 2.24274" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.92356, 0.980558, 1.05675, 1.13629, 1.38396, 1.6426", \ + "0.928687, 0.98512, 1.0603, 1.14091, 1.38717, 1.64611", \ + "0.932405, 0.988628, 1.06383, 1.1439, 1.38827, 1.64828", \ + "0.935119, 0.990996, 1.06605, 1.14581, 1.3902, 1.6499", \ + "0.93512, 0.990997, 1.06606, 1.14582, 1.39021, 1.64991", \ + "0.935121, 0.990998, 1.06607, 1.14583, 1.39022, 1.64992", \ + "0.935122, 0.990999, 1.06608, 1.14584, 1.39023, 1.64993" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : negative_unate; + timing_type : three_state_disable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.22587, 1.22588, 1.22589, 1.2259, 1.22591, 1.22592", \ + "1.24397, 1.24398, 1.24399, 1.244, 1.24401, 1.24402", \ + "1.25992, 1.25993, 1.25994, 1.25995, 1.25996, 1.25997", \ + "1.27849, 1.2785, 1.27851, 1.27852, 1.27853, 1.27854", \ + "1.30868, 1.30869, 1.3087, 1.30871, 1.30872, 1.30873", \ + "1.35317, 1.35318, 1.35319, 1.3532, 1.35321, 1.35322", \ + "1.44344, 1.44345, 1.44346, 1.44347, 1.44348, 1.44349" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.22587, 1.22588, 1.22589, 1.2259, 1.22591, 1.22592", \ + "1.24397, 1.24398, 1.24399, 1.244, 1.24401, 1.24402", \ + "1.25992, 1.25993, 1.25994, 1.25995, 1.25996, 1.25997", \ + "1.27849, 1.2785, 1.27851, 1.27852, 1.27853, 1.27854", \ + "1.30868, 1.30869, 1.3087, 1.30871, 1.30872, 1.30873", \ + "1.35317, 1.35318, 1.35319, 1.3532, 1.35321, 1.35322", \ + "1.44344, 1.44345, 1.44346, 1.44347, 1.44348, 1.44349" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.6161, 1.61611, 1.61612, 1.61613, 1.61614, 1.61615", \ + "1.63592, 1.63593, 1.63594, 1.63595, 1.63596, 1.63597", \ + "1.65413, 1.65414, 1.65415, 1.65416, 1.65417, 1.65418", \ + "1.67889, 1.6789, 1.67891, 1.67892, 1.67893, 1.67894", \ + "1.72354, 1.72355, 1.72356, 1.72357, 1.72358, 1.72359", \ + "1.78462, 1.78463, 1.78464, 1.78465, 1.78466, 1.78467", \ + "1.87229, 1.8723, 1.87231, 1.87232, 1.87233, 1.87234" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.6161, 1.61611, 1.61612, 1.61613, 1.61614, 1.61615", \ + "1.63592, 1.63593, 1.63594, 1.63595, 1.63596, 1.63597", \ + "1.65413, 1.65414, 1.65415, 1.65416, 1.65417, 1.65418", \ + "1.67889, 1.6789, 1.67891, 1.67892, 1.67893, 1.67894", \ + "1.72354, 1.72355, 1.72356, 1.72357, 1.72358, 1.72359", \ + "1.78462, 1.78463, 1.78464, 1.78465, 1.78466, 1.78467", \ + "1.87229, 1.8723, 1.87231, 1.87232, 1.87233, 1.87234" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : positive_unate; + timing_type : three_state_enable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.62274, 1.78165, 1.90605, 2.01348, 2.28101, 2.51018", \ + "1.63597, 1.7947, 1.91978, 2.02655, 2.2943, 2.52327", \ + "1.64418, 1.80309, 1.92816, 2.03492, 2.30237, 2.53162", \ + "1.65585, 1.81526, 1.939, 2.0466, 2.31424, 2.54334", \ + "1.66952, 1.82843, 1.95337, 2.06012, 2.32767, 2.5573", \ + "1.68091, 1.84029, 1.96398, 2.07199, 2.3368, 2.56843", \ + "1.68938, 1.84873, 1.97272, 2.07961, 2.34719, 2.57383" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.517536, 0.664656, 0.793824, 0.915049, 1.25577, 1.59179", \ + "0.517742, 0.664818, 0.794334, 0.915189, 1.25604, 1.59186", \ + "0.517743, 0.664819, 0.794335, 0.91519, 1.25605, 1.59187", \ + "0.517744, 0.66482, 0.794336, 0.915191, 1.25606, 1.59188", \ + "0.517745, 0.664821, 0.794337, 0.915223, 1.25607, 1.59204", \ + "0.517746, 0.664822, 0.794338, 0.915465, 1.25608, 1.59205", \ + "0.517747, 0.664823, 0.794339, 0.915749, 1.25689, 1.59206" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.913477, 1.03391, 1.13216, 1.22028, 1.45084, 1.65535", \ + "0.926281, 1.04612, 1.14486, 1.23299, 1.46355, 1.67113", \ + "0.932723, 1.05285, 1.15156, 1.23833, 1.46973, 1.67729", \ + "0.941982, 1.06213, 1.16082, 1.24759, 1.47908, 1.68655", \ + "0.948732, 1.06886, 1.16749, 1.25525, 1.48581, 1.69303", \ + "0.954002, 1.07405, 1.17325, 1.25986, 1.49096, 1.69838", \ + "0.954003, 1.07406, 1.17326, 1.25987, 1.49097, 1.69839" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.37096, 0.494606, 0.606845, 0.715326, 1.02889, 1.33938", \ + "0.371129, 0.494607, 0.60688, 0.715355, 1.02896, 1.34143", \ + "0.371279, 0.49466, 0.607282, 0.715356, 1.02897, 1.34144", \ + "0.371281, 0.494683, 0.607283, 0.715357, 1.02898, 1.34145", \ + "0.371282, 0.494684, 0.607284, 0.715358, 1.02899, 1.34146", \ + "0.371283, 0.494685, 0.607285, 0.715359, 1.02983, 1.34201", \ + "0.371284, 0.494686, 0.607286, 0.716636, 1.02984, 1.34202" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "10.1247, 9.85651, 9.78209, 9.72378, 9.56132, 9.66365", \ + "10.128, 9.88045, 9.80612, 9.7777, 9.5665, 9.67933", \ + "10.1005, 9.90754, 9.80417, 9.68873, 9.56828, 9.66359", \ + "10.1191, 9.92134, 9.82595, 9.75932, 9.57251, 9.68817", \ + "10.134, 9.90026, 9.80021, 9.73965, 9.79305, 9.67009", \ + "10.0859, 9.8663, 9.76074, 9.70312, 9.52568, 9.41731", \ + "9.98951, 9.79502, 9.68784, 9.69339, 9.48311, 9.61175" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "55.3539, 52.0435, 49.2498, 46.7916, 41.2989, 37.3427", \ + "55.7785, 52.4406, 49.6185, 47.2001, 41.6195, 37.6622", \ + "56.0743, 52.7007, 49.903, 47.4665, 41.8616, 37.8775", \ + "56.2905, 52.9059, 50.1011, 47.656, 42.0345, 38.0351", \ + "56.189, 52.792, 49.9936, 47.5626, 41.8895, 37.947", \ + "55.7527, 52.4107, 49.6469, 47.2023, 41.6306, 37.6622", \ + "54.4347, 51.1397, 48.4156, 46.037, 40.6234, 36.764" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.0762027, 0.0762033, 0.0762034, 0.0762057, 0.0761999, 0.0762042", \ + "0.075718, 0.0757183, 0.0757196, 0.0757178, 0.075715, 0.075717", \ + "0.0804571, 0.0804563, 0.0804572, 0.0804574, 0.080454, 0.0804585", \ + "0.0969696, 0.0969704, 0.0969686, 0.0969684, 0.0969667, 0.0969682", \ + "0.139073, 0.139073, 0.139074, 0.139075, 0.139075, 0.139074", \ + "0.232362, 0.232363, 0.232362, 0.232361, 0.232362, 0.232362", \ + "0.426649, 0.426635, 0.4266, 0.426636, 0.426596, 0.426605" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.189367, 0.189365, 0.189364, 0.189365, 0.189366, 0.189365", \ + "0.189049, 0.189052, 0.189048, 0.189047, 0.189053, 0.189053", \ + "0.194817, 0.194814, 0.194817, 0.194814, 0.194815, 0.194817", \ + "0.213879, 0.213879, 0.213877, 0.213876, 0.213877, 0.213879", \ + "0.256233, 0.256236, 0.256233, 0.256234, 0.256237, 0.256234", \ + "0.34836, 0.348552, 0.348598, 0.34861, 0.348581, 0.348595", \ + "0.540983, 0.540961, 0.540772, 0.540939, 0.540807, 0.541069" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "9.04711, 9.3651, 9.71378, 10.1251, 11.146, 12.2569", \ + "9.04767, 9.35957, 9.74272, 10.1199, 11.1489, 12.2499", \ + "9.04568, 9.36341, 9.74705, 10.1242, 11.1426, 12.2565", \ + "9.03928, 9.37723, 9.63385, 10.1214, 11.1525, 12.258", \ + "9.04086, 9.36073, 9.73764, 10.1145, 11.1299, 12.2751", \ + "9.03308, 9.36939, 9.64976, 10.117, 10.937, 12.2524", \ + "9.03155, 9.37315, 9.7115, 10.0809, 11.0866, 12.0429" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "4.13727, 4.14021, 4.14131, 4.14386, 4.14476, 4.14538", \ + "4.13771, 4.13908, 4.14143, 4.14401, 4.14508, 4.14318", \ + "4.13885, 4.14066, 4.14272, 4.14324, 4.14507, 4.14308", \ + "4.13879, 4.14063, 4.14266, 4.1432, 4.14524, 4.14303", \ + "4.13598, 4.13777, 4.13949, 4.14135, 4.14242, 4.13948", \ + "4.13662, 4.13855, 4.14212, 4.142, 4.14452, 4.14221", \ + "4.13839, 4.14351, 4.14272, 4.14506, 4.14475, 4.14509" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.0326881, 0.0326879, 0.0326883, 0.0326895, 0.0326919, 0.0326939", \ + "0.0349204, 0.0349204, 0.0349209, 0.0349217, 0.0349244, 0.0349263", \ + "0.042247, 0.0422468, 0.0422474, 0.0422484, 0.0422511, 0.0422527", \ + "0.0638555, 0.0638554, 0.0638558, 0.0638567, 0.0638589, 0.0638609", \ + "0.111294, 0.111295, 0.111295, 0.111296, 0.111299, 0.111301", \ + "0.208703, 0.208703, 0.208703, 0.208704, 0.208704, 0.208709", \ + "0.407651, 0.407652, 0.407655, 0.407597, 0.40759, 0.40765" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.0573606, 0.0573585, 0.057357, 0.057357, 0.0573546, 0.0573523", \ + "0.0583261, 0.0583196, 0.0583232, 0.0583231, 0.0583187, 0.0583169", \ + "0.0620584, 0.0620557, 0.0620571, 0.0620518, 0.0620528, 0.062049", \ + "0.073644, 0.0736414, 0.0736426, 0.0736374, 0.0736383, 0.0736345", \ + "0.0976266, 0.0976223, 0.0976254, 0.0976228, 0.0976181, 0.0976207", \ + "0.149981, 0.149938, 0.150014, 0.149954, 0.149811, 0.149815", \ + "0.257232, 0.257145, 0.257221, 0.25724, 0.257282, 0.257232" \ + ); + } + } + } + pin (c2p) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.016; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0290076; + rise_capacitance : 0.0292588; + rise_capacitance_range (0.0236622, 0.0346388); + fall_capacitance : 0.0287564; + fall_capacitance_range (0.0243229, 0.0305277); + internal_power () { + when : "!c2p_en"; + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0, 0, 0.000364667, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0, 0, -0.000364667, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + when : "!c2p_en"; + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0267582, -0.0276731, -0.0279767, -0.0282984, -0.028398, -0.0283991, -0.0287077" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0338115, 0.0335334, 0.0334512, 0.0334603, 0.0334553, 0.033134, 0.0332224" \ + ); + } + } + internal_power () { + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0, 0, 0.000364667, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0, 0, -0.000364667, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0267582, -0.0276731, -0.0279767, -0.0282984, -0.028398, -0.0283991, -0.0287077" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.0338115, 0.0335334, 0.0334512, 0.0334603, 0.0334553, 0.033134, 0.0332224" \ + ); + } + } + } + pin (c2p_en) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.011; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0272223; + rise_capacitance : 0.0282838; + rise_capacitance_range (0.0235886, 0.03503); + fall_capacitance : 0.0261608; + fall_capacitance_range (0.0228293, 0.0304377); + } + } + cell (sg13g2_IOPadTriOut4mA) { + pad_cell : true; + area : 14400; + cell_footprint : "tri_out"; + pad_drivers : 1; + bond_pads : 1; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 13.8342; + when : "!c2p_en&!c2p"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 3944.54; + when : "!c2p_en&!c2p"; + related_pg_pin : vdd; + } + leakage_power () { + value : 13.8342; + when : "!c2p_en&c2p"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 5232.1; + when : "!c2p_en&c2p"; + related_pg_pin : vdd; + } + leakage_power () { + value : 62.7147; + when : "c2p_en&c2p&pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 5697.08; + when : "c2p_en&c2p&pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 117.701; + when : "c2p_en&!c2p&!pad"; + related_pg_pin : iovdd; + } + leakage_power () { + value : 4690.13; + when : "c2p_en&!c2p&!pad"; + related_pg_pin : vdd; + } + leakage_power () { + value : 52.021; + related_pg_pin : iovdd; + } + leakage_power () { + value : 4890.96; + related_pg_pin : vdd; + } + pin (pad) { + direction : "output"; + is_pad : true; + function : "c2p"; + three_state : "c2p_en'"; + drive_current : 4; + output_voltage : "pad"; + related_ground_pin : iovss; + related_power_pin : iovdd; + max_capacitance : 1.11192; + capacitance : 0.163207; + rise_capacitance : 0.167318; + rise_capacitance_range (0.167318, 0.167318); + fall_capacitance : 0.159097; + fall_capacitance_range (0.159097, 0.159097); + timing () { + related_pin : "c2p"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.4434, 1.8798, 2.31301, 2.746, 4.0429, 5.33849", \ + "1.45515, 1.89127, 2.32453, 2.75751, 4.05443, 5.35032", \ + "1.46193, 1.89804, 2.3313, 2.76426, 4.06117, 5.35712", \ + "1.47026, 1.90619, 2.33964, 2.77263, 4.06946, 5.36444", \ + "1.48114, 1.91711, 2.35042, 2.78339, 4.08035, 5.37758", \ + "1.48772, 1.92379, 2.35752, 2.7904, 4.0873, 5.38499", \ + "1.48773, 1.9238, 2.35753, 2.79041, 4.08731, 5.385" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.10118, 1.98835, 2.88457, 3.78277, 6.48434, 9.18184", \ + "1.10119, 1.98851, 2.88458, 3.78278, 6.48435, 9.18259", \ + "1.1012, 1.98894, 2.88459, 3.78373, 6.48436, 9.1826", \ + "1.10121, 1.98895, 2.8846, 3.78374, 6.48437, 9.18261", \ + "1.10122, 1.98921, 2.88461, 3.78375, 6.48438, 9.18418", \ + "1.10123, 1.98922, 2.88462, 3.78376, 6.48439, 9.18419", \ + "1.10143, 1.98923, 2.88463, 3.78377, 6.4844, 9.18501" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.07065, 1.49944, 1.92706, 2.35476, 3.63673, 4.91963", \ + "1.08538, 1.514, 1.94146, 2.3691, 3.65096, 4.93267", \ + "1.09819, 1.52667, 1.95392, 2.38152, 3.66321, 4.94626", \ + "1.1265, 1.55481, 1.98202, 2.40932, 3.69129, 4.97424", \ + "1.17208, 1.60059, 2.0278, 2.45542, 3.73717, 5.02012", \ + "1.25095, 1.67999, 2.10745, 2.53508, 3.81679, 5.09854", \ + "1.39414, 1.82361, 2.2513, 2.67952, 3.96141, 5.24335" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.0016, 1.82584, 2.65436, 3.48507, 5.97982, 8.4795", \ + "1.00219, 1.82585, 2.65438, 3.48532, 5.97983, 8.47951", \ + "1.0022, 1.82586, 2.65442, 3.48566, 5.98245, 8.47952", \ + "1.00221, 1.82587, 2.65443, 3.48567, 5.98246, 8.47953", \ + "1.00222, 1.82588, 2.6546, 3.48568, 5.98247, 8.47954", \ + "1.00253, 1.82589, 2.65461, 3.48685, 5.98248, 8.48008", \ + "1.003, 1.8259, 2.65462, 3.48686, 5.98249, 8.483" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : negative_unate; + timing_type : three_state_disable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.841521, 0.841522, 0.841523, 0.841524, 0.841525, 0.841526", \ + "0.858005, 0.858006, 0.858007, 0.858008, 0.858009, 0.85801", \ + "0.866545, 0.866546, 0.866547, 0.866548, 0.866549, 0.86655", \ + "0.892296, 0.892297, 0.892298, 0.892299, 0.8923, 0.892301", \ + "0.924396, 0.924397, 0.924398, 0.924399, 0.9244, 0.924401", \ + "0.973152, 0.973153, 0.973154, 0.973155, 0.973156, 0.973157", \ + "1.04988, 1.04989, 1.0499, 1.04991, 1.04992, 1.04993" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.841521, 0.841522, 0.841523, 0.841524, 0.841525, 0.841526", \ + "0.858005, 0.858006, 0.858007, 0.858008, 0.858009, 0.85801", \ + "0.866545, 0.866546, 0.866547, 0.866548, 0.866549, 0.86655", \ + "0.892296, 0.892297, 0.892298, 0.892299, 0.8923, 0.892301", \ + "0.924396, 0.924397, 0.924398, 0.924399, 0.9244, 0.924401", \ + "0.973152, 0.973153, 0.973154, 0.973155, 0.973156, 0.973157", \ + "1.04988, 1.04989, 1.0499, 1.04991, 1.04992, 1.04993" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.52451, 0.524511, 0.524512, 0.524513, 0.524514, 0.524515", \ + "0.546032, 0.546033, 0.546034, 0.546035, 0.546036, 0.546037", \ + "0.56093, 0.560931, 0.560932, 0.560933, 0.560934, 0.560935", \ + "0.590419, 0.59042, 0.590421, 0.590422, 0.590423, 0.590424", \ + "0.631685, 0.631686, 0.631687, 0.631688, 0.631689, 0.63169", \ + "0.700941, 0.700942, 0.700943, 0.700944, 0.700945, 0.700946", \ + "0.816928, 0.816929, 0.81693, 0.816931, 0.816932, 0.816933" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.52451, 0.524511, 0.524512, 0.524513, 0.524514, 0.524515", \ + "0.546032, 0.546033, 0.546034, 0.546035, 0.546036, 0.546037", \ + "0.56093, 0.560931, 0.560932, 0.560933, 0.560934, 0.560935", \ + "0.590419, 0.59042, 0.590421, 0.590422, 0.590423, 0.590424", \ + "0.631685, 0.631686, 0.631687, 0.631688, 0.631689, 0.63169", \ + "0.700941, 0.700942, 0.700943, 0.700944, 0.700945, 0.700946", \ + "0.816928, 0.816929, 0.81693, 0.816931, 0.816932, 0.816933" \ + ); + } + } + timing () { + related_pin : "c2p_en"; + timing_sense : positive_unate; + timing_type : three_state_enable; + cell_rise (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.45139, 1.90577, 2.35802, 2.80811, 4.16033, 5.51332", \ + "1.46439, 1.91897, 2.37116, 2.82182, 4.17373, 5.52652", \ + "1.4717, 1.92617, 2.37839, 2.82932, 4.18104, 5.53378", \ + "1.48355, 1.93816, 2.39039, 2.84105, 4.19282, 5.54563", \ + "1.4983, 1.95341, 2.40561, 2.85622, 4.20909, 5.56095", \ + "1.51044, 1.96532, 2.41753, 2.86806, 4.21937, 5.57067", \ + "1.5177, 1.97212, 2.42412, 2.87577, 4.22688, 5.57985" \ + ); + } + rise_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.09888, 1.98723, 2.88373, 3.78304, 6.48293, 9.18182", \ + "1.09889, 1.98724, 2.88417, 3.78312, 6.48442, 9.18183", \ + "1.09916, 1.98725, 2.88418, 3.78313, 6.48454, 9.18184", \ + "1.09917, 1.98788, 2.88419, 3.78353, 6.48455, 9.18185", \ + "1.09918, 1.98789, 2.8842, 3.78354, 6.48456, 9.18186", \ + "1.09919, 1.9879, 2.88421, 3.78365, 6.48457, 9.18187", \ + "1.09995, 1.98791, 2.88427, 3.78366, 6.48458, 9.18188" \ + ); + } + cell_fall (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.08992, 1.55924, 2.02707, 2.49435, 3.89545, 5.29613", \ + "1.10239, 1.57168, 2.03953, 2.50681, 3.90792, 5.30861", \ + "1.10893, 1.57825, 2.04607, 2.51335, 3.91445, 5.31514", \ + "1.11764, 1.58696, 2.05479, 2.52207, 3.92317, 5.32385", \ + "1.12477, 1.59411, 2.06192, 2.5292, 3.93031, 5.33099", \ + "1.13035, 1.59975, 2.06745, 2.53482, 3.93585, 5.33655", \ + "1.13036, 1.59976, 2.06746, 2.53483, 3.93586, 5.33656" \ + ); + } + fall_transition (delay_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.996319, 1.82216, 2.65291, 3.48375, 5.98542, 8.48408", \ + "0.99632, 1.82227, 2.65293, 3.48376, 5.98543, 8.48409", \ + "0.996321, 1.82228, 2.65294, 3.48377, 5.98544, 8.4841", \ + "0.996322, 1.82229, 2.65295, 3.48378, 5.98545, 8.48411", \ + "0.996323, 1.8223, 2.65296, 3.48379, 5.98546, 8.48412", \ + "0.996324, 1.82249, 2.65319, 3.48507, 5.98547, 8.48413", \ + "0.997246, 1.82274, 2.65405, 3.48508, 5.98548, 8.48414" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "3.14242, 3.11792, 3.08685, 3.0559, 2.96802, 2.8744", \ + "3.14169, 3.11258, 3.08058, 3.05676, 2.96931, 2.87054", \ + "3.13946, 3.11358, 3.08088, 3.0527, 2.96594, 2.86648", \ + "3.13529, 3.10689, 3.07266, 3.04927, 2.96152, 2.85434", \ + "3.13296, 3.1113, 3.07553, 3.04653, 2.96063, 2.86127", \ + "3.13028, 3.11405, 3.08187, 3.05217, 2.96951, 2.86387", \ + "3.12891, 3.10708, 3.06778, 3.03719, 2.94938, 2.87258" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.83117, 1.81816, 1.81185, 1.80846, 1.80367, 1.80223", \ + "1.84037, 1.82232, 1.81575, 1.81163, 1.80566, 1.80349", \ + "1.84712, 1.82709, 1.81917, 1.8141, 1.80609, 1.80337", \ + "1.85276, 1.83096, 1.82252, 1.81656, 1.80881, 1.80467", \ + "1.84928, 1.82849, 1.82074, 1.81477, 1.80729, 1.80367", \ + "1.84857, 1.82794, 1.82079, 1.81398, 1.81065, 1.80841", \ + "1.82642, 1.81935, 1.81878, 1.81574, 1.81336, 1.8129" \ + ); + } + } + internal_power () { + related_pin : "c2p"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.0762927, 0.0762894, 0.0762853, 0.0762858, 0.0762902, 0.0762893", \ + "0.0758002, 0.0757945, 0.0757909, 0.0757923, 0.075794, 0.0757946", \ + "0.0805407, 0.0805348, 0.080531, 0.0805323, 0.0805351, 0.0805345", \ + "0.0970655, 0.0970584, 0.0970558, 0.0970563, 0.0970574, 0.097058", \ + "0.139152, 0.139148, 0.139143, 0.139145, 0.139146, 0.139146", \ + "0.232525, 0.232519, 0.232519, 0.232519, 0.23252, 0.232522", \ + "0.426212, 0.426189, 0.42626, 0.426171, 0.426258, 0.426154" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.189675, 0.189683, 0.189681, 0.189684, 0.189676, 0.189686", \ + "0.189393, 0.189386, 0.189385, 0.189392, 0.189383, 0.189395", \ + "0.195155, 0.19516, 0.195155, 0.195162, 0.195155, 0.195155", \ + "0.214212, 0.214218, 0.214211, 0.214219, 0.214208, 0.214211", \ + "0.256515, 0.256512, 0.25651, 0.256514, 0.256501, 0.256505", \ + "0.348913, 0.348808, 0.348813, 0.348616, 0.348821, 0.348814", \ + "0.541451, 0.541436, 0.541519, 0.541112, 0.541477, 0.541499" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : iovdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "3.03314, 3.24147, 3.45068, 3.65772, 4.29248, 4.91723", \ + "3.03215, 3.24746, 3.45447, 3.66676, 4.30548, 4.9238", \ + "3.03027, 3.24447, 3.45325, 3.65693, 4.29703, 4.92093", \ + "3.02427, 3.24322, 3.44705, 3.65742, 4.28465, 4.9133", \ + "3.01955, 3.23511, 3.44381, 3.65142, 4.29271, 4.91568", \ + "3.02726, 3.24776, 3.45546, 3.66165, 4.2897, 4.92802", \ + "3.03882, 3.24156, 3.4522, 3.66152, 4.29805, 4.92393" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "1.05078, 1.0497, 1.04977, 1.04868, 1.04812, 1.0482", \ + "1.04987, 1.04955, 1.04892, 1.04788, 1.04726, 1.04731", \ + "1.05064, 1.04956, 1.04964, 1.04856, 1.04798, 1.04806", \ + "1.0499, 1.0488, 1.04883, 1.04773, 1.04717, 1.04727", \ + "1.04747, 1.04629, 1.04666, 1.04537, 1.04478, 1.04484", \ + "1.05065, 1.05094, 1.05058, 1.05043, 1.04937, 1.04948", \ + "1.05023, 1.04852, 1.04945, 1.04846, 1.04779, 1.04775" \ + ); + } + } + internal_power () { + related_pin : "c2p_en"; + related_pg_pin : vdd; + rise_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.0327691, 0.0327644, 0.0327643, 0.032767, 0.032768, 0.032767", \ + "0.0350039, 0.035, 0.0349997, 0.0350007, 0.0350038, 0.035003", \ + "0.0423274, 0.0423235, 0.0423229, 0.0423243, 0.0423285, 0.0423268", \ + "0.0639359, 0.0639317, 0.063932, 0.0639326, 0.0639351, 0.063934", \ + "0.111362, 0.111363, 0.11136, 0.111361, 0.111364, 0.111363", \ + "0.212833, 0.212828, 0.21283, 0.212831, 0.212832, 0.212831", \ + "0.420771, 0.420837, 0.420826, 0.420756, 0.420849, 0.420792" \ + ); + } + fall_power (power_template_7x6_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + index_2 ("1, 2, 3, 4, 7, 10"); + values ( \ + "0.0577047, 0.0577053, 0.057711, 0.0577113, 0.0577084, 0.0577078", \ + "0.0587205, 0.0587208, 0.0587265, 0.0587268, 0.0587242, 0.0587235", \ + "0.0625507, 0.0625514, 0.062557, 0.0625573, 0.0625542, 0.0625535", \ + "0.0740887, 0.0740896, 0.0740955, 0.0740958, 0.074092, 0.0740913", \ + "0.0980043, 0.0980053, 0.0980104, 0.0980103, 0.0980056, 0.0980048", \ + "0.150946, 0.15085, 0.150879, 0.150929, 0.15094, 0.150942", \ + "0.26273, 0.26276, 0.262611, 0.262524, 0.262533, 0.26248" \ + ); + } + } + } + pin (c2p) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.016; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0290077; + rise_capacitance : 0.0292586; + rise_capacitance_range (0.0236619, 0.0346383); + fall_capacitance : 0.0287568; + fall_capacitance_range (0.0243225, 0.0305279); + internal_power () { + when : "!c2p_en"; + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0, 0, 0, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0, 0, 0, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + when : "!c2p_en"; + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0267584, -0.0276732, -0.027976, -0.0282985, -0.028398, -0.0283991, -0.0287077" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.033693, 0.0335283, 0.0334904, 0.0334562, 0.0334601, 0.0331745, 0.0332246" \ + ); + } + } + internal_power () { + related_pg_pin : iovdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0, 0, 0, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0, 0, 0, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + related_pg_pin : vdd; + rise_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "-0.0267584, -0.0276732, -0.027976, -0.0282985, -0.028398, -0.0283991, -0.0287077" \ + ); + } + fall_power (passive_power_template_7x1_16) { + index_1 ("0.02, 0.1, 0.17, 0.33, 0.64, 1.26, 2.5"); + values ( \ + "0.033693, 0.0335283, 0.0334904, 0.0334562, 0.0334601, 0.0331745, 0.0332246" \ + ); + } + } + } + pin (c2p_en) { + direction : "input"; + input_voltage : "core"; + fanout_load : 0.011; + related_ground_pin : vss; + related_power_pin : vdd; + max_transition : 2.5; + capacitance : 0.0272155; + rise_capacitance : 0.0282677; + rise_capacitance_range (0.0235898, 0.034779); + fall_capacitance : 0.0261633; + fall_capacitance_range (0.0228314, 0.0303865); + } + } + cell (sg13g2_IOPadVdd) { + area : 14400; + pad_cell : true; + bond_pads : 1; + dont_touch : true; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + is_pad : true; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + } + leakage_power () { + value : 0; + related_pg_pin : iovdd; + } + leakage_power () { + value : 0; + related_pg_pin : vdd; + } + } + cell (sg13g2_IOPadVss) { + area : 14400; + pad_cell : true; + bond_pads : 1; + dont_touch : true; + pg_pin (iovdd) { + pg_type : primary_power; + voltage_name : "iovdd"; + } + pg_pin (iovss) { + pg_type : primary_ground; + voltage_name : "iovss"; + } + pg_pin (vdd) { + pg_type : primary_power; + voltage_name : "vdd"; + } + pg_pin (vss) { + pg_type : primary_ground; + voltage_name : "vss"; + is_pad : true; + } + leakage_power () { + value : 0; + related_pg_pin : iovdd; + } + leakage_power () { + value : 1.48806; + related_pg_pin : vdd; + } + } +} diff --git a/flow/platforms/ihp-sg13g2/pdn.tcl b/flow/platforms/ihp-sg13g2/pdn.tcl index d433d3c295..99d911feae 100644 --- a/flow/platforms/ihp-sg13g2/pdn.tcl +++ b/flow/platforms/ihp-sg13g2/pdn.tcl @@ -1,11 +1,15 @@ #################################### # global connections #################################### +# standard cells add_global_connection -net {VDD} -pin_pattern {^VDD$} -power add_global_connection -net {VDD} -pin_pattern {^VDDPE$} add_global_connection -net {VDD} -pin_pattern {^VDDCE$} add_global_connection -net {VSS} -pin_pattern {^VSS$} -ground add_global_connection -net {VSS} -pin_pattern {^VSSE$} +# I/O pads +add_global_connection -net {VDD} -pin_pattern {^vdd$} -power +add_global_connection -net {VSS} -pin_pattern {^vss$} -ground global_connect #################################### # voltage domains @@ -21,4 +25,7 @@ add_pdn_stripe -grid {grid} -layer {Metal5} -width {2.200} -pitch {75.6} -of add_pdn_stripe -grid {grid} -layer {TopMetal1} -width {1.800} -pitch {75.6} -offset {13.570} -extend_to_core_ring add_pdn_connect -grid {grid} -layers {Metal1 Metal5} add_pdn_connect -grid {grid} -layers {Metal5 TopMetal1} +# I/O pads +add_pdn_connect -grid {grid} -layers {Metal5 TopMetal2} +add_pdn_connect -grid {grid} -layers {TopMetal1 TopMetal2} #################################### diff --git a/flow/platforms/ihp-sg13g2/sg13g2.lyt b/flow/platforms/ihp-sg13g2/sg13g2.lyt index 1ffafb9380..488e57bfcb 100644 --- a/flow/platforms/ihp-sg13g2/sg13g2.lyt +++ b/flow/platforms/ihp-sg13g2/sg13g2.lyt @@ -20,6 +20,7 @@ sg13g2.lyp true + 0.01,0.005! 1 diff --git a/flow/platforms/ihp-sg13g2/sg13g2_update.py b/flow/platforms/ihp-sg13g2/sg13g2_update.py index 0047d70c11..4ebd2adfee 100644 --- a/flow/platforms/ihp-sg13g2/sg13g2_update.py +++ b/flow/platforms/ihp-sg13g2/sg13g2_update.py @@ -1,5 +1,6 @@ """Module to download latest files from IHP"s Open PDK.""" +# fmt: off # pylint: disable=line-too-long import os import requests @@ -51,11 +52,14 @@ def download_github_file( sram_files = [ + "RM_IHPSG13_1P_1024x16_c2_bm_bist", "RM_IHPSG13_1P_1024x64_c2_bm_bist", - "RM_IHPSG13_1P_1024x64_c2_bm_bist", + "RM_IHPSG13_1P_1024x8_c2_bm_bist", "RM_IHPSG13_1P_2048x64_c2_bm_bist", "RM_IHPSG13_1P_256x48_c2_bm_bist", "RM_IHPSG13_1P_256x64_c2_bm_bist", + "RM_IHPSG13_1P_4096x16_c3_bm_bist", + "RM_IHPSG13_1P_4096x8_c3_bm_bist", "RM_IHPSG13_1P_512x64_c2_bm_bist", "RM_IHPSG13_1P_64x64_c2_bm_bist", ] @@ -68,32 +72,25 @@ def download_github_file( # Klayout download_github_file("ihp-sg13g2/libs.tech/klayout/tech/sg13g2.lyp") download_github_file("ihp-sg13g2/libs.tech/klayout/tech/sg13g2.lyt") -download_github_file("ihp-sg13g2/libs.tech/klayout/tech/drc/sg13g2.lydrc", "drc") +download_github_file("ihp-sg13g2/libs.tech/klayout/tech/drc/sg13g2_minimal.lydrc", "drc") +download_github_file("ihp-sg13g2/libs.tech/klayout/tech/drc/sg13g2_maximal.lydrc", "drc") # LIB -download_github_file( - "ihp-sg13g2/libs.ref/sg13g2_stdcell/lib/sg13g2_stdcell_slow_1p35V_125C.lib", "lib" -) -download_github_file( - "ihp-sg13g2/libs.ref/sg13g2_stdcell/lib/sg13g2_stdcell_slow_1p08V_125C.lib", "lib" -) -download_github_file( - "ihp-sg13g2/libs.ref/sg13g2_stdcell/lib/sg13g2_stdcell_fast_1p32V_m40C.lib", "lib" -) -download_github_file( - "ihp-sg13g2/libs.ref/sg13g2_stdcell/lib/sg13g2_stdcell_fast_1p65V_m40C.lib", "lib" -) -download_github_file( - "ihp-sg13g2/libs.ref/sg13g2_stdcell/lib/sg13g2_stdcell_typ_1p20V_25C.lib", "lib" -) -download_github_file( - "ihp-sg13g2/libs.ref/sg13g2_stdcell/lib/sg13g2_stdcell_typ_1p50V_25C.lib", "lib" -) -download_github_file("ihp-sg13g2/libs.ref/sg13g2_io/liberty/sg13g2_io_dummy.lib", "lib") +download_github_file("ihp-sg13g2/libs.ref/sg13g2_stdcell/lib/sg13g2_stdcell_slow_1p35V_125C.lib", "lib") +download_github_file("ihp-sg13g2/libs.ref/sg13g2_stdcell/lib/sg13g2_stdcell_slow_1p08V_125C.lib", "lib") +download_github_file("ihp-sg13g2/libs.ref/sg13g2_stdcell/lib/sg13g2_stdcell_fast_1p32V_m40C.lib", "lib") +download_github_file("ihp-sg13g2/libs.ref/sg13g2_stdcell/lib/sg13g2_stdcell_fast_1p65V_m40C.lib", "lib") +download_github_file("ihp-sg13g2/libs.ref/sg13g2_stdcell/lib/sg13g2_stdcell_typ_1p20V_25C.lib", "lib") +download_github_file("ihp-sg13g2/libs.ref/sg13g2_stdcell/lib/sg13g2_stdcell_typ_1p50V_25C.lib", "lib") +download_github_file("ihp-sg13g2/libs.ref/sg13g2_io/lib/sg13g2_io_dummy.lib", "lib") +download_github_file("ihp-sg13g2/libs.ref/sg13g2_io/lib/sg13g2_io_fast_1p32V_3p6V_m40C.lib", "lib") +download_github_file("ihp-sg13g2/libs.ref/sg13g2_io/lib/sg13g2_io_fast_1p65V_3p6V_m40C.lib", "lib") +download_github_file("ihp-sg13g2/libs.ref/sg13g2_io/lib/sg13g2_io_slow_1p08V_3p0V_125C.lib", "lib") +download_github_file("ihp-sg13g2/libs.ref/sg13g2_io/lib/sg13g2_io_slow_1p35V_3p0V_125C.lib", "lib") +download_github_file("ihp-sg13g2/libs.ref/sg13g2_io/lib/sg13g2_io_typ_1p2V_3p3V_25C.lib", "lib") +download_github_file("ihp-sg13g2/libs.ref/sg13g2_io/lib/sg13g2_io_typ_1p5V_3p3V_25C.lib", "lib") for sram in sram_files: for corner in sram_lib_corners: - download_github_file( - f"ihp-sg13g2/libs.ref/sg13g2_sram/lib/{sram}_{corner}.lib", "lib" - ) + download_github_file(f"ihp-sg13g2/libs.ref/sg13g2_sram/lib/{sram}_{corner}.lib", "lib") # GDS download_github_file("ihp-sg13g2/libs.ref/sg13g2_stdcell/gds/sg13g2_stdcell.gds", "gds") download_github_file("ihp-sg13g2/libs.ref/sg13g2_io/gds/sg13g2_io.gds", "gds") @@ -106,14 +103,12 @@ def download_github_file( for sram in sram_files: download_github_file(f"ihp-sg13g2/libs.ref/sg13g2_sram/lef/{sram}.lef", "lef") # Verilog -download_github_file( - "ihp-sg13g2/libs.ref/sg13g2_stdcell/verilog/sg13g2_stdcell.v", "verilog" -) +download_github_file("ihp-sg13g2/libs.ref/sg13g2_stdcell/verilog/sg13g2_stdcell.v", "verilog") download_github_file("ihp-sg13g2/libs.ref/sg13g2_io/verilog/sg13g2_io.v", "verilog") for sram in sram_files: download_github_file(f"ihp-sg13g2/libs.ref/sg13g2_sram/verilog/{sram}.v", "verilog") # CDL download_github_file("ihp-sg13g2/libs.ref/sg13g2_stdcell/cdl/sg13g2_stdcell.cdl", "cdl") -download_github_file("ihp-sg13g2/libs.ref/sg13g2_io/cdl/sg13g2_iocell.cdl", "cdl") +download_github_file("ihp-sg13g2/libs.ref/sg13g2_io/cdl/sg13g2_io.cdl", "cdl") for sram in sram_files: download_github_file(f"ihp-sg13g2/libs.ref/sg13g2_sram/cdl/{sram}.cdl", "cdl") diff --git a/flow/platforms/ihp-sg13g2/verilog/RM_IHPSG13_1P_1024x16_c2_bm_bist.v b/flow/platforms/ihp-sg13g2/verilog/RM_IHPSG13_1P_1024x16_c2_bm_bist.v new file mode 100644 index 0000000000..9f324fbaec --- /dev/null +++ b/flow/platforms/ihp-sg13g2/verilog/RM_IHPSG13_1P_1024x16_c2_bm_bist.v @@ -0,0 +1,175 @@ +// ------------------------------------------------------ +// +// Copyright 2024 IHP PDK Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// Generated on Fri Jul 19 08:58:12 2024 +// +// ------------------------------------------------------ +`celldefine +module RM_IHPSG13_1P_1024x16_c2_bm_bist ( + A_CLK, + A_MEN, + A_WEN, + A_REN, + A_ADDR, + A_DIN, + A_DLY, + A_DOUT, + A_BM, + A_BIST_CLK, + A_BIST_EN, + A_BIST_MEN, + A_BIST_WEN, + A_BIST_REN, + A_BIST_ADDR, + A_BIST_DIN, + A_BIST_BM +); + + input A_CLK; + input A_MEN; + input A_WEN; + input A_REN; + input [9:0] A_ADDR; + input [15:0] A_DIN; + input A_DLY; + output [15:0] A_DOUT; + input [15:0] A_BM; + input A_BIST_CLK; + input A_BIST_EN; + input A_BIST_MEN; + input A_BIST_WEN; + input A_BIST_REN; + input [9:0] A_BIST_ADDR; + input [15:0] A_BIST_DIN; + input [15:0] A_BIST_BM; + + +`ifdef FUNCTIONAL // functional // + + + SRAM_1P_behavioral_bm_bist #( + .P_DATA_WIDTH(16), + .P_ADDR_WIDTH(10) + ) i_SRAM_1P_behavioral_bm_bist ( + .A_CLK(A_CLK), + .A_MEN(A_MEN), + .A_WEN(A_WEN), + .A_REN(A_REN), + .A_ADDR(A_ADDR), + .A_DLY(A_DLY), + .A_DIN(A_DIN), + .A_DOUT(A_DOUT), + .A_BM(A_BM), + .A_BIST_CLK(A_BIST_CLK), + .A_BIST_EN(A_BIST_EN), + .A_BIST_MEN(A_BIST_MEN), + .A_BIST_WEN(A_BIST_WEN), + .A_BIST_REN(A_BIST_REN), + .A_BIST_ADDR(A_BIST_ADDR), + .A_BIST_DIN(A_BIST_DIN), + .A_BIST_BM(A_BIST_BM) + ); + +`else + + wire A_CLK_DELAY; + wire A_MEN_DELAY; + wire A_WEN_DELAY; + wire A_REN_DELAY; + wire [9:0] A_ADDR_DELAY; + wire [15:0] A_DIN_DELAY; + wire [15:0] A_BM_DELAY; + wire A_BIST_CLK_DELAY; + wire A_BIST_MEN_DELAY; + wire A_BIST_WEN_DELAY; + wire A_BIST_REN_DELAY; + wire [9:0] A_BIST_ADDR_DELAY; + wire [15:0] A_BIST_DIN_DELAY; + wire [15:0] A_BIST_BM_DELAY; + + reg notifier; + + wire A_RW_ACCESS = (A_WEN || A_REN) && A_MEN; + wire A_W_ACCESS = A_WEN && A_MEN; + wire A_BIST_RW_ACCESS = (A_BIST_WEN || A_BIST_REN) && A_BIST_MEN; + wire A_BIST_W_ACCESS = A_BIST_WEN && A_BIST_MEN; + + + + SRAM_1P_behavioral_bm_bist #( + .P_DATA_WIDTH(16), + .P_ADDR_WIDTH(10) + ) i_SRAM_1P_behavioral_bm_bist ( + .A_CLK(A_CLK_DELAY), + .A_MEN(A_MEN_DELAY), + .A_WEN(A_WEN_DELAY), + .A_REN(A_REN_DELAY), + .A_ADDR(A_ADDR_DELAY), + .A_DLY(A_DLY), + .A_DIN(A_DIN_DELAY), + .A_DOUT(A_DOUT), + .A_BM(A_BM_DELAY), + .A_BIST_CLK(A_BIST_CLK_DELAY), + .A_BIST_EN(A_BIST_EN), + .A_BIST_MEN(A_BIST_MEN_DELAY), + .A_BIST_WEN(A_BIST_WEN_DELAY), + .A_BIST_REN(A_BIST_REN_DELAY), + .A_BIST_ADDR(A_BIST_ADDR_DELAY), + .A_BIST_DIN(A_BIST_DIN_DELAY), + .A_BIST_BM(A_BIST_BM_DELAY) + ); + + + specify + + (posedge A_CLK *> (A_DOUT : A_DIN)) = (1.0, 1.0); + $width(posedge A_CLK, 1.0,0,notifier); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_MEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_MEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_REN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_REN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_WEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_WEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_MEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_MEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_REN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_REN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_WEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_WEN_DELAY); + $setuphold(posedge A_CLK &&& A_RW_ACCESS, posedge A_ADDR, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_ADDR_DELAY); + $setuphold(posedge A_CLK &&& A_RW_ACCESS, negedge A_ADDR, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_ADDR_DELAY); + + $setuphold(posedge A_CLK &&& A_W_ACCESS, posedge A_DIN, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_DIN_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, negedge A_DIN, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_DIN_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, posedge A_BM, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_BM_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, negedge A_BM, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_BM_DELAY); + (posedge A_BIST_CLK *> (A_DOUT : A_BIST_DIN)) = (1.0, 1.0); + $width(posedge A_BIST_CLK, 1.0,0,notifier); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_MEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_MEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_REN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_REN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_WEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_WEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_MEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_MEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_REN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_REN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_WEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_WEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_RW_ACCESS, posedge A_BIST_ADDR, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_ADDR_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_RW_ACCESS, negedge A_BIST_ADDR, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_ADDR_DELAY); + + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, posedge A_BIST_DIN, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_DIN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, negedge A_BIST_DIN, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_DIN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, posedge A_BIST_BM, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_BM_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, negedge A_BIST_BM, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_BM_DELAY); + + + endspecify + +`endif + +endmodule +`endcelldefine \ No newline at end of file diff --git a/flow/platforms/ihp-sg13g2/verilog/RM_IHPSG13_1P_1024x8_c2_bm_bist.v b/flow/platforms/ihp-sg13g2/verilog/RM_IHPSG13_1P_1024x8_c2_bm_bist.v new file mode 100644 index 0000000000..94a7d0ae2b --- /dev/null +++ b/flow/platforms/ihp-sg13g2/verilog/RM_IHPSG13_1P_1024x8_c2_bm_bist.v @@ -0,0 +1,175 @@ +// ------------------------------------------------------ +// +// Copyright 2024 IHP PDK Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// Generated on Fri Jul 19 09:01:22 2024 +// +// ------------------------------------------------------ +`celldefine +module RM_IHPSG13_1P_1024x8_c2_bm_bist ( + A_CLK, + A_MEN, + A_WEN, + A_REN, + A_ADDR, + A_DIN, + A_DLY, + A_DOUT, + A_BM, + A_BIST_CLK, + A_BIST_EN, + A_BIST_MEN, + A_BIST_WEN, + A_BIST_REN, + A_BIST_ADDR, + A_BIST_DIN, + A_BIST_BM +); + + input A_CLK; + input A_MEN; + input A_WEN; + input A_REN; + input [9:0] A_ADDR; + input [7:0] A_DIN; + input A_DLY; + output [7:0] A_DOUT; + input [7:0] A_BM; + input A_BIST_CLK; + input A_BIST_EN; + input A_BIST_MEN; + input A_BIST_WEN; + input A_BIST_REN; + input [9:0] A_BIST_ADDR; + input [7:0] A_BIST_DIN; + input [7:0] A_BIST_BM; + + +`ifdef FUNCTIONAL // functional // + + + SRAM_1P_behavioral_bm_bist #( + .P_DATA_WIDTH(8), + .P_ADDR_WIDTH(10) + ) i_SRAM_1P_behavioral_bm_bist ( + .A_CLK(A_CLK), + .A_MEN(A_MEN), + .A_WEN(A_WEN), + .A_REN(A_REN), + .A_ADDR(A_ADDR), + .A_DLY(A_DLY), + .A_DIN(A_DIN), + .A_DOUT(A_DOUT), + .A_BM(A_BM), + .A_BIST_CLK(A_BIST_CLK), + .A_BIST_EN(A_BIST_EN), + .A_BIST_MEN(A_BIST_MEN), + .A_BIST_WEN(A_BIST_WEN), + .A_BIST_REN(A_BIST_REN), + .A_BIST_ADDR(A_BIST_ADDR), + .A_BIST_DIN(A_BIST_DIN), + .A_BIST_BM(A_BIST_BM) + ); + +`else + + wire A_CLK_DELAY; + wire A_MEN_DELAY; + wire A_WEN_DELAY; + wire A_REN_DELAY; + wire [9:0] A_ADDR_DELAY; + wire [7:0] A_DIN_DELAY; + wire [7:0] A_BM_DELAY; + wire A_BIST_CLK_DELAY; + wire A_BIST_MEN_DELAY; + wire A_BIST_WEN_DELAY; + wire A_BIST_REN_DELAY; + wire [9:0] A_BIST_ADDR_DELAY; + wire [7:0] A_BIST_DIN_DELAY; + wire [7:0] A_BIST_BM_DELAY; + + reg notifier; + + wire A_RW_ACCESS = (A_WEN || A_REN) && A_MEN; + wire A_W_ACCESS = A_WEN && A_MEN; + wire A_BIST_RW_ACCESS = (A_BIST_WEN || A_BIST_REN) && A_BIST_MEN; + wire A_BIST_W_ACCESS = A_BIST_WEN && A_BIST_MEN; + + + + SRAM_1P_behavioral_bm_bist #( + .P_DATA_WIDTH(8), + .P_ADDR_WIDTH(10) + ) i_SRAM_1P_behavioral_bm_bist ( + .A_CLK(A_CLK_DELAY), + .A_MEN(A_MEN_DELAY), + .A_WEN(A_WEN_DELAY), + .A_REN(A_REN_DELAY), + .A_ADDR(A_ADDR_DELAY), + .A_DLY(A_DLY), + .A_DIN(A_DIN_DELAY), + .A_DOUT(A_DOUT), + .A_BM(A_BM_DELAY), + .A_BIST_CLK(A_BIST_CLK_DELAY), + .A_BIST_EN(A_BIST_EN), + .A_BIST_MEN(A_BIST_MEN_DELAY), + .A_BIST_WEN(A_BIST_WEN_DELAY), + .A_BIST_REN(A_BIST_REN_DELAY), + .A_BIST_ADDR(A_BIST_ADDR_DELAY), + .A_BIST_DIN(A_BIST_DIN_DELAY), + .A_BIST_BM(A_BIST_BM_DELAY) + ); + + + specify + + (posedge A_CLK *> (A_DOUT : A_DIN)) = (1.0, 1.0); + $width(posedge A_CLK, 1.0,0,notifier); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_MEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_MEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_REN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_REN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_WEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_WEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_MEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_MEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_REN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_REN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_WEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_WEN_DELAY); + $setuphold(posedge A_CLK &&& A_RW_ACCESS, posedge A_ADDR, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_ADDR_DELAY); + $setuphold(posedge A_CLK &&& A_RW_ACCESS, negedge A_ADDR, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_ADDR_DELAY); + + $setuphold(posedge A_CLK &&& A_W_ACCESS, posedge A_DIN, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_DIN_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, negedge A_DIN, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_DIN_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, posedge A_BM, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_BM_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, negedge A_BM, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_BM_DELAY); + (posedge A_BIST_CLK *> (A_DOUT : A_BIST_DIN)) = (1.0, 1.0); + $width(posedge A_BIST_CLK, 1.0,0,notifier); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_MEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_MEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_REN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_REN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_WEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_WEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_MEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_MEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_REN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_REN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_WEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_WEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_RW_ACCESS, posedge A_BIST_ADDR, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_ADDR_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_RW_ACCESS, negedge A_BIST_ADDR, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_ADDR_DELAY); + + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, posedge A_BIST_DIN, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_DIN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, negedge A_BIST_DIN, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_DIN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, posedge A_BIST_BM, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_BM_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, negedge A_BIST_BM, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_BM_DELAY); + + + endspecify + +`endif + +endmodule +`endcelldefine \ No newline at end of file diff --git a/flow/platforms/ihp-sg13g2/verilog/RM_IHPSG13_1P_4096x16_c3_bm_bist.v b/flow/platforms/ihp-sg13g2/verilog/RM_IHPSG13_1P_4096x16_c3_bm_bist.v new file mode 100644 index 0000000000..0a96fc0464 --- /dev/null +++ b/flow/platforms/ihp-sg13g2/verilog/RM_IHPSG13_1P_4096x16_c3_bm_bist.v @@ -0,0 +1,175 @@ +// ------------------------------------------------------ +// +// Copyright 2024 IHP PDK Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// Generated on Fri Jul 12 17:37:43 2024 +// +// ------------------------------------------------------ +`celldefine +module RM_IHPSG13_1P_4096x16_c3_bm_bist ( + A_CLK, + A_MEN, + A_WEN, + A_REN, + A_ADDR, + A_DIN, + A_DLY, + A_DOUT, + A_BM, + A_BIST_CLK, + A_BIST_EN, + A_BIST_MEN, + A_BIST_WEN, + A_BIST_REN, + A_BIST_ADDR, + A_BIST_DIN, + A_BIST_BM +); + + input A_CLK; + input A_MEN; + input A_WEN; + input A_REN; + input [11:0] A_ADDR; + input [15:0] A_DIN; + input A_DLY; + output [15:0] A_DOUT; + input [15:0] A_BM; + input A_BIST_CLK; + input A_BIST_EN; + input A_BIST_MEN; + input A_BIST_WEN; + input A_BIST_REN; + input [11:0] A_BIST_ADDR; + input [15:0] A_BIST_DIN; + input [15:0] A_BIST_BM; + + +`ifdef FUNCTIONAL // functional // + + + SRAM_1P_behavioral_bm_bist #( + .P_DATA_WIDTH(16), + .P_ADDR_WIDTH(12) + ) i_SRAM_1P_behavioral_bm_bist ( + .A_CLK(A_CLK), + .A_MEN(A_MEN), + .A_WEN(A_WEN), + .A_REN(A_REN), + .A_ADDR(A_ADDR), + .A_DLY(A_DLY), + .A_DIN(A_DIN), + .A_DOUT(A_DOUT), + .A_BM(A_BM), + .A_BIST_CLK(A_BIST_CLK), + .A_BIST_EN(A_BIST_EN), + .A_BIST_MEN(A_BIST_MEN), + .A_BIST_WEN(A_BIST_WEN), + .A_BIST_REN(A_BIST_REN), + .A_BIST_ADDR(A_BIST_ADDR), + .A_BIST_DIN(A_BIST_DIN), + .A_BIST_BM(A_BIST_BM) + ); + +`else + + wire A_CLK_DELAY; + wire A_MEN_DELAY; + wire A_WEN_DELAY; + wire A_REN_DELAY; + wire [11:0] A_ADDR_DELAY; + wire [15:0] A_DIN_DELAY; + wire [15:0] A_BM_DELAY; + wire A_BIST_CLK_DELAY; + wire A_BIST_MEN_DELAY; + wire A_BIST_WEN_DELAY; + wire A_BIST_REN_DELAY; + wire [11:0] A_BIST_ADDR_DELAY; + wire [15:0] A_BIST_DIN_DELAY; + wire [15:0] A_BIST_BM_DELAY; + + reg notifier; + + wire A_RW_ACCESS = (A_WEN || A_REN) && A_MEN; + wire A_W_ACCESS = A_WEN && A_MEN; + wire A_BIST_RW_ACCESS = (A_BIST_WEN || A_BIST_REN) && A_BIST_MEN; + wire A_BIST_W_ACCESS = A_BIST_WEN && A_BIST_MEN; + + + + SRAM_1P_behavioral_bm_bist #( + .P_DATA_WIDTH(16), + .P_ADDR_WIDTH(12) + ) i_SRAM_1P_behavioral_bm_bist ( + .A_CLK(A_CLK_DELAY), + .A_MEN(A_MEN_DELAY), + .A_WEN(A_WEN_DELAY), + .A_REN(A_REN_DELAY), + .A_ADDR(A_ADDR_DELAY), + .A_DLY(A_DLY), + .A_DIN(A_DIN_DELAY), + .A_DOUT(A_DOUT), + .A_BM(A_BM_DELAY), + .A_BIST_CLK(A_BIST_CLK_DELAY), + .A_BIST_EN(A_BIST_EN), + .A_BIST_MEN(A_BIST_MEN_DELAY), + .A_BIST_WEN(A_BIST_WEN_DELAY), + .A_BIST_REN(A_BIST_REN_DELAY), + .A_BIST_ADDR(A_BIST_ADDR_DELAY), + .A_BIST_DIN(A_BIST_DIN_DELAY), + .A_BIST_BM(A_BIST_BM_DELAY) + ); + + + specify + + (posedge A_CLK *> (A_DOUT : A_DIN)) = (1.0, 1.0); + $width(posedge A_CLK, 1.0,0,notifier); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_MEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_MEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_REN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_REN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_WEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_WEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_MEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_MEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_REN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_REN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_WEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_WEN_DELAY); + $setuphold(posedge A_CLK &&& A_RW_ACCESS, posedge A_ADDR, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_ADDR_DELAY); + $setuphold(posedge A_CLK &&& A_RW_ACCESS, negedge A_ADDR, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_ADDR_DELAY); + + $setuphold(posedge A_CLK &&& A_W_ACCESS, posedge A_DIN, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_DIN_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, negedge A_DIN, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_DIN_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, posedge A_BM, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_BM_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, negedge A_BM, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_BM_DELAY); + (posedge A_BIST_CLK *> (A_DOUT : A_BIST_DIN)) = (1.0, 1.0); + $width(posedge A_BIST_CLK, 1.0,0,notifier); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_MEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_MEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_REN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_REN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_WEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_WEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_MEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_MEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_REN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_REN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_WEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_WEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_RW_ACCESS, posedge A_BIST_ADDR, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_ADDR_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_RW_ACCESS, negedge A_BIST_ADDR, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_ADDR_DELAY); + + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, posedge A_BIST_DIN, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_DIN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, negedge A_BIST_DIN, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_DIN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, posedge A_BIST_BM, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_BM_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, negedge A_BIST_BM, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_BM_DELAY); + + + endspecify + +`endif + +endmodule +`endcelldefine \ No newline at end of file diff --git a/flow/platforms/ihp-sg13g2/verilog/RM_IHPSG13_1P_4096x8_c3_bm_bist.v b/flow/platforms/ihp-sg13g2/verilog/RM_IHPSG13_1P_4096x8_c3_bm_bist.v new file mode 100644 index 0000000000..af3029d5ce --- /dev/null +++ b/flow/platforms/ihp-sg13g2/verilog/RM_IHPSG13_1P_4096x8_c3_bm_bist.v @@ -0,0 +1,175 @@ +// ------------------------------------------------------ +// +// Copyright 2024 IHP PDK Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// Generated on Fri Jul 19 08:59:30 2024 +// +// ------------------------------------------------------ +`celldefine +module RM_IHPSG13_1P_4096x8_c3_bm_bist ( + A_CLK, + A_MEN, + A_WEN, + A_REN, + A_ADDR, + A_DIN, + A_DLY, + A_DOUT, + A_BM, + A_BIST_CLK, + A_BIST_EN, + A_BIST_MEN, + A_BIST_WEN, + A_BIST_REN, + A_BIST_ADDR, + A_BIST_DIN, + A_BIST_BM +); + + input A_CLK; + input A_MEN; + input A_WEN; + input A_REN; + input [11:0] A_ADDR; + input [7:0] A_DIN; + input A_DLY; + output [7:0] A_DOUT; + input [7:0] A_BM; + input A_BIST_CLK; + input A_BIST_EN; + input A_BIST_MEN; + input A_BIST_WEN; + input A_BIST_REN; + input [11:0] A_BIST_ADDR; + input [7:0] A_BIST_DIN; + input [7:0] A_BIST_BM; + + +`ifdef FUNCTIONAL // functional // + + + SRAM_1P_behavioral_bm_bist #( + .P_DATA_WIDTH(8), + .P_ADDR_WIDTH(12) + ) i_SRAM_1P_behavioral_bm_bist ( + .A_CLK(A_CLK), + .A_MEN(A_MEN), + .A_WEN(A_WEN), + .A_REN(A_REN), + .A_ADDR(A_ADDR), + .A_DLY(A_DLY), + .A_DIN(A_DIN), + .A_DOUT(A_DOUT), + .A_BM(A_BM), + .A_BIST_CLK(A_BIST_CLK), + .A_BIST_EN(A_BIST_EN), + .A_BIST_MEN(A_BIST_MEN), + .A_BIST_WEN(A_BIST_WEN), + .A_BIST_REN(A_BIST_REN), + .A_BIST_ADDR(A_BIST_ADDR), + .A_BIST_DIN(A_BIST_DIN), + .A_BIST_BM(A_BIST_BM) + ); + +`else + + wire A_CLK_DELAY; + wire A_MEN_DELAY; + wire A_WEN_DELAY; + wire A_REN_DELAY; + wire [11:0] A_ADDR_DELAY; + wire [7:0] A_DIN_DELAY; + wire [7:0] A_BM_DELAY; + wire A_BIST_CLK_DELAY; + wire A_BIST_MEN_DELAY; + wire A_BIST_WEN_DELAY; + wire A_BIST_REN_DELAY; + wire [11:0] A_BIST_ADDR_DELAY; + wire [7:0] A_BIST_DIN_DELAY; + wire [7:0] A_BIST_BM_DELAY; + + reg notifier; + + wire A_RW_ACCESS = (A_WEN || A_REN) && A_MEN; + wire A_W_ACCESS = A_WEN && A_MEN; + wire A_BIST_RW_ACCESS = (A_BIST_WEN || A_BIST_REN) && A_BIST_MEN; + wire A_BIST_W_ACCESS = A_BIST_WEN && A_BIST_MEN; + + + + SRAM_1P_behavioral_bm_bist #( + .P_DATA_WIDTH(8), + .P_ADDR_WIDTH(12) + ) i_SRAM_1P_behavioral_bm_bist ( + .A_CLK(A_CLK_DELAY), + .A_MEN(A_MEN_DELAY), + .A_WEN(A_WEN_DELAY), + .A_REN(A_REN_DELAY), + .A_ADDR(A_ADDR_DELAY), + .A_DLY(A_DLY), + .A_DIN(A_DIN_DELAY), + .A_DOUT(A_DOUT), + .A_BM(A_BM_DELAY), + .A_BIST_CLK(A_BIST_CLK_DELAY), + .A_BIST_EN(A_BIST_EN), + .A_BIST_MEN(A_BIST_MEN_DELAY), + .A_BIST_WEN(A_BIST_WEN_DELAY), + .A_BIST_REN(A_BIST_REN_DELAY), + .A_BIST_ADDR(A_BIST_ADDR_DELAY), + .A_BIST_DIN(A_BIST_DIN_DELAY), + .A_BIST_BM(A_BIST_BM_DELAY) + ); + + + specify + + (posedge A_CLK *> (A_DOUT : A_DIN)) = (1.0, 1.0); + $width(posedge A_CLK, 1.0,0,notifier); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_MEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_MEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_REN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_REN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_WEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_WEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_MEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_MEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_REN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_REN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_WEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_WEN_DELAY); + $setuphold(posedge A_CLK &&& A_RW_ACCESS, posedge A_ADDR, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_ADDR_DELAY); + $setuphold(posedge A_CLK &&& A_RW_ACCESS, negedge A_ADDR, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_ADDR_DELAY); + + $setuphold(posedge A_CLK &&& A_W_ACCESS, posedge A_DIN, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_DIN_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, negedge A_DIN, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_DIN_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, posedge A_BM, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_BM_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, negedge A_BM, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_BM_DELAY); + (posedge A_BIST_CLK *> (A_DOUT : A_BIST_DIN)) = (1.0, 1.0); + $width(posedge A_BIST_CLK, 1.0,0,notifier); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_MEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_MEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_REN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_REN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_WEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_WEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_MEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_MEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_REN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_REN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_WEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_WEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_RW_ACCESS, posedge A_BIST_ADDR, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_ADDR_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_RW_ACCESS, negedge A_BIST_ADDR, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_ADDR_DELAY); + + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, posedge A_BIST_DIN, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_DIN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, negedge A_BIST_DIN, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_DIN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, posedge A_BIST_BM, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_BM_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, negedge A_BIST_BM, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_BM_DELAY); + + + endspecify + +`endif + +endmodule +`endcelldefine \ No newline at end of file diff --git a/flow/platforms/ihp-sg13g2/verilog/sg13g2_io.v b/flow/platforms/ihp-sg13g2/verilog/sg13g2_io.v index c26682d0f0..1fa45dfc54 100644 --- a/flow/platforms/ihp-sg13g2/verilog/sg13g2_io.v +++ b/flow/platforms/ihp-sg13g2/verilog/sg13g2_io.v @@ -72,7 +72,7 @@ module sg13g2_IOPadIn (pad, p2c); // Timing specify - (p2c => pad) = 0; + (pad => p2c) = 0; endspecify endmodule `endcelldefine @@ -89,7 +89,7 @@ module sg13g2_IOPadOut4mA (pad, c2p); // Timing specify - (pad => c2p) = 0; + (c2p => pad) = 0; endspecify endmodule `endcelldefine @@ -106,7 +106,7 @@ module sg13g2_IOPadOut16mA (pad, c2p); // Timing specify - (pad => c2p) = 0; + (c2p => pad) = 0; endspecify endmodule `endcelldefine @@ -123,7 +123,7 @@ module sg13g2_IOPadOut30mA (pad, c2p); // Timing specify - (pad => c2p) = 0; + (c2p => pad) = 0; endspecify endmodule `endcelldefine @@ -141,7 +141,8 @@ module sg13g2_IOPadTriOut4mA (pad, c2p, c2p_en); // Timing specify - (pad => c2p) = 0; + if (c2p_en == 1'b1) + (c2p => pad) = 0; endspecify endmodule `endcelldefine @@ -159,7 +160,8 @@ module sg13g2_IOPadTriOut16mA (pad, c2p, c2p_en); // Timing specify - (pad => c2p) = 0; + if (c2p_en == 1'b1) + (c2p => pad) = 0; endspecify endmodule `endcelldefine @@ -177,7 +179,8 @@ module sg13g2_IOPadTriOut30mA (pad, c2p, c2p_en); // Timing specify - (pad => c2p) = 0; + if (c2p_en == 1'b1) + (c2p => pad) = 0; endspecify endmodule `endcelldefine @@ -197,8 +200,9 @@ module sg13g2_IOPadInOut4mA (pad, c2p, c2p_en, p2c); // Timing specify - (pad => c2p) = 0; - (p2c => pad) = 0; + if (c2p_en == 1'b1) + (c2p => pad) = 0; + (pad => p2c) = 0; endspecify endmodule `endcelldefine @@ -218,8 +222,9 @@ module sg13g2_IOPadInOut16mA (pad, c2p, c2p_en, p2c); // Timing specify - (pad => c2p) = 0; - (p2c => pad) = 0; + if (c2p_en == 1'b1) + (c2p => pad) = 0; + (pad => p2c) = 0; endspecify endmodule `endcelldefine @@ -239,8 +244,9 @@ module sg13g2_IOPadInOut30mA (pad, c2p, c2p_en, p2c); // Timing specify - (pad => c2p) = 0; - (p2c => pad) = 0; + if (c2p_en == 1'b1) + (c2p => pad) = 0; + (pad => p2c) = 0; endspecify endmodule `endcelldefine diff --git a/flow/scripts/defaults.py b/flow/scripts/defaults.py index 3a74d30b48..3c8f779d39 100755 --- a/flow/scripts/defaults.py +++ b/flow/scripts/defaults.py @@ -12,4 +12,4 @@ for key, value in data.items(): if value.get("default", None) is None: continue - print(f'{key}?={value["default"]}') + print(f'export {key}?={str(value["default"]).replace(" ", "__SPACE__")}') diff --git a/flow/scripts/detail_route.tcl b/flow/scripts/detail_route.tcl index acd6377fa0..7aeafcdb31 100644 --- a/flow/scripts/detail_route.tcl +++ b/flow/scripts/detail_route.tcl @@ -20,7 +20,7 @@ append_env_var additional_args DISABLE_VIA_GEN -disable_via_gen 0 append_env_var additional_args REPAIR_PDN_VIA_LAYER -repair_pdn_vias 1 append_env_var additional_args DETAILED_ROUTE_END_ITERATION -droute_end_iter 1 -append additional_args " -save_guide_updates -verbose 1" +append additional_args " -verbose 1" # DETAILED_ROUTE_ARGS is used when debugging detailed, route, e.g. append # "-droute_end_iter 5" to look at routing violations after only 5 iterations, @@ -46,9 +46,7 @@ set all_args [concat [list \ log_cmd detailed_route {*}$all_args -set_global_routing_layer_adjustment $env(MIN_ROUTING_LAYER)-$env(MAX_ROUTING_LAYER) 0.5 -set_routing_layers -signal $env(MIN_ROUTING_LAYER)-$env(MAX_ROUTING_LAYER) - +fast_route if {![env_var_equals SKIP_ANTENNA_REPAIR_POST_DRT 1]} { set repair_antennas_iters 1 diff --git a/flow/scripts/floorplan.tcl b/flow/scripts/floorplan.tcl index 83cb91e3c9..d2b26dbefe 100644 --- a/flow/scripts/floorplan.tcl +++ b/flow/scripts/floorplan.tcl @@ -113,8 +113,8 @@ if { [env_var_equals REMOVE_ABC_BUFFERS 1] } { ##### Restructure for timing ######### if { [env_var_equals RESYNTH_TIMING_RECOVER 1] } { - repair_design - repair_timing + repair_design_helper + repair_timing_helper # pre restructure area/timing report (ideal clocks) puts "Post synth-opt area" report_design_area @@ -133,8 +133,8 @@ if { [env_var_equals RESYNTH_TIMING_RECOVER 1] } { # post restructure area/timing report (ideal clocks) remove_buffers - repair_design - repair_timing + repair_design_helper + repair_timing_helper puts "Post restructure-opt wns" report_worst_slack -max -digits 3 @@ -194,4 +194,4 @@ if { [env_var_exists_and_non_empty POST_FLOORPLAN_TCL] } { } write_db $::env(RESULTS_DIR)/2_1_floorplan.odb -write_sdc -no_timestamp $::env(RESULTS_DIR)/2_floorplan.sdc +write_sdc -no_timestamp $::env(RESULTS_DIR)/2_1_floorplan.sdc diff --git a/flow/scripts/generate-variables-docs.py b/flow/scripts/generate-variables-docs.py index c1940b326f..3c10c1be24 100755 --- a/flow/scripts/generate-variables-docs.py +++ b/flow/scripts/generate-variables-docs.py @@ -25,7 +25,10 @@ markdown_table = "" markdown_table += "## Variables in alphabetic order\n\n" -table_header = "| Variable | Description | Default |\n| --- | --- | --- |\n" +table_header = """ +| Variable | Description | Default | Deprecated | +| --- | --- | --- | --- | +""" table_rows = "" for key in sorted(data): value = data[key] @@ -33,7 +36,9 @@ table_rows += ( f'| {key}' + f"| {description}" - + f'| {value.get("default", "")} |\n' + + f'| {value.get("default", "")}' + + f'| {"yes" if value.get("deprecated", 0) == 1 else ""}' + + "|\n" ) markdown_table += table_header + table_rows diff --git a/flow/scripts/global_place.tcl b/flow/scripts/global_place.tcl index 6b0f25486a..34ca29e50b 100644 --- a/flow/scripts/global_place.tcl +++ b/flow/scripts/global_place.tcl @@ -7,8 +7,6 @@ set_dont_use $::env(DONT_USE_CELLS) fast_route -source $::env(SCRIPTS_DIR)/set_place_density.tcl - set global_placement_args {} # Parameters for routability mode in global placement @@ -21,20 +19,18 @@ if {$::env(GPL_TIMING_DRIVEN)} { lappend global_placement_args {-timing_driven} } -proc do_placement {place_density global_placement_args} { - set all_args [concat [list -density $place_density \ +proc do_placement {global_placement_args} { + set all_args [concat [list -density [place_density_with_lb_addon] \ -pad_left $::env(CELL_PAD_IN_SITES_GLOBAL_PLACEMENT) \ -pad_right $::env(CELL_PAD_IN_SITES_GLOBAL_PLACEMENT)] \ $global_placement_args] - if { 0 != [llength [array get ::env GLOBAL_PLACEMENT_ARGS]] } { - lappend all_args {*}$::env(GLOBAL_PLACEMENT_ARGS) - } + lappend all_args {*}$::env(GLOBAL_PLACEMENT_ARGS) log_cmd global_placement {*}$all_args } -set result [catch {do_placement $place_density $global_placement_args} errMsg] +set result [catch {do_placement $global_placement_args} errMsg] if {$result != 0} { write_db $::env(RESULTS_DIR)/3_3_place_gp-failed.odb error $errMsg diff --git a/flow/scripts/global_place_skip_io.tcl b/flow/scripts/global_place_skip_io.tcl index e0e1f448f0..fa9a53d537 100644 --- a/flow/scripts/global_place_skip_io.tcl +++ b/flow/scripts/global_place_skip_io.tcl @@ -2,22 +2,13 @@ source $::env(SCRIPTS_DIR)/load.tcl erase_non_stage_variables place load_design 2_floorplan.odb 2_floorplan.sdc - if { [env_var_exists_and_non_empty FLOORPLAN_DEF] } { puts "FLOORPLAN_DEF is set. Skipping global placement without IOs" } else { - source $::env(SCRIPTS_DIR)/set_place_density.tcl - - if { 0 != [llength [array get ::env GLOBAL_PLACEMENT_ARGS]] } { - global_placement -skip_io -density $place_density \ + log_cmd global_placement -skip_io -density [place_density_with_lb_addon] \ -pad_left $::env(CELL_PAD_IN_SITES_GLOBAL_PLACEMENT) \ -pad_right $::env(CELL_PAD_IN_SITES_GLOBAL_PLACEMENT) \ {*}$::env(GLOBAL_PLACEMENT_ARGS) - } else { - global_placement -skip_io -density $place_density \ - -pad_left $::env(CELL_PAD_IN_SITES_GLOBAL_PLACEMENT) \ - -pad_right $::env(CELL_PAD_IN_SITES_GLOBAL_PLACEMENT) - } } write_db $::env(RESULTS_DIR)/3_1_place_gp_skip_io.odb diff --git a/flow/scripts/global_route.tcl b/flow/scripts/global_route.tcl index 7c1a9b6d86..16639a3c93 100644 --- a/flow/scripts/global_route.tcl +++ b/flow/scripts/global_route.tcl @@ -12,15 +12,10 @@ proc global_route_helper {} { fast_route - # The default behavior if the user didn't specify GLOBAL_ROUTE_ARGS is to - # produce a drc report every 5 iterations. - # - # If GLOBAL_ROUTE_ARGS is specified, then we do only what the - # GLOBAL_ROUTE_ARGS specifies. proc do_global_route {} { - set all_args [concat [list -congestion_report_file $::global_route_congestion_report] \ - [expr {[env_var_exists_and_non_empty GLOBAL_ROUTE_ARGS] ? $::env(GLOBAL_ROUTE_ARGS) : \ - {-congestion_iterations 30 -congestion_report_iter_step 5 -verbose}}]] + set all_args [concat [list \ + -congestion_report_file $::global_route_congestion_report] \ + $::env(GLOBAL_ROUTE_ARGS)] log_cmd global_route {*}$all_args } @@ -34,6 +29,7 @@ proc global_route_helper {} { write_db $::env(RESULTS_DIR)/5_1_grt-failed.odb error $errMsg } + write_sdc -no_timestamp $::env(RESULTS_DIR)/5_1_grt.sdc write_db $::env(RESULTS_DIR)/5_1_grt.odb return } @@ -55,8 +51,7 @@ proc global_route_helper {} { } # Repair design using global route parasitics - puts "Perform buffer insertion..." - repair_design + repair_design_helper if { $::env(DETAILED_METRICS) } { report_metrics 5 "global route post repair design" } diff --git a/flow/scripts/io_placement_random.tcl b/flow/scripts/io_placement_random.tcl index b5de6aa143..7535485af1 100644 --- a/flow/scripts/io_placement_random.tcl +++ b/flow/scripts/io_placement_random.tcl @@ -2,7 +2,7 @@ source $::env(SCRIPTS_DIR)/load.tcl erase_non_stage_variables floorplan if {![env_var_equals IS_CHIP 1]} { - load_design 2_1_floorplan.odb 2_floorplan.sdc + load_design 2_1_floorplan.odb 2_1_floorplan.sdc lappend ::env(PLACE_PINS_ARGS) -random source $::env(SCRIPTS_DIR)/io_placement_util.tcl write_db $::env(RESULTS_DIR)/2_2_floorplan_io.odb diff --git a/flow/scripts/macro_place.tcl b/flow/scripts/macro_place.tcl index 7c1a319907..12d59b1008 100644 --- a/flow/scripts/macro_place.tcl +++ b/flow/scripts/macro_place.tcl @@ -1,7 +1,7 @@ source $::env(SCRIPTS_DIR)/load.tcl erase_non_stage_variables floorplan -load_design 2_3_floorplan_tdms.odb 2_floorplan.sdc +load_design 2_2_floorplan_io.odb 2_1_floorplan.sdc source $::env(SCRIPTS_DIR)/macro_place_util.tcl -write_db $::env(RESULTS_DIR)/2_4_floorplan_macro.odb +write_db $::env(RESULTS_DIR)/2_3_floorplan_macro.odb diff --git a/flow/scripts/macro_place_util.tcl b/flow/scripts/macro_place_util.tcl index dd7543e73a..54bbff6ade 100644 --- a/flow/scripts/macro_place_util.tcl +++ b/flow/scripts/macro_place_util.tcl @@ -33,7 +33,7 @@ if {[find_macros] != ""} { } elseif {[env_var_exists_and_non_empty MACRO_PLACEMENT]} { source $::env(SCRIPTS_DIR)/read_macro_placement.tcl log_cmd read_macro_placement $::env(MACRO_PLACEMENT) - } elseif {[env_var_equals RTLMP_FLOW 1]} { + } else { set additional_rtlmp_args "" append_env_var additional_rtlmp_args RTLMP_MAX_LEVEL -max_num_level 1 append_env_var additional_rtlmp_args RTLMP_MAX_INST -max_num_inst 1 @@ -49,16 +49,14 @@ if {[find_macros] != ""} { append_env_var additional_rtlmp_args RTLMP_OUTLINE_WT -outline_weight 1 append_env_var additional_rtlmp_args RTLMP_BOUNDARY_WT -boundary_weight 1 append_env_var additional_rtlmp_args RTLMP_NOTCH_WT -notch_weight 1 - append_env_var additional_rtlmp_args RTLMP_DEAD_SPACE -dead_space 1 - append_env_var additional_rtlmp_args RTLMP_CONFIG_FILE -config_file 1 + append_env_var additional_rtlmp_args RTLMP_DEAD_SPACE -target_dead_space 1 append_env_var additional_rtlmp_args RTLMP_RPT_DIR -report_directory 1 append_env_var additional_rtlmp_args RTLMP_FENCE_LX -fence_lx 1 append_env_var additional_rtlmp_args RTLMP_FENCE_LY -fence_ly 1 append_env_var additional_rtlmp_args RTLMP_FENCE_UX -fence_ux 1 append_env_var additional_rtlmp_args RTLMP_FENCE_UY -fence_uy 1 - source $::env(SCRIPTS_DIR)/set_place_density.tcl - append additional_rtlmp_args " -target_util $place_density" + append additional_rtlmp_args " -target_util [place_density_with_lb_addon]" set all_args $additional_rtlmp_args @@ -67,10 +65,6 @@ if {[find_macros] != ""} { } log_cmd rtl_macro_placer {*}$all_args - } else { - macro_placement \ - -halo $::env(MACRO_PLACE_HALO) \ - -channel $::env(MACRO_PLACE_CHANNEL) } source $::env(SCRIPTS_DIR)/placement_blockages.tcl diff --git a/flow/scripts/open.tcl b/flow/scripts/open.tcl index c276db161a..64b7617da4 100644 --- a/flow/scripts/open.tcl +++ b/flow/scripts/open.tcl @@ -51,11 +51,10 @@ proc read_timing {input_file} { log_cmd estimate_parasitics -placement } - fast_route - - puts "Populating timing paths..." + puts -nonewline "Populating timing paths..." # Warm up OpenSTA, so clicking on timing related buttons reacts faster set _tmp [find_timing_paths] + puts "OK" } if {[env_var_equals GUI_TIMING 1]} { @@ -63,8 +62,10 @@ if {[env_var_equals GUI_TIMING 1]} { read_timing $input_file } +fast_route + if {[env_var_equals GUI_SHOW 1]} { # Show the GUI when it is ready; it is unresponsive(with modal requesters # saying it is unresponsive) until everything is loaded - gui::show + gui::unminimize } diff --git a/flow/scripts/pdn.tcl b/flow/scripts/pdn.tcl index d6dd9e5d1c..a43f95ef19 100644 --- a/flow/scripts/pdn.tcl +++ b/flow/scripts/pdn.tcl @@ -1,6 +1,6 @@ source $::env(SCRIPTS_DIR)/load.tcl erase_non_stage_variables floorplan -load_design 2_5_floorplan_tapcell.odb 2_floorplan.sdc +load_design 2_4_floorplan_tapcell.odb 2_1_floorplan.sdc source $::env(PDN_TCL) pdngen @@ -20,4 +20,4 @@ foreach net [$block getNets] { } } -write_db $::env(RESULTS_DIR)/2_6_floorplan_pdn.odb +write_db $::env(RESULTS_DIR)/2_5_floorplan_pdn.odb diff --git a/flow/scripts/report_metrics.tcl b/flow/scripts/report_metrics.tcl index 7c635598e3..d0af3e97af 100644 --- a/flow/scripts/report_metrics.tcl +++ b/flow/scripts/report_metrics.tcl @@ -31,7 +31,7 @@ proc report_metrics { stage when {include_erc true} {include_clock_skew true} } report_worst_slack >> $filename report_worst_slack_metric >> $filename - if {$include_clock_skew} { + if {$include_clock_skew && $::env(REPORT_CLOCK_SKEW)} { report_puts "\n==========================================================================" report_puts "$when report_clock_skew" report_puts "--------------------------------------------------------------------------" diff --git a/flow/scripts/resize.tcl b/flow/scripts/resize.tcl index 61ec9727a2..cb38355043 100644 --- a/flow/scripts/resize.tcl +++ b/flow/scripts/resize.tcl @@ -21,18 +21,7 @@ if { ![env_var_exists_and_non_empty FOOTPRINT] } { } } -puts "Perform buffer insertion..." -set additional_args "" -if { [env_var_exists_and_non_empty CAP_MARGIN] && $::env(CAP_MARGIN) > 0.0} { - puts "Cap margin $::env(CAP_MARGIN)" - append additional_args " -cap_margin $::env(CAP_MARGIN)" -} -if { [env_var_exists_and_non_empty SLEW_MARGIN] && $::env(SLEW_MARGIN) > 0.0} { - puts "Slew margin $::env(SLEW_MARGIN)" - append additional_args " -slew_margin $::env(SLEW_MARGIN)" -} - -repair_design {*}$additional_args +repair_design_helper if { [env_var_exists_and_non_empty TIE_SEPARATION] } { set tie_separation $env(TIE_SEPARATION) diff --git a/flow/scripts/set_place_density.tcl b/flow/scripts/set_place_density.tcl deleted file mode 100644 index 70417129da..0000000000 --- a/flow/scripts/set_place_density.tcl +++ /dev/null @@ -1,12 +0,0 @@ -# check the lower boundary of the PLACE_DENSITY and add PLACE_DENSITY_LB_ADDON if it exists -if {[info exist ::env(PLACE_DENSITY_LB_ADDON)]} { - set place_density_lb [gpl::get_global_placement_uniform_density \ - -pad_left $::env(CELL_PAD_IN_SITES_GLOBAL_PLACEMENT) \ - -pad_right $::env(CELL_PAD_IN_SITES_GLOBAL_PLACEMENT)] - set place_density [expr $place_density_lb + ((1.0 - $place_density_lb) * $::env(PLACE_DENSITY_LB_ADDON)) + 0.01] - if {$place_density > 1.0} { - utl::error FLW 24 "Place density exceeds 1.0 (current PLACE_DENSITY_LB_ADDON = $::env(PLACE_DENSITY_LB_ADDON)). Please check if the value of PLACE_DENSITY_LB_ADDON is between 0 and 0.99." - } -} else { - set place_density $::env(PLACE_DENSITY) -} diff --git a/flow/scripts/synth.tcl b/flow/scripts/synth.tcl index af8e41cc42..99eede38fb 100644 --- a/flow/scripts/synth.tcl +++ b/flow/scripts/synth.tcl @@ -1,15 +1,37 @@ source $::env(SCRIPTS_DIR)/synth_preamble.tcl -source $::env(SYNTH_STOP_MODULE_SCRIPT) +hierarchy -check -top $::env(DESIGN_NAME) + +set ungroup_threshold 0 +if { $::env(MAX_UNGROUP_SIZE) > 0 } { + set ungroup_threshold $::env(MAX_UNGROUP_SIZE) + puts "Ungroup modules of size greater than $ungroup_threshold" +} + +set fp [open $::env(SYNTH_STATS) r] +while {[gets $fp line] != -1} { + set fields [split $line " "] + set area [lindex $fields 0] + set module_name [lindex $fields 1] + + if {[expr $area > $ungroup_threshold]} { + puts "Keeping module $module_name (area: $area)" + select -module $module_name + setattr -mod -set keep_hierarchy 1 + select -clear + } else { + puts "Flattening module $module_name (area: $area)" + } +} +close $fp if { [env_var_equals SYNTH_GUT 1] } { - hierarchy -check -top $::env(DESIGN_NAME) # /deletes all cells at the top level, which will quickly optimize away # everything else, including macros. delete $::env(DESIGN_NAME)/c:* } -synthesize_check $::env(SYNTH_FULL_ARGS) +synthesize_check mem $::env(SYNTH_FULL_ARGS) # rename registers to have the verilog register name in its name # of the form \regName$_DFF_P_. We should fix yosys to make it the reg name. diff --git a/flow/scripts/synth_preamble.tcl b/flow/scripts/synth_preamble.tcl index bfeb1c463d..89a11db660 100644 --- a/flow/scripts/synth_preamble.tcl +++ b/flow/scripts/synth_preamble.tcl @@ -107,12 +107,12 @@ puts $constr "set_driving_cell $::env(ABC_DRIVER_CELL)" puts $constr "set_load $::env(ABC_LOAD_IN_FF)" close $constr -proc synthesize_check {synth_args} { +proc synthesize_check {report synth_args} { # Generic synthesis log_cmd synth -top $::env(DESIGN_NAME) -run :fine {*}$synth_args - json -o $::env(RESULTS_DIR)/mem.json + json -o $::env(RESULTS_DIR)/$report.json # Run report and check here so as to fail early if this synthesis run is doomed - exec -- python3 $::env(SCRIPTS_DIR)/mem_dump.py --max-bits $::env(SYNTH_MEMORY_MAX_BITS) $::env(RESULTS_DIR)/mem.json + exec -- python3 $::env(SCRIPTS_DIR)/mem_dump.py --max-bits $::env(SYNTH_MEMORY_MAX_BITS) $::env(RESULTS_DIR)/$report.json synth -top $::env(DESIGN_NAME) -run fine: {*}$synth_args # Get rid of indigestibles chformal -remove diff --git a/flow/scripts/synth_hier_report.tcl b/flow/scripts/synth_stats.tcl similarity index 60% rename from flow/scripts/synth_hier_report.tcl rename to flow/scripts/synth_stats.tcl index ee419e55c0..1cd73b49a5 100644 --- a/flow/scripts/synth_hier_report.tcl +++ b/flow/scripts/synth_stats.tcl @@ -1,15 +1,20 @@ +# Gather statistics, if needed. Gathering the statistics is +# time consuming, because it requires a full synthesis run. +# +# The statistics is needed for SYNTH_HIERARCHICAL=1 flattening/keep +# module policy, and write to $::env(SYNTH_STATS) source $::env(SCRIPTS_DIR)/util.tcl proc write_keep_hierarchy {} { if { ![env_var_equals SYNTH_HIERARCHICAL 1] } { - set out_script_ptr [open $::env(SYNTH_STOP_MODULE_SCRIPT) w] + set out_script_ptr [open $::env(SYNTH_STATS) w] close $out_script_ptr return } source $::env(SCRIPTS_DIR)/synth_preamble.tcl - synthesize_check {} + synthesize_check mem_hierarchical {} if { [env_var_exists_and_non_empty ADDER_MAP_FILE] && [file isfile $::env(ADDER_MAP_FILE)] } { techmap -map $::env(ADDER_MAP_FILE) @@ -25,11 +30,6 @@ proc write_keep_hierarchy {} { tee -o $::env(REPORTS_DIR)/synth_hier_stat.txt stat {*}$stat_libs - set ungroup_threshold 0 - if { [env_var_exists_and_non_empty MAX_UNGROUP_SIZE] && $::env(MAX_UNGROUP_SIZE) > 0 } { - set ungroup_threshold $::env(MAX_UNGROUP_SIZE) - puts "Ungroup modules of size $ungroup_threshold" - } hierarchy -check -top $::env(DESIGN_NAME) set fptr [open $::env(REPORTS_DIR)/synth_hier_stat.txt r] set contents [read -nonewline $fptr] @@ -53,27 +53,26 @@ proc write_keep_hierarchy {} { } } } - set out_script_ptr [open $::env(SYNTH_STOP_MODULE_SCRIPT) w] - puts $out_script_ptr "hierarchy -check -top $::env(DESIGN_NAME)" + + set areas {} foreach module $module_list { - tee -o $::env(REPORTS_DIR)/synth_hier_stat_temp_module.txt stat -top "$module" {*}$stat_libs - set fptr1 [open $::env(REPORTS_DIR)/synth_hier_stat_temp_module.txt r] + tee -o $::env(OBJECTS_DIR)/synth_stat_temp_module.txt stat -top "$module" {*}$stat_libs + set fptr1 [open $::env(OBJECTS_DIR)/synth_stat_temp_module.txt r] set contents1 [read -nonewline $fptr1] close $fptr1 set split_cont1 [split $contents1 "\n"] foreach line $split_cont1 { if {[regexp { +Chip area for top module '(\S+)': (.*)} $line -> module_name area]} { - if {[expr $area > $ungroup_threshold]} { - puts "Preserving module: $module_name (area: $area)" - puts $out_script_ptr "select -module {$module_name}" - puts $out_script_ptr "setattr -mod -set keep_hierarchy 1" - puts $out_script_ptr "select -clear" - } else { - puts "Flattening module $module_name (area: $area)" - } + lappend areas "$area $module_name" } } - file delete -force $::env(REPORTS_DIR)/synth_hier_stat_temp_module.txt + file delete -force $::env(OBJECTS_DIR)/synth_stat_temp_module.txt + } + set areas [lsort -index 0 -real $areas] + + set out_script_ptr [open $::env(SYNTH_STATS) w] + foreach {line} $areas { + puts $out_script_ptr $line } close $out_script_ptr } diff --git a/flow/scripts/tapcell.tcl b/flow/scripts/tapcell.tcl index 604f008f2f..842a858ea1 100644 --- a/flow/scripts/tapcell.tcl +++ b/flow/scripts/tapcell.tcl @@ -1,7 +1,7 @@ source $::env(SCRIPTS_DIR)/load.tcl erase_non_stage_variables floorplan -load_design 2_4_floorplan_macro.odb 2_floorplan.sdc +load_design 2_3_floorplan_macro.odb 2_1_floorplan.sdc if {[env_var_exists_and_non_empty TAPCELL_TCL]} { source $::env(TAPCELL_TCL) @@ -9,4 +9,4 @@ if {[env_var_exists_and_non_empty TAPCELL_TCL]} { cut_rows } -write_db $::env(RESULTS_DIR)/2_5_floorplan_tapcell.odb +write_db $::env(RESULTS_DIR)/2_4_floorplan_tapcell.odb diff --git a/flow/scripts/tdms_place.tcl b/flow/scripts/tdms_place.tcl deleted file mode 100644 index 472b1db6af..0000000000 --- a/flow/scripts/tdms_place.tcl +++ /dev/null @@ -1,37 +0,0 @@ -source $::env(SCRIPTS_DIR)/load.tcl -erase_non_stage_variables floorplan - -proc find_macros {} { - set macros "" - - set db [::ord::get_db] - set block [[$db getChip] getBlock] - foreach inst [$block getInsts] { - set inst_master [$inst getMaster] - - # BLOCK means MACRO cells - if { [string match [$inst_master getType] "BLOCK"] } { - append macros " " $inst - } - } - return $macros -} - -if {!([env_var_exists_and_non_empty MACRO_PLACEMENT] || - [env_var_exists_and_non_empty MACRO_PLACEMENT_TCL]) && - ![env_var_equals RTLMP_FLOW 1]} { - load_design 2_2_floorplan_io.odb 2_floorplan.sdc - - set_dont_use $::env(DONT_USE_CELLS) - - if {[find_macros] != ""} { - log_cmd global_placement -density $::env(PLACE_DENSITY) \ - -pad_left $::env(CELL_PAD_IN_SITES_GLOBAL_PLACEMENT) \ - -pad_right $::env(CELL_PAD_IN_SITES_GLOBAL_PLACEMENT) - } else { - puts "No macros found: Skipping global_placement" - } - write_db $::env(RESULTS_DIR)/2_3_floorplan_tdms.odb -} else { - log_cmd exec cp $::env(RESULTS_DIR)/2_2_floorplan_io.odb $::env(RESULTS_DIR)/2_3_floorplan_tdms.odb -} diff --git a/flow/scripts/util.tcl b/flow/scripts/util.tcl index eaf3d8baf3..418353e920 100644 --- a/flow/scripts/util.tcl +++ b/flow/scripts/util.tcl @@ -15,11 +15,10 @@ proc fast_route {} { } } -# -hold_margin is only set when hold_margin is set, default 1 proc repair_timing_helper { {hold_margin 1} } { set additional_args "-verbose" append_env_var additional_args SETUP_SLACK_MARGIN -setup_margin 1 - if {$hold_margin} { + if {$hold_margin || $::env(HOLD_SLACK_MARGIN) < 0} { append_env_var additional_args HOLD_SLACK_MARGIN -hold_margin 1 } append_env_var additional_args TNS_END_PERCENT -repair_tns 1 @@ -27,10 +26,23 @@ proc repair_timing_helper { {hold_margin 1} } { append_env_var additional_args SKIP_GATE_CLONING -skip_gate_cloning 0 append_env_var additional_args SKIP_BUFFER_REMOVAL -skip_buffer_removal 0 append_env_var additional_args SKIP_LAST_GASP -skip_last_gasp 0 + append_env_var additional_args MATCH_CELL_FOOTPRINT -match_cell_footprint 0 puts "repair_timing [join $additional_args " "]" repair_timing {*}$additional_args } +proc repair_design_helper {} { + puts "Perform buffer insertion and gate resizing..." + + set additional_args "" + append_env_var additional_args CAP_MARGIN -cap_margin 1 + append_env_var additional_args SLEW_MARGIN -slew_margin 1 + append_env_var additional_args MATCH_CELL_FOOTPRINT -match_cell_footprint 0 + puts "repair_design [join $additional_args " "]" + + repair_design {*}$additional_args +} + proc recover_power {} { if { $::env(RECOVER_POWER) == 0 } { return @@ -40,30 +52,52 @@ proc recover_power {} { report_tns report_wns report_power - repair_timing -recover_power $::env(RECOVER_POWER) + set additional_args "" + append_env_var additional_args RECOVER_POWER -recover_power 1 + append_env_var additional_args MATCH_CELL_FOOTPRINT -match_cell_footprint 0 + repair_timing {*}$additional_args report_tns report_wns report_power } +proc extract_stage {input_file} { + if {![regexp {/([0-9])_(([0-9])_)?} $input_file match num1 _ num2]} { + puts "ERROR: Could not determine design stage from $input_file" + exit 1 + } + lappend number_groups $num1 + if {$num2!=""} { + lappend number_groups $num2 + } else { + lappend number_groups "0" + } +} + proc find_sdc_file {input_file} { - # Determine design stage (1 ... 6) - set input_pieces [split [file tail $input_file] "_"] - set design_stage [lindex $input_pieces 0] - if { [llength $input_pieces] == 3 } { - set start [expr $design_stage - 1] - } else { - set start $design_stage - } - # Read SDC, first try to find the most recent SDC file for the stage - set sdc_file "" - for {set s $start} {$s > 0} {incr s -1} { - set sdc_file [glob -nocomplain -directory $::env(RESULTS_DIR) -types f "${s}_\[A-Za-z\]*\.sdc"] - if {$sdc_file != ""} { - break - } + # canonicalize input file, sometimes it is called with an input + # file relative to $::env(RESULTS_DIR), other times with + # an absolute path + if { ![file exists $input_file] } { + set input_file [file join $::env(RESULTS_DIR) $input_file] + } + set input_file [file normalize $input_file] + + set stage [extract_stage $input_file] + set design_stage [lindex $stage 0] + set sdc_file "" + + set exact_sdc [string map {.odb .sdc} $input_file] + set sdc_files [glob -nocomplain -directory $::env(RESULTS_DIR) -types f "\[1-9+\]_\[1-9_A-Za-z\]*\.sdc"] + set sdc_files [lsort -decreasing -dictionary $sdc_files] + set sdc_files [lmap file $sdc_files {file normalize $file}] + foreach name $sdc_files { + if {[lindex [lsort -decreasing -dictionary [list $name $exact_sdc] ] 0] == $exact_sdc} { + set sdc_file $name + break } - return [list $design_stage $sdc_file] + } + return [list $design_stage $sdc_file] } proc env_var_equals {env_var value} { @@ -117,3 +151,20 @@ proc erase_non_stage_variables {stage_name} { } set global_route_congestion_report $::env(REPORTS_DIR)/congestion.rpt + +proc place_density_with_lb_addon {} { + if {[env_var_exists_and_non_empty PLACE_DENSITY_LB_ADDON]} { + # check the lower boundary of the PLACE_DENSITY and add PLACE_DENSITY_LB_ADDON + set place_density_lb [gpl::get_global_placement_uniform_density \ + -pad_left $::env(CELL_PAD_IN_SITES_GLOBAL_PLACEMENT) \ + -pad_right $::env(CELL_PAD_IN_SITES_GLOBAL_PLACEMENT)] + set place_density [expr $place_density_lb + ((1.0 - $place_density_lb) * $::env(PLACE_DENSITY_LB_ADDON)) + 0.01] + if {$place_density > 1.0} { + utl::error FLW 24 "Place density exceeds 1.0 (current PLACE_DENSITY_LB_ADDON = $::env(PLACE_DENSITY_LB_ADDON)). Please check if the value of PLACE_DENSITY_LB_ADDON is between 0 and 0.99." + } + puts "Placement density is $place_density, computed from PLACE_DENSITY_LB_ADDON $::env(PLACE_DENSITY_LB_ADDON) and lower bound $place_density_lb" + } else { + set place_density $::env(PLACE_DENSITY) + } + return $place_density +} diff --git a/flow/scripts/variables.yaml b/flow/scripts/variables.yaml index 12fe952453..0039bdbd42 100644 --- a/flow/scripts/variables.yaml +++ b/flow/scripts/variables.yaml @@ -1,3 +1,4 @@ +--- GENERATE_ARTIFACTS_ON_FAILURE: description: > For instance Bazel needs artifacts (.odb and .rpt files) on a failure to @@ -11,9 +12,10 @@ GENERATE_ARTIFACTS_ON_FAILURE: failures that aren't covered by the "useful to inspect the artifacts on failure" use-case. - Example: just like detailed routing, a global route that fails with congestion, is not - a build failure(as in exit code non-zero), it is a successful(as in zero exit code) - global route that produce reports detailing the problem. + Example: just like detailed routing, a global route that fails with + congestion, is not a build failure(as in exit code non-zero), it is a + successful(as in zero exit code) global route that produce reports + detailing the problem. Detailed route will not proceed, if there is global routing congestion @@ -48,7 +50,8 @@ ROUTING_LAYER_ADJUSTMENT: - final RECOVER_POWER: description: > - Specifies how many percent of paths with positive slacks can be slowed for power savings [0-100]. + Specifies how many percent of paths with positive slacks can be slowed for + power savings [0-100]. default: 0 SKIP_INCREMENTAL_REPAIR: default: 0 @@ -59,14 +62,15 @@ SKIP_INCREMENTAL_REPAIR: DETAILED_METRICS: description: > If set, then calls report_metrics prior to repair operations in the CTS - and global route stages + and global route stages default: 0 stages: - cts - grt EQUIVALENCE_CHECK: description: > - Enable running equivalence checks to verify logical correctness of repair_timing. + Enable running equivalence checks to verify logical correctness of + repair_timing. default: 0 stages: - cts @@ -77,13 +81,27 @@ CORE_UTILIZATION: - floorplan CORE_AREA: description: > - The core area specified as a list of lower-left and upper-right corners in microns + The core area specified as a list of lower-left and upper-right corners in + microns (X1 Y1 X2 Y2). stages: - floorplan +REPORT_CLOCK_SKEW: + description: + Report clock skew as part of reporting metrics, starting at CTS, + before which there is no clock skew. + + This metric can be quite time-consuming, so it can be useful to disable. + stages: + - cts + - grt + - route + - final + default: 1 SKIP_REPORT_METRICS: description: > - If set to 1, then metrics, report_metrics does nothing. Useful to speed up builds. + If set to 1, then metrics, report_metrics does nothing. Useful to speed up + builds. stages: - floorplan - place @@ -96,7 +114,7 @@ PROCESS: Technology node or process in use. CORNER: description: > - Library to select based on corner BC/TC/WC. + PVT corner library selection. Only available for ASAP7 and GF180 PDKs. TECH_LEF: description: > A technology LEF file of the PDK that includes all relevant information @@ -110,7 +128,8 @@ GDS_FILES: LIB_FILES: description: > A Liberty file of the standard cell library with PVT characterization, - input and output characteristics, timing and power definitions for each cell. + input and output characteristics, timing and power definitions for each + cell. DONT_USE_CELLS: description: > Dont use cells eases pin access in detailed routing. @@ -127,6 +146,7 @@ SYNTH_HIERARCHICAL: Enable to Synthesis hierarchically, otherwise considered flat synthesis. stages: - synth + default: 0 LATCH_MAP_FILE: description: > List of latches treated as a black box by Yosys. @@ -144,7 +164,8 @@ ADDER_MAP_FILE: - synth TIEHI_CELL_AND_PORT: description: > - Tie high cells used in Yosys synthesis to replace a logical 1 in the Netlist. + Tie high cells used in Yosys synthesis to replace a logical 1 in the + Netlist. stages: - synth - place @@ -161,7 +182,8 @@ MIN_BUF_CELL_AND_PORTS: - synth ABC_CLOCK_PERIOD_IN_PS: description: > - Clock period to be used by STA during synthesis. Default value read from `constraint.sdc`. + Clock period to be used by STA during synthesis. Default value read from + `constraint.sdc`. stages: - synth ABC_DRIVER_CELL: @@ -176,7 +198,8 @@ ABC_LOAD_IN_FF: - synth MAX_UNGROUP_SIZE: description: > - For hierarchical synthesis, we ungroup modules of size given by this variable. + For hierarchical synthesis, we ungroup modules of larger area than given by + this variable. The default value is > 0 platform specific. stages: - synth FLOORPLAN_DEF: @@ -187,9 +210,12 @@ FLOORPLAN_DEF: - place REMOVE_ABC_BUFFERS: description: > - Remove abc buffers from the netlist. + Remove abc buffers from the netlist. If timing repair in floorplanning is + taking too long, use a SETUP_HOLD_MARGIN to terminate timing repair early + instead of using REMOVE_ABC_BUFFERS or set SKIP_LAST_GAST=1. stages: - floorplan + deprecated: 1 PLACE_SITE: description: > Placement site for core cells defined in the technology LEF file. @@ -200,14 +226,10 @@ TAPCELL_TCL: Path to Endcap and Welltie cells file. stages: - floorplan -RTLMP_FLOW: - description: > - 1 to enable the Hierarchical RTLMP flow, default empty. - stages: - - floorplan MACRO_PLACEMENT: description: > - Specifies the path of a file on how to place certain macros manually using read_macro_placement. + Specifies the path of a file on how to place certain macros manually using + read_macro_placement. stages: - floorplan MACRO_PLACEMENT_TCL: @@ -217,13 +239,15 @@ MACRO_PLACEMENT_TCL: - floorplan MACRO_PLACE_HALO: description: > - Horizontal/vertical halo around macros (microns). Used by automatic macro placement. + Horizontal/vertical halo around macros (microns). Used by automatic macro + placement. stages: - floorplan MACRO_PLACE_CHANNEL: description: > - Horizontal/vertical channel width between macros (microns). Used by automatic macro placement when RTLMP_FLOW is disabled. - Imagine channel=10 and halo=5. Then macros must be 10 apart but standard cells must be 5 away from a macro. + Horizontal/vertical channel width between macros (microns). Used by + automatic macro placement. Imagine channel=10 and halo=5. Then macros must + be 10 apart but standard cells must be 5 away from a macro. stages: - floorplan MACRO_BLOCKAGE_HALO: @@ -233,7 +257,9 @@ MACRO_BLOCKAGE_HALO: - floorplan PDN_TCL: description: > - File path which has a set of power grid policies used by pdn to be applied to the design, such as layers to use, stripe width and spacing to generate the actual metal straps. + File path which has a set of power grid policies used by pdn to be applied + to the design, such as layers to use, stripe width and spacing to generate + the actual metal straps. stages: - floorplan MAKE_TRACKS: @@ -249,13 +275,15 @@ IO_CONSTRAINTS: - place IO_PLACER_H: description: > - The metal layer on which to place the I/O pins horizontally (top and bottom of the die). + The metal layer on which to place the I/O pins horizontally (top and bottom + of the die). stages: - floorplan - place IO_PLACER_V: description: > - The metal layer on which to place the I/O pins vertically (sides of the die). + The metal layer on which to place the I/O pins vertically (sides of the + die). stages: - floorplan - place @@ -267,7 +295,8 @@ GUI_TIMING: default: 1 FILL_CELLS: description: > - Fill cells are used to fill empty sites. If not set or empty, fill cell insertion is skipped. + Fill cells are used to fill empty sites. If not set or empty, fill cell + insertion is skipped. stages: - route TAP_CELL_NAME: @@ -275,61 +304,75 @@ TAP_CELL_NAME: Name of the cell to use in tap cell insertion. CELL_PAD_IN_SITES_GLOBAL_PLACEMENT: description: > - Cell padding on both sides in site widths to ease routability during global placement. + Cell padding on both sides in site widths to ease routability during global + placement. stages: - place - floorplan + default: 0 CELL_PAD_IN_SITES_DETAIL_PLACEMENT: description: > - Cell padding on both sides in site widths to ease routability in detail placement. + Cell padding on both sides in site widths to ease routability in detail + placement. stages: - place - cts - grt + default: 0 PLACE_PINS_ARGS: description: > Arguments to place_pins stages: - place - floorplan + default: "" PLACE_DENSITY: description: > - The desired placement density of cells. It reflects how spread the cells would be on the core area. - 1.0 = closely dense. 0.0 = widely spread. + The desired placement density of cells. It reflects how spread the cells + would be on the core area. 1.0 = closely dense. 0.0 = widely spread. stages: - floorplan - place PLACE_DENSITY_LB_ADDON: description: > - Check the lower boundary of the PLACE_DENSITY and add PLACE_DENSITY_LB_ADDON if it exists. + Check the lower boundary of the PLACE_DENSITY and add + PLACE_DENSITY_LB_ADDON if it exists. REPAIR_PDN_VIA_LAYER: description: > Remove power grid vias which generate DRC violations after detailed routing. GLOBAL_PLACEMENT_ARGS: description: > - Use additional tuning parameters during global placement other than default args defined in global_place.tcl. + Use additional tuning parameters during global placement other than default + args defined in global_place.tcl. + default: "" ENABLE_DPO: description: > Enable detail placement with improve_placement feature. + default: 1 DPO_MAX_DISPLACEMENT: description: > Specifies how far an instance can be moved when optimizing. + default: 5 1 GPL_TIMING_DRIVEN: description: > Specifies whether the placer should use timing driven placement. stages: - place + default: 1 GPL_ROUTABILITY_DRIVEN: description: > Specifies whether the placer should use routability driven placement. stages: - place + default: 1 CAP_MARGIN: description: > - Specifies a capacitance margin when fixing max capacitance violations. This option allows you to overfix. + Specifies a capacitance margin when fixing max capacitance violations. This + option allows you to overfix. SLEW_MARGIN: description: > - Specifies a slew margin when fixing max slew violations. This option allows you to overfix. + Specifies a slew margin when fixing max slew violations. This option allows + you to overfix. CTS_ARGS: description: > Override `clock_tree_synthesis` arguments. @@ -340,10 +383,22 @@ HOLD_SLACK_MARGIN: Specifies a time margin for the slack when fixing hold violations. This option allows you to overfix or underfix(negative value, terminate retiming before 0 or positive slack). + + Use min of HOLD_SLACK_MARGIN and 0(default hold slack margin) in floorplan. + + This avoids overrepair in floorplan for hold by default, but allows skipping + hold repair using a negative HOLD_SLACK_MARGIN. + + Exiting timing repair early is useful in exploration where + + the .sdc has a fixed clock period at designs target clock period and where + HOLD/SETUP_SLACK_MARGIN is used to avoid overrepair(extremely long running + times) when exploring different parameter settings. stages: - cts - floorplan - grt + default: 0 SETUP_SLACK_MARGIN: description: > Specifies a time margin for the slack when fixing setup violations. @@ -353,36 +408,41 @@ SETUP_SLACK_MARGIN: - cts - floorplan - grt + default: 0 SKIP_GATE_CLONING: description: > - Do not use gate cloning transform to fix timing violations (default: use gate cloning). + Do not use gate cloning transform to fix timing violations (default: use + gate cloning). stages: - cts - floorplan - grt SKIP_LAST_GASP: description: > - Do not use last gasp optimization to fix timing violations (default: use gate last gasp). + Do not use last gasp optimization to fix timing violations (default: use + gate last gasp). stages: - cts - floorplan - grt SKIP_PIN_SWAP: description: > - Do not use pin swapping as a transform to fix timing violations (default: use pin swapping). + Do not use pin swapping as a transform to fix timing violations (default: + use pin swapping). stages: - cts - floorplan - grt REMOVE_CELLS_FOR_EQY: description: > - String patterns directly passed to write_verilog -remove_cells <> for equivalence checks. + String patterns directly passed to write_verilog -remove_cells <> for + equivalence checks. stages: - cts SKIP_CTS_REPAIR_TIMING: description: > - Skipping CTS repair, which can take a long time, can be useful in architectural exploration - or when getting CI up and running. + Skipping CTS repair, which can take a long time, can be useful in + architectural exploration or when getting CI up and running. stages: - cts MIN_ROUTING_LAYER: @@ -411,7 +471,8 @@ MACRO_EXTENSION: Sets the number of GCells added to the blockages boundaries from macros. DETAILED_ROUTE_END_ITERATION: description: > - Maximum number of iterations, default 64. + Maximum number of iterations. + default: 64 stages: - route RCX_RULES: @@ -463,25 +524,22 @@ ADDITIONAL_FILES: Additional files to be added to `make issue` archive. ADDITIONAL_LEFS: description: > - Hardened macro LEF view files listed here. The LEF information of the macros - is immutable and used throughout all stages. Stored in the .odb file. + Hardened macro LEF view files listed here. The LEF information of the + macros is immutable and used throughout all stages. Stored in the .odb file. ADDITIONAL_LIBS: description: > - Hardened macro library files listed here. The library information is immutable - and used throughout all stages. Not stored in the .odb file. + Hardened macro library files listed here. The library information is + immutable and used throughout all stages. Not stored in the .odb file. ADDITIONAL_GDS: description: > Hardened macro GDS files listed here. stages: - - final + - final VERILOG_INCLUDE_DIRS: description: > Specifies the include directories for the Verilog input files. stages: - synth -CORNER: - description: > - PVT corner library selection. Only available for ASAP7 and GF180 PDK. DESIGN_NICKNAME: description: > DESIGN_NICKNAME just changes the directory name that ORFS outputs to be @@ -492,6 +550,7 @@ ABC_AREA: Strategies for Yosys ABC synthesis: Area/Speed. Default ABC_SPEED. stages: - synth + default: 0 PWR_NETS_VOLTAGES: description: > Used for IR Drop calculation. @@ -521,6 +580,7 @@ PRESERVE_CELLS: SYNTH_ARGS: description: > Optional synthesis variables for yosys. + default: -flatten VERILOG_TOP_PARAMS: description: > Apply toplevel params (if exist). @@ -528,20 +588,23 @@ VERILOG_TOP_PARAMS: - synth CORE_ASPECT_RATIO: description: > - The core aspect ratio (height / width). This value is ignored if `CORE_UTILIZATION` - is undefined. + The core aspect ratio (height / width). This value is ignored if + `CORE_UTILIZATION` is undefined. stages: - floorplan CORE_MARGIN: description: > - The margin between the core area and die area, in multiples of SITE heights. - The margin is applied to each side. This variable is ignored if `CORE_UTILIZATION` + The margin between the core area and die area, specified in microns. + Allowed values are either one value for all margins or a set of four + values, one for each margin. The order of the four values are: + `{bottom top left right}`. This variable is ignored if `CORE_UTILIZATION` is undefined. stages: - floorplan DIE_AREA: description: > - The die area specified as a list of lower-left and upper-right corners in microns + The die area specified as a list of lower-left and upper-right corners in + microns (X1 Y1 X2 Y2). stages: - floorplan @@ -550,11 +613,13 @@ RESYNTH_AREA_RECOVER: Enable re-synthesis for area reclaim. stages: - synth + default: 0 RESYNTH_TIMING_RECOVER: description: > Enable re-synthesis for timing optimization. stages: - synth + default: 0 MACRO_HALO_X: description: > Set macro halo for x-direction. Only available for ASAP7 PDK. @@ -577,12 +642,14 @@ CTS_BUF_DISTANCE: - cts CTS_CLUSTER_DIAMETER: description: > - Maximum diameter (in microns) of sink cluster. Default 20. + Maximum diameter (in microns) of sink cluster. + default: 20 stages: - cts CTS_CLUSTER_SIZE: description: > - Maximum number of sinks per cluster. Default 50. + Maximum number of sinks per cluster. + default: 50 stages: - cts CTS_SNAPSHOT: @@ -600,7 +667,8 @@ FASTROUTE_TCL: Specifies a Tcl script with commands to run before FastRoute. USE_FILL: description: > - Whether to perform metal density filling. Default 0 (=off). + Whether to perform metal density filling. + default: 0 SEAL_GDS: description: > Seal macro to place around the design. @@ -609,3 +677,140 @@ ABSTRACT_SOURCE: Which .odb file to use to create abstract stages: - generate_abstract +GLOBAL_ROUTE_ARGS: + description: > + Replaces default arguments for global route. + stages: + - grt + default: -congestion_iterations 30 -congestion_report_iter_step 5 -verbose +MATCH_CELL_FOOTPRINT: + description: > + Enforce sizing operations to only swap cells that have the same layout + boundary. + stages: + - floorplan + - place + - cts + - route + default: 0 +RTLMP_MAX_LEVEL: + description: > + Maximum depth of the physical hierarchy tree. + default: 2 + stages: + - floorplan +RTLMP_MAX_INST: + description: > + Maximum number of standard cells in a cluster. If unset, rtl_macro_placer + will calculate a value based on the design attributes. + stages: + - floorplan +RTLMP_MIN_INST: + description: > + Minimum number of standard cells in a cluster. If unset, rtl_macro_placer + will calculate a value based on the design attributes. + stages: + - floorplan +RTLMP_MAX_MACRO: + description: > + Maximum number of macros in a cluster. If unset, rtl_macro_placer will + calculate a value based on the design attributes. + stages: + - floorplan +RTLMP_MIN_MACRO: + description: > + Minimum number of macros in a cluster. If unset, rtl_macro_placer will + calculate a value based on the design attributes. + stages: + - floorplan +RTLMP_MIN_AR: + description: > + Specifies the minimum aspect ratio (height/width). + default: 0.33 + stages: + - floorplan +RTLMP_SIGNATURE_NET_THRESHOLD: + description: > + Minimum number of connections between two clusters to be identified as + connected. + default: 50 + stages: + - floorplan +RTLMP_AREA_WT: + description: > + Weight for the area of the current floorplan. + default: 0.1 + stages: + - floorplan +RTLMP_WIRELENGTH_WT: + description: > + Weight for half-perimiter wirelength. + default: 100.0 + stages: + - floorplan +RTLMP_OUTLINE_WT: + description: > + Weight for violating the fixed outline constraint, meaning that all + clusters should be placed within the shape of their parent cluster. + default: 100.00 + stages: + - floorplan +RTLMP_BOUNDARY_WT: + description: > + Weight for the boundary or how far the hard macro clusters are from + boundaries. + default: 50.0 + stages: + - floorplan +RTLMP_NOTCH_WT: + description: > + Weight for the notch, or the existence of dead space that cannot be used + for placement and routing. + default: 10.0 + stages: + - floorplan +RTLMP_DEAD_SPACE: + description: > + Specifies the target dead space percentage, which influences the + utilization of a cluster. + default: 0.05 + stages: + - floorplan +RTLMP_RPT_DIR: + description: > + Path to the directory where reports are saved. + stages: + - floorplan +RTLMP_FENCE_LX: + description: > + Defines the lower left X coordinate for the global fence bounding box in + microns. + default: 0.0 + stages: + - floorplan +RTLMP_FENCE_LY: + description: > + Defines the lower left Y coordinate for the global fence bounding box in + microns. + default: 0.0 + stages: + - floorplan +RTLMP_FENCE_UX: + description: > + Defines the upper right X coordinate for the global fence bounding box in + microns. + default: 100000000.0 + stages: + - floorplan +RTLMP_FENCE_UY: + description: > + Defines the upper right Y coordinate for the global fence bounding box in + microns. + default: 100000000.0 + stages: + - floorplan +RTLMP_ARGS: + description: > + Overrides all other RTL macro placer arguments. + stages: + - floorplan diff --git a/flow/test/test-do-stage.sh b/flow/test/test-do-stage.sh new file mode 100755 index 0000000000..afd64ff4e2 --- /dev/null +++ b/flow/test/test-do-stage.sh @@ -0,0 +1,15 @@ +#!/usr/bin/env bash +set -ex +make clean_all +make do-yosys-canonicalize +make do-yosys-keep-hierarchy +make do-yosys +make do-synth +make do-floorplan +make do-place +make do-cts +make do-route +make do-final +make do-generate_abstract + + diff --git a/flow/test/test_helper.sh b/flow/test/test_helper.sh index 594541c98b..9b2409d114 100755 --- a/flow/test/test_helper.sh +++ b/flow/test/test_helper.sh @@ -77,23 +77,7 @@ if [ $ret -eq 0 ] && grep -q 'power:' <(echo $TARGETS); then ret=$(( ret + $? )) fi -# Run Autotuner CI specifically for gcd on selected platforms. -RUN_AUTOTUNER=0 -case $DESIGN_NAME in - "gcd") - RUN_AUTOTUNER=1 - ;; -esac -case $PLATFORM in - "asap7" | "sky130hd" | "ihp-sg13g2" ) - # Keep RUN_AUTOTUNER enabled only for these platforms - ;; - *) - RUN_AUTOTUNER=0 - ;; -esac - -if [ $RUN_AUTOTUNER -eq 1 ]; then +if [[ -n "${RUN_AUTOTUNER+x}" ]] && [[ ${RUN_AUTOTUNER} -eq 1 ]]; then # run the commands in ORFS root dir echo "[INFO FLW-0029] Installing dependencies in virtual environment." cd ../ diff --git a/flow/util/convertDrc.py b/flow/util/convertDrc.py index f16f3a6f75..4e0346fe02 100644 --- a/flow/util/convertDrc.py +++ b/flow/util/convertDrc.py @@ -1,10 +1,118 @@ # This is a KLayout script to load a RVE DRC rpt file # and write out a json the DRC viewer can read. +import os import pya - import json + +def convert_drc(rdb): + source = os.path.abspath(in_drc) + + ordb = {"source": source, "description": "KLayout DRC conversion", "category": {}} + + for category in rdb.each_category(): + if category.num_items() == 0: + # ignore categories with no data + continue + + ordb_category = { + "description": category.description, + "source": source, + "violations": [], + } + ordb["category"][category.name()] = ordb_category + + for item in rdb.each_item_per_category(category.rdb_id()): + violation = { + "visited": item.is_visited(), + "visible": True, + "waived": "waived" in item.tags_str, + } + + ordb_category["violations"].append(violation) + + shapes = [] + violation["shape"] = shapes + + text = [] + + for value in item.each_value(): + if value.is_box(): + shapes.append( + { + "type": "box", + "points": [ + {"x": value.box().left, "y": value.box().bottom}, + {"x": value.box().right, "y": value.box().top}, + ], + } + ) + elif value.is_edge(): + shapes.append( + { + "type": "line", + "points": [ + {"x": value.edge().p1.x, "y": value.edge().p1.y}, + {"x": value.edge().p2.x, "y": value.edge().p2.y}, + ], + } + ) + elif value.is_edge_pair(): + edge1 = value.edge_pair().first + edge2 = value.edge_pair().second + + shapes.append( + { + "type": "line", + "points": [ + {"x": edge1.p1.x, "y": edge1.p1.y}, + {"x": edge1.p2.x, "y": edge1.p2.y}, + ], + } + ) + shapes.append( + { + "type": "line", + "points": [ + {"x": edge2.p1.x, "y": edge2.p1.y}, + {"x": edge2.p2.x, "y": edge2.p2.y}, + ], + } + ) + elif value.is_polygon(): + points = [] + for edge in value.polygon().each_edge(): + points.append({"x": edge.p1.x, "y": edge.p1.y}) + points.append({"x": edge.p2.x, "y": edge.p2.y}) + shapes.append({"type": "polygon", "points": points}) + elif value.is_path(): + points = [] + for edge in value.path().polygon().each_edge(): + points.append({"x": edge.p1.x, "y": edge.p1.y}) + points.append({"x": edge.p2.x, "y": edge.p2.y}) + shapes.append({"type": "polygon", "points": points}) + elif value.is_text(): + text.append(value.text()) + elif value.is_string(): + text.append(value.string()) + else: + print("[WARN] Unknown violation shape:", value) + + comment = "" + if hasattr(item, "comment"): + comment = item.comment + if text: + if comment: + comment += ": " + comment += ", ".join(text) + + if comment: + violation["comment"] = comment + + return ordb + + app = pya.Application.instance() win = app.main_window() @@ -16,68 +124,10 @@ rdb = layout_view.rdb(rdb_id) rdb.load(in_drc) -violations = [] - -for category in rdb.each_category(): - if category.num_items() == 0: - # ignore categories with no data - continue - - violations_shapes = [] - for item in rdb.each_item_per_category(category.rdb_id()): - for value in item.each_value(): - if value.is_box(): - violations_shapes.append( - { - "type": "box", - "shape": [ - {"x": value.box().left, "y": value.box().bottom}, - {"x": value.box().right, "y": value.box().top}, - ], - } - ) - elif value.is_edge(): - violations_shapes.append( - { - "type": "edge", - "shape": [ - {"x": value.edge().p1.x, "y": value.edge().p1.y}, - {"x": value.edge().p2.x, "y": value.edge().p2.y}, - ], - } - ) - elif value.is_edge_pair(): - edge1 = value.edge_pair().first - edge2 = value.edge_pair().second - violations_shapes.append( - { - "type": "edge_pair", - "shape": [ - {"x": edge1.p1.x, "y": edge1.p1.y}, - {"x": edge1.p2.x, "y": edge1.p2.y}, - {"x": edge2.p1.x, "y": edge2.p1.y}, - {"x": edge2.p2.x, "y": edge2.p2.y}, - ], - } - ) - elif value.is_polygon(): - points = [] - for edge in value.polygon().each_edge(): - points.append({"x": edge.p1.x, "y": edge.p1.y}) - points.append({"x": edge.p2.x, "y": edge.p2.y}) - violations_shapes.append({"type": "polygon", "shape": points}) - else: - print("Unknown violation shape:", value) - - violations.append( - { - "name": category.name(), - "description": category.description, - "violations": violations_shapes, - } - ) +ordb = {} +ordb["DRC"] = convert_drc(rdb) with open(out_file, "w") as outfile: - json.dump({"DRC": violations}, outfile) + json.dump(ordb, outfile) app.exit(0) diff --git a/flow/util/genMetrics.py b/flow/util/genMetrics.py index a937b3a26b..9c4ecba2ce 100755 --- a/flow/util/genMetrics.py +++ b/flow/util/genMetrics.py @@ -313,14 +313,13 @@ def extract_metrics(cwd, platform, design, flow_variant, output, hier_json): extractGnuTime("synth", metrics_dict, logPath + "/1_1_yosys.log") extractGnuTime("floorplan", metrics_dict, logPath + "/2_1_floorplan.log") extractGnuTime("floorplan_io", metrics_dict, logPath + "/2_2_floorplan_io.log") - extractGnuTime("floorplan_tdms", metrics_dict, logPath + "/2_3_floorplan_tdms.log") extractGnuTime( - "floorplan_macro", metrics_dict, logPath + "/2_4_floorplan_macro.log" + "floorplan_macro", metrics_dict, logPath + "/2_3_floorplan_macro.log" ) extractGnuTime( - "floorplan_tap", metrics_dict, logPath + "/2_5_floorplan_tapcell.log" + "floorplan_tap", metrics_dict, logPath + "/2_4_floorplan_tapcell.log" ) - extractGnuTime("floorplan_pdn", metrics_dict, logPath + "/2_6_floorplan_pdn.log") + extractGnuTime("floorplan_pdn", metrics_dict, logPath + "/2_5_floorplan_pdn.log") extractGnuTime( "globalplace_skip_io", metrics_dict, logPath + "/3_1_place_gp_skip_io.log" ) diff --git a/tools/AutoTuner/src/autotuner/distributed.py b/tools/AutoTuner/src/autotuner/distributed.py index 9af8da60a0..fc84c9a05a 100644 --- a/tools/AutoTuner/src/autotuner/distributed.py +++ b/tools/AutoTuner/src/autotuner/distributed.py @@ -789,7 +789,7 @@ def parse_arguments(): type=int, metavar="", default=1, - help="Number of CPUs to request for each tunning job.", + help="Number of CPUs to request for each tuning job.", ) tune_parser.add_argument( "--reference", diff --git a/tools/OpenROAD b/tools/OpenROAD index 86a2cb529c..dc6a3ac80d 160000 --- a/tools/OpenROAD +++ b/tools/OpenROAD @@ -1 +1 @@ -Subproject commit 86a2cb529cd3965e546b484792e8724d81703a00 +Subproject commit dc6a3ac80d520240bf8154fd31941391cd9fa504 diff --git a/tools/yosys b/tools/yosys index e97731b9dd..9ed031ddd5 160000 --- a/tools/yosys +++ b/tools/yosys @@ -1 +1 @@ -Subproject commit e97731b9dda91fa5fa53ed87df7c34163ba59a41 +Subproject commit 9ed031ddd588442f22be13ce608547a5809b62f0