From 103e52fbdcf472579ae0e554d37a8042657c3cc4 Mon Sep 17 00:00:00 2001 From: Matthew Naylor Date: Sun, 2 Sep 2018 15:05:46 +0000 Subject: [PATCH] Update README --- README.md | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/README.md b/README.md index 9e13b29f..9a7fa372 100644 --- a/README.md +++ b/README.md @@ -343,8 +343,8 @@ structure of each cache. `LogDCachesPerDRAM` | 3 | Caches per DRAM `DCacheLogWordsPerBeat` | 3 | Number of 32-bit words per beat `DCacheLogBeatsPerLine` | 0 | Beats per cache line - `DCacheLogNumWays` | 3 | Cache lines in each associative set - `DCacheLogSetsPerThread` | 2 | Associative sets per thread + `DCacheLogNumWays` | 2 | Cache lines in each associative set + `DCacheLogSetsPerThread` | 3 | Associative sets per thread `LogBeatsPerDRAM` | 26 | Size of DRAM ## 4. Tinsel Mailbox @@ -805,8 +805,8 @@ ALMs, *58% of the DE5-Net*. `LogDCachesPerDRAM` | 3 | Caches per DRAM `DCacheLogWordsPerBeat` | 3 | Number of 32-bit words per beat `DCacheLogBeatsPerLine` | 0 | Beats per cache line - `DCacheLogNumWays` | 3 | Cache lines in each associative set - `DCacheLogSetsPerThread` | 2 | Associative sets per thread + `DCacheLogNumWays` | 2 | Cache lines in each associative set + `DCacheLogSetsPerThread` | 3 | Associative sets per thread `LogBeatsPerDRAM` | 26 | Size of DRAM `SRAMAddrWidth` | 20 | Address width of each off-chip SRAM `LogBytesPerSRAMBeat` | 3 | Data width of each off-chip SRAM