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S32X.sv
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S32X.sv
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//============================================================================
// FPGAGen port to MiSTer
// Copyright (c) 2017-2019 Sorgelig
//
// YM2612 implementation by Jose Tejada Gomez. Twitter: @topapate
// Original Genesis code: Copyright (c) 2010-2013 Gregory Estrade ([email protected])
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//============================================================================
module emu
(
//Master input clock
input CLK_50M,
//Async reset from top-level module.
//Can be used as initial reset.
input RESET,
//Must be passed to hps_io module
inout [48:0] HPS_BUS,
//Base video clock. Usually equals to CLK_SYS.
output CLK_VIDEO,
//Multiple resolutions are supported using different CE_PIXEL rates.
//Must be based on CLK_VIDEO
output CE_PIXEL,
//Video aspect ratio for HDMI. Most retro systems have ratio 4:3.
//if VIDEO_ARX[12] or VIDEO_ARY[12] is set then [11:0] contains scaled size instead of aspect ratio.
output [12:0] VIDEO_ARX,
output [12:0] VIDEO_ARY,
output [7:0] VGA_R,
output [7:0] VGA_G,
output [7:0] VGA_B,
output VGA_HS,
output VGA_VS,
output VGA_DE, // = ~(VBlank | HBlank)
output VGA_F1,
output [1:0] VGA_SL,
output VGA_SCALER, // Force VGA scaler
output VGA_DISABLE, // analog out is off
input [11:0] HDMI_WIDTH,
input [11:0] HDMI_HEIGHT,
output HDMI_FREEZE,
`ifdef MISTER_FB
// Use framebuffer in DDRAM
// FB_FORMAT:
// [2:0] : 011=8bpp(palette) 100=16bpp 101=24bpp 110=32bpp
// [3] : 0=16bits 565 1=16bits 1555
// [4] : 0=RGB 1=BGR (for 16/24/32 modes)
//
// FB_STRIDE either 0 (rounded to 256 bytes) or multiple of pixel size (in bytes)
output FB_EN,
output [4:0] FB_FORMAT,
output [11:0] FB_WIDTH,
output [11:0] FB_HEIGHT,
output [31:0] FB_BASE,
output [13:0] FB_STRIDE,
input FB_VBL,
input FB_LL,
output FB_FORCE_BLANK,
`ifdef MISTER_FB_PALETTE
// Palette control for 8bit modes.
// Ignored for other video modes.
output FB_PAL_CLK,
output [7:0] FB_PAL_ADDR,
output [23:0] FB_PAL_DOUT,
input [23:0] FB_PAL_DIN,
output FB_PAL_WR,
`endif
`endif
output LED_USER, // 1 - ON, 0 - OFF.
// b[1]: 0 - LED status is system status OR'd with b[0]
// 1 - LED status is controled solely by b[0]
// hint: supply 2'b00 to let the system control the LED.
output [1:0] LED_POWER,
output [1:0] LED_DISK,
// I/O board button press simulation (active high)
// b[1]: user button
// b[0]: osd button
output [1:0] BUTTONS,
input CLK_AUDIO, // 24.576 MHz
output [15:0] AUDIO_L,
output [15:0] AUDIO_R,
output AUDIO_S, // 1 - signed audio samples, 0 - unsigned
output [1:0] AUDIO_MIX, // 0 - no mix, 1 - 25%, 2 - 50%, 3 - 100% (mono)
//ADC
inout [3:0] ADC_BUS,
//SD-SPI
output SD_SCK,
output SD_MOSI,
input SD_MISO,
output SD_CS,
input SD_CD,
//High latency DDR3 RAM interface
//Use for non-critical time purposes
output DDRAM_CLK,
input DDRAM_BUSY,
output [7:0] DDRAM_BURSTCNT,
output [28:0] DDRAM_ADDR,
input [63:0] DDRAM_DOUT,
input DDRAM_DOUT_READY,
output DDRAM_RD,
output [63:0] DDRAM_DIN,
output [7:0] DDRAM_BE,
output DDRAM_WE,
//SDRAM interface with lower latency
output SDRAM_CLK,
output SDRAM_CKE,
output [12:0] SDRAM_A,
output [1:0] SDRAM_BA,
inout [15:0] SDRAM_DQ,
output SDRAM_DQML,
output SDRAM_DQMH,
output SDRAM_nCS,
output SDRAM_nCAS,
output SDRAM_nRAS,
output SDRAM_nWE,
`ifdef MISTER_DUAL_SDRAM
//Secondary SDRAM
//Set all output SDRAM_* signals to Z ASAP if SDRAM2_EN is 0
input SDRAM2_EN,
output SDRAM2_CLK,
output [12:0] SDRAM2_A,
output [1:0] SDRAM2_BA,
inout [15:0] SDRAM2_DQ,
output SDRAM2_nCS,
output SDRAM2_nCAS,
output SDRAM2_nRAS,
output SDRAM2_nWE,
`endif
input UART_CTS,
output UART_RTS,
input UART_RXD,
output UART_TXD,
output UART_DTR,
input UART_DSR,
// Open-drain User port.
// 0 - D+/RX
// 1 - D-/TX
// 2..6 - USR2..USR6
// Set USER_OUT to 1 to read from USER_IN.
input [6:0] USER_IN,
output [6:0] USER_OUT,
input OSD_STATUS
);
assign ADC_BUS = 'Z;
assign {UART_RTS, UART_TXD, UART_DTR} = 0;
assign BUTTONS = osd_btn;
assign {SD_SCK, SD_MOSI, SD_CS} = 'Z;
assign LED_DISK = 0;
assign LED_POWER = 0;
assign LED_USER = rom_download | sav_pending;
assign VGA_SCALER= 0;
assign VGA_DISABLE = 0;
assign AUDIO_S = 1;
assign AUDIO_MIX = 0;
assign HDMI_FREEZE = 0;
wire [1:0] ar = status[49:48];
wire [7:0] arx,ary;
always_comb begin
case(res) // {V30, H40}
2'b00: begin // 256 x 224
arx = 8'd64;
ary = 8'd49;
end
2'b01: begin // 320 x 224
arx = status[30] ? 8'd10: 8'd64;
ary = status[30] ? 8'd7 : 8'd49;
end
2'b10: begin // 256 x 240
arx = 8'd128;
ary = 8'd105;
end
2'b11: begin // 320 x 240
arx = status[30] ? 8'd4 : 8'd128;
ary = status[30] ? 8'd3 : 8'd105;
end
endcase
end
wire vcrop_en = status[34];
wire [3:0] vcopt = status[53:50];
reg en216p;
reg [4:0] voff;
always @(posedge CLK_VIDEO) begin
en216p <= ((HDMI_WIDTH == 1920) && (HDMI_HEIGHT == 1080) && !forced_scandoubler && !scale);
voff <= (vcopt < 6) ? {vcopt,1'b0} : ({vcopt,1'b0} - 5'd24);
end
wire vga_de;
video_freak video_freak
(
.*,
.VGA_DE_IN(vga_de),
.ARX((!ar) ? arx : (ar - 1'd1)),
.ARY((!ar) ? ary : 12'd0),
.CROP_SIZE((en216p & vcrop_en) ? 10'd216 : 10'd0),
.CROP_OFF(voff),
.SCALE(status[55:54])
);
// Status Bit Map:
// Upper Lower
// 0 1 2 3 4 5 6
// 01234567890123456789012345678901 23456789012345678901234567890123
// 0123456789ABCDEFGHIJKLMNOPQRSTUV 0123456789ABCDEFGHIJKLMNOPQRSTUV
// XXXXXXXXXXXX XXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXXXXXX
`include "build_id.v"
localparam CONF_STR = {
"S32X;;",
"FS,32X;",
"-;",
"O67,Region,JP,US,EU;",
"O9,Auto Region,Header,Disabled;",
"D2ORS,Priority,US>EU>JP,EU>US>JP,US>JP>EU,JP>US>EU;",
"-;",
/*
"C,Cheats;",
"H1OO,Cheats Enabled,Yes,No;",
"-;",
*/
"D0RG,Load Backup RAM;",
"D0RH,Save Backup RAM;",
"D0OD,Autosave,Off,On;",
"-;",
"P1,Audio & Video;",
"P1-;",
"P1oGH,Aspect ratio,Original,Full Screen,[ARC1],[ARC2];",
"P1OU,320x224 Aspect,Original,Corrected;",
"P1O13,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%,CRT 75%;",
"P1-;",
"d5P1o2,Vertical Crop,Disabled,216p(5x);",
"d5P1oIL,Crop Offset,0,2,4,8,10,12,-12,-10,-8,-6,-4,-2;",
"P1oMN,Scale,Normal,V-Integer,Narrower HV-Integer,Wider HV-Integer;",
"P1-;",
"P1OT,Border,No,Yes;",
"P1oEF,Composite Blend,Off,On,Adaptive;",
"P1-;",
"P1OEF,Audio Filter,Model 1,Model 2,Minimal,No Filter;",
"P1OB,FM Chip,YM2612,YM3438;",
"P1ON,HiFi PCM,No,Yes;",
"P2,Input;",
"P2-;",
"P2O4,Swap Joysticks,No,Yes;",
"P2O5,6 Buttons Mode,No,Yes;",
"P2o57,Multitap,Disabled,4-Way,TeamPlayer: Port1,TeamPlayer: Port2,J-Cart;",
"P2-;",
"P2OIJ,Mouse,None,Port1,Port2;",
"P2OK,Mouse Flip Y,No,Yes;",
"P2-;",
"P2oD,Serial,OFF,SNAC;",
"P2-;",
"P2o89,Gun Control,Disabled,Joy1,Joy2,Mouse;",
"D4P2oA,Gun Fire,Joy,Mouse;",
"D4P2oBC,Cross,Small,Medium,Big,None;",
"P3,Miscellaneous;",
"P3-;",
"P3o34,ROM Storage,Auto,SDRAM,DDR3;",
"P3-;",
"P3OPQ,CPU Turbo,None,Medium,High;",
"P3OV,Sprite Limit,Normal,High;",
"P3-;",
"- ;",
"H3o0,Enable FM,Yes,No;",
"H3o1,Enable PSG,Yes,No;",
"H3-;",
"R0,Reset;",
"J1,A,B,C,Start,Mode,X,Y,Z;",
"jn,A,B,R,Start,Select,X,Y,L;", // name map to SNES layout.
"jp,Y,B,A,Start,Select,L,X,R;", // positional map to SNES layout (3 button friendly)
"V,v",`BUILD_DATE
};
wire [63:0] status;
wire [1:0] buttons;
wire [11:0] joystick_0,joystick_1,joystick_2,joystick_3,joystick_4;
wire [7:0] joy0_x,joy0_y,joy1_x,joy1_y;
wire ioctl_download;
wire ioctl_wr;
wire [24:0] ioctl_addr;
wire [15:0] ioctl_data;
wire [7:0] ioctl_index;
reg ioctl_wait = 0;
reg [31:0] sd_lba;
reg sd_rd = 0;
reg sd_wr = 0;
wire sd_ack;
wire [7:0] sd_buff_addr;
wire [15:0] sd_buff_dout;
wire [15:0] sd_buff_din;
wire sd_buff_wr;
wire img_mounted;
wire img_readonly;
wire [63:0] img_size;
wire forced_scandoubler;
wire [10:0] ps2_key;
wire [24:0] ps2_mouse;
wire [21:0] gamma_bus;
wire [15:0] sdram_sz;
hps_io #(.CONF_STR(CONF_STR), .WIDE(1)) hps_io
(
.clk_sys(clk_sys),
.HPS_BUS(HPS_BUS),
.joystick_0(joystick_0),
.joystick_1(joystick_1),
.joystick_2(joystick_2),
.joystick_3(joystick_3),
.joystick_4(joystick_4),
.joystick_l_analog_0({joy0_y, joy0_x}),
.joystick_l_analog_1({joy1_y, joy1_x}),
.buttons(buttons),
.forced_scandoubler(forced_scandoubler),
.new_vmode(new_vmode),
.status(status),
.status_in({status[63:8],region_req,status[5:0]}),
.status_set(region_set),
.status_menumask({en216p,!gun_mode,1'b1,status[9],~gg_available,~bk_ena}),
.ioctl_download(ioctl_download),
.ioctl_index(ioctl_index),
.ioctl_wr(ioctl_wr),
.ioctl_addr(ioctl_addr),
.ioctl_dout(ioctl_data),
.ioctl_wait(ioctl_wait),
.sd_lba('{sd_lba}),
.sd_rd(sd_rd),
.sd_wr(sd_wr),
.sd_ack(sd_ack),
.sd_buff_addr(sd_buff_addr),
.sd_buff_dout(sd_buff_dout),
.sd_buff_din('{sd_buff_din}),
.sd_buff_wr(sd_buff_wr),
.img_mounted(img_mounted),
.img_readonly(img_readonly),
.img_size(img_size),
.gamma_bus(gamma_bus),
.sdram_sz(sdram_sz),
.ps2_key(ps2_key),
.ps2_mouse(ps2_mouse)
);
wire [1:0] gun_mode = status[41:40];
wire gun_btn_mode = status[42];
wire code_index = &ioctl_index;
wire rom_download = ioctl_download & ~code_index;
wire code_download = ioctl_download & code_index;
reg osd_btn = 0;
always @(posedge clk_sys) begin
integer timeout = 0;
reg has_bootrom = 0;
reg last_rst = 0;
if (RESET) last_rst = 0;
if (status[0]) last_rst = 1;
if (rom_download & ioctl_wr & status[0]) has_bootrom <= 1;
if(last_rst & ~status[0]) begin
osd_btn <= 0;
if(timeout < 24000000) begin
timeout <= timeout + 1;
osd_btn <= ~has_bootrom;
end
end
end
///////////////////////////////////////////////////
wire clk_sys, clk_ram, locked;
pll pll
(
.refclk(CLK_50M),
.rst(0),
.outclk_0(clk_sys),
.outclk_1(clk_ram),
.reconfig_to_pll(reconfig_to_pll),
.reconfig_from_pll(reconfig_from_pll),
.locked(locked)
);
wire [63:0] reconfig_to_pll;
wire [63:0] reconfig_from_pll;
wire cfg_waitrequest;
reg cfg_write;
reg [5:0] cfg_address;
reg [31:0] cfg_data;
pll_cfg pll_cfg
(
.mgmt_clk(CLK_50M),
.mgmt_reset(0),
.mgmt_waitrequest(cfg_waitrequest),
.mgmt_read(0),
.mgmt_readdata(),
.mgmt_write(cfg_write),
.mgmt_address(cfg_address),
.mgmt_writedata(cfg_data),
.reconfig_to_pll(reconfig_to_pll),
.reconfig_from_pll(reconfig_from_pll)
);
always @(posedge CLK_50M) begin
reg pald = 0, pald2 = 0;
reg [2:0] state = 0;
reg pal_r;
pald <= PAL;
pald2 <= pald;
cfg_write <= 0;
if(pald2 == pald && pald2 != pal_r) begin
state <= 1;
pal_r <= pald2;
end
if(!cfg_waitrequest) begin
if(state) state<=state+1'd1;
case(state)
1: begin
cfg_address <= 0;
cfg_data <= 0;
cfg_write <= 1;
end
5: begin
cfg_address <= 7;
cfg_data <= pal_r ? 2201376125 : 2537930535;
cfg_write <= 1;
end
7: begin
cfg_address <= 2;
cfg_data <= 0;
cfg_write <= 1;
end
endcase
end
end
wire reset = RESET | status[0] | buttons[1] | region_set;
///////////////////////////////////////////////////
// Code loading for WIDE IO (16 bit)
reg [128:0] gg_code;
wire gg_available;
// Code layout:
// {clock bit, code flags, 32'b address, 32'b compare, 32'b replace}
// 128 127:96 95:64 63:32 31:0
// Integer values are in BIG endian byte order, so it up to the loader
// or generator of the code to re-arrange them correctly.
always_ff @(posedge clk_sys) begin
gg_code[128] <= 1'b0;
if (code_download & ioctl_wr) begin
case (ioctl_addr[3:0])
0: gg_code[111:96] <= ioctl_data; // Flags Bottom Word
2: gg_code[127:112] <= ioctl_data; // Flags Top Word
4: gg_code[79:64] <= ioctl_data; // Address Bottom Word
6: gg_code[95:80] <= ioctl_data; // Address Top Word
8: gg_code[47:32] <= ioctl_data; // Compare Bottom Word
10: gg_code[63:48] <= ioctl_data; // Compare top Word
12: gg_code[15:0] <= ioctl_data; // Replace Bottom Word
14: begin
gg_code[31:16] <= ioctl_data; // Replace Top Word
gg_code[128] <= 1'b1; // Clock it in
end
endcase
end
end
//Genesis
wire [23:1] GEN_VA;
wire [15:0] GEN_VDI, GEN_VDO;
wire GEN_RNW, GEN_LDS_N, GEN_UDS_N;
wire GEN_AS_N, GEN_DTACK_N, GEN_ASEL_N;
wire GEN_RAS2_N, GEN_CAS2_N;
wire EXT_ROM_N;
wire EXT_FDC_N;
wire GEN_VCLK_CE;
wire GEN_CE0_N;
wire GEN_LWR_N, GEN_UWR_N, GEN_CAS0_N;
wire GEN_ROM_CE_N;
wire GEN_RAM_CE_N;
wire GEN_TIME_N;
//wire [15:0] GEN_MEM_DO;
wire GEN_MEM_BUSY;
wire [7:0] color_lut[16] = '{
8'd0, 8'd27, 8'd49, 8'd71,
8'd87, 8'd103, 8'd119, 8'd130,
8'd146, 8'd157, 8'd174, 8'd190,
8'd206, 8'd228, 8'd255, 8'd255
};
wire [3:0] GEN_R, GEN_G, GEN_B;
wire YS_N;
wire EDCLK;
wire vs,hs;
wire ce_pix;
wire hblank, vblank;
wire interlace;
wire [1:0] resolution;
gen gen
(
.RESET_N(~reset),
.MCLK(clk_sys),
.VA(GEN_VA),
.VDI(GEN_VDI),
.VDO(GEN_VDO),
.RNW(GEN_RNW),
.LDS_N(GEN_LDS_N),
.UDS_N(GEN_UDS_N),
.AS_N(GEN_AS_N),
.DTACK_N(GEN_DTACK_N),
.ASEL_N(GEN_ASEL_N),
.VCLK_CE(GEN_VCLK_CE),
.CE0_N(GEN_CE0_N),
.RAS2_N(GEN_RAS2_N),
.CAS2_N(GEN_CAS2_N),
.ROM_N(EXT_ROM_N),
.FDC_N(EXT_FDC_N),
.CART_N(0),
.DISK_N(1),
.LWR_N(GEN_LWR_N),
.UWR_N(GEN_UWR_N),
.CAS0_N(GEN_CAS0_N),
.TIME_N(GEN_TIME_N),
.LOADING(rom_download),
.EXPORT(|status[7:6]),
.PAL(PAL),
.RED(GEN_R),
.GREEN(GEN_G),
.BLUE(GEN_B),
.YS_N(YS_N),
.EDCLK(EDCLK),
.VS(vs),
.HS(hs),
.HBL(hblank),
.VBL(vblank),
.BORDER(status[29]),
.CE_PIX(ce_pix),
.FIELD(VGA_F1),
.INTERLACE(interlace),
.RESOLUTION(resolution),
.J3BUT(~status[5]),
.JOY_1(status[4] ? joystick_1 : joystick_0),
.JOY_2(status[4] ? joystick_0 : joystick_1),
.JOY_3(joystick_2),
.JOY_4(joystick_3),
.JOY_5(joystick_4),
.MULTITAP(status[22:21]),
.MOUSE(ps2_mouse),
.MOUSE_OPT(status[20:18]),
.GUN_OPT(|gun_mode),
.GUN_TYPE(gun_type),
.GUN_SENSOR(lg_sensor),
.GUN_A(lg_a),
.GUN_B(lg_b),
.GUN_C(lg_c),
.GUN_START(lg_start),
.SERJOYSTICK_IN(SERJOYSTICK_IN),
.SERJOYSTICK_OUT(SERJOYSTICK_OUT),
.SER_OPT(SER_OPT),
.EN_GEN_FM(EN_GEN_FM),
.EN_GEN_PSG(EN_GEN_PSG),
.EN_32X_PWM(EN_32X_PWM),
.EN_HIFI_PCM(status[23]), // Option "N"
.LADDER(~status[8]),
.LPF_MODE(status[15:14]),
.FMBUSY_QUIRK(fmbusy_quirk),
.EXT_SL(S32X_SL),
.EXT_SR(S32X_SR),
.DAC_LDATA(AUDIO_L),
.DAC_RDATA(AUDIO_R),
.OBJ_LIMIT_HIGH(status[31]),
.MEM_RDY(~GEN_MEM_BUSY),
.GG_RESET(code_download && ioctl_wr && !ioctl_addr),
.GG_EN(status[24]),
.GG_CODE({~gg_code[95] & gg_code[128], gg_code[127:0]}),
.GG_AVAILABLE(gg_available),
.PAUSE_EN(DBG_PAUSE_EN),
.BGA_EN(VDP_BGA_EN),
.BGB_EN(VDP_BGB_EN),
.SPR_EN(VDP_SPR_EN),
.BG_GRID_EN(VDP_BG_GRID_EN),
.SPR_GRID_EN(VDP_SPR_GRID_EN)
);
assign GEN_MEM_BUSY = !GEN_RAS2_N ? 1'b0 :
CART_SRAM_RD || CART_SRAM_WR ? sdr_busy[2] :
sdr_busy[1];
assign GEN_VDI = s32x_rom ? S32X_VDO : CART_VDO;
assign GEN_DTACK_N = S32X_DTACK_N & CART_DTACK_N;
// 32X
wire [23:1] S32X_CA;
wire [15:0] S32X_CDO;
wire [15:0] S32X_CDI;
wire S32X_CASEL_N;
wire S32X_CLWR_N;
wire S32X_CUWR_N;
wire S32X_CCE0_N;
wire S32X_CCAS0_N;
wire S32X_CCAS2_N;
wire [15:0] S32X_VDO;
wire S32X_DTACK_N;
wire [17:1] S32X_SDR_A;
wire [15:0] S32X_SDR_DO;
reg [15:0] S32X_SDR_DI;
wire S32X_SDR_CS;
wire [1:0] S32X_SDR_WE;
wire S32X_SDR_RD;
wire S32X_SDR_WAIT;
wire [15:0] S32X_MEM_DO;
wire S32X_ROM_WAIT;
wire [15:0] S32X_FB0_A;
wire [15:0] S32X_FB0_DI;
wire [15:0] S32X_FB0_DO;
wire [1:0] S32X_FB0_WE;
wire S32X_FB0_RD;
wire [15:0] S32X_FB1_A;
wire [15:0] S32X_FB1_DI;
wire [15:0] S32X_FB1_DO;
wire [1:0] S32X_FB1_WE;
wire S32X_FB1_RD;
wire [4:0] S32X_R;
wire [4:0] S32X_G;
wire [4:0] S32X_B;
wire S32X_YSO_N;
wire [15:0] S32X_SL;
wire [15:0] S32X_SR;
S32X #(
.USE_ROM_WAIT(1),
.USE_ASYNC_FB(0)
) S32X
(
.RST_N(~(reset | rom_download)),
.CLK(clk_sys),
.VCLK(GEN_VCLK_CE),
.VA(GEN_VA),
.VDI(GEN_VDO),
.VDO(S32X_VDO),
.AS_N(GEN_AS_N),
.DTACK_N(S32X_DTACK_N),
.LWR_N(GEN_LWR_N),
.UWR_N(GEN_UWR_N),
.CE0_N(GEN_CE0_N),
.CAS0_N(GEN_CAS0_N),
.CAS2_N(GEN_CAS2_N),
.ASEL_N(GEN_ASEL_N),
.VRES_N(1'b1),
.MRES_N(1'b1),
.CART_N(1'b0),
.VSYNC_N(vs),
.HSYNC_N(hs),
.EDCLK(EDCLK),
.YS_N(YS_N),
.PAL(PAL),
.CA(S32X_CA),
.CDI(S32X_CDI),
.CDO(S32X_CDO),
.CASEL_N(S32X_CASEL_N),
.CLWR_N(S32X_CLWR_N),
.CUWR_N(S32X_CUWR_N),
.CCE0_N(S32X_CCE0_N),
.CCAS0_N(S32X_CCAS0_N),
.CCAS2_N(S32X_CCAS2_N),
.ROM_WAIT(S32X_ROM_WAIT),
.SDR_A(S32X_SDR_A),
.SDR_DI(S32X_SDR_DI),
.SDR_DO(S32X_SDR_DO),
.SDR_CS(S32X_SDR_CS),
.SDR_WE(S32X_SDR_WE),
.SDR_RD(S32X_SDR_RD),
.SDR_WAIT(S32X_SDR_WAIT),
.FB0_A(S32X_FB0_A),
.FB0_DI(S32X_FB0_DI),
.FB0_DO(S32X_FB0_DO),
.FB0_WE(S32X_FB0_WE),
.FB0_RD(S32X_FB0_RD),
.FB1_A(S32X_FB1_A),
.FB1_DI(S32X_FB1_DI),
.FB1_DO(S32X_FB1_DO),
.FB1_WE(S32X_FB1_WE),
.FB1_RD(S32X_FB1_RD),
.R(S32X_R),
.G(S32X_G),
.B(S32X_B),
.YSO_N(S32X_YSO_N),
.PWM_L(S32X_SL),
.PWM_R(S32X_SR)
);
assign S32X_CDI = CART_VDO;
assign S32X_ROM_WAIT = CART_SRAM_RD || CART_SRAM_WR ? sdr_busy[2] : sdr_busy[1];
//Cart
wire [15:0] CART_VDO;
wire CART_DTACK_N;
wire [23:1] CART_ROM_A;
wire [15:0] CART_ROM_DI;
wire [15:0] CART_ROM_DO;
wire CART_ROM_WRL;
wire CART_ROM_WRH;
wire CART_ROM_RD;
wire [15:1] CART_SRAM_A;
wire [7:0] CART_SRAM_DI;
wire [7:0] CART_SRAM_DO;
wire CART_SRAM_WR;
wire CART_SRAM_RD;
CART cart
(
.CLK(clk_sys),
.RST_N(~(reset || rom_download)),
.VCLK(GEN_VCLK_CE),
.VA(!s32x_rom ? GEN_VA : S32X_CA),
.VDI(!s32x_rom ? GEN_VDO : S32X_CDO),
.VDO(CART_VDO),
.AS_N(GEN_AS_N),
.DTACK_N(CART_DTACK_N),
.LWR_N(!s32x_rom ? GEN_LWR_N : S32X_CLWR_N),
.UWR_N(!s32x_rom ? GEN_UWR_N : S32X_CUWR_N),
.CE0_N(!s32x_rom ? GEN_CE0_N : S32X_CCE0_N),
.CAS0_N(!s32x_rom ? GEN_CAS0_N : S32X_CCAS0_N),
.CAS2_N(!s32x_rom ? GEN_CAS2_N : S32X_CCAS2_N),
.ASEL_N(!s32x_rom ? GEN_ASEL_N : S32X_CASEL_N),
.TIME_N(GEN_TIME_N),
.ROM_A(CART_ROM_A),
.ROM_DI(CART_ROM_DI),
.ROM_DO(CART_ROM_DO),
.ROM_RD(CART_ROM_RD),
.ROM_WRL(CART_ROM_WRL),
.ROM_WRH(CART_ROM_WRH),
.SRAM_A(CART_SRAM_A),
.SRAM_DI(CART_SRAM_DI),
.SRAM_DO(CART_SRAM_DO),
.SRAM_RD(CART_SRAM_RD),
.SRAM_WR(CART_SRAM_WR),
.rom_sz(rom_sz),
.s32x(s32x_rom),
.eeprom_map(eeprom_map),
.noram_quirk(noram_quirk),
.realtec_map(realtec_map),
.sf_map(sf_map)
);
assign CART_ROM_DI = sdr_do[1];
assign CART_SRAM_DI = sdr_do[2][7:0];
always @(posedge clk_sys) begin
reg old_busy;
old_busy <= sdr_busy[3];
if(rom_download & ioctl_wr) ioctl_wait <= 1;
if(old_busy & ~sdr_busy[3]) ioctl_wait <= 0;
end
reg use_sdr = 0;
wire ddr_busy;
wire [31:0] ddr_do;
ddram ddram
(
.*,
.clk(clk_ram),
.mem_addr({10'b0000000000,S32X_SDR_A}),
.mem_dout(ddr_do),
.mem_din({16'h0000,S32X_SDR_DO}),
.mem_rd(S32X_SDR_CS & S32X_SDR_RD),
.mem_wr({2'b00,{2{S32X_SDR_CS}} & S32X_SDR_WE}),
.mem_chan(0),
.mem_16b(1),
.mem_busy(ddr_busy)
);
assign S32X_SDR_DI = ddr_do[15:0];
assign S32X_SDR_WAIT = ddr_busy;
wire sdr_busy[4];
wire [15:0] sdr_do[4];
sdram sdram
(
.*,
.init(~locked),
.clk(clk_ram),
//SDRAM
.addr0({7'b1000000,S32X_SDR_A}), // 1000000-103FFFF
.din0(S32X_SDR_DO),
.dout0(sdr_do[0]),
.rd0(use_sdr & S32X_SDR_CS & S32X_SDR_RD),
.wr0(S32X_SDR_WE & {2{use_sdr & S32X_SDR_CS}}),
.busy0(sdr_busy[0]),
//CART ROM
.addr1({1'b0,CART_ROM_A[23:1]}),
.din1(CART_ROM_DO),
.dout1(sdr_do[1]),
.rd1(CART_ROM_RD | CART_ROM_WRL | CART_ROM_WRH),
.wr1({CART_ROM_WRH,CART_ROM_WRL} & {2{schan_quirk}}),
.busy1(sdr_busy[1]),
//CART SRAM
.addr2({9'b110000000,CART_SRAM_A[15:1]}), //CART RAM 1800000-180FFFF
.din2({8'hFF,CART_SRAM_DO}),
.dout2(sdr_do[2]),
.rd2(CART_SRAM_RD),
.wr2({2{CART_SRAM_WR}}),
.busy2(sdr_busy[2]),
//ROM/BRAM Load/Save
.addr3(rom_download ? {1'b0,ioctl_addr[23:1]} : {9'b110000000,sd_lba[6:0],tmpram_addr}),
.din3(rom_download ? {ioctl_data[7:0],ioctl_data[15:8]} : {tmpram_dout[7:0],tmpram_dout[15:8]}),
.dout3(sdr_do[3]),
.rd3(rom_download ? 1'b0 : (tmpram_req & ~bk_loading)),
.wr3(rom_download ? {2{ioctl_wait}} : {2{tmpram_req & bk_loading}}),
.busy3(sdr_busy[3])
);
`ifdef DUAL_SDRAM
wire sdr2_busy;
wire [15:0] sdr2_do;
sdram2 sdram2
(
.SDRAM_CLK(SDRAM2_CLK),
.SDRAM_A(SDRAM2_A),
.SDRAM_BA(SDRAM2_BA),
.SDRAM_DQ(SDRAM2_DQ),
.SDRAM_nCS(SDRAM2_nCS),
.SDRAM_nWE(SDRAM2_nWE),
.SDRAM_nRAS(SDRAM2_nRAS),
.SDRAM_nCAS(SDRAM2_nCAS),
.init(~locked),
.clk(clk_ram),
//
.addr0({8'b00000000,S32X_FB0_A}), // 0000000-001FFFF
.din0(S32X_FB0_DO),
.dout0(S32X_FB0_DI),
.rd0(S32X_FB0_RD),
.wrl0(S32X_FB0_WE[0]),
.wrh0(S32X_FB0_WE[1]),
.busy0(sdr2_busy),
//
.addr1('0),
.din1('0),
.dout1(),
.rd1(0),
.wrl1(0),
.wrh1(0),
.busy1(),
//
.addr2('0),
.din2('0),
.dout2(),
.rd2(0),
.wrl2(0),
.wrh2(0),
.busy2()
);
`else
spram #(16,8) vdp_fb0_l
(
.clock(clk_sys),
.address(S32X_FB0_A),
.data(S32X_FB0_DO[7:0]),
.wren(S32X_FB0_WE[0]),
.q(S32X_FB0_DI[7:0])
);
spram #(16,8) vdp_fb0_u
(
.clock(clk_sys),
.address(S32X_FB0_A),
.data(S32X_FB0_DO[15:8]),
.wren(S32X_FB0_WE[1]),
.q(S32X_FB0_DI[15:8])
);
`endif
spram #(16,8) vdp_fb1_l
(
.clock(clk_sys),
.address(S32X_FB1_A),
.data(S32X_FB1_DO[7:0]),
.wren(S32X_FB1_WE[0]),
.q(S32X_FB1_DI[7:0])
);
spram #(16,8) vdp_fb1_u
(
.clock(clk_sys),
.address(S32X_FB1_A),
.data(S32X_FB1_DO[15:8]),
.wren(S32X_FB1_WE[1]),
.q(S32X_FB1_DI[15:8])
);