Memora.yml

# Copyright 2021 ETH Zurich and University of Bologna.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0

cache_root_dir: /usr/scratch2/dolent1/gitlabci/buildcache/mempool

artifacts:
  tc-riscv-gcc:
    inputs:
      - Makefile
      - toolchain/riscv-gnu-toolchain
    outputs:
      - install/riscv-gcc

  tc-llvm:
    inputs:
      - Makefile
      - toolchain/llvm-project
    outputs:
      - install/llvm

  riscv-isa-sim:
    inputs:
      - Makefile
      - toolchain/riscv-isa-sim
      - toolchain/riscv-opcodes/encoding_out.h
    outputs:
      - install/riscv-isa-sim

  verilator:
    inputs:
      - Makefile
      - toolchain/verilator
    outputs:
      - install/verilator

  verilator-model:
    inputs:
      - Makefile
      - toolchain/verilator
      - config/config.mk
      - hardware/deps
      - hardware/src
      - hardware/tb
      - hardware/Makefile
    outputs:
      - hardware/verilator_build/Vmempool_tb_verilator

  halide:
    inputs:
      - Makefile
      - toolchain/halide
    outputs:
      - install/halide