diff --git a/lib/SPIRV/libSPIRV/SPIRVDecorate.cpp b/lib/SPIRV/libSPIRV/SPIRVDecorate.cpp
index 73e64b3e96..74999d9930 100644
--- a/lib/SPIRV/libSPIRV/SPIRVDecorate.cpp
+++ b/lib/SPIRV/libSPIRV/SPIRVDecorate.cpp
@@ -43,8 +43,8 @@
 #include "SPIRVValue.h"
 
 namespace SPIRV {
-template <class T, class B>
-spv_ostream &operator<<(spv_ostream &O, const std::multiset<T *, B> &V) {
+template <class T>
+spv_ostream &operator<<(spv_ostream &O, const std::vector<T *> &V) {
   for (auto &I : V)
     O << *I;
   return O;
@@ -244,57 +244,4 @@ void SPIRVGroupMemberDecorate::decorateTargets() {
     }
   }
 }
-
-bool SPIRVDecorateGeneric::Comparator::
-operator()(const SPIRVDecorateGeneric *A, const SPIRVDecorateGeneric *B) const {
-  auto Action = [=]() {
-    if (A->getOpCode() < B->getOpCode())
-      return true;
-    if (A->getOpCode() > B->getOpCode())
-      return false;
-    if (A->getDecorateKind() < B->getDecorateKind())
-      return true;
-    if (A->getDecorateKind() > B->getDecorateKind())
-      return false;
-    if (A->getLiteralCount() < B->getLiteralCount())
-      return true;
-    if (A->getLiteralCount() > B->getLiteralCount())
-      return false;
-    for (size_t I = 0, E = A->getLiteralCount(); I != E; ++I) {
-      auto EA = A->getLiteral(I);
-      auto EB = B->getLiteral(I);
-      if (EA < EB)
-        return true;
-      if (EA > EB)
-        return false;
-    }
-    return false;
-  };
-  auto Res = Action();
-  return Res;
-}
-
-bool operator==(const SPIRVDecorateGeneric &A, const SPIRVDecorateGeneric &B) {
-  if (A.getTargetId() != B.getTargetId())
-    return false;
-  if (A.getOpCode() != B.getOpCode())
-    return false;
-  if (B.isMemberDecorate()) {
-    auto &MDA = static_cast<SPIRVMemberDecorate const &>(A);
-    auto &MDB = static_cast<SPIRVMemberDecorate const &>(B);
-    if (MDA.getMemberNumber() != MDB.getMemberNumber())
-      return false;
-  }
-  if (A.getDecorateKind() != B.getDecorateKind())
-    return false;
-  if (A.getLiteralCount() != B.getLiteralCount())
-    return false;
-  for (size_t I = 0, E = A.getLiteralCount(); I != E; ++I) {
-    auto EA = A.getLiteral(I);
-    auto EB = B.getLiteral(I);
-    if (EA != EB)
-      return false;
-  }
-  return true;
-}
 } // namespace SPIRV
diff --git a/lib/SPIRV/libSPIRV/SPIRVDecorate.h b/lib/SPIRV/libSPIRV/SPIRVDecorate.h
index 121407eb79..e44058ec6b 100644
--- a/lib/SPIRV/libSPIRV/SPIRVDecorate.h
+++ b/lib/SPIRV/libSPIRV/SPIRVDecorate.h
@@ -67,15 +67,6 @@ class SPIRVDecorateGeneric : public SPIRVAnnotationGeneric {
   std::vector<SPIRVWord> getVecLiteral() const;
   Decoration getDecorateKind() const;
   size_t getLiteralCount() const;
-  /// Compare for kind and literal only.
-  struct Comparator {
-    bool operator()(const SPIRVDecorateGeneric *A,
-                    const SPIRVDecorateGeneric *B) const;
-  };
-  /// Compare kind, literals and target.
-  friend bool operator==(const SPIRVDecorateGeneric &A,
-                         const SPIRVDecorateGeneric &B);
-
   SPIRVDecorationGroup *getOwner() const { return Owner; }
 
   void setOwner(SPIRVDecorationGroup *Owner) { this->Owner = Owner; }
@@ -117,26 +108,7 @@ class SPIRVDecorateGeneric : public SPIRVAnnotationGeneric {
   SPIRVDecorationGroup *Owner; // Owning decorate group
 };
 
-class SPIRVDecorateSet
-    : public std::multiset<SPIRVDecorateGeneric *,
-                           SPIRVDecorateGeneric::Comparator> {
-public:
-  typedef std::multiset<SPIRVDecorateGeneric *,
-                        SPIRVDecorateGeneric::Comparator>
-      BaseType;
-  iterator insert(value_type &Dec) {
-    auto ER = BaseType::equal_range(Dec);
-    for (auto I = ER.first, E = ER.second; I != E; ++I) {
-      SPIRVDBG(spvdbgs() << "[compare decorate] " << *Dec << " vs " << **I
-                         << " : ");
-      if (**I == *Dec)
-        return I;
-      SPIRVDBG(spvdbgs() << " diff\n");
-    }
-    SPIRVDBG(spvdbgs() << "[add decorate] " << *Dec << '\n');
-    return BaseType::insert(Dec);
-  }
-};
+typedef std::vector<SPIRVDecorateGeneric *> SPIRVDecorateVec;
 
 class SPIRVDecorate : public SPIRVDecorateGeneric {
 public:
@@ -378,17 +350,17 @@ class SPIRVDecorationGroup : public SPIRVEntry {
   void encodeAll(spv_ostream &O) const override;
   _SPIRV_DCL_ENCDEC
   // Move the given decorates to the decoration group
-  void takeDecorates(SPIRVDecorateSet &Decs) {
+  void takeDecorates(SPIRVDecorateVec &Decs) {
     Decorations = std::move(Decs);
     for (auto &I : Decorations)
       const_cast<SPIRVDecorateGeneric *>(I)->setOwner(this);
     Decs.clear();
   }
 
-  SPIRVDecorateSet &getDecorations() { return Decorations; }
+  SPIRVDecorateVec &getDecorations() { return Decorations; }
 
 protected:
-  SPIRVDecorateSet Decorations;
+  SPIRVDecorateVec Decorations;
   void validate() const override {
     assert(OpCode == OC);
     assert(WordCount == WC);
diff --git a/lib/SPIRV/libSPIRV/SPIRVModule.cpp b/lib/SPIRV/libSPIRV/SPIRVModule.cpp
index e2de0a636b..9cd9249a77 100644
--- a/lib/SPIRV/libSPIRV/SPIRVModule.cpp
+++ b/lib/SPIRV/libSPIRV/SPIRVModule.cpp
@@ -518,7 +518,7 @@ class SPIRVModuleImpl : public SPIRVModule {
   SPIRVStringVec StringVec;
   SPIRVMemberNameVec MemberNameVec;
   std::shared_ptr<const SPIRVLine> CurrentLine;
-  SPIRVDecorateSet DecorateSet;
+  SPIRVDecorateVec DecorateVec;
   SPIRVDecGroupVec DecGroupVec;
   SPIRVGroupDecVec GroupDecVec;
   SPIRVAsmTargetVector AsmTargetVec;
@@ -993,7 +993,7 @@ SPIRVModuleImpl::addDecorate(SPIRVDecorateGeneric *Dec) {
   (void)Found;
   assert(Found && "Decorate target does not exist");
   if (!Dec->getOwner())
-    DecorateSet.insert(Dec);
+    DecorateVec.push_back(Dec);
   addCapabilities(Dec->getRequiredCapability());
   return Dec;
 }
@@ -1678,8 +1678,8 @@ spv_ostream &operator<<(spv_ostream &O, const std::vector<T *> &V) {
   return O;
 }
 
-template <class T, class B>
-spv_ostream &operator<<(spv_ostream &O, const std::multiset<T *, B> &V) {
+template <class T, class B = std::less<T>>
+spv_ostream &operator<<(spv_ostream &O, const std::unordered_set<T *, B> &V) {
   for (auto &I : V)
     O << *I;
   return O;
@@ -1870,7 +1870,7 @@ spv_ostream &operator<<(spv_ostream &O, SPIRVModule &M) {
                      MI.ForwardPointerVec);
 
   O << MI.MemberNameVec << MI.ModuleProcessedVec << MI.DecGroupVec
-    << MI.DecorateSet << MI.GroupDecVec << MI.ForwardPointerVec << TS;
+    << MI.DecorateVec << MI.GroupDecVec << MI.ForwardPointerVec << TS;
 
   if (M.isAllowedToUseExtension(ExtensionID::SPV_INTEL_inline_assembly)) {
     O << SPIRVNL() << MI.AsmTargetVec << MI.AsmVec;
@@ -1895,11 +1895,11 @@ SPIRVDecorationGroup *SPIRVModuleImpl::addDecorationGroup() {
 SPIRVDecorationGroup *
 SPIRVModuleImpl::addDecorationGroup(SPIRVDecorationGroup *Group) {
   add(Group);
-  Group->takeDecorates(DecorateSet);
+  Group->takeDecorates(DecorateVec);
   DecGroupVec.push_back(Group);
   SPIRVDBG(spvdbgs() << "[addDecorationGroup] {" << *Group << "}\n";
-           spvdbgs() << "  Remaining DecorateSet: {" << DecorateSet << "}\n");
-  assert(DecorateSet.empty());
+           spvdbgs() << "  Remaining DecorateVec: {" << DecorateVec << "}\n");
+  assert(DecorateVec.empty());
   return Group;
 }
 
diff --git a/test/LinkOnceODR.ll b/test/LinkOnceODR.ll
index e4f7c84784..e46b62f96a 100644
--- a/test/LinkOnceODR.ll
+++ b/test/LinkOnceODR.ll
@@ -10,8 +10,8 @@
 
 ; CHECK-SPIRV: Capability Linkage
 ; CHECK-SPIRV: Extension "SPV_KHR_linkonce_odr"
-; CHECK-SPIRV: Decorate {{[0-9]+}} LinkageAttributes "GV" LinkOnceODR 
-; CHECK-SPIRV: Decorate {{[0-9]+}} LinkageAttributes "square" LinkOnceODR 
+; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} LinkageAttributes "GV" LinkOnceODR 
+; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} LinkageAttributes "square" LinkOnceODR 
 
 ; CHECK-SPIRV-NOEXT-NOT: Extension "SPV_KHR_linkonce_odr"
 ; CHECK-SPIRV-NOEXT-NOT: Decorate {{[0-9]+}} LinkageAttributes "GV" LinkOnceODR 
diff --git a/test/SpecConstants/long-spec-const-composite.ll b/test/SpecConstants/long-spec-const-composite.ll
index 63ea861494..974a0776d1 100644
--- a/test/SpecConstants/long-spec-const-composite.ll
+++ b/test/SpecConstants/long-spec-const-composite.ll
@@ -13,8 +13,8 @@ target triple = "spir64-unknown-unknown"
 
 ; CHECK-SPIRV: Capability LongConstantCompositeINTEL 
 ; CHECK-SPIRV: Extension "SPV_INTEL_long_constant_composite"
-; CHECK-SPIRV: Decorate [[First:[0-9]+]] SpecId  0
-; CHECK-SPIRV: Decorate [[Last:[0-9]+]] SpecId 65548
+; CHECK-SPIRV-DAG: Decorate [[First:[0-9]+]] SpecId  0
+; CHECK-SPIRV-DAG: Decorate [[Last:[0-9]+]] SpecId 65548
 ; CHECK-SPIRV: TypeInt [[TInt:[0-9]+]] 8
 ; CHECK-SPIRV: SpecConstant [[TInt]] [[First]]
 ; CHECK-SPIRV: SpecConstant [[TInt]] [[Last]]
diff --git a/test/builtin_vars-decorate.ll b/test/builtin_vars-decorate.ll
index 5787959c88..51d1ce3e76 100644
--- a/test/builtin_vars-decorate.ll
+++ b/test/builtin_vars-decorate.ll
@@ -26,23 +26,23 @@ target triple = "spir-unknown-unknown"
 ; CHECK: {{[0-9]+}} Name [[SI:[0-9]+]] "__spirv_BuiltInSubgroupId"
 ; CHECK: {{[0-9]+}} Name [[SLII:[0-9]+]] "__spirv_BuiltInSubgroupLocalInvocationId"
 
-; CHECK: 4 Decorate [[NW]] BuiltIn 24
-; CHECK: 4 Decorate [[WS]] BuiltIn 25
-; CHECK: 4 Decorate [[WI]] BuiltIn 26
-; CHECK: 4 Decorate [[LLI]] BuiltIn 27
-; CHECK: 4 Decorate [[GII]] BuiltIn 28
-; CHECK: 4 Decorate [[LLII]] BuiltIn 29
-; CHECK: 4 Decorate [[WD]] BuiltIn 30
-; CHECK: 4 Decorate [[GS]] BuiltIn 31
-; CHECK: 4 Decorate [[EWS]] BuiltIn 32
-; CHECK: 4 Decorate [[GO]] BuiltIn 33
-; CHECK: 4 Decorate [[GLI]] BuiltIn 34
-; CHECK: 4 Decorate [[SS]] BuiltIn 36
-; CHECK: 4 Decorate [[SMS]] BuiltIn 37
-; CHECK: 4 Decorate [[NS]] BuiltIn 38
-; CHECK: 4 Decorate [[NES]] BuiltIn 39
-; CHECK: 4 Decorate [[SI]] BuiltIn 40
-; CHECK: 4 Decorate [[SLII]] BuiltIn 41
+; CHECK-DAG: 4 Decorate [[NW]] BuiltIn 24
+; CHECK-DAG: 4 Decorate [[WS]] BuiltIn 25
+; CHECK-DAG: 4 Decorate [[WI]] BuiltIn 26
+; CHECK-DAG: 4 Decorate [[LLI]] BuiltIn 27
+; CHECK-DAG: 4 Decorate [[GII]] BuiltIn 28
+; CHECK-DAG: 4 Decorate [[LLII]] BuiltIn 29
+; CHECK-DAG: 4 Decorate [[WD]] BuiltIn 30
+; CHECK-DAG: 4 Decorate [[GS]] BuiltIn 31
+; CHECK-DAG: 4 Decorate [[EWS]] BuiltIn 32
+; CHECK-DAG: 4 Decorate [[GO]] BuiltIn 33
+; CHECK-DAG: 4 Decorate [[GLI]] BuiltIn 34
+; CHECK-DAG: 4 Decorate [[SS]] BuiltIn 36
+; CHECK-DAG: 4 Decorate [[SMS]] BuiltIn 37
+; CHECK-DAG: 4 Decorate [[NS]] BuiltIn 38
+; CHECK-DAG: 4 Decorate [[NES]] BuiltIn 39
+; CHECK-DAG: 4 Decorate [[SI]] BuiltIn 40
+; CHECK-DAG: 4 Decorate [[SLII]] BuiltIn 41
 @__spirv_BuiltInWorkDim = external addrspace(1) global i32
 @__spirv_BuiltInGlobalSize = external addrspace(1) global <3 x i32>
 @__spirv_BuiltInGlobalInvocationId = external addrspace(1) global <3 x i32>
diff --git a/test/float-controls-decorations.ll b/test/float-controls-decorations.ll
index c678a8b958..68e2507e43 100644
--- a/test/float-controls-decorations.ll
+++ b/test/float-controls-decorations.ll
@@ -23,24 +23,24 @@ entry:
 ; CHECK-LLVM: "VCFloatControl"="48"
 ; CHECK-SPIRV: 3 Name [[#FOO_ID:]] "foo"
 ; CHECK-SPIRV: 3 Name [[#BAR_ID:]] "bar"
-; CHECK-SPIRV: 5 Decorate [[#FOO_ID]] FunctionRoundingModeINTEL 16 0
-; CHECK-SPIRV-NEXT: 5 Decorate [[#BAR_ID]] FunctionRoundingModeINTEL 16 1
-; CHECK-SPIRV-NEXT: 5 Decorate [[#FOO_ID]] FunctionRoundingModeINTEL 32 0
-; CHECK-SPIRV-NEXT: 5 Decorate [[#BAR_ID]] FunctionRoundingModeINTEL 32 1
-; CHECK-SPIRV-NEXT: 5 Decorate [[#FOO_ID]] FunctionRoundingModeINTEL 64 0
-; CHECK-SPIRV-NEXT: 5 Decorate [[#BAR_ID]] FunctionRoundingModeINTEL 64 1
-; CHECK-SPIRV: 5 Decorate [[#FOO_ID]] FunctionDenormModeINTEL 16 1
-; CHECK-SPIRV: 5 Decorate [[#BAR_ID]] FunctionDenormModeINTEL 16 1
-; CHECK-SPIRV: 5 Decorate [[#FOO_ID]] FunctionDenormModeINTEL 32 1
-; CHECK-SPIRV: 5 Decorate [[#BAR_ID]] FunctionDenormModeINTEL 32 1
-; CHECK-SPIRV: 5 Decorate [[#FOO_ID]] FunctionDenormModeINTEL 64 1
-; CHECK-SPIRV: 5 Decorate [[#BAR_ID]] FunctionDenormModeINTEL 64 1
-; CHECK-SPIRV: 5 Decorate [[#FOO_ID]] FunctionFloatingPointModeINTEL 16 0
-; CHECK-SPIRV: 5 Decorate [[#BAR_ID]] FunctionFloatingPointModeINTEL 16 0
-; CHECK-SPIRV: 5 Decorate [[#FOO_ID]] FunctionFloatingPointModeINTEL 32 0
-; CHECK-SPIRV: 5 Decorate [[#BAR_ID]] FunctionFloatingPointModeINTEL 32 0
-; CHECK-SPIRV: 5 Decorate [[#FOO_ID]] FunctionFloatingPointModeINTEL 64 0
-; CHECK-SPIRV: 5 Decorate [[#BAR_ID]] FunctionFloatingPointModeINTEL 64 0
+; CHECK-SPIRV-DAG: 5 Decorate [[#FOO_ID]] FunctionRoundingModeINTEL 16 0
+; CHECK-SPIRV-DAG: 5 Decorate [[#BAR_ID]] FunctionRoundingModeINTEL 16 1
+; CHECK-SPIRV-DAG: 5 Decorate [[#FOO_ID]] FunctionRoundingModeINTEL 32 0
+; CHECK-SPIRV-DAG: 5 Decorate [[#BAR_ID]] FunctionRoundingModeINTEL 32 1
+; CHECK-SPIRV-DAG: 5 Decorate [[#FOO_ID]] FunctionRoundingModeINTEL 64 0
+; CHECK-SPIRV-DAG: 5 Decorate [[#BAR_ID]] FunctionRoundingModeINTEL 64 1
+; CHECK-SPIRV-DAG: 5 Decorate [[#FOO_ID]] FunctionDenormModeINTEL 16 1
+; CHECK-SPIRV-DAG: 5 Decorate [[#BAR_ID]] FunctionDenormModeINTEL 16 1
+; CHECK-SPIRV-DAG: 5 Decorate [[#FOO_ID]] FunctionDenormModeINTEL 32 1
+; CHECK-SPIRV-DAG: 5 Decorate [[#BAR_ID]] FunctionDenormModeINTEL 32 1
+; CHECK-SPIRV-DAG: 5 Decorate [[#FOO_ID]] FunctionDenormModeINTEL 64 1
+; CHECK-SPIRV-DAG: 5 Decorate [[#BAR_ID]] FunctionDenormModeINTEL 64 1
+; CHECK-SPIRV-DAG: 5 Decorate [[#FOO_ID]] FunctionFloatingPointModeINTEL 16 0
+; CHECK-SPIRV-DAG: 5 Decorate [[#BAR_ID]] FunctionFloatingPointModeINTEL 16 0
+; CHECK-SPIRV-DAG: 5 Decorate [[#FOO_ID]] FunctionFloatingPointModeINTEL 32 0
+; CHECK-SPIRV-DAG: 5 Decorate [[#BAR_ID]] FunctionFloatingPointModeINTEL 32 0
+; CHECK-SPIRV-DAG: 5 Decorate [[#FOO_ID]] FunctionFloatingPointModeINTEL 64 0
+; CHECK-SPIRV-DAG: 5 Decorate [[#BAR_ID]] FunctionFloatingPointModeINTEL 64 0
 
 attributes #0 = { "VCFloatControl"="0" "VCFunction"  }
 attributes #1 = { "VCFloatControl"="48" "VCFunction" }
diff --git a/test/llvm-intrinsics/constrained-arithmetic.ll b/test/llvm-intrinsics/constrained-arithmetic.ll
index 8a5652c1c4..daa0082b30 100644
--- a/test/llvm-intrinsics/constrained-arithmetic.ll
+++ b/test/llvm-intrinsics/constrained-arithmetic.ll
@@ -11,10 +11,10 @@
 
 ; CHECK-NOT: Decorate {{[0-9]+}} FPRoundingMode
 
-; CHECK: Decorate [[ad]] FPRoundingMode 0
-; CHECK: Decorate [[di]] FPRoundingMode 1
-; CHECK: Decorate [[su]] FPRoundingMode 2
-; CHECK: Decorate [[mu]] FPRoundingMode 3
+; CHECK-DAG: Decorate [[ad]] FPRoundingMode 0
+; CHECK-DAG: Decorate [[di]] FPRoundingMode 1
+; CHECK-DAG: Decorate [[su]] FPRoundingMode 2
+; CHECK-DAG: Decorate [[mu]] FPRoundingMode 3
 
 ; CHECK-NOT: Decorate {{[0-9]+}} FPRoundingMode
 
diff --git a/test/llvm-intrinsics/constrained-convert.ll b/test/llvm-intrinsics/constrained-convert.ll
index d2ce551fc3..0bc030f38e 100644
--- a/test/llvm-intrinsics/constrained-convert.ll
+++ b/test/llvm-intrinsics/constrained-convert.ll
@@ -10,14 +10,14 @@
 ; CHECK: Name [[fe:[0-9]+]] "conv4"
 ; CHECK: Name [[ft:[0-9]+]] "conv5"
 
-; CHECK: Decorate [[sf]] FPRoundingMode 0
-; CHECK: Decorate [[uf]] FPRoundingMode 1
+; CHECK-DAG: Decorate [[sf]] FPRoundingMode 0
+; CHECK-DAG: Decorate [[uf]] FPRoundingMode 1
+; CHECK-DAG: Decorate [[ft]] FPRoundingMode 2
 
 ; CHECK-NOT: Decorate [[fs]] FPRoundingMode
 ; CHECK-NOT: Decorate [[fu]] FPRoundingMode
 ; CHECK-NOT: Decorate [[fe]] FPRoundingMode
 
-; CHECK: Decorate [[ft]] FPRoundingMode 2
 
 ;CHECK: ConvertSToF {{[0-9]+}} [[sf]]
 ;CHECK: ConvertUToF {{[0-9]+}} [[uf]]
diff --git a/test/transcoding/DecorationMaxByteOffset.ll b/test/transcoding/DecorationMaxByteOffset.ll
index bb5bbc0c43..b8cf6f4348 100644
--- a/test/transcoding/DecorationMaxByteOffset.ll
+++ b/test/transcoding/DecorationMaxByteOffset.ll
@@ -11,8 +11,8 @@
 
 ; CHECK-SPIRV: 3 Name [[PTR_ID:[0-9]+]] "ptr"
 ; CHECK-SPIRV: 4 Name [[PTR2_ID:[0-9]+]] "ptr2"
-; CHECK-SPIRV: 4 Decorate [[PTR_ID]] MaxByteOffset 12
-; CHECK-SPIRV: 4 Decorate [[PTR2_ID]] MaxByteOffset 123
+; CHECK-SPIRV-DAG: 4 Decorate [[PTR_ID]] MaxByteOffset 12
+; CHECK-SPIRV-DAG: 4 Decorate [[PTR2_ID]] MaxByteOffset 123
 ; CHECK-SPIRV: 4 TypeInt [[CHAR_T:[0-9]+]] 8 0
 ; CHECK-SPIRV: 4 TypePointer [[CHAR_PTR_T:[0-9]+]] 4 [[CHAR_T]]
 ; CHECK-SPIRV: 3 FunctionParameter [[CHAR_PTR_T]] [[PTR_ID]]
diff --git a/test/transcoding/IntelFPGAMemoryAccesses.ll b/test/transcoding/IntelFPGAMemoryAccesses.ll
index 09c48ba8a4..1eb8e5d6c4 100644
--- a/test/transcoding/IntelFPGAMemoryAccesses.ll
+++ b/test/transcoding/IntelFPGAMemoryAccesses.ll
@@ -52,12 +52,12 @@
 ; CHECK-SPIRV: Extension "SPV_INTEL_fpga_memory_accesses"
 ; Check that the semantically meaningless decoration was
 ; translated as a mere annotation
-; CHECK-SPIRV: Decorate {{[0-9]+}} UserSemantic "{params:0}{cache-size:127}"
-; CHECK-SPIRV: Decorate {{[0-9]+}} BurstCoalesceINTEL
-; CHECK-SPIRV: Decorate {{[0-9]+}} CacheSizeINTEL 0
-; CHECK-SPIRV: Decorate {{[0-9]+}} CacheSizeINTEL 127
-; CHECK-SPIRV: Decorate {{[0-9]+}} DontStaticallyCoalesceINTEL
-; CHECK-SPIRV: Decorate {{[0-9]+}} PrefetchINTEL 0
+; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} UserSemantic "{params:0}{cache-size:127}"
+; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} BurstCoalesceINTEL
+; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} CacheSizeINTEL 0
+; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} CacheSizeINTEL 127
+; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} DontStaticallyCoalesceINTEL
+; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} PrefetchINTEL 0
 
 target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-n8:16:32:64"
 target triple = "spir64-unknown-unknown"
diff --git a/test/transcoding/IntelFPGAMemoryAttributes.ll b/test/transcoding/IntelFPGAMemoryAttributes.ll
index 888c89bc1b..26fd2bcf33 100644
--- a/test/transcoding/IntelFPGAMemoryAttributes.ll
+++ b/test/transcoding/IntelFPGAMemoryAttributes.ll
@@ -220,34 +220,34 @@
 
 ; CHECK-SPIRV: Capability FPGAMemoryAttributesINTEL
 ; CHECK-SPIRV: Extension "SPV_INTEL_fpga_memory_attributes"
-; CHECK-SPIRV: Decorate {{[0-9]+}} RegisterINTEL
-; CHECK-SPIRV: Decorate {{[0-9]+}} MemoryINTEL "DEFAULT"
-; CHECK-SPIRV: Decorate {{[0-9]+}} MemoryINTEL "MLAB"
-; CHECK-SPIRV: Decorate {{[0-9]+}} MemoryINTEL "BLOCK_RAM"
-; CHECK-SPIRV: Decorate {{[0-9]+}} NumbanksINTEL 2
-; CHECK-SPIRV: Decorate {{[0-9]+}} NumbanksINTEL 4
-; CHECK-SPIRV: Decorate {{[0-9]+}} NumbanksINTEL 8
-; CHECK-SPIRV: Decorate {{[0-9]+}} NumbanksINTEL 16
-; CHECK-SPIRV: Decorate {{[0-9]+}} BankwidthINTEL 4
-; CHECK-SPIRV: Decorate {{[0-9]+}} BankwidthINTEL 8
-; CHECK-SPIRV: Decorate {{[0-9]+}} BankwidthINTEL 16
-; CHECK-SPIRV: Decorate {{[0-9]+}} MaxPrivateCopiesINTEL 2
-; CHECK-SPIRV: Decorate {{[0-9]+}} MaxPrivateCopiesINTEL 4
-; CHECK-SPIRV: Decorate {{[0-9]+}} MaxPrivateCopiesINTEL 8
-; CHECK-SPIRV: Decorate {{[0-9]+}} SinglepumpINTEL
-; CHECK-SPIRV: Decorate {{[0-9]+}} DoublepumpINTEL
-; CHECK-SPIRV: Decorate {{[0-9]+}} MaxReplicatesINTEL 2
-; CHECK-SPIRV: Decorate {{[0-9]+}} MaxReplicatesINTEL 4
-; CHECK-SPIRV: Decorate {{[0-9]+}} MaxReplicatesINTEL 8
-; CHECK-SPIRV: Decorate {{[0-9]+}} SimpleDualPortINTEL
-; CHECK-SPIRV: Decorate {{[0-9]+}} MergeINTEL "foo" "depth"
-; CHECK-SPIRV: Decorate {{[0-9]+}} MergeINTEL "bar" "width"
-; CHECK-SPIRV: Decorate {{[0-9]+}} BankBitsINTEL 2
-; CHECK-SPIRV: Decorate {{[0-9]+}} BankBitsINTEL 5
-; CHECK-SPIRV: Decorate {{[0-9]+}} BankBitsINTEL 4 5
-; CHECK-SPIRV: Decorate {{[0-9]+}} BankBitsINTEL 2 1 0
-; CHECK-SPIRV: Decorate {{[0-9]+}} ForcePow2DepthINTEL 0
-; CHECK-SPIRV: Decorate {{[0-9]+}} ForcePow2DepthINTEL 1
+; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} RegisterINTEL
+; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} MemoryINTEL "DEFAULT"
+; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} MemoryINTEL "MLAB"
+; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} MemoryINTEL "BLOCK_RAM"
+; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} NumbanksINTEL 2
+; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} NumbanksINTEL 4
+; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} NumbanksINTEL 8
+; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} NumbanksINTEL 16
+; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} BankwidthINTEL 4
+; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} BankwidthINTEL 8
+; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} BankwidthINTEL 16
+; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} MaxPrivateCopiesINTEL 2
+; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} MaxPrivateCopiesINTEL 4
+; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} MaxPrivateCopiesINTEL 8
+; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} SinglepumpINTEL
+; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} DoublepumpINTEL
+; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} MaxReplicatesINTEL 2
+; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} MaxReplicatesINTEL 4
+; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} MaxReplicatesINTEL 8
+; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} SimpleDualPortINTEL
+; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} MergeINTEL "foo" "depth"
+; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} MergeINTEL "bar" "width"
+; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} BankBitsINTEL 2 1 0
+; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} BankBitsINTEL 2
+; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} BankBitsINTEL 5
+; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} BankBitsINTEL 4 5
+; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} ForcePow2DepthINTEL 0
+; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} ForcePow2DepthINTEL 1
 
 ; CHECK-SPIRV-NOT: Decorate [[#]] UserSemantic "{memory:MLAB}{sizeinfo:4,500}"
 
diff --git a/test/transcoding/IntelFPGAMemoryAttributesForStaticVar.ll b/test/transcoding/IntelFPGAMemoryAttributesForStaticVar.ll
index 34823d60fd..9c465e0c86 100644
--- a/test/transcoding/IntelFPGAMemoryAttributesForStaticVar.ll
+++ b/test/transcoding/IntelFPGAMemoryAttributesForStaticVar.ll
@@ -48,11 +48,11 @@
 
 ; CHECK-SPIRV: Capability FPGAMemoryAttributesINTEL
 ; CHECK-SPIRV: Extension "SPV_INTEL_fpga_memory_attributes"
-; CHECK-SPIRV: Decorate {{[0-9]+}} UserSemantic "foobarbaz"
-; CHECK-SPIRV: Decorate {{[0-9]+}} MemoryINTEL "DEFAULT"
-; CHECK-SPIRV: Decorate {{[0-9]+}} MemoryINTEL "MLAB"
-; CHECK-SPIRV: Decorate {{[0-9]+}} NumbanksINTEL 2
-; CHECK-SPIRV: Decorate {{[0-9]+}} ForcePow2DepthINTEL 0
+; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} UserSemantic "foobarbaz"
+; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} MemoryINTEL "DEFAULT"
+; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} MemoryINTEL "MLAB"
+; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} NumbanksINTEL 2
+; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} ForcePow2DepthINTEL 0
 
 target datalayout = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
 target triple = "spir"
diff --git a/test/transcoding/IntelFPGAMemoryAttributesForStruct.ll b/test/transcoding/IntelFPGAMemoryAttributesForStruct.ll
index 3b7e9885d3..1bfded7ae1 100644
--- a/test/transcoding/IntelFPGAMemoryAttributesForStruct.ll
+++ b/test/transcoding/IntelFPGAMemoryAttributesForStruct.ll
@@ -196,26 +196,26 @@
 
 ; CHECK-SPIRV: Capability FPGAMemoryAttributesINTEL
 ; CHECK-SPIRV: Extension "SPV_INTEL_fpga_memory_attributes"
-; CHECK-SPIRV: MemberDecorate {{[0-9]+}} 0 RegisterINTEL
-; CHECK-SPIRV: MemberDecorate {{[0-9]+}} 0 MemoryINTEL "DEFAULT"
-; CHECK-SPIRV: MemberDecorate {{[0-9]+}} 0 MemoryINTEL "MLAB"
-; CHECK-SPIRV: MemberDecorate {{[0-9]+}} 0 NumbanksINTEL 2
-; CHECK-SPIRV: MemberDecorate {{[0-9]+}} 0 NumbanksINTEL 4
-; CHECK-SPIRV: MemberDecorate {{[0-9]+}} 0 NumbanksINTEL 8
-; CHECK-SPIRV: MemberDecorate {{[0-9]+}} 0 BankwidthINTEL 4
-; CHECK-SPIRV: MemberDecorate {{[0-9]+}} 0 BankwidthINTEL 8
-; CHECK-SPIRV: MemberDecorate {{[0-9]+}} 0 MaxPrivateCopiesINTEL 2
-; CHECK-SPIRV: MemberDecorate {{[0-9]+}} 0 MaxPrivateCopiesINTEL 4
-; CHECK-SPIRV: MemberDecorate {{[0-9]+}} 0 SinglepumpINTEL
-; CHECK-SPIRV: MemberDecorate {{[0-9]+}} 0 DoublepumpINTEL
-; CHECK-SPIRV: MemberDecorate {{[0-9]+}} 0 MaxReplicatesINTEL 2
-; CHECK-SPIRV: MemberDecorate {{[0-9]+}} 0 MaxReplicatesINTEL 4
-; CHECK-SPIRV: MemberDecorate {{[0-9]+}} 0 SimpleDualPortINTEL
-; CHECK-SPIRV: MemberDecorate {{[0-9]+}} 0 MergeINTEL "foobar" "width"
-; CHECK-SPIRV: MemberDecorate {{[0-9]+}} 0 BankBitsINTEL 2 3
-; CHECK-SPIRV: MemberDecorate {{[0-9]+}} 0 BankBitsINTEL 42 41 40
-; CHECK-SPIRV: MemberDecorate {{[0-9]+}} 0 ForcePow2DepthINTEL 0
-; CHECK-SPIRV: MemberDecorate {{[0-9]+}} 0 ForcePow2DepthINTEL 1
+; CHECK-SPIRV-DAG: MemberDecorate {{[0-9]+}} 0 RegisterINTEL
+; CHECK-SPIRV-DAG: MemberDecorate {{[0-9]+}} 0 MemoryINTEL "DEFAULT"
+; CHECK-SPIRV-DAG: MemberDecorate {{[0-9]+}} 0 MemoryINTEL "MLAB"
+; CHECK-SPIRV-DAG: MemberDecorate {{[0-9]+}} 0 NumbanksINTEL 2
+; CHECK-SPIRV-DAG: MemberDecorate {{[0-9]+}} 0 NumbanksINTEL 4
+; CHECK-SPIRV-DAG: MemberDecorate {{[0-9]+}} 0 NumbanksINTEL 8
+; CHECK-SPIRV-DAG: MemberDecorate {{[0-9]+}} 0 BankwidthINTEL 4
+; CHECK-SPIRV-DAG: MemberDecorate {{[0-9]+}} 0 BankwidthINTEL 8
+; CHECK-SPIRV-DAG: MemberDecorate {{[0-9]+}} 0 MaxPrivateCopiesINTEL 2
+; CHECK-SPIRV-DAG: MemberDecorate {{[0-9]+}} 0 MaxPrivateCopiesINTEL 4
+; CHECK-SPIRV-DAG: MemberDecorate {{[0-9]+}} 0 SinglepumpINTEL
+; CHECK-SPIRV-DAG: MemberDecorate {{[0-9]+}} 0 DoublepumpINTEL
+; CHECK-SPIRV-DAG: MemberDecorate {{[0-9]+}} 0 MaxReplicatesINTEL 2
+; CHECK-SPIRV-DAG: MemberDecorate {{[0-9]+}} 0 MaxReplicatesINTEL 4
+; CHECK-SPIRV-DAG: MemberDecorate {{[0-9]+}} 0 SimpleDualPortINTEL
+; CHECK-SPIRV-DAG: MemberDecorate {{[0-9]+}} 0 MergeINTEL "foobar" "width"
+; CHECK-SPIRV-DAG: MemberDecorate {{[0-9]+}} 0 BankBitsINTEL 2 3
+; CHECK-SPIRV-DAG: MemberDecorate {{[0-9]+}} 0 BankBitsINTEL 42 41 40
+; CHECK-SPIRV-DAG: MemberDecorate {{[0-9]+}} 0 ForcePow2DepthINTEL 0
+; CHECK-SPIRV-DAG: MemberDecorate {{[0-9]+}} 0 ForcePow2DepthINTEL 1
 
 target datalayout = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
 target triple = "spir"
diff --git a/test/transcoding/NoSignedUnsignedWrap.ll b/test/transcoding/NoSignedUnsignedWrap.ll
index cf508c359e..a67c729840 100644
--- a/test/transcoding/NoSignedUnsignedWrap.ll
+++ b/test/transcoding/NoSignedUnsignedWrap.ll
@@ -43,8 +43,8 @@
 ; CHECK-SPIRV-EXT: 119734787 65536
 ; CHECK-SPIRV-EXT: Extension "SPV_KHR_no_integer_wrap_decoration"
 ; CHECK-SPIRV-NOEXT: 119734787 66560
-; CHECK-SPIRV: Decorate {{[0-9]+}} NoSignedWrap
-; CHECK-SPIRV: Decorate {{[0-9]+}} NoUnsignedWrap
+; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} NoSignedWrap
+; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} NoUnsignedWrap
 ;
 ; CHECK-SPIRV-NEGATIVE-NOT: Extension "SPV_KHR_no_integer_wrap_decoration"
 ; CHECK-SPIRV-NEGATIVE-NOT: Decorate {{[0-9]+}} NoSignedWrap
diff --git a/test/transcoding/SPV_INTEL_function_pointers/global_ctor_dtor.ll b/test/transcoding/SPV_INTEL_function_pointers/global_ctor_dtor.ll
index 6d5b7e2dd0..50b3494324 100644
--- a/test/transcoding/SPV_INTEL_function_pointers/global_ctor_dtor.ll
+++ b/test/transcoding/SPV_INTEL_function_pointers/global_ctor_dtor.ll
@@ -16,8 +16,8 @@ target triple = "spir64-unknown-unknown"
 ; CHECK: Name [[Name2:[0-9]+]] "llvm.global_dtors"
 ; CHECK: Name [[NameInit:[0-9]+]] "__cxx_global_var_init"
 
-; CHECK: LinkageAttributes "llvm.global_ctors" Export
-; CHECK: LinkageAttributes "llvm.global_dtors" Export
+; CHECK-DAG: Decorate {{[0-9]+}} LinkageAttributes "llvm.global_ctors" Export
+; CHECK-DAG: Decorate {{[0-9]+}} LinkageAttributes "llvm.global_dtors" Export
 
 ; CHECK: TypeFunction {{[0-9]+}} [[TF:[0-9]+]]
 
diff --git a/test/transcoding/SPV_INTEL_kernel_attributes/intel_fpga_function_attributes.ll b/test/transcoding/SPV_INTEL_kernel_attributes/intel_fpga_function_attributes.ll
index a5feea0964..043351b846 100644
--- a/test/transcoding/SPV_INTEL_kernel_attributes/intel_fpga_function_attributes.ll
+++ b/test/transcoding/SPV_INTEL_kernel_attributes/intel_fpga_function_attributes.ll
@@ -48,11 +48,11 @@
 ; CHECK-SPIRV: ExecutionMode [[FUNCENTRY]] 5895
 ; CHECK-SPIRV: ExecutionMode [[FUNCENTRY]] 5896 8
 ; CHECK-SPIRV: ExecutionMode [[FUNCENTRY]] 5903 1000
-; CHECK-SPIRV: Decorate [[FUNCENTRY]] StallEnableINTEL
-; CHECK-SPIRV: Decorate [[FUNCENTRY]] FuseLoopsInFunctionINTEL 3 1
-; CHECK-SPIRV: Decorate [[FUNCENTRY]] InitiationIntervalINTEL 10
-; CHECK-SPIRV: Decorate [[FUNCENTRY]] MaxConcurrencyINTEL 12
-; CHECK-SPIRV: Decorate [[FUNCENTRY]] PipelineEnableINTEL 0
+; CHECK-SPIRV-DAG: Decorate [[FUNCENTRY]] StallEnableINTEL
+; CHECK-SPIRV-DAG: Decorate [[FUNCENTRY]] FuseLoopsInFunctionINTEL 3 1
+; CHECK-SPIRV-DAG: Decorate [[FUNCENTRY]] InitiationIntervalINTEL 10
+; CHECK-SPIRV-DAG: Decorate [[FUNCENTRY]] MaxConcurrencyINTEL 12
+; CHECK-SPIRV-DAG: Decorate [[FUNCENTRY]] PipelineEnableINTEL 0
 ; CHECK-SPIRV: Function {{.*}} [[FUNCENTRY]] {{.*}}
 
 ; CHECK-LLVM: define spir_kernel void {{.*}}kernel_name()
diff --git a/test/transcoding/SPV_INTEL_memory_access_aliasing/intel-alias-masked-load-store.ll b/test/transcoding/SPV_INTEL_memory_access_aliasing/intel-alias-masked-load-store.ll
index 910608b307..40df52c2d3 100644
--- a/test/transcoding/SPV_INTEL_memory_access_aliasing/intel-alias-masked-load-store.ll
+++ b/test/transcoding/SPV_INTEL_memory_access_aliasing/intel-alias-masked-load-store.ll
@@ -47,19 +47,19 @@
 ; CHECK-SPIRV: AliasDomainDeclINTEL [[DOMAIN3:[0-9]+]]
 ; CHECK-SPIRV: AliasScopeDeclINTEL [[SCOPE3:[0-9]+]] [[DOMAIN3]]
 ; CHECK-SPIRV: AliasScopeListDeclINTEL [[LIST3:[0-9]+]] [[SCOPE3]]
-; CHECK-SPIRV: DecorateId [[TARGET1:[0-9]+]] AliasScopeINTEL [[LIST1]]
-; CHECK-SPIRV: DecorateId [[TARGET2:[0-9]+]] AliasScopeINTEL [[LIST1]]
-; CHECK-SPIRV: DecorateId [[TARGET3:[0-9]+]] AliasScopeINTEL [[LIST3]]
-; CHECK-SPIRV: DecorateId [[TARGET4:[0-9]+]] AliasScopeINTEL [[LIST3]]
-; CHECK-SPIRV: DecorateId [[TARGET5:[0-9]+]] NoAliasINTEL [[LIST1]]
-; CHECK-SPIRV: DecorateId [[TARGET2]] NoAliasINTEL [[LIST2]]
-; CHECK-SPIRV: DecorateId [[TARGET6:[0-9]+]] NoAliasINTEL [[LIST3]]
-; CHECK-SPIRV: FunctionCall {{.*}} [[TARGET1]]
-; CHECK-SPIRV: FunctionCall {{.*}} [[TARGET2]]
-; CHECK-SPIRV: FunctionCall {{.*}} [[TARGET5]]
-; CHECK-SPIRV: FunctionCall {{.*}} [[TARGET3]]
-; CHECK-SPIRV: FunctionCall {{.*}} [[TARGET4]]
-; CHECK-SPIRV: FunctionCall {{.*}} [[TARGET6]]
+; CHECK-SPIRV-DAG: DecorateId [[TARGET2:[0-9]+]] NoAliasINTEL [[LIST2]]
+; CHECK-SPIRV-DAG: DecorateId [[TARGET2]] AliasScopeINTEL [[LIST1]]
+; CHECK-SPIRV-DAG: DecorateId [[TARGET1:[0-9]+]] AliasScopeINTEL [[LIST1]]
+; CHECK-SPIRV-DAG: DecorateId [[TARGET3:[0-9]+]] AliasScopeINTEL [[LIST3]]
+; CHECK-SPIRV-DAG: DecorateId [[TARGET4:[0-9]+]] AliasScopeINTEL [[LIST3]]
+; CHECK-SPIRV-DAG: DecorateId [[TARGET5:[0-9]+]] NoAliasINTEL [[LIST1]]
+; CHECK-SPIRV-DAG: DecorateId [[TARGET6:[0-9]+]] NoAliasINTEL [[LIST3]]
+; CHECK-SPIRV-DAG: FunctionCall {{.*}} [[TARGET1]]
+; CHECK-SPIRV-DAG: FunctionCall {{.*}} [[TARGET2]]
+; CHECK-SPIRV-DAG: FunctionCall {{.*}} [[TARGET5]]
+; CHECK-SPIRV-DAG: FunctionCall {{.*}} [[TARGET3]]
+; CHECK-SPIRV-DAG: FunctionCall {{.*}} [[TARGET4]]
+; CHECK-SPIRV-DAG: FunctionCall {{.*}} [[TARGET6]]
 
 ; CHECK-SPIRV-NEGATIVE-NOT: Capability MemoryAccessAliasingINTEL
 ; CHECK-SPIRV-NEGATIVE-NOT: Extension "SPV_INTEL_memory_access_aliasing"
diff --git a/test/transcoding/SpecConstantComposite.ll b/test/transcoding/SpecConstantComposite.ll
index d9efda4044..a1978cbb2a 100644
--- a/test/transcoding/SpecConstantComposite.ll
+++ b/test/transcoding/SpecConstantComposite.ll
@@ -6,12 +6,12 @@
 ; RUN: llvm-spirv %t.spv -r -o - | llvm-dis -o %t.ll
 ; RUN: FileCheck < %t.ll %s --check-prefix=CHECK-LLVM
 
-; CHECK-SPIRV: Decorate [[#SC3:]] SpecId 3
-; CHECK-SPIRV: Decorate [[#SC4:]] SpecId 4
-; CHECK-SPIRV: Decorate [[#SC6:]] SpecId 6
-; CHECK-SPIRV: Decorate [[#SC7:]] SpecId 7
-; CHECK-SPIRV: Decorate [[#SC10:]] SpecId 10
-; CHECK-SPIRV: Decorate [[#SC11:]] SpecId 11
+; CHECK-SPIRV-DAG: Decorate [[#SC3:]] SpecId 3
+; CHECK-SPIRV-DAG: Decorate [[#SC4:]] SpecId 4
+; CHECK-SPIRV-DAG: Decorate [[#SC6:]] SpecId 6
+; CHECK-SPIRV-DAG: Decorate [[#SC7:]] SpecId 7
+; CHECK-SPIRV-DAG: Decorate [[#SC10:]] SpecId 10
+; CHECK-SPIRV-DAG: Decorate [[#SC11:]] SpecId 11
 
 ; CHECK-SPIRV-DAG: TypeInt [[#Int:]] 32
 ; CHECK-SPIRV-DAG: TypeFloat [[#Float:]] 32
diff --git a/test/transcoding/annotate_attribute.ll b/test/transcoding/annotate_attribute.ll
index 3d45f7087c..2bdc6c6d04 100644
--- a/test/transcoding/annotate_attribute.ll
+++ b/test/transcoding/annotate_attribute.ll
@@ -13,14 +13,14 @@
 ; Check SPIR-V versions in a format magic number + version
 ; CHECK-SPIRV: 119734787 66560
 
-; CHECK-SPIRV: Decorate {{[0-9]+}} UserSemantic "42"
-; CHECK-SPIRV: Decorate {{[0-9]+}} UserSemantic "bar"
-; CHECK-SPIRV: Decorate {{[0-9]+}} UserSemantic "{FOO}"
-; CHECK-SPIRV: Decorate {{[0-9]+}} UserSemantic "my_custom_annotations: 30, 60"
-; CHECK-SPIRV: MemberDecorate {{[0-9]+}} 1 UserSemantic "128"
-; CHECK-SPIRV: MemberDecorate {{[0-9]+}} 2 UserSemantic "qux"
-; CHECK-SPIRV: MemberDecorate {{[0-9]+}} 0 UserSemantic "{baz}"
-; CHECK-SPIRV: MemberDecorate {{[0-9]+}} 3 UserSemantic "my_custom_annotations: 20, 60, 80"
+; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} UserSemantic "42"
+; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} UserSemantic "bar"
+; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} UserSemantic "{FOO}"
+; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} UserSemantic "my_custom_annotations: 30, 60"
+; CHECK-SPIRV-DAG: MemberDecorate {{[0-9]+}} 1 UserSemantic "128"
+; CHECK-SPIRV-DAG: MemberDecorate {{[0-9]+}} 2 UserSemantic "qux"
+; CHECK-SPIRV-DAG: MemberDecorate {{[0-9]+}} 0 UserSemantic "{baz}"
+; CHECK-SPIRV-DAG: MemberDecorate {{[0-9]+}} 3 UserSemantic "my_custom_annotations: 20, 60, 80"
 
 target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
 target triple = "spir64-unknown-linux"
diff --git a/test/transcoding/builtin_calls.ll b/test/transcoding/builtin_calls.ll
index 9c34841378..bf2dd88065 100644
--- a/test/transcoding/builtin_calls.ll
+++ b/test/transcoding/builtin_calls.ll
@@ -11,8 +11,8 @@ target datalayout = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:2
 target triple = "spir-unknown-unknown"
 
 ; Check that builtin-call based SPV-IR is recognized by the translator.
-; CHECK-SPIRV: Decorate [[Id:[0-9]+]] BuiltIn 28
-; CHECK-SPIRV: Decorate [[Id:[0-9]+]] BuiltIn 34
+; CHECK-SPIRV-DAG: Decorate [[Id:[0-9]+]] BuiltIn 28
+; CHECK-SPIRV-DAG: Decorate [[Id:[0-9]+]] BuiltIn 34
 ; CHECK-SPIRV: Variable {{[0-9]+}} [[Id:[0-9]+]]
 ; CHECK-SPIRV: Variable {{[0-9]+}} [[Id:[0-9]+]]
 
diff --git a/test/transcoding/builtin_vars_arithmetics.ll b/test/transcoding/builtin_vars_arithmetics.ll
index c74659c388..4ecbbb4977 100644
--- a/test/transcoding/builtin_vars_arithmetics.ll
+++ b/test/transcoding/builtin_vars_arithmetics.ll
@@ -35,15 +35,15 @@
 ; clang++ -fsycl -fsycl-device-only emit-llvm tmp.cpp -o tmp.bc
 ; llvm-spirv tmp.bc -spirv-text -o builtin_vars_arithmetics.ll
 
-; CHECK-SPIRV: Decorate [[GlobalInvocationId:[0-9]+]] BuiltIn 28
-; CHECK-SPIRV: Decorate [[GlobalSize:[0-9]+]] BuiltIn 31
-; CHECK-SPIRV: Decorate [[GlobalOffset:[0-9]+]] BuiltIn 33
-; CHECK-SPIRV: Decorate [[GlobalInvocationId]] Constant
-; CHECK-SPIRV: Decorate [[GlobalSize]] Constant
-; CHECK-SPIRV: Decorate [[GlobalOffset]] Constant
-; CHECK-SPIRV: Decorate [[GlobalOffset]] LinkageAttributes "__spirv_BuiltInGlobalOffset" Import 
-; CHECK-SPIRV: Decorate [[GlobalSize]] LinkageAttributes "__spirv_BuiltInGlobalSize" Import 
-; CHECK-SPIRV: Decorate [[GlobalInvocationId]] LinkageAttributes "__spirv_BuiltInGlobalInvocationId" Import 
+; CHECK-SPIRV-DAG: Decorate [[GlobalInvocationId:[0-9]+]] BuiltIn 28
+; CHECK-SPIRV-DAG: Decorate [[GlobalSize:[0-9]+]] BuiltIn 31
+; CHECK-SPIRV-DAG: Decorate [[GlobalOffset:[0-9]+]] BuiltIn 33
+; CHECK-SPIRV-DAG: Decorate [[GlobalInvocationId]] Constant
+; CHECK-SPIRV-DAG: Decorate [[GlobalSize]] Constant
+; CHECK-SPIRV-DAG: Decorate [[GlobalOffset]] Constant
+; CHECK-SPIRV-DAG: Decorate [[GlobalOffset]] LinkageAttributes "__spirv_BuiltInGlobalOffset" Import 
+; CHECK-SPIRV-DAG: Decorate [[GlobalSize]] LinkageAttributes "__spirv_BuiltInGlobalSize" Import 
+; CHECK-SPIRV-DAG: Decorate [[GlobalInvocationId]] LinkageAttributes "__spirv_BuiltInGlobalInvocationId" Import 
 ;
 ; CHECK-LLVM-NOT: addrspacecast <3 x 64> addrspace(1)* @__spirv_BuiltInGlobalInvocationId to <3 x 64> addrspace(4)*
 ; CHECK-LLVM-NOT: load <3 x i64>
diff --git a/test/transcoding/builtin_vars_opt.ll b/test/transcoding/builtin_vars_opt.ll
index 75c1007578..14c297f100 100644
--- a/test/transcoding/builtin_vars_opt.ll
+++ b/test/transcoding/builtin_vars_opt.ll
@@ -39,9 +39,9 @@
 ; clang -fsycl -fsycl-device-only -Xclang -fsycl-enable-optimizations tmp.cpp -o tmp.bc
 ; llvm-spirv tmp.bc -s -o builtin_vars_opt.ll
 
-; CHECK-SPIRV: Decorate [[#SG_MaxSize_BI:]] BuiltIn 37
-; CHECK-SPIRV: Decorate [[#SG_MaxSize_BI:]] Constant
-; CHECK-SPIRV: Decorate [[#SG_MaxSize_BI:]] LinkageAttributes "__spirv_BuiltInSubgroupMaxSize" Import
+; CHECK-SPIRV-DAG: Decorate [[#SG_MaxSize_BI:]] BuiltIn 37
+; CHECK-SPIRV-DAG: Decorate [[#SG_MaxSize_BI:]] Constant
+; CHECK-SPIRV-DAG: Decorate [[#SG_MaxSize_BI:]] LinkageAttributes "__spirv_BuiltInSubgroupMaxSize" Import
 ;
 ; CHECK-LLVM-OCL-NOT: @__spirv_BuiltInSubgroupMaxSize
 ; CHECK-LLVM-NOT: addrspacecast i32 addrspace(1)* @__spirv_BuiltInSubgroupMaxSize to i32 addrspace(4)*
diff --git a/test/transcoding/fp_contract_reassoc_fast_mode.ll b/test/transcoding/fp_contract_reassoc_fast_mode.ll
index 351654c639..997bcd87a4 100644
--- a/test/transcoding/fp_contract_reassoc_fast_mode.ll
+++ b/test/transcoding/fp_contract_reassoc_fast_mode.ll
@@ -7,8 +7,8 @@
 ; CHECK-SPIRV-ON: 2 Capability FPFastMathModeINTEL
 ; CHECK-SPIRV-ON: 3 Name [[mu:[0-9]+]] "mul"
 ; CHECK-SPIRV-ON: 3 Name [[su:[0-9]+]] "sub"
-; CHECK-SPIRV-ON: 4 Decorate [[mu]] FPFastMathMode 65536
-; CHECK-SPIRV-ON: 4 Decorate [[su]] FPFastMathMode 131072
+; CHECK-SPIRV-ON-DAG: 4 Decorate [[mu]] FPFastMathMode 65536
+; CHECK-SPIRV-ON-DAG: 4 Decorate [[su]] FPFastMathMode 131072
 
 ; CHECK-SPIRV-OFF-NOT: 2 Capability FPFastMathModeINTEL
 ; CHECK-SPIRV-OFF: 3 Name [[mu:[0-9]+]] "mul"
diff --git a/test/transcoding/spirv-types.ll b/test/transcoding/spirv-types.ll
index e1b1f89837..616c23bc51 100644
--- a/test/transcoding/spirv-types.ll
+++ b/test/transcoding/spirv-types.ll
@@ -5,7 +5,6 @@
 ; RUN: FileCheck < %t.spv.txt %s --check-prefix=CHECK-SPIRV
 ; RUN: llvm-spirv %t.bc -o %t.from-llvm.spv
 ; RUN: llvm-spirv -to-binary %t.spv.txt -o %t.from-text.spv
-; RUN: cmp %t.from-llvm.spv %t.from-text.spv
 ; RUN: llvm-spirv %t.bc -o %t.spv
 ; RUN: spirv-val %t.spv
 ; RUN: llvm-spirv -r %t.spv -o %t.rev.bc