From 7c386741efedd9bde7a7e2e3da028d610dced87a Mon Sep 17 00:00:00 2001 From: "Wlodarczyk, Bertrand" Date: Thu, 5 Oct 2023 05:32:53 -0700 Subject: [PATCH] Support for new SPV_INTEL_fpga_memory_attributes This commit adds StridesizeINTEL, WordsizeINTEL and TrueDualPortINTEL support to translator. --- lib/SPIRV/SPIRVReader.cpp | 12 + lib/SPIRV/SPIRVWriter.cpp | 13 +- lib/SPIRV/libSPIRV/SPIRVDecorate.h | 6 + lib/SPIRV/libSPIRV/SPIRVEnum.h | 5 + lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h | 3 + spirv-headers-tag.conf | 2 +- .../IntelFPGAMemoryAttributes.ll | 753 -------------- .../IntelFPGAMemoryAttributesForStruct.ll | 917 +++++------------- .../IntelFPGAMemoryAttributesForVar.ll | 197 ++++ 9 files changed, 457 insertions(+), 1451 deletions(-) delete mode 100644 test/extensions/INTEL/SPV_INTEL_fpga_memory_attributes/IntelFPGAMemoryAttributes.ll create mode 100644 test/extensions/INTEL/SPV_INTEL_fpga_memory_attributes/IntelFPGAMemoryAttributesForVar.ll diff --git a/lib/SPIRV/SPIRVReader.cpp b/lib/SPIRV/SPIRVReader.cpp index 318f60422e..ba80be28be 100644 --- a/lib/SPIRV/SPIRVReader.cpp +++ b/lib/SPIRV/SPIRVReader.cpp @@ -3513,6 +3513,12 @@ void generateIntelFPGAAnnotation( } if (E->hasDecorate(DecorationForcePow2DepthINTEL, 0, &Result)) Out << "{force_pow2_depth:" << Result << '}'; + if (E->hasDecorate(DecorationStridesizeINTEL, 0, &Result)) + Out << "{stride_size:" << Result << "}"; + if (E->hasDecorate(DecorationWordsizeINTEL, 0, &Result)) + Out << "{word_size:" << Result << "}"; + if (E->hasDecorate(DecorationTrueDualPortINTEL)) + Out << "{true_dual_port:1}"; if (E->hasDecorate(DecorationBufferLocationINTEL, 0, &Result)) Out << "{sycl-buffer-location:" << Result << '}'; if (E->hasDecorate(DecorationLatencyControlLabelINTEL, 0, &Result)) @@ -3610,6 +3616,12 @@ void generateIntelFPGAAnnotationForStructMember( if (E->hasMemberDecorate(DecorationForcePow2DepthINTEL, 0, MemberNumber, &Result)) Out << "{force_pow2_depth:" << Result << '}'; + if (E->hasMemberDecorate(DecorationStridesizeINTEL, 0, MemberNumber, &Result)) + Out << "{stride_size:" << Result << "}"; + if (E->hasMemberDecorate(DecorationWordsizeINTEL, 0, MemberNumber, &Result)) + Out << "{word_size:" << Result << "}"; + if (E->hasMemberDecorate(DecorationTrueDualPortINTEL, 0, MemberNumber)) + Out << "{true_dual_port:1}"; if (!AnnotStr.empty()) AnnotStrVec.emplace_back(AnnotStr); diff --git a/lib/SPIRV/SPIRVWriter.cpp b/lib/SPIRV/SPIRVWriter.cpp index 01031e9cc7..3b0321e706 100644 --- a/lib/SPIRV/SPIRVWriter.cpp +++ b/lib/SPIRV/SPIRVWriter.cpp @@ -3179,6 +3179,9 @@ AnnotationDecorations tryParseAnnotationString(SPIRVModule *BM, .Case("bank_bits", DecorationBankBitsINTEL) .Case("merge", DecorationMergeINTEL) .Case("force_pow2_depth", DecorationForcePow2DepthINTEL) + .Case("stride_size", DecorationStridesizeINTEL) + .Case("word_size", DecorationWordsizeINTEL) + .Case("true_dual_port", DecorationTrueDualPortINTEL) .Default(DecorationUserSemantic); if (Dec == DecorationUserSemantic) // Restore the braces to translate the whole input string @@ -3277,7 +3280,8 @@ void addAnnotationDecorations(SPIRVEntry *E, DecorationsInfoVec &Decorations) { case DecorationRegisterINTEL: case DecorationSinglepumpINTEL: case DecorationDoublepumpINTEL: - case DecorationSimpleDualPortINTEL: { + case DecorationSimpleDualPortINTEL: + case DecorationTrueDualPortINTEL: { if (M->isAllowedToUseExtension( ExtensionID::SPV_INTEL_fpga_memory_attributes)) { M->getErrorLog().checkError(I.second.empty(), SPIRVEC_InvalidLlvmModule, @@ -3298,7 +3302,9 @@ void addAnnotationDecorations(SPIRVEntry *E, DecorationsInfoVec &Decorations) { case DecorationBankwidthINTEL: case DecorationMaxPrivateCopiesINTEL: case DecorationMaxReplicatesINTEL: - case DecorationForcePow2DepthINTEL: { + case DecorationForcePow2DepthINTEL: + case DecorationStridesizeINTEL: + case DecorationWordsizeINTEL: { if (M->isAllowedToUseExtension( ExtensionID::SPV_INTEL_fpga_memory_attributes)) { M->getErrorLog().checkError(I.second.size() == 1, @@ -3427,6 +3433,7 @@ void addAnnotationDecorationsForStructMember(SPIRVEntry *E, case DecorationSinglepumpINTEL: case DecorationDoublepumpINTEL: case DecorationSimpleDualPortINTEL: + case DecorationTrueDualPortINTEL: M->getErrorLog().checkError(I.second.empty(), SPIRVEC_InvalidLlvmModule, "Member decoration takes no arguments."); E->addMemberDecorate(MemberNumber, I.first); @@ -3437,6 +3444,8 @@ void addAnnotationDecorationsForStructMember(SPIRVEntry *E, // DecorationMaxPrivateCopiesINTEL // DecorationMaxReplicatesINTEL // DecorationForcePow2DepthINTEL + // DecorarionStridesizeINTEL + // DecorationWordsizeINTEL default: M->getErrorLog().checkError( I.second.size() == 1, SPIRVEC_InvalidLlvmModule, diff --git a/lib/SPIRV/libSPIRV/SPIRVDecorate.h b/lib/SPIRV/libSPIRV/SPIRVDecorate.h index 367d95449f..31c329b932 100644 --- a/lib/SPIRV/libSPIRV/SPIRVDecorate.h +++ b/lib/SPIRV/libSPIRV/SPIRVDecorate.h @@ -151,6 +151,9 @@ class SPIRVDecorate : public SPIRVDecorateGeneric { case DecorationMergeINTEL: case DecorationBankBitsINTEL: case DecorationForcePow2DepthINTEL: + case DecorationStridesizeINTEL: + case DecorationWordsizeINTEL: + case DecorationTrueDualPortINTEL: return ExtensionID::SPV_INTEL_fpga_memory_attributes; case DecorationBurstCoalesceINTEL: case DecorationCacheSizeINTEL: @@ -336,6 +339,9 @@ class SPIRVMemberDecorate : public SPIRVDecorateGeneric { case DecorationMergeINTEL: case DecorationBankBitsINTEL: case DecorationForcePow2DepthINTEL: + case DecorationStridesizeINTEL: + case DecorationWordsizeINTEL: + case DecorationTrueDualPortINTEL: return ExtensionID::SPV_INTEL_fpga_memory_attributes; case DecorationBurstCoalesceINTEL: case DecorationCacheSizeINTEL: diff --git a/lib/SPIRV/libSPIRV/SPIRVEnum.h b/lib/SPIRV/libSPIRV/SPIRVEnum.h index 3f61c69104..69e6eed325 100644 --- a/lib/SPIRV/libSPIRV/SPIRVEnum.h +++ b/lib/SPIRV/libSPIRV/SPIRVEnum.h @@ -416,6 +416,11 @@ template <> inline void SPIRVMap::init() { ADD_VEC_INIT(DecorationBankBitsINTEL, {CapabilityFPGAMemoryAttributesINTEL}); ADD_VEC_INIT(DecorationForcePow2DepthINTEL, {CapabilityFPGAMemoryAttributesINTEL}); + ADD_VEC_INIT(DecorationStridesizeINTEL, + {CapabilityFPGAMemoryAttributesINTEL}); + ADD_VEC_INIT(DecorationWordsizeINTEL, {CapabilityFPGAMemoryAttributesINTEL}); + ADD_VEC_INIT(DecorationTrueDualPortINTEL, + {CapabilityFPGAMemoryAttributesINTEL}); ADD_VEC_INIT(DecorationReferencedIndirectlyINTEL, {CapabilityIndirectReferencesINTEL}); ADD_VEC_INIT(DecorationIOPipeStorageINTEL, {CapabilityIOPipesINTEL}); diff --git a/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h b/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h index 52b5a56f64..40c78b32c8 100644 --- a/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h +++ b/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h @@ -161,6 +161,9 @@ template <> inline void SPIRVMap::init() { add(DecorationMergeINTEL, "MergeINTEL"); add(DecorationBankBitsINTEL, "BankBitsINTEL"); add(DecorationForcePow2DepthINTEL, "ForcePow2DepthINTEL"); + add(DecorationStridesizeINTEL, "StridesizeINTEL"); + add(DecorationWordsizeINTEL, "WordsizeINTEL"); + add(DecorationTrueDualPortINTEL, "TrueDualPortINTEL"); add(DecorationBurstCoalesceINTEL, "BurstCoalesceINTEL"); add(DecorationCacheSizeINTEL, "CacheSizeINTEL"); add(DecorationDontStaticallyCoalesceINTEL, "DontStaticallyCoalesceINTEL"); diff --git a/spirv-headers-tag.conf b/spirv-headers-tag.conf index 44e9079c13..c16a9208b9 100644 --- a/spirv-headers-tag.conf +++ b/spirv-headers-tag.conf @@ -1 +1 @@ -b8b9eb8640c8c0107ba580fbcb10f969022ca32c +88bc5e321c2839707df8b1ab534e243e00744177 diff --git a/test/extensions/INTEL/SPV_INTEL_fpga_memory_attributes/IntelFPGAMemoryAttributes.ll b/test/extensions/INTEL/SPV_INTEL_fpga_memory_attributes/IntelFPGAMemoryAttributes.ll deleted file mode 100644 index b62a27ed7e..0000000000 --- a/test/extensions/INTEL/SPV_INTEL_fpga_memory_attributes/IntelFPGAMemoryAttributes.ll +++ /dev/null @@ -1,753 +0,0 @@ -; LLVM IR generated by Intel SYCL Clang compiler (https://github.com/intel/llvm) - -; SYCL source code for this test: -; void numbanks_attr() { -; [[intelfpga::numbanks(16)]] int numbanks_var; -; -; [[intelfpga::numbanks(2)]] struct numbanks_st { -; int field; -; } s; -; s.field = 0; -; } -; -; template -; void templ_numbanks_attr() { -; [[intelfpga::numbanks(A)]] int templ_numbanks_var; -; -; [[intelfpga::numbanks(A)]] struct templ_numbanks_st { -; int field; -; } s; -; s.field = 0; -; } -; -; void register_attr() { -; [[intelfpga::register]] int register_var; -; -; [[intelfpga::register]] struct register_st { -; int field; -; } s; -; s.field = 0; -; } -; -; void memory_attr() { -; [[intelfpga::memory("MLAB")]] int memory_var[500]; -; -; [[intelfpga::memory("BLOCK_RAM")]] struct memory_st { -; int field[10][2]; -; } s; -; s.field[0][0] = {0}; -; } -; -; void bankwidth_attr() { -; [[intelfpga::bankwidth(8)]] int bankwidth_var; -; -; [[intelfpga::bankwidth(4)]] struct bankwidth_st { -; int field; -; } s; -; s.field = 0; -; } -; -; template -; void templ_bankwidth_attr() { -; [[intelfpga::bankwidth(A)]] int templ_bankwidth_var; -; -; [[intelfpga::bankwidth(A)]] struct templ_bankwidth_st { -; int field; -; } s; -; s.field = 0; -; } -; -; void private_copies_attr() { -; [[intelfpga::private_copies(4)]] int priv_copies_var; -; -; [[intelfpga::private_copies(2)]] struct priv_copies_st { -; int field; -; } s; -; s.field = 0; -; } -; -; template -; void templ_private_copies_attr() { -; [[intelfpga::private_copies(A)]] int templ_priv_copies_var; -; -; [[intelfpga::private_copies(A)]] struct templ_priv_copies_st { -; int field; -; } s; -; s.field = 0; -; } -; -; void singlepump_attr() { -; [[intelfpga::singlepump]] int singlepump_var; -; -; [[intelfpga::singlepump]] struct singlepump_st { -; int field; -; } s; -; s.field = 0; -; } -; -; void doublepump_attr() { -; [[intelfpga::doublepump]] int doublepump_var; -; -; [[intelfpga::doublepump]] struct doublepump_st { -; int field; -; } s; -; s.field = 0; -; } -; -; void merge_attr() { -; [[intelfpga::merge("foo", "depth")]] int merge_var; -; -; [[intelfpga::merge("bar", "width")]] struct merge_st { -; int field; -; } s; -; s.field = 0; -; } -; -; void max_replicates_attr() { -; [[intelfpga::max_replicates(4)]] int max_repl_var; -; -; [[intelfpga::max_replicates(2)]] struct max_repl_st { -; int field; -; } s; -; s.field = 0; -; } -; -; template -; void templ_max_replicates_attr() { -; [[intelfpga::max_replicates(A)]] int templ_max_repl_var; -; -; [[intelfpga::max_replicates(A)]] struct templ_max_repl_st { -; int field; -; } s; -; s.field = 0; -; } -; -; void simple_dual_port_attr() { -; [[intelfpga::simple_dual_port]] int simple_dual_port_var; -; -; [[intelfpga::simple_dual_port]] struct simple_dual_port_st { -; int field; -; } s; -; s.field = 0; -; } -; -; void bank_bits_attr() { -; [[intelfpga::numbanks(8), intelfpga::bank_bits(2, 1, 0)]] int bank_bits_var; -; -; [[intelfpga::bank_bits(2)]] struct bank_bits_st { -; int field; -; } s; -; s.field = 0; -; } -; -; template -; void templ_bank_bits_attr() { -; [[intelfpga::bank_bits(A, B)]] int templ_bank_bits_var; -; -; [[intelfpga::bank_bits(B)]] struct templ_bank_bits_st { -; int field; -; } s; -; s.field = 0; -; } -; -; void force_pow2_depth_attr() { -; [[intelfpga::force_pow2_depth(0)]] int fp2d_var; -; -; [[intelfpga::force_pow2_depth(1)]] struct fp2d_st { -; int field; -; } s; -; s.field = 0; -; } -; -; template -; void templ_force_pow2_depth_attr() { -; [[intelfpga::force_pow2_depth(A)]] int templ_fp2d_var; -; -; [[intelfpga::force_pow2_depth(A)]] struct templ_fp2d_st { -; int field; -; } s; -; s.field = 0; -; } -; void memory_attribute_on_array() { -; [[intelfpga::register]] int register_var[32]; -; } -; -; template -; __attribute__((sycl_kernel)) void kernel_single_task(Func kernelFunc) { -; kernelFunc(); -; } -; -; int main() { -; kernel_single_task([]() { -; numbanks_attr(); -; templ_numbanks_attr<4>(); -; register_attr(); -; memory_attr(); -; bankwidth_attr(); -; templ_bankwidth_attr<16>(); -; private_copies_attr(); -; templ_private_copies_attr<8>(); -; singlepump_attr(); -; doublepump_attr(); -; merge_attr(); -; max_replicates_attr(); -; templ_max_replicates_attr<8>(); -; simple_dual_port_attr(); -; bank_bits_attr(); -; templ_bank_bits_attr<4, 5>(); -; force_pow2_depth_attr(); -; templ_force_pow2_depth_attr<1>(); -; memory_attribute_on_array(); -; }); -; return 0; -; } - -; LLVM IR compilation command: -; clang -cc1 -triple spir -disable-llvm-passes -fsycl-is-device -emit-llvm intel-fpga-local-var.cpp - -; RUN: llvm-as %s -o %t.bc -; RUN: llvm-spirv %t.bc --spirv-ext=+SPV_INTEL_fpga_memory_attributes -o %t.spv -; RUN: llvm-spirv %t.spv --spirv-ext=+SPV_INTEL_fpga_memory_attributes -to-text -o %t.spt -; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV - -; RUN: llvm-spirv -r %t.spv -o %t.rev.bc -; RUN: llvm-dis < %t.rev.bc | FileCheck %s --check-prefix=CHECK-LLVM - -; RUN: llvm-spirv -spirv-text -r %t.spt -o %t.rev.bc -; RUN: llvm-dis < %t.rev.bc | FileCheck %s --check-prefix=CHECK-LLVM - -; TODO: add a bunch of different tests for --spirv-ext option - -; CHECK-SPIRV: Capability FPGAMemoryAttributesINTEL -; CHECK-SPIRV: Extension "SPV_INTEL_fpga_memory_attributes" -; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} RegisterINTEL -; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} MemoryINTEL "DEFAULT" -; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} MemoryINTEL "MLAB" -; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} MemoryINTEL "BLOCK_RAM" -; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} NumbanksINTEL 2 -; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} NumbanksINTEL 4 -; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} NumbanksINTEL 8 -; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} NumbanksINTEL 16 -; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} BankwidthINTEL 4 -; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} BankwidthINTEL 8 -; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} BankwidthINTEL 16 -; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} MaxPrivateCopiesINTEL 2 -; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} MaxPrivateCopiesINTEL 4 -; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} MaxPrivateCopiesINTEL 8 -; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} SinglepumpINTEL -; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} DoublepumpINTEL -; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} MaxReplicatesINTEL 2 -; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} MaxReplicatesINTEL 4 -; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} MaxReplicatesINTEL 8 -; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} SimpleDualPortINTEL -; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} MergeINTEL "foo" "depth" -; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} MergeINTEL "bar" "width" -; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} BankBitsINTEL 2 1 0 -; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} BankBitsINTEL 2 -; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} BankBitsINTEL 5 -; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} BankBitsINTEL 4 5 -; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} ForcePow2DepthINTEL 0 -; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} ForcePow2DepthINTEL 1 - -; CHECK-SPIRV-DAG: Decorate {{[0-9]+}} UserSemantic "{sizeinfo:4,500}" -; CHECK-SPIRV-NOT: Decorate [[#]] UserSemantic "{memory:MLAB}{sizeinfo:4,500}" - -target datalayout = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024" -target triple = "spir" - -%class.anon = type { i8 } -%struct.numbanks_st = type { i32 } -%struct.templ_numbanks_st = type { i32 } -%struct.register_st = type { i32 } -%struct.memory_st = type { [10 x [2 x i32]] } -%struct.bankwidth_st = type { i32 } -%struct.templ_bankwidth_st = type { i32 } -%struct.priv_copies_st = type { i32 } -%struct.templ_priv_copies_st = type { i32 } -%struct.singlepump_st = type { i32 } -%struct.doublepump_st = type { i32 } -%struct.merge_st = type { i32 } -%struct.max_repl_st = type { i32 } -%struct.templ_max_repl_st = type { i32 } -%struct.simple_dual_port_st = type { i32 } -%struct.bank_bits_st = type { i32 } -%struct.templ_bank_bits_st = type { i32 } -%struct.fp2d_st = type { i32 } -%struct.templ_fp2d_st = type { i32 } - -; CHECK-LLVM: [[STR_NMB_VAR:@[0-9_.]+]] = {{.*}}{memory:DEFAULT}{numbanks:16} -; CHECK-LLVM: [[STR_NMB_SCT:@[0-9_.]+]] = {{.*}}{memory:DEFAULT}{numbanks:2} -; CHECK-LLVM: [[STR_NMB_TE:@[0-9_.]+]] = {{.*}}{memory:DEFAULT}{numbanks:4} -; CHECK-LLVM: [[STR_REG_VAR:@[0-9_.]+]] = {{.*}}{register:1} -; CHECK-LLVM: [[STR_MEM_VAR:@[0-9_.]+]] = {{.*}}{memory:MLAB} -; CHECK-LLVM: [[STR_MEM_VAR:@[0-9_.]+]] = {{.*}}{sizeinfo:4,500} -; CHECK-LLVM: [[STR_MEM_SCT:@[0-9_.]+]] = {{.*}}{memory:BLOCK_RAM} -; CHECK-LLVM: [[STR_BWD_VAR:@[0-9_.]+]] = {{.*}}{memory:DEFAULT}{bankwidth:8} -; CHECK-LLVM: [[STR_BWD_SCT:@[0-9_.]+]] = {{.*}}{memory:DEFAULT}{bankwidth:4} -; CHECK-LLVM: [[STR_BWD_TE:@[0-9_.]+]] = {{.*}}{memory:DEFAULT}{bankwidth:16} -; CHECK-LLVM: [[STR_PRC_VAR:@[0-9_.]+]] = {{.*}}{memory:DEFAULT}{private_copies:4} -; CHECK-LLVM: [[STR_PRC_SCT:@[0-9_.]+]] = {{.*}}{memory:DEFAULT}{private_copies:2} -; CHECK-LLVM: [[STR_PRC_TE:@[0-9_.]+]] = {{.*}}{memory:DEFAULT}{private_copies:8} -; CHECK-LLVM: [[STR_SNP_VAR:@[0-9_.]+]] = {{.*}}{memory:DEFAULT}{pump:1} -; CHECK-LLVM: [[STR_DBP_VAR:@[0-9_.]+]] = {{.*}}{memory:DEFAULT}{pump:2} -; CHECK-LLVM: [[STR_MRG_VAR:@[0-9_.]+]] = {{.*}}{memory:DEFAULT}{merge:foo:depth} -; CHECK-LLVM: [[STR_MRG_SCT:@[0-9_.]+]] = {{.*}}{memory:DEFAULT}{merge:bar:width} -; CHECK-LLVM: [[STR_MXR_VAR:@[0-9_.]+]] = {{.*}}{max_replicates:4} -; CHECK-LLVM: [[STR_MXR_SCT:@[0-9_.]+]] = {{.*}}{max_replicates:2} -; CHECK-LLVM: [[STR_MXR_TE:@[0-9_.]+]] = {{.*}}{max_replicates:8} -; CHECK-LLVM: [[STR_SDP_VAR:@[0-9_.]+]] = {{.*}}{memory:DEFAULT}{simple_dual_port:1} -; CHECK-LLVM: [[STR_BBT_VAR:@[0-9_.]+]] = {{.*}}{memory:DEFAULT}{numbanks:8}{bank_bits:2,1,0} -; CHECK-LLVM: [[STR_BBT_SCT:@[0-9_.]+]] = {{.*}}{memory:DEFAULT}{numbanks:2}{bank_bits:2} -; CHECK-LLVM: [[STR_BBT_TE1:@[0-9_.]+]] = {{.*}}{memory:DEFAULT}{numbanks:4}{bank_bits:4,5} -; CHECK-LLVM: [[STR_BBT_TE2:@[0-9_.]+]] = {{.*}}{memory:DEFAULT}{numbanks:2}{bank_bits:5} -; CHECK-LLVM: [[STR_FP2_VAR:@[0-9_.]+]] = {{.*}}{memory:DEFAULT}{force_pow2_depth:0} -; CHECK-LLVM: [[STR_FP2_SCT:@[0-9_.]+]] = {{.*}}{memory:DEFAULT}{force_pow2_depth:1} -@.str = private unnamed_addr constant [42 x i8] c"{memory:DEFAULT}{sizeinfo:4}{numbanks:16}\00", section "llvm.metadata" -@.str.1 = private unnamed_addr constant [25 x i8] c"intel-fpga-local-var.cpp\00", section "llvm.metadata" -@.str.2 = private unnamed_addr constant [41 x i8] c"{memory:DEFAULT}{sizeinfo:4}{numbanks:2}\00", section "llvm.metadata" -@.str.3 = private unnamed_addr constant [41 x i8] c"{memory:DEFAULT}{sizeinfo:4}{numbanks:4}\00", section "llvm.metadata" -@.str.4 = private unnamed_addr constant [13 x i8] c"{register:1}\00", section "llvm.metadata" -@.str.5 = private unnamed_addr constant [30 x i8] c"{memory:MLAB}{sizeinfo:4,500}\00", section "llvm.metadata" -@.str.6 = private unnamed_addr constant [32 x i8] c"{memory:BLOCK_RAM}{sizeinfo:80}\00", section "llvm.metadata" -@.str.7 = private unnamed_addr constant [42 x i8] c"{memory:DEFAULT}{sizeinfo:4}{bankwidth:8}\00", section "llvm.metadata" -@.str.8 = private unnamed_addr constant [42 x i8] c"{memory:DEFAULT}{sizeinfo:4}{bankwidth:4}\00", section "llvm.metadata" -@.str.9 = private unnamed_addr constant [43 x i8] c"{memory:DEFAULT}{sizeinfo:4}{bankwidth:16}\00", section "llvm.metadata" -@.str.10 = private unnamed_addr constant [47 x i8] c"{memory:DEFAULT}{sizeinfo:4}{private_copies:4}\00", section "llvm.metadata" -@.str.11 = private unnamed_addr constant [47 x i8] c"{memory:DEFAULT}{sizeinfo:4}{private_copies:2}\00", section "llvm.metadata" -@.str.12 = private unnamed_addr constant [47 x i8] c"{memory:DEFAULT}{sizeinfo:4}{private_copies:8}\00", section "llvm.metadata" -@.str.13 = private unnamed_addr constant [37 x i8] c"{memory:DEFAULT}{sizeinfo:4}{pump:1}\00", section "llvm.metadata" -@.str.14 = private unnamed_addr constant [37 x i8] c"{memory:DEFAULT}{sizeinfo:4}{pump:2}\00", section "llvm.metadata" -@.str.15 = private unnamed_addr constant [46 x i8] c"{memory:DEFAULT}{sizeinfo:4}{merge:foo:depth}\00", section "llvm.metadata" -@.str.16 = private unnamed_addr constant [46 x i8] c"{memory:DEFAULT}{sizeinfo:4}{merge:bar:width}\00", section "llvm.metadata" -@.str.17 = private unnamed_addr constant [19 x i8] c"{max_replicates:4}\00", section "llvm.metadata" -@.str.18 = private unnamed_addr constant [19 x i8] c"{max_replicates:2}\00", section "llvm.metadata" -@.str.19 = private unnamed_addr constant [19 x i8] c"{max_replicates:8}\00", section "llvm.metadata" -@.str.20 = private unnamed_addr constant [49 x i8] c"{memory:DEFAULT}{sizeinfo:4}{simple_dual_port:1}\00", section "llvm.metadata" -@.str.21 = private unnamed_addr constant [58 x i8] c"{memory:DEFAULT}{sizeinfo:4}{numbanks:8}{bank_bits:2,1,0}\00", section "llvm.metadata" -@.str.22 = private unnamed_addr constant [54 x i8] c"{memory:DEFAULT}{sizeinfo:4}{numbanks:2}{bank_bits:2}\00", section "llvm.metadata" -@.str.23 = private unnamed_addr constant [56 x i8] c"{memory:DEFAULT}{sizeinfo:4}{numbanks:4}{bank_bits:4,5}\00", section "llvm.metadata" -@.str.24 = private unnamed_addr constant [54 x i8] c"{memory:DEFAULT}{sizeinfo:4}{numbanks:2}{bank_bits:5}\00", section "llvm.metadata" -@.str.25 = private unnamed_addr constant [49 x i8] c"{memory:DEFAULT}{sizeinfo:4}{force_pow2_depth:0}\00", section "llvm.metadata" -@.str.26 = private unnamed_addr constant [49 x i8] c"{memory:DEFAULT}{sizeinfo:4}{force_pow2_depth:1}\00", section "llvm.metadata" - -; Function Attrs: norecurse nounwind -define spir_kernel void @_ZTSZ4mainE15kernel_function() #0 !kernel_arg_addr_space !4 !kernel_arg_access_qual !4 !kernel_arg_type !4 !kernel_arg_base_type !4 !kernel_arg_type_qual !4 { -entry: - %0 = alloca %class.anon, align 1 - call void @llvm.lifetime.start.p0(i64 1, ptr %0) #5 - call spir_func void @"_ZZ4mainENK3$_0clEv"(ptr %0) - call void @llvm.lifetime.end.p0(i64 1, ptr %0) #5 - ret void -} - -; Function Attrs: argmemonly nounwind willreturn -declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1 - -; Function Attrs: inlinehint norecurse nounwind -define internal spir_func void @"_ZZ4mainENK3$_0clEv"(ptr %this) #2 align 2 { -entry: - %this.addr = alloca ptr, align 4 - store ptr %this, ptr %this.addr, align 4, !tbaa !5 - %this1 = load ptr, ptr %this.addr, align 4 - call spir_func void @_Z13numbanks_attrv() - call spir_func void @_Z19templ_numbanks_attrILi4EEvv() - call spir_func void @_Z13register_attrv() - call spir_func void @_Z11memory_attrv() - call spir_func void @_Z14bankwidth_attrv() - call spir_func void @_Z20templ_bankwidth_attrILi16EEvv() - call spir_func void @_Z19private_copies_attrv() - call spir_func void @_Z25templ_private_copies_attrILi8EEvv() - call spir_func void @_Z15singlepump_attrv() - call spir_func void @_Z15doublepump_attrv() - call spir_func void @_Z10merge_attrv() - call spir_func void @_Z19max_replicates_attrv() - call spir_func void @_Z25templ_max_replicates_attrILi8EEvv() - call spir_func void @_Z21simple_dual_port_attrv() - call spir_func void @_Z14bank_bits_attrv() - call spir_func void @_Z20templ_bank_bits_attrILi4ELi5EEvv() - call spir_func void @_Z21force_pow2_depth_attrv() - call spir_func void @_Z27templ_force_pow2_depth_attrILi1EEvv() - call spir_func void @_Z25memory_attribute_on_arrayv() - ret void -} - -; Function Attrs: argmemonly nounwind willreturn -declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1 - -; Function Attrs: nounwind willreturn -declare void @llvm.var.annotation(ptr, ptr, ptr, i32, ptr) #4 - -; Function Attrs: norecurse nounwind -define spir_func void @_Z13numbanks_attrv() #3 { -entry: - %numbanks_var = alloca i32, align 4 - %s = alloca %struct.numbanks_st, align 4 - call void @llvm.lifetime.start.p0(i64 4, ptr %numbanks_var) #5 - ; CHECK-LLVM: call void @llvm.var.annotation.p0.p0(ptr %{{[a-zA-Z0-9_]+}}, ptr [[STR_NMB_VAR]], ptr undef, i32 undef, ptr undef) - call void @llvm.var.annotation(ptr %numbanks_var, ptr @.str, ptr @.str.1, i32 2, ptr null) - call void @llvm.lifetime.start.p0(i64 4, ptr %s) #5 - ; CHECK-LLVM: call void @llvm.var.annotation.p0.p0(ptr %{{[a-zA-Z0-9_]+}}, ptr [[STR_NMB_SCT]], ptr undef, i32 undef, ptr undef) - call void @llvm.var.annotation(ptr %s, ptr @.str.2, ptr @.str.1, i32 6, ptr null) - store i32 0, ptr %s, align 4, !tbaa !9 - call void @llvm.lifetime.end.p0(i64 4, ptr %s) #5 - call void @llvm.lifetime.end.p0(i64 4, ptr %numbanks_var) #5 - ret void -} - -; Function Attrs: norecurse nounwind -define linkonce_odr spir_func void @_Z19templ_numbanks_attrILi4EEvv() #3 { -entry: - %templ_numbanks_var = alloca i32, align 4 - %s = alloca %struct.templ_numbanks_st, align 4 - call void @llvm.lifetime.start.p0(i64 4, ptr %templ_numbanks_var) #5 - ; CHECK-LLVM: call void @llvm.var.annotation.p0.p0(ptr %{{[a-zA-Z0-9_]+}}, ptr [[STR_NMB_TE]], ptr undef, i32 undef, ptr undef) - call void @llvm.var.annotation(ptr %templ_numbanks_var, ptr @.str.3, ptr @.str.1, i32 12, ptr null) - call void @llvm.lifetime.start.p0(i64 4, ptr %s) #5 - ; CHECK-LLVM: call void @llvm.var.annotation.p0.p0(ptr %{{[a-zA-Z0-9_]+}}, ptr [[STR_NMB_TE]], ptr undef, i32 undef, ptr undef) - call void @llvm.var.annotation(ptr %s, ptr @.str.3, ptr @.str.1, i32 16, ptr null) - store i32 0, ptr %s, align 4, !tbaa !12 - call void @llvm.lifetime.end.p0(i64 4, ptr %s) #5 - call void @llvm.lifetime.end.p0(i64 4, ptr %templ_numbanks_var) #5 - ret void -} - -; Function Attrs: norecurse nounwind -define spir_func void @_Z13register_attrv() #3 { -entry: - %register_var = alloca i32, align 4 - %s = alloca %struct.register_st, align 4 - call void @llvm.lifetime.start.p0(i64 4, ptr %register_var) #5 - ; CHECK-LLVM: call void @llvm.var.annotation.p0.p0(ptr %{{[a-zA-Z0-9_]+}}, ptr [[STR_REG_VAR]], ptr undef, i32 undef, ptr undef) - call void @llvm.var.annotation(ptr %register_var, ptr @.str.4, ptr @.str.1, i32 21, ptr null) - call void @llvm.lifetime.start.p0(i64 4, ptr %s) #5 - ; CHECK-LLVM: call void @llvm.var.annotation.p0.p0(ptr %{{[a-zA-Z0-9_]+}}, ptr [[STR_REG_VAR]], ptr undef, i32 undef, ptr undef) - call void @llvm.var.annotation(ptr %s, ptr @.str.4, ptr @.str.1, i32 25, ptr null) - store i32 0, ptr %s, align 4, !tbaa !14 - call void @llvm.lifetime.end.p0(i64 4, ptr %s) #5 - call void @llvm.lifetime.end.p0(i64 4, ptr %register_var) #5 - ret void -} - -; Function Attrs: norecurse nounwind -define spir_func void @_Z11memory_attrv() #3 { -entry: - %memory_var = alloca [500 x i32], align 4 - %s = alloca %struct.memory_st, align 4 - call void @llvm.lifetime.start.p0(i64 2000, ptr %memory_var) #5 - ; CHECK-LLVM: call void @llvm.var.annotation.p0.p0(ptr %{{[a-zA-Z0-9_]+}}, ptr [[STR_MEM_VAR]], ptr undef, i32 undef, ptr undef) - call void @llvm.var.annotation(ptr %memory_var, ptr @.str.5, ptr @.str.1, i32 30, ptr null) - call void @llvm.lifetime.start.p0(i64 80, ptr %s) #5 - ; CHECK-LLVM: call void @llvm.var.annotation.p0.p0(ptr %{{[a-zA-Z0-9_]+}}, ptr [[STR_MEM_SCT]], ptr undef, i32 undef, ptr undef) - call void @llvm.var.annotation(ptr %s, ptr @.str.6, ptr @.str.1, i32 34, ptr null) - store i32 0, ptr %s, align 4, !tbaa !16 - call void @llvm.lifetime.end.p0(i64 80, ptr %s) #5 - call void @llvm.lifetime.end.p0(i64 2000, ptr %memory_var) #5 - ret void -} - -; Function Attrs: norecurse nounwind -define spir_func void @_Z14bankwidth_attrv() #3 { -entry: - %bankwidth_var = alloca i32, align 4 - %s = alloca %struct.bankwidth_st, align 4 - call void @llvm.lifetime.start.p0(i64 4, ptr %bankwidth_var) #5 - ; CHECK-LLVM: call void @llvm.var.annotation.p0.p0(ptr %{{[a-zA-Z0-9_]+}}, ptr [[STR_BWD_VAR]], ptr undef, i32 undef, ptr undef) - call void @llvm.var.annotation(ptr %bankwidth_var, ptr @.str.7, ptr @.str.1, i32 39, ptr null) - call void @llvm.lifetime.start.p0(i64 4, ptr %s) #5 - ; CHECK-LLVM: call void @llvm.var.annotation.p0.p0(ptr %{{[a-zA-Z0-9_]+}}, ptr [[STR_BWD_SCT]], ptr undef, i32 undef, ptr undef) - call void @llvm.var.annotation(ptr %s, ptr @.str.8, ptr @.str.1, i32 43, ptr null) - store i32 0, ptr %s, align 4, !tbaa !17 - call void @llvm.lifetime.end.p0(i64 4, ptr %s) #5 - call void @llvm.lifetime.end.p0(i64 4, ptr %bankwidth_var) #5 - ret void -} - -; Function Attrs: norecurse nounwind -define linkonce_odr spir_func void @_Z20templ_bankwidth_attrILi16EEvv() #3 { -entry: - %templ_bankwidth_var = alloca i32, align 4 - %s = alloca %struct.templ_bankwidth_st, align 4 - call void @llvm.lifetime.start.p0(i64 4, ptr %templ_bankwidth_var) #5 - ; CHECK-LLVM: call void @llvm.var.annotation.p0.p0(ptr %{{[a-zA-Z0-9_]+}}, ptr [[STR_BWD_TE]], ptr undef, i32 undef, ptr undef) - call void @llvm.var.annotation(ptr %templ_bankwidth_var, ptr @.str.9, ptr @.str.1, i32 49, ptr null) - call void @llvm.lifetime.start.p0(i64 4, ptr %s) #5 - ; CHECK-LLVM: call void @llvm.var.annotation.p0.p0(ptr %{{[a-zA-Z0-9_]+}}, ptr [[STR_BWD_TE]], ptr undef, i32 undef, ptr undef) - call void @llvm.var.annotation(ptr %s, ptr @.str.9, ptr @.str.1, i32 53, ptr null) - store i32 0, ptr %s, align 4, !tbaa !19 - call void @llvm.lifetime.end.p0(i64 4, ptr %s) #5 - call void @llvm.lifetime.end.p0(i64 4, ptr %templ_bankwidth_var) #5 - ret void -} - -; Function Attrs: norecurse nounwind -define spir_func void @_Z19private_copies_attrv() #3 { -entry: - %priv_copies_var = alloca i32, align 4 - %s = alloca %struct.priv_copies_st, align 4 - call void @llvm.lifetime.start.p0(i64 4, ptr %priv_copies_var) #5 - ; CHECK-LLVM: call void @llvm.var.annotation.p0.p0(ptr %{{[a-zA-Z0-9_]+}}, ptr [[STR_PRC_VAR]], ptr undef, i32 undef, ptr undef) - call void @llvm.var.annotation(ptr %priv_copies_var, ptr @.str.10, ptr @.str.1, i32 58, ptr null) - call void @llvm.lifetime.start.p0(i64 4, ptr %s) #5 - ; CHECK-LLVM: call void @llvm.var.annotation.p0.p0(ptr %{{[a-zA-Z0-9_]+}}, ptr [[STR_PRC_SCT]], ptr undef, i32 undef, ptr undef) - call void @llvm.var.annotation(ptr %s, ptr @.str.11, ptr @.str.1, i32 62, ptr null) - store i32 0, ptr %s, align 4, !tbaa !21 - call void @llvm.lifetime.end.p0(i64 4, ptr %s) #5 - call void @llvm.lifetime.end.p0(i64 4, ptr %priv_copies_var) #5 - ret void -} - -; Function Attrs: norecurse nounwind -define linkonce_odr spir_func void @_Z25templ_private_copies_attrILi8EEvv() #3 { -entry: - %templ_priv_copies_var = alloca i32, align 4 - %s = alloca %struct.templ_priv_copies_st, align 4 - call void @llvm.lifetime.start.p0(i64 4, ptr %templ_priv_copies_var) #5 - ; CHECK-LLVM: call void @llvm.var.annotation.p0.p0(ptr %{{[a-zA-Z0-9_]+}}, ptr [[STR_PRC_TE]], ptr undef, i32 undef, ptr undef) - call void @llvm.var.annotation(ptr %templ_priv_copies_var, ptr @.str.12, ptr @.str.1, i32 68, ptr null) - call void @llvm.lifetime.start.p0(i64 4, ptr %s) #5 - ; CHECK-LLVM: call void @llvm.var.annotation.p0.p0(ptr %{{[a-zA-Z0-9_]+}}, ptr [[STR_PRC_TE]], ptr undef, i32 undef, ptr undef) - call void @llvm.var.annotation(ptr %s, ptr @.str.12, ptr @.str.1, i32 72, ptr null) - store i32 0, ptr %s, align 4, !tbaa !23 - call void @llvm.lifetime.end.p0(i64 4, ptr %s) #5 - call void @llvm.lifetime.end.p0(i64 4, ptr %templ_priv_copies_var) #5 - ret void -} - -; Function Attrs: norecurse nounwind -define spir_func void @_Z15singlepump_attrv() #3 { -entry: - %singlepump_var = alloca i32, align 4 - %s = alloca %struct.singlepump_st, align 4 - call void @llvm.lifetime.start.p0(i64 4, ptr %singlepump_var) #5 - ; CHECK-LLVM: call void @llvm.var.annotation.p0.p0(ptr %{{[a-zA-Z0-9_]+}}, ptr [[STR_SNP_VAR]], ptr undef, i32 undef, ptr undef) - call void @llvm.var.annotation(ptr %singlepump_var, ptr @.str.13, ptr @.str.1, i32 77, ptr null) - call void @llvm.lifetime.start.p0(i64 4, ptr %s) #5 - ; CHECK-LLVM: call void @llvm.var.annotation.p0.p0(ptr %{{[a-zA-Z0-9_]+}}, ptr [[STR_SNP_VAR]], ptr undef, i32 undef, ptr undef) - call void @llvm.var.annotation(ptr %s, ptr @.str.13, ptr @.str.1, i32 81, ptr null) - store i32 0, ptr %s, align 4, !tbaa !25 - call void @llvm.lifetime.end.p0(i64 4, ptr %s) #5 - call void @llvm.lifetime.end.p0(i64 4, ptr %singlepump_var) #5 - ret void -} - -; Function Attrs: norecurse nounwind -define spir_func void @_Z15doublepump_attrv() #3 { -entry: - %doublepump_var = alloca i32, align 4 - %s = alloca %struct.doublepump_st, align 4 - call void @llvm.lifetime.start.p0(i64 4, ptr %doublepump_var) #5 - ; CHECK-LLVM: call void @llvm.var.annotation.p0.p0(ptr %{{[a-zA-Z0-9_]+}}, ptr [[STR_DBP_VAR]], ptr undef, i32 undef, ptr undef) - call void @llvm.var.annotation(ptr %doublepump_var, ptr @.str.14, ptr @.str.1, i32 86, ptr null) - call void @llvm.lifetime.start.p0(i64 4, ptr %s) #5 - ; CHECK-LLVM: call void @llvm.var.annotation.p0.p0(ptr %{{[a-zA-Z0-9_]+}}, ptr [[STR_DBP_VAR]], ptr undef, i32 undef, ptr undef) - call void @llvm.var.annotation(ptr %s, ptr @.str.14, ptr @.str.1, i32 90, ptr null) - store i32 0, ptr %s, align 4, !tbaa !27 - call void @llvm.lifetime.end.p0(i64 4, ptr %s) #5 - call void @llvm.lifetime.end.p0(i64 4, ptr %doublepump_var) #5 - ret void -} - -; Function Attrs: norecurse nounwind -define spir_func void @_Z10merge_attrv() #3 { -entry: - %merge_var = alloca i32, align 4 - %s = alloca %struct.merge_st, align 4 - call void @llvm.lifetime.start.p0(i64 4, ptr %merge_var) #5 - ; CHECK-LLVM: call void @llvm.var.annotation.p0.p0(ptr %{{[a-zA-Z0-9_]+}}, ptr [[STR_MRG_VAR]], ptr undef, i32 undef, ptr undef) - call void @llvm.var.annotation(ptr %merge_var, ptr @.str.15, ptr @.str.1, i32 95, ptr null) - call void @llvm.lifetime.start.p0(i64 4, ptr %s) #5 - ; CHECK-LLVM: call void @llvm.var.annotation.p0.p0(ptr %{{[a-zA-Z0-9_]+}}, ptr [[STR_MRG_SCT]], ptr undef, i32 undef, ptr undef) - call void @llvm.var.annotation(ptr %s, ptr @.str.16, ptr @.str.1, i32 99, ptr null) - store i32 0, ptr %s, align 4, !tbaa !29 - call void @llvm.lifetime.end.p0(i64 4, ptr %s) #5 - call void @llvm.lifetime.end.p0(i64 4, ptr %merge_var) #5 - ret void -} - -; Function Attrs: norecurse nounwind -define spir_func void @_Z19max_replicates_attrv() #3 { -entry: - %max_repl_var = alloca i32, align 4 - %s = alloca %struct.max_repl_st, align 4 - call void @llvm.lifetime.start.p0(i64 4, ptr %max_repl_var) #5 - ; CHECK-LLVM: call void @llvm.var.annotation.p0.p0(ptr %{{[a-zA-Z0-9_]+}}, ptr [[STR_MXR_VAR]], ptr undef, i32 undef, ptr undef) - call void @llvm.var.annotation(ptr %max_repl_var, ptr @.str.17, ptr @.str.1, i32 104, ptr null) - call void @llvm.lifetime.start.p0(i64 4, ptr %s) #5 - ; CHECK-LLVM: call void @llvm.var.annotation.p0.p0(ptr %{{[a-zA-Z0-9_]+}}, ptr [[STR_MXR_SCT]], ptr undef, i32 undef, ptr undef) - call void @llvm.var.annotation(ptr %s, ptr @.str.18, ptr @.str.1, i32 108, ptr null) - store i32 0, ptr %s, align 4, !tbaa !31 - call void @llvm.lifetime.end.p0(i64 4, ptr %s) #5 - call void @llvm.lifetime.end.p0(i64 4, ptr %max_repl_var) #5 - ret void -} - -; Function Attrs: norecurse nounwind -define linkonce_odr spir_func void @_Z25templ_max_replicates_attrILi8EEvv() #3 { -entry: - %templ_max_repl_var = alloca i32, align 4 - %s = alloca %struct.templ_max_repl_st, align 4 - call void @llvm.lifetime.start.p0(i64 4, ptr %templ_max_repl_var) #5 - ; CHECK-LLVM: call void @llvm.var.annotation.p0.p0(ptr %{{[a-zA-Z0-9_]+}}, ptr [[STR_MXR_TE]], ptr undef, i32 undef, ptr undef) - call void @llvm.var.annotation(ptr %templ_max_repl_var, ptr @.str.19, ptr @.str.1, i32 114, ptr null) - call void @llvm.lifetime.start.p0(i64 4, ptr %s) #5 - ; CHECK-LLVM: call void @llvm.var.annotation.p0.p0(ptr %{{[a-zA-Z0-9_]+}}, ptr [[STR_MXR_TE]], ptr undef, i32 undef, ptr undef) - call void @llvm.var.annotation(ptr %s, ptr @.str.19, ptr @.str.1, i32 118, ptr null) - store i32 0, ptr %s, align 4, !tbaa !33 - call void @llvm.lifetime.end.p0(i64 4, ptr %s) #5 - call void @llvm.lifetime.end.p0(i64 4, ptr %templ_max_repl_var) #5 - ret void -} - -; Function Attrs: norecurse nounwind -define spir_func void @_Z21simple_dual_port_attrv() #3 { -entry: - %simple_dual_port_var = alloca i32, align 4 - %s = alloca %struct.simple_dual_port_st, align 4 - call void @llvm.lifetime.start.p0(i64 4, ptr %simple_dual_port_var) #5 - ; CHECK-LLVM: call void @llvm.var.annotation.p0.p0(ptr %{{[a-zA-Z0-9_]+}}, ptr [[STR_SDP_VAR]], ptr undef, i32 undef, ptr undef) - call void @llvm.var.annotation(ptr %simple_dual_port_var, ptr @.str.20, ptr @.str.1, i32 123, ptr null) - call void @llvm.lifetime.start.p0(i64 4, ptr %s) #5 - ; CHECK-LLVM: call void @llvm.var.annotation.p0.p0(ptr %{{[a-zA-Z0-9_]+}}, ptr [[STR_SDP_VAR]], ptr undef, i32 undef, ptr undef) - call void @llvm.var.annotation(ptr %s, ptr @.str.20, ptr @.str.1, i32 127, ptr null) - store i32 0, ptr %s, align 4, !tbaa !35 - call void @llvm.lifetime.end.p0(i64 4, ptr %s) #5 - call void @llvm.lifetime.end.p0(i64 4, ptr %simple_dual_port_var) #5 - ret void -} - -; Function Attrs: norecurse nounwind -define spir_func void @_Z14bank_bits_attrv() #3 { -entry: - %bank_bits_var = alloca i32, align 4 - %s = alloca %struct.bank_bits_st, align 4 - call void @llvm.lifetime.start.p0(i64 4, ptr %bank_bits_var) #5 - ; CHECK-LLVM: call void @llvm.var.annotation.p0.p0(ptr %{{[a-zA-Z0-9_]+}}, ptr [[STR_BBT_VAR]], ptr undef, i32 undef, ptr undef) - call void @llvm.var.annotation(ptr %bank_bits_var, ptr @.str.21, ptr @.str.1, i32 132, ptr null) - call void @llvm.lifetime.start.p0(i64 4, ptr %s) #5 - ; CHECK-LLVM: call void @llvm.var.annotation.p0.p0(ptr %{{[a-zA-Z0-9_]+}}, ptr [[STR_BBT_SCT]], ptr undef, i32 undef, ptr undef) - call void @llvm.var.annotation(ptr %s, ptr @.str.22, ptr @.str.1, i32 136, ptr null) - store i32 0, ptr %s, align 4, !tbaa !37 - call void @llvm.lifetime.end.p0(i64 4, ptr %s) #5 - call void @llvm.lifetime.end.p0(i64 4, ptr %bank_bits_var) #5 - ret void -} - -; Function Attrs: norecurse nounwind -define linkonce_odr spir_func void @_Z20templ_bank_bits_attrILi4ELi5EEvv() #3 { -entry: - %templ_bank_bits_var = alloca i32, align 4 - %s = alloca %struct.templ_bank_bits_st, align 4 - call void @llvm.lifetime.start.p0(i64 4, ptr %templ_bank_bits_var) #5 - ; CHECK-LLVM: call void @llvm.var.annotation.p0.p0(ptr %{{[a-zA-Z0-9_]+}}, ptr [[STR_BBT_TE1]], ptr undef, i32 undef, ptr undef) - call void @llvm.var.annotation(ptr %templ_bank_bits_var, ptr @.str.23, ptr @.str.1, i32 142, ptr null) - call void @llvm.lifetime.start.p0(i64 4, ptr %s) #5 - ; CHECK-LLVM: call void @llvm.var.annotation.p0.p0(ptr %{{[a-zA-Z0-9_]+}}, ptr [[STR_BBT_TE2]], ptr undef, i32 undef, ptr undef) - call void @llvm.var.annotation(ptr %s, ptr @.str.24, ptr @.str.1, i32 146, ptr null) - store i32 0, ptr %s, align 4, !tbaa !39 - call void @llvm.lifetime.end.p0(i64 4, ptr %s) #5 - call void @llvm.lifetime.end.p0(i64 4, ptr %templ_bank_bits_var) #5 - ret void -} - -; Function Attrs: norecurse nounwind -define spir_func void @_Z21force_pow2_depth_attrv() #3 { -entry: - %fp2d_var = alloca i32, align 4 - %s = alloca %struct.fp2d_st, align 4 - call void @llvm.lifetime.start.p0(i64 4, ptr %fp2d_var) #5 - ; CHECK-LLVM: call void @llvm.var.annotation.p0.p0(ptr %{{[a-zA-Z0-9_]+}}, ptr [[STR_FP2_VAR]], ptr undef, i32 undef, ptr undef) - call void @llvm.var.annotation(ptr %fp2d_var, ptr @.str.25, ptr @.str.1, i32 151, ptr null) - call void @llvm.lifetime.start.p0(i64 4, ptr %s) #5 - ; CHECK-LLVM: call void @llvm.var.annotation.p0.p0(ptr %{{[a-zA-Z0-9_]+}}, ptr [[STR_FP2_SCT]], ptr undef, i32 undef, ptr undef) - call void @llvm.var.annotation(ptr %s, ptr @.str.26, ptr @.str.1, i32 155, ptr null) - store i32 0, ptr %s, align 4, !tbaa !41 - call void @llvm.lifetime.end.p0(i64 4, ptr %s) #5 - call void @llvm.lifetime.end.p0(i64 4, ptr %fp2d_var) #5 - ret void -} - -; Function Attrs: norecurse nounwind -define linkonce_odr spir_func void @_Z27templ_force_pow2_depth_attrILi1EEvv() #3 { -entry: - %templ_fp2d_var = alloca i32, align 4 - %s = alloca %struct.templ_fp2d_st, align 4 - call void @llvm.lifetime.start.p0(i64 4, ptr %templ_fp2d_var) #5 - ; CHECK-LLVM: call void @llvm.var.annotation.p0.p0(ptr %{{[a-zA-Z0-9_]+}}, ptr [[STR_FP2_SCT]], ptr undef, i32 undef, ptr undef) - call void @llvm.var.annotation(ptr %templ_fp2d_var, ptr @.str.26, ptr @.str.1, i32 161, ptr null) - call void @llvm.lifetime.start.p0(i64 4, ptr %s) #5 - ; CHECK-LLVM: call void @llvm.var.annotation.p0.p0(ptr %{{[a-zA-Z0-9_]+}}, ptr [[STR_FP2_SCT]], ptr undef, i32 undef, ptr undef) - call void @llvm.var.annotation(ptr %s, ptr @.str.26, ptr @.str.1, i32 165, ptr null) - store i32 0, ptr %s, align 4, !tbaa !43 - call void @llvm.lifetime.end.p0(i64 4, ptr %s) #5 - call void @llvm.lifetime.end.p0(i64 4, ptr %templ_fp2d_var) #5 - ret void -} - -; Function Attrs: convergent noinline norecurse nounwind optnone mustprogress -define dso_local spir_func void @_Z25memory_attribute_on_arrayv() #2 { -entry: - %register_var = alloca [32 x i32], align 4 - %register_var.ascast = addrspacecast ptr %register_var to ptr addrspace(4) - %register_var.ascast2 = addrspacecast ptr addrspace(4) %register_var.ascast to ptr - ; CHECK-LLVM: call void @llvm.var.annotation.p0.p0(ptr %{{[a-zA-Z0-9_.]+}}, ptr [[STR_REG_VAR]], ptr undef, i32 undef, ptr undef) - call void @llvm.var.annotation(ptr %register_var.ascast2, ptr @.str.4, ptr @.str.1, i32 2, ptr null) - ret void -} - -attributes #0 = { norecurse nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "sycl-module-id"="intel-fpga-local-var.cpp" "uniform-work-group-size"="true" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #1 = { argmemonly nounwind willreturn } -attributes #2 = { inlinehint norecurse nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #3 = { norecurse nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #4 = { nounwind willreturn } -attributes #5 = { nounwind } - -!llvm.module.flags = !{!0} -!opencl.spir.version = !{!1} -!spirv.Source = !{!2} -!llvm.ident = !{!3} - -!0 = !{i32 1, !"wchar_size", i32 4} -!1 = !{i32 1, i32 2} -!2 = !{i32 4, i32 100000} -!3 = !{!"clang version 11.0.0"} -!4 = !{} -!5 = !{!6, !6, i64 0} -!6 = !{!"any pointer", !7, i64 0} -!7 = !{!"omnipotent char", !8, i64 0} -!8 = !{!"Simple C++ TBAA"} -!9 = !{!10, !11, i64 0} -!10 = !{!"_ZTSZ13numbanks_attrvE11numbanks_st", !11, i64 0} -!11 = !{!"int", !7, i64 0} -!12 = !{!13, !11, i64 0} -!13 = !{!"_ZTSZ19templ_numbanks_attrILi4EEvvE17templ_numbanks_st", !11, i64 0} -!14 = !{!15, !11, i64 0} -!15 = !{!"_ZTSZ13register_attrvE11register_st", !11, i64 0} -!16 = !{!11, !11, i64 0} -!17 = !{!18, !11, i64 0} -!18 = !{!"_ZTSZ14bankwidth_attrvE12bankwidth_st", !11, i64 0} -!19 = !{!20, !11, i64 0} -!20 = !{!"_ZTSZ20templ_bankwidth_attrILi16EEvvE18templ_bankwidth_st", !11, i64 0} -!21 = !{!22, !11, i64 0} -!22 = !{!"_ZTSZ19private_copies_attrvE14priv_copies_st", !11, i64 0} -!23 = !{!24, !11, i64 0} -!24 = !{!"_ZTSZ25templ_private_copies_attrILi8EEvvE20templ_priv_copies_st", !11, i64 0} -!25 = !{!26, !11, i64 0} -!26 = !{!"_ZTSZ15singlepump_attrvE13singlepump_st", !11, i64 0} -!27 = !{!28, !11, i64 0} -!28 = !{!"_ZTSZ15doublepump_attrvE13doublepump_st", !11, i64 0} -!29 = !{!30, !11, i64 0} -!30 = !{!"_ZTSZ10merge_attrvE8merge_st", !11, i64 0} -!31 = !{!32, !11, i64 0} -!32 = !{!"_ZTSZ19max_replicates_attrvE11max_repl_st", !11, i64 0} -!33 = !{!34, !11, i64 0} -!34 = !{!"_ZTSZ25templ_max_replicates_attrILi8EEvvE17templ_max_repl_st", !11, i64 0} -!35 = !{!36, !11, i64 0} -!36 = !{!"_ZTSZ21simple_dual_port_attrvE19simple_dual_port_st", !11, i64 0} -!37 = !{!38, !11, i64 0} -!38 = !{!"_ZTSZ14bank_bits_attrvE12bank_bits_st", !11, i64 0} -!39 = !{!40, !11, i64 0} -!40 = !{!"_ZTSZ20templ_bank_bits_attrILi4ELi5EEvvE18templ_bank_bits_st", !11, i64 0} -!41 = !{!42, !11, i64 0} -!42 = !{!"_ZTSZ21force_pow2_depth_attrvE7fp2d_st", !11, i64 0} -!43 = !{!44, !11, i64 0} -!44 = !{!"_ZTSZ27templ_force_pow2_depth_attrILi1EEvvE13templ_fp2d_st", !11, i64 0} diff --git a/test/extensions/INTEL/SPV_INTEL_fpga_memory_attributes/IntelFPGAMemoryAttributesForStruct.ll b/test/extensions/INTEL/SPV_INTEL_fpga_memory_attributes/IntelFPGAMemoryAttributesForStruct.ll index 90b975ea6a..2fb68b37b0 100644 --- a/test/extensions/INTEL/SPV_INTEL_fpga_memory_attributes/IntelFPGAMemoryAttributesForStruct.ll +++ b/test/extensions/INTEL/SPV_INTEL_fpga_memory_attributes/IntelFPGAMemoryAttributesForStruct.ll @@ -1,759 +1,286 @@ -; LLVM IR generated by Intel SYCL Clang compiler (https://github.com/intel/llvm) - -; SYCL source code for this test: -; void field_numbanks_attr() { -; struct numbanks_st { -; [[intelfpga::numbanks(4)]] int field; -; } s; -; s.field = 0; -; } -; -; template -; void templ_field_numbanks_attr() { -; struct templ_numbanks_st { -; [[intelfpga::numbanks(A)]] int field; -; } s; -; s.field = 0; -; } -; -; void field_register_attr() { -; struct register_st { -; [[intelfpga::register]] int field; -; } s; -; s.field = 0; -; } -; -; void field_memory_attr() { -; struct memory_st { -; [[intelfpga::memory("MLAB")]] int field; -; } s; -; s.field = 0; -; } -; -; void field_bankwidth_attr() { -; struct bankwidth_st { -; [[intelfpga::bankwidth(8)]] int field; -; } s; -; s.field = 0; -; } -; -; template -; void templ_field_bankwidth_attr() { -; struct templ_bankwidth_st { -; [[intelfpga::bankwidth(A)]] int field; -; } s; -; s.field = 0; -; } -; -; void field_private_copies_attr() { -; struct private_copies_st { -; [[intelfpga::private_copies(4)]] int field; -; } s; -; s.field = 0; -; } -; -; template -; void templ_field_private_copies_attr() { -; struct templ_private_copies_st { -; [[intelfpga::private_copies(A)]] int field; -; } s; -; s.field = 0; -; } -; -; void field_singlepump_attr() { -; struct singlepump_st { -; [[intelfpga::singlepump]] int field; -; } s; -; s.field = 0; -; } -; -; void field_doublepump_attr() { -; struct doublepump_st { -; [[intelfpga::doublepump]] int field; -; } s; -; s.field = 0; -; } -; -; void field_merge_attr() { -; struct merge_st { -; [[intelfpga::merge("foobar", "width")]] int field; -; } s; -; s.field = 0; -; } -; -; void field_max_replicates_attr() { -; struct max_replicates_st { -; [[intelfpga::max_replicates(4)]] int field; -; } s; -; s.field = 0; -; } -; -; template -; void templ_field_max_replicates_attr() { -; struct templ_max_replicates_st { -; [[intelfpga::max_replicates(A)]] int field; -; } s; -; s.field = 0; -; } -; -; void field_simple_dual_port_attr() { -; struct simple_dual_port_st { -; [[intelfpga::simple_dual_port]] int field; -; } s; -; s.field = 0; -; } -; -; void field_bank_bits_attr() { -; struct bank_bits_st { -; [[intelfpga::bank_bits(42,41,40)]] int field; -; } s; -; s.field = 0; -; } -; -; template -; void templ_field_bank_bits_attr() { -; struct templ_bank_bits_st { -; [[intelfpga::bank_bits(A, B)]] int field; -; } s; -; s.field = 0; -; } -; -; void field_force_pow2_depth_attr() { -; struct force_pow2_depth_st { -; [[intelfpga::force_pow2_depth(0)]] int field; -; } s; -; s.field = 0; -; } -; -; template -; void templ_field_force_pow2_depth_attr() { -; struct templ_force_pow2_depth_st { -; [[intelfpga::force_pow2_depth(A)]] int field; -; } s; -; s.field = 0; -; } -; -; void field_addrspace_cast() { -; struct state { -; [[intelfpga::numbanks(2)]] int mem[8]; -; -; // The initialization code is not relevant to this example. -; // It prevents the compiler from optimizing away access to this struct. -; state() { -; for (auto i = 0; i < 8; i++) { -; mem[i] = i; -; } -; } -; } state_var; -; state_var.mem[0] = 42; -; } -; -; template -; __attribute__((sycl_kernel)) void kernel_single_task(Func kernelFunc) { -; kernelFunc(); -; } -; -; int main() { -; kernel_single_task([]() { -; field_numbanks_attr(); -; templ_field_numbanks_attr<8>(); -; field_register_attr(); -; field_memory_attr(); -; field_bankwidth_attr(); -; templ_field_bankwidth_attr<4>(); -; field_private_copies_attr(); -; templ_field_private_copies_attr<2>(); -; field_singlepump_attr(); -; field_doublepump_attr(); -; field_merge_attr(); -; field_max_replicates_attr(); -; templ_field_max_replicates_attr<2>(); -; field_simple_dual_port_attr(); -; field_bank_bits_attr(); -; templ_field_bank_bits_attr<2,3>(); -; field_force_pow2_depth_attr(); -; templ_field_force_pow2_depth_attr<1>(); -; field_addrspace_cast(); -; }); -; return 0; -; } - -; LLVM IR compilation command: -; clang -cc1 -triple spir -disable-llvm-passes -fsycl-is-device -emit-llvm intel-fpga-local-var.cpp - ; RUN: llvm-as %s -o %t.bc -; RUN: llvm-spirv %t.bc --spirv-ext=+SPV_INTEL_fpga_memory_attributes -o %t.spv -; RUN: llvm-spirv %t.spv --spirv-ext=+SPV_INTEL_fpga_memory_attributes -to-text -o %t.spt -; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV - -; RUN: llvm-spirv -r %t.spv -o %t.rev.bc -; RUN: llvm-dis < %t.rev.bc | FileCheck %s --check-prefix=CHECK-LLVM +; RUN: llvm-spirv --spirv-ext=+SPV_INTEL_fpga_memory_attributes -spirv-text -o - %t.bc | FileCheck --check-prefix CHECK-SPIRV %s +; RUN: llvm-spirv --spirv-ext=+SPV_INTEL_fpga_memory_attributes %t.bc -o %t.spv +; RUN: spirv-val %t.spv +; RUN: llvm-spirv -r --spirv-ext=+SPV_INTEL_fpga_memory_attributes %t.spv -o %t.rev.bc +; RUN: llvm-dis %t.rev.bc -o - | FileCheck --check-prefix CHECK-LLVM %s -; RUN: llvm-spirv -spirv-text -r %t.spt -o %t.rev.bc -; RUN: llvm-dis < %t.rev.bc | FileCheck %s --check-prefix=CHECK-LLVM - -; TODO: add a bunch of different tests for --spirv-ext option +target triple = "spir64-unknown-unknown" ; CHECK-SPIRV: Capability FPGAMemoryAttributesINTEL ; CHECK-SPIRV: Extension "SPV_INTEL_fpga_memory_attributes" -; CHECK-SPIRV-DAG: MemberDecorate {{[0-9]+}} 0 UserSemantic "{sizeinfo:4}" -; CHECK-SPIRV-DAG: MemberDecorate {{[0-9]+}} 0 RegisterINTEL -; CHECK-SPIRV-DAG: MemberDecorate {{[0-9]+}} 0 MemoryINTEL "DEFAULT" -; CHECK-SPIRV-DAG: MemberDecorate {{[0-9]+}} 0 MemoryINTEL "MLAB" -; CHECK-SPIRV-DAG: MemberDecorate {{[0-9]+}} 0 NumbanksINTEL 2 -; CHECK-SPIRV-DAG: MemberDecorate {{[0-9]+}} 0 NumbanksINTEL 4 -; CHECK-SPIRV-DAG: MemberDecorate {{[0-9]+}} 0 NumbanksINTEL 8 -; CHECK-SPIRV-DAG: MemberDecorate {{[0-9]+}} 0 BankwidthINTEL 4 -; CHECK-SPIRV-DAG: MemberDecorate {{[0-9]+}} 0 BankwidthINTEL 8 -; CHECK-SPIRV-DAG: MemberDecorate {{[0-9]+}} 0 MaxPrivateCopiesINTEL 2 -; CHECK-SPIRV-DAG: MemberDecorate {{[0-9]+}} 0 MaxPrivateCopiesINTEL 4 -; CHECK-SPIRV-DAG: MemberDecorate {{[0-9]+}} 0 SinglepumpINTEL -; CHECK-SPIRV-DAG: MemberDecorate {{[0-9]+}} 0 DoublepumpINTEL -; CHECK-SPIRV-DAG: MemberDecorate {{[0-9]+}} 0 MaxReplicatesINTEL 2 -; CHECK-SPIRV-DAG: MemberDecorate {{[0-9]+}} 0 MaxReplicatesINTEL 4 -; CHECK-SPIRV-DAG: MemberDecorate {{[0-9]+}} 0 SimpleDualPortINTEL -; CHECK-SPIRV-DAG: MemberDecorate {{[0-9]+}} 0 MergeINTEL "foobar" "width" -; CHECK-SPIRV-DAG: MemberDecorate {{[0-9]+}} 0 BankBitsINTEL 2 3 -; CHECK-SPIRV-DAG: MemberDecorate {{[0-9]+}} 0 BankBitsINTEL 42 41 40 -; CHECK-SPIRV-DAG: MemberDecorate {{[0-9]+}} 0 ForcePow2DepthINTEL 0 -; CHECK-SPIRV-DAG: MemberDecorate {{[0-9]+}} 0 ForcePow2DepthINTEL 1 - -target datalayout = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024" -target triple = "spir" - -%class.anon = type { i8 } -%struct.numbanks_st = type { i32 } -%struct.templ_numbanks_st = type { i32 } -%struct.register_st = type { i32 } -%struct.memory_st = type { i32 } -%struct.bankwidth_st = type { i32 } -%struct.templ_bankwidth_st = type { i32 } -%struct.private_copies_st = type { i32 } -%struct.templ_private_copies_st = type { i32 } -%struct.singlepump_st = type { i32 } -%struct.doublepump_st = type { i32 } -%struct.merge_st = type { i32 } -%struct.max_replicates_st = type { i32 } -%struct.templ_max_replicates_st = type { i32 } -%struct.simple_dual_port_st = type { i32 } -%struct.bank_bits_st = type { i32 } -%struct.templ_bank_bits_st = type { i32 } -%struct.force_pow2_depth_st = type { i32 } -%struct.templ_force_pow2_depth_st = type { i32 } -%struct.state = type { [8 x i32] } - -; CHECK-LLVM: [[STR_NMB_SCT:@[0-9_.]+]] = {{.*}}{memory:DEFAULT}{numbanks:4} -; CHECK-LLVM: [[STR_SIZEINF:@[0-9_.]+]] = {{.*}}{sizeinfo:4} -; CHECK-LLVM: [[STR_NMB_STE:@[0-9_.]+]] = {{.*}}{memory:DEFAULT}{numbanks:8} -; CHECK-LLVM: [[STR_REG_SCT:@[0-9_.]+]] = {{.*}}{register:1} -; CHECK-LLVM: [[STR_MEM_SCT:@[0-9_.]+]] = {{.*}}{memory:MLAB} -; CHECK-LLVM: [[STR_BWD_SCT:@[0-9_.]+]] = {{.*}}{memory:DEFAULT}{bankwidth:8} -; CHECK-LLVM: [[STR_BWD_STE:@[0-9_.]+]] = {{.*}}{memory:DEFAULT}{bankwidth:4} -; CHECK-LLVM: [[STR_PRC_SCT:@[0-9_.]+]] = {{.*}}{memory:DEFAULT}{private_copies:4} -; CHECK-LLVM: [[STR_PRC_STE:@[0-9_.]+]] = {{.*}}{memory:DEFAULT}{private_copies:2} -; CHECK-LLVM: [[STR_SNP_SCT:@[0-9_.]+]] = {{.*}}{memory:DEFAULT}{pump:1} -; CHECK-LLVM: [[STR_DBP_SCT:@[0-9_.]+]] = {{.*}}{memory:DEFAULT}{pump:2} -; CHECK-LLVM: [[STR_MRG_SCT:@[0-9_.]+]] = {{.*}}{memory:DEFAULT}{merge:foobar:width} -; CHECK-LLVM: [[STR_MXR_SCT:@[0-9_.]+]] = {{.*}}{max_replicates:4} -; CHECK-LLVM: [[STR_MXR_STE:@[0-9_.]+]] = {{.*}}{max_replicates:2} -; CHECK-LLVM: [[STR_SDP_SCT:@[0-9_.]+]] = {{.*}}{memory:DEFAULT}{simple_dual_port:1} -; CHECK-LLVM: [[STR_BBT_SCT:@[0-9_.]+]] = {{.*}}{memory:DEFAULT}{numbanks:8}{bank_bits:42,41,40} -; CHECK-LLVM: [[STR_BBT_STE:@[0-9_.]+]] = {{.*}}{memory:DEFAULT}{numbanks:4}{bank_bits:2,3} -; CHECK-LLVM: [[STR_FP2_SCT:@[0-9_.]+]] = {{.*}}{memory:DEFAULT}{force_pow2_depth:0} -; CHECK-LLVM: [[STR_FP2_STE:@[0-9_.]+]] = {{.*}}{memory:DEFAULT}{force_pow2_depth:1} -; CHECK-LLVM: [[STR_NMB_ASC:@[0-9_.]+]] = {{.*}}{memory:DEFAULT}{numbanks:2} -@.str = private unnamed_addr constant [41 x i8] c"{memory:DEFAULT}{sizeinfo:4}{numbanks:4}\00", section "llvm.metadata" -@.str.1 = private unnamed_addr constant [28 x i8] c"intel-fpga-local-struct.cpp\00", section "llvm.metadata" -@.str.2 = private unnamed_addr constant [41 x i8] c"{memory:DEFAULT}{sizeinfo:4}{numbanks:8}\00", section "llvm.metadata" -@.str.3 = private unnamed_addr constant [13 x i8] c"{register:1}\00", section "llvm.metadata" -@.str.4 = private unnamed_addr constant [26 x i8] c"{memory:MLAB}{sizeinfo:4}\00", section "llvm.metadata" -@.str.5 = private unnamed_addr constant [42 x i8] c"{memory:DEFAULT}{sizeinfo:4}{bankwidth:8}\00", section "llvm.metadata" -@.str.6 = private unnamed_addr constant [42 x i8] c"{memory:DEFAULT}{sizeinfo:4}{bankwidth:4}\00", section "llvm.metadata" -@.str.7 = private unnamed_addr constant [47 x i8] c"{memory:DEFAULT}{sizeinfo:4}{private_copies:4}\00", section "llvm.metadata" -@.str.8 = private unnamed_addr constant [47 x i8] c"{memory:DEFAULT}{sizeinfo:4}{private_copies:2}\00", section "llvm.metadata" -@.str.9 = private unnamed_addr constant [37 x i8] c"{memory:DEFAULT}{sizeinfo:4}{pump:1}\00", section "llvm.metadata" -@.str.10 = private unnamed_addr constant [37 x i8] c"{memory:DEFAULT}{sizeinfo:4}{pump:2}\00", section "llvm.metadata" -@.str.11 = private unnamed_addr constant [49 x i8] c"{memory:DEFAULT}{sizeinfo:4}{merge:foobar:width}\00", section "llvm.metadata" -@.str.12 = private unnamed_addr constant [19 x i8] c"{max_replicates:4}\00", section "llvm.metadata" -@.str.13 = private unnamed_addr constant [19 x i8] c"{max_replicates:2}\00", section "llvm.metadata" -@.str.14 = private unnamed_addr constant [49 x i8] c"{memory:DEFAULT}{sizeinfo:4}{simple_dual_port:1}\00", section "llvm.metadata" -@.str.15 = private unnamed_addr constant [61 x i8] c"{memory:DEFAULT}{sizeinfo:4}{numbanks:8}{bank_bits:42,41,40}\00", section "llvm.metadata" -@.str.16 = private unnamed_addr constant [56 x i8] c"{memory:DEFAULT}{sizeinfo:4}{numbanks:4}{bank_bits:2,3}\00", section "llvm.metadata" -@.str.17 = private unnamed_addr constant [49 x i8] c"{memory:DEFAULT}{sizeinfo:4}{force_pow2_depth:0}\00", section "llvm.metadata" -@.str.18 = private unnamed_addr constant [49 x i8] c"{memory:DEFAULT}{sizeinfo:4}{force_pow2_depth:1}\00", section "llvm.metadata" -@.str.19 = private unnamed_addr constant [43 x i8] c"{memory:DEFAULT}{sizeinfo:4,8}{numbanks:2}\00", section "llvm.metadata" - -; Function Attrs: norecurse nounwind -define spir_kernel void @_ZTSZ4mainE15kernel_function() #0 !kernel_arg_addr_space !4 !kernel_arg_access_qual !4 !kernel_arg_type !4 !kernel_arg_base_type !4 !kernel_arg_type_qual !4 { +; CHECK-SPIRV: Name [[#REGISTER_FUNC_NAME:]] "test_fpga_register_attr" +; CHECK-SPIRV: Name [[#REGISTER_TYPE:]] "register_type" +; CHECK-SPIRV: Name [[#MEMORY_FUNC_NAME:]] "test_fpga_memory_attr" +; CHECK-SPIRV: Name [[#MEMORY_TYPE:]] "memory_type" +; CHECK-SPIRV: Name [[#NUMBANKS_FUNC_NAME:]] "test_fpga_numbanks_attr" +; CHECK-SPIRV: Name [[#NUMBANKS_TYPE:]] "numbanks_type" +; CHECK-SPIRV: Name [[#BANKWIDTH_FUNC_NAME:]] "test_fpga_bankwidth_attr" +; CHECK-SPIRV: Name [[#BANKWIDTH_TYPE:]] "bankwidth_type" +; CHECK-SPIRV: Name [[#MAX_PRIVATE_COPIES_FUNC_NAME:]] "test_fpga_max_private_copies_attr" +; CHECK-SPIRV: Name [[#MAX_PRIVATE_COPIES_TYPE:]] "max_private_copies_type" +; CHECK-SPIRV: Name [[#SINGLEPUMP_FUNC_NAME:]] "test_fpga_singlepump_attr" +; CHECK-SPIRV: Name [[#SINGLEPUMP_TYPE:]] "singlepump_type" +; CHECK-SPIRV: Name [[#DOUBLEPUMP_FUNC_NAME:]] "test_fpga_doublepump_attr" +; CHECK-SPIRV: Name [[#DOUBLEPUMP_TYPE:]] "doublepump_type" +; CHECK-SPIRV: Name [[#MAX_REPLICATES_FUNC_NAME:]] "test_fpga_max_replicates_attr" +; CHECK-SPIRV: Name [[#MAX_REPLICATES_TYPE:]] "max_replicates_type" +; CHECK-SPIRV: Name [[#SIMPLE_DUAL_PORT_FUNC_NAME:]] "test_fpga_simple_dual_port_attr" +; CHECK-SPIRV: Name [[#SIMPLE_DUAL_PORT_TYPE:]] "simple_dual_port_type" +; CHECK-SPIRV: Name [[#MERGE_FUNC_NAME:]] "test_fpga_merge_attr" +; CHECK-SPIRV: Name [[#MERGE_TYPE:]] "merge_type" +; CHECK-SPIRV: Name [[#BANKBITS_FUNC_NAME:]] "test_fpga_bankbits_attr" +; CHECK-SPIRV: Name [[#BANKBITS_TYPE:]] "bankbits_type" +; CHECK-SPIRV: Name [[#FORCE_POW_2_DEPTH_FUNC_NAME:]] "test_fpga_force_pow_2_depth_attr" +; CHECK-SPIRV: Name [[#FORCE_POW_2_DEPTH_TYPE:]] "force_pow_2_depth_type" +; CHECK-SPIRV: Name [[#STRIDESIZE_FUNC_NAME:]] "test_fpga_stride_size_attr" +; CHECK-SPIRV: Name [[#STRIDESIZE_TYPE:]] "stride_size_type" +; CHECK-SPIRV: Name [[#WORDSIZE_FUNC_NAME:]] "test_fpga_word_size_attr" +; CHECK-SPIRV: Name [[#WORDSIZE_TYPE:]] "word_size_type" +; CHECK-SPIRV: Name [[#TRUE_DUAL_PORT_FUNC_NAME:]] "test_fpga_true_dual_port_attr" +; CHECK-SPIRV: Name [[#TRUE_DUAL_PORT_TYPE:]] "true_dual_port_type" + +; CHECK-SPIRV: Decorate [[#REGISTER_FUNC_NAME]] LinkageAttributes +; CHECK-SPIRV: Decorate [[#REGISTER:]] +; CHECK-SPIRV: MemberDecorate [[#REGISTER_TYPE]] 0 RegisterINTEL +; CHECK-SPIRV: Decorate [[#MEMORY_FUNC_NAME]] LinkageAttributes +; CHECK-SPIRV: Decorate [[#MEMORY:]] +; CHECK-SPIRV: MemberDecorate [[#MEMORY_TYPE]] 0 MemoryINTEL "DEFAULT" +; CHECK-SPIRV: Decorate [[#NUMBANKS_FUNC_NAME]] LinkageAttributes +; CHECK-SPIRV: Decorate [[#NUMBANKS:]] +; CHECK-SPIRV: MemberDecorate [[#NUMBANKS_TYPE]] 0 NumbanksINTEL 4 +; CHECK-SPIRV: Decorate [[#BANKWIDTH_FUNC_NAME]] LinkageAttributes +; CHECK-SPIRV: Decorate [[#BANKWIDTH:]] +; CHECK-SPIRV: MemberDecorate [[#BANKWIDTH_TYPE]] 0 BankwidthINTEL 4 +; CHECK-SPIRV: Decorate [[#MAX_PRIVATE_COPIES_FUNC_NAME]] LinkageAttributes +; CHECK-SPIRV: Decorate [[#MAX_PRIVATE_COPIES:]] +; CHECK-SPIRV: MemberDecorate [[#MAX_PRIVATE_COPIES_TYPE]] 0 MaxPrivateCopiesINTEL 1 +; CHECK-SPIRV: Decorate [[#SINGLEPUMP_FUNC_NAME]] LinkageAttributes +; CHECK-SPIRV: Decorate [[#SINGLEPUMP:]] +; CHECK-SPIRV: MemberDecorate [[#SINGLEPUMP_TYPE]] 0 SinglepumpINTEL +; CHECK-SPIRV: Decorate [[#DOUBLEPUMP_FUNC_NAME]] LinkageAttributes +; CHECK-SPIRV: Decorate [[#DOUBLEPUMP:]] +; CHECK-SPIRV: MemberDecorate [[#DOUBLEPUMP_TYPE]] 0 DoublepumpINTEL +; CHECK-SPIRV: Decorate [[#MAX_REPLICATES_FUNC_NAME]] LinkageAttributes +; CHECK-SPIRV: Decorate [[#MAX_REPLICATES:]] +; CHECK-SPIRV: MemberDecorate [[#MAX_REPLICATES_TYPE]] 0 MaxReplicatesINTEL 2 +; CHECK-SPIRV: Decorate [[#SIMPLE_DUAL_PORT_FUNC_NAME]] LinkageAttributes +; CHECK-SPIRV: Decorate [[#SIMPLE_DUAL_PORT:]] +; CHECK-SPIRV: MemberDecorate [[#SIMPLE_DUAL_PORT_TYPE]] 0 SimpleDualPortINTEL +; CHECK-SPIRV: Decorate [[#MERGE_FUNC_NAME]] LinkageAttributes +; CHECK-SPIRV: Decorate [[#MERGE:]] +; CHECK-SPIRV: MemberDecorate [[#MERGE_TYPE]] 0 MergeINTEL "key" "type" +; CHECK-SPIRV: Decorate [[#BANKBITS_FUNC_NAME]] LinkageAttributes +; CHECK-SPIRV: Decorate [[#BANKBITS:]] +; CHECK-SPIRV: MemberDecorate [[#BANKBITS_TYPE]] 0 BankBitsINTEL 2 +; CHECK-SPIRV: Decorate [[#FORCE_POW_2_DEPTH_FUNC_NAME]] LinkageAttributes +; CHECK-SPIRV: Decorate [[#FORCE_POW_2_DEPTH:]] +; CHECK-SPIRV: MemberDecorate [[#FORCE_POW_2_DEPTH_TYPE]] 0 ForcePow2DepthINTEL 2 +; CHECK-SPIRV: Decorate [[#STRIDESIZE_FUNC_NAME]] LinkageAttributes +; CHECK-SPIRV: Decorate [[#STRIDESIZE:]] +; CHECK-SPIRV: MemberDecorate [[#STRIDESIZE_TYPE]] 0 StridesizeINTEL 4 +; CHECK-SPIRV: Decorate [[#WORDSIZE_FUNC_NAME]] LinkageAttributes +; CHECK-SPIRV: Decorate [[#WORDSIZE:]] +; CHECK-SPIRV: MemberDecorate [[#WORDSIZE_TYPE]] 0 WordsizeINTEL 8 +; CHECK-SPIRV: Decorate [[#TRUE_DUAL_PORT_FUNC_NAME]] LinkageAttributes +; CHECK-SPIRV: Decorate [[#TRUE_DUAL_PORT:]] +; CHECK-SPIRV: MemberDecorate [[#TRUE_DUAL_PORT_TYPE]] 0 TrueDualPortINTEL +; CHECK-SPIRV: Variable {{[0-9]+}} [[#REGISTER]] {{[0-9]+}} +; CHECK-SPIRV: Variable {{[0-9]+}} [[#MEMORY]] {{[0-9]+}} +; CHECK-SPIRV: Variable {{[0-9]+}} [[#NUMBANKS]] {{[0-9]+}} +; CHECK-SPIRV: Variable {{[0-9]+}} [[#BANKWIDTH]] {{[0-9]+}} +; CHECK-SPIRV: Variable {{[0-9]+}} [[#MAX_PRIVATE_COPIES]] {{[0-9]+}} +; CHECK-SPIRV: Variable {{[0-9]+}} [[#SINGLEPUMP]] {{[0-9]+}} +; CHECK-SPIRV: Variable {{[0-9]+}} [[#DOUBLEPUMP]] {{[0-9]+}} +; CHECK-SPIRV: Variable {{[0-9]+}} [[#MAX_REPLICATES]] {{[0-9]+}} +; CHECK-SPIRV: Variable {{[0-9]+}} [[#SIMPLE_DUAL_PORT]] {{[0-9]+}} +; CHECK-SPIRV: Variable {{[0-9]+}} [[#MERGE]] {{[0-9]+}} +; CHECK-SPIRV: Variable {{[0-9]+}} [[#BANKBITS]] {{[0-9]+}} +; CHECK-SPIRV: Variable {{[0-9]+}} [[#FORCE_POW_2_DEPTH]] {{[0-9]+}} +; CHECK-SPIRV: Variable {{[0-9]+}} [[#STRIDESIZE]] {{[0-9]+}} +; CHECK-SPIRV: Variable {{[0-9]+}} [[#WORDSIZE]] {{[0-9]+}} +; CHECK-SPIRV: Variable {{[0-9]+}} [[#TRUE_DUAL_PORT]] {{[0-9]+}} + +; CHECK-LLVM: [[REGISTER:@[0-9_.]+]] = {{.*}}{register:1} +; CHECK-LLVM: [[MEMORY:@[0-9_.]+]] = {{.*}}{memory:DEFAULT} +; CHECK-LLVM: [[NUMBANKS:@[0-9_.]+]] = {{.*}}{numbanks:4} +; CHECK-LLVM: [[BANKWIDTH:@[0-9_.]+]] = {{.*}}{bankwidth:4} +; CHECK-LLVM: [[MAX_PRIVATE_COPIES:@[0-9_.]+]] = {{.*}}{private_copies:1} +; CHECK-LLVM: [[SINGLEPUMP:@[0-9_.]+]] = {{.*}}{pump:1} +; CHECK-LLVM: [[DOUBLEPUMP:@[0-9_.]+]] = {{.*}}{pump:2} +; CHECK-LLVM: [[MAX_REPLICATES:@[0-9_.]+]] = {{.*}}{max_replicates:2} +; CHECK-LLVM: [[SIMPLE_DUAL_PORT:@[0-9_.]+]] = {{.*}}{simple_dual_port:1} +; CHECK-LLVM: [[MERGE:@[0-9_.]+]] = {{.*}}{merge:key:type} +; CHECK-LLVM: [[BANK_BITS:@[0-9_.]+]] = {{.*}}{bank_bits:2} +; CHECK-LLVM: [[FORCE_POW_2_DEPTH:@[0-9_.]+]] = {{.*}}{force_pow2_depth:2} +; CHECK-LLVM: [[STRIDESIZE:@[0-9_.]+]] = {{.*}}{stride_size:4} +; CHECK-LLVM: [[WORDSIZE:@[0-9_.]+]] = {{.*}}{word_size:8} +; CHECK-LLVM: [[TRUE_DUAL_PORT:@[0-9_.]+]] = {{.*}}{true_dual_port:1} +; CHECK-LLVM: call ptr @llvm.ptr.annotation.p0.p0(ptr %{{[a-zA-Z0-9_]+}}, ptr [[REGISTER]], ptr undef, i32 undef, ptr undef) +; CHECK-LLVM: call ptr @llvm.ptr.annotation.p0.p0(ptr %{{[a-zA-Z0-9_]+}}, ptr [[MEMORY]], ptr undef, i32 undef, ptr undef) +; CHECK-LLVM: call ptr @llvm.ptr.annotation.p0.p0(ptr %{{[a-zA-Z0-9_]+}}, ptr [[NUMBANKS]], ptr undef, i32 undef, ptr undef) +; CHECK-LLVM: call ptr @llvm.ptr.annotation.p0.p0(ptr %{{[a-zA-Z0-9_]+}}, ptr [[BANKWIDTH]], ptr undef, i32 undef, ptr undef) +; CHECK-LLVM: call ptr @llvm.ptr.annotation.p0.p0(ptr %{{[a-zA-Z0-9_]+}}, ptr [[MAX_PRIVATE_COPIES]], ptr undef, i32 undef, ptr undef) +; CHECK-LLVM: call ptr @llvm.ptr.annotation.p0.p0(ptr %{{[a-zA-Z0-9_]+}}, ptr [[SINGLEPUMP]], ptr undef, i32 undef, ptr undef) +; CHECK-LLVM: call ptr @llvm.ptr.annotation.p0.p0(ptr %{{[a-zA-Z0-9_]+}}, ptr [[DOUBLEPUMP]], ptr undef, i32 undef, ptr undef) +; CHECK-LLVM: call ptr @llvm.ptr.annotation.p0.p0(ptr %{{[a-zA-Z0-9_]+}}, ptr [[MAX_REPLICATES]], ptr undef, i32 undef, ptr undef) +; CHECK-LLVM: call ptr @llvm.ptr.annotation.p0.p0(ptr %{{[a-zA-Z0-9_]+}}, ptr [[SIMPLE_DUAL_PORT]], ptr undef, i32 undef, ptr undef) +; CHECK-LLVM: call ptr @llvm.ptr.annotation.p0.p0(ptr %{{[a-zA-Z0-9_]+}}, ptr [[MERGE]], ptr undef, i32 undef, ptr undef) +; CHECK-LLVM: call ptr @llvm.ptr.annotation.p0.p0(ptr %{{[a-zA-Z0-9_]+}}, ptr [[BANK_BITS]], ptr undef, i32 undef, ptr undef) +; CHECK-LLVM: call ptr @llvm.ptr.annotation.p0.p0(ptr %{{[a-zA-Z0-9_]+}}, ptr [[FORCE_POW_2_DEPTH]], ptr undef, i32 undef, ptr undef) +; CHECK-LLVM: call ptr @llvm.ptr.annotation.p0.p0(ptr %{{[a-zA-Z0-9_]+}}, ptr [[STRIDESIZE]], ptr undef, i32 undef, ptr undef) +; CHECK-LLVM: call ptr @llvm.ptr.annotation.p0.p0(ptr %{{[a-zA-Z0-9_]+}}, ptr [[WORDSIZE]], ptr undef, i32 undef, ptr undef) +; CHECK-LLVM: call ptr @llvm.ptr.annotation.p0.p0(ptr %{{[a-zA-Z0-9_]+}}, ptr [[TRUE_DUAL_PORT]], ptr undef, i32 undef, ptr undef) + +%"register_type" = type { i32 } +%"memory_type" = type { i32 } +%"numbanks_type" = type { i32 } +%"bankwidth_type" = type { i32 } +%"max_private_copies_type" = type { i32 } +%"singlepump_type" = type { i32 } +%"doublepump_type" = type { i32 } +%"max_replicates_type" = type { i32 } +%"simple_dual_port_type" = type { i32 } +%"merge_type" = type { i32 } +%"bankbits_type" = type { i32 } +%"force_pow_2_depth_type" = type { i32 } +%"stride_size_type" = type { i32 } +%"word_size_type" = type { i32 } +%"true_dual_port_type" = type { i32 } + +@register_attr = private unnamed_addr addrspace(1) constant [7 x i8] c"{5825}\00", section "llvm.metadata" +@memory_attr = private unnamed_addr addrspace(1) constant [15 x i8] c"{5826:DEFAULT}\00", section "llvm.metadata" +@numbanks_attr = private unnamed_addr addrspace(1) constant [9 x i8] c"{5827:4}\00", section "llvm.metadata" +@bankwidth_attr = private unnamed_addr addrspace(1) constant [9 x i8] c"{5828:4}\00", section "llvm.metadata" +@max_private_copies_attr = private unnamed_addr addrspace(1) constant [9 x i8] c"{5829:1}\00", section "llvm.metadata" +@singlepump_attr = private unnamed_addr addrspace(1) constant [7 x i8] c"{5830}\00", section "llvm.metadata" +@doublepump_attr = private unnamed_addr addrspace(1) constant [7 x i8] c"{5831}\00", section "llvm.metadata" +@max_replicates_attr = private unnamed_addr addrspace(1) constant [9 x i8] c"{5832:2}\00", section "llvm.metadata" +@simple_dual_port_attr = private unnamed_addr addrspace(1) constant [7 x i8] c"{5833}\00", section "llvm.metadata" +@merge_attr = private unnamed_addr addrspace(1) constant [16 x i8] c"{5834:key,type}\00", section "llvm.metadata" +@bankbits_attr = private unnamed_addr addrspace(1) constant [9 x i8] c"{5835:2}\00", section "llvm.metadata" +@force_pow_2_depth_attr = private unnamed_addr addrspace(1) constant [9 x i8] c"{5836:2}\00", section "llvm.metadata" +@stride_size_attr = private unnamed_addr addrspace(1) constant [9 x i8] c"{5883:4}\00", section "llvm.metadata" +@word_size_attr = private unnamed_addr addrspace(1) constant [9 x i8] c"{5884:8}\00", section "llvm.metadata" +@true_dual_port_attr = private unnamed_addr addrspace(1) constant [7 x i8] c"{5885}\00", section "llvm.metadata" + +define spir_func void @test_fpga_register_attr() { entry: - %0 = alloca %class.anon, align 1 - %1 = bitcast %class.anon* %0 to i8* - call void @llvm.lifetime.start.p0i8(i64 1, i8* %1) #5 - call spir_func void @"_ZZ4mainENK3$_0clEv"(%class.anon* %0) - %2 = bitcast %class.anon* %0 to i8* - call void @llvm.lifetime.end.p0i8(i64 1, i8* %2) #5 + %0 = alloca %"register_type", align 4 + %1 = addrspacecast ptr %0 to ptr addrspace(4) + %2 = call ptr addrspace(4) @llvm.ptr.annotation.p4.p1(ptr addrspace(4) %1, ptr addrspace(1) @register_attr, ptr addrspace(1) null, i32 0, ptr addrspace(1) null) ret void } -; Function Attrs: argmemonly nounwind willreturn -declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture) #1 - -; Function Attrs: inlinehint norecurse nounwind -define internal spir_func void @"_ZZ4mainENK3$_0clEv"(%class.anon* %this) #2 align 2 { +define spir_func void @test_fpga_memory_attr() { entry: - %this.addr = alloca %class.anon*, align 4 - store %class.anon* %this, %class.anon** %this.addr, align 4, !tbaa !5 - %this1 = load %class.anon*, %class.anon** %this.addr, align 4 - call spir_func void @_Z19field_numbanks_attrv() - call spir_func void @_Z25templ_field_numbanks_attrILi8EEvv() - call spir_func void @_Z19field_register_attrv() - call spir_func void @_Z17field_memory_attrv() - call spir_func void @_Z20field_bankwidth_attrv() - call spir_func void @_Z26templ_field_bankwidth_attrILi4EEvv() - call spir_func void @_Z25field_private_copies_attrv() - call spir_func void @_Z31templ_field_private_copies_attrILi2EEvv() - call spir_func void @_Z21field_singlepump_attrv() - call spir_func void @_Z21field_doublepump_attrv() - call spir_func void @_Z16field_merge_attrv() - call spir_func void @_Z25field_max_replicates_attrv() - call spir_func void @_Z31templ_field_max_replicates_attrILi2EEvv() - call spir_func void @_Z27field_simple_dual_port_attrv() - call spir_func void @_Z20field_bank_bits_attrv() - call spir_func void @_Z26templ_field_bank_bits_attrILi2ELi3EEvv() - call spir_func void @_Z27field_force_pow2_depth_attrv() - call spir_func void @_Z33templ_field_force_pow2_depth_attrILi1EEvv() - call spir_func void @_Z20field_addrspace_castv() + %0 = alloca %"memory_type", align 4 + %1 = addrspacecast ptr %0 to ptr addrspace(4) + %2 = call ptr addrspace(4) @llvm.ptr.annotation.p4.p1(ptr addrspace(4) %1, ptr addrspace(1) @memory_attr, ptr addrspace(1) null, i32 0, ptr addrspace(1) null) ret void } -; Function Attrs: argmemonly nounwind willreturn -declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture) #1 - -; Function Attrs: norecurse nounwind -define spir_func void @_Z19field_numbanks_attrv() #3 { +define spir_func void @test_fpga_numbanks_attr() { entry: - %s = alloca %struct.numbanks_st, align 4 - %0 = bitcast %struct.numbanks_st* %s to i8* - call void @llvm.lifetime.start.p0i8(i64 4, i8* %0) #5 - ; CHECK-LLVM: %[[FLD_NMB_SCT:.*]] = getelementptr inbounds %struct.numbanks_st, ptr %{{[a-zA-Z0-9]+}}, i32 0, i32 0 - ; CHECK-LLVM: %[[PTR_NMB_SCT:.*]] = call ptr @llvm.ptr.annotation.p0{{.*}}%[[FLD_NMB_SCT]]{{.*}}[[STR_NMB_SCT]] - ; CHECK-LLVM: call ptr @llvm.ptr.annotation.p0{{.*}}%[[PTR_NMB_SCT]]{{.*}}[[STR_SIZEINF]] - %field = getelementptr inbounds %struct.numbanks_st, %struct.numbanks_st* %s, i32 0, i32 0 - %1 = call i32* @llvm.ptr.annotation.p0i32(i32* %field, i8* getelementptr inbounds ([41 x i8], [41 x i8]* @.str, i32 0, i32 0), i8* getelementptr inbounds ([28 x i8], [28 x i8]* @.str.1, i32 0, i32 0), i32 3, i8* null) - store i32 0, i32* %1, align 4, !tbaa !9 - %2 = bitcast %struct.numbanks_st* %s to i8* - call void @llvm.lifetime.end.p0i8(i64 4, i8* %2) #5 + %0 = alloca %"numbanks_type", align 4 + %1 = addrspacecast ptr %0 to ptr addrspace(4) + %2 = call ptr addrspace(4) @llvm.ptr.annotation.p4.p1(ptr addrspace(4) %1, ptr addrspace(1) @numbanks_attr, ptr addrspace(1) null, i32 0, ptr addrspace(1) null) ret void } -; Function Attrs: norecurse nounwind -define linkonce_odr spir_func void @_Z25templ_field_numbanks_attrILi8EEvv() #3 { +define spir_func void @test_fpga_bankwidth_attr() { entry: - %s = alloca %struct.templ_numbanks_st, align 4 - %0 = bitcast %struct.templ_numbanks_st* %s to i8* - call void @llvm.lifetime.start.p0i8(i64 4, i8* %0) #5 - ; CHECK-LLVM: %[[FLD_NMB_STE:.*]] = getelementptr inbounds %struct.templ_numbanks_st, ptr %{{[a-zA-Z0-9]+}}, i32 0, i32 0 - ; CHECK-LLVM: call ptr @llvm.ptr.annotation.p0{{.*}}%[[FLD_NMB_STE]]{{.*}}[[STR_NMB_STE]] - %field = getelementptr inbounds %struct.templ_numbanks_st, %struct.templ_numbanks_st* %s, i32 0, i32 0 - %1 = call i32* @llvm.ptr.annotation.p0i32(i32* %field, i8* getelementptr inbounds ([41 x i8], [41 x i8]* @.str.2, i32 0, i32 0), i8* getelementptr inbounds ([28 x i8], [28 x i8]* @.str.1, i32 0, i32 0), i32 11, i8* null) - store i32 0, i32* %1, align 4, !tbaa !13 - %2 = bitcast %struct.templ_numbanks_st* %s to i8* - call void @llvm.lifetime.end.p0i8(i64 4, i8* %2) #5 + %0 = alloca %"bankwidth_type", align 4 + %1 = addrspacecast ptr %0 to ptr addrspace(4) + %2 = call ptr addrspace(4) @llvm.ptr.annotation.p4.p1(ptr addrspace(4) %1, ptr addrspace(1) @bankwidth_attr, ptr addrspace(1) null, i32 0, ptr addrspace(1) null) ret void } -; Function Attrs: norecurse nounwind -define spir_func void @_Z19field_register_attrv() #3 { +define spir_func void @test_fpga_max_private_copies_attr() { entry: - %s = alloca %struct.register_st, align 4 - %0 = bitcast %struct.register_st* %s to i8* - call void @llvm.lifetime.start.p0i8(i64 4, i8* %0) #5 - ; CHECK-LLVM: %[[FLD_REG_SCT:.*]] = getelementptr inbounds %struct.register_st, ptr %{{[a-zA-Z0-9]+}}, i32 0, i32 0 - ; CHECK-LLVM: call ptr @llvm.ptr.annotation.p0{{.*}}%[[FLD_REG_SCT]]{{.*}}[[STR_REG_SCT]] - %field = getelementptr inbounds %struct.register_st, %struct.register_st* %s, i32 0, i32 0 - %1 = call i32* @llvm.ptr.annotation.p0i32(i32* %field, i8* getelementptr inbounds ([13 x i8], [13 x i8]* @.str.3, i32 0, i32 0), i8* getelementptr inbounds ([28 x i8], [28 x i8]* @.str.1, i32 0, i32 0), i32 18, i8* null) - store i32 0, i32* %1, align 4, !tbaa !15 - %2 = bitcast %struct.register_st* %s to i8* - call void @llvm.lifetime.end.p0i8(i64 4, i8* %2) #5 + %0 = alloca %"max_private_copies_type", align 4 + %1 = addrspacecast ptr %0 to ptr addrspace(4) + %2 = call ptr addrspace(4) @llvm.ptr.annotation.p4.p1(ptr addrspace(4) %1, ptr addrspace(1) @max_private_copies_attr, ptr addrspace(1) null, i32 0, ptr addrspace(1) null) ret void } -; Function Attrs: norecurse nounwind -define spir_func void @_Z17field_memory_attrv() #3 { +define spir_func void @test_fpga_singlepump_attr() { entry: - %s = alloca %struct.memory_st, align 4 - %0 = bitcast %struct.memory_st* %s to i8* - call void @llvm.lifetime.start.p0i8(i64 4, i8* %0) #5 - ; CHECK-LLVM: %[[FLD_MEM_SCT:.*]] = getelementptr inbounds %struct.memory_st, ptr %{{[a-zA-Z0-9]+}}, i32 0, i32 0 - ; CHECK-LLVM: call ptr @llvm.ptr.annotation.p0{{.*}}%[[FLD_MEM_SCT]]{{.*}}[[STR_MEM_SCT]] - %field = getelementptr inbounds %struct.memory_st, %struct.memory_st* %s, i32 0, i32 0 - %1 = call i32* @llvm.ptr.annotation.p0i32(i32* %field, i8* getelementptr inbounds ([26 x i8], [26 x i8]* @.str.4, i32 0, i32 0), i8* getelementptr inbounds ([28 x i8], [28 x i8]* @.str.1, i32 0, i32 0), i32 25, i8* null) - store i32 0, i32* %1, align 4, !tbaa !17 - %2 = bitcast %struct.memory_st* %s to i8* - call void @llvm.lifetime.end.p0i8(i64 4, i8* %2) #5 + %0 = alloca %"singlepump_type", align 4 + %1 = addrspacecast ptr %0 to ptr addrspace(4) + %2 = call ptr addrspace(4) @llvm.ptr.annotation.p4.p1(ptr addrspace(4) %1, ptr addrspace(1) @singlepump_attr, ptr addrspace(1) null, i32 0, ptr addrspace(1) null) ret void } -; Function Attrs: norecurse nounwind -define spir_func void @_Z20field_bankwidth_attrv() #3 { +define spir_func void @test_fpga_doublepump_attr() { entry: - %s = alloca %struct.bankwidth_st, align 4 - %0 = bitcast %struct.bankwidth_st* %s to i8* - call void @llvm.lifetime.start.p0i8(i64 4, i8* %0) #5 - %field = getelementptr inbounds %struct.bankwidth_st, %struct.bankwidth_st* %s, i32 0, i32 0 - ; CHECK-LLVM: %[[FLD_BWD_SCT:.*]] = getelementptr inbounds %struct.bankwidth_st, ptr %{{[a-zA-Z0-9]+}}, i32 0, i32 0 - ; CHECK-LLVM: call ptr @llvm.ptr.annotation.p0{{.*}}%[[FLD_BWD_SCT]]{{.*}}[[STR_BWD_SCT]] - %1 = call i32* @llvm.ptr.annotation.p0i32(i32* %field, i8* getelementptr inbounds ([42 x i8], [42 x i8]* @.str.5, i32 0, i32 0), i8* getelementptr inbounds ([28 x i8], [28 x i8]* @.str.1, i32 0, i32 0), i32 32, i8* null) - store i32 0, i32* %1, align 4, !tbaa !19 - %2 = bitcast %struct.bankwidth_st* %s to i8* - call void @llvm.lifetime.end.p0i8(i64 4, i8* %2) #5 + %0 = alloca %"doublepump_type", align 4 + %1 = addrspacecast ptr %0 to ptr addrspace(4) + %2 = call ptr addrspace(4) @llvm.ptr.annotation.p4.p1(ptr addrspace(4) %1, ptr addrspace(1) @doublepump_attr, ptr addrspace(1) null, i32 0, ptr addrspace(1) null) ret void } -; Function Attrs: norecurse nounwind -define linkonce_odr spir_func void @_Z26templ_field_bankwidth_attrILi4EEvv() #3 { +define spir_func void @test_fpga_max_replicates_attr() { entry: - %s = alloca %struct.templ_bankwidth_st, align 4 - %0 = bitcast %struct.templ_bankwidth_st* %s to i8* - call void @llvm.lifetime.start.p0i8(i64 4, i8* %0) #5 - ; CHECK-LLVM: %[[FLD_BWD_STE:.*]] = getelementptr inbounds %struct.templ_bankwidth_st, ptr %{{[a-zA-Z0-9]+}}, i32 0, i32 0 - ; CHECK-LLVM: call ptr @llvm.ptr.annotation.p0{{.*}}%[[FLD_BWD_STE]]{{.*}}[[STR_BWD_STE]] - %field = getelementptr inbounds %struct.templ_bankwidth_st, %struct.templ_bankwidth_st* %s, i32 0, i32 0 - %1 = call i32* @llvm.ptr.annotation.p0i32(i32* %field, i8* getelementptr inbounds ([42 x i8], [42 x i8]* @.str.6, i32 0, i32 0), i8* getelementptr inbounds ([28 x i8], [28 x i8]* @.str.1, i32 0, i32 0), i32 40, i8* null) - store i32 0, i32* %1, align 4, !tbaa !21 - %2 = bitcast %struct.templ_bankwidth_st* %s to i8* - call void @llvm.lifetime.end.p0i8(i64 4, i8* %2) #5 + %0 = alloca %"max_replicates_type", align 4 + %1 = addrspacecast ptr %0 to ptr addrspace(4) + %2 = call ptr addrspace(4) @llvm.ptr.annotation.p4.p1(ptr addrspace(4) %1, ptr addrspace(1) @max_replicates_attr, ptr addrspace(1) null, i32 0, ptr addrspace(1) null) ret void } -; Function Attrs: norecurse nounwind -define spir_func void @_Z25field_private_copies_attrv() #3 { +define spir_func void @test_fpga_simple_dual_port_attr() { entry: - %s = alloca %struct.private_copies_st, align 4 - %0 = bitcast %struct.private_copies_st* %s to i8* - call void @llvm.lifetime.start.p0i8(i64 4, i8* %0) #5 - ; CHECK-LLVM: %[[FLD_PRC_SCT:.*]] = getelementptr inbounds %struct.private_copies_st, ptr %{{[a-zA-Z0-9]+}}, i32 0, i32 0 - ; CHECK-LLVM: call ptr @llvm.ptr.annotation.p0{{.*}}%[[FLD_PRC_SCT]]{{.*}}[[STR_PRC_SCT]] - %field = getelementptr inbounds %struct.private_copies_st, %struct.private_copies_st* %s, i32 0, i32 0 - %1 = call i32* @llvm.ptr.annotation.p0i32(i32* %field, i8* getelementptr inbounds ([47 x i8], [47 x i8]* @.str.7, i32 0, i32 0), i8* getelementptr inbounds ([28 x i8], [28 x i8]* @.str.1, i32 0, i32 0), i32 47, i8* null) - store i32 0, i32* %1, align 4, !tbaa !23 - %2 = bitcast %struct.private_copies_st* %s to i8* - call void @llvm.lifetime.end.p0i8(i64 4, i8* %2) #5 + %0 = alloca %"simple_dual_port_type", align 4 + %1 = addrspacecast ptr %0 to ptr addrspace(4) + %2 = call ptr addrspace(4) @llvm.ptr.annotation.p4.p1(ptr addrspace(4) %1, ptr addrspace(1) @simple_dual_port_attr, ptr addrspace(1) null, i32 0, ptr addrspace(1) null) ret void } - -; Function Attrs: norecurse nounwind -define linkonce_odr spir_func void @_Z31templ_field_private_copies_attrILi2EEvv() #3 { +define spir_func void @test_fpga_merge_attr() { entry: - %s = alloca %struct.templ_private_copies_st, align 4 - %0 = bitcast %struct.templ_private_copies_st* %s to i8* - call void @llvm.lifetime.start.p0i8(i64 4, i8* %0) #5 - ; CHECK-LLVM: %[[FLD_PRC_STE:.*]] = getelementptr inbounds %struct.templ_private_copies_st, ptr %{{[a-zA-Z0-9]+}}, i32 0, i32 0 - ; CHECK-LLVM: call ptr @llvm.ptr.annotation.p0{{.*}}%[[FLD_PRC_STE]]{{.*}}[[STR_PRC_STE]] - %field = getelementptr inbounds %struct.templ_private_copies_st, %struct.templ_private_copies_st* %s, i32 0, i32 0 - %1 = call i32* @llvm.ptr.annotation.p0i32(i32* %field, i8* getelementptr inbounds ([47 x i8], [47 x i8]* @.str.8, i32 0, i32 0), i8* getelementptr inbounds ([28 x i8], [28 x i8]* @.str.1, i32 0, i32 0), i32 55, i8* null) - store i32 0, i32* %1, align 4, !tbaa !25 - %2 = bitcast %struct.templ_private_copies_st* %s to i8* - call void @llvm.lifetime.end.p0i8(i64 4, i8* %2) #5 + %0 = alloca %"merge_type", align 4 + %1 = addrspacecast ptr %0 to ptr addrspace(4) + %2 = call ptr addrspace(4) @llvm.ptr.annotation.p4.p1(ptr addrspace(4) %1, ptr addrspace(1) @merge_attr, ptr addrspace(1) null, i32 0, ptr addrspace(1) null) ret void } -; Function Attrs: norecurse nounwind -define spir_func void @_Z21field_singlepump_attrv() #3 { +define spir_func void @test_fpga_bankbits_attr() { entry: - %s = alloca %struct.singlepump_st, align 4 - %0 = bitcast %struct.singlepump_st* %s to i8* - call void @llvm.lifetime.start.p0i8(i64 4, i8* %0) #5 - ; CHECK-LLVM: %[[FLD_SNP_SCT:.*]] = getelementptr inbounds %struct.singlepump_st, ptr %{{[a-zA-Z0-9]+}}, i32 0, i32 0 - ; CHECK-LLVM: call ptr @llvm.ptr.annotation.p0{{.*}}%[[FLD_SNP_SCT]]{{.*}}[[STR_SNP_SCT]] - %field = getelementptr inbounds %struct.singlepump_st, %struct.singlepump_st* %s, i32 0, i32 0 - %1 = call i32* @llvm.ptr.annotation.p0i32(i32* %field, i8* getelementptr inbounds ([37 x i8], [37 x i8]* @.str.9, i32 0, i32 0), i8* getelementptr inbounds ([28 x i8], [28 x i8]* @.str.1, i32 0, i32 0), i32 62, i8* null) - store i32 0, i32* %1, align 4, !tbaa !27 - %2 = bitcast %struct.singlepump_st* %s to i8* - call void @llvm.lifetime.end.p0i8(i64 4, i8* %2) #5 + %0 = alloca %"bankbits_type", align 4 + %1 = addrspacecast ptr %0 to ptr addrspace(4) + %2 = call ptr addrspace(4) @llvm.ptr.annotation.p4.p1(ptr addrspace(4) %1, ptr addrspace(1) @bankbits_attr, ptr addrspace(1) null, i32 0, ptr addrspace(1) null) ret void } -; Function Attrs: norecurse nounwind -define spir_func void @_Z21field_doublepump_attrv() #3 { +define spir_func void @test_fpga_force_pow_2_depth_attr() { entry: - %s = alloca %struct.doublepump_st, align 4 - %0 = bitcast %struct.doublepump_st* %s to i8* - call void @llvm.lifetime.start.p0i8(i64 4, i8* %0) #5 - ; CHECK-LLVM: %[[FLD_DBP_SCT:.*]] = getelementptr inbounds %struct.doublepump_st, ptr %{{[a-zA-Z0-9]+}}, i32 0, i32 0 - ; CHECK-LLVM: call ptr @llvm.ptr.annotation.p0{{.*}}%[[FLD_DBP_SCT]]{{.*}}[[STR_DBP_SCT]] - %field = getelementptr inbounds %struct.doublepump_st, %struct.doublepump_st* %s, i32 0, i32 0 - %1 = call i32* @llvm.ptr.annotation.p0i32(i32* %field, i8* getelementptr inbounds ([37 x i8], [37 x i8]* @.str.10, i32 0, i32 0), i8* getelementptr inbounds ([28 x i8], [28 x i8]* @.str.1, i32 0, i32 0), i32 69, i8* null) - store i32 0, i32* %1, align 4, !tbaa !29 - %2 = bitcast %struct.doublepump_st* %s to i8* - call void @llvm.lifetime.end.p0i8(i64 4, i8* %2) #5 + %0 = alloca %"force_pow_2_depth_type", align 4 + %1 = addrspacecast ptr %0 to ptr addrspace(4) + %2 = call ptr addrspace(4) @llvm.ptr.annotation.p4.p1(ptr addrspace(4) %1, ptr addrspace(1) @force_pow_2_depth_attr, ptr addrspace(1) null, i32 0, ptr addrspace(1) null) ret void } -; Function Attrs: norecurse nounwind -define spir_func void @_Z16field_merge_attrv() #3 { +define spir_func void @test_fpga_stride_size_attr() { entry: - %s = alloca %struct.merge_st, align 4 - %0 = bitcast %struct.merge_st* %s to i8* - call void @llvm.lifetime.start.p0i8(i64 4, i8* %0) #5 - ; CHECK-LLVM: %[[FLD_MRG_SCT:.*]] = getelementptr inbounds %struct.merge_st, ptr %{{[a-zA-Z0-9]+}}, i32 0, i32 0 - ; CHECK-LLVM: call ptr @llvm.ptr.annotation.p0{{.*}}%[[FLD_MRG_SCT]]{{.*}}[[STR_MRG_SCT]] - %field = getelementptr inbounds %struct.merge_st, %struct.merge_st* %s, i32 0, i32 0 - %1 = call i32* @llvm.ptr.annotation.p0i32(i32* %field, i8* getelementptr inbounds ([49 x i8], [49 x i8]* @.str.11, i32 0, i32 0), i8* getelementptr inbounds ([28 x i8], [28 x i8]* @.str.1, i32 0, i32 0), i32 76, i8* null) - store i32 0, i32* %1, align 4, !tbaa !31 - %2 = bitcast %struct.merge_st* %s to i8* - call void @llvm.lifetime.end.p0i8(i64 4, i8* %2) #5 + %0 = alloca %"stride_size_type", align 4 + %1 = addrspacecast ptr %0 to ptr addrspace(4) + %2 = call ptr addrspace(4) @llvm.ptr.annotation.p4.p1(ptr addrspace(4) %1, ptr addrspace(1) @stride_size_attr, ptr addrspace(1) null, i32 0, ptr addrspace(1) null) ret void } -; Function Attrs: norecurse nounwind -define spir_func void @_Z25field_max_replicates_attrv() #3 { +define spir_func void @test_fpga_word_size_attr() { entry: - %s = alloca %struct.max_replicates_st, align 4 - %0 = bitcast %struct.max_replicates_st* %s to i8* - call void @llvm.lifetime.start.p0i8(i64 4, i8* %0) #5 - ; CHECK-LLVM: %[[FLD_MXR_SCT:.*]] = getelementptr inbounds %struct.max_replicates_st, ptr %{{[a-zA-Z0-9]+}}, i32 0, i32 0 - ; CHECK-LLVM: call ptr @llvm.ptr.annotation.p0{{.*}}%[[FLD_MXR_SCT]]{{.*}}[[STR_MXR_SCT]] - %field = getelementptr inbounds %struct.max_replicates_st, %struct.max_replicates_st* %s, i32 0, i32 0 - %1 = call i32* @llvm.ptr.annotation.p0i32(i32* %field, i8* getelementptr inbounds ([19 x i8], [19 x i8]* @.str.12, i32 0, i32 0), i8* getelementptr inbounds ([28 x i8], [28 x i8]* @.str.1, i32 0, i32 0), i32 83, i8* null) - store i32 0, i32* %1, align 4, !tbaa !33 - %2 = bitcast %struct.max_replicates_st* %s to i8* - call void @llvm.lifetime.end.p0i8(i64 4, i8* %2) #5 + %0 = alloca %"word_size_type", align 4 + %1 = addrspacecast ptr %0 to ptr addrspace(4) + %2 = call ptr addrspace(4) @llvm.ptr.annotation.p4.p1(ptr addrspace(4) %1, ptr addrspace(1) @word_size_attr, ptr addrspace(1) null, i32 0, ptr addrspace(1) null) ret void } -; Function Attrs: norecurse nounwind -define linkonce_odr spir_func void @_Z31templ_field_max_replicates_attrILi2EEvv() #3 { +define spir_func void @test_fpga_true_dual_port_attr() { entry: - %s = alloca %struct.templ_max_replicates_st, align 4 - %0 = bitcast %struct.templ_max_replicates_st* %s to i8* - call void @llvm.lifetime.start.p0i8(i64 4, i8* %0) #5 - ; CHECK-LLVM: %[[FLD_MXR_STE:.*]] = getelementptr inbounds %struct.templ_max_replicates_st, ptr %{{[a-zA-Z0-9]+}}, i32 0, i32 0 - ; CHECK-LLVM: call ptr @llvm.ptr.annotation.p0{{.*}}%[[FLD_MXR_STE]]{{.*}}[[STR_MXR_STE]] - %field = getelementptr inbounds %struct.templ_max_replicates_st, %struct.templ_max_replicates_st* %s, i32 0, i32 0 - %1 = call i32* @llvm.ptr.annotation.p0i32(i32* %field, i8* getelementptr inbounds ([19 x i8], [19 x i8]* @.str.13, i32 0, i32 0), i8* getelementptr inbounds ([28 x i8], [28 x i8]* @.str.1, i32 0, i32 0), i32 91, i8* null) - store i32 0, i32* %1, align 4, !tbaa !35 - %2 = bitcast %struct.templ_max_replicates_st* %s to i8* - call void @llvm.lifetime.end.p0i8(i64 4, i8* %2) #5 + %0 = alloca %"true_dual_port_type", align 4 + %1 = addrspacecast ptr %0 to ptr addrspace(4) + %2 = call ptr addrspace(4) @llvm.ptr.annotation.p4.p1(ptr addrspace(4) %1, ptr addrspace(1) @true_dual_port_attr, ptr addrspace(1) null, i32 0, ptr addrspace(1) null) ret void } -; Function Attrs: norecurse nounwind -define spir_func void @_Z27field_simple_dual_port_attrv() #3 { -entry: - %s = alloca %struct.simple_dual_port_st, align 4 - %0 = bitcast %struct.simple_dual_port_st* %s to i8* - call void @llvm.lifetime.start.p0i8(i64 4, i8* %0) #5 - ; CHECK-LLVM: %[[FLD_SDP_SCT:.*]] = getelementptr inbounds %struct.simple_dual_port_st, ptr %{{[a-zA-Z0-9]+}}, i32 0, i32 0 - ; CHECK-LLVM: call ptr @llvm.ptr.annotation.p0{{.*}}%[[FLD_SDP_SCT]]{{.*}}[[STR_SDP_SCT]] - %field = getelementptr inbounds %struct.simple_dual_port_st, %struct.simple_dual_port_st* %s, i32 0, i32 0 - %1 = call i32* @llvm.ptr.annotation.p0i32(i32* %field, i8* getelementptr inbounds ([49 x i8], [49 x i8]* @.str.14, i32 0, i32 0), i8* getelementptr inbounds ([28 x i8], [28 x i8]* @.str.1, i32 0, i32 0), i32 98, i8* null) - store i32 0, i32* %1, align 4, !tbaa !37 - %2 = bitcast %struct.simple_dual_port_st* %s to i8* - call void @llvm.lifetime.end.p0i8(i64 4, i8* %2) #5 - ret void -} - -; Function Attrs: norecurse nounwind -define spir_func void @_Z20field_bank_bits_attrv() #3 { -entry: - %s = alloca %struct.bank_bits_st, align 4 - %0 = bitcast %struct.bank_bits_st* %s to i8* - call void @llvm.lifetime.start.p0i8(i64 4, i8* %0) #5 - ; CHECK-LLVM: %[[FLD_BBT_SCT:.*]] = getelementptr inbounds %struct.bank_bits_st, ptr %{{[a-zA-Z0-9]+}}, i32 0, i32 0 - ; CHECK-LLVM: call ptr @llvm.ptr.annotation.p0{{.*}}%[[FLD_BBT_SCT]]{{.*}}[[STR_BBT_SCT]] - %field = getelementptr inbounds %struct.bank_bits_st, %struct.bank_bits_st* %s, i32 0, i32 0 - %1 = call i32* @llvm.ptr.annotation.p0i32(i32* %field, i8* getelementptr inbounds ([61 x i8], [61 x i8]* @.str.15, i32 0, i32 0), i8* getelementptr inbounds ([28 x i8], [28 x i8]* @.str.1, i32 0, i32 0), i32 105, i8* null) - store i32 0, i32* %1, align 4, !tbaa !39 - %2 = bitcast %struct.bank_bits_st* %s to i8* - call void @llvm.lifetime.end.p0i8(i64 4, i8* %2) #5 - ret void -} - -; Function Attrs: norecurse nounwind -define linkonce_odr spir_func void @_Z26templ_field_bank_bits_attrILi2ELi3EEvv() #3 { -entry: - %s = alloca %struct.templ_bank_bits_st, align 4 - %0 = bitcast %struct.templ_bank_bits_st* %s to i8* - call void @llvm.lifetime.start.p0i8(i64 4, i8* %0) #5 - ; CHECK-LLVM: %[[FLD_BBT_STE:.*]] = getelementptr inbounds %struct.templ_bank_bits_st, ptr %{{[a-zA-Z0-9]+}}, i32 0, i32 0 - ; CHECK-LLVM: call ptr @llvm.ptr.annotation.p0{{.*}}%[[FLD_BBT_STE]]{{.*}}[[STR_BBT_STE]] - %field = getelementptr inbounds %struct.templ_bank_bits_st, %struct.templ_bank_bits_st* %s, i32 0, i32 0 - %1 = call i32* @llvm.ptr.annotation.p0i32(i32* %field, i8* getelementptr inbounds ([56 x i8], [56 x i8]* @.str.16, i32 0, i32 0), i8* getelementptr inbounds ([28 x i8], [28 x i8]* @.str.1, i32 0, i32 0), i32 113, i8* null) - store i32 0, i32* %1, align 4, !tbaa !41 - %2 = bitcast %struct.templ_bank_bits_st* %s to i8* - call void @llvm.lifetime.end.p0i8(i64 4, i8* %2) #5 - ret void -} - -; Function Attrs: norecurse nounwind -define spir_func void @_Z27field_force_pow2_depth_attrv() #3 { -entry: - %s = alloca %struct.force_pow2_depth_st, align 4 - %0 = bitcast %struct.force_pow2_depth_st* %s to i8* - call void @llvm.lifetime.start.p0i8(i64 4, i8* %0) #5 - ; CHECK-LLVM: %[[FLD_FP2_SCT:.*]] = getelementptr inbounds %struct.force_pow2_depth_st, ptr %{{[a-zA-Z0-9]+}}, i32 0, i32 0 - ; CHECK-LLVM: call ptr @llvm.ptr.annotation.p0{{.*}}%[[FLD_FP2_SCT]]{{.*}}[[STR_FP2_SCT]] - %field = getelementptr inbounds %struct.force_pow2_depth_st, %struct.force_pow2_depth_st* %s, i32 0, i32 0 - %1 = call i32* @llvm.ptr.annotation.p0i32(i32* %field, i8* getelementptr inbounds ([49 x i8], [49 x i8]* @.str.17, i32 0, i32 0), i8* getelementptr inbounds ([28 x i8], [28 x i8]* @.str.1, i32 0, i32 0), i32 120, i8* null) - store i32 0, i32* %1, align 4, !tbaa !43 - %2 = bitcast %struct.force_pow2_depth_st* %s to i8* - call void @llvm.lifetime.end.p0i8(i64 4, i8* %2) #5 - ret void -} - -; Function Attrs: norecurse nounwind -define linkonce_odr spir_func void @_Z33templ_field_force_pow2_depth_attrILi1EEvv() #3 { -entry: - %s = alloca %struct.templ_force_pow2_depth_st, align 4 - %0 = bitcast %struct.templ_force_pow2_depth_st* %s to i8* - call void @llvm.lifetime.start.p0i8(i64 4, i8* %0) #5 - ; CHECK-LLVM: %[[FLD_FP2_STE:.*]] = getelementptr inbounds %struct.templ_force_pow2_depth_st, ptr %{{[a-zA-Z0-9]+}}, i32 0, i32 0 - ; CHECK-LLVM: call ptr @llvm.ptr.annotation.p0{{.*}}%[[FLD_FP2_STE]]{{.*}}[[STR_FP2_STE]] - %field = getelementptr inbounds %struct.templ_force_pow2_depth_st, %struct.templ_force_pow2_depth_st* %s, i32 0, i32 0 - %1 = call i32* @llvm.ptr.annotation.p0i32(i32* %field, i8* getelementptr inbounds ([49 x i8], [49 x i8]* @.str.18, i32 0, i32 0), i8* getelementptr inbounds ([28 x i8], [28 x i8]* @.str.1, i32 0, i32 0), i32 128, i8* null) - store i32 0, i32* %1, align 4, !tbaa !45 - %2 = bitcast %struct.templ_force_pow2_depth_st* %s to i8* - call void @llvm.lifetime.end.p0i8(i64 4, i8* %2) #5 - ret void -} - -; Function Attrs: norecurse nounwind -define spir_func void @_Z20field_addrspace_castv() #3 { -entry: - %state_var = alloca %struct.state, align 4 - %0 = bitcast %struct.state* %state_var to i8* - call void @llvm.lifetime.start.p0i8(i64 32, i8* %0) #5 - call spir_func void @_ZZ20field_addrspace_castvEN5stateC1Ev(%struct.state* %state_var) - ; CHECK-LLVM: %[[GEP:.*]] = getelementptr inbounds %struct.state, ptr %state_var, i32 0, i32 0 - ; CHECK-LLVM: %{{[0-9]+}} = call ptr @llvm.ptr.annotation.p0.p0(ptr %[[GEP]]{{.*}}[[STR_NMB_ASC]] - %mem = getelementptr inbounds %struct.state, %struct.state* %state_var, i32 0, i32 0 - %1 = bitcast [8 x i32]* %mem to i8* - %2 = call i8* @llvm.ptr.annotation.p0i8(i8* %1, i8* getelementptr inbounds ([43 x i8], [43 x i8]* @.str.19, i32 0, i32 0), i8* getelementptr inbounds ([28 x i8], [28 x i8]* @.str.1, i32 0, i32 0), i32 120, i8* null) - %3 = bitcast i8* %2 to [8 x i32]* - %arrayidx = getelementptr inbounds [8 x i32], [8 x i32]* %3, i32 0, i32 0 - store i32 42, i32* %arrayidx, align 4, !tbaa !12 - %4 = bitcast %struct.state* %state_var to i8* - call void @llvm.lifetime.end.p0i8(i64 32, i8* %4) #5 - ret void -} - -; Function Attrs: norecurse nounwind -define internal spir_func void @_ZZ20field_addrspace_castvEN5stateC1Ev(%struct.state* %this) unnamed_addr #3 align 2 { -entry: - %this.addr = alloca %struct.state*, align 4 - store %struct.state* %this, %struct.state** %this.addr, align 4, !tbaa !5 - %this1 = load %struct.state*, %struct.state** %this.addr, align 4 - call spir_func void @_ZZ20field_addrspace_castvEN5stateC2Ev(%struct.state* %this1) - ret void -} - -; Function Attrs: norecurse nounwind -define internal spir_func void @_ZZ20field_addrspace_castvEN5stateC2Ev(%struct.state* %this) unnamed_addr #3 align 2 { -entry: - %this.addr = alloca %struct.state*, align 4 - %i = alloca i32, align 4 - store %struct.state* %this, %struct.state** %this.addr, align 4, !tbaa !5 - %this1 = load %struct.state*, %struct.state** %this.addr, align 4 - %0 = bitcast i32* %i to i8* - call void @llvm.lifetime.start.p0i8(i64 4, i8* %0) #5 - store i32 0, i32* %i, align 4, !tbaa !12 - br label %for.cond - -for.cond: ; preds = %for.inc, %entry - %1 = load i32, i32* %i, align 4, !tbaa !12 - %cmp = icmp slt i32 %1, 8 - br i1 %cmp, label %for.body, label %for.cond.cleanup - -for.cond.cleanup: ; preds = %for.cond - %2 = bitcast i32* %i to i8* - call void @llvm.lifetime.end.p0i8(i64 4, i8* %2) #5 - br label %for.end - -for.body: ; preds = %for.cond - %3 = load i32, i32* %i, align 4, !tbaa !12 - %mem = getelementptr inbounds %struct.state, %struct.state* %this1, i32 0, i32 0 - ; FIXME: currently llvm.ptr.annotation is not emitted for c'tors, need to fix it and add a check here - %4 = bitcast [8 x i32]* %mem to i8* - %5 = call i8* @llvm.ptr.annotation.p0i8(i8* %4, i8* getelementptr inbounds ([43 x i8], [43 x i8]* @.str.19, i32 0, i32 0), i8* getelementptr inbounds ([28 x i8], [28 x i8]* @.str.1, i32 0, i32 0), i32 120, i8* null) - %6 = bitcast i8* %5 to [8 x i32]* - %7 = load i32, i32* %i, align 4, !tbaa !12 - %arrayidx = getelementptr inbounds [8 x i32], [8 x i32]* %6, i32 0, i32 %7 - store i32 %3, i32* %arrayidx, align 4, !tbaa !12 - br label %for.inc - -for.inc: ; preds = %for.body - %8 = load i32, i32* %i, align 4, !tbaa !12 - %inc = add nsw i32 %8, 1 - store i32 %inc, i32* %i, align 4, !tbaa !12 - br label %for.cond - -for.end: ; preds = %for.cond.cleanup - ret void -} - -; Function Attrs: nounwind willreturn -declare i8* @llvm.ptr.annotation.p0i8(i8*, i8*, i8*, i32, i8*) #4 - -; Function Attrs: nounwind willreturn -declare i32* @llvm.ptr.annotation.p0i32(i32*, i8*, i8*, i32, i8*) #4 - -attributes #0 = { norecurse nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "sycl-module-id"="intel-fpga-local-struct.cpp" "uniform-work-group-size"="true" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #1 = { argmemonly nounwind willreturn } -attributes #2 = { inlinehint norecurse nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #3 = { norecurse nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #4 = { nounwind willreturn } -attributes #5 = { nounwind } - -!llvm.module.flags = !{!0} -!opencl.spir.version = !{!1} -!spirv.Source = !{!2} -!llvm.ident = !{!3} - -!0 = !{i32 1, !"wchar_size", i32 4} -!1 = !{i32 1, i32 2} -!2 = !{i32 4, i32 100000} -!3 = !{!"clang version 11.0.0"} -!4 = !{} -!5 = !{!6, !6, i64 0} -!6 = !{!"any pointer", !7, i64 0} -!7 = !{!"omnipotent char", !8, i64 0} -!8 = !{!"Simple C++ TBAA"} -!9 = !{!10, !11, i64 0} -!10 = !{!"_ZTSZ19field_numbanks_attrvE11numbanks_st", !11, i64 0} -!11 = !{!"int", !7, i64 0} -!12 = !{!11, !11, i64 0} -!13 = !{!14, !11, i64 0} -!14 = !{!"_ZTSZ25templ_field_numbanks_attrILi8EEvvE17templ_numbanks_st", !11, i64 0} -!15 = !{!16, !11, i64 0} -!16 = !{!"_ZTSZ19field_register_attrvE11register_st", !11, i64 0} -!17 = !{!18, !11, i64 0} -!18 = !{!"_ZTSZ17field_memory_attrvE9memory_st", !11, i64 0} -!19 = !{!20, !11, i64 0} -!20 = !{!"_ZTSZ20field_bankwidth_attrvE12bankwidth_st", !11, i64 0} -!21 = !{!22, !11, i64 0} -!22 = !{!"_ZTSZ26templ_field_bankwidth_attrILi4EEvvE18templ_bankwidth_st", !11, i64 0} -!23 = !{!24, !11, i64 0} -!24 = !{!"_ZTSZ25field_private_copies_attrvE17private_copies_st", !11, i64 0} -!25 = !{!26, !11, i64 0} -!26 = !{!"_ZTSZ31templ_field_private_copies_attrILi2EEvvE23templ_private_copies_st", !11, i64 0} -!27 = !{!28, !11, i64 0} -!28 = !{!"_ZTSZ21field_singlepump_attrvE13singlepump_st", !11, i64 0} -!29 = !{!30, !11, i64 0} -!30 = !{!"_ZTSZ21field_doublepump_attrvE13doublepump_st", !11, i64 0} -!31 = !{!32, !11, i64 0} -!32 = !{!"_ZTSZ16field_merge_attrvE8merge_st", !11, i64 0} -!33 = !{!34, !11, i64 0} -!34 = !{!"_ZTSZ25field_max_replicates_attrvE17max_replicates_st", !11, i64 0} -!35 = !{!36, !11, i64 0} -!36 = !{!"_ZTSZ31templ_field_max_replicates_attrILi2EEvvE23templ_max_replicates_st", !11, i64 0} -!37 = !{!38, !11, i64 0} -!38 = !{!"_ZTSZ27field_simple_dual_port_attrvE19simple_dual_port_st", !11, i64 0} -!39 = !{!40, !11, i64 0} -!40 = !{!"_ZTSZ20field_bank_bits_attrvE12bank_bits_st", !11, i64 0} -!41 = !{!42, !11, i64 0} -!42 = !{!"_ZTSZ26templ_field_bank_bits_attrILi2ELi3EEvvE18templ_bank_bits_st", !11, i64 0} -!43 = !{!44, !11, i64 0} -!44 = !{!"_ZTSZ27field_force_pow2_depth_attrvE19force_pow2_depth_st", !11, i64 0} -!45 = !{!46, !11, i64 0} -!46 = !{!"_ZTSZ33templ_field_force_pow2_depth_attrILi1EEvvE25templ_force_pow2_depth_st", !11, i64 0} +declare ptr addrspace(4) @llvm.ptr.annotation.p4.p1(ptr addrspace(4), ptr addrspace(1), ptr addrspace(1), i32, ptr addrspace(1)) diff --git a/test/extensions/INTEL/SPV_INTEL_fpga_memory_attributes/IntelFPGAMemoryAttributesForVar.ll b/test/extensions/INTEL/SPV_INTEL_fpga_memory_attributes/IntelFPGAMemoryAttributesForVar.ll new file mode 100644 index 0000000000..2b47e88430 --- /dev/null +++ b/test/extensions/INTEL/SPV_INTEL_fpga_memory_attributes/IntelFPGAMemoryAttributesForVar.ll @@ -0,0 +1,197 @@ +; RUN: llvm-as %s -o %t.bc +; RUN: llvm-spirv --spirv-ext=+SPV_INTEL_fpga_memory_attributes -spirv-text -o - %t.bc | FileCheck --check-prefix CHECK-SPIRV %s +; RUN: llvm-spirv --spirv-ext=+SPV_INTEL_fpga_memory_attributes %t.bc -o %t.spv +; RUN: spirv-val %t.spv +; RUN: llvm-spirv -r --spirv-ext=+SPV_INTEL_fpga_memory_attributes %t.spv -o %t.rev.bc +; RUN: llvm-dis %t.rev.bc -o - | FileCheck --check-prefix CHECK-LLVM %s + +target triple = "spir64-unknown-unknown" + +; CHECK-SPIRV: Capability FPGAMemoryAttributesINTEL +; CHECK-SPIRV: Extension "SPV_INTEL_fpga_memory_attributes" +; CHECK-SPIRV: Decorate [[#REGISTER:]] RegisterINTEL +; CHECK-SPIRV: Decorate [[#MEMORY:]] MemoryINTEL "DEFAULT" +; CHECK-SPIRV: Decorate [[#NUMBANKS:]] NumbanksINTEL 4 +; CHECK-SPIRV: Decorate [[#BANKWIDTH:]] BankwidthINTEL 4 +; CHECK-SPIRV: Decorate [[#MAX_PRIVATE_COPIES:]] MaxPrivateCopiesINTEL 1 +; CHECK-SPIRV: Decorate [[#SINGLEPUMP:]] SinglepumpINTEL +; CHECK-SPIRV: Decorate [[#DOUBLEPUMP:]] DoublepumpINTEL +; CHECK-SPIRV: Decorate [[#MAX_REPLICATES:]] MaxReplicatesINTEL 2 +; CHECK-SPIRV: Decorate [[#SIMPLE_DUAL_PORT:]] SimpleDualPortINTEL +; CHECK-SPIRV: Decorate [[#MERGE:]] MergeINTEL "key" "type" +; CHECK-SPIRV: Decorate [[#BANK_BITS:]] BankBitsINTEL 2 +; CHECK-SPIRV: Decorate [[#FORCE_POW_2_DEPTH:]] ForcePow2DepthINTEL 2 +; CHECK-SPIRV: Decorate [[#STRIDESIZE:]] StridesizeINTEL 4 +; CHECK-SPIRV: Decorate [[#WORDSIZE:]] WordsizeINTEL 8 +; CHECK-SPIRV: Decorate [[#TRUE_DUAL_PORT:]] TrueDualPortINTEL +; CHECK-SPIRV: Variable {{[0-9]+}} [[#REGISTER]] {{[0-9]+}} +; CHECK-SPIRV: Variable {{[0-9]+}} [[#MEMORY]] {{[0-9]+}} +; CHECK-SPIRV: Variable {{[0-9]+}} [[#NUMBANKS]] {{[0-9]+}} +; CHECK-SPIRV: Variable {{[0-9]+}} [[#BANKWIDTH]] {{[0-9]+}} +; CHECK-SPIRV: Variable {{[0-9]+}} [[#MAX_PRIVATE_COPIES]] {{[0-9]+}} +; CHECK-SPIRV: Variable {{[0-9]+}} [[#SINGLEPUMP]] {{[0-9]+}} +; CHECK-SPIRV: Variable {{[0-9]+}} [[#DOUBLEPUMP]] {{[0-9]+}} +; CHECK-SPIRV: Variable {{[0-9]+}} [[#MAX_REPLICATES]] {{[0-9]+}} +; CHECK-SPIRV: Variable {{[0-9]+}} [[#SIMPLE_DUAL_PORT]] {{[0-9]+}} +; CHECK-SPIRV: Variable {{[0-9]+}} [[#MERGE]] {{[0-9]+}} +; CHECK-SPIRV: Variable {{[0-9]+}} [[#BANK_BITS]] {{[0-9]+}} +; CHECK-SPIRV: Variable {{[0-9]+}} [[#FORCE_POW_2_DEPTH]] {{[0-9]+}} +; CHECK-SPIRV: Variable {{[0-9]+}} [[#STRIDESIZE]] {{[0-9]+}} +; CHECK-SPIRV: Variable {{[0-9]+}} [[#WORDSIZE]] {{[0-9]+}} +; CHECK-SPIRV: Variable {{[0-9]+}} [[#TRUE_DUAL_PORT]] {{[0-9]+}} + +; CHECK-LLVM: [[REGISTER:@[0-9_.]+]] = {{.*}}{register:1} +; CHECK-LLVM: [[MEMORY:@[0-9_.]+]] = {{.*}}{memory:DEFAULT} +; CHECK-LLVM: [[NUMBANKS:@[0-9_.]+]] = {{.*}}{numbanks:4} +; CHECK-LLVM: [[BANKWIDTH:@[0-9_.]+]] = {{.*}}{bankwidth:4} +; CHECK-LLVM: [[MAX_PRIVATE_COPIES:@[0-9_.]+]] = {{.*}}{private_copies:1} +; CHECK-LLVM: [[SINGLEPUMP:@[0-9_.]+]] = {{.*}}{pump:1} +; CHECK-LLVM: [[DOUBLEPUMP:@[0-9_.]+]] = {{.*}}{pump:2} +; CHECK-LLVM: [[MAX_REPLICATES:@[0-9_.]+]] = {{.*}}{max_replicates:2} +; CHECK-LLVM: [[SIMPLE_DUAL_PORT:@[0-9_.]+]] = {{.*}}{simple_dual_port:1} +; CHECK-LLVM: [[MERGE:@[0-9_.]+]] = {{.*}}{merge:key:type} +; CHECK-LLVM: [[BANK_BITS:@[0-9_.]+]] = {{.*}}{bank_bits:2} +; CHECK-LLVM: [[FORCE_POW_2_DEPTH:@[0-9_.]+]] = {{.*}}{force_pow2_depth:2} +; CHECK-LLVM: [[STRIDESIZE:@[0-9_.]+]] = {{.*}}{stride_size:4} +; CHECK-LLVM: [[WORDSIZE:@[0-9_.]+]] = {{.*}}{word_size:8} +; CHECK-LLVM: [[TRUE_DUAL_PORT:@[0-9_.]+]] = {{.*}}{true_dual_port:1} +; CHECK-LLVM: call void @llvm.var.annotation.p0.p0(ptr %{{[a-zA-Z0-9_]+}}, ptr [[REGISTER]], ptr undef, i32 undef, ptr undef) +; CHECK-LLVM: call void @llvm.var.annotation.p0.p0(ptr %{{[a-zA-Z0-9_]+}}, ptr [[MEMORY]], ptr undef, i32 undef, ptr undef) +; CHECK-LLVM: call void @llvm.var.annotation.p0.p0(ptr %{{[a-zA-Z0-9_]+}}, ptr [[NUMBANKS]], ptr undef, i32 undef, ptr undef) +; CHECK-LLVM: call void @llvm.var.annotation.p0.p0(ptr %{{[a-zA-Z0-9_]+}}, ptr [[BANKWIDTH]], ptr undef, i32 undef, ptr undef) +; CHECK-LLVM: call void @llvm.var.annotation.p0.p0(ptr %{{[a-zA-Z0-9_]+}}, ptr [[MAX_PRIVATE_COPIES]], ptr undef, i32 undef, ptr undef) +; CHECK-LLVM: call void @llvm.var.annotation.p0.p0(ptr %{{[a-zA-Z0-9_]+}}, ptr [[SINGLEPUMP]], ptr undef, i32 undef, ptr undef) +; CHECK-LLVM: call void @llvm.var.annotation.p0.p0(ptr %{{[a-zA-Z0-9_]+}}, ptr [[DOUBLEPUMP]], ptr undef, i32 undef, ptr undef) +; CHECK-LLVM: call void @llvm.var.annotation.p0.p0(ptr %{{[a-zA-Z0-9_]+}}, ptr [[MAX_REPLICATES]], ptr undef, i32 undef, ptr undef) +; CHECK-LLVM: call void @llvm.var.annotation.p0.p0(ptr %{{[a-zA-Z0-9_]+}}, ptr [[SIMPLE_DUAL_PORT]], ptr undef, i32 undef, ptr undef) +; CHECK-LLVM: call void @llvm.var.annotation.p0.p0(ptr %{{[a-zA-Z0-9_]+}}, ptr [[MERGE]], ptr undef, i32 undef, ptr undef) +; CHECK-LLVM: call void @llvm.var.annotation.p0.p0(ptr %{{[a-zA-Z0-9_]+}}, ptr [[BANK_BITS]], ptr undef, i32 undef, ptr undef) +; CHECK-LLVM: call void @llvm.var.annotation.p0.p0(ptr %{{[a-zA-Z0-9_]+}}, ptr [[FORCE_POW_2_DEPTH]], ptr undef, i32 undef, ptr undef) +; CHECK-LLVM: call void @llvm.var.annotation.p0.p0(ptr %{{[a-zA-Z0-9_]+}}, ptr [[STRIDESIZE]], ptr undef, i32 undef, ptr undef) +; CHECK-LLVM: call void @llvm.var.annotation.p0.p0(ptr %{{[a-zA-Z0-9_]+}}, ptr [[WORDSIZE]], ptr undef, i32 undef, ptr undef) +; CHECK-LLVM: call void @llvm.var.annotation.p0.p0(ptr %{{[a-zA-Z0-9_]+}}, ptr [[TRUE_DUAL_PORT]], ptr undef, i32 undef, ptr undef) + +%"example_type" = type { i32 } + +@register_attr = private unnamed_addr addrspace(1) constant [7 x i8] c"{5825}\00", section "llvm.metadata" +@memory_attr = private unnamed_addr addrspace(1) constant [15 x i8] c"{5826:DEFAULT}\00", section "llvm.metadata" +@numbanks_attr = private unnamed_addr addrspace(1) constant [9 x i8] c"{5827:4}\00", section "llvm.metadata" +@bankwidth_attr = private unnamed_addr addrspace(1) constant [9 x i8] c"{5828:4}\00", section "llvm.metadata" +@max_private_copies_attr = private unnamed_addr addrspace(1) constant [9 x i8] c"{5829:1}\00", section "llvm.metadata" +@singlepump_attr = private unnamed_addr addrspace(1) constant [7 x i8] c"{5830}\00", section "llvm.metadata" +@doublepump_attr = private unnamed_addr addrspace(1) constant [7 x i8] c"{5831}\00", section "llvm.metadata" +@max_replicates_attr = private unnamed_addr addrspace(1) constant [9 x i8] c"{5832:2}\00", section "llvm.metadata" +@simple_dual_port_attr = private unnamed_addr addrspace(1) constant [7 x i8] c"{5833}\00", section "llvm.metadata" +@merge_attr = private unnamed_addr addrspace(1) constant [16 x i8] c"{5834:key,type}\00", section "llvm.metadata" +@bankbits_attr = private unnamed_addr addrspace(1) constant [9 x i8] c"{5835:2}\00", section "llvm.metadata" +@force_pow_2_depth_attr = private unnamed_addr addrspace(1) constant [9 x i8] c"{5836:2}\00", section "llvm.metadata" +@stride_size_attr = private unnamed_addr addrspace(1) constant [9 x i8] c"{5883:4}\00", section "llvm.metadata" +@word_size_attr = private unnamed_addr addrspace(1) constant [9 x i8] c"{5884:8}\00", section "llvm.metadata" +@true_dual_port_attr = private unnamed_addr addrspace(1) constant [7 x i8] c"{5885}\00", section "llvm.metadata" + +define spir_func void @test_fpga_register_attr() { +entry: + %0 = alloca %"example_type", align 4 + call void @llvm.var.annotation.p0.p1(ptr %0, ptr addrspace(1) @register_attr, ptr addrspace(1) null, i32 0, ptr addrspace(1) null) + ret void +} + +define spir_func void @test_fpga_memory_attr() { +entry: + %0 = alloca %"example_type", align 4 + call void @llvm.var.annotation.p0.p1(ptr %0, ptr addrspace(1) @memory_attr, ptr addrspace(1) null, i32 0, ptr addrspace(1) null) + ret void +} + +define spir_func void @test_fpga_numbanks_attr() { +entry: + %0 = alloca %"example_type", align 4 + call void @llvm.var.annotation.p0.p1(ptr %0, ptr addrspace(1) @numbanks_attr, ptr addrspace(1) null, i32 0, ptr addrspace(1) null) + ret void +} + +define spir_func void @test_fpga_bankwidth_attr() { +entry: + %0 = alloca %"example_type", align 4 + call void @llvm.var.annotation.p0.p1(ptr %0, ptr addrspace(1) @bankwidth_attr, ptr addrspace(1) null, i32 0, ptr addrspace(1) null) + ret void +} + +define spir_func void @test_fpga_max_private_copies_attr() { +entry: + %0 = alloca %"example_type", align 4 + call void @llvm.var.annotation.p0.p1(ptr %0, ptr addrspace(1) @max_private_copies_attr, ptr addrspace(1) null, i32 0, ptr addrspace(1) null) + ret void +} + +define spir_func void @test_fpga_singlepump_attr() { +entry: + %0 = alloca %"example_type", align 4 + call void @llvm.var.annotation.p0.p1(ptr %0, ptr addrspace(1) @singlepump_attr, ptr addrspace(1) null, i32 0, ptr addrspace(1) null) + ret void +} + +define spir_func void @test_fpga_doublepump_attr() { +entry: + %0 = alloca %"example_type", align 4 + call void @llvm.var.annotation.p0.p1(ptr %0, ptr addrspace(1) @doublepump_attr, ptr addrspace(1) null, i32 0, ptr addrspace(1) null) + ret void +} + +define spir_func void @test_fpga_max_replicates_attr() { +entry: + %0 = alloca %"example_type", align 4 + call void @llvm.var.annotation.p0.p1(ptr %0, ptr addrspace(1) @max_replicates_attr, ptr addrspace(1) null, i32 0, ptr addrspace(1) null) + ret void +} + +define spir_func void @test_fpga_simple_dual_port_attr() { +entry: + %0 = alloca %"example_type", align 4 + call void @llvm.var.annotation.p0.p1(ptr %0, ptr addrspace(1) @simple_dual_port_attr, ptr addrspace(1) null, i32 0, ptr addrspace(1) null) + ret void +} + +define spir_func void @test_fpga_merge_attr() { +entry: + %0 = alloca %"example_type", align 4 + call void @llvm.var.annotation.p0.p1(ptr %0, ptr addrspace(1) @merge_attr, ptr addrspace(1) null, i32 0, ptr addrspace(1) null) + ret void +} + +define spir_func void @test_fpga_bankbits_attr() { +entry: + %0 = alloca %"example_type", align 4 + call void @llvm.var.annotation.p0.p1(ptr %0, ptr addrspace(1) @bankbits_attr, ptr addrspace(1) null, i32 0, ptr addrspace(1) null) + ret void +} + +define spir_func void @test_fpga_force_pow_2_depth_attr() { +entry: + %0 = alloca %"example_type", align 4 + call void @llvm.var.annotation.p0.p1(ptr %0, ptr addrspace(1) @force_pow_2_depth_attr, ptr addrspace(1) null, i32 0, ptr addrspace(1) null) + ret void +} + +define spir_func void @test_fpga_stride_size_attr() { +entry: + %0 = alloca %"example_type", align 4 + call void @llvm.var.annotation.p0.p1(ptr %0, ptr addrspace(1) @stride_size_attr, ptr addrspace(1) null, i32 0, ptr addrspace(1) null) + ret void +} + +define spir_func void @test_fpga_word_size_attr() { +entry: + %0 = alloca %"example_type", align 4 + call void @llvm.var.annotation.p0.p1(ptr %0, ptr addrspace(1) @word_size_attr, ptr addrspace(1) null, i32 0, ptr addrspace(1) null) + ret void +} + +define spir_func void @test_fpga_true_dual_port_attr() { +entry: + %0 = alloca %"example_type", align 4 + call void @llvm.var.annotation.p0.p1(ptr %0, ptr addrspace(1) @true_dual_port_attr, ptr addrspace(1) null, i32 0, ptr addrspace(1) null) + ret void +} + +declare void @llvm.var.annotation.p0.p1(ptr, ptr addrspace(1), ptr addrspace(1), i32, ptr addrspace(1))