From 09af962fdec89a5a46eae0b0cda59c69938c4856 Mon Sep 17 00:00:00 2001 From: Connor Davis Date: Wed, 20 Oct 2021 16:17:06 +0000 Subject: [PATCH] x86: Add 'l' suffix to btr/bts instructions Add an explicit suffix to the btr/bts instructions within atomic_test_and_{re,}set_bit. This addition silences the following assembler warnings: ktf/include/arch/x86/atomic.h:62: Warning: no instruction mnemonic suffix given and no register operands; using default for `bts' ktf/include/arch/x86/atomic.h:74: Warning: no instruction mnemonic suffix given and no register operands; using default for `btr' Signed-off-by: Connor Davis --- include/arch/x86/atomic.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/arch/x86/atomic.h b/include/arch/x86/atomic.h index fee6c1a6..2437a860 100644 --- a/include/arch/x86/atomic.h +++ b/include/arch/x86/atomic.h @@ -59,7 +59,7 @@ static inline bool atomic_test_bit(unsigned int bit, volatile void *addr) { static inline bool atomic_test_and_set_bit(unsigned int bit, volatile void *addr) { bool status; - asm volatile("lock bts %[bit], %[addr];" + asm volatile("lock btsl %[bit], %[addr];" "setc %[status];" : [ status ] "=r"(status) : [ bit ] "Ir"(bit), [ addr ] "m"(*(uint8_t *) addr) @@ -71,7 +71,7 @@ static inline bool atomic_test_and_set_bit(unsigned int bit, volatile void *addr static inline bool atomic_test_and_reset_bit(unsigned int bit, volatile void *addr) { bool status; - asm volatile("lock btr %[bit], %[addr];" + asm volatile("lock btrl %[bit], %[addr];" "setc %[status];" : [ status ] "=r"(status) : [ bit ] "Ir"(bit), [ addr ] "m"(*(uint8_t *) addr)