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AES.qsf
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AES.qsf
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2023 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition
# Date created = 22:39:10 May 04, 2024
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# AES_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Intel recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CSEMA5F31C6
set_global_assignment -name TOP_LEVEL_ENTITY AES
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 23.1STD.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:39:10 MAY 04, 2024"
set_global_assignment -name LAST_QUARTUS_VERSION "23.1std.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name BOARD "DE1-SoC Board"
set_global_assignment -name EDA_SIMULATION_TOOL "QuestaSim (Verilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
set_global_assignment -name VERILOG_FILE AES.v
set_global_assignment -name VERILOG_FILE AES_Encrypt.v
set_global_assignment -name VERILOG_FILE AES_Decrypt.v
set_global_assignment -name VERILOG_FILE round.v
set_global_assignment -name VERILOG_FILE invround.v
set_global_assignment -name VERILOG_FILE subBytes.v
set_global_assignment -name VERILOG_FILE Addroundkey.v
set_global_assignment -name VERILOG_FILE KeyExpansion.v
set_global_assignment -name VERILOG_FILE ShiftBytes.v
set_global_assignment -name VERILOG_FILE invsubBytes.v
set_global_assignment -name VERILOG_FILE mixColumns.v
set_global_assignment -name VERILOG_FILE invMixColumns.v
set_global_assignment -name VERILOG_FILE xtime.v
set_global_assignment -name VERILOG_FILE bin2bcd.v
set_global_assignment -name VERILOG_FILE segment7.v
set_global_assignment -name VERILOG_FILE ERER.v
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name VERILOG_FILE invShiftBytes.v
set_location_assignment PIN_AB12 -to A
set_location_assignment PIN_AC12 -to B
set_location_assignment PIN_AB23 -to H[6]
set_location_assignment PIN_AE29 -to H[5]
set_location_assignment PIN_AD29 -to H[4]
set_location_assignment PIN_AC28 -to H[3]
set_location_assignment PIN_AD30 -to H[2]
set_location_assignment PIN_AC29 -to H[1]
set_location_assignment PIN_AC30 -to H[0]
set_location_assignment PIN_V16 -to L1
set_location_assignment PIN_W16 -to L2
set_location_assignment PIN_V17 -to L3
set_location_assignment PIN_AE26 -to O[6]
set_location_assignment PIN_AE27 -to O[5]
set_location_assignment PIN_AE28 -to O[4]
set_location_assignment PIN_AG27 -to O[3]
set_location_assignment PIN_AF28 -to O[2]
set_location_assignment PIN_AG28 -to O[1]
set_location_assignment PIN_AH28 -to O[0]
set_location_assignment PIN_AJ29 -to T[6]
set_location_assignment PIN_AH29 -to T[5]
set_location_assignment PIN_AH30 -to T[4]
set_location_assignment PIN_AG30 -to T[3]
set_location_assignment PIN_AF29 -to T[2]
set_location_assignment PIN_AF30 -to T[1]
set_location_assignment PIN_AD27 -to T[0]
set_location_assignment PIN_AA14 -to clk
set_location_assignment PIN_AF9 -to reset
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name SMART_RECOMPILE ON
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top