From 086956d8a5af0804ccd4e202ec7006dcc1f745d3 Mon Sep 17 00:00:00 2001
From: calithameridi <107025477+calithameridi@users.noreply.github.com>
Date: Wed, 7 Feb 2024 01:40:01 -0800
Subject: [PATCH] Update stm32h7.c

fixes clock configuration error with non-25 MHz crystals
---
 src/stm32/stm32h7.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/src/stm32/stm32h7.c b/src/stm32/stm32h7.c
index 387e47dd9..875415f99 100644
--- a/src/stm32/stm32h7.c
+++ b/src/stm32/stm32h7.c
@@ -98,9 +98,14 @@ clock_setup(void)
     PWR->CR3 = (PWR->CR3 | PWR_CR3_LDOEN) & ~(PWR_CR3_BYPASS | PWR_CR3_SCUEN);
     while (!(PWR->CSR1 & PWR_CSR1_ACTVOSRDY))
         ;
-    // (HSE 25mhz) /DIVM1(5) (pll_base 5Mhz) *DIVN1(192) (pll_freq 960Mhz)
-    // /DIVP1(2) (SYSCLK 480Mhz)
+// klipper supports 8, 12, 16, 20, 24, and 25 MHz crystals on HSE
+#if CONFIG_CLOCK_REF_FREQ % 5000000 == 0
     uint32_t pll_base = 5000000;
+#elif CONFIG_CLOCK_REF_FREQ % 4000000 == 0
+    uint32_t pll_base = 4000000;
+#else
+#error Unknown pll_base for CLOCK_REF_FREQ
+#endif
     // Only even dividers (DIVP1) are allowed
     uint32_t pll_freq = CONFIG_CLOCK_FREQ * 2;
     if (!CONFIG_STM32_CLOCK_REF_INTERNAL) {