Chronogram visualization in VHDL problems when the solution is right.

[FranciscoNaveros]

Right now, in the VHDL problems, when the student' solution differs of the professor' solution, a new windows is generated, showing the differences between both solutions. That differences are additionally represented in a chronogram ploting all the signals. Nevertheless, when the solution is right, that chronogram showing the evolution of the signals is not generated. The chronogram should be always generated, regardless of whether the solution is wrong or right.

Additionally, the time represented in that chronogram should be all the simulation time. Right now, the amount of time represented in the chronogram can be inferior to the simulation time, depending on the errors in the student' solution.

Finally, it whould be very usefull if the chronogram would include in the x axe the time of each step.

Francisco Naveros