From 1635bc078c2ad13780a9f877267e314e1e931632 Mon Sep 17 00:00:00 2001 From: gitlab-runner Date: Thu, 12 Dec 2019 04:41:23 -0600 Subject: [PATCH] Upload psoc6pdl 1.4.0.1889 --- README.md | 4 + RELEASE.md | 36 +- devices/include/cyb06445lqi_s3d42.h | 4 +- devices/include/gpio_psoc6_01_104_m_csp_ble.h | 4 +- .../include/gpio_psoc6_01_104_m_csp_ble_usb.h | 4 +- devices/include/gpio_psoc6_01_116_bga_ble.h | 4 +- devices/include/gpio_psoc6_01_116_bga_usb.h | 4 +- devices/include/gpio_psoc6_01_124_bga.h | 4 +- devices/include/gpio_psoc6_01_124_bga_sip.h | 4 +- devices/include/gpio_psoc6_01_43_smt.h | 4 +- devices/include/gpio_psoc6_01_68_qfn_ble.h | 4 +- devices/include/gpio_psoc6_01_80_wlcsp.h | 4 +- .../TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct | 15 +- .../TOOLCHAIN_ARM/cy8c6xx6_cm0plus.sct | 15 +- .../TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct | 15 +- .../TOOLCHAIN_ARM/cy8c6xx8_cm0plus.sct | 15 +- .../TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct | 15 +- .../TOOLCHAIN_ARM/cyb06xx5_cm0plus.sct | 293 ++++++++ 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+-- .../CY8C6336BZI-BUD13/base/view.xml | 30 +- .../PSoC6ABLE2/CY8C6336BZI-BUD13/info.xml | 10 +- .../CY8C6336BZI-BUD13/studio/presentation | 4 +- .../CY8C6336BZI-BUD13/studio/view.xml | 110 +-- .../CY8C6336LQI-BLF02/base/view.xml | 30 +- .../PSoC6ABLE2/CY8C6336LQI-BLF02/info.xml | 10 +- .../CY8C6336LQI-BLF02/studio/presentation | 4 +- .../CY8C6336LQI-BLF02/studio/view.xml | 110 +-- .../CY8C6336LQI-BLF42/base/view.xml | 30 +- .../PSoC6ABLE2/CY8C6336LQI-BLF42/info.xml | 10 +- .../CY8C6336LQI-BLF42/studio/presentation | 4 +- .../CY8C6336LQI-BLF42/studio/view.xml | 110 +-- .../CY8C6337BZI-BLF13/base/view.xml | 30 +- .../PSoC6ABLE2/CY8C6337BZI-BLF13/info.xml | 10 +- .../CY8C6337BZI-BLF13/studio/presentation | 4 +- .../CY8C6337BZI-BLF13/studio/view.xml | 110 +-- .../CY8C6347BZI-BLD33/base/view.xml | 30 +- .../PSoC6ABLE2/CY8C6347BZI-BLD33/info.xml | 10 +- .../CY8C6347BZI-BLD33/studio/presentation | 4 +- .../CY8C6347BZI-BLD33/studio/view.xml | 110 +-- .../CY8C6347BZI-BLD34/base/view.xml | 30 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| 10 +- .../CY8C6347BZI-BUD33/studio/presentation | 4 +- .../CY8C6347BZI-BUD33/studio/view.xml | 110 +-- .../CY8C6347BZI-BUD43/base/view.xml | 30 +- .../PSoC6ABLE2/CY8C6347BZI-BUD43/info.xml | 10 +- .../CY8C6347BZI-BUD43/studio/presentation | 4 +- .../CY8C6347BZI-BUD43/studio/view.xml | 110 +-- .../CY8C6347BZI-BUD53/base/view.xml | 30 +- .../PSoC6ABLE2/CY8C6347BZI-BUD53/info.xml | 10 +- .../CY8C6347BZI-BUD53/studio/presentation | 4 +- .../CY8C6347BZI-BUD53/studio/view.xml | 110 +-- .../CY8C6347FMI-BLD13/base/view.xml | 30 +- .../PSoC6ABLE2/CY8C6347FMI-BLD13/info.xml | 10 +- .../CY8C6347FMI-BLD13/studio/presentation | 4 +- .../CY8C6347FMI-BLD13/studio/view.xml | 110 +-- .../CY8C6347FMI-BLD33/base/view.xml | 30 +- .../PSoC6ABLE2/CY8C6347FMI-BLD33/info.xml | 10 +- .../CY8C6347FMI-BLD33/studio/presentation | 4 +- .../CY8C6347FMI-BLD33/studio/view.xml | 110 +-- .../CY8C6347FMI-BLD43/base/view.xml | 30 +- .../PSoC6ABLE2/CY8C6347FMI-BLD43/info.xml | 10 +- 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+- .../CY8C6347FMI-BUD53/studio/view.xml | 110 +-- .../CY8C6347LQI-BLD52/base/view.xml | 30 +- .../PSoC6ABLE2/CY8C6347LQI-BLD52/info.xml | 10 +- .../CY8C6347LQI-BLD52/studio/presentation | 4 +- .../CY8C6347LQI-BLD52/studio/view.xml | 110 +-- .../PSoC6ABLE2/CY8C637BZI-BLD74/base/view.xml | 30 +- .../PSoC6ABLE2/CY8C637BZI-BLD74/info.xml | 10 +- .../CY8C637BZI-BLD74/studio/presentation | 4 +- .../CY8C637BZI-BLD74/studio/view.xml | 110 +-- .../PSoC6ABLE2/CY8C637BZI-MD76/base/view.xml | 30 +- .../MXS40/PSoC6ABLE2/CY8C637BZI-MD76/info.xml | 10 +- .../CY8C637BZI-MD76/studio/presentation | 4 +- .../CY8C637BZI-MD76/studio/view.xml | 110 +-- .../PSoC6ABLE2/CY8C637FMI-BLD73/base/view.xml | 30 +- .../PSoC6ABLE2/CY8C637FMI-BLD73/info.xml | 10 +- .../CY8C637FMI-BLD73/studio/presentation | 4 +- .../CY8C637FMI-BLD73/studio/view.xml | 110 +-- .../PSoC6ABLE2/CY8C68237BZ-BLE/base/view.xml | 30 +- .../MXS40/PSoC6ABLE2/CY8C68237BZ-BLE/info.xml | 10 +- .../CY8C68237BZ-BLE/studio/presentation | 4 +- .../CY8C68237BZ-BLE/studio/view.xml | 110 +-- .../PSoC6ABLE2/CY8C68237FM-BLE/base/view.xml | 30 +- .../MXS40/PSoC6ABLE2/CY8C68237FM-BLE/info.xml | 10 +- .../CY8C68237FM-BLE/studio/presentation | 4 +- .../CY8C68237FM-BLE/studio/view.xml | 110 +-- .../CYB06447BZI-BLD53/base/view.xml | 30 +- .../PSoC6ABLE2/CYB06447BZI-BLD53/info.xml | 10 +- .../CYB06447BZI-BLD53/studio/presentation | 4 +- .../CYB06447BZI-BLD53/studio/view.xml | 110 +-- .../CYB06447BZI-BLD54/base/view.xml | 30 +- .../PSoC6ABLE2/CYB06447BZI-BLD54/info.xml | 10 +- .../CYB06447BZI-BLD54/studio/presentation | 4 +- .../CYB06447BZI-BLD54/studio/view.xml | 110 +-- .../PSoC6ABLE2/CYB06447BZI-D54/base/view.xml | 30 +- .../MXS40/PSoC6ABLE2/CYB06447BZI-D54/info.xml | 10 +- .../CYB06447BZI-D54/studio/presentation | 4 +- .../CYB06447BZI-D54/studio/view.xml | 110 +-- .../PSoC6ABLE2/CYBLE-416045-02/base/view.xml | 30 +- .../MXS40/PSoC6ABLE2/CYBLE-416045-02/info.xml | 10 +- .../CYBLE-416045-02/studio/presentation | 4 +- .../CYBLE-416045-02/studio/view.xml | 108 +-- .../MXS40/PSoC6ABLE2/hobto/amuxbus.cydata | Bin 2873 -> 2877 bytes .../MXS40/PSoC6ABLE2/hobto/clocks.cydata | Bin 1529 -> 1565 bytes udd/devices/MXS40/PSoC6ABLE2/hobto/dsi.cydata | Bin 7193 -> 7273 bytes .../MXS40/PSoC6ABLE2/hobto/interrupts.cydata | Bin 2229 -> 2447 bytes .../MXS40/PSoC6ABLE2/hobto/ipblocks.cydata | Bin 16443 -> 16423 bytes .../MXS40/PSoC6ABLE2/hobto/pins.cydata | Bin 32867 -> 32827 bytes .../MXS40/PSoC6ABLE2/hobto/triggers.cydata | Bin 16443 -> 16423 bytes udd/devices/MXS40/PSoC6ABLE2/hobto/view.xml | 26 +- udd/devices/MXS40/PSoC6ABLE2/info.xml | 8 +- .../MXS40/PSoC6ABLE2/studio/analog.cysem | 11 +- .../MXS40/PSoC6ABLE2/studio/analog.cyvis | 10 +- .../PSoC6ABLE2/studio/analogResourceMap.txt | 2 +- .../studio/modules/module_43-SMT.cydata | Bin 1643 -> 1655 bytes .../PSoC6ABLE2/studio/product_links.list | 1 + udd/devices/MXS40/hobto/view.xml | 1 - udd/devices/MXS40/info.xml | 8 +- .../studio/connectivity/m4cpuss_v1-dw0.cydata | Bin 531 -> 531 bytes .../studio/connectivity/m4cpuss_v1-dw1.cydata | Bin 531 -> 531 bytes .../studio/connectivity/m4cpuss_v1.cydata | Bin 1703 -> 1713 bytes .../connectivity/m4cpuss_ver2_v1-dmac.cydata | Bin 531 -> 531 bytes .../connectivity/m4cpuss_ver2_v1-dw0.cydata | Bin 531 -> 531 bytes .../connectivity/m4cpuss_ver2_v1-dw1.cydata | Bin 531 -> 531 bytes .../connectivity/m4cpuss_ver2_v1.cydata | Bin 1823 -> 1837 bytes .../studio/connectivity/mxaudioss_v1.cydata | Bin 1331 -> 1339 bytes .../studio/connectivity/mxbless_v1.cydata | Bin 1131 -> 1137 bytes .../studio/connectivity/mxcan_s40s_v1.cydata | Bin 531 -> 531 bytes .../studio/connectivity/mxcsdv2_v1.cydata | Bin 1919 -> 1935 bytes .../studio/connectivity/mxefuse_v1.cydata | Bin 275 -> 275 bytes .../MXS40/studio/connectivity/mxlcd_v1.cydata | Bin 1199 -> 1199 bytes .../studio/connectivity/mxlcd_ver2_v1.cydata | Bin 1243 -> 1243 bytes .../studio/connectivity/mxlpcomp_s40.cydata | Bin 1481 -> 1505 bytes .../studio/connectivity/mxperi_v1.cydata | Bin 1113 -> 1145 bytes .../studio/connectivity/mxperi_ver2_v1.cydata | Bin 1145 -> 1177 bytes .../studio/connectivity/mxprofile_v1.cydata | Bin 531 -> 531 bytes .../connectivity/mxs40ioss_v1-port.cydata | Bin 4113 -> 4133 bytes .../studio/connectivity/mxs40ioss_v1.cydata | Bin 1749 -> 1767 bytes .../connectivity/mxs40ioss_v2-port.cydata | Bin 4121 -> 4141 bytes .../studio/connectivity/mxs40ioss_v2.cydata | Bin 1855 -> 1875 bytes .../connectivity/mxs40pass_v1-ctbm.cydata | Bin 2697 -> 2737 bytes .../connectivity/mxs40pass_v1-sar.cydata | Bin 1595 -> 1617 bytes .../connectivity/mxs40pass_v1-sarmux.cydata | Bin 2487 -> 2555 bytes .../studio/connectivity/mxs40pass_v1.cydata | Bin 2837 -> 2855 bytes .../connectivity/mxs40srss_v1-power.cydata | Bin 0 -> 531 bytes .../connectivity/mxs40srss_v1-sysclk.cydata | Bin 1941 -> 1961 bytes .../studio/connectivity/mxs40srss_v1.cydata | Bin 2289 -> 2221 bytes .../MXS40/studio/connectivity/mxscb_v1.cydata | Bin 531 -> 531 bytes .../studio/connectivity/mxsdhc_v1.cydata | Bin 531 -> 531 bytes .../studio/connectivity/mxsmif_v1.cydata | Bin 531 -> 531 bytes .../studio/connectivity/mxtcpwm_v1.cydata | Bin 1707 -> 1711 bytes .../connectivity/mxttcanfd_s40s_v1.cydata | Bin 1067 -> 1081 bytes .../MXS40/studio/connectivity/mxudb_v1.cydata | Bin 531 -> 531 bytes .../studio/connectivity/mxusbfs_v1.cydata | Bin 531 -> 531 bytes udd/devices/MXS40/studio/features.mk | 87 +-- udd/version.dat | 2 +- udd/version.xml | 2 +- version.xml | 2 +- 830 files changed, 21638 insertions(+), 12232 deletions(-) rename devices/{bsp/COMPONENT_MBED/linker => templates/COMPONENT_MBED/COMPONENT_CM0P}/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct (97%) rename devices/{bsp/COMPONENT_MBED/linker => templates/COMPONENT_MBED/COMPONENT_CM0P}/TOOLCHAIN_ARM/cy8c6xx6_cm0plus.sct (97%) rename devices/{bsp/COMPONENT_MBED/linker => templates/COMPONENT_MBED/COMPONENT_CM0P}/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct (97%) rename devices/{bsp/COMPONENT_MBED/linker => templates/COMPONENT_MBED/COMPONENT_CM0P}/TOOLCHAIN_ARM/cy8c6xx8_cm0plus.sct (97%) rename devices/{bsp/COMPONENT_MBED/linker => templates/COMPONENT_MBED/COMPONENT_CM0P}/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct (97%) create mode 100644 devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx5_cm0plus.sct create mode 100644 devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx7_cm0plus.sct create mode 100644 devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct rename devices/{bsp/COMPONENT_MBED/startup => templates/COMPONENT_MBED/COMPONENT_CM0P}/TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.S (90%) rename devices/{bsp/COMPONENT_MBED/startup => templates/COMPONENT_MBED/COMPONENT_CM0P}/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S (87%) rename devices/{bsp/COMPONENT_MBED/startup => templates/COMPONENT_MBED/COMPONENT_CM0P}/TOOLCHAIN_ARM/startup_psoc6_03_cm0plus.S (87%) rename devices/{bsp/COMPONENT_MBED/linker => templates/COMPONENT_MBED/COMPONENT_CM0P}/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm0plus.ld (99%) rename devices/{bsp/COMPONENT_MBED/linker => templates/COMPONENT_MBED/COMPONENT_CM0P}/TOOLCHAIN_GCC_ARM/cy8c6xx6_cm0plus.ld (99%) rename devices/{bsp/COMPONENT_MBED/linker => templates/COMPONENT_MBED/COMPONENT_CM0P}/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld (99%) rename devices/{bsp/COMPONENT_MBED/linker => templates/COMPONENT_MBED/COMPONENT_CM0P}/TOOLCHAIN_GCC_ARM/cy8c6xx8_cm0plus.ld (99%) rename devices/{bsp/COMPONENT_MBED/linker => templates/COMPONENT_MBED/COMPONENT_CM0P}/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld (99%) create mode 100644 devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xx5_cm0plus.ld create mode 100644 devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xx7_cm0plus.ld create mode 100644 devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xxa_cm0plus.ld rename devices/{bsp/COMPONENT_MBED/startup => templates/COMPONENT_MBED/COMPONENT_CM0P}/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm0plus.S (100%) rename devices/{bsp/COMPONENT_MBED/startup => templates/COMPONENT_MBED/COMPONENT_CM0P}/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm0plus.S (100%) rename devices/{bsp/COMPONENT_MBED/startup => templates/COMPONENT_MBED/COMPONENT_CM0P}/TOOLCHAIN_GCC_ARM/startup_psoc6_03_cm0plus.S (100%) rename devices/{bsp/COMPONENT_MBED/linker => templates/COMPONENT_MBED/COMPONENT_CM0P}/TOOLCHAIN_IAR/cy8c6xx5_cm0plus.icf (99%) rename devices/{bsp/COMPONENT_MBED/linker => templates/COMPONENT_MBED/COMPONENT_CM0P}/TOOLCHAIN_IAR/cy8c6xx6_cm0plus.icf (99%) rename devices/{bsp/COMPONENT_MBED/linker => templates/COMPONENT_MBED/COMPONENT_CM0P}/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf (99%) rename devices/{bsp/COMPONENT_MBED/linker => templates/COMPONENT_MBED/COMPONENT_CM0P}/TOOLCHAIN_IAR/cy8c6xx8_cm0plus.icf (99%) rename devices/{bsp/COMPONENT_MBED/linker => templates/COMPONENT_MBED/COMPONENT_CM0P}/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf (99%) create mode 100644 devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xx5_cm0plus.icf create mode 100644 devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xx7_cm0plus.icf create mode 100644 devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xxa_cm0plus.icf rename devices/{bsp/COMPONENT_MBED/startup => templates/COMPONENT_MBED/COMPONENT_CM0P}/TOOLCHAIN_IAR/startup_psoc6_01_cm0plus.S (100%) rename devices/{bsp/COMPONENT_MBED/startup => templates/COMPONENT_MBED/COMPONENT_CM0P}/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.S (100%) rename devices/{bsp/COMPONENT_MBED/startup => templates/COMPONENT_MBED/COMPONENT_CM0P}/TOOLCHAIN_IAR/startup_psoc6_03_cm0plus.S (100%) rename devices/{bsp/COMPONENT_MBED/startup => templates/COMPONENT_MBED/COMPONENT_CM0P}/system_psoc6_cm0plus.c (69%) rename devices/{bsp/COMPONENT_MBED/linker => templates/COMPONENT_MBED/COMPONENT_CM4}/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct (97%) rename devices/{bsp/COMPONENT_MBED/linker => templates/COMPONENT_MBED/COMPONENT_CM4}/TOOLCHAIN_ARM/cy8c6xx6_cm4_dual.sct (97%) rename devices/{bsp/COMPONENT_MBED/linker => templates/COMPONENT_MBED/COMPONENT_CM4}/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct (97%) rename devices/{bsp/COMPONENT_MBED/linker => templates/COMPONENT_MBED/COMPONENT_CM4}/TOOLCHAIN_ARM/cy8c6xx8_cm4_dual.sct (97%) rename devices/{bsp/COMPONENT_MBED/linker => templates/COMPONENT_MBED/COMPONENT_CM4}/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct (97%) create mode 100644 devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx5_cm4.sct rename devices/{bsp/COMPONENT_MBED/linker/TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct => templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4.sct} (91%) rename devices/{bsp/COMPONENT_MBED/linker/TOOLCHAIN_ARM/cyb06xxa_cm4_dual.sct => templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4.sct} (91%) rename devices/{bsp/COMPONENT_MBED/startup => templates/COMPONENT_MBED/COMPONENT_CM4}/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S (96%) rename devices/{bsp/COMPONENT_MBED/startup => templates/COMPONENT_MBED/COMPONENT_CM4}/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S (97%) rename devices/{bsp/COMPONENT_MBED/startup => templates/COMPONENT_MBED/COMPONENT_CM4}/TOOLCHAIN_ARM/startup_psoc6_03_cm4.S (97%) rename devices/{bsp/COMPONENT_MBED/linker => templates/COMPONENT_MBED/COMPONENT_CM4}/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm4_dual.ld (98%) rename devices/{bsp/COMPONENT_MBED/linker => templates/COMPONENT_MBED/COMPONENT_CM4}/TOOLCHAIN_GCC_ARM/cy8c6xx6_cm4_dual.ld (98%) rename devices/{bsp/COMPONENT_MBED/linker => templates/COMPONENT_MBED/COMPONENT_CM4}/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld (98%) rename devices/{bsp/COMPONENT_MBED/linker => templates/COMPONENT_MBED/COMPONENT_CM4}/TOOLCHAIN_GCC_ARM/cy8c6xx8_cm4_dual.ld (98%) rename devices/{bsp/COMPONENT_MBED/linker => templates/COMPONENT_MBED/COMPONENT_CM4}/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld (98%) create mode 100644 devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx5_cm4.ld rename devices/{bsp/COMPONENT_MBED/linker/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4_dual.ld => templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4.ld} (94%) rename devices/{bsp/COMPONENT_MBED/linker/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4_dual.ld => templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4.ld} (94%) rename devices/{bsp/COMPONENT_MBED/startup => templates/COMPONENT_MBED/COMPONENT_CM4}/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S (100%) rename devices/{bsp/COMPONENT_MBED/startup => templates/COMPONENT_MBED/COMPONENT_CM4}/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S (100%) rename devices/{bsp/COMPONENT_MBED/startup => templates/COMPONENT_MBED/COMPONENT_CM4}/TOOLCHAIN_GCC_ARM/startup_psoc6_03_cm4.S (100%) rename devices/{bsp/COMPONENT_MBED/linker => templates/COMPONENT_MBED/COMPONENT_CM4}/TOOLCHAIN_IAR/cy8c6xx5_cm4_dual.icf (99%) rename devices/{bsp/COMPONENT_MBED/linker => templates/COMPONENT_MBED/COMPONENT_CM4}/TOOLCHAIN_IAR/cy8c6xx6_cm4_dual.icf (99%) rename devices/{bsp/COMPONENT_MBED/linker => templates/COMPONENT_MBED/COMPONENT_CM4}/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf (99%) rename devices/{bsp/COMPONENT_MBED/linker => templates/COMPONENT_MBED/COMPONENT_CM4}/TOOLCHAIN_IAR/cy8c6xx8_cm4_dual.icf (99%) rename devices/{bsp/COMPONENT_MBED/linker => templates/COMPONENT_MBED/COMPONENT_CM4}/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf (99%) create mode 100644 devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx5_cm4.icf rename devices/{bsp/COMPONENT_MBED/linker/TOOLCHAIN_IAR/cyb06xx7_cm4_dual.icf => templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx7_cm4.icf} (94%) rename devices/{bsp/COMPONENT_MBED/linker/TOOLCHAIN_IAR/cyb06xxa_cm4_dual.icf => templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xxa_cm4.icf} (94%) rename devices/{bsp/COMPONENT_MBED/startup => templates/COMPONENT_MBED/COMPONENT_CM4}/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S (100%) rename devices/{bsp/COMPONENT_MBED/startup => templates/COMPONENT_MBED/COMPONENT_CM4}/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S (100%) rename devices/{bsp/COMPONENT_MBED/startup => templates/COMPONENT_MBED/COMPONENT_CM4}/TOOLCHAIN_IAR/startup_psoc6_03_cm4.S (100%) rename devices/{bsp/COMPONENT_MTB/startup => templates/COMPONENT_MBED/COMPONENT_CM4}/system_psoc6_cm4.c (63%) rename devices/{bsp/COMPONENT_MBED/startup => templates/COMPONENT_MBED}/system_psoc6.h (91%) rename devices/{bsp/COMPONENT_MTB/linker => templates/COMPONENT_MTB/COMPONENT_CM0P}/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct (98%) rename devices/{bsp/COMPONENT_MTB/linker => templates/COMPONENT_MTB/COMPONENT_CM0P}/TOOLCHAIN_ARM/cy8c6xx6_cm0plus.sct (98%) rename devices/{bsp/COMPONENT_MTB/linker => templates/COMPONENT_MTB/COMPONENT_CM0P}/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct (98%) rename devices/{bsp/COMPONENT_MTB/linker => templates/COMPONENT_MTB/COMPONENT_CM0P}/TOOLCHAIN_ARM/cy8c6xx8_cm0plus.sct (98%) rename devices/{bsp/COMPONENT_MTB/linker => templates/COMPONENT_MTB/COMPONENT_CM0P}/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct (98%) create mode 100644 devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx5_cm0plus.sct create mode 100644 devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx7_cm0plus.sct create mode 100644 devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct rename devices/{bsp/COMPONENT_MTB/startup => templates/COMPONENT_MTB/COMPONENT_CM0P}/TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.s (100%) rename devices/{bsp/COMPONENT_MTB/startup => templates/COMPONENT_MTB/COMPONENT_CM0P}/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.s (100%) rename devices/{bsp/COMPONENT_MTB/startup => templates/COMPONENT_MTB/COMPONENT_CM0P}/TOOLCHAIN_ARM/startup_psoc6_03_cm0plus.s (100%) rename devices/{bsp/COMPONENT_MTB/startup => templates/COMPONENT_MTB/COMPONENT_CM0P}/TOOLCHAIN_A_Clang/startup_psoc6_01_cm0plus.S (85%) rename devices/{bsp/COMPONENT_MTB/startup => templates/COMPONENT_MTB/COMPONENT_CM0P}/TOOLCHAIN_A_Clang/startup_psoc6_02_cm0plus.S (81%) rename devices/{bsp/COMPONENT_MTB/startup => templates/COMPONENT_MTB/COMPONENT_CM0P}/TOOLCHAIN_A_Clang/startup_psoc6_03_cm0plus.S (81%) rename devices/{bsp/COMPONENT_MTB/linker => templates/COMPONENT_MTB/COMPONENT_CM0P}/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm0plus.ld (99%) rename devices/{bsp/COMPONENT_MTB/linker => templates/COMPONENT_MTB/COMPONENT_CM0P}/TOOLCHAIN_GCC_ARM/cy8c6xx6_cm0plus.ld (99%) rename devices/{bsp/COMPONENT_MTB/linker => templates/COMPONENT_MTB/COMPONENT_CM0P}/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld (99%) rename devices/{bsp/COMPONENT_MTB/linker => templates/COMPONENT_MTB/COMPONENT_CM0P}/TOOLCHAIN_GCC_ARM/cy8c6xx8_cm0plus.ld (99%) rename devices/{bsp/COMPONENT_MTB/linker => templates/COMPONENT_MTB/COMPONENT_CM0P}/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld (99%) create mode 100644 devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xx5_cm0plus.ld create mode 100644 devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xx7_cm0plus.ld create mode 100644 devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xxa_cm0plus.ld rename devices/{bsp/COMPONENT_MTB/startup => templates/COMPONENT_MTB/COMPONENT_CM0P}/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm0plus.S (100%) rename devices/{bsp/COMPONENT_MTB/startup => templates/COMPONENT_MTB/COMPONENT_CM0P}/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm0plus.S (100%) rename devices/{bsp/COMPONENT_MTB/startup => templates/COMPONENT_MTB/COMPONENT_CM0P}/TOOLCHAIN_GCC_ARM/startup_psoc6_03_cm0plus.S (100%) rename devices/{bsp/COMPONENT_MTB/linker => templates/COMPONENT_MTB/COMPONENT_CM0P}/TOOLCHAIN_IAR/cy8c6xx5_cm0plus.icf (99%) rename devices/{bsp/COMPONENT_MTB/linker => templates/COMPONENT_MTB/COMPONENT_CM0P}/TOOLCHAIN_IAR/cy8c6xx6_cm0plus.icf (99%) rename devices/{bsp/COMPONENT_MTB/linker => templates/COMPONENT_MTB/COMPONENT_CM0P}/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf (99%) rename devices/{bsp/COMPONENT_MTB/linker => templates/COMPONENT_MTB/COMPONENT_CM0P}/TOOLCHAIN_IAR/cy8c6xx8_cm0plus.icf (99%) rename devices/{bsp/COMPONENT_MTB/linker => templates/COMPONENT_MTB/COMPONENT_CM0P}/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf (99%) create mode 100644 devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xx5_cm0plus.icf create mode 100644 devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xx7_cm0plus.icf create mode 100644 devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xxa_cm0plus.icf rename devices/{bsp/COMPONENT_MTB/startup => templates/COMPONENT_MTB/COMPONENT_CM0P}/TOOLCHAIN_IAR/startup_psoc6_01_cm0plus.s (98%) rename devices/{bsp/COMPONENT_MTB/startup => templates/COMPONENT_MTB/COMPONENT_CM0P}/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.s (98%) rename devices/{bsp/COMPONENT_MTB/startup => templates/COMPONENT_MTB/COMPONENT_CM0P}/TOOLCHAIN_IAR/startup_psoc6_03_cm0plus.s (98%) rename devices/{bsp/COMPONENT_MTB/startup => templates/COMPONENT_MTB/COMPONENT_CM0P}/system_psoc6_cm0plus.c (69%) rename devices/{bsp/COMPONENT_MTB/linker => templates/COMPONENT_MTB/COMPONENT_CM4}/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct (98%) rename devices/{bsp/COMPONENT_MTB/linker => templates/COMPONENT_MTB/COMPONENT_CM4}/TOOLCHAIN_ARM/cy8c6xx6_cm4.sct (99%) rename devices/{bsp/COMPONENT_MTB/linker => templates/COMPONENT_MTB/COMPONENT_CM4}/TOOLCHAIN_ARM/cy8c6xx6_cm4_dual.sct (98%) rename devices/{bsp/COMPONENT_MTB/linker => templates/COMPONENT_MTB/COMPONENT_CM4}/TOOLCHAIN_ARM/cy8c6xx7_cm4.sct (99%) rename devices/{bsp/COMPONENT_MTB/linker => templates/COMPONENT_MTB/COMPONENT_CM4}/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct (98%) rename devices/{bsp/COMPONENT_MTB/linker => templates/COMPONENT_MTB/COMPONENT_CM4}/TOOLCHAIN_ARM/cy8c6xx8_cm4_dual.sct (98%) rename devices/{bsp/COMPONENT_MTB/linker => templates/COMPONENT_MTB/COMPONENT_CM4}/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct (98%) create mode 100644 devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx5_cm4.sct create mode 100644 devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx5_cm4_dual.sct create mode 100644 devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4.sct rename devices/{bsp/COMPONENT_MTB/linker => templates/COMPONENT_MTB/COMPONENT_CM4}/TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct (93%) create mode 100644 devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4.sct rename devices/{bsp/COMPONENT_MTB/linker => templates/COMPONENT_MTB/COMPONENT_CM4}/TOOLCHAIN_ARM/cyb06xxa_cm4_dual.sct (93%) rename devices/{bsp/COMPONENT_MTB/startup => templates/COMPONENT_MTB/COMPONENT_CM4}/TOOLCHAIN_ARM/startup_psoc6_01_cm4.s (100%) rename devices/{bsp/COMPONENT_MTB/startup => templates/COMPONENT_MTB/COMPONENT_CM4}/TOOLCHAIN_ARM/startup_psoc6_02_cm4.s (100%) rename devices/{bsp/COMPONENT_MTB/startup => templates/COMPONENT_MTB/COMPONENT_CM4}/TOOLCHAIN_ARM/startup_psoc6_03_cm4.s (100%) rename devices/{bsp/COMPONENT_MTB/linker => templates/COMPONENT_MTB/COMPONENT_CM4}/TOOLCHAIN_A_Clang/cy8c6xx5_cm4_dual.mk (96%) rename devices/{bsp/COMPONENT_MTB/linker => templates/COMPONENT_MTB/COMPONENT_CM4}/TOOLCHAIN_A_Clang/cy8c6xx6_cm4.mk (96%) rename devices/{bsp/COMPONENT_MTB/linker => templates/COMPONENT_MTB/COMPONENT_CM4}/TOOLCHAIN_A_Clang/cy8c6xx6_cm4_dual.mk (96%) rename devices/{bsp/COMPONENT_MTB/linker => templates/COMPONENT_MTB/COMPONENT_CM4}/TOOLCHAIN_A_Clang/cy8c6xx7_cm4.mk (96%) rename devices/{bsp/COMPONENT_MTB/linker => templates/COMPONENT_MTB/COMPONENT_CM4}/TOOLCHAIN_A_Clang/cy8c6xx7_cm4_dual.mk (96%) rename devices/{bsp/COMPONENT_MTB/linker => templates/COMPONENT_MTB/COMPONENT_CM4}/TOOLCHAIN_A_Clang/cy8c6xx8_cm4_dual.mk (96%) rename devices/{bsp/COMPONENT_MTB/linker => templates/COMPONENT_MTB/COMPONENT_CM4}/TOOLCHAIN_A_Clang/cy8c6xxa_cm4_dual.mk (96%) rename devices/{bsp/COMPONENT_MTB/startup => templates/COMPONENT_MTB/COMPONENT_CM4}/TOOLCHAIN_A_Clang/startup_psoc6_01_cm4.S (94%) rename devices/{bsp/COMPONENT_MTB/startup => templates/COMPONENT_MTB/COMPONENT_CM4}/TOOLCHAIN_A_Clang/startup_psoc6_02_cm4.S (95%) rename devices/{bsp/COMPONENT_MTB/startup => templates/COMPONENT_MTB/COMPONENT_CM4}/TOOLCHAIN_A_Clang/startup_psoc6_03_cm4.S (95%) rename devices/{bsp/COMPONENT_MTB/linker => templates/COMPONENT_MTB/COMPONENT_CM4}/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm4_dual.ld (98%) rename devices/{bsp/COMPONENT_MTB/linker => templates/COMPONENT_MTB/COMPONENT_CM4}/TOOLCHAIN_GCC_ARM/cy8c6xx6_cm4.ld (99%) rename devices/{bsp/COMPONENT_MTB/linker => templates/COMPONENT_MTB/COMPONENT_CM4}/TOOLCHAIN_GCC_ARM/cy8c6xx6_cm4_dual.ld (98%) rename devices/{bsp/COMPONENT_MTB/linker => templates/COMPONENT_MTB/COMPONENT_CM4}/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4.ld (99%) rename devices/{bsp/COMPONENT_MTB/linker => templates/COMPONENT_MTB/COMPONENT_CM4}/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld (98%) rename devices/{bsp/COMPONENT_MTB/linker => templates/COMPONENT_MTB/COMPONENT_CM4}/TOOLCHAIN_GCC_ARM/cy8c6xx8_cm4_dual.ld (98%) rename devices/{bsp/COMPONENT_MTB/linker => templates/COMPONENT_MTB/COMPONENT_CM4}/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld (98%) create mode 100644 devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx5_cm4.ld create mode 100644 devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx5_cm4_dual.ld create mode 100644 devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4.ld rename devices/{bsp/COMPONENT_MTB/linker => templates/COMPONENT_MTB/COMPONENT_CM4}/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4_dual.ld (96%) create mode 100644 devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4.ld rename devices/{bsp/COMPONENT_MTB/linker => templates/COMPONENT_MTB/COMPONENT_CM4}/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4_dual.ld (96%) rename devices/{bsp/COMPONENT_MTB/startup => templates/COMPONENT_MTB/COMPONENT_CM4}/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S (100%) rename devices/{bsp/COMPONENT_MTB/startup => templates/COMPONENT_MTB/COMPONENT_CM4}/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S (100%) rename devices/{bsp/COMPONENT_MTB/startup => templates/COMPONENT_MTB/COMPONENT_CM4}/TOOLCHAIN_GCC_ARM/startup_psoc6_03_cm4.S (100%) rename devices/{bsp/COMPONENT_MTB/linker => templates/COMPONENT_MTB/COMPONENT_CM4}/TOOLCHAIN_IAR/cy8c6xx5_cm4_dual.icf (99%) rename devices/{bsp/COMPONENT_MTB/linker => templates/COMPONENT_MTB/COMPONENT_CM4}/TOOLCHAIN_IAR/cy8c6xx6_cm4.icf (99%) rename devices/{bsp/COMPONENT_MTB/linker => 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mode 100644 udd/devices/MXS40/PSoC6ABLE2/studio/product_links.list delete mode 100644 udd/devices/MXS40/hobto/view.xml create mode 100644 udd/devices/MXS40/studio/connectivity/mxs40srss_v1-power.cydata diff --git a/README.md b/README.md index 05b54d1..5f18753 100644 --- a/README.md +++ b/README.md @@ -6,6 +6,10 @@ The PDL integrates device header files, startup code, and peripheral drivers into a single package. The drivers abstract the hardware functions into a set of easy-to-use APIs. These are fully documented in the [PDL API Reference Manual](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/index.html). +This version of the PDL is compatible with ModusToolbox. It is not compatible +with PSoC Creator. The most recent PSoC Creator-compatible version of the PDL +is [available here](https://www.cypress.com/documentation/software-and-drivers/peripheral-driver-library-pdl). + ### Features * Includes all the updates made to the peripheral drivers for ModusToolbox™ software * Contains standard set of PSoC® 6 digital and analog peripheral drivers that enable rapid peripheral software development in third-party IDEs diff --git a/RELEASE.md b/RELEASE.md index 2eb1fec..246c6bd 100644 --- a/RELEASE.md +++ b/RELEASE.md @@ -1,19 +1,37 @@ -# PSoC 6 Peripheral Driver Library v1.3.1 +# PSoC 6 Peripheral Driver Library v1.4.0 Please refer to the [README.md](./README.md) and the [PDL API Reference Manual](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/index.html) for a complete description of the Peripheral Driver Library. ### New Features +* The structure of BSP startup templates directory (devices/templates) is updated to match the BSP layout. +* The updated core-lib is reused - see [SysLib changelog](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__syslib.html) for details. +* Removed redundant legacy PSoC Creator-compatibility macros. +* The startup code reuses sysclk driver API - see [Startup changelog](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__system__config.html) for details. + +Updated Personalities +* CSD +* Power +* SegLCD +* WiFi +Updated the configurators launch parameters in CSD and SegLCD personalities: switched from GUI to console applications for regenerating the source code without opening the configurator itself. This improves the user experience, performance, and enables using machines without a GUI. +The Power personality code generation is corrected due to the customer's request. +The TCP Keepalive Offload feature support is added to the WiFi Low Power Assistant (LPA) personality. + Updated Drivers -* [SysInt 1.30](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__sysint.html) -* [SysPm 4.40](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__syspm.html) -* [USBFS 2.20](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__usbfs__dev__drv.html) +* [BLE_CLK 3.30](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__ble__clk.html) +* [SCB 2.40](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__system__scb.html) +* [Startup 2.70](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__system__config.html) +* [SysClk 1.50](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__sysclk.html) +* [SysLib 2.50](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__syslib.html) +* [SysPm 4.50](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__syspm.html) +* [WDT 1.20](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__wdt.html) Drivers with patch version updates -* [CAN FD 1.0.1](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__canfd.html) -* [Flash 3.30.2](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__flash.html) -* [Prot 1.30.1](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__prot.html) -* [SysClk 1.40.2](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__sysclk.html) - +* [Flash 3.30.3](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__flash.html) +* [SAR 1.20.2](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__sar.html) +* [SegLCD 1.0.1](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__seglcd.html) +* [SMIF 1.40.1](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__smif.html) +* [TrigMux 1.20.1](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__trigmux.html) ### Known Issues None diff --git a/devices/include/cyb06445lqi_s3d42.h b/devices/include/cyb06445lqi_s3d42.h index 8b23c5c..fac6b9f 100644 --- a/devices/include/cyb06445lqi_s3d42.h +++ b/devices/include/cyb06445lqi_s3d42.h @@ -5,7 +5,7 @@ * CYB06445LQI-S3D42 device header * * \note -* Generator version: 1.5.0.1292 +* Generator version: 1.5.0.1314 * ******************************************************************************** * \copyright @@ -423,7 +423,7 @@ typedef enum { #define CY_SRAM_BASE 0x08000000UL #define CY_SRAM_SIZE 0x00040000UL #define CY_FLASH_BASE 0x10000000UL -#define CY_FLASH_SIZE 0x00080000UL +#define CY_FLASH_SIZE 0x00070000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL #define CY_XIP_BASE 0x18000000UL diff --git a/devices/include/gpio_psoc6_01_104_m_csp_ble.h b/devices/include/gpio_psoc6_01_104_m_csp_ble.h index 0dbcf02..ab43a2f 100644 --- a/devices/include/gpio_psoc6_01_104_m_csp_ble.h +++ b/devices/include/gpio_psoc6_01_104_m_csp_ble.h @@ -5,7 +5,7 @@ * PSoC6_01 device GPIO header for 104-M-CSP-BLE package * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.5.0.1304 * ******************************************************************************** * \copyright @@ -63,12 +63,12 @@ typedef enum { AMUX_SPLIT_CTL_0 = 0x0000u, /* Left = AMUXBUS_ADFT0_VDDD; Right = AMUXBUS_MAIN */ AMUX_SPLIT_CTL_1 = 0x0001u, /* Left = AMUXBUS_MAIN; Right = AMUXBUS_NOISY */ - AMUX_SPLIT_CTL_7 = 0x0007u, /* Left = AMUXBUS_ADFT1_VDDD; Right = AMUXBUS_NOISY */ AMUX_SPLIT_CTL_2 = 0x0002u, /* Left = AMUXBUS_CSD0; Right = AMUXBUS_NOISY */ AMUX_SPLIT_CTL_3 = 0x0003u, /* Left = AMUXBUS_VDDIO_1; Right = AMUXBUS_CSD0 */ AMUX_SPLIT_CTL_4 = 0x0004u, /* Left = AMUXBUS_CSD1; Right = AMUXBUS_CSD0 */ AMUX_SPLIT_CTL_5 = 0x0005u, /* Left = AMUXBUS_SAR; Right = AMUXBUS_CSD1 */ AMUX_SPLIT_CTL_6 = 0x0006u, /* Left = AMUXBUS_SAR; Right = AMUXBUS_MAIN */ + AMUX_SPLIT_CTL_7 = 0x0007u, /* Left = AMUXBUS_ADFT1_VDDD; Right = AMUXBUS_NOISY */ AMUX_SPLIT_CTL_8 = 0x0008u /* Left = AMUXBUS_ANALOG_VDDD; Right = AMUXBUS_ANALOG_VDDA */ } cy_en_amux_split_t; diff --git a/devices/include/gpio_psoc6_01_104_m_csp_ble_usb.h b/devices/include/gpio_psoc6_01_104_m_csp_ble_usb.h index 0c56c6d..cc86612 100644 --- a/devices/include/gpio_psoc6_01_104_m_csp_ble_usb.h +++ b/devices/include/gpio_psoc6_01_104_m_csp_ble_usb.h @@ -5,7 +5,7 @@ * PSoC6_01 device GPIO header for 104-M-CSP-BLE-USB package * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.5.0.1304 * ******************************************************************************** * \copyright @@ -63,12 +63,12 @@ typedef enum { AMUX_SPLIT_CTL_0 = 0x0000u, /* Left = AMUXBUS_ADFT0_VDDD; Right = AMUXBUS_MAIN */ AMUX_SPLIT_CTL_1 = 0x0001u, /* Left = AMUXBUS_MAIN; Right = AMUXBUS_NOISY */ - AMUX_SPLIT_CTL_7 = 0x0007u, /* Left = AMUXBUS_ADFT1_VDDD; Right = AMUXBUS_NOISY */ AMUX_SPLIT_CTL_2 = 0x0002u, /* Left = AMUXBUS_CSD0; Right = AMUXBUS_NOISY */ AMUX_SPLIT_CTL_3 = 0x0003u, /* Left = AMUXBUS_VDDIO_1; Right = AMUXBUS_CSD0 */ AMUX_SPLIT_CTL_4 = 0x0004u, /* Left = AMUXBUS_CSD1; Right = AMUXBUS_CSD0 */ AMUX_SPLIT_CTL_5 = 0x0005u, /* Left = AMUXBUS_SAR; Right = AMUXBUS_CSD1 */ AMUX_SPLIT_CTL_6 = 0x0006u, /* Left = AMUXBUS_SAR; Right = AMUXBUS_MAIN */ + AMUX_SPLIT_CTL_7 = 0x0007u, /* Left = AMUXBUS_ADFT1_VDDD; Right = AMUXBUS_NOISY */ AMUX_SPLIT_CTL_8 = 0x0008u /* Left = AMUXBUS_ANALOG_VDDD; Right = AMUXBUS_ANALOG_VDDA */ } cy_en_amux_split_t; diff --git a/devices/include/gpio_psoc6_01_116_bga_ble.h b/devices/include/gpio_psoc6_01_116_bga_ble.h index 6682218..2c9b4f4 100644 --- a/devices/include/gpio_psoc6_01_116_bga_ble.h +++ b/devices/include/gpio_psoc6_01_116_bga_ble.h @@ -5,7 +5,7 @@ * PSoC6_01 device GPIO header for 116-BGA-BLE package * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.5.0.1304 * ******************************************************************************** * \copyright @@ -63,12 +63,12 @@ typedef enum { AMUX_SPLIT_CTL_0 = 0x0000u, /* Left = AMUXBUS_ADFT0_VDDD; Right = AMUXBUS_MAIN */ AMUX_SPLIT_CTL_1 = 0x0001u, /* Left = AMUXBUS_MAIN; Right = AMUXBUS_NOISY */ - AMUX_SPLIT_CTL_7 = 0x0007u, /* Left = AMUXBUS_ADFT1_VDDD; Right = AMUXBUS_NOISY */ AMUX_SPLIT_CTL_2 = 0x0002u, /* Left = AMUXBUS_CSD0; Right = AMUXBUS_NOISY */ AMUX_SPLIT_CTL_3 = 0x0003u, /* Left = AMUXBUS_VDDIO_1; Right = AMUXBUS_CSD0 */ AMUX_SPLIT_CTL_4 = 0x0004u, /* Left = AMUXBUS_CSD1; Right = AMUXBUS_CSD0 */ AMUX_SPLIT_CTL_5 = 0x0005u, /* Left = AMUXBUS_SAR; Right = AMUXBUS_CSD1 */ AMUX_SPLIT_CTL_6 = 0x0006u, /* Left = AMUXBUS_SAR; Right = AMUXBUS_MAIN */ + AMUX_SPLIT_CTL_7 = 0x0007u, /* Left = AMUXBUS_ADFT1_VDDD; Right = AMUXBUS_NOISY */ AMUX_SPLIT_CTL_8 = 0x0008u /* Left = AMUXBUS_ANALOG_VDDD; Right = AMUXBUS_ANALOG_VDDA */ } cy_en_amux_split_t; diff --git a/devices/include/gpio_psoc6_01_116_bga_usb.h b/devices/include/gpio_psoc6_01_116_bga_usb.h index 77a07a4..08e3996 100644 --- a/devices/include/gpio_psoc6_01_116_bga_usb.h +++ b/devices/include/gpio_psoc6_01_116_bga_usb.h @@ -5,7 +5,7 @@ * PSoC6_01 device GPIO header for 116-BGA-USB package * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.5.0.1304 * ******************************************************************************** * \copyright @@ -63,12 +63,12 @@ typedef enum { AMUX_SPLIT_CTL_0 = 0x0000u, /* Left = AMUXBUS_ADFT0_VDDD; Right = AMUXBUS_MAIN */ AMUX_SPLIT_CTL_1 = 0x0001u, /* Left = AMUXBUS_MAIN; Right = AMUXBUS_NOISY */ - AMUX_SPLIT_CTL_7 = 0x0007u, /* Left = AMUXBUS_ADFT1_VDDD; Right = AMUXBUS_NOISY */ AMUX_SPLIT_CTL_2 = 0x0002u, /* Left = AMUXBUS_CSD0; Right = AMUXBUS_NOISY */ AMUX_SPLIT_CTL_3 = 0x0003u, /* Left = AMUXBUS_VDDIO_1; Right = AMUXBUS_CSD0 */ AMUX_SPLIT_CTL_4 = 0x0004u, /* Left = AMUXBUS_CSD1; Right = AMUXBUS_CSD0 */ AMUX_SPLIT_CTL_5 = 0x0005u, /* Left = AMUXBUS_SAR; Right = AMUXBUS_CSD1 */ AMUX_SPLIT_CTL_6 = 0x0006u, /* Left = AMUXBUS_SAR; Right = AMUXBUS_MAIN */ + AMUX_SPLIT_CTL_7 = 0x0007u, /* Left = AMUXBUS_ADFT1_VDDD; Right = AMUXBUS_NOISY */ AMUX_SPLIT_CTL_8 = 0x0008u /* Left = AMUXBUS_ANALOG_VDDD; Right = AMUXBUS_ANALOG_VDDA */ } cy_en_amux_split_t; diff --git a/devices/include/gpio_psoc6_01_124_bga.h b/devices/include/gpio_psoc6_01_124_bga.h index 2816a3c..f1f07c9 100644 --- a/devices/include/gpio_psoc6_01_124_bga.h +++ b/devices/include/gpio_psoc6_01_124_bga.h @@ -5,7 +5,7 @@ * PSoC6_01 device GPIO header for 124-BGA package * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.5.0.1304 * ******************************************************************************** * \copyright @@ -63,12 +63,12 @@ typedef enum { AMUX_SPLIT_CTL_0 = 0x0000u, /* Left = AMUXBUS_ADFT0_VDDD; Right = AMUXBUS_MAIN */ AMUX_SPLIT_CTL_1 = 0x0001u, /* Left = AMUXBUS_MAIN; Right = AMUXBUS_NOISY */ - AMUX_SPLIT_CTL_7 = 0x0007u, /* Left = AMUXBUS_ADFT1_VDDD; Right = AMUXBUS_NOISY */ AMUX_SPLIT_CTL_2 = 0x0002u, /* Left = AMUXBUS_CSD0; Right = AMUXBUS_NOISY */ AMUX_SPLIT_CTL_3 = 0x0003u, /* Left = AMUXBUS_VDDIO_1; Right = AMUXBUS_CSD0 */ AMUX_SPLIT_CTL_4 = 0x0004u, /* Left = AMUXBUS_CSD1; Right = AMUXBUS_CSD0 */ AMUX_SPLIT_CTL_5 = 0x0005u, /* Left = AMUXBUS_SAR; Right = AMUXBUS_CSD1 */ AMUX_SPLIT_CTL_6 = 0x0006u, /* Left = AMUXBUS_SAR; Right = AMUXBUS_MAIN */ + AMUX_SPLIT_CTL_7 = 0x0007u, /* Left = AMUXBUS_ADFT1_VDDD; Right = AMUXBUS_NOISY */ AMUX_SPLIT_CTL_8 = 0x0008u /* Left = AMUXBUS_ANALOG_VDDD; Right = AMUXBUS_ANALOG_VDDA */ } cy_en_amux_split_t; diff --git a/devices/include/gpio_psoc6_01_124_bga_sip.h b/devices/include/gpio_psoc6_01_124_bga_sip.h index c5c91ad..15c7230 100644 --- a/devices/include/gpio_psoc6_01_124_bga_sip.h +++ b/devices/include/gpio_psoc6_01_124_bga_sip.h @@ -5,7 +5,7 @@ * PSoC6_01 device GPIO header for 124-BGA-SIP package * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.5.0.1304 * ******************************************************************************** * \copyright @@ -63,12 +63,12 @@ typedef enum { AMUX_SPLIT_CTL_0 = 0x0000u, /* Left = AMUXBUS_ADFT0_VDDD; Right = AMUXBUS_MAIN */ AMUX_SPLIT_CTL_1 = 0x0001u, /* Left = AMUXBUS_MAIN; Right = AMUXBUS_NOISY */ - AMUX_SPLIT_CTL_7 = 0x0007u, /* Left = AMUXBUS_ADFT1_VDDD; Right = AMUXBUS_NOISY */ AMUX_SPLIT_CTL_2 = 0x0002u, /* Left = AMUXBUS_CSD0; Right = AMUXBUS_NOISY */ AMUX_SPLIT_CTL_3 = 0x0003u, /* Left = AMUXBUS_VDDIO_1; Right = AMUXBUS_CSD0 */ AMUX_SPLIT_CTL_4 = 0x0004u, /* Left = AMUXBUS_CSD1; Right = AMUXBUS_CSD0 */ AMUX_SPLIT_CTL_5 = 0x0005u, /* Left = AMUXBUS_SAR; Right = AMUXBUS_CSD1 */ AMUX_SPLIT_CTL_6 = 0x0006u, /* Left = AMUXBUS_SAR; Right = AMUXBUS_MAIN */ + AMUX_SPLIT_CTL_7 = 0x0007u, /* Left = AMUXBUS_ADFT1_VDDD; Right = AMUXBUS_NOISY */ AMUX_SPLIT_CTL_8 = 0x0008u /* Left = AMUXBUS_ANALOG_VDDD; Right = AMUXBUS_ANALOG_VDDA */ } cy_en_amux_split_t; diff --git a/devices/include/gpio_psoc6_01_43_smt.h b/devices/include/gpio_psoc6_01_43_smt.h index 7bb2963..fca88f2 100644 --- a/devices/include/gpio_psoc6_01_43_smt.h +++ b/devices/include/gpio_psoc6_01_43_smt.h @@ -5,7 +5,7 @@ * PSoC6_01 device GPIO header for 43-SMT package * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.5.0.1304 * ******************************************************************************** * \copyright @@ -63,12 +63,12 @@ typedef enum { AMUX_SPLIT_CTL_0 = 0x0000u, /* Left = AMUXBUS_ADFT0_VDDD; Right = AMUXBUS_MAIN */ AMUX_SPLIT_CTL_1 = 0x0001u, /* Left = AMUXBUS_MAIN; Right = AMUXBUS_NOISY */ - AMUX_SPLIT_CTL_7 = 0x0007u, /* Left = AMUXBUS_ADFT1_VDDD; Right = AMUXBUS_NOISY */ AMUX_SPLIT_CTL_2 = 0x0002u, /* Left = AMUXBUS_CSD0; Right = AMUXBUS_NOISY */ AMUX_SPLIT_CTL_3 = 0x0003u, /* Left = AMUXBUS_VDDIO_1; Right = AMUXBUS_CSD0 */ AMUX_SPLIT_CTL_4 = 0x0004u, /* Left = AMUXBUS_CSD1; Right = AMUXBUS_CSD0 */ AMUX_SPLIT_CTL_5 = 0x0005u, /* Left = AMUXBUS_SAR; Right = AMUXBUS_CSD1 */ AMUX_SPLIT_CTL_6 = 0x0006u, /* Left = AMUXBUS_SAR; Right = AMUXBUS_MAIN */ + AMUX_SPLIT_CTL_7 = 0x0007u, /* Left = AMUXBUS_ADFT1_VDDD; Right = AMUXBUS_NOISY */ AMUX_SPLIT_CTL_8 = 0x0008u /* Left = AMUXBUS_ANALOG_VDDD; Right = AMUXBUS_ANALOG_VDDA */ } cy_en_amux_split_t; diff --git a/devices/include/gpio_psoc6_01_68_qfn_ble.h b/devices/include/gpio_psoc6_01_68_qfn_ble.h index d85ef68..2719e9b 100644 --- a/devices/include/gpio_psoc6_01_68_qfn_ble.h +++ b/devices/include/gpio_psoc6_01_68_qfn_ble.h @@ -5,7 +5,7 @@ * PSoC6_01 device GPIO header for 68-QFN-BLE package * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.5.0.1304 * ******************************************************************************** * \copyright @@ -63,12 +63,12 @@ typedef enum { AMUX_SPLIT_CTL_0 = 0x0000u, /* Left = AMUXBUS_ADFT0_VDDD; Right = AMUXBUS_MAIN */ AMUX_SPLIT_CTL_1 = 0x0001u, /* Left = AMUXBUS_MAIN; Right = AMUXBUS_NOISY */ - AMUX_SPLIT_CTL_7 = 0x0007u, /* Left = AMUXBUS_ADFT1_VDDD; Right = AMUXBUS_NOISY */ AMUX_SPLIT_CTL_2 = 0x0002u, /* Left = AMUXBUS_CSD0; Right = AMUXBUS_NOISY */ AMUX_SPLIT_CTL_3 = 0x0003u, /* Left = AMUXBUS_VDDIO_1; Right = AMUXBUS_CSD0 */ AMUX_SPLIT_CTL_4 = 0x0004u, /* Left = AMUXBUS_CSD1; Right = AMUXBUS_CSD0 */ AMUX_SPLIT_CTL_5 = 0x0005u, /* Left = AMUXBUS_SAR; Right = AMUXBUS_CSD1 */ AMUX_SPLIT_CTL_6 = 0x0006u, /* Left = AMUXBUS_SAR; Right = AMUXBUS_MAIN */ + AMUX_SPLIT_CTL_7 = 0x0007u, /* Left = AMUXBUS_ADFT1_VDDD; Right = AMUXBUS_NOISY */ AMUX_SPLIT_CTL_8 = 0x0008u /* Left = AMUXBUS_ANALOG_VDDD; Right = AMUXBUS_ANALOG_VDDA */ } cy_en_amux_split_t; diff --git a/devices/include/gpio_psoc6_01_80_wlcsp.h b/devices/include/gpio_psoc6_01_80_wlcsp.h index 2b4230a..09f3677 100644 --- a/devices/include/gpio_psoc6_01_80_wlcsp.h +++ b/devices/include/gpio_psoc6_01_80_wlcsp.h @@ -5,7 +5,7 @@ * PSoC6_01 device GPIO header for 80-WLCSP package * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.5.0.1304 * ******************************************************************************** * \copyright @@ -63,12 +63,12 @@ typedef enum { AMUX_SPLIT_CTL_0 = 0x0000u, /* Left = AMUXBUS_ADFT0_VDDD; Right = AMUXBUS_MAIN */ AMUX_SPLIT_CTL_1 = 0x0001u, /* Left = AMUXBUS_MAIN; Right = AMUXBUS_NOISY */ - AMUX_SPLIT_CTL_7 = 0x0007u, /* Left = AMUXBUS_ADFT1_VDDD; Right = AMUXBUS_NOISY */ AMUX_SPLIT_CTL_2 = 0x0002u, /* Left = AMUXBUS_CSD0; Right = AMUXBUS_NOISY */ AMUX_SPLIT_CTL_3 = 0x0003u, /* Left = AMUXBUS_VDDIO_1; Right = AMUXBUS_CSD0 */ AMUX_SPLIT_CTL_4 = 0x0004u, /* Left = AMUXBUS_CSD1; Right = AMUXBUS_CSD0 */ AMUX_SPLIT_CTL_5 = 0x0005u, /* Left = AMUXBUS_SAR; Right = AMUXBUS_CSD1 */ AMUX_SPLIT_CTL_6 = 0x0006u, /* Left = AMUXBUS_SAR; Right = AMUXBUS_MAIN */ + AMUX_SPLIT_CTL_7 = 0x0007u, /* Left = AMUXBUS_ADFT1_VDDD; Right = AMUXBUS_NOISY */ AMUX_SPLIT_CTL_8 = 0x0008u /* Left = AMUXBUS_ANALOG_VDDD; Right = AMUXBUS_ANALOG_VDDA */ } cy_en_amux_split_t; diff --git a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct similarity index 97% rename from devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct rename to devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct index 1ae3cb2..d9f2493 100644 --- a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xx5_cm0plus.sct -;* \version 2.60 +;* \version 2.70 ;* ;* Linker file for the ARMCC. ;* @@ -78,7 +78,7 @@ #define MBED_PUBLIC_RAM_SIZE 0x200 #endif -; Size of the stack section at the end of CM0+ SRAM +; The size of the stack section at the end of CM0+ SRAM #if !defined(MBED_BOOT_STACK_SIZE) #define MBED_BOOT_STACK_SIZE 0x400 #endif @@ -108,7 +108,7 @@ #define FLASH_START MBED_APP_START #define FLASH_SIZE MBED_APP_SIZE -; The following defines describe a 32K flash region used for EEPROM emulation. +; The following defines describe a 32K flash region used for EEPROM emulation. ; This region can also be used as the general purpose flash. ; You can assign sections to this memory region for only one of the cores. ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. @@ -189,18 +189,17 @@ LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000) } ; Application heap area (HEAP) - ARM_LIB_HEAP +0 + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2) { - * (HEAP) } - + ; Stack region growing down - ARM_LIB_STACK RAM_START+RAM_SIZE -STACK_SIZE + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE { - * (STACK) } } + ; Emulated EEPROM Flash area LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE { diff --git a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_ARM/cy8c6xx6_cm0plus.sct b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx6_cm0plus.sct similarity index 97% rename from devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_ARM/cy8c6xx6_cm0plus.sct rename to devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx6_cm0plus.sct index 1bc7174..eb63380 100644 --- a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_ARM/cy8c6xx6_cm0plus.sct +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx6_cm0plus.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xx6_cm0plus.sct -;* \version 2.60 +;* \version 2.70 ;* ;* Linker file for the ARMCC. ;* @@ -78,7 +78,7 @@ #define MBED_PUBLIC_RAM_SIZE 0x200 #endif -; Size of the stack section at the end of CM0+ SRAM +; The size of the stack section at the end of CM0+ SRAM #if !defined(MBED_BOOT_STACK_SIZE) #define MBED_BOOT_STACK_SIZE 0x400 #endif @@ -108,7 +108,7 @@ #define FLASH_START MBED_APP_START #define FLASH_SIZE MBED_APP_SIZE -; The following defines describe a 32K flash region used for EEPROM emulation. +; The following defines describe a 32K flash region used for EEPROM emulation. ; This region can also be used as the general purpose flash. ; You can assign sections to this memory region for only one of the cores. ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. @@ -189,18 +189,17 @@ LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000) } ; Application heap area (HEAP) - ARM_LIB_HEAP +0 + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2) { - * (HEAP) } - + ; Stack region growing down - ARM_LIB_STACK RAM_START+RAM_SIZE -STACK_SIZE + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE { - * (STACK) } } + ; Emulated EEPROM Flash area LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE { diff --git a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct similarity index 97% rename from devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct rename to devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct index ff0e80b..4ff5ccb 100644 --- a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xx7_cm0plus.sct -;* \version 2.60 +;* \version 2.70 ;* ;* Linker file for the ARMCC. ;* @@ -78,7 +78,7 @@ #define MBED_PUBLIC_RAM_SIZE 0x200 #endif -; Size of the stack section at the end of CM0+ SRAM +; The size of the stack section at the end of CM0+ SRAM #if !defined(MBED_BOOT_STACK_SIZE) #define MBED_BOOT_STACK_SIZE 0x400 #endif @@ -108,7 +108,7 @@ #define FLASH_START MBED_APP_START #define FLASH_SIZE MBED_APP_SIZE -; The following defines describe a 32K flash region used for EEPROM emulation. +; The following defines describe a 32K flash region used for EEPROM emulation. ; This region can also be used as the general purpose flash. ; You can assign sections to this memory region for only one of the cores. ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. @@ -189,18 +189,17 @@ LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000) } ; Application heap area (HEAP) - ARM_LIB_HEAP +0 + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2) { - * (HEAP) } - + ; Stack region growing down - ARM_LIB_STACK RAM_START+RAM_SIZE -STACK_SIZE + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE { - * (STACK) } } + ; Emulated EEPROM Flash area LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE { diff --git a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_ARM/cy8c6xx8_cm0plus.sct b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx8_cm0plus.sct similarity index 97% rename from devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_ARM/cy8c6xx8_cm0plus.sct rename to devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx8_cm0plus.sct index 4c466ff..cf27334 100644 --- a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_ARM/cy8c6xx8_cm0plus.sct +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx8_cm0plus.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xx8_cm0plus.sct -;* \version 2.60 +;* \version 2.70 ;* ;* Linker file for the ARMCC. ;* @@ -78,7 +78,7 @@ #define MBED_PUBLIC_RAM_SIZE 0x200 #endif -; Size of the stack section at the end of CM0+ SRAM +; The size of the stack section at the end of CM0+ SRAM #if !defined(MBED_BOOT_STACK_SIZE) #define MBED_BOOT_STACK_SIZE 0x400 #endif @@ -108,7 +108,7 @@ #define FLASH_START MBED_APP_START #define FLASH_SIZE MBED_APP_SIZE -; The following defines describe a 32K flash region used for EEPROM emulation. +; The following defines describe a 32K flash region used for EEPROM emulation. ; This region can also be used as the general purpose flash. ; You can assign sections to this memory region for only one of the cores. ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. @@ -189,18 +189,17 @@ LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000) } ; Application heap area (HEAP) - ARM_LIB_HEAP +0 + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2) { - * (HEAP) } - + ; Stack region growing down - ARM_LIB_STACK RAM_START+RAM_SIZE -STACK_SIZE + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE { - * (STACK) } } + ; Emulated EEPROM Flash area LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE { diff --git a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct similarity index 97% rename from devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct rename to devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct index 4935f52..f5a9981 100644 --- a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xxa_cm0plus.sct -;* \version 2.60 +;* \version 2.70 ;* ;* Linker file for the ARMCC. ;* @@ -78,7 +78,7 @@ #define MBED_PUBLIC_RAM_SIZE 0x200 #endif -; Size of the stack section at the end of CM0+ SRAM +; The size of the stack section at the end of CM0+ SRAM #if !defined(MBED_BOOT_STACK_SIZE) #define MBED_BOOT_STACK_SIZE 0x400 #endif @@ -108,7 +108,7 @@ #define FLASH_START MBED_APP_START #define FLASH_SIZE MBED_APP_SIZE -; The following defines describe a 32K flash region used for EEPROM emulation. +; The following defines describe a 32K flash region used for EEPROM emulation. ; This region can also be used as the general purpose flash. ; You can assign sections to this memory region for only one of the cores. ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. @@ -189,18 +189,17 @@ LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000) } ; Application heap area (HEAP) - ARM_LIB_HEAP +0 + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2) { - * (HEAP) } - + ; Stack region growing down - ARM_LIB_STACK RAM_START+RAM_SIZE -STACK_SIZE + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE { - * (STACK) } } + ; Emulated EEPROM Flash area LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE { diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx5_cm0plus.sct b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx5_cm0plus.sct new file mode 100644 index 0000000..317c801 --- /dev/null +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx5_cm0plus.sct @@ -0,0 +1,293 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cyb06xx5_cm0plus.sct +;* \version 2.70 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +;* MBED_APP_START is being used by the bootloader build script and +;* will be calculate by the system. Without bootloader the MBED_APP_START +;* is equal to MBED_ROM_START +;* +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x80000 +#endif + +;* MBED_APP_SIZE is being used by the bootloader build script and +;* will be calculate by the system. Without bootloader the MBED_APP_SIZE +;* is equal to MBED_ROM_SIZE +;* +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08000000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x00010000 +#endif + +#if !defined(MBED_PUBLIC_RAM_SIZE) + #define MBED_PUBLIC_RAM_SIZE 0x200 +#endif + +; The size of the stack section at the end of CM0+ SRAM +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +#define STACK_SIZE MBED_BOOT_STACK_SIZE + +#if !defined(MBED_PUBLIC_RAM_START) + #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE) +#endif + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM0+ core. +; You can change the memory allocation by editing the RAM and Flash defines. +; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', +; where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.scat'. +; RAM +#define RAM_START MBED_RAM_START +#define RAM_SIZE MBED_RAM_SIZE +; Public RAM +#define PUBLIC_RAM_START MBED_PUBLIC_RAM_START +#define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE +; Flash +#define FLASH_START MBED_APP_START +#define FLASH_SIZE MBED_APP_SIZE + +; The size of the MCU boot header area at the start of FLASH +#define BOOT_HEADER_SIZE 0x00000400 + + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M0+ application flash area +LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000) +{ + .cy_app_header +0 + { + * (.cy_app_header) + } + + ER_FLASH_VECTORS +BOOT_HEADER_SIZE + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + RW_IRAM2 PUBLIC_RAM_START UNINIT + { + * (.cy_sharedmem) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2) + { + } + + ; Stack region growing down + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE + { + } +} + + + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + .cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00070000 +#define __cy_memory_0_row_size 0x200 + + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx7_cm0plus.sct b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx7_cm0plus.sct new file mode 100644 index 0000000..1a7e1db --- /dev/null +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx7_cm0plus.sct @@ -0,0 +1,312 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cyb06xx7_cm0plus.sct +;* \version 2.70 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +;* MBED_APP_START is being used by the bootloader build script and +;* will be calculate by the system. Without bootloader the MBED_APP_START +;* is equal to MBED_ROM_START +;* +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x80000 +#endif + +;* MBED_APP_SIZE is being used by the bootloader build script and +;* will be calculate by the system. Without bootloader the MBED_APP_SIZE +;* is equal to MBED_ROM_SIZE +;* +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08000000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x00010000 +#endif + +#if !defined(MBED_PUBLIC_RAM_SIZE) + #define MBED_PUBLIC_RAM_SIZE 0x200 +#endif + +; The size of the stack section at the end of CM0+ SRAM +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +#define STACK_SIZE MBED_BOOT_STACK_SIZE + +#if !defined(MBED_PUBLIC_RAM_START) + #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE) +#endif + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM0+ core. +; You can change the memory allocation by editing the RAM and Flash defines. +; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', +; where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.scat'. +; RAM +#define RAM_START MBED_RAM_START +#define RAM_SIZE MBED_RAM_SIZE +; Public RAM +#define PUBLIC_RAM_START MBED_PUBLIC_RAM_START +#define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE +; Flash +#define FLASH_START MBED_APP_START +#define FLASH_SIZE MBED_APP_SIZE + +; The size of the MCU boot header area at the start of FLASH +#define BOOT_HEADER_SIZE 0x00000400 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M0+ application flash area +LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000) +{ + .cy_app_header +0 + { + * (.cy_app_header) + } + + ER_FLASH_VECTORS +BOOT_HEADER_SIZE + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + RW_IRAM2 PUBLIC_RAM_START UNINIT + { + * (.cy_sharedmem) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2) + { + } + + ; Stack region growing down + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE + { + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + .cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x000D0000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct new file mode 100644 index 0000000..b16001c --- /dev/null +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct @@ -0,0 +1,312 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cyb06xxa_cm0plus.sct +;* \version 2.70 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +;* MBED_APP_START is being used by the bootloader build script and +;* will be calculate by the system. Without bootloader the MBED_APP_START +;* is equal to MBED_ROM_START +;* +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x80000 +#endif + +;* MBED_APP_SIZE is being used by the bootloader build script and +;* will be calculate by the system. Without bootloader the MBED_APP_SIZE +;* is equal to MBED_ROM_SIZE +;* +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08000000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x00010000 +#endif + +#if !defined(MBED_PUBLIC_RAM_SIZE) + #define MBED_PUBLIC_RAM_SIZE 0x200 +#endif + +; The size of the stack section at the end of CM0+ SRAM +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +#define STACK_SIZE MBED_BOOT_STACK_SIZE + +#if !defined(MBED_PUBLIC_RAM_START) + #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE) +#endif + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM0+ core. +; You can change the memory allocation by editing the RAM and Flash defines. +; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', +; where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.scat'. +; RAM +#define RAM_START MBED_RAM_START +#define RAM_SIZE MBED_RAM_SIZE +; Public RAM +#define PUBLIC_RAM_START MBED_PUBLIC_RAM_START +#define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE +; Flash +#define FLASH_START MBED_APP_START +#define FLASH_SIZE MBED_APP_SIZE + +; The size of the MCU boot header area at the start of FLASH +#define BOOT_HEADER_SIZE 0x00000400 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M0+ application flash area +LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000) +{ + .cy_app_header +0 + { + * (.cy_app_header) + } + + ER_FLASH_VECTORS +BOOT_HEADER_SIZE + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + RW_IRAM2 PUBLIC_RAM_START UNINIT + { + * (.cy_sharedmem) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2) + { + } + + ; Stack region growing down + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE + { + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + .cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x001D0000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/devices/bsp/COMPONENT_MBED/startup/TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.S b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.S similarity index 90% rename from devices/bsp/COMPONENT_MBED/startup/TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.S rename to devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.S index 536d029..09d6b4c 100644 --- a/devices/bsp/COMPONENT_MBED/startup/TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.S +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.S @@ -23,36 +23,6 @@ ; * limitations under the License. ; */ -;/* -;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -;*/ - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - IF :DEF:__STACK_SIZE -Stack_Size EQU __STACK_SIZE - ELSE -Stack_Size EQU 0x00000400 - ENDIF - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - IF :DEF:__HEAP_SIZE -Heap_Size EQU __HEAP_SIZE - ELSE -Heap_Size EQU 0x00000400 - ENDIF - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 THUMB @@ -62,8 +32,9 @@ __heap_limit EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| -__Vectors DCD __initial_sp ; Top of Stack +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack DCD Reset_Handler ; Reset Handler DCD 0x0000000D ; NMI Handler located at ROM code @@ -284,23 +255,6 @@ NvicMux31_IRQHandler ALIGN - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - - ALIGN - - ENDIF - END diff --git a/devices/bsp/COMPONENT_MBED/startup/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S similarity index 87% rename from devices/bsp/COMPONENT_MBED/startup/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S rename to devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S index 47553fb..2ebb953 100644 --- a/devices/bsp/COMPONENT_MBED/startup/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S @@ -23,36 +23,6 @@ ; * limitations under the License. ; */ -;/* -;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -;*/ - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - IF :DEF:__STACK_SIZE -Stack_Size EQU __STACK_SIZE - ELSE -Stack_Size EQU 0x00000400 - ENDIF - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - IF :DEF:__HEAP_SIZE -Heap_Size EQU __HEAP_SIZE - ELSE -Heap_Size EQU 0x00000400 - ENDIF - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 THUMB @@ -62,8 +32,9 @@ __heap_limit EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| -__Vectors DCD __initial_sp ; Top of Stack +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack DCD Reset_Handler ; Reset Handler DCD 0x0000000D ; NMI Handler located at ROM code @@ -236,23 +207,6 @@ Internal7_IRQHandler ALIGN - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - - ALIGN - - ENDIF - END diff --git a/devices/bsp/COMPONENT_MBED/startup/TOOLCHAIN_ARM/startup_psoc6_03_cm0plus.S b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_03_cm0plus.S similarity index 87% rename from devices/bsp/COMPONENT_MBED/startup/TOOLCHAIN_ARM/startup_psoc6_03_cm0plus.S rename to devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_03_cm0plus.S index cd5bc7d..ba67c4b 100644 --- a/devices/bsp/COMPONENT_MBED/startup/TOOLCHAIN_ARM/startup_psoc6_03_cm0plus.S +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_03_cm0plus.S @@ -23,36 +23,6 @@ ; * limitations under the License. ; */ -;/* -;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -;*/ - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - IF :DEF:__STACK_SIZE -Stack_Size EQU __STACK_SIZE - ELSE -Stack_Size EQU 0x00000400 - ENDIF - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - IF :DEF:__HEAP_SIZE -Heap_Size EQU __HEAP_SIZE - ELSE -Heap_Size EQU 0x00000400 - ENDIF - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 THUMB @@ -62,8 +32,9 @@ __heap_limit EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| -__Vectors DCD __initial_sp ; Top of Stack +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack DCD Reset_Handler ; Reset Handler DCD 0x0000000D ; NMI Handler located at ROM code @@ -236,23 +207,6 @@ Internal7_IRQHandler ALIGN - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - - ALIGN - - ENDIF - END diff --git a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm0plus.ld b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm0plus.ld similarity index 99% rename from devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm0plus.ld rename to devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm0plus.ld index 1147ac7..5611270 100644 --- a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm0plus.ld +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm0plus.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx5_cm0plus.ld -* \version 2.50 +* \version 2.70 * * Linker file for the GNU C compiler. * @@ -76,7 +76,7 @@ ENTRY(Reset_Handler) #define MBED_PUBLIC_RAM_SIZE 0x200 #endif -/* Size of the stack section at the end of CM0+ SRAM */ +/* The size of the stack section at the end of CM0+ SRAM */ #if !defined(MBED_BOOT_STACK_SIZE) #define MBED_BOOT_STACK_SIZE 0x400 #endif diff --git a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_GCC_ARM/cy8c6xx6_cm0plus.ld b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx6_cm0plus.ld similarity index 99% rename from devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_GCC_ARM/cy8c6xx6_cm0plus.ld rename to devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx6_cm0plus.ld index 72769dc..f2586c3 100644 --- a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_GCC_ARM/cy8c6xx6_cm0plus.ld +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx6_cm0plus.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx6_cm0plus.ld -* \version 2.50 +* \version 2.70 * * Linker file for the GNU C compiler. * @@ -76,7 +76,7 @@ ENTRY(Reset_Handler) #define MBED_PUBLIC_RAM_SIZE 0x200 #endif -/* Size of the stack section at the end of CM0+ SRAM */ +/* The size of the stack section at the end of CM0+ SRAM */ #if !defined(MBED_BOOT_STACK_SIZE) #define MBED_BOOT_STACK_SIZE 0x400 #endif diff --git a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld similarity index 99% rename from devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld rename to devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld index b8339aa..a9d2857 100644 --- a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx7_cm0plus.ld -* \version 2.50 +* \version 2.70 * * Linker file for the GNU C compiler. * @@ -76,7 +76,7 @@ ENTRY(Reset_Handler) #define MBED_PUBLIC_RAM_SIZE 0x200 #endif -/* Size of the stack section at the end of CM0+ SRAM */ +/* The size of the stack section at the end of CM0+ SRAM */ #if !defined(MBED_BOOT_STACK_SIZE) #define MBED_BOOT_STACK_SIZE 0x400 #endif diff --git a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_GCC_ARM/cy8c6xx8_cm0plus.ld b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx8_cm0plus.ld similarity index 99% rename from devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_GCC_ARM/cy8c6xx8_cm0plus.ld rename to devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx8_cm0plus.ld index d8c773a..d1d65d4 100644 --- a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_GCC_ARM/cy8c6xx8_cm0plus.ld +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx8_cm0plus.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx8_cm0plus.ld -* \version 2.50 +* \version 2.70 * * Linker file for the GNU C compiler. * @@ -76,7 +76,7 @@ ENTRY(Reset_Handler) #define MBED_PUBLIC_RAM_SIZE 0x200 #endif -/* Size of the stack section at the end of CM0+ SRAM */ +/* The size of the stack section at the end of CM0+ SRAM */ #if !defined(MBED_BOOT_STACK_SIZE) #define MBED_BOOT_STACK_SIZE 0x400 #endif diff --git a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld similarity index 99% rename from devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld rename to devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld index 26b4330..e6ab901 100644 --- a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xxa_cm0plus.ld -* \version 2.50 +* \version 2.70 * * Linker file for the GNU C compiler. * @@ -76,7 +76,7 @@ ENTRY(Reset_Handler) #define MBED_PUBLIC_RAM_SIZE 0x200 #endif -/* Size of the stack section at the end of CM0+ SRAM */ +/* The size of the stack section at the end of CM0+ SRAM */ #if !defined(MBED_BOOT_STACK_SIZE) #define MBED_BOOT_STACK_SIZE 0x400 #endif diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xx5_cm0plus.ld b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xx5_cm0plus.ld new file mode 100644 index 0000000..d3da953 --- /dev/null +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xx5_cm0plus.ld @@ -0,0 +1,456 @@ +/***************************************************************************//** +* \file cyb06xx5_cm0plus.ld +* \version 2.70 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +/* MBED_APP_START is being used by the bootloader build script and +* will be calculate by the system. Without bootloader the MBED_APP_START +* is equal to MBED_ROM_START +*/ +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x80000 +#endif + +/* MBED_APP_SIZE is being used by the bootloader build script and +* will be calculate by the system. Without bootloader the MBED_APP_SIZE +* is equal to MBED_ROM_SIZE +*/ +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08000000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x00010000 +#endif + +#if !defined(MBED_PUBLIC_RAM_SIZE) + #define MBED_PUBLIC_RAM_SIZE 0x200 +#endif + +/* The size of the stack section at the end of CM0+ SRAM */ +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +STACK_SIZE = MBED_BOOT_STACK_SIZE; + +#if !defined(MBED_PUBLIC_RAM_START) + #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE) +#endif + +/* The size of the MCU boot header area at the start of FLASH */ +BOOT_HEADER_SIZE = 0x400; + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM0+ core. + * You can change the memory allocation by editing the 'ram' and 'flash' regions. + * Your changes must be aligned with the corresponding memory regions for the CM4 core in 'xx_cm4_dual.ld', + * where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.ld'. + */ + ram (rwx) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE + public_ram (rw) : ORIGIN = MBED_PUBLIC_RAM_START, LENGTH = MBED_PUBLIC_RAM_SIZE + flash (rx) : ORIGIN = MBED_APP_START, LENGTH = (MBED_APP_SIZE - 0x8000) + + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + .cy_app_header : + { + KEEP(*(.cy_app_header)) + } > flash + + /* Cortex-M0+ application flash area */ + .text ORIGIN(flash) + BOOT_HEADER_SIZE : + { + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_03_cm0plus.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_03_cm0plus.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > ram + + + /* Public RAM */ + .cy_sharedmem (NOLOAD): + { + . = ALIGN(4); + KEEP(*(.cy_sharedmem)) + } > public_ram + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + .cy_xip : + { + KEEP(*(.cy_xip)) + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x00070000; +__cy_memory_0_row_size = 0x200; + + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xx7_cm0plus.ld b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xx7_cm0plus.ld new file mode 100644 index 0000000..c37386f --- /dev/null +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xx7_cm0plus.ld @@ -0,0 +1,471 @@ +/***************************************************************************//** +* \file cyb06xx7_cm0plus.ld +* \version 2.70 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +/* MBED_APP_START is being used by the bootloader build script and +* will be calculate by the system. Without bootloader the MBED_APP_START +* is equal to MBED_ROM_START +*/ +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x80000 +#endif + +/* MBED_APP_SIZE is being used by the bootloader build script and +* will be calculate by the system. Without bootloader the MBED_APP_SIZE +* is equal to MBED_ROM_SIZE +*/ +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08000000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x00010000 +#endif + +#if !defined(MBED_PUBLIC_RAM_SIZE) + #define MBED_PUBLIC_RAM_SIZE 0x200 +#endif + +/* The size of the stack section at the end of CM0+ SRAM */ +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +STACK_SIZE = MBED_BOOT_STACK_SIZE; + +#if !defined(MBED_PUBLIC_RAM_START) + #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE) +#endif + +/* The size of the MCU boot header area at the start of FLASH */ +BOOT_HEADER_SIZE = 0x400; + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM0+ core. + * You can change the memory allocation by editing the 'ram' and 'flash' regions. + * Your changes must be aligned with the corresponding memory regions for the CM4 core in 'xx_cm4_dual.ld', + * where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.ld'. + */ + ram (rwx) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE + public_ram (rw) : ORIGIN = MBED_PUBLIC_RAM_START, LENGTH = MBED_PUBLIC_RAM_SIZE + flash (rx) : ORIGIN = MBED_APP_START, LENGTH = (MBED_APP_SIZE - 0x8000) + + /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ + em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */ + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + .cy_app_header : + { + KEEP(*(.cy_app_header)) + } > flash + + /* Cortex-M0+ application flash area */ + .text ORIGIN(flash) + BOOT_HEADER_SIZE : + { + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_01_cm0plus.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_01_cm0plus.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > ram + + + /* Public RAM */ + .cy_sharedmem (NOLOAD): + { + . = ALIGN(4); + KEEP(*(.cy_sharedmem)) + } > public_ram + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + .cy_xip : + { + KEEP(*(.cy_xip)) + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x000D0000; +__cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +__cy_memory_1_start = 0x14000000; +__cy_memory_1_length = 0x8000; +__cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xxa_cm0plus.ld b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xxa_cm0plus.ld new file mode 100644 index 0000000..15f6a88 --- /dev/null +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xxa_cm0plus.ld @@ -0,0 +1,471 @@ +/***************************************************************************//** +* \file cyb06xxa_cm0plus.ld +* \version 2.70 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +/* MBED_APP_START is being used by the bootloader build script and +* will be calculate by the system. Without bootloader the MBED_APP_START +* is equal to MBED_ROM_START +*/ +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x80000 +#endif + +/* MBED_APP_SIZE is being used by the bootloader build script and +* will be calculate by the system. Without bootloader the MBED_APP_SIZE +* is equal to MBED_ROM_SIZE +*/ +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08000000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x00010000 +#endif + +#if !defined(MBED_PUBLIC_RAM_SIZE) + #define MBED_PUBLIC_RAM_SIZE 0x200 +#endif + +/* The size of the stack section at the end of CM0+ SRAM */ +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +STACK_SIZE = MBED_BOOT_STACK_SIZE; + +#if !defined(MBED_PUBLIC_RAM_START) + #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE) +#endif + +/* The size of the MCU boot header area at the start of FLASH */ +BOOT_HEADER_SIZE = 0x400; + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM0+ core. + * You can change the memory allocation by editing the 'ram' and 'flash' regions. + * Your changes must be aligned with the corresponding memory regions for the CM4 core in 'xx_cm4_dual.ld', + * where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.ld'. + */ + ram (rwx) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE + public_ram (rw) : ORIGIN = MBED_PUBLIC_RAM_START, LENGTH = MBED_PUBLIC_RAM_SIZE + flash (rx) : ORIGIN = MBED_APP_START, LENGTH = (MBED_APP_SIZE - 0x8000) + + /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ + em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */ + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + .cy_app_header : + { + KEEP(*(.cy_app_header)) + } > flash + + /* Cortex-M0+ application flash area */ + .text ORIGIN(flash) + BOOT_HEADER_SIZE : + { + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_02_cm0plus.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_02_cm0plus.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > ram + + + /* Public RAM */ + .cy_sharedmem (NOLOAD): + { + . = ALIGN(4); + KEEP(*(.cy_sharedmem)) + } > public_ram + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + .cy_xip : + { + KEEP(*(.cy_xip)) + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x001D0000; +__cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +__cy_memory_1_start = 0x14000000; +__cy_memory_1_length = 0x8000; +__cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/devices/bsp/COMPONENT_MBED/startup/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm0plus.S b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm0plus.S similarity index 100% rename from devices/bsp/COMPONENT_MBED/startup/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm0plus.S rename to devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm0plus.S diff --git a/devices/bsp/COMPONENT_MBED/startup/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm0plus.S b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm0plus.S similarity index 100% rename from devices/bsp/COMPONENT_MBED/startup/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm0plus.S rename to devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm0plus.S diff --git a/devices/bsp/COMPONENT_MBED/startup/TOOLCHAIN_GCC_ARM/startup_psoc6_03_cm0plus.S b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_03_cm0plus.S similarity index 100% rename from devices/bsp/COMPONENT_MBED/startup/TOOLCHAIN_GCC_ARM/startup_psoc6_03_cm0plus.S rename to devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_03_cm0plus.S diff --git a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_IAR/cy8c6xx5_cm0plus.icf b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx5_cm0plus.icf similarity index 99% rename from devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_IAR/cy8c6xx5_cm0plus.icf rename to devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx5_cm0plus.icf index 669e6ed..68b322d 100644 --- a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_IAR/cy8c6xx5_cm0plus.icf +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx5_cm0plus.icf @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx5_cm0plus.icf -* \version 2.60 +* \version 2.70 * * Linker file for the IAR compiler. * @@ -122,7 +122,7 @@ define symbol __ICFEDIT_region_IRAM2_end__ = (MBED_PUBLIC_RAM_START + MBED_PUB define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 0x8000); -/* The following symbols define a 32K flash region used for EEPROM emulation. +/* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. * You can assign sections to this memory region for only one of the cores. * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. @@ -202,7 +202,6 @@ define block RO {first section .intvec, readonly}; initialize by copy { readwrite }; do not initialize { section .noinit, section .intvec_ram }; - /*-Placement-*/ /* Flash - Cortex-M0+ application */ diff --git a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_IAR/cy8c6xx6_cm0plus.icf b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx6_cm0plus.icf similarity index 99% rename from devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_IAR/cy8c6xx6_cm0plus.icf rename to devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx6_cm0plus.icf index 4515b69..069cdcd 100644 --- a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_IAR/cy8c6xx6_cm0plus.icf +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx6_cm0plus.icf @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx6_cm0plus.icf -* \version 2.60 +* \version 2.70 * * Linker file for the IAR compiler. * @@ -122,7 +122,7 @@ define symbol __ICFEDIT_region_IRAM2_end__ = (MBED_PUBLIC_RAM_START + MBED_PUB define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 0x8000); -/* The following symbols define a 32K flash region used for EEPROM emulation. +/* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. * You can assign sections to this memory region for only one of the cores. * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. @@ -202,7 +202,6 @@ define block RO {first section .intvec, readonly}; initialize by copy { readwrite }; do not initialize { section .noinit, section .intvec_ram }; - /*-Placement-*/ /* Flash - Cortex-M0+ application */ diff --git a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf similarity index 99% rename from devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf rename to devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf index 3b98b65..3a0414e 100644 --- a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx7_cm0plus.icf -* \version 2.60 +* \version 2.70 * * Linker file for the IAR compiler. * @@ -122,7 +122,7 @@ define symbol __ICFEDIT_region_IRAM2_end__ = (MBED_PUBLIC_RAM_START + MBED_PUB define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 0x8000); -/* The following symbols define a 32K flash region used for EEPROM emulation. +/* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. * You can assign sections to this memory region for only one of the cores. * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. @@ -202,7 +202,6 @@ define block RO {first section .intvec, readonly}; initialize by copy { readwrite }; do not initialize { section .noinit, section .intvec_ram }; - /*-Placement-*/ /* Flash - Cortex-M0+ application */ diff --git a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_IAR/cy8c6xx8_cm0plus.icf b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx8_cm0plus.icf similarity index 99% rename from devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_IAR/cy8c6xx8_cm0plus.icf rename to devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx8_cm0plus.icf index ded31ec..5534a17 100644 --- a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_IAR/cy8c6xx8_cm0plus.icf +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx8_cm0plus.icf @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx8_cm0plus.icf -* \version 2.60 +* \version 2.70 * * Linker file for the IAR compiler. * @@ -122,7 +122,7 @@ define symbol __ICFEDIT_region_IRAM2_end__ = (MBED_PUBLIC_RAM_START + MBED_PUB define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 0x8000); -/* The following symbols define a 32K flash region used for EEPROM emulation. +/* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. * You can assign sections to this memory region for only one of the cores. * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. @@ -202,7 +202,6 @@ define block RO {first section .intvec, readonly}; initialize by copy { readwrite }; do not initialize { section .noinit, section .intvec_ram }; - /*-Placement-*/ /* Flash - Cortex-M0+ application */ diff --git a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf similarity index 99% rename from devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf rename to devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf index d06a250..fea3f6e 100644 --- a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xxa_cm0plus.icf -* \version 2.60 +* \version 2.70 * * Linker file for the IAR compiler. * @@ -122,7 +122,7 @@ define symbol __ICFEDIT_region_IRAM2_end__ = (MBED_PUBLIC_RAM_START + MBED_PUB define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 0x8000); -/* The following symbols define a 32K flash region used for EEPROM emulation. +/* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. * You can assign sections to this memory region for only one of the cores. * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. @@ -202,7 +202,6 @@ define block RO {first section .intvec, readonly}; initialize by copy { readwrite }; do not initialize { section .noinit, section .intvec_ram }; - /*-Placement-*/ /* Flash - Cortex-M0+ application */ diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xx5_cm0plus.icf b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xx5_cm0plus.icf new file mode 100644 index 0000000..32e9a78 --- /dev/null +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xx5_cm0plus.icf @@ -0,0 +1,281 @@ +/***************************************************************************//** +* \file cyb06xx5_cm0plus.icf +* \version 2.70 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +if (!isdefinedsymbol(MBED_ROM_START)) { + define symbol MBED_ROM_START = 0x10000000; +} + +/* MBED_APP_START is being used by the bootloader build script and + * will be calculate by the system. Without bootloader the MBED_APP_START + * is equal to MBED_ROM_START + */ +if (!isdefinedsymbol(MBED_APP_START)) { + define symbol MBED_APP_START = MBED_ROM_START; +} + +if (!isdefinedsymbol(MBED_ROM_SIZE)) { + define symbol MBED_ROM_SIZE = 0x80000; +} + +/* MBED_APP_SIZE is being used by the bootloader build script and + * will be calculate by the system. Without bootloader the MBED_APP_SIZE + * is equal to MBED_ROM_SIZE + */ +if (!isdefinedsymbol(MBED_APP_SIZE)) { + define symbol MBED_APP_SIZE = MBED_ROM_SIZE; +} + +if (!isdefinedsymbol(MBED_RAM_START)) { + define symbol MBED_RAM_START = 0x08000000; +} + +if (!isdefinedsymbol(MBED_RAM_SIZE)) { + define symbol MBED_RAM_SIZE = 0x00010000; +} + +/*-Sizes-*/ +if (!isdefinedsymbol(MBED_PUBLIC_RAM_SIZE)) { + define symbol MBED_PUBLIC_RAM_SIZE = 0x200; +} +if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { + + if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol MBED_BOOT_STACK_SIZE = 0x0400; + } else { + define symbol MBED_BOOT_STACK_SIZE = __STACK_SIZE; + } +} + +define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; + +define symbol __ICFEDIT_size_proc_stack__ = 0x0; + +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} + +if (!isdefinedsymbol(MBED_PUBLIC_RAM_START)) { + define symbol MBED_PUBLIC_RAM_START = (MBED_RAM_START + MBED_RAM_SIZE - __ICFEDIT_size_cstack__ - MBED_PUBLIC_RAM_SIZE); +} + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM0+ core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Your changes must be aligned with the corresponding symbols for CM4 core in 'xx_cm4_dual.icf', + * where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; +define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE); +/* Public RAM */ +define symbol __ICFEDIT_region_IRAM2_start__ = MBED_PUBLIC_RAM_START; +define symbol __ICFEDIT_region_IRAM2_end__ = (MBED_PUBLIC_RAM_START + MBED_PUBLIC_RAM_SIZE); +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; +define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 0x8000); + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x160007FF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/**** End of ICF editor section. ###ICF###*/ + +/* The size of the MCU boot header area at the start of FLASH */ +define symbol BOOT_HEADER_SIZE = 0x400; + + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; +define region IRAM2_region = mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; + +define block RAM_DATA {readwrite section .data}; +define block RAM_OTHER {readwrite section * }; +define block RAM_NOINIT {readwrite section .noinit}; +define block RAM_BSS {readwrite section .bss}; +define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NOINIT, block RAM_BSS}; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; +define block RO {first section .intvec, readonly}; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M0+ application */ +".cy_app_header" : place at start of IROM1_region { section .cy_app_header }; +place at address (__ICFEDIT_region_IROM1_start__ + BOOT_HEADER_SIZE) { block RO }; + + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +".cy_xip" : place at start of EROM1_region { section .cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { block RAM}; +place in IRAM1_region { readwrite section .cy_ramfunc }; +place at end of IRAM1_region { block HSTACK }; + +/* Public RAM */ +place at start of IRAM2_region { section .cy_sharedmem }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_app_header, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00070000; +define exported symbol __cy_memory_0_row_size = 0x200; + + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xx7_cm0plus.icf b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xx7_cm0plus.icf new file mode 100644 index 0000000..f48b2e9 --- /dev/null +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xx7_cm0plus.icf @@ -0,0 +1,288 @@ +/***************************************************************************//** +* \file cyb06xx7_cm0plus.icf +* \version 2.70 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +if (!isdefinedsymbol(MBED_ROM_START)) { + define symbol MBED_ROM_START = 0x10000000; +} + +/* MBED_APP_START is being used by the bootloader build script and + * will be calculate by the system. Without bootloader the MBED_APP_START + * is equal to MBED_ROM_START + */ +if (!isdefinedsymbol(MBED_APP_START)) { + define symbol MBED_APP_START = MBED_ROM_START; +} + +if (!isdefinedsymbol(MBED_ROM_SIZE)) { + define symbol MBED_ROM_SIZE = 0x80000; +} + +/* MBED_APP_SIZE is being used by the bootloader build script and + * will be calculate by the system. Without bootloader the MBED_APP_SIZE + * is equal to MBED_ROM_SIZE + */ +if (!isdefinedsymbol(MBED_APP_SIZE)) { + define symbol MBED_APP_SIZE = MBED_ROM_SIZE; +} + +if (!isdefinedsymbol(MBED_RAM_START)) { + define symbol MBED_RAM_START = 0x08000000; +} + +if (!isdefinedsymbol(MBED_RAM_SIZE)) { + define symbol MBED_RAM_SIZE = 0x00010000; +} + +/*-Sizes-*/ +if (!isdefinedsymbol(MBED_PUBLIC_RAM_SIZE)) { + define symbol MBED_PUBLIC_RAM_SIZE = 0x200; +} +if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { + + if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol MBED_BOOT_STACK_SIZE = 0x0400; + } else { + define symbol MBED_BOOT_STACK_SIZE = __STACK_SIZE; + } +} + +define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; + +define symbol __ICFEDIT_size_proc_stack__ = 0x0; + +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} + +if (!isdefinedsymbol(MBED_PUBLIC_RAM_START)) { + define symbol MBED_PUBLIC_RAM_START = (MBED_RAM_START + MBED_RAM_SIZE - __ICFEDIT_size_cstack__ - MBED_PUBLIC_RAM_SIZE); +} + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM0+ core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Your changes must be aligned with the corresponding symbols for CM4 core in 'xx_cm4_dual.icf', + * where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; +define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE); +/* Public RAM */ +define symbol __ICFEDIT_region_IRAM2_start__ = MBED_PUBLIC_RAM_START; +define symbol __ICFEDIT_region_IRAM2_end__ = (MBED_PUBLIC_RAM_START + MBED_PUBLIC_RAM_SIZE); +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; +define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 0x8000); + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x160007FF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/**** End of ICF editor section. ###ICF###*/ + +/* The size of the MCU boot header area at the start of FLASH */ +define symbol BOOT_HEADER_SIZE = 0x400; + + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; +define region IRAM2_region = mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; + +define block RAM_DATA {readwrite section .data}; +define block RAM_OTHER {readwrite section * }; +define block RAM_NOINIT {readwrite section .noinit}; +define block RAM_BSS {readwrite section .bss}; +define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NOINIT, block RAM_BSS}; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; +define block RO {first section .intvec, readonly}; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M0+ application */ +".cy_app_header" : place at start of IROM1_region { section .cy_app_header }; +place at address (__ICFEDIT_region_IROM1_start__ + BOOT_HEADER_SIZE) { block RO }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +".cy_xip" : place at start of EROM1_region { section .cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { block RAM}; +place in IRAM1_region { readwrite section .cy_ramfunc }; +place at end of IRAM1_region { block HSTACK }; + +/* Public RAM */ +place at start of IRAM2_region { section .cy_sharedmem }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_app_header, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x000D0000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xxa_cm0plus.icf b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xxa_cm0plus.icf new file mode 100644 index 0000000..05bbaa0 --- /dev/null +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xxa_cm0plus.icf @@ -0,0 +1,288 @@ +/***************************************************************************//** +* \file cyb06xxa_cm0plus.icf +* \version 2.70 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +if (!isdefinedsymbol(MBED_ROM_START)) { + define symbol MBED_ROM_START = 0x10000000; +} + +/* MBED_APP_START is being used by the bootloader build script and + * will be calculate by the system. Without bootloader the MBED_APP_START + * is equal to MBED_ROM_START + */ +if (!isdefinedsymbol(MBED_APP_START)) { + define symbol MBED_APP_START = MBED_ROM_START; +} + +if (!isdefinedsymbol(MBED_ROM_SIZE)) { + define symbol MBED_ROM_SIZE = 0x80000; +} + +/* MBED_APP_SIZE is being used by the bootloader build script and + * will be calculate by the system. Without bootloader the MBED_APP_SIZE + * is equal to MBED_ROM_SIZE + */ +if (!isdefinedsymbol(MBED_APP_SIZE)) { + define symbol MBED_APP_SIZE = MBED_ROM_SIZE; +} + +if (!isdefinedsymbol(MBED_RAM_START)) { + define symbol MBED_RAM_START = 0x08000000; +} + +if (!isdefinedsymbol(MBED_RAM_SIZE)) { + define symbol MBED_RAM_SIZE = 0x00010000; +} + +/*-Sizes-*/ +if (!isdefinedsymbol(MBED_PUBLIC_RAM_SIZE)) { + define symbol MBED_PUBLIC_RAM_SIZE = 0x200; +} +if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { + + if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol MBED_BOOT_STACK_SIZE = 0x0400; + } else { + define symbol MBED_BOOT_STACK_SIZE = __STACK_SIZE; + } +} + +define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; + +define symbol __ICFEDIT_size_proc_stack__ = 0x0; + +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} + +if (!isdefinedsymbol(MBED_PUBLIC_RAM_START)) { + define symbol MBED_PUBLIC_RAM_START = (MBED_RAM_START + MBED_RAM_SIZE - __ICFEDIT_size_cstack__ - MBED_PUBLIC_RAM_SIZE); +} + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM0+ core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Your changes must be aligned with the corresponding symbols for CM4 core in 'xx_cm4_dual.icf', + * where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; +define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE); +/* Public RAM */ +define symbol __ICFEDIT_region_IRAM2_start__ = MBED_PUBLIC_RAM_START; +define symbol __ICFEDIT_region_IRAM2_end__ = (MBED_PUBLIC_RAM_START + MBED_PUBLIC_RAM_SIZE); +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; +define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 0x8000); + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x160007FF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/**** End of ICF editor section. ###ICF###*/ + +/* The size of the MCU boot header area at the start of FLASH */ +define symbol BOOT_HEADER_SIZE = 0x400; + + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; +define region IRAM2_region = mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; + +define block RAM_DATA {readwrite section .data}; +define block RAM_OTHER {readwrite section * }; +define block RAM_NOINIT {readwrite section .noinit}; +define block RAM_BSS {readwrite section .bss}; +define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NOINIT, block RAM_BSS}; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; +define block RO {first section .intvec, readonly}; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M0+ application */ +".cy_app_header" : place at start of IROM1_region { section .cy_app_header }; +place at address (__ICFEDIT_region_IROM1_start__ + BOOT_HEADER_SIZE) { block RO }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +".cy_xip" : place at start of EROM1_region { section .cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { block RAM}; +place in IRAM1_region { readwrite section .cy_ramfunc }; +place at end of IRAM1_region { block HSTACK }; + +/* Public RAM */ +place at start of IRAM2_region { section .cy_sharedmem }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_app_header, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x001D0000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/devices/bsp/COMPONENT_MBED/startup/TOOLCHAIN_IAR/startup_psoc6_01_cm0plus.S b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_01_cm0plus.S similarity index 100% rename from devices/bsp/COMPONENT_MBED/startup/TOOLCHAIN_IAR/startup_psoc6_01_cm0plus.S rename to devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_01_cm0plus.S diff --git a/devices/bsp/COMPONENT_MBED/startup/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.S b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.S similarity index 100% rename from devices/bsp/COMPONENT_MBED/startup/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.S rename to devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.S diff --git a/devices/bsp/COMPONENT_MBED/startup/TOOLCHAIN_IAR/startup_psoc6_03_cm0plus.S b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_03_cm0plus.S similarity index 100% rename from devices/bsp/COMPONENT_MBED/startup/TOOLCHAIN_IAR/startup_psoc6_03_cm0plus.S rename to devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_03_cm0plus.S diff --git a/devices/bsp/COMPONENT_MBED/startup/system_psoc6_cm0plus.c b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/system_psoc6_cm0plus.c similarity index 69% rename from devices/bsp/COMPONENT_MBED/startup/system_psoc6_cm0plus.c rename to devices/templates/COMPONENT_MBED/COMPONENT_CM0P/system_psoc6_cm0plus.c index 9164b15..18cc197 100644 --- a/devices/bsp/COMPONENT_MBED/startup/system_psoc6_cm0plus.c +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/system_psoc6_cm0plus.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file system_psoc6_cm0plus.c -* \version 2.60 +* \version 2.70 * * The device system-source file. * @@ -27,6 +27,7 @@ #include "cy_device.h" #include "cy_device_headers.h" #include "cy_syslib.h" +#include "cy_sysclk.h" #include "cy_wdt.h" #if !defined(CY_IPC_DEFAULT_CFG_DISABLE) @@ -37,7 +38,6 @@ #if defined(CY_DEVICE_PSOC6ABLE2) #include "cy_flash.h" #endif /* defined(CY_DEVICE_PSOC6ABLE2) */ - #endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */ @@ -54,21 +54,6 @@ /** Default SlowClk system core frequency in Hz */ #define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (4000000UL) -/** IMO frequency in Hz */ -#define CY_CLK_IMO_FREQ_HZ (8000000UL) - -/** HVILO frequency in Hz */ -#define CY_CLK_HVILO_FREQ_HZ (32000UL) - -/** PILO frequency in Hz */ -#define CY_CLK_PILO_FREQ_HZ (32768UL) - -/** WCO frequency in Hz */ -#define CY_CLK_WCO_FREQ_HZ (32768UL) - -/** ALTLF frequency in Hz */ -#define CY_CLK_ALTLF_FREQ_HZ (32768UL) - /** * Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock, @@ -92,10 +77,8 @@ uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT; /** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */ uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; -/** Holds the Alternate high frequency clock in Hz. Updated by \ref SystemCoreClockUpdate(). */ -#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) - uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ; -#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */ +/** Holds the Alternate high frequency clock in Hz. Updated by \ref Cy_BLE_EcoConfigure(). */ +uint32_t cy_BleEcoClockFreqHz = 0UL; /******************************************************************************* @@ -116,37 +99,14 @@ uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; /* Do not use these definitions directly in your application */ #define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u) #define CY_DELAY_1K_THRESHOLD (1000u) -#define CY_DELAY_1K_MINUS_1_THRESHOLD (CY_DELAY_1K_THRESHOLD - 1u) #define CY_DELAY_1M_THRESHOLD (1000000u) -#define CY_DELAY_1M_MINUS_1_THRESHOLD (CY_DELAY_1M_THRESHOLD - 1u) -uint32_t cy_delayFreqHz = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; -uint32_t cy_delayFreqKhz = (CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / - CY_DELAY_1K_THRESHOLD; +uint32_t cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD); -uint8_t cy_delayFreqMhz = (uint8_t)((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1M_MINUS_1_THRESHOLD) / - CY_DELAY_1M_THRESHOLD); +uint8_t cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1M_THRESHOLD); uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * - ((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD); - -#define CY_ROOT_PATH_SRC_IMO (0UL) -#define CY_ROOT_PATH_SRC_EXT (1UL) -#if (SRSS_ECO_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_ECO (2UL) -#endif /* (SRSS_ECO_PRESENT == 1U) */ -#if (SRSS_ALTHF_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_ALTHF (3UL) -#endif /* (SRSS_ALTHF_PRESENT == 1U) */ -#define CY_ROOT_PATH_SRC_DSI_MUX (4UL) -#define CY_ROOT_PATH_SRC_DSI_MUX_HVILO (16UL) -#define CY_ROOT_PATH_SRC_DSI_MUX_WCO (17UL) -#if (SRSS_ALTLF_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_DSI_MUX_ALTLF (18UL) -#endif /* (SRSS_ALTLF_PRESENT == 1U) */ -#if (SRSS_PILO_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_DSI_MUX_PILO (19UL) -#endif /* (SRSS_PILO_PRESENT == 1U) */ + CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD); /******************************************************************************* @@ -194,15 +154,11 @@ void SystemInit(void) Cy_SystemInit(); SystemCoreClockUpdate(); -#if defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE) - if (CY_SYSLIB_DEVICE_REV_0A == Cy_SysLib_GetDeviceRevision()) - { - /* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */ - IPC_STRUCT7->DATA = 0UL; - /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */ - IPC_STRUCT7->RELEASE = 0UL; - } -#endif /* defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE) */ + /* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */ + REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL; + + /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */ + REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL; #if !defined(CY_IPC_DEFAULT_CFG_DISABLE) /* Allocate and initialize semaphores for the system operations. */ @@ -256,10 +212,7 @@ void SystemInit(void) /* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm0 }; - if (cy_device->flashPipeRequired != 0u) - { - Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0); - } + Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0); #if defined(CY_DEVICE_PSOC6ABLE2) Cy_Flash_Init(); @@ -295,8 +248,7 @@ __WEAK void Cy_SystemInit(void) * Function Name: SystemCoreClockUpdate ****************************************************************************//** * -* Gets core clock frequency and updates \ref SystemCoreClock, \ref -* cy_Hfclk0FreqHz, and \ref cy_PeriClkFreqHz. +* Gets core clock frequency and updates \ref SystemCoreClock. * * Updates global variables used by the \ref Cy_SysLib_Delay(), \ref * Cy_SysLib_DelayUs(), and \ref Cy_SysLib_DelayCycles(). @@ -304,155 +256,19 @@ __WEAK void Cy_SystemInit(void) *******************************************************************************/ void SystemCoreClockUpdate (void) { - uint32_t srcFreqHz; - uint32_t pathFreqHz; - uint32_t slowClkDiv; - uint32_t periClkDiv; - uint32_t rootPath; - uint32_t srcClk; - - /* Get root path clock for the high-frequency clock # 0 */ - rootPath = _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_MUX, SRSS->CLK_ROOT_SELECT[0u]); - - /* Get source of the root path clock */ - srcClk = _FLD2VAL(SRSS_CLK_PATH_SELECT_PATH_MUX, SRSS->CLK_PATH_SELECT[rootPath]); - - /* Get frequency of the source */ - switch (srcClk) - { - case CY_ROOT_PATH_SRC_IMO: - srcFreqHz = CY_CLK_IMO_FREQ_HZ; - break; - - case CY_ROOT_PATH_SRC_EXT: - srcFreqHz = CY_CLK_EXT_FREQ_HZ; - break; - - #if (SRSS_ECO_PRESENT == 1U) - case CY_ROOT_PATH_SRC_ECO: - srcFreqHz = CY_CLK_ECO_FREQ_HZ; - break; - #endif /* (SRSS_ECO_PRESENT == 1U) */ - -#if defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) - case CY_ROOT_PATH_SRC_ALTHF: - srcFreqHz = cy_BleEcoClockFreqHz; - break; -#endif /* defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) */ - - case CY_ROOT_PATH_SRC_DSI_MUX: - { - uint32_t dsi_src; - dsi_src = _FLD2VAL(SRSS_CLK_DSI_SELECT_DSI_MUX, SRSS->CLK_DSI_SELECT[rootPath]); - switch (dsi_src) - { - case CY_ROOT_PATH_SRC_DSI_MUX_HVILO: - srcFreqHz = CY_CLK_HVILO_FREQ_HZ; - break; - - case CY_ROOT_PATH_SRC_DSI_MUX_WCO: - srcFreqHz = CY_CLK_WCO_FREQ_HZ; - break; - - #if (SRSS_ALTLF_PRESENT == 1U) - case CY_ROOT_PATH_SRC_DSI_MUX_ALTLF: - srcFreqHz = CY_CLK_ALTLF_FREQ_HZ; - break; - #endif /* (SRSS_ALTLF_PRESENT == 1U) */ - - #if (SRSS_PILO_PRESENT == 1U) - case CY_ROOT_PATH_SRC_DSI_MUX_PILO: - srcFreqHz = CY_CLK_PILO_FREQ_HZ; - break; - #endif /* (SRSS_PILO_PRESENT == 1U) */ - - default: - srcFreqHz = CY_CLK_HVILO_FREQ_HZ; - break; - } - } - break; - - default: - srcFreqHz = CY_CLK_EXT_FREQ_HZ; - break; - } + uint32 locHf0Clock = Cy_SysClk_ClkHfGetFrequency(0UL); - if (rootPath == 0UL) + if (0UL != locHf0Clock) { - /* FLL */ - bool fllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_FLL_STATUS_LOCKED, SRSS->CLK_FLL_STATUS)); - bool fllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)); - bool fllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)) || - (1UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3))); - if ((fllOutputAuto && fllLocked) || fllOutputOutput) - { - uint32_t fllMult; - uint32_t refDiv; - uint32_t outputDiv; - - fllMult = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_MULT, SRSS->CLK_FLL_CONFIG); - refDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, SRSS->CLK_FLL_CONFIG2); - outputDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, SRSS->CLK_FLL_CONFIG) + 1UL; - - pathFreqHz = ((srcFreqHz / refDiv) * fllMult) / outputDiv; - } - else - { - pathFreqHz = srcFreqHz; - } + cy_Hfclk0FreqHz = locHf0Clock; + cy_PeriClkFreqHz = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkPeriGetDivider()); + SystemCoreClock = cy_PeriClkFreqHz / (1UL + (uint32_t)Cy_SysClk_ClkSlowGetDivider()); + + /* Sets clock frequency for Delay API */ + cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1M_THRESHOLD); + cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1K_THRESHOLD); + cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz; } - else if ((rootPath == 1UL) || (rootPath == 2UL)) - { - /* PLL */ - bool pllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_PLL_STATUS_LOCKED, SRSS->CLK_PLL_STATUS[rootPath - 1UL])); - bool pllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])); - bool pllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])) || - (1UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]))); - if ((pllOutputAuto && pllLocked) || pllOutputOutput) - { - uint32_t feedbackDiv; - uint32_t referenceDiv; - uint32_t outputDiv; - - feedbackDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); - referenceDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_REFERENCE_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); - outputDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_OUTPUT_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); - - pathFreqHz = ((srcFreqHz * feedbackDiv) / referenceDiv) / outputDiv; - - } - else - { - pathFreqHz = srcFreqHz; - } - } - else - { - /* Direct */ - pathFreqHz = srcFreqHz; - } - - /* Get frequency after hf_clk pre-divider */ - pathFreqHz = pathFreqHz >> _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_DIV, SRSS->CLK_ROOT_SELECT[0u]); - cy_Hfclk0FreqHz = pathFreqHz; - - /* Slow Clock Divider */ - slowClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_SLOW_INT_DIV, CPUSS->CM0_CLOCK_CTL); - - /* Peripheral Clock Divider */ - periClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV, CPUSS->CM0_CLOCK_CTL); - - pathFreqHz = pathFreqHz / periClkDiv; - cy_PeriClkFreqHz = pathFreqHz; - pathFreqHz = pathFreqHz / slowClkDiv; - SystemCoreClock = pathFreqHz; - - /* Sets clock frequency for Delay API */ - cy_delayFreqHz = SystemCoreClock; - cy_delayFreqMhz = (uint8_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD); - cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD; - cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz; } diff --git a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct similarity index 97% rename from devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct rename to devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct index 9a43a22..4f8eeea 100644 --- a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xx5_cm4_dual.sct -;* \version 2.60 +;* \version 2.70 ;* ;* Linker file for the ARMCC. ;* @@ -42,7 +42,7 @@ ;* limitations under the License. ;******************************************************************************/ -; Size of the Cortex-M0+ application flash image +; The size of the Cortex-M0+ application flash image #define FLASH_CM0P_SIZE 0x2000 #if !defined(MBED_ROM_START) @@ -82,7 +82,7 @@ #define MBED_BOOT_STACK_SIZE 0x400 #endif -; Size of the stack section at the end of CM4 SRAM +; The size of the stack section at the end of CM4 SRAM #define STACK_SIZE MBED_BOOT_STACK_SIZE ; The defines below describe the location and size of blocks of memory in the target. @@ -181,15 +181,13 @@ LR_IROM1 FLASH_START FLASH_SIZE } ; Application heap area (HEAP) - ARM_LIB_HEAP +0 + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1) { - * (HEAP) } ; Stack region growing down - ARM_LIB_STACK RAM_START+RAM_SIZE -STACK_SIZE + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE { - * (STACK) } ; Used for the digital signature of the secure application and the diff --git a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_ARM/cy8c6xx6_cm4_dual.sct b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx6_cm4_dual.sct similarity index 97% rename from devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_ARM/cy8c6xx6_cm4_dual.sct rename to devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx6_cm4_dual.sct index d19d8e4..ae49aba 100644 --- a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_ARM/cy8c6xx6_cm4_dual.sct +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx6_cm4_dual.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xx6_cm4_dual.sct -;* \version 2.60 +;* \version 2.70 ;* ;* Linker file for the ARMCC. ;* @@ -42,7 +42,7 @@ ;* limitations under the License. ;******************************************************************************/ -; Size of the Cortex-M0+ application flash image +; The size of the Cortex-M0+ application flash image #define FLASH_CM0P_SIZE 0x2000 #if !defined(MBED_ROM_START) @@ -82,7 +82,7 @@ #define MBED_BOOT_STACK_SIZE 0x400 #endif -; Size of the stack section at the end of CM4 SRAM +; The size of the stack section at the end of CM4 SRAM #define STACK_SIZE MBED_BOOT_STACK_SIZE ; The defines below describe the location and size of blocks of memory in the target. @@ -181,15 +181,13 @@ LR_IROM1 FLASH_START FLASH_SIZE } ; Application heap area (HEAP) - ARM_LIB_HEAP +0 + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1) { - * (HEAP) } ; Stack region growing down - ARM_LIB_STACK RAM_START+RAM_SIZE -STACK_SIZE + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE { - * (STACK) } ; Used for the digital signature of the secure application and the diff --git a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct similarity index 97% rename from devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct rename to devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct index 7ccd6c5..0f7f5fe 100644 --- a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xx7_cm4_dual.sct -;* \version 2.60 +;* \version 2.70 ;* ;* Linker file for the ARMCC. ;* @@ -42,7 +42,7 @@ ;* limitations under the License. ;******************************************************************************/ -; Size of the Cortex-M0+ application flash image +; The size of the Cortex-M0+ application flash image #define FLASH_CM0P_SIZE 0x2000 #if !defined(MBED_ROM_START) @@ -82,7 +82,7 @@ #define MBED_BOOT_STACK_SIZE 0x400 #endif -; Size of the stack section at the end of CM4 SRAM +; The size of the stack section at the end of CM4 SRAM #define STACK_SIZE MBED_BOOT_STACK_SIZE ; The defines below describe the location and size of blocks of memory in the target. @@ -181,15 +181,13 @@ LR_IROM1 FLASH_START FLASH_SIZE } ; Application heap area (HEAP) - ARM_LIB_HEAP +0 + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1) { - * (HEAP) } ; Stack region growing down - ARM_LIB_STACK RAM_START+RAM_SIZE -STACK_SIZE + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE { - * (STACK) } ; Used for the digital signature of the secure application and the diff --git a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_ARM/cy8c6xx8_cm4_dual.sct b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx8_cm4_dual.sct similarity index 97% rename from devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_ARM/cy8c6xx8_cm4_dual.sct rename to devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx8_cm4_dual.sct index 93518ae..05248f9 100644 --- a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_ARM/cy8c6xx8_cm4_dual.sct +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx8_cm4_dual.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xx8_cm4_dual.sct -;* \version 2.60 +;* \version 2.70 ;* ;* Linker file for the ARMCC. ;* @@ -42,7 +42,7 @@ ;* limitations under the License. ;******************************************************************************/ -; Size of the Cortex-M0+ application flash image +; The size of the Cortex-M0+ application flash image #define FLASH_CM0P_SIZE 0x2000 #if !defined(MBED_ROM_START) @@ -82,7 +82,7 @@ #define MBED_BOOT_STACK_SIZE 0x400 #endif -; Size of the stack section at the end of CM4 SRAM +; The size of the stack section at the end of CM4 SRAM #define STACK_SIZE MBED_BOOT_STACK_SIZE ; The defines below describe the location and size of blocks of memory in the target. @@ -181,15 +181,13 @@ LR_IROM1 FLASH_START FLASH_SIZE } ; Application heap area (HEAP) - ARM_LIB_HEAP +0 + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1) { - * (HEAP) } ; Stack region growing down - ARM_LIB_STACK RAM_START+RAM_SIZE -STACK_SIZE + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE { - * (STACK) } ; Used for the digital signature of the secure application and the diff --git a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct similarity index 97% rename from devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct rename to devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct index 5537046..620923d 100644 --- a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xxa_cm4_dual.sct -;* \version 2.60 +;* \version 2.70 ;* ;* Linker file for the ARMCC. ;* @@ -42,7 +42,7 @@ ;* limitations under the License. ;******************************************************************************/ -; Size of the Cortex-M0+ application flash image +; The size of the Cortex-M0+ application flash image #define FLASH_CM0P_SIZE 0x2000 #if !defined(MBED_ROM_START) @@ -82,7 +82,7 @@ #define MBED_BOOT_STACK_SIZE 0x400 #endif -; Size of the stack section at the end of CM4 SRAM +; The size of the stack section at the end of CM4 SRAM #define STACK_SIZE MBED_BOOT_STACK_SIZE ; The defines below describe the location and size of blocks of memory in the target. @@ -181,15 +181,13 @@ LR_IROM1 FLASH_START FLASH_SIZE } ; Application heap area (HEAP) - ARM_LIB_HEAP +0 + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1) { - * (HEAP) } ; Stack region growing down - ARM_LIB_STACK RAM_START+RAM_SIZE -STACK_SIZE + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE { - * (STACK) } ; Used for the digital signature of the secure application and the diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx5_cm4.sct b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx5_cm4.sct new file mode 100644 index 0000000..68059e1 --- /dev/null +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx5_cm4.sct @@ -0,0 +1,277 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cyb06xx5_cm4.sct +;* \version 2.70 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +;* MBED_APP_START is being used by the bootloader build script and +;* will be calculate by the system. Without bootloader the MBED_APP_START +;* is equal to MBED_ROM_START +;* +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x00060000 +#endif + +;* MBED_APP_SIZE is being used by the bootloader build script and +;* will be calculate by the system. Without bootloader the MBED_APP_SIZE +;* is equal to MBED_ROM_SIZE +;* +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08000000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x0002A000 +#endif + +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +; The size of the stack section at the end of CM4 SRAM +#define STACK_SIZE MBED_BOOT_STACK_SIZE + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; RAM +#define RAM_START MBED_RAM_START +#define RAM_SIZE MBED_RAM_SIZE +; Flash +#define FLASH_START MBED_APP_START +#define FLASH_SIZE MBED_APP_SIZE + +; The size of the MCU boot header area at the start of FLASH +#define BOOT_HEADER_SIZE 0x00000400 + + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M4 application flash area +LR_IROM1 FLASH_START FLASH_SIZE +{ + ER_FLASH_VECTORS +BOOT_HEADER_SIZE + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1) + { + } + + ; Stack region growing down + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + .cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00070000 +#define __cy_memory_0_row_size 0x200 + + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4.sct similarity index 91% rename from devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct rename to devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4.sct index b2d1ee2..77d3f71 100644 --- a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4.sct @@ -3,8 +3,8 @@ ; to pass a scatter file through a C preprocessor. ;******************************************************************************* -;* \file cyb06xx7_cm4_dual.sct -;* \version 2.60 +;* \file cyb06xx7_cm4.sct +;* \version 2.70 ;* ;* Linker file for the ARMCC. ;* @@ -43,7 +43,7 @@ ;******************************************************************************/ #if !defined(MBED_ROM_START) - #define MBED_ROM_START 0x10000400 + #define MBED_ROM_START 0x10000000 #endif ;* MBED_APP_START is being used by the bootloader build script and @@ -55,7 +55,7 @@ #endif #if !defined(MBED_ROM_SIZE) - #define MBED_ROM_SIZE 0x000CFC00 + #define MBED_ROM_SIZE 0x000D0000 #endif ;* MBED_APP_SIZE is being used by the bootloader build script and @@ -71,25 +71,20 @@ #endif #if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x00020000 + #define MBED_RAM_SIZE 0x0002A000 #endif #if !defined(MBED_BOOT_STACK_SIZE) #define MBED_BOOT_STACK_SIZE 0x400 #endif -; Size of the stack section at the end of CM4 SRAM +; The size of the stack section at the end of CM4 SRAM #define STACK_SIZE MBED_BOOT_STACK_SIZE ; The defines below describe the location and size of blocks of memory in the target. ; Use these defines to specify the memory regions available for allocation. ; The following defines control RAM and flash memory allocation for the CM4 core. -; You can change the memory allocation by editing RAM and Flash defines. -; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. -; Using this memory region for other purposes will lead to unexpected behavior. -; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', -; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. ; RAM #define RAM_START MBED_RAM_START #define RAM_SIZE MBED_RAM_SIZE @@ -97,6 +92,9 @@ #define FLASH_START MBED_APP_START #define FLASH_SIZE MBED_APP_SIZE +; The size of the MCU boot header area at the start of FLASH +#define BOOT_HEADER_SIZE 0x00000400 + ; The following defines describe a 32K flash region used for EEPROM emulation. ; This region can also be used as the general purpose flash. ; You can assign sections to this memory region for only one of the cores. @@ -138,7 +136,7 @@ ; Cortex-M4 application flash area LR_IROM1 FLASH_START FLASH_SIZE { - ER_FLASH_VECTORS +0 + ER_FLASH_VECTORS +BOOT_HEADER_SIZE { * (RESET, +FIRST) } @@ -168,17 +166,15 @@ LR_IROM1 FLASH_START FLASH_SIZE } ; Application heap area (HEAP) - ARM_LIB_HEAP +0 + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1) { - * (HEAP) } ; Stack region growing down - ARM_LIB_STACK RAM_START+RAM_SIZE -STACK_SIZE + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE { - * (STACK) - } - + } + ; Used for the digital signature of the secure application and the ; Bootloader SDK application. The size of the section depends on the required ; data size. diff --git a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_ARM/cyb06xxa_cm4_dual.sct b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4.sct similarity index 91% rename from devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_ARM/cyb06xxa_cm4_dual.sct rename to devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4.sct index 2e5ebd3..0a03d5c 100644 --- a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_ARM/cyb06xxa_cm4_dual.sct +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4.sct @@ -3,8 +3,8 @@ ; to pass a scatter file through a C preprocessor. ;******************************************************************************* -;* \file cyb06xxa_cm4_dual.sct -;* \version 2.60 +;* \file cyb06xxa_cm4.sct +;* \version 2.70 ;* ;* Linker file for the ARMCC. ;* @@ -43,7 +43,7 @@ ;******************************************************************************/ #if !defined(MBED_ROM_START) - #define MBED_ROM_START 0x10000400 + #define MBED_ROM_START 0x10000000 #endif ;* MBED_APP_START is being used by the bootloader build script and @@ -55,7 +55,7 @@ #endif #if !defined(MBED_ROM_SIZE) - #define MBED_ROM_SIZE 0x001CFC00 + #define MBED_ROM_SIZE 0x001D0000 #endif ;* MBED_APP_SIZE is being used by the bootloader build script and @@ -71,25 +71,20 @@ #endif #if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x000D8000 + #define MBED_RAM_SIZE 0x000EA000 #endif #if !defined(MBED_BOOT_STACK_SIZE) #define MBED_BOOT_STACK_SIZE 0x400 #endif -; Size of the stack section at the end of CM4 SRAM +; The size of the stack section at the end of CM4 SRAM #define STACK_SIZE MBED_BOOT_STACK_SIZE ; The defines below describe the location and size of blocks of memory in the target. ; Use these defines to specify the memory regions available for allocation. ; The following defines control RAM and flash memory allocation for the CM4 core. -; You can change the memory allocation by editing RAM and Flash defines. -; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. -; Using this memory region for other purposes will lead to unexpected behavior. -; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', -; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. ; RAM #define RAM_START MBED_RAM_START #define RAM_SIZE MBED_RAM_SIZE @@ -97,6 +92,9 @@ #define FLASH_START MBED_APP_START #define FLASH_SIZE MBED_APP_SIZE +; The size of the MCU boot header area at the start of FLASH +#define BOOT_HEADER_SIZE 0x00000400 + ; The following defines describe a 32K flash region used for EEPROM emulation. ; This region can also be used as the general purpose flash. ; You can assign sections to this memory region for only one of the cores. @@ -138,7 +136,7 @@ ; Cortex-M4 application flash area LR_IROM1 FLASH_START FLASH_SIZE { - ER_FLASH_VECTORS +0 + ER_FLASH_VECTORS +BOOT_HEADER_SIZE { * (RESET, +FIRST) } @@ -168,17 +166,15 @@ LR_IROM1 FLASH_START FLASH_SIZE } ; Application heap area (HEAP) - ARM_LIB_HEAP +0 + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1) { - * (HEAP) } ; Stack region growing down - ARM_LIB_STACK RAM_START+RAM_SIZE -STACK_SIZE + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE { - * (STACK) - } - + } + ; Used for the digital signature of the secure application and the ; Bootloader SDK application. The size of the section depends on the required ; data size. diff --git a/devices/bsp/COMPONENT_MBED/startup/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S similarity index 96% rename from devices/bsp/COMPONENT_MBED/startup/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S rename to devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S index 5bd2271..fa2247e 100644 --- a/devices/bsp/COMPONENT_MBED/startup/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S @@ -23,36 +23,6 @@ ; * limitations under the License. ; */ -;/* -;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -;*/ - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - IF :DEF:__STACK_SIZE -Stack_Size EQU __STACK_SIZE - ELSE -Stack_Size EQU 0x00000400 - ENDIF - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - IF :DEF:__HEAP_SIZE -Heap_Size EQU __HEAP_SIZE - ELSE -Heap_Size EQU 0x00000400 - ENDIF - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 THUMB @@ -62,8 +32,9 @@ __heap_limit EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| -__Vectors DCD __initial_sp ; Top of Stack +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack DCD Reset_Handler ; Reset Handler DCD 0x0000000D ; NMI Handler located at ROM code @@ -661,23 +632,6 @@ pass_interrupt_dacs_IRQHandler ALIGN - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - - ALIGN - - ENDIF - END diff --git a/devices/bsp/COMPONENT_MBED/startup/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S similarity index 97% rename from devices/bsp/COMPONENT_MBED/startup/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S rename to devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S index dddf31e..114d71e 100644 --- a/devices/bsp/COMPONENT_MBED/startup/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S @@ -23,36 +23,6 @@ ; * limitations under the License. ; */ -;/* -;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -;*/ - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - IF :DEF:__STACK_SIZE -Stack_Size EQU __STACK_SIZE - ELSE -Stack_Size EQU 0x00000400 - ENDIF - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - IF :DEF:__HEAP_SIZE -Heap_Size EQU __HEAP_SIZE - ELSE -Heap_Size EQU 0x00000400 - ENDIF - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 THUMB @@ -62,8 +32,9 @@ __heap_limit EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| -__Vectors DCD __initial_sp ; Top of Stack +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack DCD Reset_Handler ; Reset Handler DCD 0x0000000D ; NMI Handler located at ROM code @@ -724,23 +695,6 @@ sdhc_1_interrupt_general_IRQHandler ALIGN - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - - ALIGN - - ENDIF - END diff --git a/devices/bsp/COMPONENT_MBED/startup/TOOLCHAIN_ARM/startup_psoc6_03_cm4.S b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_03_cm4.S similarity index 97% rename from devices/bsp/COMPONENT_MBED/startup/TOOLCHAIN_ARM/startup_psoc6_03_cm4.S rename to devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_03_cm4.S index e3f3cbf..f4739ec 100644 --- a/devices/bsp/COMPONENT_MBED/startup/TOOLCHAIN_ARM/startup_psoc6_03_cm4.S +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_03_cm4.S @@ -23,36 +23,6 @@ ; * limitations under the License. ; */ -;/* -;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -;*/ - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - IF :DEF:__STACK_SIZE -Stack_Size EQU __STACK_SIZE - ELSE -Stack_Size EQU 0x00000400 - ENDIF - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - IF :DEF:__HEAP_SIZE -Heap_Size EQU __HEAP_SIZE - ELSE -Heap_Size EQU 0x00000400 - ENDIF - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 THUMB @@ -62,8 +32,9 @@ __heap_limit EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| -__Vectors DCD __initial_sp ; Top of Stack +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack DCD Reset_Handler ; Reset Handler DCD 0x0000000D ; NMI Handler located at ROM code @@ -668,23 +639,6 @@ cpuss_interrupts_dw1_31_IRQHandler ALIGN - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - - ALIGN - - ENDIF - END diff --git a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm4_dual.ld b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm4_dual.ld similarity index 98% rename from devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm4_dual.ld rename to devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm4_dual.ld index be9d6bd..f6fbe4a 100644 --- a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm4_dual.ld +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm4_dual.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx5_cm4_dual.ld -* \version 2.60 +* \version 2.70 * * Linker file for the GNU C compiler. * @@ -40,7 +40,7 @@ SEARCH_DIR(.) GROUP(-lgcc -lc -lnosys) ENTRY(Reset_Handler) -/* Size of the Cortex-M0+ application image at the start of FLASH */ +/* The size of the Cortex-M0+ application image at the start of FLASH */ FLASH_CM0P_SIZE = 0x2000; #if !defined(MBED_ROM_START) @@ -79,7 +79,7 @@ FLASH_CM0P_SIZE = 0x2000; #define MBED_BOOT_STACK_SIZE 0x400 #endif -/* Size of the stack section at the end of CM4 SRAM */ +/* The size of the stack section at the end of CM4 SRAM */ STACK_SIZE = MBED_BOOT_STACK_SIZE; /* Force symbol to be entered in the output file as an undefined symbol. Doing diff --git a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_GCC_ARM/cy8c6xx6_cm4_dual.ld b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx6_cm4_dual.ld similarity index 98% rename from devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_GCC_ARM/cy8c6xx6_cm4_dual.ld rename to devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx6_cm4_dual.ld index fed99cb..9de6a36 100644 --- a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_GCC_ARM/cy8c6xx6_cm4_dual.ld +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx6_cm4_dual.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx6_cm4_dual.ld -* \version 2.60 +* \version 2.70 * * Linker file for the GNU C compiler. * @@ -40,7 +40,7 @@ SEARCH_DIR(.) GROUP(-lgcc -lc -lnosys) ENTRY(Reset_Handler) -/* Size of the Cortex-M0+ application image at the start of FLASH */ +/* The size of the Cortex-M0+ application image at the start of FLASH */ FLASH_CM0P_SIZE = 0x2000; #if !defined(MBED_ROM_START) @@ -79,7 +79,7 @@ FLASH_CM0P_SIZE = 0x2000; #define MBED_BOOT_STACK_SIZE 0x400 #endif -/* Size of the stack section at the end of CM4 SRAM */ +/* The size of the stack section at the end of CM4 SRAM */ STACK_SIZE = MBED_BOOT_STACK_SIZE; /* Force symbol to be entered in the output file as an undefined symbol. Doing diff --git a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld similarity index 98% rename from devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld rename to devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld index e7c641e..9be3c4a 100644 --- a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx7_cm4_dual.ld -* \version 2.60 +* \version 2.70 * * Linker file for the GNU C compiler. * @@ -40,7 +40,7 @@ SEARCH_DIR(.) GROUP(-lgcc -lc -lnosys) ENTRY(Reset_Handler) -/* Size of the Cortex-M0+ application image at the start of FLASH */ +/* The size of the Cortex-M0+ application image at the start of FLASH */ FLASH_CM0P_SIZE = 0x2000; #if !defined(MBED_ROM_START) @@ -79,7 +79,7 @@ FLASH_CM0P_SIZE = 0x2000; #define MBED_BOOT_STACK_SIZE 0x400 #endif -/* Size of the stack section at the end of CM4 SRAM */ +/* The size of the stack section at the end of CM4 SRAM */ STACK_SIZE = MBED_BOOT_STACK_SIZE; /* Force symbol to be entered in the output file as an undefined symbol. Doing diff --git a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_GCC_ARM/cy8c6xx8_cm4_dual.ld b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx8_cm4_dual.ld similarity index 98% rename from devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_GCC_ARM/cy8c6xx8_cm4_dual.ld rename to devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx8_cm4_dual.ld index 7ea0275..0f94372 100644 --- a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_GCC_ARM/cy8c6xx8_cm4_dual.ld +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx8_cm4_dual.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx8_cm4_dual.ld -* \version 2.60 +* \version 2.70 * * Linker file for the GNU C compiler. * @@ -40,7 +40,7 @@ SEARCH_DIR(.) GROUP(-lgcc -lc -lnosys) ENTRY(Reset_Handler) -/* Size of the Cortex-M0+ application image at the start of FLASH */ +/* The size of the Cortex-M0+ application image at the start of FLASH */ FLASH_CM0P_SIZE = 0x2000; #if !defined(MBED_ROM_START) @@ -79,7 +79,7 @@ FLASH_CM0P_SIZE = 0x2000; #define MBED_BOOT_STACK_SIZE 0x400 #endif -/* Size of the stack section at the end of CM4 SRAM */ +/* The size of the stack section at the end of CM4 SRAM */ STACK_SIZE = MBED_BOOT_STACK_SIZE; /* Force symbol to be entered in the output file as an undefined symbol. Doing diff --git a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld similarity index 98% rename from devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld rename to devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld index 964fb03..ffbeca9 100644 --- a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xxa_cm4_dual.ld -* \version 2.60 +* \version 2.70 * * Linker file for the GNU C compiler. * @@ -40,7 +40,7 @@ SEARCH_DIR(.) GROUP(-lgcc -lc -lnosys) ENTRY(Reset_Handler) -/* Size of the Cortex-M0+ application image at the start of FLASH */ +/* The size of the Cortex-M0+ application image at the start of FLASH */ FLASH_CM0P_SIZE = 0x2000; #if !defined(MBED_ROM_START) @@ -79,7 +79,7 @@ FLASH_CM0P_SIZE = 0x2000; #define MBED_BOOT_STACK_SIZE 0x400 #endif -/* Size of the stack section at the end of CM4 SRAM */ +/* The size of the stack section at the end of CM4 SRAM */ STACK_SIZE = MBED_BOOT_STACK_SIZE; /* Force symbol to be entered in the output file as an undefined symbol. Doing diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx5_cm4.ld b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx5_cm4.ld new file mode 100644 index 0000000..f5220a9 --- /dev/null +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx5_cm4.ld @@ -0,0 +1,432 @@ +/***************************************************************************//** +* \file cyb06xx5_cm4.ld +* \version 2.70 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +/* MBED_APP_START is being used by the bootloader build script and +* will be calculate by the system. Without bootloader the MBED_APP_START +* is equal to MBED_ROM_START +*/ +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x00060000 +#endif + +/* MBED_APP_SIZE is being used by the bootloader build script and +* will be calculate by the system. Without bootloader the MBED_APP_SIZE +* is equal to MBED_ROM_SIZE +*/ +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08000000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x0002A000 +#endif + +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +/* The size of the stack section at the end of CM4 SRAM */ +STACK_SIZE = MBED_BOOT_STACK_SIZE; + +/* The size of the MCU boot header area at the start of FLASH */ +BOOT_HEADER_SIZE = 0x400; + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM4 core. + */ + ram (rwx) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE + flash (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE + + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + /* Cortex-M4 application flash area */ + .text ORIGIN(flash) + BOOT_HEADER_SIZE : + { + /* Cortex-M4 flash vector table */ + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_03_cm4.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_03_cm4.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Used for the digital signature of the secure application and the Bootloader SDK application. + * The size of the section depends on the required data size. */ + .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 : + { + KEEP(*(.cy_app_signature)) + } > flash + + + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + .cy_xip : + { + KEEP(*(.cy_xip)) + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x00070000; +__cy_memory_0_row_size = 0x200; + + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4_dual.ld b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4.ld similarity index 94% rename from devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4_dual.ld rename to devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4.ld index 0a81d0b..da76487 100644 --- a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4_dual.ld +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4.ld @@ -1,6 +1,6 @@ /***************************************************************************//** -* \file cyb06xx7_cm4_dual.ld -* \version 2.60 +* \file cyb06xx7_cm4.ld +* \version 2.70 * * Linker file for the GNU C compiler. * @@ -41,7 +41,7 @@ GROUP(-lgcc -lc -lnosys) ENTRY(Reset_Handler) #if !defined(MBED_ROM_START) - #define MBED_ROM_START 0x10000400 + #define MBED_ROM_START 0x10000000 #endif /* MBED_APP_START is being used by the bootloader build script and @@ -53,7 +53,7 @@ ENTRY(Reset_Handler) #endif #if !defined(MBED_ROM_SIZE) - #define MBED_ROM_SIZE 0x000CFC00 + #define MBED_ROM_SIZE 0x000D0000 #endif /* MBED_APP_SIZE is being used by the bootloader build script and @@ -69,16 +69,19 @@ ENTRY(Reset_Handler) #endif #if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x00020000 + #define MBED_RAM_SIZE 0x0002A000 #endif #if !defined(MBED_BOOT_STACK_SIZE) #define MBED_BOOT_STACK_SIZE 0x400 #endif -/* Size of the stack section at the end of CM4 SRAM */ +/* The size of the stack section at the end of CM4 SRAM */ STACK_SIZE = MBED_BOOT_STACK_SIZE; +/* The size of the MCU boot header area at the start of FLASH */ +BOOT_HEADER_SIZE = 0x400; + /* Force symbol to be entered in the output file as an undefined symbol. Doing * this may, for example, trigger linking of additional modules from standard * libraries. You may list several symbols for each EXTERN, and you may use @@ -93,11 +96,6 @@ EXTERN(Reset_Handler) MEMORY { /* The ram and flash regions control RAM and flash memory allocation for the CM4 core. - * You can change the memory allocation by editing the 'ram' and 'flash' regions. - * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. - * Using this memory region for other purposes will lead to unexpected behavior. - * Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld', - * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'. */ ram (rwx) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE flash (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE @@ -159,8 +157,9 @@ GROUP(libgcc.a libc.a libm.a libnosys.a) SECTIONS { /* Cortex-M4 application flash area */ - .text ORIGIN(flash) : + .text ORIGIN(flash) + BOOT_HEADER_SIZE : { + /* Cortex-M4 flash vector table */ . = ALIGN(4); __Vectors = . ; KEEP(*(.vectors)) diff --git a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4_dual.ld b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4.ld similarity index 94% rename from devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4_dual.ld rename to devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4.ld index ac40c26..6bc500f 100644 --- a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4_dual.ld +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4.ld @@ -1,6 +1,6 @@ /***************************************************************************//** -* \file cyb06xxa_cm4_dual.ld -* \version 2.60 +* \file cyb06xxa_cm4.ld +* \version 2.70 * * Linker file for the GNU C compiler. * @@ -41,7 +41,7 @@ GROUP(-lgcc -lc -lnosys) ENTRY(Reset_Handler) #if !defined(MBED_ROM_START) - #define MBED_ROM_START 0x10000400 + #define MBED_ROM_START 0x10000000 #endif /* MBED_APP_START is being used by the bootloader build script and @@ -53,7 +53,7 @@ ENTRY(Reset_Handler) #endif #if !defined(MBED_ROM_SIZE) - #define MBED_ROM_SIZE 0x001CFC00 + #define MBED_ROM_SIZE 0x001D0000 #endif /* MBED_APP_SIZE is being used by the bootloader build script and @@ -69,16 +69,19 @@ ENTRY(Reset_Handler) #endif #if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x000D8000 + #define MBED_RAM_SIZE 0x000EA000 #endif #if !defined(MBED_BOOT_STACK_SIZE) #define MBED_BOOT_STACK_SIZE 0x400 #endif -/* Size of the stack section at the end of CM4 SRAM */ +/* The size of the stack section at the end of CM4 SRAM */ STACK_SIZE = MBED_BOOT_STACK_SIZE; +/* The size of the MCU boot header area at the start of FLASH */ +BOOT_HEADER_SIZE = 0x400; + /* Force symbol to be entered in the output file as an undefined symbol. Doing * this may, for example, trigger linking of additional modules from standard * libraries. You may list several symbols for each EXTERN, and you may use @@ -93,11 +96,6 @@ EXTERN(Reset_Handler) MEMORY { /* The ram and flash regions control RAM and flash memory allocation for the CM4 core. - * You can change the memory allocation by editing the 'ram' and 'flash' regions. - * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. - * Using this memory region for other purposes will lead to unexpected behavior. - * Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld', - * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'. */ ram (rwx) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE flash (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE @@ -159,8 +157,9 @@ GROUP(libgcc.a libc.a libm.a libnosys.a) SECTIONS { /* Cortex-M4 application flash area */ - .text ORIGIN(flash) : + .text ORIGIN(flash) + BOOT_HEADER_SIZE : { + /* Cortex-M4 flash vector table */ . = ALIGN(4); __Vectors = . ; KEEP(*(.vectors)) diff --git a/devices/bsp/COMPONENT_MBED/startup/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S similarity index 100% rename from devices/bsp/COMPONENT_MBED/startup/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S rename to devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S diff --git a/devices/bsp/COMPONENT_MBED/startup/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S similarity index 100% rename from devices/bsp/COMPONENT_MBED/startup/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S rename to devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S diff --git a/devices/bsp/COMPONENT_MBED/startup/TOOLCHAIN_GCC_ARM/startup_psoc6_03_cm4.S b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_03_cm4.S similarity index 100% rename from devices/bsp/COMPONENT_MBED/startup/TOOLCHAIN_GCC_ARM/startup_psoc6_03_cm4.S rename to devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_03_cm4.S diff --git a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_IAR/cy8c6xx5_cm4_dual.icf b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx5_cm4_dual.icf similarity index 99% rename from devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_IAR/cy8c6xx5_cm4_dual.icf rename to devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx5_cm4_dual.icf index fc2074a..07f3242 100644 --- a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_IAR/cy8c6xx5_cm4_dual.icf +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx5_cm4_dual.icf @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx5_cm4_dual.icf -* \version 2.60 +* \version 2.70 * * Linker file for the IAR compiler. * @@ -41,7 +41,7 @@ /*-Specials-*/ define symbol __ICFEDIT_intvec_start__ = 0x00000000; -/* Size of the Cortex-M0+ application image */ +/* The size of the Cortex-M0+ application image */ define symbol FLASH_CM0P_SIZE = 0x2000; if (!isdefinedsymbol(MBED_ROM_START)) { @@ -108,7 +108,7 @@ define symbol __ICFEDIT_region_IROM0_end__ = (MBED_ROM_START + FLASH_CM0P_SIZE define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE); -/* The following symbols define a 32K flash region used for EEPROM emulation. +/* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. * You can assign sections to this memory region for only one of the cores. * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. diff --git a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_IAR/cy8c6xx6_cm4_dual.icf b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx6_cm4_dual.icf similarity index 99% rename from devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_IAR/cy8c6xx6_cm4_dual.icf rename to devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx6_cm4_dual.icf index cd0a8a4..bd1a118 100644 --- a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_IAR/cy8c6xx6_cm4_dual.icf +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx6_cm4_dual.icf @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx6_cm4_dual.icf -* \version 2.60 +* \version 2.70 * * Linker file for the IAR compiler. * @@ -41,7 +41,7 @@ /*-Specials-*/ define symbol __ICFEDIT_intvec_start__ = 0x00000000; -/* Size of the Cortex-M0+ application image */ +/* The size of the Cortex-M0+ application image */ define symbol FLASH_CM0P_SIZE = 0x2000; if (!isdefinedsymbol(MBED_ROM_START)) { @@ -108,7 +108,7 @@ define symbol __ICFEDIT_region_IROM0_end__ = (MBED_ROM_START + FLASH_CM0P_SIZE define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE); -/* The following symbols define a 32K flash region used for EEPROM emulation. +/* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. * You can assign sections to this memory region for only one of the cores. * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. diff --git a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf similarity index 99% rename from devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf rename to devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf index ae61379..b405a8b 100644 --- a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx7_cm4_dual.icf -* \version 2.60 +* \version 2.70 * * Linker file for the IAR compiler. * @@ -41,7 +41,7 @@ /*-Specials-*/ define symbol __ICFEDIT_intvec_start__ = 0x00000000; -/* Size of the Cortex-M0+ application image */ +/* The size of the Cortex-M0+ application image */ define symbol FLASH_CM0P_SIZE = 0x2000; if (!isdefinedsymbol(MBED_ROM_START)) { @@ -108,7 +108,7 @@ define symbol __ICFEDIT_region_IROM0_end__ = (MBED_ROM_START + FLASH_CM0P_SIZE define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE); -/* The following symbols define a 32K flash region used for EEPROM emulation. +/* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. * You can assign sections to this memory region for only one of the cores. * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. diff --git a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_IAR/cy8c6xx8_cm4_dual.icf b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx8_cm4_dual.icf similarity index 99% rename from devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_IAR/cy8c6xx8_cm4_dual.icf rename to devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx8_cm4_dual.icf index ea10310..dfb32a4 100644 --- a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_IAR/cy8c6xx8_cm4_dual.icf +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx8_cm4_dual.icf @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx8_cm4_dual.icf -* \version 2.60 +* \version 2.70 * * Linker file for the IAR compiler. * @@ -41,7 +41,7 @@ /*-Specials-*/ define symbol __ICFEDIT_intvec_start__ = 0x00000000; -/* Size of the Cortex-M0+ application image */ +/* The size of the Cortex-M0+ application image */ define symbol FLASH_CM0P_SIZE = 0x2000; if (!isdefinedsymbol(MBED_ROM_START)) { @@ -108,7 +108,7 @@ define symbol __ICFEDIT_region_IROM0_end__ = (MBED_ROM_START + FLASH_CM0P_SIZE define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE); -/* The following symbols define a 32K flash region used for EEPROM emulation. +/* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. * You can assign sections to this memory region for only one of the cores. * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. diff --git a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf similarity index 99% rename from devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf rename to devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf index 7f2b290..3080c25 100644 --- a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xxa_cm4_dual.icf -* \version 2.60 +* \version 2.70 * * Linker file for the IAR compiler. * @@ -41,7 +41,7 @@ /*-Specials-*/ define symbol __ICFEDIT_intvec_start__ = 0x00000000; -/* Size of the Cortex-M0+ application image */ +/* The size of the Cortex-M0+ application image */ define symbol FLASH_CM0P_SIZE = 0x2000; if (!isdefinedsymbol(MBED_ROM_START)) { @@ -108,7 +108,7 @@ define symbol __ICFEDIT_region_IROM0_end__ = (MBED_ROM_START + FLASH_CM0P_SIZE define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE); -/* The following symbols define a 32K flash region used for EEPROM emulation. +/* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. * You can assign sections to this memory region for only one of the cores. * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx5_cm4.icf b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx5_cm4.icf new file mode 100644 index 0000000..b1e1283 --- /dev/null +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx5_cm4.icf @@ -0,0 +1,265 @@ +/***************************************************************************//** +* \file cyb06xx5_cm4.icf +* \version 2.70 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +if (!isdefinedsymbol(MBED_ROM_START)) { + define symbol MBED_ROM_START = 0x10000000; +} + +/* MBED_APP_START is being used by the bootloader build script and + * will be calculate by the system. Without bootloader the MBED_APP_START + * is equal to MBED_ROM_START + */ +if (!isdefinedsymbol(MBED_APP_START)) { + define symbol MBED_APP_START = MBED_ROM_START; +} + +if (!isdefinedsymbol(MBED_ROM_SIZE)) { + define symbol MBED_ROM_SIZE = 0x00060000; +} + +/* MBED_APP_SIZE is being used by the bootloader build script and + * will be calculate by the system. Without bootloader the MBED_APP_SIZE + * is equal to MBED_ROM_SIZE + */ +if (!isdefinedsymbol(MBED_APP_SIZE)) { + define symbol MBED_APP_SIZE = MBED_ROM_SIZE; +} + +if (!isdefinedsymbol(MBED_RAM_START)) { + define symbol MBED_RAM_START = 0x08000000; +} + +if (!isdefinedsymbol(MBED_RAM_SIZE)) { + define symbol MBED_RAM_SIZE = 0x0002A000; +} + +if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { + define symbol MBED_BOOT_STACK_SIZE = 0x400; +} + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM4 core. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; +define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE); +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; +define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE); + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x160007FF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/*-Sizes-*/ +if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; +} else { + define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; +} + +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} +/**** End of ICF editor section. ###ICF###*/ + +/* The size of the MCU boot header area at the start of FLASH */ +define symbol BOOT_HEADER_SIZE = 0x400; + + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; + +define block RAM_DATA {readwrite section .data}; +define block RAM_OTHER {readwrite section * }; +define block RAM_NOINIT {readwrite section .noinit}; +define block RAM_BSS {readwrite section .bss}; +define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NOINIT, block RAM_BSS}; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; + +define block RO {first section .intvec, readonly}; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M4 application */ +place at address (__ICFEDIT_region_IROM1_start__ + BOOT_HEADER_SIZE) { block RO }; + +/* Used for the digital signature of the secure application and the Bootloader SDK application. */ +".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; + + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +".cy_xip" : place at start of EROM1_region { section .cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { block RAM}; +place in IRAM1_region { block HEAP}; +place at end of IRAM1_region { block CSTACK }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_app_signature, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00070000; +define exported symbol __cy_memory_0_row_size = 0x200; + + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_IAR/cyb06xx7_cm4_dual.icf b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx7_cm4.icf similarity index 94% rename from devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_IAR/cyb06xx7_cm4_dual.icf rename to devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx7_cm4.icf index f6322dc..076a8ff 100644 --- a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_IAR/cyb06xx7_cm4_dual.icf +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx7_cm4.icf @@ -1,6 +1,6 @@ /***************************************************************************//** -* \file cyb06xx7_cm4_dual.icf -* \version 2.60 +* \file cyb06xx7_cm4.icf +* \version 2.70 * * Linker file for the IAR compiler. * @@ -42,7 +42,7 @@ define symbol __ICFEDIT_intvec_start__ = 0x00000000; if (!isdefinedsymbol(MBED_ROM_START)) { - define symbol MBED_ROM_START = 0x10000400; + define symbol MBED_ROM_START = 0x10000000; } /* MBED_APP_START is being used by the bootloader build script and @@ -54,7 +54,7 @@ if (!isdefinedsymbol(MBED_APP_START)) { } if (!isdefinedsymbol(MBED_ROM_SIZE)) { - define symbol MBED_ROM_SIZE = 0x000CFC00; + define symbol MBED_ROM_SIZE = 0x000D0000; } /* MBED_APP_SIZE is being used by the bootloader build script and @@ -70,7 +70,7 @@ if (!isdefinedsymbol(MBED_RAM_START)) { } if (!isdefinedsymbol(MBED_RAM_SIZE)) { - define symbol MBED_RAM_SIZE = 0x00020000; + define symbol MBED_RAM_SIZE = 0x0002A000; } if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { @@ -82,11 +82,6 @@ if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { */ /* The following symbols control RAM and flash memory allocation for the CM4 core. - * You can change the memory allocation by editing RAM and Flash symbols. - * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. - * Using this memory region for other purposes will lead to unexpected behavior. - * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf', - * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'. */ /* RAM */ define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; @@ -95,7 +90,7 @@ define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE); define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE); -/* The following symbols define a 32K flash region used for EEPROM emulation. +/* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. * You can assign sections to this memory region for only one of the cores. * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. @@ -162,6 +157,10 @@ if (!isdefinedsymbol(__HEAP_SIZE)) { } /**** End of ICF editor section. ###ICF###*/ +/* The size of the MCU boot header area at the start of FLASH */ +define symbol BOOT_HEADER_SIZE = 0x400; + + define memory mem with size = 4G; define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; @@ -192,7 +191,7 @@ do not initialize { section .noinit, section .intvec_ram }; /*-Placement-*/ /* Flash - Cortex-M4 application */ -place at start of IROM1_region { block RO }; +place at address (__ICFEDIT_region_IROM1_start__ + BOOT_HEADER_SIZE) { block RO }; /* Used for the digital signature of the secure application and the Bootloader SDK application. */ ".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; diff --git a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_IAR/cyb06xxa_cm4_dual.icf b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xxa_cm4.icf similarity index 94% rename from devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_IAR/cyb06xxa_cm4_dual.icf rename to devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xxa_cm4.icf index dad6602..22ac13a 100644 --- a/devices/bsp/COMPONENT_MBED/linker/TOOLCHAIN_IAR/cyb06xxa_cm4_dual.icf +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xxa_cm4.icf @@ -1,6 +1,6 @@ /***************************************************************************//** -* \file cyb06xxa_cm4_dual.icf -* \version 2.60 +* \file cyb06xxa_cm4.icf +* \version 2.70 * * Linker file for the IAR compiler. * @@ -42,7 +42,7 @@ define symbol __ICFEDIT_intvec_start__ = 0x00000000; if (!isdefinedsymbol(MBED_ROM_START)) { - define symbol MBED_ROM_START = 0x10000400; + define symbol MBED_ROM_START = 0x10000000; } /* MBED_APP_START is being used by the bootloader build script and @@ -54,7 +54,7 @@ if (!isdefinedsymbol(MBED_APP_START)) { } if (!isdefinedsymbol(MBED_ROM_SIZE)) { - define symbol MBED_ROM_SIZE = 0x001CFC00; + define symbol MBED_ROM_SIZE = 0x001D0000; } /* MBED_APP_SIZE is being used by the bootloader build script and @@ -70,7 +70,7 @@ if (!isdefinedsymbol(MBED_RAM_START)) { } if (!isdefinedsymbol(MBED_RAM_SIZE)) { - define symbol MBED_RAM_SIZE = 0x000D8000; + define symbol MBED_RAM_SIZE = 0x000EA000; } if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { @@ -82,11 +82,6 @@ if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { */ /* The following symbols control RAM and flash memory allocation for the CM4 core. - * You can change the memory allocation by editing RAM and Flash symbols. - * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. - * Using this memory region for other purposes will lead to unexpected behavior. - * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf', - * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'. */ /* RAM */ define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; @@ -95,7 +90,7 @@ define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE); define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE); -/* The following symbols define a 32K flash region used for EEPROM emulation. +/* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. * You can assign sections to this memory region for only one of the cores. * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. @@ -162,6 +157,10 @@ if (!isdefinedsymbol(__HEAP_SIZE)) { } /**** End of ICF editor section. ###ICF###*/ +/* The size of the MCU boot header area at the start of FLASH */ +define symbol BOOT_HEADER_SIZE = 0x400; + + define memory mem with size = 4G; define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; @@ -192,7 +191,7 @@ do not initialize { section .noinit, section .intvec_ram }; /*-Placement-*/ /* Flash - Cortex-M4 application */ -place at start of IROM1_region { block RO }; +place at address (__ICFEDIT_region_IROM1_start__ + BOOT_HEADER_SIZE) { block RO }; /* Used for the digital signature of the secure application and the Bootloader SDK application. */ ".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; diff --git a/devices/bsp/COMPONENT_MBED/startup/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S similarity index 100% rename from devices/bsp/COMPONENT_MBED/startup/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S rename to devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S diff --git a/devices/bsp/COMPONENT_MBED/startup/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S similarity index 100% rename from devices/bsp/COMPONENT_MBED/startup/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S rename to devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S diff --git a/devices/bsp/COMPONENT_MBED/startup/TOOLCHAIN_IAR/startup_psoc6_03_cm4.S b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_03_cm4.S similarity index 100% rename from devices/bsp/COMPONENT_MBED/startup/TOOLCHAIN_IAR/startup_psoc6_03_cm4.S rename to devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_03_cm4.S diff --git a/devices/bsp/COMPONENT_MTB/startup/system_psoc6_cm4.c b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/system_psoc6_cm4.c similarity index 63% rename from devices/bsp/COMPONENT_MTB/startup/system_psoc6_cm4.c rename to devices/templates/COMPONENT_MBED/COMPONENT_CM4/system_psoc6_cm4.c index 0a18f50..7800d6b 100644 --- a/devices/bsp/COMPONENT_MTB/startup/system_psoc6_cm4.c +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/system_psoc6_cm4.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file system_psoc6_cm4.c -* \version 2.60 +* \version 2.70 * * The device system-source file. * @@ -27,6 +27,7 @@ #include "cy_device.h" #include "cy_device_headers.h" #include "cy_syslib.h" +#include "cy_sysclk.h" #include "cy_wdt.h" #if !defined(CY_IPC_DEFAULT_CFG_DISABLE) @@ -50,24 +51,9 @@ /** Default PeriClk frequency in Hz */ #define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (4000000UL) -/** Default SlowClk system core frequency in Hz */ +/** Default FastClk system core frequency in Hz */ #define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (8000000UL) -/** IMO frequency in Hz */ -#define CY_CLK_IMO_FREQ_HZ (8000000UL) - -/** HVILO frequency in Hz */ -#define CY_CLK_HVILO_FREQ_HZ (32000UL) - -/** PILO frequency in Hz */ -#define CY_CLK_PILO_FREQ_HZ (32768UL) - -/** WCO frequency in Hz */ -#define CY_CLK_WCO_FREQ_HZ (32768UL) - -/** ALTLF frequency in Hz */ -#define CY_CLK_ALTLF_FREQ_HZ (32768UL) - /** * Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock, @@ -91,10 +77,8 @@ uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT; /** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */ uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; -/** Holds the Alternate high frequency clock in Hz. Updated by \ref SystemCoreClockUpdate(). */ -#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) - uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ; -#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */ +/** Holds the Alternate high frequency clock in Hz. Updated by \ref Cy_BLE_EcoConfigure(). */ +uint32_t cy_BleEcoClockFreqHz = 0UL; /* SCB->CPACR */ #define SCB_CPACR_CP10_CP11_ENABLE (0xFUL << 20u) @@ -110,6 +94,10 @@ uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; #define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u) #define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu) +/* IPC_STRUCT7->DATA configuration */ +#define CY_STARTUP_CM0_DP_STATE (0x2uL) +#define CY_STARTUP_IPC7_DP_OFFSET (0x28u) + /******************************************************************************* * SystemCoreClockUpdate (void) @@ -118,37 +106,14 @@ uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; /* Do not use these definitions directly in your application */ #define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u) #define CY_DELAY_1K_THRESHOLD (1000u) -#define CY_DELAY_1K_MINUS_1_THRESHOLD (CY_DELAY_1K_THRESHOLD - 1u) #define CY_DELAY_1M_THRESHOLD (1000000u) -#define CY_DELAY_1M_MINUS_1_THRESHOLD (CY_DELAY_1M_THRESHOLD - 1u) -uint32_t cy_delayFreqHz = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; -uint32_t cy_delayFreqKhz = (CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / - CY_DELAY_1K_THRESHOLD; +uint32_t cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD); -uint8_t cy_delayFreqMhz = (uint8_t)((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1M_MINUS_1_THRESHOLD) / - CY_DELAY_1M_THRESHOLD); +uint8_t cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1M_THRESHOLD); uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * - ((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD); - -#define CY_ROOT_PATH_SRC_IMO (0UL) -#define CY_ROOT_PATH_SRC_EXT (1UL) -#if (SRSS_ECO_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_ECO (2UL) -#endif /* (SRSS_ECO_PRESENT == 1U) */ -#if (SRSS_ALTHF_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_ALTHF (3UL) -#endif /* (SRSS_ALTHF_PRESENT == 1U) */ -#define CY_ROOT_PATH_SRC_DSI_MUX (4UL) -#define CY_ROOT_PATH_SRC_DSI_MUX_HVILO (16UL) -#define CY_ROOT_PATH_SRC_DSI_MUX_WCO (17UL) -#if (SRSS_ALTLF_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_DSI_MUX_ALTLF (18UL) -#endif /* (SRSS_ALTLF_PRESENT == 1U) */ -#if (SRSS_PILO_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_DSI_MUX_PILO (19UL) -#endif /* (SRSS_PILO_PRESENT == 1U) */ + CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD); /******************************************************************************* @@ -192,6 +157,17 @@ void SystemInit(void) Cy_SystemInit(); SystemCoreClockUpdate(); +#ifdef __CM0P_PRESENT + #if (__CM0P_PRESENT == 0) + /* Configure data register (as CM0p in deep sleep state) of IPC structure #7, reserved for the Deep-Sleep operations. */ + REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = (CY_STARTUP_CM0_DP_STATE << + CY_STARTUP_IPC7_DP_OFFSET); + + /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */ + REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL; + #endif /* (__CM0P_PRESENT == 0) */ +#endif /* __CM0P_PRESENT */ + #if !defined(CY_IPC_DEFAULT_CFG_DISABLE) #ifdef __CM0P_PRESENT @@ -250,10 +226,7 @@ void SystemInit(void) /* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm4 }; - if (cy_device->flashPipeRequired != 0u) - { - Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4); - } + Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4); #if defined(CY_DEVICE_PSOC6ABLE2) Cy_Flash_Init(); @@ -298,154 +271,19 @@ __WEAK void Cy_SystemInit(void) *******************************************************************************/ void SystemCoreClockUpdate (void) { - uint32_t srcFreqHz; - uint32_t pathFreqHz; - uint32_t fastClkDiv; - uint32_t periClkDiv; - uint32_t rootPath; - uint32_t srcClk; - - /* Get root path clock for the high-frequency clock # 0 */ - rootPath = _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_MUX, SRSS->CLK_ROOT_SELECT[0u]); - - /* Get source of the root path clock */ - srcClk = _FLD2VAL(SRSS_CLK_PATH_SELECT_PATH_MUX, SRSS->CLK_PATH_SELECT[rootPath]); + uint32 locHf0Clock = Cy_SysClk_ClkHfGetFrequency(0UL); - /* Get frequency of the source */ - switch (srcClk) + if (0UL != locHf0Clock) { - case CY_ROOT_PATH_SRC_IMO: - srcFreqHz = CY_CLK_IMO_FREQ_HZ; - break; - - case CY_ROOT_PATH_SRC_EXT: - srcFreqHz = CY_CLK_EXT_FREQ_HZ; - break; - - #if (SRSS_ECO_PRESENT == 1U) - case CY_ROOT_PATH_SRC_ECO: - srcFreqHz = CY_CLK_ECO_FREQ_HZ; - break; - #endif /* (SRSS_ECO_PRESENT == 1U) */ - -#if defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) - case CY_ROOT_PATH_SRC_ALTHF: - srcFreqHz = cy_BleEcoClockFreqHz; - break; -#endif /* defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) */ - - case CY_ROOT_PATH_SRC_DSI_MUX: - { - uint32_t dsi_src; - dsi_src = _FLD2VAL(SRSS_CLK_DSI_SELECT_DSI_MUX, SRSS->CLK_DSI_SELECT[rootPath]); - switch (dsi_src) - { - case CY_ROOT_PATH_SRC_DSI_MUX_HVILO: - srcFreqHz = CY_CLK_HVILO_FREQ_HZ; - break; - - case CY_ROOT_PATH_SRC_DSI_MUX_WCO: - srcFreqHz = CY_CLK_WCO_FREQ_HZ; - break; - - #if (SRSS_ALTLF_PRESENT == 1U) - case CY_ROOT_PATH_SRC_DSI_MUX_ALTLF: - srcFreqHz = CY_CLK_ALTLF_FREQ_HZ; - break; - #endif /* (SRSS_ALTLF_PRESENT == 1U) */ - - #if (SRSS_PILO_PRESENT == 1U) - case CY_ROOT_PATH_SRC_DSI_MUX_PILO: - srcFreqHz = CY_CLK_PILO_FREQ_HZ; - break; - #endif /* (SRSS_PILO_PRESENT == 1U) */ - - default: - srcFreqHz = CY_CLK_HVILO_FREQ_HZ; - break; - } + cy_Hfclk0FreqHz = locHf0Clock; + cy_PeriClkFreqHz = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkPeriGetDivider()); + SystemCoreClock = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkFastGetDivider()); + + /* Sets clock frequency for Delay API */ + cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1M_THRESHOLD); + cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1K_THRESHOLD); + cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz; } - break; - - default: - srcFreqHz = CY_CLK_EXT_FREQ_HZ; - break; - } - - if (rootPath == 0UL) - { - /* FLL */ - bool fllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_FLL_STATUS_LOCKED, SRSS->CLK_FLL_STATUS)); - bool fllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)); - bool fllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)) || - (1UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3))); - if ((fllOutputAuto && fllLocked) || fllOutputOutput) - { - uint32_t fllMult; - uint32_t refDiv; - uint32_t outputDiv; - - fllMult = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_MULT, SRSS->CLK_FLL_CONFIG); - refDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, SRSS->CLK_FLL_CONFIG2); - outputDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, SRSS->CLK_FLL_CONFIG) + 1UL; - - pathFreqHz = ((srcFreqHz / refDiv) * fllMult) / outputDiv; - } - else - { - pathFreqHz = srcFreqHz; - } - } - else if ((rootPath == 1UL) || (rootPath == 2UL)) - { - /* PLL */ - bool pllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_PLL_STATUS_LOCKED, SRSS->CLK_PLL_STATUS[rootPath - 1UL])); - bool pllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])); - bool pllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])) || - (1UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]))); - if ((pllOutputAuto && pllLocked) || pllOutputOutput) - { - uint32_t feedbackDiv; - uint32_t referenceDiv; - uint32_t outputDiv; - - feedbackDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); - referenceDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_REFERENCE_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); - outputDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_OUTPUT_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); - - pathFreqHz = ((srcFreqHz * feedbackDiv) / referenceDiv) / outputDiv; - - } - else - { - pathFreqHz = srcFreqHz; - } - } - else - { - /* Direct */ - pathFreqHz = srcFreqHz; - } - - /* Get frequency after hf_clk pre-divider */ - pathFreqHz = pathFreqHz >> _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_DIV, SRSS->CLK_ROOT_SELECT[0u]); - cy_Hfclk0FreqHz = pathFreqHz; - - /* Fast Clock Divider */ - fastClkDiv = 1u + _FLD2VAL(CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV, CPUSS->CM4_CLOCK_CTL); - - /* Peripheral Clock Divider */ - periClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV, CPUSS->CM0_CLOCK_CTL); - cy_PeriClkFreqHz = pathFreqHz / periClkDiv; - - pathFreqHz = pathFreqHz / fastClkDiv; - SystemCoreClock = pathFreqHz; - - /* Sets clock frequency for Delay API */ - cy_delayFreqHz = SystemCoreClock; - cy_delayFreqMhz = (uint8_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD); - cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD; - cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz; } diff --git a/devices/bsp/COMPONENT_MBED/startup/system_psoc6.h b/devices/templates/COMPONENT_MBED/system_psoc6.h similarity index 91% rename from devices/bsp/COMPONENT_MBED/startup/system_psoc6.h rename to devices/templates/COMPONENT_MBED/system_psoc6.h index 423361f..8dd97ff 100644 --- a/devices/bsp/COMPONENT_MBED/startup/system_psoc6.h +++ b/devices/templates/COMPONENT_MBED/system_psoc6.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file system_psoc6.h -* \version 2.60 +* \version 2.70 * * \brief Device system header file. * @@ -320,6 +320,28 @@ * Reason for Change * * +* 2.70 +* Updated \ref SystemCoreClockUpdate() implementation - The SysClk API is reused. +* Code optimization. +* +* +* Updated \ref SystemInit() implementation - The IPC7 structure is initialized for both cores. +* Provided support for SysPM driver updates. +* +* +* Updated the linker scripts. +* Reserved FLASH area for the MCU boot headers. +* +* +* Added System Pipe initialization for all devices. +* Improved PDL usability according to user experience. +* +* +* Removed redundant legacy macros: CY_CLK_EXT_FREQ_HZ, CY_CLK_ECO_FREQ_HZ and CY_CLK_ALTHF_FREQ_HZ. +* Use \ref Cy_SysClk_ExtClkSetFrequency, \ref Cy_SysClk_EcoConfigure and \ref Cy_BLE_EcoConfigure functions instead them. +* Defect fixing. +* +* * 2.60 * Updated linker scripts. * Provided support for new devices, updated usage of CM0p prebuilt image. @@ -439,12 +461,6 @@ extern "C" { #define CY_SYSTEM_CPU_CM0P 0UL #endif -#if defined (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) - #include "cyfitter.h" -#endif /* (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) */ - - - /******************************************************************************* * @@ -460,44 +476,6 @@ extern "C" { * \{ */ -#if defined (CYDEV_CLK_EXTCLK__HZ) - #define CY_CLK_EXT_FREQ_HZ (CYDEV_CLK_EXTCLK__HZ) -#else - /***************************************************************************//** - * External Clock Frequency (in Hz, [value]UL). If compiled within - * PSoC Creator and the clock is enabled in the DWR, the value from DWR used. - * Otherwise, edit the value below. - * (USER SETTING) - *******************************************************************************/ - #define CY_CLK_EXT_FREQ_HZ (24000000UL) /* <<< 24 MHz */ -#endif /* (CYDEV_CLK_EXTCLK__HZ) */ - - -#if defined (CYDEV_CLK_ECO__HZ) - #define CY_CLK_ECO_FREQ_HZ (CYDEV_CLK_ECO__HZ) -#else - /***************************************************************************//** - * \brief External crystal oscillator frequency (in Hz, [value]UL). If compiled - * within PSoC Creator and the clock is enabled in the DWR, the value from DWR - * used. - * (USER SETTING) - *******************************************************************************/ - #define CY_CLK_ECO_FREQ_HZ (24000000UL) /* <<< 24 MHz */ -#endif /* (CYDEV_CLK_ECO__HZ) */ - - -#if defined (CYDEV_CLK_ALTHF__HZ) - #define CY_CLK_ALTHF_FREQ_HZ (CYDEV_CLK_ALTHF__HZ) -#else - /***************************************************************************//** - * \brief Alternate high frequency (in Hz, [value]UL). If compiled within - * PSoC Creator and the clock is enabled in the DWR, the value from DWR used. - * Otherwise, edit the value below. - * (USER SETTING) - *******************************************************************************/ - #define CY_CLK_ALTHF_FREQ_HZ (32000000UL) /* <<< 32 MHz */ -#endif /* (CYDEV_CLK_ALTHF__HZ) */ - /***************************************************************************//** * \brief Start address of the Cortex-M4 application ([address]UL) @@ -581,7 +559,6 @@ void Cy_SysIpcPipeIsrCm4(void); extern void Cy_SystemInit(void); extern void Cy_SystemInitFpuEnable(void); -extern uint32_t cy_delayFreqHz; extern uint32_t cy_delayFreqKhz; extern uint8_t cy_delayFreqMhz; extern uint32_t cy_delay32kMs; @@ -634,11 +611,11 @@ extern uint32_t cy_delay32kMs; #define CY_SYS_CYPIPE_INTR_MASK ( CY_SYS_CYPIPE_CHAN_MASK_EP0 | CY_SYS_CYPIPE_CHAN_MASK_EP1 ) #define CY_SYS_CYPIPE_CONFIG_EP0 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ - | (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \ - | CY_IPC_CHAN_CYPIPE_EP0) + | (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \ + | CY_IPC_CHAN_CYPIPE_EP0) #define CY_SYS_CYPIPE_CONFIG_EP1 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ - | (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \ - | CY_IPC_CHAN_CYPIPE_EP1) + | (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \ + | CY_IPC_CHAN_CYPIPE_EP1) /******************************************************************************/ @@ -658,7 +635,7 @@ extern uint32_t cy_PeriClkFreqHz; /** \cond INTERNAL */ /******************************************************************************* -* Backward compatibility macro. The following code is DEPRECATED and must +* Backward compatibility macros. The following code is DEPRECATED and must * not be used in new projects *******************************************************************************/ @@ -667,6 +644,7 @@ extern uint32_t cy_PeriClkFreqHz; #define Cy_RestoreIRQ Cy_SysLib_ExitCriticalSection #define CY_SYS_INTR_CYPIPE_EP0 (CY_IPC_INTR_CYPIPE_EP0) #define CY_SYS_INTR_CYPIPE_EP1 (CY_IPC_INTR_CYPIPE_EP1) +#define cy_delayFreqHz (SystemCoreClock) /** \endcond */ diff --git a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct similarity index 98% rename from devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct rename to devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct index 48948b4..f936c20 100644 --- a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xx5_cm0plus.sct -;* \version 2.60 +;* \version 2.70 ;* ;* Linker file for the ARMCC. ;* @@ -58,10 +58,10 @@ #define FLASH_START 0x10000000 #define FLASH_SIZE 0x00002000 -; Size of the stack section at the end of CM0+ SRAM +; The size of the stack section at the end of CM0+ SRAM #define STACK_SIZE 0x00001000 -; The following defines describe a 32K flash region used for EEPROM emulation. +; The following defines describe a 32K flash region used for EEPROM emulation. ; This region can also be used as the general purpose flash. ; You can assign sections to this memory region for only one of the cores. ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. @@ -147,6 +147,7 @@ LR_IROM1 FLASH_START FLASH_SIZE } } + ; Emulated EEPROM Flash area LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE { diff --git a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_ARM/cy8c6xx6_cm0plus.sct b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx6_cm0plus.sct similarity index 98% rename from devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_ARM/cy8c6xx6_cm0plus.sct rename to devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx6_cm0plus.sct index f04066c..9bd350d 100644 --- a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_ARM/cy8c6xx6_cm0plus.sct +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx6_cm0plus.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xx6_cm0plus.sct -;* \version 2.60 +;* \version 2.70 ;* ;* Linker file for the ARMCC. ;* @@ -58,10 +58,10 @@ #define FLASH_START 0x10000000 #define FLASH_SIZE 0x00002000 -; Size of the stack section at the end of CM0+ SRAM +; The size of the stack section at the end of CM0+ SRAM #define STACK_SIZE 0x00001000 -; The following defines describe a 32K flash region used for EEPROM emulation. +; The following defines describe a 32K flash region used for EEPROM emulation. ; This region can also be used as the general purpose flash. ; You can assign sections to this memory region for only one of the cores. ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. @@ -147,6 +147,7 @@ LR_IROM1 FLASH_START FLASH_SIZE } } + ; Emulated EEPROM Flash area LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE { diff --git a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct similarity index 98% rename from devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct rename to devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct index a829307..9e4e930 100644 --- a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xx7_cm0plus.sct -;* \version 2.60 +;* \version 2.70 ;* ;* Linker file for the ARMCC. ;* @@ -58,10 +58,10 @@ #define FLASH_START 0x10000000 #define FLASH_SIZE 0x00002000 -; Size of the stack section at the end of CM0+ SRAM +; The size of the stack section at the end of CM0+ SRAM #define STACK_SIZE 0x00001000 -; The following defines describe a 32K flash region used for EEPROM emulation. +; The following defines describe a 32K flash region used for EEPROM emulation. ; This region can also be used as the general purpose flash. ; You can assign sections to this memory region for only one of the cores. ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. @@ -147,6 +147,7 @@ LR_IROM1 FLASH_START FLASH_SIZE } } + ; Emulated EEPROM Flash area LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE { diff --git a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_ARM/cy8c6xx8_cm0plus.sct b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx8_cm0plus.sct similarity index 98% rename from devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_ARM/cy8c6xx8_cm0plus.sct rename to devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx8_cm0plus.sct index da6710a..11dd0da 100644 --- a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_ARM/cy8c6xx8_cm0plus.sct +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx8_cm0plus.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xx8_cm0plus.sct -;* \version 2.60 +;* \version 2.70 ;* ;* Linker file for the ARMCC. ;* @@ -58,10 +58,10 @@ #define FLASH_START 0x10000000 #define FLASH_SIZE 0x00002000 -; Size of the stack section at the end of CM0+ SRAM +; The size of the stack section at the end of CM0+ SRAM #define STACK_SIZE 0x00001000 -; The following defines describe a 32K flash region used for EEPROM emulation. +; The following defines describe a 32K flash region used for EEPROM emulation. ; This region can also be used as the general purpose flash. ; You can assign sections to this memory region for only one of the cores. ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. @@ -147,6 +147,7 @@ LR_IROM1 FLASH_START FLASH_SIZE } } + ; Emulated EEPROM Flash area LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE { diff --git a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct similarity index 98% rename from devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct rename to devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct index 0046808..68cfabe 100644 --- a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xxa_cm0plus.sct -;* \version 2.60 +;* \version 2.70 ;* ;* Linker file for the ARMCC. ;* @@ -58,10 +58,10 @@ #define FLASH_START 0x10000000 #define FLASH_SIZE 0x00002000 -; Size of the stack section at the end of CM0+ SRAM +; The size of the stack section at the end of CM0+ SRAM #define STACK_SIZE 0x00001000 -; The following defines describe a 32K flash region used for EEPROM emulation. +; The following defines describe a 32K flash region used for EEPROM emulation. ; This region can also be used as the general purpose flash. ; You can assign sections to this memory region for only one of the cores. ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. @@ -147,6 +147,7 @@ LR_IROM1 FLASH_START FLASH_SIZE } } + ; Emulated EEPROM Flash area LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE { diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx5_cm0plus.sct b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx5_cm0plus.sct new file mode 100644 index 0000000..784c7b6 --- /dev/null +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx5_cm0plus.sct @@ -0,0 +1,241 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cyb06xx5_cm0plus.sct +;* \version 2.70 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM0+ core. +; You can change the memory allocation by editing the RAM and Flash defines. +; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', +; where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.scat'. +; RAM +#define RAM_START 0x08000000 +#define RAM_SIZE 0x00010000 +; Flash +#define FLASH_START 0x10000000 +#define FLASH_SIZE 0x00010000 + +; The size of the stack section at the end of CM0+ SRAM +#define STACK_SIZE 0x00001000 + +; The size of the MCU boot header area at the start of FLASH +#define BOOT_HEADER_SIZE 0x00000400 + + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M0+ application flash area +LR_IROM1 FLASH_START FLASH_SIZE +{ + .cy_app_header +0 + { + * (.cy_app_header) + } + + ER_FLASH_VECTORS FLASH_START + BOOT_HEADER_SIZE + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } +} + + + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + .cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00070000 +#define __cy_memory_0_row_size 0x200 + + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx7_cm0plus.sct b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx7_cm0plus.sct new file mode 100644 index 0000000..1b4b3ce --- /dev/null +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx7_cm0plus.sct @@ -0,0 +1,260 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cyb06xx7_cm0plus.sct +;* \version 2.70 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM0+ core. +; You can change the memory allocation by editing the RAM and Flash defines. +; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', +; where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.scat'. +; RAM +#define RAM_START 0x08000000 +#define RAM_SIZE 0x00010000 +; Flash +#define FLASH_START 0x10000000 +#define FLASH_SIZE 0x00020000 + +; The size of the stack section at the end of CM0+ SRAM +#define STACK_SIZE 0x00001000 + +; The size of the MCU boot header area at the start of FLASH +#define BOOT_HEADER_SIZE 0x00000400 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M0+ application flash area +LR_IROM1 FLASH_START FLASH_SIZE +{ + .cy_app_header +0 + { + * (.cy_app_header) + } + + ER_FLASH_VECTORS FLASH_START + BOOT_HEADER_SIZE + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + .cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x000D0000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct new file mode 100644 index 0000000..b06d119 --- /dev/null +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct @@ -0,0 +1,260 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cyb06xxa_cm0plus.sct +;* \version 2.70 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM0+ core. +; You can change the memory allocation by editing the RAM and Flash defines. +; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', +; where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.scat'. +; RAM +#define RAM_START 0x08000000 +#define RAM_SIZE 0x00040000 +; Flash +#define FLASH_START 0x10000000 +#define FLASH_SIZE 0x00040000 + +; The size of the stack section at the end of CM0+ SRAM +#define STACK_SIZE 0x00001000 + +; The size of the MCU boot header area at the start of FLASH +#define BOOT_HEADER_SIZE 0x00000400 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M0+ application flash area +LR_IROM1 FLASH_START FLASH_SIZE +{ + .cy_app_header +0 + { + * (.cy_app_header) + } + + ER_FLASH_VECTORS FLASH_START + BOOT_HEADER_SIZE + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + .cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x001D0000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/devices/bsp/COMPONENT_MTB/startup/TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.s b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.s similarity index 100% rename from devices/bsp/COMPONENT_MTB/startup/TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.s rename to devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.s diff --git a/devices/bsp/COMPONENT_MTB/startup/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.s b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.s similarity index 100% rename from devices/bsp/COMPONENT_MTB/startup/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.s rename to devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.s diff --git a/devices/bsp/COMPONENT_MTB/startup/TOOLCHAIN_ARM/startup_psoc6_03_cm0plus.s b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_03_cm0plus.s similarity index 100% rename from devices/bsp/COMPONENT_MTB/startup/TOOLCHAIN_ARM/startup_psoc6_03_cm0plus.s rename to devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_03_cm0plus.s diff --git a/devices/bsp/COMPONENT_MTB/startup/TOOLCHAIN_A_Clang/startup_psoc6_01_cm0plus.S b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_A_Clang/startup_psoc6_01_cm0plus.S similarity index 85% rename from devices/bsp/COMPONENT_MTB/startup/TOOLCHAIN_A_Clang/startup_psoc6_01_cm0plus.S rename to devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_A_Clang/startup_psoc6_01_cm0plus.S index fa4a2cb..aef119c 100644 --- a/devices/bsp/COMPONENT_MTB/startup/TOOLCHAIN_A_Clang/startup_psoc6_01_cm0plus.S +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_A_Clang/startup_psoc6_01_cm0plus.S @@ -43,7 +43,7 @@ __StackLimit: .space Stack_Size - .equ __StackTop, . - Stack_Size + .equ __StackTop, . - Stack_Size .section __HEAP, __heap .align 3 @@ -53,7 +53,6 @@ __StackLimit: .equ Heap_Size, 0x00000400 #endif .globl __HeapBase - .globl __HeapLimit __HeapBase: .if Heap_Size .space Heap_Size @@ -64,7 +63,7 @@ __HeapBase: .globl ___Vectors ___Vectors: .long __StackTop /* Top of Stack */ - .long Reset_Handler+1 /* Reset Handler. Added +1, clang doesn't make lsb to 1 for thumb */ + .long Reset_Handler /* Reset Handler */ .long CY_NMI_HANLDER_ADDR /* NMI Handler */ .long HardFault_Handler /* Hard Fault Handler */ .long 0 /* Reserved */ @@ -123,10 +122,10 @@ ___Vectors: ___ramVectors: .space __VectorsSize - /* Only .text, otherwise the linker is smart enough to treat .thumb_func as 2 byte aligned and the - * Reset handler vector + 1 in the vector table ends up at +2 and boot fails. Clang/LLVM issue. - */ + .text + .thumb_func + .align 2 /* Reset handler */ .globl Reset_Handler @@ -143,54 +142,22 @@ Reset_Handler: * * All addresses must be aligned to 4 bytes boundary. */ - .equ __copy_table_start__, ___Vectors - .equ __data_start__, ___ramVectors - .equ __data_end__, __data_start__ + __VectorsSize - ldr r1, =__copy_table_start__ - ldr r2, =__data_start__ - ldr r3, =__data_end__ -.L_loop_copy_table: - subs r4, r3, r2 - ble .L_loop_copy_table_done - ldr r0, [r1,r4] - str r0, [r2,r4] - subs r3, #4 - bgt .L_loop_copy_table -.L_loop_copy_table_done: - ldr r1, =segment$end$__TEXT + 3 - ldr r2, =section$start$__DATA$__data - ldr r3, =section$end$__DATA$__data - movs r4, #3 - mvns r4,r4 - ands r1, r1, r4 -.L_loop_copy_data: - subs r4, r3, r2 - ble .L_loop_copy_data_done - ldr r0, [r1,r4] - str r0, [r2,r4] - subs r3, #4 - bgt .L_loop_copy_data -.L_loop_copy_data_done: - ldr r2, =section$start$__DATA$__bss - ldr r3, =section$end$__DATA$__bss -.L_loop_bss: - subs r1, r3, r2 - ble .L_loop_bss_done - movs r0, #0 - str r0, [r2,r1] - subs r3, #4 - bgt .L_loop_bss -.L_loop_bss_done: + ldr r0, =___ramVectors + ldr r1, =___Vectors + ldr r2, =__VectorsSize + bl _memcpy + + ldr r0, =segment$start$__DATA + ldr r1, =segment$end$__TEXT ldr r2, =section$start$__DATA$__zerofill - ldr r3, =section$end$__DATA$__zerofill -.L_loop_zerofill: - subs r1, r3, r2 - ble .L_loop_zerofill_done - movs r0, #0 - str r0, [r2,r1] - subs r3, #4 - bgt .L_loop_zerofill -.L_loop_zerofill_done: + sub r2, r0 + bl _memcpy + + ldr r0, =section$start$__DATA$__zerofill + eor r1, r1 + ldr r2, =section$end$__DATA$__zerofill + sub r2, r0 + bl _memset /* Update Vector Table Offset Register. */ ldr r0, =___ramVectors @@ -200,10 +167,10 @@ Reset_Handler: bl _HeapInit #ifndef __NO_SYSTEM_INIT - bl _SystemInit + bl _SystemInit #endif - bl _main + bl _main /* Should never get here */ b . @@ -221,12 +188,17 @@ Reset_Handler: Cy_OnResetUser: bx lr + .text .align 1 .thumb_func - .weak_definition Default_Handler + .weak_reference Default_Handler Default_Handler: b . + + .text + .thumb_func + .align 2 .weak_definition Cy_SysLib_FaultHandler Cy_SysLib_FaultHandler: @@ -234,7 +206,8 @@ Cy_SysLib_FaultHandler: .text .thumb_func - .align 2 + .align 2 + Fault_Handler: /* Storing LR content for Creator call stack trace */ push {LR} diff --git a/devices/bsp/COMPONENT_MTB/startup/TOOLCHAIN_A_Clang/startup_psoc6_02_cm0plus.S b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_A_Clang/startup_psoc6_02_cm0plus.S similarity index 81% rename from devices/bsp/COMPONENT_MTB/startup/TOOLCHAIN_A_Clang/startup_psoc6_02_cm0plus.S rename to devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_A_Clang/startup_psoc6_02_cm0plus.S index ed0d524..89e4f15 100644 --- a/devices/bsp/COMPONENT_MTB/startup/TOOLCHAIN_A_Clang/startup_psoc6_02_cm0plus.S +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_A_Clang/startup_psoc6_02_cm0plus.S @@ -43,7 +43,7 @@ __StackLimit: .space Stack_Size - .equ __StackTop, . - Stack_Size + .equ __StackTop, . - Stack_Size .section __HEAP, __heap .align 3 @@ -53,7 +53,6 @@ __StackLimit: .equ Heap_Size, 0x00000400 #endif .globl __HeapBase - .globl __HeapLimit __HeapBase: .if Heap_Size .space Heap_Size @@ -64,7 +63,7 @@ __HeapBase: .globl ___Vectors ___Vectors: .long __StackTop /* Top of Stack */ - .long Reset_Handler+1 /* Reset Handler. Added +1, clang doesn't make lsb to 1 for thumb */ + .long Reset_Handler /* Reset Handler */ .long CY_NMI_HANLDER_ADDR /* NMI Handler */ .long HardFault_Handler /* Hard Fault Handler */ .long 0 /* Reserved */ @@ -107,10 +106,10 @@ ___Vectors: ___ramVectors: .space __VectorsSize - /* Only .text, otherwise the linker is smart enough to treat .thumb_func as 2 byte aligned and the - * Reset handler vector + 1 in the vector table ends up at +2 and boot fails. Clang/LLVM issue. - */ + .text + .thumb_func + .align 2 /* Reset handler */ .globl Reset_Handler @@ -127,54 +126,22 @@ Reset_Handler: * * All addresses must be aligned to 4 bytes boundary. */ - .equ __copy_table_start__, ___Vectors - .equ __data_start__, ___ramVectors - .equ __data_end__, __data_start__ + __VectorsSize - ldr r1, =__copy_table_start__ - ldr r2, =__data_start__ - ldr r3, =__data_end__ -.L_loop_copy_table: - subs r4, r3, r2 - ble .L_loop_copy_table_done - ldr r0, [r1,r4] - str r0, [r2,r4] - subs r3, #4 - bgt .L_loop_copy_table -.L_loop_copy_table_done: - ldr r1, =segment$end$__TEXT + 3 - ldr r2, =section$start$__DATA$__data - ldr r3, =section$end$__DATA$__data - movs r4, #3 - mvns r4,r4 - ands r1, r1, r4 -.L_loop_copy_data: - subs r4, r3, r2 - ble .L_loop_copy_data_done - ldr r0, [r1,r4] - str r0, [r2,r4] - subs r3, #4 - bgt .L_loop_copy_data -.L_loop_copy_data_done: - ldr r2, =section$start$__DATA$__bss - ldr r3, =section$end$__DATA$__bss -.L_loop_bss: - subs r1, r3, r2 - ble .L_loop_bss_done - movs r0, #0 - str r0, [r2,r1] - subs r3, #4 - bgt .L_loop_bss -.L_loop_bss_done: + ldr r0, =___ramVectors + ldr r1, =___Vectors + ldr r2, =__VectorsSize + bl _memcpy + + ldr r0, =segment$start$__DATA + ldr r1, =segment$end$__TEXT ldr r2, =section$start$__DATA$__zerofill - ldr r3, =section$end$__DATA$__zerofill -.L_loop_zerofill: - subs r1, r3, r2 - ble .L_loop_zerofill_done - movs r0, #0 - str r0, [r2,r1] - subs r3, #4 - bgt .L_loop_zerofill -.L_loop_zerofill_done: + sub r2, r0 + bl _memcpy + + ldr r0, =section$start$__DATA$__zerofill + eor r1, r1 + ldr r2, =section$end$__DATA$__zerofill + sub r2, r0 + bl _memset /* Update Vector Table Offset Register. */ ldr r0, =___ramVectors @@ -184,10 +151,10 @@ Reset_Handler: bl _HeapInit #ifndef __NO_SYSTEM_INIT - bl _SystemInit + bl _SystemInit #endif - bl _main + bl _main /* Should never get here */ b . @@ -205,12 +172,17 @@ Reset_Handler: Cy_OnResetUser: bx lr + .text .align 1 .thumb_func - .weak_definition Default_Handler + .weak_reference Default_Handler Default_Handler: b . + + .text + .thumb_func + .align 2 .weak_definition Cy_SysLib_FaultHandler Cy_SysLib_FaultHandler: @@ -218,7 +190,8 @@ Cy_SysLib_FaultHandler: .text .thumb_func - .align 2 + .align 2 + Fault_Handler: /* Storing LR content for Creator call stack trace */ push {LR} diff --git a/devices/bsp/COMPONENT_MTB/startup/TOOLCHAIN_A_Clang/startup_psoc6_03_cm0plus.S b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_A_Clang/startup_psoc6_03_cm0plus.S similarity index 81% rename from devices/bsp/COMPONENT_MTB/startup/TOOLCHAIN_A_Clang/startup_psoc6_03_cm0plus.S rename to devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_A_Clang/startup_psoc6_03_cm0plus.S index 9e32813..bb7bea9 100644 --- a/devices/bsp/COMPONENT_MTB/startup/TOOLCHAIN_A_Clang/startup_psoc6_03_cm0plus.S +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_A_Clang/startup_psoc6_03_cm0plus.S @@ -43,7 +43,7 @@ __StackLimit: .space Stack_Size - .equ __StackTop, . - Stack_Size + .equ __StackTop, . - Stack_Size .section __HEAP, __heap .align 3 @@ -53,7 +53,6 @@ __StackLimit: .equ Heap_Size, 0x00000400 #endif .globl __HeapBase - .globl __HeapLimit __HeapBase: .if Heap_Size .space Heap_Size @@ -64,7 +63,7 @@ __HeapBase: .globl ___Vectors ___Vectors: .long __StackTop /* Top of Stack */ - .long Reset_Handler+1 /* Reset Handler. Added +1, clang doesn't make lsb to 1 for thumb */ + .long Reset_Handler /* Reset Handler */ .long CY_NMI_HANLDER_ADDR /* NMI Handler */ .long HardFault_Handler /* Hard Fault Handler */ .long 0 /* Reserved */ @@ -107,10 +106,10 @@ ___Vectors: ___ramVectors: .space __VectorsSize - /* Only .text, otherwise the linker is smart enough to treat .thumb_func as 2 byte aligned and the - * Reset handler vector + 1 in the vector table ends up at +2 and boot fails. Clang/LLVM issue. - */ + .text + .thumb_func + .align 2 /* Reset handler */ .globl Reset_Handler @@ -127,54 +126,22 @@ Reset_Handler: * * All addresses must be aligned to 4 bytes boundary. */ - .equ __copy_table_start__, ___Vectors - .equ __data_start__, ___ramVectors - .equ __data_end__, __data_start__ + __VectorsSize - ldr r1, =__copy_table_start__ - ldr r2, =__data_start__ - ldr r3, =__data_end__ -.L_loop_copy_table: - subs r4, r3, r2 - ble .L_loop_copy_table_done - ldr r0, [r1,r4] - str r0, [r2,r4] - subs r3, #4 - bgt .L_loop_copy_table -.L_loop_copy_table_done: - ldr r1, =segment$end$__TEXT + 3 - ldr r2, =section$start$__DATA$__data - ldr r3, =section$end$__DATA$__data - movs r4, #3 - mvns r4,r4 - ands r1, r1, r4 -.L_loop_copy_data: - subs r4, r3, r2 - ble .L_loop_copy_data_done - ldr r0, [r1,r4] - str r0, [r2,r4] - subs r3, #4 - bgt .L_loop_copy_data -.L_loop_copy_data_done: - ldr r2, =section$start$__DATA$__bss - ldr r3, =section$end$__DATA$__bss -.L_loop_bss: - subs r1, r3, r2 - ble .L_loop_bss_done - movs r0, #0 - str r0, [r2,r1] - subs r3, #4 - bgt .L_loop_bss -.L_loop_bss_done: + ldr r0, =___ramVectors + ldr r1, =___Vectors + ldr r2, =__VectorsSize + bl _memcpy + + ldr r0, =segment$start$__DATA + ldr r1, =segment$end$__TEXT ldr r2, =section$start$__DATA$__zerofill - ldr r3, =section$end$__DATA$__zerofill -.L_loop_zerofill: - subs r1, r3, r2 - ble .L_loop_zerofill_done - movs r0, #0 - str r0, [r2,r1] - subs r3, #4 - bgt .L_loop_zerofill -.L_loop_zerofill_done: + sub r2, r0 + bl _memcpy + + ldr r0, =section$start$__DATA$__zerofill + eor r1, r1 + ldr r2, =section$end$__DATA$__zerofill + sub r2, r0 + bl _memset /* Update Vector Table Offset Register. */ ldr r0, =___ramVectors @@ -184,10 +151,10 @@ Reset_Handler: bl _HeapInit #ifndef __NO_SYSTEM_INIT - bl _SystemInit + bl _SystemInit #endif - bl _main + bl _main /* Should never get here */ b . @@ -205,12 +172,17 @@ Reset_Handler: Cy_OnResetUser: bx lr + .text .align 1 .thumb_func - .weak_definition Default_Handler + .weak_reference Default_Handler Default_Handler: b . + + .text + .thumb_func + .align 2 .weak_definition Cy_SysLib_FaultHandler Cy_SysLib_FaultHandler: @@ -218,7 +190,8 @@ Cy_SysLib_FaultHandler: .text .thumb_func - .align 2 + .align 2 + Fault_Handler: /* Storing LR content for Creator call stack trace */ push {LR} diff --git a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm0plus.ld b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm0plus.ld similarity index 99% rename from devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm0plus.ld rename to devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm0plus.ld index fe45e66..8822cbc 100644 --- a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm0plus.ld +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm0plus.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx5_cm0plus.ld -* \version 2.60 +* \version 2.70 * * Linker file for the GNU C compiler. * @@ -40,7 +40,7 @@ SEARCH_DIR(.) GROUP(-lgcc -lc -lnosys) ENTRY(Reset_Handler) -/* Size of the stack section at the end of CM0+ SRAM */ +/* The size of the stack section at the end of CM0+ SRAM */ STACK_SIZE = 0x1000; /* Force symbol to be entered in the output file as an undefined symbol. Doing diff --git a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_GCC_ARM/cy8c6xx6_cm0plus.ld b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx6_cm0plus.ld similarity index 99% rename from devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_GCC_ARM/cy8c6xx6_cm0plus.ld rename to devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx6_cm0plus.ld index 1b01bff..26518f0 100644 --- a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_GCC_ARM/cy8c6xx6_cm0plus.ld +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx6_cm0plus.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx6_cm0plus.ld -* \version 2.60 +* \version 2.70 * * Linker file for the GNU C compiler. * @@ -40,7 +40,7 @@ SEARCH_DIR(.) GROUP(-lgcc -lc -lnosys) ENTRY(Reset_Handler) -/* Size of the stack section at the end of CM0+ SRAM */ +/* The size of the stack section at the end of CM0+ SRAM */ STACK_SIZE = 0x1000; /* Force symbol to be entered in the output file as an undefined symbol. Doing diff --git a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld similarity index 99% rename from devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld rename to devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld index ebd4964..93b42aa 100644 --- a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx7_cm0plus.ld -* \version 2.60 +* \version 2.70 * * Linker file for the GNU C compiler. * @@ -40,7 +40,7 @@ SEARCH_DIR(.) GROUP(-lgcc -lc -lnosys) ENTRY(Reset_Handler) -/* Size of the stack section at the end of CM0+ SRAM */ +/* The size of the stack section at the end of CM0+ SRAM */ STACK_SIZE = 0x1000; /* Force symbol to be entered in the output file as an undefined symbol. Doing diff --git a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_GCC_ARM/cy8c6xx8_cm0plus.ld b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx8_cm0plus.ld similarity index 99% rename from devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_GCC_ARM/cy8c6xx8_cm0plus.ld rename to devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx8_cm0plus.ld index 643a15a..fcf5c75 100644 --- a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_GCC_ARM/cy8c6xx8_cm0plus.ld +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx8_cm0plus.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx8_cm0plus.ld -* \version 2.60 +* \version 2.70 * * Linker file for the GNU C compiler. * @@ -40,7 +40,7 @@ SEARCH_DIR(.) GROUP(-lgcc -lc -lnosys) ENTRY(Reset_Handler) -/* Size of the stack section at the end of CM0+ SRAM */ +/* The size of the stack section at the end of CM0+ SRAM */ STACK_SIZE = 0x1000; /* Force symbol to be entered in the output file as an undefined symbol. Doing diff --git a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld similarity index 99% rename from devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld rename to devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld index c880d2d..1f3a5a9 100644 --- a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xxa_cm0plus.ld -* \version 2.60 +* \version 2.70 * * Linker file for the GNU C compiler. * @@ -40,7 +40,7 @@ SEARCH_DIR(.) GROUP(-lgcc -lc -lnosys) ENTRY(Reset_Handler) -/* Size of the stack section at the end of CM0+ SRAM */ +/* The size of the stack section at the end of CM0+ SRAM */ STACK_SIZE = 0x1000; /* Force symbol to be entered in the output file as an undefined symbol. Doing diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xx5_cm0plus.ld b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xx5_cm0plus.ld new file mode 100644 index 0000000..da316b1 --- /dev/null +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xx5_cm0plus.ld @@ -0,0 +1,404 @@ +/***************************************************************************//** +* \file cyb06xx5_cm0plus.ld +* \version 2.70 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + +/* The size of the stack section at the end of CM0+ SRAM */ +STACK_SIZE = 0x1000; + +/* The size of the MCU boot header area at the start of FLASH */ +BOOT_HEADER_SIZE = 0x400; + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM0+ core. + * You can change the memory allocation by editing the 'ram' and 'flash' regions. + * Your changes must be aligned with the corresponding memory regions for the CM4 core in 'xx_cm4_dual.ld', + * where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.ld'. + */ + ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x10000 + flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x10000 + + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + .cy_app_header : + { + KEEP(*(.cy_app_header)) + } > flash + + /* Cortex-M0+ application flash area */ + .text ORIGIN(flash) + BOOT_HEADER_SIZE : + { + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_03_cm0plus.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_03_cm0plus.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > ram + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + .cy_xip : + { + KEEP(*(.cy_xip)) + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x00070000; +__cy_memory_0_row_size = 0x200; + + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xx7_cm0plus.ld b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xx7_cm0plus.ld new file mode 100644 index 0000000..18233c2 --- /dev/null +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xx7_cm0plus.ld @@ -0,0 +1,419 @@ +/***************************************************************************//** +* \file cyb06xx7_cm0plus.ld +* \version 2.70 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + +/* The size of the stack section at the end of CM0+ SRAM */ +STACK_SIZE = 0x1000; + +/* The size of the MCU boot header area at the start of FLASH */ +BOOT_HEADER_SIZE = 0x400; + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM0+ core. + * You can change the memory allocation by editing the 'ram' and 'flash' regions. + * Your changes must be aligned with the corresponding memory regions for the CM4 core in 'xx_cm4_dual.ld', + * where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.ld'. + */ + ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x10000 + flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x20000 + + /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ + em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */ + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + .cy_app_header : + { + KEEP(*(.cy_app_header)) + } > flash + + /* Cortex-M0+ application flash area */ + .text ORIGIN(flash) + BOOT_HEADER_SIZE : + { + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_01_cm0plus.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_01_cm0plus.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > ram + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + .cy_xip : + { + KEEP(*(.cy_xip)) + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x000D0000; +__cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +__cy_memory_1_start = 0x14000000; +__cy_memory_1_length = 0x8000; +__cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xxa_cm0plus.ld b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xxa_cm0plus.ld new file mode 100644 index 0000000..062f5fd --- /dev/null +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xxa_cm0plus.ld @@ -0,0 +1,419 @@ +/***************************************************************************//** +* \file cyb06xxa_cm0plus.ld +* \version 2.70 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + +/* The size of the stack section at the end of CM0+ SRAM */ +STACK_SIZE = 0x1000; + +/* The size of the MCU boot header area at the start of FLASH */ +BOOT_HEADER_SIZE = 0x400; + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM0+ core. + * You can change the memory allocation by editing the 'ram' and 'flash' regions. + * Your changes must be aligned with the corresponding memory regions for the CM4 core in 'xx_cm4_dual.ld', + * where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.ld'. + */ + ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x40000 + flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x40000 + + /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ + em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */ + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + .cy_app_header : + { + KEEP(*(.cy_app_header)) + } > flash + + /* Cortex-M0+ application flash area */ + .text ORIGIN(flash) + BOOT_HEADER_SIZE : + { + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_02_cm0plus.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_02_cm0plus.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > ram + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + .cy_xip : + { + KEEP(*(.cy_xip)) + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x001D0000; +__cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +__cy_memory_1_start = 0x14000000; +__cy_memory_1_length = 0x8000; +__cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/devices/bsp/COMPONENT_MTB/startup/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm0plus.S b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm0plus.S similarity index 100% rename from devices/bsp/COMPONENT_MTB/startup/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm0plus.S rename to devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm0plus.S diff --git a/devices/bsp/COMPONENT_MTB/startup/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm0plus.S b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm0plus.S similarity index 100% rename from devices/bsp/COMPONENT_MTB/startup/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm0plus.S rename to devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm0plus.S diff --git a/devices/bsp/COMPONENT_MTB/startup/TOOLCHAIN_GCC_ARM/startup_psoc6_03_cm0plus.S b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_03_cm0plus.S similarity index 100% rename from devices/bsp/COMPONENT_MTB/startup/TOOLCHAIN_GCC_ARM/startup_psoc6_03_cm0plus.S rename to devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_03_cm0plus.S diff --git a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_IAR/cy8c6xx5_cm0plus.icf b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx5_cm0plus.icf similarity index 99% rename from devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_IAR/cy8c6xx5_cm0plus.icf rename to devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx5_cm0plus.icf index 296a313..e57aae5 100644 --- a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_IAR/cy8c6xx5_cm0plus.icf +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx5_cm0plus.icf @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx5_cm0plus.icf -* \version 2.60 +* \version 2.70 * * Linker file for the IAR compiler. * @@ -150,7 +150,6 @@ define block RO {first section .intvec, readonly}; initialize by copy { readwrite }; do not initialize { section .noinit, section .intvec_ram }; - /*-Placement-*/ /* Flash - Cortex-M0+ application */ diff --git a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_IAR/cy8c6xx6_cm0plus.icf b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx6_cm0plus.icf similarity index 99% rename from devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_IAR/cy8c6xx6_cm0plus.icf rename to devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx6_cm0plus.icf index fe6a710..d7365c5 100644 --- a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_IAR/cy8c6xx6_cm0plus.icf +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx6_cm0plus.icf @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx6_cm0plus.icf -* \version 2.60 +* \version 2.70 * * Linker file for the IAR compiler. * @@ -150,7 +150,6 @@ define block RO {first section .intvec, readonly}; initialize by copy { readwrite }; do not initialize { section .noinit, section .intvec_ram }; - /*-Placement-*/ /* Flash - Cortex-M0+ application */ diff --git a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf similarity index 99% rename from devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf rename to devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf index 5d3343d..0179139 100644 --- a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx7_cm0plus.icf -* \version 2.60 +* \version 2.70 * * Linker file for the IAR compiler. * @@ -150,7 +150,6 @@ define block RO {first section .intvec, readonly}; initialize by copy { readwrite }; do not initialize { section .noinit, section .intvec_ram }; - /*-Placement-*/ /* Flash - Cortex-M0+ application */ diff --git a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_IAR/cy8c6xx8_cm0plus.icf b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx8_cm0plus.icf similarity index 99% rename from devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_IAR/cy8c6xx8_cm0plus.icf rename to devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx8_cm0plus.icf index 16b88f2..c331450 100644 --- a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_IAR/cy8c6xx8_cm0plus.icf +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx8_cm0plus.icf @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx8_cm0plus.icf -* \version 2.60 +* \version 2.70 * * Linker file for the IAR compiler. * @@ -150,7 +150,6 @@ define block RO {first section .intvec, readonly}; initialize by copy { readwrite }; do not initialize { section .noinit, section .intvec_ram }; - /*-Placement-*/ /* Flash - Cortex-M0+ application */ diff --git a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf similarity index 99% rename from devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf rename to devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf index d9399a7..9ccd5bd 100644 --- a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xxa_cm0plus.icf -* \version 2.60 +* \version 2.70 * * Linker file for the IAR compiler. * @@ -150,7 +150,6 @@ define block RO {first section .intvec, readonly}; initialize by copy { readwrite }; do not initialize { section .noinit, section .intvec_ram }; - /*-Placement-*/ /* Flash - Cortex-M0+ application */ diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xx5_cm0plus.icf b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xx5_cm0plus.icf new file mode 100644 index 0000000..23684ad --- /dev/null +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xx5_cm0plus.icf @@ -0,0 +1,225 @@ +/***************************************************************************//** +* \file cyb06xx5_cm0plus.icf +* \version 2.70 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM0+ core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Your changes must be aligned with the corresponding symbols for CM4 core in 'xx_cm4_dual.icf', + * where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x08010000; +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x10010000; + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x160007FF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/*-Sizes-*/ +if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol __ICFEDIT_size_cstack__ = 0x1000; +} else { + define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; +} +define symbol __ICFEDIT_size_proc_stack__ = 0x0; + +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} +/**** End of ICF editor section. ###ICF###*/ + +/* The size of the MCU boot header area at the start of FLASH */ +define symbol BOOT_HEADER_SIZE = 0x400; + + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; +define block RO {first section .intvec, readonly}; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M0+ application */ +".cy_app_header" : place at start of IROM1_region { section .cy_app_header }; +place at address (__ICFEDIT_region_IROM1_start__ + BOOT_HEADER_SIZE) { block RO }; + + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +".cy_xip" : place at start of EROM1_region { section .cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { readwrite }; +place at end of IRAM1_region { block HSTACK }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_app_header, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00070000; +define exported symbol __cy_memory_0_row_size = 0x200; + + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xx7_cm0plus.icf b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xx7_cm0plus.icf new file mode 100644 index 0000000..fa3adff --- /dev/null +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xx7_cm0plus.icf @@ -0,0 +1,232 @@ +/***************************************************************************//** +* \file cyb06xx7_cm0plus.icf +* \version 2.70 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM0+ core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Your changes must be aligned with the corresponding symbols for CM4 core in 'xx_cm4_dual.icf', + * where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x08010000; +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x10020000; + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x160007FF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/*-Sizes-*/ +if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol __ICFEDIT_size_cstack__ = 0x1000; +} else { + define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; +} +define symbol __ICFEDIT_size_proc_stack__ = 0x0; + +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} +/**** End of ICF editor section. ###ICF###*/ + +/* The size of the MCU boot header area at the start of FLASH */ +define symbol BOOT_HEADER_SIZE = 0x400; + + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; +define block RO {first section .intvec, readonly}; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M0+ application */ +".cy_app_header" : place at start of IROM1_region { section .cy_app_header }; +place at address (__ICFEDIT_region_IROM1_start__ + BOOT_HEADER_SIZE) { block RO }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +".cy_xip" : place at start of EROM1_region { section .cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { readwrite }; +place at end of IRAM1_region { block HSTACK }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_app_header, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x000D0000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xxa_cm0plus.icf b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xxa_cm0plus.icf new file mode 100644 index 0000000..4997407 --- /dev/null +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xxa_cm0plus.icf @@ -0,0 +1,232 @@ +/***************************************************************************//** +* \file cyb06xxa_cm0plus.icf +* \version 2.70 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM0+ core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Your changes must be aligned with the corresponding symbols for CM4 core in 'xx_cm4_dual.icf', + * where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x08040000; +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x10040000; + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x160007FF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/*-Sizes-*/ +if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol __ICFEDIT_size_cstack__ = 0x1000; +} else { + define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; +} +define symbol __ICFEDIT_size_proc_stack__ = 0x0; + +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} +/**** End of ICF editor section. ###ICF###*/ + +/* The size of the MCU boot header area at the start of FLASH */ +define symbol BOOT_HEADER_SIZE = 0x400; + + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; +define block RO {first section .intvec, readonly}; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M0+ application */ +".cy_app_header" : place at start of IROM1_region { section .cy_app_header }; +place at address (__ICFEDIT_region_IROM1_start__ + BOOT_HEADER_SIZE) { block RO }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +".cy_xip" : place at start of EROM1_region { section .cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { readwrite }; +place at end of IRAM1_region { block HSTACK }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_app_header, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x001D0000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/devices/bsp/COMPONENT_MTB/startup/TOOLCHAIN_IAR/startup_psoc6_01_cm0plus.s b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_01_cm0plus.s similarity index 98% rename from devices/bsp/COMPONENT_MTB/startup/TOOLCHAIN_IAR/startup_psoc6_01_cm0plus.s rename to devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_01_cm0plus.s index a2efd0e..dbba869 100644 --- a/devices/bsp/COMPONENT_MTB/startup/TOOLCHAIN_IAR/startup_psoc6_01_cm0plus.s +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_01_cm0plus.s @@ -49,6 +49,7 @@ EXTERN __iar_program_start EXTERN SystemInit EXTERN __iar_data_init3 + EXTERN __iar_dynamic_initialization PUBLIC __vector_table PUBLIC __vector_table_0x1c PUBLIC __Vectors @@ -199,6 +200,9 @@ intvec_copy LDR R0, =__iar_data_init3 BLX R0 + ; --manual_dynamic_initialization + BL __iar_dynamic_initialization + LDR R0, =SystemInit BLX R0 diff --git a/devices/bsp/COMPONENT_MTB/startup/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.s b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.s similarity index 98% rename from devices/bsp/COMPONENT_MTB/startup/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.s rename to devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.s index b12679e..3fa2e86 100644 --- a/devices/bsp/COMPONENT_MTB/startup/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.s +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.s @@ -49,6 +49,7 @@ EXTERN __iar_program_start EXTERN SystemInit EXTERN __iar_data_init3 + EXTERN __iar_dynamic_initialization PUBLIC __vector_table PUBLIC __vector_table_0x1c PUBLIC __Vectors @@ -183,6 +184,9 @@ intvec_copy LDR R0, =__iar_data_init3 BLX R0 + ; --manual_dynamic_initialization + BL __iar_dynamic_initialization + LDR R0, =SystemInit BLX R0 diff --git a/devices/bsp/COMPONENT_MTB/startup/TOOLCHAIN_IAR/startup_psoc6_03_cm0plus.s b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_03_cm0plus.s similarity index 98% rename from devices/bsp/COMPONENT_MTB/startup/TOOLCHAIN_IAR/startup_psoc6_03_cm0plus.s rename to devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_03_cm0plus.s index d72e599..56c38a9 100644 --- a/devices/bsp/COMPONENT_MTB/startup/TOOLCHAIN_IAR/startup_psoc6_03_cm0plus.s +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_03_cm0plus.s @@ -49,6 +49,7 @@ EXTERN __iar_program_start EXTERN SystemInit EXTERN __iar_data_init3 + EXTERN __iar_dynamic_initialization PUBLIC __vector_table PUBLIC __vector_table_0x1c PUBLIC __Vectors @@ -183,6 +184,9 @@ intvec_copy LDR R0, =__iar_data_init3 BLX R0 + ; --manual_dynamic_initialization + BL __iar_dynamic_initialization + LDR R0, =SystemInit BLX R0 diff --git a/devices/bsp/COMPONENT_MTB/startup/system_psoc6_cm0plus.c b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/system_psoc6_cm0plus.c similarity index 69% rename from devices/bsp/COMPONENT_MTB/startup/system_psoc6_cm0plus.c rename to devices/templates/COMPONENT_MTB/COMPONENT_CM0P/system_psoc6_cm0plus.c index 9164b15..18cc197 100644 --- a/devices/bsp/COMPONENT_MTB/startup/system_psoc6_cm0plus.c +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/system_psoc6_cm0plus.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file system_psoc6_cm0plus.c -* \version 2.60 +* \version 2.70 * * The device system-source file. * @@ -27,6 +27,7 @@ #include "cy_device.h" #include "cy_device_headers.h" #include "cy_syslib.h" +#include "cy_sysclk.h" #include "cy_wdt.h" #if !defined(CY_IPC_DEFAULT_CFG_DISABLE) @@ -37,7 +38,6 @@ #if defined(CY_DEVICE_PSOC6ABLE2) #include "cy_flash.h" #endif /* defined(CY_DEVICE_PSOC6ABLE2) */ - #endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */ @@ -54,21 +54,6 @@ /** Default SlowClk system core frequency in Hz */ #define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (4000000UL) -/** IMO frequency in Hz */ -#define CY_CLK_IMO_FREQ_HZ (8000000UL) - -/** HVILO frequency in Hz */ -#define CY_CLK_HVILO_FREQ_HZ (32000UL) - -/** PILO frequency in Hz */ -#define CY_CLK_PILO_FREQ_HZ (32768UL) - -/** WCO frequency in Hz */ -#define CY_CLK_WCO_FREQ_HZ (32768UL) - -/** ALTLF frequency in Hz */ -#define CY_CLK_ALTLF_FREQ_HZ (32768UL) - /** * Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock, @@ -92,10 +77,8 @@ uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT; /** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */ uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; -/** Holds the Alternate high frequency clock in Hz. Updated by \ref SystemCoreClockUpdate(). */ -#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) - uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ; -#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */ +/** Holds the Alternate high frequency clock in Hz. Updated by \ref Cy_BLE_EcoConfigure(). */ +uint32_t cy_BleEcoClockFreqHz = 0UL; /******************************************************************************* @@ -116,37 +99,14 @@ uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; /* Do not use these definitions directly in your application */ #define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u) #define CY_DELAY_1K_THRESHOLD (1000u) -#define CY_DELAY_1K_MINUS_1_THRESHOLD (CY_DELAY_1K_THRESHOLD - 1u) #define CY_DELAY_1M_THRESHOLD (1000000u) -#define CY_DELAY_1M_MINUS_1_THRESHOLD (CY_DELAY_1M_THRESHOLD - 1u) -uint32_t cy_delayFreqHz = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; -uint32_t cy_delayFreqKhz = (CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / - CY_DELAY_1K_THRESHOLD; +uint32_t cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD); -uint8_t cy_delayFreqMhz = (uint8_t)((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1M_MINUS_1_THRESHOLD) / - CY_DELAY_1M_THRESHOLD); +uint8_t cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1M_THRESHOLD); uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * - ((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD); - -#define CY_ROOT_PATH_SRC_IMO (0UL) -#define CY_ROOT_PATH_SRC_EXT (1UL) -#if (SRSS_ECO_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_ECO (2UL) -#endif /* (SRSS_ECO_PRESENT == 1U) */ -#if (SRSS_ALTHF_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_ALTHF (3UL) -#endif /* (SRSS_ALTHF_PRESENT == 1U) */ -#define CY_ROOT_PATH_SRC_DSI_MUX (4UL) -#define CY_ROOT_PATH_SRC_DSI_MUX_HVILO (16UL) -#define CY_ROOT_PATH_SRC_DSI_MUX_WCO (17UL) -#if (SRSS_ALTLF_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_DSI_MUX_ALTLF (18UL) -#endif /* (SRSS_ALTLF_PRESENT == 1U) */ -#if (SRSS_PILO_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_DSI_MUX_PILO (19UL) -#endif /* (SRSS_PILO_PRESENT == 1U) */ + CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD); /******************************************************************************* @@ -194,15 +154,11 @@ void SystemInit(void) Cy_SystemInit(); SystemCoreClockUpdate(); -#if defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE) - if (CY_SYSLIB_DEVICE_REV_0A == Cy_SysLib_GetDeviceRevision()) - { - /* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */ - IPC_STRUCT7->DATA = 0UL; - /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */ - IPC_STRUCT7->RELEASE = 0UL; - } -#endif /* defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE) */ + /* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */ + REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL; + + /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */ + REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL; #if !defined(CY_IPC_DEFAULT_CFG_DISABLE) /* Allocate and initialize semaphores for the system operations. */ @@ -256,10 +212,7 @@ void SystemInit(void) /* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm0 }; - if (cy_device->flashPipeRequired != 0u) - { - Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0); - } + Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0); #if defined(CY_DEVICE_PSOC6ABLE2) Cy_Flash_Init(); @@ -295,8 +248,7 @@ __WEAK void Cy_SystemInit(void) * Function Name: SystemCoreClockUpdate ****************************************************************************//** * -* Gets core clock frequency and updates \ref SystemCoreClock, \ref -* cy_Hfclk0FreqHz, and \ref cy_PeriClkFreqHz. +* Gets core clock frequency and updates \ref SystemCoreClock. * * Updates global variables used by the \ref Cy_SysLib_Delay(), \ref * Cy_SysLib_DelayUs(), and \ref Cy_SysLib_DelayCycles(). @@ -304,155 +256,19 @@ __WEAK void Cy_SystemInit(void) *******************************************************************************/ void SystemCoreClockUpdate (void) { - uint32_t srcFreqHz; - uint32_t pathFreqHz; - uint32_t slowClkDiv; - uint32_t periClkDiv; - uint32_t rootPath; - uint32_t srcClk; - - /* Get root path clock for the high-frequency clock # 0 */ - rootPath = _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_MUX, SRSS->CLK_ROOT_SELECT[0u]); - - /* Get source of the root path clock */ - srcClk = _FLD2VAL(SRSS_CLK_PATH_SELECT_PATH_MUX, SRSS->CLK_PATH_SELECT[rootPath]); - - /* Get frequency of the source */ - switch (srcClk) - { - case CY_ROOT_PATH_SRC_IMO: - srcFreqHz = CY_CLK_IMO_FREQ_HZ; - break; - - case CY_ROOT_PATH_SRC_EXT: - srcFreqHz = CY_CLK_EXT_FREQ_HZ; - break; - - #if (SRSS_ECO_PRESENT == 1U) - case CY_ROOT_PATH_SRC_ECO: - srcFreqHz = CY_CLK_ECO_FREQ_HZ; - break; - #endif /* (SRSS_ECO_PRESENT == 1U) */ - -#if defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) - case CY_ROOT_PATH_SRC_ALTHF: - srcFreqHz = cy_BleEcoClockFreqHz; - break; -#endif /* defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) */ - - case CY_ROOT_PATH_SRC_DSI_MUX: - { - uint32_t dsi_src; - dsi_src = _FLD2VAL(SRSS_CLK_DSI_SELECT_DSI_MUX, SRSS->CLK_DSI_SELECT[rootPath]); - switch (dsi_src) - { - case CY_ROOT_PATH_SRC_DSI_MUX_HVILO: - srcFreqHz = CY_CLK_HVILO_FREQ_HZ; - break; - - case CY_ROOT_PATH_SRC_DSI_MUX_WCO: - srcFreqHz = CY_CLK_WCO_FREQ_HZ; - break; - - #if (SRSS_ALTLF_PRESENT == 1U) - case CY_ROOT_PATH_SRC_DSI_MUX_ALTLF: - srcFreqHz = CY_CLK_ALTLF_FREQ_HZ; - break; - #endif /* (SRSS_ALTLF_PRESENT == 1U) */ - - #if (SRSS_PILO_PRESENT == 1U) - case CY_ROOT_PATH_SRC_DSI_MUX_PILO: - srcFreqHz = CY_CLK_PILO_FREQ_HZ; - break; - #endif /* (SRSS_PILO_PRESENT == 1U) */ - - default: - srcFreqHz = CY_CLK_HVILO_FREQ_HZ; - break; - } - } - break; - - default: - srcFreqHz = CY_CLK_EXT_FREQ_HZ; - break; - } + uint32 locHf0Clock = Cy_SysClk_ClkHfGetFrequency(0UL); - if (rootPath == 0UL) + if (0UL != locHf0Clock) { - /* FLL */ - bool fllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_FLL_STATUS_LOCKED, SRSS->CLK_FLL_STATUS)); - bool fllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)); - bool fllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)) || - (1UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3))); - if ((fllOutputAuto && fllLocked) || fllOutputOutput) - { - uint32_t fllMult; - uint32_t refDiv; - uint32_t outputDiv; - - fllMult = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_MULT, SRSS->CLK_FLL_CONFIG); - refDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, SRSS->CLK_FLL_CONFIG2); - outputDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, SRSS->CLK_FLL_CONFIG) + 1UL; - - pathFreqHz = ((srcFreqHz / refDiv) * fllMult) / outputDiv; - } - else - { - pathFreqHz = srcFreqHz; - } + cy_Hfclk0FreqHz = locHf0Clock; + cy_PeriClkFreqHz = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkPeriGetDivider()); + SystemCoreClock = cy_PeriClkFreqHz / (1UL + (uint32_t)Cy_SysClk_ClkSlowGetDivider()); + + /* Sets clock frequency for Delay API */ + cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1M_THRESHOLD); + cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1K_THRESHOLD); + cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz; } - else if ((rootPath == 1UL) || (rootPath == 2UL)) - { - /* PLL */ - bool pllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_PLL_STATUS_LOCKED, SRSS->CLK_PLL_STATUS[rootPath - 1UL])); - bool pllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])); - bool pllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])) || - (1UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]))); - if ((pllOutputAuto && pllLocked) || pllOutputOutput) - { - uint32_t feedbackDiv; - uint32_t referenceDiv; - uint32_t outputDiv; - - feedbackDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); - referenceDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_REFERENCE_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); - outputDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_OUTPUT_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); - - pathFreqHz = ((srcFreqHz * feedbackDiv) / referenceDiv) / outputDiv; - - } - else - { - pathFreqHz = srcFreqHz; - } - } - else - { - /* Direct */ - pathFreqHz = srcFreqHz; - } - - /* Get frequency after hf_clk pre-divider */ - pathFreqHz = pathFreqHz >> _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_DIV, SRSS->CLK_ROOT_SELECT[0u]); - cy_Hfclk0FreqHz = pathFreqHz; - - /* Slow Clock Divider */ - slowClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_SLOW_INT_DIV, CPUSS->CM0_CLOCK_CTL); - - /* Peripheral Clock Divider */ - periClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV, CPUSS->CM0_CLOCK_CTL); - - pathFreqHz = pathFreqHz / periClkDiv; - cy_PeriClkFreqHz = pathFreqHz; - pathFreqHz = pathFreqHz / slowClkDiv; - SystemCoreClock = pathFreqHz; - - /* Sets clock frequency for Delay API */ - cy_delayFreqHz = SystemCoreClock; - cy_delayFreqMhz = (uint8_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD); - cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD; - cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz; } diff --git a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct similarity index 98% rename from devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct rename to devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct index 1a6d41a..47ed29d 100644 --- a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xx5_cm4_dual.sct -;* \version 2.60 +;* \version 2.70 ;* ;* Linker file for the ARMCC. ;* @@ -58,10 +58,10 @@ #define FLASH_START 0x10000000 #define FLASH_SIZE 0x00080000 -; Size of the stack section at the end of CM4 SRAM +; The size of the stack section at the end of CM4 SRAM #define STACK_SIZE 0x00001000 -; Size of the Cortex-M0+ application flash image +; The size of the Cortex-M0+ application flash image #define FLASH_CM0P_SIZE 0x2000 ; The following defines describe a 32K flash region used for EEPROM emulation. @@ -147,7 +147,7 @@ LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE) ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) { } - + ; Stack region growing down ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE { diff --git a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_ARM/cy8c6xx6_cm4.sct b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx6_cm4.sct similarity index 99% rename from devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_ARM/cy8c6xx6_cm4.sct rename to devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx6_cm4.sct index 33446d8..f573555 100644 --- a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_ARM/cy8c6xx6_cm4.sct +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx6_cm4.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xx6_cm4.sct -;* \version 2.60 +;* \version 2.70 ;* ;* Linker file for the ARMCC. ;* @@ -55,7 +55,7 @@ #define FLASH_START 0x10000000 #define FLASH_SIZE 0x00080000 -; Size of the stack section at the end of CM4 SRAM +; The size of the stack section at the end of CM4 SRAM #define STACK_SIZE 0x00001000 ; The following defines describe a 32K flash region used for EEPROM emulation. @@ -132,7 +132,7 @@ LR_IROM1 FLASH_START FLASH_SIZE ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) { } - + ; Stack region growing down ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE { diff --git a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_ARM/cy8c6xx6_cm4_dual.sct b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx6_cm4_dual.sct similarity index 98% rename from devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_ARM/cy8c6xx6_cm4_dual.sct rename to devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx6_cm4_dual.sct index 79352cf..7bfcba9 100644 --- a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_ARM/cy8c6xx6_cm4_dual.sct +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx6_cm4_dual.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xx6_cm4_dual.sct -;* \version 2.60 +;* \version 2.70 ;* ;* Linker file for the ARMCC. ;* @@ -58,10 +58,10 @@ #define FLASH_START 0x10000000 #define FLASH_SIZE 0x00080000 -; Size of the stack section at the end of CM4 SRAM +; The size of the stack section at the end of CM4 SRAM #define STACK_SIZE 0x00001000 -; Size of the Cortex-M0+ application flash image +; The size of the Cortex-M0+ application flash image #define FLASH_CM0P_SIZE 0x2000 ; The following defines describe a 32K flash region used for EEPROM emulation. @@ -147,7 +147,7 @@ LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE) ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) { } - + ; Stack region growing down ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE { diff --git a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_ARM/cy8c6xx7_cm4.sct b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4.sct similarity index 99% rename from devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_ARM/cy8c6xx7_cm4.sct rename to devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4.sct index 422b622..3c1a00e 100644 --- a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_ARM/cy8c6xx7_cm4.sct +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xx7_cm4.sct -;* \version 2.60 +;* \version 2.70 ;* ;* Linker file for the ARMCC. ;* @@ -55,7 +55,7 @@ #define FLASH_START 0x10000000 #define FLASH_SIZE 0x00100000 -; Size of the stack section at the end of CM4 SRAM +; The size of the stack section at the end of CM4 SRAM #define STACK_SIZE 0x00001000 ; The following defines describe a 32K flash region used for EEPROM emulation. @@ -132,7 +132,7 @@ LR_IROM1 FLASH_START FLASH_SIZE ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) { } - + ; Stack region growing down ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE { diff --git a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct similarity index 98% rename from devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct rename to devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct index 5af1eb2..5efe315 100644 --- a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xx7_cm4_dual.sct -;* \version 2.60 +;* \version 2.70 ;* ;* Linker file for the ARMCC. ;* @@ -58,10 +58,10 @@ #define FLASH_START 0x10000000 #define FLASH_SIZE 0x00100000 -; Size of the stack section at the end of CM4 SRAM +; The size of the stack section at the end of CM4 SRAM #define STACK_SIZE 0x00001000 -; Size of the Cortex-M0+ application flash image +; The size of the Cortex-M0+ application flash image #define FLASH_CM0P_SIZE 0x2000 ; The following defines describe a 32K flash region used for EEPROM emulation. @@ -147,7 +147,7 @@ LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE) ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) { } - + ; Stack region growing down ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE { diff --git a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_ARM/cy8c6xx8_cm4_dual.sct b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx8_cm4_dual.sct similarity index 98% rename from devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_ARM/cy8c6xx8_cm4_dual.sct rename to devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx8_cm4_dual.sct index b5fb2a0..0327a2b 100644 --- a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_ARM/cy8c6xx8_cm4_dual.sct +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx8_cm4_dual.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xx8_cm4_dual.sct -;* \version 2.60 +;* \version 2.70 ;* ;* Linker file for the ARMCC. ;* @@ -58,10 +58,10 @@ #define FLASH_START 0x10000000 #define FLASH_SIZE 0x00100000 -; Size of the stack section at the end of CM4 SRAM +; The size of the stack section at the end of CM4 SRAM #define STACK_SIZE 0x00001000 -; Size of the Cortex-M0+ application flash image +; The size of the Cortex-M0+ application flash image #define FLASH_CM0P_SIZE 0x2000 ; The following defines describe a 32K flash region used for EEPROM emulation. @@ -147,7 +147,7 @@ LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE) ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) { } - + ; Stack region growing down ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE { diff --git a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct similarity index 98% rename from devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct rename to devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct index 45c24ba..18abfff 100644 --- a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xxa_cm4_dual.sct -;* \version 2.60 +;* \version 2.70 ;* ;* Linker file for the ARMCC. ;* @@ -58,10 +58,10 @@ #define FLASH_START 0x10000000 #define FLASH_SIZE 0x00200000 -; Size of the stack section at the end of CM4 SRAM +; The size of the stack section at the end of CM4 SRAM #define STACK_SIZE 0x00001000 -; Size of the Cortex-M0+ application flash image +; The size of the Cortex-M0+ application flash image #define FLASH_CM0P_SIZE 0x2000 ; The following defines describe a 32K flash region used for EEPROM emulation. @@ -147,7 +147,7 @@ LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE) ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) { } - + ; Stack region growing down ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE { diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx5_cm4.sct b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx5_cm4.sct new file mode 100644 index 0000000..0a61404 --- /dev/null +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx5_cm4.sct @@ -0,0 +1,241 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cyb06xx5_cm4.sct +;* \version 2.70 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; RAM +#define RAM_START 0x08000000 +#define RAM_SIZE 0x0002A000 +; Flash +#define FLASH_START 0x10000000 +#define FLASH_SIZE 0x00060000 + +; The size of the stack section at the end of CM4 SRAM +#define STACK_SIZE 0x00001000 + +; The size of the MCU boot header area at the start of FLASH +#define BOOT_HEADER_SIZE 0x00000400 + + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M4 application flash area +LR_IROM1 FLASH_START FLASH_SIZE +{ + ER_FLASH_VECTORS +BOOT_HEADER_SIZE + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + .cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00070000 +#define __cy_memory_0_row_size 0x200 + + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx5_cm4_dual.sct b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx5_cm4_dual.sct new file mode 100644 index 0000000..ba9834b --- /dev/null +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx5_cm4_dual.sct @@ -0,0 +1,244 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cyb06xx5_cm4_dual.sct +;* \version 2.70 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; You can change the memory allocation by editing RAM and Flash defines. +; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', +; where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.scat'. +; RAM +#define RAM_START 0x08010000 +#define RAM_SIZE 0x0001A000 +; Flash +#define FLASH_START 0x10010000 +#define FLASH_SIZE 0x00020000 + +; The size of the stack section at the end of CM4 SRAM +#define STACK_SIZE 0x00001000 + +; The size of the MCU boot header area at the start of FLASH +#define BOOT_HEADER_SIZE 0x00000400 + + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M4 application flash area +LR_IROM1 FLASH_START FLASH_SIZE +{ + ER_FLASH_VECTORS +BOOT_HEADER_SIZE + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + .cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00070000 +#define __cy_memory_0_row_size 0x200 + + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4.sct b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4.sct new file mode 100644 index 0000000..d0de70c --- /dev/null +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4.sct @@ -0,0 +1,260 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cyb06xx7_cm4.sct +;* \version 2.70 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; RAM +#define RAM_START 0x08000000 +#define RAM_SIZE 0x0002A000 +; Flash +#define FLASH_START 0x10000000 +#define FLASH_SIZE 0x000D0000 + +; The size of the stack section at the end of CM4 SRAM +#define STACK_SIZE 0x00001000 + +; The size of the MCU boot header area at the start of FLASH +#define BOOT_HEADER_SIZE 0x00000400 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M4 application flash area +LR_IROM1 FLASH_START FLASH_SIZE +{ + ER_FLASH_VECTORS +BOOT_HEADER_SIZE + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + .cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x000D0000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct similarity index 93% rename from devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct rename to devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct index 71c89e0..ed8c6d1 100644 --- a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cyb06xx7_cm4_dual.sct -;* \version 2.60 +;* \version 2.70 ;* ;* Linker file for the ARMCC. ;* @@ -47,20 +47,21 @@ ; The following defines control RAM and flash memory allocation for the CM4 core. ; You can change the memory allocation by editing RAM and Flash defines. -; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. -; Using this memory region for other purposes will lead to unexpected behavior. ; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', -; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. +; where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.scat'. ; RAM -#define RAM_START 0x08000000 -#define RAM_SIZE 0x00020000 +#define RAM_START 0x08010000 +#define RAM_SIZE 0x0001A000 ; Flash -#define FLASH_START 0x10000400 -#define FLASH_SIZE 0x000CFC00 +#define FLASH_START 0x10020000 +#define FLASH_SIZE 0x00040000 -; Size of the stack section at the end of CM4 SRAM +; The size of the stack section at the end of CM4 SRAM #define STACK_SIZE 0x00001000 +; The size of the MCU boot header area at the start of FLASH +#define BOOT_HEADER_SIZE 0x00000400 + ; The following defines describe a 32K flash region used for EEPROM emulation. ; This region can also be used as the general purpose flash. ; You can assign sections to this memory region for only one of the cores. @@ -102,7 +103,7 @@ ; Cortex-M4 application flash area LR_IROM1 FLASH_START FLASH_SIZE { - ER_FLASH_VECTORS +0 + ER_FLASH_VECTORS +BOOT_HEADER_SIZE { * (RESET, +FIRST) } @@ -135,7 +136,7 @@ LR_IROM1 FLASH_START FLASH_SIZE ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) { } - + ; Stack region growing down ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE { diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4.sct b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4.sct new file mode 100644 index 0000000..c95e2d4 --- /dev/null +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4.sct @@ -0,0 +1,260 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cyb06xxa_cm4.sct +;* \version 2.70 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; RAM +#define RAM_START 0x08000000 +#define RAM_SIZE 0x000EA000 +; Flash +#define FLASH_START 0x10000000 +#define FLASH_SIZE 0x001D0000 + +; The size of the stack section at the end of CM4 SRAM +#define STACK_SIZE 0x00001000 + +; The size of the MCU boot header area at the start of FLASH +#define BOOT_HEADER_SIZE 0x00000400 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M4 application flash area +LR_IROM1 FLASH_START FLASH_SIZE +{ + ER_FLASH_VECTORS +BOOT_HEADER_SIZE + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + .cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x001D0000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_ARM/cyb06xxa_cm4_dual.sct b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4_dual.sct similarity index 93% rename from devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_ARM/cyb06xxa_cm4_dual.sct rename to devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4_dual.sct index c2e8f97..f80d292 100644 --- a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_ARM/cyb06xxa_cm4_dual.sct +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4_dual.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cyb06xxa_cm4_dual.sct -;* \version 2.60 +;* \version 2.70 ;* ;* Linker file for the ARMCC. ;* @@ -47,20 +47,21 @@ ; The following defines control RAM and flash memory allocation for the CM4 core. ; You can change the memory allocation by editing RAM and Flash defines. -; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. -; Using this memory region for other purposes will lead to unexpected behavior. ; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', -; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. +; where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.scat'. ; RAM -#define RAM_START 0x08000000 -#define RAM_SIZE 0x000D8000 +#define RAM_START 0x08040000 +#define RAM_SIZE 0x000AA000 ; Flash -#define FLASH_START 0x10000400 -#define FLASH_SIZE 0x001CFC00 +#define FLASH_START 0x10040000 +#define FLASH_SIZE 0x000A8000 -; Size of the stack section at the end of CM4 SRAM +; The size of the stack section at the end of CM4 SRAM #define STACK_SIZE 0x00001000 +; The size of the MCU boot header area at the start of FLASH +#define BOOT_HEADER_SIZE 0x00000400 + ; The following defines describe a 32K flash region used for EEPROM emulation. ; This region can also be used as the general purpose flash. ; You can assign sections to this memory region for only one of the cores. @@ -102,7 +103,7 @@ ; Cortex-M4 application flash area LR_IROM1 FLASH_START FLASH_SIZE { - ER_FLASH_VECTORS +0 + ER_FLASH_VECTORS +BOOT_HEADER_SIZE { * (RESET, +FIRST) } @@ -135,7 +136,7 @@ LR_IROM1 FLASH_START FLASH_SIZE ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) { } - + ; Stack region growing down ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE { diff --git a/devices/bsp/COMPONENT_MTB/startup/TOOLCHAIN_ARM/startup_psoc6_01_cm4.s b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.s similarity index 100% rename from devices/bsp/COMPONENT_MTB/startup/TOOLCHAIN_ARM/startup_psoc6_01_cm4.s rename to devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.s diff --git a/devices/bsp/COMPONENT_MTB/startup/TOOLCHAIN_ARM/startup_psoc6_02_cm4.s b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.s similarity index 100% rename from devices/bsp/COMPONENT_MTB/startup/TOOLCHAIN_ARM/startup_psoc6_02_cm4.s rename to devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.s diff --git a/devices/bsp/COMPONENT_MTB/startup/TOOLCHAIN_ARM/startup_psoc6_03_cm4.s b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_03_cm4.s similarity index 100% rename from devices/bsp/COMPONENT_MTB/startup/TOOLCHAIN_ARM/startup_psoc6_03_cm4.s rename to devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_03_cm4.s diff --git a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_A_Clang/cy8c6xx5_cm4_dual.mk b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx5_cm4_dual.mk similarity index 96% rename from devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_A_Clang/cy8c6xx5_cm4_dual.mk rename to devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx5_cm4_dual.mk index 0251f8c..3d54b9f 100644 --- a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_A_Clang/cy8c6xx5_cm4_dual.mk +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx5_cm4_dual.mk @@ -1,6 +1,6 @@ ################################################################################ # \file cy8c6xx5_cm4_dual.mk -# \version 2.60 +# \version 2.70 # # \brief # Specifies the starting address and the size of the segments in the output @@ -77,9 +77,13 @@ SECTIONS_CM4 := \ # Pass section addresses to the linker ifeq ($(CORE),CM4) -LDFLAGS += $(SECTIONS_CM4) +LDFLAGS += \ + -segalign 4 \ + $(SECTIONS_CM4) else ifeq ($(CORE),CM0P) -LDFLAGS += $(SECTIONS_CM0P) +LDFLAGS += \ + -segalign 4 \ + $(SECTIONS_CM0P) endif # EOF diff --git a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_A_Clang/cy8c6xx6_cm4.mk b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx6_cm4.mk similarity index 96% rename from devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_A_Clang/cy8c6xx6_cm4.mk rename to devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx6_cm4.mk index 42fc19d..fe29c43 100644 --- a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_A_Clang/cy8c6xx6_cm4.mk +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx6_cm4.mk @@ -1,6 +1,6 @@ ################################################################################ # \file cy8c6xx6_cm4.mk -# \version 2.60 +# \version 2.70 # # \brief # Specifies the starting address and the size of the segments in the output @@ -52,7 +52,9 @@ SECTIONS_CM4 := \ # Pass section addresses to the linker ifeq ($(CORE),CM4) -LDFLAGS += $(SECTIONS_CM4) +LDFLAGS += \ + -segalign 4 \ + $(SECTIONS_CM4) endif # EOF diff --git a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_A_Clang/cy8c6xx6_cm4_dual.mk b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx6_cm4_dual.mk similarity index 96% rename from devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_A_Clang/cy8c6xx6_cm4_dual.mk rename to devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx6_cm4_dual.mk index efd2b1f..5c158bc 100644 --- a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_A_Clang/cy8c6xx6_cm4_dual.mk +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx6_cm4_dual.mk @@ -1,6 +1,6 @@ ################################################################################ # \file cy8c6xx6_cm4_dual.mk -# \version 2.60 +# \version 2.70 # # \brief # Specifies the starting address and the size of the segments in the output @@ -77,9 +77,13 @@ SECTIONS_CM4 := \ # Pass section addresses to the linker ifeq ($(CORE),CM4) -LDFLAGS += $(SECTIONS_CM4) +LDFLAGS += \ + -segalign 4 \ + $(SECTIONS_CM4) else ifeq ($(CORE),CM0P) -LDFLAGS += $(SECTIONS_CM0P) +LDFLAGS += \ + -segalign 4 \ + $(SECTIONS_CM0P) endif # EOF diff --git a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_A_Clang/cy8c6xx7_cm4.mk b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx7_cm4.mk similarity index 96% rename from devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_A_Clang/cy8c6xx7_cm4.mk rename to devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx7_cm4.mk index dc6bd8e..8fa9337 100644 --- a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_A_Clang/cy8c6xx7_cm4.mk +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx7_cm4.mk @@ -1,6 +1,6 @@ ################################################################################ # \file cy8c6xx7_cm4.mk -# \version 2.60 +# \version 2.70 # # \brief # Specifies the starting address and the size of the segments in the output @@ -52,7 +52,9 @@ SECTIONS_CM4 := \ # Pass section addresses to the linker ifeq ($(CORE),CM4) -LDFLAGS += $(SECTIONS_CM4) +LDFLAGS += \ + -segalign 4 \ + $(SECTIONS_CM4) endif # EOF diff --git a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_A_Clang/cy8c6xx7_cm4_dual.mk b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx7_cm4_dual.mk similarity index 96% rename from devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_A_Clang/cy8c6xx7_cm4_dual.mk rename to devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx7_cm4_dual.mk index 212b141..495c6ce 100644 --- a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_A_Clang/cy8c6xx7_cm4_dual.mk +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx7_cm4_dual.mk @@ -1,6 +1,6 @@ ################################################################################ # \file cy8c6xx7_cm4_dual.mk -# \version 2.60 +# \version 2.70 # # \brief # Specifies the starting address and the size of the segments in the output @@ -77,9 +77,13 @@ SECTIONS_CM4 := \ # Pass section addresses to the linker ifeq ($(CORE),CM4) -LDFLAGS += $(SECTIONS_CM4) +LDFLAGS += \ + -segalign 4 \ + $(SECTIONS_CM4) else ifeq ($(CORE),CM0P) -LDFLAGS += $(SECTIONS_CM0P) +LDFLAGS += \ + -segalign 4 \ + $(SECTIONS_CM0P) endif # EOF diff --git a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_A_Clang/cy8c6xx8_cm4_dual.mk b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx8_cm4_dual.mk similarity index 96% rename from devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_A_Clang/cy8c6xx8_cm4_dual.mk rename to devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx8_cm4_dual.mk index 01154b9..598c856 100644 --- a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_A_Clang/cy8c6xx8_cm4_dual.mk +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx8_cm4_dual.mk @@ -1,6 +1,6 @@ ################################################################################ # \file cy8c6xx8_cm4_dual.mk -# \version 2.60 +# \version 2.70 # # \brief # Specifies the starting address and the size of the segments in the output @@ -77,9 +77,13 @@ SECTIONS_CM4 := \ # Pass section addresses to the linker ifeq ($(CORE),CM4) -LDFLAGS += $(SECTIONS_CM4) +LDFLAGS += \ + -segalign 4 \ + $(SECTIONS_CM4) else ifeq ($(CORE),CM0P) -LDFLAGS += $(SECTIONS_CM0P) +LDFLAGS += \ + -segalign 4 \ + $(SECTIONS_CM0P) endif # EOF diff --git a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_A_Clang/cy8c6xxa_cm4_dual.mk b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xxa_cm4_dual.mk similarity index 96% rename from devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_A_Clang/cy8c6xxa_cm4_dual.mk rename to devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xxa_cm4_dual.mk index e6d0045..9fff442 100644 --- a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_A_Clang/cy8c6xxa_cm4_dual.mk +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xxa_cm4_dual.mk @@ -1,6 +1,6 @@ ################################################################################ # \file cy8c6xxa_cm4_dual.mk -# \version 2.60 +# \version 2.70 # # \brief # Specifies the starting address and the size of the segments in the output @@ -77,9 +77,13 @@ SECTIONS_CM4 := \ # Pass section addresses to the linker ifeq ($(CORE),CM4) -LDFLAGS += $(SECTIONS_CM4) +LDFLAGS += \ + -segalign 4 \ + $(SECTIONS_CM4) else ifeq ($(CORE),CM0P) -LDFLAGS += $(SECTIONS_CM0P) +LDFLAGS += \ + -segalign 4 \ + $(SECTIONS_CM0P) endif # EOF diff --git a/devices/bsp/COMPONENT_MTB/startup/TOOLCHAIN_A_Clang/startup_psoc6_01_cm4.S b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/startup_psoc6_01_cm4.S similarity index 94% rename from devices/bsp/COMPONENT_MTB/startup/TOOLCHAIN_A_Clang/startup_psoc6_01_cm4.S rename to devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/startup_psoc6_01_cm4.S index e641b3c..75205b0 100644 --- a/devices/bsp/COMPONENT_MTB/startup/TOOLCHAIN_A_Clang/startup_psoc6_01_cm4.S +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/startup_psoc6_01_cm4.S @@ -40,7 +40,8 @@ #endif .globl __StackTop .globl __StackLimit - __StackLimit: + +__StackLimit: .space Stack_Size .equ __StackTop, . - Stack_Size @@ -54,7 +55,7 @@ .globl __HeapBase __HeapBase: .if Heap_Size - .space Heap_Size + .space Heap_Size .endif .section __VECT, ___Vectors @@ -62,7 +63,7 @@ __HeapBase: .globl ___Vectors ___Vectors: .long __StackTop /* Top of Stack */ - .long Reset_Handler+1 /* Reset Handler. Added +1, clang doesn't make lsb to 1 for thumb */ + .long Reset_Handler /* Reset Handler */ .long CY_NMI_HANLDER_ADDR /* NMI Handler */ .long HardFault_Handler /* Hard Fault Handler */ .long MemManage_Handler /* MPU Fault Handler */ @@ -232,14 +233,14 @@ ___Vectors: .section __RAMVECTORS, ___ramVectors .align 2 .globl ___ramVectors + ___ramVectors: .space __VectorsSize - /* Only .text, otherwise the linker is smart enough to treat .thumb_func as 2 byte aligned and the - * Reset handler vector + 1 in the vector table ends up at +2 and boot fails. Clang/LLVM issue. - */ .text + .thumb_func + .align 2 /* Reset handler */ .globl Reset_Handler @@ -256,55 +257,22 @@ Reset_Handler: * * All addresses must be aligned to 4 bytes boundary. */ - .equ __copy_table_start__, ___Vectors - .equ __data_start__, ___ramVectors - .equ __data_end__, __data_start__ + __VectorsSize - ldr r1, =__copy_table_start__ - ldr r2, =__data_start__ - ldr r3, =__data_end__ -.L_loop_copy_table: - subs r4, r3, r2 - ble .L_loop_copy_table_done - ldr r0, [r1,r4] - str r0, [r2,r4] - subs r3, #4 - bgt .L_loop_copy_table -.L_loop_copy_table_done: + ldr r0, =___ramVectors + ldr r1, =___Vectors + ldr r2, =__VectorsSize + bl _memcpy + + ldr r0, =segment$start$__DATA ldr r1, =segment$end$__TEXT - ldr r2, =section$start$__DATA$__data - ldr r3, =section$end$__DATA$__data - mov r4, #3 - adds r1, #3 - mvn r4, r4 - and r1, r4 -.L_loop_copy_data: - subs r4, r3, r2 - ble .L_loop_copy_data_done - ldr r0, [r1,r4] - str r0, [r2,r4] - subs r3, #4 - bgt .L_loop_copy_data -.L_loop_copy_data_done: - ldr r2, =section$start$__DATA$__bss - ldr r3, =section$end$__DATA$__bss -.L_loop_bss: - subs r1, r3, r2 - ble .L_loop_bss_done - movs r0, #0 - str r0, [r2,r1] - subs r3, #4 - bgt .L_loop_bss -.L_loop_bss_done: ldr r2, =section$start$__DATA$__zerofill - ldr r3, =section$end$__DATA$__zerofill -.L_loop_zerofill: - subs r1, r3, r2 - ble .L_loop_zerofill_done - movs r0, #0 - str r0, [r2,r1] - subs r3, #4 - bgt .L_loop_zerofill -.L_loop_zerofill_done: + sub r2, r0 + bl _memcpy + + ldr r0, =section$start$__DATA$__zerofill + eor r1, r1 + ldr r2, =section$end$__DATA$__zerofill + sub r2, r0 + bl _memset /* Update Vector Table Offset Register. */ ldr r0, =___ramVectors @@ -330,11 +298,11 @@ Reset_Handler: .text .thumb .thumb_func - .align 2 + .align 2 /* Device startup customization */ .weak_definition Cy_OnResetUser - .global Cy_OnResetUser, Cy_OnResetUser + .global Cy_OnResetUser, Cy_OnResetUser Cy_OnResetUser: bx lr diff --git a/devices/bsp/COMPONENT_MTB/startup/TOOLCHAIN_A_Clang/startup_psoc6_02_cm4.S b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/startup_psoc6_02_cm4.S similarity index 95% rename from devices/bsp/COMPONENT_MTB/startup/TOOLCHAIN_A_Clang/startup_psoc6_02_cm4.S rename to devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/startup_psoc6_02_cm4.S index bff6fd5..02d2c66 100644 --- a/devices/bsp/COMPONENT_MTB/startup/TOOLCHAIN_A_Clang/startup_psoc6_02_cm4.S +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/startup_psoc6_02_cm4.S @@ -40,7 +40,8 @@ #endif .globl __StackTop .globl __StackLimit - __StackLimit: + +__StackLimit: .space Stack_Size .equ __StackTop, . - Stack_Size @@ -54,7 +55,7 @@ .globl __HeapBase __HeapBase: .if Heap_Size - .space Heap_Size + .space Heap_Size .endif .section __VECT, ___Vectors @@ -62,7 +63,7 @@ __HeapBase: .globl ___Vectors ___Vectors: .long __StackTop /* Top of Stack */ - .long Reset_Handler+1 /* Reset Handler. Added +1, clang doesn't make lsb to 1 for thumb */ + .long Reset_Handler /* Reset Handler */ .long CY_NMI_HANLDER_ADDR /* NMI Handler */ .long HardFault_Handler /* Hard Fault Handler */ .long MemManage_Handler /* MPU Fault Handler */ @@ -253,14 +254,14 @@ ___Vectors: .section __RAMVECTORS, ___ramVectors .align 2 .globl ___ramVectors + ___ramVectors: .space __VectorsSize - /* Only .text, otherwise the linker is smart enough to treat .thumb_func as 2 byte aligned and the - * Reset handler vector + 1 in the vector table ends up at +2 and boot fails. Clang/LLVM issue. - */ .text + .thumb_func + .align 2 /* Reset handler */ .globl Reset_Handler @@ -277,55 +278,22 @@ Reset_Handler: * * All addresses must be aligned to 4 bytes boundary. */ - .equ __copy_table_start__, ___Vectors - .equ __data_start__, ___ramVectors - .equ __data_end__, __data_start__ + __VectorsSize - ldr r1, =__copy_table_start__ - ldr r2, =__data_start__ - ldr r3, =__data_end__ -.L_loop_copy_table: - subs r4, r3, r2 - ble .L_loop_copy_table_done - ldr r0, [r1,r4] - str r0, [r2,r4] - subs r3, #4 - bgt .L_loop_copy_table -.L_loop_copy_table_done: + ldr r0, =___ramVectors + ldr r1, =___Vectors + ldr r2, =__VectorsSize + bl _memcpy + + ldr r0, =segment$start$__DATA ldr r1, =segment$end$__TEXT - ldr r2, =section$start$__DATA$__data - ldr r3, =section$end$__DATA$__data - mov r4, #3 - adds r1, #3 - mvn r4, r4 - and r1, r4 -.L_loop_copy_data: - subs r4, r3, r2 - ble .L_loop_copy_data_done - ldr r0, [r1,r4] - str r0, [r2,r4] - subs r3, #4 - bgt .L_loop_copy_data -.L_loop_copy_data_done: - ldr r2, =section$start$__DATA$__bss - ldr r3, =section$end$__DATA$__bss -.L_loop_bss: - subs r1, r3, r2 - ble .L_loop_bss_done - movs r0, #0 - str r0, [r2,r1] - subs r3, #4 - bgt .L_loop_bss -.L_loop_bss_done: ldr r2, =section$start$__DATA$__zerofill - ldr r3, =section$end$__DATA$__zerofill -.L_loop_zerofill: - subs r1, r3, r2 - ble .L_loop_zerofill_done - movs r0, #0 - str r0, [r2,r1] - subs r3, #4 - bgt .L_loop_zerofill -.L_loop_zerofill_done: + sub r2, r0 + bl _memcpy + + ldr r0, =section$start$__DATA$__zerofill + eor r1, r1 + ldr r2, =section$end$__DATA$__zerofill + sub r2, r0 + bl _memset /* Update Vector Table Offset Register. */ ldr r0, =___ramVectors @@ -351,11 +319,11 @@ Reset_Handler: .text .thumb .thumb_func - .align 2 + .align 2 /* Device startup customization */ .weak_definition Cy_OnResetUser - .global Cy_OnResetUser, Cy_OnResetUser + .global Cy_OnResetUser, Cy_OnResetUser Cy_OnResetUser: bx lr diff --git a/devices/bsp/COMPONENT_MTB/startup/TOOLCHAIN_A_Clang/startup_psoc6_03_cm4.S b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/startup_psoc6_03_cm4.S similarity index 95% rename from devices/bsp/COMPONENT_MTB/startup/TOOLCHAIN_A_Clang/startup_psoc6_03_cm4.S rename to devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/startup_psoc6_03_cm4.S index 1482bcd..45ba41c 100644 --- a/devices/bsp/COMPONENT_MTB/startup/TOOLCHAIN_A_Clang/startup_psoc6_03_cm4.S +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/startup_psoc6_03_cm4.S @@ -40,7 +40,8 @@ #endif .globl __StackTop .globl __StackLimit - __StackLimit: + +__StackLimit: .space Stack_Size .equ __StackTop, . - Stack_Size @@ -54,7 +55,7 @@ .globl __HeapBase __HeapBase: .if Heap_Size - .space Heap_Size + .space Heap_Size .endif .section __VECT, ___Vectors @@ -62,7 +63,7 @@ __HeapBase: .globl ___Vectors ___Vectors: .long __StackTop /* Top of Stack */ - .long Reset_Handler+1 /* Reset Handler. Added +1, clang doesn't make lsb to 1 for thumb */ + .long Reset_Handler /* Reset Handler */ .long CY_NMI_HANLDER_ADDR /* NMI Handler */ .long HardFault_Handler /* Hard Fault Handler */ .long MemManage_Handler /* MPU Fault Handler */ @@ -259,14 +260,14 @@ ___Vectors: .section __RAMVECTORS, ___ramVectors .align 2 .globl ___ramVectors + ___ramVectors: .space __VectorsSize - /* Only .text, otherwise the linker is smart enough to treat .thumb_func as 2 byte aligned and the - * Reset handler vector + 1 in the vector table ends up at +2 and boot fails. Clang/LLVM issue. - */ .text + .thumb_func + .align 2 /* Reset handler */ .globl Reset_Handler @@ -283,55 +284,22 @@ Reset_Handler: * * All addresses must be aligned to 4 bytes boundary. */ - .equ __copy_table_start__, ___Vectors - .equ __data_start__, ___ramVectors - .equ __data_end__, __data_start__ + __VectorsSize - ldr r1, =__copy_table_start__ - ldr r2, =__data_start__ - ldr r3, =__data_end__ -.L_loop_copy_table: - subs r4, r3, r2 - ble .L_loop_copy_table_done - ldr r0, [r1,r4] - str r0, [r2,r4] - subs r3, #4 - bgt .L_loop_copy_table -.L_loop_copy_table_done: + ldr r0, =___ramVectors + ldr r1, =___Vectors + ldr r2, =__VectorsSize + bl _memcpy + + ldr r0, =segment$start$__DATA ldr r1, =segment$end$__TEXT - ldr r2, =section$start$__DATA$__data - ldr r3, =section$end$__DATA$__data - mov r4, #3 - adds r1, #3 - mvn r4, r4 - and r1, r4 -.L_loop_copy_data: - subs r4, r3, r2 - ble .L_loop_copy_data_done - ldr r0, [r1,r4] - str r0, [r2,r4] - subs r3, #4 - bgt .L_loop_copy_data -.L_loop_copy_data_done: - ldr r2, =section$start$__DATA$__bss - ldr r3, =section$end$__DATA$__bss -.L_loop_bss: - subs r1, r3, r2 - ble .L_loop_bss_done - movs r0, #0 - str r0, [r2,r1] - subs r3, #4 - bgt .L_loop_bss -.L_loop_bss_done: ldr r2, =section$start$__DATA$__zerofill - ldr r3, =section$end$__DATA$__zerofill -.L_loop_zerofill: - subs r1, r3, r2 - ble .L_loop_zerofill_done - movs r0, #0 - str r0, [r2,r1] - subs r3, #4 - bgt .L_loop_zerofill -.L_loop_zerofill_done: + sub r2, r0 + bl _memcpy + + ldr r0, =section$start$__DATA$__zerofill + eor r1, r1 + ldr r2, =section$end$__DATA$__zerofill + sub r2, r0 + bl _memset /* Update Vector Table Offset Register. */ ldr r0, =___ramVectors @@ -357,11 +325,11 @@ Reset_Handler: .text .thumb .thumb_func - .align 2 + .align 2 /* Device startup customization */ .weak_definition Cy_OnResetUser - .global Cy_OnResetUser, Cy_OnResetUser + .global Cy_OnResetUser, Cy_OnResetUser Cy_OnResetUser: bx lr diff --git a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm4_dual.ld b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm4_dual.ld similarity index 98% rename from devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm4_dual.ld rename to devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm4_dual.ld index 9517cd6..7b9ea66 100644 --- a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm4_dual.ld +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm4_dual.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx5_cm4_dual.ld -* \version 2.60 +* \version 2.70 * * Linker file for the GNU C compiler. * @@ -40,10 +40,10 @@ SEARCH_DIR(.) GROUP(-lgcc -lc -lnosys) ENTRY(Reset_Handler) -/* Size of the stack section at the end of CM4 SRAM */ +/* The size of the stack section at the end of CM4 SRAM */ STACK_SIZE = 0x1000; -/* Size of the Cortex-M0+ application image at the start of FLASH */ +/* The size of the Cortex-M0+ application image at the start of FLASH */ FLASH_CM0P_SIZE = 0x2000; /* Force symbol to be entered in the output file as an undefined symbol. Doing diff --git a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_GCC_ARM/cy8c6xx6_cm4.ld b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx6_cm4.ld similarity index 99% rename from devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_GCC_ARM/cy8c6xx6_cm4.ld rename to devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx6_cm4.ld index 6258edb..1e41911 100644 --- a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_GCC_ARM/cy8c6xx6_cm4.ld +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx6_cm4.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx6_cm4.ld -* \version 2.60 +* \version 2.70 * * Linker file for the GNU C compiler. * @@ -40,7 +40,7 @@ SEARCH_DIR(.) GROUP(-lgcc -lc -lnosys) ENTRY(Reset_Handler) -/* Size of the stack section at the end of CM4 SRAM */ +/* The size of the stack section at the end of CM4 SRAM */ STACK_SIZE = 0x1000; /* Force symbol to be entered in the output file as an undefined symbol. Doing diff --git a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_GCC_ARM/cy8c6xx6_cm4_dual.ld b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx6_cm4_dual.ld similarity index 98% rename from devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_GCC_ARM/cy8c6xx6_cm4_dual.ld rename to devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx6_cm4_dual.ld index 5ec86a0..01382f8 100644 --- a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_GCC_ARM/cy8c6xx6_cm4_dual.ld +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx6_cm4_dual.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx6_cm4_dual.ld -* \version 2.60 +* \version 2.70 * * Linker file for the GNU C compiler. * @@ -40,10 +40,10 @@ SEARCH_DIR(.) GROUP(-lgcc -lc -lnosys) ENTRY(Reset_Handler) -/* Size of the stack section at the end of CM4 SRAM */ +/* The size of the stack section at the end of CM4 SRAM */ STACK_SIZE = 0x1000; -/* Size of the Cortex-M0+ application image at the start of FLASH */ +/* The size of the Cortex-M0+ application image at the start of FLASH */ FLASH_CM0P_SIZE = 0x2000; /* Force symbol to be entered in the output file as an undefined symbol. Doing diff --git a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4.ld b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4.ld similarity index 99% rename from devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4.ld rename to devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4.ld index ce0395f..825375f 100644 --- a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4.ld +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx7_cm4.ld -* \version 2.60 +* \version 2.70 * * Linker file for the GNU C compiler. * @@ -40,7 +40,7 @@ SEARCH_DIR(.) GROUP(-lgcc -lc -lnosys) ENTRY(Reset_Handler) -/* Size of the stack section at the end of CM4 SRAM */ +/* The size of the stack section at the end of CM4 SRAM */ STACK_SIZE = 0x1000; /* Force symbol to be entered in the output file as an undefined symbol. Doing diff --git a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld similarity index 98% rename from devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld rename to devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld index 31d3596..2d23d29 100644 --- a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx7_cm4_dual.ld -* \version 2.60 +* \version 2.70 * * Linker file for the GNU C compiler. * @@ -40,10 +40,10 @@ SEARCH_DIR(.) GROUP(-lgcc -lc -lnosys) ENTRY(Reset_Handler) -/* Size of the stack section at the end of CM4 SRAM */ +/* The size of the stack section at the end of CM4 SRAM */ STACK_SIZE = 0x1000; -/* Size of the Cortex-M0+ application image at the start of FLASH */ +/* The size of the Cortex-M0+ application image at the start of FLASH */ FLASH_CM0P_SIZE = 0x2000; /* Force symbol to be entered in the output file as an undefined symbol. Doing diff --git a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_GCC_ARM/cy8c6xx8_cm4_dual.ld b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx8_cm4_dual.ld similarity index 98% rename from devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_GCC_ARM/cy8c6xx8_cm4_dual.ld rename to devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx8_cm4_dual.ld index ac7a17e..bb27662 100644 --- a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_GCC_ARM/cy8c6xx8_cm4_dual.ld +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx8_cm4_dual.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx8_cm4_dual.ld -* \version 2.60 +* \version 2.70 * * Linker file for the GNU C compiler. * @@ -40,10 +40,10 @@ SEARCH_DIR(.) GROUP(-lgcc -lc -lnosys) ENTRY(Reset_Handler) -/* Size of the stack section at the end of CM4 SRAM */ +/* The size of the stack section at the end of CM4 SRAM */ STACK_SIZE = 0x1000; -/* Size of the Cortex-M0+ application image at the start of FLASH */ +/* The size of the Cortex-M0+ application image at the start of FLASH */ FLASH_CM0P_SIZE = 0x2000; /* Force symbol to be entered in the output file as an undefined symbol. Doing diff --git a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld similarity index 98% rename from devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld rename to devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld index 2a2607a..ec70309 100644 --- a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xxa_cm4_dual.ld -* \version 2.60 +* \version 2.70 * * Linker file for the GNU C compiler. * @@ -40,10 +40,10 @@ SEARCH_DIR(.) GROUP(-lgcc -lc -lnosys) ENTRY(Reset_Handler) -/* Size of the stack section at the end of CM4 SRAM */ +/* The size of the stack section at the end of CM4 SRAM */ STACK_SIZE = 0x1000; -/* Size of the Cortex-M0+ application image at the start of FLASH */ +/* The size of the Cortex-M0+ application image at the start of FLASH */ FLASH_CM0P_SIZE = 0x2000; /* Force symbol to be entered in the output file as an undefined symbol. Doing diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx5_cm4.ld b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx5_cm4.ld new file mode 100644 index 0000000..8979753 --- /dev/null +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx5_cm4.ld @@ -0,0 +1,405 @@ +/***************************************************************************//** +* \file cyb06xx5_cm4.ld +* \version 2.70 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + +/* The size of the stack section at the end of CM4 SRAM */ +STACK_SIZE = 0x1000; + +/* The size of the MCU boot header area at the start of FLASH */ +BOOT_HEADER_SIZE = 0x400; + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM4 core. + */ + ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x2A000 + flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x60000 + + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + /* Cortex-M4 application flash area */ + .text ORIGIN(flash) + BOOT_HEADER_SIZE : + { + /* Cortex-M4 flash vector table */ + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_03_cm4.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_03_cm4.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > ram + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Used for the digital signature of the secure application and the Bootloader SDK application. + * The size of the section depends on the required data size. */ + .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 : + { + KEEP(*(.cy_app_signature)) + } > flash + + + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + .cy_xip : + { + KEEP(*(.cy_xip)) + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x00070000; +__cy_memory_0_row_size = 0x200; + + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx5_cm4_dual.ld b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx5_cm4_dual.ld new file mode 100644 index 0000000..594c705 --- /dev/null +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx5_cm4_dual.ld @@ -0,0 +1,407 @@ +/***************************************************************************//** +* \file cyb06xx5_cm4_dual.ld +* \version 2.70 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + +/* The size of the stack section at the end of CM4 SRAM */ +STACK_SIZE = 0x1000; + +/* The size of the MCU boot header area at the start of FLASH */ +BOOT_HEADER_SIZE = 0x400; + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing the 'ram' and 'flash' regions. + * Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld', + * where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.ld'. + */ + ram (rwx) : ORIGIN = 0x08010000, LENGTH = 0x1A000 + flash (rx) : ORIGIN = 0x10010000, LENGTH = 0x20000 + + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + /* Cortex-M4 application flash area */ + .text ORIGIN(flash) + BOOT_HEADER_SIZE : + { + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_03_cm4.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_03_cm4.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > ram + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Used for the digital signature of the secure application and the Bootloader SDK application. + * The size of the section depends on the required data size. */ + .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 : + { + KEEP(*(.cy_app_signature)) + } > flash + + + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + .cy_xip : + { + KEEP(*(.cy_xip)) + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x00070000; +__cy_memory_0_row_size = 0x200; + + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4.ld b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4.ld new file mode 100644 index 0000000..0726ab2 --- /dev/null +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4.ld @@ -0,0 +1,420 @@ +/***************************************************************************//** +* \file cyb06xx7_cm4.ld +* \version 2.70 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + +/* The size of the stack section at the end of CM4 SRAM */ +STACK_SIZE = 0x1000; + +/* The size of the MCU boot header area at the start of FLASH */ +BOOT_HEADER_SIZE = 0x400; + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM4 core. + */ + ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x2A000 + flash (rx) : ORIGIN = 0x10000000, LENGTH = 0xD0000 + + /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ + em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */ + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + /* Cortex-M4 application flash area */ + .text ORIGIN(flash) + BOOT_HEADER_SIZE : + { + /* Cortex-M4 flash vector table */ + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_01_cm4.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_01_cm4.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > ram + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Used for the digital signature of the secure application and the Bootloader SDK application. + * The size of the section depends on the required data size. */ + .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 : + { + KEEP(*(.cy_app_signature)) + } > flash + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + .cy_xip : + { + KEEP(*(.cy_xip)) + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x000D0000; +__cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +__cy_memory_1_start = 0x14000000; +__cy_memory_1_length = 0x8000; +__cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4_dual.ld b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4_dual.ld similarity index 96% rename from devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4_dual.ld rename to devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4_dual.ld index e170033..c2e2db4 100644 --- a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4_dual.ld +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4_dual.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cyb06xx7_cm4_dual.ld -* \version 2.60 +* \version 2.70 * * Linker file for the GNU C compiler. * @@ -40,9 +40,12 @@ SEARCH_DIR(.) GROUP(-lgcc -lc -lnosys) ENTRY(Reset_Handler) -/* Size of the stack section at the end of CM4 SRAM */ +/* The size of the stack section at the end of CM4 SRAM */ STACK_SIZE = 0x1000; +/* The size of the MCU boot header area at the start of FLASH */ +BOOT_HEADER_SIZE = 0x400; + /* Force symbol to be entered in the output file as an undefined symbol. Doing * this may, for example, trigger linking of additional modules from standard * libraries. You may list several symbols for each EXTERN, and you may use @@ -58,13 +61,11 @@ MEMORY { /* The ram and flash regions control RAM and flash memory allocation for the CM4 core. * You can change the memory allocation by editing the 'ram' and 'flash' regions. - * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. - * Using this memory region for other purposes will lead to unexpected behavior. * Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld', - * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'. + * where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.ld'. */ - ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x20000 - flash (rx) : ORIGIN = 0x10000400, LENGTH = 0xCFC00 + ram (rwx) : ORIGIN = 0x08010000, LENGTH = 0x1A000 + flash (rx) : ORIGIN = 0x10020000, LENGTH = 0x40000 /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. * You can assign sections to this memory region for only one of the cores. @@ -123,7 +124,7 @@ GROUP(libgcc.a libc.a libm.a libnosys.a) SECTIONS { /* Cortex-M4 application flash area */ - .text ORIGIN(flash) : + .text ORIGIN(flash) + BOOT_HEADER_SIZE : { . = ALIGN(4); __Vectors = . ; diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4.ld b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4.ld new file mode 100644 index 0000000..6f35751 --- /dev/null +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4.ld @@ -0,0 +1,420 @@ +/***************************************************************************//** +* \file cyb06xxa_cm4.ld +* \version 2.70 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + +/* The size of the stack section at the end of CM4 SRAM */ +STACK_SIZE = 0x1000; + +/* The size of the MCU boot header area at the start of FLASH */ +BOOT_HEADER_SIZE = 0x400; + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM4 core. + */ + ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0xEA000 + flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x1D0000 + + /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ + em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */ + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + /* Cortex-M4 application flash area */ + .text ORIGIN(flash) + BOOT_HEADER_SIZE : + { + /* Cortex-M4 flash vector table */ + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_02_cm4.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_02_cm4.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > ram + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Used for the digital signature of the secure application and the Bootloader SDK application. + * The size of the section depends on the required data size. */ + .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 : + { + KEEP(*(.cy_app_signature)) + } > flash + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + .cy_xip : + { + KEEP(*(.cy_xip)) + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x001D0000; +__cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +__cy_memory_1_start = 0x14000000; +__cy_memory_1_length = 0x8000; +__cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4_dual.ld b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4_dual.ld similarity index 96% rename from devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4_dual.ld rename to devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4_dual.ld index 84584de..926961d 100644 --- a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4_dual.ld +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4_dual.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cyb06xxa_cm4_dual.ld -* \version 2.60 +* \version 2.70 * * Linker file for the GNU C compiler. * @@ -40,9 +40,12 @@ SEARCH_DIR(.) GROUP(-lgcc -lc -lnosys) ENTRY(Reset_Handler) -/* Size of the stack section at the end of CM4 SRAM */ +/* The size of the stack section at the end of CM4 SRAM */ STACK_SIZE = 0x1000; +/* The size of the MCU boot header area at the start of FLASH */ +BOOT_HEADER_SIZE = 0x400; + /* Force symbol to be entered in the output file as an undefined symbol. Doing * this may, for example, trigger linking of additional modules from standard * libraries. You may list several symbols for each EXTERN, and you may use @@ -58,13 +61,11 @@ MEMORY { /* The ram and flash regions control RAM and flash memory allocation for the CM4 core. * You can change the memory allocation by editing the 'ram' and 'flash' regions. - * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. - * Using this memory region for other purposes will lead to unexpected behavior. * Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld', - * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'. + * where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.ld'. */ - ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0xD8000 - flash (rx) : ORIGIN = 0x10000400, LENGTH = 0x1CFC00 + ram (rwx) : ORIGIN = 0x08040000, LENGTH = 0xAA000 + flash (rx) : ORIGIN = 0x10040000, LENGTH = 0xA8000 /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. * You can assign sections to this memory region for only one of the cores. @@ -123,7 +124,7 @@ GROUP(libgcc.a libc.a libm.a libnosys.a) SECTIONS { /* Cortex-M4 application flash area */ - .text ORIGIN(flash) : + .text ORIGIN(flash) + BOOT_HEADER_SIZE : { . = ALIGN(4); __Vectors = . ; diff --git a/devices/bsp/COMPONENT_MTB/startup/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S similarity index 100% rename from devices/bsp/COMPONENT_MTB/startup/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S rename to devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S diff --git a/devices/bsp/COMPONENT_MTB/startup/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S similarity index 100% rename from devices/bsp/COMPONENT_MTB/startup/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S rename to devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S diff --git a/devices/bsp/COMPONENT_MTB/startup/TOOLCHAIN_GCC_ARM/startup_psoc6_03_cm4.S b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_03_cm4.S similarity index 100% rename from devices/bsp/COMPONENT_MTB/startup/TOOLCHAIN_GCC_ARM/startup_psoc6_03_cm4.S rename to devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_03_cm4.S diff --git a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_IAR/cy8c6xx5_cm4_dual.icf b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx5_cm4_dual.icf similarity index 99% rename from devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_IAR/cy8c6xx5_cm4_dual.icf rename to devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx5_cm4_dual.icf index 84654f0..def0b36 100644 --- a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_IAR/cy8c6xx5_cm4_dual.icf +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx5_cm4_dual.icf @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx5_cm4_dual.icf -* \version 2.60 +* \version 2.70 * * Linker file for the IAR compiler. * @@ -127,7 +127,7 @@ if (!isdefinedsymbol(__HEAP_SIZE)) { } /**** End of ICF editor section. ###ICF###*/ -/* Size of the Cortex-M0+ application image */ +/* The size of the Cortex-M0+ application image */ define symbol FLASH_CM0P_SIZE = 0x2000; define memory mem with size = 4G; diff --git a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_IAR/cy8c6xx6_cm4.icf b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx6_cm4.icf similarity index 99% rename from devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_IAR/cy8c6xx6_cm4.icf rename to devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx6_cm4.icf index daa9ad1..e433e16 100644 --- a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_IAR/cy8c6xx6_cm4.icf +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx6_cm4.icf @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx6_cm4.icf -* \version 2.60 +* \version 2.70 * * Linker file for the IAR compiler. * @@ -147,7 +147,6 @@ define block RO { first section .intvec, readonly }; initialize by copy { readwrite }; do not initialize { section .noinit, section .intvec_ram }; - /*-Placement-*/ /* Flash - Cortex-M4 application */ diff --git a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_IAR/cy8c6xx6_cm4_dual.icf b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx6_cm4_dual.icf similarity index 99% rename from devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_IAR/cy8c6xx6_cm4_dual.icf rename to devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx6_cm4_dual.icf index 2d8a820..60fd088 100644 --- a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_IAR/cy8c6xx6_cm4_dual.icf +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx6_cm4_dual.icf @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx6_cm4_dual.icf -* \version 2.60 +* \version 2.70 * * Linker file for the IAR compiler. * @@ -127,7 +127,7 @@ if (!isdefinedsymbol(__HEAP_SIZE)) { } /**** End of ICF editor section. ###ICF###*/ -/* Size of the Cortex-M0+ application image */ +/* The size of the Cortex-M0+ application image */ define symbol FLASH_CM0P_SIZE = 0x2000; define memory mem with size = 4G; diff --git a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_IAR/cy8c6xx7_cm4.icf b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4.icf similarity index 99% rename from devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_IAR/cy8c6xx7_cm4.icf rename to devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4.icf index bc8702c..2f95bf9 100644 --- a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_IAR/cy8c6xx7_cm4.icf +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4.icf @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx7_cm4.icf -* \version 2.60 +* \version 2.70 * * Linker file for the IAR compiler. * @@ -147,7 +147,6 @@ define block RO { first section .intvec, readonly }; initialize by copy { readwrite }; do not initialize { section .noinit, section .intvec_ram }; - /*-Placement-*/ /* Flash - Cortex-M4 application */ diff --git a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf similarity index 99% rename from devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf rename to devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf index e301337..227f659 100644 --- a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx7_cm4_dual.icf -* \version 2.60 +* \version 2.70 * * Linker file for the IAR compiler. * @@ -127,7 +127,7 @@ if (!isdefinedsymbol(__HEAP_SIZE)) { } /**** End of ICF editor section. ###ICF###*/ -/* Size of the Cortex-M0+ application image */ +/* The size of the Cortex-M0+ application image */ define symbol FLASH_CM0P_SIZE = 0x2000; define memory mem with size = 4G; diff --git a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_IAR/cy8c6xx8_cm4_dual.icf b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx8_cm4_dual.icf similarity index 99% rename from devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_IAR/cy8c6xx8_cm4_dual.icf rename to devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx8_cm4_dual.icf index 9cd663d..438512c 100644 --- a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_IAR/cy8c6xx8_cm4_dual.icf +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx8_cm4_dual.icf @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx8_cm4_dual.icf -* \version 2.60 +* \version 2.70 * * Linker file for the IAR compiler. * @@ -127,7 +127,7 @@ if (!isdefinedsymbol(__HEAP_SIZE)) { } /**** End of ICF editor section. ###ICF###*/ -/* Size of the Cortex-M0+ application image */ +/* The size of the Cortex-M0+ application image */ define symbol FLASH_CM0P_SIZE = 0x2000; define memory mem with size = 4G; diff --git a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf similarity index 99% rename from devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf rename to devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf index ef3bdd7..52177fa 100644 --- a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xxa_cm4_dual.icf -* \version 2.60 +* \version 2.70 * * Linker file for the IAR compiler. * @@ -127,7 +127,7 @@ if (!isdefinedsymbol(__HEAP_SIZE)) { } /**** End of ICF editor section. ###ICF###*/ -/* Size of the Cortex-M0+ application image */ +/* The size of the Cortex-M0+ application image */ define symbol FLASH_CM0P_SIZE = 0x2000; define memory mem with size = 4G; diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx5_cm4.icf b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx5_cm4.icf new file mode 100644 index 0000000..4205e23 --- /dev/null +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx5_cm4.icf @@ -0,0 +1,221 @@ +/***************************************************************************//** +* \file cyb06xx5_cm4.icf +* \version 2.70 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x0802A000; +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x10060000; + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x160007FF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/*-Sizes-*/ +if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol __ICFEDIT_size_cstack__ = 0x1000; +} else { + define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; +} +define symbol __ICFEDIT_size_proc_stack__ = 0x0; + +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} +/**** End of ICF editor section. ###ICF###*/ + +/* The size of the MCU boot header area at the start of FLASH */ +define symbol BOOT_HEADER_SIZE = 0x400; + + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; +define block RO {first section .intvec, readonly}; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M4 application */ +place at address (__ICFEDIT_region_IROM1_start__ + BOOT_HEADER_SIZE) { block RO }; + +/* Used for the digital signature of the secure application and the Bootloader SDK application. */ +".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; + + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +".cy_xip" : place at start of EROM1_region { section .cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { readwrite }; +place at end of IRAM1_region { block HSTACK }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_app_signature, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00070000; +define exported symbol __cy_memory_0_row_size = 0x200; + + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx5_cm4_dual.icf b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx5_cm4_dual.icf new file mode 100644 index 0000000..3954305 --- /dev/null +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx5_cm4_dual.icf @@ -0,0 +1,227 @@ +/***************************************************************************//** +* \file cyb06xx5_cm4_dual.icf +* \version 2.70 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf', + * where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = 0x08010000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x0802A000; +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = 0x10010000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x10030000; + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x160007FF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/*-Sizes-*/ +if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol __ICFEDIT_size_cstack__ = 0x1000; +} else { + define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; +} +define symbol __ICFEDIT_size_proc_stack__ = 0x0; + +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} +/**** End of ICF editor section. ###ICF###*/ + +/* The size of the MCU boot header area at the start of FLASH */ +define symbol BOOT_HEADER_SIZE = 0x400; + + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; +define block RO {first section .intvec, readonly}; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M4 application */ +place at address (__ICFEDIT_region_IROM1_start__ + BOOT_HEADER_SIZE) { block RO }; + +/* Used for the digital signature of the secure application and the Bootloader SDK application. */ +".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; + + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +".cy_xip" : place at start of EROM1_region { section .cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { readwrite }; +place at end of IRAM1_region { block HSTACK }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_app_signature, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00070000; +define exported symbol __cy_memory_0_row_size = 0x200; + + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx7_cm4.icf b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx7_cm4.icf new file mode 100644 index 0000000..3e7e32e --- /dev/null +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx7_cm4.icf @@ -0,0 +1,228 @@ +/***************************************************************************//** +* \file cyb06xx7_cm4.icf +* \version 2.70 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x0802A000; +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x100D0000; + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x160007FF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/*-Sizes-*/ +if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol __ICFEDIT_size_cstack__ = 0x1000; +} else { + define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; +} +define symbol __ICFEDIT_size_proc_stack__ = 0x0; + +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} +/**** End of ICF editor section. ###ICF###*/ + +/* The size of the MCU boot header area at the start of FLASH */ +define symbol BOOT_HEADER_SIZE = 0x400; + + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; +define block RO {first section .intvec, readonly}; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M4 application */ +place at address (__ICFEDIT_region_IROM1_start__ + BOOT_HEADER_SIZE) { block RO }; + +/* Used for the digital signature of the secure application and the Bootloader SDK application. */ +".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +".cy_xip" : place at start of EROM1_region { section .cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { readwrite }; +place at end of IRAM1_region { block HSTACK }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_app_signature, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x000D0000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_IAR/cyb06xx7_cm4_dual.icf b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx7_cm4_dual.icf similarity index 94% rename from devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_IAR/cyb06xx7_cm4_dual.icf rename to devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx7_cm4_dual.icf index 4b16aaf..b19511f 100644 --- a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_IAR/cyb06xx7_cm4_dual.icf +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx7_cm4_dual.icf @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cyb06xx7_cm4_dual.icf -* \version 2.60 +* \version 2.70 * * Linker file for the IAR compiler. * @@ -47,17 +47,15 @@ define symbol __ICFEDIT_intvec_start__ = 0x00000000; /* The following symbols control RAM and flash memory allocation for the CM4 core. * You can change the memory allocation by editing RAM and Flash symbols. - * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. - * Using this memory region for other purposes will lead to unexpected behavior. * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf', - * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'. + * where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.icf'. */ /* RAM */ -define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; -define symbol __ICFEDIT_region_IRAM1_end__ = 0x08020000; +define symbol __ICFEDIT_region_IRAM1_start__ = 0x08010000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x0802A000; /* Flash */ -define symbol __ICFEDIT_region_IROM1_start__ = 0x10000400; -define symbol __ICFEDIT_region_IROM1_end__ = 0x100D0000; +define symbol __ICFEDIT_region_IROM1_start__ = 0x10020000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x10060000; /* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. @@ -127,6 +125,10 @@ if (!isdefinedsymbol(__HEAP_SIZE)) { } /**** End of ICF editor section. ###ICF###*/ +/* The size of the MCU boot header area at the start of FLASH */ +define symbol BOOT_HEADER_SIZE = 0x400; + + define memory mem with size = 4G; define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; @@ -152,7 +154,7 @@ do not initialize { section .noinit, section .intvec_ram }; /*-Placement-*/ /* Flash - Cortex-M4 application */ -place at start of IROM1_region { block RO }; +place at address (__ICFEDIT_region_IROM1_start__ + BOOT_HEADER_SIZE) { block RO }; /* Used for the digital signature of the secure application and the Bootloader SDK application. */ ".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xxa_cm4.icf b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xxa_cm4.icf new file mode 100644 index 0000000..7c69a32 --- /dev/null +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xxa_cm4.icf @@ -0,0 +1,228 @@ +/***************************************************************************//** +* \file cyb06xxa_cm4.icf +* \version 2.70 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x080EA000; +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x101D0000; + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x160007FF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/*-Sizes-*/ +if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol __ICFEDIT_size_cstack__ = 0x1000; +} else { + define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; +} +define symbol __ICFEDIT_size_proc_stack__ = 0x0; + +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} +/**** End of ICF editor section. ###ICF###*/ + +/* The size of the MCU boot header area at the start of FLASH */ +define symbol BOOT_HEADER_SIZE = 0x400; + + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; +define block RO {first section .intvec, readonly}; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M4 application */ +place at address (__ICFEDIT_region_IROM1_start__ + BOOT_HEADER_SIZE) { block RO }; + +/* Used for the digital signature of the secure application and the Bootloader SDK application. */ +".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +".cy_xip" : place at start of EROM1_region { section .cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { readwrite }; +place at end of IRAM1_region { block HSTACK }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_app_signature, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x001D0000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_IAR/cyb06xxa_cm4_dual.icf b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xxa_cm4_dual.icf similarity index 94% rename from devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_IAR/cyb06xxa_cm4_dual.icf rename to devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xxa_cm4_dual.icf index e26b2b3..fef329b 100644 --- a/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_IAR/cyb06xxa_cm4_dual.icf +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xxa_cm4_dual.icf @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cyb06xxa_cm4_dual.icf -* \version 2.60 +* \version 2.70 * * Linker file for the IAR compiler. * @@ -47,17 +47,15 @@ define symbol __ICFEDIT_intvec_start__ = 0x00000000; /* The following symbols control RAM and flash memory allocation for the CM4 core. * You can change the memory allocation by editing RAM and Flash symbols. - * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. - * Using this memory region for other purposes will lead to unexpected behavior. * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf', - * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'. + * where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.icf'. */ /* RAM */ -define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; -define symbol __ICFEDIT_region_IRAM1_end__ = 0x080D8000; +define symbol __ICFEDIT_region_IRAM1_start__ = 0x08040000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x080EA000; /* Flash */ -define symbol __ICFEDIT_region_IROM1_start__ = 0x10000400; -define symbol __ICFEDIT_region_IROM1_end__ = 0x101D0000; +define symbol __ICFEDIT_region_IROM1_start__ = 0x10040000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x100E8000; /* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. @@ -127,6 +125,10 @@ if (!isdefinedsymbol(__HEAP_SIZE)) { } /**** End of ICF editor section. ###ICF###*/ +/* The size of the MCU boot header area at the start of FLASH */ +define symbol BOOT_HEADER_SIZE = 0x400; + + define memory mem with size = 4G; define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; @@ -152,7 +154,7 @@ do not initialize { section .noinit, section .intvec_ram }; /*-Placement-*/ /* Flash - Cortex-M4 application */ -place at start of IROM1_region { block RO }; +place at address (__ICFEDIT_region_IROM1_start__ + BOOT_HEADER_SIZE) { block RO }; /* Used for the digital signature of the secure application and the Bootloader SDK application. */ ".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; diff --git a/devices/bsp/COMPONENT_MTB/startup/TOOLCHAIN_IAR/startup_psoc6_01_cm4.s b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_01_cm4.s similarity index 99% rename from devices/bsp/COMPONENT_MTB/startup/TOOLCHAIN_IAR/startup_psoc6_01_cm4.s rename to devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_01_cm4.s index 2ce41f1..678f9c6 100644 --- a/devices/bsp/COMPONENT_MTB/startup/TOOLCHAIN_IAR/startup_psoc6_01_cm4.s +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_01_cm4.s @@ -50,6 +50,7 @@ EXTERN SystemInit EXTERN Cy_SystemInitFpuEnable EXTERN __iar_data_init3 + EXTERN __iar_dynamic_initialization PUBLIC __vector_table PUBLIC __vector_table_0x1c PUBLIC __Vectors @@ -319,13 +320,16 @@ intvec_copy STR r0, [r1] dsb - ; OS-specific low-level initialization - LDR R0, =cy_toolchain_init - BLX R0 - ; Initialize data sections LDR R0, =__iar_data_init3 BLX R0 + + ; OS-specific low-level initialization + LDR R0, =cy_toolchain_init + BLX R0 + + ; --manual_dynamic_initialization + BL __iar_dynamic_initialization LDR R0, =SystemInit BLX R0 diff --git a/devices/bsp/COMPONENT_MTB/startup/TOOLCHAIN_IAR/startup_psoc6_02_cm4.s b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.s similarity index 99% rename from devices/bsp/COMPONENT_MTB/startup/TOOLCHAIN_IAR/startup_psoc6_02_cm4.s rename to devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.s index 022f6a9..8f1e4a5 100644 --- a/devices/bsp/COMPONENT_MTB/startup/TOOLCHAIN_IAR/startup_psoc6_02_cm4.s +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.s @@ -50,6 +50,7 @@ EXTERN SystemInit EXTERN Cy_SystemInitFpuEnable EXTERN __iar_data_init3 + EXTERN __iar_dynamic_initialization PUBLIC __vector_table PUBLIC __vector_table_0x1c PUBLIC __Vectors @@ -340,13 +341,16 @@ intvec_copy STR r0, [r1] dsb - ; OS-specific low-level initialization - LDR R0, =cy_toolchain_init - BLX R0 - ; Initialize data sections LDR R0, =__iar_data_init3 BLX R0 + + ; OS-specific low-level initialization + LDR R0, =cy_toolchain_init + BLX R0 + + ; --manual_dynamic_initialization + BL __iar_dynamic_initialization LDR R0, =SystemInit BLX R0 diff --git a/devices/bsp/COMPONENT_MTB/startup/TOOLCHAIN_IAR/startup_psoc6_03_cm4.s b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_03_cm4.s similarity index 99% rename from devices/bsp/COMPONENT_MTB/startup/TOOLCHAIN_IAR/startup_psoc6_03_cm4.s rename to devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_03_cm4.s index 50717e1..1d212b8 100644 --- a/devices/bsp/COMPONENT_MTB/startup/TOOLCHAIN_IAR/startup_psoc6_03_cm4.s +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_03_cm4.s @@ -50,6 +50,7 @@ EXTERN SystemInit EXTERN Cy_SystemInitFpuEnable EXTERN __iar_data_init3 + EXTERN __iar_dynamic_initialization PUBLIC __vector_table PUBLIC __vector_table_0x1c PUBLIC __Vectors @@ -346,13 +347,16 @@ intvec_copy STR r0, [r1] dsb - ; OS-specific low-level initialization - LDR R0, =cy_toolchain_init - BLX R0 - ; Initialize data sections LDR R0, =__iar_data_init3 BLX R0 + + ; OS-specific low-level initialization + LDR R0, =cy_toolchain_init + BLX R0 + + ; --manual_dynamic_initialization + BL __iar_dynamic_initialization LDR R0, =SystemInit BLX R0 diff --git a/devices/bsp/COMPONENT_MBED/startup/system_psoc6_cm4.c b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/system_psoc6_cm4.c similarity index 63% rename from devices/bsp/COMPONENT_MBED/startup/system_psoc6_cm4.c rename to devices/templates/COMPONENT_MTB/COMPONENT_CM4/system_psoc6_cm4.c index 0a18f50..7800d6b 100644 --- a/devices/bsp/COMPONENT_MBED/startup/system_psoc6_cm4.c +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/system_psoc6_cm4.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file system_psoc6_cm4.c -* \version 2.60 +* \version 2.70 * * The device system-source file. * @@ -27,6 +27,7 @@ #include "cy_device.h" #include "cy_device_headers.h" #include "cy_syslib.h" +#include "cy_sysclk.h" #include "cy_wdt.h" #if !defined(CY_IPC_DEFAULT_CFG_DISABLE) @@ -50,24 +51,9 @@ /** Default PeriClk frequency in Hz */ #define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (4000000UL) -/** Default SlowClk system core frequency in Hz */ +/** Default FastClk system core frequency in Hz */ #define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (8000000UL) -/** IMO frequency in Hz */ -#define CY_CLK_IMO_FREQ_HZ (8000000UL) - -/** HVILO frequency in Hz */ -#define CY_CLK_HVILO_FREQ_HZ (32000UL) - -/** PILO frequency in Hz */ -#define CY_CLK_PILO_FREQ_HZ (32768UL) - -/** WCO frequency in Hz */ -#define CY_CLK_WCO_FREQ_HZ (32768UL) - -/** ALTLF frequency in Hz */ -#define CY_CLK_ALTLF_FREQ_HZ (32768UL) - /** * Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock, @@ -91,10 +77,8 @@ uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT; /** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */ uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; -/** Holds the Alternate high frequency clock in Hz. Updated by \ref SystemCoreClockUpdate(). */ -#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) - uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ; -#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */ +/** Holds the Alternate high frequency clock in Hz. Updated by \ref Cy_BLE_EcoConfigure(). */ +uint32_t cy_BleEcoClockFreqHz = 0UL; /* SCB->CPACR */ #define SCB_CPACR_CP10_CP11_ENABLE (0xFUL << 20u) @@ -110,6 +94,10 @@ uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; #define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u) #define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu) +/* IPC_STRUCT7->DATA configuration */ +#define CY_STARTUP_CM0_DP_STATE (0x2uL) +#define CY_STARTUP_IPC7_DP_OFFSET (0x28u) + /******************************************************************************* * SystemCoreClockUpdate (void) @@ -118,37 +106,14 @@ uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; /* Do not use these definitions directly in your application */ #define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u) #define CY_DELAY_1K_THRESHOLD (1000u) -#define CY_DELAY_1K_MINUS_1_THRESHOLD (CY_DELAY_1K_THRESHOLD - 1u) #define CY_DELAY_1M_THRESHOLD (1000000u) -#define CY_DELAY_1M_MINUS_1_THRESHOLD (CY_DELAY_1M_THRESHOLD - 1u) -uint32_t cy_delayFreqHz = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; -uint32_t cy_delayFreqKhz = (CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / - CY_DELAY_1K_THRESHOLD; +uint32_t cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD); -uint8_t cy_delayFreqMhz = (uint8_t)((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1M_MINUS_1_THRESHOLD) / - CY_DELAY_1M_THRESHOLD); +uint8_t cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1M_THRESHOLD); uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * - ((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD); - -#define CY_ROOT_PATH_SRC_IMO (0UL) -#define CY_ROOT_PATH_SRC_EXT (1UL) -#if (SRSS_ECO_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_ECO (2UL) -#endif /* (SRSS_ECO_PRESENT == 1U) */ -#if (SRSS_ALTHF_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_ALTHF (3UL) -#endif /* (SRSS_ALTHF_PRESENT == 1U) */ -#define CY_ROOT_PATH_SRC_DSI_MUX (4UL) -#define CY_ROOT_PATH_SRC_DSI_MUX_HVILO (16UL) -#define CY_ROOT_PATH_SRC_DSI_MUX_WCO (17UL) -#if (SRSS_ALTLF_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_DSI_MUX_ALTLF (18UL) -#endif /* (SRSS_ALTLF_PRESENT == 1U) */ -#if (SRSS_PILO_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_DSI_MUX_PILO (19UL) -#endif /* (SRSS_PILO_PRESENT == 1U) */ + CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD); /******************************************************************************* @@ -192,6 +157,17 @@ void SystemInit(void) Cy_SystemInit(); SystemCoreClockUpdate(); +#ifdef __CM0P_PRESENT + #if (__CM0P_PRESENT == 0) + /* Configure data register (as CM0p in deep sleep state) of IPC structure #7, reserved for the Deep-Sleep operations. */ + REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = (CY_STARTUP_CM0_DP_STATE << + CY_STARTUP_IPC7_DP_OFFSET); + + /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */ + REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL; + #endif /* (__CM0P_PRESENT == 0) */ +#endif /* __CM0P_PRESENT */ + #if !defined(CY_IPC_DEFAULT_CFG_DISABLE) #ifdef __CM0P_PRESENT @@ -250,10 +226,7 @@ void SystemInit(void) /* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm4 }; - if (cy_device->flashPipeRequired != 0u) - { - Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4); - } + Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4); #if defined(CY_DEVICE_PSOC6ABLE2) Cy_Flash_Init(); @@ -298,154 +271,19 @@ __WEAK void Cy_SystemInit(void) *******************************************************************************/ void SystemCoreClockUpdate (void) { - uint32_t srcFreqHz; - uint32_t pathFreqHz; - uint32_t fastClkDiv; - uint32_t periClkDiv; - uint32_t rootPath; - uint32_t srcClk; - - /* Get root path clock for the high-frequency clock # 0 */ - rootPath = _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_MUX, SRSS->CLK_ROOT_SELECT[0u]); - - /* Get source of the root path clock */ - srcClk = _FLD2VAL(SRSS_CLK_PATH_SELECT_PATH_MUX, SRSS->CLK_PATH_SELECT[rootPath]); + uint32 locHf0Clock = Cy_SysClk_ClkHfGetFrequency(0UL); - /* Get frequency of the source */ - switch (srcClk) + if (0UL != locHf0Clock) { - case CY_ROOT_PATH_SRC_IMO: - srcFreqHz = CY_CLK_IMO_FREQ_HZ; - break; - - case CY_ROOT_PATH_SRC_EXT: - srcFreqHz = CY_CLK_EXT_FREQ_HZ; - break; - - #if (SRSS_ECO_PRESENT == 1U) - case CY_ROOT_PATH_SRC_ECO: - srcFreqHz = CY_CLK_ECO_FREQ_HZ; - break; - #endif /* (SRSS_ECO_PRESENT == 1U) */ - -#if defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) - case CY_ROOT_PATH_SRC_ALTHF: - srcFreqHz = cy_BleEcoClockFreqHz; - break; -#endif /* defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) */ - - case CY_ROOT_PATH_SRC_DSI_MUX: - { - uint32_t dsi_src; - dsi_src = _FLD2VAL(SRSS_CLK_DSI_SELECT_DSI_MUX, SRSS->CLK_DSI_SELECT[rootPath]); - switch (dsi_src) - { - case CY_ROOT_PATH_SRC_DSI_MUX_HVILO: - srcFreqHz = CY_CLK_HVILO_FREQ_HZ; - break; - - case CY_ROOT_PATH_SRC_DSI_MUX_WCO: - srcFreqHz = CY_CLK_WCO_FREQ_HZ; - break; - - #if (SRSS_ALTLF_PRESENT == 1U) - case CY_ROOT_PATH_SRC_DSI_MUX_ALTLF: - srcFreqHz = CY_CLK_ALTLF_FREQ_HZ; - break; - #endif /* (SRSS_ALTLF_PRESENT == 1U) */ - - #if (SRSS_PILO_PRESENT == 1U) - case CY_ROOT_PATH_SRC_DSI_MUX_PILO: - srcFreqHz = CY_CLK_PILO_FREQ_HZ; - break; - #endif /* (SRSS_PILO_PRESENT == 1U) */ - - default: - srcFreqHz = CY_CLK_HVILO_FREQ_HZ; - break; - } + cy_Hfclk0FreqHz = locHf0Clock; + cy_PeriClkFreqHz = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkPeriGetDivider()); + SystemCoreClock = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkFastGetDivider()); + + /* Sets clock frequency for Delay API */ + cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1M_THRESHOLD); + cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1K_THRESHOLD); + cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz; } - break; - - default: - srcFreqHz = CY_CLK_EXT_FREQ_HZ; - break; - } - - if (rootPath == 0UL) - { - /* FLL */ - bool fllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_FLL_STATUS_LOCKED, SRSS->CLK_FLL_STATUS)); - bool fllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)); - bool fllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)) || - (1UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3))); - if ((fllOutputAuto && fllLocked) || fllOutputOutput) - { - uint32_t fllMult; - uint32_t refDiv; - uint32_t outputDiv; - - fllMult = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_MULT, SRSS->CLK_FLL_CONFIG); - refDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, SRSS->CLK_FLL_CONFIG2); - outputDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, SRSS->CLK_FLL_CONFIG) + 1UL; - - pathFreqHz = ((srcFreqHz / refDiv) * fllMult) / outputDiv; - } - else - { - pathFreqHz = srcFreqHz; - } - } - else if ((rootPath == 1UL) || (rootPath == 2UL)) - { - /* PLL */ - bool pllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_PLL_STATUS_LOCKED, SRSS->CLK_PLL_STATUS[rootPath - 1UL])); - bool pllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])); - bool pllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])) || - (1UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]))); - if ((pllOutputAuto && pllLocked) || pllOutputOutput) - { - uint32_t feedbackDiv; - uint32_t referenceDiv; - uint32_t outputDiv; - - feedbackDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); - referenceDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_REFERENCE_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); - outputDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_OUTPUT_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); - - pathFreqHz = ((srcFreqHz * feedbackDiv) / referenceDiv) / outputDiv; - - } - else - { - pathFreqHz = srcFreqHz; - } - } - else - { - /* Direct */ - pathFreqHz = srcFreqHz; - } - - /* Get frequency after hf_clk pre-divider */ - pathFreqHz = pathFreqHz >> _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_DIV, SRSS->CLK_ROOT_SELECT[0u]); - cy_Hfclk0FreqHz = pathFreqHz; - - /* Fast Clock Divider */ - fastClkDiv = 1u + _FLD2VAL(CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV, CPUSS->CM4_CLOCK_CTL); - - /* Peripheral Clock Divider */ - periClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV, CPUSS->CM0_CLOCK_CTL); - cy_PeriClkFreqHz = pathFreqHz / periClkDiv; - - pathFreqHz = pathFreqHz / fastClkDiv; - SystemCoreClock = pathFreqHz; - - /* Sets clock frequency for Delay API */ - cy_delayFreqHz = SystemCoreClock; - cy_delayFreqMhz = (uint8_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD); - cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD; - cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz; } diff --git a/devices/bsp/COMPONENT_MTB/startup/system_psoc6.h b/devices/templates/COMPONENT_MTB/system_psoc6.h similarity index 91% rename from devices/bsp/COMPONENT_MTB/startup/system_psoc6.h rename to devices/templates/COMPONENT_MTB/system_psoc6.h index f0276e3..9af8a90 100644 --- a/devices/bsp/COMPONENT_MTB/startup/system_psoc6.h +++ b/devices/templates/COMPONENT_MTB/system_psoc6.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file system_psoc6.h -* \version 2.60 +* \version 2.70 * * \brief Device system header file. * @@ -320,6 +320,28 @@ * Reason for Change * * +* 2.70 +* Updated \ref SystemCoreClockUpdate() implementation - The SysClk API is reused. +* Code optimization. +* +* +* Updated \ref SystemInit() implementation - The IPC7 structure is initialized for both cores. +* Provided support for SysPM driver updates. +* +* +* Updated the linker scripts. +* Reserved FLASH area for the MCU boot headers. +* +* +* Added System Pipe initialization for all devices. +* Improved PDL usability according to user experience. +* +* +* Removed redundant legacy macros: CY_CLK_EXT_FREQ_HZ, CY_CLK_ECO_FREQ_HZ and CY_CLK_ALTHF_FREQ_HZ. +* Use \ref Cy_SysClk_ExtClkSetFrequency, \ref Cy_SysClk_EcoConfigure and \ref Cy_BLE_EcoConfigure functions instead them. +* Defect fixing. +* +* * 2.60 * Updated linker scripts. * Provided support for new devices, updated usage of CM0p prebuilt image. @@ -439,12 +461,6 @@ extern "C" { #define CY_SYSTEM_CPU_CM0P 0UL #endif -#if defined (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) - #include "cyfitter.h" -#endif /* (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) */ - - - /******************************************************************************* * @@ -460,44 +476,6 @@ extern "C" { * \{ */ -#if defined (CYDEV_CLK_EXTCLK__HZ) - #define CY_CLK_EXT_FREQ_HZ (CYDEV_CLK_EXTCLK__HZ) -#else - /***************************************************************************//** - * External Clock Frequency (in Hz, [value]UL). If compiled within - * PSoC Creator and the clock is enabled in the DWR, the value from DWR used. - * Otherwise, edit the value below. - * (USER SETTING) - *******************************************************************************/ - #define CY_CLK_EXT_FREQ_HZ (24000000UL) /* <<< 24 MHz */ -#endif /* (CYDEV_CLK_EXTCLK__HZ) */ - - -#if defined (CYDEV_CLK_ECO__HZ) - #define CY_CLK_ECO_FREQ_HZ (CYDEV_CLK_ECO__HZ) -#else - /***************************************************************************//** - * \brief External crystal oscillator frequency (in Hz, [value]UL). If compiled - * within PSoC Creator and the clock is enabled in the DWR, the value from DWR - * used. - * (USER SETTING) - *******************************************************************************/ - #define CY_CLK_ECO_FREQ_HZ (24000000UL) /* <<< 24 MHz */ -#endif /* (CYDEV_CLK_ECO__HZ) */ - - -#if defined (CYDEV_CLK_ALTHF__HZ) - #define CY_CLK_ALTHF_FREQ_HZ (CYDEV_CLK_ALTHF__HZ) -#else - /***************************************************************************//** - * \brief Alternate high frequency (in Hz, [value]UL). If compiled within - * PSoC Creator and the clock is enabled in the DWR, the value from DWR used. - * Otherwise, edit the value below. - * (USER SETTING) - *******************************************************************************/ - #define CY_CLK_ALTHF_FREQ_HZ (32000000UL) /* <<< 32 MHz */ -#endif /* (CYDEV_CLK_ALTHF__HZ) */ - /***************************************************************************//** * \brief Start address of the Cortex-M4 application ([address]UL) @@ -585,7 +563,6 @@ void Cy_SysIpcPipeIsrCm4(void); extern void Cy_SystemInit(void); extern void Cy_SystemInitFpuEnable(void); -extern uint32_t cy_delayFreqHz; extern uint32_t cy_delayFreqKhz; extern uint8_t cy_delayFreqMhz; extern uint32_t cy_delay32kMs; @@ -638,11 +615,11 @@ extern uint32_t cy_delay32kMs; #define CY_SYS_CYPIPE_INTR_MASK ( CY_SYS_CYPIPE_CHAN_MASK_EP0 | CY_SYS_CYPIPE_CHAN_MASK_EP1 ) #define CY_SYS_CYPIPE_CONFIG_EP0 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ - | (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \ - | CY_IPC_CHAN_CYPIPE_EP0) + | (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \ + | CY_IPC_CHAN_CYPIPE_EP0) #define CY_SYS_CYPIPE_CONFIG_EP1 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ - | (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \ - | CY_IPC_CHAN_CYPIPE_EP1) + | (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \ + | CY_IPC_CHAN_CYPIPE_EP1) /******************************************************************************/ @@ -662,7 +639,7 @@ extern uint32_t cy_PeriClkFreqHz; /** \cond INTERNAL */ /******************************************************************************* -* Backward compatibility macro. The following code is DEPRECATED and must +* Backward compatibility macros. The following code is DEPRECATED and must * not be used in new projects *******************************************************************************/ @@ -671,6 +648,7 @@ extern uint32_t cy_PeriClkFreqHz; #define Cy_RestoreIRQ Cy_SysLib_ExitCriticalSection #define CY_SYS_INTR_CYPIPE_EP0 (CY_IPC_INTR_CYPIPE_EP0) #define CY_SYS_INTR_CYPIPE_EP1 (CY_IPC_INTR_CYPIPE_EP1) +#define cy_delayFreqHz (SystemCoreClock) /** \endcond */ diff --git a/docs/pdl_api_reference_manual/html/functions_c.html b/docs/pdl_api_reference_manual/html/functions_c.html index 76179b1..3e73544 100644 --- a/docs/pdl_api_reference_manual/html/functions_c.html +++ b/docs/pdl_api_reference_manual/html/functions_c.html @@ -330,6 +330,12 @@

- c -