From 0e38b78ef9ae3ce5db0563bdcde80a028c5fc38a Mon Sep 17 00:00:00 2001 From: gitlab-runner Date: Mon, 17 Feb 2020 04:50:08 -0600 Subject: [PATCH] Upload psoc6pdl 1.4.1.2240 --- README.md | 2 +- RELEASE.md | 53 +- devices/include/cy8c6245fni_s3d11.h | 15 +- devices/include/cy8c6245fni_s3d41.h | 15 +- devices/include/cy8c6245fni_s3d71.h | 15 +- devices/include/cy_device_headers.h | 8 +- devices/include/cyb0644abzi_s2d44.h | 6 +- devices/include/cys0644abzi_s2d44.h | 1329 + devices/include/gpio_psoc6_04_68_qfn.h | 1166 + devices/include/ip/cyip_ctbm_v2.h | 271 + devices/include/ip/cyip_efuse_data_psoc6_04.h | 250 + devices/include/ip/cyip_pass_v2.h | 342 + devices/include/ip/cyip_sar_v2.h | 563 + devices/include/ip/cyip_sflash.h | 62 +- devices/include/ip/cyip_tcpwm_v2.h | 272 + devices/include/ip/cyip_usbfs.h | 98 +- devices/include/psoc6_04_config.h | 2972 ++ devices/include/psoc6a256k.h | 1197 + devices/svd/psoc6_01.svd | 275 +- devices/svd/psoc6_02.svd | 520 +- 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drivers/source/cy_sysclk.c | 304 +- drivers/source/cy_syslib.c | 4 +- drivers/source/cy_syspm.c | 25 +- personalities/.cymigration | 2 +- .../peripheral/canfd-1.0.cypersonality | 11 +- .../connectivity_wifi-1.0.cypersonality | 6 +- .../peripheral/i2s-1.0.cypersonality | 12 +- .../peripheral/pdm_pcm-1.0.cypersonality | 12 +- .../peripheral/seglcd-1.1.cypersonality | 10 +- .../peripheral/smartio-1.0.cypersonality | 10 +- .../peripheral/smif-1.1.cypersonality | 28 +- personalities/platform/dma-1.0.cypersonality | 6 +- .../platform/sysclock-1.2.cypersonality | 1 + udd/001-91989.revision | 1 + udd/MXS40.revision | 1 + .../43012C0/CYW43012C0WKWBG/base/view.xml | 16 + .../43012C0/CYW43012C0WKWBG/info.xml | 6 + .../CYW43012C0WKWBG/studio/presentation | 2 + .../43012C0/CYW43012C0WKWBG/studio/view.xml | 23 + .../MXS40/PSoC6A256K/PSoC6A256K/base/view.xml | 16 + .../MXS40/PSoC6A256K/PSoC6A256K/info.xml | 6 + udd/devices/MXS40/PSoC6A256K/info.xml | 5 + .../PSoC6A2M/CYB0644ABZI-S2D44/base/view.xml | 4 +- .../CYB0644ABZI-S2D44/studio/view.xml | 2 +- .../PSoC6A2M/CYS0644ABZI-S2D44/base/view.xml | 16 + .../MXS40/PSoC6A2M/CYS0644ABZI-S2D44/info.xml | 6 + .../CYS0644ABZI-S2D44/studio/presentation | 2 + .../CYS0644ABZI-S2D44/studio/view.xml | 59 + .../MXS40/PSoC6A2M/studio/clocks.cysem | 2 +- .../CY8C6245FNI-S3D11/studio/view.xml | 2 +- .../CY8C6245FNI-S3D41/studio/view.xml | 2 +- .../CY8C6245FNI-S3D71/studio/view.xml | 2 +- .../MXS40/PSoC6A512K/studio/clocks.cysem | 2 +- .../MXS40/PSoC6ABLE2/studio/clocks.cysem | 18 +- .../MXS40/PSoC6ABLE2/studio/clocks.cyvis | 2 +- .../studio/connectivity/mxprofile_v1.cydata | Bin 531 -> 531 bytes .../connectivity/mxs40srss_v1-power.cydata | Bin 531 -> 0 bytes .../studio/connectivity/mxs40srss_v1.cydata | Bin 2221 -> 2295 bytes .../studio/connectivity/mxsdhc_v1.cydata | Bin 531 -> 531 bytes .../studio/connectivity/mxtcpwm_v1.cydata | Bin 1711 -> 1743 bytes udd/devices/MXS40/studio/features.mk | 33 +- udd/version.dat | 2 +- udd/version.xml | 2 +- version.xml | 2 +- 372 files changed, 67267 insertions(+), 3385 deletions(-) create mode 100644 devices/include/cys0644abzi_s2d44.h create mode 100644 devices/include/gpio_psoc6_04_68_qfn.h create mode 100644 devices/include/ip/cyip_ctbm_v2.h create mode 100644 devices/include/ip/cyip_efuse_data_psoc6_04.h create mode 100644 devices/include/ip/cyip_pass_v2.h create mode 100644 devices/include/ip/cyip_sar_v2.h create mode 100644 devices/include/ip/cyip_tcpwm_v2.h create mode 100644 devices/include/psoc6_04_config.h create mode 100644 devices/include/psoc6a256k.h create mode 100644 devices/svd/psoc6_04.svd create mode 100644 devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx4_cm0plus.sct create mode 100644 devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_04_cm0plus.S create mode 100644 devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx4_cm0plus.ld create mode 100644 devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_04_cm0plus.S create mode 100644 devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx4_cm0plus.icf create mode 100644 devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_04_cm0plus.S create mode 100644 devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx4_cm4_dual.sct create mode 100644 devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_04_cm4.S create mode 100644 devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx4_cm4_dual.ld create mode 100644 devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_04_cm4.S create mode 100644 devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx4_cm4_dual.icf create mode 100644 devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_04_cm4.S create mode 100644 devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx4_cm0plus.sct create mode 100644 devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_04_cm0plus.s create mode 100644 devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_A_Clang/startup_psoc6_04_cm0plus.S create mode 100644 devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx4_cm0plus.ld create mode 100644 devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_04_cm0plus.S create mode 100644 devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx4_cm0plus.icf create mode 100644 devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_04_cm0plus.s create mode 100644 devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx4_cm4_dual.sct create mode 100644 devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_04_cm4.s create mode 100644 devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx4_cm4_dual.mk create mode 100644 devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/startup_psoc6_04_cm4.S create mode 100644 devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx4_cm4_dual.ld create mode 100644 devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_04_cm4.S create mode 100644 devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx4_cm4_dual.icf create mode 100644 devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_04_cm4.s create mode 100644 docs/pdl_api_reference_manual/html/group__group__sysclk__alt__hf.html create mode 100644 docs/pdl_api_reference_manual/html/group__group__sysclk__alt__hf.js create mode 100644 docs/pdl_api_reference_manual/html/group__group__sysclk__alt__hf__funcs.html create mode 100644 docs/pdl_api_reference_manual/html/group__group__sysclk__alt__hf__funcs.js create mode 100644 docs/pdl_api_reference_manual/html/structcy__stc__smif__hybrid__region__info__t.html create mode 100644 udd/001-91989.revision create mode 100644 udd/MXS40.revision create mode 100644 udd/devices/Connectivity/43012C0/CYW43012C0WKWBG/base/view.xml create mode 100644 udd/devices/Connectivity/43012C0/CYW43012C0WKWBG/info.xml create mode 100644 udd/devices/Connectivity/43012C0/CYW43012C0WKWBG/studio/presentation create mode 100644 udd/devices/Connectivity/43012C0/CYW43012C0WKWBG/studio/view.xml create mode 100644 udd/devices/MXS40/PSoC6A256K/PSoC6A256K/base/view.xml create mode 100644 udd/devices/MXS40/PSoC6A256K/PSoC6A256K/info.xml create mode 100644 udd/devices/MXS40/PSoC6A256K/info.xml create mode 100644 udd/devices/MXS40/PSoC6A2M/CYS0644ABZI-S2D44/base/view.xml create mode 100644 udd/devices/MXS40/PSoC6A2M/CYS0644ABZI-S2D44/info.xml create mode 100644 udd/devices/MXS40/PSoC6A2M/CYS0644ABZI-S2D44/studio/presentation create mode 100644 udd/devices/MXS40/PSoC6A2M/CYS0644ABZI-S2D44/studio/view.xml delete mode 100644 udd/devices/MXS40/studio/connectivity/mxs40srss_v1-power.cydata diff --git a/README.md b/README.md index 5f18753..f5b45df 100644 --- a/README.md +++ b/README.md @@ -41,4 +41,4 @@ See the [PDL API Reference Manual Getting Started section](https://cypresssemico * [Cypress Semiconductor](http://www.cypress.com) --- -© Cypress Semiconductor Corporation, 2019. \ No newline at end of file +© Cypress Semiconductor Corporation, 2020. \ No newline at end of file diff --git a/RELEASE.md b/RELEASE.md index 246c6bd..1bb6397 100644 --- a/RELEASE.md +++ b/RELEASE.md @@ -1,37 +1,35 @@ -# PSoC 6 Peripheral Driver Library v1.4.0 +# PSoC 6 Peripheral Driver Library v1.4.1 Please refer to the [README.md](./README.md) and the [PDL API Reference Manual](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/index.html) for a complete description of the Peripheral Driver Library. ### New Features -* The structure of BSP startup templates directory (devices/templates) is updated to match the BSP layout. * The updated core-lib is reused - see [SysLib changelog](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__syslib.html) for details. -* Removed redundant legacy PSoC Creator-compatibility macros. -* The startup code reuses sysclk driver API - see [Startup changelog](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__system__config.html) for details. + Updated Personalities -* CSD -* Power -* SegLCD -* WiFi -Updated the configurators launch parameters in CSD and SegLCD personalities: switched from GUI to console applications for regenerating the source code without opening the configurator itself. This improves the user experience, performance, and enables using machines without a GUI. -The Power personality code generation is corrected due to the customer's request. -The TCP Keepalive Offload feature support is added to the WiFi Low Power Assistant (LPA) personality. +* CAN FD - Fix filter configuration issue. +* DMA - Fixed the Trigger Input parameter behaviour. +* WiFi - Update for LPA TCP keepalive offload. +* I2S - Fixed the IRQn generation for all supported devices. +* PDM-PCM - Fixed the IRQn generation for all supported devices. +* QSPI - Data terminals UI enhancement. +* SegLCD - Added the ability to route output signals to Smart I/O. +* Smart I/O - GUI improvement. +* SysClocks - Disable ILO in Hibernate. Updated Drivers -* [BLE_CLK 3.30](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__ble__clk.html) -* [SCB 2.40](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__system__scb.html) -* [Startup 2.70](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__system__config.html) -* [SysClk 1.50](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__sysclk.html) -* [SysLib 2.50](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__syslib.html) -* [SysPm 4.50](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__syspm.html) -* [WDT 1.20](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__wdt.html) +* [BLE_CLK 3.40](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__ble__clk.html) +* [CAN FD 1.10](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__canfd.html) +* [RTC 2.30](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__rtc.html) +* [SMIF 1.50](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__smif.html) +* [SysClk 1.60](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__sysclk.html) +* [SysPm 5.0](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__syspm.html) Drivers with patch version updates -* [Flash 3.30.3](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__flash.html) -* [SAR 1.20.2](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__sar.html) -* [SegLCD 1.0.1](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__seglcd.html) -* [SMIF 1.40.1](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__smif.html) -* [TrigMux 1.20.1](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__trigmux.html) +* [eFuse 1.10.2](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__efuse.html) +* [Flash 3.30.4](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__flash.html) +* [Prot 1.30.2](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__prot.html) +* [SysLib 2.50.1](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__syslib.html) ### Known Issues None @@ -44,11 +42,12 @@ This version of PDL was validated for compatibility with the following Software | Software and Tools | Version | | :--- | :---- | +| [Cypress Core Library](https://github.com/cypresssemiconductorco/core-lib) | 1.1.1 | +| [Cypress HAL](https://github.com/cypresssemiconductorco/psoc6hal) | 1.1.1 | | CMSIS-Core(M) | 5.2.1 | -| GCC Compiler | 7.2.1 | +| GCC Compiler | 9.2.1 | | IAR Compiler | 8.32 | -| ARM Compiler 6 | 6.11 | -| MBED OS | 5.13.1 | +| ARM Compiler 6 | 6.13 | | FreeRTOS | 10.0.1 | ### More information @@ -62,4 +61,4 @@ This version of PDL was validated for compatibility with the following Software * [Cypress Semiconductor](http://www.cypress.com) --- -© Cypress Semiconductor Corporation, 2019. \ No newline at end of file +© Cypress Semiconductor Corporation, 2020. \ No newline at end of file diff --git a/devices/include/cy8c6245fni_s3d11.h b/devices/include/cy8c6245fni_s3d11.h index da1cc41..e9ec4b4 100644 --- a/devices/include/cy8c6245fni_s3d11.h +++ b/devices/include/cy8c6245fni_s3d11.h @@ -5,7 +5,7 @@ * CY8C6245FNI-S3D11 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.5.1.36 * ******************************************************************************** * \copyright @@ -489,9 +489,6 @@ typedef enum { #define CY_IP_MXS40IOSS 1u #define CY_IP_MXS40IOSS_INSTANCES 1u #define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u @@ -1103,16 +1100,6 @@ typedef enum { #define LCD0_BASE 0x403B0000UL #define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ -/******************************************************************************* -* USBFS -*******************************************************************************/ - -#define USBFS0_BASE 0x403F0000UL -#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ -#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ -#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ -#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ - /******************************************************************************* * SMIF *******************************************************************************/ diff --git a/devices/include/cy8c6245fni_s3d41.h b/devices/include/cy8c6245fni_s3d41.h index 770c018..5b1fe6c 100644 --- a/devices/include/cy8c6245fni_s3d41.h +++ b/devices/include/cy8c6245fni_s3d41.h @@ -5,7 +5,7 @@ * CY8C6245FNI-S3D41 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.5.1.36 * ******************************************************************************** * \copyright @@ -492,9 +492,6 @@ typedef enum { #define CY_IP_MXS40IOSS 1u #define CY_IP_MXS40IOSS_INSTANCES 1u #define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u @@ -1113,16 +1110,6 @@ typedef enum { #define LCD0_BASE 0x403B0000UL #define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ -/******************************************************************************* -* USBFS -*******************************************************************************/ - -#define USBFS0_BASE 0x403F0000UL -#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ -#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ -#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ -#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ - /******************************************************************************* * SMIF *******************************************************************************/ diff --git a/devices/include/cy8c6245fni_s3d71.h b/devices/include/cy8c6245fni_s3d71.h index 4192d7b..0c7af9d 100644 --- a/devices/include/cy8c6245fni_s3d71.h +++ b/devices/include/cy8c6245fni_s3d71.h @@ -5,7 +5,7 @@ * CY8C6245FNI-S3D71 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.5.1.36 * ******************************************************************************** * \copyright @@ -492,9 +492,6 @@ typedef enum { #define CY_IP_MXS40IOSS 1u #define CY_IP_MXS40IOSS_INSTANCES 1u #define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u @@ -1113,16 +1110,6 @@ typedef enum { #define LCD0_BASE 0x403B0000UL #define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ -/******************************************************************************* -* USBFS -*******************************************************************************/ - -#define USBFS0_BASE 0x403F0000UL -#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ -#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ -#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ -#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ - /******************************************************************************* * SMIF *******************************************************************************/ diff --git a/devices/include/cy_device_headers.h b/devices/include/cy_device_headers.h index 4a0d2bd..8f1be62 100644 --- a/devices/include/cy_device_headers.h +++ b/devices/include/cy_device_headers.h @@ -5,11 +5,11 @@ * Common header file to be included by the drivers. * * \note -* Generator version: 1.5.0.1292 +* Generator version: 1.6.0.81 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -184,6 +184,8 @@ #include "cy8c624alqi_d42.h" #elif defined (CYB0644ABZI_S2D44) #include "cyb0644abzi_s2d44.h" +#elif defined (CYS0644ABZI_S2D44) + #include "cys0644abzi_s2d44.h" #elif defined (CY8C624ABZI_S2D44A0) #include "cy8c624abzi_s2d44a0.h" #elif defined (CY8C624ABZI_S2D44) @@ -236,6 +238,8 @@ #include "cy8c6245lqi_s3d02.h" #elif defined (CY8C6245W_S3D72) #include "cy8c6245w_s3d72.h" +#elif defined (PSoC6A256K) + #include "psoc6a256k.h" #else #include "cy_device_common.h" #endif diff --git a/devices/include/cyb0644abzi_s2d44.h b/devices/include/cyb0644abzi_s2d44.h index e5a3c7c..fae778f 100644 --- a/devices/include/cyb0644abzi_s2d44.h +++ b/devices/include/cyb0644abzi_s2d44.h @@ -5,11 +5,11 @@ * CYB0644ABZI-S2D44 device header * * \note -* Generator version: 1.5.0.1292 +* Generator version: 1.6.0.81 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -572,7 +572,7 @@ typedef enum { #include "gpio_psoc6_02_124_bga.h" #define CY_DEVICE_PSOC6A2M -#define CY_SILICON_ID 0xE4301102UL +#define CY_SILICON_ID 0xE4701202UL #define CY_HF_CLK_MAX_FREQ 150000000UL #define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL diff --git a/devices/include/cys0644abzi_s2d44.h b/devices/include/cys0644abzi_s2d44.h new file mode 100644 index 0000000..1894820 --- /dev/null +++ b/devices/include/cys0644abzi_s2d44.h @@ -0,0 +1,1329 @@ +/***************************************************************************//** +* \file cys0644abzi_s2d44.h +* +* \brief +* CYS0644ABZI-S2D44 device header +* +* \note +* Generator version: 1.6.0.81 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CYS0644ABZI_S2D44_H_ +#define _CYS0644ABZI_S2D44_H_ + +/** +* \addtogroup group_device CYS0644ABZI-S2D44 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + /* ARM Cortex-M0+ Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CYS0644ABZI-S2D44 User Interrupt Numbers */ + NvicMux0_IRQn = 0, /*!< 0 [DeepSleep] CPU User Interrupt #0 */ + NvicMux1_IRQn = 1, /*!< 1 [DeepSleep] CPU User Interrupt #1 */ + NvicMux2_IRQn = 2, /*!< 2 [DeepSleep] CPU User Interrupt #2 */ + NvicMux3_IRQn = 3, /*!< 3 [DeepSleep] CPU User Interrupt #3 */ + NvicMux4_IRQn = 4, /*!< 4 [DeepSleep] CPU User Interrupt #4 */ + NvicMux5_IRQn = 5, /*!< 5 [DeepSleep] CPU User Interrupt #5 */ + NvicMux6_IRQn = 6, /*!< 6 [DeepSleep] CPU User Interrupt #6 */ + NvicMux7_IRQn = 7, /*!< 7 [DeepSleep] CPU User Interrupt #7 */ + /* CYS0644ABZI-S2D44 Internal SW Interrupt Numbers */ + Internal0_IRQn = 8, /*!< 8 [Active] Internal SW Interrupt #0 */ + Internal1_IRQn = 9, /*!< 9 [Active] Internal SW Interrupt #1 */ + Internal2_IRQn = 10, /*!< 10 [Active] Internal SW Interrupt #2 */ + Internal3_IRQn = 11, /*!< 11 [Active] Internal SW Interrupt #3 */ + Internal4_IRQn = 12, /*!< 12 [Active] Internal SW Interrupt #4 */ + Internal5_IRQn = 13, /*!< 13 [Active] Internal SW Interrupt #5 */ + Internal6_IRQn = 14, /*!< 14 [Active] Internal SW Interrupt #6 */ + Internal7_IRQn = 15, /*!< 15 [Active] Internal SW Interrupt #7 */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#else + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CYS0644ABZI-S2D44 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #7 */ + scb_9_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #9 */ + scb_10_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #10 */ + scb_11_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #11 */ + scb_12_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #12 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dmac_2_IRQn = 54, /*!< 54 [Active] CPUSS DMAC, Channel #2 */ + cpuss_interrupts_dmac_3_IRQn = 55, /*!< 55 [Active] CPUSS DMAC, Channel #3 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 127, /*!< 127 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 128, /*!< 128 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 129, /*!< 129 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 130, /*!< 130 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 139, /*!< 139 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 140, /*!< 140 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 141, /*!< 141 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 142, /*!< 142 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 143, /*!< 143 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 144, /*!< 144 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 145, /*!< 145 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 146, /*!< 146 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 147, /*!< 147 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 148, /*!< 148 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 149, /*!< 149 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 150, /*!< 150 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 151, /*!< 151 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 152, /*!< 152 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 153, /*!< 153 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 154, /*!< 154 [Active] TCPWM #1, Counter #23 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + audioss_0_interrupt_i2s_IRQn = 156, /*!< 156 [Active] I2S0 Audio interrupt */ + audioss_0_interrupt_pdm_IRQn = 157, /*!< 157 [Active] PDM0/PCM0 Audio interrupt */ + audioss_1_interrupt_i2s_IRQn = 158, /*!< 158 [Active] I2S1 Audio interrupt */ + profile_interrupt_IRQn = 159, /*!< 159 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + sdhc_1_interrupt_wakeup_IRQn = 166, /*!< 166 [Active] EEMC wakeup interrupt for mxsdhc, not used */ + sdhc_1_interrupt_general_IRQn = 167, /*!< 167 [Active] Consolidated interrupt for mxsdhc for everything else */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#endif +} IRQn_Type; + + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* CYS0644ABZI-S2D44 interrupts that can be routed to the CM0+ NVIC */ +typedef enum { + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #7 */ + scb_9_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #9 */ + scb_10_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #10 */ + scb_11_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #11 */ + scb_12_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #12 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dmac_2_IRQn = 54, /*!< 54 [Active] CPUSS DMAC, Channel #2 */ + cpuss_interrupts_dmac_3_IRQn = 55, /*!< 55 [Active] CPUSS DMAC, Channel #3 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 127, /*!< 127 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 128, /*!< 128 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 129, /*!< 129 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 130, /*!< 130 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 139, /*!< 139 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 140, /*!< 140 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 141, /*!< 141 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 142, /*!< 142 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 143, /*!< 143 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 144, /*!< 144 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 145, /*!< 145 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 146, /*!< 146 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 147, /*!< 147 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 148, /*!< 148 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 149, /*!< 149 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 150, /*!< 150 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 151, /*!< 151 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 152, /*!< 152 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 153, /*!< 153 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 154, /*!< 154 [Active] TCPWM #1, Counter #23 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + audioss_0_interrupt_i2s_IRQn = 156, /*!< 156 [Active] I2S0 Audio interrupt */ + audioss_0_interrupt_pdm_IRQn = 157, /*!< 157 [Active] PDM0/PCM0 Audio interrupt */ + audioss_1_interrupt_i2s_IRQn = 158, /*!< 158 [Active] I2S1 Audio interrupt */ + profile_interrupt_IRQn = 159, /*!< 159 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + sdhc_1_interrupt_wakeup_IRQn = 166, /*!< 166 [Active] EEMC wakeup interrupt for mxsdhc, not used */ + sdhc_1_interrupt_general_IRQn = 167, /*!< 167 [Active] Consolidated interrupt for mxsdhc for everything else */ + disconnected_IRQn =1023 /*!< 1023 Disconnected */ +} cy_en_intr_t; + +#endif + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */ +#define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */ + +#else + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 1 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + +#endif + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00100000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x001D0000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCRYPTO 1u +#define CY_IP_MXCRYPTO_INSTANCES 1u +#define CY_IP_MXCRYPTO_VERSION 2u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPROFILE 1u +#define CY_IP_MXPROFILE_INSTANCES 1u +#define CY_IP_MXPROFILE_VERSION 1u + +#include "psoc6_02_config.h" +#include "gpio_psoc6_02_124_bga.h" + +#define CY_DEVICE_PSOC6A2M +#define CY_SILICON_ID 0xE4A01202UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_GR10 ((PERI_GR_Type*) &PERI->GR[10]) /* 0x40004140 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR10_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU6_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_DMAC_CH3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_PROFILE ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_SDHC1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ +#define PERI_MS_PPU_FX_SCB7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ +#define PERI_MS_PPU_FX_SCB8 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ +#define PERI_MS_PPU_FX_SCB9 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ +#define PERI_MS_PPU_FX_SCB10 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ +#define PERI_MS_PPU_FX_SCB11 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ +#define PERI_MS_PPU_FX_SCB12 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ +#define PERI_MS_PPU_FX_PDM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[226]) /* 0x40014080 */ +#define PERI_MS_PPU_FX_I2S0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[227]) /* 0x400140C0 */ +#define PERI_MS_PPU_FX_I2S1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[228]) /* 0x40014100 */ + +/******************************************************************************* +* CRYPTO +*******************************************************************************/ + +#define CRYPTO_BASE 0x40100000UL +#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40100000 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU6_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[0]) /* 0x40235A00 */ +#define PROT_MPU6_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[1]) /* 0x40235A20 */ +#define PROT_MPU6_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[2]) /* 0x40235A40 */ +#define PROT_MPU6_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[3]) /* 0x40235A60 */ +#define PROT_MPU6_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[4]) /* 0x40235A80 */ +#define PROT_MPU6_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[5]) /* 0x40235AA0 */ +#define PROT_MPU6_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[6]) /* 0x40235AC0 */ +#define PROT_MPU6_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[7]) /* 0x40235AE0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ +#define DMAC_CH2 ((DMAC_CH_Type*) &DMAC->CH[2]) /* 0x402A1200 */ +#define DMAC_CH3 ((DMAC_CH_Type*) &DMAC->CH[3]) /* 0x402A1300 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* PROFILE +*******************************************************************************/ + +#define PROFILE_BASE 0x402D0000UL +#define PROFILE ((PROFILE_Type*) PROFILE_BASE) /* 0x402D0000 */ +#define PROFILE_CNT_STRUCT0 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[0]) /* 0x402D0800 */ +#define PROFILE_CNT_STRUCT1 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[1]) /* 0x402D0810 */ +#define PROFILE_CNT_STRUCT2 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[2]) /* 0x402D0820 */ +#define PROFILE_CNT_STRUCT3 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[3]) /* 0x402D0830 */ +#define PROFILE_CNT_STRUCT4 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[4]) /* 0x402D0840 */ +#define PROFILE_CNT_STRUCT5 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[5]) /* 0x402D0850 */ +#define PROFILE_CNT_STRUCT6 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[6]) /* 0x402D0860 */ +#define PROFILE_CNT_STRUCT7 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[7]) /* 0x402D0870 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM0_CNT4 ((TCPWM_CNT_Type*) &TCPWM0->CNT[4]) /* 0x40380200 */ +#define TCPWM0_CNT5 ((TCPWM_CNT_Type*) &TCPWM0->CNT[5]) /* 0x40380240 */ +#define TCPWM0_CNT6 ((TCPWM_CNT_Type*) &TCPWM0->CNT[6]) /* 0x40380280 */ +#define TCPWM0_CNT7 ((TCPWM_CNT_Type*) &TCPWM0->CNT[7]) /* 0x403802C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ +#define TCPWM1_CNT8 ((TCPWM_CNT_Type*) &TCPWM1->CNT[8]) /* 0x40390300 */ +#define TCPWM1_CNT9 ((TCPWM_CNT_Type*) &TCPWM1->CNT[9]) /* 0x40390340 */ +#define TCPWM1_CNT10 ((TCPWM_CNT_Type*) &TCPWM1->CNT[10]) /* 0x40390380 */ +#define TCPWM1_CNT11 ((TCPWM_CNT_Type*) &TCPWM1->CNT[11]) /* 0x403903C0 */ +#define TCPWM1_CNT12 ((TCPWM_CNT_Type*) &TCPWM1->CNT[12]) /* 0x40390400 */ +#define TCPWM1_CNT13 ((TCPWM_CNT_Type*) &TCPWM1->CNT[13]) /* 0x40390440 */ +#define TCPWM1_CNT14 ((TCPWM_CNT_Type*) &TCPWM1->CNT[14]) /* 0x40390480 */ +#define TCPWM1_CNT15 ((TCPWM_CNT_Type*) &TCPWM1->CNT[15]) /* 0x403904C0 */ +#define TCPWM1_CNT16 ((TCPWM_CNT_Type*) &TCPWM1->CNT[16]) /* 0x40390500 */ +#define TCPWM1_CNT17 ((TCPWM_CNT_Type*) &TCPWM1->CNT[17]) /* 0x40390540 */ +#define TCPWM1_CNT18 ((TCPWM_CNT_Type*) &TCPWM1->CNT[18]) /* 0x40390580 */ +#define TCPWM1_CNT19 ((TCPWM_CNT_Type*) &TCPWM1->CNT[19]) /* 0x403905C0 */ +#define TCPWM1_CNT20 ((TCPWM_CNT_Type*) &TCPWM1->CNT[20]) /* 0x40390600 */ +#define TCPWM1_CNT21 ((TCPWM_CNT_Type*) &TCPWM1->CNT[21]) /* 0x40390640 */ +#define TCPWM1_CNT22 ((TCPWM_CNT_Type*) &TCPWM1->CNT[22]) /* 0x40390680 */ +#define TCPWM1_CNT23 ((TCPWM_CNT_Type*) &TCPWM1->CNT[23]) /* 0x403906C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ +#define SMIF0_DEVICE3 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[3]) /* 0x40420980 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC1_BASE 0x40470000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC1 ((SDHC_Type*) SDHC1_BASE) /* 0x40470000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC1_WRAP ((SDHC_WRAP_Type*) &SDHC1->WRAP) /* 0x40470000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ +#define SDHC1_CORE ((SDHC_CORE_Type*) &SDHC1->CORE) /* 0x40471000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB7_BASE 0x40670000UL +#define SCB8_BASE 0x40680000UL +#define SCB9_BASE 0x40690000UL +#define SCB10_BASE 0x406A0000UL +#define SCB11_BASE 0x406B0000UL +#define SCB12_BASE 0x406C0000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ +#define SCB7 ((CySCB_Type*) SCB7_BASE) /* 0x40670000 */ +#define SCB8 ((CySCB_Type*) SCB8_BASE) /* 0x40680000 */ +#define SCB9 ((CySCB_Type*) SCB9_BASE) /* 0x40690000 */ +#define SCB10 ((CySCB_Type*) SCB10_BASE) /* 0x406A0000 */ +#define SCB11 ((CySCB_Type*) SCB11_BASE) /* 0x406B0000 */ +#define SCB12 ((CySCB_Type*) SCB12_BASE) /* 0x406C0000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/******************************************************************************* +* PDM +*******************************************************************************/ + +#define PDM0_BASE 0x40A00000UL +#define PDM0 ((PDM_Type*) PDM0_BASE) /* 0x40A00000 */ + +/******************************************************************************* +* I2S +*******************************************************************************/ + +#define I2S0_BASE 0x40A10000UL +#define I2S1_BASE 0x40A11000UL +#define I2S0 ((I2S_Type*) I2S0_BASE) /* 0x40A10000 */ +#define I2S1 ((I2S_Type*) I2S1_BASE) /* 0x40A11000 */ + +/** \} CYS0644ABZI-S2D44 */ + +#endif /* _CYS0644ABZI_S2D44_H_ */ + + +/* [] END OF FILE */ diff --git a/devices/include/gpio_psoc6_04_68_qfn.h b/devices/include/gpio_psoc6_04_68_qfn.h new file mode 100644 index 0000000..fb586f7 --- /dev/null +++ b/devices/include/gpio_psoc6_04_68_qfn.h @@ -0,0 +1,1166 @@ +/***************************************************************************//** +* \file gpio_psoc6_04_68_qfn.h +* +* \brief +* PSoC6_04 device GPIO header for 68-QFN package +* +* \note +* Generator version: 1.5.1.36 +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _GPIO_PSOC6_04_68_QFN_H_ +#define _GPIO_PSOC6_04_68_QFN_H_ + +/* Package type */ +enum +{ + CY_GPIO_PACKAGE_QFN, + CY_GPIO_PACKAGE_BGA, + CY_GPIO_PACKAGE_CSP, + CY_GPIO_PACKAGE_WLCSP, + CY_GPIO_PACKAGE_LQFP, + CY_GPIO_PACKAGE_TQFP, + CY_GPIO_PACKAGE_SMT, +}; + +#define CY_GPIO_PACKAGE_TYPE CY_GPIO_PACKAGE_QFN +#define CY_GPIO_PIN_COUNT 68u + +/* AMUXBUS Segments */ +enum +{ + AMUXBUS_ANALOG_VDDD, + AMUXBUS_CSD0, + AMUXBUS_CSD1, + AMUXBUS_MAIN, + AMUXBUS_SAR, + AMUXBUS_VDDIO_1, + AMUXBUS_VSSA, + AMUXBUS_SRSS_AMUXBUSA_ADFT_VDDD, + AMUXBUS_SRSS_AMUXBUSB_ADFT_VDDD, +}; + +/* AMUX Splitter Controls */ +typedef enum +{ + AMUX_SPLIT_CTL_1 = 0x0001u, /* Left = AMUXBUS_VDDIO_1; Right = AMUXBUS_MAIN */ + AMUX_SPLIT_CTL_2 = 0x0002u, /* Left = AMUXBUS_CSD1; Right = AMUXBUS_CSD0 */ + AMUX_SPLIT_CTL_3 = 0x0003u, /* Left = AMUXBUS_SAR; Right = AMUXBUS_CSD1 */ + AMUX_SPLIT_CTL_5 = 0x0005u /* Left = AMUXBUS_SAR; Right = AMUXBUS_MAIN */ +} cy_en_amux_split_t; + +/* Port List */ +/* PORT 0 (GPIO) */ +#define P0_0_PORT GPIO_PRT0 +#define P0_0_PIN 0u +#define P0_0_NUM 0u +#define P0_1_PORT GPIO_PRT0 +#define P0_1_PIN 1u +#define P0_1_NUM 1u +#define P0_2_PORT GPIO_PRT0 +#define P0_2_PIN 2u +#define P0_2_NUM 2u +#define P0_3_PORT GPIO_PRT0 +#define P0_3_PIN 3u +#define P0_3_NUM 3u +#define P0_4_PORT GPIO_PRT0 +#define P0_4_PIN 4u +#define P0_4_NUM 4u +#define P0_5_PORT GPIO_PRT0 +#define P0_5_PIN 5u +#define P0_5_NUM 5u + +/* PORT 2 (GPIO) */ +#define P2_0_PORT GPIO_PRT2 +#define P2_0_PIN 0u +#define P2_0_NUM 0u +#define P2_1_PORT GPIO_PRT2 +#define P2_1_PIN 1u +#define P2_1_NUM 1u +#define P2_2_PORT GPIO_PRT2 +#define P2_2_PIN 2u +#define P2_2_NUM 2u +#define P2_3_PORT GPIO_PRT2 +#define P2_3_PIN 3u +#define P2_3_NUM 3u +#define P2_4_PORT GPIO_PRT2 +#define P2_4_PIN 4u +#define P2_4_NUM 4u +#define P2_5_PORT GPIO_PRT2 +#define P2_5_PIN 5u +#define P2_5_NUM 5u +#define P2_6_PORT GPIO_PRT2 +#define P2_6_PIN 6u +#define P2_6_NUM 6u +#define P2_7_PORT GPIO_PRT2 +#define P2_7_PIN 7u +#define P2_7_NUM 7u + +/* PORT 3 (GPIO_OVT) */ +#define P3_0_PORT GPIO_PRT3 +#define P3_0_PIN 0u +#define P3_0_NUM 0u +#define P3_0_AMUXSEGMENT AMUXBUS_VSSA +#define P3_1_PORT GPIO_PRT3 +#define P3_1_PIN 1u +#define P3_1_NUM 1u +#define P3_1_AMUXSEGMENT AMUXBUS_VSSA + +/* PORT 5 (GPIO) */ +#define P5_0_PORT GPIO_PRT5 +#define P5_0_PIN 0u +#define P5_0_NUM 0u +#define P5_1_PORT GPIO_PRT5 +#define P5_1_PIN 1u +#define P5_1_NUM 1u +#define P5_6_PORT GPIO_PRT5 +#define P5_6_PIN 6u +#define P5_6_NUM 6u +#define P5_7_PORT GPIO_PRT5 +#define P5_7_PIN 7u +#define P5_7_NUM 7u + +/* PORT 6 (GPIO) */ +#define P6_2_PORT GPIO_PRT6 +#define P6_2_PIN 2u +#define P6_2_NUM 2u +#define P6_3_PORT GPIO_PRT6 +#define P6_3_PIN 3u +#define P6_3_NUM 3u +#define P6_4_PORT GPIO_PRT6 +#define P6_4_PIN 4u +#define P6_4_NUM 4u +#define P6_5_PORT GPIO_PRT6 +#define P6_5_PIN 5u +#define P6_5_NUM 5u +#define P6_6_PORT GPIO_PRT6 +#define P6_6_PIN 6u +#define P6_6_NUM 6u +#define P6_7_PORT GPIO_PRT6 +#define P6_7_PIN 7u +#define P6_7_NUM 7u + +/* PORT 7 (GPIO) */ +#define P7_0_PORT GPIO_PRT7 +#define P7_0_PIN 0u +#define P7_0_NUM 0u +#define P7_0_AMUXSEGMENT AMUXBUS_CSD0 +#define P7_1_PORT GPIO_PRT7 +#define P7_1_PIN 1u +#define P7_1_NUM 1u +#define P7_1_AMUXSEGMENT AMUXBUS_CSD0 +#define P7_2_PORT GPIO_PRT7 +#define P7_2_PIN 2u +#define P7_2_NUM 2u +#define P7_2_AMUXSEGMENT AMUXBUS_CSD0 +#define P7_3_PORT GPIO_PRT7 +#define P7_3_PIN 3u +#define P7_3_NUM 3u +#define P7_3_AMUXSEGMENT AMUXBUS_CSD0 +#define P7_7_PORT GPIO_PRT7 +#define P7_7_PIN 7u +#define P7_7_NUM 7u +#define P7_7_AMUXSEGMENT AMUXBUS_CSD0 + +/* PORT 8 (GPIO) */ +#define P8_0_PORT GPIO_PRT8 +#define P8_0_PIN 0u +#define P8_0_NUM 0u +#define P8_0_AMUXSEGMENT AMUXBUS_CSD0 +#define P8_1_PORT GPIO_PRT8 +#define P8_1_PIN 1u +#define P8_1_NUM 1u +#define P8_1_AMUXSEGMENT AMUXBUS_CSD0 + +/* PORT 9 (GPIO) */ +#define P9_0_PORT GPIO_PRT9 +#define P9_0_PIN 0u +#define P9_0_NUM 0u +#define P9_0_AMUXSEGMENT AMUXBUS_SAR +#define P9_1_PORT GPIO_PRT9 +#define P9_1_PIN 1u +#define P9_1_NUM 1u +#define P9_1_AMUXSEGMENT AMUXBUS_SAR +#define P9_2_PORT GPIO_PRT9 +#define P9_2_PIN 2u +#define P9_2_NUM 2u +#define P9_2_AMUXSEGMENT AMUXBUS_SAR +#define P9_3_PORT GPIO_PRT9 +#define P9_3_PIN 3u +#define P9_3_NUM 3u +#define P9_3_AMUXSEGMENT AMUXBUS_SAR + +/* PORT 10 (GPIO) */ +#define P10_0_PORT GPIO_PRT10 +#define P10_0_PIN 0u +#define P10_0_NUM 0u +#define P10_0_AMUXSEGMENT AMUXBUS_SAR +#define P10_1_PORT GPIO_PRT10 +#define P10_1_PIN 1u +#define P10_1_NUM 1u +#define P10_1_AMUXSEGMENT AMUXBUS_SAR +#define P10_2_PORT GPIO_PRT10 +#define P10_2_PIN 2u +#define P10_2_NUM 2u +#define P10_2_AMUXSEGMENT AMUXBUS_SAR +#define P10_3_PORT GPIO_PRT10 +#define P10_3_PIN 3u +#define P10_3_NUM 3u +#define P10_3_AMUXSEGMENT AMUXBUS_SAR +#define P10_4_PORT GPIO_PRT10 +#define P10_4_PIN 4u +#define P10_4_NUM 4u +#define P10_4_AMUXSEGMENT AMUXBUS_SAR +#define P10_5_PORT GPIO_PRT10 +#define P10_5_PIN 5u +#define P10_5_NUM 5u +#define P10_5_AMUXSEGMENT AMUXBUS_SAR +#define P10_6_PORT GPIO_PRT10 +#define P10_6_PIN 6u +#define P10_6_NUM 6u +#define P10_6_AMUXSEGMENT AMUXBUS_SAR +#define P10_7_PORT GPIO_PRT10 +#define P10_7_PIN 7u +#define P10_7_NUM 7u +#define P10_7_AMUXSEGMENT AMUXBUS_SAR + +/* PORT 11 (GPIO) */ +#define P11_2_PORT GPIO_PRT11 +#define P11_2_PIN 2u +#define P11_2_NUM 2u +#define P11_3_PORT GPIO_PRT11 +#define P11_3_PIN 3u +#define P11_3_NUM 3u +#define P11_4_PORT GPIO_PRT11 +#define P11_4_PIN 4u +#define P11_4_NUM 4u +#define P11_5_PORT GPIO_PRT11 +#define P11_5_PIN 5u +#define P11_5_NUM 5u +#define P11_6_PORT GPIO_PRT11 +#define P11_6_PIN 6u +#define P11_6_NUM 6u +#define P11_7_PORT GPIO_PRT11 +#define P11_7_PIN 7u +#define P11_7_NUM 7u + +/* PORT 12 (GPIO) */ +#define P12_6_PORT GPIO_PRT12 +#define P12_6_PIN 6u +#define P12_6_NUM 6u +#define P12_7_PORT GPIO_PRT12 +#define P12_7_PIN 7u +#define P12_7_NUM 7u + +/* PORT 14 (AUX) */ +#define USBDP_PORT GPIO_PRT14 +#define USBDP_PIN 0u +#define USBDP_NUM 0u +#define USBDM_PORT GPIO_PRT14 +#define USBDM_PIN 1u +#define USBDM_NUM 1u + +/* Analog Connections */ +#define CSD_CMODPADD_PORT 7u +#define CSD_CMODPADD_PIN 1u +#define CSD_CMODPADS_PORT 7u +#define CSD_CMODPADS_PIN 1u +#define CSD_CSH_TANKPADD_PORT 7u +#define CSD_CSH_TANKPADD_PIN 2u +#define CSD_CSH_TANKPADS_PORT 7u +#define CSD_CSH_TANKPADS_PIN 2u +#define CSD_CSHIELDPADS_PORT 8u +#define CSD_CSHIELDPADS_PIN 1u +#define CSD_VREF_EXT_PORT 7u +#define CSD_VREF_EXT_PIN 3u +#define IOSS_ADFT0_NET_PORT 10u +#define IOSS_ADFT0_NET_PIN 0u +#define IOSS_ADFT1_NET_PORT 10u +#define IOSS_ADFT1_NET_PIN 1u +#define LPCOMP_INN_COMP0_PORT 5u +#define LPCOMP_INN_COMP0_PIN 7u +#define LPCOMP_INN_COMP1_PORT 6u +#define LPCOMP_INN_COMP1_PIN 3u +#define LPCOMP_INP_COMP0_PORT 5u +#define LPCOMP_INP_COMP0_PIN 6u +#define LPCOMP_INP_COMP1_PORT 6u +#define LPCOMP_INP_COMP1_PIN 2u +#define PASS_CTB_OA0_OUT_10X_PORT 9u +#define PASS_CTB_OA0_OUT_10X_PIN 2u +#define PASS_CTB_OA1_OUT_10X_PORT 9u +#define PASS_CTB_OA1_OUT_10X_PIN 3u +#define PASS_CTB_PADS0_PORT 9u +#define PASS_CTB_PADS0_PIN 0u +#define PASS_CTB_PADS1_PORT 9u +#define PASS_CTB_PADS1_PIN 1u +#define PASS_CTB_PADS2_PORT 9u +#define PASS_CTB_PADS2_PIN 2u +#define PASS_CTB_PADS3_PORT 9u +#define PASS_CTB_PADS3_PIN 3u +#define PASS_SARMUX_PADS0_PORT 10u +#define PASS_SARMUX_PADS0_PIN 0u +#define PASS_SARMUX_PADS1_PORT 10u +#define PASS_SARMUX_PADS1_PIN 1u +#define PASS_SARMUX_PADS10_PORT 10u +#define PASS_SARMUX_PADS10_PIN 2u +#define PASS_SARMUX_PADS11_PORT 10u +#define PASS_SARMUX_PADS11_PIN 3u +#define PASS_SARMUX_PADS12_PORT 10u +#define PASS_SARMUX_PADS12_PIN 4u +#define PASS_SARMUX_PADS13_PORT 10u +#define PASS_SARMUX_PADS13_PIN 5u +#define PASS_SARMUX_PADS14_PORT 10u +#define PASS_SARMUX_PADS14_PIN 6u +#define PASS_SARMUX_PADS15_PORT 10u +#define PASS_SARMUX_PADS15_PIN 7u +#define PASS_SARMUX_PADS2_PORT 10u +#define PASS_SARMUX_PADS2_PIN 2u +#define PASS_SARMUX_PADS3_PORT 10u +#define PASS_SARMUX_PADS3_PIN 3u +#define PASS_SARMUX_PADS4_PORT 10u +#define PASS_SARMUX_PADS4_PIN 4u +#define PASS_SARMUX_PADS5_PORT 10u +#define PASS_SARMUX_PADS5_PIN 5u +#define PASS_SARMUX_PADS6_PORT 10u +#define PASS_SARMUX_PADS6_PIN 6u +#define PASS_SARMUX_PADS7_PORT 10u +#define PASS_SARMUX_PADS7_PIN 7u +#define PASS_SARMUX_PADS8_PORT 10u +#define PASS_SARMUX_PADS8_PIN 0u +#define PASS_SARMUX_PADS9_PORT 10u +#define PASS_SARMUX_PADS9_PIN 1u +#define SRSS_ADFT_PIN0_PORT 10u +#define SRSS_ADFT_PIN0_PIN 0u +#define SRSS_ADFT_PIN1_PORT 10u +#define SRSS_ADFT_PIN1_PIN 1u +#define SRSS_ECO_IN_PORT 12u +#define SRSS_ECO_IN_PIN 6u +#define SRSS_ECO_OUT_PORT 12u +#define SRSS_ECO_OUT_PIN 7u +#define SRSS_WCO_IN_PORT 0u +#define SRSS_WCO_IN_PIN 0u +#define SRSS_WCO_OUT_PORT 0u +#define SRSS_WCO_OUT_PIN 1u + +/* HSIOM Connections */ +typedef enum +{ + /* Generic HSIOM connections */ + HSIOM_SEL_GPIO = 0, /* N/A */ + HSIOM_SEL_GPIO_DSI = 1, /* N/A */ + HSIOM_SEL_DSI_DSI = 2, /* N/A */ + HSIOM_SEL_DSI_GPIO = 3, /* N/A */ + HSIOM_SEL_AMUXA = 4, /* AMUXBUS A */ + HSIOM_SEL_AMUXB = 5, /* AMUXBUS B */ + HSIOM_SEL_AMUXA_DSI = 6, /* N/A */ + HSIOM_SEL_AMUXB_DSI = 7, /* N/A */ + HSIOM_SEL_ACT_0 = 8, /* Active peripherals 0 */ + HSIOM_SEL_ACT_1 = 9, /* Active peripherals 1 */ + HSIOM_SEL_ACT_2 = 10, /* Active peripherals 2 */ + HSIOM_SEL_ACT_3 = 11, /* Active peripherals 4 */ + HSIOM_SEL_DS_0 = 12, /* Deep Sleep peripherals 0 */ + HSIOM_SEL_DS_1 = 13, /* Deep Sleep peripherals 1 */ + HSIOM_SEL_DS_2 = 14, /* Deep Sleep peripherals 2 */ + HSIOM_SEL_DS_3 = 15, /* Deep Sleep peripherals 3 */ + HSIOM_SEL_ACT_4 = 16, /* Active peripherals 4 */ + HSIOM_SEL_ACT_5 = 17, /* Active peripherals 5 */ + HSIOM_SEL_ACT_6 = 18, /* Active peripherals 6 */ + HSIOM_SEL_ACT_7 = 19, /* Active peripherals 7 */ + HSIOM_SEL_ACT_8 = 20, /* Active peripherals 8 */ + HSIOM_SEL_ACT_9 = 21, /* Active peripherals 9 */ + HSIOM_SEL_ACT_10 = 22, /* Active peripherals 10 */ + HSIOM_SEL_ACT_11 = 23, /* Active peripherals 11 */ + HSIOM_SEL_ACT_12 = 24, /* Active peripherals 12 */ + HSIOM_SEL_ACT_13 = 25, /* Active peripherals 13 */ + HSIOM_SEL_ACT_14 = 26, /* Active peripherals 14 */ + HSIOM_SEL_ACT_15 = 27, /* Active peripherals 15 */ + HSIOM_SEL_DS_4 = 28, /* N/A */ + HSIOM_SEL_DS_5 = 29, /* N/A */ + HSIOM_SEL_DS_6 = 30, /* N/A */ + HSIOM_SEL_DS_7 = 31, /* N/A */ + + /* P0.0 */ + P0_0_GPIO = 0, /* N/A */ + P0_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:0 */ + P0_0_TCPWM0_LINE256 = 9, /* Digital Active - tcpwm[0].line[256]:0 */ + P0_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:0 */ + P0_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:0 */ + P0_0_LCD_COM0 = 12, /* Digital Deep Sleep - lcd.com[0]:0 */ + P0_0_LCD_SEG0 = 13, /* Digital Deep Sleep - lcd.seg[0]:0 */ + P0_0_SRSS_EXT_CLK = 16, /* Digital Active - srss.ext_clk:0 */ + P0_0_SCB0_SPI_SELECT1 = 20, /* Digital Active - scb[0].spi_select1:0 */ + P0_0_TCPWM0_TR_ONE_CNT_IN0 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[0]:0 */ + P0_0_PERI_TR_IO_INPUT0 = 24, /* Digital Active - peri.tr_io_input[0]:0 */ + + /* P0.1 */ + P0_1_GPIO = 0, /* N/A */ + P0_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:0 */ + P0_1_TCPWM0_LINE_COMPL256 = 9, /* Digital Active - tcpwm[0].line_compl[256]:0 */ + P0_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:1 */ + P0_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:1 */ + P0_1_LCD_COM1 = 12, /* Digital Deep Sleep - lcd.com[1]:0 */ + P0_1_LCD_SEG1 = 13, /* Digital Deep Sleep - lcd.seg[1]:0 */ + P0_1_SCB0_SPI_SELECT2 = 20, /* Digital Active - scb[0].spi_select2:0 */ + P0_1_TCPWM0_TR_ONE_CNT_IN1 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[1]:0 */ + P0_1_PERI_TR_IO_INPUT1 = 24, /* Digital Active - peri.tr_io_input[1]:0 */ + P0_1_CPUSS_SWJ_TRSTN = 29, /* Digital Deep Sleep - cpuss.swj_trstn */ + + /* P0.2 */ + P0_2_GPIO = 0, /* N/A */ + P0_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:0 */ + P0_2_TCPWM0_LINE257 = 9, /* Digital Active - tcpwm[0].line[257]:0 */ + P0_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:2 */ + P0_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:2 */ + P0_2_LCD_COM2 = 12, /* Digital Deep Sleep - lcd.com[2]:0 */ + P0_2_LCD_SEG2 = 13, /* Digital Deep Sleep - lcd.seg[2]:0 */ + P0_2_SCB0_UART_RX = 18, /* Digital Active - scb[0].uart_rx:0 */ + P0_2_SCB0_I2C_SCL = 19, /* Digital Active - scb[0].i2c_scl:0 */ + P0_2_SCB0_SPI_MOSI = 20, /* Digital Active - scb[0].spi_mosi:0 */ + P0_2_TCPWM0_TR_ONE_CNT_IN2 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[2]:0 */ + + /* P0.3 */ + P0_3_GPIO = 0, /* N/A */ + P0_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:0 */ + P0_3_TCPWM0_LINE_COMPL257 = 9, /* Digital Active - tcpwm[0].line_compl[257]:0 */ + P0_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:3 */ + P0_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:3 */ + P0_3_LCD_COM3 = 12, /* Digital Deep Sleep - lcd.com[3]:0 */ + P0_3_LCD_SEG3 = 13, /* Digital Deep Sleep - lcd.seg[3]:0 */ + P0_3_SCB0_UART_TX = 18, /* Digital Active - scb[0].uart_tx:0 */ + P0_3_SCB0_I2C_SDA = 19, /* Digital Active - scb[0].i2c_sda:0 */ + P0_3_SCB0_SPI_MISO = 20, /* Digital Active - scb[0].spi_miso:0 */ + P0_3_TCPWM0_TR_ONE_CNT_IN3 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[3]:0 */ + + /* P0.4 */ + P0_4_GPIO = 0, /* N/A */ + P0_4_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:0 */ + P0_4_TCPWM0_LINE258 = 9, /* Digital Active - tcpwm[0].line[258]:0 */ + P0_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:4 */ + P0_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:4 */ + P0_4_LCD_COM4 = 12, /* Digital Deep Sleep - lcd.com[4]:0 */ + P0_4_LCD_SEG4 = 13, /* Digital Deep Sleep - lcd.seg[4]:0 */ + P0_4_SCB0_UART_RTS = 18, /* Digital Active - scb[0].uart_rts:0 */ + P0_4_SCB0_SPI_CLK = 20, /* Digital Active - scb[0].spi_clk:0 */ + P0_4_TCPWM0_TR_ONE_CNT_IN256 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[256]:0 */ + P0_4_PERI_TR_IO_INPUT2 = 24, /* Digital Active - peri.tr_io_input[2]:0 */ + P0_4_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:2 */ + + /* P0.5 */ + P0_5_GPIO = 0, /* N/A */ + P0_5_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:0 */ + P0_5_TCPWM0_LINE_COMPL258 = 9, /* Digital Active - tcpwm[0].line_compl[258]:0 */ + P0_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:5 */ + P0_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:5 */ + P0_5_LCD_COM5 = 12, /* Digital Deep Sleep - lcd.com[5]:0 */ + P0_5_LCD_SEG5 = 13, /* Digital Deep Sleep - lcd.seg[5]:0 */ + P0_5_SRSS_EXT_CLK = 16, /* Digital Active - srss.ext_clk:1 */ + P0_5_SCB0_UART_CTS = 18, /* Digital Active - scb[0].uart_cts:0 */ + P0_5_SCB0_SPI_SELECT0 = 20, /* Digital Active - scb[0].spi_select0:0 */ + P0_5_TCPWM0_TR_ONE_CNT_IN257 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[257]:0 */ + P0_5_PERI_TR_IO_INPUT3 = 24, /* Digital Active - peri.tr_io_input[3]:0 */ + P0_5_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:2 */ + + /* USBDM */ + USBDM_GPIO = 0, /* N/A */ + + /* USBDP */ + USBDP_GPIO = 0, /* N/A */ + + /* P2.0 */ + P2_0_GPIO = 0, /* N/A */ + P2_0_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:0 */ + P2_0_TCPWM0_LINE259 = 9, /* Digital Active - tcpwm[0].line[259]:0 */ + P2_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:9 */ + P2_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:9 */ + P2_0_LCD_COM6 = 12, /* Digital Deep Sleep - lcd.com[6]:0 */ + P2_0_LCD_SEG6 = 13, /* Digital Deep Sleep - lcd.seg[6]:0 */ + P2_0_SCB1_UART_RX = 18, /* Digital Active - scb[1].uart_rx:1 */ + P2_0_SCB1_I2C_SCL = 19, /* Digital Active - scb[1].i2c_scl:1 */ + P2_0_SCB1_SPI_MOSI = 20, /* Digital Active - scb[1].spi_mosi:1 */ + P2_0_TCPWM0_TR_ONE_CNT_IN261 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[261]:0 */ + P2_0_PERI_TR_IO_INPUT4 = 24, /* Digital Active - peri.tr_io_input[4]:0 */ + + /* P2.1 */ + P2_1_GPIO = 0, /* N/A */ + P2_1_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:0 */ + P2_1_TCPWM0_LINE_COMPL259 = 9, /* Digital Active - tcpwm[0].line_compl[259]:0 */ + P2_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:10 */ + P2_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:10 */ + P2_1_LCD_COM7 = 12, /* Digital Deep Sleep - lcd.com[7]:0 */ + P2_1_LCD_SEG7 = 13, /* Digital Deep Sleep - lcd.seg[7]:0 */ + P2_1_SCB1_UART_TX = 18, /* Digital Active - scb[1].uart_tx:1 */ + P2_1_SCB1_I2C_SDA = 19, /* Digital Active - scb[1].i2c_sda:1 */ + P2_1_SCB1_SPI_MISO = 20, /* Digital Active - scb[1].spi_miso:1 */ + P2_1_TCPWM0_TR_ONE_CNT_IN262 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[262]:0 */ + P2_1_PERI_TR_IO_INPUT5 = 24, /* Digital Active - peri.tr_io_input[5]:0 */ + + /* P2.2 */ + P2_2_GPIO = 0, /* N/A */ + P2_2_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:1 */ + P2_2_TCPWM0_LINE260 = 9, /* Digital Active - tcpwm[0].line[260]:0 */ + P2_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:11 */ + P2_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:11 */ + P2_2_LCD_COM8 = 12, /* Digital Deep Sleep - lcd.com[8]:0 */ + P2_2_LCD_SEG8 = 13, /* Digital Deep Sleep - lcd.seg[8]:0 */ + P2_2_SCB1_UART_RTS = 18, /* Digital Active - scb[1].uart_rts:1 */ + P2_2_SCB1_SPI_CLK = 20, /* Digital Active - scb[1].spi_clk:1 */ + P2_2_TCPWM0_TR_ONE_CNT_IN263 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[263]:0 */ + + /* P2.3 */ + P2_3_GPIO = 0, /* N/A */ + P2_3_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:1 */ + P2_3_TCPWM0_LINE_COMPL260 = 9, /* Digital Active - tcpwm[0].line_compl[260]:0 */ + P2_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:12 */ + P2_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:12 */ + P2_3_LCD_COM9 = 12, /* Digital Deep Sleep - lcd.com[9]:0 */ + P2_3_LCD_SEG9 = 13, /* Digital Deep Sleep - lcd.seg[9]:0 */ + P2_3_SCB1_UART_CTS = 18, /* Digital Active - scb[1].uart_cts:1 */ + P2_3_SCB1_SPI_SELECT0 = 20, /* Digital Active - scb[1].spi_select0:1 */ + P2_3_TCPWM0_TR_ONE_CNT_IN0 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[0]:1 */ + + /* P2.4 */ + P2_4_GPIO = 0, /* N/A */ + P2_4_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:1 */ + P2_4_TCPWM0_LINE261 = 9, /* Digital Active - tcpwm[0].line[261]:0 */ + P2_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:13 */ + P2_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:13 */ + P2_4_LCD_COM10 = 12, /* Digital Deep Sleep - lcd.com[10]:0 */ + P2_4_LCD_SEG10 = 13, /* Digital Deep Sleep - lcd.seg[10]:0 */ + P2_4_SCB1_SPI_SELECT1 = 20, /* Digital Active - scb[1].spi_select1:1 */ + P2_4_TCPWM0_TR_ONE_CNT_IN1 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[1]:1 */ + + /* P2.5 */ + P2_5_GPIO = 0, /* N/A */ + P2_5_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:1 */ + P2_5_TCPWM0_LINE_COMPL261 = 9, /* Digital Active - tcpwm[0].line_compl[261]:0 */ + P2_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:14 */ + P2_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:14 */ + P2_5_LCD_COM11 = 12, /* Digital Deep Sleep - lcd.com[11]:0 */ + P2_5_LCD_SEG11 = 13, /* Digital Deep Sleep - lcd.seg[11]:0 */ + P2_5_SCB1_SPI_SELECT2 = 20, /* Digital Active - scb[1].spi_select2:1 */ + P2_5_TCPWM0_TR_ONE_CNT_IN2 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[2]:1 */ + + /* P2.6 */ + P2_6_GPIO = 0, /* N/A */ + P2_6_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:1 */ + P2_6_TCPWM0_LINE262 = 9, /* Digital Active - tcpwm[0].line[262]:0 */ + P2_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:15 */ + P2_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:15 */ + P2_6_LCD_COM12 = 12, /* Digital Deep Sleep - lcd.com[12]:0 */ + P2_6_LCD_SEG12 = 13, /* Digital Deep Sleep - lcd.seg[12]:0 */ + P2_6_LPCOMP_DSI_COMP0 = 15, /* Digital Deep Sleep - lpcomp.dsi_comp0:0 */ + P2_6_SCB1_SPI_SELECT3 = 20, /* Digital Active - scb[1].spi_select3:1 */ + P2_6_TCPWM0_TR_ONE_CNT_IN3 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[3]:1 */ + P2_6_PERI_TR_IO_INPUT8 = 24, /* Digital Active - peri.tr_io_input[8]:0 */ + + /* P2.7 */ + P2_7_GPIO = 0, /* N/A */ + P2_7_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:1 */ + P2_7_TCPWM0_LINE_COMPL262 = 9, /* Digital Active - tcpwm[0].line_compl[262]:0 */ + P2_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:16 */ + P2_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:16 */ + P2_7_LCD_COM13 = 12, /* Digital Deep Sleep - lcd.com[13]:0 */ + P2_7_LCD_SEG13 = 13, /* Digital Deep Sleep - lcd.seg[13]:0 */ + P2_7_LPCOMP_DSI_COMP1 = 15, /* Digital Deep Sleep - lpcomp.dsi_comp1:0 */ + P2_7_TCPWM0_TR_ONE_CNT_IN256 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[256]:1 */ + P2_7_PERI_TR_IO_INPUT9 = 24, /* Digital Active - peri.tr_io_input[9]:0 */ + + /* P3.0 */ + P3_0_GPIO = 0, /* N/A */ + P3_0_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:1 */ + P3_0_TCPWM0_LINE263 = 9, /* Digital Active - tcpwm[0].line[263]:0 */ + P3_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:17 */ + P3_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:17 */ + P3_0_LCD_COM14 = 12, /* Digital Deep Sleep - lcd.com[14]:0 */ + P3_0_LCD_SEG14 = 13, /* Digital Deep Sleep - lcd.seg[14]:0 */ + P3_0_SCB2_UART_RX = 18, /* Digital Active - scb[2].uart_rx:1 */ + P3_0_SCB2_I2C_SCL = 19, /* Digital Active - scb[2].i2c_scl:1 */ + P3_0_TCPWM0_TR_ONE_CNT_IN257 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[257]:1 */ + P3_0_PERI_TR_IO_INPUT6 = 24, /* Digital Active - peri.tr_io_input[6]:0 */ + + /* P3.1 */ + P3_1_GPIO = 0, /* N/A */ + P3_1_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:1 */ + P3_1_TCPWM0_LINE_COMPL263 = 9, /* Digital Active - tcpwm[0].line_compl[263]:0 */ + P3_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:18 */ + P3_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:18 */ + P3_1_LCD_COM15 = 12, /* Digital Deep Sleep - lcd.com[15]:0 */ + P3_1_LCD_SEG15 = 13, /* Digital Deep Sleep - lcd.seg[15]:0 */ + P3_1_SCB2_UART_TX = 18, /* Digital Active - scb[2].uart_tx:1 */ + P3_1_SCB2_I2C_SDA = 19, /* Digital Active - scb[2].i2c_sda:1 */ + P3_1_TCPWM0_TR_ONE_CNT_IN258 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[258]:1 */ + P3_1_PERI_TR_IO_INPUT7 = 24, /* Digital Active - peri.tr_io_input[7]:0 */ + + /* P5.0 */ + P5_0_GPIO = 0, /* N/A */ + P5_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:2 */ + P5_0_TCPWM0_LINE256 = 9, /* Digital Active - tcpwm[0].line[256]:1 */ + P5_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:19 */ + P5_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:19 */ + P5_0_LCD_COM16 = 12, /* Digital Deep Sleep - lcd.com[16]:0 */ + P5_0_LCD_SEG16 = 13, /* Digital Deep Sleep - lcd.seg[16]:0 */ + P5_0_SCB5_UART_RX = 18, /* Digital Active - scb[5].uart_rx:0 */ + P5_0_SCB5_I2C_SCL = 19, /* Digital Active - scb[5].i2c_scl:0 */ + P5_0_SCB5_SPI_MOSI = 20, /* Digital Active - scb[5].spi_mosi:0 */ + P5_0_CANFD0_TTCAN_RX0 = 22, /* Digital Active - canfd[0].ttcan_rx[0] */ + P5_0_TCPWM0_TR_ONE_CNT_IN259 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[259]:1 */ + P5_0_PERI_TR_IO_INPUT10 = 24, /* Digital Active - peri.tr_io_input[10]:0 */ + + /* P5.1 */ + P5_1_GPIO = 0, /* N/A */ + P5_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:2 */ + P5_1_TCPWM0_LINE_COMPL256 = 9, /* Digital Active - tcpwm[0].line_compl[256]:1 */ + P5_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:20 */ + P5_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:20 */ + P5_1_LCD_COM17 = 12, /* Digital Deep Sleep - lcd.com[17]:0 */ + P5_1_LCD_SEG17 = 13, /* Digital Deep Sleep - lcd.seg[17]:0 */ + P5_1_SCB5_UART_TX = 18, /* Digital Active - scb[5].uart_tx:0 */ + P5_1_SCB5_I2C_SDA = 19, /* Digital Active - scb[5].i2c_sda:0 */ + P5_1_SCB5_SPI_MISO = 20, /* Digital Active - scb[5].spi_miso:0 */ + P5_1_CANFD0_TTCAN_TX0 = 22, /* Digital Active - canfd[0].ttcan_tx[0] */ + P5_1_TCPWM0_TR_ONE_CNT_IN260 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[260]:1 */ + P5_1_PERI_TR_IO_INPUT11 = 24, /* Digital Active - peri.tr_io_input[11]:0 */ + + /* P5.6 */ + P5_6_GPIO = 0, /* N/A */ + P5_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:2 */ + P5_6_TCPWM0_LINE257 = 9, /* Digital Active - tcpwm[0].line[257]:1 */ + P5_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:22 */ + P5_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:22 */ + P5_6_LCD_COM18 = 12, /* Digital Deep Sleep - lcd.com[18]:0 */ + P5_6_LCD_SEG18 = 13, /* Digital Deep Sleep - lcd.seg[18]:0 */ + P5_6_TCPWM0_TR_ONE_CNT_IN262 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[262]:1 */ + + /* P5.7 */ + P5_7_GPIO = 0, /* N/A */ + P5_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:2 */ + P5_7_TCPWM0_LINE_COMPL257 = 9, /* Digital Active - tcpwm[0].line_compl[257]:1 */ + P5_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:23 */ + P5_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:23 */ + P5_7_LCD_COM19 = 12, /* Digital Deep Sleep - lcd.com[19]:0 */ + P5_7_LCD_SEG19 = 13, /* Digital Deep Sleep - lcd.seg[19]:0 */ + P5_7_TCPWM0_TR_ONE_CNT_IN263 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[263]:1 */ + + /* P6.2 */ + P6_2_GPIO = 0, /* N/A */ + P6_2_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:2 */ + P6_2_TCPWM0_LINE259 = 9, /* Digital Active - tcpwm[0].line[259]:1 */ + P6_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:24 */ + P6_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:24 */ + P6_2_LCD_COM22 = 12, /* Digital Deep Sleep - lcd.com[22]:0 */ + P6_2_LCD_SEG22 = 13, /* Digital Deep Sleep - lcd.seg[22]:0 */ + P6_2_TCPWM0_TR_ONE_CNT_IN0 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[0]:2 */ + P6_2_CPUSS_FAULT_OUT0 = 25, /* Digital Active - cpuss.fault_out[0] */ + + /* P6.3 */ + P6_3_GPIO = 0, /* N/A */ + P6_3_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:2 */ + P6_3_TCPWM0_LINE_COMPL259 = 9, /* Digital Active - tcpwm[0].line_compl[259]:1 */ + P6_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:25 */ + P6_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:25 */ + P6_3_LCD_COM23 = 12, /* Digital Deep Sleep - lcd.com[23]:0 */ + P6_3_LCD_SEG23 = 13, /* Digital Deep Sleep - lcd.seg[23]:0 */ + P6_3_TCPWM0_TR_ONE_CNT_IN1 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[1]:2 */ + P6_3_CPUSS_FAULT_OUT1 = 25, /* Digital Active - cpuss.fault_out[1] */ + + /* P6.4 */ + P6_4_GPIO = 0, /* N/A */ + P6_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:3 */ + P6_4_TCPWM0_LINE260 = 9, /* Digital Active - tcpwm[0].line[260]:1 */ + P6_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:26 */ + P6_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:26 */ + P6_4_LCD_COM24 = 12, /* Digital Deep Sleep - lcd.com[24]:0 */ + P6_4_LCD_SEG24 = 13, /* Digital Deep Sleep - lcd.seg[24]:0 */ + P6_4_SCB6_I2C_SCL = 14, /* Digital Deep Sleep - scb[6].i2c_scl:0 */ + P6_4_TCPWM0_TR_ONE_CNT_IN2 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[2]:2 */ + P6_4_PERI_TR_IO_INPUT12 = 24, /* Digital Active - peri.tr_io_input[12]:0 */ + P6_4_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:1 */ + P6_4_CPUSS_SWJ_SWO_TDO = 29, /* Digital Deep Sleep - cpuss.swj_swo_tdo */ + P6_4_SCB6_SPI_MOSI = 30, /* Digital Deep Sleep - scb[6].spi_mosi:0 */ + P6_4_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:0 */ + + /* P6.5 */ + P6_5_GPIO = 0, /* N/A */ + P6_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:3 */ + P6_5_TCPWM0_LINE_COMPL260 = 9, /* Digital Active - tcpwm[0].line_compl[260]:1 */ + P6_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:27 */ + P6_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:27 */ + P6_5_LCD_COM25 = 12, /* Digital Deep Sleep - lcd.com[25]:0 */ + P6_5_LCD_SEG25 = 13, /* Digital Deep Sleep - lcd.seg[25]:0 */ + P6_5_SCB6_I2C_SDA = 14, /* Digital Deep Sleep - scb[6].i2c_sda:0 */ + P6_5_TCPWM0_TR_ONE_CNT_IN3 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[3]:2 */ + P6_5_PERI_TR_IO_INPUT13 = 24, /* Digital Active - peri.tr_io_input[13]:0 */ + P6_5_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:1 */ + P6_5_CPUSS_SWJ_SWDOE_TDI = 29, /* Digital Deep Sleep - cpuss.swj_swdoe_tdi */ + P6_5_SCB6_SPI_MISO = 30, /* Digital Deep Sleep - scb[6].spi_miso:0 */ + P6_5_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:0 */ + + /* P6.6 */ + P6_6_GPIO = 0, /* N/A */ + P6_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:3 */ + P6_6_TCPWM0_LINE261 = 9, /* Digital Active - tcpwm[0].line[261]:1 */ + P6_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:28 */ + P6_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:28 */ + P6_6_LCD_COM26 = 12, /* Digital Deep Sleep - lcd.com[26]:0 */ + P6_6_LCD_SEG26 = 13, /* Digital Deep Sleep - lcd.seg[26]:0 */ + P6_6_TCPWM0_TR_ONE_CNT_IN256 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[256]:2 */ + P6_6_CPUSS_SWJ_SWDIO_TMS = 29, /* Digital Deep Sleep - cpuss.swj_swdio_tms */ + P6_6_SCB6_SPI_CLK = 30, /* Digital Deep Sleep - scb[6].spi_clk:0 */ + + /* P6.7 */ + P6_7_GPIO = 0, /* N/A */ + P6_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:3 */ + P6_7_TCPWM0_LINE_COMPL261 = 9, /* Digital Active - tcpwm[0].line_compl[261]:1 */ + P6_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:29 */ + P6_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:29 */ + P6_7_LCD_COM27 = 12, /* Digital Deep Sleep - lcd.com[27]:0 */ + P6_7_LCD_SEG27 = 13, /* Digital Deep Sleep - lcd.seg[27]:0 */ + P6_7_TCPWM0_TR_ONE_CNT_IN257 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[257]:2 */ + P6_7_CPUSS_SWJ_SWCLK_TCLK = 29, /* Digital Deep Sleep - cpuss.swj_swclk_tclk */ + P6_7_SCB6_SPI_SELECT0 = 30, /* Digital Deep Sleep - scb[6].spi_select0:0 */ + + /* P7.0 */ + P7_0_GPIO = 0, /* N/A */ + P7_0_AMUXA = 4, /* AMUXBUS A */ + P7_0_AMUXB = 5, /* AMUXBUS B */ + P7_0_AMUXA_DSI = 6, /* N/A */ + P7_0_AMUXB_DSI = 7, /* N/A */ + P7_0_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:2 */ + P7_0_TCPWM0_LINE262 = 9, /* Digital Active - tcpwm[0].line[262]:1 */ + P7_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:30 */ + P7_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:30 */ + P7_0_LCD_COM28 = 12, /* Digital Deep Sleep - lcd.com[28]:0 */ + P7_0_LCD_SEG28 = 13, /* Digital Deep Sleep - lcd.seg[28]:0 */ + P7_0_SCB4_UART_RX = 18, /* Digital Active - scb[4].uart_rx:0 */ + P7_0_SCB4_I2C_SCL = 19, /* Digital Active - scb[4].i2c_scl:0 */ + P7_0_SCB4_SPI_MOSI = 20, /* Digital Active - scb[4].spi_mosi:0 */ + P7_0_TCPWM0_TR_ONE_CNT_IN258 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[258]:2 */ + P7_0_PERI_TR_IO_INPUT14 = 24, /* Digital Active - peri.tr_io_input[14]:0 */ + P7_0_CPUSS_TRACE_CLOCK = 26, /* Digital Active - cpuss.trace_clock */ + + /* P7.1 */ + P7_1_GPIO = 0, /* N/A */ + P7_1_AMUXA = 4, /* AMUXBUS A */ + P7_1_AMUXB = 5, /* AMUXBUS B */ + P7_1_AMUXA_DSI = 6, /* N/A */ + P7_1_AMUXB_DSI = 7, /* N/A */ + P7_1_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:2 */ + P7_1_TCPWM0_LINE_COMPL262 = 9, /* Digital Active - tcpwm[0].line_compl[262]:1 */ + P7_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:31 */ + P7_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:31 */ + P7_1_LCD_COM29 = 12, /* Digital Deep Sleep - lcd.com[29]:0 */ + P7_1_LCD_SEG29 = 13, /* Digital Deep Sleep - lcd.seg[29]:0 */ + P7_1_SCB4_UART_TX = 18, /* Digital Active - scb[4].uart_tx:0 */ + P7_1_SCB4_I2C_SDA = 19, /* Digital Active - scb[4].i2c_sda:0 */ + P7_1_SCB4_SPI_MISO = 20, /* Digital Active - scb[4].spi_miso:0 */ + P7_1_TCPWM0_TR_ONE_CNT_IN259 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[259]:2 */ + P7_1_PERI_TR_IO_INPUT15 = 24, /* Digital Active - peri.tr_io_input[15]:0 */ + + /* P7.2 */ + P7_2_GPIO = 0, /* N/A */ + P7_2_AMUXA = 4, /* AMUXBUS A */ + P7_2_AMUXB = 5, /* AMUXBUS B */ + P7_2_AMUXA_DSI = 6, /* N/A */ + P7_2_AMUXB_DSI = 7, /* N/A */ + P7_2_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:3 */ + P7_2_TCPWM0_LINE263 = 9, /* Digital Active - tcpwm[0].line[263]:1 */ + P7_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:32 */ + P7_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:32 */ + P7_2_LCD_COM30 = 12, /* Digital Deep Sleep - lcd.com[30]:0 */ + P7_2_LCD_SEG30 = 13, /* Digital Deep Sleep - lcd.seg[30]:0 */ + P7_2_SCB4_UART_RTS = 18, /* Digital Active - scb[4].uart_rts:0 */ + P7_2_SCB4_SPI_CLK = 20, /* Digital Active - scb[4].spi_clk:0 */ + P7_2_TCPWM0_TR_ONE_CNT_IN260 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[260]:2 */ + + /* P7.3 */ + P7_3_GPIO = 0, /* N/A */ + P7_3_AMUXA = 4, /* AMUXBUS A */ + P7_3_AMUXB = 5, /* AMUXBUS B */ + P7_3_AMUXA_DSI = 6, /* N/A */ + P7_3_AMUXB_DSI = 7, /* N/A */ + P7_3_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:3 */ + P7_3_TCPWM0_LINE_COMPL263 = 9, /* Digital Active - tcpwm[0].line_compl[263]:1 */ + P7_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:33 */ + P7_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:33 */ + P7_3_LCD_COM31 = 12, /* Digital Deep Sleep - lcd.com[31]:0 */ + P7_3_LCD_SEG31 = 13, /* Digital Deep Sleep - lcd.seg[31]:0 */ + P7_3_SCB4_UART_CTS = 18, /* Digital Active - scb[4].uart_cts:0 */ + P7_3_SCB4_SPI_SELECT0 = 20, /* Digital Active - scb[4].spi_select0:0 */ + P7_3_TCPWM0_TR_ONE_CNT_IN261 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[261]:2 */ + + /* P7.7 */ + P7_7_GPIO = 0, /* N/A */ + P7_7_AMUXA = 4, /* AMUXBUS A */ + P7_7_AMUXB = 5, /* AMUXBUS B */ + P7_7_AMUXA_DSI = 6, /* N/A */ + P7_7_AMUXB_DSI = 7, /* N/A */ + P7_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:36 */ + P7_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:36 */ + P7_7_LCD_COM35 = 12, /* Digital Deep Sleep - lcd.com[35]:0 */ + P7_7_LCD_SEG35 = 13, /* Digital Deep Sleep - lcd.seg[35]:0 */ + P7_7_CPUSS_CLK_FM_PUMP = 21, /* Digital Active - cpuss.clk_fm_pump */ + P7_7_TCPWM0_TR_ONE_CNT_IN0 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[0]:3 */ + + /* P8.0 */ + P8_0_GPIO = 0, /* N/A */ + P8_0_AMUXA = 4, /* AMUXBUS A */ + P8_0_AMUXB = 5, /* AMUXBUS B */ + P8_0_AMUXA_DSI = 6, /* N/A */ + P8_0_AMUXB_DSI = 7, /* N/A */ + P8_0_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:3 */ + P8_0_TCPWM0_LINE258 = 9, /* Digital Active - tcpwm[0].line[258]:1 */ + P8_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:37 */ + P8_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:37 */ + P8_0_LCD_COM36 = 12, /* Digital Deep Sleep - lcd.com[36]:0 */ + P8_0_LCD_SEG36 = 13, /* Digital Deep Sleep - lcd.seg[36]:0 */ + P8_0_SCB4_UART_RX = 18, /* Digital Active - scb[4].uart_rx:1 */ + P8_0_SCB4_I2C_SCL = 19, /* Digital Active - scb[4].i2c_scl:1 */ + P8_0_SCB4_SPI_MOSI = 20, /* Digital Active - scb[4].spi_mosi:1 */ + P8_0_TCPWM0_TR_ONE_CNT_IN1 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[1]:3 */ + P8_0_PERI_TR_IO_INPUT16 = 24, /* Digital Active - peri.tr_io_input[16]:0 */ + + /* P8.1 */ + P8_1_GPIO = 0, /* N/A */ + P8_1_AMUXA = 4, /* AMUXBUS A */ + P8_1_AMUXB = 5, /* AMUXBUS B */ + P8_1_AMUXA_DSI = 6, /* N/A */ + P8_1_AMUXB_DSI = 7, /* N/A */ + P8_1_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:3 */ + P8_1_TCPWM0_LINE_COMPL258 = 9, /* Digital Active - tcpwm[0].line_compl[258]:1 */ + P8_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:38 */ + P8_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:38 */ + P8_1_LCD_COM37 = 12, /* Digital Deep Sleep - lcd.com[37]:0 */ + P8_1_LCD_SEG37 = 13, /* Digital Deep Sleep - lcd.seg[37]:0 */ + P8_1_SCB4_UART_TX = 18, /* Digital Active - scb[4].uart_tx:1 */ + P8_1_SCB4_I2C_SDA = 19, /* Digital Active - scb[4].i2c_sda:1 */ + P8_1_SCB4_SPI_MISO = 20, /* Digital Active - scb[4].spi_miso:1 */ + P8_1_TCPWM0_TR_ONE_CNT_IN2 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[2]:3 */ + P8_1_PERI_TR_IO_INPUT17 = 24, /* Digital Active - peri.tr_io_input[17]:0 */ + + /* P9.0 */ + P9_0_GPIO = 0, /* N/A */ + P9_0_AMUXA = 4, /* AMUXBUS A */ + P9_0_AMUXB = 5, /* AMUXBUS B */ + P9_0_AMUXA_DSI = 6, /* N/A */ + P9_0_AMUXB_DSI = 7, /* N/A */ + P9_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:4 */ + P9_0_TCPWM0_LINE260 = 9, /* Digital Active - tcpwm[0].line[260]:2 */ + P9_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:39 */ + P9_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:39 */ + P9_0_LCD_COM40 = 12, /* Digital Deep Sleep - lcd.com[40]:0 */ + P9_0_LCD_SEG40 = 13, /* Digital Deep Sleep - lcd.seg[40]:0 */ + P9_0_SCB2_UART_RX = 18, /* Digital Active - scb[2].uart_rx:0 */ + P9_0_SCB2_I2C_SCL = 19, /* Digital Active - scb[2].i2c_scl:0 */ + P9_0_SCB2_SPI_MOSI = 20, /* Digital Active - scb[2].spi_mosi:0 */ + P9_0_TCPWM0_TR_ONE_CNT_IN3 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[3]:3 */ + P9_0_PERI_TR_IO_INPUT18 = 24, /* Digital Active - peri.tr_io_input[18]:0 */ + P9_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:1 */ + + /* P9.1 */ + P9_1_GPIO = 0, /* N/A */ + P9_1_AMUXA = 4, /* AMUXBUS A */ + P9_1_AMUXB = 5, /* AMUXBUS B */ + P9_1_AMUXA_DSI = 6, /* N/A */ + P9_1_AMUXB_DSI = 7, /* N/A */ + P9_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:4 */ + P9_1_TCPWM0_LINE_COMPL260 = 9, /* Digital Active - tcpwm[0].line_compl[260]:2 */ + P9_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:40 */ + P9_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:40 */ + P9_1_LCD_COM41 = 12, /* Digital Deep Sleep - lcd.com[41]:0 */ + P9_1_LCD_SEG41 = 13, /* Digital Deep Sleep - lcd.seg[41]:0 */ + P9_1_SCB2_UART_TX = 18, /* Digital Active - scb[2].uart_tx:0 */ + P9_1_SCB2_I2C_SDA = 19, /* Digital Active - scb[2].i2c_sda:0 */ + P9_1_SCB2_SPI_MISO = 20, /* Digital Active - scb[2].spi_miso:0 */ + P9_1_TCPWM0_TR_ONE_CNT_IN256 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[256]:3 */ + P9_1_PERI_TR_IO_INPUT19 = 24, /* Digital Active - peri.tr_io_input[19]:0 */ + P9_1_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:1 */ + P9_1_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:1 */ + + /* P9.2 */ + P9_2_GPIO = 0, /* N/A */ + P9_2_AMUXA = 4, /* AMUXBUS A */ + P9_2_AMUXB = 5, /* AMUXBUS B */ + P9_2_AMUXA_DSI = 6, /* N/A */ + P9_2_AMUXB_DSI = 7, /* N/A */ + P9_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:4 */ + P9_2_TCPWM0_LINE261 = 9, /* Digital Active - tcpwm[0].line[261]:2 */ + P9_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:41 */ + P9_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:41 */ + P9_2_LCD_COM42 = 12, /* Digital Deep Sleep - lcd.com[42]:0 */ + P9_2_LCD_SEG42 = 13, /* Digital Deep Sleep - lcd.seg[42]:0 */ + P9_2_SCB2_UART_RTS = 18, /* Digital Active - scb[2].uart_rts:0 */ + P9_2_SCB2_SPI_CLK = 20, /* Digital Active - scb[2].spi_clk:0 */ + P9_2_PASS_DSI_CTB_CMP0 = 22, /* Digital Active - pass.dsi_ctb_cmp0:1 */ + P9_2_TCPWM0_TR_ONE_CNT_IN257 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[257]:3 */ + P9_2_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:1 */ + + /* P9.3 */ + P9_3_GPIO = 0, /* N/A */ + P9_3_AMUXA = 4, /* AMUXBUS A */ + P9_3_AMUXB = 5, /* AMUXBUS B */ + P9_3_AMUXA_DSI = 6, /* N/A */ + P9_3_AMUXB_DSI = 7, /* N/A */ + P9_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:4 */ + P9_3_TCPWM0_LINE_COMPL261 = 9, /* Digital Active - tcpwm[0].line_compl[261]:3 */ + P9_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:42 */ + P9_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:42 */ + P9_3_LCD_COM43 = 12, /* Digital Deep Sleep - lcd.com[43]:0 */ + P9_3_LCD_SEG43 = 13, /* Digital Deep Sleep - lcd.seg[43]:0 */ + P9_3_SCB2_UART_CTS = 18, /* Digital Active - scb[2].uart_cts:0 */ + P9_3_SCB2_SPI_SELECT0 = 20, /* Digital Active - scb[2].spi_select0:0 */ + P9_3_PASS_DSI_CTB_CMP1 = 22, /* Digital Active - pass.dsi_ctb_cmp1:1 */ + P9_3_TCPWM0_TR_ONE_CNT_IN258 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[258]:3 */ + P9_3_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:1 */ + P9_3_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:1 */ + + /* P10.0 */ + P10_0_GPIO = 0, /* N/A */ + P10_0_AMUXA = 4, /* AMUXBUS A */ + P10_0_AMUXB = 5, /* AMUXBUS B */ + P10_0_AMUXA_DSI = 6, /* N/A */ + P10_0_AMUXB_DSI = 7, /* N/A */ + P10_0_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:4 */ + P10_0_TCPWM0_LINE262 = 9, /* Digital Active - tcpwm[0].line[262]:2 */ + P10_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:45 */ + P10_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:45 */ + P10_0_LCD_COM44 = 12, /* Digital Deep Sleep - lcd.com[44]:0 */ + P10_0_LCD_SEG44 = 13, /* Digital Deep Sleep - lcd.seg[44]:0 */ + P10_0_SCB1_UART_RX = 18, /* Digital Active - scb[1].uart_rx:0 */ + P10_0_SCB1_I2C_SCL = 19, /* Digital Active - scb[1].i2c_scl:0 */ + P10_0_SCB1_SPI_MOSI = 20, /* Digital Active - scb[1].spi_mosi:0 */ + P10_0_TCPWM0_TR_ONE_CNT_IN261 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[261]:3 */ + P10_0_PERI_TR_IO_INPUT20 = 24, /* Digital Active - peri.tr_io_input[20]:0 */ + P10_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:0 */ + + /* P10.1 */ + P10_1_GPIO = 0, /* N/A */ + P10_1_AMUXA = 4, /* AMUXBUS A */ + P10_1_AMUXB = 5, /* AMUXBUS B */ + P10_1_AMUXA_DSI = 6, /* N/A */ + P10_1_AMUXB_DSI = 7, /* N/A */ + P10_1_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:4 */ + P10_1_TCPWM0_LINE_COMPL262 = 9, /* Digital Active - tcpwm[0].line_compl[262]:2 */ + P10_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:46 */ + P10_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:46 */ + P10_1_LCD_COM45 = 12, /* Digital Deep Sleep - lcd.com[45]:0 */ + P10_1_LCD_SEG45 = 13, /* Digital Deep Sleep - lcd.seg[45]:0 */ + P10_1_SCB1_UART_TX = 18, /* Digital Active - scb[1].uart_tx:0 */ + P10_1_SCB1_I2C_SDA = 19, /* Digital Active - scb[1].i2c_sda:0 */ + P10_1_SCB1_SPI_MISO = 20, /* Digital Active - scb[1].spi_miso:0 */ + P10_1_TCPWM0_TR_ONE_CNT_IN262 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[262]:3 */ + P10_1_PERI_TR_IO_INPUT21 = 24, /* Digital Active - peri.tr_io_input[21]:0 */ + P10_1_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:0 */ + + /* P10.2 */ + P10_2_GPIO = 0, /* N/A */ + P10_2_AMUXA = 4, /* AMUXBUS A */ + P10_2_AMUXB = 5, /* AMUXBUS B */ + P10_2_AMUXA_DSI = 6, /* N/A */ + P10_2_AMUXB_DSI = 7, /* N/A */ + P10_2_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:4 */ + P10_2_TCPWM0_LINE263 = 9, /* Digital Active - tcpwm[0].line[263]:2 */ + P10_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:47 */ + P10_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:47 */ + P10_2_LCD_COM46 = 12, /* Digital Deep Sleep - lcd.com[46]:0 */ + P10_2_LCD_SEG46 = 13, /* Digital Deep Sleep - lcd.seg[46]:0 */ + P10_2_SCB1_UART_RTS = 18, /* Digital Active - scb[1].uart_rts:0 */ + P10_2_SCB1_SPI_CLK = 20, /* Digital Active - scb[1].spi_clk:0 */ + P10_2_TCPWM0_TR_ONE_CNT_IN263 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[263]:3 */ + P10_2_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:0 */ + + /* P10.3 */ + P10_3_GPIO = 0, /* N/A */ + P10_3_AMUXA = 4, /* AMUXBUS A */ + P10_3_AMUXB = 5, /* AMUXBUS B */ + P10_3_AMUXA_DSI = 6, /* N/A */ + P10_3_AMUXB_DSI = 7, /* N/A */ + P10_3_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:4 */ + P10_3_TCPWM0_LINE_COMPL263 = 9, /* Digital Active - tcpwm[0].line_compl[263]:2 */ + P10_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:48 */ + P10_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:48 */ + P10_3_LCD_COM47 = 12, /* Digital Deep Sleep - lcd.com[47]:0 */ + P10_3_LCD_SEG47 = 13, /* Digital Deep Sleep - lcd.seg[47]:0 */ + P10_3_SCB1_UART_CTS = 18, /* Digital Active - scb[1].uart_cts:0 */ + P10_3_SCB1_SPI_SELECT0 = 20, /* Digital Active - scb[1].spi_select0:0 */ + P10_3_TCPWM0_TR_ONE_CNT_IN0 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[0]:4 */ + P10_3_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:0 */ + + /* P10.4 */ + P10_4_GPIO = 0, /* N/A */ + P10_4_AMUXA = 4, /* AMUXBUS A */ + P10_4_AMUXB = 5, /* AMUXBUS B */ + P10_4_AMUXA_DSI = 6, /* N/A */ + P10_4_AMUXB_DSI = 7, /* N/A */ + P10_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:5 */ + P10_4_TCPWM0_LINE256 = 9, /* Digital Active - tcpwm[0].line[256]:2 */ + P10_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:49 */ + P10_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:49 */ + P10_4_LCD_COM48 = 12, /* Digital Deep Sleep - lcd.com[48]:0 */ + P10_4_LCD_SEG48 = 13, /* Digital Deep Sleep - lcd.seg[48]:0 */ + P10_4_SCB1_SPI_SELECT1 = 20, /* Digital Active - scb[1].spi_select1:0 */ + P10_4_TCPWM0_TR_ONE_CNT_IN1 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[1]:4 */ + + /* P10.5 */ + P10_5_GPIO = 0, /* N/A */ + P10_5_AMUXA = 4, /* AMUXBUS A */ + P10_5_AMUXB = 5, /* AMUXBUS B */ + P10_5_AMUXA_DSI = 6, /* N/A */ + P10_5_AMUXB_DSI = 7, /* N/A */ + P10_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:5 */ + P10_5_TCPWM0_LINE_COMPL256 = 9, /* Digital Active - tcpwm[0].line_compl[256]:2 */ + P10_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:50 */ + P10_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:50 */ + P10_5_LCD_COM49 = 12, /* Digital Deep Sleep - lcd.com[49]:0 */ + P10_5_LCD_SEG49 = 13, /* Digital Deep Sleep - lcd.seg[49]:0 */ + P10_5_SCB1_SPI_SELECT2 = 20, /* Digital Active - scb[1].spi_select2:0 */ + P10_5_TCPWM0_TR_ONE_CNT_IN2 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[2]:4 */ + + /* P10.6 */ + P10_6_GPIO = 0, /* N/A */ + P10_6_AMUXA = 4, /* AMUXBUS A */ + P10_6_AMUXB = 5, /* AMUXBUS B */ + P10_6_AMUXA_DSI = 6, /* N/A */ + P10_6_AMUXB_DSI = 7, /* N/A */ + P10_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:5 */ + P10_6_TCPWM0_LINE257 = 9, /* Digital Active - tcpwm[0].line[257]:2 */ + P10_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:51 */ + P10_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:51 */ + P10_6_LCD_COM50 = 12, /* Digital Deep Sleep - lcd.com[50]:0 */ + P10_6_LCD_SEG50 = 13, /* Digital Deep Sleep - lcd.seg[50]:0 */ + P10_6_SCB1_SPI_SELECT3 = 20, /* Digital Active - scb[1].spi_select3:0 */ + P10_6_TCPWM0_TR_ONE_CNT_IN3 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[3]:4 */ + P10_6_PERI_TR_IO_INPUT22 = 24, /* Digital Active - peri.tr_io_input[22]:0 */ + + /* P10.7 */ + P10_7_GPIO = 0, /* N/A */ + P10_7_AMUXA = 4, /* AMUXBUS A */ + P10_7_AMUXB = 5, /* AMUXBUS B */ + P10_7_AMUXA_DSI = 6, /* N/A */ + P10_7_AMUXB_DSI = 7, /* N/A */ + P10_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:5 */ + P10_7_TCPWM0_LINE_COMPL257 = 9, /* Digital Active - tcpwm[0].line_compl[257]:2 */ + P10_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:52 */ + P10_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:52 */ + P10_7_LCD_COM51 = 12, /* Digital Deep Sleep - lcd.com[51]:0 */ + P10_7_LCD_SEG51 = 13, /* Digital Deep Sleep - lcd.seg[51]:0 */ + P10_7_SMIF_SPI_SELECT2 = 17, /* Digital Active - smif.spi_select2 */ + P10_7_TCPWM0_TR_ONE_CNT_IN256 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[256]:4 */ + P10_7_PERI_TR_IO_INPUT23 = 24, /* Digital Active - peri.tr_io_input[23]:0 */ + + /* P11.2 */ + P11_2_GPIO = 0, /* N/A */ + P11_2_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:5 */ + P11_2_TCPWM0_LINE259 = 9, /* Digital Active - tcpwm[0].line[259]:2 */ + P11_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:54 */ + P11_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:54 */ + P11_2_LCD_COM54 = 12, /* Digital Deep Sleep - lcd.com[54]:0 */ + P11_2_LCD_SEG54 = 13, /* Digital Deep Sleep - lcd.seg[54]:0 */ + P11_2_SMIF_SPI_SELECT0 = 17, /* Digital Active - smif.spi_select0 */ + P11_2_SCB5_UART_RTS = 18, /* Digital Active - scb[5].uart_rts:0 */ + P11_2_SCB5_SPI_CLK = 20, /* Digital Active - scb[5].spi_clk:0 */ + P11_2_TCPWM0_TR_ONE_CNT_IN258 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[258]:4 */ + + /* P11.3 */ + P11_3_GPIO = 0, /* N/A */ + P11_3_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:5 */ + P11_3_TCPWM0_LINE_COMPL259 = 9, /* Digital Active - tcpwm[0].line_compl[259]:2 */ + P11_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:55 */ + P11_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:55 */ + P11_3_LCD_COM55 = 12, /* Digital Deep Sleep - lcd.com[55]:0 */ + P11_3_LCD_SEG55 = 13, /* Digital Deep Sleep - lcd.seg[55]:0 */ + P11_3_SMIF_SPI_DATA3 = 17, /* Digital Active - smif.spi_data3 */ + P11_3_SCB5_UART_CTS = 18, /* Digital Active - scb[5].uart_cts:0 */ + P11_3_SCB5_SPI_SELECT0 = 20, /* Digital Active - scb[5].spi_select0:0 */ + P11_3_TCPWM0_TR_ONE_CNT_IN259 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[259]:4 */ + P11_3_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:0 */ + + /* P11.4 */ + P11_4_GPIO = 0, /* N/A */ + P11_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:6 */ + P11_4_TCPWM0_LINE260 = 9, /* Digital Active - tcpwm[0].line[260]:3 */ + P11_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:56 */ + P11_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:56 */ + P11_4_LCD_COM56 = 12, /* Digital Deep Sleep - lcd.com[56]:0 */ + P11_4_LCD_SEG56 = 13, /* Digital Deep Sleep - lcd.seg[56]:0 */ + P11_4_SMIF_SPI_DATA2 = 17, /* Digital Active - smif.spi_data2 */ + P11_4_SCB5_SPI_SELECT1 = 20, /* Digital Active - scb[5].spi_select1:0 */ + P11_4_TCPWM0_TR_ONE_CNT_IN260 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[260]:4 */ + P11_4_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:0 */ + + /* P11.5 */ + P11_5_GPIO = 0, /* N/A */ + P11_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:6 */ + P11_5_TCPWM0_LINE_COMPL260 = 9, /* Digital Active - tcpwm[0].line_compl[260]:3 */ + P11_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:57 */ + P11_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:57 */ + P11_5_LCD_COM57 = 12, /* Digital Deep Sleep - lcd.com[57]:0 */ + P11_5_LCD_SEG57 = 13, /* Digital Deep Sleep - lcd.seg[57]:0 */ + P11_5_SMIF_SPI_DATA1 = 17, /* Digital Active - smif.spi_data1 */ + P11_5_SCB5_SPI_SELECT2 = 20, /* Digital Active - scb[5].spi_select2:0 */ + P11_5_TCPWM0_TR_ONE_CNT_IN261 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[261]:4 */ + + /* P11.6 */ + P11_6_GPIO = 0, /* N/A */ + P11_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:6 */ + P11_6_TCPWM0_LINE261 = 9, /* Digital Active - tcpwm[0].line[261]:3 */ + P11_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:58 */ + P11_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:58 */ + P11_6_LCD_COM58 = 12, /* Digital Deep Sleep - lcd.com[58]:0 */ + P11_6_LCD_SEG58 = 13, /* Digital Deep Sleep - lcd.seg[58]:0 */ + P11_6_SMIF_SPI_DATA0 = 17, /* Digital Active - smif.spi_data0 */ + P11_6_SCB5_SPI_SELECT3 = 20, /* Digital Active - scb[5].spi_select3:0 */ + P11_6_TCPWM0_TR_ONE_CNT_IN262 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[262]:4 */ + + /* P11.7 */ + P11_7_GPIO = 0, /* N/A */ + P11_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:6 */ + P11_7_TCPWM0_LINE_COMPL261 = 9, /* Digital Active - tcpwm[0].line_compl[261]:2 */ + P11_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:59 */ + P11_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:59 */ + P11_7_LCD_COM59 = 12, /* Digital Deep Sleep - lcd.com[59]:0 */ + P11_7_LCD_SEG59 = 13, /* Digital Deep Sleep - lcd.seg[59]:0 */ + P11_7_SMIF_SPI_CLK = 17, /* Digital Active - smif.spi_clk */ + P11_7_TCPWM0_TR_ONE_CNT_IN263 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[263]:4 */ + + /* P12.6 */ + P12_6_GPIO = 0, /* N/A */ + P12_6_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:6 */ + P12_6_TCPWM0_LINE263 = 9, /* Digital Active - tcpwm[0].line[263]:3 */ + P12_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:60 */ + P12_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:60 */ + P12_6_LCD_COM2 = 12, /* Digital Deep Sleep - lcd.com[2]:1 */ + P12_6_LCD_SEG2 = 13, /* Digital Deep Sleep - lcd.seg[2]:1 */ + P12_6_TCPWM0_TR_ONE_CNT_IN0 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[0]:5 */ + + /* P12.7 */ + P12_7_GPIO = 0, /* N/A */ + P12_7_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:6 */ + P12_7_TCPWM0_LINE_COMPL263 = 9, /* Digital Active - tcpwm[0].line_compl[263]:3 */ + P12_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:61 */ + P12_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:61 */ + P12_7_LCD_COM3 = 12, /* Digital Deep Sleep - lcd.com[3]:1 */ + P12_7_LCD_SEG3 = 13, /* Digital Deep Sleep - lcd.seg[3]:1 */ + P12_7_TCPWM0_TR_ONE_CNT_IN1 = 23 /* Digital Active - tcpwm[0].tr_one_cnt_in[1]:5 */ +} en_hsiom_sel_t; + +#endif /* _GPIO_PSOC6_04_68_QFN_H_ */ + + +/* [] END OF FILE */ diff --git a/devices/include/ip/cyip_ctbm_v2.h b/devices/include/ip/cyip_ctbm_v2.h new file mode 100644 index 0000000..54b84f2 --- /dev/null +++ b/devices/include/ip/cyip_ctbm_v2.h @@ -0,0 +1,271 @@ +/***************************************************************************//** +* \file cyip_ctbm_v2.h +* +* \brief +* CTBM IP definitions +* +* \note +* Generator version: 1.5.1.36 +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CYIP_CTBM_V2_H_ +#define _CYIP_CTBM_V2_H_ + +#include "cyip_headers.h" + +/******************************************************************************* +* CTBM +*******************************************************************************/ + +#define CTBM_V2_SECTION_SIZE 0x00010000UL + +/** + * \brief Continuous Time Block Mini (CTBM) + */ +typedef struct { + __IOM uint32_t CTB_CTRL; /*!< 0x00000000 global CTB and power control */ + __IOM uint32_t OA_RES0_CTRL; /*!< 0x00000004 Opamp0 and resistor0 control */ + __IOM uint32_t OA_RES1_CTRL; /*!< 0x00000008 Opamp1 and resistor1 control */ + __IM uint32_t COMP_STAT; /*!< 0x0000000C Comparator status */ + __IM uint32_t RESERVED[4]; + __IOM uint32_t INTR; /*!< 0x00000020 Interrupt request register */ + __IOM uint32_t INTR_SET; /*!< 0x00000024 Interrupt request set register */ + __IOM uint32_t INTR_MASK; /*!< 0x00000028 Interrupt request mask */ + __IM uint32_t INTR_MASKED; /*!< 0x0000002C Interrupt request masked */ + __IM uint32_t RESERVED1[20]; + __IOM uint32_t OA0_SW; /*!< 0x00000080 Opamp0 switch control */ + __IOM uint32_t OA0_SW_CLEAR; /*!< 0x00000084 Opamp0 switch control clear */ + __IOM uint32_t OA1_SW; /*!< 0x00000088 Opamp1 switch control */ + __IOM uint32_t OA1_SW_CLEAR; /*!< 0x0000008C Opamp1 switch control clear */ + __IM uint32_t RESERVED2[4]; + __IOM uint32_t CTD_SW; /*!< 0x000000A0 CTDAC connection switch control */ + __IOM uint32_t CTD_SW_CLEAR; /*!< 0x000000A4 CTDAC connection switch control clear */ + __IM uint32_t RESERVED3[6]; + __IOM uint32_t CTB_SW_DS_CTRL; /*!< 0x000000C0 CTB bus switch control */ + __IOM uint32_t CTB_SW_SQ_CTRL; /*!< 0x000000C4 CTB bus switch Sar Sequencer control */ + __IM uint32_t CTB_SW_STATUS; /*!< 0x000000C8 CTB bus switch control status */ +} CTBM_V2_Type; /*!< Size = 204 (0xCC) */ + + +/* CTBM.CTB_CTRL */ +#define CTBM_V2_CTB_CTRL_DEEPSLEEP_ON_Pos 30UL +#define CTBM_V2_CTB_CTRL_DEEPSLEEP_ON_Msk 0x40000000UL +#define CTBM_V2_CTB_CTRL_ENABLED_Pos 31UL +#define CTBM_V2_CTB_CTRL_ENABLED_Msk 0x80000000UL +/* CTBM.OA_RES0_CTRL */ +#define CTBM_V2_OA_RES0_CTRL_OA0_PWR_MODE_Pos 0UL +#define CTBM_V2_OA_RES0_CTRL_OA0_PWR_MODE_Msk 0x7UL +#define CTBM_V2_OA_RES0_CTRL_OA0_DRIVE_STR_SEL_Pos 3UL +#define CTBM_V2_OA_RES0_CTRL_OA0_DRIVE_STR_SEL_Msk 0x8UL +#define CTBM_V2_OA_RES0_CTRL_OA0_COMP_EN_Pos 4UL +#define CTBM_V2_OA_RES0_CTRL_OA0_COMP_EN_Msk 0x10UL +#define CTBM_V2_OA_RES0_CTRL_OA0_HYST_EN_Pos 5UL +#define CTBM_V2_OA_RES0_CTRL_OA0_HYST_EN_Msk 0x20UL +#define CTBM_V2_OA_RES0_CTRL_OA0_BYPASS_DSI_SYNC_Pos 6UL +#define CTBM_V2_OA_RES0_CTRL_OA0_BYPASS_DSI_SYNC_Msk 0x40UL +#define CTBM_V2_OA_RES0_CTRL_OA0_DSI_LEVEL_Pos 7UL +#define CTBM_V2_OA_RES0_CTRL_OA0_DSI_LEVEL_Msk 0x80UL +#define CTBM_V2_OA_RES0_CTRL_OA0_COMPINT_Pos 8UL +#define CTBM_V2_OA_RES0_CTRL_OA0_COMPINT_Msk 0x300UL +#define CTBM_V2_OA_RES0_CTRL_OA0_PUMP_EN_Pos 11UL +#define CTBM_V2_OA_RES0_CTRL_OA0_PUMP_EN_Msk 0x800UL +#define CTBM_V2_OA_RES0_CTRL_OA0_BOOST_EN_Pos 12UL +#define CTBM_V2_OA_RES0_CTRL_OA0_BOOST_EN_Msk 0x1000UL +/* CTBM.OA_RES1_CTRL */ +#define CTBM_V2_OA_RES1_CTRL_OA1_PWR_MODE_Pos 0UL +#define CTBM_V2_OA_RES1_CTRL_OA1_PWR_MODE_Msk 0x7UL +#define CTBM_V2_OA_RES1_CTRL_OA1_DRIVE_STR_SEL_Pos 3UL +#define CTBM_V2_OA_RES1_CTRL_OA1_DRIVE_STR_SEL_Msk 0x8UL +#define CTBM_V2_OA_RES1_CTRL_OA1_COMP_EN_Pos 4UL +#define CTBM_V2_OA_RES1_CTRL_OA1_COMP_EN_Msk 0x10UL +#define CTBM_V2_OA_RES1_CTRL_OA1_HYST_EN_Pos 5UL +#define CTBM_V2_OA_RES1_CTRL_OA1_HYST_EN_Msk 0x20UL +#define CTBM_V2_OA_RES1_CTRL_OA1_BYPASS_DSI_SYNC_Pos 6UL +#define CTBM_V2_OA_RES1_CTRL_OA1_BYPASS_DSI_SYNC_Msk 0x40UL +#define CTBM_V2_OA_RES1_CTRL_OA1_DSI_LEVEL_Pos 7UL +#define CTBM_V2_OA_RES1_CTRL_OA1_DSI_LEVEL_Msk 0x80UL +#define CTBM_V2_OA_RES1_CTRL_OA1_COMPINT_Pos 8UL +#define CTBM_V2_OA_RES1_CTRL_OA1_COMPINT_Msk 0x300UL +#define CTBM_V2_OA_RES1_CTRL_OA1_PUMP_EN_Pos 11UL +#define CTBM_V2_OA_RES1_CTRL_OA1_PUMP_EN_Msk 0x800UL +#define CTBM_V2_OA_RES1_CTRL_OA1_BOOST_EN_Pos 12UL +#define CTBM_V2_OA_RES1_CTRL_OA1_BOOST_EN_Msk 0x1000UL +/* CTBM.COMP_STAT */ +#define CTBM_V2_COMP_STAT_OA0_COMP_Pos 0UL +#define CTBM_V2_COMP_STAT_OA0_COMP_Msk 0x1UL +#define CTBM_V2_COMP_STAT_OA1_COMP_Pos 16UL +#define CTBM_V2_COMP_STAT_OA1_COMP_Msk 0x10000UL +/* CTBM.INTR */ +#define CTBM_V2_INTR_COMP0_Pos 0UL +#define CTBM_V2_INTR_COMP0_Msk 0x1UL +#define CTBM_V2_INTR_COMP1_Pos 1UL +#define CTBM_V2_INTR_COMP1_Msk 0x2UL +/* CTBM.INTR_SET */ +#define CTBM_V2_INTR_SET_COMP0_SET_Pos 0UL +#define CTBM_V2_INTR_SET_COMP0_SET_Msk 0x1UL +#define CTBM_V2_INTR_SET_COMP1_SET_Pos 1UL +#define CTBM_V2_INTR_SET_COMP1_SET_Msk 0x2UL +/* CTBM.INTR_MASK */ +#define CTBM_V2_INTR_MASK_COMP0_MASK_Pos 0UL +#define CTBM_V2_INTR_MASK_COMP0_MASK_Msk 0x1UL +#define CTBM_V2_INTR_MASK_COMP1_MASK_Pos 1UL +#define CTBM_V2_INTR_MASK_COMP1_MASK_Msk 0x2UL +/* CTBM.INTR_MASKED */ +#define CTBM_V2_INTR_MASKED_COMP0_MASKED_Pos 0UL +#define CTBM_V2_INTR_MASKED_COMP0_MASKED_Msk 0x1UL +#define CTBM_V2_INTR_MASKED_COMP1_MASKED_Pos 1UL +#define CTBM_V2_INTR_MASKED_COMP1_MASKED_Msk 0x2UL +/* CTBM.OA0_SW */ +#define CTBM_V2_OA0_SW_OA0P_A00_Pos 0UL +#define CTBM_V2_OA0_SW_OA0P_A00_Msk 0x1UL +#define CTBM_V2_OA0_SW_OA0P_A20_Pos 2UL +#define CTBM_V2_OA0_SW_OA0P_A20_Msk 0x4UL +#define CTBM_V2_OA0_SW_OA0P_A30_Pos 3UL +#define CTBM_V2_OA0_SW_OA0P_A30_Msk 0x8UL +#define CTBM_V2_OA0_SW_OA0M_A11_Pos 8UL +#define CTBM_V2_OA0_SW_OA0M_A11_Msk 0x100UL +#define CTBM_V2_OA0_SW_OA0M_A81_Pos 14UL +#define CTBM_V2_OA0_SW_OA0M_A81_Msk 0x4000UL +#define CTBM_V2_OA0_SW_OA0O_D51_Pos 18UL +#define CTBM_V2_OA0_SW_OA0O_D51_Msk 0x40000UL +#define CTBM_V2_OA0_SW_OA0O_D81_Pos 21UL +#define CTBM_V2_OA0_SW_OA0O_D81_Msk 0x200000UL +/* CTBM.OA0_SW_CLEAR */ +#define CTBM_V2_OA0_SW_CLEAR_OA0P_A00_Pos 0UL +#define CTBM_V2_OA0_SW_CLEAR_OA0P_A00_Msk 0x1UL +#define CTBM_V2_OA0_SW_CLEAR_OA0P_A20_Pos 2UL +#define CTBM_V2_OA0_SW_CLEAR_OA0P_A20_Msk 0x4UL +#define CTBM_V2_OA0_SW_CLEAR_OA0P_A30_Pos 3UL +#define CTBM_V2_OA0_SW_CLEAR_OA0P_A30_Msk 0x8UL +#define CTBM_V2_OA0_SW_CLEAR_OA0M_A11_Pos 8UL +#define CTBM_V2_OA0_SW_CLEAR_OA0M_A11_Msk 0x100UL +#define CTBM_V2_OA0_SW_CLEAR_OA0M_A81_Pos 14UL +#define CTBM_V2_OA0_SW_CLEAR_OA0M_A81_Msk 0x4000UL +#define CTBM_V2_OA0_SW_CLEAR_OA0O_D51_Pos 18UL +#define CTBM_V2_OA0_SW_CLEAR_OA0O_D51_Msk 0x40000UL +#define CTBM_V2_OA0_SW_CLEAR_OA0O_D81_Pos 21UL +#define CTBM_V2_OA0_SW_CLEAR_OA0O_D81_Msk 0x200000UL +/* CTBM.OA1_SW */ +#define CTBM_V2_OA1_SW_OA1P_A03_Pos 0UL +#define CTBM_V2_OA1_SW_OA1P_A03_Msk 0x1UL +#define CTBM_V2_OA1_SW_OA1P_A13_Pos 1UL +#define CTBM_V2_OA1_SW_OA1P_A13_Msk 0x2UL +#define CTBM_V2_OA1_SW_OA1P_A43_Pos 4UL +#define CTBM_V2_OA1_SW_OA1P_A43_Msk 0x10UL +#define CTBM_V2_OA1_SW_OA1P_A73_Pos 7UL +#define CTBM_V2_OA1_SW_OA1P_A73_Msk 0x80UL +#define CTBM_V2_OA1_SW_OA1M_A22_Pos 8UL +#define CTBM_V2_OA1_SW_OA1M_A22_Msk 0x100UL +#define CTBM_V2_OA1_SW_OA1M_A82_Pos 14UL +#define CTBM_V2_OA1_SW_OA1M_A82_Msk 0x4000UL +#define CTBM_V2_OA1_SW_OA1O_D52_Pos 18UL +#define CTBM_V2_OA1_SW_OA1O_D52_Msk 0x40000UL +#define CTBM_V2_OA1_SW_OA1O_D62_Pos 19UL +#define CTBM_V2_OA1_SW_OA1O_D62_Msk 0x80000UL +#define CTBM_V2_OA1_SW_OA1O_D82_Pos 21UL +#define CTBM_V2_OA1_SW_OA1O_D82_Msk 0x200000UL +/* CTBM.OA1_SW_CLEAR */ +#define CTBM_V2_OA1_SW_CLEAR_OA1P_A03_Pos 0UL +#define CTBM_V2_OA1_SW_CLEAR_OA1P_A03_Msk 0x1UL +#define CTBM_V2_OA1_SW_CLEAR_OA1P_A13_Pos 1UL +#define CTBM_V2_OA1_SW_CLEAR_OA1P_A13_Msk 0x2UL +#define CTBM_V2_OA1_SW_CLEAR_OA1P_A43_Pos 4UL +#define CTBM_V2_OA1_SW_CLEAR_OA1P_A43_Msk 0x10UL +#define CTBM_V2_OA1_SW_CLEAR_OA1P_A73_Pos 7UL +#define CTBM_V2_OA1_SW_CLEAR_OA1P_A73_Msk 0x80UL +#define CTBM_V2_OA1_SW_CLEAR_OA1M_A22_Pos 8UL +#define CTBM_V2_OA1_SW_CLEAR_OA1M_A22_Msk 0x100UL +#define CTBM_V2_OA1_SW_CLEAR_OA1M_A82_Pos 14UL +#define CTBM_V2_OA1_SW_CLEAR_OA1M_A82_Msk 0x4000UL +#define CTBM_V2_OA1_SW_CLEAR_OA1O_D52_Pos 18UL +#define CTBM_V2_OA1_SW_CLEAR_OA1O_D52_Msk 0x40000UL +#define CTBM_V2_OA1_SW_CLEAR_OA1O_D62_Pos 19UL +#define CTBM_V2_OA1_SW_CLEAR_OA1O_D62_Msk 0x80000UL +#define CTBM_V2_OA1_SW_CLEAR_OA1O_D82_Pos 21UL +#define CTBM_V2_OA1_SW_CLEAR_OA1O_D82_Msk 0x200000UL +/* CTBM.CTD_SW */ +#define CTBM_V2_CTD_SW_CTDD_CRD_Pos 1UL +#define CTBM_V2_CTD_SW_CTDD_CRD_Msk 0x2UL +#define CTBM_V2_CTD_SW_CTDS_CRS_Pos 4UL +#define CTBM_V2_CTD_SW_CTDS_CRS_Msk 0x10UL +#define CTBM_V2_CTD_SW_CTDS_COR_Pos 5UL +#define CTBM_V2_CTD_SW_CTDS_COR_Msk 0x20UL +#define CTBM_V2_CTD_SW_CTDO_C6H_Pos 8UL +#define CTBM_V2_CTD_SW_CTDO_C6H_Msk 0x100UL +#define CTBM_V2_CTD_SW_CTDO_COS_Pos 9UL +#define CTBM_V2_CTD_SW_CTDO_COS_Msk 0x200UL +#define CTBM_V2_CTD_SW_CTDH_COB_Pos 10UL +#define CTBM_V2_CTD_SW_CTDH_COB_Msk 0x400UL +#define CTBM_V2_CTD_SW_CTDH_CHD_Pos 12UL +#define CTBM_V2_CTD_SW_CTDH_CHD_Msk 0x1000UL +#define CTBM_V2_CTD_SW_CTDH_CA0_Pos 13UL +#define CTBM_V2_CTD_SW_CTDH_CA0_Msk 0x2000UL +#define CTBM_V2_CTD_SW_CTDH_CIS_Pos 14UL +#define CTBM_V2_CTD_SW_CTDH_CIS_Msk 0x4000UL +#define CTBM_V2_CTD_SW_CTDH_ILR_Pos 15UL +#define CTBM_V2_CTD_SW_CTDH_ILR_Msk 0x8000UL +/* CTBM.CTD_SW_CLEAR */ +#define CTBM_V2_CTD_SW_CLEAR_CTDD_CRD_Pos 1UL +#define CTBM_V2_CTD_SW_CLEAR_CTDD_CRD_Msk 0x2UL +#define CTBM_V2_CTD_SW_CLEAR_CTDS_CRS_Pos 4UL +#define CTBM_V2_CTD_SW_CLEAR_CTDS_CRS_Msk 0x10UL +#define CTBM_V2_CTD_SW_CLEAR_CTDS_COR_Pos 5UL +#define CTBM_V2_CTD_SW_CLEAR_CTDS_COR_Msk 0x20UL +#define CTBM_V2_CTD_SW_CLEAR_CTDO_C6H_Pos 8UL +#define CTBM_V2_CTD_SW_CLEAR_CTDO_C6H_Msk 0x100UL +#define CTBM_V2_CTD_SW_CLEAR_CTDO_COS_Pos 9UL +#define CTBM_V2_CTD_SW_CLEAR_CTDO_COS_Msk 0x200UL +#define CTBM_V2_CTD_SW_CLEAR_CTDH_COB_Pos 10UL +#define CTBM_V2_CTD_SW_CLEAR_CTDH_COB_Msk 0x400UL +#define CTBM_V2_CTD_SW_CLEAR_CTDH_CHD_Pos 12UL +#define CTBM_V2_CTD_SW_CLEAR_CTDH_CHD_Msk 0x1000UL +#define CTBM_V2_CTD_SW_CLEAR_CTDH_CA0_Pos 13UL +#define CTBM_V2_CTD_SW_CLEAR_CTDH_CA0_Msk 0x2000UL +#define CTBM_V2_CTD_SW_CLEAR_CTDH_CIS_Pos 14UL +#define CTBM_V2_CTD_SW_CLEAR_CTDH_CIS_Msk 0x4000UL +#define CTBM_V2_CTD_SW_CLEAR_CTDH_ILR_Pos 15UL +#define CTBM_V2_CTD_SW_CLEAR_CTDH_ILR_Msk 0x8000UL +/* CTBM.CTB_SW_DS_CTRL */ +#define CTBM_V2_CTB_SW_DS_CTRL_P2_DS_CTRL23_Pos 10UL +#define CTBM_V2_CTB_SW_DS_CTRL_P2_DS_CTRL23_Msk 0x400UL +#define CTBM_V2_CTB_SW_DS_CTRL_P3_DS_CTRL23_Pos 11UL +#define CTBM_V2_CTB_SW_DS_CTRL_P3_DS_CTRL23_Msk 0x800UL +#define CTBM_V2_CTB_SW_DS_CTRL_CTD_COS_DS_CTRL_Pos 31UL +#define CTBM_V2_CTB_SW_DS_CTRL_CTD_COS_DS_CTRL_Msk 0x80000000UL +/* CTBM.CTB_SW_SQ_CTRL */ +#define CTBM_V2_CTB_SW_SQ_CTRL_P2_SQ_CTRL23_Pos 10UL +#define CTBM_V2_CTB_SW_SQ_CTRL_P2_SQ_CTRL23_Msk 0x400UL +#define CTBM_V2_CTB_SW_SQ_CTRL_P3_SQ_CTRL23_Pos 11UL +#define CTBM_V2_CTB_SW_SQ_CTRL_P3_SQ_CTRL23_Msk 0x800UL +/* CTBM.CTB_SW_STATUS */ +#define CTBM_V2_CTB_SW_STATUS_OA0O_D51_STAT_Pos 28UL +#define CTBM_V2_CTB_SW_STATUS_OA0O_D51_STAT_Msk 0x10000000UL +#define CTBM_V2_CTB_SW_STATUS_OA1O_D52_STAT_Pos 29UL +#define CTBM_V2_CTB_SW_STATUS_OA1O_D52_STAT_Msk 0x20000000UL +#define CTBM_V2_CTB_SW_STATUS_OA1O_D62_STAT_Pos 30UL +#define CTBM_V2_CTB_SW_STATUS_OA1O_D62_STAT_Msk 0x40000000UL +#define CTBM_V2_CTB_SW_STATUS_CTD_COS_STAT_Pos 31UL +#define CTBM_V2_CTB_SW_STATUS_CTD_COS_STAT_Msk 0x80000000UL + + +#endif /* _CYIP_CTBM_V2_H_ */ + + +/* [] END OF FILE */ diff --git a/devices/include/ip/cyip_efuse_data_psoc6_04.h b/devices/include/ip/cyip_efuse_data_psoc6_04.h new file mode 100644 index 0000000..9e2a5d9 --- /dev/null +++ b/devices/include/ip/cyip_efuse_data_psoc6_04.h @@ -0,0 +1,250 @@ +/***************************************************************************//** +* \file cyip_efuse_data_psoc6_04.h +* +* \brief +* EFUSE_DATA IP definitions +* +* \note +* Generator version: 1.5.1.21 +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CYIP_EFUSE_DATA_PSOC6_04_H_ +#define _CYIP_EFUSE_DATA_PSOC6_04_H_ + +#include "cyip_headers.h" + +/** + * \brief Access restrictions for DEAD life cycle stage (DEAD_ACCESS_RESTRICT0) + */ +typedef struct { + uint8_t CM0_DISABLE; + uint8_t CM4_DISABLE; + uint8_t SYS_DISABLE; + uint8_t SYS_AP_MPU_ENABLE; + uint8_t SFLASH_ALLOWED[2]; + uint8_t MMIO_ALLOWED[2]; +} cy_stc_dead_access_restrict0_t; + +/** + * \brief Access restrictions for DEAD life cycle stage (DEAD_ACCESS_RESTRICT1) + */ +typedef struct { + uint8_t FLASH_ALLOWED[3]; + uint8_t SRAM_ALLOWED[3]; + uint8_t UNUSED; + uint8_t DIRECT_EXECUTE_DISABLE; +} cy_stc_dead_access_restrict1_t; + +/** + * \brief Access restrictions for SECURE life cycle stage (SECURE_ACCESS_RESTRICT0) + */ +typedef struct { + uint8_t CM0_DISABLE; + uint8_t CM4_DISABLE; + uint8_t SYS_DISABLE; + uint8_t SYS_AP_MPU_ENABLE; + uint8_t SFLASH_ALLOWED[2]; + uint8_t MMIO_ALLOWED[2]; +} cy_stc_secure_access_restrict0_t; + +/** + * \brief Access restrictions for SECURE life cycle stage (SECURE_ACCESS_RESTRICT1) + */ +typedef struct { + uint8_t FLASH_ALLOWED[3]; + uint8_t SRAM_ALLOWED[3]; + uint8_t UNUSED; + uint8_t DIRECT_EXECUTE_DISABLE; +} cy_stc_secure_access_restrict1_t; + +/** + * \brief NORMAL, SECURE_WITH_DEBUG, SECURE, and RMA fuse bits (LIFECYCLE_STAGE) + */ +typedef struct { + uint8_t NORMAL; + uint8_t SECURE_WITH_DEBUG; + uint8_t SECURE; + uint8_t RMA; + uint8_t RESERVED[4]; +} cy_stc_lifecycle_stage_t; + +/** + * \brief Cypress asset hash byte 0 (CY_ASSET_HASH0) + */ +typedef struct { + uint8_t HASH_BYTE[8]; +} cy_stc_cy_asset_hash0_t; + +/** + * \brief Cypress asset hash byte 1 (CY_ASSET_HASH1) + */ +typedef struct { + uint8_t HASH_BYTE[8]; +} cy_stc_cy_asset_hash1_t; + +/** + * \brief Cypress asset hash byte 2 (CY_ASSET_HASH2) + */ +typedef struct { + uint8_t HASH_BYTE[8]; +} cy_stc_cy_asset_hash2_t; + +/** + * \brief Cypress asset hash byte 3 (CY_ASSET_HASH3) + */ +typedef struct { + uint8_t HASH_BYTE[8]; +} cy_stc_cy_asset_hash3_t; + +/** + * \brief Cypress asset hash byte 4 (CY_ASSET_HASH4) + */ +typedef struct { + uint8_t HASH_BYTE[8]; +} cy_stc_cy_asset_hash4_t; + +/** + * \brief Cypress asset hash byte 5 (CY_ASSET_HASH5) + */ +typedef struct { + uint8_t HASH_BYTE[8]; +} cy_stc_cy_asset_hash5_t; + +/** + * \brief Cypress asset hash byte 6 (CY_ASSET_HASH6) + */ +typedef struct { + uint8_t CY_ASSET_HASH[8]; +} cy_stc_cy_asset_hash6_t; + +/** + * \brief Cypress asset hash byte 7 (CY_ASSET_HASH7) + */ +typedef struct { + uint8_t HASH_BYTE[8]; +} cy_stc_cy_asset_hash7_t; + +/** + * \brief Cypress asset hash byte 8 (CY_ASSET_HASH8) + */ +typedef struct { + uint8_t HASH_BYTE[8]; +} cy_stc_cy_asset_hash8_t; + +/** + * \brief Cypress asset hash byte 9 (CY_ASSET_HASH9) + */ +typedef struct { + uint8_t HASH_BYTE[8]; +} cy_stc_cy_asset_hash9_t; + +/** + * \brief Cypress asset hash byte 10 (CY_ASSET_HASH10) + */ +typedef struct { + uint8_t HASH_BYTE[8]; +} cy_stc_cy_asset_hash10_t; + +/** + * \brief Cypress asset hash byte 11 (CY_ASSET_HASH11) + */ +typedef struct { + uint8_t CY_ASSET_HASH[8]; +} cy_stc_cy_asset_hash11_t; + +/** + * \brief Cypress asset hash byte 12 (CY_ASSET_HASH12) + */ +typedef struct { + uint8_t HASH_BYTE[8]; +} cy_stc_cy_asset_hash12_t; + +/** + * \brief Cypress asset hash byte 13 (CY_ASSET_HASH13) + */ +typedef struct { + uint8_t CY_ASSET_HASH[8]; +} cy_stc_cy_asset_hash13_t; + +/** + * \brief Cypress asset hash byte 14 (CY_ASSET_HASH14) + */ +typedef struct { + uint8_t HASH_BYTE[8]; +} cy_stc_cy_asset_hash14_t; + +/** + * \brief Cypress asset hash byte 15 (CY_ASSET_HASH15) + */ +typedef struct { + uint8_t HASH_BYTE[8]; +} cy_stc_cy_asset_hash15_t; + +/** + * \brief Number of zeros in Cypress asset hash (CY_ASSET_HASH_ZEROS) + */ +typedef struct { + uint8_t HASH_BYTE[8]; +} cy_stc_cy_asset_hash_zeros_t; + +/** + * \brief Customer data (CUSTOMER_DATA) + */ +typedef struct { + uint8_t CUSTOMER_USE[8]; +} cy_stc_customer_data_t; + + +/** + * \brief eFUSE memory (EFUSE_DATA) + */ +typedef struct { + uint8_t RESERVED[312]; + cy_stc_dead_access_restrict0_t DEAD_ACCESS_RESTRICT0; + cy_stc_dead_access_restrict1_t DEAD_ACCESS_RESTRICT1; + cy_stc_secure_access_restrict0_t SECURE_ACCESS_RESTRICT0; + cy_stc_secure_access_restrict1_t SECURE_ACCESS_RESTRICT1; + cy_stc_lifecycle_stage_t LIFECYCLE_STAGE; + uint8_t RESERVED1[160]; + cy_stc_cy_asset_hash0_t CY_ASSET_HASH0; + cy_stc_cy_asset_hash1_t CY_ASSET_HASH1; + cy_stc_cy_asset_hash2_t CY_ASSET_HASH2; + cy_stc_cy_asset_hash3_t CY_ASSET_HASH3; + cy_stc_cy_asset_hash4_t CY_ASSET_HASH4; + cy_stc_cy_asset_hash5_t CY_ASSET_HASH5; + cy_stc_cy_asset_hash6_t CY_ASSET_HASH6; + cy_stc_cy_asset_hash7_t CY_ASSET_HASH7; + cy_stc_cy_asset_hash8_t CY_ASSET_HASH8; + cy_stc_cy_asset_hash9_t CY_ASSET_HASH9; + cy_stc_cy_asset_hash10_t CY_ASSET_HASH10; + cy_stc_cy_asset_hash11_t CY_ASSET_HASH11; + cy_stc_cy_asset_hash12_t CY_ASSET_HASH12; + cy_stc_cy_asset_hash13_t CY_ASSET_HASH13; + cy_stc_cy_asset_hash14_t CY_ASSET_HASH14; + cy_stc_cy_asset_hash15_t CY_ASSET_HASH15; + cy_stc_cy_asset_hash_zeros_t CY_ASSET_HASH_ZEROS; + cy_stc_customer_data_t CUSTOMER_DATA[47]; +} cy_stc_efuse_data_t; + + +#endif /* _CYIP_EFUSE_DATA_PSOC6_04_H_ */ + + +/* [] END OF FILE */ diff --git a/devices/include/ip/cyip_pass_v2.h b/devices/include/ip/cyip_pass_v2.h new file mode 100644 index 0000000..5d104f6 --- /dev/null +++ b/devices/include/ip/cyip_pass_v2.h @@ -0,0 +1,342 @@ +/***************************************************************************//** +* \file cyip_pass_v2.h +* +* \brief +* PASS IP definitions +* +* \note +* Generator version: 1.6.0.81 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CYIP_PASS_V2_H_ +#define _CYIP_PASS_V2_H_ + +#include "cyip_headers.h" + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_TIMER_V2_SECTION_SIZE 0x00000100UL +#define PASS_LPOSC_V2_SECTION_SIZE 0x00000100UL +#define PASS_FIFO_V2_SECTION_SIZE 0x00000100UL +#define PASS_AREFV2_V2_SECTION_SIZE 0x00000100UL +#define PASS_V2_SECTION_SIZE 0x00010000UL + +/** + * \brief Programmable Analog Subsystem (PASS_TIMER) + */ +typedef struct { + __IOM uint32_t CTRL; /*!< 0x00000000 Timer control register */ + __IOM uint32_t CONFIG; /*!< 0x00000004 Timer configuration register */ + __IOM uint32_t TIMER_PERIOD; /*!< 0x00000008 Timer period register */ + __IM uint32_t RESERVED[61]; +} PASS_TIMER_V2_Type; /*!< Size = 256 (0x100) */ + +/** + * \brief LPOSC configuration (PASS_LPOSC) + */ +typedef struct { + __IOM uint32_t CTRL; /*!< 0x00000000 Low Power Oscillator control */ + __IOM uint32_t CONFIG; /*!< 0x00000004 Low Power Oscillator configuration register */ + __IOM uint32_t ADFT; /*!< 0x00000008 Retention */ + __IM uint32_t RESERVED[61]; +} PASS_LPOSC_V2_Type; /*!< Size = 256 (0x100) */ + +/** + * \brief FIFO configuration (PASS_FIFO) + */ +typedef struct { + __IOM uint32_t CTRL; /*!< 0x00000000 FIFO control register */ + __IOM uint32_t CONFIG; /*!< 0x00000004 FIFO configuration register */ + __IM uint32_t STATUS; /*!< 0x00000008 FIFO status register */ + __IM uint32_t RD_DATA; /*!< 0x0000000C FIFO read data register */ + __IOM uint32_t INTR; /*!< 0x00000010 Interrupt register */ + __IOM uint32_t INTR_SET; /*!< 0x00000014 Interrupt set register */ + __IOM uint32_t INTR_MASK; /*!< 0x00000018 Interrupt mask register */ + __IM uint32_t INTR_MASKED; /*!< 0x0000001C Interrupt masked register */ + __IM uint32_t RESERVED[56]; +} PASS_FIFO_V2_Type; /*!< Size = 256 (0x100) */ + +/** + * \brief AREF configuration (PASS_AREFV2) + */ +typedef struct { + __IOM uint32_t AREF_CTRL; /*!< 0x00000000 global AREF control */ + __IM uint32_t RESERVED[63]; +} PASS_AREFV2_V2_Type; /*!< Size = 256 (0x100) */ + +/** + * \brief PASS top-level MMIO (AREF, LPOSC, FIFO, INTR, Trigger) (PASS) + */ +typedef struct { + __IM uint32_t INTR_CAUSE; /*!< 0x00000000 Interrupt cause register */ + __IM uint32_t RESERVED[3]; + __IOM uint32_t DPSLP_CLOCK_SEL; /*!< 0x00000010 Deepsleep clock select */ + __IOM uint32_t PWR_WAKE_CTRL; /*!< 0x00000014 Deepsleep wakeup control */ + __IM uint32_t RESERVED1[2]; + __IOM uint32_t CTBM_CLOCK_SEL; /*!< 0x00000020 Clock select for CTBm */ + __IM uint32_t RESERVED2[3]; + __IOM uint32_t SAR_DPSLP_CTRL[2]; /*!< 0x00000030 Deepsleep control for SARv3 */ + __IM uint32_t RESERVED3[2]; + __IOM uint32_t SAR_DPSLP_CONFIG[2]; /*!< 0x00000040 Deepsleep configuration for SARv3 */ + __IM uint32_t RESERVED4[2]; + __IOM uint32_t SAR_HW_TR_SMP_CNT; /*!< 0x00000050 SAR HW trigger sample control */ + __IOM uint32_t SAR_HW_TR_CTRL; /*!< 0x00000054 SAR HW trigger override */ + __IOM uint32_t SAR_SIMULT_HW_TR_CTRL; /*!< 0x00000058 SAR simultaneous trigger control */ + __IOM uint32_t SAR_SIMULT_FW_START_CTRL; /*!< 0x0000005C SAR simultaneous start control */ + __IOM uint32_t SAR_TR_OUT_CTRL; /*!< 0x00000060 SAR trigger out control */ + __IM uint32_t RESERVED5[39]; + PASS_TIMER_V2_Type TIMER; /*!< 0x00000100 Programmable Analog Subsystem */ + PASS_LPOSC_V2_Type LPOSC; /*!< 0x00000200 LPOSC configuration */ + PASS_FIFO_V2_Type FIFO[2]; /*!< 0x00000300 FIFO configuration */ + __IM uint32_t RESERVED6[576]; + PASS_AREFV2_V2_Type AREFV2; /*!< 0x00000E00 AREF configuration */ + __IOM uint32_t VREF_TRIM0; /*!< 0x00000F00 VREF Trim bits */ + __IOM uint32_t VREF_TRIM1; /*!< 0x00000F04 VREF Trim bits */ + __IOM uint32_t VREF_TRIM2; /*!< 0x00000F08 VREF Trim bits */ + __IOM uint32_t VREF_TRIM3; /*!< 0x00000F0C VREF Trim bits */ + __IOM uint32_t IZTAT_TRIM0; /*!< 0x00000F10 VREF Trim bits */ + __IOM uint32_t IZTAT_TRIM1; /*!< 0x00000F14 IZTAT Trim bits */ + __IOM uint32_t IPTAT_TRIM0; /*!< 0x00000F18 IPTAT Trim bits */ + __IOM uint32_t ICTAT_TRIM0; /*!< 0x00000F1C ICTAT Trim bits */ +} PASS_V2_Type; /*!< Size = 3872 (0xF20) */ + + +/* PASS_TIMER.CTRL */ +#define PASS_TIMER_V2_CTRL_ENABLED_Pos 31UL +#define PASS_TIMER_V2_CTRL_ENABLED_Msk 0x80000000UL +/* PASS_TIMER.CONFIG */ +#define PASS_TIMER_V2_CONFIG_CLOCK_SEL_Pos 0UL +#define PASS_TIMER_V2_CONFIG_CLOCK_SEL_Msk 0x3UL +/* PASS_TIMER.TIMER_PERIOD */ +#define PASS_TIMER_V2_TIMER_PERIOD_PER_VAL_Pos 0UL +#define PASS_TIMER_V2_TIMER_PERIOD_PER_VAL_Msk 0xFFFFUL + + +/* PASS_LPOSC.CTRL */ +#define PASS_LPOSC_V2_CTRL_ENABLED_Pos 31UL +#define PASS_LPOSC_V2_CTRL_ENABLED_Msk 0x80000000UL +/* PASS_LPOSC.CONFIG */ +#define PASS_LPOSC_V2_CONFIG_DEEPSLEEP_MODE_Pos 0UL +#define PASS_LPOSC_V2_CONFIG_DEEPSLEEP_MODE_Msk 0x1UL +/* PASS_LPOSC.ADFT */ +#define PASS_LPOSC_V2_ADFT_ADFT_SEL_Pos 0UL +#define PASS_LPOSC_V2_ADFT_ADFT_SEL_Msk 0x3UL + + +/* PASS_FIFO.CTRL */ +#define PASS_FIFO_V2_CTRL_ENABLED_Pos 31UL +#define PASS_FIFO_V2_CTRL_ENABLED_Msk 0x80000000UL +/* PASS_FIFO.CONFIG */ +#define PASS_FIFO_V2_CONFIG_LEVEL_Pos 0UL +#define PASS_FIFO_V2_CONFIG_LEVEL_Msk 0xFFUL +#define PASS_FIFO_V2_CONFIG_CHAN_ID_EN_Pos 8UL +#define PASS_FIFO_V2_CONFIG_CHAN_ID_EN_Msk 0x100UL +#define PASS_FIFO_V2_CONFIG_CHAIN_EN_Pos 9UL +#define PASS_FIFO_V2_CONFIG_CHAIN_EN_Msk 0x200UL +/* PASS_FIFO.STATUS */ +#define PASS_FIFO_V2_STATUS_USED_Pos 0UL +#define PASS_FIFO_V2_STATUS_USED_Msk 0xFFUL +#define PASS_FIFO_V2_STATUS_RD_PTR_Pos 16UL +#define PASS_FIFO_V2_STATUS_RD_PTR_Msk 0xFF0000UL +#define PASS_FIFO_V2_STATUS_WR_PTR_Pos 24UL +#define PASS_FIFO_V2_STATUS_WR_PTR_Msk 0xFF000000UL +/* PASS_FIFO.RD_DATA */ +#define PASS_FIFO_V2_RD_DATA_RESULT_Pos 0UL +#define PASS_FIFO_V2_RD_DATA_RESULT_Msk 0xFFFFUL +#define PASS_FIFO_V2_RD_DATA_CHAN_ID_Pos 16UL +#define PASS_FIFO_V2_RD_DATA_CHAN_ID_Msk 0xF0000UL +/* PASS_FIFO.INTR */ +#define PASS_FIFO_V2_INTR_FIFO_LEVEL_Pos 0UL +#define PASS_FIFO_V2_INTR_FIFO_LEVEL_Msk 0x1UL +#define PASS_FIFO_V2_INTR_FIFO_OVERFLOW_Pos 1UL +#define PASS_FIFO_V2_INTR_FIFO_OVERFLOW_Msk 0x2UL +#define PASS_FIFO_V2_INTR_FIFO_UNDERFLOW_Pos 2UL +#define PASS_FIFO_V2_INTR_FIFO_UNDERFLOW_Msk 0x4UL +/* PASS_FIFO.INTR_SET */ +#define PASS_FIFO_V2_INTR_SET_FIFO_LEVEL_Pos 0UL +#define PASS_FIFO_V2_INTR_SET_FIFO_LEVEL_Msk 0x1UL +#define PASS_FIFO_V2_INTR_SET_FIFO_OVERFLOW_Pos 1UL +#define PASS_FIFO_V2_INTR_SET_FIFO_OVERFLOW_Msk 0x2UL +#define PASS_FIFO_V2_INTR_SET_FIFO_UNDERFLOW_Pos 2UL +#define PASS_FIFO_V2_INTR_SET_FIFO_UNDERFLOW_Msk 0x4UL +/* PASS_FIFO.INTR_MASK */ +#define PASS_FIFO_V2_INTR_MASK_FIFO_LEVEL_Pos 0UL +#define PASS_FIFO_V2_INTR_MASK_FIFO_LEVEL_Msk 0x1UL +#define PASS_FIFO_V2_INTR_MASK_FIFO_OVERFLOW_Pos 1UL +#define PASS_FIFO_V2_INTR_MASK_FIFO_OVERFLOW_Msk 0x2UL +#define PASS_FIFO_V2_INTR_MASK_FIFO_UNDERFLOW_Pos 2UL +#define PASS_FIFO_V2_INTR_MASK_FIFO_UNDERFLOW_Msk 0x4UL +/* PASS_FIFO.INTR_MASKED */ +#define PASS_FIFO_V2_INTR_MASKED_FIFO_LEVEL_Pos 0UL +#define PASS_FIFO_V2_INTR_MASKED_FIFO_LEVEL_Msk 0x1UL +#define PASS_FIFO_V2_INTR_MASKED_FIFO_OVERFLOW_Pos 1UL +#define PASS_FIFO_V2_INTR_MASKED_FIFO_OVERFLOW_Msk 0x2UL +#define PASS_FIFO_V2_INTR_MASKED_FIFO_UNDERFLOW_Pos 2UL +#define PASS_FIFO_V2_INTR_MASKED_FIFO_UNDERFLOW_Msk 0x4UL + + +/* PASS_AREFV2.AREF_CTRL */ +#define PASS_AREFV2_V2_AREF_CTRL_AREF_MODE_Pos 0UL +#define PASS_AREFV2_V2_AREF_CTRL_AREF_MODE_Msk 0x1UL +#define PASS_AREFV2_V2_AREF_CTRL_AREF_BIAS_SCALE_Pos 2UL +#define PASS_AREFV2_V2_AREF_CTRL_AREF_BIAS_SCALE_Msk 0xCUL +#define PASS_AREFV2_V2_AREF_CTRL_AREF_RMB_Pos 4UL +#define PASS_AREFV2_V2_AREF_CTRL_AREF_RMB_Msk 0x70UL +#define PASS_AREFV2_V2_AREF_CTRL_CTB_IPTAT_SCALE_Pos 7UL +#define PASS_AREFV2_V2_AREF_CTRL_CTB_IPTAT_SCALE_Msk 0x80UL +#define PASS_AREFV2_V2_AREF_CTRL_CTB_IPTAT_REDIRECT_Pos 8UL +#define PASS_AREFV2_V2_AREF_CTRL_CTB_IPTAT_REDIRECT_Msk 0xFF00UL +#define PASS_AREFV2_V2_AREF_CTRL_IZTAT_SEL_Pos 16UL +#define PASS_AREFV2_V2_AREF_CTRL_IZTAT_SEL_Msk 0x10000UL +#define PASS_AREFV2_V2_AREF_CTRL_CLOCK_PUMP_PERI_SEL_Pos 19UL +#define PASS_AREFV2_V2_AREF_CTRL_CLOCK_PUMP_PERI_SEL_Msk 0x80000UL +#define PASS_AREFV2_V2_AREF_CTRL_VREF_SEL_Pos 20UL +#define PASS_AREFV2_V2_AREF_CTRL_VREF_SEL_Msk 0x300000UL +#define PASS_AREFV2_V2_AREF_CTRL_LP_VREF_EN_Pos 22UL +#define PASS_AREFV2_V2_AREF_CTRL_LP_VREF_EN_Msk 0x400000UL +#define PASS_AREFV2_V2_AREF_CTRL_IZTAT_SCALE_Pos 23UL +#define PASS_AREFV2_V2_AREF_CTRL_IZTAT_SCALE_Msk 0x800000UL +#define PASS_AREFV2_V2_AREF_CTRL_DEEPSLEEP_MODE_Pos 28UL +#define PASS_AREFV2_V2_AREF_CTRL_DEEPSLEEP_MODE_Msk 0x30000000UL +#define PASS_AREFV2_V2_AREF_CTRL_DEEPSLEEP_ON_Pos 30UL +#define PASS_AREFV2_V2_AREF_CTRL_DEEPSLEEP_ON_Msk 0x40000000UL +#define PASS_AREFV2_V2_AREF_CTRL_ENABLED_Pos 31UL +#define PASS_AREFV2_V2_AREF_CTRL_ENABLED_Msk 0x80000000UL + + +/* PASS.INTR_CAUSE */ +#define PASS_V2_INTR_CAUSE_CTB0_INT_Pos 0UL +#define PASS_V2_INTR_CAUSE_CTB0_INT_Msk 0x1UL +#define PASS_V2_INTR_CAUSE_CTB1_INT_Pos 1UL +#define PASS_V2_INTR_CAUSE_CTB1_INT_Msk 0x2UL +#define PASS_V2_INTR_CAUSE_CTB2_INT_Pos 2UL +#define PASS_V2_INTR_CAUSE_CTB2_INT_Msk 0x4UL +#define PASS_V2_INTR_CAUSE_CTB3_INT_Pos 3UL +#define PASS_V2_INTR_CAUSE_CTB3_INT_Msk 0x8UL +#define PASS_V2_INTR_CAUSE_CTDAC0_INT_Pos 4UL +#define PASS_V2_INTR_CAUSE_CTDAC0_INT_Msk 0x10UL +#define PASS_V2_INTR_CAUSE_CTDAC1_INT_Pos 5UL +#define PASS_V2_INTR_CAUSE_CTDAC1_INT_Msk 0x20UL +#define PASS_V2_INTR_CAUSE_CTDAC2_INT_Pos 6UL +#define PASS_V2_INTR_CAUSE_CTDAC2_INT_Msk 0x40UL +#define PASS_V2_INTR_CAUSE_CTDAC3_INT_Pos 7UL +#define PASS_V2_INTR_CAUSE_CTDAC3_INT_Msk 0x80UL +#define PASS_V2_INTR_CAUSE_SAR0_INT_Pos 8UL +#define PASS_V2_INTR_CAUSE_SAR0_INT_Msk 0x100UL +#define PASS_V2_INTR_CAUSE_SAR1_INT_Pos 9UL +#define PASS_V2_INTR_CAUSE_SAR1_INT_Msk 0x200UL +#define PASS_V2_INTR_CAUSE_SAR2_INT_Pos 10UL +#define PASS_V2_INTR_CAUSE_SAR2_INT_Msk 0x400UL +#define PASS_V2_INTR_CAUSE_SAR3_INT_Pos 11UL +#define PASS_V2_INTR_CAUSE_SAR3_INT_Msk 0x800UL +#define PASS_V2_INTR_CAUSE_FIFO0_INT_Pos 12UL +#define PASS_V2_INTR_CAUSE_FIFO0_INT_Msk 0x1000UL +#define PASS_V2_INTR_CAUSE_FIFO1_INT_Pos 13UL +#define PASS_V2_INTR_CAUSE_FIFO1_INT_Msk 0x2000UL +#define PASS_V2_INTR_CAUSE_FIFO2_INT_Pos 14UL +#define PASS_V2_INTR_CAUSE_FIFO2_INT_Msk 0x4000UL +#define PASS_V2_INTR_CAUSE_FIFO3_INT_Pos 15UL +#define PASS_V2_INTR_CAUSE_FIFO3_INT_Msk 0x8000UL +/* PASS.DPSLP_CLOCK_SEL */ +#define PASS_V2_DPSLP_CLOCK_SEL_DPSLP_CLOCK_SEL_Pos 0UL +#define PASS_V2_DPSLP_CLOCK_SEL_DPSLP_CLOCK_SEL_Msk 0x1UL +#define PASS_V2_DPSLP_CLOCK_SEL_DPSLP_CLOCK_DIV_Pos 4UL +#define PASS_V2_DPSLP_CLOCK_SEL_DPSLP_CLOCK_DIV_Msk 0x70UL +/* PASS.PWR_WAKE_CTRL */ +#define PASS_V2_PWR_WAKE_CTRL_WAKE_DELAY_Pos 0UL +#define PASS_V2_PWR_WAKE_CTRL_WAKE_DELAY_Msk 0x3FUL +/* PASS.CTBM_CLOCK_SEL */ +#define PASS_V2_CTBM_CLOCK_SEL_PUMP_CLOCK_SEL_Pos 0UL +#define PASS_V2_CTBM_CLOCK_SEL_PUMP_CLOCK_SEL_Msk 0x1UL +/* PASS.SAR_DPSLP_CTRL */ +#define PASS_V2_SAR_DPSLP_CTRL_ENABLED_Pos 31UL +#define PASS_V2_SAR_DPSLP_CTRL_ENABLED_Msk 0x80000000UL +/* PASS.SAR_DPSLP_CONFIG */ +#define PASS_V2_SAR_DPSLP_CONFIG_DEEPSLEEP_ON_Pos 30UL +#define PASS_V2_SAR_DPSLP_CONFIG_DEEPSLEEP_ON_Msk 0x40000000UL +/* PASS.SAR_HW_TR_SMP_CNT */ +#define PASS_V2_SAR_HW_TR_SMP_CNT_SMP_CNT_Pos 0UL +#define PASS_V2_SAR_HW_TR_SMP_CNT_SMP_CNT_Msk 0x3FUL +/* PASS.SAR_HW_TR_CTRL */ +#define PASS_V2_SAR_HW_TR_CTRL_HW_TR_TIMER_SEL_Pos 0UL +#define PASS_V2_SAR_HW_TR_CTRL_HW_TR_TIMER_SEL_Msk 0xFUL +#define PASS_V2_SAR_HW_TR_CTRL_HW_TR_SMP_CNT_SEL_Pos 4UL +#define PASS_V2_SAR_HW_TR_CTRL_HW_TR_SMP_CNT_SEL_Msk 0xF0UL +/* PASS.SAR_SIMULT_HW_TR_CTRL */ +#define PASS_V2_SAR_SIMULT_HW_TR_CTRL_SIMULT_HW_TR_EN_Pos 0UL +#define PASS_V2_SAR_SIMULT_HW_TR_CTRL_SIMULT_HW_TR_EN_Msk 0xFUL +#define PASS_V2_SAR_SIMULT_HW_TR_CTRL_SIMULT_HW_TR_SRC_Pos 4UL +#define PASS_V2_SAR_SIMULT_HW_TR_CTRL_SIMULT_HW_TR_SRC_Msk 0x30UL +#define PASS_V2_SAR_SIMULT_HW_TR_CTRL_SIMULT_HW_TR_TIMER_SEL_Pos 8UL +#define PASS_V2_SAR_SIMULT_HW_TR_CTRL_SIMULT_HW_TR_TIMER_SEL_Msk 0x100UL +#define PASS_V2_SAR_SIMULT_HW_TR_CTRL_SIMULT_HW_TR_LEVEL_Pos 18UL +#define PASS_V2_SAR_SIMULT_HW_TR_CTRL_SIMULT_HW_TR_LEVEL_Msk 0x40000UL +#define PASS_V2_SAR_SIMULT_HW_TR_CTRL_SIMULT_HW_SYNC_TR_Pos 19UL +#define PASS_V2_SAR_SIMULT_HW_TR_CTRL_SIMULT_HW_SYNC_TR_Msk 0x80000UL +#define PASS_V2_SAR_SIMULT_HW_TR_CTRL_SIMULT_HW_TR_SMP_CNT_SEL_Pos 20UL +#define PASS_V2_SAR_SIMULT_HW_TR_CTRL_SIMULT_HW_TR_SMP_CNT_SEL_Msk 0x100000UL +/* PASS.SAR_SIMULT_FW_START_CTRL */ +#define PASS_V2_SAR_SIMULT_FW_START_CTRL_FW_TRIGGER_Pos 0UL +#define PASS_V2_SAR_SIMULT_FW_START_CTRL_FW_TRIGGER_Msk 0xFUL +#define PASS_V2_SAR_SIMULT_FW_START_CTRL_CONTINUOUS_Pos 16UL +#define PASS_V2_SAR_SIMULT_FW_START_CTRL_CONTINUOUS_Msk 0xF0000UL +/* PASS.SAR_TR_OUT_CTRL */ +#define PASS_V2_SAR_TR_OUT_CTRL_SAR0_TR_OUT_SEL_Pos 0UL +#define PASS_V2_SAR_TR_OUT_CTRL_SAR0_TR_OUT_SEL_Msk 0x1UL +#define PASS_V2_SAR_TR_OUT_CTRL_SAR1_TR_OUT_SEL_Pos 1UL +#define PASS_V2_SAR_TR_OUT_CTRL_SAR1_TR_OUT_SEL_Msk 0x2UL +#define PASS_V2_SAR_TR_OUT_CTRL_SAR2_TR_OUT_SEL_Pos 2UL +#define PASS_V2_SAR_TR_OUT_CTRL_SAR2_TR_OUT_SEL_Msk 0x4UL +#define PASS_V2_SAR_TR_OUT_CTRL_SAR3_TR_OUT_SEL_Pos 3UL +#define PASS_V2_SAR_TR_OUT_CTRL_SAR3_TR_OUT_SEL_Msk 0x8UL +/* PASS.VREF_TRIM0 */ +#define PASS_V2_VREF_TRIM0_VREF_ABS_TRIM_Pos 0UL +#define PASS_V2_VREF_TRIM0_VREF_ABS_TRIM_Msk 0xFFUL +/* PASS.VREF_TRIM1 */ +#define PASS_V2_VREF_TRIM1_VREF_TEMPCO_TRIM_Pos 0UL +#define PASS_V2_VREF_TRIM1_VREF_TEMPCO_TRIM_Msk 0xFFUL +/* PASS.VREF_TRIM2 */ +#define PASS_V2_VREF_TRIM2_VREF_CURV_TRIM_Pos 0UL +#define PASS_V2_VREF_TRIM2_VREF_CURV_TRIM_Msk 0xFFUL +/* PASS.VREF_TRIM3 */ +#define PASS_V2_VREF_TRIM3_VREF_ATTEN_TRIM_Pos 0UL +#define PASS_V2_VREF_TRIM3_VREF_ATTEN_TRIM_Msk 0xFUL +/* PASS.IZTAT_TRIM0 */ +#define PASS_V2_IZTAT_TRIM0_IZTAT_ABS_TRIM_Pos 0UL +#define PASS_V2_IZTAT_TRIM0_IZTAT_ABS_TRIM_Msk 0xFFUL +/* PASS.IZTAT_TRIM1 */ +#define PASS_V2_IZTAT_TRIM1_IZTAT_TC_TRIM_Pos 0UL +#define PASS_V2_IZTAT_TRIM1_IZTAT_TC_TRIM_Msk 0xFFUL +/* PASS.IPTAT_TRIM0 */ +#define PASS_V2_IPTAT_TRIM0_IPTAT_CORE_TRIM_Pos 0UL +#define PASS_V2_IPTAT_TRIM0_IPTAT_CORE_TRIM_Msk 0xFUL +#define PASS_V2_IPTAT_TRIM0_IPTAT_CTBM_TRIM_Pos 4UL +#define PASS_V2_IPTAT_TRIM0_IPTAT_CTBM_TRIM_Msk 0xF0UL +/* PASS.ICTAT_TRIM0 */ +#define PASS_V2_ICTAT_TRIM0_ICTAT_TRIM_Pos 0UL +#define PASS_V2_ICTAT_TRIM0_ICTAT_TRIM_Msk 0xFUL + + +#endif /* _CYIP_PASS_V2_H_ */ + + +/* [] END OF FILE */ diff --git a/devices/include/ip/cyip_sar_v2.h b/devices/include/ip/cyip_sar_v2.h new file mode 100644 index 0000000..40d096b --- /dev/null +++ b/devices/include/ip/cyip_sar_v2.h @@ -0,0 +1,563 @@ +/***************************************************************************//** +* \file cyip_sar_v2.h +* +* \brief +* SAR IP definitions +* +* \note +* Generator version: 1.5.1.36 +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CYIP_SAR_V2_H_ +#define _CYIP_SAR_V2_H_ + +#include "cyip_headers.h" + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_V2_SECTION_SIZE 0x00010000UL + +/** + * \brief SAR ADC with Sequencer (SAR) + */ +typedef struct { + __IOM uint32_t CTRL; /*!< 0x00000000 Analog control register. */ + __IOM uint32_t SAMPLE_CTRL; /*!< 0x00000004 Sample control register. */ + __IM uint32_t RESERVED[2]; + __IOM uint32_t SAMPLE_TIME01; /*!< 0x00000010 Sample time specification ST0 and ST1 */ + __IOM uint32_t SAMPLE_TIME23; /*!< 0x00000014 Sample time specification ST2 and ST3 */ + __IOM uint32_t RANGE_THRES; /*!< 0x00000018 Global range detect threshold register. */ + __IOM uint32_t RANGE_COND; /*!< 0x0000001C Global range detect mode register. */ + __IOM uint32_t CHAN_EN; /*!< 0x00000020 Enable bits for the channels */ + __IOM uint32_t START_CTRL; /*!< 0x00000024 Start control register (firmware trigger). */ + __IM uint32_t RESERVED1[22]; + __IOM uint32_t CHAN_CONFIG[16]; /*!< 0x00000080 Channel configuration register. */ + __IM uint32_t RESERVED2[16]; + __IM uint32_t CHAN_WORK[16]; /*!< 0x00000100 Channel working data register */ + __IM uint32_t RESERVED3[16]; + __IM uint32_t CHAN_RESULT[16]; /*!< 0x00000180 Channel result data register */ + __IM uint32_t RESERVED4[16]; + __IM uint32_t CHAN_WORK_UPDATED; /*!< 0x00000200 Channel working data register 'updated' bits */ + __IM uint32_t CHAN_RESULT_UPDATED; /*!< 0x00000204 Channel result data register 'updated' bits */ + __IM uint32_t CHAN_WORK_NEWVALUE; /*!< 0x00000208 Channel working data register 'new value' bits */ + __IM uint32_t CHAN_RESULT_NEWVALUE; /*!< 0x0000020C Channel result data register 'new value' bits */ + __IOM uint32_t INTR; /*!< 0x00000210 Interrupt request register. */ + __IOM uint32_t INTR_SET; /*!< 0x00000214 Interrupt set request register */ + __IOM uint32_t INTR_MASK; /*!< 0x00000218 Interrupt mask register. */ + __IM uint32_t INTR_MASKED; /*!< 0x0000021C Interrupt masked request register */ + __IOM uint32_t SATURATE_INTR; /*!< 0x00000220 Saturate interrupt request register. */ + __IOM uint32_t SATURATE_INTR_SET; /*!< 0x00000224 Saturate interrupt set request register */ + __IOM uint32_t SATURATE_INTR_MASK; /*!< 0x00000228 Saturate interrupt mask register. */ + __IM uint32_t SATURATE_INTR_MASKED; /*!< 0x0000022C Saturate interrupt masked request register */ + __IOM uint32_t RANGE_INTR; /*!< 0x00000230 Range detect interrupt request register. */ + __IOM uint32_t RANGE_INTR_SET; /*!< 0x00000234 Range detect interrupt set request register */ + __IOM uint32_t RANGE_INTR_MASK; /*!< 0x00000238 Range detect interrupt mask register. */ + __IM uint32_t RANGE_INTR_MASKED; /*!< 0x0000023C Range interrupt masked request register */ + __IM uint32_t INTR_CAUSE; /*!< 0x00000240 Interrupt cause register */ + __IM uint32_t RESERVED5[23]; + __IM uint32_t STATUS; /*!< 0x000002A0 Current status of internal SAR registers (mostly for debug) */ + __IM uint32_t AVG_STAT; /*!< 0x000002A4 Current averaging status (for debug) */ + __IM uint32_t RESERVED6[22]; + __IOM uint32_t MUX_SWITCH0; /*!< 0x00000300 SARMUX Firmware switch controls */ + __IOM uint32_t MUX_SWITCH_CLEAR0; /*!< 0x00000304 SARMUX Firmware switch control clear */ + __IM uint32_t RESERVED7[15]; + __IOM uint32_t MUX_SWITCH_SQ_CTRL; /*!< 0x00000344 SARMUX switch Sar Sequencer control */ + __IM uint32_t MUX_SWITCH_STATUS; /*!< 0x00000348 SARMUX switch status */ +} SAR_V2_Type; /*!< Size = 844 (0x34C) */ + + +/* SAR.CTRL */ +#define SAR_V2_CTRL_PWR_CTRL_VREF_Pos 0UL +#define SAR_V2_CTRL_PWR_CTRL_VREF_Msk 0x7UL +#define SAR_V2_CTRL_VREF_SEL_Pos 4UL +#define SAR_V2_CTRL_VREF_SEL_Msk 0x70UL +#define SAR_V2_CTRL_VREF_BYP_CAP_EN_Pos 7UL +#define SAR_V2_CTRL_VREF_BYP_CAP_EN_Msk 0x80UL +#define SAR_V2_CTRL_NEG_SEL_Pos 9UL +#define SAR_V2_CTRL_NEG_SEL_Msk 0xE00UL +#define SAR_V2_CTRL_SAR_HW_CTRL_NEGVREF_Pos 13UL +#define SAR_V2_CTRL_SAR_HW_CTRL_NEGVREF_Msk 0x2000UL +#define SAR_V2_CTRL_COMP_DLY_Pos 14UL +#define SAR_V2_CTRL_COMP_DLY_Msk 0xC000UL +#define SAR_V2_CTRL_SPARE_Pos 16UL +#define SAR_V2_CTRL_SPARE_Msk 0xF0000UL +#define SAR_V2_CTRL_BOOSTPUMP_EN_Pos 20UL +#define SAR_V2_CTRL_BOOSTPUMP_EN_Msk 0x100000UL +#define SAR_V2_CTRL_REFBUF_EN_Pos 21UL +#define SAR_V2_CTRL_REFBUF_EN_Msk 0x200000UL +#define SAR_V2_CTRL_COMP_PWR_Pos 24UL +#define SAR_V2_CTRL_COMP_PWR_Msk 0x7000000UL +#define SAR_V2_CTRL_DEEPSLEEP_ON_Pos 27UL +#define SAR_V2_CTRL_DEEPSLEEP_ON_Msk 0x8000000UL +#define SAR_V2_CTRL_DSI_SYNC_CONFIG_Pos 28UL +#define SAR_V2_CTRL_DSI_SYNC_CONFIG_Msk 0x10000000UL +#define SAR_V2_CTRL_DSI_MODE_Pos 29UL +#define SAR_V2_CTRL_DSI_MODE_Msk 0x20000000UL +#define SAR_V2_CTRL_SWITCH_DISABLE_Pos 30UL +#define SAR_V2_CTRL_SWITCH_DISABLE_Msk 0x40000000UL +#define SAR_V2_CTRL_ENABLED_Pos 31UL +#define SAR_V2_CTRL_ENABLED_Msk 0x80000000UL +/* SAR.SAMPLE_CTRL */ +#define SAR_V2_SAMPLE_CTRL_LEFT_ALIGN_Pos 1UL +#define SAR_V2_SAMPLE_CTRL_LEFT_ALIGN_Msk 0x2UL +#define SAR_V2_SAMPLE_CTRL_SINGLE_ENDED_SIGNED_Pos 2UL +#define SAR_V2_SAMPLE_CTRL_SINGLE_ENDED_SIGNED_Msk 0x4UL +#define SAR_V2_SAMPLE_CTRL_DIFFERENTIAL_SIGNED_Pos 3UL +#define SAR_V2_SAMPLE_CTRL_DIFFERENTIAL_SIGNED_Msk 0x8UL +#define SAR_V2_SAMPLE_CTRL_AVG_CNT_Pos 4UL +#define SAR_V2_SAMPLE_CTRL_AVG_CNT_Msk 0x70UL +#define SAR_V2_SAMPLE_CTRL_AVG_SHIFT_Pos 7UL +#define SAR_V2_SAMPLE_CTRL_AVG_SHIFT_Msk 0x80UL +#define SAR_V2_SAMPLE_CTRL_AVG_MODE_Pos 8UL +#define SAR_V2_SAMPLE_CTRL_AVG_MODE_Msk 0x100UL +#define SAR_V2_SAMPLE_CTRL_CONTINUOUS_Pos 16UL +#define SAR_V2_SAMPLE_CTRL_CONTINUOUS_Msk 0x10000UL +#define SAR_V2_SAMPLE_CTRL_DSI_TRIGGER_EN_Pos 17UL +#define SAR_V2_SAMPLE_CTRL_DSI_TRIGGER_EN_Msk 0x20000UL +#define SAR_V2_SAMPLE_CTRL_DSI_TRIGGER_LEVEL_Pos 18UL +#define SAR_V2_SAMPLE_CTRL_DSI_TRIGGER_LEVEL_Msk 0x40000UL +#define SAR_V2_SAMPLE_CTRL_DSI_SYNC_TRIGGER_Pos 19UL +#define SAR_V2_SAMPLE_CTRL_DSI_SYNC_TRIGGER_Msk 0x80000UL +#define SAR_V2_SAMPLE_CTRL_UAB_SCAN_MODE_Pos 22UL +#define SAR_V2_SAMPLE_CTRL_UAB_SCAN_MODE_Msk 0x400000UL +#define SAR_V2_SAMPLE_CTRL_REPEAT_INVALID_Pos 23UL +#define SAR_V2_SAMPLE_CTRL_REPEAT_INVALID_Msk 0x800000UL +#define SAR_V2_SAMPLE_CTRL_VALID_SEL_Pos 24UL +#define SAR_V2_SAMPLE_CTRL_VALID_SEL_Msk 0x7000000UL +#define SAR_V2_SAMPLE_CTRL_VALID_SEL_EN_Pos 27UL +#define SAR_V2_SAMPLE_CTRL_VALID_SEL_EN_Msk 0x8000000UL +#define SAR_V2_SAMPLE_CTRL_VALID_IGNORE_Pos 28UL +#define SAR_V2_SAMPLE_CTRL_VALID_IGNORE_Msk 0x10000000UL +#define SAR_V2_SAMPLE_CTRL_TRIGGER_OUT_EN_Pos 30UL +#define SAR_V2_SAMPLE_CTRL_TRIGGER_OUT_EN_Msk 0x40000000UL +#define SAR_V2_SAMPLE_CTRL_EOS_DSI_OUT_EN_Pos 31UL +#define SAR_V2_SAMPLE_CTRL_EOS_DSI_OUT_EN_Msk 0x80000000UL +/* SAR.SAMPLE_TIME01 */ +#define SAR_V2_SAMPLE_TIME01_SAMPLE_TIME0_Pos 0UL +#define SAR_V2_SAMPLE_TIME01_SAMPLE_TIME0_Msk 0x3FFUL +#define SAR_V2_SAMPLE_TIME01_SAMPLE_TIME1_Pos 16UL +#define SAR_V2_SAMPLE_TIME01_SAMPLE_TIME1_Msk 0x3FF0000UL +/* SAR.SAMPLE_TIME23 */ +#define SAR_V2_SAMPLE_TIME23_SAMPLE_TIME2_Pos 0UL +#define SAR_V2_SAMPLE_TIME23_SAMPLE_TIME2_Msk 0x3FFUL +#define SAR_V2_SAMPLE_TIME23_SAMPLE_TIME3_Pos 16UL +#define SAR_V2_SAMPLE_TIME23_SAMPLE_TIME3_Msk 0x3FF0000UL +/* SAR.RANGE_THRES */ +#define SAR_V2_RANGE_THRES_RANGE_LOW_Pos 0UL +#define SAR_V2_RANGE_THRES_RANGE_LOW_Msk 0xFFFFUL +#define SAR_V2_RANGE_THRES_RANGE_HIGH_Pos 16UL +#define SAR_V2_RANGE_THRES_RANGE_HIGH_Msk 0xFFFF0000UL +/* SAR.RANGE_COND */ +#define SAR_V2_RANGE_COND_RANGE_COND_Pos 30UL +#define SAR_V2_RANGE_COND_RANGE_COND_Msk 0xC0000000UL +/* SAR.CHAN_EN */ +#define SAR_V2_CHAN_EN_CHAN_EN_Pos 0UL +#define SAR_V2_CHAN_EN_CHAN_EN_Msk 0xFFFFUL +/* SAR.START_CTRL */ +#define SAR_V2_START_CTRL_FW_TRIGGER_Pos 0UL +#define SAR_V2_START_CTRL_FW_TRIGGER_Msk 0x1UL +/* SAR.CHAN_CONFIG */ +#define SAR_V2_CHAN_CONFIG_POS_PIN_ADDR_Pos 0UL +#define SAR_V2_CHAN_CONFIG_POS_PIN_ADDR_Msk 0x7UL +#define SAR_V2_CHAN_CONFIG_POS_PORT_ADDR_Pos 4UL +#define SAR_V2_CHAN_CONFIG_POS_PORT_ADDR_Msk 0x70UL +#define SAR_V2_CHAN_CONFIG_DIFFERENTIAL_EN_Pos 8UL +#define SAR_V2_CHAN_CONFIG_DIFFERENTIAL_EN_Msk 0x100UL +#define SAR_V2_CHAN_CONFIG_AVG_EN_Pos 10UL +#define SAR_V2_CHAN_CONFIG_AVG_EN_Msk 0x400UL +#define SAR_V2_CHAN_CONFIG_SAMPLE_TIME_SEL_Pos 12UL +#define SAR_V2_CHAN_CONFIG_SAMPLE_TIME_SEL_Msk 0x3000UL +#define SAR_V2_CHAN_CONFIG_NEG_PIN_ADDR_Pos 16UL +#define SAR_V2_CHAN_CONFIG_NEG_PIN_ADDR_Msk 0x70000UL +#define SAR_V2_CHAN_CONFIG_NEG_PORT_ADDR_Pos 20UL +#define SAR_V2_CHAN_CONFIG_NEG_PORT_ADDR_Msk 0x700000UL +#define SAR_V2_CHAN_CONFIG_NEG_ADDR_EN_Pos 24UL +#define SAR_V2_CHAN_CONFIG_NEG_ADDR_EN_Msk 0x1000000UL +#define SAR_V2_CHAN_CONFIG_DSI_OUT_EN_Pos 31UL +#define SAR_V2_CHAN_CONFIG_DSI_OUT_EN_Msk 0x80000000UL +/* SAR.CHAN_WORK */ +#define SAR_V2_CHAN_WORK_WORK_Pos 0UL +#define SAR_V2_CHAN_WORK_WORK_Msk 0xFFFFUL +#define SAR_V2_CHAN_WORK_CHAN_WORK_NEWVALUE_MIR_Pos 27UL +#define SAR_V2_CHAN_WORK_CHAN_WORK_NEWVALUE_MIR_Msk 0x8000000UL +#define SAR_V2_CHAN_WORK_CHAN_WORK_UPDATED_MIR_Pos 31UL +#define SAR_V2_CHAN_WORK_CHAN_WORK_UPDATED_MIR_Msk 0x80000000UL +/* SAR.CHAN_RESULT */ +#define SAR_V2_CHAN_RESULT_RESULT_Pos 0UL +#define SAR_V2_CHAN_RESULT_RESULT_Msk 0xFFFFUL +#define SAR_V2_CHAN_RESULT_CHAN_RESULT_NEWVALUE_MIR_Pos 27UL +#define SAR_V2_CHAN_RESULT_CHAN_RESULT_NEWVALUE_MIR_Msk 0x8000000UL +#define SAR_V2_CHAN_RESULT_SATURATE_INTR_MIR_Pos 29UL +#define SAR_V2_CHAN_RESULT_SATURATE_INTR_MIR_Msk 0x20000000UL +#define SAR_V2_CHAN_RESULT_RANGE_INTR_MIR_Pos 30UL +#define SAR_V2_CHAN_RESULT_RANGE_INTR_MIR_Msk 0x40000000UL +#define SAR_V2_CHAN_RESULT_CHAN_RESULT_UPDATED_MIR_Pos 31UL +#define SAR_V2_CHAN_RESULT_CHAN_RESULT_UPDATED_MIR_Msk 0x80000000UL +/* SAR.CHAN_WORK_UPDATED */ +#define SAR_V2_CHAN_WORK_UPDATED_CHAN_WORK_UPDATED_Pos 0UL +#define SAR_V2_CHAN_WORK_UPDATED_CHAN_WORK_UPDATED_Msk 0xFFFFUL +/* SAR.CHAN_RESULT_UPDATED */ +#define SAR_V2_CHAN_RESULT_UPDATED_CHAN_RESULT_UPDATED_Pos 0UL +#define SAR_V2_CHAN_RESULT_UPDATED_CHAN_RESULT_UPDATED_Msk 0xFFFFUL +/* SAR.CHAN_WORK_NEWVALUE */ +#define SAR_V2_CHAN_WORK_NEWVALUE_CHAN_WORK_NEWVALUE_Pos 0UL +#define SAR_V2_CHAN_WORK_NEWVALUE_CHAN_WORK_NEWVALUE_Msk 0xFFFFUL +/* SAR.CHAN_RESULT_NEWVALUE */ +#define SAR_V2_CHAN_RESULT_NEWVALUE_CHAN_RESULT_NEWVALUE_Pos 0UL +#define SAR_V2_CHAN_RESULT_NEWVALUE_CHAN_RESULT_NEWVALUE_Msk 0xFFFFUL +/* SAR.INTR */ +#define SAR_V2_INTR_EOS_INTR_Pos 0UL +#define SAR_V2_INTR_EOS_INTR_Msk 0x1UL +#define SAR_V2_INTR_OVERFLOW_INTR_Pos 1UL +#define SAR_V2_INTR_OVERFLOW_INTR_Msk 0x2UL +#define SAR_V2_INTR_FW_COLLISION_INTR_Pos 2UL +#define SAR_V2_INTR_FW_COLLISION_INTR_Msk 0x4UL +#define SAR_V2_INTR_DSI_COLLISION_INTR_Pos 3UL +#define SAR_V2_INTR_DSI_COLLISION_INTR_Msk 0x8UL +#define SAR_V2_INTR_INJ_EOC_INTR_Pos 4UL +#define SAR_V2_INTR_INJ_EOC_INTR_Msk 0x10UL +#define SAR_V2_INTR_INJ_SATURATE_INTR_Pos 5UL +#define SAR_V2_INTR_INJ_SATURATE_INTR_Msk 0x20UL +#define SAR_V2_INTR_INJ_RANGE_INTR_Pos 6UL +#define SAR_V2_INTR_INJ_RANGE_INTR_Msk 0x40UL +#define SAR_V2_INTR_INJ_COLLISION_INTR_Pos 7UL +#define SAR_V2_INTR_INJ_COLLISION_INTR_Msk 0x80UL +/* SAR.INTR_SET */ +#define SAR_V2_INTR_SET_EOS_SET_Pos 0UL +#define SAR_V2_INTR_SET_EOS_SET_Msk 0x1UL +#define SAR_V2_INTR_SET_OVERFLOW_SET_Pos 1UL +#define SAR_V2_INTR_SET_OVERFLOW_SET_Msk 0x2UL +#define SAR_V2_INTR_SET_FW_COLLISION_SET_Pos 2UL +#define SAR_V2_INTR_SET_FW_COLLISION_SET_Msk 0x4UL +#define SAR_V2_INTR_SET_DSI_COLLISION_SET_Pos 3UL +#define SAR_V2_INTR_SET_DSI_COLLISION_SET_Msk 0x8UL +#define SAR_V2_INTR_SET_INJ_EOC_SET_Pos 4UL +#define SAR_V2_INTR_SET_INJ_EOC_SET_Msk 0x10UL +#define SAR_V2_INTR_SET_INJ_SATURATE_SET_Pos 5UL +#define SAR_V2_INTR_SET_INJ_SATURATE_SET_Msk 0x20UL +#define SAR_V2_INTR_SET_INJ_RANGE_SET_Pos 6UL +#define SAR_V2_INTR_SET_INJ_RANGE_SET_Msk 0x40UL +#define SAR_V2_INTR_SET_INJ_COLLISION_SET_Pos 7UL +#define SAR_V2_INTR_SET_INJ_COLLISION_SET_Msk 0x80UL +/* SAR.INTR_MASK */ +#define SAR_V2_INTR_MASK_EOS_MASK_Pos 0UL +#define SAR_V2_INTR_MASK_EOS_MASK_Msk 0x1UL +#define SAR_V2_INTR_MASK_OVERFLOW_MASK_Pos 1UL +#define SAR_V2_INTR_MASK_OVERFLOW_MASK_Msk 0x2UL +#define SAR_V2_INTR_MASK_FW_COLLISION_MASK_Pos 2UL +#define SAR_V2_INTR_MASK_FW_COLLISION_MASK_Msk 0x4UL +#define SAR_V2_INTR_MASK_DSI_COLLISION_MASK_Pos 3UL +#define SAR_V2_INTR_MASK_DSI_COLLISION_MASK_Msk 0x8UL +#define SAR_V2_INTR_MASK_INJ_EOC_MASK_Pos 4UL +#define SAR_V2_INTR_MASK_INJ_EOC_MASK_Msk 0x10UL +#define SAR_V2_INTR_MASK_INJ_SATURATE_MASK_Pos 5UL +#define SAR_V2_INTR_MASK_INJ_SATURATE_MASK_Msk 0x20UL +#define SAR_V2_INTR_MASK_INJ_RANGE_MASK_Pos 6UL +#define SAR_V2_INTR_MASK_INJ_RANGE_MASK_Msk 0x40UL +#define SAR_V2_INTR_MASK_INJ_COLLISION_MASK_Pos 7UL +#define SAR_V2_INTR_MASK_INJ_COLLISION_MASK_Msk 0x80UL +/* SAR.INTR_MASKED */ +#define SAR_V2_INTR_MASKED_EOS_MASKED_Pos 0UL +#define SAR_V2_INTR_MASKED_EOS_MASKED_Msk 0x1UL +#define SAR_V2_INTR_MASKED_OVERFLOW_MASKED_Pos 1UL +#define SAR_V2_INTR_MASKED_OVERFLOW_MASKED_Msk 0x2UL +#define SAR_V2_INTR_MASKED_FW_COLLISION_MASKED_Pos 2UL +#define SAR_V2_INTR_MASKED_FW_COLLISION_MASKED_Msk 0x4UL +#define SAR_V2_INTR_MASKED_DSI_COLLISION_MASKED_Pos 3UL +#define SAR_V2_INTR_MASKED_DSI_COLLISION_MASKED_Msk 0x8UL +#define SAR_V2_INTR_MASKED_INJ_EOC_MASKED_Pos 4UL +#define SAR_V2_INTR_MASKED_INJ_EOC_MASKED_Msk 0x10UL +#define SAR_V2_INTR_MASKED_INJ_SATURATE_MASKED_Pos 5UL +#define SAR_V2_INTR_MASKED_INJ_SATURATE_MASKED_Msk 0x20UL +#define SAR_V2_INTR_MASKED_INJ_RANGE_MASKED_Pos 6UL +#define SAR_V2_INTR_MASKED_INJ_RANGE_MASKED_Msk 0x40UL +#define SAR_V2_INTR_MASKED_INJ_COLLISION_MASKED_Pos 7UL +#define SAR_V2_INTR_MASKED_INJ_COLLISION_MASKED_Msk 0x80UL +/* SAR.SATURATE_INTR */ +#define SAR_V2_SATURATE_INTR_SATURATE_INTR_Pos 0UL +#define SAR_V2_SATURATE_INTR_SATURATE_INTR_Msk 0xFFFFUL +/* SAR.SATURATE_INTR_SET */ +#define SAR_V2_SATURATE_INTR_SET_SATURATE_SET_Pos 0UL +#define SAR_V2_SATURATE_INTR_SET_SATURATE_SET_Msk 0xFFFFUL +/* SAR.SATURATE_INTR_MASK */ +#define SAR_V2_SATURATE_INTR_MASK_SATURATE_MASK_Pos 0UL +#define SAR_V2_SATURATE_INTR_MASK_SATURATE_MASK_Msk 0xFFFFUL +/* SAR.SATURATE_INTR_MASKED */ +#define SAR_V2_SATURATE_INTR_MASKED_SATURATE_MASKED_Pos 0UL +#define SAR_V2_SATURATE_INTR_MASKED_SATURATE_MASKED_Msk 0xFFFFUL +/* SAR.RANGE_INTR */ +#define SAR_V2_RANGE_INTR_RANGE_INTR_Pos 0UL +#define SAR_V2_RANGE_INTR_RANGE_INTR_Msk 0xFFFFUL +/* SAR.RANGE_INTR_SET */ +#define SAR_V2_RANGE_INTR_SET_RANGE_SET_Pos 0UL +#define SAR_V2_RANGE_INTR_SET_RANGE_SET_Msk 0xFFFFUL +/* SAR.RANGE_INTR_MASK */ +#define SAR_V2_RANGE_INTR_MASK_RANGE_MASK_Pos 0UL +#define SAR_V2_RANGE_INTR_MASK_RANGE_MASK_Msk 0xFFFFUL +/* SAR.RANGE_INTR_MASKED */ +#define SAR_V2_RANGE_INTR_MASKED_RANGE_MASKED_Pos 0UL +#define SAR_V2_RANGE_INTR_MASKED_RANGE_MASKED_Msk 0xFFFFUL +/* SAR.INTR_CAUSE */ +#define SAR_V2_INTR_CAUSE_EOS_MASKED_MIR_Pos 0UL +#define SAR_V2_INTR_CAUSE_EOS_MASKED_MIR_Msk 0x1UL +#define SAR_V2_INTR_CAUSE_OVERFLOW_MASKED_MIR_Pos 1UL +#define SAR_V2_INTR_CAUSE_OVERFLOW_MASKED_MIR_Msk 0x2UL +#define SAR_V2_INTR_CAUSE_FW_COLLISION_MASKED_MIR_Pos 2UL +#define SAR_V2_INTR_CAUSE_FW_COLLISION_MASKED_MIR_Msk 0x4UL +#define SAR_V2_INTR_CAUSE_DSI_COLLISION_MASKED_MIR_Pos 3UL +#define SAR_V2_INTR_CAUSE_DSI_COLLISION_MASKED_MIR_Msk 0x8UL +#define SAR_V2_INTR_CAUSE_INJ_EOC_MASKED_MIR_Pos 4UL +#define SAR_V2_INTR_CAUSE_INJ_EOC_MASKED_MIR_Msk 0x10UL +#define SAR_V2_INTR_CAUSE_INJ_SATURATE_MASKED_MIR_Pos 5UL +#define SAR_V2_INTR_CAUSE_INJ_SATURATE_MASKED_MIR_Msk 0x20UL +#define SAR_V2_INTR_CAUSE_INJ_RANGE_MASKED_MIR_Pos 6UL +#define SAR_V2_INTR_CAUSE_INJ_RANGE_MASKED_MIR_Msk 0x40UL +#define SAR_V2_INTR_CAUSE_INJ_COLLISION_MASKED_MIR_Pos 7UL +#define SAR_V2_INTR_CAUSE_INJ_COLLISION_MASKED_MIR_Msk 0x80UL +#define SAR_V2_INTR_CAUSE_SATURATE_MASKED_RED_Pos 30UL +#define SAR_V2_INTR_CAUSE_SATURATE_MASKED_RED_Msk 0x40000000UL +#define SAR_V2_INTR_CAUSE_RANGE_MASKED_RED_Pos 31UL +#define SAR_V2_INTR_CAUSE_RANGE_MASKED_RED_Msk 0x80000000UL +/* SAR.STATUS */ +#define SAR_V2_STATUS_CUR_CHAN_Pos 0UL +#define SAR_V2_STATUS_CUR_CHAN_Msk 0x1FUL +#define SAR_V2_STATUS_SW_VREF_NEG_Pos 30UL +#define SAR_V2_STATUS_SW_VREF_NEG_Msk 0x40000000UL +#define SAR_V2_STATUS_BUSY_Pos 31UL +#define SAR_V2_STATUS_BUSY_Msk 0x80000000UL +/* SAR.AVG_STAT */ +#define SAR_V2_AVG_STAT_CUR_AVG_ACCU_Pos 0UL +#define SAR_V2_AVG_STAT_CUR_AVG_ACCU_Msk 0xFFFFFUL +#define SAR_V2_AVG_STAT_INTRLV_BUSY_Pos 23UL +#define SAR_V2_AVG_STAT_INTRLV_BUSY_Msk 0x800000UL +#define SAR_V2_AVG_STAT_CUR_AVG_CNT_Pos 24UL +#define SAR_V2_AVG_STAT_CUR_AVG_CNT_Msk 0xFF000000UL +/* SAR.MUX_SWITCH0 */ +#define SAR_V2_MUX_SWITCH0_MUX_FW_P0_VPLUS_Pos 0UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P0_VPLUS_Msk 0x1UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P1_VPLUS_Pos 1UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P1_VPLUS_Msk 0x2UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P2_VPLUS_Pos 2UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P2_VPLUS_Msk 0x4UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P3_VPLUS_Pos 3UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P3_VPLUS_Msk 0x8UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P4_VPLUS_Pos 4UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P4_VPLUS_Msk 0x10UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P5_VPLUS_Pos 5UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P5_VPLUS_Msk 0x20UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P6_VPLUS_Pos 6UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P6_VPLUS_Msk 0x40UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P7_VPLUS_Pos 7UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P7_VPLUS_Msk 0x80UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P0_VMINUS_Pos 8UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P0_VMINUS_Msk 0x100UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P1_VMINUS_Pos 9UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P1_VMINUS_Msk 0x200UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P2_VMINUS_Pos 10UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P2_VMINUS_Msk 0x400UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P3_VMINUS_Pos 11UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P3_VMINUS_Msk 0x800UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P4_VMINUS_Pos 12UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P4_VMINUS_Msk 0x1000UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P5_VMINUS_Pos 13UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P5_VMINUS_Msk 0x2000UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P6_VMINUS_Pos 14UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P6_VMINUS_Msk 0x4000UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P7_VMINUS_Pos 15UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P7_VMINUS_Msk 0x8000UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_VSSA_VMINUS_Pos 16UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_VSSA_VMINUS_Msk 0x10000UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_TEMP_VPLUS_Pos 17UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_TEMP_VPLUS_Msk 0x20000UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_AMUXBUSA_VPLUS_Pos 18UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_AMUXBUSA_VPLUS_Msk 0x40000UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_AMUXBUSB_VPLUS_Pos 19UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_AMUXBUSB_VPLUS_Msk 0x80000UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_AMUXBUSA_VMINUS_Pos 20UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_AMUXBUSA_VMINUS_Msk 0x100000UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_AMUXBUSB_VMINUS_Pos 21UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_AMUXBUSB_VMINUS_Msk 0x200000UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_SARBUS0_VPLUS_Pos 22UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_SARBUS0_VPLUS_Msk 0x400000UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_SARBUS1_VPLUS_Pos 23UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_SARBUS1_VPLUS_Msk 0x800000UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_SARBUS0_VMINUS_Pos 24UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_SARBUS0_VMINUS_Msk 0x1000000UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_SARBUS1_VMINUS_Pos 25UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_SARBUS1_VMINUS_Msk 0x2000000UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P4_COREIO0_Pos 26UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P4_COREIO0_Msk 0x4000000UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P5_COREIO1_Pos 27UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P5_COREIO1_Msk 0x8000000UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P6_COREIO2_Pos 28UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P6_COREIO2_Msk 0x10000000UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P7_COREIO3_Pos 29UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P7_COREIO3_Msk 0x20000000UL +/* SAR.MUX_SWITCH_CLEAR0 */ +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P0_VPLUS_Pos 0UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P0_VPLUS_Msk 0x1UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P1_VPLUS_Pos 1UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P1_VPLUS_Msk 0x2UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P2_VPLUS_Pos 2UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P2_VPLUS_Msk 0x4UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P3_VPLUS_Pos 3UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P3_VPLUS_Msk 0x8UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P4_VPLUS_Pos 4UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P4_VPLUS_Msk 0x10UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P5_VPLUS_Pos 5UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P5_VPLUS_Msk 0x20UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P6_VPLUS_Pos 6UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P6_VPLUS_Msk 0x40UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P7_VPLUS_Pos 7UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P7_VPLUS_Msk 0x80UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P0_VMINUS_Pos 8UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P0_VMINUS_Msk 0x100UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P1_VMINUS_Pos 9UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P1_VMINUS_Msk 0x200UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P2_VMINUS_Pos 10UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P2_VMINUS_Msk 0x400UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P3_VMINUS_Pos 11UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P3_VMINUS_Msk 0x800UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P4_VMINUS_Pos 12UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P4_VMINUS_Msk 0x1000UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P5_VMINUS_Pos 13UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P5_VMINUS_Msk 0x2000UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P6_VMINUS_Pos 14UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P6_VMINUS_Msk 0x4000UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P7_VMINUS_Pos 15UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P7_VMINUS_Msk 0x8000UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_VSSA_VMINUS_Pos 16UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_VSSA_VMINUS_Msk 0x10000UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_TEMP_VPLUS_Pos 17UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_TEMP_VPLUS_Msk 0x20000UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_AMUXBUSA_VPLUS_Pos 18UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_AMUXBUSA_VPLUS_Msk 0x40000UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_AMUXBUSB_VPLUS_Pos 19UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_AMUXBUSB_VPLUS_Msk 0x80000UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_AMUXBUSA_VMINUS_Pos 20UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_AMUXBUSA_VMINUS_Msk 0x100000UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_AMUXBUSB_VMINUS_Pos 21UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_AMUXBUSB_VMINUS_Msk 0x200000UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_SARBUS0_VPLUS_Pos 22UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_SARBUS0_VPLUS_Msk 0x400000UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_SARBUS1_VPLUS_Pos 23UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_SARBUS1_VPLUS_Msk 0x800000UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_SARBUS0_VMINUS_Pos 24UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_SARBUS0_VMINUS_Msk 0x1000000UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_SARBUS1_VMINUS_Pos 25UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_SARBUS1_VMINUS_Msk 0x2000000UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P4_COREIO0_Pos 26UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P4_COREIO0_Msk 0x4000000UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P5_COREIO1_Pos 27UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P5_COREIO1_Msk 0x8000000UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P6_COREIO2_Pos 28UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P6_COREIO2_Msk 0x10000000UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P7_COREIO3_Pos 29UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P7_COREIO3_Msk 0x20000000UL +/* SAR.MUX_SWITCH_SQ_CTRL */ +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P0_Pos 0UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P0_Msk 0x1UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P1_Pos 1UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P1_Msk 0x2UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P2_Pos 2UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P2_Msk 0x4UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P3_Pos 3UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P3_Msk 0x8UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P4_Pos 4UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P4_Msk 0x10UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P5_Pos 5UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P5_Msk 0x20UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P6_Pos 6UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P6_Msk 0x40UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P7_Pos 7UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P7_Msk 0x80UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_VSSA_Pos 16UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_VSSA_Msk 0x10000UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_TEMP_Pos 17UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_TEMP_Msk 0x20000UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_AMUXBUSA_Pos 18UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_AMUXBUSA_Msk 0x40000UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_AMUXBUSB_Pos 19UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_AMUXBUSB_Msk 0x80000UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_SARBUS0_Pos 22UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_SARBUS0_Msk 0x400000UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_SARBUS1_Pos 23UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_SARBUS1_Msk 0x800000UL +/* SAR.MUX_SWITCH_STATUS */ +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P0_VPLUS_Pos 0UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P0_VPLUS_Msk 0x1UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P1_VPLUS_Pos 1UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P1_VPLUS_Msk 0x2UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P2_VPLUS_Pos 2UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P2_VPLUS_Msk 0x4UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P3_VPLUS_Pos 3UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P3_VPLUS_Msk 0x8UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P4_VPLUS_Pos 4UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P4_VPLUS_Msk 0x10UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P5_VPLUS_Pos 5UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P5_VPLUS_Msk 0x20UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P6_VPLUS_Pos 6UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P6_VPLUS_Msk 0x40UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P7_VPLUS_Pos 7UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P7_VPLUS_Msk 0x80UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P0_VMINUS_Pos 8UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P0_VMINUS_Msk 0x100UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P1_VMINUS_Pos 9UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P1_VMINUS_Msk 0x200UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P2_VMINUS_Pos 10UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P2_VMINUS_Msk 0x400UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P3_VMINUS_Pos 11UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P3_VMINUS_Msk 0x800UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P4_VMINUS_Pos 12UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P4_VMINUS_Msk 0x1000UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P5_VMINUS_Pos 13UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P5_VMINUS_Msk 0x2000UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P6_VMINUS_Pos 14UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P6_VMINUS_Msk 0x4000UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P7_VMINUS_Pos 15UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P7_VMINUS_Msk 0x8000UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_VSSA_VMINUS_Pos 16UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_VSSA_VMINUS_Msk 0x10000UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_TEMP_VPLUS_Pos 17UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_TEMP_VPLUS_Msk 0x20000UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_AMUXBUSA_VPLUS_Pos 18UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_AMUXBUSA_VPLUS_Msk 0x40000UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_AMUXBUSB_VPLUS_Pos 19UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_AMUXBUSB_VPLUS_Msk 0x80000UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_AMUXBUSA_VMINUS_Pos 20UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_AMUXBUSA_VMINUS_Msk 0x100000UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_AMUXBUSB_VMINUS_Pos 21UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_AMUXBUSB_VMINUS_Msk 0x200000UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_SARBUS0_VPLUS_Pos 22UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_SARBUS0_VPLUS_Msk 0x400000UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_SARBUS1_VPLUS_Pos 23UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_SARBUS1_VPLUS_Msk 0x800000UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_SARBUS0_VMINUS_Pos 24UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_SARBUS0_VMINUS_Msk 0x1000000UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_SARBUS1_VMINUS_Pos 25UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_SARBUS1_VMINUS_Msk 0x2000000UL + + +#endif /* _CYIP_SAR_V2_H_ */ + + +/* [] END OF FILE */ diff --git a/devices/include/ip/cyip_sflash.h b/devices/include/ip/cyip_sflash.h index f824008..16fcf8f 100644 --- a/devices/include/ip/cyip_sflash.h +++ b/devices/include/ip/cyip_sflash.h @@ -5,7 +5,7 @@ * SFLASH IP definitions * * \note -* Generator version: 1.5.0.1287 +* Generator version: 1.5.1.36 * ******************************************************************************** * \copyright @@ -47,7 +47,14 @@ typedef struct { __IOM uint16_t FAMILY_ID; /*!< 0x0000000C Indicates Family ID of the device */ __IM uint16_t RESERVED2[3]; __IOM uint32_t CPUSS_WOUNDING; /*!< 0x00000014 CPUSS Wounding */ - __IM uint32_t RESERVED3[378]; + __IM uint32_t RESERVED3[2]; + __IOM uint8_t SORT_REV[3]; /*!< 0x00000020 SORT Revision */ + __IOM uint8_t CRI_BB_REV; /*!< 0x00000023 CRI BB Revision */ + __IOM uint8_t CRI_AB_REV; /*!< 0x00000024 CRI AB Revision */ + __IOM uint8_t CHI_AB_REV; /*!< 0x00000025 CHI AB Revision */ + __IM uint16_t RESERVED4[43]; + __IOM uint32_t FB_FLAGS; /*!< 0x0000007C Flash boot flags */ + __IM uint32_t RESERVED5[352]; __IOM uint8_t DIE_LOT[3]; /*!< 0x00000600 Lot Number (3 bytes) */ __IOM uint8_t DIE_WAFER; /*!< 0x00000603 Wafer Number */ __IOM uint8_t DIE_X; /*!< 0x00000604 X Position on Wafer, CRI Pass/Fail Bin */ @@ -57,20 +64,20 @@ typedef struct { __IOM uint8_t DIE_DAY; /*!< 0x00000608 Day number */ __IOM uint8_t DIE_MONTH; /*!< 0x00000609 Month number */ __IOM uint8_t DIE_YEAR; /*!< 0x0000060A Year number */ - __IM uint8_t RESERVED4[61]; + __IM uint8_t RESERVED6[61]; __IOM uint16_t SAR_TEMP_MULTIPLIER; /*!< 0x00000648 SAR Temperature Sensor Multiplication Factor */ __IOM uint16_t SAR_TEMP_OFFSET; /*!< 0x0000064A SAR Temperature Sensor Offset */ - __IM uint32_t RESERVED5[8]; + __IM uint32_t RESERVED7[8]; __IOM uint32_t CSP_PANEL_ID; /*!< 0x0000066C CSP Panel Id to record panel ID of CSP die */ - __IM uint32_t RESERVED6[52]; + __IM uint32_t RESERVED8[52]; __IOM uint8_t LDO_0P9V_TRIM; /*!< 0x00000740 LDO_0P9V_TRIM */ __IOM uint8_t LDO_1P1V_TRIM; /*!< 0x00000741 LDO_1P1V_TRIM */ - __IM uint16_t RESERVED7[95]; + __IM uint16_t RESERVED9[95]; __IOM uint32_t BLE_DEVICE_ADDRESS[128]; /*!< 0x00000800 BLE_DEVICE_ADDRESS */ __IOM uint32_t USER_FREE_ROW1[128]; /*!< 0x00000A00 USER_FREE_ROW1 */ __IOM uint32_t USER_FREE_ROW2[128]; /*!< 0x00000C00 USER_FREE_ROW2 */ __IOM uint32_t USER_FREE_ROW3[128]; /*!< 0x00000E00 USER_FREE_ROW3 */ - __IM uint32_t RESERVED8[302]; + __IM uint32_t RESERVED10[302]; __IOM uint8_t DEVICE_UID[16]; /*!< 0x000014B8 Unique Identifier Number for each device */ __IOM uint8_t MASTER_KEY[16]; /*!< 0x000014C8 Master key to change other keys */ __IOM uint32_t STANDARD_SMPU_STRUCT_SLAVE_ADDR[16]; /*!< 0x000014D8 Standard SMPU STRUCT Slave Address value */ @@ -78,36 +85,36 @@ typedef struct { __IOM uint32_t STANDARD_SMPU_STRUCT_MASTER_ATTR[16]; /*!< 0x00001558 Standard SMPU STRUCT Master Attribute value */ __IOM uint32_t STANDARD_MPU_STRUCT[16]; /*!< 0x00001598 Standard MPU STRUCT */ __IOM uint32_t STANDARD_PPU_STRUCT[16]; /*!< 0x000015D8 Standard PPU STRUCT */ - __IM uint32_t RESERVED9[122]; + __IM uint32_t RESERVED11[122]; __IOM uint16_t PILO_FREQ_STEP; /*!< 0x00001800 Resolution step for PILO at class in BCD format */ - __IM uint16_t RESERVED10; + __IM uint16_t RESERVED12; __IOM uint32_t CSDV2_CSD0_ADC_VREF0; /*!< 0x00001804 CSD 1p2 & 1p6 voltage levels for accuracy */ __IOM uint32_t CSDV2_CSD0_ADC_VREF1; /*!< 0x00001808 CSD 2p1 & 0p8 voltage levels for accuracy */ __IOM uint32_t CSDV2_CSD0_ADC_VREF2; /*!< 0x0000180C CSD calibration spare voltage level for accuracy */ __IOM uint32_t PWR_TRIM_WAKE_CTL; /*!< 0x00001810 Wakeup delay */ - __IM uint16_t RESERVED11; + __IM uint16_t RESERVED13; __IOM uint16_t RADIO_LDO_TRIMS; /*!< 0x00001816 Radio LDO Trims */ __IOM uint32_t CPUSS_TRIM_ROM_CTL_ULP; /*!< 0x00001818 CPUSS TRIM ROM CTL ULP value */ __IOM uint32_t CPUSS_TRIM_RAM_CTL_ULP; /*!< 0x0000181C CPUSS TRIM RAM CTL ULP value */ __IOM uint32_t CPUSS_TRIM_ROM_CTL_LP; /*!< 0x00001820 CPUSS TRIM ROM CTL LP value */ __IOM uint32_t CPUSS_TRIM_RAM_CTL_LP; /*!< 0x00001824 CPUSS TRIM RAM CTL LP value */ - __IM uint32_t RESERVED12[7]; + __IM uint32_t RESERVED14[7]; __IOM uint32_t CPUSS_TRIM_ROM_CTL_HALF_ULP; /*!< 0x00001844 CPUSS TRIM ROM CTL HALF ULP value */ __IOM uint32_t CPUSS_TRIM_RAM_CTL_HALF_ULP; /*!< 0x00001848 CPUSS TRIM RAM CTL HALF ULP value */ __IOM uint32_t CPUSS_TRIM_ROM_CTL_HALF_LP; /*!< 0x0000184C CPUSS TRIM ROM CTL HALF LP value */ __IOM uint32_t CPUSS_TRIM_RAM_CTL_HALF_LP; /*!< 0x00001850 CPUSS TRIM RAM CTL HALF LP value */ - __IM uint32_t RESERVED13[491]; + __IM uint32_t RESERVED15[491]; __IOM uint32_t FLASH_BOOT_OBJECT_SIZE; /*!< 0x00002000 Flash Boot - Object Size */ __IOM uint32_t FLASH_BOOT_APP_ID; /*!< 0x00002004 Flash Boot - Application ID/Version */ __IOM uint32_t FLASH_BOOT_ATTRIBUTE; /*!< 0x00002008 N/A */ __IOM uint32_t FLASH_BOOT_N_CORES; /*!< 0x0000200C Flash Boot - Number of Cores(N) */ __IOM uint32_t FLASH_BOOT_VT_OFFSET; /*!< 0x00002010 Flash Boot - Core Vector Table offset */ __IOM uint32_t FLASH_BOOT_CORE_CPUID; /*!< 0x00002014 Flash Boot - Core CPU ID/Core Index */ - __IM uint32_t RESERVED14[48]; + __IM uint32_t RESERVED16[48]; __IOM uint8_t FLASH_BOOT_CODE[14632]; /*!< 0x000020D8 Flash Boot - Code and Data */ __IOM uint8_t PUBLIC_KEY[3072]; /*!< 0x00005A00 Public key for signature verification (max RSA key size 4096) */ __IOM uint32_t BOOT_PROT_SETTINGS[384]; /*!< 0x00006600 Boot protection settings (not present in PSOC6ABLE2) */ - __IM uint32_t RESERVED15[768]; + __IM uint32_t RESERVED17[768]; __IOM uint32_t TOC1_OBJECT_SIZE; /*!< 0x00007800 Object size in bytes for CRC calculation starting from offset 0x00 */ __IOM uint32_t TOC1_MAGIC_NUMBER; /*!< 0x00007804 Magic number(0x01211219) */ @@ -118,7 +125,7 @@ typedef struct { __IOM uint32_t TOC1_FB_OBJECT_ADDR; /*!< 0x00007814 Addresss of FLASH Boot(FB) object that include FLASH patch also */ __IOM uint32_t TOC1_SYSCALL_TABLE_ADDR_UNUSED; /*!< 0x00007818 Unused (Address is Hardcoded in ROM) */ __IOM uint32_t TOC1_OBJECT_ADDR_UNUSED; /*!< 0x0000781C Unused (Address is Hardcoded in ROM) */ - __IM uint32_t RESERVED16[119]; + __IM uint32_t RESERVED18[119]; __IOM uint32_t TOC1_CRC_ADDR; /*!< 0x000079FC Upper 2 bytes contain CRC16-CCITT and lower 2 bytes are 0 */ __IOM uint32_t RTOC1_OBJECT_SIZE; /*!< 0x00007A00 Redundant Object size in bytes for CRC calculation starting from offset 0x00 */ @@ -131,7 +138,7 @@ typedef struct { patch also */ __IOM uint32_t RTOC1_SYSCALL_TABLE_ADDR_UNUSED; /*!< 0x00007A18 Redundant Unused (Address is Hardcoded in ROM) */ __IOM uint32_t RTOC1_OBJECT_ADDR_UNUSED; /*!< 0x00007A1C Redundant Unused (Address is Hardcoded in ROM) */ - __IM uint32_t RESERVED17[119]; + __IM uint32_t RESERVED19[119]; __IOM uint32_t RTOC1_CRC_ADDR; /*!< 0x00007BFC Redundant CRC,Upper 2 bytes contain CRC16-CCITT and lower 2 bytes are 0 */ __IOM uint32_t TOC2_OBJECT_SIZE; /*!< 0x00007C00 Object size in bytes for CRC calculation starting from offset @@ -151,7 +158,7 @@ typedef struct { SECURE_HASH(SHASH) */ __IOM uint32_t TOC2_SIGNATURE_VERIF_KEY; /*!< 0x00007C24 Address of signature verification key (0 if none).The object is signature specific key. It is the public key in case of RSA */ - __IM uint32_t RESERVED18[115]; + __IM uint32_t RESERVED20[115]; __IOM uint32_t TOC2_REVISION; /*!< 0x00007DF4 Indicates TOC2 Revision. It is not used now. */ __IOM uint32_t TOC2_FLAGS; /*!< 0x00007DF8 TOC2_FLAGS */ __IOM uint32_t TOC2_CRC_ADDR; /*!< 0x00007DFC CRC,Upper 2 bytes contain CRC16-CCITT and lower 2 bytes are 0 */ @@ -173,7 +180,7 @@ typedef struct { __IOM uint32_t RTOC2_SIGNATURE_VERIF_KEY; /*!< 0x00007E24 Redundant Address of signature verification key (0 if none).The object is signature specific key. It is the public key in case of RSA */ - __IM uint32_t RESERVED19[115]; + __IM uint32_t RESERVED21[115]; __IOM uint32_t RTOC2_REVISION; /*!< 0x00007FF4 Indicates RTOC2 Revision. It is not used now. */ __IOM uint32_t RTOC2_FLAGS; /*!< 0x00007FF8 RTOC2_FLAGS */ __IOM uint32_t RTOC2_CRC_ADDR; /*!< 0x00007FFC Redundant CRC,Upper 2 bytes contain CRC16-CCITT and lower 2 @@ -193,6 +200,25 @@ typedef struct { /* SFLASH.CPUSS_WOUNDING */ #define SFLASH_CPUSS_WOUNDING_CPUSS_WOUNDING_Pos 0UL #define SFLASH_CPUSS_WOUNDING_CPUSS_WOUNDING_Msk 0xFFFFFFFFUL +/* SFLASH.SORT_REV */ +#define SFLASH_SORT_REV_DATA_Pos 0UL +#define SFLASH_SORT_REV_DATA_Msk 0xFFUL +/* SFLASH.CRI_BB_REV */ +#define SFLASH_CRI_BB_REV_DATA_Pos 0UL +#define SFLASH_CRI_BB_REV_DATA_Msk 0xFFUL +/* SFLASH.CRI_AB_REV */ +#define SFLASH_CRI_AB_REV_DATA_Pos 0UL +#define SFLASH_CRI_AB_REV_DATA_Msk 0xFFUL +/* SFLASH.CHI_AB_REV */ +#define SFLASH_CHI_AB_REV_DATA_Pos 0UL +#define SFLASH_CHI_AB_REV_DATA_Msk 0xFFUL +/* SFLASH.FB_FLAGS */ +#define SFLASH_FB_FLAGS_FB_PIN_CTL_Pos 0UL +#define SFLASH_FB_FLAGS_FB_PIN_CTL_Msk 0x3UL +#define SFLASH_FB_FLAGS_FB_RSA3K_CTL_Pos 2UL +#define SFLASH_FB_FLAGS_FB_RSA3K_CTL_Msk 0xCUL +#define SFLASH_FB_FLAGS_FB_RSA4K_CTL_Pos 4UL +#define SFLASH_FB_FLAGS_FB_RSA4K_CTL_Msk 0x30UL /* SFLASH.DIE_LOT */ #define SFLASH_DIE_LOT_LOT_Pos 0UL #define SFLASH_DIE_LOT_LOT_Msk 0xFFUL diff --git a/devices/include/ip/cyip_tcpwm_v2.h b/devices/include/ip/cyip_tcpwm_v2.h new file mode 100644 index 0000000..fadb32d --- /dev/null +++ b/devices/include/ip/cyip_tcpwm_v2.h @@ -0,0 +1,272 @@ +/***************************************************************************//** +* \file cyip_tcpwm_v2.h +* +* \brief +* TCPWM IP definitions +* +* \note +* Generator version: 1.5.1.36 +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CYIP_TCPWM_V2_H_ +#define _CYIP_TCPWM_V2_H_ + +#include "cyip_headers.h" + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM_GRP_CNT_V2_SECTION_SIZE 0x00000080UL +#define TCPWM_GRP_V2_SECTION_SIZE 0x00008000UL +#define TCPWM_V2_SECTION_SIZE 0x00020000UL + +/** + * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT) + */ +typedef struct { + __IOM uint32_t CTRL; /*!< 0x00000000 Counter control register */ + __IM uint32_t STATUS; /*!< 0x00000004 Counter status register */ + __IOM uint32_t COUNTER; /*!< 0x00000008 Counter count register */ + __IM uint32_t RESERVED; + __IOM uint32_t CC0; /*!< 0x00000010 Counter compare/capture 0 register */ + __IOM uint32_t CC0_BUFF; /*!< 0x00000014 Counter buffered compare/capture 0 register */ + __IOM uint32_t CC1; /*!< 0x00000018 Counter compare/capture 1 register */ + __IOM uint32_t CC1_BUFF; /*!< 0x0000001C Counter buffered compare/capture 1 register */ + __IOM uint32_t PERIOD; /*!< 0x00000020 Counter period register */ + __IOM uint32_t PERIOD_BUFF; /*!< 0x00000024 Counter buffered period register */ + __IOM uint32_t LINE_SEL; /*!< 0x00000028 Counter line selection register */ + __IOM uint32_t LINE_SEL_BUFF; /*!< 0x0000002C Counter buffered line selection register */ + __IOM uint32_t DT; /*!< 0x00000030 Counter PWM dead time register */ + __IM uint32_t RESERVED1[3]; + __IOM uint32_t TR_CMD; /*!< 0x00000040 Counter trigger command register */ + __IOM uint32_t TR_IN_SEL0; /*!< 0x00000044 Counter input trigger selection register 0 */ + __IOM uint32_t TR_IN_SEL1; /*!< 0x00000048 Counter input trigger selection register 1 */ + __IOM uint32_t TR_IN_EDGE_SEL; /*!< 0x0000004C Counter input trigger edge selection register */ + __IOM uint32_t TR_PWM_CTRL; /*!< 0x00000050 Counter trigger PWM control register */ + __IOM uint32_t TR_OUT_SEL; /*!< 0x00000054 Counter output trigger selection register */ + __IM uint32_t RESERVED2[6]; + __IOM uint32_t INTR; /*!< 0x00000070 Interrupt request register */ + __IOM uint32_t INTR_SET; /*!< 0x00000074 Interrupt set request register */ + __IOM uint32_t INTR_MASK; /*!< 0x00000078 Interrupt mask register */ + __IM uint32_t INTR_MASKED; /*!< 0x0000007C Interrupt masked request register */ +} TCPWM_GRP_CNT_V2_Type; /*!< Size = 128 (0x80) */ + +/** + * \brief Group of counters (TCPWM_GRP) + */ +typedef struct { + TCPWM_GRP_CNT_V2_Type CNT[256]; /*!< 0x00000000 Timer/Counter/PWM Counter Module */ +} TCPWM_GRP_V2_Type; /*!< Size = 32768 (0x8000) */ + +/** + * \brief Timer/Counter/PWM (TCPWM) + */ +typedef struct { + TCPWM_GRP_V2_Type GRP[4]; /*!< 0x00000000 Group of counters */ +} TCPWM_V2_Type; /*!< Size = 131072 (0x20000) */ + + +/* TCPWM_GRP_CNT.CTRL */ +#define TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_CC0_Pos 0UL +#define TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_CC0_Msk 0x1UL +#define TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_CC1_Pos 1UL +#define TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_CC1_Msk 0x2UL +#define TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_PERIOD_Pos 2UL +#define TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_PERIOD_Msk 0x4UL +#define TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_LINE_SEL_Pos 3UL +#define TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_LINE_SEL_Msk 0x8UL +#define TCPWM_GRP_CNT_V2_CTRL_CC0_MATCH_UP_EN_Pos 4UL +#define TCPWM_GRP_CNT_V2_CTRL_CC0_MATCH_UP_EN_Msk 0x10UL +#define TCPWM_GRP_CNT_V2_CTRL_CC0_MATCH_DOWN_EN_Pos 5UL +#define TCPWM_GRP_CNT_V2_CTRL_CC0_MATCH_DOWN_EN_Msk 0x20UL +#define TCPWM_GRP_CNT_V2_CTRL_CC1_MATCH_UP_EN_Pos 6UL +#define TCPWM_GRP_CNT_V2_CTRL_CC1_MATCH_UP_EN_Msk 0x40UL +#define TCPWM_GRP_CNT_V2_CTRL_CC1_MATCH_DOWN_EN_Pos 7UL +#define TCPWM_GRP_CNT_V2_CTRL_CC1_MATCH_DOWN_EN_Msk 0x80UL +#define TCPWM_GRP_CNT_V2_CTRL_PWM_IMM_KILL_Pos 8UL +#define TCPWM_GRP_CNT_V2_CTRL_PWM_IMM_KILL_Msk 0x100UL +#define TCPWM_GRP_CNT_V2_CTRL_PWM_STOP_ON_KILL_Pos 9UL +#define TCPWM_GRP_CNT_V2_CTRL_PWM_STOP_ON_KILL_Msk 0x200UL +#define TCPWM_GRP_CNT_V2_CTRL_PWM_SYNC_KILL_Pos 10UL +#define TCPWM_GRP_CNT_V2_CTRL_PWM_SYNC_KILL_Msk 0x400UL +#define TCPWM_GRP_CNT_V2_CTRL_PWM_DISABLE_MODE_Pos 12UL +#define TCPWM_GRP_CNT_V2_CTRL_PWM_DISABLE_MODE_Msk 0x3000UL +#define TCPWM_GRP_CNT_V2_CTRL_UP_DOWN_MODE_Pos 16UL +#define TCPWM_GRP_CNT_V2_CTRL_UP_DOWN_MODE_Msk 0x30000UL +#define TCPWM_GRP_CNT_V2_CTRL_ONE_SHOT_Pos 18UL +#define TCPWM_GRP_CNT_V2_CTRL_ONE_SHOT_Msk 0x40000UL +#define TCPWM_GRP_CNT_V2_CTRL_QUAD_ENCODING_MODE_Pos 20UL +#define TCPWM_GRP_CNT_V2_CTRL_QUAD_ENCODING_MODE_Msk 0x300000UL +#define TCPWM_GRP_CNT_V2_CTRL_MODE_Pos 24UL +#define TCPWM_GRP_CNT_V2_CTRL_MODE_Msk 0x7000000UL +#define TCPWM_GRP_CNT_V2_CTRL_DBG_FREEZE_EN_Pos 30UL +#define TCPWM_GRP_CNT_V2_CTRL_DBG_FREEZE_EN_Msk 0x40000000UL +#define TCPWM_GRP_CNT_V2_CTRL_ENABLED_Pos 31UL +#define TCPWM_GRP_CNT_V2_CTRL_ENABLED_Msk 0x80000000UL +/* TCPWM_GRP_CNT.STATUS */ +#define TCPWM_GRP_CNT_V2_STATUS_DOWN_Pos 0UL +#define TCPWM_GRP_CNT_V2_STATUS_DOWN_Msk 0x1UL +#define TCPWM_GRP_CNT_V2_STATUS_TR_CAPTURE0_Pos 4UL +#define TCPWM_GRP_CNT_V2_STATUS_TR_CAPTURE0_Msk 0x10UL +#define TCPWM_GRP_CNT_V2_STATUS_TR_COUNT_Pos 5UL +#define TCPWM_GRP_CNT_V2_STATUS_TR_COUNT_Msk 0x20UL +#define TCPWM_GRP_CNT_V2_STATUS_TR_RELOAD_Pos 6UL +#define TCPWM_GRP_CNT_V2_STATUS_TR_RELOAD_Msk 0x40UL +#define TCPWM_GRP_CNT_V2_STATUS_TR_STOP_Pos 7UL +#define TCPWM_GRP_CNT_V2_STATUS_TR_STOP_Msk 0x80UL +#define TCPWM_GRP_CNT_V2_STATUS_TR_START_Pos 8UL +#define TCPWM_GRP_CNT_V2_STATUS_TR_START_Msk 0x100UL +#define TCPWM_GRP_CNT_V2_STATUS_TR_CAPTURE1_Pos 9UL +#define TCPWM_GRP_CNT_V2_STATUS_TR_CAPTURE1_Msk 0x200UL +#define TCPWM_GRP_CNT_V2_STATUS_LINE_OUT_Pos 10UL +#define TCPWM_GRP_CNT_V2_STATUS_LINE_OUT_Msk 0x400UL +#define TCPWM_GRP_CNT_V2_STATUS_LINE_COMPL_OUT_Pos 11UL +#define TCPWM_GRP_CNT_V2_STATUS_LINE_COMPL_OUT_Msk 0x800UL +#define TCPWM_GRP_CNT_V2_STATUS_RUNNING_Pos 15UL +#define TCPWM_GRP_CNT_V2_STATUS_RUNNING_Msk 0x8000UL +#define TCPWM_GRP_CNT_V2_STATUS_DT_CNT_L_Pos 16UL +#define TCPWM_GRP_CNT_V2_STATUS_DT_CNT_L_Msk 0xFF0000UL +#define TCPWM_GRP_CNT_V2_STATUS_DT_CNT_H_Pos 24UL +#define TCPWM_GRP_CNT_V2_STATUS_DT_CNT_H_Msk 0xFF000000UL +/* TCPWM_GRP_CNT.COUNTER */ +#define TCPWM_GRP_CNT_V2_COUNTER_COUNTER_Pos 0UL +#define TCPWM_GRP_CNT_V2_COUNTER_COUNTER_Msk 0xFFFFFFFFUL +/* TCPWM_GRP_CNT.CC0 */ +#define TCPWM_GRP_CNT_V2_CC0_CC_Pos 0UL +#define TCPWM_GRP_CNT_V2_CC0_CC_Msk 0xFFFFFFFFUL +/* TCPWM_GRP_CNT.CC0_BUFF */ +#define TCPWM_GRP_CNT_V2_CC0_BUFF_CC_Pos 0UL +#define TCPWM_GRP_CNT_V2_CC0_BUFF_CC_Msk 0xFFFFFFFFUL +/* TCPWM_GRP_CNT.CC1 */ +#define TCPWM_GRP_CNT_V2_CC1_CC_Pos 0UL +#define TCPWM_GRP_CNT_V2_CC1_CC_Msk 0xFFFFFFFFUL +/* TCPWM_GRP_CNT.CC1_BUFF */ +#define TCPWM_GRP_CNT_V2_CC1_BUFF_CC_Pos 0UL +#define TCPWM_GRP_CNT_V2_CC1_BUFF_CC_Msk 0xFFFFFFFFUL +/* TCPWM_GRP_CNT.PERIOD */ +#define TCPWM_GRP_CNT_V2_PERIOD_PERIOD_Pos 0UL +#define TCPWM_GRP_CNT_V2_PERIOD_PERIOD_Msk 0xFFFFFFFFUL +/* TCPWM_GRP_CNT.PERIOD_BUFF */ +#define TCPWM_GRP_CNT_V2_PERIOD_BUFF_PERIOD_Pos 0UL +#define TCPWM_GRP_CNT_V2_PERIOD_BUFF_PERIOD_Msk 0xFFFFFFFFUL +/* TCPWM_GRP_CNT.LINE_SEL */ +#define TCPWM_GRP_CNT_V2_LINE_SEL_OUT_SEL_Pos 0UL +#define TCPWM_GRP_CNT_V2_LINE_SEL_OUT_SEL_Msk 0x7UL +#define TCPWM_GRP_CNT_V2_LINE_SEL_COMPL_OUT_SEL_Pos 4UL +#define TCPWM_GRP_CNT_V2_LINE_SEL_COMPL_OUT_SEL_Msk 0x70UL +/* TCPWM_GRP_CNT.LINE_SEL_BUFF */ +#define TCPWM_GRP_CNT_V2_LINE_SEL_BUFF_OUT_SEL_Pos 0UL +#define TCPWM_GRP_CNT_V2_LINE_SEL_BUFF_OUT_SEL_Msk 0x7UL +#define TCPWM_GRP_CNT_V2_LINE_SEL_BUFF_COMPL_OUT_SEL_Pos 4UL +#define TCPWM_GRP_CNT_V2_LINE_SEL_BUFF_COMPL_OUT_SEL_Msk 0x70UL +/* TCPWM_GRP_CNT.DT */ +#define TCPWM_GRP_CNT_V2_DT_DT_LINE_OUT_L_Pos 0UL +#define TCPWM_GRP_CNT_V2_DT_DT_LINE_OUT_L_Msk 0xFFUL +#define TCPWM_GRP_CNT_V2_DT_DT_LINE_OUT_H_Pos 8UL +#define TCPWM_GRP_CNT_V2_DT_DT_LINE_OUT_H_Msk 0xFF00UL +#define TCPWM_GRP_CNT_V2_DT_DT_LINE_COMPL_OUT_Pos 16UL +#define TCPWM_GRP_CNT_V2_DT_DT_LINE_COMPL_OUT_Msk 0xFFFF0000UL +/* TCPWM_GRP_CNT.TR_CMD */ +#define TCPWM_GRP_CNT_V2_TR_CMD_CAPTURE0_Pos 0UL +#define TCPWM_GRP_CNT_V2_TR_CMD_CAPTURE0_Msk 0x1UL +#define TCPWM_GRP_CNT_V2_TR_CMD_RELOAD_Pos 2UL +#define TCPWM_GRP_CNT_V2_TR_CMD_RELOAD_Msk 0x4UL +#define TCPWM_GRP_CNT_V2_TR_CMD_STOP_Pos 3UL +#define TCPWM_GRP_CNT_V2_TR_CMD_STOP_Msk 0x8UL +#define TCPWM_GRP_CNT_V2_TR_CMD_START_Pos 4UL +#define TCPWM_GRP_CNT_V2_TR_CMD_START_Msk 0x10UL +#define TCPWM_GRP_CNT_V2_TR_CMD_CAPTURE1_Pos 5UL +#define TCPWM_GRP_CNT_V2_TR_CMD_CAPTURE1_Msk 0x20UL +/* TCPWM_GRP_CNT.TR_IN_SEL0 */ +#define TCPWM_GRP_CNT_V2_TR_IN_SEL0_CAPTURE0_SEL_Pos 0UL +#define TCPWM_GRP_CNT_V2_TR_IN_SEL0_CAPTURE0_SEL_Msk 0xFFUL +#define TCPWM_GRP_CNT_V2_TR_IN_SEL0_COUNT_SEL_Pos 8UL +#define TCPWM_GRP_CNT_V2_TR_IN_SEL0_COUNT_SEL_Msk 0xFF00UL +#define TCPWM_GRP_CNT_V2_TR_IN_SEL0_RELOAD_SEL_Pos 16UL +#define TCPWM_GRP_CNT_V2_TR_IN_SEL0_RELOAD_SEL_Msk 0xFF0000UL +#define TCPWM_GRP_CNT_V2_TR_IN_SEL0_STOP_SEL_Pos 24UL +#define TCPWM_GRP_CNT_V2_TR_IN_SEL0_STOP_SEL_Msk 0xFF000000UL +/* TCPWM_GRP_CNT.TR_IN_SEL1 */ +#define TCPWM_GRP_CNT_V2_TR_IN_SEL1_START_SEL_Pos 0UL +#define TCPWM_GRP_CNT_V2_TR_IN_SEL1_START_SEL_Msk 0xFFUL +#define TCPWM_GRP_CNT_V2_TR_IN_SEL1_CAPTURE1_SEL_Pos 8UL +#define TCPWM_GRP_CNT_V2_TR_IN_SEL1_CAPTURE1_SEL_Msk 0xFF00UL +/* TCPWM_GRP_CNT.TR_IN_EDGE_SEL */ +#define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_CAPTURE0_EDGE_Pos 0UL +#define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_CAPTURE0_EDGE_Msk 0x3UL +#define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_COUNT_EDGE_Pos 2UL +#define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_COUNT_EDGE_Msk 0xCUL +#define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_RELOAD_EDGE_Pos 4UL +#define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_RELOAD_EDGE_Msk 0x30UL +#define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_STOP_EDGE_Pos 6UL +#define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_STOP_EDGE_Msk 0xC0UL +#define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_START_EDGE_Pos 8UL +#define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_START_EDGE_Msk 0x300UL +#define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_CAPTURE1_EDGE_Pos 10UL +#define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_CAPTURE1_EDGE_Msk 0xC00UL +/* TCPWM_GRP_CNT.TR_PWM_CTRL */ +#define TCPWM_GRP_CNT_V2_TR_PWM_CTRL_CC0_MATCH_MODE_Pos 0UL +#define TCPWM_GRP_CNT_V2_TR_PWM_CTRL_CC0_MATCH_MODE_Msk 0x3UL +#define TCPWM_GRP_CNT_V2_TR_PWM_CTRL_OVERFLOW_MODE_Pos 2UL +#define TCPWM_GRP_CNT_V2_TR_PWM_CTRL_OVERFLOW_MODE_Msk 0xCUL +#define TCPWM_GRP_CNT_V2_TR_PWM_CTRL_UNDERFLOW_MODE_Pos 4UL +#define TCPWM_GRP_CNT_V2_TR_PWM_CTRL_UNDERFLOW_MODE_Msk 0x30UL +#define TCPWM_GRP_CNT_V2_TR_PWM_CTRL_CC1_MATCH_MODE_Pos 6UL +#define TCPWM_GRP_CNT_V2_TR_PWM_CTRL_CC1_MATCH_MODE_Msk 0xC0UL +/* TCPWM_GRP_CNT.TR_OUT_SEL */ +#define TCPWM_GRP_CNT_V2_TR_OUT_SEL_OUT0_Pos 0UL +#define TCPWM_GRP_CNT_V2_TR_OUT_SEL_OUT0_Msk 0x7UL +#define TCPWM_GRP_CNT_V2_TR_OUT_SEL_OUT1_Pos 4UL +#define TCPWM_GRP_CNT_V2_TR_OUT_SEL_OUT1_Msk 0x70UL +/* TCPWM_GRP_CNT.INTR */ +#define TCPWM_GRP_CNT_V2_INTR_TC_Pos 0UL +#define TCPWM_GRP_CNT_V2_INTR_TC_Msk 0x1UL +#define TCPWM_GRP_CNT_V2_INTR_CC0_MATCH_Pos 1UL +#define TCPWM_GRP_CNT_V2_INTR_CC0_MATCH_Msk 0x2UL +#define TCPWM_GRP_CNT_V2_INTR_CC1_MATCH_Pos 2UL +#define TCPWM_GRP_CNT_V2_INTR_CC1_MATCH_Msk 0x4UL +/* TCPWM_GRP_CNT.INTR_SET */ +#define TCPWM_GRP_CNT_V2_INTR_SET_TC_Pos 0UL +#define TCPWM_GRP_CNT_V2_INTR_SET_TC_Msk 0x1UL +#define TCPWM_GRP_CNT_V2_INTR_SET_CC0_MATCH_Pos 1UL +#define TCPWM_GRP_CNT_V2_INTR_SET_CC0_MATCH_Msk 0x2UL +#define TCPWM_GRP_CNT_V2_INTR_SET_CC1_MATCH_Pos 2UL +#define TCPWM_GRP_CNT_V2_INTR_SET_CC1_MATCH_Msk 0x4UL +/* TCPWM_GRP_CNT.INTR_MASK */ +#define TCPWM_GRP_CNT_V2_INTR_MASK_TC_Pos 0UL +#define TCPWM_GRP_CNT_V2_INTR_MASK_TC_Msk 0x1UL +#define TCPWM_GRP_CNT_V2_INTR_MASK_CC0_MATCH_Pos 1UL +#define TCPWM_GRP_CNT_V2_INTR_MASK_CC0_MATCH_Msk 0x2UL +#define TCPWM_GRP_CNT_V2_INTR_MASK_CC1_MATCH_Pos 2UL +#define TCPWM_GRP_CNT_V2_INTR_MASK_CC1_MATCH_Msk 0x4UL +/* TCPWM_GRP_CNT.INTR_MASKED */ +#define TCPWM_GRP_CNT_V2_INTR_MASKED_TC_Pos 0UL +#define TCPWM_GRP_CNT_V2_INTR_MASKED_TC_Msk 0x1UL +#define TCPWM_GRP_CNT_V2_INTR_MASKED_CC0_MATCH_Pos 1UL +#define TCPWM_GRP_CNT_V2_INTR_MASKED_CC0_MATCH_Msk 0x2UL +#define TCPWM_GRP_CNT_V2_INTR_MASKED_CC1_MATCH_Pos 2UL +#define TCPWM_GRP_CNT_V2_INTR_MASKED_CC1_MATCH_Msk 0x4UL + + +#endif /* _CYIP_TCPWM_V2_H_ */ + + +/* [] END OF FILE */ diff --git a/devices/include/ip/cyip_usbfs.h b/devices/include/ip/cyip_usbfs.h index 2c2d5df..8ea26a2 100644 --- a/devices/include/ip/cyip_usbfs.h +++ b/devices/include/ip/cyip_usbfs.h @@ -5,7 +5,7 @@ * USBFS IP definitions * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.5.1.36 * ******************************************************************************** * \copyright @@ -99,10 +99,10 @@ typedef struct { __IOM uint32_t ARB_EP1_INT_EN; /*!< 0x00000204 Endpoint Interrupt Enable Register *1 */ __IOM uint32_t ARB_EP1_SR; /*!< 0x00000208 Endpoint Interrupt Enable Register *1 */ __IM uint32_t RESERVED13; - __IOM uint32_t ARB_RW1_WA; /*!< 0x00000210 Endpoint Write Address value *1 */ - __IOM uint32_t ARB_RW1_WA_MSB; /*!< 0x00000214 Endpoint Write Address value *1 */ - __IOM uint32_t ARB_RW1_RA; /*!< 0x00000218 Endpoint Read Address value *1 */ - __IOM uint32_t ARB_RW1_RA_MSB; /*!< 0x0000021C Endpoint Read Address value *1 */ + __IOM uint32_t ARB_RW1_WA; /*!< 0x00000210 Endpoint Write Address value *1, *2 */ + __IOM uint32_t ARB_RW1_WA_MSB; /*!< 0x00000214 Endpoint Write Address value *1, *2 */ + __IOM uint32_t ARB_RW1_RA; /*!< 0x00000218 Endpoint Read Address value *1, *2 */ + __IOM uint32_t ARB_RW1_RA_MSB; /*!< 0x0000021C Endpoint Read Address value *1, *2 */ __IOM uint32_t ARB_RW1_DR; /*!< 0x00000220 Endpoint Data Register */ __IM uint32_t RESERVED14[3]; __IOM uint32_t BUF_SIZE; /*!< 0x00000230 Dedicated Endpoint Buffer Size Register *1 */ @@ -113,10 +113,10 @@ typedef struct { __IOM uint32_t ARB_EP2_INT_EN; /*!< 0x00000244 Endpoint Interrupt Enable Register *1 */ __IOM uint32_t ARB_EP2_SR; /*!< 0x00000248 Endpoint Interrupt Enable Register *1 */ __IM uint32_t RESERVED16; - __IOM uint32_t ARB_RW2_WA; /*!< 0x00000250 Endpoint Write Address value *1 */ - __IOM uint32_t ARB_RW2_WA_MSB; /*!< 0x00000254 Endpoint Write Address value *1 */ - __IOM uint32_t ARB_RW2_RA; /*!< 0x00000258 Endpoint Read Address value *1 */ - __IOM uint32_t ARB_RW2_RA_MSB; /*!< 0x0000025C Endpoint Read Address value *1 */ + __IOM uint32_t ARB_RW2_WA; /*!< 0x00000250 Endpoint Write Address value *1, *2 */ + __IOM uint32_t ARB_RW2_WA_MSB; /*!< 0x00000254 Endpoint Write Address value *1, *2 */ + __IOM uint32_t ARB_RW2_RA; /*!< 0x00000258 Endpoint Read Address value *1, *2 */ + __IOM uint32_t ARB_RW2_RA_MSB; /*!< 0x0000025C Endpoint Read Address value *1, *2 */ __IOM uint32_t ARB_RW2_DR; /*!< 0x00000260 Endpoint Data Register */ __IM uint32_t RESERVED17[3]; __IOM uint32_t ARB_CFG; /*!< 0x00000270 Arbiter Configuration Register *1 */ @@ -127,10 +127,10 @@ typedef struct { __IOM uint32_t ARB_EP3_INT_EN; /*!< 0x00000284 Endpoint Interrupt Enable Register *1 */ __IOM uint32_t ARB_EP3_SR; /*!< 0x00000288 Endpoint Interrupt Enable Register *1 */ __IM uint32_t RESERVED18; - __IOM uint32_t ARB_RW3_WA; /*!< 0x00000290 Endpoint Write Address value *1 */ - __IOM uint32_t ARB_RW3_WA_MSB; /*!< 0x00000294 Endpoint Write Address value *1 */ - __IOM uint32_t ARB_RW3_RA; /*!< 0x00000298 Endpoint Read Address value *1 */ - __IOM uint32_t ARB_RW3_RA_MSB; /*!< 0x0000029C Endpoint Read Address value *1 */ + __IOM uint32_t ARB_RW3_WA; /*!< 0x00000290 Endpoint Write Address value *1, *2 */ + __IOM uint32_t ARB_RW3_WA_MSB; /*!< 0x00000294 Endpoint Write Address value *1, *2 */ + __IOM uint32_t ARB_RW3_RA; /*!< 0x00000298 Endpoint Read Address value *1, *2 */ + __IOM uint32_t ARB_RW3_RA_MSB; /*!< 0x0000029C Endpoint Read Address value *1, *2 */ __IOM uint32_t ARB_RW3_DR; /*!< 0x000002A0 Endpoint Data Register */ __IM uint32_t RESERVED19[3]; __IOM uint32_t CWA; /*!< 0x000002B0 Common Area Write Address *1 */ @@ -140,10 +140,10 @@ typedef struct { __IOM uint32_t ARB_EP4_INT_EN; /*!< 0x000002C4 Endpoint Interrupt Enable Register *1 */ __IOM uint32_t ARB_EP4_SR; /*!< 0x000002C8 Endpoint Interrupt Enable Register *1 */ __IM uint32_t RESERVED21; - __IOM uint32_t ARB_RW4_WA; /*!< 0x000002D0 Endpoint Write Address value *1 */ - __IOM uint32_t ARB_RW4_WA_MSB; /*!< 0x000002D4 Endpoint Write Address value *1 */ - __IOM uint32_t ARB_RW4_RA; /*!< 0x000002D8 Endpoint Read Address value *1 */ - __IOM uint32_t ARB_RW4_RA_MSB; /*!< 0x000002DC Endpoint Read Address value *1 */ + __IOM uint32_t ARB_RW4_WA; /*!< 0x000002D0 Endpoint Write Address value *1, *2 */ + __IOM uint32_t ARB_RW4_WA_MSB; /*!< 0x000002D4 Endpoint Write Address value *1, *2 */ + __IOM uint32_t ARB_RW4_RA; /*!< 0x000002D8 Endpoint Read Address value *1, *2 */ + __IOM uint32_t ARB_RW4_RA_MSB; /*!< 0x000002DC Endpoint Read Address value *1, *2 */ __IOM uint32_t ARB_RW4_DR; /*!< 0x000002E0 Endpoint Data Register */ __IM uint32_t RESERVED22[3]; __IOM uint32_t DMA_THRES; /*!< 0x000002F0 DMA Burst / Threshold Configuration */ @@ -153,10 +153,10 @@ typedef struct { __IOM uint32_t ARB_EP5_INT_EN; /*!< 0x00000304 Endpoint Interrupt Enable Register *1 */ __IOM uint32_t ARB_EP5_SR; /*!< 0x00000308 Endpoint Interrupt Enable Register *1 */ __IM uint32_t RESERVED24; - __IOM uint32_t ARB_RW5_WA; /*!< 0x00000310 Endpoint Write Address value *1 */ - __IOM uint32_t ARB_RW5_WA_MSB; /*!< 0x00000314 Endpoint Write Address value *1 */ - __IOM uint32_t ARB_RW5_RA; /*!< 0x00000318 Endpoint Read Address value *1 */ - __IOM uint32_t ARB_RW5_RA_MSB; /*!< 0x0000031C Endpoint Read Address value *1 */ + __IOM uint32_t ARB_RW5_WA; /*!< 0x00000310 Endpoint Write Address value *1, *2 */ + __IOM uint32_t ARB_RW5_WA_MSB; /*!< 0x00000314 Endpoint Write Address value *1, *2 */ + __IOM uint32_t ARB_RW5_RA; /*!< 0x00000318 Endpoint Read Address value *1, *2 */ + __IOM uint32_t ARB_RW5_RA_MSB; /*!< 0x0000031C Endpoint Read Address value *1, *2 */ __IOM uint32_t ARB_RW5_DR; /*!< 0x00000320 Endpoint Data Register */ __IM uint32_t RESERVED25[3]; __IOM uint32_t BUS_RST_CNT; /*!< 0x00000330 Bus Reset Count Register */ @@ -165,30 +165,30 @@ typedef struct { __IOM uint32_t ARB_EP6_INT_EN; /*!< 0x00000344 Endpoint Interrupt Enable Register *1 */ __IOM uint32_t ARB_EP6_SR; /*!< 0x00000348 Endpoint Interrupt Enable Register *1 */ __IM uint32_t RESERVED27; - __IOM uint32_t ARB_RW6_WA; /*!< 0x00000350 Endpoint Write Address value *1 */ - __IOM uint32_t ARB_RW6_WA_MSB; /*!< 0x00000354 Endpoint Write Address value *1 */ - __IOM uint32_t ARB_RW6_RA; /*!< 0x00000358 Endpoint Read Address value *1 */ - __IOM uint32_t ARB_RW6_RA_MSB; /*!< 0x0000035C Endpoint Read Address value *1 */ + __IOM uint32_t ARB_RW6_WA; /*!< 0x00000350 Endpoint Write Address value *1, *2 */ + __IOM uint32_t ARB_RW6_WA_MSB; /*!< 0x00000354 Endpoint Write Address value *1, *2 */ + __IOM uint32_t ARB_RW6_RA; /*!< 0x00000358 Endpoint Read Address value *1, *2 */ + __IOM uint32_t ARB_RW6_RA_MSB; /*!< 0x0000035C Endpoint Read Address value *1, *2 */ __IOM uint32_t ARB_RW6_DR; /*!< 0x00000360 Endpoint Data Register */ __IM uint32_t RESERVED28[7]; __IOM uint32_t ARB_EP7_CFG; /*!< 0x00000380 Endpoint Configuration Register *1 */ __IOM uint32_t ARB_EP7_INT_EN; /*!< 0x00000384 Endpoint Interrupt Enable Register *1 */ __IOM uint32_t ARB_EP7_SR; /*!< 0x00000388 Endpoint Interrupt Enable Register *1 */ __IM uint32_t RESERVED29; - __IOM uint32_t ARB_RW7_WA; /*!< 0x00000390 Endpoint Write Address value *1 */ - __IOM uint32_t ARB_RW7_WA_MSB; /*!< 0x00000394 Endpoint Write Address value *1 */ - __IOM uint32_t ARB_RW7_RA; /*!< 0x00000398 Endpoint Read Address value *1 */ - __IOM uint32_t ARB_RW7_RA_MSB; /*!< 0x0000039C Endpoint Read Address value *1 */ + __IOM uint32_t ARB_RW7_WA; /*!< 0x00000390 Endpoint Write Address value *1, *2 */ + __IOM uint32_t ARB_RW7_WA_MSB; /*!< 0x00000394 Endpoint Write Address value *1, *2 */ + __IOM uint32_t ARB_RW7_RA; /*!< 0x00000398 Endpoint Read Address value *1, *2 */ + __IOM uint32_t ARB_RW7_RA_MSB; /*!< 0x0000039C Endpoint Read Address value *1, *2 */ __IOM uint32_t ARB_RW7_DR; /*!< 0x000003A0 Endpoint Data Register */ __IM uint32_t RESERVED30[7]; __IOM uint32_t ARB_EP8_CFG; /*!< 0x000003C0 Endpoint Configuration Register *1 */ __IOM uint32_t ARB_EP8_INT_EN; /*!< 0x000003C4 Endpoint Interrupt Enable Register *1 */ __IOM uint32_t ARB_EP8_SR; /*!< 0x000003C8 Endpoint Interrupt Enable Register *1 */ __IM uint32_t RESERVED31; - __IOM uint32_t ARB_RW8_WA; /*!< 0x000003D0 Endpoint Write Address value *1 */ - __IOM uint32_t ARB_RW8_WA_MSB; /*!< 0x000003D4 Endpoint Write Address value *1 */ - __IOM uint32_t ARB_RW8_RA; /*!< 0x000003D8 Endpoint Read Address value *1 */ - __IOM uint32_t ARB_RW8_RA_MSB; /*!< 0x000003DC Endpoint Read Address value *1 */ + __IOM uint32_t ARB_RW8_WA; /*!< 0x000003D0 Endpoint Write Address value *1, *2 */ + __IOM uint32_t ARB_RW8_WA_MSB; /*!< 0x000003D4 Endpoint Write Address value *1, *2 */ + __IOM uint32_t ARB_RW8_RA; /*!< 0x000003D8 Endpoint Read Address value *1, *2 */ + __IOM uint32_t ARB_RW8_RA_MSB; /*!< 0x000003DC Endpoint Read Address value *1, *2 */ __IOM uint32_t ARB_RW8_DR; /*!< 0x000003E0 Endpoint Data Register */ __IM uint32_t RESERVED32[7]; __IOM uint32_t MEM_DATA[512]; /*!< 0x00000400 DATA */ @@ -197,55 +197,55 @@ typedef struct { __IM uint32_t RESERVED34[7]; __IM uint32_t OSCLK_DR16; /*!< 0x00001080 Oscillator lock data register */ __IM uint32_t RESERVED35[99]; - __IOM uint32_t ARB_RW1_WA16; /*!< 0x00001210 Endpoint Write Address value */ + __IOM uint32_t ARB_RW1_WA16; /*!< 0x00001210 Endpoint Write Address value *3 */ __IM uint32_t RESERVED36; - __IOM uint32_t ARB_RW1_RA16; /*!< 0x00001218 Endpoint Read Address value */ + __IOM uint32_t ARB_RW1_RA16; /*!< 0x00001218 Endpoint Read Address value *3 */ __IM uint32_t RESERVED37; __IOM uint32_t ARB_RW1_DR16; /*!< 0x00001220 Endpoint Data Register */ __IM uint32_t RESERVED38[11]; - __IOM uint32_t ARB_RW2_WA16; /*!< 0x00001250 Endpoint Write Address value */ + __IOM uint32_t ARB_RW2_WA16; /*!< 0x00001250 Endpoint Write Address value *3 */ __IM uint32_t RESERVED39; - __IOM uint32_t ARB_RW2_RA16; /*!< 0x00001258 Endpoint Read Address value */ + __IOM uint32_t ARB_RW2_RA16; /*!< 0x00001258 Endpoint Read Address value *3 */ __IM uint32_t RESERVED40; __IOM uint32_t ARB_RW2_DR16; /*!< 0x00001260 Endpoint Data Register */ __IM uint32_t RESERVED41[11]; - __IOM uint32_t ARB_RW3_WA16; /*!< 0x00001290 Endpoint Write Address value */ + __IOM uint32_t ARB_RW3_WA16; /*!< 0x00001290 Endpoint Write Address value *3 */ __IM uint32_t RESERVED42; - __IOM uint32_t ARB_RW3_RA16; /*!< 0x00001298 Endpoint Read Address value */ + __IOM uint32_t ARB_RW3_RA16; /*!< 0x00001298 Endpoint Read Address value *3 */ __IM uint32_t RESERVED43; __IOM uint32_t ARB_RW3_DR16; /*!< 0x000012A0 Endpoint Data Register */ __IM uint32_t RESERVED44[3]; __IOM uint32_t CWA16; /*!< 0x000012B0 Common Area Write Address */ __IM uint32_t RESERVED45[7]; - __IOM uint32_t ARB_RW4_WA16; /*!< 0x000012D0 Endpoint Write Address value */ + __IOM uint32_t ARB_RW4_WA16; /*!< 0x000012D0 Endpoint Write Address value *3 */ __IM uint32_t RESERVED46; - __IOM uint32_t ARB_RW4_RA16; /*!< 0x000012D8 Endpoint Read Address value */ + __IOM uint32_t ARB_RW4_RA16; /*!< 0x000012D8 Endpoint Read Address value *3 */ __IM uint32_t RESERVED47; __IOM uint32_t ARB_RW4_DR16; /*!< 0x000012E0 Endpoint Data Register */ __IM uint32_t RESERVED48[3]; __IOM uint32_t DMA_THRES16; /*!< 0x000012F0 DMA Burst / Threshold Configuration */ __IM uint32_t RESERVED49[7]; - __IOM uint32_t ARB_RW5_WA16; /*!< 0x00001310 Endpoint Write Address value */ + __IOM uint32_t ARB_RW5_WA16; /*!< 0x00001310 Endpoint Write Address value *3 */ __IM uint32_t RESERVED50; - __IOM uint32_t ARB_RW5_RA16; /*!< 0x00001318 Endpoint Read Address value */ + __IOM uint32_t ARB_RW5_RA16; /*!< 0x00001318 Endpoint Read Address value *3 */ __IM uint32_t RESERVED51; __IOM uint32_t ARB_RW5_DR16; /*!< 0x00001320 Endpoint Data Register */ __IM uint32_t RESERVED52[11]; - __IOM uint32_t ARB_RW6_WA16; /*!< 0x00001350 Endpoint Write Address value */ + __IOM uint32_t ARB_RW6_WA16; /*!< 0x00001350 Endpoint Write Address value *3 */ __IM uint32_t RESERVED53; - __IOM uint32_t ARB_RW6_RA16; /*!< 0x00001358 Endpoint Read Address value */ + __IOM uint32_t ARB_RW6_RA16; /*!< 0x00001358 Endpoint Read Address value *3 */ __IM uint32_t RESERVED54; __IOM uint32_t ARB_RW6_DR16; /*!< 0x00001360 Endpoint Data Register */ __IM uint32_t RESERVED55[11]; - __IOM uint32_t ARB_RW7_WA16; /*!< 0x00001390 Endpoint Write Address value */ + __IOM uint32_t ARB_RW7_WA16; /*!< 0x00001390 Endpoint Write Address value *3 */ __IM uint32_t RESERVED56; - __IOM uint32_t ARB_RW7_RA16; /*!< 0x00001398 Endpoint Read Address value */ + __IOM uint32_t ARB_RW7_RA16; /*!< 0x00001398 Endpoint Read Address value *3 */ __IM uint32_t RESERVED57; __IOM uint32_t ARB_RW7_DR16; /*!< 0x000013A0 Endpoint Data Register */ __IM uint32_t RESERVED58[11]; - __IOM uint32_t ARB_RW8_WA16; /*!< 0x000013D0 Endpoint Write Address value */ + __IOM uint32_t ARB_RW8_WA16; /*!< 0x000013D0 Endpoint Write Address value *3 */ __IM uint32_t RESERVED59; - __IOM uint32_t ARB_RW8_RA16; /*!< 0x000013D8 Endpoint Read Address value */ + __IOM uint32_t ARB_RW8_RA16; /*!< 0x000013D8 Endpoint Read Address value *3 */ __IM uint32_t RESERVED60; __IOM uint32_t ARB_RW8_DR16; /*!< 0x000013E0 Endpoint Data Register */ __IM uint32_t RESERVED61[775]; diff --git a/devices/include/psoc6_04_config.h b/devices/include/psoc6_04_config.h new file mode 100644 index 0000000..d4ebde4 --- /dev/null +++ b/devices/include/psoc6_04_config.h @@ -0,0 +1,2972 @@ +/***************************************************************************//** +* \file psoc6_04_config.h +* +* \brief +* PSoC6_04 device configuration header +* +* \note +* Generator version: 1.6.0.76 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _PSOC6_04_CONFIG_H_ +#define _PSOC6_04_CONFIG_H_ + +/* Clock Connections */ +typedef enum +{ + PCLK_SCB0_CLOCK = 0x0000u, /* scb[0].clock */ + PCLK_SCB1_CLOCK = 0x0001u, /* scb[1].clock */ + PCLK_SCB2_CLOCK = 0x0002u, /* scb[2].clock */ + PCLK_SCB4_CLOCK = 0x0003u, /* scb[4].clock */ + PCLK_SCB5_CLOCK = 0x0004u, /* scb[5].clock */ + PCLK_SCB6_CLOCK = 0x0005u, /* scb[6].clock */ + PCLK_SMARTIO9_CLOCK = 0x0006u, /* smartio[9].clock */ + PCLK_TCPWM0_CLOCKS0 = 0x0007u, /* tcpwm[0].clocks[0] */ + PCLK_TCPWM0_CLOCKS1 = 0x0008u, /* tcpwm[0].clocks[1] */ + PCLK_TCPWM0_CLOCKS2 = 0x0009u, /* tcpwm[0].clocks[2] */ + PCLK_TCPWM0_CLOCKS3 = 0x000Au, /* tcpwm[0].clocks[3] */ + PCLK_TCPWM0_CLOCKS256 = 0x000Bu, /* tcpwm[0].clocks[256] */ + PCLK_TCPWM0_CLOCKS257 = 0x000Cu, /* tcpwm[0].clocks[257] */ + PCLK_TCPWM0_CLOCKS258 = 0x000Du, /* tcpwm[0].clocks[258] */ + PCLK_TCPWM0_CLOCKS259 = 0x000Eu, /* tcpwm[0].clocks[259] */ + PCLK_TCPWM0_CLOCKS260 = 0x000Fu, /* tcpwm[0].clocks[260] */ + PCLK_TCPWM0_CLOCKS261 = 0x0010u, /* tcpwm[0].clocks[261] */ + PCLK_TCPWM0_CLOCKS262 = 0x0011u, /* tcpwm[0].clocks[262] */ + PCLK_TCPWM0_CLOCKS263 = 0x0012u, /* tcpwm[0].clocks[263] */ + PCLK_CSD_CLOCK = 0x0013u, /* csd.clock */ + PCLK_LCD_CLOCK = 0x0014u, /* lcd.clock */ + PCLK_CPUSS_CLOCK_TRACE_IN = 0x0015u, /* cpuss.clock_trace_in */ + PCLK_PASS_CLOCK_PUMP_PERI = 0x0016u, /* pass.clock_pump_peri */ + PCLK_PASS_CLOCK_SAR0 = 0x0017u, /* pass.clock_sar[0] */ + PCLK_CANFD0_CLOCK_CAN0 = 0x0018u, /* canfd[0].clock_can[0] */ + PCLK_USB_CLOCK_DEV_BRS = 0x0019u, /* usb.clock_dev_brs */ + PCLK_PASS_CLOCK_CTDAC = 0x001Au, /* pass.clock_ctdac */ + PCLK_PASS_CLOCK_SAR1 = 0x001Bu /* pass.clock_sar[1] */ +} en_clk_dst_t; + +/* Trigger Group */ +/* This section contains the enums related to the Trigger multiplexer (TrigMux) driver. +* Refer to the Cypress Peripheral Driver Library Documentation, section Trigger multiplexer (TrigMux) -> Enumerated Types for details. +*/ +/* Trigger Group Inputs */ +/* Trigger Input Group 0 - PDMA0 Request Assignments */ +typedef enum +{ + TRIG_IN_MUX_0_PDMA0_TR_OUT0 = 0x00000001u, /* cpuss.dw0_tr_out[0] */ + TRIG_IN_MUX_0_PDMA0_TR_OUT1 = 0x00000002u, /* cpuss.dw0_tr_out[1] */ + TRIG_IN_MUX_0_PDMA0_TR_OUT2 = 0x00000003u, /* cpuss.dw0_tr_out[2] */ + TRIG_IN_MUX_0_PDMA0_TR_OUT3 = 0x00000004u, /* cpuss.dw0_tr_out[3] */ + TRIG_IN_MUX_0_PDMA0_TR_OUT4 = 0x00000005u, /* cpuss.dw0_tr_out[4] */ + TRIG_IN_MUX_0_PDMA0_TR_OUT5 = 0x00000006u, /* cpuss.dw0_tr_out[5] */ + TRIG_IN_MUX_0_PDMA0_TR_OUT6 = 0x00000007u, /* cpuss.dw0_tr_out[6] */ + TRIG_IN_MUX_0_PDMA0_TR_OUT7 = 0x00000008u, /* cpuss.dw0_tr_out[7] */ + TRIG_IN_MUX_0_PDMA1_TR_OUT0 = 0x00000009u, /* cpuss.dw1_tr_out[0] */ + TRIG_IN_MUX_0_PDMA1_TR_OUT1 = 0x0000000Au, /* cpuss.dw1_tr_out[1] */ + TRIG_IN_MUX_0_PDMA1_TR_OUT2 = 0x0000000Bu, /* cpuss.dw1_tr_out[2] */ + TRIG_IN_MUX_0_PDMA1_TR_OUT3 = 0x0000000Cu, /* cpuss.dw1_tr_out[3] */ + TRIG_IN_MUX_0_PDMA1_TR_OUT4 = 0x0000000Du, /* cpuss.dw1_tr_out[4] */ + TRIG_IN_MUX_0_PDMA1_TR_OUT5 = 0x0000000Eu, /* cpuss.dw1_tr_out[5] */ + TRIG_IN_MUX_0_PDMA1_TR_OUT6 = 0x0000000Fu, /* cpuss.dw1_tr_out[6] */ + TRIG_IN_MUX_0_PDMA1_TR_OUT7 = 0x00000010u, /* cpuss.dw1_tr_out[7] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT00 = 0x00000011u, /* tcpwm[0].tr_out0[0] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT10 = 0x00000012u, /* tcpwm[0].tr_out1[0] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT01 = 0x00000014u, /* tcpwm[0].tr_out0[1] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT11 = 0x00000015u, /* tcpwm[0].tr_out1[1] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT02 = 0x00000017u, /* tcpwm[0].tr_out0[2] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT12 = 0x00000018u, /* tcpwm[0].tr_out1[2] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT03 = 0x0000001Au, /* tcpwm[0].tr_out0[3] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT13 = 0x0000001Bu, /* tcpwm[0].tr_out1[3] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT0256 = 0x0000001Du, /* tcpwm[0].tr_out0[256] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT1256 = 0x0000001Eu, /* tcpwm[0].tr_out1[256] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT0257 = 0x00000020u, /* tcpwm[0].tr_out0[257] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT1257 = 0x00000021u, /* tcpwm[0].tr_out1[257] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT0258 = 0x00000023u, /* tcpwm[0].tr_out0[258] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT1258 = 0x00000024u, /* tcpwm[0].tr_out1[258] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT0259 = 0x00000026u, /* tcpwm[0].tr_out0[259] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT1259 = 0x00000027u, /* tcpwm[0].tr_out1[259] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT0260 = 0x00000029u, /* tcpwm[0].tr_out0[260] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT1260 = 0x0000002Au, /* tcpwm[0].tr_out1[260] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT0261 = 0x0000002Cu, /* tcpwm[0].tr_out0[261] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT1261 = 0x0000002Du, /* tcpwm[0].tr_out1[261] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT0262 = 0x0000002Fu, /* tcpwm[0].tr_out0[262] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT1262 = 0x00000030u, /* tcpwm[0].tr_out1[262] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT0263 = 0x00000032u, /* tcpwm[0].tr_out0[263] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT1263 = 0x00000033u, /* tcpwm[0].tr_out1[263] */ + TRIG_IN_MUX_0_MDMA_TR_OUT0 = 0x00000041u, /* cpuss.dmac_tr_out[0] */ + TRIG_IN_MUX_0_MDMA_TR_OUT1 = 0x00000042u, /* cpuss.dmac_tr_out[1] */ + TRIG_IN_MUX_0_HSIOM_TR_OUT0 = 0x00000045u, /* peri.tr_io_input[0] */ + TRIG_IN_MUX_0_HSIOM_TR_OUT1 = 0x00000046u, /* peri.tr_io_input[1] */ + TRIG_IN_MUX_0_HSIOM_TR_OUT2 = 0x00000047u, /* peri.tr_io_input[2] */ + TRIG_IN_MUX_0_HSIOM_TR_OUT3 = 0x00000048u, /* peri.tr_io_input[3] */ + TRIG_IN_MUX_0_HSIOM_TR_OUT4 = 0x00000049u, /* peri.tr_io_input[4] */ + TRIG_IN_MUX_0_HSIOM_TR_OUT5 = 0x0000004Au, /* peri.tr_io_input[5] */ + TRIG_IN_MUX_0_HSIOM_TR_OUT6 = 0x0000004Bu, /* peri.tr_io_input[6] */ + TRIG_IN_MUX_0_HSIOM_TR_OUT7 = 0x0000004Cu, /* peri.tr_io_input[7] */ + TRIG_IN_MUX_0_HSIOM_TR_OUT8 = 0x0000004Du, /* peri.tr_io_input[8] */ + TRIG_IN_MUX_0_HSIOM_TR_OUT9 = 0x0000004Eu, /* peri.tr_io_input[9] */ + TRIG_IN_MUX_0_HSIOM_TR_OUT10 = 0x0000004Fu, /* peri.tr_io_input[10] */ + TRIG_IN_MUX_0_HSIOM_TR_OUT11 = 0x00000050u, /* peri.tr_io_input[11] */ + TRIG_IN_MUX_0_HSIOM_TR_OUT12 = 0x00000051u, /* peri.tr_io_input[12] */ + TRIG_IN_MUX_0_HSIOM_TR_OUT13 = 0x00000052u, /* peri.tr_io_input[13] */ + TRIG_IN_MUX_0_CTI_TR_OUT0 = 0x00000053u, /* cpuss.cti_tr_out[0] */ + TRIG_IN_MUX_0_CTI_TR_OUT1 = 0x00000054u, /* cpuss.cti_tr_out[1] */ + TRIG_IN_MUX_0_FAULT_TR_OUT0 = 0x00000055u, /* cpuss.tr_fault[0] */ + TRIG_IN_MUX_0_FAULT_TR_OUT1 = 0x00000056u /* cpuss.tr_fault[1] */ +} en_trig_input_pdma0_tr_t; + +/* Trigger Input Group 1 - PDMA1 Request Assignments */ +typedef enum +{ + TRIG_IN_MUX_1_PDMA0_TR_OUT0 = 0x00000101u, /* cpuss.dw0_tr_out[0] */ + TRIG_IN_MUX_1_PDMA0_TR_OUT1 = 0x00000102u, /* cpuss.dw0_tr_out[1] */ + TRIG_IN_MUX_1_PDMA0_TR_OUT2 = 0x00000103u, /* cpuss.dw0_tr_out[2] */ + TRIG_IN_MUX_1_PDMA0_TR_OUT3 = 0x00000104u, /* cpuss.dw0_tr_out[3] */ + TRIG_IN_MUX_1_PDMA0_TR_OUT4 = 0x00000105u, /* cpuss.dw0_tr_out[4] */ + TRIG_IN_MUX_1_PDMA0_TR_OUT5 = 0x00000106u, /* cpuss.dw0_tr_out[5] */ + TRIG_IN_MUX_1_PDMA0_TR_OUT6 = 0x00000107u, /* cpuss.dw0_tr_out[6] */ + TRIG_IN_MUX_1_PDMA0_TR_OUT7 = 0x00000108u, /* cpuss.dw0_tr_out[7] */ + TRIG_IN_MUX_1_PDMA1_TR_OUT0 = 0x00000109u, /* cpuss.dw1_tr_out[0] */ + TRIG_IN_MUX_1_PDMA1_TR_OUT1 = 0x0000010Au, /* cpuss.dw1_tr_out[1] */ + TRIG_IN_MUX_1_PDMA1_TR_OUT2 = 0x0000010Bu, /* cpuss.dw1_tr_out[2] */ + TRIG_IN_MUX_1_PDMA1_TR_OUT3 = 0x0000010Cu, /* cpuss.dw1_tr_out[3] */ + TRIG_IN_MUX_1_PDMA1_TR_OUT4 = 0x0000010Du, /* cpuss.dw1_tr_out[4] */ + TRIG_IN_MUX_1_PDMA1_TR_OUT5 = 0x0000010Eu, /* cpuss.dw1_tr_out[5] */ + TRIG_IN_MUX_1_PDMA1_TR_OUT6 = 0x0000010Fu, /* cpuss.dw1_tr_out[6] */ + TRIG_IN_MUX_1_PDMA1_TR_OUT7 = 0x00000110u, /* cpuss.dw1_tr_out[7] */ + TRIG_IN_MUX_1_MDMA_TR_OUT0 = 0x00000141u, /* cpuss.dmac_tr_out[0] */ + TRIG_IN_MUX_1_MDMA_TR_OUT1 = 0x00000142u, /* cpuss.dmac_tr_out[1] */ + TRIG_IN_MUX_1_CSD_ADC_DONE = 0x00000145u, /* csd.tr_adc_done */ + TRIG_IN_MUX_1_HSIOM_TR_OUT14 = 0x00000146u, /* peri.tr_io_input[14] */ + TRIG_IN_MUX_1_HSIOM_TR_OUT15 = 0x00000147u, /* peri.tr_io_input[15] */ + TRIG_IN_MUX_1_HSIOM_TR_OUT16 = 0x00000148u, /* peri.tr_io_input[16] */ + TRIG_IN_MUX_1_HSIOM_TR_OUT17 = 0x00000149u, /* peri.tr_io_input[17] */ + TRIG_IN_MUX_1_HSIOM_TR_OUT18 = 0x0000014Au, /* peri.tr_io_input[18] */ + TRIG_IN_MUX_1_HSIOM_TR_OUT19 = 0x0000014Bu, /* peri.tr_io_input[19] */ + TRIG_IN_MUX_1_HSIOM_TR_OUT20 = 0x0000014Cu, /* peri.tr_io_input[20] */ + TRIG_IN_MUX_1_HSIOM_TR_OUT21 = 0x0000014Du, /* peri.tr_io_input[21] */ + TRIG_IN_MUX_1_HSIOM_TR_OUT22 = 0x0000014Eu, /* peri.tr_io_input[22] */ + TRIG_IN_MUX_1_HSIOM_TR_OUT23 = 0x0000014Fu, /* peri.tr_io_input[23] */ + TRIG_IN_MUX_1_LPCOMP_DSI_COMP0 = 0x00000154u, /* lpcomp.dsi_comp0 */ + TRIG_IN_MUX_1_LPCOMP_DSI_COMP1 = 0x00000155u, /* lpcomp.dsi_comp1 */ + TRIG_IN_MUX_1_CANFD_TT_TR_OUT0 = 0x00000156u /* canfd[0].tr_tmp_rtp_out[0] */ +} en_trig_input_pdma1_tr_t; + +/* Trigger Input Group 2 - TCPWM0 trigger multiplexer */ +typedef enum +{ + TRIG_IN_MUX_2_PDMA0_TR_OUT0 = 0x00000201u, /* cpuss.dw0_tr_out[0] */ + TRIG_IN_MUX_2_PDMA0_TR_OUT1 = 0x00000202u, /* cpuss.dw0_tr_out[1] */ + TRIG_IN_MUX_2_PDMA0_TR_OUT2 = 0x00000203u, /* cpuss.dw0_tr_out[2] */ + TRIG_IN_MUX_2_PDMA0_TR_OUT3 = 0x00000204u, /* cpuss.dw0_tr_out[3] */ + TRIG_IN_MUX_2_PDMA0_TR_OUT4 = 0x00000205u, /* cpuss.dw0_tr_out[4] */ + TRIG_IN_MUX_2_PDMA0_TR_OUT5 = 0x00000206u, /* cpuss.dw0_tr_out[5] */ + TRIG_IN_MUX_2_PDMA0_TR_OUT6 = 0x00000207u, /* cpuss.dw0_tr_out[6] */ + TRIG_IN_MUX_2_PDMA0_TR_OUT7 = 0x00000208u, /* cpuss.dw0_tr_out[7] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT00 = 0x00000209u, /* tcpwm[0].tr_out0[0] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT10 = 0x0000020Au, /* tcpwm[0].tr_out1[0] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT01 = 0x0000020Cu, /* tcpwm[0].tr_out0[1] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT11 = 0x0000020Du, /* tcpwm[0].tr_out1[1] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT02 = 0x0000020Fu, /* tcpwm[0].tr_out0[2] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT12 = 0x00000210u, /* tcpwm[0].tr_out1[2] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT03 = 0x00000212u, /* tcpwm[0].tr_out0[3] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT13 = 0x00000213u, /* tcpwm[0].tr_out1[3] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT0256 = 0x00000221u, /* tcpwm[0].tr_out0[256] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT1256 = 0x00000222u, /* tcpwm[0].tr_out1[256] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT0257 = 0x00000224u, /* tcpwm[0].tr_out0[257] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT1257 = 0x00000225u, /* tcpwm[0].tr_out1[257] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT0258 = 0x00000227u, /* tcpwm[0].tr_out0[258] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT1258 = 0x00000228u, /* tcpwm[0].tr_out1[258] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT0259 = 0x0000022Au, /* tcpwm[0].tr_out0[259] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT1259 = 0x0000022Bu, /* tcpwm[0].tr_out1[259] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT0260 = 0x0000022Du, /* tcpwm[0].tr_out0[260] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT1260 = 0x0000022Eu, /* tcpwm[0].tr_out1[260] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT0261 = 0x00000230u, /* tcpwm[0].tr_out0[261] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT1261 = 0x00000231u, /* tcpwm[0].tr_out1[261] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT0262 = 0x00000233u, /* tcpwm[0].tr_out0[262] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT1262 = 0x00000234u, /* tcpwm[0].tr_out1[262] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT0263 = 0x00000236u, /* tcpwm[0].tr_out0[263] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT1263 = 0x00000237u, /* tcpwm[0].tr_out1[263] */ + TRIG_IN_MUX_2_MDMA_TR_OUT0 = 0x00000239u, /* cpuss.dmac_tr_out[0] */ + TRIG_IN_MUX_2_MDMA_TR_OUT1 = 0x0000023Au, /* cpuss.dmac_tr_out[1] */ + TRIG_IN_MUX_2_SCB_I2C_SCL0 = 0x0000023Du, /* scb[0].tr_i2c_scl_filtered */ + TRIG_IN_MUX_2_SCB_TX0 = 0x0000023Eu, /* scb[0].tr_tx_req */ + TRIG_IN_MUX_2_SCB_RX0 = 0x0000023Fu, /* scb[0].tr_rx_req */ + TRIG_IN_MUX_2_SCB_I2C_SCL1 = 0x00000240u, /* scb[1].tr_i2c_scl_filtered */ + TRIG_IN_MUX_2_SCB_TX1 = 0x00000241u, /* scb[1].tr_tx_req */ + TRIG_IN_MUX_2_SCB_RX1 = 0x00000242u, /* scb[1].tr_rx_req */ + TRIG_IN_MUX_2_SCB_I2C_SCL2 = 0x00000243u, /* scb[2].tr_i2c_scl_filtered */ + TRIG_IN_MUX_2_SCB_TX2 = 0x00000244u, /* scb[2].tr_tx_req */ + TRIG_IN_MUX_2_SCB_RX2 = 0x00000245u, /* scb[2].tr_rx_req */ + TRIG_IN_MUX_2_SCB_I2C_SCL4 = 0x00000249u, /* scb[4].tr_i2c_scl_filtered */ + TRIG_IN_MUX_2_SCB_TX4 = 0x0000024Au, /* scb[4].tr_tx_req */ + TRIG_IN_MUX_2_SCB_RX4 = 0x0000024Bu, /* scb[4].tr_rx_req */ + TRIG_IN_MUX_2_SCB_I2C_SCL5 = 0x0000024Cu, /* scb[5].tr_i2c_scl_filtered */ + TRIG_IN_MUX_2_SCB_TX5 = 0x0000024Du, /* scb[5].tr_tx_req */ + TRIG_IN_MUX_2_SCB_RX5 = 0x0000024Eu, /* scb[5].tr_rx_req */ + TRIG_IN_MUX_2_SCB_I2C_SCL6 = 0x0000024Fu, /* scb[6].tr_i2c_scl_filtered */ + TRIG_IN_MUX_2_SCB_TX6 = 0x00000250u, /* scb[6].tr_tx_req */ + TRIG_IN_MUX_2_SCB_RX6 = 0x00000251u, /* scb[6].tr_rx_req */ + TRIG_IN_MUX_2_SMIF_TX = 0x00000264u, /* smif.tr_tx_req */ + TRIG_IN_MUX_2_SMIF_RX = 0x00000265u, /* smif.tr_rx_req */ + TRIG_IN_MUX_2_USB_DMA0 = 0x00000266u, /* usb.dma_req[0] */ + TRIG_IN_MUX_2_USB_DMA1 = 0x00000267u, /* usb.dma_req[1] */ + TRIG_IN_MUX_2_USB_DMA2 = 0x00000268u, /* usb.dma_req[2] */ + TRIG_IN_MUX_2_USB_DMA3 = 0x00000269u, /* usb.dma_req[3] */ + TRIG_IN_MUX_2_USB_DMA4 = 0x0000026Au, /* usb.dma_req[4] */ + TRIG_IN_MUX_2_USB_DMA5 = 0x0000026Bu, /* usb.dma_req[5] */ + TRIG_IN_MUX_2_USB_DMA6 = 0x0000026Cu, /* usb.dma_req[6] */ + TRIG_IN_MUX_2_USB_DMA7 = 0x0000026Du, /* usb.dma_req[7] */ + TRIG_IN_MUX_2_PASS_SAR0_DONE = 0x00000273u, /* pass.tr_sar_out[0] */ + TRIG_IN_MUX_2_CSD_SENSE = 0x00000274u, /* csd.dsi_sense_out */ + TRIG_IN_MUX_2_HSIOM_TR_OUT0 = 0x00000275u, /* peri.tr_io_input[0] */ + TRIG_IN_MUX_2_HSIOM_TR_OUT1 = 0x00000276u, /* peri.tr_io_input[1] */ + TRIG_IN_MUX_2_HSIOM_TR_OUT2 = 0x00000277u, /* peri.tr_io_input[2] */ + TRIG_IN_MUX_2_HSIOM_TR_OUT3 = 0x00000278u, /* peri.tr_io_input[3] */ + TRIG_IN_MUX_2_HSIOM_TR_OUT4 = 0x00000279u, /* peri.tr_io_input[4] */ + TRIG_IN_MUX_2_HSIOM_TR_OUT5 = 0x0000027Au, /* peri.tr_io_input[5] */ + TRIG_IN_MUX_2_HSIOM_TR_OUT6 = 0x0000027Bu, /* peri.tr_io_input[6] */ + TRIG_IN_MUX_2_HSIOM_TR_OUT7 = 0x0000027Cu, /* peri.tr_io_input[7] */ + TRIG_IN_MUX_2_HSIOM_TR_OUT8 = 0x0000027Du, /* peri.tr_io_input[8] */ + TRIG_IN_MUX_2_HSIOM_TR_OUT9 = 0x0000027Eu, /* peri.tr_io_input[9] */ + TRIG_IN_MUX_2_HSIOM_TR_OUT10 = 0x0000027Fu, /* peri.tr_io_input[10] */ + TRIG_IN_MUX_2_HSIOM_TR_OUT11 = 0x00000280u, /* peri.tr_io_input[11] */ + TRIG_IN_MUX_2_HSIOM_TR_OUT12 = 0x00000281u, /* peri.tr_io_input[12] */ + TRIG_IN_MUX_2_HSIOM_TR_OUT13 = 0x00000282u, /* peri.tr_io_input[13] */ + TRIG_IN_MUX_2_CTI_TR_OUT0 = 0x00000283u, /* cpuss.cti_tr_out[0] */ + TRIG_IN_MUX_2_CTI_TR_OUT1 = 0x00000284u, /* cpuss.cti_tr_out[1] */ + TRIG_IN_MUX_2_LPCOMP_DSI_COMP0 = 0x00000285u, /* lpcomp.dsi_comp0 */ + TRIG_IN_MUX_2_LPCOMP_DSI_COMP1 = 0x00000286u, /* lpcomp.dsi_comp1 */ + TRIG_IN_MUX_2_CANFD_TT_TR_OUT0 = 0x00000287u, /* canfd[0].tr_tmp_rtp_out[0] */ + TRIG_IN_MUX_2_PASS_CTDAC_EMPTY = 0x00000288u, /* pass.tr_ctdac_empty */ + TRIG_IN_MUX_2_PASS_CTB_CMP0 = 0x00000289u, /* pass.dsi_ctb_cmp0 */ + TRIG_IN_MUX_2_PASS_SAR1_DONE = 0x0000028Au /* pass.tr_sar_out[1] */ +} en_trig_input_tcpwm0_t; + +/* Trigger Input Group 3 - TCPWM0 trigger multiplexer - 2nd */ +typedef enum +{ + TRIG_IN_MUX_3_PDMA1_TR_OUT0 = 0x00000301u, /* cpuss.dw1_tr_out[0] */ + TRIG_IN_MUX_3_PDMA1_TR_OUT1 = 0x00000302u, /* cpuss.dw1_tr_out[1] */ + TRIG_IN_MUX_3_PDMA1_TR_OUT2 = 0x00000303u, /* cpuss.dw1_tr_out[2] */ + TRIG_IN_MUX_3_PDMA1_TR_OUT3 = 0x00000304u, /* cpuss.dw1_tr_out[3] */ + TRIG_IN_MUX_3_PDMA1_TR_OUT4 = 0x00000305u, /* cpuss.dw1_tr_out[4] */ + TRIG_IN_MUX_3_PDMA1_TR_OUT5 = 0x00000306u, /* cpuss.dw1_tr_out[5] */ + TRIG_IN_MUX_3_PDMA1_TR_OUT6 = 0x00000307u, /* cpuss.dw1_tr_out[6] */ + TRIG_IN_MUX_3_PDMA1_TR_OUT7 = 0x00000308u, /* cpuss.dw1_tr_out[7] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT00 = 0x00000309u, /* tcpwm[0].tr_out0[0] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT10 = 0x0000030Au, /* tcpwm[0].tr_out1[0] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT01 = 0x0000030Cu, /* tcpwm[0].tr_out0[1] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT11 = 0x0000030Du, /* tcpwm[0].tr_out1[1] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT02 = 0x0000030Fu, /* tcpwm[0].tr_out0[2] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT12 = 0x00000310u, /* tcpwm[0].tr_out1[2] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT03 = 0x00000312u, /* tcpwm[0].tr_out0[3] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT13 = 0x00000313u, /* tcpwm[0].tr_out1[3] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT0256 = 0x00000321u, /* tcpwm[0].tr_out0[256] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT1256 = 0x00000322u, /* tcpwm[0].tr_out1[256] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT0257 = 0x00000324u, /* tcpwm[0].tr_out0[257] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT1257 = 0x00000325u, /* tcpwm[0].tr_out1[257] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT0258 = 0x00000327u, /* tcpwm[0].tr_out0[258] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT1258 = 0x00000328u, /* tcpwm[0].tr_out1[258] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT0259 = 0x0000032Au, /* tcpwm[0].tr_out0[259] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT1259 = 0x0000032Bu, /* tcpwm[0].tr_out1[259] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT0260 = 0x0000032Du, /* tcpwm[0].tr_out0[260] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT1260 = 0x0000032Eu, /* tcpwm[0].tr_out1[260] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT0261 = 0x00000330u, /* tcpwm[0].tr_out0[261] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT1261 = 0x00000331u, /* tcpwm[0].tr_out1[261] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT0262 = 0x00000333u, /* tcpwm[0].tr_out0[262] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT1262 = 0x00000334u, /* tcpwm[0].tr_out1[262] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT0263 = 0x00000336u, /* tcpwm[0].tr_out0[263] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT1263 = 0x00000337u, /* tcpwm[0].tr_out1[263] */ + TRIG_IN_MUX_3_MDMA_TR_OUT0 = 0x00000339u, /* cpuss.dmac_tr_out[0] */ + TRIG_IN_MUX_3_MDMA_TR_OUT1 = 0x0000033Au, /* cpuss.dmac_tr_out[1] */ + TRIG_IN_MUX_3_SCB_I2C_SCL0 = 0x0000033Du, /* scb[0].tr_i2c_scl_filtered */ + TRIG_IN_MUX_3_SCB_TX0 = 0x0000033Eu, /* scb[0].tr_tx_req */ + TRIG_IN_MUX_3_SCB_RX0 = 0x0000033Fu, /* scb[0].tr_rx_req */ + TRIG_IN_MUX_3_SCB_I2C_SCL1 = 0x00000340u, /* scb[1].tr_i2c_scl_filtered */ + TRIG_IN_MUX_3_SCB_TX1 = 0x00000341u, /* scb[1].tr_tx_req */ + TRIG_IN_MUX_3_SCB_RX1 = 0x00000342u, /* scb[1].tr_rx_req */ + TRIG_IN_MUX_3_SCB_I2C_SCL2 = 0x00000343u, /* scb[2].tr_i2c_scl_filtered */ + TRIG_IN_MUX_3_SCB_TX2 = 0x00000344u, /* scb[2].tr_tx_req */ + TRIG_IN_MUX_3_SCB_RX2 = 0x00000345u, /* scb[2].tr_rx_req */ + TRIG_IN_MUX_3_SCB_I2C_SCL4 = 0x00000349u, /* scb[4].tr_i2c_scl_filtered */ + TRIG_IN_MUX_3_SCB_TX4 = 0x0000034Au, /* scb[4].tr_tx_req */ + TRIG_IN_MUX_3_SCB_RX4 = 0x0000034Bu, /* scb[4].tr_rx_req */ + TRIG_IN_MUX_3_SCB_I2C_SCL5 = 0x0000034Cu, /* scb[5].tr_i2c_scl_filtered */ + TRIG_IN_MUX_3_SCB_TX5 = 0x0000034Du, /* scb[5].tr_tx_req */ + TRIG_IN_MUX_3_SCB_RX5 = 0x0000034Eu, /* scb[5].tr_rx_req */ + TRIG_IN_MUX_3_SCB_I2C_SCL6 = 0x0000034Fu, /* scb[6].tr_i2c_scl_filtered */ + TRIG_IN_MUX_3_SCB_TX6 = 0x00000350u, /* scb[6].tr_tx_req */ + TRIG_IN_MUX_3_SCB_RX6 = 0x00000351u, /* scb[6].tr_rx_req */ + TRIG_IN_MUX_3_SMIF_TX = 0x00000364u, /* smif.tr_tx_req */ + TRIG_IN_MUX_3_SMIF_RX = 0x00000365u, /* smif.tr_rx_req */ + TRIG_IN_MUX_3_USB_DMA0 = 0x00000366u, /* usb.dma_req[0] */ + TRIG_IN_MUX_3_USB_DMA1 = 0x00000367u, /* usb.dma_req[1] */ + TRIG_IN_MUX_3_USB_DMA2 = 0x00000368u, /* usb.dma_req[2] */ + TRIG_IN_MUX_3_USB_DMA3 = 0x00000369u, /* usb.dma_req[3] */ + TRIG_IN_MUX_3_USB_DMA4 = 0x0000036Au, /* usb.dma_req[4] */ + TRIG_IN_MUX_3_USB_DMA5 = 0x0000036Bu, /* usb.dma_req[5] */ + TRIG_IN_MUX_3_USB_DMA6 = 0x0000036Cu, /* usb.dma_req[6] */ + TRIG_IN_MUX_3_USB_DMA7 = 0x0000036Du, /* usb.dma_req[7] */ + TRIG_IN_MUX_3_PASS_SAR0_DONE = 0x00000373u, /* pass.tr_sar_out[0] */ + TRIG_IN_MUX_3_CSD_SENSE = 0x00000374u, /* csd.dsi_sense_out */ + TRIG_IN_MUX_3_HSIOM_TR_OUT14 = 0x00000375u, /* peri.tr_io_input[14] */ + TRIG_IN_MUX_3_HSIOM_TR_OUT15 = 0x00000376u, /* peri.tr_io_input[15] */ + TRIG_IN_MUX_3_HSIOM_TR_OUT16 = 0x00000377u, /* peri.tr_io_input[16] */ + TRIG_IN_MUX_3_HSIOM_TR_OUT17 = 0x00000378u, /* peri.tr_io_input[17] */ + TRIG_IN_MUX_3_HSIOM_TR_OUT18 = 0x00000379u, /* peri.tr_io_input[18] */ + TRIG_IN_MUX_3_HSIOM_TR_OUT19 = 0x0000037Au, /* peri.tr_io_input[19] */ + TRIG_IN_MUX_3_HSIOM_TR_OUT20 = 0x0000037Bu, /* peri.tr_io_input[20] */ + TRIG_IN_MUX_3_HSIOM_TR_OUT21 = 0x0000037Cu, /* peri.tr_io_input[21] */ + TRIG_IN_MUX_3_HSIOM_TR_OUT22 = 0x0000037Du, /* peri.tr_io_input[22] */ + TRIG_IN_MUX_3_HSIOM_TR_OUT23 = 0x0000037Eu, /* peri.tr_io_input[23] */ + TRIG_IN_MUX_3_FAULT_TR_OUT0 = 0x00000383u, /* cpuss.tr_fault[0] */ + TRIG_IN_MUX_3_FAULT_TR_OUT1 = 0x00000384u, /* cpuss.tr_fault[1] */ + TRIG_IN_MUX_3_LPCOMP_DSI_COMP0 = 0x00000385u, /* lpcomp.dsi_comp0 */ + TRIG_IN_MUX_3_LPCOMP_DSI_COMP1 = 0x00000386u, /* lpcomp.dsi_comp1 */ + TRIG_IN_MUX_3_CANFD_TT_TR_OUT0 = 0x00000387u, /* canfd[0].tr_tmp_rtp_out[0] */ + TRIG_IN_MUX_3_PASS_CTDAC_EMPTY = 0x00000388u, /* pass.tr_ctdac_empty */ + TRIG_IN_MUX_3_PASS_CTB_CMP0 = 0x00000389u, /* pass.dsi_ctb_cmp1 */ + TRIG_IN_MUX_3_PASS_SAR1_DONE = 0x0000038Au /* pass.tr_sar_out[1] */ +} en_trig_input_tcpwm0_2_t; + +/* Trigger Input Group 4 - HSIOM trigger multiplexer */ +typedef enum +{ + TRIG_IN_MUX_4_PDMA0_TR_OUT0 = 0x00000401u, /* cpuss.dw0_tr_out[0] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT1 = 0x00000402u, /* cpuss.dw0_tr_out[1] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT2 = 0x00000403u, /* cpuss.dw0_tr_out[2] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT3 = 0x00000404u, /* cpuss.dw0_tr_out[3] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT4 = 0x00000405u, /* cpuss.dw0_tr_out[4] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT5 = 0x00000406u, /* cpuss.dw0_tr_out[5] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT6 = 0x00000407u, /* cpuss.dw0_tr_out[6] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT7 = 0x00000408u, /* cpuss.dw0_tr_out[7] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT8 = 0x00000409u, /* cpuss.dw0_tr_out[8] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT9 = 0x0000040Au, /* cpuss.dw0_tr_out[9] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT10 = 0x0000040Bu, /* cpuss.dw0_tr_out[10] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT11 = 0x0000040Cu, /* cpuss.dw0_tr_out[11] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT12 = 0x0000040Du, /* cpuss.dw0_tr_out[12] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT13 = 0x0000040Eu, /* cpuss.dw0_tr_out[13] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT14 = 0x0000040Fu, /* cpuss.dw0_tr_out[14] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT15 = 0x00000410u, /* cpuss.dw0_tr_out[15] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT16 = 0x00000411u, /* cpuss.dw0_tr_out[16] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT17 = 0x00000412u, /* cpuss.dw0_tr_out[17] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT18 = 0x00000413u, /* cpuss.dw0_tr_out[18] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT19 = 0x00000414u, /* cpuss.dw0_tr_out[19] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT20 = 0x00000415u, /* cpuss.dw0_tr_out[20] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT21 = 0x00000416u, /* cpuss.dw0_tr_out[21] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT22 = 0x00000417u, /* cpuss.dw0_tr_out[22] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT23 = 0x00000418u, /* cpuss.dw0_tr_out[23] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT24 = 0x00000419u, /* cpuss.dw0_tr_out[24] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT25 = 0x0000041Au, /* cpuss.dw0_tr_out[25] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT26 = 0x0000041Bu, /* cpuss.dw0_tr_out[26] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT27 = 0x0000041Cu, /* cpuss.dw0_tr_out[27] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT28 = 0x0000041Du, /* cpuss.dw0_tr_out[28] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT0 = 0x0000041Eu, /* cpuss.dw1_tr_out[0] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT1 = 0x0000041Fu, /* cpuss.dw1_tr_out[1] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT2 = 0x00000420u, /* cpuss.dw1_tr_out[2] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT3 = 0x00000421u, /* cpuss.dw1_tr_out[3] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT4 = 0x00000422u, /* cpuss.dw1_tr_out[4] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT5 = 0x00000423u, /* cpuss.dw1_tr_out[5] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT6 = 0x00000424u, /* cpuss.dw1_tr_out[6] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT7 = 0x00000425u, /* cpuss.dw1_tr_out[7] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT8 = 0x00000426u, /* cpuss.dw1_tr_out[8] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT9 = 0x00000427u, /* cpuss.dw1_tr_out[9] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT10 = 0x00000428u, /* cpuss.dw1_tr_out[10] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT11 = 0x00000429u, /* cpuss.dw1_tr_out[11] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT12 = 0x0000042Au, /* cpuss.dw1_tr_out[12] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT13 = 0x0000042Bu, /* cpuss.dw1_tr_out[13] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT14 = 0x0000042Cu, /* cpuss.dw1_tr_out[14] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT15 = 0x0000042Du, /* cpuss.dw1_tr_out[15] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT16 = 0x0000042Eu, /* cpuss.dw1_tr_out[16] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT17 = 0x0000042Fu, /* cpuss.dw1_tr_out[17] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT18 = 0x00000430u, /* cpuss.dw1_tr_out[18] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT19 = 0x00000431u, /* cpuss.dw1_tr_out[19] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT20 = 0x00000432u, /* cpuss.dw1_tr_out[20] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT21 = 0x00000433u, /* cpuss.dw1_tr_out[21] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT22 = 0x00000434u, /* cpuss.dw1_tr_out[22] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT23 = 0x00000435u, /* cpuss.dw1_tr_out[23] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT24 = 0x00000436u, /* cpuss.dw1_tr_out[24] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT25 = 0x00000437u, /* cpuss.dw1_tr_out[25] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT26 = 0x00000438u, /* cpuss.dw1_tr_out[26] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT27 = 0x00000439u, /* cpuss.dw1_tr_out[27] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT28 = 0x0000043Au, /* cpuss.dw1_tr_out[28] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT00 = 0x0000043Bu, /* tcpwm[0].tr_out0[0] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT10 = 0x0000043Cu, /* tcpwm[0].tr_out1[0] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT01 = 0x0000043Eu, /* tcpwm[0].tr_out0[1] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT11 = 0x0000043Fu, /* tcpwm[0].tr_out1[1] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT02 = 0x00000441u, /* tcpwm[0].tr_out0[2] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT12 = 0x00000442u, /* tcpwm[0].tr_out1[2] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT03 = 0x00000444u, /* tcpwm[0].tr_out0[3] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT13 = 0x00000445u, /* tcpwm[0].tr_out1[3] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT0256 = 0x00000453u, /* tcpwm[0].tr_out0[256] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT1256 = 0x00000454u, /* tcpwm[0].tr_out1[256] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT0257 = 0x00000456u, /* tcpwm[0].tr_out0[257] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT1257 = 0x00000457u, /* tcpwm[0].tr_out1[257] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT0258 = 0x00000459u, /* tcpwm[0].tr_out0[258] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT1258 = 0x0000045Au, /* tcpwm[0].tr_out1[258] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT0259 = 0x0000045Cu, /* tcpwm[0].tr_out0[259] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT1259 = 0x0000045Du, /* tcpwm[0].tr_out1[259] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT0260 = 0x0000045Fu, /* tcpwm[0].tr_out0[260] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT1260 = 0x00000460u, /* tcpwm[0].tr_out1[260] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT0261 = 0x00000462u, /* tcpwm[0].tr_out0[261] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT1261 = 0x00000463u, /* tcpwm[0].tr_out1[261] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT0262 = 0x00000465u, /* tcpwm[0].tr_out0[262] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT1262 = 0x00000466u, /* tcpwm[0].tr_out1[262] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT0263 = 0x00000468u, /* tcpwm[0].tr_out0[263] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT1263 = 0x00000469u, /* tcpwm[0].tr_out1[263] */ + TRIG_IN_MUX_4_MDMA_TR_OUT0 = 0x0000049Bu, /* cpuss.dmac_tr_out[0] */ + TRIG_IN_MUX_4_MDMA_TR_OUT1 = 0x0000049Cu, /* cpuss.dmac_tr_out[1] */ + TRIG_IN_MUX_4_SCB_I2C_SCL0 = 0x0000049Fu, /* scb[0].tr_i2c_scl_filtered */ + TRIG_IN_MUX_4_SCB_TX0 = 0x000004A0u, /* scb[0].tr_tx_req */ + TRIG_IN_MUX_4_SCB_RX0 = 0x000004A1u, /* scb[0].tr_rx_req */ + TRIG_IN_MUX_4_SCB_I2C_SCL1 = 0x000004A2u, /* scb[1].tr_i2c_scl_filtered */ + TRIG_IN_MUX_4_SCB_TX1 = 0x000004A3u, /* scb[1].tr_tx_req */ + TRIG_IN_MUX_4_SCB_RX1 = 0x000004A4u, /* scb[1].tr_rx_req */ + TRIG_IN_MUX_4_SCB_I2C_SCL2 = 0x000004A5u, /* scb[2].tr_i2c_scl_filtered */ + TRIG_IN_MUX_4_SCB_TX2 = 0x000004A6u, /* scb[2].tr_tx_req */ + TRIG_IN_MUX_4_SCB_RX2 = 0x000004A7u, /* scb[2].tr_rx_req */ + TRIG_IN_MUX_4_SCB_I2C_SCL4 = 0x000004ABu, /* scb[4].tr_i2c_scl_filtered */ + TRIG_IN_MUX_4_SCB_TX4 = 0x000004ACu, /* scb[4].tr_tx_req */ + TRIG_IN_MUX_4_SCB_RX4 = 0x000004ADu, /* scb[4].tr_rx_req */ + TRIG_IN_MUX_4_SCB_I2C_SCL5 = 0x000004AEu, /* scb[5].tr_i2c_scl_filtered */ + TRIG_IN_MUX_4_SCB_TX5 = 0x000004AFu, /* scb[5].tr_tx_req */ + TRIG_IN_MUX_4_SCB_RX5 = 0x000004B0u, /* scb[5].tr_rx_req */ + TRIG_IN_MUX_4_SCB_I2C_SCL6 = 0x000004B1u, /* scb[6].tr_i2c_scl_filtered */ + TRIG_IN_MUX_4_SCB_TX6 = 0x000004B2u, /* scb[6].tr_tx_req */ + TRIG_IN_MUX_4_SCB_RX6 = 0x000004B3u, /* scb[6].tr_rx_req */ + TRIG_IN_MUX_4_SMIF_TX = 0x000004C6u, /* smif.tr_tx_req */ + TRIG_IN_MUX_4_SMIF_RX = 0x000004C7u, /* smif.tr_rx_req */ + TRIG_IN_MUX_4_USB_DMA0 = 0x000004C8u, /* usb.dma_req[0] */ + TRIG_IN_MUX_4_USB_DMA1 = 0x000004C9u, /* usb.dma_req[1] */ + TRIG_IN_MUX_4_USB_DMA2 = 0x000004CAu, /* usb.dma_req[2] */ + TRIG_IN_MUX_4_USB_DMA3 = 0x000004CBu, /* usb.dma_req[3] */ + TRIG_IN_MUX_4_USB_DMA4 = 0x000004CCu, /* usb.dma_req[4] */ + TRIG_IN_MUX_4_USB_DMA5 = 0x000004CDu, /* usb.dma_req[5] */ + TRIG_IN_MUX_4_USB_DMA6 = 0x000004CEu, /* usb.dma_req[6] */ + TRIG_IN_MUX_4_USB_DMA7 = 0x000004CFu, /* usb.dma_req[7] */ + TRIG_IN_MUX_4_CSD_SENSE = 0x000004D5u, /* csd.dsi_sense_out */ + TRIG_IN_MUX_4_CSD_SAMPLE = 0x000004D6u, /* csd.dsi_sample_out */ + TRIG_IN_MUX_4_CSD_ADC_DONE = 0x000004D7u, /* csd.tr_adc_done */ + TRIG_IN_MUX_4_PASS_SAR0_DONE = 0x000004D8u, /* pass.tr_sar_out[0] */ + TRIG_IN_MUX_4_FAULT_TR_OUT0 = 0x000004D9u, /* cpuss.tr_fault[0] */ + TRIG_IN_MUX_4_FAULT_TR_OUT1 = 0x000004DAu, /* cpuss.tr_fault[1] */ + TRIG_IN_MUX_4_CTI_TR_OUT0 = 0x000004DBu, /* cpuss.cti_tr_out[0] */ + TRIG_IN_MUX_4_CTI_TR_OUT1 = 0x000004DCu, /* cpuss.cti_tr_out[1] */ + TRIG_IN_MUX_4_LPCOMP_DSI_COMP0 = 0x000004DDu, /* lpcomp.dsi_comp0 */ + TRIG_IN_MUX_4_LPCOMP_DSI_COMP1 = 0x000004DEu, /* lpcomp.dsi_comp1 */ + TRIG_IN_MUX_4_CANFD_TT_TR_OUT0 = 0x000004DFu, /* canfd[0].tr_tmp_rtp_out[0] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT29 = 0x000004E0u, /* cpuss.dw1_tr_out[29] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT30 = 0x000004E1u, /* cpuss.dw1_tr_out[30] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT31 = 0x000004E2u, /* cpuss.dw1_tr_out[31] */ + TRIG_IN_MUX_4_PASS_SAR1_DONE = 0x000004E3u, /* pass.tr_sar_out[1] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT29 = 0x000004E4u /* cpuss.dw0_tr_out[29] */ +} en_trig_input_hsiom_t; + +/* Trigger Input Group 5 - CPUSS Debug trigger multiplexer */ +typedef enum +{ + TRIG_IN_MUX_5_PDMA0_TR_OUT0 = 0x00000501u, /* cpuss.dw0_tr_out[0] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT1 = 0x00000502u, /* cpuss.dw0_tr_out[1] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT2 = 0x00000503u, /* cpuss.dw0_tr_out[2] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT3 = 0x00000504u, /* cpuss.dw0_tr_out[3] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT4 = 0x00000505u, /* cpuss.dw0_tr_out[4] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT5 = 0x00000506u, /* cpuss.dw0_tr_out[5] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT6 = 0x00000507u, /* cpuss.dw0_tr_out[6] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT7 = 0x00000508u, /* cpuss.dw0_tr_out[7] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT8 = 0x00000509u, /* cpuss.dw0_tr_out[8] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT9 = 0x0000050Au, /* cpuss.dw0_tr_out[9] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT10 = 0x0000050Bu, /* cpuss.dw0_tr_out[10] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT11 = 0x0000050Cu, /* cpuss.dw0_tr_out[11] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT12 = 0x0000050Du, /* cpuss.dw0_tr_out[12] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT13 = 0x0000050Eu, /* cpuss.dw0_tr_out[13] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT14 = 0x0000050Fu, /* cpuss.dw0_tr_out[14] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT15 = 0x00000510u, /* cpuss.dw0_tr_out[15] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT16 = 0x00000511u, /* cpuss.dw0_tr_out[16] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT17 = 0x00000512u, /* cpuss.dw0_tr_out[17] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT18 = 0x00000513u, /* cpuss.dw0_tr_out[18] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT19 = 0x00000514u, /* cpuss.dw0_tr_out[19] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT20 = 0x00000515u, /* cpuss.dw0_tr_out[20] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT21 = 0x00000516u, /* cpuss.dw0_tr_out[21] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT22 = 0x00000517u, /* cpuss.dw0_tr_out[22] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT23 = 0x00000518u, /* cpuss.dw0_tr_out[23] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT24 = 0x00000519u, /* cpuss.dw0_tr_out[24] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT25 = 0x0000051Au, /* cpuss.dw0_tr_out[25] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT26 = 0x0000051Bu, /* cpuss.dw0_tr_out[26] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT27 = 0x0000051Cu, /* cpuss.dw0_tr_out[27] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT28 = 0x0000051Du, /* cpuss.dw0_tr_out[28] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT0 = 0x0000051Eu, /* cpuss.dw1_tr_out[0] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT1 = 0x0000051Fu, /* cpuss.dw1_tr_out[1] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT2 = 0x00000520u, /* cpuss.dw1_tr_out[2] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT3 = 0x00000521u, /* cpuss.dw1_tr_out[3] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT4 = 0x00000522u, /* cpuss.dw1_tr_out[4] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT5 = 0x00000523u, /* cpuss.dw1_tr_out[5] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT6 = 0x00000524u, /* cpuss.dw1_tr_out[6] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT7 = 0x00000525u, /* cpuss.dw1_tr_out[7] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT8 = 0x00000526u, /* cpuss.dw1_tr_out[8] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT9 = 0x00000527u, /* cpuss.dw1_tr_out[9] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT10 = 0x00000528u, /* cpuss.dw1_tr_out[10] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT11 = 0x00000529u, /* cpuss.dw1_tr_out[11] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT12 = 0x0000052Au, /* cpuss.dw1_tr_out[12] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT13 = 0x0000052Bu, /* cpuss.dw1_tr_out[13] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT14 = 0x0000052Cu, /* cpuss.dw1_tr_out[14] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT15 = 0x0000052Du, /* cpuss.dw1_tr_out[15] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT16 = 0x0000052Eu, /* cpuss.dw1_tr_out[16] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT17 = 0x0000052Fu, /* cpuss.dw1_tr_out[17] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT18 = 0x00000530u, /* cpuss.dw1_tr_out[18] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT19 = 0x00000531u, /* cpuss.dw1_tr_out[19] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT20 = 0x00000532u, /* cpuss.dw1_tr_out[20] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT21 = 0x00000533u, /* cpuss.dw1_tr_out[21] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT22 = 0x00000534u, /* cpuss.dw1_tr_out[22] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT23 = 0x00000535u, /* cpuss.dw1_tr_out[23] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT24 = 0x00000536u, /* cpuss.dw1_tr_out[24] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT25 = 0x00000537u, /* cpuss.dw1_tr_out[25] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT26 = 0x00000538u, /* cpuss.dw1_tr_out[26] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT27 = 0x00000539u, /* cpuss.dw1_tr_out[27] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT28 = 0x0000053Au, /* cpuss.dw1_tr_out[28] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT00 = 0x0000053Bu, /* tcpwm[0].tr_out0[0] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT10 = 0x0000053Cu, /* tcpwm[0].tr_out1[0] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT01 = 0x0000053Eu, /* tcpwm[0].tr_out0[1] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT11 = 0x0000053Fu, /* tcpwm[0].tr_out1[1] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT02 = 0x00000541u, /* tcpwm[0].tr_out0[2] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT12 = 0x00000542u, /* tcpwm[0].tr_out1[2] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT03 = 0x00000544u, /* tcpwm[0].tr_out0[3] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT13 = 0x00000545u, /* tcpwm[0].tr_out1[3] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT0256 = 0x00000553u, /* tcpwm[0].tr_out0[256] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT1256 = 0x00000554u, /* tcpwm[0].tr_out1[256] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT0257 = 0x00000556u, /* tcpwm[0].tr_out0[257] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT1257 = 0x00000557u, /* tcpwm[0].tr_out1[257] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT0258 = 0x00000559u, /* tcpwm[0].tr_out0[258] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT1258 = 0x0000055Au, /* tcpwm[0].tr_out1[258] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT0259 = 0x0000055Cu, /* tcpwm[0].tr_out0[259] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT1259 = 0x0000055Du, /* tcpwm[0].tr_out1[259] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT0260 = 0x0000055Fu, /* tcpwm[0].tr_out0[260] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT1260 = 0x00000560u, /* tcpwm[0].tr_out1[260] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT0261 = 0x00000562u, /* tcpwm[0].tr_out0[261] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT1261 = 0x00000563u, /* tcpwm[0].tr_out1[261] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT0262 = 0x00000565u, /* tcpwm[0].tr_out0[262] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT1262 = 0x00000566u, /* tcpwm[0].tr_out1[262] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT0263 = 0x00000568u, /* tcpwm[0].tr_out0[263] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT1263 = 0x00000569u, /* tcpwm[0].tr_out1[263] */ + TRIG_IN_MUX_5_MDMA_TR_OUT0 = 0x0000059Bu, /* cpuss.dmac_tr_out[0] */ + TRIG_IN_MUX_5_MDMA_TR_OUT1 = 0x0000059Cu, /* cpuss.dmac_tr_out[1] */ + TRIG_IN_MUX_5_SCB_I2C_SCL0 = 0x0000059Fu, /* scb[0].tr_i2c_scl_filtered */ + TRIG_IN_MUX_5_SCB_TX0 = 0x000005A0u, /* scb[0].tr_tx_req */ + TRIG_IN_MUX_5_SCB_RX0 = 0x000005A1u, /* scb[0].tr_rx_req */ + TRIG_IN_MUX_5_SCB_I2C_SCL1 = 0x000005A2u, /* scb[1].tr_i2c_scl_filtered */ + TRIG_IN_MUX_5_SCB_TX1 = 0x000005A3u, /* scb[1].tr_tx_req */ + TRIG_IN_MUX_5_SCB_RX1 = 0x000005A4u, /* scb[1].tr_rx_req */ + TRIG_IN_MUX_5_SCB_I2C_SCL2 = 0x000005A5u, /* scb[2].tr_i2c_scl_filtered */ + TRIG_IN_MUX_5_SCB_TX2 = 0x000005A6u, /* scb[2].tr_tx_req */ + TRIG_IN_MUX_5_SCB_RX2 = 0x000005A7u, /* scb[2].tr_rx_req */ + TRIG_IN_MUX_5_SCB_I2C_SCL4 = 0x000005ABu, /* scb[4].tr_i2c_scl_filtered */ + TRIG_IN_MUX_5_SCB_TX4 = 0x000005ACu, /* scb[4].tr_tx_req */ + TRIG_IN_MUX_5_SCB_RX4 = 0x000005ADu, /* scb[4].tr_rx_req */ + TRIG_IN_MUX_5_SCB_I2C_SCL5 = 0x000005AEu, /* scb[5].tr_i2c_scl_filtered */ + TRIG_IN_MUX_5_SCB_TX5 = 0x000005AFu, /* scb[5].tr_tx_req */ + TRIG_IN_MUX_5_SCB_RX5 = 0x000005B0u, /* scb[5].tr_rx_req */ + TRIG_IN_MUX_5_SCB_I2C_SCL6 = 0x000005B1u, /* scb[6].tr_i2c_scl_filtered */ + TRIG_IN_MUX_5_SCB_TX6 = 0x000005B2u, /* scb[6].tr_tx_req */ + TRIG_IN_MUX_5_SCB_RX6 = 0x000005B3u, /* scb[6].tr_rx_req */ + TRIG_IN_MUX_5_SMIF_TX = 0x000005C6u, /* smif.tr_tx_req */ + TRIG_IN_MUX_5_SMIF_RX = 0x000005C7u, /* smif.tr_rx_req */ + TRIG_IN_MUX_5_USB_DMA0 = 0x000005C8u, /* usb.dma_req[0] */ + TRIG_IN_MUX_5_USB_DMA1 = 0x000005C9u, /* usb.dma_req[1] */ + TRIG_IN_MUX_5_USB_DMA2 = 0x000005CAu, /* usb.dma_req[2] */ + TRIG_IN_MUX_5_USB_DMA3 = 0x000005CBu, /* usb.dma_req[3] */ + TRIG_IN_MUX_5_USB_DMA4 = 0x000005CCu, /* usb.dma_req[4] */ + TRIG_IN_MUX_5_USB_DMA5 = 0x000005CDu, /* usb.dma_req[5] */ + TRIG_IN_MUX_5_USB_DMA6 = 0x000005CEu, /* usb.dma_req[6] */ + TRIG_IN_MUX_5_USB_DMA7 = 0x000005CFu, /* usb.dma_req[7] */ + TRIG_IN_MUX_5_CSD_SENSE = 0x000005D5u, /* csd.dsi_sense_out */ + TRIG_IN_MUX_5_CSD_SAMPLE = 0x000005D6u, /* csd.dsi_sample_out */ + TRIG_IN_MUX_5_CSD_ADC_DONE = 0x000005D7u, /* csd.tr_adc_done */ + TRIG_IN_MUX_5_PASS_SAR0_DONE = 0x000005D8u, /* pass.tr_sar_out[0] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT0 = 0x000005D9u, /* peri.tr_io_input[0] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT1 = 0x000005DAu, /* peri.tr_io_input[1] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT2 = 0x000005DBu, /* peri.tr_io_input[2] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT3 = 0x000005DCu, /* peri.tr_io_input[3] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT4 = 0x000005DDu, /* peri.tr_io_input[4] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT5 = 0x000005DEu, /* peri.tr_io_input[5] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT6 = 0x000005DFu, /* peri.tr_io_input[6] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT7 = 0x000005E0u, /* peri.tr_io_input[7] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT8 = 0x000005E1u, /* peri.tr_io_input[8] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT9 = 0x000005E2u, /* peri.tr_io_input[9] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT10 = 0x000005E3u, /* peri.tr_io_input[10] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT11 = 0x000005E4u, /* peri.tr_io_input[11] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT12 = 0x000005E5u, /* peri.tr_io_input[12] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT13 = 0x000005E6u, /* peri.tr_io_input[13] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT14 = 0x000005E7u, /* peri.tr_io_input[14] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT15 = 0x000005E8u, /* peri.tr_io_input[15] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT16 = 0x000005E9u, /* peri.tr_io_input[16] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT17 = 0x000005EAu, /* peri.tr_io_input[17] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT18 = 0x000005EBu, /* peri.tr_io_input[18] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT19 = 0x000005ECu, /* peri.tr_io_input[19] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT20 = 0x000005EDu, /* peri.tr_io_input[20] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT21 = 0x000005EEu, /* peri.tr_io_input[21] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT22 = 0x000005EFu, /* peri.tr_io_input[22] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT23 = 0x000005F0u, /* peri.tr_io_input[23] */ + TRIG_IN_MUX_5_FAULT_TR_OUT0 = 0x000005F5u, /* cpuss.tr_fault[0] */ + TRIG_IN_MUX_5_FAULT_TR_OUT1 = 0x000005F6u, /* cpuss.tr_fault[1] */ + TRIG_IN_MUX_5_CTI_TR_OUT0 = 0x000005F7u, /* cpuss.cti_tr_out[0] */ + TRIG_IN_MUX_5_CTI_TR_OUT1 = 0x000005F8u, /* cpuss.cti_tr_out[1] */ + TRIG_IN_MUX_5_LPCOMP_DSI_COMP0 = 0x000005F9u, /* lpcomp.dsi_comp0 */ + TRIG_IN_MUX_5_LPCOMP_DSI_COMP1 = 0x000005FAu, /* lpcomp.dsi_comp1 */ + TRIG_IN_MUX_5_CANFD_TT_TR_OUT0 = 0x000005FBu, /* canfd[0].tr_tmp_rtp_out[0] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT29 = 0x000005FCu, /* cpuss.dw1_tr_out[29] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT30 = 0x000005FDu, /* cpuss.dw1_tr_out[30] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT31 = 0x000005FEu, /* cpuss.dw1_tr_out[31] */ + TRIG_IN_MUX_5_PASS_SAR1_DONE = 0x000005FFu /* pass.tr_sar_out[1] */ +} en_trig_input_cpuss_cti_t; + +/* Trigger Input Group 6 - MDMA trigger multiplexer */ +typedef enum +{ + TRIG_IN_MUX_6_TCPWM0_TR_OUT0256 = 0x00000601u, /* tcpwm[0].tr_out0[256] */ + TRIG_IN_MUX_6_TCPWM0_TR_OUT1256 = 0x00000602u, /* tcpwm[0].tr_out1[256] */ + TRIG_IN_MUX_6_TCPWM0_TR_OUT0257 = 0x00000604u, /* tcpwm[0].tr_out0[257] */ + TRIG_IN_MUX_6_TCPWM0_TR_OUT1257 = 0x00000605u, /* tcpwm[0].tr_out1[257] */ + TRIG_IN_MUX_6_TCPWM0_TR_OUT0258 = 0x00000607u, /* tcpwm[0].tr_out0[258] */ + TRIG_IN_MUX_6_TCPWM0_TR_OUT1258 = 0x00000608u, /* tcpwm[0].tr_out1[258] */ + TRIG_IN_MUX_6_TCPWM0_TR_OUT0259 = 0x0000060Au, /* tcpwm[0].tr_out0[259] */ + TRIG_IN_MUX_6_TCPWM0_TR_OUT1259 = 0x0000060Bu, /* tcpwm[0].tr_out1[259] */ + TRIG_IN_MUX_6_TCPWM0_TR_OUT0260 = 0x0000060Du, /* tcpwm[0].tr_out0[260] */ + TRIG_IN_MUX_6_TCPWM0_TR_OUT1260 = 0x0000060Eu, /* tcpwm[0].tr_out1[260] */ + TRIG_IN_MUX_6_TCPWM0_TR_OUT0261 = 0x00000610u, /* tcpwm[0].tr_out0[261] */ + TRIG_IN_MUX_6_TCPWM0_TR_OUT1261 = 0x00000611u, /* tcpwm[0].tr_out1[261] */ + TRIG_IN_MUX_6_TCPWM0_TR_OUT0262 = 0x00000613u, /* tcpwm[0].tr_out0[262] */ + TRIG_IN_MUX_6_TCPWM0_TR_OUT1262 = 0x00000614u, /* tcpwm[0].tr_out1[262] */ + TRIG_IN_MUX_6_TCPWM0_TR_OUT0263 = 0x00000616u, /* tcpwm[0].tr_out0[263] */ + TRIG_IN_MUX_6_TCPWM0_TR_OUT1263 = 0x00000617u, /* tcpwm[0].tr_out1[263] */ + TRIG_IN_MUX_6_SMIF_TX = 0x00000619u, /* smif.tr_tx_req */ + TRIG_IN_MUX_6_SMIF_RX = 0x0000061Au /* smif.tr_rx_req */ +} en_trig_input_mdma_t; + +/* Trigger Input Group 7 - PERI Freeze trigger multiplexer */ +typedef enum +{ + TRIG_IN_MUX_7_CTI_TR_OUT0 = 0x00000701u, /* cpuss.cti_tr_out[0] */ + TRIG_IN_MUX_7_CTI_TR_OUT1 = 0x00000702u /* cpuss.cti_tr_out[1] */ +} en_trig_input_peri_freeze_t; + +/* Trigger Input Group 8 - Capsense trigger multiplexer */ +typedef enum +{ + TRIG_IN_MUX_8_TCPWM0_TR_OUT00 = 0x00000801u, /* tcpwm[0].tr_out0[0] */ + TRIG_IN_MUX_8_TCPWM0_TR_OUT10 = 0x00000802u, /* tcpwm[0].tr_out1[0] */ + TRIG_IN_MUX_8_TCPWM0_TR_OUT01 = 0x00000804u, /* tcpwm[0].tr_out0[1] */ + TRIG_IN_MUX_8_TCPWM0_TR_OUT11 = 0x00000805u, /* tcpwm[0].tr_out1[1] */ + TRIG_IN_MUX_8_TCPWM0_TR_OUT02 = 0x00000807u, /* tcpwm[0].tr_out0[2] */ + TRIG_IN_MUX_8_TCPWM0_TR_OUT12 = 0x00000808u, /* tcpwm[0].tr_out1[2] */ + TRIG_IN_MUX_8_TCPWM0_TR_OUT03 = 0x0000080Au, /* tcpwm[0].tr_out0[3] */ + TRIG_IN_MUX_8_TCPWM0_TR_OUT13 = 0x0000080Bu, /* tcpwm[0].tr_out1[3] */ + TRIG_IN_MUX_8_TCPWM0_TR_OUT0256 = 0x00000819u, /* tcpwm[0].tr_out0[256] */ + TRIG_IN_MUX_8_TCPWM0_TR_OUT1256 = 0x0000081Au, /* tcpwm[0].tr_out1[256] */ + TRIG_IN_MUX_8_TCPWM0_TR_OUT0257 = 0x0000081Cu, /* tcpwm[0].tr_out0[257] */ + TRIG_IN_MUX_8_TCPWM0_TR_OUT1257 = 0x0000081Du, /* tcpwm[0].tr_out1[257] */ + TRIG_IN_MUX_8_TCPWM0_TR_OUT0258 = 0x0000081Fu, /* tcpwm[0].tr_out0[258] */ + TRIG_IN_MUX_8_TCPWM0_TR_OUT1258 = 0x00000820u, /* tcpwm[0].tr_out1[258] */ + TRIG_IN_MUX_8_TCPWM0_TR_OUT0259 = 0x00000822u, /* tcpwm[0].tr_out0[259] */ + TRIG_IN_MUX_8_TCPWM0_TR_OUT1259 = 0x00000823u, /* tcpwm[0].tr_out1[259] */ + TRIG_IN_MUX_8_TCPWM0_TR_OUT0260 = 0x00000825u, /* tcpwm[0].tr_out0[260] */ + TRIG_IN_MUX_8_TCPWM0_TR_OUT1260 = 0x00000826u, /* tcpwm[0].tr_out1[260] */ + TRIG_IN_MUX_8_TCPWM0_TR_OUT0261 = 0x00000828u, /* tcpwm[0].tr_out0[261] */ + TRIG_IN_MUX_8_TCPWM0_TR_OUT1261 = 0x00000829u, /* tcpwm[0].tr_out1[261] */ + TRIG_IN_MUX_8_TCPWM0_TR_OUT0262 = 0x0000082Bu, /* tcpwm[0].tr_out0[262] */ + TRIG_IN_MUX_8_TCPWM0_TR_OUT1262 = 0x0000082Cu, /* tcpwm[0].tr_out1[262] */ + TRIG_IN_MUX_8_TCPWM0_TR_OUT0263 = 0x0000082Eu, /* tcpwm[0].tr_out0[263] */ + TRIG_IN_MUX_8_TCPWM0_TR_OUT1263 = 0x0000082Fu, /* tcpwm[0].tr_out1[263] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT0 = 0x0000086Du, /* peri.tr_io_input[0] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT1 = 0x0000086Eu, /* peri.tr_io_input[1] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT2 = 0x0000086Fu, /* peri.tr_io_input[2] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT3 = 0x00000870u, /* peri.tr_io_input[3] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT4 = 0x00000871u, /* peri.tr_io_input[4] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT5 = 0x00000872u, /* peri.tr_io_input[5] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT6 = 0x00000873u, /* peri.tr_io_input[6] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT7 = 0x00000874u, /* peri.tr_io_input[7] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT8 = 0x00000875u, /* peri.tr_io_input[8] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT9 = 0x00000876u, /* peri.tr_io_input[9] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT10 = 0x00000877u, /* peri.tr_io_input[10] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT11 = 0x00000878u, /* peri.tr_io_input[11] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT12 = 0x00000879u, /* peri.tr_io_input[12] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT13 = 0x0000087Au, /* peri.tr_io_input[13] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT14 = 0x0000087Bu, /* peri.tr_io_input[14] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT15 = 0x0000087Cu, /* peri.tr_io_input[15] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT16 = 0x0000087Du, /* peri.tr_io_input[16] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT17 = 0x0000087Eu, /* peri.tr_io_input[17] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT18 = 0x0000087Fu, /* peri.tr_io_input[18] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT19 = 0x00000880u, /* peri.tr_io_input[19] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT20 = 0x00000881u, /* peri.tr_io_input[20] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT21 = 0x00000882u, /* peri.tr_io_input[21] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT22 = 0x00000883u, /* peri.tr_io_input[22] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT23 = 0x00000884u, /* peri.tr_io_input[23] */ + TRIG_IN_MUX_8_LPCOMP_DSI_COMP0 = 0x00000889u, /* lpcomp.dsi_comp0 */ + TRIG_IN_MUX_8_LPCOMP_DSI_COMP1 = 0x0000088Au /* lpcomp.dsi_comp1 */ +} en_trig_input_csd_t; + +/* Trigger Input Group 9 - ADC trigger multiplexer */ +typedef enum +{ + TRIG_IN_MUX_9_TCPWM0_TR_OUT00 = 0x00000901u, /* tcpwm[0].tr_out0[0] */ + TRIG_IN_MUX_9_TCPWM0_TR_OUT10 = 0x00000902u, /* tcpwm[0].tr_out1[0] */ + TRIG_IN_MUX_9_TCPWM0_TR_OUT01 = 0x00000904u, /* tcpwm[0].tr_out0[1] */ + TRIG_IN_MUX_9_TCPWM0_TR_OUT11 = 0x00000905u, /* tcpwm[0].tr_out1[1] */ + TRIG_IN_MUX_9_TCPWM0_TR_OUT02 = 0x00000907u, /* tcpwm[0].tr_out0[2] */ + TRIG_IN_MUX_9_TCPWM0_TR_OUT12 = 0x00000908u, /* tcpwm[0].tr_out1[2] */ + TRIG_IN_MUX_9_TCPWM0_TR_OUT03 = 0x0000090Au, /* tcpwm[0].tr_out0[3] */ + TRIG_IN_MUX_9_TCPWM0_TR_OUT13 = 0x0000090Bu, /* tcpwm[0].tr_out1[3] */ + TRIG_IN_MUX_9_TCPWM0_TR_OUT0256 = 0x00000919u, /* tcpwm[0].tr_out0[256] */ + TRIG_IN_MUX_9_TCPWM0_TR_OUT1256 = 0x0000091Au, /* tcpwm[0].tr_out1[256] */ + TRIG_IN_MUX_9_TCPWM0_TR_OUT0257 = 0x0000091Cu, /* tcpwm[0].tr_out0[257] */ + TRIG_IN_MUX_9_TCPWM0_TR_OUT1257 = 0x0000091Du, /* tcpwm[0].tr_out1[257] */ + TRIG_IN_MUX_9_TCPWM0_TR_OUT0258 = 0x0000091Fu, /* tcpwm[0].tr_out0[258] */ + TRIG_IN_MUX_9_TCPWM0_TR_OUT1258 = 0x00000920u, /* tcpwm[0].tr_out1[258] */ + TRIG_IN_MUX_9_TCPWM0_TR_OUT0259 = 0x00000922u, /* tcpwm[0].tr_out0[259] */ + TRIG_IN_MUX_9_TCPWM0_TR_OUT1259 = 0x00000923u, /* tcpwm[0].tr_out1[259] */ + TRIG_IN_MUX_9_TCPWM0_TR_OUT0260 = 0x00000925u, /* tcpwm[0].tr_out0[260] */ + TRIG_IN_MUX_9_TCPWM0_TR_OUT1260 = 0x00000926u, /* tcpwm[0].tr_out1[260] */ + TRIG_IN_MUX_9_TCPWM0_TR_OUT0261 = 0x00000928u, /* tcpwm[0].tr_out0[261] */ + TRIG_IN_MUX_9_TCPWM0_TR_OUT1261 = 0x00000929u, /* tcpwm[0].tr_out1[261] */ + TRIG_IN_MUX_9_TCPWM0_TR_OUT0262 = 0x0000092Bu, /* tcpwm[0].tr_out0[262] */ + TRIG_IN_MUX_9_TCPWM0_TR_OUT1262 = 0x0000092Cu, /* tcpwm[0].tr_out1[262] */ + TRIG_IN_MUX_9_TCPWM0_TR_OUT0263 = 0x0000092Eu, /* tcpwm[0].tr_out0[263] */ + TRIG_IN_MUX_9_TCPWM0_TR_OUT1263 = 0x0000092Fu, /* tcpwm[0].tr_out1[263] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT0 = 0x00000961u, /* peri.tr_io_input[0] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT1 = 0x00000962u, /* peri.tr_io_input[1] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT2 = 0x00000963u, /* peri.tr_io_input[2] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT3 = 0x00000964u, /* peri.tr_io_input[3] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT4 = 0x00000965u, /* peri.tr_io_input[4] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT5 = 0x00000966u, /* peri.tr_io_input[5] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT6 = 0x00000967u, /* peri.tr_io_input[6] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT7 = 0x00000968u, /* peri.tr_io_input[7] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT8 = 0x00000969u, /* peri.tr_io_input[8] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT9 = 0x0000096Au, /* peri.tr_io_input[9] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT10 = 0x0000096Bu, /* peri.tr_io_input[10] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT11 = 0x0000096Cu, /* peri.tr_io_input[11] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT12 = 0x0000096Du, /* peri.tr_io_input[12] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT13 = 0x0000096Eu, /* peri.tr_io_input[13] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT14 = 0x0000096Fu, /* peri.tr_io_input[14] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT15 = 0x00000970u, /* peri.tr_io_input[15] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT16 = 0x00000971u, /* peri.tr_io_input[16] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT17 = 0x00000972u, /* peri.tr_io_input[17] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT18 = 0x00000973u, /* peri.tr_io_input[18] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT19 = 0x00000974u, /* peri.tr_io_input[19] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT20 = 0x00000975u, /* peri.tr_io_input[20] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT21 = 0x00000976u, /* peri.tr_io_input[21] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT22 = 0x00000977u, /* peri.tr_io_input[22] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT23 = 0x00000978u, /* peri.tr_io_input[23] */ + TRIG_IN_MUX_9_LPCOMP_DSI_COMP0 = 0x0000097Du, /* lpcomp.dsi_comp0 */ + TRIG_IN_MUX_9_LPCOMP_DSI_COMP1 = 0x0000097Eu /* lpcomp.dsi_comp1 */ +} en_trig_input_sar_adc_start_t; + +/* Trigger Input Group 10 - CAN TT Synchronization triggers */ +typedef enum +{ + TRIG_IN_MUX_10_CAN_TT_TR_OUT0 = 0x00000A01u /* canfd[0].tr_tmp_rtp_out[0] */ +} en_trig_input_cantt_t; + +/* Trigger Group Outputs */ +/* Trigger Output Group 0 - PDMA0 Request Assignments */ +typedef enum +{ + TRIG_OUT_MUX_0_PDMA0_TR_IN0 = 0x40000000u, /* cpuss.dw0_tr_in[0] */ + TRIG_OUT_MUX_0_PDMA0_TR_IN1 = 0x40000001u, /* cpuss.dw0_tr_in[1] */ + TRIG_OUT_MUX_0_PDMA0_TR_IN2 = 0x40000002u, /* cpuss.dw0_tr_in[2] */ + TRIG_OUT_MUX_0_PDMA0_TR_IN3 = 0x40000003u, /* cpuss.dw0_tr_in[3] */ + TRIG_OUT_MUX_0_PDMA0_TR_IN4 = 0x40000004u, /* cpuss.dw0_tr_in[4] */ + TRIG_OUT_MUX_0_PDMA0_TR_IN5 = 0x40000005u, /* cpuss.dw0_tr_in[5] */ + TRIG_OUT_MUX_0_PDMA0_TR_IN6 = 0x40000006u, /* cpuss.dw0_tr_in[6] */ + TRIG_OUT_MUX_0_PDMA0_TR_IN7 = 0x40000007u /* cpuss.dw0_tr_in[7] */ +} en_trig_output_pdma0_tr_t; + +/* Trigger Output Group 1 - PDMA1 Request Assignments */ +typedef enum +{ + TRIG_OUT_MUX_1_PDMA1_TR_IN0 = 0x40000100u, /* cpuss.dw1_tr_in[0] */ + TRIG_OUT_MUX_1_PDMA1_TR_IN1 = 0x40000101u, /* cpuss.dw1_tr_in[1] */ + TRIG_OUT_MUX_1_PDMA1_TR_IN2 = 0x40000102u, /* cpuss.dw1_tr_in[2] */ + TRIG_OUT_MUX_1_PDMA1_TR_IN3 = 0x40000103u, /* cpuss.dw1_tr_in[3] */ + TRIG_OUT_MUX_1_PDMA1_TR_IN4 = 0x40000104u, /* cpuss.dw1_tr_in[4] */ + TRIG_OUT_MUX_1_PDMA1_TR_IN5 = 0x40000105u, /* cpuss.dw1_tr_in[5] */ + TRIG_OUT_MUX_1_PDMA1_TR_IN6 = 0x40000106u, /* cpuss.dw1_tr_in[6] */ + TRIG_OUT_MUX_1_PDMA1_TR_IN7 = 0x40000107u /* cpuss.dw1_tr_in[7] */ +} en_trig_output_pdma1_tr_t; + +/* Trigger Output Group 2 - TCPWM0 trigger multiplexer */ +typedef enum +{ + TRIG_OUT_MUX_2_TCPWM0_TR_IN0 = 0x40000200u, /* tcpwm[0].tr_all_cnt_in[0] */ + TRIG_OUT_MUX_2_TCPWM0_TR_IN1 = 0x40000201u, /* tcpwm[0].tr_all_cnt_in[1] */ + TRIG_OUT_MUX_2_TCPWM0_TR_IN2 = 0x40000202u, /* tcpwm[0].tr_all_cnt_in[2] */ + TRIG_OUT_MUX_2_TCPWM0_TR_IN3 = 0x40000203u, /* tcpwm[0].tr_all_cnt_in[3] */ + TRIG_OUT_MUX_2_TCPWM0_TR_IN4 = 0x40000204u, /* tcpwm[0].tr_all_cnt_in[4] */ + TRIG_OUT_MUX_2_TCPWM0_TR_IN5 = 0x40000205u, /* tcpwm[0].tr_all_cnt_in[5] */ + TRIG_OUT_MUX_2_TCPWM0_TR_IN6 = 0x40000206u, /* tcpwm[0].tr_all_cnt_in[6] */ + TRIG_OUT_MUX_2_TCPWM0_TR_IN7 = 0x40000207u, /* tcpwm[0].tr_all_cnt_in[7] */ + TRIG_OUT_MUX_2_TCPWM0_TR_IN8 = 0x40000208u, /* tcpwm[0].tr_all_cnt_in[8] */ + TRIG_OUT_MUX_2_TCPWM0_TR_IN9 = 0x40000209u, /* tcpwm[0].tr_all_cnt_in[9] */ + TRIG_OUT_MUX_2_TCPWM0_TR_IN10 = 0x4000020Au, /* tcpwm[0].tr_all_cnt_in[10] */ + TRIG_OUT_MUX_2_TCPWM0_TR_IN11 = 0x4000020Bu, /* tcpwm[0].tr_all_cnt_in[11] */ + TRIG_OUT_MUX_2_TCPWM0_TR_IN12 = 0x4000020Cu, /* tcpwm[0].tr_all_cnt_in[12] */ + TRIG_OUT_MUX_2_TCPWM0_TR_IN13 = 0x4000020Du /* tcpwm[0].tr_all_cnt_in[13] */ +} en_trig_output_tcpwm0_t; + +/* Trigger Output Group 3 - TCPWM0 trigger multiplexer - 2nd */ +typedef enum +{ + TRIG_OUT_MUX_3_TCPWM1_TR_IN0 = 0x40000300u, /* tcpwm[0].tr_all_cnt_in[14] */ + TRIG_OUT_MUX_3_TCPWM1_TR_IN1 = 0x40000301u, /* tcpwm[0].tr_all_cnt_in[15] */ + TRIG_OUT_MUX_3_TCPWM1_TR_IN2 = 0x40000302u, /* tcpwm[0].tr_all_cnt_in[16] */ + TRIG_OUT_MUX_3_TCPWM1_TR_IN3 = 0x40000303u, /* tcpwm[0].tr_all_cnt_in[17] */ + TRIG_OUT_MUX_3_TCPWM1_TR_IN4 = 0x40000304u, /* tcpwm[0].tr_all_cnt_in[18] */ + TRIG_OUT_MUX_3_TCPWM1_TR_IN5 = 0x40000305u, /* tcpwm[0].tr_all_cnt_in[19] */ + TRIG_OUT_MUX_3_TCPWM1_TR_IN6 = 0x40000306u, /* tcpwm[0].tr_all_cnt_in[20] */ + TRIG_OUT_MUX_3_TCPWM1_TR_IN7 = 0x40000307u, /* tcpwm[0].tr_all_cnt_in[21] */ + TRIG_OUT_MUX_3_TCPWM1_TR_IN8 = 0x40000308u, /* tcpwm[0].tr_all_cnt_in[22] */ + TRIG_OUT_MUX_3_TCPWM1_TR_IN9 = 0x40000309u, /* tcpwm[0].tr_all_cnt_in[23] */ + TRIG_OUT_MUX_3_TCPWM1_TR_IN10 = 0x4000030Au, /* tcpwm[0].tr_all_cnt_in[24] */ + TRIG_OUT_MUX_3_TCPWM1_TR_IN11 = 0x4000030Bu, /* tcpwm[0].tr_all_cnt_in[25] */ + TRIG_OUT_MUX_3_TCPWM1_TR_IN12 = 0x4000030Cu, /* tcpwm[0].tr_all_cnt_in[26] */ + TRIG_OUT_MUX_3_TCPWM1_TR_IN13 = 0x4000030Du /* tcpwm[0].tr_all_cnt_in[27] */ +} en_trig_output_tcpwm0_2_t; + +/* Trigger Output Group 4 - HSIOM trigger multiplexer */ +typedef enum +{ + TRIG_OUT_MUX_4_HSIOM_TR_IO_OUTPUT0 = 0x40000400u, /* peri.tr_io_output[0] */ + TRIG_OUT_MUX_4_HSIOM_TR_IO_OUTPUT1 = 0x40000401u /* peri.tr_io_output[1] */ +} en_trig_output_hsiom_t; + +/* Trigger Output Group 5 - CPUSS Debug trigger multiplexer */ +typedef enum +{ + TRIG_OUT_MUX_5_CPUSS_CTI_TR_IN0 = 0x40000500u, /* cpuss.cti_tr_in[0] */ + TRIG_OUT_MUX_5_CPUSS_CTI_TR_IN1 = 0x40000501u /* cpuss.cti_tr_in[1] */ +} en_trig_output_cpuss_cti_t; + +/* Trigger Output Group 6 - MDMA trigger multiplexer */ +typedef enum +{ + TRIG_OUT_MUX_6_MDMA_TR_IN0 = 0x40000600u, /* cpuss.dmac_tr_in[0] */ + TRIG_OUT_MUX_6_MDMA_TR_IN1 = 0x40000601u /* cpuss.dmac_tr_in[1] */ +} en_trig_output_mdma_t; + +/* Trigger Output Group 7 - PERI Freeze trigger multiplexer */ +typedef enum +{ + TRIG_OUT_MUX_7_DEBUG_FREEZE_TR_IN = 0x40000700u, /* peri.tr_dbg_freeze */ + TRIG_OUT_MUX_7_TCPWM_DEBUG_FREEZE_TR_IN = 0x40000701u /* tcpwm[0].tr_debug_freeze */ +} en_trig_output_peri_freeze_t; + +/* Trigger Output Group 8 - Capsense trigger multiplexer */ +typedef enum +{ + TRIG_OUT_MUX_8_CSD_DSI_START = 0x40000800u /* csd.dsi_start */ +} en_trig_output_csd_t; + +/* Trigger Output Group 9 - ADC trigger multiplexer */ +typedef enum +{ + TRIG_OUT_MUX_9_PASS_TR_SAR_IN0 = 0x40000900u, /* pass.tr_sar_in[0] */ + TRIG_OUT_MUX_9_PASS_TR_SAR_IN1 = 0x40000901u /* pass.tr_sar_in[1] */ +} en_trig_output_sar_adc_start_t; + +/* Trigger Output Group 10 - CAN TT Synchronization triggers */ +typedef enum +{ + TRIG_OUT_MUX_10_CAN_TT_TR_IN0 = 0x40000A00u /* canfd[0].tr_evt_swt_in[0] */ +} en_trig_output_cantt_t; + +/* Trigger Output Group 0 - SCB PDMA0 Triggers (OneToOne) */ +typedef enum +{ + TRIG_OUT_1TO1_0_SCB0_TX_TO_PDMA0_TR_IN16 = 0x40001000u, /* From scb[0].tr_tx_req to cpuss.dw0_tr_in[16] */ + TRIG_OUT_1TO1_0_SCB0_RX_TO_PDMA0_TR_IN17 = 0x40001001u, /* From scb[0].tr_rx_req to cpuss.dw0_tr_in[17] */ + TRIG_OUT_1TO1_0_SCB1_TX_TO_PDMA0_TR_IN18 = 0x40001002u, /* From scb[1].tr_tx_req to cpuss.dw0_tr_in[18] */ + TRIG_OUT_1TO1_0_SCB1_RX_TO_PDMA0_TR_IN19 = 0x40001003u, /* From scb[1].tr_rx_req to cpuss.dw0_tr_in[19] */ + TRIG_OUT_1TO1_0_SCB2_TX_TO_PDMA0_TR_IN20 = 0x40001004u, /* From scb[2].tr_tx_req to cpuss.dw0_tr_in[20] */ + TRIG_OUT_1TO1_0_SCB2_RX_TO_PDMA0_TR_IN21 = 0x40001005u, /* From scb[2].tr_rx_req to cpuss.dw0_tr_in[21] */ + TRIG_OUT_1TO1_0_DUMMY_TO_PDMA0_TR_IN22 = 0x40001006u, /* From cpuss.zero to cpuss.dw0_tr_in[22] */ + TRIG_OUT_1TO1_0_DUMMY_TO_PDMA0_TR_IN23 = 0x40001007u, /* From cpuss.zero to cpuss.dw0_tr_in[23] */ + TRIG_OUT_1TO1_0_SCB4_TX_TO_PDMA0_TR_IN24 = 0x40001008u, /* From scb[4].tr_tx_req to cpuss.dw0_tr_in[24] */ + TRIG_OUT_1TO1_0_SCB4_RX_TO_PDMA0_TR_IN25 = 0x40001009u, /* From scb[4].tr_rx_req to cpuss.dw0_tr_in[25] */ + TRIG_OUT_1TO1_0_SCB5_TX_TO_PDMA0_TR_IN26 = 0x4000100Au, /* From scb[5].tr_tx_req to cpuss.dw0_tr_in[26] */ + TRIG_OUT_1TO1_0_SCB5_RX_TO_PDMA0_TR_IN27 = 0x4000100Bu /* From scb[5].tr_rx_req to cpuss.dw0_tr_in[27] */ +} en_trig_output_1to1_scb_pdma0_tr_t; + +/* Trigger Output Group 1 - SCB PDMA1 Triggers (OneToOne) */ +typedef enum +{ + TRIG_OUT_1TO1_1_SCB6_TX_TO_PDMA1_TR_IN8 = 0x40001100u, /* From scb[6].tr_tx_req to cpuss.dw1_tr_in[8] */ + TRIG_OUT_1TO1_1_SCB6_RX_TO_PDMA1_TR_IN9 = 0x40001101u, /* From scb[6].tr_rx_req to cpuss.dw1_tr_in[9] */ + TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN10 = 0x40001102u, /* From cpuss.zero to cpuss.dw1_tr_in[10] */ + TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN11 = 0x40001103u, /* From cpuss.zero to cpuss.dw1_tr_in[11] */ + TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN12 = 0x40001104u, /* From cpuss.zero to cpuss.dw1_tr_in[12] */ + TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN13 = 0x40001105u, /* From cpuss.zero to cpuss.dw1_tr_in[13] */ + TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN14 = 0x40001106u, /* From cpuss.zero to cpuss.dw1_tr_in[14] */ + TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN15 = 0x40001107u, /* From cpuss.zero to cpuss.dw1_tr_in[15] */ + TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN16 = 0x40001108u, /* From cpuss.zero to cpuss.dw1_tr_in[16] */ + TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN17 = 0x40001109u, /* From cpuss.zero to cpuss.dw1_tr_in[17] */ + TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN18 = 0x4000110Au, /* From cpuss.zero to cpuss.dw1_tr_in[18] */ + TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN19 = 0x4000110Bu, /* From cpuss.zero to cpuss.dw1_tr_in[19] */ + TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN20 = 0x4000110Cu, /* From cpuss.zero to cpuss.dw1_tr_in[20] */ + TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN21 = 0x4000110Du /* From cpuss.zero to cpuss.dw1_tr_in[21] */ +} en_trig_output_1to1_scb_pdma1_tr_t; + +/* Trigger Output Group 2 - PASS to PDMA0 direct connect (OneToOne) */ +typedef enum +{ + TRIG_OUT_1TO1_2_PASS_SAR0_DONE_TO_PDMA0_TR_IN28 = 0x40001200u /* From pass.tr_sar_out[0] to cpuss.dw0_tr_in[28] */ +} en_trig_output_1to1_sar0_to_pdma1_t; + +/* Trigger Output Group 3 - (OneToOne) */ +typedef enum +{ + TRIG_OUT_1TO1_3_SMIF_TX_TO_PDMA1_TR_IN22 = 0x40001300u, /* From smif.tr_tx_req to cpuss.dw1_tr_in[22] */ + TRIG_OUT_1TO1_3_SMIF_RX_TO_PDMA1_TR_IN23 = 0x40001301u, /* From smif.tr_rx_req to cpuss.dw1_tr_in[23] */ + TRIG3_OUT_1TO1_CPUSS_DW1_TR_IN24 = 0x40001302u, /* From cpuss.zero to cpuss.dw1_tr_in[24] */ + TRIG3_OUT_1TO1_CPUSS_DW1_TR_IN25 = 0x40001303u, /* From cpuss.zero to cpuss.dw1_tr_in[25] */ + TRIG3_OUT_1TO1_CPUSS_DW1_TR_IN26 = 0x40001304u, /* From cpuss.zero to cpuss.dw1_tr_in[26] */ + TRIG3_OUT_1TO1_CPUSS_DW1_TR_IN27 = 0x40001305u, /* From cpuss.zero to cpuss.dw1_tr_in[27] */ + TRIG3_OUT_1TO1_CPUSS_DW1_TR_IN28 = 0x40001306u /* From cpuss.zero to cpuss.dw1_tr_in[28] */ +} en_trig_output_1to1_smif_to_pdma1_t; + +/* Trigger Output Group 4 - CAN DW triggers (OneToOne) */ +typedef enum +{ + TRIG_OUT_1TO1_4_CAN_DBG_TO_PDMA1_TR_IN29 = 0x40001400u, /* From canfd[0].tr_dbg_dma_req[0] to cpuss.dw1_tr_in[29] */ + TRIG_OUT_1TO1_4_CAN_FIFO0_TO_PDMA1_TR_IN30 = 0x40001401u, /* From canfd[0].tr_fifo0[0] to cpuss.dw1_tr_in[30] */ + TRIG_OUT_1TO1_4_CAN_FIFO1_TO_PDMA1_TR_IN31 = 0x40001402u /* From canfd[0].tr_fifo1[0] to cpuss.dw1_tr_in[31] */ +} en_trig_output_1to1_can_dw_tr_t; + +/* Trigger Output Group 5 - USB PDMA0 Triggers (OneToOne) */ +typedef enum +{ + TRIG_OUT_1TO1_5_USB_DMA0_TO_PDMA0_TR_IN8 = 0x40001500u, /* From usb.dma_req[0] to cpuss.dw0_tr_in[8] */ + TRIG_OUT_1TO1_5_USB_DMA1_TO_PDMA0_TR_IN9 = 0x40001501u, /* From usb.dma_req[1] to cpuss.dw0_tr_in[9] */ + TRIG_OUT_1TO1_5_USB_DMA2_TO_PDMA0_TR_IN10 = 0x40001502u, /* From usb.dma_req[2] to cpuss.dw0_tr_in[10] */ + TRIG_OUT_1TO1_5_USB_DMA3_TO_PDMA0_TR_IN11 = 0x40001503u, /* From usb.dma_req[3] to cpuss.dw0_tr_in[11] */ + TRIG_OUT_1TO1_5_USB_DMA4_TO_PDMA0_TR_IN12 = 0x40001504u, /* From usb.dma_req[4] to cpuss.dw0_tr_in[12] */ + TRIG_OUT_1TO1_5_USB_DMA5_TO_PDMA0_TR_IN13 = 0x40001505u, /* From usb.dma_req[5] to cpuss.dw0_tr_in[13] */ + TRIG_OUT_1TO1_5_USB_DMA6_TO_PDMA0_TR_IN14 = 0x40001506u, /* From usb.dma_req[6] to cpuss.dw0_tr_in[14] */ + TRIG_OUT_1TO1_5_USB_DMA7_TO_PDMA0_TR_IN15 = 0x40001507u /* From usb.dma_req[7] to cpuss.dw0_tr_in[15] */ +} en_trig_output_1to1_usb_pdma0_tr_t; + +/* Trigger Output Group 6 - USB PDMA0 Acknowledge Triggers (OneToOne) */ +typedef enum +{ + TRIG_OUT_1TO1_6_PDMA0_TR_OUT8_TO_USB_ACK0 = 0x40001600u, /* From cpuss.dw0_tr_out[8] to usb.dma_burstend[0] */ + TRIG_OUT_1TO1_6_PDMA0_TR_OUT9_TO_USB_ACK1 = 0x40001601u, /* From cpuss.dw0_tr_out[9] to usb.dma_burstend[1] */ + TRIG_OUT_1TO1_6_PDMA0_TR_OUT10_TO_USB_ACK2 = 0x40001602u, /* From cpuss.dw0_tr_out[10] to usb.dma_burstend[2] */ + TRIG_OUT_1TO1_6_PDMA0_TR_OUT11_TO_USB_ACK3 = 0x40001603u, /* From cpuss.dw0_tr_out[11] to usb.dma_burstend[3] */ + TRIG_OUT_1TO1_6_PDMA0_TR_OUT12_TO_USB_ACK4 = 0x40001604u, /* From cpuss.dw0_tr_out[12] to usb.dma_burstend[4] */ + TRIG_OUT_1TO1_6_PDMA0_TR_OUT13_TO_USB_ACK5 = 0x40001605u, /* From cpuss.dw0_tr_out[13] to usb.dma_burstend[5] */ + TRIG_OUT_1TO1_6_PDMA0_TR_OUT14_TO_USB_ACK6 = 0x40001606u, /* From cpuss.dw0_tr_out[14] to usb.dma_burstend[6] */ + TRIG_OUT_1TO1_6_PDMA0_TR_OUT15_TO_USB_ACK7 = 0x40001607u /* From cpuss.dw0_tr_out[15] to usb.dma_burstend[7] */ +} en_trig_output_1to1_usb_pdma0_ack_tr_t; + +/* Trigger Output Group 7 - Acknowledge dma request triggers from DW0 to CAN (OneToOne) */ +typedef enum +{ + TRIG_OUT_1TO1_7_PDMA1_TR_OUT29_ACK_TO_CAN_0 = 0x40001700u /* From cpuss.dw1_tr_out[29] to canfd[0].tr_dbg_dma_ack[0] */ +} en_trig_output_1to1_can0_dw_ack_t; + +/* Trigger Output Group 8 - PASS SAR1 to PDMA0 direct connect (OneToOne) */ +typedef enum +{ + TRIG_OUT_1TO1_8_PASS_SAR1_DONE_TO_PDMA0_TR_IN29 = 0x40001800u /* From pass.tr_sar_out[1] to cpuss.dw0_tr_in[29] */ +} en_trig_output_1to1_sar1_to_pdma1_t; + +/* Level or edge detection setting for a trigger mux */ +typedef enum +{ + /* The trigger is a simple level output */ + TRIGGER_TYPE_LEVEL = 0u, + /* The trigger is synchronized to the consumer blocks clock + and a two cycle pulse is generated on this clock */ + TRIGGER_TYPE_EDGE = 1u +} en_trig_type_t; + +/* Trigger Type Defines */ +/* CANFD Trigger Types */ +#define TRIGGER_TYPE_CANFD_TR_DBG_DMA_ACK TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CANFD_TR_DBG_DMA_REQ TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_CANFD_TR_EVT_SWT_IN TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CANFD_TR_FIFO0 TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_CANFD_TR_FIFO1 TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_CANFD_TR_TMP_RTP_OUT TRIGGER_TYPE_EDGE +/* CPUSS Trigger Types */ +#define TRIGGER_TYPE_CPUSS_CTI_TR_IN TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_CTI_TR_OUT TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_DMAC_TR_IN__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_CPUSS_DMAC_TR_IN__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_DMAC_TR_OUT TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_DW0_TR_IN__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_CPUSS_DW0_TR_IN__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_DW0_TR_OUT TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_DW1_TR_IN__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_CPUSS_DW1_TR_IN__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_DW1_TR_OUT TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_TR_FAULT TRIGGER_TYPE_EDGE +/* CSD Trigger Types */ +#define TRIGGER_TYPE_CSD_DSI_SAMPLE_OUT TRIGGER_TYPE_EDGE +/* LPCOMP Trigger Types */ +#define TRIGGER_TYPE_LPCOMP_DSI_COMP0 TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_LPCOMP_DSI_COMP1 TRIGGER_TYPE_LEVEL +/* PASS Trigger Types */ +#define TRIGGER_TYPE_PASS_DSI_CTB_CMP0__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_PASS_DSI_CTB_CMP0__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_PASS_DSI_CTB_CMP1__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_PASS_DSI_CTB_CMP1__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_PASS_TR_CTDAC_EMPTY TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_PASS_TR_SAR_IN__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_PASS_TR_SAR_IN__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_PASS_TR_SAR_OUT TRIGGER_TYPE_EDGE +/* PERI Trigger Types */ +#define TRIGGER_TYPE_PERI_TR_DBG_FREEZE TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_PERI_TR_IO_INPUT__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_PERI_TR_IO_INPUT__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_PERI_TR_IO_OUTPUT__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_PERI_TR_IO_OUTPUT__EDGE TRIGGER_TYPE_EDGE +/* SCB Trigger Types */ +#define TRIGGER_TYPE_SCB_TR_I2C_SCL_FILTERED TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_SCB_TR_RX_REQ TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_SCB_TR_TX_REQ TRIGGER_TYPE_LEVEL +/* SMIF Trigger Types */ +#define TRIGGER_TYPE_SMIF_TR_RX_REQ TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_SMIF_TR_TX_REQ TRIGGER_TYPE_LEVEL +/* TCPWM Trigger Types */ +#define TRIGGER_TYPE_TCPWM_TR_DEBUG_FREEZE TRIGGER_TYPE_LEVEL +/* USB Trigger Types */ +#define TRIGGER_TYPE_USB_DMA_BURSTEND TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_USB_DMA_REQ TRIGGER_TYPE_EDGE + +/* Bus masters */ +typedef enum +{ + CPUSS_MS_ID_CM0 = 0, + CPUSS_MS_ID_CRYPTO = 1, + CPUSS_MS_ID_DW0 = 2, + CPUSS_MS_ID_DW1 = 3, + CPUSS_MS_ID_DMAC = 4, + CPUSS_MS_ID_SLOW0 = 5, + CPUSS_MS_ID_SLOW1 = 6, + CPUSS_MS_ID_CM4 = 14, + CPUSS_MS_ID_TC = 15 +} en_prot_master_t; + +/* Pointer to device configuration structure */ +#define CY_DEVICE_CFG (&cy_deviceIpBlockCfgPSoC6_04) + +/* Include IP definitions */ +#include "ip/cyip_sflash.h" +#include "ip/cyip_peri_v2.h" +#include "ip/cyip_peri_ms_v2.h" +#include "ip/cyip_crypto_v2.h" +#include "ip/cyip_cpuss_v2.h" +#include "ip/cyip_fault_v2.h" +#include "ip/cyip_ipc_v2.h" +#include "ip/cyip_prot_v2.h" +#include "ip/cyip_flashc_v2.h" +#include "ip/cyip_srss.h" +#include "ip/cyip_backup.h" +#include "ip/cyip_dw_v2.h" +#include "ip/cyip_dmac_v2.h" +#include "ip/cyip_efuse.h" +#include "ip/cyip_efuse_data_psoc6_04.h" +#include "ip/cyip_hsiom_v2.h" +#include "ip/cyip_gpio_v2.h" +#include "ip/cyip_smartio_v2.h" +#include "ip/cyip_lpcomp.h" +#include "ip/cyip_csd.h" +#include "ip/cyip_tcpwm_v2.h" +#include "ip/cyip_lcd_v2.h" +#include "ip/cyip_usbfs.h" +#include "ip/cyip_smif.h" +#include "ip/cyip_canfd.h" +#include "ip/cyip_scb.h" +#include "ip/cyip_scb.h" +#include "ip/cyip_ctbm_v2.h" +#include "ip/cyip_ctdac.h" +#include "ip/cyip_sar_v2.h" +#include "ip/cyip_pass_v2.h" + +/* IP type definitions */ +typedef SFLASH_V1_Type SFLASH_Type; +typedef PERI_GR_V2_Type PERI_GR_Type; +typedef PERI_TR_GR_V2_Type PERI_TR_GR_Type; +typedef PERI_TR_1TO1_GR_V2_Type PERI_TR_1TO1_GR_Type; +typedef PERI_V2_Type PERI_Type; +typedef PERI_MS_PPU_PR_V2_Type PERI_MS_PPU_PR_Type; +typedef PERI_MS_PPU_FX_V2_Type PERI_MS_PPU_FX_Type; +typedef PERI_MS_V2_Type PERI_MS_Type; +typedef CRYPTO_V2_Type CRYPTO_Type; +typedef CPUSS_V2_Type CPUSS_Type; +typedef FAULT_STRUCT_V2_Type FAULT_STRUCT_Type; +typedef FAULT_V2_Type FAULT_Type; +typedef IPC_STRUCT_V2_Type IPC_STRUCT_Type; +typedef IPC_INTR_STRUCT_V2_Type IPC_INTR_STRUCT_Type; +typedef IPC_V2_Type IPC_Type; +typedef PROT_SMPU_SMPU_STRUCT_V2_Type PROT_SMPU_SMPU_STRUCT_Type; +typedef PROT_SMPU_V2_Type PROT_SMPU_Type; +typedef PROT_MPU_MPU_STRUCT_V2_Type PROT_MPU_MPU_STRUCT_Type; +typedef PROT_MPU_V2_Type PROT_MPU_Type; +typedef PROT_V2_Type PROT_Type; +typedef FLASHC_FM_CTL_V2_Type FLASHC_FM_CTL_Type; +typedef FLASHC_V2_Type FLASHC_Type; +typedef MCWDT_STRUCT_V1_Type MCWDT_STRUCT_Type; +typedef SRSS_V1_Type SRSS_Type; +typedef BACKUP_V1_Type BACKUP_Type; +typedef DW_CH_STRUCT_V2_Type DW_CH_STRUCT_Type; +typedef DW_V2_Type DW_Type; +typedef DMAC_CH_V2_Type DMAC_CH_Type; +typedef DMAC_V2_Type DMAC_Type; +typedef EFUSE_V1_Type EFUSE_Type; +typedef HSIOM_PRT_V2_Type HSIOM_PRT_Type; +typedef HSIOM_V2_Type HSIOM_Type; +typedef GPIO_PRT_V2_Type GPIO_PRT_Type; +typedef GPIO_V2_Type GPIO_Type; +typedef SMARTIO_PRT_V2_Type SMARTIO_PRT_Type; +typedef SMARTIO_V2_Type SMARTIO_Type; +typedef LPCOMP_V1_Type LPCOMP_Type; +typedef CSD_V1_Type CSD_Type; +typedef TCPWM_GRP_CNT_V2_Type TCPWM_GRP_CNT_Type; +typedef TCPWM_GRP_V2_Type TCPWM_GRP_Type; +typedef TCPWM_V2_Type TCPWM_Type; +typedef LCD_V2_Type LCD_Type; +typedef USBFS_USBDEV_V1_Type USBFS_USBDEV_Type; +typedef USBFS_USBLPM_V1_Type USBFS_USBLPM_Type; +typedef USBFS_USBHOST_V1_Type USBFS_USBHOST_Type; +typedef USBFS_V1_Type USBFS_Type; +typedef SMIF_DEVICE_V1_Type SMIF_DEVICE_Type; +typedef SMIF_V1_Type SMIF_Type; +typedef CANFD_CH_M_TTCAN_V1_Type CANFD_CH_M_TTCAN_Type; +typedef CANFD_CH_V1_Type CANFD_CH_Type; +typedef CANFD_V1_Type CANFD_Type; +typedef CySCB_V1_Type CySCB_Type; +typedef CTBM_V2_Type CTBM_Type; +typedef CTDAC_V1_Type CTDAC_Type; +typedef SAR_V2_Type SAR_Type; +typedef PASS_TIMER_V2_Type PASS_TIMER_Type; +typedef PASS_LPOSC_V2_Type PASS_LPOSC_Type; +typedef PASS_FIFO_V2_Type PASS_FIFO_Type; +typedef PASS_AREFV2_V2_Type PASS_AREFV2_Type; +typedef PASS_V2_Type PASS_Type; + +/* Parameter Defines */ +/* Number of TTCAN instances */ +#define CANFD_CAN_NR 1u +/* ECC logic present or not */ +#define CANFD_ECC_PRESENT 0u +/* address included in ECC logic or not */ +#define CANFD_ECC_ADDR_PRESENT 0u +/* Time Stamp counter present or not (required for instance 0, otherwise not + allowed) */ +#define CANFD_TS_PRESENT 1u +/* Message RAM size in KB */ +#define CANFD_MRAM_SIZE 4u +/* Message RAM address width */ +#define CANFD_MRAM_ADDR_WIDTH 10u +/* UDB present or not ('0': no, '1': yes) */ +#define CPUSS_UDB_PRESENT 0u +/* MBIST MMIO for Synopsys MBIST ('0': no, '1': yes). Set this to '1' only for the + chips which doesn't use mxdft. */ +#define CPUSS_MBIST_MMIO_PRESENT 1u +/* System RAM 0 size in kilobytes */ +#define CPUSS_SRAM0_SIZE 128u +/* Number of macros used to implement System RAM 0. Example: 8 if 256 KB System + SRAM0 is implemented with 8 32KB macros. */ +#define CPUSS_RAMC0_MACRO_NR 4u +/* System RAM 1 present or not (0=No, 1=Yes) */ +#define CPUSS_RAMC1_PRESENT 0u +/* System RAM 1 size in kilobytes */ +#define CPUSS_SRAM1_SIZE 1u +/* Number of macros used to implement System RAM 1. Example: 8 if 256 KB System + RAM 1 is implemented with 8 32KB macros. */ +#define CPUSS_RAMC1_MACRO_NR 1u +/* System RAM 2 present or not (0=No, 1=Yes) */ +#define CPUSS_RAMC2_PRESENT 0u +/* System RAM 2 size in kilobytes */ +#define CPUSS_SRAM2_SIZE 1u +/* Number of macros used to implement System RAM 2. Example: 8 if 256 KB System + RAM 2 is implemented with 8 32KB macros. */ +#define CPUSS_RAMC2_MACRO_NR 1u +/* System SRAM(s) ECC present or not ('0': no, '1': yes) */ +#define CPUSS_RAMC_ECC_PRESENT 0u +/* System SRAM(s) address ECC present or not ('0': no, '1': yes) */ +#define CPUSS_RAMC_ECC_ADDR_PRESENT 0u +/* ECC present in either system RAM or interrupt handler (RAMC_ECC_PRESENT) */ +#define CPUSS_ECC_PRESENT 0u +/* DataWire SRAMs ECC present or not ('0': no, '1': yes) */ +#define CPUSS_DW_ECC_PRESENT 0u +/* DataWire SRAMs address ECC present or not ('0': no, '1': yes) */ +#define CPUSS_DW_ECC_ADDR_PRESENT 0u +/* System ROM size in KB */ +#define CPUSS_ROM_SIZE 64u +/* Number of macros used to implement system ROM. Example: 4 if 512 KB system ROM + is implemented with 4 128KB macros. */ +#define CPUSS_ROMC_MACRO_NR 1u +/* Flash memory present or not ('0': no, '1': yes) */ +#define CPUSS_FLASHC_PRESENT 1u +/* Flash memory type ('0' : SONOS, '1': ECT) */ +#define CPUSS_FLASHC_ECT 0u +/* Flash main region size in KB */ +#define CPUSS_FLASH_SIZE 256u +/* Flash work region size in KB (EEPROM emulation, data) */ +#define CPUSS_WFLASH_SIZE 0u +/* Flash supervisory region size in KB */ +#define CPUSS_SFLASH_SIZE 32u +/* Flash data output word size (in Bytes) */ +#define CPUSS_FLASHC_MAIN_DATA_WIDTH 16u +/* SONOS Flash RWW present or not ('0': no, '1': yes) When RWW is '0', No special + sectors present in Flash. Part of main sector 0 is allowcated for Supervisory + Flash, and no Work Flash present. */ +#define CPUSS_FLASHC_SONOS_RWW 1u +/* SONOS Flash, number of main sectors. */ +#define CPUSS_FLASHC_SONOS_MAIN_SECTORS 2u +/* SONOS Flash, number of rows per main sector. */ +#define CPUSS_FLASHC_SONOS_MAIN_ROWS 256u +/* SONOS Flash, number of words per row of main sector. */ +#define CPUSS_FLASHC_SONOS_MAIN_WORDS 128u +/* SONOS Flash, number of special sectors. */ +#define CPUSS_FLASHC_SONOS_SPL_SECTORS 1u +/* SONOS Flash, number of rows per special sector. */ +#define CPUSS_FLASHC_SONOS_SPL_ROWS 64u +/* Flash memory ECC present or not ('0': no, '1': yes) */ +#define CPUSS_FLASHC_FLASH_ECC_PRESENT 0u +/* Flash cache SRAM(s) ECC present or not ('0': no, '1': yes) */ +#define CPUSS_FLASHC_RAM_ECC_PRESENT 0u +/* Number of external slaves directly connected to slow AHB-Lite infrastructure. + Maximum nubmer of slave supported is 4. Width of this parameter is 4-bits. + 1-bit mask for each slave indicating present or not. Example: 4'b0011 - slave + 0 and slave 1 are present. Note: The SLOW_SLx_ADDR and SLOW_SLx_MASK + parameters (for the slaves present) should be derived from the Memory Map. */ +#define CPUSS_SLOW_SL_PRESENT 1u +/* Number of external slaves directly connected to fast AHB-Lite infrastructure. + Maximum nubmer of slave supported is 4. Width of this parameter is 4-bits. + 1-bit mask for each slave indicating present or not. Example: 4'b0011 - slave + 0 and slave 1 are present. Note: The FAST_SLx_ADDR and FAST_SLx_MASK + parameters (for the slaves present) should be derived from the Memory Map. */ +#define CPUSS_FAST_SL_PRESENT 1u +/* Number of external masters driving the slow AHB-Lite infrastructure. Maximum + number of masters supported is 2. Width of this parameter is 2-bits. 1-bit + mask for each master indicating present or not. Example: 2'b01 - master 0 is + present. */ +#define CPUSS_SLOW_MS_PRESENT 0u +/* System interrupt functionality present or not ('0': no; '1': yes). Not used for + CM0+ PCU, which always uses system interrupt functionality. */ +#define CPUSS_SYSTEM_IRQ_PRESENT 0u +/* Number of total interrupt request inputs to CPUSS */ +#define CPUSS_SYSTEM_INT_NR 175u +/* Number of DeepSleep wakeup interrupt inputs to CPUSS */ +#define CPUSS_SYSTEM_DPSLP_INT_NR 45u +/* CM4 CPU present or not ('0': no, '1': yes) */ +#define CPUSS_CM4_PRESENT 1u +/* Width of the CM4 interrupt priority bits. Legal range [3,8] Example: 3 = 8 + levels of priority 8 = 256 levels of priority */ +#define CPUSS_CM4_LVL_WIDTH 3u +/* CM4 Floating point unit present or not (0=No, 1=Yes) */ +#define CPUSS_CM4_FPU_PRESENT 1u +/* Debug level. Legal range [0,3] (0= No support, 1= Minimum: CM0/4 both 2 + breakpoints +1 watchpoint, 2= Full debug: CM0/4 have 4/6 breakpoints, 2/4 + watchpoints and 0/2 literal compare, 3= Full debug + data matching) */ +#define CPUSS_DEBUG_LVL 3u +/* Trace level. Legal range [0,2] (0= No tracing, 1= ITM + TPIU + SWO, 2= ITM + + ETM + TPIU + SWO) Note: CM4 HTM is not supported. Hence vaule 3 for trace + level is not supported in CPUSS. */ +#define CPUSS_TRACE_LVL 2u +/* Embedded Trace Buffer present or not (0=No, 1=Yes) */ +#define CPUSS_ETB_PRESENT 0u +/* CM0+ MTB SRAM buffer size in kilobytes. Legal vaules 4, 8 or 16 */ +#define CPUSS_MTB_SRAM_SIZE 4u +/* CM4 ETB SRAM buffer size in kilobytes. Legal vaules 4, 8 or 16 */ +#define CPUSS_ETB_SRAM_SIZE 8u +/* PTM interface present (0=No, 1=Yes) */ +#define CPUSS_PTM_PRESENT 0u +/* Width of the PTM interface in bits ([2,32]) */ +#define CPUSS_PTM_WIDTH 1u +/* Width of the TPIU interface in bits ([1,4]) */ +#define CPUSS_TPIU_WIDTH 4u +/* CoreSight Part Identification Number */ +#define CPUSS_JEPID 52u +/* CoreSight Part Identification Number */ +#define CPUSS_JEPCONTINUATION 0u +/* CoreSight Part Identification Number */ +#define CPUSS_FAMILYID 270u +/* ROM trim register width (for ARM 3, for Synopsys 5) */ +#define CPUSS_ROM_TRIM_WIDTH 5u +/* ROM trim register default (for both ARM and Synopsys 0x0000_0012) */ +#define CPUSS_ROM_TRIM_DEFAULT 18u +/* RAM trim register width (for ARM 8, for Synopsys 15) */ +#define CPUSS_RAM_TRIM_WIDTH 15u +/* RAM trim register default (for ARM 0x0000_0062 and for Synopsys 0x0000_6012) */ +#define CPUSS_RAM_TRIM_DEFAULT 24594u +/* Cryptography IP present or not (0=No, 1=Yes) */ +#define CPUSS_CRYPTO_PRESENT 1u +/* DataWire and DMAC SW trigger per channel present or not ('0': no, '1': yes) */ +#define CPUSS_SW_TR_PRESENT 0u +/* DataWire 0 present or not (0=No, 1=Yes) */ +#define CPUSS_DW0_PRESENT 1u +/* Number of DataWire 0 channels (8, 16 or 32) */ +#define CPUSS_DW0_CH_NR 30u +/* DataWire 1 present or not (0=No, 1=Yes) */ +#define CPUSS_DW1_PRESENT 1u +/* Number of DataWire 1 channels (8, 16 or 32) */ +#define CPUSS_DW1_CH_NR 32u +/* DMA controller present or not ('0': no, '1': yes) */ +#define CPUSS_DMAC_PRESENT 1u +/* Number of DMA controller channels ([1, 8]) */ +#define CPUSS_DMAC_CH_NR 2u +/* DMAC SW trigger per channel present or not ('0': no, '1': yes) */ +#define CPUSS_CH_SW_TR_PRESENT 0u +/* Copy value from Globals */ +#define CPUSS_CHIP_TOP_PROFILER_PRESENT 0u +/* ETAS Calibration support pin out present (automotive only) */ +#define CPUSS_CHIP_TOP_CAL_SUP_NZ_PRESENT 0u +/* TRACE_LVL>0 */ +#define CPUSS_CHIP_TOP_TRACE_PRESENT 1u +/* DataWire SW trigger per channel present or not ('0': no, '1': yes) */ +#define CPUSS_CH_STRUCT_SW_TR_PRESENT 0u +/* Number of DataWire controllers present (max 2) (same as DW.NR above) */ +#define CPUSS_CPUSS_DW_DW_NR 2u +/* Number of channels in each DataWire controller */ +#define CPUSS_CPUSS_DW_DW_NR0_DW_CH_NR 30u +/* Width of a channel number in bits */ +#define CPUSS_CPUSS_DW_DW_NR0_DW_CH_NR_WIDTH 5u +/* Number of channels in each DataWire controller */ +#define CPUSS_CPUSS_DW_DW_NR1_DW_CH_NR 32u +/* Width of a channel number in bits */ +#define CPUSS_CPUSS_DW_DW_NR1_DW_CH_NR_WIDTH 5u +/* Cryptography SRAMs ECC present or not ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_ECC_PRESENT 0u +/* Cryptography SRAMs address ECC present or not ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_ECC_ADDR_PRESENT 0u +/* AES cipher support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_AES 1u +/* (Tripple) DES cipher support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_DES 1u +/* Chacha support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_CHACHA 1u +/* Pseudo random number generation support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_PR 1u +/* SHA1 hash support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_SHA1 1u +/* SHA2 hash support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_SHA2 1u +/* SHA3 hash support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_SHA3 1u +/* Cyclic Redundancy Check support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_CRC 1u +/* True random number generation support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_TR 1u +/* Vector unit support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_VU 1u +/* Galios/Counter Mode (GCM) support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_GCM 1u +/* Number of 32-bit words in the IP internal memory buffer (from the set [64, 128, + 256, 512, 1024, 2048, 4096], to allow for a 256 B, 512 B, 1 kB, 2 kB, 4 kB, 8 + kB and 16 kB memory buffer) */ +#define CPUSS_CRYPTO_BUFF_SIZE 1024u +/* Number of DMA controller channels ([1, 8]) */ +#define CPUSS_DMAC_CH_NR 2u +/* Number of DataWire controllers present (max 2) */ +#define CPUSS_DW_NR 2u +/* DataWire SRAMs ECC present or not ('0': no, '1': yes) */ +#define CPUSS_DW_ECC_PRESENT 0u +/* Number of fault structures. Legal range [1, 4] */ +#define CPUSS_FAULT_FAULT_NR 2u +/* Number of Flash BIST_DATA registers */ +#define CPUSS_FLASHC_FLASHC_BIST_DATA_NR 4u +/* Page size in # of 32-bit words (1: 4 bytes, 2: 8 bytes, ... */ +#define CPUSS_FLASHC_PA_SIZE 128u +/* SONOS Flash is used or not ('0': no, '1': yes) */ +#define CPUSS_FLASHC_FLASHC_IS_SONOS 1u +/* eCT Flash is used or not ('0': no, '1': yes) */ +#define CPUSS_FLASHC_FLASHC_IS_ECT 0u +/* CM4 CPU present or not ('0': no, '1': yes) */ +#define CPUSS_FLASHC_CM4_PRESENT 1u +/* Number of IPC structures. Legal range [1, 16] */ +#define CPUSS_IPC_IPC_NR 16u +/* Number of IPC interrupt structures. Legal range [1, 16] */ +#define CPUSS_IPC_IPC_IRQ_NR 16u +/* Master 0 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS0_PC_NR_MINUS1 7u +/* Master 1 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS1_PC_NR_MINUS1 0u +/* Master 2 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS2_PC_NR_MINUS1 0u +/* Master 3 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS3_PC_NR_MINUS1 0u +/* Master 4 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS4_PC_NR_MINUS1 0u +/* Master 5 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS5_PC_NR_MINUS1 0u +/* Master 6 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS6_PC_NR_MINUS1 0u +/* Master 7 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS7_PC_NR_MINUS1 0u +/* Master 8 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS8_PC_NR_MINUS1 0u +/* Master 9 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS9_PC_NR_MINUS1 0u +/* Master 10 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS10_PC_NR_MINUS1 0u +/* Master 11 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS11_PC_NR_MINUS1 0u +/* Master 12 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS12_PC_NR_MINUS1 0u +/* Master 13 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS13_PC_NR_MINUS1 0u +/* Master 14 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS14_PC_NR_MINUS1 7u +/* Master 15 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS15_PC_NR_MINUS1 7u +/* Number of SMPU protection structures */ +#define CPUSS_PROT_SMPU_STRUCT_NR 16u +/* Number of protection contexts supported minus 1. Legal range [1,16] */ +#define CPUSS_SMPU_STRUCT_PC_NR_MINUS1 7u +/* Number of instantiated eFUSE macros (256 bit macros). Legal range [1, 16] */ +#define EFUSE_EFUSE_NR 4u +/* Number of GPIO ports in range 0..31 */ +#define IOSS_GPIO_GPIO_PORT_NR_0_31 15u +/* Number of GPIO ports in range 32..63 */ +#define IOSS_GPIO_GPIO_PORT_NR_32_63 0u +/* Number of GPIO ports in range 64..95 */ +#define IOSS_GPIO_GPIO_PORT_NR_64_95 0u +/* Number of GPIO ports in range 96..127 */ +#define IOSS_GPIO_GPIO_PORT_NR_96_127 0u +/* Number of ports in device */ +#define IOSS_GPIO_GPIO_PORT_NR 15u +/* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_GPIO 1u +/* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SIO 0u +/* Indicates port is a GPIO port including the "AUTO" input threshold */ +#define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_AUTOLVL 0u +/* Indicates that pin #0 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO0 1u +/* Indicates that pin #1 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO1 1u +/* Indicates that pin #2 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO2 1u +/* Indicates that pin #3 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO3 1u +/* Indicates that pin #4 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO4 1u +/* Indicates that pin #5 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO5 1u +/* Indicates that pin #6 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO6 0u +/* Indicates that pin #7 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO7 0u +/* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_GPIO 1u +/* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SIO 0u +/* Indicates port is a GPIO port including the "AUTO" input threshold */ +#define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_AUTOLVL 0u +/* Indicates that pin #0 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO0 1u +/* Indicates that pin #1 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO1 1u +/* Indicates that pin #2 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO2 1u +/* Indicates that pin #3 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO3 0u +/* Indicates that pin #4 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO4 0u +/* Indicates that pin #5 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO5 0u +/* Indicates that pin #6 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO6 0u +/* Indicates that pin #7 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO7 0u +/* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_GPIO 1u +/* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SIO 0u +/* Indicates port is a GPIO port including the "AUTO" input threshold */ +#define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_AUTOLVL 0u +/* Indicates that pin #0 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO0 1u +/* Indicates that pin #1 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO1 1u +/* Indicates that pin #2 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO2 1u +/* Indicates that pin #3 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO3 1u +/* Indicates that pin #4 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO4 1u +/* Indicates that pin #5 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO5 1u +/* Indicates that pin #6 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO6 1u +/* Indicates that pin #7 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO7 1u +/* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_GPIO 1u +/* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SIO 0u +/* Indicates port is a GPIO port including the "AUTO" input threshold */ +#define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_AUTOLVL 0u +/* Indicates that pin #0 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO0 1u +/* Indicates that pin #1 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO1 1u +/* Indicates that pin #2 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO2 0u +/* Indicates that pin #3 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO3 0u +/* Indicates that pin #4 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO4 0u +/* Indicates that pin #5 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO5 0u +/* Indicates that pin #6 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO6 0u +/* Indicates that pin #7 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO7 0u +/* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_GPIO 0u +/* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SIO 0u +/* Indicates port is a GPIO port including the "AUTO" input threshold */ +#define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_AUTOLVL 0u +/* Indicates that pin #0 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO0 0u +/* Indicates that pin #1 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO1 0u +/* Indicates that pin #2 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO2 0u +/* Indicates that pin #3 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO3 0u +/* Indicates that pin #4 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO4 0u +/* Indicates that pin #5 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO5 0u +/* Indicates that pin #6 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO6 0u +/* Indicates that pin #7 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO7 0u +/* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_GPIO 1u +/* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SIO 0u +/* Indicates port is a GPIO port including the "AUTO" input threshold */ +#define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_AUTOLVL 0u +/* Indicates that pin #0 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO0 1u +/* Indicates that pin #1 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO1 1u +/* Indicates that pin #2 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO2 1u +/* Indicates that pin #3 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO3 0u +/* Indicates that pin #4 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO4 0u +/* Indicates that pin #5 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO5 0u +/* Indicates that pin #6 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO6 1u +/* Indicates that pin #7 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO7 1u +/* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_GPIO 1u +/* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SIO 0u +/* Indicates port is a GPIO port including the "AUTO" input threshold */ +#define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_AUTOLVL 0u +/* Indicates that pin #0 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO0 0u +/* Indicates that pin #1 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO1 0u +/* Indicates that pin #2 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO2 1u +/* Indicates that pin #3 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO3 1u +/* Indicates that pin #4 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO4 1u +/* Indicates that pin #5 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO5 1u +/* Indicates that pin #6 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO6 1u +/* Indicates that pin #7 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO7 1u +/* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_GPIO 1u +/* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SIO 0u +/* Indicates port is a GPIO port including the "AUTO" input threshold */ +#define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_AUTOLVL 0u +/* Indicates that pin #0 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO0 1u +/* Indicates that pin #1 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO1 1u +/* Indicates that pin #2 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO2 1u +/* Indicates that pin #3 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO3 1u +/* Indicates that pin #4 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO4 1u +/* Indicates that pin #5 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO5 1u +/* Indicates that pin #6 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO6 0u +/* Indicates that pin #7 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO7 1u +/* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_GPIO 1u +/* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SIO 0u +/* Indicates port is a GPIO port including the "AUTO" input threshold */ +#define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_AUTOLVL 0u +/* Indicates that pin #0 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO0 1u +/* Indicates that pin #1 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO1 1u +/* Indicates that pin #2 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO2 0u +/* Indicates that pin #3 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO3 0u +/* Indicates that pin #4 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO4 0u +/* Indicates that pin #5 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO5 0u +/* Indicates that pin #6 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO6 0u +/* Indicates that pin #7 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO7 0u +/* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_GPIO 1u +/* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SIO 0u +/* Indicates port is a GPIO port including the "AUTO" input threshold */ +#define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_AUTOLVL 0u +/* Indicates that pin #0 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO0 1u +/* Indicates that pin #1 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO1 1u +/* Indicates that pin #2 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO2 1u +/* Indicates that pin #3 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO3 1u +/* Indicates that pin #4 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO4 1u +/* Indicates that pin #5 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO5 1u +/* Indicates that pin #6 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO6 0u +/* Indicates that pin #7 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO7 0u +/* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_GPIO 1u +/* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SIO 0u +/* Indicates port is a GPIO port including the "AUTO" input threshold */ +#define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_AUTOLVL 0u +/* Indicates that pin #0 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO0 1u +/* Indicates that pin #1 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO1 1u +/* Indicates that pin #2 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO2 1u +/* Indicates that pin #3 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO3 1u +/* Indicates that pin #4 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO4 1u +/* Indicates that pin #5 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO5 1u +/* Indicates that pin #6 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO6 1u +/* Indicates that pin #7 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO7 1u +/* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_GPIO 1u +/* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SIO 0u +/* Indicates port is a GPIO port including the "AUTO" input threshold */ +#define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_AUTOLVL 0u +/* Indicates that pin #0 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO0 0u +/* Indicates that pin #1 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO1 1u +/* Indicates that pin #2 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO2 1u +/* Indicates that pin #3 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO3 1u +/* Indicates that pin #4 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO4 1u +/* Indicates that pin #5 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO5 1u +/* Indicates that pin #6 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO6 1u +/* Indicates that pin #7 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO7 1u +/* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_GPIO 1u +/* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SIO 0u +/* Indicates port is a GPIO port including the "AUTO" input threshold */ +#define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_AUTOLVL 0u +/* Indicates that pin #0 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO0 0u +/* Indicates that pin #1 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO1 0u +/* Indicates that pin #2 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO2 0u +/* Indicates that pin #3 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO3 0u +/* Indicates that pin #4 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO4 0u +/* Indicates that pin #5 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO5 0u +/* Indicates that pin #6 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO6 1u +/* Indicates that pin #7 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO7 1u +/* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_GPIO 0u +/* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SIO 0u +/* Indicates port is a GPIO port including the "AUTO" input threshold */ +#define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_AUTOLVL 0u +/* Indicates that pin #0 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO0 0u +/* Indicates that pin #1 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO1 0u +/* Indicates that pin #2 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO2 0u +/* Indicates that pin #3 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO3 0u +/* Indicates that pin #4 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO4 0u +/* Indicates that pin #5 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO5 0u +/* Indicates that pin #6 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO6 0u +/* Indicates that pin #7 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO7 0u +/* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_GPIO 0u +/* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SIO 0u +/* Indicates port is a GPIO port including the "AUTO" input threshold */ +#define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_AUTOLVL 0u +/* Indicates that pin #0 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO0 1u +/* Indicates that pin #1 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO1 1u +/* Indicates that pin #2 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO2 0u +/* Indicates that pin #3 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO3 0u +/* Indicates that pin #4 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO4 0u +/* Indicates that pin #5 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO5 0u +/* Indicates that pin #6 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO6 0u +/* Indicates that pin #7 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO7 0u +/* Number of AMUX splitter cells */ +#define IOSS_HSIOM_AMUX_SPLIT_NR 6u +/* Number of HSIOM ports in device (same as GPIO.GPIO_PRT_NR) */ +#define IOSS_HSIOM_HSIOM_PORT_NR 15u +/* Number of PWR/GND MONITOR CELLs in the device */ +#define IOSS_HSIOM_MONITOR_NR 0u +/* Number of PWR/GND MONITOR CELLs in range 0..31 */ +#define IOSS_HSIOM_MONITOR_NR_0_31 0u +/* Number of PWR/GND MONITOR CELLs in range 32..63 */ +#define IOSS_HSIOM_MONITOR_NR_32_63 0u +/* Number of PWR/GND MONITOR CELLs in range 64..95 */ +#define IOSS_HSIOM_MONITOR_NR_64_95 0u +/* Number of PWR/GND MONITOR CELLs in range 96..127 */ +#define IOSS_HSIOM_MONITOR_NR_96_127 0u +/* Indicates the presence of alternate JTAG interface */ +#define IOSS_HSIOM_ALTJTAG_PRESENT 0u +/* Mask of SMARTIO instances presence */ +#define IOSS_SMARTIO_SMARTIO_MASK 512u +/* Number of ports supoprting up to 4 COMs */ +#define LCD_NUMPORTS 8u +/* Number of ports supporting up to 8 COMs */ +#define LCD_NUMPORTS8 8u +/* Number of ports supporting up to 16 COMs */ +#define LCD_NUMPORTS16 0u +/* Max number of LCD commons supported */ +#define LCD_CHIP_TOP_COM_NR 8u +/* Max number of LCD pins (total) supported */ +#define LCD_CHIP_TOP_PIN_NR 60u +/* Number of CTBs in the Subsystem */ +#define PASS_NR_CTBS 1u +/* Number of CTDACs in the Subsystem */ +#define PASS_NR_CTDACS 1u +/* Number of SARs in the Subsystem */ +#define PASS_NR_SARS 2u +/* Number of IREF outputs from AREF */ +#define PASS_NR_IREFS 4u +/* CTB0 Exists */ +#define PASS_CTB0_EXISTS 1u +/* CTB1 Exists */ +#define PASS_CTB1_EXISTS 0u +/* CTB2 Exists */ +#define PASS_CTB2_EXISTS 0u +/* CTB3 Exists */ +#define PASS_CTB3_EXISTS 0u +/* CTDAC0 Exists */ +#define PASS_CTDAC0_EXISTS 1u +/* CTDAC1 Exists */ +#define PASS_CTDAC1_EXISTS 0u +/* CTDAC2 Exists */ +#define PASS_CTDAC2_EXISTS 0u +/* CTDAC3 Exists */ +#define PASS_CTDAC3_EXISTS 0u +/* SAR0 Exists */ +#define PASS_SAR0_EXISTS 1u +/* SAR1 Exists */ +#define PASS_SAR1_EXISTS 1u +/* SAR2 Exists */ +#define PASS_SAR2_EXISTS 0u +/* SAR3 Exists */ +#define PASS_SAR3_EXISTS 0u +/* NR_SARS*UDB_PRESENT */ +#define PASS_SAR_UDB_IF 0u +/* NR_CTBS*UDB_PRESENT */ +#define PASS_CTB_UDB_IF 0u +/* NR_CTDACS*UDB_PRESENT */ +#define PASS_CTDAC_UDB_IF 0u +#define PASS_CTBM_CTDAC_PRESENT 1u +#define PASS_CTBM_UDB_PRESENT 0u +/* Number of SAR channels */ +#define PASS_SAR_SAR_CHANNELS 16u +/* Averaging logic present in SAR */ +#define PASS_SAR_SAR_AVERAGE 1u +/* Range detect logic present in SAR */ +#define PASS_SAR_SAR_RANGEDET 1u +/* Support for UAB sampling */ +#define PASS_SAR_SAR_UAB 0u +#define PASS_SAR_CTB0_EXISTS 1u +#define PASS_SAR_UDB_PRESENT 0u +/* The number of protection contexts ([2, 16]). */ +#define PERI_PC_NR 8u +/* Master interface presence mask (4 bits) */ +#define PERI_MS_PRESENT 15u +/* Protection structures SRAM ECC present or not ('0': no, '1': yes) */ +#define PERI_ECC_PRESENT 0u +/* Protection structures SRAM address ECC present or not ('0': no, '1': yes) */ +#define PERI_ECC_ADDR_PRESENT 0u +/* Clock control functionality present ('0': no, '1': yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL0_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL1_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL2_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL4_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL5_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL6_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL8_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Clock control functionality present ('0': no, '1': yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL0_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL1_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL2_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL4_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL5_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL6_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL8_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Clock control functionality present ('0': no, '1': yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL0_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL1_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL2_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL3_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL4_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL5_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL6_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL7_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL8_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL9_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL10_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL12_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Clock control functionality present ('0': no, '1': yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL0_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL1_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL2_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL4_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL5_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL6_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL8_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL11_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL15_PRESENT 1u +/* Clock control functionality present ('0': no, '1': yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL0_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL1_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL2_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL4_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL5_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL6_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL8_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Clock control functionality present ('0': no, '1': yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL0_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL1_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL2_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL4_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL5_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL6_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL8_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Clock control functionality present ('0': no, '1': yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL0_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL1_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL2_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL4_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL5_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL6_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL8_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Clock control functionality present ('0': no, '1': yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL0_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL1_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL2_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL4_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL5_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL6_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL8_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Clock control functionality present ('0': no, '1': yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL0_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL1_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL2_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL4_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL5_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL6_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL8_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Clock control functionality present ('0': no, '1': yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL0_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL1_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL2_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL4_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL5_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL6_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL8_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Clock control functionality present ('0': no, '1': yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL0_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL1_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL2_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL4_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL5_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL6_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL8_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Clock control functionality present ('0': no, '1': yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL0_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL1_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL2_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL4_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL5_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL6_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL8_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Clock control functionality present ('0': no, '1': yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL0_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL1_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL2_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL4_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL5_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL6_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL8_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Clock control functionality present ('0': no, '1': yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL0_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL1_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL2_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL4_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL5_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL6_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL8_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Clock control functionality present ('0': no, '1': yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL0_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL1_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL2_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL4_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL5_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL6_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL8_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Clock control functionality present ('0': no, '1': yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL0_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL1_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL2_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL4_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL5_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL6_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL8_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Number of programmable clocks (outputs) */ +#define PERI_CLOCK_NR 28u +/* Number of 8.0 dividers */ +#define PERI_DIV_8_NR 4u +/* Number of 16.0 dividers */ +#define PERI_DIV_16_NR 8u +/* Number of 16.5 (fractional) dividers */ +#define PERI_DIV_16_5_NR 2u +/* Number of 24.5 (fractional) dividers */ +#define PERI_DIV_24_5_NR 1u +/* Divider number width: max(1,roundup(log2(max(DIV_*_NR))) */ +#define PERI_DIV_ADDR_WIDTH 3u +/* Timeout functionality present ('0': no, '1': yes) */ +#define PERI_TIMEOUT_PRESENT 1u +/* Trigger module present (0=No, 1=Yes) */ +#define PERI_TR 1u +/* Number of trigger groups */ +#define PERI_TR_GROUP_NR 11u +/* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_GROUP_NR0_TR_GROUP_TR_MANIPULATION_PRESENT 1u +/* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_GROUP_NR1_TR_GROUP_TR_MANIPULATION_PRESENT 1u +/* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_GROUP_NR2_TR_GROUP_TR_MANIPULATION_PRESENT 1u +/* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_GROUP_NR3_TR_GROUP_TR_MANIPULATION_PRESENT 1u +/* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_GROUP_NR4_TR_GROUP_TR_MANIPULATION_PRESENT 1u +/* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_GROUP_NR5_TR_GROUP_TR_MANIPULATION_PRESENT 1u +/* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_GROUP_NR6_TR_GROUP_TR_MANIPULATION_PRESENT 1u +/* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_GROUP_NR7_TR_GROUP_TR_MANIPULATION_PRESENT 1u +/* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_GROUP_NR8_TR_GROUP_TR_MANIPULATION_PRESENT 1u +/* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_GROUP_NR9_TR_GROUP_TR_MANIPULATION_PRESENT 1u +/* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_GROUP_NR10_TR_GROUP_TR_MANIPULATION_PRESENT 1u +/* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_1TO1_GROUP_NR0_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u +/* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_1TO1_GROUP_NR1_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u +/* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_1TO1_GROUP_NR2_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u +/* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_1TO1_GROUP_NR3_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u +/* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_1TO1_GROUP_NR4_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u +/* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_1TO1_GROUP_NR5_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u +/* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_1TO1_GROUP_NR6_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u +/* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_1TO1_GROUP_NR7_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u +/* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_1TO1_GROUP_NR8_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u +/* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ +#define PERI_MASTER_WIDTH 8u +/* DeepSleep support ('0':no, '1': yes) */ +#define SCB0_DEEPSLEEP 0u +/* Externally clocked support? ('0': no, '1': yes) */ +#define SCB0_EC 0u +/* I2C master support? ('0': no, '1': yes) */ +#define SCB0_I2C_M 1u +/* I2C slave support? ('0': no, '1': yes) */ +#define SCB0_I2C_S 1u +/* I2C support? (I2C_M | I2C_S) */ +#define SCB0_I2C 1u +/* I2C glitch filters present? ('0': no, '1': yes) */ +#define SCB0_I2C_GLITCH 1u +/* I2C externally clocked support? ('0': no, '1': yes) */ +#define SCB0_I2C_EC 0u +/* I2C master and slave support? (I2C_M & I2C_S) */ +#define SCB0_I2C_M_S 1u +/* I2C slave with EC? (I2C_S & I2C_EC) */ +#define SCB0_I2C_S_EC 0u +/* SPI master support? ('0': no, '1': yes) */ +#define SCB0_SPI_M 1u +/* SPI slave support? ('0': no, '1': yes) */ +#define SCB0_SPI_S 1u +/* SPI support? (SPI_M | SPI_S) */ +#define SCB0_SPI 1u +/* SPI externally clocked support? ('0': no, '1': yes) */ +#define SCB0_SPI_EC 0u +/* SPI slave with EC? (SPI_S & SPI_EC) */ +#define SCB0_SPI_S_EC 0u +/* UART support? ('0': no, '1': yes) */ +#define SCB0_UART 1u +/* SPI or UART (SPI | UART) */ +#define SCB0_SPI_UART 1u +/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, + CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only + 256 B are used. This is because the EZ mode uses 8-bit addresses. */ +#define SCB0_EZ_DATA_NR 256u +/* Command/response mode support? ('0': no, '1': yes) */ +#define SCB0_CMD_RESP 0u +/* EZ mode support? ('0': no, '1': yes) */ +#define SCB0_EZ 0u +/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ +#define SCB0_EZ_CMD_RESP 0u +/* I2C slave with EZ mode (I2C_S & EZ) */ +#define SCB0_I2C_S_EZ 0u +/* SPI slave with EZ mode (SPI_S & EZ) */ +#define SCB0_SPI_S_EZ 0u +/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ +#define SCB0_I2C_FAST_PLUS 1u +/* Number of used spi_select signals (max 4) */ +#define SCB0_CHIP_TOP_SPI_SEL_NR 3u +/* DeepSleep support ('0':no, '1': yes) */ +#define SCB1_DEEPSLEEP 0u +/* Externally clocked support? ('0': no, '1': yes) */ +#define SCB1_EC 0u +/* I2C master support? ('0': no, '1': yes) */ +#define SCB1_I2C_M 1u +/* I2C slave support? ('0': no, '1': yes) */ +#define SCB1_I2C_S 1u +/* I2C support? (I2C_M | I2C_S) */ +#define SCB1_I2C 1u +/* I2C glitch filters present? ('0': no, '1': yes) */ +#define SCB1_I2C_GLITCH 1u +/* I2C externally clocked support? ('0': no, '1': yes) */ +#define SCB1_I2C_EC 0u +/* I2C master and slave support? (I2C_M & I2C_S) */ +#define SCB1_I2C_M_S 1u +/* I2C slave with EC? (I2C_S & I2C_EC) */ +#define SCB1_I2C_S_EC 0u +/* SPI master support? ('0': no, '1': yes) */ +#define SCB1_SPI_M 1u +/* SPI slave support? ('0': no, '1': yes) */ +#define SCB1_SPI_S 1u +/* SPI support? (SPI_M | SPI_S) */ +#define SCB1_SPI 1u +/* SPI externally clocked support? ('0': no, '1': yes) */ +#define SCB1_SPI_EC 0u +/* SPI slave with EC? (SPI_S & SPI_EC) */ +#define SCB1_SPI_S_EC 0u +/* UART support? ('0': no, '1': yes) */ +#define SCB1_UART 1u +/* SPI or UART (SPI | UART) */ +#define SCB1_SPI_UART 1u +/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, + CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only + 256 B are used. This is because the EZ mode uses 8-bit addresses. */ +#define SCB1_EZ_DATA_NR 256u +/* Command/response mode support? ('0': no, '1': yes) */ +#define SCB1_CMD_RESP 0u +/* EZ mode support? ('0': no, '1': yes) */ +#define SCB1_EZ 0u +/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ +#define SCB1_EZ_CMD_RESP 0u +/* I2C slave with EZ mode (I2C_S & EZ) */ +#define SCB1_I2C_S_EZ 0u +/* SPI slave with EZ mode (SPI_S & EZ) */ +#define SCB1_SPI_S_EZ 0u +/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ +#define SCB1_I2C_FAST_PLUS 1u +/* Number of used spi_select signals (max 4) */ +#define SCB1_CHIP_TOP_SPI_SEL_NR 4u +/* DeepSleep support ('0':no, '1': yes) */ +#define SCB2_DEEPSLEEP 0u +/* Externally clocked support? ('0': no, '1': yes) */ +#define SCB2_EC 0u +/* I2C master support? ('0': no, '1': yes) */ +#define SCB2_I2C_M 1u +/* I2C slave support? ('0': no, '1': yes) */ +#define SCB2_I2C_S 1u +/* I2C support? (I2C_M | I2C_S) */ +#define SCB2_I2C 1u +/* I2C glitch filters present? ('0': no, '1': yes) */ +#define SCB2_I2C_GLITCH 1u +/* I2C externally clocked support? ('0': no, '1': yes) */ +#define SCB2_I2C_EC 0u +/* I2C master and slave support? (I2C_M & I2C_S) */ +#define SCB2_I2C_M_S 1u +/* I2C slave with EC? (I2C_S & I2C_EC) */ +#define SCB2_I2C_S_EC 0u +/* SPI master support? ('0': no, '1': yes) */ +#define SCB2_SPI_M 1u +/* SPI slave support? ('0': no, '1': yes) */ +#define SCB2_SPI_S 1u +/* SPI support? (SPI_M | SPI_S) */ +#define SCB2_SPI 1u +/* SPI externally clocked support? ('0': no, '1': yes) */ +#define SCB2_SPI_EC 0u +/* SPI slave with EC? (SPI_S & SPI_EC) */ +#define SCB2_SPI_S_EC 0u +/* UART support? ('0': no, '1': yes) */ +#define SCB2_UART 1u +/* SPI or UART (SPI | UART) */ +#define SCB2_SPI_UART 1u +/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, + CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only + 256 B are used. This is because the EZ mode uses 8-bit addresses. */ +#define SCB2_EZ_DATA_NR 256u +/* Command/response mode support? ('0': no, '1': yes) */ +#define SCB2_CMD_RESP 0u +/* EZ mode support? ('0': no, '1': yes) */ +#define SCB2_EZ 0u +/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ +#define SCB2_EZ_CMD_RESP 0u +/* I2C slave with EZ mode (I2C_S & EZ) */ +#define SCB2_I2C_S_EZ 0u +/* SPI slave with EZ mode (SPI_S & EZ) */ +#define SCB2_SPI_S_EZ 0u +/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ +#define SCB2_I2C_FAST_PLUS 1u +/* Number of used spi_select signals (max 4) */ +#define SCB2_CHIP_TOP_SPI_SEL_NR 3u +/* DeepSleep support ('0':no, '1': yes) */ +#define SCB3_DEEPSLEEP 0u +/* Externally clocked support? ('0': no, '1': yes) */ +#define SCB3_EC 0u +/* I2C master support? ('0': no, '1': yes) */ +#define SCB3_I2C_M 1u +/* I2C slave support? ('0': no, '1': yes) */ +#define SCB3_I2C_S 1u +/* I2C support? (I2C_M | I2C_S) */ +#define SCB3_I2C 1u +/* I2C glitch filters present? ('0': no, '1': yes) */ +#define SCB3_I2C_GLITCH 1u +/* I2C externally clocked support? ('0': no, '1': yes) */ +#define SCB3_I2C_EC 0u +/* I2C master and slave support? (I2C_M & I2C_S) */ +#define SCB3_I2C_M_S 1u +/* I2C slave with EC? (I2C_S & I2C_EC) */ +#define SCB3_I2C_S_EC 0u +/* SPI master support? ('0': no, '1': yes) */ +#define SCB3_SPI_M 1u +/* SPI slave support? ('0': no, '1': yes) */ +#define SCB3_SPI_S 1u +/* SPI support? (SPI_M | SPI_S) */ +#define SCB3_SPI 1u +/* SPI externally clocked support? ('0': no, '1': yes) */ +#define SCB3_SPI_EC 0u +/* SPI slave with EC? (SPI_S & SPI_EC) */ +#define SCB3_SPI_S_EC 0u +/* UART support? ('0': no, '1': yes) */ +#define SCB3_UART 1u +/* SPI or UART (SPI | UART) */ +#define SCB3_SPI_UART 1u +/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, + CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only + 256 B are used. This is because the EZ mode uses 8-bit addresses. */ +#define SCB3_EZ_DATA_NR 256u +/* Command/response mode support? ('0': no, '1': yes) */ +#define SCB3_CMD_RESP 0u +/* EZ mode support? ('0': no, '1': yes) */ +#define SCB3_EZ 0u +/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ +#define SCB3_EZ_CMD_RESP 0u +/* I2C slave with EZ mode (I2C_S & EZ) */ +#define SCB3_I2C_S_EZ 0u +/* SPI slave with EZ mode (SPI_S & EZ) */ +#define SCB3_SPI_S_EZ 0u +/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ +#define SCB3_I2C_FAST_PLUS 1u +/* Number of used spi_select signals (max 4) */ +#define SCB3_CHIP_TOP_SPI_SEL_NR 3u +/* DeepSleep support ('0':no, '1': yes) */ +#define SCB4_DEEPSLEEP 0u +/* Externally clocked support? ('0': no, '1': yes) */ +#define SCB4_EC 0u +/* I2C master support? ('0': no, '1': yes) */ +#define SCB4_I2C_M 1u +/* I2C slave support? ('0': no, '1': yes) */ +#define SCB4_I2C_S 1u +/* I2C support? (I2C_M | I2C_S) */ +#define SCB4_I2C 1u +/* I2C glitch filters present? ('0': no, '1': yes) */ +#define SCB4_I2C_GLITCH 1u +/* I2C externally clocked support? ('0': no, '1': yes) */ +#define SCB4_I2C_EC 0u +/* I2C master and slave support? (I2C_M & I2C_S) */ +#define SCB4_I2C_M_S 1u +/* I2C slave with EC? (I2C_S & I2C_EC) */ +#define SCB4_I2C_S_EC 0u +/* SPI master support? ('0': no, '1': yes) */ +#define SCB4_SPI_M 1u +/* SPI slave support? ('0': no, '1': yes) */ +#define SCB4_SPI_S 1u +/* SPI support? (SPI_M | SPI_S) */ +#define SCB4_SPI 1u +/* SPI externally clocked support? ('0': no, '1': yes) */ +#define SCB4_SPI_EC 0u +/* SPI slave with EC? (SPI_S & SPI_EC) */ +#define SCB4_SPI_S_EC 0u +/* UART support? ('0': no, '1': yes) */ +#define SCB4_UART 1u +/* SPI or UART (SPI | UART) */ +#define SCB4_SPI_UART 1u +/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, + CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only + 256 B are used. This is because the EZ mode uses 8-bit addresses. */ +#define SCB4_EZ_DATA_NR 256u +/* Command/response mode support? ('0': no, '1': yes) */ +#define SCB4_CMD_RESP 0u +/* EZ mode support? ('0': no, '1': yes) */ +#define SCB4_EZ 0u +/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ +#define SCB4_EZ_CMD_RESP 0u +/* I2C slave with EZ mode (I2C_S & EZ) */ +#define SCB4_I2C_S_EZ 0u +/* SPI slave with EZ mode (SPI_S & EZ) */ +#define SCB4_SPI_S_EZ 0u +/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ +#define SCB4_I2C_FAST_PLUS 1u +/* Number of used spi_select signals (max 4) */ +#define SCB4_CHIP_TOP_SPI_SEL_NR 3u +/* DeepSleep support ('0':no, '1': yes) */ +#define SCB5_DEEPSLEEP 0u +/* Externally clocked support? ('0': no, '1': yes) */ +#define SCB5_EC 0u +/* I2C master support? ('0': no, '1': yes) */ +#define SCB5_I2C_M 1u +/* I2C slave support? ('0': no, '1': yes) */ +#define SCB5_I2C_S 1u +/* I2C support? (I2C_M | I2C_S) */ +#define SCB5_I2C 1u +/* I2C glitch filters present? ('0': no, '1': yes) */ +#define SCB5_I2C_GLITCH 1u +/* I2C externally clocked support? ('0': no, '1': yes) */ +#define SCB5_I2C_EC 0u +/* I2C master and slave support? (I2C_M & I2C_S) */ +#define SCB5_I2C_M_S 1u +/* I2C slave with EC? (I2C_S & I2C_EC) */ +#define SCB5_I2C_S_EC 0u +/* SPI master support? ('0': no, '1': yes) */ +#define SCB5_SPI_M 1u +/* SPI slave support? ('0': no, '1': yes) */ +#define SCB5_SPI_S 1u +/* SPI support? (SPI_M | SPI_S) */ +#define SCB5_SPI 1u +/* SPI externally clocked support? ('0': no, '1': yes) */ +#define SCB5_SPI_EC 0u +/* SPI slave with EC? (SPI_S & SPI_EC) */ +#define SCB5_SPI_S_EC 0u +/* UART support? ('0': no, '1': yes) */ +#define SCB5_UART 1u +/* SPI or UART (SPI | UART) */ +#define SCB5_SPI_UART 1u +/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, + CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only + 256 B are used. This is because the EZ mode uses 8-bit addresses. */ +#define SCB5_EZ_DATA_NR 256u +/* Command/response mode support? ('0': no, '1': yes) */ +#define SCB5_CMD_RESP 0u +/* EZ mode support? ('0': no, '1': yes) */ +#define SCB5_EZ 0u +/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ +#define SCB5_EZ_CMD_RESP 0u +/* I2C slave with EZ mode (I2C_S & EZ) */ +#define SCB5_I2C_S_EZ 0u +/* SPI slave with EZ mode (SPI_S & EZ) */ +#define SCB5_SPI_S_EZ 0u +/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ +#define SCB5_I2C_FAST_PLUS 1u +/* Number of used spi_select signals (max 4) */ +#define SCB5_CHIP_TOP_SPI_SEL_NR 4u +/* SONOS Flash is used or not ('0': no, '1': yes) */ +#define SFLASH_FLASHC_IS_SONOS 1u +/* CPUSS_WOUNDING_PRESENT or not ('0': no, '1': yes) */ +#define SFLASH_CPUSS_WOUNDING_PRESENT 0u +/* Base address of the SMIF XIP memory region. This address must be a multiple of + the SMIF XIP memory capacity. This address must be a multiple of 64 KB. This + address must be in the [0x0000:0000, 0x1fff:ffff] memory region. The XIP + memory region should NOT overlap with other memory regions. */ +#define SMIF_SMIF_XIP_ADDR 402653184u +/* Capacity of the SMIF XIP memory region. The more significant bits of this + parameter must be '1' and the lesser significant bits of this paramter must + be '0'. E.g., 0xfff0:0000 specifies a 1 MB memory region. Legal values are + {0xffff:0000, 0xfffe:0000, 0xfffc:0000, 0xfff8:0000, 0xfff0:0000, + 0xffe0:0000, ..., 0xe000:0000}. */ +#define SMIF_SMIF_XIP_MASK 4160749568u +/* Cryptography (AES) support ('0' = no support, '1' = support) */ +#define SMIF_CRYPTO 1u +/* Number of external devices supported ([1,4]) */ +#define SMIF_DEVICE_NR 3u +/* External device write support. This is a 4-bit field. Each external device has + a dedicated bit. E.g., if bit 2 is '1', external device 2 has write support. */ +#define SMIF_DEVICE_WR_EN 15u +/* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ +#define SMIF_MASTER_WIDTH 8u +/* Chip top connect all 8 data pins (0= connect 4 or 6 data pins based on + DATA6_PRESENT, 1= connect 8 data pins) */ +#define SMIF_CHIP_TOP_DATA8_PRESENT 0u +/* Number of used spi_select signals (max 4) */ +#define SMIF_CHIP_TOP_SPI_SEL_NR 3u +/* Number of regulator modules instantiated within SRSS, start with estimate, + update after CMR feedback */ +#define SRSS_NUM_ACTREG_PWRMOD 2u +/* Number of shorting switches between vccd and vccact (target dynamic voltage + drop < 10mV) */ +#define SRSS_NUM_ACTIVE_SWITCH 3u +/* ULP linear regulator system is present */ +#define SRSS_ULPLINREG_PRESENT 1u +/* HT linear regulator system is present */ +#define SRSS_HTLINREG_PRESENT 0u +/* Low-current buck regulator present. Can be derived from S40S_SISOBUCKLC_PRESENT + or SIMOBUCK_PRESENT. */ +#define SRSS_BUCKCTL_PRESENT 1u +/* Low-current SISO buck core regulator is present. Only compatible with ULP + linear regulator system (ULPLINREG_PRESENT==1). */ +#define SRSS_S40S_SISOBUCKLC_PRESENT 1u +/* SIMO buck core regulator is present. Only compatible with ULP linear regulator + system (ULPLINREG_PRESENT==1). */ +#define SRSS_SIMOBUCK_PRESENT 0u +/* Precision ILO (PILO) is present */ +#define SRSS_PILO_PRESENT 0u +/* External Crystal Oscillator is present (high frequency) */ +#define SRSS_ECO_PRESENT 1u +/* System Buck-Boost is present */ +#define SRSS_SYSBB_PRESENT 0u +/* Number of clock paths. Must be > 0 */ +#define SRSS_NUM_CLKPATH 5u +/* Number of PLLs present. Must be <= NUM_CLKPATH */ +#define SRSS_NUM_PLL 1u +/* Number of HFCLK roots present. Must be > 0 */ +#define SRSS_NUM_HFROOT 4u +/* Number of PWR_HIB_DATA registers, should not be needed if BACKUP_PRESENT */ +#define SRSS_NUM_HIBDATA 1u +/* Backup domain is present (includes RTC and WCO) */ +#define SRSS_BACKUP_PRESENT 1u +/* Mask of HFCLK root clock supervisors (CSV). For each clock root i, bit[i] of + mask indicates presence of a CSV. */ +#define SRSS_MASK_HFCSV 0u +/* Clock supervisor is present on WCO. Must be 0 if BACKUP_PRESENT==0. */ +#define SRSS_WCOCSV_PRESENT 0u +/* Number of software watchdog timers. */ +#define SRSS_NUM_MCWDT 2u +/* Number of DSI inputs into clock muxes. This is used for logic optimization. */ +#define SRSS_NUM_DSI 0u +/* Alternate high-frequency clock is present. This is used for logic optimization. */ +#define SRSS_ALTHF_PRESENT 0u +/* Alternate low-frequency clock is present. This is used for logic optimization. */ +#define SRSS_ALTLF_PRESENT 0u +/* Use the hardened clkactfllmux block */ +#define SRSS_USE_HARD_CLKACTFLLMUX 1u +/* Number of clock paths, including direct paths in hardened clkactfllmux block + (Must be >= NUM_CLKPATH) */ +#define SRSS_HARD_CLKPATH 6u +/* Number of clock paths with muxes in hardened clkactfllmux block (Must be >= + NUM_PLL+1) */ +#define SRSS_HARD_CLKPATHMUX 6u +/* Number of HFCLKS present in hardened clkactfllmux block (Must be >= NUM_HFROOT) */ +#define SRSS_HARD_HFROOT 6u +/* ECO mux is present in hardened clkactfllmux block (Must be >= ECO_PRESENT) */ +#define SRSS_HARD_ECOMUX_PRESENT 1u +/* ALTHF mux is present in hardened clkactfllmux block (Must be >= ALTHF_PRESENT) */ +#define SRSS_HARD_ALTHFMUX_PRESENT 1u +/* SRSS version is at least SRSS_VER1P3. Set to 1 for new products. Set to 0 for + PSoC6ABLE2, PSoC6A2M. */ +#define SRSS_SRSS_VER1P3 1u +/* Backup memory is present (only used when BACKUP_PRESENT==1) */ +#define SRSS_BACKUP_BMEM_PRESENT 0u +/* Number of Backup registers to include (each is 32b). Only used when + BACKUP_PRESENT==1. */ +#define SRSS_BACKUP_NUM_BREG 16u +/* Number of input triggers per counter only routed to one counter (0..8) */ +#define TCPWM_TR_ONE_CNT_NR 1u +/* Number of input triggers routed to all counters (0..254), TR_ONE_CNT_NR+TR_ALL + CNT_NR <= 254 */ +#define TCPWM_TR_ALL_CNT_NR 28u +/* Number of TCPWM counter groups (1..4) */ +#define TCPWM_GRP_NR 2u +/* Counter width in number of bits per TCPWM group (16: 16-bits, 32: 32-bits) */ +#define TCPWM_GRP_NR0_CNT_GRP_CNT_WIDTH 32u +/* Second Capture / Compare Unit is present (0, 1) */ +#define TCPWM_GRP_NR0_CNT_GRP_CC1_PRESENT 0u +/* Advanced Motor Control features are present (0, 1). Should only be 1 when + GRP_CC1_PRESENT = 1 */ +#define TCPWM_GRP_NR0_CNT_GRP_AMC_PRESENT 0u +/* Stepper Motor Control features are present (0, 1). */ +#define TCPWM_GRP_NR0_CNT_GRP_SMC_PRESENT 0u +/* Number of counters per TCPWM group (1..256) */ +#define TCPWM_GRP_NR0_GRP_GRP_CNT_NR 4u +/* Counter width in number of bits per TCPWM group (16: 16-bits, 32: 32-bits) */ +#define TCPWM_GRP_NR1_CNT_GRP_CNT_WIDTH 16u +/* Second Capture / Compare Unit is present (0, 1) */ +#define TCPWM_GRP_NR1_CNT_GRP_CC1_PRESENT 1u +/* Advanced Motor Control features are present (0, 1). Should only be 1 when + GRP_CC1_PRESENT = 1 */ +#define TCPWM_GRP_NR1_CNT_GRP_AMC_PRESENT 1u +/* Stepper Motor Control features are present (0, 1). */ +#define TCPWM_GRP_NR1_CNT_GRP_SMC_PRESENT 0u +/* Number of counters per TCPWM group (1..256) */ +#define TCPWM_GRP_NR1_GRP_GRP_CNT_NR 8u +/* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ +#define TCPWM_MASTER_WIDTH 8u + +/* MMIO Targets Defines */ +#define CY_MMIO_CRYPTO_GROUP_NR 1u +#define CY_MMIO_CRYPTO_SLAVE_NR 0u +#define CY_MMIO_CPUSS_GROUP_NR 2u +#define CY_MMIO_CPUSS_SLAVE_NR 0u +#define CY_MMIO_FAULT_GROUP_NR 2u +#define CY_MMIO_FAULT_SLAVE_NR 1u +#define CY_MMIO_IPC_GROUP_NR 2u +#define CY_MMIO_IPC_SLAVE_NR 2u +#define CY_MMIO_PROT_GROUP_NR 2u +#define CY_MMIO_PROT_SLAVE_NR 3u +#define CY_MMIO_FLASHC_GROUP_NR 2u +#define CY_MMIO_FLASHC_SLAVE_NR 4u +#define CY_MMIO_SRSS_GROUP_NR 2u +#define CY_MMIO_SRSS_SLAVE_NR 6u +#define CY_MMIO_BACKUP_GROUP_NR 2u +#define CY_MMIO_BACKUP_SLAVE_NR 7u +#define CY_MMIO_DW_GROUP_NR 2u +#define CY_MMIO_DW_SLAVE_NR 8u +#define CY_MMIO_DMAC_GROUP_NR 2u +#define CY_MMIO_DMAC_SLAVE_NR 10u +#define CY_MMIO_EFUSE_GROUP_NR 2u +#define CY_MMIO_EFUSE_SLAVE_NR 12u +#define CY_MMIO_HSIOM_GROUP_NR 3u +#define CY_MMIO_HSIOM_SLAVE_NR 0u +#define CY_MMIO_GPIO_GROUP_NR 3u +#define CY_MMIO_GPIO_SLAVE_NR 1u +#define CY_MMIO_SMARTIO_GROUP_NR 3u +#define CY_MMIO_SMARTIO_SLAVE_NR 2u +#define CY_MMIO_LPCOMP_GROUP_NR 3u +#define CY_MMIO_LPCOMP_SLAVE_NR 5u +#define CY_MMIO_CSD0_GROUP_NR 3u +#define CY_MMIO_CSD0_SLAVE_NR 6u +#define CY_MMIO_TCPWM0_GROUP_NR 3u +#define CY_MMIO_TCPWM0_SLAVE_NR 8u +#define CY_MMIO_LCD0_GROUP_NR 3u +#define CY_MMIO_LCD0_SLAVE_NR 11u +#define CY_MMIO_USBFS0_GROUP_NR 3u +#define CY_MMIO_USBFS0_SLAVE_NR 15u +#define CY_MMIO_SMIF0_GROUP_NR 4u +#define CY_MMIO_SMIF0_SLAVE_NR 2u +#define CY_MMIO_CANFD0_GROUP_NR 5u +#define CY_MMIO_CANFD0_SLAVE_NR 2u +#define CY_MMIO_SCB0_GROUP_NR 6u +#define CY_MMIO_SCB0_SLAVE_NR 0u +#define CY_MMIO_SCB1_GROUP_NR 6u +#define CY_MMIO_SCB1_SLAVE_NR 1u +#define CY_MMIO_SCB2_GROUP_NR 6u +#define CY_MMIO_SCB2_SLAVE_NR 2u +#define CY_MMIO_SCB04_GROUP_NR 6u +#define CY_MMIO_SCB04_SLAVE_NR 4u +#define CY_MMIO_SCB05_GROUP_NR 6u +#define CY_MMIO_SCB05_SLAVE_NR 5u +#define CY_MMIO_SCB06_GROUP_NR 6u +#define CY_MMIO_SCB06_SLAVE_NR 6u +#define CY_MMIO_PASS_GROUP_NR 9u +#define CY_MMIO_PASS_SLAVE_NR 0u + +/* Backward compatibility definitions */ +#define CPUSS_IRQ_NR CPUSS_SYSTEM_INT_NR +#define CPUSS_DPSLP_IRQ_NR CPUSS_SYSTEM_DPSLP_INT_NR + +#endif /* _PSOC6_04_CONFIG_H_ */ + + +/* [] END OF FILE */ diff --git a/devices/include/psoc6a256k.h b/devices/include/psoc6a256k.h new file mode 100644 index 0000000..c028486 --- /dev/null +++ b/devices/include/psoc6a256k.h @@ -0,0 +1,1197 @@ +/***************************************************************************//** +* \file psoc6a256k.h +* +* \brief +* PSoC6A256K device header +* +* \note +* Generator version: 1.5.1.42 +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _PSOC6A256K_H_ +#define _PSOC6A256K_H_ + +/** +* \addtogroup group_device PSoC6A256K +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + /* ARM Cortex-M0+ Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* PSoC6A256K User Interrupt Numbers */ + NvicMux0_IRQn = 0, /*!< 0 [DeepSleep] CPU User Interrupt #0 */ + NvicMux1_IRQn = 1, /*!< 1 [DeepSleep] CPU User Interrupt #1 */ + NvicMux2_IRQn = 2, /*!< 2 [DeepSleep] CPU User Interrupt #2 */ + NvicMux3_IRQn = 3, /*!< 3 [DeepSleep] CPU User Interrupt #3 */ + NvicMux4_IRQn = 4, /*!< 4 [DeepSleep] CPU User Interrupt #4 */ + NvicMux5_IRQn = 5, /*!< 5 [DeepSleep] CPU User Interrupt #5 */ + NvicMux6_IRQn = 6, /*!< 6 [DeepSleep] CPU User Interrupt #6 */ + NvicMux7_IRQn = 7, /*!< 7 [DeepSleep] CPU User Interrupt #7 */ + /* PSoC6A256K Internal SW Interrupt Numbers */ + Internal0_IRQn = 8, /*!< 8 [Active] Internal SW Interrupt #0 */ + Internal1_IRQn = 9, /*!< 9 [Active] Internal SW Interrupt #1 */ + Internal2_IRQn = 10, /*!< 10 [Active] Internal SW Interrupt #2 */ + Internal3_IRQn = 11, /*!< 11 [Active] Internal SW Interrupt #3 */ + Internal4_IRQn = 12, /*!< 12 [Active] Internal SW Interrupt #4 */ + Internal5_IRQn = 13, /*!< 13 [Active] Internal SW Interrupt #5 */ + Internal6_IRQn = 14, /*!< 14 [Active] Internal SW Interrupt #6 */ + Internal7_IRQn = 15, /*!< 15 [Active] Internal SW Interrupt #7 */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#else + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* PSoC6A256K Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */ + pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */ + pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */ + pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */ + pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */ + scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #2 */ + scb_4_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_256_IRQn = 131, /*!< 131 [Active] TCPWM #0, Counter #256 */ + tcpwm_0_interrupts_257_IRQn = 132, /*!< 132 [Active] TCPWM #0, Counter #257 */ + tcpwm_0_interrupts_258_IRQn = 133, /*!< 133 [Active] TCPWM #0, Counter #258 */ + tcpwm_0_interrupts_259_IRQn = 134, /*!< 134 [Active] TCPWM #0, Counter #259 */ + tcpwm_0_interrupts_260_IRQn = 135, /*!< 135 [Active] TCPWM #0, Counter #260 */ + tcpwm_0_interrupts_261_IRQn = 136, /*!< 136 [Active] TCPWM #0, Counter #261 */ + tcpwm_0_interrupts_262_IRQn = 137, /*!< 137 [Active] TCPWM #0, Counter #262 */ + tcpwm_0_interrupts_263_IRQn = 138, /*!< 138 [Active] TCPWM #0, Counter #263 */ + pass_interrupt_dacs_IRQn = 146, /*!< 146 [Active] Consolidated interrrupt for all DACs */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + cpuss_interrupts_dw0_29_IRQn = 174, /*!< 174 [Active] CPUSS DataWire #0, Channel #29 */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#endif +} IRQn_Type; + + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* PSoC6A256K interrupts that can be routed to the CM0+ NVIC */ +typedef enum { + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */ + pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */ + pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */ + pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */ + pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */ + scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #2 */ + scb_4_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_256_IRQn = 131, /*!< 131 [Active] TCPWM #0, Counter #256 */ + tcpwm_0_interrupts_257_IRQn = 132, /*!< 132 [Active] TCPWM #0, Counter #257 */ + tcpwm_0_interrupts_258_IRQn = 133, /*!< 133 [Active] TCPWM #0, Counter #258 */ + tcpwm_0_interrupts_259_IRQn = 134, /*!< 134 [Active] TCPWM #0, Counter #259 */ + tcpwm_0_interrupts_260_IRQn = 135, /*!< 135 [Active] TCPWM #0, Counter #260 */ + tcpwm_0_interrupts_261_IRQn = 136, /*!< 136 [Active] TCPWM #0, Counter #261 */ + tcpwm_0_interrupts_262_IRQn = 137, /*!< 137 [Active] TCPWM #0, Counter #262 */ + tcpwm_0_interrupts_263_IRQn = 138, /*!< 138 [Active] TCPWM #0, Counter #263 */ + pass_interrupt_dacs_IRQn = 146, /*!< 146 [Active] Consolidated interrrupt for all DACs */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + cpuss_interrupts_dw0_29_IRQn = 174, /*!< 174 [Active] CPUSS DataWire #0, Channel #29 */ + disconnected_IRQn =1023 /*!< 1023 Disconnected */ +} cy_en_intr_t; + +#endif + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */ +#define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */ + +#else + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 1 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + +#endif + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00020000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00040000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00000000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCRYPTO 1u +#define CY_IP_MXCRYPTO_INSTANCES 1u +#define CY_IP_MXCRYPTO_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +//#define CY_IP_MXS40PASS 1u +//#define CY_IP_MXS40PASS_INSTANCES 1u +//#define CY_IP_MXS40PASS_VERSION 2u +//#define CY_IP_MXS40PASS_SAR 1u +//#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +//#define CY_IP_MXS40PASS_SAR_VERSION 2u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 6u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +//#define CY_IP_MXTCPWM 1u +//#define CY_IP_MXTCPWM_INSTANCES 1u +//#define CY_IP_MXTCPWM_VERSION 2u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u + +#include "psoc6_04_config.h" +#include "gpio_psoc6_04_68_qfn.h" + +#define CY_DEVICE_PSOC6A256K +#define CY_SILICON_ID 0xFFFFFFFFUL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR5 ((PERI_GR_Type*) &PERI->GR[5]) /* 0x400040A0 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ +#define PERI_TR_1TO1_GR7 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[7]) /* 0x4000DC00 */ +#define PERI_TR_1TO1_GR8 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[8]) /* 0x4000E000 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR5_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT0_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT1_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT2_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT3_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT0_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT1_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT2_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT3_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT4_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT5_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT6_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT7_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_CANFD0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_CANFD0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_CANFD0_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ + +/******************************************************************************* +* CRYPTO +*******************************************************************************/ + +#define CRYPTO_BASE 0x40100000UL +#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40100000 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW0_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[29]) /* 0x40288740 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ +#define DW1_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[29]) /* 0x40298740 */ +#define DW1_CH_STRUCT30 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[30]) /* 0x40298780 */ +#define DW1_CH_STRUCT31 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[31]) /* 0x402987C0 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM0_GRP0_CNT0 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[0]) /* 0x40380000 */ +#define TCPWM0_GRP0_CNT1 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[1]) /* 0x40380080 */ +#define TCPWM0_GRP0_CNT2 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[2]) /* 0x40380100 */ +#define TCPWM0_GRP0_CNT3 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[3]) /* 0x40380180 */ +#define TCPWM0_GRP1_CNT0 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[0]) /* 0x40388000 */ +#define TCPWM0_GRP1_CNT1 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[1]) /* 0x40388080 */ +#define TCPWM0_GRP1_CNT2 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[2]) /* 0x40388100 */ +#define TCPWM0_GRP1_CNT3 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[3]) /* 0x40388180 */ +#define TCPWM0_GRP1_CNT4 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[4]) /* 0x40388200 */ +#define TCPWM0_GRP1_CNT5 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[5]) /* 0x40388280 */ +#define TCPWM0_GRP1_CNT6 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[6]) /* 0x40388300 */ +#define TCPWM0_GRP1_CNT7 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[7]) /* 0x40388380 */ +#define TCPWM0_GRP0 ((TCPWM_GRP_Type*) &TCPWM0->GRP[0]) /* 0x40380000 */ +#define TCPWM0_GRP1 ((TCPWM_GRP_Type*) &TCPWM0->GRP[1]) /* 0x40388000 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ + +/******************************************************************************* +* CANFD +*******************************************************************************/ + +#define CANFD0_BASE 0x40520000UL +#define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ +#define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ + +/******************************************************************************* +* CTBM +*******************************************************************************/ + +#define CTBM0_BASE 0x40900000UL +#define CTBM0 ((CTBM_Type*) CTBM0_BASE) /* 0x40900000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR0_BASE 0x409D0000UL +#define SAR1_BASE 0x409E0000UL +#define SAR0 ((SAR_Type*) SAR0_BASE) /* 0x409D0000 */ +#define SAR1 ((SAR_Type*) SAR1_BASE) /* 0x409E0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_TIMER ((PASS_TIMER_Type*) &PASS->TIMER) /* 0x409F0100 */ +#define PASS_LPOSC ((PASS_LPOSC_Type*) &PASS->LPOSC) /* 0x409F0200 */ +#define PASS_FIFO0 ((PASS_FIFO_Type*) &PASS->FIFO[0]) /* 0x409F0300 */ +#define PASS_FIFO1 ((PASS_FIFO_Type*) &PASS->FIFO[1]) /* 0x409F0400 */ +#define PASS_AREFV2 ((PASS_AREFV2_Type*) &PASS->AREFV2) /* 0x409F0E00 */ + +/** \} PSoC6A256K */ + +#endif /* _PSOC6A256K_H_ */ + + +/* [] END OF FILE */ diff --git a/devices/svd/psoc6_01.svd b/devices/svd/psoc6_01.svd index 024c76f..21f5b09 100644 --- a/devices/svd/psoc6_01.svd +++ b/devices/svd/psoc6_01.svd @@ -1,5 +1,5 @@ - + Cypress Semiconductor Cypress @@ -7,7 +7,7 @@ PSoC6_01 1.0 PSoC6_01 - Copyright 2016-2019 Cypress Semiconductor Corporation\n + Copyright 2016-2020 Cypress Semiconductor Corporation\n Licensed under the Apache License, Version 2.0 (the "License");\n you may not use this file except in compliance with the License.\n You may obtain a copy of the License at\n @@ -3186,235 +3186,6 @@ The 'fault_reset_req' signals of the individual fault report structures are comb Note: this register field (and associated fault source data in DATA0 through DATA3) should only be considered valid, when VALID is '1'. [6:0] read-only - - - MPU_0 - Bus master 0 MPU/SMPU. -DATA0[31:0]: Violating address. -DATA1[0]: User read. -DATA1[1]: User write. -DATA1[2]: User execute. -DATA1[3]: Privileged read. -DATA1[4]: Privileged write. -DATA1[5]: Privileged execute. -DATA1[6]: Non-secure. -DATA1[11:8]: Master identifier. -DATA1[15:12]: Protection context identifier. -DATA1[31]: '0' MPU violation; '1': SMPU violation. - 0 - - - MPU_1 - Bus master 1 MPU. See MPU_0 description. - 1 - - - MPU_2 - Bus master 2 MPU. See MPU_0 description. - 2 - - - MPU_3 - Bus master 3 MPU. See MPU_0 description. - 3 - - - MPU_4 - Bus master 4 MPU. See MPU_0 description. - 4 - - - MPU_5 - Bus master 5 MPU. See MPU_0 description. - 5 - - - MPU_6 - Bus master 6 MPU. See MPU_0 description. - 6 - - - MPU_7 - Bus master 7 MPU. See MPU_0 description. - 7 - - - MPU_8 - Bus master 8 MPU. See MPU_0 description. - 8 - - - MPU_9 - Bus master 9 MPU. See MPU_0 description. - 9 - - - MPU_10 - Bus master 10 MPU. See MPU_0 description. - 10 - - - MPU_11 - Bus master 11 MPU. See MPU_0 description. - 11 - - - MPU_12 - Bus master 12 MPU. See MPU_0 description. - 12 - - - MPU_13 - Bus master 13 MPU. See MPU_0 description. - 13 - - - MPU_14 - Bus master 14 MPU. See MPU_0 description. - 14 - - - MPU_15 - Bus master 15 MPU. See MPU_0 description. - 15 - - - CM4_SYS_MPU - CM4 system bus AHB-Lite interface MPU. See MPU_0 description. - 16 - - - MS_PPU_0 - Peripheral master interface 0 PPU. -DATA0[31:0]: Violating address. -DATA1[0]: User read. -DATA1[1]: User write. -DATA1[2]: User execute. -DATA1[3]: Privileged read. -DATA1[4]: Privileged write. -DATA1[5]: Privileged execute. -DATA1[6]: Non-secure. -DATA1[11:8]: Master identifier. -DATA1[15:12]: Protection context identifier. -DATA1[31]: '0': PPU violation, '1': peripheral bus error. - 28 - - - MS_PPU_1 - Peripheral master interface 0 PPU. See MS_PPU_0 description. - 29 - - - MS_PPU_2 - Peripheral master interface 1 PPU. See MS_PPU_0 description. - 30 - - - MS_PPU_3 - Peripheral master interface 2 PPU. See MS_PPU_0 description. - 31 - - - GROUP_PPU_0 - Peripheral group 0 PPU. -DATA0[31:0]: Violating address. -DATA1[0]: User read. -DATA1[1]: User write. -DATA1[2]: User execute. -DATA1[3]: Privileged read. -DATA1[4]: Privileged write. -DATA1[5]: Privileged execute. -DATA1[6]: Non-secure. -DATA1[11:8]: Master identifier. -DATA1[15:12]: Protection context identifier. -DATA1[31:30]: '0': PPU violation, '1': timeout detected, '2': peripheral bus error. - 32 - - - GROUP_PPU_1 - Peripheral group 1 PPU. See GROUP_PPU_0 description. - 33 - - - GROUP_PPU_2 - Peripheral group 2 PPU. See GROUP_PPU_0 description. - 34 - - - GROUP_PPU_3 - Peripheral group 3 PPU. See GROUP_PPU_0 description. - 35 - - - GROUP_PPU_4 - Peripheral group 4 PPU. See GROUP_PPU_0 description. - 36 - - - GROUP_PPU_5 - Peripheral group 5 PPU. See GROUP_PPU_0 description. - 37 - - - GROUP_PPU_6 - Peripheral group 6 PPU. See GROUP_PPU_0 description. - 38 - - - GROUP_PPU_7 - Peripheral group 7 PPU. See GROUP_PPU_0 description. - 39 - - - GROUP_PPU_8 - Peripheral group 8 PPU. See GROUP_PPU_0 description. - 40 - - - GROUP_PPU_9 - Peripheral group 9 PPU. See GROUP_PPU_0 description. - 41 - - - GROUP_PPU_10 - Peripheral group 10 PPU. See GROUP_PPU_0 description. - 42 - - - GROUP_PPU_11 - Peripheral group 11 PPU. See GROUP_PPU_0 description. - 43 - - - GROUP_PPU_12 - Peripheral group 12 PPU. See GROUP_PPU_0 description. - 44 - - - GROUP_PPU_13 - Peripheral group 13 PPU. See GROUP_PPU_0 description. - 45 - - - GROUP_PPU_14 - Peripheral group 14 PPU. See GROUP_PPU_0 description. - 46 - - - GROUP_PPU_15 - Peripheral group 15 PPU. See GROUP_PPU_0 description. - 47 - - - FLASHC_MAIN_BUS_ERROR - Flash controller, main interface, bus error: -FAULT_DATA0[31:0]: Violating address. -FAULT_DATA1[31]: '0': FLASH macro interface bus error; '1': memory hole. -FAULT_DATA1[15:12]: Protection context identifier. -FAULT_DATA1[11:8]: Master identifier. - 50 - - VALID @@ -17792,48 +17563,6 @@ This field has a function in PWM, PWM_DT and PWM_PR modes only. Generic 8-bit control field. In PWM_DT mode, this field is used to determine the dead time: amount of dead time cycles in the counter clock domain. In all other modes, the lower 3 bits of this field determine pre-scaling of the selected counter clock. [15:8] read-write - - - DIVBY1 - Divide by 1 (other-than-PWM_DT mode) - 0 - - - DIVBY2 - Divide by 2 (other-than-PWM_DT mode) - 1 - - - DIVBY4 - Divide by 4 (other-than-PWM_DT mode) - 2 - - - DIVBY8 - Divide by 8 (other-than-PWM_DT mode) - 3 - - - DIVBY16 - Divide by 16 (other-than-PWM_DT mode) - 4 - - - DIVBY32 - Divide by 32 (other-than-PWM_DT mode) - 5 - - - DIVBY64 - Divide by 64 (other-than-PWM_DT mode) - 6 - - - DIVBY128 - Divide by 128 (other-than-PWM_DT mode) - 7 - - UP_DOWN_MODE diff --git a/devices/svd/psoc6_02.svd b/devices/svd/psoc6_02.svd index c5222ae..ef53304 100644 --- a/devices/svd/psoc6_02.svd +++ b/devices/svd/psoc6_02.svd @@ -1,5 +1,5 @@ - + Cypress Semiconductor Cypress @@ -7,7 +7,7 @@ PSoC6_02 1.0 PSoC6_02 - Copyright 2016-2019 Cypress Semiconductor Corporation\n + Copyright 2016-2020 Cypress Semiconductor Corporation\n Licensed under the Apache License, Version 2.0 (the "License");\n you may not use this file except in compliance with the License.\n You may obtain a copy of the License at\n @@ -5767,480 +5767,6 @@ The 'fault_reset_req' signals of the individual fault report structures are comb Note: this register field (and associated fault source data in DATA0 through DATA3) should only be considered valid, when VALID is '1'. [6:0] read-write - - - MPU_0 - Bus master 0 MPU/SMPU. -DATA0[31:0]: Violating address. -DATA1[0]: User read. -DATA1[1]: User write. -DATA1[2]: User execute. -DATA1[3]: Privileged read. -DATA1[4]: Privileged write. -DATA1[5]: Privileged execute. -DATA1[6]: Non-secure. -DATA1[11:8]: Master identifier. -DATA1[15:12]: Protection context identifier. -DATA1[31]: '0' MPU violation; '1': SMPU violation. - 0 - - - MPU_1 - Bus master 1 MPU. See MPU_0 description. - 1 - - - MPU_2 - Bus master 2 MPU. See MPU_0 description. - 2 - - - MPU_3 - Bus master 3 MPU. See MPU_0 description. - 3 - - - MPU_4 - Bus master 4 MPU. See MPU_0 description. - 4 - - - MPU_5 - Bus master 5 MPU. See MPU_0 description. - 5 - - - MPU_6 - Bus master 6 MPU. See MPU_0 description. - 6 - - - MPU_7 - Bus master 7 MPU. See MPU_0 description. - 7 - - - MPU_8 - Bus master 8 MPU. See MPU_0 description. - 8 - - - MPU_9 - Bus master 9 MPU. See MPU_0 description. - 9 - - - MPU_10 - Bus master 10 MPU. See MPU_0 description. - 10 - - - MPU_11 - Bus master 11 MPU. See MPU_0 description. - 11 - - - MPU_12 - Bus master 12 MPU. See MPU_0 description. - 12 - - - MPU_13 - Bus master 13 MPU. See MPU_0 description. - 13 - - - MPU_14 - Bus master 14 MPU. See MPU_0 description. - 14 - - - MPU_15 - Bus master 15 MPU. See MPU_0 description. - 15 - - - CM4_SYS_MPU - CM4 system bus AHB-Lite interface MPU. See MPU_0 description. - 16 - - - CM4_CODE_MPU - CM4 code bus AHB-Lite interface MPU for non flash controller accesses. See MPU_0 description. - 17 - - - CM4_CODE_FLASHC_MPU - CM4 code bus AHB-Lite interface MPU for flash controller accesses. See MPU_0 description. - 18 - - - MS_PPU_4 - Peripheral interconnect, master interface 4 PPU. See MS_PPU_0 description. - 25 - - - PERI_ECC - Peripheral interconnect, protection structures SRAM, correctable ECC error: -DATA0[10:0]: Violating address. -DATA1[7:0]: Syndrome of SRAM word. - 26 - - - PERI_NC_ECC - Peripheral interconnect, protection structures SRAM, non-correctable ECC error. See PERI_ECC description. - 27 - - - MS_PPU_0 - Peripheral interconnect, master interface 0 PPU. -DATA0[31:0]: Violating address. -DATA1[0]: User read. -DATA1[1]: User write. -DATA1[2]: User execute. -DATA1[3]: Privileged read. -DATA1[4]: Privileged write. -DATA1[5]: Privileged execute. -DATA1[6]: Non-secure. -DATA1[11:8]: Master identifier. -DATA1[15:12]: Protection context identifier. -DATA1[31:28]: '0': master interface, PPU violation, '1': timeout detected, '2': bus error, other: undefined. - 28 - - - MS_PPU_1 - Peripheral interconnect, master interface 1 PPU. See MS_PPU_0 description. - 29 - - - MS_PPU_2 - Peripheral interconnect, master interface 2 PPU. See MS_PPU_0 description. - 30 - - - MS_PPU_3 - Peripheral interconnect, master interface 3 PPU. See MS_PPU_0 description. - 31 - - - GROUP_FAULT_0 - Peripheral group 0 fault detection. -DATA0[31:0]: Violating address. -DATA1[0]: User read. -DATA1[1]: User write. -DATA1[2]: User execute. -DATA1[3]: Privileged read. -DATA1[4]: Privileged write. -DATA1[5]: Privileged execute. -DATA1[6]: Non-secure. -DATA1[11:8]: Master identifier. -DATA1[15:12]: Protection context identifier. -DATA1[31:28]: '0': decoder or peripheral bus error, other: undefined. - 32 - - - GROUP_FAULT_1 - Peripheral group 1 fault detection. See GROUP_FAULT_0 description. - 33 - - - GROUP_FAULT_2 - Peripheral group 2 fault detection. See GROUP_FAULT_0 description. - 34 - - - GROUP_FAULT_3 - Peripheral group 3 fault detection. See GROUP_FAULT_0 description. - 35 - - - GROUP_FAULT_4 - Peripheral group 4 fault detection. See GROUP_FAULT_0 description. - 36 - - - GROUP_FAULT_5 - Peripheral group 5 fault detection. See GROUP_FAULT_0 description. - 37 - - - GROUP_FAULT_6 - Peripheral group 6 fault detection. See GROUP_FAULT_0 description. - 38 - - - GROUP_FAULT_7 - Peripheral group 7 fault detection. See GROUP_FAULT_0 description. - 39 - - - GROUP_FAULT_8 - Peripheral group 8 fault detection. See GROUP_FAULT_0 description. - 40 - - - GROUP_FAULT_9 - Peripheral group 9 fault detection. See GROUP_FAULT_0 description. - 41 - - - GROUP_FAULT_10 - Peripheral group 10 fault detection. See GROUP_FAULT_0 description. - 42 - - - GROUP_FAULT_11 - Peripheral group 11 fault detection. See GROUP_FAULT_0 description. - 43 - - - GROUP_FAULT_12 - Peripheral group 12 fault detection. See GROUP_FAULT_0 description. - 44 - - - GROUP_FAULT_13 - Peripheral group 13 fault detection. See GROUP_FAULT_0 description. - 45 - - - GROUP_FAULT_14 - Peripheral group 14 fault detection. See GROUP_FAULT_0 description. - 46 - - - GROUP_FAULT_15 - Peripheral group 15 fault detection. See GROUP_FAULT_0 description. - 47 - - - FLASHC_MAIN_BUS_ERROR - Flash controller, main interface, bus error: -FAULT_DATA0[26:0]: Violating address. Append 5'b00010 as most significant bits to derive 32-bit system address. -FAULT_DATA1[11:8]: Master identifier. - 48 - - - FLASHC_MAIN_C_ECC - Flash controller, main interface, correctable ECC error: -DATA[26:0]: Violating address. Append 5'b00010 as most significant bits to derive 32-bit system address. -DATA1[7:0]: Syndrome of 64-bit word (at address offset 0x00). -DATA1[15:8]: Syndrome of 64-bit word (at address offset 0x08). -DATA1[23:16]: Syndrome of 64-bit word (at address offset 0x10). -DATA1[31:24]: Syndrome of 64-bit word (at address offset 0x18). - 49 - - - FLASHC_MAIN_NC_ECC - Flash controller, main interface, non-correctable ECC error. See FLASHC_MAIN_C_ECC description. - 50 - - - FLASHC_WORK_BUS_ERROR - Flash controller, work interface, bus error. -FAULT_DATA0[26:0]: Violating address. Append 5'b00010 as most significant bits to derive 32-bit system address. -FAULT_DATA1[11:8]: Master identifier. - 51 - - - FLASHC_WORK_C_ECC - Flash controller, work interface, correctable ECC error: -DATA0[26:0]: Violating address. Append 5'b00010 as most significant bits to derive 32-bit system address. -DATA1[6:0]: Syndrome of 32-bit word. - 52 - - - FLASHC_WORK_NC_ECC - Flash controller, work interface, non-correctable ECC error. See FLASHC_WORK_C_ECC description. - 53 - - - FLASHC_CM0_CA_C_ECC - Flash controller, CM0+ cache, correctable ECC error: -DATA0[26:0]: Violating address. -DATA1[6:0]: Syndrome of 32-bit SRAM word (at address offset 0x0). -DATA1[14:8]: Syndrome of 32-bit SRAM word (at address offset 0x4). -DATA1[22:16]: Syndrome of 32-bit SRAM word (at address offset 0x8). -DATA1[30:24]: Syndrome of 32-bit SRAM word (at address offset 0xc). - 54 - - - FLASHC_CM0_CA_NC_ECC - Flash controller, CM0+ cache, non-correctable ECC error. See FLASHC_CM0_CA_C_ECC description. - 55 - - - FLASHC_CM4_CA_C_ECC - Flash controller, CM4 cache, correctable ECC error. See FLASHC_CM0_CA_C_ECC description. - 56 - - - FLASHC_CM4_CA_NC_ECC - Flash controller, CM4 cache, non-correctable ECC error. See FLASHC_CM0_CA_C_ECC description. - 57 - - - RAMC0_C_ECC - System SRAM 0 correctable ECC error: -DATA0[31:0]: Violating address. -DATA1[6:0]: Syndrome of 32-bit SRAM code word. - 58 - - - RAMC0_NC_ECC - System SRAM 0 non-correctable ECC error. See RAMC0_C_ECC description. - 59 - - - RAMC1_C_ECC - System SRAM 1 correctable ECC error. See RAMC0_C_ECC description. - 60 - - - RAMC1_NC_ECC - System SRAM 1 non-correctable ECC error. See RAMC0_C_ECC description. - 61 - - - RAMC2_C_ECC - System SRAM 2 correctable ECC error. See RAMC0_C_ECC description. - 62 - - - RAMC2_NC_ECC - System SRAM 2 non-correctable ECC error. See RAMC0_C_ECC description. - 63 - - - CRYPTO_C_ECC - Cryptography SRAM correctable ECC error. -DATA0[31:0]: Violating address. -DATA1[6:0]: Syndrome of Least Significant 32-bit SRAM. -DATA1[14:8]: Syndrome of Most Significant 32-bit SRAM. - 64 - - - CRYPTO_NC_ECC - Cryptography SRAM non-correctable ECC error. See CRYPTO_C_ECC description. - 65 - - - DW0_C_ECC - DataWire 0 SRAM 1 correctable ECC error: -DATA0[11:0]: Violating DW SRAM address (word address, assuming byte addressable). -DATA1[6:0]: Syndrome of 32-bit SRAM code word. - 70 - - - DW0_NC_ECC - DataWire 0 SRAM 1 non-correctable ECC error. See DW0_C_ECC description. - 71 - - - DW1_C_ECC - DataWire 1 SRAM 1 correctable ECC error. See DW0_C_ECC description. - 72 - - - DW1_NC_ECC - DataWire 1 SRAM 1 non-correctable ECC error. See DW0_C_ECC description. - 73 - - - FM_SRAM_C_ECC - eCT Flash SRAM (for embedded operations) correctable ECC error: -DATA0[15:0]: Address location in the eCT Flash SRAM. -DATA1[6:0]: Syndrome of 32-bit SRAM word. - 74 - - - FM_SRAM_NC_ECC - eCT Flash SRAM non-correctable ECC error: See FM_SRAM_C_ECC description. - 75 - - - CAN0_C_ECC - CAN controller 0 MRAM correctable ECC error: -DATA0[15:0]: Violating address. -DATA0[22:16]: ECC violating data[38:32] from MRAM. -DATA0[27:24]: Master ID: 0-7 = CAN channel ID within mxttcanfd cluster, 8 = AHB I/F -DATA1[31:0]: ECC violating data[31:0] from MRAM. - 80 - - - CAN0_NC_ECC - CAN controller 0 MRAM non-correctable ECC error: -DATA0[15:0]: Violating address. -DATA0[22:16]: ECC violating data[38:32] from MRAM (not for Address Error). -DATA0[27:24]: Master ID: 0-7 = CAN channel ID within mxttcanfd cluster, 8 = AHB I/F -DATA0[30]: Write access, only possible for Address Error -DATA0[31]: Address Error: a CAN channel did an MRAM access above MRAM_SIZE -DATA1[31:0]: ECC violating data[31:0] from MRAM (not for Address Error). - 81 - - - CAN1_C_ECC - CAN controller 1 MRAM correctable ECC error. See CAN0_C_ECC description. - 82 - - - CAN1_NC_ECC - CAN controller 1 MRAM non-correctable ECC error. See CAN0_NC_ECC description. - 83 - - - CAN2_C_ECC - CAN controller 2 MRAM correctable ECC error. See CAN0_C_ECC description. - 84 - - - CAN2_NC_ECC - CAN controller 2 MRAM non-correctable ECC error. See CAN0_NC_ECC description. - 85 - - - SRSS_CSV - SRSS Clock SuperVisor (CSV) violation detected. Multiple CSV can detect a violation at the same time. -DATA0[15:0]: CSV violation occurred on corresponding clk_hf* root clock -DATA0[24]: CSV violation occurred on reference clock for clk_hf CSVs -DATA0[25]: CSV violation occurred on clk_lf -DATA0[26]: CSV violation occurred on clk_ilo0 - 90 - - - SRSS_SSV - SRSS Supply SuperVisor (SSV) violation detected. Multiple SSV can detect a violation at the same time. -DATA0[0]: BOD detected on VDDA -DATA0[1]: OVD detected on VDDA -DATA0[16]: violation detected on LVD/HVD #1 -DATA0[17]: violation detected on LVD/HVD #2 - 91 - - - SRSS_MCWDT0 - SRSS Multi-Counter Watch Dog Timer (MCWDT) #0 violation detected. Multiple counters can detect a violation at the same time. -DATA0[0]: MCWDT subcounter 0 LOWER_LIMIT -DATA0[1]: MCWDT subcounter 0 UPPER_LIMIT -DATA0[2]: MCWDT subcounter 1 LOWER_LIMIT -DATA0[3]: MCWDT subcounter 1 UPPER_LIMIT - 92 - - - SRSS_MCWDT1 - SRSS Multi-Counter Watch Dog Timer (MCWDT) #1 violation detected. See SRSS_MCWDT0 description. - 93 - - - SRSS_MCWDT2 - SRSS Multi-Counter Watch Dog Timer (MCWDT) #2 violation detected. See SRSS_MCWDT0 description. - 94 - - - SRSS_MCWDT3 - SRSS Multi-Counter Watch Dog Timer (MCWDT) #3 violation detected. See SRSS_MCWDT0 description. - 95 - - VALID @@ -22055,48 +21581,6 @@ This field has a function in PWM, PWM_DT and PWM_PR modes only. Generic 8-bit control field. In PWM_DT mode, this field is used to determine the dead time: amount of dead time cycles in the counter clock domain. In all other modes, the lower 3 bits of this field determine pre-scaling of the selected counter clock. [15:8] read-write - - - DIVBY1 - Divide by 1 (other-than-PWM_DT mode) - 0 - - - DIVBY2 - Divide by 2 (other-than-PWM_DT mode) - 1 - - - DIVBY4 - Divide by 4 (other-than-PWM_DT mode) - 2 - - - DIVBY8 - Divide by 8 (other-than-PWM_DT mode) - 3 - - - DIVBY16 - Divide by 16 (other-than-PWM_DT mode) - 4 - - - DIVBY32 - Divide by 32 (other-than-PWM_DT mode) - 5 - - - DIVBY64 - Divide by 64 (other-than-PWM_DT mode) - 6 - - - DIVBY128 - Divide by 128 (other-than-PWM_DT mode) - 7 - - UP_DOWN_MODE diff --git a/devices/svd/psoc6_03.svd b/devices/svd/psoc6_03.svd index 8002187..6cb7a99 100644 --- a/devices/svd/psoc6_03.svd +++ b/devices/svd/psoc6_03.svd @@ -1,5 +1,5 @@ - + Cypress Semiconductor Cypress @@ -7,7 +7,7 @@ PSoC6_03 1.0 PSoC6_03 - Copyright 2016-2019 Cypress Semiconductor Corporation\n + Copyright 2016-2020 Cypress Semiconductor Corporation\n Licensed under the Apache License, Version 2.0 (the "License");\n you may not use this file except in compliance with the License.\n You may obtain a copy of the License at\n @@ -5612,480 +5612,6 @@ The 'fault_reset_req' signals of the individual fault report structures are comb Note: this register field (and associated fault source data in DATA0 through DATA3) should only be considered valid, when VALID is '1'. [6:0] read-write - - - MPU_0 - Bus master 0 MPU/SMPU. -DATA0[31:0]: Violating address. -DATA1[0]: User read. -DATA1[1]: User write. -DATA1[2]: User execute. -DATA1[3]: Privileged read. -DATA1[4]: Privileged write. -DATA1[5]: Privileged execute. -DATA1[6]: Non-secure. -DATA1[11:8]: Master identifier. -DATA1[15:12]: Protection context identifier. -DATA1[31]: '0' MPU violation; '1': SMPU violation. - 0 - - - MPU_1 - Bus master 1 MPU. See MPU_0 description. - 1 - - - MPU_2 - Bus master 2 MPU. See MPU_0 description. - 2 - - - MPU_3 - Bus master 3 MPU. See MPU_0 description. - 3 - - - MPU_4 - Bus master 4 MPU. See MPU_0 description. - 4 - - - MPU_5 - Bus master 5 MPU. See MPU_0 description. - 5 - - - MPU_6 - Bus master 6 MPU. See MPU_0 description. - 6 - - - MPU_7 - Bus master 7 MPU. See MPU_0 description. - 7 - - - MPU_8 - Bus master 8 MPU. See MPU_0 description. - 8 - - - MPU_9 - Bus master 9 MPU. See MPU_0 description. - 9 - - - MPU_10 - Bus master 10 MPU. See MPU_0 description. - 10 - - - MPU_11 - Bus master 11 MPU. See MPU_0 description. - 11 - - - MPU_12 - Bus master 12 MPU. See MPU_0 description. - 12 - - - MPU_13 - Bus master 13 MPU. See MPU_0 description. - 13 - - - MPU_14 - Bus master 14 MPU. See MPU_0 description. - 14 - - - MPU_15 - Bus master 15 MPU. See MPU_0 description. - 15 - - - CM4_SYS_MPU - CM4 system bus AHB-Lite interface MPU. See MPU_0 description. - 16 - - - CM4_CODE_MPU - CM4 code bus AHB-Lite interface MPU for non flash controller accesses. See MPU_0 description. - 17 - - - CM4_CODE_FLASHC_MPU - CM4 code bus AHB-Lite interface MPU for flash controller accesses. See MPU_0 description. - 18 - - - MS_PPU_4 - Peripheral interconnect, master interface 4 PPU. See MS_PPU_0 description. - 25 - - - PERI_ECC - Peripheral interconnect, protection structures SRAM, correctable ECC error: -DATA0[10:0]: Violating address. -DATA1[7:0]: Syndrome of SRAM word. - 26 - - - PERI_NC_ECC - Peripheral interconnect, protection structures SRAM, non-correctable ECC error. See PERI_ECC description. - 27 - - - MS_PPU_0 - Peripheral interconnect, master interface 0 PPU. -DATA0[31:0]: Violating address. -DATA1[0]: User read. -DATA1[1]: User write. -DATA1[2]: User execute. -DATA1[3]: Privileged read. -DATA1[4]: Privileged write. -DATA1[5]: Privileged execute. -DATA1[6]: Non-secure. -DATA1[11:8]: Master identifier. -DATA1[15:12]: Protection context identifier. -DATA1[31:28]: '0': master interface, PPU violation, '1': timeout detected, '2': bus error, other: undefined. - 28 - - - MS_PPU_1 - Peripheral interconnect, master interface 1 PPU. See MS_PPU_0 description. - 29 - - - MS_PPU_2 - Peripheral interconnect, master interface 2 PPU. See MS_PPU_0 description. - 30 - - - MS_PPU_3 - Peripheral interconnect, master interface 3 PPU. See MS_PPU_0 description. - 31 - - - GROUP_FAULT_0 - Peripheral group 0 fault detection. -DATA0[31:0]: Violating address. -DATA1[0]: User read. -DATA1[1]: User write. -DATA1[2]: User execute. -DATA1[3]: Privileged read. -DATA1[4]: Privileged write. -DATA1[5]: Privileged execute. -DATA1[6]: Non-secure. -DATA1[11:8]: Master identifier. -DATA1[15:12]: Protection context identifier. -DATA1[31:28]: '0': decoder or peripheral bus error, other: undefined. - 32 - - - GROUP_FAULT_1 - Peripheral group 1 fault detection. See GROUP_FAULT_0 description. - 33 - - - GROUP_FAULT_2 - Peripheral group 2 fault detection. See GROUP_FAULT_0 description. - 34 - - - GROUP_FAULT_3 - Peripheral group 3 fault detection. See GROUP_FAULT_0 description. - 35 - - - GROUP_FAULT_4 - Peripheral group 4 fault detection. See GROUP_FAULT_0 description. - 36 - - - GROUP_FAULT_5 - Peripheral group 5 fault detection. See GROUP_FAULT_0 description. - 37 - - - GROUP_FAULT_6 - Peripheral group 6 fault detection. See GROUP_FAULT_0 description. - 38 - - - GROUP_FAULT_7 - Peripheral group 7 fault detection. See GROUP_FAULT_0 description. - 39 - - - GROUP_FAULT_8 - Peripheral group 8 fault detection. See GROUP_FAULT_0 description. - 40 - - - GROUP_FAULT_9 - Peripheral group 9 fault detection. See GROUP_FAULT_0 description. - 41 - - - GROUP_FAULT_10 - Peripheral group 10 fault detection. See GROUP_FAULT_0 description. - 42 - - - GROUP_FAULT_11 - Peripheral group 11 fault detection. See GROUP_FAULT_0 description. - 43 - - - GROUP_FAULT_12 - Peripheral group 12 fault detection. See GROUP_FAULT_0 description. - 44 - - - GROUP_FAULT_13 - Peripheral group 13 fault detection. See GROUP_FAULT_0 description. - 45 - - - GROUP_FAULT_14 - Peripheral group 14 fault detection. See GROUP_FAULT_0 description. - 46 - - - GROUP_FAULT_15 - Peripheral group 15 fault detection. See GROUP_FAULT_0 description. - 47 - - - FLASHC_MAIN_BUS_ERROR - Flash controller, main interface, bus error: -FAULT_DATA0[26:0]: Violating address. Append 5'b00010 as most significant bits to derive 32-bit system address. -FAULT_DATA1[11:8]: Master identifier. - 48 - - - FLASHC_MAIN_C_ECC - Flash controller, main interface, correctable ECC error: -DATA[26:0]: Violating address. Append 5'b00010 as most significant bits to derive 32-bit system address. -DATA1[7:0]: Syndrome of 64-bit word (at address offset 0x00). -DATA1[15:8]: Syndrome of 64-bit word (at address offset 0x08). -DATA1[23:16]: Syndrome of 64-bit word (at address offset 0x10). -DATA1[31:24]: Syndrome of 64-bit word (at address offset 0x18). - 49 - - - FLASHC_MAIN_NC_ECC - Flash controller, main interface, non-correctable ECC error. See FLASHC_MAIN_C_ECC description. - 50 - - - FLASHC_WORK_BUS_ERROR - Flash controller, work interface, bus error. -FAULT_DATA0[26:0]: Violating address. Append 5'b00010 as most significant bits to derive 32-bit system address. -FAULT_DATA1[11:8]: Master identifier. - 51 - - - FLASHC_WORK_C_ECC - Flash controller, work interface, correctable ECC error: -DATA0[26:0]: Violating address. Append 5'b00010 as most significant bits to derive 32-bit system address. -DATA1[6:0]: Syndrome of 32-bit word. - 52 - - - FLASHC_WORK_NC_ECC - Flash controller, work interface, non-correctable ECC error. See FLASHC_WORK_C_ECC description. - 53 - - - FLASHC_CM0_CA_C_ECC - Flash controller, CM0+ cache, correctable ECC error: -DATA0[26:0]: Violating address. -DATA1[6:0]: Syndrome of 32-bit SRAM word (at address offset 0x0). -DATA1[14:8]: Syndrome of 32-bit SRAM word (at address offset 0x4). -DATA1[22:16]: Syndrome of 32-bit SRAM word (at address offset 0x8). -DATA1[30:24]: Syndrome of 32-bit SRAM word (at address offset 0xc). - 54 - - - FLASHC_CM0_CA_NC_ECC - Flash controller, CM0+ cache, non-correctable ECC error. See FLASHC_CM0_CA_C_ECC description. - 55 - - - FLASHC_CM4_CA_C_ECC - Flash controller, CM4 cache, correctable ECC error. See FLASHC_CM0_CA_C_ECC description. - 56 - - - FLASHC_CM4_CA_NC_ECC - Flash controller, CM4 cache, non-correctable ECC error. See FLASHC_CM0_CA_C_ECC description. - 57 - - - RAMC0_C_ECC - System SRAM 0 correctable ECC error: -DATA0[31:0]: Violating address. -DATA1[6:0]: Syndrome of 32-bit SRAM code word. - 58 - - - RAMC0_NC_ECC - System SRAM 0 non-correctable ECC error. See RAMC0_C_ECC description. - 59 - - - RAMC1_C_ECC - System SRAM 1 correctable ECC error. See RAMC0_C_ECC description. - 60 - - - RAMC1_NC_ECC - System SRAM 1 non-correctable ECC error. See RAMC0_C_ECC description. - 61 - - - RAMC2_C_ECC - System SRAM 2 correctable ECC error. See RAMC0_C_ECC description. - 62 - - - RAMC2_NC_ECC - System SRAM 2 non-correctable ECC error. See RAMC0_C_ECC description. - 63 - - - CRYPTO_C_ECC - Cryptography SRAM correctable ECC error. -DATA0[31:0]: Violating address. -DATA1[6:0]: Syndrome of Least Significant 32-bit SRAM. -DATA1[14:8]: Syndrome of Most Significant 32-bit SRAM. - 64 - - - CRYPTO_NC_ECC - Cryptography SRAM non-correctable ECC error. See CRYPTO_C_ECC description. - 65 - - - DW0_C_ECC - DataWire 0 SRAM 1 correctable ECC error: -DATA0[11:0]: Violating DW SRAM address (word address, assuming byte addressable). -DATA1[6:0]: Syndrome of 32-bit SRAM code word. - 70 - - - DW0_NC_ECC - DataWire 0 SRAM 1 non-correctable ECC error. See DW0_C_ECC description. - 71 - - - DW1_C_ECC - DataWire 1 SRAM 1 correctable ECC error. See DW0_C_ECC description. - 72 - - - DW1_NC_ECC - DataWire 1 SRAM 1 non-correctable ECC error. See DW0_C_ECC description. - 73 - - - FM_SRAM_C_ECC - eCT Flash SRAM (for embedded operations) correctable ECC error: -DATA0[15:0]: Address location in the eCT Flash SRAM. -DATA1[6:0]: Syndrome of 32-bit SRAM word. - 74 - - - FM_SRAM_NC_ECC - eCT Flash SRAM non-correctable ECC error: See FM_SRAM_C_ECC description. - 75 - - - CAN0_C_ECC - CAN controller 0 MRAM correctable ECC error: -DATA0[15:0]: Violating address. -DATA0[22:16]: ECC violating data[38:32] from MRAM. -DATA0[27:24]: Master ID: 0-7 = CAN channel ID within mxttcanfd cluster, 8 = AHB I/F -DATA1[31:0]: ECC violating data[31:0] from MRAM. - 80 - - - CAN0_NC_ECC - CAN controller 0 MRAM non-correctable ECC error: -DATA0[15:0]: Violating address. -DATA0[22:16]: ECC violating data[38:32] from MRAM (not for Address Error). -DATA0[27:24]: Master ID: 0-7 = CAN channel ID within mxttcanfd cluster, 8 = AHB I/F -DATA0[30]: Write access, only possible for Address Error -DATA0[31]: Address Error: a CAN channel did an MRAM access above MRAM_SIZE -DATA1[31:0]: ECC violating data[31:0] from MRAM (not for Address Error). - 81 - - - CAN1_C_ECC - CAN controller 1 MRAM correctable ECC error. See CAN0_C_ECC description. - 82 - - - CAN1_NC_ECC - CAN controller 1 MRAM non-correctable ECC error. See CAN0_NC_ECC description. - 83 - - - CAN2_C_ECC - CAN controller 2 MRAM correctable ECC error. See CAN0_C_ECC description. - 84 - - - CAN2_NC_ECC - CAN controller 2 MRAM non-correctable ECC error. See CAN0_NC_ECC description. - 85 - - - SRSS_CSV - SRSS Clock SuperVisor (CSV) violation detected. Multiple CSV can detect a violation at the same time. -DATA0[15:0]: CSV violation occurred on corresponding clk_hf* root clock -DATA0[24]: CSV violation occurred on reference clock for clk_hf CSVs -DATA0[25]: CSV violation occurred on clk_lf -DATA0[26]: CSV violation occurred on clk_ilo0 - 90 - - - SRSS_SSV - SRSS Supply SuperVisor (SSV) violation detected. Multiple SSV can detect a violation at the same time. -DATA0[0]: BOD detected on VDDA -DATA0[1]: OVD detected on VDDA -DATA0[16]: violation detected on LVD/HVD #1 -DATA0[17]: violation detected on LVD/HVD #2 - 91 - - - SRSS_MCWDT0 - SRSS Multi-Counter Watch Dog Timer (MCWDT) #0 violation detected. Multiple counters can detect a violation at the same time. -DATA0[0]: MCWDT subcounter 0 LOWER_LIMIT -DATA0[1]: MCWDT subcounter 0 UPPER_LIMIT -DATA0[2]: MCWDT subcounter 1 LOWER_LIMIT -DATA0[3]: MCWDT subcounter 1 UPPER_LIMIT - 92 - - - SRSS_MCWDT1 - SRSS Multi-Counter Watch Dog Timer (MCWDT) #1 violation detected. See SRSS_MCWDT0 description. - 93 - - - SRSS_MCWDT2 - SRSS Multi-Counter Watch Dog Timer (MCWDT) #2 violation detected. See SRSS_MCWDT0 description. - 94 - - - SRSS_MCWDT3 - SRSS Multi-Counter Watch Dog Timer (MCWDT) #3 violation detected. See SRSS_MCWDT0 description. - 95 - - VALID @@ -21692,48 +21218,6 @@ This field has a function in PWM, PWM_DT and PWM_PR modes only. Generic 8-bit control field. In PWM_DT mode, this field is used to determine the dead time: amount of dead time cycles in the counter clock domain. In all other modes, the lower 3 bits of this field determine pre-scaling of the selected counter clock. [15:8] read-write - - - DIVBY1 - Divide by 1 (other-than-PWM_DT mode) - 0 - - - DIVBY2 - Divide by 2 (other-than-PWM_DT mode) - 1 - - - DIVBY4 - Divide by 4 (other-than-PWM_DT mode) - 2 - - - DIVBY8 - Divide by 8 (other-than-PWM_DT mode) - 3 - - - DIVBY16 - Divide by 16 (other-than-PWM_DT mode) - 4 - - - DIVBY32 - Divide by 32 (other-than-PWM_DT mode) - 5 - - - DIVBY64 - Divide by 64 (other-than-PWM_DT mode) - 6 - - - DIVBY128 - Divide by 128 (other-than-PWM_DT mode) - 7 - - UP_DOWN_MODE diff --git a/devices/svd/psoc6_04.svd b/devices/svd/psoc6_04.svd new file mode 100644 index 0000000..3dc385a --- /dev/null +++ b/devices/svd/psoc6_04.svd @@ -0,0 +1,42559 @@ + + + + Cypress Semiconductor + Cypress + psoc6_04 + PSoC6_04 + 1.0 + PSoC6_04 + Copyright 2016-2020 Cypress Semiconductor Corporation\n + Licensed under the Apache License, Version 2.0 (the "License");\n + you may not use this file except in compliance with the License.\n + You may obtain a copy of the License at\n +\n + http://www.apache.org/licenses/LICENSE-2.0\n +\n + Unless required by applicable law or agreed to in writing, software\n + distributed under the License is distributed on an "AS IS" BASIS,\n + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n + See the License for the specific language governing permissions and\n + limitations under the License. + + CM4 + r0p1 + little + true + true + 1 + 3 + 0 + + 8 + 32 + 0x00000000 + 0xFFFFFFFF + + + PERI + Peripheral interconnect + 0x40000000 + + 0 + 65536 + registers + + + + TIMEOUT_CTL + Timeout control + 0x200 + 32 + read-write + 0xFFFF + 0xFFFF + + + TIMEOUT + This field specifies a number of clock cycles (clk_slow). If an AHB-Lite bus transfer takes more than the specified number of cycles (timeout detection), the bus transfer is terminated with an AHB-Lite bus error and a fault is generated (and possibly recorded in the fault report structure(s)). +'0x0000'-'0xfffe': Number of clock cycles. +'0xffff': This value is the default/reset value and specifies that no timeout detection is performed: a bus transfer will never be terminated and a fault will never be generated. + [15:0] + read-write + + + + + TR_CMD + Trigger command + 0x220 + 32 + read-write + 0x0 + 0xE0001FFF + + + TR_SEL + Specifies the activated trigger when ACTIVATE is '1'. If the specified trigger is not present, the trigger activation has no effect. + [7:0] + read-write + + + GROUP_SEL + Specifies the trigger group: +'0'-'15': trigger multiplexer groups. +'16'-'31': trigger 1-to-1 groups. + [12:8] + read-write + + + TR_EDGE + Specifies if the activated trigger is treated as a level sensitive or edge sensitive trigger. +'0': level sensitive. The trigger reflects TR_CMD.ACTIVATE. +'1': edge sensitive trigger. The trigger is activated for two clk_peri cycles. + [29:29] + read-write + + + OUT_SEL + Specifies whether trigger activation is for a specific input or output trigger of the trigger multiplexer. Activation of a specific input trigger, will result in activation of all output triggers that have the specific input trigger selected through their TR_OUT_CTL.TR_SEL field. Activation of a specific output trigger, will result in activation of the specified TR_SEL output trigger only. +'0': TR_SEL selection and trigger activation is for an input trigger to the trigger multiplexer. +'1': TR_SEL selection and trigger activation is for an output trigger from the trigger multiplexer. + +Note: this field is not used for trigger 1-to-1 groups. + [30:30] + read-write + + + ACTIVATE + SW sets this field to '1' to activate (set to '1') a trigger as identified by TR_SEL, TR_EDGE and OUT_SEL. HW sets this field to '0' for edge sensitive triggers AFTER the selected trigger is activated for two clk_peri cycles. + +Note: when ACTIVATE is '1', SW should not modify the other register fields. + [31:31] + read-write + + + + + DIV_CMD + Divider command + 0x400 + 32 + read-write + 0x3FF03FF + 0xC3FF03FF + + + DIV_SEL + (TYPE_SEL, DIV_SEL) specifies the divider on which the command (DISABLE/ENABLE) is performed. + +If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock signal(s) are generated. + [7:0] + read-write + + + TYPE_SEL + Specifies the divider type of the divider on which the command is performed: +0: 8.0 (integer) clock dividers. +1: 16.0 (integer) clock dividers. +2: 16.5 (fractional) clock dividers. +3: 24.5 (fractional) clock dividers. + [9:8] + read-write + + + PA_DIV_SEL + (PA_TYPE_SEL, PA_DIV_SEL) specifies the divider to which phase alignment is performed for the clock enable command. Any enabled divider can be used as reference. This allows all dividers to be aligned with each other, even when they are enabled at different times. + +If PA_DIV_SEL is '255' and PA_TYPE_SEL is '3', 'clk_peri' is used as reference. + [23:16] + read-write + + + PA_TYPE_SEL + Specifies the divider type of the divider to which phase alignment is performed for the clock enable command: +0: 8.0 (integer) clock dividers. +1: 16.0 (integer) clock dividers. +2: 16.5 (fractional) clock dividers. +3: 24.5 (fractional) clock dividers. + [25:24] + read-write + + + DISABLE + Clock divider disable command (mutually exclusive with ENABLE). SW sets this field to '1' and HW sets this field to '0'. + +The DIV_SEL and TYPE_SEL fields specify which divider is to be disabled. + +The HW sets the DISABLE field to '0' immediately and the HW sets the DIV_XXX_CTL.EN field of the divider to '0' immediately. + [30:30] + read-write + + + ENABLE + Clock divider enable command (mutually exclusive with DISABLE). Typically, SW sets this field to '1' to enable a divider and HW sets this field to '0' to indicate that divider enabling has completed. When a divider is enabled, its integer and fractional (if present) counters are initialized to '0'. If a divider is to be re-enabled using different integer and fractional divider values, the SW should follow these steps: +0: Disable the divider using the DIV_CMD.DISABLE field. +1: Configure the divider's DIV_XXX_CTL register. +2: Enable the divider using the DIV_CMD_ENABLE field. + +The DIV_SEL and TYPE_SEL fields specify which divider is to be enabled. The enabled divider may be phase aligned to either 'clk_peri' (typical usage) or to ANY enabled divider. + +The PA_DIV_SEL and PA_TYPE_SEL fields specify the reference divider. + +The HW sets the ENABLE field to '0' when the enabling is performed and the HW set the DIV_XXX_CTL.EN field of the divider to '1' when the enabling is performed. Note that enabling with phase alignment to a low frequency divider takes time. E.g. To align to a divider that generates a clock of 'clk_peri'/n (with n being the integer divider value INT_DIV+1), up to n cycles may be required to perform alignment. Phase alignment to 'clk_peri' takes affect immediately. SW can set this field to '0' during phase alignment to abort the enabling process. + [31:31] + read-write + + + + + 256 + 4 + CLOCK_CTL[%s] + Clock control + 0xC00 + 32 + read-write + 0x3FF + 0x3FF + + + DIV_SEL + Specifies one of the dividers of the divider type specified by TYPE_SEL. + +If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. + +When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. + [7:0] + read-write + + + TYPE_SEL + Specifies divider type: +0: 8.0 (integer) clock dividers. +1: 16.0 (integer) clock dividers. +2: 16.5 (fractional) clock dividers. +3: 24.5 (fractional) clock dividers. + [9:8] + read-write + + + + + 256 + 4 + DIV_8_CTL[%s] + Divider control (for 8.0 divider) + 0x1000 + 32 + read-write + 0x0 + 0xFF01 + + + EN + Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. + +Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. + [0:0] + read-only + + + INT8_DIV + Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. + +For the generation of a divided clock, the integer division range is restricted to [2, 256]. + +For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. + +Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. + [15:8] + read-write + + + + + 256 + 4 + DIV_16_CTL[%s] + Divider control (for 16.0 divider) + 0x1400 + 32 + read-write + 0x0 + 0xFFFF01 + + + EN + Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. + +Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. + [0:0] + read-only + + + INT16_DIV + Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. + +For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. + +For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. + +Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. + [23:8] + read-write + + + + + 256 + 4 + DIV_16_5_CTL[%s] + Divider control (for 16.5 divider) + 0x1800 + 32 + read-write + 0x0 + 0xFFFFF9 + + + EN + Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. + +Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. + [0:0] + read-only + + + FRAC5_DIV + Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. + +Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. + [7:3] + read-write + + + INT16_DIV + Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. + +For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. + +For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. + +Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. + [23:8] + read-write + + + + + 255 + 4 + DIV_24_5_CTL[%s] + Divider control (for 24.5 divider) + 0x1C00 + 32 + read-write + 0x0 + 0xFFFFFFF9 + + + EN + Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. + +Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. + [0:0] + read-only + + + FRAC5_DIV + Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. + +Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. + [7:3] + read-write + + + INT24_DIV + Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. + +For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. + +For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. + +Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. + [31:8] + read-write + + + + + ECC_CTL + ECC control + 0x2000 + 32 + read-write + 0x10000 + 0xFF0507FF + + + WORD_ADDR + Specifies the word address where the parity is injected. +- On a 32-bit write access to this SRAM address and when ECC_INJ_EN bit is '1', the parity (PARITY) is injected. + [10:0] + read-write + + + ECC_EN + Enable ECC checking: +'0': Disabled. +'1': Enabled. + [16:16] + read-write + + + ECC_INJ_EN + Enable error injection for PERI protection structure SRAM. +When '1', the parity (PARITY) is used when a write is done to the WORD_ADDR word address of the SRAM. + [18:18] + read-write + + + PARITY + ECC parity to use for ECC error injection at address WORD_ADDR. + [31:24] + read-write + + + + + 10 + 32 + GR[%s] + Peripheral group structure + 0x00004000 + + CLOCK_CTL + Clock control + 0x0 + 32 + read-write + 0x0 + 0xFF00 + + + INT8_DIV + Specifies a group clock divider (from the peripheral clock 'clk_peri' to the group clock 'clk_group[3/4/5/...15]'). Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. + +Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. + [15:8] + read-write + + + + + SL_CTL + Slave control + 0x10 + 32 + read-write + 0xFFFF + 0xFFFFFFFF + + + ENABLED_0 + Peripheral group, slave 0 enable. If the slave is disabled, its clock is gated off (constant '0') and its resets are activated. + +Note: For peripheral group 0 (the peripheral interconnect MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled. + [0:0] + read-write + + + ENABLED_1 + Peripheral group, slave 1 enable. If the slave is disabled, its clock is gated off (constant '0') and its resets are activated. + +Note: For peripheral group 0 (the peripheral interconnect, master interface MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled. + [1:1] + read-write + + + ENABLED_2 + N/A + [2:2] + read-write + + + ENABLED_3 + N/A + [3:3] + read-write + + + ENABLED_4 + N/A + [4:4] + read-write + + + ENABLED_5 + N/A + [5:5] + read-write + + + ENABLED_6 + N/A + [6:6] + read-write + + + ENABLED_7 + N/A + [7:7] + read-write + + + ENABLED_8 + N/A + [8:8] + read-write + + + ENABLED_9 + N/A + [9:9] + read-write + + + ENABLED_10 + N/A + [10:10] + read-write + + + ENABLED_11 + N/A + [11:11] + read-write + + + ENABLED_12 + N/A + [12:12] + read-write + + + ENABLED_13 + N/A + [13:13] + read-write + + + ENABLED_14 + N/A + [14:14] + read-write + + + ENABLED_15 + N/A + [15:15] + read-write + + + DISABLED_0 + Peripheral group, slave 0 permanent disable. Setting this bit to 1 has the same effect as setting ENABLED_0 to 0. However, once set to 1, this bit cannot be changed back to 0 anymore. + [16:16] + read-write + + + DISABLED_1 + N/A + [17:17] + read-write + + + DISABLED_2 + N/A + [18:18] + read-write + + + DISABLED_3 + N/A + [19:19] + read-write + + + DISABLED_4 + N/A + [20:20] + read-write + + + DISABLED_5 + N/A + [21:21] + read-write + + + DISABLED_6 + N/A + [22:22] + read-write + + + DISABLED_7 + N/A + [23:23] + read-write + + + DISABLED_8 + N/A + [24:24] + read-write + + + DISABLED_9 + N/A + [25:25] + read-write + + + DISABLED_10 + N/A + [26:26] + read-write + + + DISABLED_11 + N/A + [27:27] + read-write + + + DISABLED_12 + N/A + [28:28] + read-write + + + DISABLED_13 + N/A + [29:29] + read-write + + + DISABLED_14 + N/A + [30:30] + read-write + + + DISABLED_15 + N/A + [31:31] + read-write + + + + + + 11 + 1024 + TR_GR[%s] + Trigger group + 0x00008000 + + 256 + 4 + TR_CTL[%s] + Trigger control register + 0x0 + 32 + read-write + 0x0 + 0x13FF + + + TR_SEL + Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. + [7:0] + read-write + + + TR_INV + Specifies if the output trigger is inverted. + [8:8] + read-write + + + TR_EDGE + Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. +'0': level sensitive. +'1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. + [9:9] + read-write + + + DBG_FREEZE_EN + Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. + [12:12] + read-write + + + + + + 9 + 1024 + TR_1TO1_GR[%s] + Trigger 1-to-1 group + 0x0000C000 + + 256 + 4 + TR_CTL[%s] + Trigger control register + 0x0 + 32 + read-write + 0x0 + 0x1301 + + + TR_SEL + Specifies input trigger: +'0'': constant signal level '0'. +'1': input trigger. + [0:0] + read-write + + + TR_INV + Specifies if the output trigger is inverted. + [8:8] + read-write + + + TR_EDGE + Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. +'0': level sensitive. +'1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. + [9:9] + read-write + + + DBG_FREEZE_EN + Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. + [12:12] + read-write + + + + + + + + PERI_MS + Peripheral interconnect, master interface + 0x40010000 + + 0 + 65536 + registers + + + + 8 + 64 + PPU_PR[%s] + Programmable protection structure pair + 0x00000000 + + SL_ADDR + Slave region, base address + 0x0 + 32 + read-write + 0x0 + 0x0 + + + ADDR30 + This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore, some of the lesser significant address bits of ADDR30 must be '0's. E.g., a 64 KB address region (REGION_SIZE is '15') must be 64 KByte aligned, and ADDR30[13:0] must be '0's. + [31:2] + read-write + + + + + SL_SIZE + Slave region, size + 0x4 + 32 + read-write + 0x0 + 0x80000000 + + + REGION_SIZE + This field specifies the size of the slave region: +'0': Undefined. +'1': 4 B region (this is the smallest region size). +'2': 8 B region +'3': 16 B region +'4': 32 B region +'5': 64 B region +'6': 128 B region +'7': 256 B region +'8': 512 B region +'9': 1 KB region +'10': 2 KB region +'11': 4 KB region +'12': 8 KB region +'13': 16 KB region +'14': 32 KB region +'15': 64 KB region +'16': 128 KB region +'17': 256 KB region +'18': 512 KB region +'19': 1 MB region +'20': 2 MB region +'21': 4 MB region +'22': 8 MB region +'23': 16 MB region +'24': 32 MB region +'25': 64 MB region +'26': 128 MB region +'27': 256 MB region +'28': 512 MB region +'29': 1 GB region +'30': 2 GB region +'31': 4 GB region + [28:24] + read-write + + + VALID + Slave region enable: +'0': Disabled. A disabled region will never result in a match on the transfer address. +'1': Enabled. + [31:31] + read-write + + + + + SL_ATT0 + Slave attributes 0 + 0x10 + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC0_UR + Protection context 0, user read enable: +'0': Disabled (user, read accesses are NOT allowed). +'1': Enabled (user, read accesses are allowed). + [0:0] + read-only + + + PC0_UW + Protection context 0, user write enable: +'0': Disabled (user, write accesses are NOT allowed). +'1': Enabled (user, write accesses are allowed). + [1:1] + read-only + + + PC0_PR + Protection context 0, privileged read enable: +'0': Disabled (privileged, read accesses are NOT allowed). +'1': Enabled (privileged, read accesses are allowed). + [2:2] + read-only + + + PC0_PW + Protection context 0, privileged write enable: +'0': Disabled (privileged, write accesses are NOT allowed). +'1': Enabled (privileged, write accesses are allowed). + [3:3] + read-only + + + PC0_NS + Protection context 0, non-secure: +'0': Secure (secure accesses allowed, non-secure access NOT allowed). +'1': Non-secure (both secure and non-secure accesses allowed). + [4:4] + read-only + + + PC1_UR + Protection context 1, user read enable. + [8:8] + read-write + + + PC1_UW + Protection context 1, user write enable. + [9:9] + read-write + + + PC1_PR + Protection context 1, privileged read enable. + [10:10] + read-write + + + PC1_PW + Protection context 1, privileged write enable. + [11:11] + read-write + + + PC1_NS + Protection context 1, non-secure. + [12:12] + read-write + + + PC2_UR + Protection context 2, user read enable. + [16:16] + read-write + + + PC2_UW + Protection context 2, user write enable. + [17:17] + read-write + + + PC2_PR + Protection context 2, privileged read enable. + [18:18] + read-write + + + PC2_PW + Protection context 2, privileged write enable. + [19:19] + read-write + + + PC2_NS + Protection context 2, non-secure. + [20:20] + read-write + + + PC3_UR + Protection context 3, user read enable. + [24:24] + read-write + + + PC3_UW + Protection context 3, user write enable. + [25:25] + read-write + + + PC3_PR + Protection context 3, privileged read enable. + [26:26] + read-write + + + PC3_PW + Protection context 3, privileged write enable. + [27:27] + read-write + + + PC3_NS + Protection context 3, non-secure. + [28:28] + read-write + + + + + SL_ATT1 + Slave attributes 1 + 0x14 + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC4_UR + Protection context 4, user read enable. + [0:0] + read-write + + + PC4_UW + Protection context 4, user write enable. + [1:1] + read-write + + + PC4_PR + Protection context 4, privileged read enable. + [2:2] + read-write + + + PC4_PW + Protection context 4, privileged write enable. + [3:3] + read-write + + + PC4_NS + Protection context 4, non-secure. + [4:4] + read-write + + + PC5_UR + Protection context 5, user read enable. + [8:8] + read-write + + + PC5_UW + Protection context 5, user write enable. + [9:9] + read-write + + + PC5_PR + Protection context 5, privileged read enable. + [10:10] + read-write + + + PC5_PW + Protection context 5, privileged write enable. + [11:11] + read-write + + + PC5_NS + Protection context 5, non-secure. + [12:12] + read-write + + + PC6_UR + Protection context 6, user read enable. + [16:16] + read-write + + + PC6_UW + Protection context 6, user write enable. + [17:17] + read-write + + + PC6_PR + Protection context 6, privileged read enable. + [18:18] + read-write + + + PC6_PW + Protection context 6, privileged write enable. + [19:19] + read-write + + + PC6_NS + Protection context 6, non-secure. + [20:20] + read-write + + + PC7_UR + Protection context 7, user read enable. + [24:24] + read-write + + + PC7_UW + Protection context 7, user write enable. + [25:25] + read-write + + + PC7_PR + Protection context 7, privileged read enable. + [26:26] + read-write + + + PC7_PW + Protection context 7, privileged write enable. + [27:27] + read-write + + + PC7_NS + Protection context 7, non-secure. + [28:28] + read-write + + + + + SL_ATT2 + Slave attributes 2 + 0x18 + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC8_UR + Protection context 8, user read enable. + [0:0] + read-write + + + PC8_UW + Protection context 8, user write enable. + [1:1] + read-write + + + PC8_PR + Protection context 8, privileged read enable. + [2:2] + read-write + + + PC8_PW + Protection context 8, privileged write enable. + [3:3] + read-write + + + PC8_NS + Protection context 8, non-secure. + [4:4] + read-write + + + PC9_UR + Protection context 9, user read enable. + [8:8] + read-write + + + PC9_UW + Protection context 9, user write enable. + [9:9] + read-write + + + PC9_PR + Protection context 9, privileged read enable. + [10:10] + read-write + + + PC9_PW + Protection context 9, privileged write enable. + [11:11] + read-write + + + PC9_NS + Protection context 9, non-secure. + [12:12] + read-write + + + PC10_UR + Protection context 10, user read enable. + [16:16] + read-write + + + PC10_UW + Protection context 10, user write enable. + [17:17] + read-write + + + PC10_PR + Protection context 10, privileged read enable. + [18:18] + read-write + + + PC10_PW + Protection context 10, privileged write enable. + [19:19] + read-write + + + PC10_NS + Protection context 10, non-secure. + [20:20] + read-write + + + PC11_UR + Protection context 11, user read enable. + [24:24] + read-write + + + PC11_UW + Protection context 11, user write enable. + [25:25] + read-write + + + PC11_PR + Protection context 11, privileged read enable. + [26:26] + read-write + + + PC11_PW + Protection context 11, privileged write enable. + [27:27] + read-write + + + PC11_NS + Protection context 11, non-secure. + [28:28] + read-write + + + + + SL_ATT3 + Slave attributes 3 + 0x1C + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC12_UR + Protection context 12, user read enable. + [0:0] + read-write + + + PC12_UW + Protection context 12, user write enable. + [1:1] + read-write + + + PC12_PR + Protection context 12, privileged read enable. + [2:2] + read-write + + + PC12_PW + Protection context 12, privileged write enable. + [3:3] + read-write + + + PC12_NS + Protection context 12, non-secure. + [4:4] + read-write + + + PC13_UR + Protection context 13, user read enable. + [8:8] + read-write + + + PC13_UW + Protection context 13, user write enable. + [9:9] + read-write + + + PC13_PR + Protection context 13, privileged read enable. + [10:10] + read-write + + + PC13_PW + Protection context 13, privileged write enable. + [11:11] + read-write + + + PC13_NS + Protection context 13, non-secure. + [12:12] + read-write + + + PC14_UR + Protection context 14, user read enable. + [16:16] + read-write + + + PC14_UW + Protection context 14, user write enable. + [17:17] + read-write + + + PC14_PR + Protection context 14, privileged read enable. + [18:18] + read-write + + + PC14_PW + Protection context 14, privileged write enable. + [19:19] + read-write + + + PC14_NS + Protection context 14, non-secure. + [20:20] + read-write + + + PC15_UR + Protection context 15, user read enable. + [24:24] + read-write + + + PC15_UW + Protection context 15, user write enable. + [25:25] + read-write + + + PC15_PR + Protection context 15, privileged read enable. + [26:26] + read-write + + + PC15_PW + Protection context 15, privileged write enable. + [27:27] + read-write + + + PC15_NS + Protection context 15, non-secure. + [28:28] + read-write + + + + + MS_ADDR + Master region, base address + 0x20 + 32 + read-only + 0x0 + 0xFFFFFFC0 + + + ADDR26 + This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register. + [31:6] + read-only + + + + + MS_SIZE + Master region, size + 0x24 + 32 + read-only + 0x85000000 + 0x9F000000 + + + REGION_SIZE + This field specifies the size of the master region: +'5': 64 B region + +The master region includes the SL_ADDR, SL_SIZE, SL_ATT0, ..., SL_ATT3, MS_ADDR, MS_SIZE, MS_ATT0, ..., MS_ATT3 registers. Therefore, the access privileges for all these registers is determined by MS_ATT0, ..., MS_ATT3. + [28:24] + read-only + + + VALID + Master region enable: +'1': Enabled. + [31:31] + read-only + + + + + MS_ATT0 + Master attributes 0 + 0x30 + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC0_UR + Protection context 0, user read enable: +'0': Disabled (user, read accesses are NOT allowed). +'1': Enabled (user, read accesses are allowed). + [0:0] + read-only + + + PC0_UW + Protection context 0, user write enable: +'0': Disabled (user, write accesses are NOT allowed). +'1': Enabled (user, write accesses are allowed). + [1:1] + read-only + + + PC0_PR + Protection context 0, privileged read enable: +'0': Disabled (privileged, read accesses are NOT allowed). +'1': Enabled (privileged, read accesses are allowed). + [2:2] + read-only + + + PC0_PW + Protection context 0, privileged write enable: +'0': Disabled (privileged, write accesses are NOT allowed). +'1': Enabled (privileged, write accesses are allowed). + [3:3] + read-only + + + PC0_NS + Protection context 0, non-secure: +'0': Secure (secure accesses allowed, non-secure access NOT allowed). +'1': Non-secure (both secure and non-secure accesses allowed). + [4:4] + read-only + + + PC1_UR + Protection context 1, user read enable. + [8:8] + read-only + + + PC1_UW + Protection context 1, user write enable. + [9:9] + read-write + + + PC1_PR + Protection context 1, privileged read enable. + [10:10] + read-only + + + PC1_PW + Protection context 1, privileged write enable. + [11:11] + read-write + + + PC1_NS + Protection context 1, non-secure. + [12:12] + read-write + + + PC2_UR + Protection context 2, user read enable. + [16:16] + read-only + + + PC2_UW + Protection context 2, user write enable. + [17:17] + read-write + + + PC2_PR + Protection context 2, privileged read enable. + [18:18] + read-only + + + PC2_PW + Protection context 2, privileged write enable. + [19:19] + read-write + + + PC2_NS + Protection context 2, non-secure. + [20:20] + read-write + + + PC3_UR + Protection context 3, user read enable. + [24:24] + read-only + + + PC3_UW + Protection context 3, user write enable. + [25:25] + read-write + + + PC3_PR + Protection context 3, privileged read enable. + [26:26] + read-only + + + PC3_PW + Protection context 3, privileged write enable. + [27:27] + read-write + + + PC3_NS + Protection context 3, non-secure. + [28:28] + read-write + + + + + MS_ATT1 + Master attributes 1 + 0x34 + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC4_UR + Protection context 4, user read enable. + [0:0] + read-only + + + PC4_UW + Protection context 4, user write enable. + [1:1] + read-write + + + PC4_PR + Protection context 4, privileged read enable. + [2:2] + read-only + + + PC4_PW + Protection context 4, privileged write enable. + [3:3] + read-write + + + PC4_NS + Protection context 4, non-secure. + [4:4] + read-write + + + PC5_UR + Protection context 5, user read enable. + [8:8] + read-only + + + PC5_UW + Protection context 5, user write enable. + [9:9] + read-write + + + PC5_PR + Protection context 5, privileged read enable. + [10:10] + read-only + + + PC5_PW + Protection context 5, privileged write enable. + [11:11] + read-write + + + PC5_NS + Protection context 5, non-secure. + [12:12] + read-write + + + PC6_UR + Protection context 6, user read enable. + [16:16] + read-only + + + PC6_UW + Protection context 6, user write enable. + [17:17] + read-write + + + PC6_PR + Protection context 6, privileged read enable. + [18:18] + read-only + + + PC6_PW + Protection context 6, privileged write enable. + [19:19] + read-write + + + PC6_NS + Protection context 6, non-secure. + [20:20] + read-write + + + PC7_UR + Protection context 7, user read enable. + [24:24] + read-only + + + PC7_UW + Protection context 7, user write enable. + [25:25] + read-write + + + PC7_PR + Protection context 7, privileged read enable. + [26:26] + read-only + + + PC7_PW + Protection context 7, privileged write enable. + [27:27] + read-write + + + PC7_NS + Protection context 7, non-secure. + [28:28] + read-write + + + + + MS_ATT2 + Master attributes 2 + 0x38 + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC8_UR + Protection context 8, user read enable. + [0:0] + read-only + + + PC8_UW + Protection context 8, user write enable. + [1:1] + read-write + + + PC8_PR + Protection context 8, privileged read enable. + [2:2] + read-only + + + PC8_PW + Protection context 8, privileged write enable. + [3:3] + read-write + + + PC8_NS + Protection context 8, non-secure. + [4:4] + read-write + + + PC9_UR + Protection context 9, user read enable. + [8:8] + read-only + + + PC9_UW + Protection context 9, user write enable. + [9:9] + read-write + + + PC9_PR + Protection context 9, privileged read enable. + [10:10] + read-only + + + PC9_PW + Protection context 9, privileged write enable. + [11:11] + read-write + + + PC9_NS + Protection context 9, non-secure. + [12:12] + read-write + + + PC10_UR + Protection context 10, user read enable. + [16:16] + read-only + + + PC10_UW + Protection context 10, user write enable. + [17:17] + read-write + + + PC10_PR + Protection context 10, privileged read enable. + [18:18] + read-only + + + PC10_PW + Protection context 10, privileged write enable. + [19:19] + read-write + + + PC10_NS + Protection context 10, non-secure. + [20:20] + read-write + + + PC11_UR + Protection context 11, user read enable. + [24:24] + read-only + + + PC11_UW + Protection context 11, user write enable. + [25:25] + read-write + + + PC11_PR + Protection context 11, privileged read enable. + [26:26] + read-only + + + PC11_PW + Protection context 11, privileged write enable. + [27:27] + read-write + + + PC11_NS + Protection context 11, non-secure. + [28:28] + read-write + + + + + MS_ATT3 + Master attributes 3 + 0x3C + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC12_UR + Protection context 12, user read enable. + [0:0] + read-only + + + PC12_UW + Protection context 12, user write enable. + [1:1] + read-write + + + PC12_PR + Protection context 12, privileged read enable. + [2:2] + read-only + + + PC12_PW + Protection context 12, privileged write enable. + [3:3] + read-write + + + PC12_NS + Protection context 12, non-secure. + [4:4] + read-write + + + PC13_UR + Protection context 13, user read enable. + [8:8] + read-only + + + PC13_UW + Protection context 13, user write enable. + [9:9] + read-write + + + PC13_PR + Protection context 13, privileged read enable. + [10:10] + read-only + + + PC13_PW + Protection context 13, privileged write enable. + [11:11] + read-write + + + PC13_NS + Protection context 13, non-secure. + [12:12] + read-write + + + PC14_UR + Protection context 14, user read enable. + [16:16] + read-only + + + PC14_UW + Protection context 14, user write enable. + [17:17] + read-write + + + PC14_PR + Protection context 14, privileged read enable. + [18:18] + read-only + + + PC14_PW + Protection context 14, privileged write enable. + [19:19] + read-write + + + PC14_NS + Protection context 14, non-secure. + [20:20] + read-write + + + PC15_UR + Protection context 15, user read enable. + [24:24] + read-only + + + PC15_UW + Protection context 15, user write enable. + [25:25] + read-write + + + PC15_PR + Protection context 15, privileged read enable. + [26:26] + read-only + + + PC15_PW + Protection context 15, privileged write enable. + [27:27] + read-write + + + PC15_NS + Protection context 15, non-secure. + [28:28] + read-write + + + + + + 226 + 64 + PPU_FX[%s] + Fixed protection structure pair + 0x00000800 + + SL_ADDR + Slave region, base address + 0x0 + 32 + read-only + 0x0 + 0xFFFFFFFC + + + ADDR30 + This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore, some of the lesser significant address bits of ADDR30 must be '0's. E.g., a 64 KB address region (REGION_SIZE is '15') must be 64 KByte aligned, and ADDR30[13:0] must be '0's. + [31:2] + read-only + + + + + SL_SIZE + Slave region, size + 0x4 + 32 + read-only + 0x80000000 + 0x9F000000 + + + REGION_SIZE + This field specifies the size of the slave region: +'0': Undefined. +'1': 4 B region (this is the smallest region size). +'2': 8 B region +'3': 16 B region +'4': 32 B region +'5': 64 B region +'6': 128 B region +'7': 256 B region +'8': 512 B region +'9': 1 KB region +'10': 2 KB region +'11': 4 KB region +'12': 8 KB region +'13': 16 KB region +'14': 32 KB region +'15': 64 KB region +'16': 128 KB region +'17': 256 KB region +'18': 512 KB region +'19': 1 MB region +'20': 2 MB region +'21': 4 MB region +'22': 8 MB region +'23': 16 MB region +'24': 32 MB region +'25': 64 MB region +'26': 128 MB region +'27': 256 MB region +'28': 512 MB region +'29': 1 GB region +'30': 2 GB region +'31': 4 GB region + [28:24] + read-only + + + VALID + Slave region enable: +'0': Disabled. A disabled region will never result in a match on the transfer address. +'1': Enabled. + [31:31] + read-only + + + + + SL_ATT0 + Slave attributes 0 + 0x10 + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC0_UR + Protection context 0, user read enable: +'0': Disabled (user, read accesses are NOT allowed). +'1': Enabled (user, read accesses are allowed). + [0:0] + read-only + + + PC0_UW + Protection context 0, user write enable: +'0': Disabled (user, write accesses are NOT allowed). +'1': Enabled (user, write accesses are allowed). + [1:1] + read-only + + + PC0_PR + Protection context 0, privileged read enable: +'0': Disabled (privileged, read accesses are NOT allowed). +'1': Enabled (privileged, read accesses are allowed). + [2:2] + read-only + + + PC0_PW + Protection context 0, privileged write enable: +'0': Disabled (privileged, write accesses are NOT allowed). +'1': Enabled (privileged, write accesses are allowed). + [3:3] + read-only + + + PC0_NS + Protection context 0, non-secure: +'0': Secure (secure accesses allowed, non-secure access NOT allowed). +'1': Non-secure (both secure and non-secure accesses allowed). + [4:4] + read-only + + + PC1_UR + Protection context 1, user read enable. + [8:8] + read-write + + + PC1_UW + Protection context 1, user write enable. + [9:9] + read-write + + + PC1_PR + Protection context 1, privileged read enable. + [10:10] + read-write + + + PC1_PW + Protection context 1, privileged write enable. + [11:11] + read-write + + + PC1_NS + Protection context 1, non-secure. + [12:12] + read-write + + + PC2_UR + Protection context 2, user read enable. + [16:16] + read-write + + + PC2_UW + Protection context 2, user write enable. + [17:17] + read-write + + + PC2_PR + Protection context 2, privileged read enable. + [18:18] + read-write + + + PC2_PW + Protection context 2, privileged write enable. + [19:19] + read-write + + + PC2_NS + Protection context 2, non-secure. + [20:20] + read-write + + + PC3_UR + Protection context 3, user read enable. + [24:24] + read-write + + + PC3_UW + Protection context 3, user write enable. + [25:25] + read-write + + + PC3_PR + Protection context 3, privileged read enable. + [26:26] + read-write + + + PC3_PW + Protection context 3, privileged write enable. + [27:27] + read-write + + + PC3_NS + Protection context 3, non-secure. + [28:28] + read-write + + + + + SL_ATT1 + Slave attributes 1 + 0x14 + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC4_UR + Protection context 4, user read enable. + [0:0] + read-write + + + PC4_UW + Protection context 4, user write enable. + [1:1] + read-write + + + PC4_PR + Protection context 4, privileged read enable. + [2:2] + read-write + + + PC4_PW + Protection context 4, privileged write enable. + [3:3] + read-write + + + PC4_NS + Protection context 4, non-secure. + [4:4] + read-write + + + PC5_UR + Protection context 5, user read enable. + [8:8] + read-write + + + PC5_UW + Protection context 5, user write enable. + [9:9] + read-write + + + PC5_PR + Protection context 5, privileged read enable. + [10:10] + read-write + + + PC5_PW + Protection context 5, privileged write enable. + [11:11] + read-write + + + PC5_NS + Protection context 5, non-secure. + [12:12] + read-write + + + PC6_UR + Protection context 6, user read enable. + [16:16] + read-write + + + PC6_UW + Protection context 6, user write enable. + [17:17] + read-write + + + PC6_PR + Protection context 6, privileged read enable. + [18:18] + read-write + + + PC6_PW + Protection context 6, privileged write enable. + [19:19] + read-write + + + PC6_NS + Protection context 6, non-secure. + [20:20] + read-write + + + PC7_UR + Protection context 7, user read enable. + [24:24] + read-write + + + PC7_UW + Protection context 7, user write enable. + [25:25] + read-write + + + PC7_PR + Protection context 7, privileged read enable. + [26:26] + read-write + + + PC7_PW + Protection context 7, privileged write enable. + [27:27] + read-write + + + PC7_NS + Protection context 7, non-secure. + [28:28] + read-write + + + + + SL_ATT2 + Slave attributes 2 + 0x18 + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC8_UR + Protection context 8, user read enable. + [0:0] + read-write + + + PC8_UW + Protection context 8, user write enable. + [1:1] + read-write + + + PC8_PR + Protection context 8, privileged read enable. + [2:2] + read-write + + + PC8_PW + Protection context 8, privileged write enable. + [3:3] + read-write + + + PC8_NS + Protection context 8, non-secure. + [4:4] + read-write + + + PC9_UR + Protection context 9, user read enable. + [8:8] + read-write + + + PC9_UW + Protection context 9, user write enable. + [9:9] + read-write + + + PC9_PR + Protection context 9, privileged read enable. + [10:10] + read-write + + + PC9_PW + Protection context 9, privileged write enable. + [11:11] + read-write + + + PC9_NS + Protection context 9, non-secure. + [12:12] + read-write + + + PC10_UR + Protection context 10, user read enable. + [16:16] + read-write + + + PC10_UW + Protection context 10, user write enable. + [17:17] + read-write + + + PC10_PR + Protection context 10, privileged read enable. + [18:18] + read-write + + + PC10_PW + Protection context 10, privileged write enable. + [19:19] + read-write + + + PC10_NS + Protection context 10, non-secure. + [20:20] + read-write + + + PC11_UR + Protection context 11, user read enable. + [24:24] + read-write + + + PC11_UW + Protection context 11, user write enable. + [25:25] + read-write + + + PC11_PR + Protection context 11, privileged read enable. + [26:26] + read-write + + + PC11_PW + Protection context 11, privileged write enable. + [27:27] + read-write + + + PC11_NS + Protection context 11, non-secure. + [28:28] + read-write + + + + + SL_ATT3 + Slave attributes 3 + 0x1C + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC12_UR + Protection context 12, user read enable. + [0:0] + read-write + + + PC12_UW + Protection context 12, user write enable. + [1:1] + read-write + + + PC12_PR + Protection context 12, privileged read enable. + [2:2] + read-write + + + PC12_PW + Protection context 12, privileged write enable. + [3:3] + read-write + + + PC12_NS + Protection context 12, non-secure. + [4:4] + read-write + + + PC13_UR + Protection context 13, user read enable. + [8:8] + read-write + + + PC13_UW + Protection context 13, user write enable. + [9:9] + read-write + + + PC13_PR + Protection context 13, privileged read enable. + [10:10] + read-write + + + PC13_PW + Protection context 13, privileged write enable. + [11:11] + read-write + + + PC13_NS + Protection context 13, non-secure. + [12:12] + read-write + + + PC14_UR + Protection context 14, user read enable. + [16:16] + read-write + + + PC14_UW + Protection context 14, user write enable. + [17:17] + read-write + + + PC14_PR + Protection context 14, privileged read enable. + [18:18] + read-write + + + PC14_PW + Protection context 14, privileged write enable. + [19:19] + read-write + + + PC14_NS + Protection context 14, non-secure. + [20:20] + read-write + + + PC15_UR + Protection context 15, user read enable. + [24:24] + read-write + + + PC15_UW + Protection context 15, user write enable. + [25:25] + read-write + + + PC15_PR + Protection context 15, privileged read enable. + [26:26] + read-write + + + PC15_PW + Protection context 15, privileged write enable. + [27:27] + read-write + + + PC15_NS + Protection context 15, non-secure. + [28:28] + read-write + + + + + MS_ADDR + Master region, base address + 0x20 + 32 + read-only + 0x0 + 0xFFFFFFC0 + + + ADDR26 + This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register. + [31:6] + read-only + + + + + MS_SIZE + Master region, size + 0x24 + 32 + read-only + 0x85000000 + 0x9F000000 + + + REGION_SIZE + This field specifies the size of the master region: +'5': 64 B region + +The master region includes the SL_ADDR, SL_SIZE, SL_ATT0, ..., SL_ATT3, MS_ADDR, MS_SIZE, MS_ATT0, ..., MS_ATT3 registers. Therefore, the access privileges for all these registers is determined by MS_ATT0, ..., MS_ATT3. + [28:24] + read-only + + + VALID + Master region enable: +'1': Enabled. + [31:31] + read-only + + + + + MS_ATT0 + Master attributes 0 + 0x30 + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC0_UR + Protection context 0, user read enable: +'0': Disabled (user, read accesses are NOT allowed). +'1': Enabled (user, read accesses are allowed). + [0:0] + read-only + + + PC0_UW + Protection context 0, user write enable: +'0': Disabled (user, write accesses are NOT allowed). +'1': Enabled (user, write accesses are allowed). + [1:1] + read-only + + + PC0_PR + Protection context 0, privileged read enable: +'0': Disabled (privileged, read accesses are NOT allowed). +'1': Enabled (privileged, read accesses are allowed). + [2:2] + read-only + + + PC0_PW + Protection context 0, privileged write enable: +'0': Disabled (privileged, write accesses are NOT allowed). +'1': Enabled (privileged, write accesses are allowed). + [3:3] + read-only + + + PC0_NS + Protection context 0, non-secure: +'0': Secure (secure accesses allowed, non-secure access NOT allowed). +'1': Non-secure (both secure and non-secure accesses allowed). + [4:4] + read-only + + + PC1_UR + Protection context 1, user read enable. + [8:8] + read-only + + + PC1_UW + Protection context 1, user write enable. + [9:9] + read-write + + + PC1_PR + Protection context 1, privileged read enable. + [10:10] + read-only + + + PC1_PW + Protection context 1, privileged write enable. + [11:11] + read-write + + + PC1_NS + Protection context 1, non-secure. + [12:12] + read-write + + + PC2_UR + Protection context 2, user read enable. + [16:16] + read-only + + + PC2_UW + Protection context 2, user write enable. + [17:17] + read-write + + + PC2_PR + Protection context 2, privileged read enable. + [18:18] + read-only + + + PC2_PW + Protection context 2, privileged write enable. + [19:19] + read-write + + + PC2_NS + Protection context 2, non-secure. + [20:20] + read-write + + + PC3_UR + Protection context 3, user read enable. + [24:24] + read-only + + + PC3_UW + Protection context 3, user write enable. + [25:25] + read-write + + + PC3_PR + Protection context 3, privileged read enable. + [26:26] + read-only + + + PC3_PW + Protection context 3, privileged write enable. + [27:27] + read-write + + + PC3_NS + Protection context 3, non-secure. + [28:28] + read-write + + + + + MS_ATT1 + Master attributes 1 + 0x34 + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC4_UR + Protection context 4, user read enable. + [0:0] + read-only + + + PC4_UW + Protection context 4, user write enable. + [1:1] + read-write + + + PC4_PR + Protection context 4, privileged read enable. + [2:2] + read-only + + + PC4_PW + Protection context 4, privileged write enable. + [3:3] + read-write + + + PC4_NS + Protection context 4, non-secure. + [4:4] + read-write + + + PC5_UR + Protection context 5, user read enable. + [8:8] + read-only + + + PC5_UW + Protection context 5, user write enable. + [9:9] + read-write + + + PC5_PR + Protection context 5, privileged read enable. + [10:10] + read-only + + + PC5_PW + Protection context 5, privileged write enable. + [11:11] + read-write + + + PC5_NS + Protection context 5, non-secure. + [12:12] + read-write + + + PC6_UR + Protection context 6, user read enable. + [16:16] + read-only + + + PC6_UW + Protection context 6, user write enable. + [17:17] + read-write + + + PC6_PR + Protection context 6, privileged read enable. + [18:18] + read-only + + + PC6_PW + Protection context 6, privileged write enable. + [19:19] + read-write + + + PC6_NS + Protection context 6, non-secure. + [20:20] + read-write + + + PC7_UR + Protection context 7, user read enable. + [24:24] + read-only + + + PC7_UW + Protection context 7, user write enable. + [25:25] + read-write + + + PC7_PR + Protection context 7, privileged read enable. + [26:26] + read-only + + + PC7_PW + Protection context 7, privileged write enable. + [27:27] + read-write + + + PC7_NS + Protection context 7, non-secure. + [28:28] + read-write + + + + + MS_ATT2 + Master attributes 2 + 0x38 + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC8_UR + Protection context 8, user read enable. + [0:0] + read-only + + + PC8_UW + Protection context 8, user write enable. + [1:1] + read-write + + + PC8_PR + Protection context 8, privileged read enable. + [2:2] + read-only + + + PC8_PW + Protection context 8, privileged write enable. + [3:3] + read-write + + + PC8_NS + Protection context 8, non-secure. + [4:4] + read-write + + + PC9_UR + Protection context 9, user read enable. + [8:8] + read-only + + + PC9_UW + Protection context 9, user write enable. + [9:9] + read-write + + + PC9_PR + Protection context 9, privileged read enable. + [10:10] + read-only + + + PC9_PW + Protection context 9, privileged write enable. + [11:11] + read-write + + + PC9_NS + Protection context 9, non-secure. + [12:12] + read-write + + + PC10_UR + Protection context 10, user read enable. + [16:16] + read-only + + + PC10_UW + Protection context 10, user write enable. + [17:17] + read-write + + + PC10_PR + Protection context 10, privileged read enable. + [18:18] + read-only + + + PC10_PW + Protection context 10, privileged write enable. + [19:19] + read-write + + + PC10_NS + Protection context 10, non-secure. + [20:20] + read-write + + + PC11_UR + Protection context 11, user read enable. + [24:24] + read-only + + + PC11_UW + Protection context 11, user write enable. + [25:25] + read-write + + + PC11_PR + Protection context 11, privileged read enable. + [26:26] + read-only + + + PC11_PW + Protection context 11, privileged write enable. + [27:27] + read-write + + + PC11_NS + Protection context 11, non-secure. + [28:28] + read-write + + + + + MS_ATT3 + Master attributes 3 + 0x3C + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC12_UR + Protection context 12, user read enable. + [0:0] + read-only + + + PC12_UW + Protection context 12, user write enable. + [1:1] + read-write + + + PC12_PR + Protection context 12, privileged read enable. + [2:2] + read-only + + + PC12_PW + Protection context 12, privileged write enable. + [3:3] + read-write + + + PC12_NS + Protection context 12, non-secure. + [4:4] + read-write + + + PC13_UR + Protection context 13, user read enable. + [8:8] + read-only + + + PC13_UW + Protection context 13, user write enable. + [9:9] + read-write + + + PC13_PR + Protection context 13, privileged read enable. + [10:10] + read-only + + + PC13_PW + Protection context 13, privileged write enable. + [11:11] + read-write + + + PC13_NS + Protection context 13, non-secure. + [12:12] + read-write + + + PC14_UR + Protection context 14, user read enable. + [16:16] + read-only + + + PC14_UW + Protection context 14, user write enable. + [17:17] + read-write + + + PC14_PR + Protection context 14, privileged read enable. + [18:18] + read-only + + + PC14_PW + Protection context 14, privileged write enable. + [19:19] + read-write + + + PC14_NS + Protection context 14, non-secure. + [20:20] + read-write + + + PC15_UR + Protection context 15, user read enable. + [24:24] + read-only + + + PC15_UW + Protection context 15, user write enable. + [25:25] + read-write + + + PC15_PR + Protection context 15, privileged read enable. + [26:26] + read-only + + + PC15_PW + Protection context 15, privileged write enable. + [27:27] + read-write + + + PC15_NS + Protection context 15, non-secure. + [28:28] + read-write + + + + + + + + CPUSS + CPU subsystem (CPUSS) + 0x40200000 + + 0 + 65536 + registers + + + ioss_interrupts_gpio_0 + GPIO Port Interrupt #0 + 0 + + + ioss_interrupts_gpio_2 + GPIO Port Interrupt #2 + 2 + + + ioss_interrupts_gpio_3 + GPIO Port Interrupt #3 + 3 + + + ioss_interrupts_gpio_5 + GPIO Port Interrupt #5 + 5 + + + ioss_interrupts_gpio_6 + GPIO Port Interrupt #6 + 6 + + + ioss_interrupts_gpio_7 + GPIO Port Interrupt #7 + 7 + + + ioss_interrupts_gpio_8 + GPIO Port Interrupt #8 + 8 + + + ioss_interrupts_gpio_9 + GPIO Port Interrupt #9 + 9 + + + ioss_interrupts_gpio_10 + GPIO Port Interrupt #10 + 10 + + + ioss_interrupts_gpio_11 + GPIO Port Interrupt #11 + 11 + + + ioss_interrupts_gpio_12 + GPIO Port Interrupt #12 + 12 + + + ioss_interrupts_gpio_14 + GPIO Port Interrupt #14 + 14 + + + ioss_interrupt_gpio + GPIO All Ports + 15 + + + ioss_interrupt_vdd + GPIO Supply Detect Interrupt + 16 + + + lpcomp_interrupt + Low Power Comparator Interrupt + 17 + + + scb_6_interrupt + Serial Communication Block #6 (DeepSleep capable) + 18 + + + srss_interrupt_mcwdt_0 + Multi Counter Watchdog Timer interrupt + 19 + + + srss_interrupt_mcwdt_1 + Multi Counter Watchdog Timer interrupt + 20 + + + srss_interrupt_backup + Backup domain interrupt + 21 + + + srss_interrupt + Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) + 22 + + + cpuss_interrupts_ipc_0 + CPUSS Inter Process Communication Interrupt #0 + 23 + + + cpuss_interrupts_ipc_1 + CPUSS Inter Process Communication Interrupt #1 + 24 + + + cpuss_interrupts_ipc_2 + CPUSS Inter Process Communication Interrupt #2 + 25 + + + cpuss_interrupts_ipc_3 + CPUSS Inter Process Communication Interrupt #3 + 26 + + + cpuss_interrupts_ipc_4 + CPUSS Inter Process Communication Interrupt #4 + 27 + + + cpuss_interrupts_ipc_5 + CPUSS Inter Process Communication Interrupt #5 + 28 + + + cpuss_interrupts_ipc_6 + CPUSS Inter Process Communication Interrupt #6 + 29 + + + cpuss_interrupts_ipc_7 + CPUSS Inter Process Communication Interrupt #7 + 30 + + + cpuss_interrupts_ipc_8 + CPUSS Inter Process Communication Interrupt #8 + 31 + + + cpuss_interrupts_ipc_9 + CPUSS Inter Process Communication Interrupt #9 + 32 + + + cpuss_interrupts_ipc_10 + CPUSS Inter Process Communication Interrupt #10 + 33 + + + cpuss_interrupts_ipc_11 + CPUSS Inter Process Communication Interrupt #11 + 34 + + + cpuss_interrupts_ipc_12 + CPUSS Inter Process Communication Interrupt #12 + 35 + + + cpuss_interrupts_ipc_13 + CPUSS Inter Process Communication Interrupt #13 + 36 + + + cpuss_interrupts_ipc_14 + CPUSS Inter Process Communication Interrupt #14 + 37 + + + cpuss_interrupts_ipc_15 + CPUSS Inter Process Communication Interrupt #15 + 38 + + + pass_interrupt_sar_0 + SAR ADC0 interrupt + 39 + + + pass_interrupt_sar_1 + SAR ADC1 interrupt + 40 + + + pass_interrupt_ctb + individual interrupt per CTB + 41 + + + pass_interrupt_fifo_0 + PASS FIFO0 + 43 + + + pass_interrupt_fifo_1 + PASS FIFO1 + 44 + + + scb_0_interrupt + Serial Communication Block #0 + 45 + + + scb_1_interrupt + Serial Communication Block #1 + 46 + + + scb_2_interrupt + Serial Communication Block #2 + 47 + + + scb_4_interrupt + Serial Communication Block #4 + 49 + + + scb_5_interrupt + Serial Communication Block #5 + 50 + + + csd_interrupt + CSD (Capsense) interrupt + 51 + + + cpuss_interrupts_dmac_0 + CPUSS DMAC, Channel #0 + 52 + + + cpuss_interrupts_dmac_1 + CPUSS DMAC, Channel #1 + 53 + + + cpuss_interrupts_dw0_0 + CPUSS DataWire #0, Channel #0 + 56 + + + cpuss_interrupts_dw0_1 + CPUSS DataWire #0, Channel #1 + 57 + + + cpuss_interrupts_dw0_2 + CPUSS DataWire #0, Channel #2 + 58 + + + cpuss_interrupts_dw0_3 + CPUSS DataWire #0, Channel #3 + 59 + + + cpuss_interrupts_dw0_4 + CPUSS DataWire #0, Channel #4 + 60 + + + cpuss_interrupts_dw0_5 + CPUSS DataWire #0, Channel #5 + 61 + + + cpuss_interrupts_dw0_6 + CPUSS DataWire #0, Channel #6 + 62 + + + cpuss_interrupts_dw0_7 + CPUSS DataWire #0, Channel #7 + 63 + + + cpuss_interrupts_dw0_8 + CPUSS DataWire #0, Channel #8 + 64 + + + cpuss_interrupts_dw0_9 + CPUSS DataWire #0, Channel #9 + 65 + + + cpuss_interrupts_dw0_10 + CPUSS DataWire #0, Channel #10 + 66 + + + cpuss_interrupts_dw0_11 + CPUSS DataWire #0, Channel #11 + 67 + + + cpuss_interrupts_dw0_12 + CPUSS DataWire #0, Channel #12 + 68 + + + cpuss_interrupts_dw0_13 + CPUSS DataWire #0, Channel #13 + 69 + + + cpuss_interrupts_dw0_14 + CPUSS DataWire #0, Channel #14 + 70 + + + cpuss_interrupts_dw0_15 + CPUSS DataWire #0, Channel #15 + 71 + + + cpuss_interrupts_dw0_16 + CPUSS DataWire #0, Channel #16 + 72 + + + cpuss_interrupts_dw0_17 + CPUSS DataWire #0, Channel #17 + 73 + + + cpuss_interrupts_dw0_18 + CPUSS DataWire #0, Channel #18 + 74 + + + cpuss_interrupts_dw0_19 + CPUSS DataWire #0, Channel #19 + 75 + + + cpuss_interrupts_dw0_20 + CPUSS DataWire #0, Channel #20 + 76 + + + cpuss_interrupts_dw0_21 + CPUSS DataWire #0, Channel #21 + 77 + + + cpuss_interrupts_dw0_22 + CPUSS DataWire #0, Channel #22 + 78 + + + cpuss_interrupts_dw0_23 + CPUSS DataWire #0, Channel #23 + 79 + + + cpuss_interrupts_dw0_24 + CPUSS DataWire #0, Channel #24 + 80 + + + cpuss_interrupts_dw0_25 + CPUSS DataWire #0, Channel #25 + 81 + + + cpuss_interrupts_dw0_26 + CPUSS DataWire #0, Channel #26 + 82 + + + cpuss_interrupts_dw0_27 + CPUSS DataWire #0, Channel #27 + 83 + + + cpuss_interrupts_dw0_28 + CPUSS DataWire #0, Channel #28 + 84 + + + cpuss_interrupts_dw1_0 + CPUSS DataWire #1, Channel #0 + 85 + + + cpuss_interrupts_dw1_1 + CPUSS DataWire #1, Channel #1 + 86 + + + cpuss_interrupts_dw1_2 + CPUSS DataWire #1, Channel #2 + 87 + + + cpuss_interrupts_dw1_3 + CPUSS DataWire #1, Channel #3 + 88 + + + cpuss_interrupts_dw1_4 + CPUSS DataWire #1, Channel #4 + 89 + + + cpuss_interrupts_dw1_5 + CPUSS DataWire #1, Channel #5 + 90 + + + cpuss_interrupts_dw1_6 + CPUSS DataWire #1, Channel #6 + 91 + + + cpuss_interrupts_dw1_7 + CPUSS DataWire #1, Channel #7 + 92 + + + cpuss_interrupts_dw1_8 + CPUSS DataWire #1, Channel #8 + 93 + + + cpuss_interrupts_dw1_9 + CPUSS DataWire #1, Channel #9 + 94 + + + cpuss_interrupts_dw1_10 + CPUSS DataWire #1, Channel #10 + 95 + + + cpuss_interrupts_dw1_11 + CPUSS DataWire #1, Channel #11 + 96 + + + cpuss_interrupts_dw1_12 + CPUSS DataWire #1, Channel #12 + 97 + + + cpuss_interrupts_dw1_13 + CPUSS DataWire #1, Channel #13 + 98 + + + cpuss_interrupts_dw1_14 + CPUSS DataWire #1, Channel #14 + 99 + + + cpuss_interrupts_dw1_15 + CPUSS DataWire #1, Channel #15 + 100 + + + cpuss_interrupts_dw1_16 + CPUSS DataWire #1, Channel #16 + 101 + + + cpuss_interrupts_dw1_17 + CPUSS DataWire #1, Channel #17 + 102 + + + cpuss_interrupts_dw1_18 + CPUSS DataWire #1, Channel #18 + 103 + + + cpuss_interrupts_dw1_19 + CPUSS DataWire #1, Channel #19 + 104 + + + cpuss_interrupts_dw1_20 + CPUSS DataWire #1, Channel #20 + 105 + + + cpuss_interrupts_dw1_21 + CPUSS DataWire #1, Channel #21 + 106 + + + cpuss_interrupts_dw1_22 + CPUSS DataWire #1, Channel #22 + 107 + + + cpuss_interrupts_dw1_23 + CPUSS DataWire #1, Channel #23 + 108 + + + cpuss_interrupts_dw1_24 + CPUSS DataWire #1, Channel #24 + 109 + + + cpuss_interrupts_dw1_25 + CPUSS DataWire #1, Channel #25 + 110 + + + cpuss_interrupts_dw1_26 + CPUSS DataWire #1, Channel #26 + 111 + + + cpuss_interrupts_dw1_27 + CPUSS DataWire #1, Channel #27 + 112 + + + cpuss_interrupts_dw1_28 + CPUSS DataWire #1, Channel #28 + 113 + + + cpuss_interrupts_fault_0 + CPUSS Fault Structure Interrupt #0 + 114 + + + cpuss_interrupts_fault_1 + CPUSS Fault Structure Interrupt #1 + 115 + + + cpuss_interrupt_crypto + CRYPTO Accelerator Interrupt + 116 + + + cpuss_interrupt_fm + FLASH Macro Interrupt + 117 + + + cpuss_interrupts_cm4_fp + Floating Point operation fault + 118 + + + cpuss_interrupts_cm0_cti_0 + CM0+ CTI #0 + 119 + + + cpuss_interrupts_cm0_cti_1 + CM0+ CTI #1 + 120 + + + cpuss_interrupts_cm4_cti_0 + CM4 CTI #0 + 121 + + + cpuss_interrupts_cm4_cti_1 + CM4 CTI #1 + 122 + + + tcpwm_0_interrupts_0 + TCPWM #0, Counter #0 + 123 + + + tcpwm_0_interrupts_1 + TCPWM #0, Counter #1 + 124 + + + tcpwm_0_interrupts_2 + TCPWM #0, Counter #2 + 125 + + + tcpwm_0_interrupts_3 + TCPWM #0, Counter #3 + 126 + + + tcpwm_0_interrupts_256 + TCPWM #0, Counter #256 + 131 + + + tcpwm_0_interrupts_257 + TCPWM #0, Counter #257 + 132 + + + tcpwm_0_interrupts_258 + TCPWM #0, Counter #258 + 133 + + + tcpwm_0_interrupts_259 + TCPWM #0, Counter #259 + 134 + + + tcpwm_0_interrupts_260 + TCPWM #0, Counter #260 + 135 + + + tcpwm_0_interrupts_261 + TCPWM #0, Counter #261 + 136 + + + tcpwm_0_interrupts_262 + TCPWM #0, Counter #262 + 137 + + + tcpwm_0_interrupts_263 + TCPWM #0, Counter #263 + 138 + + + pass_interrupt_dacs + Consolidated interrrupt for all DACs + 146 + + + smif_interrupt + Serial Memory Interface interrupt + 160 + + + usb_interrupt_hi + USB Interrupt + 161 + + + usb_interrupt_med + USB Interrupt + 162 + + + usb_interrupt_lo + USB Interrupt + 163 + + + canfd_0_interrupt0 + Can #0, Consolidated interrupt #0 + 168 + + + canfd_0_interrupts0_0 + CAN #0, Interrupt #0, Channel #0 + 169 + + + canfd_0_interrupts1_0 + CAN #0, Interrupt #1, Channel #0 + 170 + + + cpuss_interrupts_dw1_29 + CPUSS DataWire #1, Channel #29 + 171 + + + cpuss_interrupts_dw1_30 + CPUSS DataWire #1, Channel #30 + 172 + + + cpuss_interrupts_dw1_31 + CPUSS DataWire #1, Channel #31 + 173 + + + cpuss_interrupts_dw0_29 + CPUSS DataWire #0, Channel #29 + 174 + + + + IDENTITY + Identity + 0x0 + 32 + read-only + 0x0 + 0x0 + + + P + This field specifies the privileged setting ('0': user mode; '1': privileged mode) of the transfer that reads the register. + [0:0] + read-only + + + NS + This field specifies the security setting ('0': secure mode; '1': non-secure mode) of the transfer that reads the register. + [1:1] + read-only + + + PC + This field specifies the protection context of the transfer that reads the register. + [7:4] + read-only + + + MS + This field specifies the bus master identifier of the transfer that reads the register. + [11:8] + read-only + + + + + CM4_STATUS + CM4 status + 0x4 + 32 + read-only + 0x13 + 0x13 + + + SLEEPING + Specifies if the CPU is in Active, Sleep or DeepSleep power mode: +- Active power mode: SLEEPING is '0'. +- Sleep power mode: SLEEPING is '1' and SLEEPDEEP is '0'. +- DeepSleep power mode: SLEEPING is '1' and SLEEPDEEP is '1'. + [0:0] + read-only + + + SLEEPDEEP + Specifies if the CPU is in Sleep or DeepSleep power mode. See SLEEPING field. + [1:1] + read-only + + + PWR_DONE + After a PWR_MODE change this flag indicates if the new power mode has taken effect or not. +Note: this flag can also change as a result of a change in debug power up req + [4:4] + read-only + + + + + CM4_CLOCK_CTL + CM4 clock control + 0x8 + 32 + read-write + 0x0 + 0xFF00 + + + FAST_INT_DIV + Specifies the fast clock divider (from the high frequency clock 'clk_hf' to the peripheral clock 'clk_fast'). Integer division by (1+FAST_INT_DIV). Allows for integer divisions in the range [1, 256] (FAST_INT_DIV is in the range [0, 255]). + +Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. + [15:8] + read-write + + + + + CM4_CTL + CM4 control + 0xC + 32 + read-write + 0x0 + 0x9F000000 + + + IOC_MASK + CPU floating point unit (FPU) exception mask for the CPU's FPCSR.IOC 'invalid operation' exception condition: +'0': The CPU's exception condition does NOT activate the CPU's floating point interrupt. +'1': the CPU's exception condition activates the CPU's floating point interrupt. + +Note: the ARM architecture does NOT support FPU exceptions; i.e. there is no precise FPU exception handler. Instead, FPU conditions are captured in the CPU's FPCSR register and the conditions are provided as CPU interface signals. The interface signals are 'masked' with the fields a provide by this register (CM7_0_CTL). The 'masked' signals are reduced/OR-ed into a single CPU floating point interrupt signal. The associated CPU interrupt handler allows for imprecise handling of FPU exception conditions. + +Note: the CPU's FPCSR exception conditions are 'sticky'. Typically, the CPU FPU interrupt handler will clear the exception condition(s) to '0'. + +Note: by default, the FPU exception masks are '0'. Therefore, FPU exception conditions will NOT activate the CPU's floating point interrupt. + [24:24] + read-write + + + DZC_MASK + CPU FPU exception mask for the CPU's FPCSR.DZC 'divide by zero' exception condition: +'0': The CPU's exception condition does NOT activate the CPU's floating point interrupt. +'1': the CPU's exception condition activates the CPU's floating point interrupt. + [25:25] + read-write + + + OFC_MASK + CPU FPU exception mask for the CPU's FPCSR.OFC 'overflow' exception condition: +'0': The CPU's exception condition does NOT activate the CPU's floating point interrupt. +'1': the CPU's exception condition activates the CPU's floating point interrupt. + [26:26] + read-write + + + UFC_MASK + CPU FPU exception mask for the CPU's FPCSR.UFC 'underflow' exception condition: +'0': The CPU's exception condition does NOT activate the CPU's floating point interrupt. +'1': the CPU's exception condition activates the CPU's floating point interrupt. + [27:27] + read-write + + + IXC_MASK + CPU FPU exception mask for the CPU's FPCSR.IXC 'inexact' exception condition: +'0': The CPU's exception condition does NOT activate the CPU's floating point interrupt. +'1': the CPU's exception condition activates the CPU's floating point interrupt. + +Note: the 'inexact' condition is set as a result of rounding. Rounding may occur frequently and is typically not an error condition. To prevent frequent CPU FPU interrupts as a result of rounding, this field is typically set to '0'. + [28:28] + read-write + + + IDC_MASK + CPU FPU exception mask for the CPU's FPCSR.IDC 'input denormalized' exception condition: +'0': The CPU's exception condition does NOT activate the CPU's floating point interrupt. +'1': the CPU's exception condition activates the CPU's floating point interrupt. + +Note: if the CPU FPCSR.FZ field is set to '1', denormalized inputs are 'flushed to zero'. Dependent on the FPU algorithm, this may or may not occur frequently. To prevent frequent CPU FPU interrupts as a result of denormalized inputs, this field may be set to '0'. + [31:31] + read-write + + + + + CM4_INT0_STATUS + CM4 interrupt 0 status + 0x100 + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM4 activated system interrupt index for CPU interrupt 0. + +See description of CM0_INT0_STATUS. + [9:0] + read-only + + + SYSTEM_INT_VALID + See description of CM0_INT0_STATUS. + [31:31] + read-only + + + + + CM4_INT1_STATUS + CM4 interrupt 1 status + 0x104 + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM4 activated system interrupt index for CPU interrupt 1. + +See description of CM0_INT0_STATUS. + [9:0] + read-only + + + SYSTEM_INT_VALID + See description of CM0_INT0_STATUS. + [31:31] + read-only + + + + + CM4_INT2_STATUS + CM4 interrupt 2 status + 0x108 + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM4 activated system interrupt index for CPU interrupt 2. + +See description of CM0_INT0_STATUS. + [9:0] + read-only + + + SYSTEM_INT_VALID + See description of CM0_INT0_STATUS. + [31:31] + read-only + + + + + CM4_INT3_STATUS + CM4 interrupt 3 status + 0x10C + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM4 activated system interrupt index for CPU interrupt 3. + +See description of CM0_INT0_STATUS. + [9:0] + read-only + + + SYSTEM_INT_VALID + See description of CM0_INT0_STATUS. + [31:31] + read-only + + + + + CM4_INT4_STATUS + CM4 interrupt 4 status + 0x110 + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM4 activated system interrupt index for CPU interrupt 4. + +See description of CM0_INT0_STATUS. + [9:0] + read-only + + + SYSTEM_INT_VALID + See description of CM0_INT0_STATUS. + [31:31] + read-only + + + + + CM4_INT5_STATUS + CM4 interrupt 5 status + 0x114 + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM4 activated system interrupt index for CPU interrupt 5. + +See description of CM0_INT0_STATUS. + [9:0] + read-only + + + SYSTEM_INT_VALID + See description of CM0_INT0_STATUS. + [31:31] + read-only + + + + + CM4_INT6_STATUS + CM4 interrupt 6 status + 0x118 + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM4 activated system interrupt index for CPU interrupt 6. + +See description of CM0_INT0_STATUS. + [9:0] + read-only + + + SYSTEM_INT_VALID + See description of CM0_INT0_STATUS. + [31:31] + read-only + + + + + CM4_INT7_STATUS + CM4 interrupt 7 status + 0x11C + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM4 activated system interrupt index for CPU interrupt 7. + +See description of CM0_INT0_STATUS. + [9:0] + read-only + + + SYSTEM_INT_VALID + See description of CM0_INT0_STATUS. + [31:31] + read-only + + + + + CM4_VECTOR_TABLE_BASE + CM4 vector table base + 0x200 + 32 + read-write + 0x0 + 0xFFFFFC00 + + + ADDR22 + Address of CM4 vector table. This register is used for CM4 warm and cold boot purposes: the CM0+ CPU initializes the CM4_VECTOR_TABLE_BASE register and the CM4 boot code uses the register to initialize the CM4 internal VTOR register. + +Note: the CM4 vector table is at an address that is a 1024 B multiple. + [31:10] + read-write + + + + + 4 + 4 + CM4_NMI_CTL[%s] + CM4 NMI control + 0x240 + 32 + read-write + 0x3FF + 0x3FF + + + SYSTEM_INT_IDX + System interrupt select for CPU NMI. The reset value ('1023') ensures that the CPU NMI is NOT connected to any system interrupt after DeepSleep reset. + [9:0] + read-write + + + + + UDB_PWR_CTL + UDB power control + 0x300 + 32 + read-write + 0xFA050001 + 0xFFFF0003 + + + PWR_MODE + Set Power mode for UDBs + [1:0] + read-write + + + OFF + See CM4_PWR_CTL + 0 + + + RESET + See CM4_PWR_CTL + 1 + + + RETAINED + See CM4_PWR_CTL + 2 + + + ENABLED + See CM4_PWR_CTL + 3 + + + + + VECTKEYSTAT + Register key (to prevent accidental writes). +- Should be written with a 0x05fa key value for the write to take effect. +- Always reads as 0xfa05. + [31:16] + read-only + + + + + UDB_PWR_DELAY_CTL + UDB power control + 0x304 + 32 + read-write + 0x12C + 0x3FF + + + UP + Number clock cycles delay needed after power domain power up + [9:0] + read-write + + + + + CM0_CTL + CM0+ control + 0x1000 + 32 + read-write + 0xFA050002 + 0xFFFF0003 + + + SLV_STALL + Processor debug access control: +'0': Access. +'1': Stall access. + +This field is used to stall/delay debug accesses. This is useful to protect execution of code that needs to be protected from debug accesses. + [0:0] + read-write + + + ENABLED + Processor enable: +'0': Disabled. Processor clock is turned off and reset is activated. After SW clears this field to '0', HW automatically sets this field to '1'. This effectively results in a CM0+ reset, followed by a CM0+ warm boot. +'1': Enabled. +Note: The intent is that this bit is modified only through an external probe or by the CM4 while the CM0+ is in Sleep or DeepSleep power mode. If this field is cleared to '0' by the CM0+ itself, it should be done under controlled conditions (such that undesirable side effects can be prevented). + +Note: The CM0+ CPU has a AIRCR.SYSRESETREQ register field that allows the CM0+ to reset the complete device (ENABLED only disables/enables the CM0+), resulting in a warm boot. This CPU register field has similar 'built-in protection' as this CM0_CTL register to prevent accidental system writes (the upper 16-bits of the register need to be written with a 0x05fa key value; see CPU user manual for more details). + [1:1] + read-write + + + VECTKEYSTAT + Register key (to prevent accidental writes). +- Should be written with a 0x05fa key value for the write to take effect. +- Always reads as 0xfa05. + [31:16] + read-only + + + + + CM0_STATUS + CM0+ status + 0x1004 + 32 + read-only + 0x0 + 0x3 + + + SLEEPING + Specifies if the CPU is in Active, Sleep or DeepSleep power mode: +- Active power mode: SLEEPING is '0'. +- Sleep power mode: SLEEPING is '1' and SLEEPDEEP is '0'. +- DeepSleep power mode: SLEEPING is '1' and SLEEPDEEP is '1'. + [0:0] + read-only + + + SLEEPDEEP + Specifies if the CPU is in Sleep or DeepSleep power mode. See SLEEPING field. + [1:1] + read-only + + + + + CM0_CLOCK_CTL + CM0+ clock control + 0x1008 + 32 + read-write + 0x0 + 0xFF00FF00 + + + SLOW_INT_DIV + Specifies the slow clock divider (from the peripheral clock 'clk_peri' to the slow clock 'clk_slow'). Integer division by (1+SLOW_INT_DIV). Allows for integer divisions in the range [1, 256] (SLOW_INT_DIV is in the range [0, 255]). + +Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. + [15:8] + read-write + + + PERI_INT_DIV + Specifies the peripheral clock divider (from the high frequency clock 'clk_hf' to the peripheral clock 'clk_peri'). Integer division by (1+PERI_INT_DIV). Allows for integer divisions in the range [1, 256] (PERI_INT_DIV is in the range [0, 255]). + +Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. + +Note that Fperi <= Fperi_max. Fperi_max is likely to be smaller than Fhf_max. In other words, if Fhf = Fhf_max, PERI_INT_DIV should not be set to '0'. + [31:24] + read-write + + + + + CM0_INT0_STATUS + CM0+ interrupt 0 status + 0x1100 + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM0+ activated system interrupt index for CPU interrupt 0. + +Multiple system interrupts can be mapped on the same CPU interrupt. The selected system interrupt is the system interrupt with the lowest system interrupt index that has an activated interrupt request at the time of the fetch (system_interrupts[SYSTEM_INT_IDX] is '1'). + +The CPU interrupt handler SW can read SYSTEM_INT_IDX to determine the system interrupt that activated the handler. + [9:0] + read-only + + + SYSTEM_INT_VALID + Valid indication for SYSTEM_INT_IDX. When '0', no system interrupt for CPU interrupt 0 is valid/activated. + [31:31] + read-only + + + + + CM0_INT1_STATUS + CM0+ interrupt 1 status + 0x1104 + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM0+ activated system interrupt index for CPU interrupt 1. + +See description of CM0_INT0_STATUS. + [9:0] + read-only + + + SYSTEM_INT_VALID + See description of CM0_INT0_STATUS. + [31:31] + read-only + + + + + CM0_INT2_STATUS + CM0+ interrupt 2 status + 0x1108 + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM0+ activated system interrupt index for CPU interrupt 2. + +See description of CM0_INT0_STATUS. + [9:0] + read-only + + + SYSTEM_INT_VALID + See description of CM0_INT0_STATUS. + [31:31] + read-only + + + + + CM0_INT3_STATUS + CM0+ interrupt 3 status + 0x110C + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM0+ activated system interrupt index for CPU interrupt 3. + +See description of CM0_INT0_STATUS. + [9:0] + read-only + + + SYSTEM_INT_VALID + See description of CM0_INT0_STATUS. + [31:31] + read-only + + + + + CM0_INT4_STATUS + CM0+ interrupt 4 status + 0x1110 + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM0+ activated system interrupt index for CPU interrupt 4. + +See description of CM0_INT0_STATUS. + [9:0] + read-only + + + SYSTEM_INT_VALID + See description of CM0_INT0_STATUS. + [31:31] + read-only + + + + + CM0_INT5_STATUS + CM0+ interrupt 5 status + 0x1114 + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM0+ activated system interrupt index for CPU interrupt 5. + +See description of CM0_INT0_STATUS. + [9:0] + read-only + + + SYSTEM_INT_VALID + See description of CM0_INT0_STATUS. + [31:31] + read-only + + + + + CM0_INT6_STATUS + CM0+ interrupt 6 status + 0x1118 + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM0+ activated system interrupt index for CPU interrupt 6. + +See description of CM0_INT0_STATUS. + [9:0] + read-only + + + SYSTEM_INT_VALID + See description of CM0_INT0_STATUS. + [31:31] + read-only + + + + + CM0_INT7_STATUS + CM0+ interrupt 7 status + 0x111C + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM0+ activated system interrupt index for CPU interrupt 7. + +See description of CM0_INT0_STATUS. + [9:0] + read-only + + + SYSTEM_INT_VALID + See description of CM0_INT0_STATUS. + [31:31] + read-only + + + + + CM0_VECTOR_TABLE_BASE + CM0+ vector table base + 0x1120 + 32 + read-write + 0x0 + 0xFFFFFF00 + + + ADDR24 + Address of CM0+ vector table. This register is used for CM0+ warm boot purposes: the CM0+ warm boot code uses the register to initialize the CM0+ internal VTOR register. + +Note: the CM0+ vector table is at an address that is a 256 B multiple. + [31:8] + read-write + + + + + 4 + 4 + CM0_NMI_CTL[%s] + CM0+ NMI control + 0x1140 + 32 + read-write + 0x3FF + 0x3FF + + + SYSTEM_INT_IDX + System interrupt select for CPU NMI. The reset value ('1023') ensures that the CPU NMI is NOT connected to any system interrupt after DeepSleep reset. + [9:0] + read-write + + + + + CM4_PWR_CTL + CM4 power control + 0x1200 + 32 + read-write + 0xFA050001 + 0xFFFF0003 + + + PWR_MODE + Power mode. + [1:0] + read-write + + + OFF + Switch CM4 off +Power off, clock off, isolate, reset and no retain. + 0 + + + RESET + Reset CM4 +Clock off, no isolated, no retain and reset. + +Note: The CM4 CPU has a AIRCR.SYSRESETREQ register field that allows the CM4 to reset the complete device (RESET only resets the CM4), resulting in a warm boot. + 1 + + + RETAINED + Put CM4 in Retained mode +This can only become effective if CM4 is in SleepDeep mode. Check PWR_DONE flag to see if CM4 RETAINED state has been reached. +Power off, clock off, isolate, no reset and retain. + 2 + + + ENABLED + Switch CM4 on. +Power on, clock on, no isolate, no reset and no retain. + 3 + + + + + VECTKEYSTAT + Register key (to prevent accidental writes). +- Should be written with a 0x05fa key value for the write to take effect. +- Always reads as 0xfa05. + [31:16] + read-only + + + + + CM4_PWR_DELAY_CTL + CM4 power control + 0x1204 + 32 + read-write + 0x12C + 0x3FF + + + UP + Number clock cycles delay needed after power domain power up + [9:0] + read-write + + + + + RAM0_CTL0 + RAM 0 control + 0x1300 + 32 + read-write + 0x30001 + 0x70303 + + + SLOW_WS + Memory wait states for the slow clock domain ('clk_slow'). The number of wait states is expressed in 'clk_hf' clock domain cycles. + [1:0] + read-write + + + FAST_WS + Memory wait states for the fast clock domain ('clk_fast'). The number of wait states is expressed in 'clk_hf' clock domain cycles. + [9:8] + read-write + + + ECC_EN + Enable ECC checking: +'0': Disabled. +'1': Enabled. + [16:16] + read-write + + + ECC_AUTO_CORRECT + HW ECC autocorrect functionality: +'0': Disabled. +'1': Enabled. HW automatically writes back SRAM with corrected data when a recoverable ECC error is detected. + [17:17] + read-write + + + ECC_INJ_EN + Enable error injection for system SRAM 0. +When '1', the parity (ECC_CTL.PARITY) is used when a full 32-bit write is done to the ECC_CTL.WORD_ADDR word address of system SRAM 0. + [18:18] + read-write + + + + + RAM0_STATUS + RAM 0 status + 0x1304 + 32 + read-only + 0x1 + 0x1 + + + WB_EMPTY + Write buffer empty. This information is used when entering DeepSleep power mode: WB_EMPTY must be '1' before a transition to system DeepSleep power mode. +'0': Write buffer NOT empty. +'1': Write buffer empty. + +Note: the SRAM controller write buffer is only used when ECC checking is enabled. (RAMi_CTL.ECC_EN is '1'). + [0:0] + read-only + + + + + 16 + 4 + RAM0_PWR_MACRO_CTL[%s] + RAM 0 power control + 0x1340 + 32 + read-write + 0xFA050003 + 0xFFFF0003 + + + PWR_MODE + SRAM Power mode. + [1:0] + read-write + + + OFF + Turn OFF the SRAM. This will trun OFF both array and periphery power of the SRAM and SRAM memory contents are lost. + 0 + + + RSVD + undefined + 1 + + + RETAINED + Keep SRAM in Retained mode. This will turn OFF the SRAM periphery power, but array power is ON to retain memory contents. +The SRAM contents will be retained in DeepSleep system power mode. + 2 + + + ENABLED + Enable SRAM for regular operation. +The SRAM contents will be retained in DeepSleep system power mode. + 3 + + + + + VECTKEYSTAT + Register key (to prevent accidental writes). +- Should be written with a 0x05fa key value for the write to take effect. +- Always reads as 0xfa05. + [31:16] + read-only + + + + + RAM1_CTL0 + RAM 1 control + 0x1380 + 32 + read-write + 0x30001 + 0x70303 + + + SLOW_WS + See RAM0_CTL. + [1:0] + read-write + + + FAST_WS + See RAM0_CTL. + [9:8] + read-write + + + ECC_EN + See RAM0_CTL. + [16:16] + read-write + + + ECC_AUTO_CORRECT + See RAM0_CTL. + [17:17] + read-write + + + ECC_INJ_EN + See RAM0_CTL. + [18:18] + read-write + + + + + RAM1_STATUS + RAM 1 status + 0x1384 + 32 + read-only + 0x1 + 0x1 + + + WB_EMPTY + See RAM0_STATUS. + [0:0] + read-only + + + + + RAM1_PWR_CTL + RAM 1 power control + 0x1388 + 32 + read-write + 0xFA050003 + 0xFFFF0003 + + + PWR_MODE + Power mode. + [1:0] + read-write + + + OFF + See RAM0_PWR_MACRO_CTL. + 0 + + + RSVD + undefined + 1 + + + RETAINED + See RAM0_PWR_MACRO_CTL. + 2 + + + ENABLED + See RAM0_PWR_MACRO_CTL. + 3 + + + + + VECTKEYSTAT + See RAM0_PWR_MACRO_CTL. + [31:16] + read-only + + + + + RAM2_CTL0 + RAM 2 control + 0x13A0 + 32 + read-write + 0x30001 + 0x70303 + + + SLOW_WS + See RAM0_CTL. + [1:0] + read-write + + + FAST_WS + See RAM0_CTL. + [9:8] + read-write + + + ECC_EN + See RAM0_CTL. + [16:16] + read-write + + + ECC_AUTO_CORRECT + See RAM0_CTL. + [17:17] + read-write + + + ECC_INJ_EN + See RAM0_CTL. + [18:18] + read-write + + + + + RAM2_STATUS + RAM 2 status + 0x13A4 + 32 + read-only + 0x1 + 0x1 + + + WB_EMPTY + See RAM0_STATUS. + [0:0] + read-only + + + + + RAM2_PWR_CTL + RAM 2 power control + 0x13A8 + 32 + read-write + 0xFA050003 + 0xFFFF0003 + + + PWR_MODE + Power mode. + [1:0] + read-write + + + OFF + See RAM0_PWR_MACRO_CTL. + 0 + + + RSVD + undefined + 1 + + + RETAINED + See RAM0_PWR_MACRO_CTL. + 2 + + + ENABLED + See RAM0_PWR_MACRO_CTL. + 3 + + + + + VECTKEYSTAT + See RAM0_PWR_MACRO_CTL. + [31:16] + read-only + + + + + RAM_PWR_DELAY_CTL + Power up delay used for all SRAM power domains + 0x13C0 + 32 + read-write + 0x96 + 0x3FF + + + UP + Number clock cycles delay needed after power domain power up + [9:0] + read-write + + + + + ROM_CTL + ROM control + 0x13C4 + 32 + read-write + 0x1 + 0x303 + + + SLOW_WS + Memory wait states for the slow clock domain ('clk_slow'). The number of wait states is expressed in 'clk_hf' clock domain cycles. + +Timing paths to and from the memory have a (fixed) minimum duration that always needs to be considered/met. The 'clk_hf' clock domain frequency determines this field's value such that the timing paths minimum duration is met. A table/formula will be provided for this field's values for different 'clk_hf' frequencies. + [1:0] + read-write + + + FAST_WS + Memory wait states for the fast clock domain ('clk_fast'). The number of wait states is expressed in 'clk_hf' clock domain cycles. + [9:8] + read-write + + + + + ECC_CTL + ECC control + 0x13C8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + WORD_ADDR + Specifies the word address where an error will be injected. +- On a write transfer to this SRAM address and when the corresponding RAM0/RAM1/RAM2/CM0/CM4_PWR_CTL_CTL.ECC_INJ_EN bit is '1', the parity (PARITY) is injected. + [24:0] + read-write + + + PARITY + ECC parity to use for ECC error injection at address WORD_ADDR. + [31:25] + read-write + + + + + PRODUCT_ID + Product identifier and version (same as CoreSight RomTables) + 0x1400 + 32 + read-only + 0x0 + 0xFFF + + + FAMILY_ID + Family ID a.k.a. Partnumber a.k.a. Silicon ID + [11:0] + read-only + + + MAJOR_REV + Major Revision, starts with 1, increments with all layer tape-out (implemented with metal ECO-able tie-off) + [19:16] + read-only + + + MINOR_REV + Minor Revision, starts with 1, increments with metal layer only tape-out (implemented with metal ECO-able tie-off) + [23:20] + read-only + + + + + DP_STATUS + Debug port status + 0x1410 + 32 + read-only + 0x4 + 0x7 + + + SWJ_CONNECTED + Specifies if the SWJ debug port is connected; i.e. debug host interface is active: +'0': Not connected/not active. +'1': Connected/active. + [0:0] + read-only + + + SWJ_DEBUG_EN + Specifies if SWJ debug is enabled, i.e. CDBGPWRUPACK is '1' and thus debug clocks are on: +'0': Disabled. +'1': Enabled. + [1:1] + read-only + + + SWJ_JTAG_SEL + Specifies if the JTAG or SWD interface is selected. This signal is valid when DP_CTL.PTM_SEL is '0' (SWJ mode selected) and SWJ_CONNECTED is '1' (SWJ is connected). +'0': SWD selected. +'1': JTAG selected. + [2:2] + read-only + + + + + AP_CTL + Access port control + 0x1414 + 32 + read-write + 0x0 + 0x70007 + + + CM0_ENABLE + Enables the CM0 AP interface: +'0': Disabled. +'1': Enabled. + [0:0] + read-write + + + CM4_ENABLE + Enables the CM4 AP interface: +'0': Disabled. +'1': Enabled. + [1:1] + read-write + + + SYS_ENABLE + Enables the system AP interface: +'0': Disabled. +'1': Enabled. + [2:2] + read-write + + + CM0_DISABLE + Disables the CM0 AP interface: +'0': Enabled. +'1': Disabled. + +Typically, this field is set by the Cypress boot code with information from eFUSE. The access port is only enabled when CM0_DISABLE is '0' and CM0_ENABLE is '1'. + [16:16] + read-write + + + CM4_DISABLE + Disables the CM4 AP interface: +'0': Enabled. +'1': Disabled. + +Typically, this field is set by the Cypress boot code with information from eFUSE. The access port is only enabled when CM4_DISABLE is '0' and CM4_ENABLE is '1'. + [17:17] + read-write + + + SYS_DISABLE + Disables the system AP interface: +'0': Enabled. +'1': Disabled. + +Typically, this field is set by the Cypress boot code with information from eFUSE. The access port is only enabled when SYS_DISABLE is '0' and SYS_ENABLE is '1'. + [18:18] + read-write + + + + + BUFF_CTL + Buffer control + 0x1500 + 32 + read-write + 0x1 + 0x1 + + + WRITE_BUFF + Specifies if write transfer can be buffered in the bus infrastructure bridges: +'0': Write transfers are not buffered, independent of the transfer's bufferable attribute. +'1': Write transfers can be buffered, if the transfer's bufferable attribute indicates that the transfer is a bufferable/posted write. + [0:0] + read-write + + + + + SYSTICK_CTL + SysTick timer control + 0x1600 + 32 + read-write + 0x40000147 + 0xC3FFFFFF + + + TENMS + Specifies the number of clock source cycles (minus 1) that make up 10 ms. E.g., for a 32,768 Hz reference clock, TENMS is 328 - 1 = 327. + [23:0] + read-write + + + CLOCK_SOURCE + Specifies an external clock source: +'0': The low frequency clock 'clk_lf' is selected. The precision of this clock depends on whether the low frequency clock source is a SRSS internal RC oscillator (imprecise) or a device external crystal oscillator (precise). +'1': The internal main oscillator (IMO) clock 'clk_imo' is selected. The MXS40 platform uses a fixed frequency IMO clock. +o '2': The external crystal oscillator (ECO) clock 'clk_eco' is selected. +'3': The SRSS 'clk_timer' is selected ('clk_timer' is a divided/gated version of 'clk_hf' or 'clk_imo'). + +Note: If NOREF is '1', the CLOCK_SOURCE value is NOT used. +Note: It is SW's responsibility to provide the correct NOREF, SKEW and TENMS field values for the selected clock source. + [25:24] + read-write + + + SKEW + Specifies the precision of the clock source and if the TENMS field represents exactly 10 ms (clock source frequency is a multiple of 100 Hz). This affects the suitability of the SysTick timer as a SW real-time clock: +'0': Precise. +'1': Imprecise. + [30:30] + read-write + + + NOREF + Specifies if an external clock source is provided: +'0': An external clock source is provided. +'1': An external clock source is NOT provided and only the CPU internal clock can be used as SysTick timer clock source. + [31:31] + read-write + + + + + MBIST_STAT + Memory BIST status + 0x1704 + 32 + read-only + 0x0 + 0x3 + + + SFP_READY + Flag indicating the BIST run is done. Note that after starting a BIST run this flag must be set before a new run can be started. For the first BIST run this will be 0. + [0:0] + read-only + + + SFP_FAIL + Report status of the BIST run, only valid if SFP_READY=1 + [1:1] + read-only + + + + + CAL_SUP_SET + Calibration support set and read + 0x1800 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DATA + Read without side effect, write 1 to set + [31:0] + read-write + + + + + CAL_SUP_CLR + Calibration support clear and reset + 0x1804 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DATA + Read side effect: when read all bits are cleared, write 1 to clear a specific bit +Note: no exception for the debug host, it also causes the read side effect + [31:0] + read-write + + + + + CM0_PC_CTL + CM0+ protection context control + 0x2000 + 32 + read-write + 0x0 + 0xF + + + VALID + Valid fields for the protection context handler CM0_PCi_HANDLER registers: +Bit 0: Valid field for CM0_PC0_HANDLER. +Bit 1: Valid field for CM0_PC1_HANDLER. +Bit 2: Valid field for CM0_PC2_HANDLER. +Bit 3: Valid field for CM0_PC3_HANDLER. + [3:0] + read-write + + + + + CM0_PC0_HANDLER + CM0+ protection context 0 handler + 0x2040 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + ADDR + Address of the protection context 0 handler. This field is used to detect entry to Cypress 'trusted' code through an exception/interrupt. + [31:0] + read-write + + + + + CM0_PC1_HANDLER + CM0+ protection context 1 handler + 0x2044 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + ADDR + Address of the protection context 1 handler. + [31:0] + read-write + + + + + CM0_PC2_HANDLER + CM0+ protection context 2 handler + 0x2048 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + ADDR + Address of the protection context 2 handler. + [31:0] + read-write + + + + + CM0_PC3_HANDLER + CM0+ protection context 3 handler + 0x204C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + ADDR + Address of the protection context 3 handler. + [31:0] + read-write + + + + + PROTECTION + Protection status + 0x20C4 + 32 + read-write + 0x0 + 0x7 + + + STATE + Protection state: +'0': UNKNOWN. +'1': VIRGIN. +'2': NORMAL. +'3': SECURE. +'4': DEAD. + +The following state transitions are allowed (and enforced by HW): +- UNKNOWN => VIRGIN/NORMAL/SECURE/DEAD +- NORMAL => DEAD +- SECURE => DEAD +An attempt to make a NOT allowed state transition will NOT affect this register field. + [2:0] + read-write + + + + + TRIM_ROM_CTL + ROM trim control + 0x2100 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + TRIM + N/A + [31:0] + read-write + + + + + TRIM_RAM_CTL + RAM trim control + 0x2104 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + TRIM + N/A + [31:0] + read-write + + + + + 1023 + 4 + CM0_SYSTEM_INT_CTL[%s] + CM0+ system interrupt control + 0x8000 + 32 + read-write + 0x0 + 0x80000000 + + + CPU_INT_IDX + CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. + +Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. + [2:0] + read-write + + + CPU_INT_VALID + Interrupt enable: +'0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. +'1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. + +Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. + [31:31] + read-write + + + + + 1023 + 4 + CM4_SYSTEM_INT_CTL[%s] + CM4 system interrupt control + 0xA000 + 32 + read-write + 0x0 + 0x80000000 + + + CPU_INT_IDX + N/A + [2:0] + read-write + + + CPU_INT_VALID + N/A + [31:31] + read-write + + + + + + + FAULT + Fault structures + 0x40210000 + + 0 + 65536 + registers + + + + 2 + 256 + STRUCT[%s] + Fault structure + 0x00000000 + + CTL + Fault control + 0x0 + 32 + read-write + 0x0 + 0x7 + + + TR_EN + Trigger output enable: +'0': Disabled. The trigger output 'tr_fault' is '0'. +'1': Enabled. The trigger output 'tr_fault' reflects STATUS.VALID. The trigger can be used to initiate a Datawire transfer of the FAULT data (FAULT_DATA0 through FAULT_DATA3). + [0:0] + read-write + + + OUT_EN + IO output signal enable: +'0': Disabled. The IO output signal 'fault_out' is '0'. The IO output enable signal 'fault_out_en' is '0'. +'1': Enabled. The IO output signal 'fault_out' reflects STATUS.VALID. The IO output enable signal 'fault_out_en' is '1'. + [1:1] + read-write + + + RESET_REQ_EN + Reset request enable: +'0': Disabled. +'1': Enabled. The output reset request signal 'fault_reset_req' reflects STATUS.VALID. This reset causes a warm/soft/core reset. This warm/soft/core reset does not affect the fault logic STATUS, DATA0, ..., DATA3 registers (allowing for post soft reset failure analysis). + +The 'fault_reset_req' signals of the individual fault report structures are combined (logically OR'd) into a single SRSS 'fault_reset_req' signal. + [2:2] + read-write + + + + + STATUS + Fault status + 0xC + 32 + read-write + 0x0 + 0x80000000 + + + IDX + The fault source index for which fault information is captured in DATA0 through DATA3. The fault information is fault source specific and described below. + +Note: this register field (and associated fault source data in DATA0 through DATA3) should only be considered valid, when VALID is '1'. + [6:0] + read-write + + + VALID + Valid indication: +'0': Invalid. +'1': Valid. STATUS.IDX, DATA0, ..., DATA3 specify the fault. + +Note: Typically, HW sets this field to '1' (on an activated HW fault source that is 'enabled' by the MASK registers) and SW clears this field to '0' (typically by boot code SW (after a warm system reset, when the fault is handled). In this typical use case scenario, the HW source fault data is simultaneously captured into DATA0, ..., DATA3 when the VALID field is set to '1'. + +An exceptional SW use case scenario is identified as well. In this scenario, SW sets this field to '1' with a fault source index different to one of the defined HW fault sources. SW update is not restricted by the MASK registers). In both use case scenarios, the following holds: +- STATUS.IDX, DATA0, ..., DATA3 can only be written when STATUS.VALID is '0'; the fault structure is not in use yet. Writing STATUS.VALID to '1' effectively locks the fault structure (until SW clears STATUS.VALID to '0'). This restriction requires a SW update to sequentially update the DATA registers followed by an update of the STATUS register. + +Note: For the exceptional SW use case, sequential updates to the DATA and STATUS registers may be 'interrupted' by a HW fault capture. In this case, the SW DATA register updates are overwritten by the HW update (and the STATUS.IDX field will reflect the HW capture) + [31:31] + read-write + + + + + 4 + 4 + DATA[%s] + Fault data + 0x10 + 32 + read-write + 0x0 + 0x0 + + + DATA + Captured fault source data. + +Note: the DATA registers can only be written when STATUS.VALID is '0'. + +Note: the fault source index STATUS.IDX specifies the format of the DATA registers. + [31:0] + read-write + + + + + PENDING0 + Fault pending 0 + 0x40 + 32 + read-only + 0x0 + 0x0 + + + SOURCE + This field specifies the following sources: +Bit 0: CM0 MPU. +Bit 1: CRYPTO MPU. +Bit 2: DW 0 MPU. +Bit 3: DW 1 MPU. +Bit 4: DMA controller MPU. +... +Bit 15: DAP MPU. +Bit 16: CM4 system bus MPU. +Bit 17: CM4 code bus MPU (for non FLASH controller accesses). +Bit 18: CM4 code bus MPU (for FLASH controller accesses). + [31:0] + read-only + + + + + PENDING1 + Fault pending 1 + 0x44 + 32 + read-only + 0x0 + 0x0 + + + SOURCE + This field specifies the following sources: +Bit 0: Peripheral group 0 PPU. +Bit 1: Peripheral group 1 PPU. +Bit 2: Peripheral group 2 PPU. +Bit 3: Peripheral group 3 PPU. +Bit 4: Peripheral group 4 PPU. +Bit 5: Peripheral group 5 PPU. +Bit 6: Peripheral group 6 PPU. +Bit 7: Peripheral group 7 PPU. +... +Bit 15: Peripheral group 15 PPU. + +Bit 16 - 31: See STATUS register. + [31:0] + read-only + + + + + PENDING2 + Fault pending 2 + 0x48 + 32 + read-only + 0x0 + 0x0 + + + SOURCE + This field specifies the following sources: +Bit 0 - 31: See STATUS register. + [31:0] + read-only + + + + + MASK0 + Fault mask 0 + 0x50 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SOURCE + Fault source enables: +Bits 31-0: Fault sources 31 to 0. + [31:0] + read-write + + + + + MASK1 + Fault mask 1 + 0x54 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SOURCE + Fault source enables: +Bits 31-0: Fault sources 63 to 32. + [31:0] + read-write + + + + + MASK2 + Fault mask 2 + 0x58 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SOURCE + Fault source enables: +Bits 31-0: Fault sources 95 to 64. + [31:0] + read-write + + + + + INTR + Interrupt + 0xC0 + 32 + read-write + 0x0 + 0x1 + + + FAULT + This interrupt cause field is activated (HW sets the field to '1') when an enabled (MASK0/MASK1/MASK2) pending fault source is captured: +- STATUS.VALID is set to '1'. +- STATUS.IDX specifies the fault source index. +- DATA0 through DATA3 captures the fault source data. + +SW writes a '1' to this field to clear the interrupt cause to '0'. SW clear STATUS.VALID to '0' to enable capture of the next fault. Note that when there is an enabled pending fault source, the pending fault source is captured immediately and INTR.FAULT is immediately activated (set to '1'). + [0:0] + read-write + + + + + INTR_SET + Interrupt set + 0xC4 + 32 + read-write + 0x0 + 0x1 + + + FAULT + SW writes a '1' to this field to set the corresponding field in the INTR register. + [0:0] + read-write + + + + + INTR_MASK + Interrupt mask + 0xC8 + 32 + read-write + 0x0 + 0x1 + + + FAULT + Mask bit for corresponding field in the INTR register. + [0:0] + read-write + + + + + INTR_MASKED + Interrupt masked + 0xCC + 32 + read-only + 0x0 + 0x1 + + + FAULT + Logical and of corresponding INTR and INTR_MASK fields. + [0:0] + read-only + + + + + + + + IPC + IPC + 0x40220000 + + 0 + 65536 + registers + + + + 16 + 32 + STRUCT[%s] + IPC structure + 0x00000000 + + ACQUIRE + IPC acquire + 0x0 + 32 + read-only + 0x0 + 0x80000000 + + + P + User/privileged access control: +'0': user mode. +'1': privileged mode. + +This field is set with the user/privileged access control of the access that successfully acquired the lock. + [0:0] + read-only + + + NS + Secure/non-secure access control: +'0': secure. +'1': non-secure. + +This field is set with the secure/non-secure access control of the access that successfully acquired the lock. + [1:1] + read-only + + + PC + This field specifies the protection context that successfully acquired the lock. + [7:4] + read-only + + + MS + This field specifies the bus master identifier that successfully acquired the lock. + [11:8] + read-only + + + SUCCESS + Specifies if the lock is successfully acquired or not (reading the ACQUIRE register can have affect on SUCCESS and LOCK_STATUS.ACQUIRED): +'0': Not successfully acquired; i.e. the lock was already acquired by another read transaction and not released. The P, NS, PC and MS fields reflect the access attributes of the transaction that previously successfully acuired the lock; the fields are NOT affected by the current access. +'1': Successfully acquired. The P, NS, PC and MS fields reflect the access attributes of the current access. + +Note that this field is NOT SW writable. A lock is released by writing to the associated RELEASE register (irrespective of the write value). + [31:31] + read-only + + + + + RELEASE + IPC release + 0x4 + 32 + write-only + 0x0 + 0xFFFF + + + INTR_RELEASE + Writing this field releases a lock and allows for the generation of release events to the IPC interrupt structures, but only when the lock is acquired (LOCK_STATUS.ACQUIRED is '1'). The IPC release cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_RELEASE[] is set to '1'. + +SW writes a '1' to the bit fields to generate a release event. Due to the transient nature of this event, SW always reads a '0' from this field. + [15:0] + write-only + + + + + NOTIFY + IPC notification + 0x8 + 32 + write-only + 0x0 + 0xFFFF + + + INTR_NOTIFY + This field allows for the generation of notification events to the IPC interrupt structures. The IPC notification cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_NOTIFY[] is set to '1'. + +SW writes a '1' to the bit fields to generate a notify event. Due to the transient nature of this event, SW always reads a '0' from this field. + [15:0] + write-only + + + + + DATA0 + IPC data 0 + 0xC + 32 + read-write + 0x0 + 0x0 + + + DATA + This field holds a 32-bit data element that is associated with the IPC structure. + [31:0] + read-write + + + + + DATA1 + IPC data 1 + 0x10 + 32 + read-write + 0x0 + 0x0 + + + DATA + This field holds a 32-bit data element that is associated with the IPC structure. + [31:0] + read-write + + + + + LOCK_STATUS + IPC lock status + 0x1C + 32 + read-only + 0x0 + 0x80000000 + + + P + This field specifies the user/privileged access control: +'0': user mode. +'1': privileged mode. + [0:0] + read-only + + + NS + This field specifies the secure/non-secure access control: +'0': secure. +'1': non-secure. + [1:1] + read-only + + + PC + This field specifies the protection context that successfully acquired the lock. + [7:4] + read-only + + + MS + This field specifies the bus master identifier that successfully acquired the lock. + [11:8] + read-only + + + ACQUIRED + Specifies if the lock is acquired. This field is set to '1', if a ACQUIRE read transfer successfully acquires the lock (the ACQUIRE read transfer returns ACQUIRE.SUCCESS as '1'). If zero, P, NS, PC, and MS are not valid. + [31:31] + read-only + + + + + + 16 + 32 + INTR_STRUCT[%s] + IPC interrupt structure + 0x00001000 + + INTR + Interrupt + 0x0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + RELEASE + These interrupt cause fields are activated (HW sets the field to '1') when a IPC release event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause. + [15:0] + read-write + + + NOTIFY + These interrupt cause fields are activated (HW sets the field to '1') when a IPC notification event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause. + [31:16] + read-write + + + + + INTR_SET + Interrupt set + 0x4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + RELEASE + SW writes a '1' to this field to set the corresponding field in the INTR register. + [15:0] + read-write + + + NOTIFY + SW writes a '1' to this field to set the corresponding field in the INTR register. + [31:16] + read-write + + + + + INTR_MASK + Interrupt mask + 0x8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + RELEASE + Mask bit for corresponding field in the INTR register. + [15:0] + read-write + + + NOTIFY + Mask bit for corresponding field in the INTR register. + [31:16] + read-write + + + + + INTR_MASKED + Interrupt masked + 0xC + 32 + read-only + 0x0 + 0xFFFFFFFF + + + RELEASE + Logical and of corresponding request and mask bits. + [15:0] + read-only + + + NOTIFY + Logical and of corresponding INTR and INTR_MASK fields. + [31:16] + read-only + + + + + + + + PROT + Protection + 0x40230000 + + 0 + 65536 + registers + + + + SMPU + SMPU + 0x00000000 + + MS0_CTL + Master 0 protection context control + 0x0 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + Privileged setting ('0': user mode; '1': privileged mode). + +Notes: +This field is ONLY used for masters that do NOT provide their own user/privileged access control attribute. +The default/reset field value provides privileged mode access capabilities. + [0:0] + read-write + + + NS + Security setting ('0': secure mode; '1': non-secure mode). + +Notes: +This field is ONLY used for masters that do NOT provide their own secure/non-secure access control attribute. +Note that the default/reset field value provides non-secure mode access capabilities to all masters. + [1:1] + read-write + + + PRIO + Device wide bus arbitration priority setting ('0': highest priority, '3': lowest priority). + +Notes: +The AHB-Lite interconnect performs arbitration on the individual beats/transfers of a burst (this optimizes latency over locality/bandwidth). +The AXI-Lite interconnects performs a single arbitration for the complete burst (this optimizes locality/bandwidth over latency). +Masters with the same priority setting form a 'priority group'. Within a 'priority group', round robin arbitration is performed. + [9:8] + read-write + + + PC_MASK_0 + Protection context mask for protection context '0'. This field is a constant '0': +- PC_MASK_0 is '0': MPU MS_CTL.PC[3:0] can NOT be set to '0' and PC[3:0] is not changed. If the protection context of the write transfer is '0', protection is not applied and PC[3:0] can be changed. + [16:16] + read-only + + + PC_MASK_15_TO_1 + Protection context mask for protection contexts '15' down to '1'. Bit PC_MASK_15_TO_1[i] indicates if the MPU MS_CTL.PC[3:0] protection context field can be set to the value 'i+1': +- PC_MASK_15_TO_1[i] is '0': MPU MS_CTL.PC[3:0] can NOT be set to 'i+1'; and PC[3:0] is not changed. If the protection context of the write transfer is '0', protection is not applied and PC[3:0] can be changed. +- PC_MASK_15_TO_1[i] is '1': MPU MS_CTL.PC[3:0] can be set to 'i+1'. + +Note: When CPUSS_CM0_PC_CTL.VALID[i] is '1' (the associated protection context handler is valid), write transfers to PC_MASK_15_TO_1[i-1] always write '0', regardless of data written. This ensures that when valid protection context handlers are used to enter protection contexts 1, 2 or 3 through (HW modifies MPU MS_CTL.PC[3:0] on entry of the handler), it is NOT possible for SW to enter those protection contexts (SW modifies MPU MS_CTL.PC[3:0]). + [31:17] + read-write + + + + + MS1_CTL + Master 1 protection context control + 0x4 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS2_CTL + Master 2 protection context control + 0x8 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS3_CTL + Master 3 protection context control + 0xC + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS4_CTL + Master 4 protection context control + 0x10 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS5_CTL + Master 5 protection context control + 0x14 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS6_CTL + Master 6 protection context control + 0x18 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS7_CTL + Master 7 protection context control + 0x1C + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS8_CTL + Master 8 protection context control + 0x20 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS9_CTL + Master 9 protection context control + 0x24 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS10_CTL + Master 10 protection context control + 0x28 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS11_CTL + Master 11 protection context control + 0x2C + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS12_CTL + Master 12 protection context control + 0x30 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS13_CTL + Master 13 protection context control + 0x34 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS14_CTL + Master 14 protection context control + 0x38 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS15_CTL + Master 15 protection context control + 0x3C + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + 16 + 64 + SMPU_STRUCT[%s] + SMPU structure + 0x00002000 + + ADDR0 + SMPU region address 0 (slave structure) + 0x0 + 32 + read-write + 0x0 + 0x0 + + + SUBREGION_DISABLE + This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: +Bit 0: subregion 0 disable. +Bit 1: subregion 1 disable. +Bit 2: subregion 2 disable. +Bit 3: subregion 3 disable. +Bit 4: subregion 4 disable. +Bit 5: subregion 5 disable. +Bit 6: subregion 6 disable. +Bit 7: subregion 7 disable. +E.g., a 64 KByte address region (ATT0.REGION_SIZE is '15') has eight 8 KByte subregions. The access control as defined by ATT0 applies if the bus transfer address is within the address region AND the addressed subregion is NOT disabled. Note that the smallest region size is 256 B and the smallest subregion size is 32 B. + [7:0] + read-write + + + ADDR24 + This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by ATT0.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result, some of the lesser significant address bits of ADDR24 may be ignored in determining whether a bus transfer address is within an address region. E.g., a 64 KByte address region (REGION_SIZE is '15') is 64 KByte aligned, and ADDR24[7:0] are ignored. + [31:8] + read-write + + + + + ATT0 + SMPU region attributes 0 (slave structure) + 0x4 + 32 + read-write + 0x100 + 0x80000100 + + + UR + User read enable: +'0': Disabled (user, read accesses are NOT allowed). +'1': Enabled (user, read accesses are allowed). + [0:0] + read-write + + + UW + User write enable: +'0': Disabled (user, write accesses are NOT allowed). +'1': Enabled (user, write accesses are allowed). + [1:1] + read-write + + + UX + User execute enable: +'0': Disabled (user, execute accesses are NOT allowed). +'1': Enabled (user, execute accesses are allowed). + [2:2] + read-write + + + PR + Privileged read enable: +'0': Disabled (privileged, read accesses are NOT allowed). +'1': Enabled (privileged, read accesses are allowed). + [3:3] + read-write + + + PW + Privileged write enable: +'0': Disabled (privileged, write accesses are NOT allowed). +'1': Enabled (privileged, write accesses are allowed). + [4:4] + read-write + + + PX + Privileged execute enable: +'0': Disabled (privileged, execute accesses are NOT allowed). +'1': Enabled (privileged, execute accesses are allowed). + [5:5] + read-write + + + NS + Non-secure: +'0': Secure (secure accesses allowed, non-secure access NOT allowed). +'1': Non-secure (both secure and non-secure accesses allowed). + [6:6] + read-write + + + PC_MASK_0 + This field specifies protection context identifier based access control for protection context '0'. + [8:8] + read-only + + + PC_MASK_15_TO_1 + This field specifies protection context identifier based access control. +Bit i: protection context i+1 enable. If '0', protection context i+1 access is disabled; i.e. not allowed. If '1', protection context i+1 access is enabled; i.e. allowed. + [23:9] + read-write + + + REGION_SIZE + This field specifies the region size: +'0'-'6': Undefined. +'7': 256 B region +'8': 512 B region +'9': 1 KB region +'10': 2 KB region +'11': 4 KB region +'12': 8 KB region +'13': 16 KB region +'14': 32 KB region +'15': 64 KB region +'16': 128 KB region +'17': 256 KB region +'18': 512 KB region +'19': 1 MB region +'20': 2 MB region +'21': 4 MB region +'22': 8 MB region +'23': 16 MB region +'24': 32 MB region +'25': 64 MB region +'26': 128 MB region +'27': 256 MB region +'28': 512 MB region +'39': 1 GB region +'30': 2 GB region +'31': 4 GB region + [28:24] + read-write + + + PC_MATCH + This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process: +'0': PC field participates in 'access evaluation'. +'1': PC field participates in 'matching'. + +'Matching' process. For each protection structure, the process identifies if a transfer address is contained within the address range. This identifies the 'matching' regions. +'Access evaluation' process. For each protection structure, the process evaluates the bus transfer access attributes against the access control attributes. + +Note that it is possible to define different access control for multiple protection contexts by using multiple protection structures with the same address region and PC_MATCH set to '1'. + [30:30] + read-write + + + ENABLED + Region enable: +'0': Disabled. A disabled region will never result in a match on the bus transfer address. +'1': Enabled. + +Note: a disabled address region performs logic gating to reduce dynamic power consumption. + [31:31] + read-write + + + + + ADDR1 + SMPU region address 1 (master structure) + 0x20 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + SUBREGION_DISABLE + This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: +Bit 0: subregion 0 disable. +Bit 1: subregion 1 disable. +Bit 2: subregion 2 disable. +Bit 3: subregion 3 disable. +Bit 4: subregion 4 disable. +Bit 5: subregion 5 disable. +Bit 6: subregion 6 disable. +Bit 7: subregion 7 disable. + +Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1. + +Note: this field is read-only. + [7:0] + read-only + + + ADDR24 + This field specifies the most significant bits of the 32-bit address of an address region. + +'ADDR_DEF1': base address of structure. + +Note: this field is read-only. + [31:8] + read-only + + + + + ATT1 + SMPU region attributes 1 (master structure) + 0x24 + 32 + read-write + 0x7000109 + 0x9F00012D + + + UR + User read enable: +'0': Disabled (user, read accesses are NOT allowed). +'1': Enabled (user, read accesses are allowed). + +Note that this register is constant '1'; i.e. user read accesses are ALWAYS allowed. + [0:0] + read-only + + + UW + User write enable: +'0': Disabled (user, write accesses are NOT allowed). +'1': Enabled (user, write accesses are allowed). + [1:1] + read-write + + + UX + User execute enable: +'0': Disabled (user, execute accesses are NOT allowed). +'1': Enabled (user, execute accesses are allowed). + +Note that this register is constant '0'; i.e. user execute accesses are NEVER allowed. + [2:2] + read-only + + + PR + Privileged read enable: +'0': Disabled (privileged, read accesses are NOT allowed). +'1': Enabled (privileged, read accesses are allowed). + +Note that this register is constant '1'; i.e. privileged read accesses are ALWAYS allowed. + [3:3] + read-only + + + PW + Privileged write enable: +'0': Disabled (privileged, write accesses are NOT allowed). +'1': Enabled (privileged, write accesses are allowed). + [4:4] + read-write + + + PX + Privileged execute enable: +'0': Disabled (privileged, execute accesses are NOT allowed). +'1': Enabled (privileged, execute accesses are allowed). + +Note that this register is constant '0'; i.e. privileged execute accesses are NEVER allowed. + [5:5] + read-only + + + NS + Non-secure: +'0': Secure (secure accesses allowed, non-secure access NOT allowed). +'1': Non-secure (both secure and non-secure accesses allowed). + [6:6] + read-write + + + PC_MASK_0 + This field specifies protection context identifier based access control for protection context '0'. + [8:8] + read-only + + + PC_MASK_15_TO_1 + This field specifies protection context identifier based access control. +Bit i: protection context i+1 enable. If '0', protection context i+1 access is disabled; i.e. not allowed. If '1', protection context i+1 access is enabled; i.e. allowed. + [23:9] + read-write + + + REGION_SIZE + This field specifies the region size: +'7': 256 B region (8 32 B subregions) + +Note: this field is read-only. + [28:24] + read-only + + + PC_MATCH + This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process: +'0': PC field participates in 'access evaluation'. +'1': PC field participates in 'matching'. + +'Matching' process. For each protection structure, the process identifies if a transfer address is contained within the address range. This identifies the 'matching' regions. +'Access evaluation' process. For each protection structure, the process evaluates the bus transfer access attributes against the access control attributes. + +Note that it is possible to define different access control for multiple protection contexts by using multiple protection structures with the same address region and PC_MATCH set to '1'. + [30:30] + read-write + + + ENABLED + Region enable: +'0': Disabled. A disabled region will never result in a match on the bus transfer address. +'1': Enabled. + [31:31] + read-write + + + + + + + 16 + 1024 + MPU[%s] + MPU + 0x00004000 + + MS_CTL + Master control + 0x0 + 32 + read-write + 0x0 + 0xF000F + + + PC + Active protection context (PC). Modifications to this field are constrained by the associated SMPU MS_CTL.PC_MASK_0 and MS_CTL.PC_MASK_15_TO_1[] fields. In addition, a write transfer with protection context '0' can change this field (protection context 0 has unrestricted access). + +The CM0+ MPU MS_CTL register is special: the PC field is modifiable by BOTH HW and SW (for all other masters, the MPU MS_CTL.PC field is modifiable by SW ONLY. For CM0+ PC field HW modifications, the following holds: +* On entry of a CM0_PC0/1/2/3_HANDLER exception/interrupt handler: + IF (the new PC is the same as MS_CTL.PC) + PC is not affected; PC_SAVED is not affected. + ELSE IF (CM0_PC_CTL.VALID[MS_CTL.PC]) + An AHB-Lite bus error is generated for the exception handler fetch; + PC is not affected; PC_SAVED is not affected. + ELSE + PC = 'new PC'; PC_SAVED = PC (push operation). +* On entry of any other exception/interrupt handler: + PC = PC_SAVED; PC_SAVED is not affected (pop operation). + +Note that the CM0_PC0/1/2/3_HANDLER and CM0_PC_CTL registers are part of repecitve CPUSS MMIO registers. + +Note: this field is NOT used by the DW controllers, DMA controller and CRYPTO component. + [3:0] + read-write + + + PC_SAVED + Saved protection context. Modifications to this field are constrained by the associated SMPU MS_CTL.PC_MASK_0 and MS_CTL.PC_MASK_15_TO_1[] fields. + +Note: this field is ONLY used by the CM0+. + [19:16] + read-write + + + + + 127 + 4 + MS_CTL_READ_MIR[%s] + Master control read mirror + 0x4 + 32 + read-only + 0x0 + 0xF000F + + + PC + Read-only mirror of MS_CTL.PC + [3:0] + read-only + + + PC_SAVED + Read-only mirror of MS_CTL.PC_SAVED + [19:16] + read-only + + + + + 8 + 32 + MPU_STRUCT[%s] + MPU structure + 0x00000200 + + ADDR + MPU region address + 0x0 + 32 + read-write + 0x0 + 0x0 + + + SUBREGION_DISABLE + This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: +Bit 0: subregion 0 disable. +Bit 1: subregion 1 disable. +Bit 2: subregion 2 disable. +Bit 3: subregion 3 disable. +Bit 4: subregion 4 disable. +Bit 5: subregion 5 disable. +Bit 6: subregion 6 disable. +Bit 7: subregion 7 disable. +E.g., a 64 KByte address region (REGION_SIZE is '15') has eight 8 KByte subregions. The access control as defined by MPU_REGION_ATT applies if the bus transfer address is within the address region AND the addressed subregion is NOT disabled. Note that the smallest region size is 256 B and the smallest subregion size is 32 B. + [7:0] + read-write + + + ADDR24 + This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by ATT.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result, some of the lesser significant address bits of ADDR24 may be ignored in determining whether a bus transfer address is within an address region. E.g., a 64 KByte address region (REGION_SIZE is '15') is 64 KByte aligned, and ADDR24[7:0] are ignored. + [31:8] + read-write + + + + + ATT + MPU region attrributes + 0x4 + 32 + read-write + 0x0 + 0x80000000 + + + UR + User read enable: +'0': Disabled (user, read accesses are NOT allowed). +'1': Enabled (user, read accesses are allowed). + [0:0] + read-write + + + UW + User write enable: +'0': Disabled (user, write accesses are NOT allowed). +'1': Enabled (user, write accesses are allowed). + [1:1] + read-write + + + UX + User execute enable: +'0': Disabled (user, execute accesses are NOT allowed). +'1': Enabled (user, execute accesses are allowed). + [2:2] + read-write + + + PR + Privileged read enable: +'0': Disabled (privileged, read accesses are NOT allowed). +'1': Enabled (privileged, read accesses are allowed). + [3:3] + read-write + + + PW + Privileged write enable: +'0': Disabled (privileged, write accesses are NOT allowed). +'1': Enabled (privileged, write accesses are allowed). + [4:4] + read-write + + + PX + Privileged execute enable: +'0': Disabled (privileged, execute accesses are NOT allowed). +'1': Enabled (privileged, execute accesses are allowed). + [5:5] + read-write + + + NS + Non-secure: +'0': Secure (secure accesses allowed, non-secure access NOT allowed). +'1': Non-secure (both secure and non-secure accesses allowed). + [6:6] + read-write + + + REGION_SIZE + This field specifies the region size: +'0'-'6': Undefined. +'7': 256 B region +'8': 512 B region +'9': 1 KB region +'10': 2 KB region +'11': 4 KB region +'12': 8 KB region +'13': 16 KB region +'14': 32 KB region +'15': 64 KB region +'16': 128 KB region +'17': 256 KB region +'18': 512 KB region +'19': 1 MB region +'20': 2 MB region +'21': 4 MB region +'22': 8 MB region +'23': 16 MB region +'24': 32 MB region +'25': 64 MB region +'26': 128 MB region +'27': 256 MB region +'28': 512 MB region +'39': 1 GB region +'30': 2 GB region +'31': 4 GB region + [28:24] + read-write + + + ENABLED + Region enable: +'0': Disabled. A disabled region will never result in a match on the bus transfer address. +'1': Enabled. + +Note: a disabled address region performs logic gating to reduce dynamic power consumption. + [31:31] + read-write + + + + + + + + + FLASHC + Flash controller + 0x40240000 + + 0 + 65536 + registers + + + + FLASH_CTL + Control + 0x0 + 32 + read-write + 0x110000 + 0x77330F + + + MAIN_WS + FLASH macro main interface wait states: +'0': 0 wait states. +... +'15': 15 wait states + [3:0] + read-write + + + MAIN_MAP + Specifies mapping of FLASH macro main array. +0: Mapping A. +1: Mapping B. + +This field is only used when MAIN_BANK_MODE is '1' (dual bank mode). + [8:8] + read-write + + + WORK_MAP + Specifies mapping of FLASH macro work array. +0: Mapping A. +1: Mapping B. + +This field is only used when WORK_BANK_MODE is '1' (dual bank mode). + [9:9] + read-write + + + MAIN_BANK_MODE + Specifies bank mode of FLASH macro main array. +0: Single bank mode. +1: Dual bank mode. + [12:12] + read-write + + + WORK_BANK_MODE + Specifies bank mode of FLASH macro work array. +0: Single bank mode. +1: Dual bank mode. + [13:13] + read-write + + + MAIN_ECC_EN + Enable ECC checking for FLASH main interface: +0: Disabled. ECC checking/reporting on FLASH main interface is disabled. No correctable or non-correctable faults are reported. +1: Enabled. + [16:16] + read-write + + + MAIN_ECC_INJ_EN + Enable error injection for FLASH main interface. +When'1', the parity (ECC_CTL.PARITY[7:0]) is used for a load from the ECC_CTL.WORD_ADDR[23:0] word address. + [17:17] + read-write + + + MAIN_ERR_SILENT + Specifies bus transfer behavior for a non-recoverable error on the FLASH macro main interface (either a non-correctable ECC error, a FLASH macro main interface internal error, a FLASH macro main interface memory hole access): +0: Bus transfer has a bus error. +1: Bus transfer does NOT have a bus error; i.e. the error is 'silent' +In either case, the erroneous FLASH macro data is returned by the bus master interface. The erroneous data is NOT placed in a bus master interface's cache and/or buffer. + +This field is ONLY used by CPU bus transfers. Non-CPU bus transfers always have a bus transfer with a bus error, in case of a non-recoverable error. + +Note: All CPU bus masters have dedicated status registers (CM0_STATUS and CM4_STATUS) to register the occurrence of FLASH macro main interface internal errors (non-correctable ECC errors and memory hole errors are NOT registered). + +Note: fault reporting can be used to identify the error that occurred: +- FLASH macro main interface internal error. +- FLASH macro main interface non-recoverable ECC error. +- FLASH macro main interface recoverable ECC error. +- FLASH macro main interface memory hole error. + [18:18] + read-write + + + WORK_ECC_EN + Enable ECC checking for FLASH work interface: +0: Disabled. ECC checking/reporting on FLASH work interface is disabled. No correctable or non-correctable faults are reported. +1: Enabled. + [20:20] + read-write + + + WORK_ECC_INJ_EN + Enable error injection for FLASH work interface. +When'1', the parity (ECC_CTL.PARITY[6:0]) is used for a load from the ECC_CTL.WORD_ADDR[23:0] word address. + [21:21] + read-write + + + WORK_ERR_SILENT + Specifies bus transfer behavior for a non-recoverable error on the FLASH macro work interface (either a non-correctable ECC error, a FLASH macro work interface internal error, a FLASH macro work interface memory hole access): +0: Bus transfer has a bus error. +1: Bus transfer does NOT have a bus error; i.e. the error is 'silent' +In either case, the erroneous FLASH macro data is returned by the bus master interface. The erroneous data is NOT placed in a bus master interface's cache and/or buffer. + +This field is ONLY used by CPU bus transfers. Non-CPU bus transfers always have a bus transfer with a bus error, in case of a non-recoverable error. + +Note: All CPU bus masters have dedicated status registers (CM0_STATUS and CM4_STATUS) to register the occurrence of FLASH macro work interface internal errors (non-correctable ECC errors and memory hole errors are NOT registered). + +Note: fault reporting can be used to identify the error that occurred: +- FLASH macro work interface internal error. +- FLASH macro work interface non-recoverable ECC error. +- FLASH macro work interface recoverable ECC error. +- FLASH macro work interface memory hole error. + [22:22] + read-write + + + + + FLASH_PWR_CTL + Flash power control + 0x4 + 32 + read-write + 0x3 + 0x3 + + + ENABLE + Controls 'enable' pin of the Flash memory. + [0:0] + read-write + + + ENABLE_HV + Controls 'enable_hv' pin of the Flash memory. + [1:1] + read-write + + + + + FLASH_CMD + Command + 0x8 + 32 + read-write + 0x0 + 0x3 + + + INV + Invalidation of ALL caches (for CM0+ and CM4) and ALL buffers. SW writes a '1' to clear the caches. HW sets this field to '0' when the operation is completed. The operation takes a maximum of three clock cycles on the slowest of the clk_slow and clk_fast clocks. The caches' LRU structures are also reset to their default state. + [0:0] + read-write + + + BUFF_INV + Invalidation of ALL buffers (does not invalidate the caches). SW writes a '1' to clear the buffers. HW sets this field to '0' when the operation is completed. The operation takes a maximum of three clock cycles on the slowest of the clk_slow and clk_fast clocks. + +Note: the caches only capture FLASH macro main array data. Therefore, invalidating just the buffers (BUFF_INV) does not invalidate captures main array data in the caches. + [1:1] + read-write + + + + + ECC_CTL + ECC control + 0x2A0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + WORD_ADDR + Specifies the word address where an error will be injected. +- For cache SRAM ECC, the word address WORD_ADDR[23:0] is device address A[25:2]. On a FLASH macro refill to this word address and when the corresponding CM0/4_CA_CTL.RAM_ECC_INJ_EN bit is '1', the parity (PARITY[6:0]) is injected and stored in the cache. +- For FLASH main interface ECC, the word address WORD_ADDR[23:0] is device address A[26:3]. On a FLASH main interface read and when FLASH_CTL.MAIN_ECC_INJ_EN bit is '1', the parity (PARITY[7:0]) replaces the FLASH macro parity (FLASH main interface read path is manipulated). +- For FLASH work interface ECC, the word address WORD_ADDR[23:0] is device address A[24:2]. On a FLASH work interface read and when FLASH_CTL.WORK_ECC_INJ_EN bit is '1', the parity (PARITY[6:0]) replaces the FLASH macro parity (FLASH work interface read path is manipulated). + [23:0] + read-write + + + PARITY + ECC parity to use for ECC error injection at address WORD_ADDR. +- For cache SRAM ECC, the 7-bit parity PARITY[6:0] is for a 32-bit word. +- For FLASH main interface ECC, the 8-bit parity PARITY[7:0] is for a 64-bit word. +- For FLASH work interface ECC, the 7-bit parity PARITY[6:0] is for a 32-bit word. + [31:24] + read-write + + + + + FM_SRAM_ECC_CTL0 + eCT Flash SRAM ECC control 0 + 0x2B0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + ECC_INJ_DATA + 32-bit data for ECC error injection test of eCT Flash SRAM ECC logic. + [31:0] + read-write + + + + + FM_SRAM_ECC_CTL1 + eCT Flash SRAM ECC control 1 + 0x2B4 + 32 + read-write + 0x0 + 0x7F + + + ECC_INJ_PARITY + 7-bit parity for ECC error injection test of eCT Flash SRAM ECC logic. + [6:0] + read-write + + + + + FM_SRAM_ECC_CTL2 + eCT Flash SRAM ECC control 2 + 0x2B8 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + CORRECTED_DATA + 32-bit corrected data output of the ECC syndrome logic. + [31:0] + read-only + + + + + FM_SRAM_ECC_CTL3 + eCT Flash SRAM ECC control 3 + 0x2BC + 32 + read-write + 0x1 + 0x111 + + + ECC_ENABLE + ECC generation/check enable for eCT Flash SRAM memory. + [0:0] + read-write + + + ECC_INJ_EN + eCT Flash SRAM ECC error injection test enable. Follow the steps below for ECC logic test: +1. Write corrupted or uncorrupted 39-bit data to FM_SRAM_ECC_CTL0/1 registers. +2. Set the ECC_INJ_EN bit to '1'. +3. Confirm that the bit ECC_TEST_FAIL is '0'. If this is not the case, start over at item 1 because the eCT Flash was not idle. +4. Check the corrected data in FM_SRAM_ECC_CTL2. +5. Confirm that fault was reported to fault structure, and check syndrome (only applicable if +corrupted data was written in step 1). +6. If not finished, start over at 1 with different data. + [4:4] + read-write + + + ECC_TEST_FAIL + Status of ECC test. +1 : ECC test failed because eCT Flash macro is busy and using the SRAM. +0: ECC was performed. + [8:8] + read-only + + + + + CM0_CA_CTL0 + CM0+ cache control + 0x400 + 32 + read-write + 0xC0000001 + 0xC7030003 + + + RAM_ECC_EN + Enable ECC checking for cache accesses: +0: Disabled. +1: Enabled. + [0:0] + read-write + + + RAM_ECC_INJ_EN + Enable error injection for cache. +When '1', the parity (ECC_CTL.PARITY[6:0]) is used when a refill is done from the FLASH macro to the ECC_CTL.WORD_ADDR[23:0] word address. + [1:1] + read-write + + + WAY + Specifies the cache way for which cache information is provided in CM0_CA_STATUS0/1/2. + [17:16] + read-write + + + SET_ADDR + Specifies the cache set for which cache information is provided in CM0_CA_STATUS0/1/2. + [26:24] + read-write + + + PREF_EN + Prefetch enable: +0: Disabled. +1: Enabled. + +Prefetching requires the cache to be enabled; i.e. ENABLED is '1'. + [30:30] + read-write + + + CA_EN + Cache enable: +0: Disabled. The cache tag valid bits are reset to '0's and the cache LRU information is set to '1's (making way 0 the LRU way and way 3 the MRU way). +1: Enabled. + [31:31] + read-write + + + + + CM0_CA_CTL1 + CM0+ cache control + 0x404 + 32 + read-write + 0xFA050003 + 0xFFFF0003 + + + PWR_MODE + Specifies power mode for CM0 cache. + [1:0] + read-write + + + OFF + See CM4_PWR_CTL + 0 + + + RSVD + Undefined + 1 + + + RETAINED + See CM4_PWR_CTL + 2 + + + ENABLED + See CM4_PWR_CTL + 3 + + + + + VECTKEYSTAT + Register key (to prevent accidental writes). +- Should be written with a 0x05fa key value for the write to take effect. +- Always reads as 0xfa05. + [31:16] + read-only + + + + + CM0_CA_CTL2 + CM0+ cache control + 0x408 + 32 + read-write + 0x12C + 0x3FF + + + PWRUP_DELAY + Number clock cycles delay needed after power domain power up + [9:0] + read-write + + + + + CM0_CA_STATUS0 + CM0+ cache status 0 + 0x440 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + VALID32 + Sixteen valid bits of the cache line specified by CM0_CA_CTL.WAY and CM0_CA_CTL.SET_ADDR. + [31:0] + read-only + + + + + CM0_CA_STATUS1 + CM0+ cache status 1 + 0x444 + 32 + read-only + 0x0 + 0x0 + + + TAG + Cache line address of the cache line specified by CM0_CA_CTL.WAY and CM0_CA_CTL.SET_ADDR. + [31:0] + read-only + + + + + CM0_CA_STATUS2 + CM0+ cache status 2 + 0x448 + 32 + read-only + 0x0 + 0x0 + + + LRU + Six bit LRU representation of the cache set specified by CM0_CA_CTL.SET_ADDR. The encoding of the field is as follows ('X_LRU_Y' indicates that way X is Less Recently Used than way Y): +Bit 5: 0_LRU_1: way 0 less recently used than way 1. +Bit 4: 0_LRU_2. +Bit 3: 0_LRU_3. +Bit 2: 1_LRU_2. +Bit 1: 1_LRU_3. +Bit 0: 2_LRU_3. + [5:0] + read-only + + + + + CM0_STATUS + CM0+ interface status + 0x460 + 32 + read-write + 0x0 + 0x3 + + + MAIN_INTERNAL_ERR + Specifies/registers the occurrence of a FLASH macro main interface internal error (typically the result of a read access while a program erase operation is ongoing) as a result of a CM0+ access. + +SW clears this field to '0'. HW sets this field to '1' on a FLASH macro main interface internal error. Typically, SW reads this field after a code section to detect the occurrence of an error. + +Note: this field is independent of FLASH_CTL.MAIN_ERR_SILENT. + [0:0] + read-write + + + WORK_INTERNAL_ERR + See CM0_STATUS.MAIN_INTERNAL_ERROR. + [1:1] + read-write + + + + + CM4_CA_CTL0 + CM4 cache control + 0x480 + 32 + read-write + 0xC0000001 + 0xC7030003 + + + RAM_ECC_EN + See CM0_CA_CTL. + [0:0] + read-write + + + RAM_ECC_INJ_EN + See CM0_CA_CTL. + [1:1] + read-write + + + WAY + See CM0_CA_CTL. + [17:16] + read-write + + + SET_ADDR + See CM0_CA_CTL. + [26:24] + read-write + + + PREF_EN + See CM0_CA_CTL. + [30:30] + read-write + + + CA_EN + See CM0_CA_CTL. + [31:31] + read-write + + + + + CM4_CA_CTL1 + CM4 cache control + 0x484 + 32 + read-write + 0xFA050003 + 0xFFFF0003 + + + PWR_MODE + Specifies power mode for CM4 cache. + [1:0] + read-write + + + OFF + See CM4_PWR_CTL + 0 + + + RSVD + Undefined + 1 + + + RETAINED + See CM4_PWR_CTL + 2 + + + ENABLED + See CM4_PWR_CTL + 3 + + + + + VECTKEYSTAT + Register key (to prevent accidental writes). +- Should be written with a 0x05fa key value for the write to take effect. +- Always reads as 0xfa05. + [31:16] + read-only + + + + + CM4_CA_CTL2 + CM4 cache control + 0x488 + 32 + read-write + 0x12C + 0x3FF + + + PWRUP_DELAY + Number clock cycles delay needed after power domain power up + [9:0] + read-write + + + + + CM4_CA_STATUS0 + CM4 cache status 0 + 0x4C0 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + VALID32 + See CM0_CA_STATUS0. + [31:0] + read-only + + + + + CM4_CA_STATUS1 + CM4 cache status 1 + 0x4C4 + 32 + read-only + 0x0 + 0x0 + + + TAG + See CM0_CA_STATUS1. + [31:0] + read-only + + + + + CM4_CA_STATUS2 + CM4 cache status 2 + 0x4C8 + 32 + read-only + 0x0 + 0x0 + + + LRU + See CM0_CA_STATUS2. + [5:0] + read-only + + + + + CM4_STATUS + CM4 interface status + 0x4E0 + 32 + read-write + 0x0 + 0x3 + + + MAIN_INTERNAL_ERR + See CM0_STATUS.MAIN_INTERNAL_ERROR. + [0:0] + read-write + + + WORK_INTERNAL_ERR + See CM0_STATUS.MAIN_INTERNAL_ERROR. + [1:1] + read-write + + + + + CRYPTO_BUFF_CTL + Cryptography buffer control + 0x500 + 32 + read-write + 0x40000000 + 0x40000000 + + + PREF_EN + Prefetch enable: +0: Disabled. +1: Enabled. +A prefetch will be done when there is read 'hit' on the last 32-bit word of the buffer. +For eCT work Flash, prefetch will not be done. + [30:30] + read-write + + + + + DW0_BUFF_CTL + Datawire 0 buffer control + 0x580 + 32 + read-write + 0x40000000 + 0x40000000 + + + PREF_EN + See CRYPTO_BUFF_CTL. + [30:30] + read-write + + + + + DW1_BUFF_CTL + Datawire 1 buffer control + 0x600 + 32 + read-write + 0x40000000 + 0x40000000 + + + PREF_EN + See CRYPTO_BUFF_CTL. + [30:30] + read-write + + + + + DMAC_BUFF_CTL + DMA controller buffer control + 0x680 + 32 + read-write + 0x40000000 + 0x40000000 + + + PREF_EN + See CRYPTO_BUFF_CTL. + [30:30] + read-write + + + + + EXT_MS0_BUFF_CTL + External master 0 buffer control + 0x700 + 32 + read-write + 0x40000000 + 0x40000000 + + + PREF_EN + See CRYPTO_BUFF_CTL. + [30:30] + read-write + + + + + EXT_MS1_BUFF_CTL + External master 1 buffer control + 0x780 + 32 + read-write + 0x40000000 + 0x40000000 + + + PREF_EN + See CRYPTO_BUFF_CTL. + [30:30] + read-write + + + + + FM_CTL + Flash Macro Registers + 0x0000F000 + + FM_CTL + Flash macro control + 0x0 + 32 + read-write + 0x0 + 0x37F030F + + + FM_MODE + Requires (IF_SEL|WR_EN)=1 +Flash macro mode selection + [3:0] + read-write + + + FM_SEQ + Requires (IF_SEL|WR_EN)=1 +Flash macro sequence selection + [9:8] + read-write + + + DAA_MUX_SEL + Direct memory cell access address. + [22:16] + read-write + + + IF_SEL + Interface selection. Specifies the interface that is used for flash memory read operations: +0: R interface is used (default value). In this case, the flash memory address is provided as part of the R signal interface. +1: C interface is used. In this case, the flash memory address is provided by FM_MEM_ADDR (the page address) and by the C interface access offset in the FM_MEM_DATA structure. +Note: IF_SEL and WR_EN cannot be changed at the same time + [24:24] + read-write + + + WR_EN + 0: normal mode +1: Fm Write Enable +Note: IF_SEL and WR_EN cannot be changed at the same time + [25:25] + read-write + + + + + STATUS + Status + 0x4 + 32 + read-only + 0x1800 + 0xFFFFFFFF + + + TIMER_ENABLED + This is the timer_en bit set by writing a '1' in the TIMER_CTL bit 31. It is reset by HW when the timer expires +0: timer not running +1: Timer is enabled and not expired yet + [0:0] + read-only + + + HV_REGS_ISOLATED + Indicates the isolation status at HV trim and redundancy registers inputs +0: Not isolated, writing permitted +1: isolated writing disabled + [1:1] + read-only + + + ILLEGAL_HVOP + Indicates a bulk, sector erase, program has been requested when axa=1 +0: no error +1: illegal HV operation error + [2:2] + read-only + + + TURBO_N + After FM power up indicates the analog blocks currents are boosted to faster reach their functional state.. +Used in the testchip boot only as an 'FM READY' flag. +0: turbo mode +1: normal mode + [3:3] + read-only + + + WR_EN_MON + FM_CTL.WR_EN bit after being synchronized in clk_r domain + [4:4] + read-only + + + IF_SEL_MON + FM_CTL.IF_SEL bit after being synchronized in clk_r domain + [5:5] + read-only + + + TIMER_STATUS + The actual timer state sync-ed in clk_c domain: +0: timer is not running: +1: timer is running; + [6:6] + read-only + + + R_GRANT_DELAY_STATUS + 0: R_GRANT_DELAY timer is not running +1: R_GRANT_DELAY timer is running + [7:7] + read-only + + + FM_BUSY + 0': FM not busy +1: FM BUSY : R_GRANT is 0 as result of a busy request from FM ready, or from HV operations. + [8:8] + read-only + + + FM_READY + 0: FM not ready +1: FM ready + [9:9] + read-only + + + POS_PUMP_VLO + POS pump VLO + [10:10] + read-only + + + NEG_PUMP_VHI + NEG pump VHI + [11:11] + read-only + + + RWW + FM Type (Read While Write or Not Read While Write): +0: Non RWW FM Type +1: RWW FM Type + [12:12] + read-only + + + MAX_DOUT_WIDTH + Internal memory core max data out size +(number of data out bits per column): +0: x128 bits +1: x256 bits + [13:13] + read-only + + + SECTOR0_SR + 0: Sector 0 does not contain special rows. The special rows are located in separate special sectors. +1: Sector 0 contains special rows + [14:14] + read-only + + + RESET_MM + Test_only, internal node: mpcon reset_mm + [15:15] + read-only + + + ROW_ODD + Test_only, internal node: mpcon row_odd + [16:16] + read-only + + + ROW_EVEN + Test_only, internal node: mpcon row_even + [17:17] + read-only + + + HVOP_SUB_SECTOR_N + Test_only, internal node: mpcon bk_subb + [18:18] + read-only + + + HVOP_SECTOR + Test_only, internal node: mpcon bk_sec + [19:19] + read-only + + + HVOP_BULK_ALL + Test_only, internal node: mpcon bk_all + [20:20] + read-only + + + CBUS_RA_MATCH + Test_only, internal node: mpcon ra match + [21:21] + read-only + + + CBUS_RED_ROW_EN + Test_only, internal node: mpcon red_row_en + [22:22] + read-only + + + RQ_ERROR + Test_only, internal node: rq_error sync-de in clk_c domain + [23:23] + read-only + + + PUMP_PDAC + Test_only, internal node: regif pdac outputs to pos pump + [27:24] + read-only + + + PUMP_NDAC + Test_only, internal node: regif ndac outputs to pos pump + [31:28] + read-only + + + + + FM_ADDR + Flash macro address + 0x8 + 32 + read-write + 0x0 + 0x1FFFFFF + + + RA + Row address. + [15:0] + read-write + + + BA + Bank address. + [23:16] + read-write + + + AXA + Auxiliary address field: +0: regular flash memory. +1: supervisory flash memory. + [24:24] + read-write + + + + + BOOKMARK + Bookmark register - keeps the current FW HV seq + 0xC + 32 + read-write + 0x0 + 0xFFFFFFFF + + + BOOKMARK + Used by FW. Keeps the Current HV cycle sequence + [31:0] + read-write + + + + + GEOMETRY + Regular flash geometry + 0x10 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + ROW_COUNT + Number of rows (minus 1): +0: 1 row +1: 2 rows +2: 3 rows +... +'65535': 65536 rows + [15:0] + read-only + + + BANK_COUNT + Number of banks (minus 1): +0: 1 bank +1: 2 banks +... +'255': 256 banks + [23:16] + read-only + + + WORD_SIZE_LOG2 + Number of Bytes per word (log 2). A word is defined as the data that is read from the flash macro over the R interface with a single read access: +0: 1 Byte +1: 2 Bytes +2: 4 Bytes +... +3: 128 Bytes + +The currently planned flash macros have a word size of either 32-bit, 64-bit or 128-bit, resulting in WORD_SIZE_LOG2 settings of 2, 3 and 4 respectively. + [27:24] + read-only + + + PAGE_SIZE_LOG2 + Number of Bytes per page (log 2): +0: 1 Byte +1: 2 Bytes +2: 4 Bytes +... +15: 32768 Bytes + +The currently planned flash macros have a page size of either 256 Byte or 512 Byte, resulting in PAGE_SIZE_LOG2 settings of 8 and 9 respectively. + [31:28] + read-only + + + + + GEOMETRY_SUPERVISORY + Supervisory flash geometry + 0x14 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + ROW_COUNT + Number of rows (minus 1). ROW_COUNT is typically less than GEOMETRY.ROW_COUNT + [15:0] + read-only + + + BANK_COUNT + Number of banks (minus 1). BANK_COUNT is less or equal to GEOMETRY.BANK_COUNT. + [23:16] + read-only + + + WORD_SIZE_LOG2 + Number of Bytes per word (log 2). See GEOMETRY.WORD_SIZE_LOG2. Typically, WORD_SIZE_LOG2 equals GEOMETRY.WORD_SIZE_LOG2. + [27:24] + read-only + + + PAGE_SIZE_LOG2 + Number of Bytes per page (log 2). See GEOMETRY.PAGE_SIZE_LOG2. Typically, PAGE_SIZE_LOG2 equals GEOMETRY.PAGE_SIZE_LOG2. + [31:28] + read-only + + + + + ANA_CTL0 + Analog control 0 + 0x18 + 32 + read-write + 0x400 + 0xFFFFFFFF + + + MDAC + Trimming of the output margin Voltage as a function of Vpos and Vneg. + [7:0] + read-write + + + CSLDAC + Trimming of common source line DAC. + [10:8] + read-write + + + FLIP_AMUXBUS_AB + Flips amuxbusa and amuxbusb +0: amuxbusa, amuxbusb +1: amuxbusb, amuxbusb + [11:11] + read-write + + + NDAC_MIN + NDAC staircase min value + [15:12] + read-write + + + PDAC_MIN + PDAC staircase min value + [19:16] + read-write + + + SCALE_PRG_SEQ01 + PROG&PRE_PROG: Scale for R_GRANT_DELAY on seq0-seq1 transition: +00: 0.125uS +01: 1uS +10: 10uS +11: 100uS + [21:20] + read-write + + + SCALE_PRG_SEQ12 + PROG&PRE_PROG: Scale for R_GRANT_DELAY on seq1-seq2 transition: +00: 0.125uS +01: 1uS +10: 10uS +11: 100uS + [23:22] + read-write + + + SCALE_PRG_SEQ23 + PROG&PRE_PROG: Scale for R_GRANT_DELAY on seq2-seq3 transition: +00: 0.125uS +01: 1uS +10: 10uS +11: 100uS + [25:24] + read-write + + + SCALE_SEQ30 + PROG&PRE_PROG& ERASE: Scale for R_GRANT_DELAY on seq3-seq0 transition: +00: 0.125uS +01: 1uS +10: 10uS +11: 100uS + [27:26] + read-write + + + SCALE_PRG_PEON + PROG&PRE_PROG: Scale for R_GRANT_DELAY on PE On transition: +00: 0.125uS +01: 1uS +10: 10uS +11: 100uS + [29:28] + read-write + + + SCALE_PRG_PEOFF + PROG&PRE_PROG: Scale for R_GRANT_DELAY on PE OFF transition: +00: 0.125uS +01: 1uS +10: 10uS +11: 100uS + [31:30] + read-write + + + + + ANA_CTL1 + Analog control 1 + 0x1C + 32 + read-write + 0xD32FAFA + 0xFFFFFFFF + + + NDAC_MAX + Ndac Max Value.Trimming of negative pump output Voltage. + [3:0] + read-write + + + NDAC_STEP + Ndac step increment + [7:4] + read-write + + + PDAC_MAX + Pdac Max Value.Trimming of positive pump output Voltage: + [11:8] + read-write + + + PDAC_STEP + Pdac step increment + [15:12] + read-write + + + NPDAC_STEP_TIME + Ndac/Pdac step duration: (1uS .. 255uS) * 8 +When = 0 N/PDAC_MAX control the pumps + [23:16] + read-write + + + NPDAC_ZERO_TIME + Ndac/Pdac LO duration: (1uS .. 255uS) * 8 +When 0, N/PDAC don't return to 0 + [31:24] + read-write + + + + + WAIT_CTL + Wait State control + 0x28 + 32 + read-write + 0x30B09 + 0x3F070F0F + + + WAIT_FM_MEM_RD + Number of C interface wait cycles (on 'clk_c') for a read from the memory + [3:0] + read-write + + + WAIT_FM_HV_RD + Number of C interface wait cycles (on 'clk_c') for a read from the high Voltage page latches. +Common for reading HV Page Latches and the DATA_COMP_RESULT bit + [11:8] + read-write + + + WAIT_FM_HV_WR + Number of C interface wait cycles (on 'clk_c') for a write to the high Voltage page latches. + [18:16] + read-write + + + FM_RWW_MODE + 00: Full CBUS MODE +01: RWW +10: RWW. R_GRANT is stalling r_bus for the whole program/erase duration + [25:24] + read-write + + + LV_SPARE_1 + Spare register + [26:26] + read-write + + + DRMM + 0: Normal +1: Test mode to enable Margin mode for 2 rows at a time + [27:27] + read-write + + + MBA + 0: Normal +1: Test mode to enable Master Bulk Access which allows both normal rows and redundant rows to be erased / programmed in one HV cycle (Bulk / Sector Erase and Sector Program). + [28:28] + read-write + + + PL_SOFT_SET_EN + Page latch soft set enable, 0 = disabled, 1 = enabled (at end of seq_2), taken care in API + [29:29] + read-write + + + + + TIMER_CLK_CTL + Timer prescaler (clk_t to timer clock frequency divider) + 0x34 + 32 + read-write + 0x8 + 0xFFFFFFFF + + + TIMER_CLOCK_FREQ + Clk_t frequency divider to provide the 1MHz reference clock for the Regif Timer. +Equal to the frequency in MHz of the timer clock 'clk_t'. +Example: if 'clk_t' has a frequency of 4 MHz then this field value is '4' +Max clk_t frequency = 100MHz. +This field is updated at runtime with the 'SW_TIMER_CLOCK_FREQ ' value from the HV parameters table + [7:0] + read-write + + + RGRANT_DELAY_PRG_PEON + PROG&PRE_PROG: R-grant blocking delay on PE ON. Scale = ANA_CTL0.SCALE_PEON +When = 0 R_GRANT_DELAY control is disabled +when IF_SEL=1 R_GRANT_DELAY control is disabled + [15:8] + read-write + + + RGRANT_DELAY_PRG_PEOFF + PROG&PRE_PROG: R-grant blocking delay on PE OFF. Scale = ANA_CTL0.SCALE_PEOFF +When = 0 R_GRANT_DELAY control is disabled +when IF_SEL=1 R_GRANT_DELAY control is disabled + [23:16] + read-write + + + RGRANT_DELAY_PRG_SEQ01 + PROG&PRE_PROG: R-grant blocking delay on seq0-seq1 transition. Scale = ANA_CTL0.SCALE_SEQ01 +When = 0 R_GRANT_DELAY control is disabled +when IF_SEL=1 R_GRANT_DELAY control is disabled + [31:24] + read-write + + + + + TIMER_CTL + Timer control + 0x38 + 32 + read-write + 0x4000001 + 0xE700FFFF + + + PERIOD + Timer period in either microseconds (SCALE is '0') or 100's of microseconds (SCALE is '1') multiples. + [14:0] + read-write + + + SCALE + Timer tick scale: +0: 1 microsecond. +1: 100 microseconds. + [15:15] + read-write + + + AUTO_SEQUENCE + 1': Starts1 the HV automatic sequencing +Cleared by HW + [24:24] + read-write + + + PRE_PROG + 1 during pre-program operation + [25:25] + read-write + + + PRE_PROG_CSL + 0: CSL lines driven by CSL_DAC +1: CSL lines driven by VNEG_G + [26:26] + read-write + + + PUMP_EN + Pump enable: +0: disabled +1: enabled (also requires FM_CTL.IF_SEL to be'1', this additional restriction is required to prevent non intentional clearing of the FM). +SW sets this field to '1' to generate a single PE pulse. +HW clears this field when timer is expired. + [29:29] + read-write + + + ACLK_EN + ACLK enable (generates a single cycle pulse for the FM): +0: disabled +1: enabled. SW set this field to '1' to generate a single cycle pulse. HW sets this field to '0' when the pulse is generated. + [30:30] + read-write + + + TIMER_EN + Timer enable: +0: disabled +1: enabled. SW sets this field to '1' to start the timer. HW sets this field to '0' when the timer is expired. + [31:31] + read-write + + + + + ACLK_CTL + MPCON clock + 0x3C + 32 + write-only + 0x0 + 0x1 + + + ACLK_GEN + A write to this register generates the clock pulse for HV control registers (mpcon outputs) + [0:0] + write-only + + + + + INTR + Interrupt + 0x40 + 32 + read-write + 0x0 + 0x1 + + + TIMER_EXPIRED + Set to '1', when event is detected. Write INTR field with '1', to clear bit. Write INTR_SET field with '1', to set bit. + [0:0] + read-write + + + + + INTR_SET + Interrupt set + 0x44 + 32 + read-write + 0x0 + 0x1 + + + TIMER_EXPIRED + Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). + [0:0] + read-write + + + + + INTR_MASK + Interrupt mask + 0x48 + 32 + read-write + 0x0 + 0x1 + + + TIMER_EXPIRED + Mask for corresponding field in INTR register. + [0:0] + read-write + + + + + INTR_MASKED + Interrupt masked + 0x4C + 32 + read-only + 0x0 + 0x1 + + + TIMER_EXPIRED + Logical and of corresponding request and mask fields. + [0:0] + read-only + + + + + CAL_CTL0 + Cal control BG LO trim bits + 0x50 + 32 + read-write + 0x38F8F + 0xFFFFF + + + VCT_TRIM_LO_HV + LO Bandgap Voltage Temperature Compensation trim control. + [4:0] + read-write + + + CDAC_LO_HV + LO Temperature compensated trim DAC. To control Vcstat slope for Vpos. + [7:5] + read-write + + + VBG_TRIM_LO_HV + LO Bandgap Voltage trim control. + [12:8] + read-write + + + VBG_TC_TRIM_LO_HV + LO Bandgap Voltage Temperature Compensation trim control + [15:13] + read-write + + + ICREF_TC_TRIM_LO_HV + LO Bandgap Current Temperature Compensation trim control + [18:16] + read-write + + + IPREF_TRIMA_LO_HV + Adds 100-150nA boost on IPREF_LO + [19:19] + read-write + + + + + CAL_CTL1 + Cal control BG HI trim bits + 0x54 + 32 + read-write + 0x38F8F + 0xFFFFF + + + VCT_TRIM_HI_HV + HI Bandgap Voltage Temperature Compensation trim control. + [4:0] + read-write + + + CDAC_HI_HV + HI Temperature compensated trim DAC. To control Vcstat slope for Vpos. + [7:5] + read-write + + + VBG_TRIM_HI_HV + HI Bandgap Voltage trim control. + [12:8] + read-write + + + VBG_TC_TRIM_HI_HV + HI Bandgap Voltage Temperature Compensation trim control. + [15:13] + read-write + + + ICREF_TC_TRIM_HI_HV + HI Bandgap Current Temperature Compensation trim control. + [18:16] + read-write + + + IPREF_TRIMA_HI_HV + Adds 100-150nA boost on IPREF_HI + [19:19] + read-write + + + + + CAL_CTL2 + Cal control BG LO&HI trim bits + 0x58 + 32 + read-write + 0x7BE10 + 0xFFFFF + + + ICREF_TRIM_LO_HV + LO Bandgap Current trim control. + [4:0] + read-write + + + ICREF_TRIM_HI_HV + HI Bandgap Current trim control. + [9:5] + read-write + + + IPREF_TRIM_LO_HV + LO Bandgap IPTAT trim control. + [14:10] + read-write + + + IPREF_TRIM_HI_HV + HI Bandgap IPTAT trim control. + [19:15] + read-write + + + + + CAL_CTL3 + Cal control osc trim bits, idac, sdac, itim + 0x5C + 32 + read-write + 0x2004 + 0xFFFFF + + + OSC_TRIM_HV + Flash macro pump clock trim control. + [3:0] + read-write + + + OSC_RANGE_TRIM_HV + 0: Oscillator High Frequency Range +1: Oscillator Low Frequency range + [4:4] + read-write + + + VPROT_ACT_HV + Forces VPROT in active mode all the time + [5:5] + read-write + + + IPREF_TC_HV + 0: Increases the IPREF Tempco by subtracting ICREF from IPREF - IPREF internal will be 0.5uA +1: Reduces the IPREF Tempco without subtracting ICREF from IPREF - IPREF internal will be 1uA + [6:6] + read-write + + + VREF_SEL_HV + Voltage reference: +0: internal bandgap reference +1: external voltage reference + [7:7] + read-write + + + IREF_SEL_HV + Current reference: +0: internal current reference +1: external current reference + [8:8] + read-write + + + REG_ACT_HV + 0: VBST regulator will operate in active/standby mode based on control signal. +1: Forces the VBST regulator in active mode all the time + [9:9] + read-write + + + FDIV_TRIM_HV + FDIV_TRIM_HV[1:0]: Assuming oscillator frequency of 8MHz in standby. +Following are the clock frequencies seen by doubler +00: F = 1MHz +01: F = 0.5MHz +10: F = 2MHz +11: F = 4MHz + [11:10] + read-write + + + VDDHI_HV + 0: vdd < 2.3V +1: vdd >= 2.3V +'0' setting can used for vdd > 2.3V also, but with a current penalty. + [12:12] + read-write + + + TURBO_PULSEW_HV + Turbo pulse width trim (Typical) +00: 40 us +01: 20 us +10: 15 us +11: 8 us + [14:13] + read-write + + + BGLO_EN_HV + 0: Normal (Automatic change over from HI to LO) +1: Force enable LO Bandgap + [15:15] + read-write + + + BGHI_EN_HV + 0: Normal (Automatic change over from HI to LO) +1: Force enable HI Bandgap +When both BGLO_EN_HV and BGHI_EN_HV are HIGH, only BGHI output is used and turbo_hv_n pulse is active + [16:16] + read-write + + + CL_ISO_DIS_HV + 0: The internal logic controls the CL isolation +1: Forces CL bypass + [17:17] + read-write + + + R_GRANT_EN_HV + 0: r_grant handshake disabled, r_grant always 1. +1: r_grand handshake enabled + [18:18] + read-write + + + LP_ULP_SW_HV + LP<-->ULP switch for trim signals: +0: LP +1: ULP + [19:19] + read-write + + + + + CAL_CTL4 + Cal Control Vlim, SA, fdiv, reg_act + 0x60 + 32 + read-write + 0x12AE0 + 0xFFFFF + + + VLIM_TRIM_ULP_HV + VLIM_TRIM[1:0]: +00: V2 = 650mV +01: V2 = 600mV +10: V2 = 750mV +11: V2 = 700mV + [1:0] + read-write + + + IDAC_ULP_HV + Sets the sense current reference offset value. Refer to trim tables for details. + [5:2] + read-write + + + SDAC_ULP_HV + Sets the sense current reference temp slope. Refer to trim tables for details. + [7:6] + read-write + + + ITIM_ULP_HV + Trimming of timing current + [12:8] + read-write + + + FM_READY_DEL_ULP_HV + 00: Default : delay 1ns +01: Delayed by 1.5us +10: Delayed by 2.0us +11: Delayed by 2.5us + [14:13] + read-write + + + SPARE451_ULP_HV + N/A + [15:15] + read-write + + + READY_RESTART_N_HV + Toggle: 1-->0, ready goes low, ready will remain low as long as the bit is low. Toggle the bit back to 1 to activate the ready logic. To be used by API only. + [16:16] + read-write + + + VBST_S_DIS_HV + 0: VBST_S voltage for each sector to allow VBST level to be dropped to VCC during Erase in the selected sector, reducing coupling to GBL. +1: VBST_S voltage for each sector stays at VBST level during Erase in the selected sector. + [17:17] + read-write + + + AUTO_HVPULSE_HV + 0: HV Pulse controlled by FW +1: HV Pulse controlled by Hardware + [18:18] + read-write + + + UGB_EN_HV + UGB enable in TM control + [19:19] + read-write + + + + + CAL_CTL5 + Cal control + 0x64 + 32 + read-write + 0x2AE0 + 0xFFFFF + + + VLIM_TRIM_LP_HV + VLIM_TRIM[1:0]: +00: V2 = 650mV +01: V2 = 600mV +10: V2 = 750mV +11: V2 = 700mV + [1:0] + read-write + + + IDAC_LP_HV + Sets the sense current reference offset value. Refer to trim tables for details. + [5:2] + read-write + + + SDAC_LP_HV + Sets the sense current reference temp slope. Refer to trim tables for details. + [7:6] + read-write + + + ITIM_LP_HV + Trimming of timing current + [12:8] + read-write + + + FM_READY_DEL_LP_HV + 00: Delayed by 1us +01: Delayed by 1.5us +10: Delayed by 2.0us +11: Delayed by 2.5us + [14:13] + read-write + + + SPARE451_LP_HV + N/A + [15:15] + read-write + + + SPARE52_HV + N/A + [17:16] + read-write + + + AMUX_SEL_HV + Amux Select in AMUX_UGB +00: Bypass UGB for both amuxbusa and amuxbusb +01: Bypass UGB for amuxbusb while passing amuxbusa through UGB. +10: Bypass UGB for amuxbusa while passing amuxbusb through UGB. +11: UGB Calibrate mode + [19:18] + read-write + + + + + CAL_CTL6 + SA trim LP/ULP + 0x68 + 32 + read-write + 0x36F7F + 0xFFFFF + + + SA_CTL_TRIM_T1_ULP_HV + clk_trk delay + [0:0] + read-write + + + SA_CTL_TRIM_T4_ULP_HV + SA_CTL_TRIM_T4_ULP_HV<2>= eqi (eq current trim) +SA_CTL_TRIM_T4_ULP_HV<1:0> = eqc (eq cap trim) + [3:1] + read-write + + + SA_CTL_TRIM_T5_ULP_HV + SA_CTL_TRIM_T5_ULP_HV<2>= evi (integration current trim) +SA_CTL_TRIM_T5_ULP_HV<1:0> = evc (integration cap trim) + [6:4] + read-write + + + SA_CTL_TRIM_T6_ULP_HV + SA_CTL_TRIM_T6_ULP_HV<1>= eni (enable current trim) +SA_CTL_TRIM_T6_ULP_HV<0> = ecn (enable cap trim) + [8:7] + read-write + + + SA_CTL_TRIM_T8_ULP_HV + saen3 pulse width trim (Current trim) + [9:9] + read-write + + + SA_CTL_TRIM_T1_LP_HV + clk_trk delay + [10:10] + read-write + + + SA_CTL_TRIM_T4_LP_HV + SA_CTL_TRIM_T4_LP_HV<2>= eqi (eq current trim) +SA_CTL_TRIM_T4_LP_HV<1:0> = eqc (eq cap trim) + [13:11] + read-write + + + SA_CTL_TRIM_T5_LP_HV + SA_CTL_TRIM_T5_LP_HV<2>= evi (integration current trim) +SA_CTL_TRIM_T5_LP_HV<1:0> = evc (integration cap trim) + [16:14] + read-write + + + SA_CTL_TRIM_T6_LP_HV + SA_CTL_TRIM_T6_LP_HV<1>= eni (enable current trim) +SA_CTL_TRIM_T6_LP_HV<0> = ecn (enable cap trim) + [18:17] + read-write + + + SA_CTL_TRIM_T8_LP_HV + saen3 pulse width trim (Current trim) + [19:19] + read-write + + + + + CAL_CTL7 + Cal control + 0x6C + 32 + read-write + 0x0 + 0xFFFFF + + + ERSX8_CLK_SEL_HV + Clock frequency into the ersx8 shift register block +00: Oscillator clock +01: Oscillator clock / 2 +10: Oscillator clock / 4 +11: Oscillator clock + [1:0] + read-write + + + FM_ACTIVE_HV + 0: Normal operation +1: Forces FM SYS in active mode + [2:2] + read-write + + + TURBO_EXT_HV + 0: Normal operation +1: Uses external turbo pulse + [3:3] + read-write + + + NPDAC_HWCTL_DIS_HV + 0': ndac, pdac staircase hardware controlled +1: ndac, pdac staircase disabled. Enables FW control. + [4:4] + read-write + + + FM_READY_DIS_HV + 0': fm ready is enabled +1: fm ready is disabled (fm_ready is always '1') + [5:5] + read-write + + + ERSX8_EN_ALL_HV + 0': Staggered turn on/off of GWL +1: GWL are turned on/off at the same time (old FM legacy) + [6:6] + read-write + + + DISABLE_LOAD_ONCE_HV + 0: Load common HV params during API HV operations depends on the HV_PARAMS_LOADED bit in RGRANT_DELAY_PRG register. +1: All HV params are loaded during every API HV operation irrespective of HV_PARAMS_LOADED bit in the RGRANT_DELAY_PRG register. + [7:7] + read-write + + + SPARE7_HV + N/A + [9:8] + read-write + + + SPARE7_ULP_HV + N/A + [14:10] + read-write + + + SPARE7_LP_HV + N/A + [19:15] + read-write + + + + + RED_CTL01 + Redundancy Control normal sectors 0,1 + 0x80 + 32 + read-write + 0x0 + 0x1FF01FF + + + RED_ADDR_0 + Bad Row Pair Address for Sector 0 + [7:0] + read-write + + + RED_EN_0 + 1: Redundancy Enable for Sector 0 + [8:8] + read-write + + + RED_ADDR_1 + Bad Row Pair Address for Sector 1 + [23:16] + read-write + + + RED_EN_1 + 1: Redundancy Enable for Sector 1 + [24:24] + read-write + + + + + RED_CTL23 + Redundancy Control normal sectors 2,3 + 0x84 + 32 + read-write + 0x0 + 0x1FF01FF + + + RED_ADDR_2 + Bad Row Pair Address for Sector 2 + [7:0] + read-write + + + RED_EN_2 + 1: Redundancy Enable for Sector 2 + [8:8] + read-write + + + RED_ADDR_3 + Bad Row Pair Address for Sector 3 + [23:16] + read-write + + + RED_EN_3 + 1: Redundancy Enable for Sector 3 + [24:24] + read-write + + + + + RED_CTL45 + Redundancy Control normal sectors 4,5 + 0x88 + 32 + read-write + 0x0 + 0x1FF01FF + + + RED_ADDR_4 + Bad Row Pair Address for Sector 4 + [7:0] + read-write + + + RED_EN_4 + 1: Redundancy Enable for Sector 4 + [8:8] + read-write + + + RED_ADDR_5 + Bad Row Pair Address for Sector 5 + [23:16] + read-write + + + RED_EN_5 + 1: Redundancy Enable for Sector 5 + [24:24] + read-write + + + + + RED_CTL67 + Redundancy Control normal sectors 6,7 + 0x8C + 32 + read-write + 0x0 + 0x1FF01FF + + + RED_ADDR_6 + Bad Row Pair Address for Sector 6 + [7:0] + read-write + + + RED_EN_6 + 1: Redundancy Enable for Sector 6 + [8:8] + read-write + + + RED_ADDR_7 + Bad Row Pair Address for Sector 7 + [23:16] + read-write + + + RED_EN_7 + 1: Redundancy Enable for Sector 7 + [24:24] + read-write + + + + + RED_CTL_SM01 + Redundancy Control special sectors 0,1 + 0x90 + 32 + read-write + 0x0 + 0x1FF01FF + + + RED_ADDR_SM0 + Bad Row Pair Address for Special Sector 0 + [7:0] + read-write + + + RED_EN_SM0 + Redundancy Enable for Special Sector 0 + [8:8] + read-write + + + RED_ADDR_SM1 + Bad Row Pair Address for Special Sector 1 + [23:16] + read-write + + + RED_EN_SM1 + Redundancy Enable for Special Sector 1 + [24:24] + read-write + + + + + RGRANT_DELAY_PRG + R-grant delay for program + 0x98 + 32 + read-write + 0x1000000 + 0x8FFFFFFF + + + RGRANT_DELAY_PRG_SEQ12 + PROG&PRE_PROG: R-grant blocking delay on seq1-seq2 transition. Scale = ANA_CTL0.SCALE_SEQ12 +When = 0 R_GRANT_DELAY control is disabled +when IF_SEL=1 R_GRANT_DELAY control is disabled + [7:0] + read-write + + + RGRANT_DELAY_PRG_SEQ23 + PROG&PRE_PROG: R-grant blocking delay on seq2-seq3 transition. Scale = ANA_CTL0.SCALE_SEQ23 +When = 0 R_GRANT_DELAY control is disabled +when IF_SEL=1 R_GRANT_DELAY control is disabled + [15:8] + read-write + + + RGRANT_DELAY_SEQ30 + PROG&PRE_PROG & ERASE: R-grant blocking delay on seq3-seq0 transition. Scale = ANA_CTL0.SCALE_SEQ30 +When = 0 R_GRANT_DELAY control is disabled +when IF_SEL=1 R_GRANT_DELAY control is disabled + [23:16] + read-write + + + RGRANT_DELAY_CLK + Frequency divider from clk_t to create the 8MHz reference clock for R_grant delay +The value of this field is the integer result of 'clk_t frequency / 8'. +Example: for clk_t=100 this field is INT(100/8) =12. +This field is updated at runtime with the 'SW_RGRANT_DELAY_CLK ' value from the HV parameters table + [27:24] + read-write + + + HV_PARAMS_LOADED + 0: HV Pulse common params not loaded +1: HV Pulse common params loaded: r-grant delays, r-grant scale, prescaler, timer values for seq1,seq2_pre, seq2_post, seq3 + [31:31] + read-write + + + + + PW_SEQ12 + HV Pulse Delay for seq 1&2 pre + 0xA0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + PW_SEQ1 + Seq1 delay + [15:0] + read-write + + + PW_SEQ2_PRE + Seq2 pre delay + [31:16] + read-write + + + + + PW_SEQ23 + HV Pulse Delay for seq2 post & seq3 + 0xA4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + PW_SEQ2_POST + Seq2 post delay + [15:0] + read-write + + + PW_SEQ3 + Seq3 delay + [31:16] + read-write + + + + + RGRANT_SCALE_ERS + R-grant delay scale for erase + 0xA8 + 32 + read-write + 0x0 + 0xFFFF03FF + + + SCALE_ERS_SEQ01 + ERASE: Scale for R_GRANT_DELAY on seq0-seq1 transition: +00: 0.125uS +01: 1uS +10: 10uS +11: 100uS + [1:0] + read-write + + + SCALE_ERS_SEQ12 + ERASE: Scale for R_GRANT_DELAY on seq1-seq2 transition: +00: 0.125uS +01: 1uS +10: 10uS +11: 100uS + [3:2] + read-write + + + SCALE_ERS_SEQ23 + ERASE: Scale for R_GRANT_DELAY on seq2-seq3 transition: +00: 0.125uS +01: 1uS +10: 10uS +11: 100uS + [5:4] + read-write + + + SCALE_ERS_PEON + ERASE: Scale for R_GRANT_DELAY on PE On transition: +00: 0.125uS +01: 1uS +10: 10uS +11: 100uS + [7:6] + read-write + + + SCALE_ERS_PEOFF + ERASE: Scale for R_GRANT_DELAY on PE OFF transition: +00: 0.125uS +01: 1uS +10: 10uS +11: 100uS + [9:8] + read-write + + + RGRANT_DELAY_ERS_PEON + ERASE: R-grant blocking delay on PE ON. Scale = ANA_CTL0.SCALE_PEON +When = 0 R_GRANT_DELAY control is disabled +when IF_SEL=1 R_GRANT_DELAY control is disabled + [23:16] + read-write + + + RGRANT_DELAY_ERS_PEOFF + ERASE: R-grant blocking delay on PE OFF. Scale = ANA_CTL0.SCALE_PEOFF +When = 0 R_GRANT_DELAY control is disabled +when IF_SEL=1 R_GRANT_DELAY control is disabled + [31:24] + read-write + + + + + RGRANT_DELAY_ERS + R-grant delay for erase + 0xAC + 32 + read-write + 0x0 + 0xFFFFFF + + + RGRANT_DELAY_ERS_SEQ01 + ERASE: R-grant blocking delay on seq0-seq1 transition. Scale = ANA_CTL0.SCALE_SEQ01 +When = 0 R_GRANT_DELAY control is disabled +when IF_SEL=1 R_GRANT_DELAY control is disabled + [7:0] + read-write + + + RGRANT_DELAY_ERS_SEQ12 + ERASE: R-grant blocking delay on seq1-seq2 transition. Scale = ANA_CTL0.SCALE_SEQ12 +When = 0 R_GRANT_DELAY control is disabled +when IF_SEL=1 R_GRANT_DELAY control is disabled + [15:8] + read-write + + + RGRANT_DELAY_ERS_SEQ23 + ERASE: R-grant blocking delay on seq2-seq3 transition. Scale = ANA_CTL0.SCALE_SEQ23 +When = 0 R_GRANT_DELAY control is disabled +when IF_SEL=1 R_GRANT_DELAY control is disabled + [23:16] + read-write + + + + + FM_PL_WRDATA_ALL + Flash macro write page latches all + 0x7FC + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DATA32 + Write all high Voltage page latches with the same 32-bit data in a single write cycle +Read always returns 0. + [31:0] + read-write + + + + + 256 + 4 + FM_PL_DATA[%s] + Flash macro Page Latches data + 0x800 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DATA32 + Four page latch Bytes +When reading the page latches it requires FM_CTL.IF_SEL to be '1' +Note: the high Voltage page latches are readable for test mode functionality. + [31:0] + read-write + + + + + 256 + 4 + FM_MEM_DATA[%s] + Flash macro memory sense amplifier and column decoder data + 0xC00 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DATA32 + Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: +- IF_SEL is 0: data as specified by the R interface address +- IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. + [31:0] + read-only + + + + + + + + SRSS + SRSS Core Registers + 0x40260000 + + 0 + 65536 + registers + + + + PWR_CTL + Power Mode Control + 0x0 + 32 + read-write + 0x0 + 0xFFFC0033 + + + POWER_MODE + Current power mode of the device. Note that this field cannot be read in all power modes on actual silicon. + [1:0] + read-only + + + RESET + System is resetting. + 0 + + + ACTIVE + At least one CPU is running. + 1 + + + SLEEP + No CPUs are running. Peripherals may be running. + 2 + + + DEEPSLEEP + Main high-frequency clock is off; low speed clocks are available. Communication interface clocks may be present. + 3 + + + + + DEBUG_SESSION + Indicates whether a debug session is active (CDBGPWRUPREQ signal is 1) + [4:4] + read-only + + + NO_SESSION + No debug session active + 0 + + + SESSION_ACTIVE + Debug session is active. Power modes behave differently to keep the debug session active. + 1 + + + + + LPM_READY + Indicates whether certain low power functions are ready. The low current circuits take longer to startup after XRES/POR/BOD/HIBERNATE wakeup than the normal mode circuits. HIBERNATE mode may be entered regardless of this bit. This register is only reset by XRES/POR/BOD/HIBERNATE. +0: If a low power circuit operation is requested, it will stay in its normal operating mode until it is ready. If DEEPSLEEP is requested by all processors WFI/WFE, the device will instead enter SLEEP. When low power circuits are ready, device will automatically enter the originally requested mode. +1: Normal operation. DEEPSLEEP and low power circuits operate as requested in other registers. + [5:5] + read-only + + + IREF_LPMODE + Control the power mode of the reference current generator. The value in this register is ignored and normal mode is used until LPM_READY==1. This register is only reset by XRES/POR/BOD/HIBERNATE. +0: Current reference generator operates in normal mode. It works for vddd ramp rates of 100mV/us or less. +1: Current reference generator operates in low power mode. Response time is reduced to save current, and it works for vddd ramp rates of 10mV/us or less. + [18:18] + read-write + + + VREFBUF_OK + Indicates that the voltage reference buffer is ready. Due to synchronization delays, it may take two IMO clock cycles for hardware to clear this bit after asserting VREFBUF_DIS=1. + [19:19] + read-only + + + DPSLP_REG_DIS + Disable the DeepSleep regulator. This is only legal when the on-chip buck regulator supplies vccd, but there is no hardware protection for this case. This register is only reset by XRES/POR/BOD/HIBERNATE. +0: DeepSleep Regulator is on. +1: DeepSleep Regulator is off. + [20:20] + read-write + + + RET_REG_DIS + Disable the Retention regulator. This is only legal when the on-chip buck regulator supplies vccd, but there is no hardware protection for this case. This register is only reset by XRES/POR/BOD/HIBERNATE. +0: Retention Regulator is on. +1: Retention Regulator is off. + [21:21] + read-write + + + NWELL_REG_DIS + Disable the Nwell regulator. This is only legal when the on-chip buck regulator supplies vccd, but there is no hardware protection for this case. This register is only reset by XRES/POR/BOD/HIBERNATE. +0: Nwell Regulator is on. +1: Nwell Regulator is off. + [22:22] + read-write + + + LINREG_DIS + Disable the linear Core Regulator. This is only legal when the on-chip buck regulator supplies vccd, but there is no hardware protection for this case. This register is only reset by XRES/POR/BOD/HIBERNATE. +0: Linear regulator is on. +1: Linear regulator is off. + [23:23] + read-write + + + LINREG_LPMODE + Control the power mode of the Linear Regulator. The value in this register is ignored and normal mode is used until LPM_READY==1. This register is only reset by XRES/POR/BOD/HIBERNATE. +0: Linear Regulator operates in normal mode. Internal current consumption is 50uA and load current capability is 50mA to 300mA, depending on the number of regulator modules present in the product. +1: Linear Regulator operates in low power mode. Internal current consumption is 5uA and load current capability is 25mA. Firmware must ensure the current is kept within the limit. + [24:24] + read-write + + + PORBOD_LPMODE + Control the power mode of the POR/BOD circuits. The value in this register is ignored and normal mode is used until LPM_READY==1. This register is only reset by XRES/POR/BOD/HIBERNATE. +0: POR/BOD circuits operate in normal mode. They work for vddd ramp rates of 100mV/us or less. +1: POR/BOD circuits operate in low power mode. Response time is reduced to save current, and they work for vddd ramp rates of 10mV/us or less. + [25:25] + read-write + + + BGREF_LPMODE + Control the power mode of the Bandgap Voltage and Current References. This applies to voltage and current generation and is different than the reference voltage buffer. The value in this register is ignored and normal mode is used until LPM_READY==1. When lower power mode is used, the Active Reference circuit can be disabled to reduce current. Firmware is responsible to ensure ACT_REF_OK==1 before changing back to normal mode. This register is only reset by XRES/POR/BOD/HIBERNATE. +0: Active Bandgap Voltage and Current Reference operates in normal mode. They work for vddd ramp rates of 100mV/us or less. +1: Active Bandgap Voltage and Current Reference operates in low power mode. Power supply rejection is reduced to save current, and they work for vddd ramp rates of 10mV/us or less. The Active Reference may be disabled using ACT_REF_DIS=0. + [26:26] + read-write + + + PLL_LS_BYPASS + Bypass level shifter inside the PLL. +0: Do not bypass the level shifter. This setting is ok for all operational modes and vccd target voltage. +1: Bypass the level shifter. This may reduce jitter on the PLL output clock, but can only be used when vccd is targeted to 1.1V nominal. Otherwise, it can result in clock degradation and static current. + [27:27] + read-write + + + VREFBUF_LPMODE + Control the power mode of the 800mV voltage reference buffer. The value in this register is ignored and normal mode is used until LPM_READY==1. +0: Voltage Reference Buffer operates in normal mode. They work for vddd ramp rates of 100mV/us or less. This register is only reset by XRES/POR/BOD/HIBERNATE. +1: Voltage Reference Buffer operates in low power mode. Power supply rejection is reduced to save current, and they work for vddd ramp rates of 10mV/us or less. + [28:28] + read-write + + + VREFBUF_DIS + Disable the 800mV voltage reference buffer. Firmware should only disable the buffer when there is no connected circuit that is using it. SRSS circuits that require it are the PLL and ECO. A particular product may have circuits outside the SRSS that use the buffer. This register is only reset by XRES/POR/BOD/HIBERNATE. + [29:29] + read-write + + + ACT_REF_DIS + Disables the Active Reference. Firmware must ensure that LPM_READY==1 and BGREF_LPMODE==1 for at least 1us before disabling the Active Reference. When enabling the Active Reference, use ACT_REF_OK indicator to know when it is ready. This register is only reset by XRES/POR/BOD/HIBERNATE. +0: Active Reference is enabled +1: Active Reference is disabled + [30:30] + read-write + + + ACT_REF_OK + Indicates that the normal mode of the Active Reference is ready. + [31:31] + read-only + + + + + PWR_HIBERNATE + HIBERNATE Mode Register + 0x4 + 32 + read-write + 0x0 + 0xCFFEFFFF + + + TOKEN + Contains a 8-bit token that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware to differentiate WAKEUP from a general RESET event. Note that waking up from HIBERNATE using XRES will reset this register. + [7:0] + read-write + + + UNLOCK + This byte must be set to 0x3A for FREEZE or HIBERNATE fields to operate. Any other value in this register will cause FREEZE/HIBERNATE to have no effect, except as noted in the FREEZE description. + [15:8] + read-write + + + FREEZE + Firmware sets this bit to freeze the configuration, mode and state of all GPIOs and SIOs in the system. When entering HIBERNATE mode, the first write instructs DEEPSLEEP peripherals that they cannot ignore the upcoming freeze command. This occurs even in the illegal condition where UNLOCK is not set. If UNLOCK and HIBERNATE are properly set, the IOs actually freeze on the second write. + [17:17] + read-write + + + MASK_HIBALARM + When set, HIBERNATE will wakeup for a RTC interrupt + [18:18] + read-write + + + MASK_HIBWDT + When set, HIBERNATE will wakeup if WDT matches + [19:19] + read-write + + + POLARITY_HIBPIN + Each bit sets the active polarity of the corresponding wakeup pin. +0: Pin input of 0 will wakeup the part from HIBERNATE +1: Pin input of 1 will wakeup the part from HIBERNATE + [23:20] + read-write + + + MASK_HIBPIN + When set, HIBERNATE will wakeup if the corresponding pin input matches the POLARITY_HIBPIN setting. Each bit corresponds to one of the wakeup pins. + [27:24] + read-write + + + HIBERNATE_DISABLE + Hibernate disable bit. +0: Normal operation, HIBERNATE works as described +1: Further writes to this register are ignored +Note: This bit is a write-once bit until the next reset. Avoid changing any other bits in this register while disabling HIBERNATE mode. Also, it is recommended to clear the UNLOCK code, if it was previously written.. + [30:30] + read-write + + + HIBERNATE + Firmware sets this bit to enter HIBERNATE mode. The system will enter HIBERNATE mode immediately after writing to this bit and will wakeup only in response to XRES or WAKEUP event. Both UNLOCK and FREEZE must have been set correctly in a previous write operations. Otherwise, it will not enter HIBERNATE. External supplies must have been stable for 250us before entering HIBERNATE mode. + [31:31] + read-write + + + + + PWR_LVD_CTL + Low Voltage Detector (LVD) Configuration Register + 0x8 + 32 + read-write + 0x0 + 0xFF + + + HVLVD1_TRIPSEL + Threshold selection for HVLVD1. Disable the LVD (HVLVD1_EN=0) before changing the threshold. +0: rise=1.225V (nom), fall=1.2V (nom) +1: rise=1.425V (nom), fall=1.4V (nom) +2: rise=1.625V (nom), fall=1.6V (nom) +3: rise=1.825V (nom), fall=1.8V (nom) +4: rise=2.025V (nom), fall=2V (nom) +5: rise=2.125V (nom), fall=2.1V (nom) +6: rise=2.225V (nom), fall=2.2V (nom) +7: rise=2.325V (nom), fall=2.3V (nom) +8: rise=2.425V (nom), fall=2.4V (nom) +9: rise=2.525V (nom), fall=2.5V (nom) +10: rise=2.625V (nom), fall=2.6V (nom) +11: rise=2.725V (nom), fall=2.7V (nom) +12: rise=2.825V (nom), fall=2.8V (nom) +13: rise=2.925V (nom), fall=2.9V (nom) +14: rise=3.025V (nom), fall=3.0V (nom) +15: rise=3.125V (nom), fall=3.1V (nom) + [3:0] + read-write + + + HVLVD1_SRCSEL + Source selection for HVLVD1 + [6:4] + read-write + + + VDDD + Select VDDD + 0 + + + AMUXBUSA + Select AMUXBUSA (VDDD branch) + 1 + + + RSVD + N/A + 2 + + + VDDIO + N/A + 3 + + + AMUXBUSB + Select AMUXBUSB (VDDD branch) + 4 + + + + + HVLVD1_EN + Enable HVLVD1 voltage monitor. When the LVD is enabled, it takes 20us for it to settle. There is no hardware stabilization counter, and it may falsely trigger during settling. It is recommended that firmware keep the interrupt masked for at least 8us, write a 1'b1 to the corresponding SRSS_INTR field to any falsely pended interrupt, and then optionally unmask the interrupt. After enabling, it is further recommended to read the related PWR_LVD_STATUS field, since the interrupt only triggers on edges. This bit is cleared (LVD is disabled) when entering DEEPSLEEP to prevent false interrupts during wakeup. + [7:7] + read-write + + + + + PWR_BUCK_CTL + Buck Control Register + 0x14 + 32 + read-write + 0x5 + 0xC0000007 + + + BUCK_OUT1_SEL + Voltage output selection for vccbuck1 output. This register is only reset by XRES/POR/BOD/HIBERNATE. When increasing the voltage, it can take up to 200us for the output voltage to settle. When decreasing the voltage, the settling time depends on the load current. +0: 0.85V +1: 0.875V +2: 0.90V +3: 0.95V +4: 1.05V +5: 1.10V +6: 1.15V +7: 1.20V + [2:0] + read-write + + + BUCK_EN + Master enable for buck converter. This register is only reset by XRES/POR/BOD/HIBERNATE. + [30:30] + read-write + + + BUCK_OUT1_EN + Enable for vccbuck1 output. The value in this register is ignored unless PWR_BUCK_CTL.BUCK_EN==1. This register is only reset by XRES/POR/BOD/HIBERNATE. The regulator takes up to 600us to charge the external capacitor. If there is additional load current while charging, this will increase the startup time. The TRM specifies the required sequence when transitioning vccd from the LDO to SIMO Buck output #1. + [31:31] + read-write + + + + + PWR_BUCK_CTL2 + Buck Control Register 2 + 0x18 + 32 + read-write + 0x0 + 0xC0000007 + + + BUCK_OUT2_SEL + Voltage output selection for vccbuck2 output. When increasing the voltage, it can take up to 200us for the output voltage to settle. When decreasing the voltage, the settling time depends on the load current. +0: 1.15V +1: 1.20V +2: 1.25V +3: 1.30V +4: 1.35V +5: 1.40V +6: 1.45V +7: 1.50V + [2:0] + read-write + + + BUCK_OUT2_HW_SEL + Hardware control for vccbuck2 output. When this bit is set, the value in BUCK_OUT2_EN is ignored and a hardware signal is used instead. If the product has supporting hardware, it can directly control the enable signal for vccbuck2. The same charging time in BUCK_OUT2_EN applies. + [30:30] + read-write + + + BUCK_OUT2_EN + Enable for vccbuck2 output. The value in this register is ignored unless PWR_BUCK_CTL.BUCK_EN==1. The regulator takes up to 600us to charge the external capacitor. If there is additional load current while charging, this will increase the startup time. + [31:31] + read-write + + + + + PWR_LVD_STATUS + Low Voltage Detector (LVD) Status Register + 0x1C + 32 + read-only + 0x0 + 0x1 + + + HVLVD1_OK + HVLVD1 output. +0: below voltage threshold +1: above voltage threshold + [0:0] + read-only + + + + + 16 + 4 + PWR_HIB_DATA[%s] + HIBERNATE Data Register + 0x80 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HIB_DATA + Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose. Note that waking up from HIBERNATE using XRES will reset this register. + [31:0] + read-write + + + + + WDT_CTL + Watchdog Counter Control Register + 0x180 + 32 + read-write + 0xC0000001 + 0xC0000001 + + + WDT_EN + Enable this watchdog timer. This field is retained during DEEPSLEEP and HIBERNATE modes. + [0:0] + read-write + + + WDT_LOCK + Prohibits writing to WDT_*, CLK_ILO_CONFIG, CLK_SELECT.LFCLK_SEL, and CLK_TRIM_ILO_CTL registers when not equal 0. Requires at least two different writes to unlock. A change in WDT_LOCK takes effect beginning with the next write cycle. +Note that this field is 2 bits to force multiple writes only. It represents only a single write protect signal protecting all those registers at the same time. WDT will lock on any reset. This field is not retained during DEEPSLEEP or HIBERNATE mode, so the WDT will be locked after wakeup from these modes. + [31:30] + read-write + + + NO_CHG + No effect + 0 + + + CLR0 + Clears bit 0 + 1 + + + CLR1 + Clears bit 1 + 2 + + + SET01 + Sets both bits 0 and 1 + 3 + + + + + + + WDT_CNT + Watchdog Counter Count Register + 0x184 + 32 + read-write + 0x0 + 0xFFFF + + + COUNTER + Current value of WDT Counter. The write feature of this register is for engineering use (DfV), have no synchronization, and can only be applied when the WDT is fully off. When writing, the value is updated immediately in the WDT counter, but it will read back as the old value until this register resynchronizes just after the negedge of ILO. Writes will be ignored if they occur when the WDT is enabled. + [15:0] + read-write + + + + + WDT_MATCH + Watchdog Counter Match Register + 0x188 + 32 + read-write + 0x1000 + 0xFFFFF + + + MATCH + Match value for Watchdog counter. Every time WDT_COUNTER reaches MATCH an interrupt is generated. Two unserviced interrupts will lead to a system reset (i.e. at the third match). + [15:0] + read-write + + + IGNORE_BITS + The number of MSB bits of the watchdog timer that are NOT checked against MATCH. This value provides control over the time-to-reset of the watchdog (which happens after 3 successive matches). Up to 12 MSB can be ignored. Settings >12 behave like a setting of 12. + [19:16] + read-write + + + + + 2 + 64 + MCWDT_STRUCT[%s] + Multi-Counter Watchdog Timer + MCWDT_STRUCT + 0x00000200 + + MCWDT_CNTLOW + Multi-Counter Watchdog Sub-counters 0/1 + 0x4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + WDT_CTR0 + Current value of sub-counter 0 for this MCWDT. Software writes are ignored when the sub-counter is enabled. + [15:0] + read-write + + + WDT_CTR1 + Current value of sub-counter 1 for this MCWDT. Software writes are ignored when the sub-counter is enabled + [31:16] + read-write + + + + + MCWDT_CNTHIGH + Multi-Counter Watchdog Sub-counter 2 + 0x8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + WDT_CTR2 + Current value of sub-counter 2 for this MCWDT. Software writes are ignored when the sub-counter is enabled + [31:0] + read-write + + + + + MCWDT_MATCH + Multi-Counter Watchdog Counter Match Register + 0xC + 32 + read-write + 0x0 + 0xFFFFFFFF + + + WDT_MATCH0 + Match value for sub-counter 0 of this MCWDT + [15:0] + read-write + + + WDT_MATCH1 + Match value for sub-counter 1 of this MCWDT + [31:16] + read-write + + + + + MCWDT_CONFIG + Multi-Counter Watchdog Counter Configuration + 0x10 + 32 + read-write + 0x0 + 0x1F010F0F + + + WDT_MODE0 + Watchdog Counter Action on Match. Action is taken on the next increment after the values match (WDT_CTR0=WDT_MATCH0). + [1:0] + read-write + + + NOTHING + Do nothing + 0 + + + INT + Assert WDT_INTx + 1 + + + RESET + Assert WDT Reset + 2 + + + INT_THEN_RESET + Assert WDT_INTx, assert WDT Reset after 3rd unhandled interrupt + 3 + + + + + WDT_CLEAR0 + Clear Watchdog Counter when WDT_CTR0=WDT_MATCH0. In other words WDT_CTR0 divides LFCLK by (WDT_MATCH0+1). +0: Free running counter +1: Clear on match. In this mode, the minimum legal setting of WDT_MATCH0 is 1. + [2:2] + read-write + + + WDT_CASCADE0_1 + Cascade Watchdog Counters 0,1. Counter 1 increments the cycle after WDT_CTR0=WDT_MATCH0. +0: Independent counters +1: Cascaded counters + [3:3] + read-write + + + WDT_MODE1 + Watchdog Counter Action on Match. Action is taken on the next increment after the values match (WDT_CTR1=WDT_MATCH1). + [9:8] + read-write + + + NOTHING + Do nothing + 0 + + + INT + Assert WDT_INTx + 1 + + + RESET + Assert WDT Reset + 2 + + + INT_THEN_RESET + Assert WDT_INTx, assert WDT Reset after 3rd unhandled interrupt + 3 + + + + + WDT_CLEAR1 + Clear Watchdog Counter when WDT_CTR1==WDT_MATCH1. In other words WDT_CTR1 divides LFCLK by (WDT_MATCH1+1). +0: Free running counter +1: Clear on match. In this mode, the minimum legal setting of WDT_MATCH1 is 1. + [10:10] + read-write + + + WDT_CASCADE1_2 + Cascade Watchdog Counters 1,2. Counter 2 increments the cycle after WDT_CTR1=WDT_MATCH1. It is allowed to cascade all three WDT counters. +0: Independent counters +1: Cascaded counters. When cascading all three counters, WDT_CLEAR1 must be 1. + [11:11] + read-write + + + WDT_MODE2 + Watchdog Counter 2 Mode. + [16:16] + read-write + + + NOTHING + Free running counter with no interrupt requests + 0 + + + INT + Free running counter with interrupt request that occurs one LFCLK cycle after the specified bit in CTR2 toggles (see WDT_BITS2). + 1 + + + + + WDT_BITS2 + Bit to observe for WDT_INT2: +0: Assert after bit0 of WDT_CTR2 toggles (one int every tick) +... +31: Assert after bit31 of WDT_CTR2 toggles (one int every 2^31 ticks) + [28:24] + read-write + + + + + MCWDT_CTL + Multi-Counter Watchdog Counter Control + 0x14 + 32 + read-write + 0x0 + 0xB0B0B + + + WDT_ENABLE0 + Enable subcounter 0. May take up to 2 LFCLK cycles to take effect. +0: Counter is disabled (not clocked) +1: Counter is enabled (counting up) + [0:0] + read-write + + + WDT_ENABLED0 + Indicates actual state of counter. May lag WDT_ENABLE0 by up to two LFCLK cycles. + [1:1] + read-only + + + WDT_RESET0 + Resets counter 0 back to 0000. Hardware will reset this bit after counter was reset. This will take up to one LFCLK cycle to take effect. + [3:3] + read-write + + + WDT_ENABLE1 + Enable subcounter 1. May take up to 2 LFCLK cycles to take effect. +0: Counter is disabled (not clocked) +1: Counter is enabled (counting up) + [8:8] + read-write + + + WDT_ENABLED1 + Indicates actual state of counter. May lag WDT_ENABLE1 by up to two LFCLK cycles. + [9:9] + read-only + + + WDT_RESET1 + Resets counter 0 back to 0000. Hardware will reset this bit after counter was reset. This will take up to one LFCLK cycle to take effect. + [11:11] + read-write + + + WDT_ENABLE2 + Enable subcounter 2. May take up to 2 LFCLK cycles to take effect. +0: Counter is disabled (not clocked) +1: Counter is enabled (counting up) + [16:16] + read-write + + + WDT_ENABLED2 + Indicates actual state of counter. May lag WDT_ENABLE2 by up to two LFCLK cycles. + [17:17] + read-only + + + WDT_RESET2 + Resets counter 0 back to 0000. Hardware will reset this bit after counter was reset. This will take up to one LFCLK cycle to take effect. + [19:19] + read-write + + + + + MCWDT_INTR + Multi-Counter Watchdog Counter Interrupt Register + 0x18 + 32 + read-write + 0x0 + 0x7 + + + MCWDT_INT0 + MCWDT Interrupt Request for sub-counter 0. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. Clearing this bit also prevents Reset from happening when WDT_MODE0=3. + [0:0] + read-write + + + MCWDT_INT1 + MCWDT Interrupt Request for sub-counter 1. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. Clearing this bit also prevents Reset from happening when WDT_MODE1=3. + [1:1] + read-write + + + MCWDT_INT2 + MCWDT Interrupt Request for sub-counter 2. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. Clearing this bit also prevents Reset from happening when WDT_MODE2=3. + [2:2] + read-write + + + + + MCWDT_INTR_SET + Multi-Counter Watchdog Counter Interrupt Set Register + 0x1C + 32 + read-write + 0x0 + 0x7 + + + MCWDT_INT0 + Set interrupt for MCWDT_INT0 + [0:0] + read-write + + + MCWDT_INT1 + Set interrupt for MCWDT_INT1 + [1:1] + read-write + + + MCWDT_INT2 + Set interrupt for MCWDT_INT2 + [2:2] + read-write + + + + + MCWDT_INTR_MASK + Multi-Counter Watchdog Counter Interrupt Mask Register + 0x20 + 32 + read-write + 0x0 + 0x7 + + + MCWDT_INT0 + Mask for sub-counter 0 + [0:0] + read-write + + + MCWDT_INT1 + Mask for sub-counter 1 + [1:1] + read-write + + + MCWDT_INT2 + Mask for sub-counter 2 + [2:2] + read-write + + + + + MCWDT_INTR_MASKED + Multi-Counter Watchdog Counter Interrupt Masked Register + 0x24 + 32 + read-only + 0x0 + 0x7 + + + MCWDT_INT0 + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + MCWDT_INT1 + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + MCWDT_INT2 + Logical and of corresponding request and mask bits. + [2:2] + read-only + + + + + MCWDT_LOCK + Multi-Counter Watchdog Counter Lock Register + 0x28 + 32 + read-write + 0x0 + 0xC0000000 + + + MCWDT_LOCK + Prohibits writing control and configuration registers related to this MCWDT when not equal 0 (as specified in the other register descriptions). Requires at least two different writes to unlock. +Note that this field is 2 bits to force multiple writes only. Each MCWDT has a separate local lock. LFCLK settings are locked by the global WDT_LOCK register, and this register has no effect on that. + [31:30] + read-write + + + NO_CHG + No effect + 0 + + + CLR0 + Clears bit 0 + 1 + + + CLR1 + Clears bit 1 + 2 + + + SET01 + Sets both bits 0 and 1 + 3 + + + + + + + + 16 + 4 + CLK_DSI_SELECT[%s] + Clock DSI Select Register + 0x300 + 32 + read-write + 0x0 + 0x1F + + + DSI_MUX + Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH<i> using CLK_SELECT_PATH register. Using the output of this mux as HFCLK source will result in undefined behavior. It can be used to clocks to DSI or to the reference inputs of FLL/PLL, subject to the frequency limits of those circuits. This mux is not glitch free, so do not change the selection while it is an actively selected clock. + [4:0] + read-write + + + DSI_OUT0 + DSI0 - dsi_out[0] + 0 + + + DSI_OUT1 + DSI1 - dsi_out[1] + 1 + + + DSI_OUT2 + DSI2 - dsi_out[2] + 2 + + + DSI_OUT3 + DSI3 - dsi_out[3] + 3 + + + DSI_OUT4 + DSI4 - dsi_out[4] + 4 + + + DSI_OUT5 + DSI5 - dsi_out[5] + 5 + + + DSI_OUT6 + DSI6 - dsi_out[6] + 6 + + + DSI_OUT7 + DSI7 - dsi_out[7] + 7 + + + DSI_OUT8 + DSI8 - dsi_out[8] + 8 + + + DSI_OUT9 + DSI9 - dsi_out[9] + 9 + + + DSI_OUT10 + DSI10 - dsi_out[10] + 10 + + + DSI_OUT11 + DSI11 - dsi_out[11] + 11 + + + DSI_OUT12 + DSI12 - dsi_out[12] + 12 + + + DSI_OUT13 + DSI13 - dsi_out[13] + 13 + + + DSI_OUT14 + DSI14 - dsi_out[14] + 14 + + + DSI_OUT15 + DSI15 - dsi_out[15] + 15 + + + ILO + ILO - Internal Low-speed Oscillator + 16 + + + WCO + WCO - Watch-Crystal Oscillator + 17 + + + ALTLF + ALTLF - Alternate Low-Frequency Clock + 18 + + + PILO + PILO - Precision Internal Low-speed Oscillator + 19 + + + + + + + 16 + 4 + CLK_PATH_SELECT[%s] + Clock Path Select Register + 0x340 + 32 + read-write + 0x0 + 0x7 + + + PATH_MUX + Selects a source for clock PATH<i>. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. + [2:0] + read-write + + + IMO + IMO - Internal R/C Oscillator + 0 + + + EXTCLK + EXTCLK - External Clock Pin + 1 + + + ECO + ECO - External-Crystal Oscillator + 2 + + + ALTHF + ALTHF - Alternate High-Frequency clock input (product-specific clock) + 3 + + + DSI_MUX + DSI_MUX - Output of DSI mux for this path. Using a DSI source directly as root of HFCLK will result in undefined behavior. + 4 + + + + + + + 16 + 4 + CLK_ROOT_SELECT[%s] + Clock Root Select Register + 0x380 + 32 + read-write + 0x0 + 0x8000003F + + + ROOT_MUX + Selects a clock path as the root of HFCLK<k> and for SRSS DSI input <k>. Use CLK_SELECT_PATH[i] to configure the desired path. Some paths may have FLL or PLL available (product-specific), and the control and bypass mux selections of these are in other registers. Configure the FLL using CLK_FLL_CONFIG register. Configure a PLL using the related CLK_PLL_CONFIG[k] register. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. + [3:0] + read-write + + + PATH0 + Select PATH0 (can be configured for FLL) + 0 + + + PATH1 + Select PATH1 (can be configured for PLL0, if available in the product) + 1 + + + PATH2 + Select PATH2 (can be configured for PLL1, if available in the product) + 2 + + + PATH3 + Select PATH3 (can be configured for PLL2, if available in the product) + 3 + + + PATH4 + Select PATH4 (can be configured for PLL3, if available in the product) + 4 + + + PATH5 + Select PATH5 (can be configured for PLL4, if available in the product) + 5 + + + PATH6 + Select PATH6 (can be configured for PLL5, if available in the product) + 6 + + + PATH7 + Select PATH7 (can be configured for PLL6, if available in the product) + 7 + + + PATH8 + Select PATH8 (can be configured for PLL7, if available in the product) + 8 + + + PATH9 + Select PATH9 (can be configured for PLL8, if available in the product) + 9 + + + PATH10 + Select PATH10 (can be configured for PLL9, if available in the product) + 10 + + + PATH11 + Select PATH11 (can be configured for PLL10, if available in the product) + 11 + + + PATH12 + Select PATH12 (can be configured for PLL11, if available in the product) + 12 + + + PATH13 + Select PATH13 (can be configured for PLL12, if available in the product) + 13 + + + PATH14 + Select PATH14 (can be configured for PLL13, if available in the product) + 14 + + + PATH15 + Select PATH15 (can be configured for PLL14, if available in the product) + 15 + + + + + ROOT_DIV + Selects predivider value for this clock root and DSI input. + [5:4] + read-write + + + NO_DIV + Transparent mode, feed through selected clock source w/o dividing. + 0 + + + DIV_BY_2 + Divide selected clock source by 2 + 1 + + + DIV_BY_4 + Divide selected clock source by 4 + 2 + + + DIV_BY_8 + Divide selected clock source by 8 + 3 + + + + + ENABLE + Enable for this clock root. All clock roots default to disabled (ENABLE==0) except HFCLK0, which cannot be disabled. + [31:31] + read-write + + + + + CLK_SELECT + Clock selection register + 0x500 + 32 + read-write + 0x0 + 0xFF03 + + + LFCLK_SEL + Select source for LFCLK. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register. + [1:0] + read-write + + + ILO + ILO - Internal Low-speed Oscillator + 0 + + + WCO + WCO - Watch-Crystal Oscillator. Requires Backup domain to be present and properly configured (including external watch crystal, if used). + 1 + + + ALTLF + ALTLF - Alternate Low-Frequency Clock. Capability is product-specific + 2 + + + PILO + PILO - Precision ILO. If present, it works in DEEPSLEEP and higher modes. Does not work in HIBERNATE mode. + 3 + + + + + PUMP_SEL + Selects clock PATH<k>, where k=PUMP_SEL. The output of this mux goes to the PUMP_DIV to make PUMPCLK Each product has a specific number of available clock paths. Selecting a path that is not implemented on a product will result in undefined behavior. Note that this is not a glitch free mux. + [11:8] + read-write + + + PUMP_DIV + Division ratio for PUMPCLK. Uses selected PUMP_SEL clock as the source. + [14:12] + read-write + + + NO_DIV + Transparent mode, feed through selected clock source w/o dividing. + 0 + + + DIV_BY_2 + Divide selected clock source by 2 + 1 + + + DIV_BY_4 + Divide selected clock source by 4 + 2 + + + DIV_BY_8 + Divide selected clock source by 8 + 3 + + + DIV_BY_16 + Divide selected clock source by 16 + 4 + + + + + PUMP_ENABLE + Enable the pump clock. PUMP_ENABLE and the PUMP_SEL mux are not glitch-free to minimize side-effects, avoid changing the PUMP_SEL and PUMP_DIV while changing PUMP_ENABLE. To change the settings, do the following: +1) If the pump clock is enabled, write PUMP_ENABLE=0 without changing PUMP_SEL and PUMP_DIV. +2) Change PUMP_SEL and PUMP_DIV to desired settings with PUMP_ENABLE=0. +3) Write PUMP_ENABLE=1 without changing PUMP_SEL and PUMP_DIV. + [15:15] + read-write + + + + + CLK_TIMER_CTL + Timer Clock Control Register + 0x504 + 32 + read-write + 0x70000 + 0x80FF0301 + + + TIMER_SEL + Select source for TIMERCLK. The output of this mux can be further divided using TIMER_DIV. + [0:0] + read-write + + + IMO + IMO - Internal Main Oscillator + 0 + + + HF0_DIV + Select the output of the predivider configured by TIMER_HF0_DIV. + 1 + + + + + TIMER_HF0_DIV + Predivider used when HF0_DIV is selected in TIMER_SEL. If HFCLK0 frequency is less than 100MHz and has approximately 50 percent duty cycle, then no division is required (NO_DIV). Otherwise, select a divide ratio of 2, 4, or 8 before selected HF0_DIV as the timer clock. + [9:8] + read-write + + + NO_DIV + Transparent mode, feed through selected clock source w/o dividing or correcting duty cycle. + 0 + + + DIV_BY_2 + Divide HFCLK0 by 2. + 1 + + + DIV_BY_4 + Divide HFCLK0 by 4. + 2 + + + DIV_BY_8 + Divide HFCLK0 by 8. + 3 + + + + + TIMER_DIV + Divide selected timer clock source by (1+TIMER_DIV). The output of this divider is TIMERCLK Allows for integer divisions in the range [1, 256]. Do not change this setting while the timer is enabled. + [23:16] + read-write + + + ENABLE + Enable for TIMERCLK. +0: TIMERCLK is off +1: TIMERCLK is enabled + [31:31] + read-write + + + + + CLK_ILO_CONFIG + ILO Configuration + 0x50C + 32 + read-write + 0x80000000 + 0x80000001 + + + ILO_BACKUP + If backup domain is present on this product, this register indicates that ILO should stay enabled for use by backup domain during XRES, HIBERNATE mode, and through power-related resets like BOD on VDDD/VCCD. Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register. +0: ILO turns off at XRES/BOD event or HIBERNATE entry. +1: ILO remains on if backup domain is present and powered even for XRES/BOD or HIBERNATE entry. + [0:0] + read-write + + + ENABLE + Master enable for ILO. Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register. After enabling, it takes at most two cycles to reach the accuracy spec. + [31:31] + read-write + + + + + CLK_IMO_CONFIG + IMO Configuration + 0x510 + 32 + read-write + 0x80000000 + 0x80000000 + + + ENABLE + Master enable for IMO oscillator. This bit must be high at all times for all functions to work properly. Hardware will automatically disable the IMO during HIBERNATE and XRES. It will automatically disable during DEEPSLEEP if CLK_MFO_CONFIG.DPSLP_ENABLE==0. + [31:31] + read-write + + + + + CLK_OUTPUT_FAST + Fast Clock Output Select Register + 0x514 + 32 + read-write + 0x0 + 0xFFF0FFF + + + FAST_SEL0 + Select signal for fast clock output #0 + [3:0] + read-write + + + NC + Disabled - output is 0. For power savings, clocks are blocked before entering any muxes, including PATH_SEL0 and HFCLK_SEL0. + 0 + + + ECO + External Crystal Oscillator (ECO) + 1 + + + EXTCLK + External clock input (EXTCLK) + 2 + + + ALTHF + Alternate High-Frequency (ALTHF) clock input to SRSS + 3 + + + TIMERCLK + Timer clock. It is grouped with the fast clocks because it may be a gated version of a fast clock, and therefore may have a short high pulse. + 4 + + + PATH_SEL0 + Selects the clock path chosen by PATH_SEL0 field + 5 + + + HFCLK_SEL0 + Selects the output of the HFCLK_SEL0 mux + 6 + + + SLOW_SEL0 + Selects the output of CLK_OUTPUT_SLOW.SLOW_SEL0 + 7 + + + + + PATH_SEL0 + Selects a clock path to use in fast clock output #0 logic. 0: FLL output +1-15: PLL output on path1-path15 (if available) + [7:4] + read-write + + + HFCLK_SEL0 + Selects a HFCLK tree for use in fast clock output #0 + [11:8] + read-write + + + FAST_SEL1 + Select signal for fast clock output #1 + [19:16] + read-write + + + NC + Disabled - output is 0. For power savings, clocks are blocked before entering any muxes, including PATH_SEL1 and HFCLK_SEL1. + 0 + + + ECO + External Crystal Oscillator (ECO) + 1 + + + EXTCLK + External clock input (EXTCLK) + 2 + + + ALTHF + Alternate High-Frequency (ALTHF) clock input to SRSS + 3 + + + TIMERCLK + Timer clock. It is grouped with the fast clocks because it may be a gated version of a fast clock, and therefore may have a short high pulse. + 4 + + + PATH_SEL1 + Selects the clock path chosen by PATH_SEL1 field + 5 + + + HFCLK_SEL1 + Selects the output of the HFCLK_SEL1 mux + 6 + + + SLOW_SEL1 + Selects the output of CLK_OUTPUT_SLOW.SLOW_SEL1 + 7 + + + + + PATH_SEL1 + Selects a clock path to use in fast clock output #1 logic. 0: FLL output +1-15: PLL output on path1-path15 (if available) + [23:20] + read-write + + + HFCLK_SEL1 + Selects a HFCLK tree for use in fast clock output #1 logic + [27:24] + read-write + + + + + CLK_OUTPUT_SLOW + Slow Clock Output Select Register + 0x518 + 32 + read-write + 0x0 + 0xFF + + + SLOW_SEL0 + Select signal for slow clock output #0 + [3:0] + read-write + + + NC + Disabled - output is 0. For power savings, clocks are blocked before entering any muxes. + 0 + + + ILO + Internal Low Speed Oscillator (ILO) + 1 + + + WCO + Watch-Crystal Oscillator (WCO) + 2 + + + BAK + Root of the Backup domain clock tree (BAK) + 3 + + + ALTLF + Alternate low-frequency clock input to SRSS (ALTLF) + 4 + + + LFCLK + Root of the low-speed clock tree (LFCLK) + 5 + + + IMO + Internal Main Oscillator (IMO). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit. + 6 + + + SLPCTRL + Sleep Controller clock (SLPCTRL). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit. + 7 + + + PILO + Precision Internal Low Speed Oscillator (PILO) + 8 + + + + + SLOW_SEL1 + Select signal for slow clock output #1 + [7:4] + read-write + + + NC + Disabled - output is 0. For power savings, clocks are blocked before entering any muxes. + 0 + + + ILO + Internal Low Speed Oscillator (ILO) + 1 + + + WCO + Watch-Crystal Oscillator (WCO) + 2 + + + BAK + Root of the Backup domain clock tree (BAK) + 3 + + + ALTLF + Alternate low-frequency clock input to SRSS (ALTLF) + 4 + + + LFCLK + Root of the low-speed clock tree (LFCLK) + 5 + + + IMO + Internal Main Oscillator (IMO). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit. + 6 + + + SLPCTRL + Sleep Controller clock (SLPCTRL). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit. + 7 + + + PILO + Precision Internal Low Speed Oscillator (PILO) + 8 + + + + + + + CLK_CAL_CNT1 + Clock Calibration Counter 1 + 0x51C + 32 + read-write + 0x80000000 + 0x80FFFFFF + + + CAL_COUNTER1 + Down-counter clocked on fast clock output #0 (see CLK_OUTPUT_FAST). This register always reads as zero. Counting starts internally when this register is written with a nonzero value. CAL_COUNTER_DONE goes immediately low to indicate that the counter has started and will be asserted when the counters are done. Do not write this field unless CAL_COUNTER_DONE==1. Both clocks must be running or the measurement will not complete. A stalled counter can be recovered by selecting valid clocks, waiting until the measurement completes, and discarding the first result. + [23:0] + read-write + + + CAL_COUNTER_DONE + Status bit indicating that the internal counter #1 is finished counting and CLK_CAL_CNT2.COUNTER stopped counting up + [31:31] + read-only + + + + + CLK_CAL_CNT2 + Clock Calibration Counter 2 + 0x520 + 32 + read-only + 0x0 + 0xFFFFFF + + + CAL_COUNTER2 + Up-counter clocked on fast clock output #1 (see CLK_OUTPUT_FAST). When CLK_CAL_CNT1.CAL_COUNTER_DONE==1, the counter is stopped and can be read by SW. Do not read this value unless CAL_COUNTER_DONE==1. The expected final value is related to the ratio of clock frequencies used for the two counters and the value loaded into counter 1: CLK_CAL_CNT2.COUNTER=(F_cnt2/F_cnt1)*(CLK_CAL_CNT1.COUNTER) + [23:0] + read-only + + + + + CLK_ECO_CONFIG + ECO Configuration Register + 0x52C + 32 + read-write + 0x2 + 0x80000002 + + + AGC_EN + Automatic Gain Control (AGC) enable. When set, the oscillation amplitude is controlled to the level selected by ECO_TRIM0.ATRIM. When low, the amplitude is not explicitly controlled and can be as high as the vddd supply. WARNING: use care when disabling AGC because driving a crystal beyond its rated limit can permanently damage the crystal. + [1:1] + read-write + + + ECO_EN + Master enable for ECO oscillator. + [31:31] + read-write + + + + + CLK_ECO_STATUS + ECO Status Register + 0x530 + 32 + read-only + 0x0 + 0x3 + + + ECO_OK + Indicates the ECO internal oscillator circuit has sufficient amplitude. It may not meet the PPM accuracy or duty cycle spec. + [0:0] + read-only + + + ECO_READY + Indicates the ECO internal oscillator circuit has had enough time to fully stabilize. This is the output of a counter since ECO was enabled, and it does not check the ECO output. It is recommended to also confirm ECO_OK==1. + [1:1] + read-only + + + + + CLK_PILO_CONFIG + Precision ILO Configuration Register + 0x53C + 32 + read-write + 0x80 + 0xE00003FF + + + PILO_FFREQ + Fine frequency trim allowing +/-250ppm accuracy with periodic calibration. The nominal step size of the LSB is 8Hz. + [9:0] + read-write + + + PILO_CLK_EN + Enable the PILO clock output. See PILO_EN field for required sequencing. + [29:29] + read-write + + + PILO_RESET_N + Reset the PILO. See PILO_EN field for required sequencing. + [30:30] + read-write + + + PILO_EN + Enable PILO. When enabling PILO, set PILO_EN=1, wait 1ms, then PILO_RESET_N=1 and PILO_CLK_EN=1. When disabling PILO, clear PILO_EN=0, PILO_RESET_N=0, and PLO_CLK_EN=0 in the same write cycle. + [31:31] + read-write + + + + + CLK_MF_SELECT + Medium Frequency Clock Select Register + 0x544 + 32 + read-write + 0x0 + 0x8000FF07 + + + MFCLK_SEL + Select source for MFCLK (clk_mf). Note that not all products support all clock sources. Selecting a clock source that is not supported results in undefined behavior. + [2:0] + read-write + + + MFO + MFO - medium frequency oscillator + 0 + + + + + MFCLK_DIV + Divide selected clock source by (1+MFCLK_DIV). The output of this divider is MFCLK (clk_mf). Allows for integer divisions in the range [1, 256]. Do not change this setting while ENABLE==1. + [15:8] + read-write + + + ENABLE + Enable for MFCLK (clk_mf). + [31:31] + read-write + + + + + CLK_MFO_CONFIG + MFO Configuration Register + 0x548 + 32 + read-write + 0x80000000 + 0xC0000000 + + + DPSLP_ENABLE + Enable for MFO during DEEPSLEEP. This bit is ignored when ENABLE==0. When ENABLE==1: +0: MFO is automatically disabled during DEEPSLEEP and enables upon wakeup; +1: MFO is kept enabled throughout DEEPSLEEP + [30:30] + read-write + + + ENABLE + Enable for MFO. + [31:31] + read-write + + + + + CLK_FLL_CONFIG + FLL Configuration Register + 0x580 + 32 + read-write + 0x1000000 + 0x8103FFFF + + + FLL_MULT + Multiplier to determine CCO frequency in multiples of the frequency of the selected reference clock (Fref). + +Ffll = (FLL_MULT) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV+1) + [17:0] + read-write + + + FLL_OUTPUT_DIV + Control bits for Output divider. Set the divide value before enabling the FLL, and do not change it while FLL is enabled. +0: no division +1: divide by 2 + [24:24] + read-write + + + FLL_ENABLE + Master enable for FLL. The FLL requires firmware sequencing when enabling, disabling, and entering/exiting DEEPSLEEP. + +To enable the FLL, first enable the CCO by writing CLK_FLL_CONFIG4.CCO_ENABLE=1 and wait until CLK_FLL_STATUS.CCO_READY==1. Next, ensure the reference clock has stabilized and CLK_FLL_CONFIG3.BYPASS_SEL=FLL_REF. Next, write FLL_ENABLE=1 and wait until CLK_FLL_STATUS.LOCKED==1. Finally, write CLK_FLL_CONFIG3.BYPASS_SEL=FLL_OUT to switch to the FLL output. It takes seven reference clock cycles plus four FLL output cycles to switch to the FLL output. Do not disable the FLL before this time completes. + +To disable the FLL, write CLK_FLL_CONFIG3.BYPASS_SEL=FLL_REF and (optionally) read the same register to ensure the write completes. Then, wait at least seven FLL reference clock cycles before disabling it with FLL_ENABLE=0. Lastly, disable the CCO by writing CLK_FLL_CONFIG4.CCO_ENABLE=0. + +Before entering DEEPSLEEP, either disable the FLL using above sequence or use the following procedure to deselect/select it before/after DEEPSLEEP. Before entering DEEPSLEEP, write CLK_FLL_CONFIG3.BYPASS_SEL=FLL_REF to change the FLL to use its reference clock. After DEEPSLEEP wakeup, wait until CLK_FLL_STATUS.LOCKED==1 and then write CLK_FLL_CONFIG3.BYPASS_SEL=FLL_OUT to switch to the FLL output. + +0: Block is powered off +1: Block is powered on + [31:31] + read-write + + + + + CLK_FLL_CONFIG2 + FLL Configuration Register 2 + 0x584 + 32 + read-write + 0x20001 + 0x1FF1FFF + + + FLL_REF_DIV + Control bits for reference divider. Set the divide value before enabling the FLL, and do not change it while FLL is enabled. +0: illegal (undefined behavior) +1: divide by 1 +... +8191: divide by 8191 + [12:0] + read-write + + + LOCK_TOL + Lock tolerance sets the error threshold for when the FLL output is considered locked to the reference input. A high tolerance can be used to lock more quickly or to track a less accurate source. The tolerance should be set so that the FLL does not unlock under normal conditions. The tolerance is the allowed difference between the count value for the ideal formula and the measured value. +0: tolerate error of 1 count value +1: tolerate error of 2 count values +... +511: tolerate error of 512 count values + [24:16] + read-write + + + + + CLK_FLL_CONFIG3 + FLL Configuration Register 3 + 0x588 + 32 + read-write + 0x2800 + 0x301FFFFF + + + FLL_LF_IGAIN + FLL Loop Filter Gain Setting #1. The proportional gain is the sum of FLL_LF_IGAIN and FLL_LF_PGAIN. +0: 1/256 +1: 1/128 +2: 1/64 +3: 1/32 +4: 1/16 +5: 1/8 +6: 1/4 +7: 1/2 +8: 1.0 +9: 2.0 +10: 4.0 +11: 8.0 +>=12: illegal + [3:0] + read-write + + + FLL_LF_PGAIN + FLL Loop Filter Gain Setting #2. The proportional gain is the sum of FLL_LF_IGAIN and FLL_LF_PGAIN. +0: 1/256 +1: 1/128 +2: 1/64 +3: 1/32 +4: 1/16 +5: 1/8 +6: 1/4 +7: 1/2 +8: 1.0 +9: 2.0 +10: 4.0 +11: 8.0 +>=12: illegal + [7:4] + read-write + + + SETTLING_COUNT + Number of undivided reference clock cycles to wait after changing the CCO trim until the loop measurement restarts. A delay allows the CCO output to settle and gives a more accurate measurement. The default is tuned to an 8MHz reference clock since the IMO is expected to be the most common use case. +0: no settling time +1: wait one reference clock cycle +... +8191: wait 8191 reference clock cycles + [20:8] + read-write + + + BYPASS_SEL + Bypass mux located just after FLL output. See FLL_ENABLE description for instructions on how to use this field when enabling/disabling the FLL. + [29:28] + read-write + + + AUTO + N/A + 0 + + + AUTO1 + N/A + 1 + + + FLL_REF + Select FLL reference input (bypass mode). Ignores lock indicator + 2 + + + FLL_OUT + Select FLL output. Ignores lock indicator. + 3 + + + + + + + CLK_FLL_CONFIG4 + FLL Configuration Register 4 + 0x58C + 32 + read-write + 0xFF + 0xC1FF07FF + + + CCO_LIMIT + Maximum CCO offset allowed (used to prevent FLL dynamics from selecting an CCO frequency that the logic cannot support) + [7:0] + read-write + + + CCO_RANGE + Frequency range of CCO + [10:8] + read-write + + + RANGE0 + Target frequency is in range [48, 64) MHz + 0 + + + RANGE1 + Target frequency is in range [64, 85) MHz + 1 + + + RANGE2 + Target frequency is in range [85, 113) MHz + 2 + + + RANGE3 + Target frequency is in range [113, 150) MHz + 3 + + + RANGE4 + Target frequency is in range [150, 200] MHz + 4 + + + + + CCO_FREQ + CCO frequency code. This is updated by HW when the FLL is enabled. It can be manually updated to use the CCO in an open loop configuration. The meaning of each frequency code depends on the range. + [24:16] + read-write + + + CCO_HW_UPDATE_DIS + Disable CCO frequency update by FLL hardware +0: Hardware update of CCO settings is allowed. Use this setting for normal FLL operation. +1: Hardware update of CCO settings is disabled. Use this setting for open-loop FLL operation. + [30:30] + read-write + + + CCO_ENABLE + Enable the CCO. It is required to enable the CCO before using the FLL. +0: Block is powered off +1: Block is powered on + [31:31] + read-write + + + + + CLK_FLL_STATUS + FLL Status Register + 0x590 + 32 + read-write + 0x0 + 0x7 + + + LOCKED + FLL Lock Indicator. LOCKED is high when FLL is within CLK_FLL_CONFIG2.LOCK_TOL. If FLL is outside LOCK_TOL, LOCKED goes low. Note that this can happen during normal operation, if FLL needs to recalculate due to a change in the reference clock, change in voltage, or change in temperature. + [0:0] + read-only + + + UNLOCK_OCCURRED + N/A + [1:1] + read-write + + + CCO_READY + This indicates that the CCO is internally settled and ready to use. + [2:2] + read-only + + + + + 15 + 4 + CLK_PLL_CONFIG[%s] + PLL Configuration Register + 0x600 + 32 + read-write + 0x20116 + 0xB81F1F7F + + + FEEDBACK_DIV + Control bits for feedback divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. +0-21: illegal (undefined behavior) +22: divide by 22 +... +112: divide by 112 +>112: illegal (undefined behavior) + [6:0] + read-write + + + REFERENCE_DIV + Control bits for reference divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. +0: illegal (undefined behavior) +1: divide by 1 +... +20: divide by 20 +others: illegal (undefined behavior) + [12:8] + read-write + + + OUTPUT_DIV + Control bits for Output divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. +0: illegal (undefined behavior) +1: illegal (undefined behavior) +2: divide by 2. Suitable for direct usage as HFCLK source. +... +16: divide by 16. Suitable for direct usage as HFCLK source. +>16: illegal (undefined behavior) + [20:16] + read-write + + + PLL_LF_MODE + VCO frequency range selection. Configure this bit according to the targeted VCO frequency. Do not change this setting while the PLL is enabled. +0: VCO frequency is [200MHz, 400MHz] +1: VCO frequency is [170MHz, 200MHz) + [27:27] + read-write + + + BYPASS_SEL + Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running. + [29:28] + read-write + + + AUTO + Automatic using lock indicator. When unlocked, automatically selects PLL reference input (bypass mode). When locked, automatically selects PLL output. + 0 + + + AUTO1 + Same as AUTO + 1 + + + PLL_REF + Select PLL reference input (bypass mode). Ignores lock indicator + 2 + + + PLL_OUT + Select PLL output. Ignores lock indicator. + 3 + + + + + ENABLE + Master enable for PLL. Setup FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV at least one cycle before setting ENABLE=1. To disable the PLL, first deselect it using .BYPASS_SEL=PLL_REF, wait at least six PLL clock cycles, and then disable it with .ENABLE=0. + +Fpll = (FEEDBACK_DIV) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV) + +0: Block is disabled +1: Block is enabled + [31:31] + read-write + + + + + 15 + 4 + CLK_PLL_STATUS[%s] + PLL Status Register + 0x640 + 32 + read-write + 0x0 + 0x3 + + + LOCKED + PLL Lock Indicator + [0:0] + read-only + + + UNLOCK_OCCURRED + This bit sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware. + [1:1] + read-write + + + + + SRSS_INTR + SRSS Interrupt Register + 0x700 + 32 + read-write + 0x0 + 0x23 + + + WDT_MATCH + WDT Interrupt Request. This bit is set each time WDT_COUNTR==WDT_MATCH. W1C also feeds the watch dog. Missing 2 interrupts in a row will generate a reset. Due to internal synchronization, it takes 2 SYSCLK cycles to update after a W1C. + [0:0] + read-write + + + HVLVD1 + Interrupt for low voltage detector HVLVD1 + [1:1] + read-write + + + CLK_CAL + Clock calibration counter is done. This field is reset during DEEPSLEEP mode. + [5:5] + read-write + + + + + SRSS_INTR_SET + SRSS Interrupt Set Register + 0x704 + 32 + read-write + 0x0 + 0x23 + + + WDT_MATCH + Set interrupt for low voltage detector WDT_MATCH + [0:0] + read-write + + + HVLVD1 + Set interrupt for low voltage detector HVLVD1 + [1:1] + read-write + + + CLK_CAL + Set interrupt for clock calibration counter done. This field is reset during DEEPSLEEP mode. + [5:5] + read-write + + + + + SRSS_INTR_MASK + SRSS Interrupt Mask Register + 0x708 + 32 + read-write + 0x0 + 0x23 + + + WDT_MATCH + Mask for watchdog timer. Clearing this bit will not forward the interrupt to the CPU. It will not, however, disable the WDT reset generation on 2 missed interrupts. When WDT resets the chip, it also internally pends an interrupt that survives the reset. To prevent unintended ISR execution, clear SRSS_INTR.WDT_MATCH before setting this bit. + [0:0] + read-write + + + HVLVD1 + Mask for low voltage detector HVLVD1 + [1:1] + read-write + + + CLK_CAL + Mask for clock calibration done + [5:5] + read-write + + + + + SRSS_INTR_MASKED + SRSS Interrupt Masked Register + 0x70C + 32 + read-only + 0x0 + 0x23 + + + WDT_MATCH + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + HVLVD1 + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + CLK_CAL + Logical and of corresponding request and mask bits. + [5:5] + read-only + + + + + SRSS_INTR_CFG + SRSS Interrupt Configuration Register + 0x710 + 32 + read-write + 0x0 + 0x3 + + + HVLVD1_EDGE_SEL + Sets which edge(s) will trigger an IRQ for HVLVD1 + [1:0] + read-write + + + DISABLE + Disabled + 0 + + + RISING + Rising edge + 1 + + + FALLING + Falling edge + 2 + + + BOTH + Both rising and falling edges + 3 + + + + + + + RES_CAUSE + Reset Cause Observation Register + 0x800 + 32 + read-write + 0x0 + 0x1FF + + + RESET_WDT + A basic WatchDog Timer (WDT) reset has occurred since last power cycle. + [0:0] + read-write + + + RESET_ACT_FAULT + Fault logging system requested a reset from its Active logic. + [1:1] + read-write + + + RESET_DPSLP_FAULT + Fault logging system requested a reset from its DeepSleep logic. + [2:2] + read-write + + + RESET_CSV_WCO_LOSS + Clock supervision logic requested a reset due to loss of a watch-crystal clock. + [3:3] + read-write + + + RESET_SOFT + A CPU requested a system reset through it's SYSRESETREQ. This can be done via a debugger probe or in firmware. + [4:4] + read-write + + + RESET_MCWDT0 + Multi-Counter Watchdog timer reset #0 has occurred since last power cycle. + [5:5] + read-write + + + RESET_MCWDT1 + Multi-Counter Watchdog timer reset #1 has occurred since last power cycle. + [6:6] + read-write + + + RESET_MCWDT2 + Multi-Counter Watchdog timer reset #2 has occurred since last power cycle. + [7:7] + read-write + + + RESET_MCWDT3 + Multi-Counter Watchdog timer reset #3 has occurred since last power cycle. + [8:8] + read-write + + + + + RES_CAUSE2 + Reset Cause Observation Register 2 + 0x804 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + RESET_CSV_HF_LOSS + Clock supervision logic requested a reset due to loss of a high-frequency clock. Each bit index K corresponds to a HFCLK<K>. Unimplemented clock bits return zero. + [15:0] + read-write + + + RESET_CSV_HF_FREQ + Clock supervision logic requested a reset due to frequency error of high-frequency clock. Each bit index K corresponds to a HFCLK<K>. Unimplemented clock bits return zero. + [31:16] + read-write + + + + + PWR_TRIM_REF_CTL + Reference Trim Register + 0x7F00 + 32 + read-write + 0x70F00000 + 0xF1FF5FFF + + + ACT_REF_TCTRIM + Active-Reference temperature trim. This register is only reset by XRES/POR/BOD/HIBERNATE. +0 -> default setting at POR; not for trimming use +others -> normal trim range + [3:0] + read-write + + + ACT_REF_ITRIM + Active-Reference current trim. This register is only reset by XRES/POR/BOD/HIBERNATE. +0 -> default setting at POR; not for trimming use +others -> normal trim range + [7:4] + read-write + + + ACT_REF_ABSTRIM + Active-Reference absolute voltage trim. This register is only reset by XRES/POR/BOD/HIBERNATE. +0 -> default setting at POR; not for trimming use +others -> normal trim range + [12:8] + read-write + + + ACT_REF_IBOOST + Active-Reference current boost. This register is only reset by XRES/POR/BOD/HIBERNATE. +0: normal operation +others: risk mitigation + [14:14] + read-write + + + DPSLP_REF_TCTRIM + DeepSleep-Reference temperature trim. This register is only reset by XRES/POR/BOD/HIBERNATE. +0 -> default setting at POR; not for trimming use +others -> normal trim range + [19:16] + read-write + + + DPSLP_REF_ABSTRIM + DeepSleep-Reference absolute voltage trim. This register is only reset by XRES/POR/BOD/HIBERNATE. + [24:20] + read-write + + + DPSLP_REF_ITRIM + DeepSleep current reference trim. This register is only reset by XRES/POR/BOD/HIBERNATE. + [31:28] + read-write + + + + + PWR_TRIM_BODOVP_CTL + BOD/OVP Trim Register + 0x7F04 + 32 + read-write + 0x40D04 + 0xFDFF7 + + + HVPORBOD_TRIPSEL + HVPORBOD trip point selection. Monitors vddd. This register is only reset by XRES/POR/BOD/HIBERNATE. + [2:0] + read-write + + + HVPORBOD_OFSTRIM + HVPORBOD offset trim. This register is only reset by XRES/POR/BOD/HIBERNATE. + [6:4] + read-write + + + HVPORBOD_ITRIM + HVPORBOD current trim. This register is only reset by XRES/POR/BOD/HIBERNATE. + [9:7] + read-write + + + LVPORBOD_TRIPSEL + LVPORBOD trip point selection. Monitors vccd. This register is only reset by XRES/POR/BOD/HIBERNATE. + [12:10] + read-write + + + LVPORBOD_OFSTRIM + LVPORBOD offset trim. This register is only reset by XRES/POR/BOD/HIBERNATE. + [16:14] + read-write + + + LVPORBOD_ITRIM + LVPORBOD current trim. This register is only reset by XRES/POR/BOD/HIBERNATE. + [19:17] + read-write + + + + + CLK_TRIM_CCO_CTL + CCO Trim Register + 0x7F08 + 32 + read-write + 0xA7000020 + 0xBF00003F + + + CCO_RCSTRIM + CCO reference current source trim. + [5:0] + read-write + + + CCO_STABLE_CNT + Terminal count for the stabilization counter from CCO_ENABLE until stable. + [29:24] + read-write + + + ENABLE_CNT + Enables the automatic stabilization counter. + [31:31] + read-write + + + + + CLK_TRIM_CCO_CTL2 + CCO Trim Register 2 + 0x7F0C + 32 + read-write + 0x884110 + 0x1FFFFFF + + + CCO_FCTRIM1 + CCO frequency 1st range calibration + [4:0] + read-write + + + CCO_FCTRIM2 + CCO frequency 2nd range calibration + [9:5] + read-write + + + CCO_FCTRIM3 + CCO frequency 3rd range calibration + [14:10] + read-write + + + CCO_FCTRIM4 + CCO frequency 4th range calibration + [19:15] + read-write + + + CCO_FCTRIM5 + CCO frequency 5th range calibration + [24:20] + read-write + + + + + PWR_TRIM_WAKE_CTL + Wakeup Trim Register + 0x7F30 + 32 + read-write + 0x0 + 0xFF + + + WAKE_DELAY + Wakeup holdoff. Spec (fastest) wake time is achieved with a setting of 0. Additional delay can be added for debugging or workaround. The delay is counted by the IMO. + [7:0] + read-write + + + + + PWR_TRIM_LVD_CTL + LVD Trim Register + 0xFF10 + 32 + read-write + 0x20 + 0x77 + + + HVLVD1_OFSTRIM + HVLVD1 offset trim + [2:0] + read-write + + + HVLVD1_ITRIM + HVLVD1 current trim + [6:4] + read-write + + + + + CLK_TRIM_ILO_CTL + ILO Trim Register + 0xFF18 + 32 + read-write + 0x2C + 0x3F + + + ILO_FTRIM + ILO frequency trims. LSB step size is 1.5 percent (typical) of the frequency. + [5:0] + read-write + + + + + PWR_TRIM_PWRSYS_CTL + Power System Trim Register + 0xFF1C + 32 + read-write + 0x17 + 0x1F + + + ACT_REG_TRIM + Trim for the Active-Regulator. This sets the output voltage level. This register is only reset by XRES/POR/BOD/HIBERNATE. The nominal output voltage is vccd=812.5mV + ACT_REG_TRIM*12.5mV. The actual output voltage will vary depending on conditions and load. The following settings are explicitly shown for convenience, and other values may be calculated using the formula: +5'h07: 900mV (nominal) +5'h17: 1100mV (nominal) + [4:0] + read-write + + + ACT_REG_BOOST + Controls the tradeoff between output current and internal operating current for the Active Regulator. The maximum output current depends on the silicon implementation, but an application may limit its maximum current to less than that. This may allow a reduction in the internal operating current of the regulator. The regulator internal operating current depends on the boost setting: +2'b00: 50uA +2'b01: 100uA +2'b10: 150uA +2'b11: 200uA + +The allowed setting is a lookup table based on the chip-specific maximum (set in factory) and an application-specific maximum (set by customer). The defaults are set assuming the application consumes the maximum allowed by the chip. +50mA chip: 2'b00 (default); +100mA chip: 2'b00 (default); +150mA chip: 50..100mA app => 2'b00, 150mA app => 2'b01 (default); +200mA chip: 50mA app => 2'b00, 100..150mA app => 2'b01, 200mA app => 2'b10 (default); +250mA chip: 50mA app => 2'b00, 100..150mA app => 2'b01, 200..250mA app => 2'b10 (default); +300mA chip: 50mA app => 2'b00, 100..150mA app => 2'b01, 200..250mA app => 2'b10, 300mA app => 2'b11 (default); + +This register is only reset by XRES/POR/BOD/HIBERNATE. + [31:30] + read-write + + + + + CLK_TRIM_ECO_CTL + ECO Trim Register + 0xFF20 + 32 + read-write + 0x1F0003 + 0x3F3FF7 + + + WDTRIM + Watch Dog Trim - Delta voltage below steady state level +0x0 - 50mV +0x1 - 75mV +0x2 - 100mV +0x3 - 125mV +0x4 - 150mV +0x5 - 175mV +0x6 - 200mV +0x7 - 225mV + [2:0] + read-write + + + ATRIM + Amplitude trim to set the crystal drive level when ECO_CONFIG.AGC_EN=1. WARNING: use care when setting this field because driving a crystal beyond its rated limit can permanently damage the crystal. +0x0 - 150mV +0x1 - 175mV +0x2 - 200mV +0x3 - 225mV +0x4 - 250mV +0x5 - 275mV +0x6 - 300mV +0x7 - 325mV +0x8 - 350mV +0x9 - 375mV +0xA - 400mV +0xB - 425mV +0xC - 450mV +0xD - 475mV +0xE - 500mV +0xF - 525mV + [7:4] + read-write + + + FTRIM + Filter Trim - 3rd harmonic oscillation + [9:8] + read-write + + + RTRIM + Feedback resistor Trim + [11:10] + read-write + + + GTRIM + Gain Trim - Startup time + [13:12] + read-write + + + ITRIM + Current Trim + [21:16] + read-write + + + + + CLK_TRIM_PILO_CTL + PILO Trim Register + 0xFF24 + 32 + read-write + 0x108500F + 0x7DFF703F + + + PILO_CFREQ + Coarse frequency trim to meet 32.768kHz +/-2 percent across PVT without calibration. The nominal step size of the LSB is 1kHz. + [5:0] + read-write + + + PILO_OSC_TRIM + Trim for current in oscillator block. + [14:12] + read-write + + + PILO_COMP_TRIM + Trim for comparator bias current. + [17:16] + read-write + + + PILO_NBIAS_TRIM + Trim for biasn by trimming sub-Vth NMOS width in beta-multiplier + [19:18] + read-write + + + PILO_RES_TRIM + Trim for beta-multiplier branch current + [24:20] + read-write + + + PILO_ISLOPE_TRIM + Trim for beta-multiplier current slope + [27:26] + read-write + + + PILO_VTDIFF_TRIM + Trim for VT-DIFF output (internal power supply) + [30:28] + read-write + + + + + CLK_TRIM_PILO_CTL2 + PILO Trim Register 2 + 0xFF28 + 32 + read-write + 0xDA10E0 + 0xFF1FFF + + + PILO_VREF_TRIM + Trim for voltage reference + [7:0] + read-write + + + PILO_IREFBM_TRIM + Trim for beta-multiplier current reference + [12:8] + read-write + + + PILO_IREF_TRIM + Trim for current reference + [23:16] + read-write + + + + + CLK_TRIM_PILO_CTL3 + PILO Trim Register 3 + 0xFF2C + 32 + read-write + 0x4800 + 0xFFFF + + + PILO_ENGOPT + Engineering options for PILO circuits +0: Short vdda to vpwr +1: Beta:mult current change +2: Iref generation Ptat current addition +3: Disable current path in secondary Beta:mult startup circuit +4: Double oscillator current +5: Switch between deep:sub:threshold and sub:threshold stacks in Vref generation block +6: Spare +7: Ptat component increase in Iref +8: vpwr_rc and vpwr_dig_rc shorting testmode +9: Switch b/w psub connection for cascode nfet for vref generation +10: Switch between sub:threshold and deep:sub:threshold stacks in comparator. +15-11: Frequency fine trim. See AKK-444 for an overview of the trim strategy. + [15:0] + read-write + + + + + + + BACKUP + SRSS Backup Domain + 0x40270000 + + 0 + 65536 + registers + + + + CTL + Control + 0x0 + 32 + read-write + 0x0 + 0xFF0F3308 + + + WCO_EN + Watch-crystal oscillator (WCO) enable. If there is a write in progress when this bit is cleared, the WCO will be internally kept on until the write completes. +After enabling the WCO software must wait until STATUS.WCO_OK=1 before configuring any component that depends on clk_lf/clk_bak, like for example RTC or WDTs. Follow the procedure in BACKUP_RTC_RW to access this bit. + [3:3] + read-write + + + CLK_SEL + Clock select for BAK clock + [9:8] + read-write + + + WCO + Watch-crystal oscillator input. + 0 + + + ALTBAK + This allows to use the LFCLK selection as an alternate backup domain clock. Note that LFCLK is not available in all power modes, and clock glitches can propagate into the backup logic when the clock is stopped. For this reason, if the WCO is intended as the clock source then choose it directly instead of routing through LFCLK. + 1 + + + + + PRESCALER + N/A + [13:12] + read-write + + + WCO_BYPASS + Configures the WCO for different board-level connections to the WCO pins. For example, this can be used to connect an external watch crystal oscillator instead of a watch crystal. In all cases, the two related GPIO pins (WCO input and output pins) must be configured as analog connections using GPIO registers, and they must be hooked at the board level as described below. Configure this field before enabling the WCO, and do not change this setting when WCO_EN=1. +0: Watch crystal. Connect a 32.768 kHz watch crystal between WCO input and output pins. +1: Clock signal, either a square wave or sine wave. See PRESCALER field for connection information. + [16:16] + read-write + + + VDDBAK_CTL + Controls the behavior of the switch that generates vddbak from vbackup or vddd. +0: automatically select vddd if its brownout detector says it is valid. If the brownout says its not valid, then use vmax which is the highest of vddd or vbackup. +1,2,3: force vddbak and vmax to select vbackup, regardless of its voltage. + [18:17] + read-write + + + VBACKUP_MEAS + Connect vbackup supply to the vbackup_meas output for measurement by an ADC attached to amuxbusa_adft_vddd. The vbackup_meas signal is scaled to 10 percent of vbackup, so it is within the supply range of the ADC. + [19:19] + read-write + + + EN_CHARGE_KEY + When set to 3C, the supercap charger circuit is enabled. Any other code disables the supercap charger. THIS CHARGING CIRCUIT IS FOR A SUPERCAP ONLY AND CANNOT SAFELY CHARGE A BATTERY. DO NOT WRITE THIS KEY WHEN VBACKUP IS CONNECTED TO A BATTERY. + [31:24] + read-write + + + + + RTC_RW + RTC Read Write register + 0x8 + 32 + read-write + 0x0 + 0x3 + + + READ + Read bit +When this bit is set the RTC registers will be copied to user registers and frozen so that a coherent RTC value can safely be read. The RTC will keep on running. +Do not set the read bit if the RTC is still busy with a previous update (see RTC_BUSY bit) or if the Write bit is set. Do not set the Read bit at the same time that the Write bit is cleared. + [0:0] + read-write + + + WRITE + Write bit +Only when this bit is set can the RTC registers be written to (otherwise writes are ignored). This bit cannot be set if the RTC is still busy with a previous update (see RTC_BUSY bit) or if the Read bit is set or getting set. +The user writes to the RTC user registers, when the Write bit is cleared by the user then the user registers content is copied to the actual RTC registers. +Only user RTC registers that were written to will get copied, others will not be affected. +When the SECONDS field is updated then TICKS will also be reset (WDT is not affected). +When the Write bit is cleared by a reset (brown out/DeepSleep) then the RTC update will be ignored/lost. +Do not set the Write bit if the RTC if the RTC is still busy with a previous update (see RTC_BUSY). Do not set the Write bit at the same time that the Read bit is cleared. + [1:1] + read-write + + + + + CAL_CTL + Oscillator calibration for absolute frequency + 0xC + 32 + read-write + 0x0 + 0x8000007F + + + CALIB_VAL + Calibration value for absolute frequency (at a fixed temperature). Each step causes 128 ticks to be added or removed each hour. Effectively that means that each step is 1.085ppm (= 128/(60*60*32,768)). +Positive values 0x01-0x3c (1..60) add pulses, negative values remove pulses, thus giving a range of +/-65.1 ppm (limited by 60 minutes per hour, not the range of this field) + +Calibration is performed hourly, starting at 59 minutes and 59 seconds, and applied as 64 ticks every 30 seconds until there have been 2*CALIB_VAL adjustments. + [5:0] + read-write + + + CALIB_SIGN + Calibration sign: +0= Negative sign: remove pulses (it takes more clock ticks to count one second) +1= Positive sign: add pulses (it takes less clock ticks to count one second) + [6:6] + read-write + + + CAL_OUT + Output enable for 512Hz signal for calibration and allow CALIB_VAL to be written. Note that calibration does not affect the 512Hz output signal. + [31:31] + read-write + + + + + STATUS + Status + 0x10 + 32 + read-only + 0x0 + 0x5 + + + RTC_BUSY + pending RTC write + [0:0] + read-only + + + WCO_OK + Indicates that output has transitioned. + [2:2] + read-only + + + + + RTC_TIME + Calendar Seconds, Minutes, Hours, Day of Week + 0x14 + 32 + read-write + 0x0 + 0x77F7F7F + + + RTC_SEC + Calendar seconds in BCD, 0-59 + [6:0] + read-write + + + RTC_MIN + Calendar minutes in BCD, 0-59 + [14:8] + read-write + + + RTC_HOUR + Calendar hours in BCD, value depending on 12/24HR mode +0=24HR: [21:16]=0-23 +1=12HR: [21]:0=AM, 1=PM, [20:16]=1-12 + [21:16] + read-write + + + CTRL_12HR + Select 12/24HR mode: 1=12HR, 0=24HR + [22:22] + read-write + + + RTC_DAY + Calendar Day of the week in BCD, 1-7 +It is up to the user to define the meaning of the values, but 1=Monday is recommended + [26:24] + read-write + + + + + RTC_DATE + Calendar Day of Month, Month, Year + 0x18 + 32 + read-write + 0x0 + 0xFF1F3F + + + RTC_DATE + Calendar Day of the Month in BCD, 1-31 +Automatic Leap Year Correction + [5:0] + read-write + + + RTC_MON + Calendar Month in BCD, 1-12 + [12:8] + read-write + + + RTC_YEAR + Calendar year in BCD, 0-99 + [23:16] + read-write + + + + + ALM1_TIME + Alarm 1 Seconds, Minute, Hours, Day of Week + 0x1C + 32 + read-write + 0x1000000 + 0x87BFFFFF + + + ALM_SEC + Alarm seconds in BCD, 0-59 + [6:0] + read-write + + + ALM_SEC_EN + Alarm second enable: 0=ignore, 1=match + [7:7] + read-write + + + ALM_MIN + Alarm minutes in BCD, 0-59 + [14:8] + read-write + + + ALM_MIN_EN + Alarm minutes enable: 0=ignore, 1=match + [15:15] + read-write + + + ALM_HOUR + Alarm hours in BCD, value depending on 12/24HR mode +12HR: [5]:0=AM, 1=PM, [4:0]=1-12 +24HR: [5:0]=0-23 + [21:16] + read-write + + + ALM_HOUR_EN + Alarm hour enable: 0=ignore, 1=match + [23:23] + read-write + + + ALM_DAY + Alarm Day of the week in BCD, 1-7 +It is up to the user to define the meaning of the values, but 1=Monday is recommended + [26:24] + read-write + + + ALM_DAY_EN + Alarm Day of the Week enable: 0=ignore, 1=match + [31:31] + read-write + + + + + ALM1_DATE + Alarm 1 Day of Month, Month + 0x20 + 32 + read-write + 0x101 + 0x80009FBF + + + ALM_DATE + Alarm Day of the Month in BCD, 1-31 +Leap Year corrected + [5:0] + read-write + + + ALM_DATE_EN + Alarm Day of the Month enable: 0=ignore, 1=match + [7:7] + read-write + + + ALM_MON + Alarm Month in BCD, 1-12 + [12:8] + read-write + + + ALM_MON_EN + Alarm Month enable: 0=ignore, 1=match + [15:15] + read-write + + + ALM_EN + Master enable for alarm 1. +0: Alarm 1 is disabled. Fields for date and time are ignored. +1: Alarm 1 is enabled. Alarm triggers whenever the new date and time matches all the enabled date and time fields, which can happen more than once depending on configuration. If none of the date and time fields are enabled, then this alarm triggers once every second. + [31:31] + read-write + + + + + ALM2_TIME + Alarm 2 Seconds, Minute, Hours, Day of Week + 0x24 + 32 + read-write + 0x1000000 + 0x87BFFFFF + + + ALM_SEC + Alarm seconds in BCD, 0-59 + [6:0] + read-write + + + ALM_SEC_EN + Alarm second enable: 0=ignore, 1=match + [7:7] + read-write + + + ALM_MIN + Alarm minutes in BCD, 0-59 + [14:8] + read-write + + + ALM_MIN_EN + Alarm minutes enable: 0=ignore, 1=match + [15:15] + read-write + + + ALM_HOUR + Alarm hours in BCD, value depending on 12/24HR mode +12HR: [5]:0=AM, 1=PM, [4:0]=1-12 +24HR: [5:0]=0-23 + [21:16] + read-write + + + ALM_HOUR_EN + Alarm hour enable: 0=ignore, 1=match + [23:23] + read-write + + + ALM_DAY + Alarm Day of the week in BCD, 1-7 +It is up to the user to define the meaning of the values, but 1=Monday is recommended + [26:24] + read-write + + + ALM_DAY_EN + Alarm Day of the Week enable: 0=ignore, 1=match + [31:31] + read-write + + + + + ALM2_DATE + Alarm 2 Day of Month, Month + 0x28 + 32 + read-write + 0x101 + 0x80009FBF + + + ALM_DATE + Alarm Day of the Month in BCD, 1-31 +Leap Year corrected + [5:0] + read-write + + + ALM_DATE_EN + Alarm Day of the Month enable: 0=ignore, 1=match + [7:7] + read-write + + + ALM_MON + Alarm Month in BCD, 1-12 + [12:8] + read-write + + + ALM_MON_EN + Alarm Month enable: 0=ignore, 1=match + [15:15] + read-write + + + ALM_EN + Master enable for alarm 2. +0: Alarm 2 is disabled. Fields for date and time are ignored. +1: Alarm 2 is enabled. Alarm triggers whenever the new date and time matches all the enabled date and time fields, which can happen more than once depending on configuration. If none of the date and time fields are enabled, then this alarm triggers once every second. + [31:31] + read-write + + + + + INTR + Interrupt request register + 0x2C + 32 + read-write + 0x0 + 0x7 + + + ALARM1 + Alarm 1 Interrupt + [0:0] + read-write + + + ALARM2 + Alarm 2 Interrupt + [1:1] + read-write + + + CENTURY + Century overflow interrupt + [2:2] + read-write + + + + + INTR_SET + Interrupt set request register + 0x30 + 32 + read-write + 0x0 + 0x7 + + + ALARM1 + Write with '1' to set corresponding bit in interrupt request register. + [0:0] + read-write + + + ALARM2 + Write with '1' to set corresponding bit in interrupt request register. + [1:1] + read-write + + + CENTURY + Write with '1' to set corresponding bit in interrupt request register. + [2:2] + read-write + + + + + INTR_MASK + Interrupt mask register + 0x34 + 32 + read-write + 0x0 + 0x7 + + + ALARM1 + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + ALARM2 + Mask bit for corresponding bit in interrupt request register. + [1:1] + read-write + + + CENTURY + Mask bit for corresponding bit in interrupt request register. + [2:2] + read-write + + + + + INTR_MASKED + Interrupt masked request register + 0x38 + 32 + read-only + 0x0 + 0x7 + + + ALARM1 + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + ALARM2 + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + CENTURY + Logical and of corresponding request and mask bits. + [2:2] + read-only + + + + + OSCCNT + 32kHz oscillator counter + 0x3C + 32 + read-only + 0x0 + 0xFF + + + CNT32KHZ + 32kHz oscillator count (msb=128Hz), calibration can cause bit 6 to skip. Reset when RTC_TIME.RTC_SEC fields is written. + [7:0] + read-only + + + + + TICKS + 128Hz tick counter + 0x40 + 32 + read-only + 0x0 + 0x3F + + + CNT128HZ + 128Hz counter (msb=2Hz) +When SECONDS is written this field will be reset. + [5:0] + read-only + + + + + PMIC_CTL + PMIC control register + 0x44 + 32 + read-write + 0xA0000000 + 0xE001FF00 + + + UNLOCK + This byte must be set to 0x3A for PMIC to be disabled. When the UNLOCK code is not present: writes to PMIC_EN field are ignored and the hardware ignores the value in PMIC_EN. Do not change PMIC_EN in the same write cycle as setting/clearing the UNLOCK code; do these in separate write cycles. + [15:8] + read-write + + + POLARITY + N/A + [16:16] + read-write + + + PMIC_EN_OUTEN + Output enable for the output driver in the PMIC_EN pad. +0: Output pad is tristate for PMIC_EN pin. This can allow this pin to be used for another purpose. Tristate condition is kept only if the UNLOCK key (0x3A) is present +1: Output pad is enabled for PMIC_EN pin. + [29:29] + read-write + + + PMIC_ALWAYSEN + Override normal PMIC controls to prevent accidentally turning off the PMIC by errant firmware. +0: Normal operation, PMIC_EN and PMIC_OUTEN work as described +1: PMIC_EN and PMIC_OUTEN are ignored and the output pad is forced enabled. +Note: This bit is a write-once bit until the next backup reset. + [30:30] + read-write + + + PMIC_EN + Enable for external PMIC that supplies vddd (if present). This bit will only clear if UNLOCK was written correctly in a previous write operation and PMIC_ALWAYSEN=0. When PMIC_EN=0, the system functions normally until vddd is no longer present (OFF w/Backup mode). Firmware can set this bit, if it does so before vddd is actually removed. This bit is also set by any RTC alarm or PMIC pin wakeup event regardless of UNLOCK setting. + [31:31] + read-write + + + + + RESET + Backup reset register + 0x48 + 32 + read-write + 0x0 + 0x80000000 + + + RESET + Writing 1 to this register resets the backup logic. Hardware clears it when the reset is complete. After setting this register, firmware should confirm it reads as 0 before attempting to write other backup registers. + [31:31] + read-write + + + + + 64 + 4 + BREG[%s] + Backup register region + 0x1000 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + BREG + Backup memory that contains application-specific data. Memory is retained on vbackup supply. + [31:0] + read-write + + + + + TRIM + Trim Register + 0xFF00 + 32 + read-write + 0x0 + 0x3F + + + TRIM + WCO trim + [5:0] + read-write + + + + + + + DW0 + Datawire Controller + DW + 0x40280000 + + 0 + 65536 + registers + + + + CTL + Control + 0x0 + 32 + read-write + 0x1 + 0x80000003 + + + ECC_EN + Enable ECC checking: +'0': Disabled. +'1': Enabled. + [0:0] + read-write + + + ECC_INJ_EN + Enable parity injection for SRAM. +When '1', the parity (ECC_CTL.PARITY) is used when a full 32-bit write is done to the ECC_CTL.WORD_ADDR word address of the SRAM. + [1:1] + read-write + + + ENABLED + IP enable: +'0': Disabled. Disabling the IP activates the IP's Active logic reset: Active logic and non-retention MMIO registers are reset (retention MMIO registers are not affected). +'1': Enabled. + [31:31] + read-write + + + + + STATUS + Status + 0x4 + 32 + read-only + 0x0 + 0xF0000000 + + + P + Active channel, user/privileged access control: +'0': user mode. +'1': privileged mode. + [0:0] + read-only + + + NS + Active channel, secure/non-secure access control: +'0': secure. +'1': non-secure. + [1:1] + read-only + + + B + Active channel, non-bufferable/bufferable access control: +'0': non-bufferable +'1': bufferable. + [2:2] + read-only + + + PC + Active channel protection context. + [7:4] + read-only + + + PRIO + Active channel priority. + [9:8] + read-only + + + PREEMPTABLE + Active channel preemptable. + [11:11] + read-only + + + CH_IDX + Active channel index. + [24:16] + read-only + + + STATE + State of the DW controller. +'0': Default/inactive state. +'1': Loading descriptor. +'2': Loading data element from source location. +'3': Storing data element to destination location. +'4': CRC functionality (only used for CRC transfer descriptor type). +'5': Update of active control information (e.g. source and destination addresses) and wait for trigger de-activation. +'6': Error. + [30:28] + read-only + + + ACTIVE + Active channel present: +'0': No. +'1': Yes. + [31:31] + read-only + + + + + ACT_DESCR_CTL + Active descriptor control + 0x20 + 32 + read-only + 0x0 + 0x0 + + + DATA + Copy of DESCR_CTL of the currently active descriptor. + [31:0] + read-only + + + + + ACT_DESCR_SRC + Active descriptor source + 0x24 + 32 + read-only + 0x0 + 0x0 + + + DATA + Copy of DESCR_SRC of the currently active descriptor. + [31:0] + read-only + + + + + ACT_DESCR_DST + Active descriptor destination + 0x28 + 32 + read-only + 0x0 + 0x0 + + + DATA + Copy of DESCR_DST of the currently active descriptor. + [31:0] + read-only + + + + + ACT_DESCR_X_CTL + Active descriptor X loop control + 0x30 + 32 + read-only + 0x0 + 0x0 + + + DATA + Copy of DESCR_X_CTL of the currently active descriptor. + [31:0] + read-only + + + + + ACT_DESCR_Y_CTL + Active descriptor Y loop control + 0x34 + 32 + read-only + 0x0 + 0x0 + + + DATA + Copy of DESCR_Y_CTL of the currently active descriptor. + [31:0] + read-only + + + + + ACT_DESCR_NEXT_PTR + Active descriptor next pointer + 0x38 + 32 + read-only + 0x0 + 0x0 + + + ADDR + Copy of DESCR_NEXT_PTR of the currently active descriptor. + [31:2] + read-only + + + + + ACT_SRC + Active source + 0x40 + 32 + read-only + 0x0 + 0x0 + + + SRC_ADDR + Current address of source location. + [31:0] + read-only + + + + + ACT_DST + Active destination + 0x44 + 32 + read-only + 0x0 + 0x0 + + + DST_ADDR + Current address of destination location. + [31:0] + read-only + + + + + ECC_CTL + ECC control + 0x80 + 32 + read-write + 0x0 + 0xFE0003FF + + + WORD_ADDR + Specifies the word address where an error will be injected. +- On a write transfer to this SRAM word address and when CTL.ECC_INJ_EN bit is '1', the parity (PARITY) is injected. + [9:0] + read-write + + + PARITY + ECC parity to use for ECC error injection at address WORD_ADDR. + [31:25] + read-write + + + + + CRC_CTL + CRC control + 0x100 + 32 + read-write + 0x0 + 0x101 + + + DATA_REVERSE + Specifies the bit order in which a data Byte is processed (reversal is performed after XORing): +'0': Most significant bit (bit 1) first. +'1': Least significant bit (bit 0) first. + [0:0] + read-write + + + REM_REVERSE + Specifies whether the remainder is bit reversed (reversal is performed after XORing): +'0': No. +'1': Yes. + [8:8] + read-write + + + + + CRC_DATA_CTL + CRC data control + 0x110 + 32 + read-write + 0x0 + 0xFF + + + DATA_XOR + Specifies a byte mask with which each data byte is XOR'd. The XOR is performed before data reversal. + [7:0] + read-write + + + + + CRC_POL_CTL + CRC polynomial control + 0x120 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + POLYNOMIAL + CRC polynomial. The polynomial is represented WITHOUT the high order bit (this bit is always assumed '1'). The polynomial should be aligned/shifted such that the more significant bits (bit 31 and down) contain the polynomial and the less significant bits (bit 0 and up) contain padding '0's. Some frequently used polynomials: +- CRC32: POLYNOMIAL is 0x04c11db7 (x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x + 1). +- CRC16: POLYNOMIAL is 0x80050000 (x^16 + x^15 + x^2 + 1, shifted by 16 bit positions). +- CRC16 CCITT: POLYNOMIAL is 0x10210000 (x^16 + x^12 + x^5 + 1, shifted by 16 bit positions). + [31:0] + read-write + + + + + CRC_LFSR_CTL + CRC LFSR control + 0x130 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + LFSR32 + State of a 32-bit Linear Feedback Shift Registers (LFSR) that is used to implement CRC. This register needs to be initialized by SW to provide the CRC seed value. + +The seed value should be aligned such that the more significant bits (bit 31 and down) contain the seed value and the less significant bits (bit 0 and up) contain padding '0's. + +Note that SW can write this field. This functionality can be used prevent information leakage (through either CRC_LFSR_CTL or CRC_REM_RESULT). + [31:0] + read-write + + + + + CRC_REM_CTL + CRC remainder control + 0x140 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + REM_XOR + Specifies a mask with which the CRC_LFSR_CTL.LFSR32 register is XOR'd to produce a remainder. The XOR is performed before remainder reversal. + [31:0] + read-write + + + + + CRC_REM_RESULT + CRC remainder result + 0x148 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + REM + Remainder value. The alignment of the remainder depends on CRC_REM_CTL0.REM_REVERSE: +'0': the more significant bits (bit 31 and down) contain the remainder. +'1': the less significant bits (bit 0 and up) contain the remainder. + +Note: This field is combinatorially derived from CRC_LFSR_CTL.LFSR32, CRC_CTL.REM_REVERSE and CRC_REM_CTL.REM_XOR. + [31:0] + read-only + + + + + 32 + 64 + CH_STRUCT[%s] + DW channel structure + 0x00008000 + + CH_CTL + Channel control + 0x0 + 32 + read-write + 0x2 + 0x80000BF7 + + + P + User/privileged access control: +'0': user mode. +'1': privileged mode. + +This field is set with the user/privileged access control of the transaction that writes this register; i.e. the 'write data' is ignored and instead the access control is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). + +All transactions for this channel use the P field for the user/privileged access control ('hprot[1]'). + [0:0] + read-write + + + NS + Secure/on-secure access control: +'0': secure. +'1': non-secure. + +This field is set with the secure/non-secure access control of the transaction that writes this register; i.e. the 'write data' is ignored and instead the access control is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). + +All transactions for this channel use the NS field for the secure/non-secure access control ('hprot[4]'). + [1:1] + read-write + + + B + Non-bufferable/bufferable access control: +'0': non-bufferable. +'1': bufferable. + +This field is used to indicate to an AMBA bridge that a write transaction can complete without waiting for the destination to accept the write transaction data. + +All transactions for this channel uses the B field for the non-bufferable/bufferable access control ('hprot[2]'). + [2:2] + read-write + + + PC + Protection context. + +This field is set with the protection context of the transaction that writes this register; i.e. the 'write data' is ignored and instead the context is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). + +All transactions for this channel uses the PC field for the protection context. + [7:4] + read-write + + + PRIO + Channel priority: +'0': highest priority. +'1' +'2' +'3': lowest priority. + +Channels with the same priority constitute a priority group. Priority decoding determines the highest priority pending channel. This channel is determined as follows. First, the highest priority group with pending channels is identified. Second, within this priority group, round robin arbitration is applied. Round robin arbitration (within a priority group) gives the highest priority to the lower channel indices (within the priority group). + [9:8] + read-write + + + PREEMPTABLE + Specifies if the channel is preemptable. +'0': Not preemptable. +'1': Preemptable. This field allows higher priority pending channels (from a higher priority group; i.e. an active channel can NOT be preempted by a pending channel in the same priority group) to preempt the active channel in between 'single transfers' (a 1D transfer consists out of X_COUNT single transfers; a 2D transfer consists out of X_COUNT*Y_COUNT single transfers). Preemption will NOT affect the pending status of channel. As a result, after completion of a higher priority activated channel, the current channel may be reactivated. + [11:11] + read-write + + + ENABLED + Channel enable: +'0': Disabled. The channel's trigger is ignored and the channel cannot be made pending and therefore cannot be made active. If a pending channel is disabled, the channel is made non pending. If the activate channel is disabled, the channel is de-activated (bus transactions are completed). +'1': Enabled. + +SW sets this field to '1' to enable a specific channel. + +HW sets this field to '0' on an error interrupt cause (the specific error is specified by CH_STATUS.INTR_CAUSE). + [31:31] + read-write + + + + + CH_STATUS + Channel status + 0x4 + 32 + read-only + 0x0 + 0x0 + + + INTR_CAUSE + Specifies the source of the interrupt cause: +'0': NO_INTR +'1': COMPLETION +'2': SRC_BUS_ERROR +'3': DST_BUS_ERROR +'4': SRC_MISAL +'5': DST_MISAL +'6': CURR_PTR_NULL +'7': ACTIVE_CH_DISABLED +'8': DESCR_BUS_ERROR +'9'-'15': Not used. + +For error related interrupt causes (INTR_CAUSE is '2', '3', ..., '8'), the channel is disabled (HW sets CH_CTL.ENABLED to '0'). + [3:0] + read-only + + + PENDING + Specifies pending DW channels; i.e. enabled channels whose trigger got activated. This field includes all channels that are in the pending state (not scheduled) or active state (scheduled and performing data transfer(s)). + [31:31] + read-only + + + + + CH_IDX + Channel current indices + 0x8 + 32 + read-write + 0x0 + 0x0 + + + X_IDX + Specifies the X loop index. In the range of [0, X_COUNT], with X_COUNT taken from the current descriptor. + +Note: HW sets this field to '0' when it updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. + +Note: SW should set this field to '0' when it updates CH_CURR_PTR. + [7:0] + read-write + + + Y_IDX + Specifies the Y loop index, with X_COUNT taken from the current descriptor. + +Note: HW sets this field to '0' when it updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. + +Note: SW should set this field to '0' when it updates CH_CURR_PTR. + [15:8] + read-write + + + + + CH_CURR_PTR + Channel current descriptor pointer + 0xC + 32 + read-write + 0x0 + 0x0 + + + ADDR + Address of current descriptor. When this field is '0', there is no valid descriptor. + +Note: HW updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. + +Note: Typically, when SW updates the current descriptor pointer CH_CURR_PTR, it also sets CH_IDX.X_IDX and CH_IDX.Y_IDX to '0'. + [31:2] + read-write + + + + + INTR + Interrupt + 0x10 + 32 + read-write + 0x0 + 0x1 + + + CH + Set to '1', when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1', to clear bit. Write INTR_SET.CH field with '1', to set bit. + [0:0] + read-write + + + + + INTR_SET + Interrupt set + 0x14 + 32 + read-write + 0x0 + 0x1 + + + CH + Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect). + [0:0] + read-write + + + + + INTR_MASK + Interrupt mask + 0x18 + 32 + read-write + 0x0 + 0x1 + + + CH + Mask for corresponding field in INTR register. + [0:0] + read-write + + + + + INTR_MASKED + Interrupt masked + 0x1C + 32 + read-only + 0x0 + 0x1 + + + CH + Logical and of corresponding INTR and INTR_MASK fields. + [0:0] + read-only + + + + + SRAM_DATA0 + SRAM data 0 + 0x20 + 32 + read-write + 0x0 + 0x0 + + + DATA + N/A + [31:0] + read-write + + + + + SRAM_DATA1 + SRAM data 1 + 0x24 + 32 + read-write + 0x0 + 0x0 + + + DATA + N/A + [31:0] + read-write + + + + + TR_CMD + Channel software trigger + 0x28 + 32 + read-write + 0x0 + 0x1 + + + ACTIVATE + Software trigger. When written with '1', a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0. + [0:0] + read-write + + + + + + + + DW1 + 0x40290000 + + + DMAC + DMAC + 0x402A0000 + + 0 + 65536 + registers + + + + CTL + Control + 0x0 + 32 + read-write + 0x0 + 0x80000000 + + + ENABLED + IP enable: +'0': Disabled. All non-retention registers (command and status registers) are reset to their default value when the IP is disabled. All retention registers retain their value when the IP is disabled. +'1': Enabled. + [31:31] + read-write + + + DISABLED + N/A + 0 + + + ENABLED + N/A + 1 + + + + + + + ACTIVE + Active channels + 0x8 + 32 + read-only + 0x0 + 0xFF + + + ACTIVE + Specifies active channels; i.e. enabled channels whose trigger got activated. + [7:0] + read-only + + + + + 2 + 256 + CH[%s] + DMA controller channel + 0x00001000 + + CTL + Channel control + 0x0 + 32 + read-write + 0x2 + 0x800003F7 + + + P + User/privileged access control: +'0': user mode. +'1': privileged mode. + +This field is set with the user/privileged access control of the transaction that writes this register; i.e. the access control is inherited from the write transaction and not specified by the transaction write data. + +All transactions for this channel use the P field for the user/privileged access control ('hprot[1]'). + [0:0] + read-write + + + NS + Secure/on-secure access control: +'0': secure. +'1': non-secure. + +This field is set with the secure/non-secure access control of the transaction that writes this register; i.e. the access control is inherited from the write transaction and not specified by the transaction write data. + +All transactions for this channel use the NS field for the secure/non-secure access control ('hprot[4]'). + [1:1] + read-write + + + B + Non-bufferable/bufferable access control: +'0': non-bufferable. +'1': bufferable. + +This field is used to indicate to an AMBA bridge that a write transaction can complete without waiting for the destination to accept the write transaction data. + +All transactions for this channel uses the B field for the non-bufferable/bufferable access control ('hprot[2]'). + [2:2] + read-write + + + PC + Protection context. + +This field is set with the protection context of the transaction that writes this register; i.e. the context is inherited from the write transaction and not specified by the transaction write data. + +All transactions for this channel uses the PC field for the protection context. + [7:4] + read-write + + + PRIO + Channel priority: +'0': highest priority. +'1' +'2' +'3': lowest priority. + +Channels with the same priority constitute a priority group and within this priority group, the following 'roundrobin' arbitration is applied. +A 'round' consists of a contiguous sequence of channel activations, within this priority group, without any repetition. Within a round, higher priority is given to the lower channel indices. The notion of a round guarantees that within a group, higher channel indices do not yield to lower indices indefinitely. + [9:8] + read-write + + + ENABLED + Channel enable: +'0': Disabled. The channel's trigger is ignored and the channel cannot be made pending and therefore cannot be made active. If a pending channel is disabled, the channel is made non pending. If the activate channel is disabled, the channel is de-activated (bus transactions are completed). +'1': Enabled. + +SW sets this field to '1' to enable a specific channel. + +HW sets this field to '0' when an error interrupt cause is activated. + [31:31] + read-write + + + + + IDX + Channel current indices + 0x10 + 32 + read-only + 0x0 + 0x0 + + + X + Specifies the X loop index. In the range of [0, X_COUNT], with X_COUNT taken from the current descriptor. + +Note: HW sets this field to '0' when it loads a descriptor. + [15:0] + read-only + + + Y + Specifies the Y loop index, with Y_COUNT taken from the current descriptor. + +Note: HW sets this field to '0' when it loads a descriptor.. + [31:16] + read-only + + + + + SRC + Channel current source address + 0x14 + 32 + read-only + 0x0 + 0x0 + + + ADDR + Current address of source location. + [31:0] + read-only + + + + + DST + Channel current destination address + 0x18 + 32 + read-only + 0x0 + 0x0 + + + ADDR + Current address of destination location. + [31:0] + read-only + + + + + CURR + Channel current descriptor pointer + 0x20 + 32 + read-write + 0x0 + 0x0 + + + PTR + Address of current descriptor. When this field is '0', there is no valid descriptor. + +Note: HW updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. + [31:2] + read-write + + + + + TR_CMD + Channle software trigger + 0x28 + 32 + read-write + 0x0 + 0x1 + + + ACTIVATE + Software trigger. When written with '1', a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0. + [0:0] + read-write + + + + + DESCR_STATUS + Channel descriptor status + 0x40 + 32 + read-only + 0x0 + 0x80000000 + + + VALID + Indicates whether the descriptor information present in DESCR_CTL, DESCR_SRC, DESCR_DST, DESCR_X_SIZE, DESCR_X_INCR, DESCR_Y_SIZE, DESCR_Y_INCR, DESCR_NEXT status registers is valid or not. + [31:31] + read-only + + + + + DESCR_CTL + Channel descriptor control + 0x60 + 32 + read-only + 0x0 + 0x0 + + + WAIT_FOR_DEACT + N/A + [1:0] + read-only + + + INTR_TYPE + N/A + [3:2] + read-only + + + TR_OUT_TYPE + N/A + [5:4] + read-only + + + TR_IN_TYPE + N/A + [7:6] + read-only + + + DATA_PREFETCH + N/A + [8:8] + read-only + + + DATA_SIZE + N/A + [17:16] + read-only + + + CH_DISABLE + N/A + [24:24] + read-only + + + SRC_TRANSFER_SIZE + N/A + [26:26] + read-only + + + DST_TRANSFER_SIZE + N/A + [27:27] + read-only + + + DESCR_TYPE + N/A + [30:28] + read-only + + + + + DESCR_SRC + Channel descriptor source + 0x64 + 32 + read-only + 0x0 + 0x0 + + + ADDR + N/A + [31:0] + read-only + + + + + DESCR_DST + Channel descriptor destination + 0x68 + 32 + read-only + 0x0 + 0x0 + + + ADDR + N/A + [31:0] + read-only + + + + + DESCR_X_SIZE + Channel descriptor X size + 0x6C + 32 + read-only + 0x0 + 0x0 + + + X_COUNT + N/A + [15:0] + read-only + + + + + DESCR_X_INCR + Channel descriptor X increment + 0x70 + 32 + read-only + 0x0 + 0x0 + + + SRC_X + N/A + [15:0] + read-only + + + DST_X + N/A + [31:16] + read-only + + + + + DESCR_Y_SIZE + Channel descriptor Y size + 0x74 + 32 + read-only + 0x0 + 0x0 + + + Y_COUNT + N/A + [15:0] + read-only + + + + + DESCR_Y_INCR + Channel descriptor Y increment + 0x78 + 32 + read-only + 0x0 + 0x0 + + + SRC_Y + N/A + [15:0] + read-only + + + DST_Y + N/A + [31:16] + read-only + + + + + DESCR_NEXT + Channel descriptor next pointer + 0x7C + 32 + read-only + 0x0 + 0x0 + + + PTR + N/A + [31:2] + read-only + + + + + INTR + Interrupt + 0x80 + 32 + read-write + 0x0 + 0xFF + + + COMPLETION + Activated (set to '1') on completion of data transfer(s) as specified by the descriptor's CH_DESCR_CTL.INTR_TYPE. + [0:0] + read-write + + + SRC_BUS_ERROR + Activated (set to '1') on a bus error for a load from the source. + [1:1] + read-write + + + DST_BUS_ERROR + Activated (set to '1') on a bus error for a store to the destination. + [2:2] + read-write + + + SRC_MISAL + Activated (set to '1') on a misalignment of the source address. + [3:3] + read-write + + + DST_MISAL + Activated (set to '1') on a misalignment of the destination address. + [4:4] + read-write + + + CURR_PTR_NULL + Activated (set to '1') when the channel is enabled (CH_CTL.ENABLED is '1') and CH_CURR_PTR is '0'. + [5:5] + read-write + + + ACTIVE_CH_DISABLED + Activated (set to '1') if the channel is disabled by SW (accidentally/incorrectly) when the data transfer engine is busy. + [6:6] + read-write + + + DESCR_BUS_ERROR + Activated (set to '1') on a bus error for a load of the descriptor. + [7:7] + read-write + + + + + INTR_SET + Interrupt set + 0x84 + 32 + read-write + 0x0 + 0xFF + + + COMPLETION + Write this field with '1' to set corresponding INTR field to '1' (a write of '0' has no effect). + [0:0] + read-write + + + SRC_BUS_ERROR + N/A + [1:1] + read-write + + + DST_BUS_ERROR + N/A + [2:2] + read-write + + + SRC_MISAL + N/A + [3:3] + read-write + + + DST_MISAL + N/A + [4:4] + read-write + + + CURR_PTR_NULL + N/A + [5:5] + read-write + + + ACTIVE_CH_DISABLED + N/A + [6:6] + read-write + + + DESCR_BUS_ERROR + N/A + [7:7] + read-write + + + + + INTR_MASK + Interrupt mask + 0x88 + 32 + read-write + 0x0 + 0xFF + + + COMPLETION + Mask for corresponding field in INTR register. + [0:0] + read-write + + + SRC_BUS_ERROR + N/A + [1:1] + read-write + + + DST_BUS_ERROR + N/A + [2:2] + read-write + + + SRC_MISAL + N/A + [3:3] + read-write + + + DST_MISAL + N/A + [4:4] + read-write + + + CURR_PTR_NULL + N/A + [5:5] + read-write + + + ACTIVE_CH_DISABLED + N/A + [6:6] + read-write + + + DESCR_BUS_ERROR + N/A + [7:7] + read-write + + + + + INTR_MASKED + Interrupt masked + 0x8C + 32 + read-only + 0x0 + 0xFF + + + COMPLETION + Logical and of corresponding INTR and INTR_MASK fields. + [0:0] + read-only + + + SRC_BUS_ERROR + N/A + [1:1] + read-only + + + DST_BUS_ERROR + N/A + [2:2] + read-only + + + SRC_MISAL + N/A + [3:3] + read-only + + + DST_MISAL + N/A + [4:4] + read-only + + + CURR_PTR_NULL + N/A + [5:5] + read-only + + + ACTIVE_CH_DISABLED + N/A + [6:6] + read-only + + + DESCR_BUS_ERROR + N/A + [7:7] + read-only + + + + + + + + EFUSE + EFUSE MXS40 registers + 0x402C0000 + + 0 + 128 + registers + + + + CTL + Control + 0x0 + 32 + read-write + 0x0 + 0x80000000 + + + ENABLED + IP enable: +'0': Disabled. All non-retention registers (command and status registers) are reset to their default value when the IP is disabled. All retention registers retain their value when the IP is disabled. +'1': Enabled. + [31:31] + read-write + + + + + CMD + Command + 0x10 + 32 + read-write + 0x1 + 0x800F1F71 + + + BIT_DATA + Bit data. This field specifies the bit value that is to be programmed into the eFUSE macro array. The address of the bit is specified by the BIT_ADDR, BYTE_ADDR, and MACRO_ADDR fields. This bit is a don't care for the MXS40 Macro. + [0:0] + read-write + + + BIT_ADDR + Bit address. This field specifies a bit within a Byte. + [6:4] + read-write + + + BYTE_ADDR + Byte address. This field specifies a Byte within a eFUSE macro (each macro has 32 B). + [12:8] + read-write + + + MACRO_ADDR + Macro address. This field specifies an eFUSE macro. + [19:16] + read-write + + + START + FW sets this field to '1' to start a program operation. HW sets this field to '0' to indicate that the operation has completed. + +Note: it is good practice to verify the result of a program operation by reading back a programmed eFUSE memory location. Programming can only change an eFUSE memory bit from '0' to '1'; i.e. a programming operation is a 'one-off' operation for each eFUSE memory bit: once a bit is changed to '1', it can NEVER be changed back to '0' as a hardware fuse is blown. + +Programming a memory bit to '1' requires blowing a fuse and requires an eFUSE macro operation. Therefore, this programmiong operation takes time (as specified by the SEQ_PROGRAM_CTL reguisters). Programming amemory bit to '0' does not require an eFUSE macro operation (it is the default eFUSE macro state). Therefore, this programming operation is almost instantaneous. + +Note: during a program operation, a read operation can not be performed. An AHB-Lite read transfer to the eFUSE memory during a program operation results in an AHB-Lite bus error. + [31:31] + read-write + + + + + SEQ_DEFAULT + Sequencer Default value + 0x20 + 32 + read-write + 0x1D0000 + 0x7F0000 + + + STROBE_A + Specifies value of eFUSE control signal strobe_f + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + + + SEQ_READ_CTL_0 + Sequencer read control 0 + 0x40 + 32 + read-write + 0x80560001 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_f + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + SEQ_READ_CTL_1 + Sequencer read control 1 + 0x44 + 32 + read-write + 0x540004 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_f + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + SEQ_READ_CTL_2 + Sequencer read control 2 + 0x48 + 32 + read-write + 0x560001 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_f + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + SEQ_READ_CTL_3 + Sequencer read control 3 + 0x4C + 32 + read-write + 0x540003 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_f + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + SEQ_READ_CTL_4 + Sequencer read control 4 + 0x50 + 32 + read-write + 0x80150001 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_f + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + SEQ_READ_CTL_5 + Sequencer read control 5 + 0x54 + 32 + read-write + 0x310004 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_f + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + SEQ_PROGRAM_CTL_0 + Sequencer program control 0 + 0x60 + 32 + read-write + 0x200001 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_a + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + SEQ_PROGRAM_CTL_1 + Sequencer program control 1 + 0x64 + 32 + read-write + 0x220020 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_a + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + SEQ_PROGRAM_CTL_2 + Sequencer program control 2 + 0x68 + 32 + read-write + 0x200001 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_a + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + SEQ_PROGRAM_CTL_3 + Sequencer program control 3 + 0x6C + 32 + read-write + 0x310005 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_a + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + SEQ_PROGRAM_CTL_4 + Sequencer program control 4 + 0x70 + 32 + read-write + 0x80350006 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_a + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + SEQ_PROGRAM_CTL_5 + Sequencer program control 5 + 0x74 + 32 + read-write + 0x803D0019 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_a + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + + + HSIOM + High Speed IO Matrix (HSIOM) + 0x40300000 + + 0 + 16384 + registers + + + + 15 + 16 + PRT[%s] + HSIOM port registers + 0x00000000 + + PORT_SEL0 + Port selection 0 + 0x0 + 32 + read-write + 0x0 + 0x1F1F1F1F + + + IO0_SEL + Selects the peripheral connections of Pin 0. Note that available connectivity options vary depending on the device, port and the pin. See the device Datasheet for a list of peripheral connections available at each pin. + [4:0] + read-write + + + GPIO + N/A + 0 + + + GPIO_DSI + N/A + 1 + + + DSI_DSI + N/A + 2 + + + DSI_GPIO + N/A + 3 + + + AMUXA + AMUXBUS A + 4 + + + AMUXB + AMUXBUS B + 5 + + + AMUXA_DSI + N/A + 6 + + + AMUXB_DSI + N/A + 7 + + + ACT_0 + Active peripherals 0 + 8 + + + ACT_1 + Active peripherals 1 + 9 + + + ACT_2 + Active peripherals 2 + 10 + + + ACT_3 + Active peripherals 4 + 11 + + + DS_0 + Deep Sleep peripherals 0 + 12 + + + DS_1 + Deep Sleep peripherals 1 + 13 + + + DS_2 + Deep Sleep peripherals 2 + 14 + + + DS_3 + Deep Sleep peripherals 3 + 15 + + + ACT_4 + Active peripherals 4 + 16 + + + ACT_5 + Active peripherals 5 + 17 + + + ACT_6 + Active peripherals 6 + 18 + + + ACT_7 + Active peripherals 7 + 19 + + + ACT_8 + Active peripherals 8 + 20 + + + ACT_9 + Active peripherals 9 + 21 + + + ACT_10 + Active peripherals 10 + 22 + + + ACT_11 + Active peripherals 11 + 23 + + + ACT_12 + Active peripherals 12 + 24 + + + ACT_13 + Active peripherals 13 + 25 + + + ACT_14 + Active peripherals 14 + 26 + + + ACT_15 + Active peripherals 15 + 27 + + + DS_4 + N/A + 28 + + + DS_5 + N/A + 29 + + + DS_6 + N/A + 30 + + + DS_7 + N/A + 31 + + + + + IO1_SEL + Selects the peripheral connections of Pin 1. + [12:8] + read-write + + + IO2_SEL + Selects the peripheral connections of Pin 2. + [20:16] + read-write + + + IO3_SEL + Selects the peripheral connections of Pin 3. + [28:24] + read-write + + + + + PORT_SEL1 + Port selection 1 + 0x4 + 32 + read-write + 0x0 + 0x1F1F1F1F + + + IO4_SEL + Selects the peripheral connections of Pin 4. See PORT_SEL0 for connection details. + [4:0] + read-write + + + IO5_SEL + Selects the peripheral connections of Pin 4. + [12:8] + read-write + + + IO6_SEL + Selects the peripheral connections of Pin 5. + [20:16] + read-write + + + IO7_SEL + Selects the peripheral connections of Pin 6. + [28:24] + read-write + + + + + + 64 + 4 + AMUX_SPLIT_CTL[%s] + AMUX splitter cell control + 0x2000 + 32 + read-write + 0x0 + 0x77 + + + SWITCH_AA_SL + T-switch control for Left AMUXBUSA switch: +'0': switch open. +'1': switch closed. + [0:0] + read-write + + + SWITCH_AA_SR + T-switch control for Right AMUXBUSA switch: +'0': switch open. +'1': switch closed. + [1:1] + read-write + + + SWITCH_AA_S0 + T-switch control for AMUXBUSA vssa/ground switch: +'0': switch open. +'1': switch closed. + [2:2] + read-write + + + SWITCH_BB_SL + T-switch control for Left AMUXBUSB switch. + [4:4] + read-write + + + SWITCH_BB_SR + T-switch control for Right AMUXBUSB switch. + [5:5] + read-write + + + SWITCH_BB_S0 + T-switch control for AMUXBUSB vssa/ground switch. + [6:6] + read-write + + + + + MONITOR_CTL_0 + Power/Ground Monitor cell control 0 + 0x2200 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MONITOR_EN + control for switch, which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed: +'0': switch open. +'1': switch closed. + [31:0] + read-write + + + + + MONITOR_CTL_1 + Power/Ground Monitor cell control 1 + 0x2204 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MONITOR_EN + control for switch, which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed: +'0': switch open. +'1': switch closed. + [31:0] + read-write + + + + + MONITOR_CTL_2 + Power/Ground Monitor cell control 2 + 0x2208 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MONITOR_EN + control for switch, which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed: +'0': switch open. +'1': switch closed. + [31:0] + read-write + + + + + MONITOR_CTL_3 + Power/Ground Monitor cell control 3 + 0x220C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MONITOR_EN + control for switch, which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed: +'0': switch open. +'1': switch closed. + [31:0] + read-write + + + + + ALT_JTAG_EN + Alternate JTAG IF selection register + 0x2240 + 32 + read-write + 0x0 + 0x80000000 + + + ENABLE + Provides the selection for alternate JTAG IF connectivity. +0: Primary JTAG interface is selected +1: Secondary (alternate) JTAG interface is selected. + +This connectivity works ONLY in ACTIVE mode. + [31:31] + read-write + + + + + + + GPIO + GPIO port control/configuration + 0x40310000 + + 0 + 65536 + registers + + + + 15 + 128 + PRT[%s] + GPIO port registers + 0x00000000 + + OUT + Port output data register + 0x0 + 32 + read-write + 0x0 + 0xFF + + + OUT0 + IO output data for pin 0 +'0': Output state set to '0' +'1': Output state set to '1' + [0:0] + read-write + + + OUT1 + IO output data for pin 1 + [1:1] + read-write + + + OUT2 + IO output data for pin 2 + [2:2] + read-write + + + OUT3 + IO output data for pin 3 + [3:3] + read-write + + + OUT4 + IO output data for pin 4 + [4:4] + read-write + + + OUT5 + IO output data for pin 5 + [5:5] + read-write + + + OUT6 + IO output data for pin 6 + [6:6] + read-write + + + OUT7 + IO output data for pin 7 + [7:7] + read-write + + + + + OUT_CLR + Port output data clear register + 0x4 + 32 + read-write + 0x0 + 0xFF + + + OUT0 + IO clear output for pin 0: +'0': Output state not affected. +'1': Output state set to '0'. + [0:0] + read-write + + + OUT1 + IO clear output for pin 1 + [1:1] + read-write + + + OUT2 + IO clear output for pin 2 + [2:2] + read-write + + + OUT3 + IO clear output for pin 3 + [3:3] + read-write + + + OUT4 + IO clear output for pin 4 + [4:4] + read-write + + + OUT5 + IO clear output for pin 5 + [5:5] + read-write + + + OUT6 + IO clear output for pin 6 + [6:6] + read-write + + + OUT7 + IO clear output for pin 7 + [7:7] + read-write + + + + + OUT_SET + Port output data set register + 0x8 + 32 + read-write + 0x0 + 0xFF + + + OUT0 + IO set output for pin 0: +'0': Output state not affected. +'1': Output state set to '1'. + [0:0] + read-write + + + OUT1 + IO set output for pin 1 + [1:1] + read-write + + + OUT2 + IO set output for pin 2 + [2:2] + read-write + + + OUT3 + IO set output for pin 3 + [3:3] + read-write + + + OUT4 + IO set output for pin 4 + [4:4] + read-write + + + OUT5 + IO set output for pin 5 + [5:5] + read-write + + + OUT6 + IO set output for pin 6 + [6:6] + read-write + + + OUT7 + IO set output for pin 7 + [7:7] + read-write + + + + + OUT_INV + Port output data invert register + 0xC + 32 + read-write + 0x0 + 0xFF + + + OUT0 + IO invert output for pin 0: +'0': Output state not affected. +'1': Output state inverted ('0' => '1', '1' => '0'). + [0:0] + read-write + + + OUT1 + IO invert output for pin 1 + [1:1] + read-write + + + OUT2 + IO invert output for pin 2 + [2:2] + read-write + + + OUT3 + IO invert output for pin 3 + [3:3] + read-write + + + OUT4 + IO invert output for pin 4 + [4:4] + read-write + + + OUT5 + IO invert output for pin 5 + [5:5] + read-write + + + OUT6 + IO invert output for pin 6 + [6:6] + read-write + + + OUT7 + IO invert output for pin 7 + [7:7] + read-write + + + + + IN + Port input state register + 0x10 + 32 + read-only + 0x0 + 0x1FF + + + IN0 + IO pin state for pin 0 +'0': Low logic level present on pin. +'1': High logic level present on pin. + [0:0] + read-only + + + IN1 + IO pin state for pin 1 + [1:1] + read-only + + + IN2 + IO pin state for pin 2 + [2:2] + read-only + + + IN3 + IO pin state for pin 3 + [3:3] + read-only + + + IN4 + IO pin state for pin 4 + [4:4] + read-only + + + IN5 + IO pin state for pin 5 + [5:5] + read-only + + + IN6 + IO pin state for pin 6 + [6:6] + read-only + + + IN7 + IO pin state for pin 7 + [7:7] + read-only + + + FLT_IN + Reads of this register return the logical state of the filtered pin as selected in the INTR_CFG.FLT_SEL register. + [8:8] + read-only + + + + + INTR + Port interrupt status register + 0x14 + 32 + read-write + 0x0 + 0x1FF01FF + + + EDGE0 + Edge detect for IO pin 0 +'0': No edge was detected on pin. +'1': An edge was detected on pin. + [0:0] + read-write + + + EDGE1 + Edge detect for IO pin 1 + [1:1] + read-write + + + EDGE2 + Edge detect for IO pin 2 + [2:2] + read-write + + + EDGE3 + Edge detect for IO pin 3 + [3:3] + read-write + + + EDGE4 + Edge detect for IO pin 4 + [4:4] + read-write + + + EDGE5 + Edge detect for IO pin 5 + [5:5] + read-write + + + EDGE6 + Edge detect for IO pin 6 + [6:6] + read-write + + + EDGE7 + Edge detect for IO pin 7 + [7:7] + read-write + + + FLT_EDGE + Edge detected on filtered pin selected by INTR_CFG.FLT_SEL + [8:8] + read-write + + + IN_IN0 + IO pin state for pin 0 + [16:16] + read-only + + + IN_IN1 + IO pin state for pin 1 + [17:17] + read-only + + + IN_IN2 + IO pin state for pin 2 + [18:18] + read-only + + + IN_IN3 + IO pin state for pin 3 + [19:19] + read-only + + + IN_IN4 + IO pin state for pin 4 + [20:20] + read-only + + + IN_IN5 + IO pin state for pin 5 + [21:21] + read-only + + + IN_IN6 + IO pin state for pin 6 + [22:22] + read-only + + + IN_IN7 + IO pin state for pin 7 + [23:23] + read-only + + + FLT_IN_IN + Filtered pin state for pin selected by INTR_CFG.FLT_SEL + [24:24] + read-only + + + + + INTR_MASK + Port interrupt mask register + 0x18 + 32 + read-write + 0x0 + 0x1FF + + + EDGE0 + Masks edge interrupt on IO pin 0 +'0': Pin interrupt forwarding disabled +'1': Pin interrupt forwarding enabled + [0:0] + read-write + + + EDGE1 + Masks edge interrupt on IO pin 1 + [1:1] + read-write + + + EDGE2 + Masks edge interrupt on IO pin 2 + [2:2] + read-write + + + EDGE3 + Masks edge interrupt on IO pin 3 + [3:3] + read-write + + + EDGE4 + Masks edge interrupt on IO pin 4 + [4:4] + read-write + + + EDGE5 + Masks edge interrupt on IO pin 5 + [5:5] + read-write + + + EDGE6 + Masks edge interrupt on IO pin 6 + [6:6] + read-write + + + EDGE7 + Masks edge interrupt on IO pin 7 + [7:7] + read-write + + + FLT_EDGE + Masks edge interrupt on filtered pin selected by INTR_CFG.FLT_SEL + [8:8] + read-write + + + + + INTR_MASKED + Port interrupt masked status register + 0x1C + 32 + read-only + 0x0 + 0x1FF + + + EDGE0 + Edge detected AND masked on IO pin 0 +'0': Interrupt was not forwarded to CPU +'1': Interrupt occurred and was forwarded to CPU + [0:0] + read-only + + + EDGE1 + Edge detected and masked on IO pin 1 + [1:1] + read-only + + + EDGE2 + Edge detected and masked on IO pin 2 + [2:2] + read-only + + + EDGE3 + Edge detected and masked on IO pin 3 + [3:3] + read-only + + + EDGE4 + Edge detected and masked on IO pin 4 + [4:4] + read-only + + + EDGE5 + Edge detected and masked on IO pin 5 + [5:5] + read-only + + + EDGE6 + Edge detected and masked on IO pin 6 + [6:6] + read-only + + + EDGE7 + Edge detected and masked on IO pin 7 + [7:7] + read-only + + + FLT_EDGE + Edge detected and masked on filtered pin selected by INTR_CFG.FLT_SEL + [8:8] + read-only + + + + + INTR_SET + Port interrupt set register + 0x20 + 32 + read-write + 0x0 + 0x1FF + + + EDGE0 + Sets edge detect interrupt for IO pin 0 +'0': Interrupt state not affected +'1': Interrupt set + [0:0] + read-write + + + EDGE1 + Sets edge detect interrupt for IO pin 1 + [1:1] + read-write + + + EDGE2 + Sets edge detect interrupt for IO pin 2 + [2:2] + read-write + + + EDGE3 + Sets edge detect interrupt for IO pin 3 + [3:3] + read-write + + + EDGE4 + Sets edge detect interrupt for IO pin 4 + [4:4] + read-write + + + EDGE5 + Sets edge detect interrupt for IO pin 5 + [5:5] + read-write + + + EDGE6 + Sets edge detect interrupt for IO pin 6 + [6:6] + read-write + + + EDGE7 + Sets edge detect interrupt for IO pin 7 + [7:7] + read-write + + + FLT_EDGE + Sets edge detect interrupt for filtered pin selected by INTR_CFG.FLT_SEL + [8:8] + read-write + + + + + INTR_CFG + Port interrupt configuration register + 0x40 + 32 + read-write + 0x0 + 0x1FFFFF + + + EDGE0_SEL + Sets which edge will trigger an IRQ for IO pin 0 + [1:0] + read-write + + + DISABLE + Disabled + 0 + + + RISING + Rising edge + 1 + + + FALLING + Falling edge + 2 + + + BOTH + Both rising and falling edges + 3 + + + + + EDGE1_SEL + Sets which edge will trigger an IRQ for IO pin 1 + [3:2] + read-write + + + EDGE2_SEL + Sets which edge will trigger an IRQ for IO pin 2 + [5:4] + read-write + + + EDGE3_SEL + Sets which edge will trigger an IRQ for IO pin 3 + [7:6] + read-write + + + EDGE4_SEL + Sets which edge will trigger an IRQ for IO pin 4 + [9:8] + read-write + + + EDGE5_SEL + Sets which edge will trigger an IRQ for IO pin 5 + [11:10] + read-write + + + EDGE6_SEL + Sets which edge will trigger an IRQ for IO pin 6 + [13:12] + read-write + + + EDGE7_SEL + Sets which edge will trigger an IRQ for IO pin 7 + [15:14] + read-write + + + FLT_EDGE_SEL + Sets which edge will trigger an IRQ for the glitch filtered pin (selected by INTR_CFG.FLT_SEL + [17:16] + read-write + + + DISABLE + Disabled + 0 + + + RISING + Rising edge + 1 + + + FALLING + Falling edge + 2 + + + BOTH + Both rising and falling edges + 3 + + + + + FLT_SEL + Selects which pin is routed through the 50ns glitch filter to provide a glitch-safe interrupt. + [20:18] + read-write + + + + + CFG + Port configuration register + 0x44 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DRIVE_MODE0 + The GPIO drive mode for IO pin 0. Resistive pull-up and pull-down is selected in the drive mode. +Note: when initializing IO's that are connected to a live bus (such as I2C), make sure the peripheral and HSIOM (HSIOM_PRT_SELx) is properly configured before turning the IO on here to avoid producing glitches on the bus. +Note: that peripherals other than GPIO & UDB/DSI directly control both the output and output-enable of the output buffer (peripherals can drive strong 0 or strong 1 in any mode except OFF='0'). +Note: D_OUT, D_OUT_EN are pins of GPIO cell. + [2:0] + read-write + + + HIGHZ + Output buffer is off creating a high impedance input +D_OUT = '0': High Impedance +D_OUT = '1': High Impedance + 0 + + + RSVD + N/A + 1 + + + PULLUP + Resistive pull up + +For GPIO & UDB/DSI peripherals: +When D_OUT_EN = 1: + D_OUT = '0': Strong pull down + D_OUT = '1': Weak/resistive pull up +When D_OUT_EN = 0: + D_OUT = '0': High impedance + D_OUT = '1': High impedance + +For peripherals other than GPIO & UDB/DSI: +When D_OUT_EN = 1: + D_OUT = '0': Strong pull down + D_OUT = '1': Strong pull up +When D_OUT_EN = 0: + D_OUT = '0': Weak/resistive pull up + D_OUT = '1': Weak/resistive pull up + 2 + + + PULLDOWN + Resistive pull down + +For GPIO & UDB/DSI peripherals: +When D_OUT_EN = 1: + D_OUT = '0': Weak/resistive pull down + D_OUT = '1': Strong pull up +When D_OUT_EN = 0: + D_OUT = '0': High impedance + D_OUT = '1': High impedance + +For peripherals other than GPIO & UDB/DSI: +When D_OUT_EN = 1: + D_OUT = '0': Strong pull down + D_OUT = '1': Strong pull up +When D_OUT_EN = 0: + D_OUT = '0': Weak/resistive pull down + D_OUT = '1': Weak/resistive pull down + 3 + + + OD_DRIVESLOW + Open drain, drives low + +For GPIO & UDB/DSI peripherals: +When D_OUT_EN = 1: + D_OUT = '0': Strong pull down + D_OUT = '1': High Impedance +When D_OUT_EN = 0: + D_OUT = '0': High impedance + D_OUT = '1': High impedance + +For peripherals other than GPIO & UDB/DSI: +When D_OUT_EN = 1: + D_OUT = '0': Strong pull down + D_OUT = '1': Strong pull up +When D_OUT_EN = 0: + D_OUT = '0': High Impedance + D_OUT = '1': High Impedance + 4 + + + OD_DRIVESHIGH + Open drain, drives high + +For GPIO & UDB/DSI peripherals: +When D_OUT_EN = 1: + D_OUT = '0': High Impedance + D_OUT = '1': Strong pull up +When D_OUT_EN = 0: + D_OUT = '0': High impedance + D_OUT = '1': High impedance + +For peripherals other than GPIO & UDB/DSI: +When D_OUT_EN = 1: + D_OUT = '0': Strong pull down + D_OUT = '1': Strong pull up +When D_OUT_EN = 0: + D_OUT = '0': High Impedance + D_OUT = '1': High Impedance + 5 + + + STRONG + Strong D_OUTput buffer + +For GPIO & UDB/DSI peripherals: +When D_OUT_EN = 1: + D_OUT = '0': Strong pull down + D_OUT = '1': Strong pull up +When D_OUT_EN = 0: + D_OUT = '0': High impedance + D_OUT = '1': High impedance + +For peripherals other than GPIO & UDB/DSI: +When D_OUT_EN = 1: + D_OUT = '0': Strong pull down + D_OUT = '1': Strong pull up +When D_OUT_EN = 0: + D_OUT = '0': High Impedance + D_OUT = '1': High Impedance + 6 + + + PULLUP_DOWN + Pull up or pull down + +For GPIO & UDB/DSI peripherals: +When D_OUT_EN = '0': + GPIO_DSI_OUT = '0': Weak/resistive pull down + GPIO_DSI_OUT = '1': Weak/resistive pull up +where 'GPIO_DSI_OUT' is a function of PORT_SEL, OUT & DSI_DATA_OUT. + +For peripherals other than GPIO & UDB/DSI: +When D_OUT_EN = 1: + D_OUT = '0': Strong pull down + D_OUT = '1': Strong pull up +When D_OUT_EN = 0: + D_OUT = '0': Weak/resistive pull down + D_OUT = '1': Weak/resistive pull up + 7 + + + + + IN_EN0 + Enables the input buffer for IO pin 0. This bit should be cleared when analog signals are present on the pin to avoid crowbar currents. The output buffer can be used to drive analog signals high or low without issue. +'0': Input buffer disabled +'1': Input buffer enabled + [3:3] + read-write + + + DRIVE_MODE1 + The GPIO drive mode for IO pin 1 + [6:4] + read-write + + + IN_EN1 + Enables the input buffer for IO pin 1 + [7:7] + read-write + + + DRIVE_MODE2 + The GPIO drive mode for IO pin 2 + [10:8] + read-write + + + IN_EN2 + Enables the input buffer for IO pin 2 + [11:11] + read-write + + + DRIVE_MODE3 + The GPIO drive mode for IO pin 3 + [14:12] + read-write + + + IN_EN3 + Enables the input buffer for IO pin 3 + [15:15] + read-write + + + DRIVE_MODE4 + The GPIO drive mode for IO pin4 + [18:16] + read-write + + + IN_EN4 + Enables the input buffer for IO pin 4 + [19:19] + read-write + + + DRIVE_MODE5 + The GPIO drive mode for IO pin 5 + [22:20] + read-write + + + IN_EN5 + Enables the input buffer for IO pin 5 + [23:23] + read-write + + + DRIVE_MODE6 + The GPIO drive mode for IO pin 6 + [26:24] + read-write + + + IN_EN6 + Enables the input buffer for IO pin 6 + [27:27] + read-write + + + DRIVE_MODE7 + The GPIO drive mode for IO pin 7 + [30:28] + read-write + + + IN_EN7 + Enables the input buffer for IO pin 7 + [31:31] + read-write + + + + + CFG_IN + Port input buffer configuration register + 0x48 + 32 + read-write + 0x0 + 0xFF + + + VTRIP_SEL0_0 + N/A + [0:0] + read-write + + + CMOS + S40E full encoding is shown in CFG_IN_AUTOLVL.VTRIP_SEL0_1 + 0 + + + TTL + S40E full encoding is shown in CFG_IN_AUTOLVL.VTRIP_SEL0_1 + 1 + + + + + VTRIP_SEL1_0 + N/A + [1:1] + read-write + + + VTRIP_SEL2_0 + N/A + [2:2] + read-write + + + VTRIP_SEL3_0 + N/A + [3:3] + read-write + + + VTRIP_SEL4_0 + N/A + [4:4] + read-write + + + VTRIP_SEL5_0 + N/A + [5:5] + read-write + + + VTRIP_SEL6_0 + N/A + [6:6] + read-write + + + VTRIP_SEL7_0 + N/A + [7:7] + read-write + + + + + CFG_OUT + Port output buffer configuration register + 0x4C + 32 + read-write + 0x0 + 0xFFFF00FF + + + SLOW0 + N/A + [0:0] + read-write + + + SLOW1 + N/A + [1:1] + read-write + + + SLOW2 + N/A + [2:2] + read-write + + + SLOW3 + N/A + [3:3] + read-write + + + SLOW4 + N/A + [4:4] + read-write + + + SLOW5 + N/A + [5:5] + read-write + + + SLOW6 + N/A + [6:6] + read-write + + + SLOW7 + N/A + [7:7] + read-write + + + DRIVE_SEL0 + Documentation: +Note: DRIVE_SELx are used among GPIO cells and HSIO_STD but the encoding values may differ as shown on the right side of this table + [17:16] + read-write + + + DRIVE_SEL_ZERO + S40E GPIO_STD/GPIO_ENH: Full drive strengh: GPIO drives current at its max rated spec. +S40E_GPIO_SMC: GPIO_SMC default mode. +S40E_HSIO_STD: HSIO default mode. +S40S GPIO cells and HSIO_STD cells: Full drive strength: GPIO drives current at its max rated spec. + 0 + + + DRIVE_SEL_ONE + S40E GPIO_STD/GPIO_ENH: Full drive strengh: GPIO drives current at its max rated spec. +S40E_GPIO_SMC: GPIO full drive strength. +S40E_HSIO_STD: GPIO full drive strength. +S40S GPIO cells and HSIO_STD cells: 1/2 drive strength: GPIO drives current at 1/2 of its max rated spec + 1 + + + DRIVE_SEL_TWO + S40E GPIO_STD/GPIO_ENH: 1/2 drive strength: GPIO drives current at 1/2 of its max rated spec. +S40E_GPIO_SMC: GPIO 1/2 drive strength. +S40E_HSIO_STD: GPIO 1/2 drive strength. +S40S GPIO cells and HSIO_STD cells: 1/4 drive strength. GPIO drives current at 1/4 of its max rated spec. + 2 + + + DRIVE_SEL_THREE + S40E GPIO_STD/GPIO_ENH: 1/4 drive strength: GPIO drives current at 1/4 of its max rated spec. +S40E_GPIO_SMC: GPIO 1/4 drive strength. +S40E_HSIO_STD: GPIO 1/4 drive strength. +S40S GPIO cells and HSIO_STD cells: 1/8 drive strength. GPIO drives current at 1/8 of its max rated spec. + 3 + + + + + DRIVE_SEL1 + N/A + [19:18] + read-write + + + DRIVE_SEL2 + N/A + [21:20] + read-write + + + DRIVE_SEL3 + N/A + [23:22] + read-write + + + DRIVE_SEL4 + N/A + [25:24] + read-write + + + DRIVE_SEL5 + N/A + [27:26] + read-write + + + DRIVE_SEL6 + N/A + [29:28] + read-write + + + DRIVE_SEL7 + N/A + [31:30] + read-write + + + + + CFG_SIO + Port SIO configuration register + 0x50 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VREG_EN01 + The regulated output mode is selected ONLY if the CFG.DRIVE_MODE bits are set to the strong pull up (Z_1 = '5') mode If the CFG.DRIVE_MODE bits are set to any other mode the regulated output buffer will be disabled and the standard CMOS output buffer is used. + [0:0] + read-write + + + IBUF_SEL01 + N/A + [1:1] + read-write + + + VTRIP_SEL01 + N/A + [2:2] + read-write + + + VREF_SEL01 + N/A + [4:3] + read-write + + + VOH_SEL01 + Selects trip-point of input buffer. In single ended input buffer mode (IBUF01_SEL = '0'): +0: input buffer functions as a CMOS input buffer. +1: input buffer functions as a LVTTL input buffer. +In differential input buffer mode (IBUF01_SEL = '1'): VTRIP_SEL=0: a) VREF_SEL=00, VOH_SEL=X -> Trip point=50 percent of vddio +b) VREF_SEL=01, VOH_SEL=000 -> Trip point=Vohref (buffered) +c) VREF_SEL=01, VOH_SEL=[1-7] -> Input buffer functions as CMOS input buffer. +d) VREF_SEL=10/11, VOH_SEL=000 -> Trip point=Amuxbus_a/b (buffered) +e) VREF_SEL=10/11, VOH_SEL=[1-7] -> Input buffer functions as CMOS input buffer. VTRIP_SEL=1: a) VREF_SEL=00, VOH_SEL=X -> Trip point=40 percent of vddio +b) VREF_SEL=01, VOH_SEL=000 -> Trip point=0.5*Vohref +c) VREF_SEL=01, VOH_SEL=[1-7] -> Input buffer functions as LVTTL input buffer. d) VREF_SEL=10/11, VOH_SEL=000 -> Trip point=0.5*Amuxbus_a/b (buffered) +e) VREF_SEL=10/11, VOH_SEL=[1-7] -> Input buffer functions as LVTTL input buffer. + [7:5] + read-write + + + VREG_EN23 + N/A + [8:8] + read-write + + + IBUF_SEL23 + N/A + [9:9] + read-write + + + VTRIP_SEL23 + N/A + [10:10] + read-write + + + VREF_SEL23 + N/A + [12:11] + read-write + + + VOH_SEL23 + N/A + [15:13] + read-write + + + VREG_EN45 + N/A + [16:16] + read-write + + + IBUF_SEL45 + N/A + [17:17] + read-write + + + VTRIP_SEL45 + N/A + [18:18] + read-write + + + VREF_SEL45 + N/A + [20:19] + read-write + + + VOH_SEL45 + N/A + [23:21] + read-write + + + VREG_EN67 + N/A + [24:24] + read-write + + + IBUF_SEL67 + N/A + [25:25] + read-write + + + VTRIP_SEL67 + N/A + [26:26] + read-write + + + VREF_SEL67 + N/A + [28:27] + read-write + + + VOH_SEL67 + N/A + [31:29] + read-write + + + + + CFG_IN_AUTOLVL + Port input buffer AUTOLVL configuration register for S40E GPIO + 0x58 + 32 + read-write + 0x0 + 0xFF + + + VTRIP_SEL0_1 + Configures the input buffer mode (trip points and hysteresis) for S40E GPIO upper bit. Lower bit is still selected by CFG_IN.VTRIP_SEL0_0 field. This field is used along with CFG_IN.VTRIP_SEL0_0 field as below: +{CFG_IN_AUTOLVL.VTRIP_SEL0_1,CFG_IN.VTRIP_SEL0_0}: +0,0: CMOS +0,1: TTL +1,0: input buffer is compatible with automotive. +1,1: input buffer is compatible with automotvie + [0:0] + read-write + + + CMOS_OR_TTL + Input buffer compatible with CMOS/TTL interfaces as described in CFG_IN.VTRIP_SEL0_0. + 0 + + + AUTO + Input buffer compatible with AUTO (elevated Vil) interfaces when used along with CFG_IN.VTRIP_SEL0_0. + 1 + + + + + VTRIP_SEL1_1 + Input buffer compatible with automotive (elevated Vil) interfaces. + [1:1] + read-write + + + VTRIP_SEL2_1 + Input buffer compatible with automotive (elevated Vil) interfaces. + [2:2] + read-write + + + VTRIP_SEL3_1 + Input buffer compatible with automotive (elevated Vil) interfaces. + [3:3] + read-write + + + VTRIP_SEL4_1 + Input buffer compatible with automotive (elevated Vil) interfaces. + [4:4] + read-write + + + VTRIP_SEL5_1 + Input buffer compatible with automotive (elevated Vil) interfaces. + [5:5] + read-write + + + VTRIP_SEL6_1 + Input buffer compatible with automotive (elevated Vil) interfaces. + [6:6] + read-write + + + VTRIP_SEL7_1 + Input buffer compatible with automotive (elevated Vil) interfaces. + [7:7] + read-write + + + + + + INTR_CAUSE0 + Interrupt port cause register 0 + 0x4000 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + PORT_INT + Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line 'gpio_interrupt'. The software ISR reads the register to determine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port's GPIO_PRT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt. +'0': Port has no pending interrupt +'1': Port has pending interrupt + [31:0] + read-only + + + + + INTR_CAUSE1 + Interrupt port cause register 1 + 0x4004 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + PORT_INT + Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line 'gpio_interrupt'. The software ISR reads the register to determine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port's GPIO_PORT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt. +'0': Port has no pending interrupt +'1': Port has pending interrupt + [31:0] + read-only + + + + + INTR_CAUSE2 + Interrupt port cause register 2 + 0x4008 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + PORT_INT + Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line 'gpio_interrupt'. The software ISR reads the register to determine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port's GPIO_PORT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt. +'0': Port has no pending interrupt +'1': Port has pending interrupt + [31:0] + read-only + + + + + INTR_CAUSE3 + Interrupt port cause register 3 + 0x400C + 32 + read-only + 0x0 + 0xFFFFFFFF + + + PORT_INT + Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line 'gpio_interrupt'. The software ISR reads the register to determine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port's GPIO_PORT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt. +'0': Port has no pending interrupt +'1': Port has pending interrupt + [31:0] + read-only + + + + + VDD_ACTIVE + Extern power supply detection register + 0x4010 + 32 + read-only + 0x0 + 0xC000FFFF + + + VDDIO_ACTIVE + Indicates presence or absence of VDDIO supplies (i.e. other than VDDD, VDDA) on the device (supplies are numbered 0..n-1). Note that VDDIO supplies have basic (crude) supply detectors only. If separate, robust, brown-out detection is desired on IO supplies, on-chip or off-chip analog resources need to provide it. For these bits to work reliable, the supply must be within valid spec range (per datasheet) or held at ground. Any in-between voltage has an undefined result. +'0': Supply is not present +'1': Supply is present + +When multiple VDDIO supplies are present, they will be assigned in alphanumeric ascending order to these bits during implementation. +For example 'vddusb, vddio_0, vddio_a, vbackup, vddio_r, vddio_1' are present then they will be assigned to these bits as below: +0: vbackup, +1: vddio_0, +2: vddio_1, +3: vddio_a, +4: vddio_r, +5: vddusb' + [15:0] + read-only + + + VDDA_ACTIVE + Same as VDDIO_ACTIVE for the analog supply VDDA. + [30:30] + read-only + + + VDDD_ACTIVE + This bit indicates presence of the VDDD supply. This bit will always read-back 1. The VDDD supply has robust brown-out protection monitoring and it is not possible to read back this register without a valid supply. (This bit is used in certain test-modes to observe the brown-out detector status.) + [31:31] + read-only + + + + + VDD_INTR + Supply detection interrupt register + 0x4014 + 32 + read-write + 0x0 + 0xC000FFFF + + + VDDIO_ACTIVE + Supply state change detected. +'0': No change to supply detected +'1': Change to supply detected + [15:0] + read-write + + + VDDA_ACTIVE + Same as VDDIO_ACTIVE for the analog supply VDDA. + [30:30] + read-write + + + VDDD_ACTIVE + The VDDD supply is always present during operation so a supply transition can not occur. This bit will always read back '1'. + [31:31] + read-write + + + + + VDD_INTR_MASK + Supply detection interrupt mask register + 0x4018 + 32 + read-write + 0x0 + 0xC000FFFF + + + VDDIO_ACTIVE + Masks supply interrupt on VDDIO. +'0': VDDIO interrupt forwarding disabled +'1': VDDIO interrupt forwarding enabled + [15:0] + read-write + + + VDDA_ACTIVE + Same as VDDIO_ACTIVE for the analog supply VDDA. + [30:30] + read-write + + + VDDD_ACTIVE + Same as VDDIO_ACTIVE for the digital supply VDDD. + [31:31] + read-write + + + + + VDD_INTR_MASKED + Supply detection interrupt masked register + 0x401C + 32 + read-only + 0x0 + 0xC000FFFF + + + VDDIO_ACTIVE + Supply transition detected AND masked +'0': Interrupt was not forwarded to CPU +'1': Interrupt occurred and was forwarded to CPU + [15:0] + read-only + + + VDDA_ACTIVE + Same as VDDIO_ACTIVE for the analog supply VDDA. + [30:30] + read-only + + + VDDD_ACTIVE + Same as VDDIO_ACTIVE for the digital supply VDDD. + [31:31] + read-only + + + + + VDD_INTR_SET + Supply detection interrupt set register + 0x4020 + 32 + read-write + 0x0 + 0xC000FFFF + + + VDDIO_ACTIVE + Sets supply interrupt. +'0': Interrupt state not affected +'1': Interrupt set + [15:0] + read-write + + + VDDA_ACTIVE + Same as VDDIO_ACTIVE for the analog supply VDDA. + [30:30] + read-write + + + VDDD_ACTIVE + Same as VDDIO_ACTIVE for the digital supply VDDD. + [31:31] + read-write + + + + + + + SMARTIO + Programmable IO configuration + 0x40320000 + + 0 + 65536 + registers + + + + 10 + 256 + PRT[%s] + Programmable IO port registers + 0x00000000 + + CTL + Control register + 0x0 + 32 + read-write + 0x2001400 + 0x82001F00 + + + BYPASS + Bypass of the programmable IO, one bit for each IO pin: BYPASS[i] is for IO pin i. When ENABLED is '1', this field is used. When ENABLED is '0', this field is NOT used and SMARTIO fabric is always bypassed. +'0': No bypass (programmable SMARTIO fabric is exposed). +'1': Bypass (programmable SMARTIOIO fabric is hidden). + [7:0] + read-write + + + CLOCK_SRC + Clock ('clk_fabric') and reset ('rst_fabric_n') source selection: +'0': io_data_in[0]/'1'. +... +'7': io_data_in[7]/'1'. +'8': chip_data[0]/'1'. +... +'15': chip_data[7]/'1'. +'16': clk_smartio/rst_sys_act_n. Used for both Active functionality synchronous logic on 'clk_smartio'. This selection is intended for synchronous operation on a PCLK specified clock frequency ('clock_smartio_pos_en'). Note that the fabric's clocked elements are frequency aligned, but NOT phase aligned to 'clk_sys'. +'17': clk_smartio/rst_sys_dpslp_n. Used for both DeepSleep functionality synchronous logic on 'clk_smartio' (note that 'clk_smartio' is NOT available in DeepSleep and Hibernate power modes). This selection is intended for synchronous operation on a PCLK specified clock frequency ('clock_smartio_pos_en'). Note that the fabric's clocked elements are frequency aligned, but NOT phase aligned to 'clk_sys'. +'18': Same as '17'. Note that the M0S8 SMARTIO version used the Hibernate reset for this value, but the MXS40 SMARTIO version does not support Hibernate functionality. +'19': clk_lf/rst_lf_dpslp_n (note that 'clk_lf' is available in DeepSleep power mode). This selection is intended for synchronous operation on'clk_lf'. Note that the fabric's clocked elements are frequency aligned, but NOT phase aligned to other 'clk_lf' clocked elements. +'20'-'30': Clock source is constant '0'. Any of these clock sources should be selected when the IP is disabled to ensure low power consumption. +'31': asynchronous mode/'1'. Select this when clockless operation is configured. + +NOTE: Two positive edges of the selected clock are required for the block to be enabled (to deactivate reset). In asynchronous (clockless) mode clk_sys is used to enable the block, but is not available for clocking. + [12:8] + read-write + + + HLD_OVR + IO cell hold override functionality. In DeepSleep power mode, the HSIOM holds the IO cell output and output enable signals if Active functionality is connected to the IO pads. This is undesirable if the SMARTIO is supposed to deliver DeepSleep output functionality on these IO pads. This field is used to control the hold override functionality from the SMARTIO: +'0': The HSIOM controls the IO cell hold override functionality ('hsiom_hld_ovr'). +'1': The SMARTIO controls the IO cel hold override functionality: +- In bypass mode (ENABLED is '0' or BYPASS[i] is '1'), the HSIOM control is used. +- In NON bypass mode (ENABLED is '1' and BYPASS[i] is '0'), the SMARTIO sets hold override to 'pwr_hld_ovr_hib' to enable SMARTIO functionality in DeepSleep power mode (but disables it in Hibernate or Stop power mode). + [24:24] + read-write + + + PIPELINE_EN + Enable for pipeline register: +'0': Disabled (register is bypassed). +'1': Enabled. + [25:25] + read-write + + + ENABLED + Enable for programmable IO. Should only be set to '1' when the programmable IO is completely configured: +'0': Disabled (signals are bypassed; behavior as if BYPASS is 0xFF). When disabled, the fabric (data unit and LUTs) reset is activated. + +If the IP is disabled: +- The PIPELINE_EN register field should be set to '1', to ensure low power consumption by preventing combinatorial loops. +- The CLOCK_SRC register field should be set to '20'-'30' (clock is constant '0'), to ensure low power consumption. + +'1': Enabled. Once enabled, it takes 3 'clk_fabric' clock cycles till the fabric reset is de-activated and the fabric becomes fully functional. This ensures that the IO pins' input synchronizer states are flushed when the fabric is fully functional. + [31:31] + read-write + + + + + SYNC_CTL + Synchronization control register + 0x10 + 32 + read-write + 0x0 + 0x0 + + + IO_SYNC_EN + Synchronization of the IO pin input signals to 'clk_fabric', one bit for each IO pin: IO_SYNC_EN[i] is for IO pin i. +'0': No synchronization. +'1': Synchronization. + [7:0] + read-write + + + CHIP_SYNC_EN + Synchronization of the chip input signals to 'clk_fabric', one bit for each input: CHIP_SYNC_EN[i] is for input i. +'0': No synchronization. +'1': Synchronization. + [15:8] + read-write + + + + + 8 + 4 + LUT_SEL[%s] + LUT component input selection + 0x20 + 32 + read-write + 0x0 + 0x0 + + + LUT_TR0_SEL + LUT input signal 'tr0_in' source selection: +'0': Data unit output. +'1': LUT 1 output. +'2': LUT 2 output. +'3': LUT 3 output. +'4': LUT 4 output. +'5': LUT 5 output. +'6': LUT 6 output. +'7': LUT 7 output. +'8': chip_data[0] (for LUTs 0, 1, 2, 3); chip_data[4] (for LUTs 4, 5, 6, 7). +'9': chip_data[1] (for LUTs 0, 1, 2, 3); chip_data[5] (for LUTs 4, 5, 6, 7). +'10': chip_data[2] (for LUTs 0, 1, 2, 3); chip_data[6] (for LUTs 4, 5, 6, 7). +'11': chip_data[3] (for LUTs 0, 1, 2, 3); chip_data[7] (for LUTs 4, 5, 6, 7). +'12': io_data_in[0] (for LUTs 0, 1, 2, 3); io_data_in[4] (for LUTs 4, 5, 6, 7). +'13': io_data_in[1] (for LUTs 0, 1, 2, 3); io_data_in[5] (for LUTs 4, 5, 6, 7). +'14': io_data_in[2] (for LUTs 0, 1, 2, 3); io_data_in[6] (for LUTs 4, 5, 6, 7). +'15': io_data_in[3] (for LUTs 0, 1, 2, 3); io_data_in[7] (for LUTs 4, 5, 6, 7). + [3:0] + read-write + + + LUT_TR1_SEL + LUT input signal 'tr1_in' source selection: +'0': LUT 0 output. +'1': LUT 1 output. +'2': LUT 2 output. +'3': LUT 3 output. +'4': LUT 4 output. +'5': LUT 5 output. +'6': LUT 6 output. +'7': LUT 7 output. +'8': chip_data[0] (for LUTs 0, 1, 2, 3); chip_data[4] (for LUTs 4, 5, 6, 7). +'9': chip_data[1] (for LUTs 0, 1, 2, 3); chip_data[5] (for LUTs 4, 5, 6, 7). +'10': chip_data[2] (for LUTs 0, 1, 2, 3); chip_data[6] (for LUTs 4, 5, 6, 7). +'11': chip_data[3] (for LUTs 0, 1, 2, 3); chip_data[7] (for LUTs 4, 5, 6, 7). +'12': io_data_in[0] (for LUTs 0, 1, 2, 3); io_data_in[4] (for LUTs 4, 5, 6, 7). +'13': io_data_in[1] (for LUTs 0, 1, 2, 3); io_data_in[5] (for LUTs 4, 5, 6, 7). +'14': io_data_in[2] (for LUTs 0, 1, 2, 3); io_data_in[6] (for LUTs 4, 5, 6, 7). +'15': io_data_in[3] (for LUTs 0, 1, 2, 3); io_data_in[7] (for LUTs 4, 5, 6, 7). + [11:8] + read-write + + + LUT_TR2_SEL + LUT input signal 'tr2_in' source selection. Encoding is the same as for LUT_TR1_SEL. + [19:16] + read-write + + + + + 8 + 4 + LUT_CTL[%s] + LUT component control register + 0x40 + 32 + read-write + 0x0 + 0x0 + + + LUT + LUT configuration. Depending on the LUT opcode LUT_OPC, the internal state lut_reg (captured in a flip-flop) and the LUT input signals tr0_in, tr1_in, tr2_in, the LUT configuration is used to determine the LUT output signal and the next sequential state (lut_reg). + [7:0] + read-write + + + LUT_OPC + LUT opcode specifies the LUT operation: +'0': Combinatoral output, no feedback. + tr_out = LUT[{tr2_in, tr1_in, tr0_in}]. +'1': Combinatorial output, feedback. + tr_out = LUT[{lut_reg, tr1_in, tr0_in}]. +On clock: + lut_reg <= tr_in2. +'2': Sequential output, no feedback. + temp = LUT[{tr2_in, tr1_in, tr0_in}]. + tr_out = lut_reg. +On clock: + lut_reg <= temp. +'3': Register with asynchronous set and reset. + tr_out = lut_reg. + enable = (tr2_in ^ LUT[4]) | LUT[5]. + set = enable & (tr1_in ^ LUT[2]) & LUT[3]. + clr = enable & (tr0_in ^ LUT[0]) & LUT[1]. +Asynchronously (no clock required): + lut_reg <= if (clr) '0' else if (set) '1' + [9:8] + read-write + + + + + DU_SEL + Data unit component input selection + 0xC0 + 32 + read-write + 0x0 + 0x0 + + + DU_TR0_SEL + Data unit input signal 'tr0_in' source selection: +'0': Constant '0'. +'1': Constant '1'. +'2': Data unit output. +'10-3': LUT 7 - 0 outputs. +Otherwise: Undefined. + [3:0] + read-write + + + DU_TR1_SEL + Data unit input signal 'tr1_in' source selection. Encoding is the same as for DU_TR0_SEL. + [11:8] + read-write + + + DU_TR2_SEL + Data unit input signal 'tr2_in' source selection. Encoding is the same as for DU_TR0_SEL. + [19:16] + read-write + + + DU_DATA0_SEL + Data unit input data 'data0_in' source selection: +'0': Constant '0'. +'1': chip_data[7:0]. +'2': io_data_in[7:0]. +'3': DATA.DATA MMIO register field. + [25:24] + read-write + + + DU_DATA1_SEL + Data unit input data 'data1_in' source selection. Encoding is the same as for DU_DATA0_SEL. + [29:28] + read-write + + + + + DU_CTL + Data unit component control register + 0xC4 + 32 + read-write + 0x0 + 0x0 + + + DU_SIZE + Size/width of the data unit data operands (in bits) is DU_SIZE+1. E.g., if DU_SIZE is 7, the width is 8 bits. + [2:0] + read-write + + + DU_OPC + Data unit opcode specifies the data unit operation: +'1': INCR +'2': DECR +'3': INCR_WRAP +'4': DECR_WRAP +'5': INCR_DECR +'6': INCR_DECR_WRAP +'7': ROR +'8': SHR +'9': AND_OR +'10': SHR_MAJ3 +'11': SHR_EQL. +Otherwise: Undefined. + [11:8] + read-write + + + + + DATA + Data register + 0xF0 + 32 + read-write + 0x0 + 0x0 + + + DATA + Data unit input data source. + [7:0] + read-write + + + + + + + + LPCOMP + Low Power Comparators + 0x40350000 + + 0 + 65536 + registers + + + + CONFIG + LPCOMP Configuration Register + 0x0 + 32 + read-write + 0x0 + 0xC0000000 + + + LPREF_EN + Enable the local reference generator circuit to generate the local Vref and ibias. This bit must be set for DeepSleep or Hibernate operation. + [30:30] + read-write + + + ENABLED + - 0: IP disabled (put analog in power down, open all switches, all clocks off, leakage power only) +- 1: IP enabled + [31:31] + read-write + + + + + STATUS + LPCOMP Status Register + 0x4 + 32 + read-only + 0x0 + 0x10001 + + + OUT0 + Current output value of the comparator 0. + [0:0] + read-only + + + OUT1 + Current output value of the comparator 1. + [16:16] + read-only + + + + + INTR + LPCOMP Interrupt request register + 0x10 + 32 + read-write + 0x0 + 0x3 + + + COMP0 + Comparator 0 Interrupt: hardware sets this interrupt when comparator 0 triggers. Write with '1' to clear bit. + [0:0] + read-write + + + COMP1 + Comparator 1 Interrupt: hardware sets this interrupt when comparator 1 triggers. Write with '1' to clear bit. + [1:1] + read-write + + + + + INTR_SET + LPCOMP Interrupt set register + 0x14 + 32 + read-write + 0x0 + 0x3 + + + COMP0 + Write with '1' to set corresponding bit in interrupt request register. + [0:0] + read-write + + + COMP1 + Write with '1' to set corresponding bit in interrupt request register. + [1:1] + read-write + + + + + INTR_MASK + LPCOMP Interrupt request mask + 0x18 + 32 + read-write + 0x0 + 0x3 + + + COMP0_MASK + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + COMP1_MASK + Mask bit for corresponding bit in interrupt request register. + [1:1] + read-write + + + + + INTR_MASKED + LPCOMP Interrupt request masked + 0x1C + 32 + read-only + 0x0 + 0x3 + + + COMP0_MASKED + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + COMP1_MASKED + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + + + CMP0_CTRL + Comparator 0 control Register + 0x40 + 32 + read-write + 0x0 + 0xCE3 + + + MODE0 + Operating mode for the comparator + [1:0] + read-write + + + OFF + Off + 0 + + + ULP + Ultra lowpower operating mode (uses less power, < 300nA), must be used for DeepSleep or Hibernate. Only in this mode a local iref will be used. + 1 + + + LP + Low Power operating mode (uses more power, <10uA @@@ TBD). In this mode the iref from SRSS will be used. + 2 + + + NORMAL + Normal, full speed power operating mode (uses <150uA). In this mode the iref from SRSS will be used. + 3 + + + + + HYST0 + Add 30mV hysteresis to the comparator +0= Disable Hysteresis +1= Enable Hysteresis + [5:5] + read-write + + + INTTYPE0 + Sets which edge will trigger an IRQ + [7:6] + read-write + + + DISABLE + Disabled, no interrupts will be detected + 0 + + + RISING + Rising edge + 1 + + + FALLING + Falling edge + 2 + + + BOTH + Both rising and falling edges + 3 + + + + + DSI_BYPASS0 + Asynchronous: bypass comparator output synchronization for DSI output: 0=synchronize (level or pulse), 1=bypass (output async). +Note that in DeepSleep mode this bit needs to be set to observe the DSI output on the dedicated pin. + [10:10] + read-write + + + DSI_LEVEL0 + Synchronous comparator DSI (trigger) output : 0=pulse, 1=level + [11:11] + read-write + + + + + CMP0_SW + Comparator 0 switch control + 0x50 + 32 + read-write + 0x0 + 0xF7 + + + CMP0_IP0 + Comparator 0 positive terminal isolation switch to GPIO + [0:0] + read-write + + + CMP0_AP0 + Comparator 0 positive terminal switch to amuxbusA + [1:1] + read-write + + + CMP0_BP0 + Comparator 0 positive terminal switch to amuxbusB + [2:2] + read-write + + + CMP0_IN0 + Comparator 0 negative terminal isolation switch to GPIO + [4:4] + read-write + + + CMP0_AN0 + Comparator 0 negative terminal switch to amuxbusA + [5:5] + read-write + + + CMP0_BN0 + Comparator 0 negative terminal switch to amuxbusB + [6:6] + read-write + + + CMP0_VN0 + Comparator 0 negative terminal switch to local Vref (LPREF_EN must be set) + [7:7] + read-write + + + + + CMP0_SW_CLEAR + Comparator 0 switch control clear + 0x54 + 32 + read-write + 0x0 + 0xF7 + + + CMP0_IP0 + see corresponding bit in CMP0_SW + [0:0] + read-write + + + CMP0_AP0 + see corresponding bit in CMP0_SW + [1:1] + read-write + + + CMP0_BP0 + see corresponding bit in CMP0_SW + [2:2] + read-write + + + CMP0_IN0 + see corresponding bit in CMP0_SW + [4:4] + read-write + + + CMP0_AN0 + see corresponding bit in CMP0_SW + [5:5] + read-write + + + CMP0_BN0 + see corresponding bit in CMP0_SW + [6:6] + read-write + + + CMP0_VN0 + see corresponding bit in CMP0_SW + [7:7] + read-write + + + + + CMP1_CTRL + Comparator 1 control Register + 0x80 + 32 + read-write + 0x0 + 0xCE3 + + + MODE1 + Operating mode for the comparator + [1:0] + read-write + + + OFF + Off + 0 + + + ULP + Ultra lowpower operating mode (uses less power, < 300nA), must be used for DeepSleep or Hibernate. Only in this mode a local iref will be used. + 1 + + + LP + Low Power operating mode (uses more power, <10uA @@@ TBD). In this mode the iref from SRSS will be used. + 2 + + + NORMAL + Normal, full speed power operating mode (uses <150uA). In this mode the iref from SRSS will be used. + 3 + + + + + HYST1 + Add 30mV hysteresis to the comparator +0= Disable Hysteresis +1= Enable Hysteresis + [5:5] + read-write + + + INTTYPE1 + Sets which edge will trigger an IRQ + [7:6] + read-write + + + DISABLE + Disabled, no interrupts will be detected + 0 + + + RISING + Rising edge + 1 + + + FALLING + Falling edge + 2 + + + BOTH + Both rising and falling edges + 3 + + + + + DSI_BYPASS1 + Asynchronous: bypass comparator output synchronization for DSI output: 0=synchronize (level or pulse), 1=bypass (output async). +Note that in DeepSleep mode this bit needs to be set to observe the DSI output on the dedicated pin. + [10:10] + read-write + + + DSI_LEVEL1 + Synchronous comparator DSI (trigger) output : 0=pulse, 1=level + [11:11] + read-write + + + + + CMP1_SW + Comparator 1 switch control + 0x90 + 32 + read-write + 0x0 + 0xF7 + + + CMP1_IP1 + Comparator 1 positive terminal isolation switch to GPIO + [0:0] + read-write + + + CMP1_AP1 + Comparator 1 positive terminal switch to amuxbusA + [1:1] + read-write + + + CMP1_BP1 + Comparator 1 positive terminal switch to amuxbusB + [2:2] + read-write + + + CMP1_IN1 + Comparator 1 negative terminal isolation switch to GPIO + [4:4] + read-write + + + CMP1_AN1 + Comparator 1 negative terminal switch to amuxbusA + [5:5] + read-write + + + CMP1_BN1 + Comparator 1 negative terminal switch to amuxbusB + [6:6] + read-write + + + CMP1_VN1 + Comparator 1 negative terminal switch to local Vref (LPREF_EN must be set) + [7:7] + read-write + + + + + CMP1_SW_CLEAR + Comparator 1 switch control clear + 0x94 + 32 + read-write + 0x0 + 0xF7 + + + CMP1_IP1 + see corresponding bit in CMP1_SW + [0:0] + read-write + + + CMP1_AP1 + see corresponding bit in CMP1_SW + [1:1] + read-write + + + CMP1_BP1 + see corresponding bit in CMP1_SW + [2:2] + read-write + + + CMP1_IN1 + see corresponding bit in CMP1_SW + [4:4] + read-write + + + CMP1_AN1 + see corresponding bit in CMP1_SW + [5:5] + read-write + + + CMP1_BN1 + see corresponding bit in CMP1_SW + [6:6] + read-write + + + CMP1_VN1 + see corresponding bit in CMP1_SW + [7:7] + read-write + + + + + + + CSD0 + Capsense Controller + CSD + 0x40360000 + + 0 + 4096 + registers + + + + CONFIG + Configuration and Control + 0x0 + 32 + read-write + 0x4000000 + 0xCF0E1DF1 + + + IREF_SEL + N/A + [0:0] + read-write + + + IREF_SRSS + N/A + 0 + + + IREF_PASS + N/A + 1 + + + + + FILTER_DELAY + Enables the digital filtering on the CSD comparator + [8:4] + read-write + + + SHIELD_DELAY + Configures the delay between shield clock and sensor clock + [11:10] + read-write + + + OFF + Delay line is off; sensor clock = shield clock + 0 + + + D5NS + shield clock is delayed by 5ns delay w.r.t sensor clock + 1 + + + D10NS + shield clock is delayed by 10ns delay w.r.t sensor clock + 2 + + + D20NS + shield clock is delayed by 20ns delay w.r.t sensor clock + 3 + + + + + SENSE_EN + Enables the sensor and shield clocks, CSD modulator output and turns on the IDAC compensation current as selected by CSD_IDAC. + [12:12] + read-write + + + FULL_WAVE + N/A + [17:17] + read-write + + + HALFWAVE + Half Wave mode + 0 + + + FULLWAVE + Full Wave mode + 1 + + + + + MUTUAL_CAP + N/A + [18:18] + read-write + + + SELFCAP + Self-cap mode + 0 + + + MUTUALCAP + Mutual-cap mode + 1 + + + + + CSX_DUAL_CNT + N/A + [19:19] + read-write + + + ONE + N/A + 0 + + + TWO + N/A + 1 + + + + + DSI_COUNT_SEL + N/A + [24:24] + read-write + + + CSD_RESULT + N/A + 0 + + + ADC_RESULT + N/A + 1 + + + + + DSI_SAMPLE_EN + DSI_SAMPLE_EN = 1 -> COUNTER will count the samples generated by DSI +DSI_SAMPLE_EN = 0 -> COUNTER will count the samples generated by CSD modulator + [25:25] + read-write + + + SAMPLE_SYNC + N/A + [26:26] + read-write + + + DSI_SENSE_EN + DSI_SENSE_EN = 1-> sensor clock is driven directly by DSI +DSI_SENSE_EN = 0-> sensor clock is driven by PRS/divide-by-2/DIRECT_CLOCK + [27:27] + read-write + + + LP_MODE + N/A + [30:30] + read-write + + + ENABLE + N/A + [31:31] + read-write + + + + + SPARE + Spare MMIO + 0x4 + 32 + read-write + 0x0 + 0xF + + + SPARE + Spare MMIO + [3:0] + read-write + + + + + STATUS + Status Register + 0x80 + 32 + read-only + 0x0 + 0xE + + + CSD_SENSE + Only for Debug/test purpose this internal signal (sensor clock) status can be read by CPU + [1:1] + read-only + + + HSCMP_OUT + Only for Debug/test purpose the output status of CSD comparator can be read by CPU + [2:2] + read-only + + + C_LT_VREF + N/A + 0 + + + C_GT_VREF + N/A + 1 + + + + + CSDCMP_OUT + Only for Debug/test purpose the output status of CSD modulator can be read by CPU + [3:3] + read-only + + + + + STAT_SEQ + Current Sequencer status + 0x84 + 32 + read-only + 0x0 + 0x70007 + + + SEQ_STATE + CSD sequencer state + [2:0] + read-only + + + ADC_STATE + ADC sequencer state (only relevant after SEQ_STATE has reached SAMPLE_NORM and ADC sequencer has started) + [18:16] + read-only + + + + + STAT_CNTS + Current status counts + 0x88 + 32 + read-only + 0x0 + 0xFFFF + + + NUM_CONV + Current number of conversions remaining when in Sample_* states (note that in AutoZero* states the same down counter is reused to count the cycles) + [15:0] + read-only + + + + + STAT_HCNT + Current count of the HSCMP counter + 0x8C + 32 + read-only + 0x0 + 0xFFFF + + + CNT + Current value of HSCMP counter + [15:0] + read-only + + + + + RESULT_VAL1 + Result CSD/CSX accumulation counter value 1 + 0xD0 + 32 + read-only + 0x0 + 0xFFFFFF + + + VALUE + Accumulated counter value for this result. In case of Mutual cap with two counters (CSX = config.mutual_cap & config.csx_dual_cnt) this counter counts when csd_sense is high. + [15:0] + read-only + + + BAD_CONVS + Number of 'bad' conversion for which the CSD comparator did not trigger within the normal time window, either because Vref was not crossed at all, or if the Vref was already crossed before the window started. This counter is reset when the sequencer is started and will saturate at 255 when more than 255 conversions are bad. + [23:16] + read-only + + + + + RESULT_VAL2 + Result CSX accumulation counter value 2 + 0xD4 + 32 + read-only + 0x0 + 0xFFFF + + + VALUE + Only used in case of Mutual cap with two counters (CSX = config.mutual_cap & config.csx_dual_cnt), this counter counts when csd_sense is low. + [15:0] + read-only + + + + + ADC_RES + ADC measurement + 0xE0 + 32 + read-only + 0x0 + 0xC001FFFF + + + VIN_CNT + Count to source/sink Cref1 + Cref2 from Vin to Vrefhi. + [15:0] + read-only + + + HSCMP_POL + Polarity used for IDACB for this last ADC result, 0= source, 1= sink + [16:16] + read-only + + + ADC_OVERFLOW + This flag is set when the ADC counter overflows. This is an indication to the firmware that the IDACB current level is too low. + [30:30] + read-only + + + ADC_ABORT + This flag is set when the ADC sequencer was aborted before tripping HSCMP. + [31:31] + read-only + + + + + INTR + CSD Interrupt Request Register + 0xF0 + 32 + read-write + 0x0 + 0x106 + + + SAMPLE + A normal sample is complete + [1:1] + read-write + + + INIT + Coarse initialization complete or Sample initialization complete (the latter is typically ignored) + [2:2] + read-write + + + ADC_RES + ADC Result ready + [8:8] + read-write + + + + + INTR_SET + CSD Interrupt set register + 0xF4 + 32 + read-write + 0x0 + 0x106 + + + SAMPLE + Write with '1' to set corresponding bit in interrupt request register. + [1:1] + read-write + + + INIT + Write with '1' to set corresponding bit in interrupt request register. + [2:2] + read-write + + + ADC_RES + Write with '1' to set corresponding bit in interrupt request register. + [8:8] + read-write + + + + + INTR_MASK + CSD Interrupt mask register + 0xF8 + 32 + read-write + 0x0 + 0x106 + + + SAMPLE + Mask bit for corresponding bit in interrupt request register. + [1:1] + read-write + + + INIT + Mask bit for corresponding bit in interrupt request register. + [2:2] + read-write + + + ADC_RES + Mask bit for corresponding bit in interrupt request register. + [8:8] + read-write + + + + + INTR_MASKED + CSD Interrupt masked register + 0xFC + 32 + read-only + 0x0 + 0x106 + + + SAMPLE + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + INIT + Logical and of corresponding request and mask bits. + [2:2] + read-only + + + ADC_RES + Logical and of corresponding request and mask bits. + [8:8] + read-only + + + + + HSCMP + High Speed Comparator configuration + 0x180 + 32 + read-write + 0x0 + 0x80000011 + + + HSCMP_EN + High Speed Comparator enable + [0:0] + read-write + + + OFF + Disable comparator, output is zero + 0 + + + ON + On, regular operation. Note that CONFIG.LP_MODE determines the power mode level + 1 + + + + + HSCMP_INVERT + Invert the HSCMP output before it is used to control switches and the CSD sequencer. This bit does not affect the ADC sequencer or the STATUS.HSCMP_OUT + [4:4] + read-write + + + AZ_EN + Auto-Zero enable, allow the Sequencer to Auto-Zero this component + [31:31] + read-write + + + + + AMBUF + Reference Generator configuration + 0x184 + 32 + read-write + 0x0 + 0x3 + + + PWR_MODE + Amux buffer power level + [1:0] + read-write + + + OFF + Disable buffer + 0 + + + NORM + On, normal or low power level depending on CONFIG.LP_MODE. + 1 + + + HI + On, high or low power level depending on CONFIG.LP_MODE. + 2 + + + + + + + REFGEN + Reference Generator configuration + 0x188 + 32 + read-write + 0x0 + 0x9F1F71 + + + REFGEN_EN + Reference Generator Enable + [0:0] + read-write + + + OFF + Disable Reference Generator + 0 + + + ON + On, regular operation. Note that CONFIG.LP_MODE determines the power mode level + 1 + + + + + BYPASS + Bypass selected input reference unbuffered to Vrefhi + [4:4] + read-write + + + VDDA_EN + Close Vdda switch to top of resistor string (or Vrefhi?) + [5:5] + read-write + + + RES_EN + Resistor string enable; 0= open switch on top of the resistor string (Vreflo=Vssa) + [6:6] + read-write + + + GAIN + Select resistor string tap for feedback, 0= minimum vout, 31= maximum vout = vrefhi -> gain=1 (only works if the resistor string is enabled; RES_EN=1) + [12:8] + read-write + + + VREFLO_SEL + Select resistor string tap for Vreflo/Vreflo_int, 0= minimum vout, 31= maximum vout = vrefhi (only works if the resistor string is enabled; RES_EN=1) + [20:16] + read-write + + + VREFLO_INT + Ouput the resistor string tap either to Vreflo (0) or Vreflo_int (1). + [23:23] + read-write + + + + + CSDCMP + CSD Comparator configuration + 0x18C + 32 + read-write + 0x0 + 0xB0000331 + + + CSDCMP_EN + CSD Comparator Enable + [0:0] + read-write + + + OFF + Disable comparator, output is zero + 0 + + + ON + On, regular operation. Note that CONFIG.LP_MODE determines the power mode level + 1 + + + + + POLARITY_SEL + Select which IDAC polarity to use to detect CSDCMP triggering + [5:4] + read-write + + + IDACA_POL + Use idaca_pol (firmware setting with CSX and optionally DSI mixed in) to determine the direction, this is the most common use-case, used for normal CSD and normal CSX + 0 + + + IDACB_POL + Use idacb_pol (firmware setting with optional DSI mixed in) to determine the direction, this is only used for normal CSD if IDACB is used i.s.o. IDACA (not common) + 1 + + + DUAL_POL + Use the expression (csd_sense ? idaca_pol : idacb_pol) to determine the direction, this is only useful for the CSX with DUAL_IDAC use-case + 2 + + + + + CMP_PHASE + Select in what phase(s) the comparator is active, typically set to match the BAL_MODE of the used IDAC. Note, this also determines when a bad conversion is detected, namely at the beginning and end of the comparator active phase (also taking into account FILTER_DELAY and non-overlap). + [9:8] + read-write + + + FULL + Comparator is active from start of Phi2 and kept active into Phi1. Intended usage: legacy CSD for balancing over a full csd_sense period (non-overlap should be turned off) + 0 + + + PHI1 + Comparator is active during Phi1 only. Currently no known use-case. + 1 + + + PHI2 + Comparator is active during Phi2 only. Intended usage: CSD Low EMI. + 2 + + + PHI1_2 + Comparator is activated at the start of both Phi1 and Phi2 (non-overlap should be enabled). Intended usage: CSX, or Full-Wave. + 3 + + + + + CMP_MODE + Select which signal to output on dsi_sample_out. + [28:28] + read-write + + + CSD + CSD mode: output the filtered sample signal on dsi_sample_out + 0 + + + GP + General Purpose mode: output the unfiltered sample unfiltered comparator output, either asynchronous or flopped. + 1 + + + + + FEEDBACK_MODE + This bit controls whether the output directly from the comparator (csdcmp_out) or the flopped version (csdcmp_out_ff) is used. For CSD operation, the selected signal controls the IDAC(s), in GP mode the signal goes out on dsi_sample_out. + [29:29] + read-write + + + FLOP + Use feedback from sampling flip-flop (used in most modes). + 0 + + + COMP + Use feedback from comparator directly (used in single Cmod mutual cap sensing only) + 1 + + + + + AZ_EN + Auto-Zero enable, allow the Sequencer to Auto-Zero this component + [31:31] + read-write + + + + + SW_RES + Switch Resistance configuration + 0x1F0 + 32 + read-write + 0x0 + 0xF00FF + + + RES_HCAV + Select resistance or low EMI (slow ramp) for the HCAV switch + [1:0] + read-write + + + LOW + Low + 0 + + + MED + Medium + 1 + + + HIGH + High + 2 + + + LOWEMI + Low EMI (slow ramp: 3 switches closed by fixed delay line) + 3 + + + + + RES_HCAG + Select resistance or low EMI for the corresponding switch + [3:2] + read-write + + + RES_HCBV + Select resistance or low EMI for the corresponding switch + [5:4] + read-write + + + RES_HCBG + Select resistance or low EMI for the corresponding switch + [7:6] + read-write + + + RES_F1PM + Select resistance for the corresponding switch + [17:16] + read-write + + + LOW + Low + 0 + + + MED + Medium + 1 + + + HIGH + High + 2 + + + RSVD + N/A + 3 + + + + + RES_F2PT + Select resistance for the corresponding switch + [19:18] + read-write + + + + + SENSE_PERIOD + Sense clock period + 0x200 + 32 + read-write + 0xC000000 + 0xFF70FFF + + + SENSE_DIV + The length-1 of the Sense modulation 'clock' period in clk_csd cycles. For regular CSD one sense clock cycle = one conversion (=phi1+phi2) . +Note this is the base divider, clock dithering may change the actual period length. +Note that SENSE_DIV must be at least 1 and additionally also allow for one clk_hf of non overlap (if OVERLAP_HI1/2 is set) on both phases, i.e. if clk_csd=clk_hf then SENSE_DIV must be >=3. +In addition the FILTER_DELAY needs to be added to the minimum allowed SENSE_DIV value. + [11:0] + read-write + + + LFSR_SIZE + Selects the length of the LFSR which determines the LFSR repeat period. LFSR_BITS LSB of the LFSR are used for the clock dithering variation on the base period (was PRS in CSDv1). Whenever the LFSR is used (non zero value in this field) the LFSR_CLEAR bit should also be set. + [18:16] + read-write + + + OFF + Don't use clock dithering (=spreadspectrum) (LFSR output value is zero) + 0 + + + 6B + 6-bit LFSR (G(x)=X^6 +X^4+X^3+ X+1, period= 63) + 1 + + + 7B + 7-bit LFSR (G(x)=X^7 +X^4+X^3+X^2+1, period= 127) + 2 + + + 9B + 9-bit LFSR (G(x)=X^9 +X^4+X^3+ X+1, period= 511) + 3 + + + 10B + 10-bit LFSR (G(x)=X^10+X^4+X^3+ X+1, period= 1023) + 4 + + + 8B + 8-bit LFSR (G(x)=X^8+X^4+X^3+X^2+1, period= 255) + 5 + + + 12B + 12-bit LFSR (G(x)=X^12+X^7+X^4+X^3+1, period= 4095) + 6 + + + + + LFSR_SCALE + Shift the LFSR output left by LSFR_SCALE bits before adding to SENSE_DIV. This dithering is disabled when SEL_LSFR_MSB is set. +The clock divider to be used = (SENSE_DIV+1) + (SEL_LSFR_MSB ? 0 : (LFSR_OUT<<LFSR_SCALE)). +Note that the clock divider including the dithering term must fit in 12 bits, otherwise the result is undefined. + [23:20] + read-write + + + LFSR_CLEAR + When set, forces the LFSR to it's initial state (all ones). This bit is automatically cleared by hardware after the LFSR is cleared, which is at the next clk_csd positive edge. This bit should be set whenever this register is written and the LFSR is used. +Note that the LFSR will also get reset to all ones during the AutoZero_1/2 states. + [24:24] + read-write + + + SEL_LFSR_MSB + Use the MSB of configured LSFR size as csd_sense signal. Intended to be used only with bit 8 or 12-bit LFSR size for CSDv1 backward compatibility (PRS). When this bit is set then clock divider dithering is disabled and SENSE_WIDTH is disabled. + [25:25] + read-write + + + LFSR_BITS + Selects the number of LSB bits to use from the LSFR to provide the clock dithering variation on the base period. +Caveat make sure that SENSE_DIV > the maximum absolute range (e.g. for 4B SENSE_DIV > 8), otherwise results are undefined. + [27:26] + read-write + + + 2B + use 2 bits: range = [-2,1] + 0 + + + 3B + use 3 bits: range = [-4,3] + 1 + + + 4B + use 4 bits: range = [-8,7] + 2 + + + 5B + use 5 bits: range = [-16,15] (default) + 3 + + + + + + + SENSE_DUTY + Sense clock duty cycle + 0x204 + 32 + read-write + 0x0 + 0xD0FFF + + + SENSE_WIDTH + Defines the length of the first phase of the sense clock in clk_csd cycles. +A value of 0 disables this feature and the duty cycle of csd_sense will be 50 percent, which is equal to SENSE_WIDTH = (SENSE_DIV+1)/2, or when clock dithering is used that becomes [(SENSE_DIV+1) + (LFSR_OUT << LSFR_SCALE)]/2. At all times it must be assured that the phases are at least 2 clk_csd cycles (1 for non overlap, if used), if this rule is violated the result is undefined. +Note that this feature is not available when SEL_LFSR_MSB (PRS) is selected. + [11:0] + read-write + + + SENSE_POL + Polarity of the sense clock +0 = start with low phase (typical for regular negative transfer CSD) +1 = start with high phase + [16:16] + read-write + + + OVERLAP_PHI1 + NonOverlap or not for Phi1 (csd_sense=0). +0 = Non-overlap for Phi1, the Phi1 signal is csd_sense inverted except that the signal goes low 1 clk_sample before csd_sense goes high. Intended usage: new low EMI CSD/CSX with static GPIO. +1 = 'Overlap' (= not non-overlap) for Phi1, the Phi1 signal is csd_sense inverted. Intended usage: legacy CSD with GPIO switching, the GPIO internal circuit ensures that the switches are non-overlapping. + [18:18] + read-write + + + OVERLAP_PHI2 + Same as OVERLAP_PHI1 but for Phi2 (csd_sense=1). + [19:19] + read-write + + + + + SW_HS_P_SEL + HSCMP Pos input switch Waveform selection + 0x280 + 32 + read-write + 0x0 + 0x11111111 + + + SW_HMPM + Set HMPM switch +0: static open +1: static closed + [0:0] + read-write + + + SW_HMPT + Set corresponding switch + [4:4] + read-write + + + SW_HMPS + Set corresponding switch + [8:8] + read-write + + + SW_HMMA + Set corresponding switch + [12:12] + read-write + + + SW_HMMB + Set corresponding switch + [16:16] + read-write + + + SW_HMCA + Set corresponding switch + [20:20] + read-write + + + SW_HMCB + Set corresponding switch + [24:24] + read-write + + + SW_HMRH + Set corresponding switch + [28:28] + read-write + + + + + SW_HS_N_SEL + HSCMP Neg input switch Waveform selection + 0x284 + 32 + read-write + 0x0 + 0x77110000 + + + SW_HCCC + Set corresponding switch + [16:16] + read-write + + + SW_HCCD + Set corresponding switch + [20:20] + read-write + + + SW_HCRH + Select waveform for corresponding switch + [26:24] + read-write + + + SW_HCRL + Select waveform for corresponding switch + [30:28] + read-write + + + + + SW_SHIELD_SEL + Shielding switches Waveform selection + 0x288 + 32 + read-write + 0x0 + 0x117777 + + + SW_HCAV + N/A + [2:0] + read-write + + + SW_HCAG + Select waveform for corresponding switch + [6:4] + read-write + + + SW_HCBV + N/A + [10:8] + read-write + + + SW_HCBG + Select waveform for corresponding switch, using csd_shield as base + [14:12] + read-write + + + SW_HCCV + Set corresponding switch + [16:16] + read-write + + + SW_HCCG + Set corresponding switch +If the ADC is enabled then this switch is directly controlled by the ADC sequencer. + [20:20] + read-write + + + + + SW_AMUXBUF_SEL + Amuxbuffer switches Waveform selection + 0x290 + 32 + read-write + 0x0 + 0x11171110 + + + SW_IRBY + Set corresponding switch + [4:4] + read-write + + + SW_IRLB + Set corresponding switch + [8:8] + read-write + + + SW_ICA + Set corresponding switch + [12:12] + read-write + + + SW_ICB + Select waveform for corresponding switch + [18:16] + read-write + + + SW_IRLI + Set corresponding switch + [20:20] + read-write + + + SW_IRH + Set corresponding switch + [24:24] + read-write + + + SW_IRL + Set corresponding switch + [28:28] + read-write + + + + + SW_BYP_SEL + AMUXBUS bypass switches Waveform selection + 0x294 + 32 + read-write + 0x0 + 0x111000 + + + SW_BYA + Set corresponding switch + [12:12] + read-write + + + SW_BYB + Set corresponding switch + [16:16] + read-write + + + SW_CBCC + Set corresponding switch +If the ADC is enabled then this switch is directly controlled by the ADC sequencer. + [20:20] + read-write + + + + + SW_CMP_P_SEL + CSDCMP Pos Switch Waveform selection + 0x2A0 + 32 + read-write + 0x0 + 0x1111777 + + + SW_SFPM + Select waveform for corresponding switch + [2:0] + read-write + + + SW_SFPT + Select waveform for corresponding switch + [6:4] + read-write + + + SW_SFPS + Select waveform for corresponding switch + [10:8] + read-write + + + SW_SFMA + Set corresponding switch + [12:12] + read-write + + + SW_SFMB + Set corresponding switch + [16:16] + read-write + + + SW_SFCA + Set corresponding switch + [20:20] + read-write + + + SW_SFCB + Set corresponding switch + [24:24] + read-write + + + + + SW_CMP_N_SEL + CSDCMP Neg Switch Waveform selection + 0x2A4 + 32 + read-write + 0x0 + 0x77000000 + + + SW_SCRH + Select waveform for corresponding switch + [26:24] + read-write + + + SW_SCRL + Select waveform for corresponding switch + [30:28] + read-write + + + + + SW_REFGEN_SEL + Reference Generator Switch Waveform selection + 0x2A8 + 32 + read-write + 0x0 + 0x11110011 + + + SW_IAIB + Set corresponding switch + [0:0] + read-write + + + SW_IBCB + Set corresponding switch + [4:4] + read-write + + + SW_SGMB + Set corresponding switch + [16:16] + read-write + + + SW_SGRP + Set corresponding switch + [20:20] + read-write + + + SW_SGRE + Set corresponding switch + [24:24] + read-write + + + SW_SGR + Set corresponding switch + [28:28] + read-write + + + + + SW_FW_MOD_SEL + Full Wave Cmod Switch Waveform selection + 0x2B0 + 32 + read-write + 0x0 + 0x11170701 + + + SW_F1PM + Set corresponding switch + [0:0] + read-write + + + SW_F1MA + Select waveform for corresponding switch + [10:8] + read-write + + + SW_F1CA + Select waveform for corresponding switch + [18:16] + read-write + + + SW_C1CC + Set corresponding switch + [20:20] + read-write + + + SW_C1CD + Set corresponding switch + [24:24] + read-write + + + SW_C1F1 + Set corresponding switch + [28:28] + read-write + + + + + SW_FW_TANK_SEL + Full Wave Csh_tank Switch Waveform selection + 0x2B4 + 32 + read-write + 0x0 + 0x11177710 + + + SW_F2PT + Set corresponding switch + [4:4] + read-write + + + SW_F2MA + Select waveform for corresponding switch + [10:8] + read-write + + + SW_F2CA + Select waveform for corresponding switch + [14:12] + read-write + + + SW_F2CB + Select waveform for corresponding switch + [18:16] + read-write + + + SW_C2CC + Set corresponding switch + [20:20] + read-write + + + SW_C2CD + Set corresponding switch + [24:24] + read-write + + + SW_C2F2 + Set corresponding switch + [28:28] + read-write + + + + + SW_DSI_SEL + DSI output switch control Waveform selection + 0x2C0 + 32 + read-write + 0x0 + 0xFF + + + DSI_CSH_TANK + Select waveform for dsi_csh_tank output signal +0: static open +1: static closed +2: phi1 +3: phi2 +4: phi1 & HSCMP +5: phi2 & HSCMP +6: HSCMP // ignores phi1/2 +7: !sense // = phi1 but ignores OVERLAP_PHI1 + +8: phi1_delay // phi1 delayed with shield delay +9: phi2_delay // phi2 delayed with shield delay + +10: !phi1 +11: !phi2 +12: !(phi1 & HSCMP) +13: !(phi2 & HSCMP) +14: !HSCMP // ignores phi1/2 +15: sense // = phi2 but ignores OVERLAP_PHI2 + [3:0] + read-write + + + DSI_CMOD + Select waveform for dsi_cmod output signal + [7:4] + read-write + + + + + IO_SEL + IO output control Waveform selection + 0x2D0 + 32 + read-write + 0x0 + 0xFFFF0FF + + + CSD_TX_OUT + Select waveform for csd_tx_out output signal + [3:0] + read-write + + + CSD_TX_OUT_EN + Select waveform for csd_tx_out_en output signal + [7:4] + read-write + + + CSD_TX_AMUXB_EN + Select waveform for csd_tx_amuxb_en output signal + [15:12] + read-write + + + CSD_TX_N_OUT + Select waveform for csd_tx_n_out output signal + [19:16] + read-write + + + CSD_TX_N_OUT_EN + Select waveform for csd_tx_n_out_en output signal + [23:20] + read-write + + + CSD_TX_N_AMUXA_EN + Select waveform for csd_tx_n_amuxa_en output signal + [27:24] + read-write + + + + + SEQ_TIME + Sequencer Timing + 0x300 + 32 + read-write + 0x0 + 0xFF + + + AZ_TIME + Define Auto-Zero time in csd_sense cycles -1. + [7:0] + read-write + + + + + SEQ_INIT_CNT + Sequencer Initial conversion and sample counts + 0x310 + 32 + read-write + 0x0 + 0xFFFF + + + CONV_CNT + Number of conversion per Initialization sample, if set to 0 the Sample_init state will be skipped. + [15:0] + read-write + + + + + SEQ_NORM_CNT + Sequencer Normal conversion and sample counts + 0x314 + 32 + read-write + 0x0 + 0xFFFF + + + CONV_CNT + Number of conversion per sample, if set to 0 the Sample_norm state will be skipped. +Sample window size = SEQ_NORM_CNT.CONV_CNT * (SENSE_PERIOD.SENSE_DIV+1). +Note for CSDv1 Sample window size = PERIOD + [15:0] + read-write + + + + + ADC_CTL + ADC Control + 0x320 + 32 + read-write + 0x0 + 0x300FF + + + ADC_TIME + ADC timing -1 in csd_sense clock cycles (actual time is ADC_TIME+1 cycles), either used to discharge Cref1&2, or as the aperture to capture the input voltage on Cref1&2 + [7:0] + read-write + + + ADC_MODE + Enable ADC measurement. When enabled the ADC sequencer will be started when the main sequencer goes to the SAMPLE_NORM state + [17:16] + read-write + + + OFF + No ADC measurement + 0 + + + VREF_CNT + Count time A to bring Cref1 + Cref2 up from Vssa to Vrefhi with IDACB + 1 + + + VREF_BY2_CNT + Count time B to bring Cref1 + Cref2 back up to Vrefhi with IDACB (after bringing them down for time A/2 cycles with IDACB sinking) + 2 + + + VIN_CNT + Determine HSCMP polarity and count time C to source/sink Cref1 + Cref2 from Vin to Vrefhi. + 3 + + + + + + + SEQ_START + Sequencer start + 0x340 + 32 + read-write + 0x0 + 0x31B + + + START + Start the CSD sequencer. The sequencer will clear this bit when it is done. Depending on the mode the sequencer is done when a sample has been accumulated, when the high speed comparator trips or if the sequencer is aborted. When the ADC is enabled the ADC sequencer will start when the CSD sequencer reaches the Sample_norm state (only with the regular CSD scan mode). + [0:0] + read-write + + + SEQ_MODE + 0 = regular CSD scan + optional ADC +1 = coarse initialization, the Sequencer will go to the INIT_COARSE state. + [1:1] + read-write + + + ABORT + When a 1 is written the CSD and ADC sequencers will be aborted (if they are running) and the START bit will be cleared. This bit always read as 0. + [3:3] + read-write + + + DSI_START_EN + When this bit is set a positive edge on dsi_start will start the CSD sequencer and if enabled also the ADC sequencer. + [4:4] + read-write + + + AZ0_SKIP + When set the AutoZero_0 state will be skipped + [8:8] + read-write + + + AZ1_SKIP + When set the AutoZero_1 state will be skipped + [9:9] + read-write + + + + + IDACA + IDACA Configuration + 0x400 + 32 + read-write + 0x0 + 0x3EF0FFF + + + VAL + N/A + [6:0] + read-write + + + POL_DYN + N/A + [7:7] + read-write + + + STATIC + N/A + 0 + + + DYNAMIC + N/A + 1 + + + + + POLARITY + N/A + [9:8] + read-write + + + VSSA_SRC + Normal: sensor switching between Vssio and Cmod. For non-CSD application, IDAC1 will source current. + 0 + + + VDDA_SNK + Inverted: sensor switch between Vddio and Cmod. For non-CSD application, IDAC1 will sink current. + 1 + + + SENSE + N/A + 2 + + + SENSE_INV + N/A + 3 + + + + + BAL_MODE + N/A + [11:10] + read-write + + + FULL + N/A + 0 + + + PHI1 + N/A + 1 + + + PHI2 + N/A + 2 + + + PHI1_2 + N/A + 3 + + + + + LEG1_MODE + N/A + [17:16] + read-write + + + GP_STATIC + N/A + 0 + + + GP + N/A + 1 + + + CSD_STATIC + N/A + 2 + + + CSD + N/A + 3 + + + + + LEG2_MODE + N/A + [19:18] + read-write + + + GP_STATIC + N/A + 0 + + + GP + N/A + 1 + + + CSD_STATIC + N/A + 2 + + + CSD + N/A + 3 + + + + + DSI_CTRL_EN + N/A + [21:21] + read-write + + + RANGE + N/A + [23:22] + read-write + + + IDAC_LO + N/A + 0 + + + IDAC_MED + N/A + 1 + + + IDAC_HI + N/A + 2 + + + + + LEG1_EN + N/A + [24:24] + read-write + + + LEG2_EN + N/A + [25:25] + read-write + + + + + IDACB + IDACB Configuration + 0x500 + 32 + read-write + 0x0 + 0x7EF0FFF + + + VAL + N/A + [6:0] + read-write + + + POL_DYN + N/A + [7:7] + read-write + + + STATIC + N/A + 0 + + + DYNAMIC + N/A + 1 + + + + + POLARITY + N/A + [9:8] + read-write + + + VSSA_SRC + Normal: sensor switching between Vssio and Cmod. For non-CSD application, IDAC1 will source current. + 0 + + + VDDA_SNK + Inverted: sensor switch between Vddio and Cmod. For non-CSD application, IDAC1 will sink current. + 1 + + + SENSE + N/A + 2 + + + SENSE_INV + N/A + 3 + + + + + BAL_MODE + N/A + [11:10] + read-write + + + FULL + N/A + 0 + + + PHI1 + N/A + 1 + + + PHI2 + N/A + 2 + + + PHI1_2 + N/A + 3 + + + + + LEG1_MODE + N/A + [17:16] + read-write + + + GP_STATIC + N/A + 0 + + + GP + N/A + 1 + + + CSD_STATIC + N/A + 2 + + + CSD + N/A + 3 + + + + + LEG2_MODE + N/A + [19:18] + read-write + + + GP_STATIC + N/A + 0 + + + GP + N/A + 1 + + + CSD_STATIC + N/A + 2 + + + CSD + N/A + 3 + + + + + DSI_CTRL_EN + N/A + [21:21] + read-write + + + RANGE + N/A + [23:22] + read-write + + + IDAC_LO + N/A + 0 + + + IDAC_MED + N/A + 1 + + + IDAC_HI + N/A + 2 + + + + + LEG1_EN + N/A + [24:24] + read-write + + + LEG2_EN + N/A + [25:25] + read-write + + + LEG3_EN + N/A + [26:26] + read-write + + + + + + + TCPWM0 + Timer/Counter/PWM + TCPWM + 0x40380000 + + 0 + 131072 + registers + + + + 2 + 32768 + GRP[%s] + Group of counters + 0x00000000 + + 8 + 128 + CNT[%s] + Timer/Counter/PWM Counter Module + 0x00000000 + + CTRL + Counter control register + 0x0 + 32 + read-write + 0xF0 + 0xC73737FF + + + AUTO_RELOAD_CC0 + Specifies switching of the CC0 and buffered CC0 values. This field has a function in TIMER, QUAD (QUAD_RANGE0_CMP, QUAD_RANGE1_CMP range modes), SR, PWM, PWM_DT and PWM_PR modes. +Timer, QUAD, SR modes: +'0': never switch. +'1': switch on a compare match 0 event. +PWM, PWM_DT, PWM_PR modes: +'0: never switch. +'1': switch on a terminal count event with an actively pending switch event. + [0:0] + read-write + + + AUTO_RELOAD_CC1 + Specifies switching of the CC1 and buffered CC1 values. This field has a function in TIMER, QUAD (QUAD_RANGE0_CMP, QUAD_RANGE1_CMP range modes), SR, PWM, PWM_DT and PWM_PR modes. +Timer, QUAD, SR modes: +'0': never switch. +'1': switch on a compare match 1 event. +PWM, PWM_DT, PWM_PR modes: +'0: never switch. +'1': switch on a terminal count event with an actively pending switch event. + [1:1] + read-write + + + AUTO_RELOAD_PERIOD + Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM and PWM_DT modes. +'0': never switch. +'1': switch on a terminal count event with and actively pending switch event. + +In QUAD mode, QUAD_RANGE0_CMP range mode this field is used to select the index / wrap-around capture function. +'0': Captures on index (reload) event. The counter value is copied to the PERIOD register on an index (reload) event. +'1': Captures when COUNTER equals 0 or 0xffff. The counter value is copied to the PERIOD register when COUNTER equals 0 or 0xffff. + [2:2] + read-write + + + AUTO_RELOAD_LINE_SEL + Specifies switching of the LINE_SEL and LINE_BUFF_SEL values. This field has a function in PWM and PWM_PR modes. +'0': never switch. +'1': switch on a terminal count event with and actively pending switch event. + [3:3] + read-write + + + CC0_MATCH_UP_EN + Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode. +'0': compare match 0 event generation disabled when counting up +'1': compare match 0 event generation enabled when counting up + +This field has a function in PWM and PWM_DT modes only. + [4:4] + read-write + + + CC0_MATCH_DOWN_EN + Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode. +'0': compare match 0 event generation disabled when counting down +'1': compare match 0 event generation enabled when counting down + +This field has a function in PWM and PWM_DT modes only. + [5:5] + read-write + + + CC1_MATCH_UP_EN + Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode. +'0': compare match 1 event generation disabled when counting up +'1': compare match 1 event generation enabled when counting up + +This field has a function in PWM and PWM_DT modes only. + [6:6] + read-write + + + CC1_MATCH_DOWN_EN + Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode. +'0': compare match 1 event generation disabled when counting down +'1': compare match 1 event generation enabled when counting down + +This field has a function in PWM and PWM_DT modes only. + [7:7] + read-write + + + PWM_IMM_KILL + Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter'). +'0': synchronous kill activation. Deactivates the 'dt_line_out' and 'dt_line_compl_out' signals with the next module clock ('active count' pre-scaled 'clk_counter'). +'1': immediate kill activation. Immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals. + +This field has a function in PWM, PWM_DT and PWM_PR modes only. + [8:8] + read-write + + + PWM_STOP_ON_KILL + Specifies whether the counter stops on a kill events: +'0': kill event does NOT stop counter. +'1': kill event stops counter. + +This field has a function in PWM, PWM_DT and PWM_PR modes only. + [9:9] + read-write + + + PWM_SYNC_KILL + Specifies asynchronous/synchronous kill behavior: +'1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill). In synchronous kill mode, STOP_EDGE should be RISING_EDGE. +'0': asynchronous kill mode: the kill event only disables the 'dt_line_out' and 'dt_line_compl_out' signals when present. In asynchronous kill mode, STOP_EDGE should be NO_EDGE_DET. + +This field has a function in PWM and PWM_DT modes only. This field is only used when PWM_STOP_ON_KILL is '0'. + [10:10] + read-write + + + PWM_DISABLE_MODE + Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped. + +Note: The output signal of this selection can be further modified by the immediate kill logic and line_out polarity settings (CTRL.QUAD_ENCODING_MODE). + [13:12] + read-write + + + Z + The behavior is the same is in previous mxtcpwm (version 1). + +When the counter is disabled the PWM outputs 'line_out' and 'line_compl_out' are NOT driven by the TCPWM. Instead the port default level configuration applies, e.g. 'Z' (high impedance). +Note: This is realized by driving the TCPWM output 'line_out_en' to 0. + +When the counter is stopped upon a stop event the PWM outputs are deactivated (to the polarity defined by CTL.QUAD_ENCODING_MODE). + 0 + + + RETAIN + When the counter is disabled the PWM outputs 'line_out' and 'line_compl_out' are driven by the TCPWM. +When the counter is disabled or stopped upon a stop event the PWM outputs are retained (keep their previous levels). +While the counter is disabled or stopped the PWM outputs can be changed via LINE_SEL (when parameter GRP_SMC_PRESENT = 1). + 1 + + + L + When the counter is disabled the PWM outputs 'line_out' and 'line_compl_out' are driven by the TCPWM. +When the counter is disabled or stopped upon a stop event the PWM output 'line_out' is driven as a fixed '0' and the PWM output 'line_compl_out' is driven as a fixed '1'. + 2 + + + H + When the counter is disabled the PWM outputs 'line_out' and 'line_compl_out' are driven by the TCPWM. +When the counter is disabled or stopped upon a stop event the PWM output 'line_out' is driven as a fixed '1' and the PWM output 'line_compl_out' is driven as a fixed '0'. + 3 + + + + + UP_DOWN_MODE + Determines counter direction. + +In QUAD mode this field acts as QUAD_RANGE_MODE field selecting between different counter range, reload value and compare / capture behavior. + [17:16] + read-write + + + COUNT_UP + Count up (to PERIOD). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. A terminal count event is generated when the counter changes from a state in which COUNTER equals PERIOD. + 0 + + + COUNT_DOWN + Count down (to '0'). An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'. + 1 + + + COUNT_UPDN1 + Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'. + 2 + + + COUNT_UPDN2 + Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0' AND when the counter changes from a state in which COUNTER equals PERIOD (this counter direction can be used for PWM functionality with asymmetrical updates). + 3 + + + + + ONE_SHOT + When '0', counter runs continuous. When '1', counter is turned off by hardware when a terminal count event is generated. + [18:18] + read-write + + + QUAD_ENCODING_MODE + In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode. +In PWM, PWM_DT and PWM_PR modes, these two bits can be used to invert 'dt_line_out' and 'dt_line_compl_out'. Inversion is the last step in generation of 'dt_line_out' and 'dt_line_compl_out'; i.e. a disabled output line 'dt_line_out' has the value QUAD_ENCODING_MODE[0] and a disabled output line 'dt_line_compl_out' has the value QUAD_ENCODING_MODE[1]. + [21:20] + read-write + + + X1 + X1 encoding (QUAD mode) +This encoding is identical with an up / down counting functionality of the following way: Rising edges of input phiA increment or decrement the counter depending on the state of input phiB (direction input). + 0 + + + X2 + X2 encoding (QUAD mode) + 1 + + + X4 + X4 encoding (QUAD mode) + 2 + + + UP_DOWN + Up / Down rotary counting mode. Input phiA increments the counter, input phiB decrements the counter. The trigger edge detection settings apply. + 3 + + + + + MODE + Counter mode. + [26:24] + read-write + + + TIMER + Timer mode + 0 + + + RSVD1 + N/A + 1 + + + CAPTURE + Capture mode + 2 + + + QUAD + Quadrature mode + +Different encoding modes can be selected by QUAD_ENCODING_MODE including up/down count functionality. +Different counter range, reload value and capture behavior can be selected by QUAD_RANGE_MODE (overloaded field UP_DOWN_MODE). + 3 + + + PWM + Pulse width modulation (PWM) mode + 4 + + + PWM_DT + PWM with deadtime insertion mode + 5 + + + PWM_PR + Pseudo random pulse width modulation + 6 + + + SR + Shift register mode. + 7 + + + + + DBG_FREEZE_EN + Specifies the counter behavior in debug mode. +'0': The counter operation continues in debug mode. +'1': The counter operation freezes in debug mode. + [30:30] + read-write + + + ENABLED + Counter enable. +'0': counter disabled. +'1': counter enabled. +Counter static configuration information (e.g. CTRL.MODE, all TR_IN_SEL, TR_IN_EDGE_SEL, TR_PWM_CTRL and TR_OUT_SEL register fields) should only be modified when the counter is disabled. When a counter is disabled, command and status information associated to the counter is cleared by HW, this includes: +- the associated counter triggers in the CMD register are set to '0'. +- the counter's interrupt cause fields in counter's INTR register. +- the counter's status fields in counter's STATUS register.. +- the counter's trigger outputs ('tr_out0' and tr_out1'). +- the counter's line outputs ('line_out' and 'line_compl_out'). + [31:31] + read-write + + + + + STATUS + Counter status register + 0x4 + 32 + read-only + 0x20 + 0xFFFF8FF1 + + + DOWN + When '0', counter is counting up. When '1', counter is counting down. In QUAD mode, this field indicates the direction of the latest counter change: '0' when last incremented and '1' when last decremented. + [0:0] + read-only + + + TR_CAPTURE0 + Indicates the actual level of the selected capture 0 trigger. + [4:4] + read-only + + + TR_COUNT + Indicates the actual level of the selected count trigger. + [5:5] + read-only + + + TR_RELOAD + Indicates the actual level of the selected reload trigger. + [6:6] + read-only + + + TR_STOP + Indicates the actual level of the selected stop trigger. + [7:7] + read-only + + + TR_START + Indicates the actual level of the selected start trigger. + [8:8] + read-only + + + TR_CAPTURE1 + Indicates the actual level of the selected capture 1 trigger. + [9:9] + read-only + + + LINE_OUT + Indicates the actual level of the PWM line output signal. + [10:10] + read-only + + + LINE_COMPL_OUT + Indicates the actual level of the complementary PWM line output signal. + [11:11] + read-only + + + RUNNING + When '0', the counter is NOT running. When '1', the counter is running. + +This field is used to indicate that the counter is running after a start/reload event and that the counter is stopped after a stop event. +When a running counter operation is paused in debug state (see CTRL.DBG_PAUSE) then the RUNNING bit is still '1'. + [15:15] + read-only + + + DT_CNT_L + Generic 8-bit counter field. In PWM_DT mode, this counter is used for dead time insertion (8bit dead time counter or low byte of 16-bit dead time counter). +In all other modes, this counter is used for pre-scaling the selected counter clock. PWM_DT mode can NOT use prescaled clock functionality. + [23:16] + read-only + + + DT_CNT_H + High byte of 16-bit dead time counter. In PWM_DT mode, this counter is used for dead time insertion. +In all other modes, this field has no effect. + +Note: This field only exists when parameter GRP_AMC_PRESENT for advanced motor control is set to 1. Otherwise the dead time is only 8bit wide and the only the field DT_CNT_L is used as dead time counter. + [31:24] + read-only + + + + + COUNTER + Counter count register + 0x8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + COUNTER + 16-bit / 32-bit counter value. It is advised to not write to this field when the counter is running. + [31:0] + read-write + + + + + CC0 + Counter compare/capture 0 register + 0x10 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + CC + In CAPTURE mode, captures the counter value. In other modes, compared to counter value. + [31:0] + read-write + + + + + CC0_BUFF + Counter buffered compare/capture 0 register + 0x14 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + CC + Additional buffer for counter CC register. + [31:0] + read-write + + + + + CC1 + Counter compare/capture 1 register + 0x18 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + CC + In CAPTURE mode, captures the counter value. In other modes, compared to counter value. + [31:0] + read-write + + + + + CC1_BUFF + Counter buffered compare/capture 1 register + 0x1C + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + CC + Additional buffer for counter CC1 register. + [31:0] + read-write + + + + + PERIOD + Counter period register + 0x20 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + PERIOD + Period value: upper value of the counter. When the counter should count for n cycles, this field should be set to n-1. + [31:0] + read-write + + + + + PERIOD_BUFF + Counter buffered period register + 0x24 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + PERIOD + Additional buffer for counter PERIOD register. + +In PWM_PR mode PEROD_BUFF defines the LFSR polynomial. Each bit represents a tap of the shift register which can be feed back to the MSB via an XOR tree. +Examples for GRP_CNT_WIDTH = 16: +- Maximum length 16bit LFSR + - polynomial x^16 + x^14 + x^13 + x^11 + 1 + - taps 0,2,3,5 -> PERIOD = 0x002d + - period is 2^16-1 = 65535 cycles +- Maximum length 8bit LFSR: + - polynomial x^8 + x^6 + x^5 + x^4 + 1 + - taps 8,10,11,12 (realized in 8 MSBs of 16bit LFSR) + - period is 2^8-1 = 255 cycles + +In SR mode PERIOD_BUFF defines which tap of the shift register generates the PWM output signals. For a delay of n cycles (from capture event to PWM output) the bit CNT_WIDTH-n should be set to '1'. For a shift register function only one tap should be use, i.e. a one-hot value must be written to PERIOD_BUFF. If multiple bits in PERIOD_BUFF are set then the taps are XOR combined. + [31:0] + read-write + + + + + LINE_SEL + Counter line selection register + 0x28 + 32 + read-write + 0x32 + 0x77 + + + OUT_SEL + Selects the source for the output signal 'line_out'. Default setting is the PWM signal 'line'. Other settings are useful for Stepper Motor Control. +This field has a function in PWM and PWM_PR modes only. + +Note: The output signal of this selection can be further modified by the stop / kill logic and line_out polarity setting (CTRL.QUAD_ENCODING_MODE[0]). + [2:0] + read-write + + + L + fixed '0' + 0 + + + H + fixed '1' + 1 + + + PWM + PWM signal 'line' + 2 + + + PWM_INV + inverted PWM signal 'line' + 3 + + + Z + The output 'line_out' is not driven by the TCPWM. Instead the port default level configuration applies, e.g. 'Z' (high impedance). + +Note: This is realized by driving the output 'line_out_en' to 0. + 4 + + + RSVD5 + N/A + 5 + + + RSVD6 + N/A + 6 + + + RSVD7 + N/A + 7 + + + + + COMPL_OUT_SEL + Selects the source for the output signal 'line_compl_out'. Default setting is the inverted PWM signal 'line'. Other settings are useful for Stepper Motor Control. +This field has a function in PWM and PWM_PR modes only. + +Note: The output signal of this selection can be further modified by the stop / kill logic and line_compl_out polarity setting (CTRL.QUAD_ENCODING_MODE[1]). + [6:4] + read-write + + + L + fixed '0' + 0 + + + H + fixed '1' + 1 + + + PWM + PWM signal 'line' + 2 + + + PWM_INV + inverted PWM signal 'line' + 3 + + + Z + The output 'line_compl_out' is not driven by the TCPWM. Instead the port default level configuration applies, e.g. 'Z' (high impedance). + +Note: This is realized by driving the output 'line_compl_out_en' to 0. + 4 + + + RSVD5 + N/A + 5 + + + RSVD6 + N/A + 6 + + + RSVD7 + N/A + 7 + + + + + + + LINE_SEL_BUFF + Counter buffered line selection register + 0x2C + 32 + read-write + 0x32 + 0x77 + + + OUT_SEL + Buffer for LINE_SEL.OUT_SEL. +Can be exchanged with LINE_SEL.LINE_OUT_SEL on a terminal count event with an actively pending switch event. + +This field has a function in PWM and PWM_PR modes only. + [2:0] + read-write + + + COMPL_OUT_SEL + Buffer for LINE_SEL.COMPL.OUT_SEL. +Can be exchanged with LINE_SEL.LINE_COMPL_OUT_SEL on a terminal count event with an actively pending switch event. + +This field has a function in PWM and PWM_PR modes only. + [6:4] + read-write + + + + + DT + Counter PWM dead time register + 0x30 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DT_LINE_OUT_L + In PWM_DT mode, this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain. +In all other modes, the lower 3 bits of this field determine pre-scaling of the selected counter clock. + +Note: This field determines the low byte of the 16-bit dead time before activating 'line_out' when parameter GRP_AMC_PRESENT for advanced motor control is set to 1. Otherwise the dead time is only 8 bit wide and the same dead time specified by this DT_LINE_OUT_L field is used before activating 'line_out' and 'line_compl_out'. + [7:0] + read-write + + + DT_LINE_OUT_H + In PWM_DT mode, this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain. +In all other modes, this field has no effect. + +Note: This field only exists when parameter GRP_AMC_PRESENT for advanced motor control is set to 1. Otherwise the dead time is only 8 bit wide and the same dead time specified by field DT_LINE_OUT_L is used before activating 'line_out' and 'line_compl_out'. + [15:8] + read-write + + + DT_LINE_COMPL_OUT + In PWM_DT mode, this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain. +In all other modes, this field has no effect. + +Note: This field only exists when parameter GRP_AMC_PRESENT for advanced motor control is set to 1. Otherwise the dead time is only 8 bit wide and the same dead time specified by field DT_LINE_OUT_L is used before activating 'line_out' and 'line_compl_out'. + [31:16] + read-write + + + + + TR_CMD + Counter trigger command register + 0x40 + 32 + read-write + 0x0 + 0x3D + + + CAPTURE0 + SW capture 0 trigger. When written with '1', a capture 0 trigger is generated and the HW sets the field to '0' when the SW trigger has taken effect. It should be noted that the HW operates on the counter frequency. If the counter is disabled through CTRL.ENABLED, the field is immediately set to '0'. + [0:0] + read-write + + + RELOAD + SW reload trigger. For HW behavior, see COUNTER_CAPTURE0 field. + [2:2] + read-write + + + STOP + SW stop trigger. For HW behavior, see COUNTER_CAPTURE0 field. + [3:3] + read-write + + + START + SW start trigger. For HW behavior, see COUNTER_CAPTURE0 field. + [4:4] + read-write + + + CAPTURE1 + SW capture 1 trigger. For HW behavior, see COUNTER_CAPTURE0 field. + [5:5] + read-write + + + + + TR_IN_SEL0 + Counter input trigger selection register 0 + 0x44 + 32 + read-write + 0x100 + 0xFFFFFFFF + + + CAPTURE0_SEL + Selects one of the up to 256 input triggers as a capture0 trigger. Input trigger 0 is always '0' and input trigger 1 is always '1'. If existing, the one-to-one trigger inputs 'tr_one_cnt_in' (different to each counter) are selected by setting 2 and above. The settings above are used for the general purpose trigger inputs 'tr_all_cnt_in' connected to all counters selected. +In the PWM, PWM_DT and PWM_PR modes this trigger is used to switch the values if the compare and period registers with their buffer counterparts. + [7:0] + read-write + + + COUNT_SEL + Selects one of the 256 input triggers as a count trigger. +In QUAD mode, this is the first phase (phi A). Default setting selects input trigger 1, which is always '1'. + [15:8] + read-write + + + RELOAD_SEL + Selects one of the 256 input triggers as a reload trigger. +In QUAD mode, this is the index or revolution pulse. In these modes, it will update the counter with 0x8000 (counter midpoint) or 0x0000 depending on the QUAD_RANGE_MODE. + [23:16] + read-write + + + STOP_SEL + Selects one of the 256 input triggers as a stop trigger. +In PWM, PWM_DT and PWM_PR modes, this is the kill trigger. In these modes, the kill trigger is used to either temporarily block the PWM outputs (PWM_STOP_ON_KILL is '0') or stop the functionality (PWM_STOP_ON_KILL is '1'). For the PWM and PWM_DT modes, the blocking of the output signals can be asynchronous (STOP_EDGE should be NO_EDGE_DET) in which case the blocking is as long as the trigger is '1' or synchronous (STOP_EDGE should be RISING_EDGE) in which case it extends till the next terminal count event. + [31:24] + read-write + + + + + TR_IN_SEL1 + Counter input trigger selection register 1 + 0x48 + 32 + read-write + 0x0 + 0xFFFF + + + START_SEL + Selects one of the 256 input triggers as a start trigger. In QUAD mode, this is the second phase (phi B). + [7:0] + read-write + + + CAPTURE1_SEL + Selects one of the 256 input triggers as a capture 1 trigger. + [15:8] + read-write + + + + + TR_IN_EDGE_SEL + Counter input trigger edge selection register + 0x4C + 32 + read-write + 0xFFF + 0xFFF + + + CAPTURE0_EDGE + A capture 0 event will copy the counter value into the CC0 register. + [1:0] + read-write + + + RISING_EDGE + Rising edge. Any rising edge generates an event. + 0 + + + FALLING_EDGE + Falling edge. Any falling edge generates an event. + 1 + + + ANY_EDGE + Rising AND falling edge. Any odd amount of edges generates an event. + 2 + + + NO_EDGE_DET + No edge detection, use trigger as is. + 3 + + + + + COUNT_EDGE + A counter event will increase or decrease the counter by '1'. + [3:2] + read-write + + + RISING_EDGE + Rising edge. Any rising edge generates an event. + 0 + + + FALLING_EDGE + Falling edge. Any falling edge generates an event. + 1 + + + ANY_EDGE + Rising AND falling edge. Any odd amount of edges generates an event. + 2 + + + NO_EDGE_DET + No edge detection, use trigger as is. + 3 + + + + + RELOAD_EDGE + A reload event will initialize the counter. When counting up, the counter is initialized to '0'. When counting down, the counter is initialized with PERIOD. + [5:4] + read-write + + + RISING_EDGE + Rising edge. Any rising edge generates an event. + 0 + + + FALLING_EDGE + Falling edge. Any falling edge generates an event. + 1 + + + ANY_EDGE + Rising AND falling edge. Any odd amount of edges generates an event. + 2 + + + NO_EDGE_DET + No edge detection, use trigger as is. + 3 + + + + + STOP_EDGE + A stop event, will stop the counter; i.e. it will no longer be running. Stopping will NOT disable the counter. + [7:6] + read-write + + + RISING_EDGE + Rising edge. Any rising edge generates an event. + 0 + + + FALLING_EDGE + Falling edge. Any falling edge generates an event. + 1 + + + ANY_EDGE + Rising AND falling edge. Any odd amount of edges generates an event. + 2 + + + NO_EDGE_DET + No edge detection, use trigger as is. + 3 + + + + + START_EDGE + A start event will start the counter; i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does. + [9:8] + read-write + + + RISING_EDGE + Rising edge. Any rising edge generates an event. + 0 + + + FALLING_EDGE + Falling edge. Any falling edge generates an event. + 1 + + + ANY_EDGE + Rising AND falling edge. Any odd amount of edges generates an event. + 2 + + + NO_EDGE_DET + No edge detection, use trigger as is. + 3 + + + + + CAPTURE1_EDGE + A capture 1 event will copy the counter value into the CC1 register. + [11:10] + read-write + + + RISING_EDGE + Rising edge. Any rising edge generates an event. + 0 + + + FALLING_EDGE + Falling edge. Any falling edge generates an event. + 1 + + + ANY_EDGE + Rising AND falling edge. Any odd amount of edges generates an event. + 2 + + + NO_EDGE_DET + No edge detection, use trigger as is. + 3 + + + + + + + TR_PWM_CTRL + Counter trigger PWM control register + 0x50 + 32 + read-write + 0xFF + 0xFF + + + CC0_MATCH_MODE + Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals. Note that INVERT is especially useful for center aligned pulse width modulation. +To generate a duty cycle of 0 percent, the counter CC0 register should be set to '0'. For a 100 percent duty cycle, the counter CC0 register should be set to larger than the counter PERIOD register. + [1:0] + read-write + + + SET + Set to '1' + 0 + + + CLEAR + Set to '0' + 1 + + + INVERT + Invert + 2 + + + NO_CHANGE + No Change + 3 + + + + + OVERFLOW_MODE + Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals. + [3:2] + read-write + + + SET + Set to '1' + 0 + + + CLEAR + Set to '0' + 1 + + + INVERT + Invert + 2 + + + NO_CHANGE + No Change + 3 + + + + + UNDERFLOW_MODE + Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals. + [5:4] + read-write + + + SET + Set to '1' + 0 + + + CLEAR + Set to '0' + 1 + + + INVERT + Invert + 2 + + + NO_CHANGE + No Change + 3 + + + + + CC1_MATCH_MODE + Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals. + [7:6] + read-write + + + SET + Set to '1' + 0 + + + CLEAR + Set to '0' + 1 + + + INVERT + Invert + 2 + + + NO_CHANGE + No Change + 3 + + + + + + + TR_OUT_SEL + Counter output trigger selection register + 0x54 + 32 + read-write + 0x32 + 0x77 + + + OUT0 + Selects one of the internal events to generate the output trigger 0. Default setting selects the terminal count event. + [2:0] + read-write + + + OVERFLOW + Overflow event + 0 + + + UNDERFLOW + Underflow event + 1 + + + TC + Terminal count event (default selection) + 2 + + + CC0_MATCH + Compare match 0 event + 3 + + + CC1_MATCH + Compare match 1 event + 4 + + + LINE_OUT + PWM output signal 'line_out' + 5 + + + RSVD6 + N/A + 6 + + + Disabled + Output trigger disabled. + 7 + + + + + OUT1 + Selects one of the internal events to generate the output trigger 1. Default setting selects the compare match 0 event. + [6:4] + read-write + + + OVERFLOW + Overflow event + 0 + + + UNDERFLOW + Underflow event + 1 + + + TC + Terminal count event + 2 + + + CC0_MATCH + Compare match 0 event (default selection) + 3 + + + CC1_MATCH + Compare match 1 event + 4 + + + LINE_OUT + PWM output signal 'line_out' + 5 + + + RSVD6 + N/A + 6 + + + Disabled + Output trigger disabled. + 7 + + + + + + + INTR + Interrupt request register + 0x70 + 32 + read-write + 0x0 + 0x7 + + + TC + Terminal count event. Set to '1', when event is detected. Write with '1' to clear bit. + [0:0] + read-write + + + CC0_MATCH + Counter matches CC0 register event. Set to '1', when event is detected. Write with '1' to clear bit. + [1:1] + read-write + + + CC1_MATCH + Counter matches CC1 register event. Set to '1', when event is detected. Write with '1' to clear bit. + [2:2] + read-write + + + + + INTR_SET + Interrupt set request register + 0x74 + 32 + read-write + 0x0 + 0x7 + + + TC + Write with '1' to set corresponding bit in interrupt request register. + [0:0] + read-write + + + CC0_MATCH + Write with '1' to set corresponding bit in interrupt request register. + [1:1] + read-write + + + CC1_MATCH + Write with '1' to set corresponding bit in interrupt request register. + [2:2] + read-write + + + + + INTR_MASK + Interrupt mask register + 0x78 + 32 + read-write + 0x0 + 0x7 + + + TC + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + CC0_MATCH + Mask bit for corresponding bit in interrupt request register. + [1:1] + read-write + + + CC1_MATCH + Mask bit for corresponding bit in interrupt request register. + [2:2] + read-write + + + + + INTR_MASKED + Interrupt masked request register + 0x7C + 32 + read-only + 0x0 + 0x7 + + + TC + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + CC0_MATCH + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + CC1_MATCH + Logical and of corresponding request and mask bits. + [2:2] + read-only + + + + + + + + + LCD0 + LCD Controller Block + LCD + 0x403B0000 + + 0 + 65536 + registers + + + + ID + ID & Revision + 0x0 + 32 + read-only + 0x2F0F0 + 0xFFFFFFFF + + + ID + the ID of LCD controller peripheral is 0xF0F0 + [15:0] + read-only + + + REVISION + the version number is 0x0002 + [31:16] + read-only + + + + + DIVIDER + LCD Divider Register + 0x4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SUBFR_DIV + Input clock frequency divide value, to generate the 1/4 sub-frame period. The sub-frame period is 4*(SUBFR_DIV+1) cycles long. + [15:0] + read-write + + + DEAD_DIV + Length of the dead time period in cycles. When set to zero, no dead time period exists. + [31:16] + read-write + + + + + CONTROL + LCD Configuration Register + 0x8 + 32 + read-write + 0x0 + 0x80000FFF + + + LS_EN + Low speed (LS) generator enable +1: enable +0: disable + [0:0] + read-write + + + HS_EN + High speed (HS) generator enable +1: enable +0: disable + [1:1] + read-write + + + LCD_MODE + HS/LS Mode selection + [2:2] + read-write + + + LS + Select Low Speed Generator (Works in Active, Sleep and DeepSleep power modes). Low speed clock (clk_lf) or middle speed clock (clk_mf) can be selected for Low Speed Generator. + 0 + + + HS + Select High Speed (system clock) Generator (Works in Active and Sleep power modes only). + 1 + + + + + TYPE + LCD driving waveform type configuration. + [3:3] + read-write + + + TYPE_A + Type A - Each frame addresses each COM pin only once with a balanced (DC=0) waveform. + 0 + + + TYPE_B + Type B - Each frame addresses each COM pin twice in sequence with a positive and negative waveform that together are balanced (DC=0). + 1 + + + + + OP_MODE + Driving mode configuration + [4:4] + read-write + + + PWM + PWM Mode + 0 + + + CORRELATION + Digital Correlation Mode + 1 + + + + + BIAS + PWM bias selection + [6:5] + read-write + + + HALF + 1/2 Bias + 0 + + + THIRD + 1/3 Bias + 1 + + + FOURTH + 1/4 Bias + 2 + + + FIFTH + 1/5 Bias + 3 + + + + + CLOCK_LS_SEL + Low speed (LS) generator clock source selection +1: select clk_mf +0: select clk_lf + [7:7] + read-write + + + COM_NUM + The number of COM connections minus 2. So: +0: 2 COM's +1: 3 COM's +... +13: 15 COM's +14: 16 COM's +15: undefined + [11:8] + read-write + + + LS_EN_STAT + LS enable status bit. This bit is a copy of LS_EN that is synchronized to the low speed clock domain and back to the system clock domain. Firmware can use this bit to observe whether LS_EN has taken effect in the low speed clock domain. Firmware should never change the configuration for the LS generator without ensuring this bit is 0. +The following procedure should be followed to disable the LS generator: +1. If LS_EN=0 we are done. Exit the procedure. +2. Check that LS_EN_STAT=1. If not, wait until it is. This will catch the case of a recent enable (LS_EN=1) that has not taken effect yet. +3. Set LS_EN=0. +4. Wait until LS_EN_STAT=0. + [31:31] + read-only + + + + + 8 + 4 + DATA0[%s] + LCD Pin Data Registers + 0x100 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DATA + Bits [4i+3:4i] represent the pin data for pin [i] for COMS 1-4 (COM1 is lsb). + [31:0] + read-write + + + + + 8 + 4 + DATA1[%s] + LCD Pin Data Registers + 0x200 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DATA + Bits [4i+3:4i] represent the pin data for pin [i] for COMS 5-8 (COM5 is lsb). + [31:0] + read-write + + + + + 8 + 4 + DATA2[%s] + LCD Pin Data Registers + 0x300 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DATA + Bits [4i+3:4i] represent the pin data for pin [i] for COMS 9-12 (COM9 is lsb). + [31:0] + read-write + + + + + 8 + 4 + DATA3[%s] + LCD Pin Data Registers + 0x400 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DATA + Bits [4i+3:4i] represent the pin data for pin [i] for COMS 13-16 (COM13 is lsb). + [31:0] + read-write + + + + + + + USBFS0 + USB Host and Device Controller + USBFS + 0x403F0000 + + 0 + 65536 + registers + + + + USBDEV + USB Device + 0x00000000 + + 8 + 4 + EP0_DR[%s] + Control End point EP0 Data Register + 0x0 + 32 + read-write + 0x0 + 0xFF + + + DATA_BYTE + This register is shared for both transmit and receive. The count in the EP0_CNT register determines the number of bytes received or to be transferred. + [7:0] + read-write + + + + + CR0 + USB control 0 Register + 0x20 + 32 + read-write + 0x0 + 0xFF + + + DEVICE_ADDRESS + These bits specify the USB device address to which the SIE will respond. This address must be set by firmware and is specified by the USB Host with a SET ADDRESS command during USB enumeration. This value must be programmed by firmware when assigned during enumeration. It is not set automatically by the hardware. +If USB bus reset is detected, these bits are initialized. + [6:0] + read-write + + + USB_ENABLE + This bit enables the device to respond to USB traffic. +If USB bus reset is detected, this bit is cleared. +Note: +When USB PHY is GPIO mode(USBIO_CR1.IOMODE=0), USB bus reset is detected. Therefore, when USB PHY is GPIO mode, this bit is cleared even if this bit is set to 1. If this bit is set to 1, write this bit upon USB bus reset interrupt, and do not write to this bit during initialization steps. + [7:7] + read-write + + + + + CR1 + USB control 1 Register + 0x24 + 32 + read-write + 0x0 + 0xF + + + REG_ENABLE + This bit controls the operation of the internal USB regulator. For applications with supply voltages in the 5V range this bit is set high to enable the internal regulator. For device supply voltage in the 3.3V range this bit is cleared to connect the transceiver directly to the supply. + [0:0] + read-write + + + ENABLE_LOCK + This bit is set to turn on the automatic frequency locking of the internal oscillator to USB traffic. Unless an external clock is being provided this bit should remain set for proper USB operation. + [1:1] + read-write + + + BUS_ACTIVITY + The Bus Activity bit is a stickybit that detects any non-idle USB event that has occurred on the USB bus. Once set to High by the SIE to indicate the bus activity this bit retains its logical High +value until firmware clears it. + [2:2] + read-write + + + RSVD_3 + N/A + [3:3] + read-write + + + + + SIE_EP_INT_EN + USB SIE Data Endpoints Interrupt Enable Register + 0x28 + 32 + read-write + 0x0 + 0xFF + + + EP1_INTR_EN + Enables interrupt for EP1 + [0:0] + read-write + + + EP2_INTR_EN + Enables interrupt for EP2 + [1:1] + read-write + + + EP3_INTR_EN + Enables interrupt for EP3 + [2:2] + read-write + + + EP4_INTR_EN + Enables interrupt for EP4 + [3:3] + read-write + + + EP5_INTR_EN + Enables interrupt for EP5 + [4:4] + read-write + + + EP6_INTR_EN + Enables interrupt for EP6 + [5:5] + read-write + + + EP7_INTR_EN + Enables interrupt for EP7 + [6:6] + read-write + + + EP8_INTR_EN + Enables interrupt for EP8 + [7:7] + read-write + + + + + SIE_EP_INT_SR + USB SIE Data Endpoint Interrupt Status + 0x2C + 32 + read-write + 0x0 + 0xFF + + + EP1_INTR + Interrupt status for EP1 + [0:0] + read-write + + + EP2_INTR + Interrupt status for EP2 + [1:1] + read-write + + + EP3_INTR + Interrupt status for EP3 + [2:2] + read-write + + + EP4_INTR + Interrupt status for EP4 + [3:3] + read-write + + + EP5_INTR + Interrupt status for EP5 + [4:4] + read-write + + + EP6_INTR + Interrupt status for EP6 + [5:5] + read-write + + + EP7_INTR + Interrupt status for EP7 + [6:6] + read-write + + + EP8_INTR + Interrupt status for EP8 + [7:7] + read-write + + + + + SIE_EP1_CNT0 + Non-control endpoint count register + 0x30 + 32 + read-write + 0x0 + 0xC7 + + + DATA_COUNT_MSB + These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information. + [2:0] + read-write + + + DATA_VALID + This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. + [6:6] + read-write + + + DATA_ERROR + No ACK'd transactions since bit was last cleared. + 0 + + + DATA_VALID + Indicates a transaction ended with an ACK. + 1 + + + + + DATA_TOGGLE + This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. + [7:7] + read-write + + + + + SIE_EP1_CNT1 + Non-control endpoint count register + 0x34 + 32 + read-write + 0x0 + 0xFF + + + DATA_COUNT + These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction. + [7:0] + read-write + + + + + SIE_EP1_CR0 + Non-control endpoint's control Register + 0x38 + 32 + read-write + 0x0 + 0xFF + + + MODE + The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. + [3:0] + read-write + + + DISABLE + Ignore all USB traffic to this endpoint + 0 + + + NAK_INOUT + SETUP: Accept +IN: NAK +OUT: NAK + 1 + + + STATUS_OUT_ONLY + SETUP: Accept +IN: STALL +OUT: ACK 0B tokens, NAK others + 2 + + + STALL_INOUT + SETUP: Accept +IN: STALL +OUT: STALL + 3 + + + ISO_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept Isochronous OUT token + 5 + + + STATUS_IN_ONLY + SETUP: Accept +IN: Respond with 0B data +OUT: Stall + 6 + + + ISO_IN + SETUP: Ignore +IN: Accept Isochronous IN token +OUT: Ignore + 7 + + + NAK_OUT + SETUP: Ignore +IN: Ignore +OUT: NAK + 8 + + + ACK_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept data and ACK if STALL=0, STALL otherwise. +Change to MODE=8 after one succesfull OUT token. + 9 + + + ACK_OUT_STATUS_IN + SETUP: Accept +IN: Respond with 0B data +OUT: Accept data + 11 + + + NAK_IN + SETUP: Ignore +IN: NAK +OUT: Ignore + 12 + + + ACK_IN + SETUP: Ignore +IN: Respond to IN with data if STALL=0, STALL otherwise +OUT: Ignore + 13 + + + ACK_IN_STATUS_OUT + SETUP: Accept +IN: Respond to IN with data +OUT: ACK 0B tokens, NAK others + 15 + + + + + ACKED_TXN + The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. + [4:4] + read-write + + + ACKED_NO + No ACK'd transactions since bit was last cleared. + 0 + + + ACKED_YES + Indicates a transaction ended with an ACK. + 1 + + + + + NAK_INT_EN + When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK. + [5:5] + read-write + + + ERR_IN_TXN + The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID +error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register. + [6:6] + read-write + + + STALL + When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes. + [7:7] + read-write + + + + + USBIO_CR0 + USBIO Control 0 Register + 0x40 + 32 + read-write + 0x0 + 0xE0 + + + RD + Received Data. This read only bit gives the state of the USB differential receiver when IOMODE bit is '0' and USB doesn't transmit. This bit is valid if USB Device. +If D+=D- (SE0), this value is undefined. + [0:0] + read-only + + + DIFF_LOW + D+ < D- (K state) + 0 + + + DIFF_HIGH + D+ > D- (J state) + 1 + + + + + TD + Transmit Data. Transmit a USB J or K state on the USB bus. No effect if TEN=0 or TSE0=1. + [5:5] + read-write + + + DIFF_K + Force USB K state (D+ is low D- is high). + 0 + + + DIFF_J + Force USB J state (D+ is high D- is low). + 1 + + + + + TSE0 + Transmit Single-Ended Zero. SE0: both D+ and D- low. No effect if TEN=0. + [6:6] + read-write + + + TEN + USB Transmit Enable. This is used to manually transmit on the D+ and D- pins. Normally this bit should be cleared to allow the internal SIE to drive the pins. The most common reason for manually +transmitting is to force a resume state on the bus. + [7:7] + read-write + + + + + USBIO_CR2 + USBIO control 2 Register + 0x44 + 32 + read-write + 0x0 + 0xFF + + + RSVD_5_0 + N/A + [5:0] + read-only + + + TEST_PKT + This bit enables the device to transmit a packet in response to an internally generated IN packet. When set, one packet will be generated. + [6:6] + read-write + + + RSVD_7 + N/A + [7:7] + read-write + + + + + USBIO_CR1 + USBIO control 1 Register + 0x48 + 32 + read-write + 0x20 + 0x20 + + + DMO + This read only bit gives the state of the D- pin when IOMODE bit is '0' and USB doesn't transmit. +This bit is '0' when USB transmits SE0, and this bit is '1' when USB transmits other than SE0. +This bit is valid if USB Device. + [0:0] + read-only + + + DPO + This read only bit gives the state of the D+ pin when IOMODE bit is '0' and USB doesn't transmit. +This bit displays the output value of D+ pin when USB transmits SE0 or data. +This bit is valid if USB Device. + [1:1] + read-only + + + RSVD_2 + N/A + [2:2] + read-write + + + IOMODE + This bit allows the D+ and D- pins to be configured for either USB mode or bit-banged modes. If this bit is set the DMI and DPI bits are used to drive the D- and D+ pins. + [5:5] + read-write + + + + + DYN_RECONFIG + USB Dynamic reconfiguration register + 0x50 + 32 + read-write + 0x0 + 0x1F + + + DYN_CONFIG_EN + This bit is used to enable the dynamic re-configuration for the selected EP. If set to 1, indicates the reconfiguration required for selected EP. +Use 0 for EP1, 1 for EP2, etc. + [0:0] + read-write + + + DYN_RECONFIG_EPNO + These bits indicates the EP number for which reconfiguration is required when dyn_config_en bit is set to 1. + [3:1] + read-write + + + DYN_RECONFIG_RDY_STS + This bit indicates the ready status for the dynamic reconfiguration, when set to 1, indicates the block is ready for reconfiguration. + [4:4] + read-only + + + + + SOF0 + Start Of Frame Register + 0x60 + 32 + read-only + 0x0 + 0xFF + + + FRAME_NUMBER + It has the lower 8 bits [7:0] of the SOF frame number. + [7:0] + read-only + + + + + SOF1 + Start Of Frame Register + 0x64 + 32 + read-only + 0x0 + 0x7 + + + FRAME_NUMBER_MSB + It has the upper 3 bits [10:8] of the SOF frame number. + [2:0] + read-only + + + + + SIE_EP2_CNT0 + Non-control endpoint count register + 0x70 + 32 + read-write + 0x0 + 0xC7 + + + DATA_COUNT_MSB + These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information. + [2:0] + read-write + + + DATA_VALID + This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. + [6:6] + read-write + + + DATA_ERROR + No ACK'd transactions since bit was last cleared. + 0 + + + DATA_VALID + Indicates a transaction ended with an ACK. + 1 + + + + + DATA_TOGGLE + This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. + [7:7] + read-write + + + + + SIE_EP2_CNT1 + Non-control endpoint count register + 0x74 + 32 + read-write + 0x0 + 0xFF + + + DATA_COUNT + These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction. + [7:0] + read-write + + + + + SIE_EP2_CR0 + Non-control endpoint's control Register + 0x78 + 32 + read-write + 0x0 + 0xFF + + + MODE + The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. + [3:0] + read-write + + + DISABLE + Ignore all USB traffic to this endpoint + 0 + + + NAK_INOUT + SETUP: Accept +IN: NAK +OUT: NAK + 1 + + + STATUS_OUT_ONLY + SETUP: Accept +IN: STALL +OUT: ACK 0B tokens, NAK others + 2 + + + STALL_INOUT + SETUP: Accept +IN: STALL +OUT: STALL + 3 + + + ISO_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept Isochronous OUT token + 5 + + + STATUS_IN_ONLY + SETUP: Accept +IN: Respond with 0B data +OUT: Stall + 6 + + + ISO_IN + SETUP: Ignore +IN: Accept Isochronous IN token +OUT: Ignore + 7 + + + NAK_OUT + SETUP: Ignore +IN: Ignore +OUT: NAK + 8 + + + ACK_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept data and ACK if STALL=0, STALL otherwise. +Change to MODE=8 after one succesfull OUT token. + 9 + + + ACK_OUT_STATUS_IN + SETUP: Accept +IN: Respond with 0B data +OUT: Accept data + 11 + + + NAK_IN + SETUP: Ignore +IN: NAK +OUT: Ignore + 12 + + + ACK_IN + SETUP: Ignore +IN: Respond to IN with data if STALL=0, STALL otherwise +OUT: Ignore + 13 + + + ACK_IN_STATUS_OUT + SETUP: Accept +IN: Respond to IN with data +OUT: ACK 0B tokens, NAK others + 15 + + + + + ACKED_TXN + The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. + [4:4] + read-write + + + ACKED_NO + No ACK'd transactions since bit was last cleared. + 0 + + + ACKED_YES + Indicates a transaction ended with an ACK. + 1 + + + + + NAK_INT_EN + When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK. + [5:5] + read-write + + + ERR_IN_TXN + The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID +error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register. + [6:6] + read-write + + + STALL + When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes. + [7:7] + read-write + + + + + OSCLK_DR0 + Oscillator lock data register 0 + 0x80 + 32 + read-only + 0x0 + 0x0 + + + ADDER + These bits return the lower 8 bits of the oscillator locking circuits adder output. + [7:0] + read-only + + + + + OSCLK_DR1 + Oscillator lock data register 1 + 0x84 + 32 + read-only + 0x0 + 0x0 + + + ADDER_MSB + These bits return the upper 7 bits of the oscillator locking circuits adder output. + [6:0] + read-only + + + + + EP0_CR + Endpoint0 control Register + 0xA0 + 32 + read-write + 0x0 + 0xFF + + + MODE + The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. + [3:0] + read-write + + + DISABLE + Ignore all USB traffic to this endpoint + 0 + + + NAK_INOUT + SETUP: Accept +IN: NAK +OUT: NAK + 1 + + + STATUS_OUT_ONLY + SETUP: Accept +IN: STALL +OUT: ACK 0B tokens, NAK others + 2 + + + STALL_INOUT + SETUP: Accept +IN: STALL +OUT: STALL + 3 + + + ISO_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept Isochronous OUT token + 5 + + + STATUS_IN_ONLY + SETUP: Accept +IN: Respond with 0B data +OUT: Stall + 6 + + + ISO_IN + SETUP: Ignore +IN: Accept Isochronous IN token +OUT: Ignore + 7 + + + NAK_OUT + SETUP: Ignore +IN: Ignore +OUT: NAK + 8 + + + ACK_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept data and ACK if STALL=0, STALL otherwise. +Change to MODE=8 after one succesfull OUT token. + 9 + + + ACK_OUT_STATUS_IN + SETUP: Accept +IN: Respond with 0B data +OUT: Accept data + 11 + + + NAK_IN + SETUP: Ignore +IN: NAK +OUT: Ignore + 12 + + + ACK_IN + SETUP: Ignore +IN: Respond to IN with data if STALL=0, STALL otherwise +OUT: Ignore + 13 + + + ACK_IN_STATUS_OUT + SETUP: Accept +IN: Respond to IN with data +OUT: ACK 0B tokens, NAK others + 15 + + + + + ACKED_TXN + The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. + [4:4] + read-write + + + ACKED_NO + No ACK'd transactions since bit was last cleared. + 0 + + + ACKED_YES + Indicates a transaction ended with an ACK. + 1 + + + + + OUT_RCVD + When set this bit indicates a valid OUT packet has been received and ACKed. This bit is updated to '1' after the last received packet in an OUT transaction. When clear this bit indicates no OUT received. It is cleared by any writes to the register. + [5:5] + read-write + + + IN_RCVD + When set this bit indicates a valid IN packet has been received. This bit is updated to '1' after the host acknowledges an IN data packet. When clear this bit indicates either no IN has been received or that the host did not acknowledge the IN data by sending ACK handshake. It is cleared by any writes to the register. + [6:6] + read-write + + + SETUP_RCVD + When set this bit indicates a valid SETUP packet was received and ACKed. This bit is forced HIGH from the start of the data packet phase of the SETUP transaction until the start of the ACK packet returned by the SIE. The CPU is prevented from clearing this bit during this interval. After this interval the bit will remain set until cleared by firmware. While this bit is set to '1' the CPU cannot write to the EP0_DRx registers. This prevents firmware from overwriting an incoming SETUP transaction before firmware has a chance to read the SETUP data. This bit is cleared by any non-locked writes to the register. + [7:7] + read-write + + + + + EP0_CNT + Endpoint0 count Register + 0xA4 + 32 + read-write + 0x0 + 0xCF + + + BYTE_COUNT + These bits indicate the number of data bytes in a transaction. For IN transactions firmware loads the count with the number of bytes to be transmitted to the host from the endpoint FIFO. Valid values are 0 to 8. For OUT or SETUP transactions the count is updated by hardware to the number of data bytes received plus two for the CRC bytes. Valid values are 2 to 10. + [3:0] + read-write + + + DATA_VALID + This bit is used for OUT/SETUP transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. + [6:6] + read-write + + + DATA_ERROR + No ACK'd transactions since bit was last cleared. + 0 + + + DATA_VALID + Indicates a transaction ended with an ACK. + 1 + + + + + DATA_TOGGLE + This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. + [7:7] + read-write + + + + + SIE_EP3_CNT0 + Non-control endpoint count register + 0xB0 + 32 + read-write + 0x0 + 0xC7 + + + DATA_COUNT_MSB + These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information. + [2:0] + read-write + + + DATA_VALID + This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. + [6:6] + read-write + + + DATA_ERROR + No ACK'd transactions since bit was last cleared. + 0 + + + DATA_VALID + Indicates a transaction ended with an ACK. + 1 + + + + + DATA_TOGGLE + This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. + [7:7] + read-write + + + + + SIE_EP3_CNT1 + Non-control endpoint count register + 0xB4 + 32 + read-write + 0x0 + 0xFF + + + DATA_COUNT + These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction. + [7:0] + read-write + + + + + SIE_EP3_CR0 + Non-control endpoint's control Register + 0xB8 + 32 + read-write + 0x0 + 0xFF + + + MODE + The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. + [3:0] + read-write + + + DISABLE + Ignore all USB traffic to this endpoint + 0 + + + NAK_INOUT + SETUP: Accept +IN: NAK +OUT: NAK + 1 + + + STATUS_OUT_ONLY + SETUP: Accept +IN: STALL +OUT: ACK 0B tokens, NAK others + 2 + + + STALL_INOUT + SETUP: Accept +IN: STALL +OUT: STALL + 3 + + + ISO_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept Isochronous OUT token + 5 + + + STATUS_IN_ONLY + SETUP: Accept +IN: Respond with 0B data +OUT: Stall + 6 + + + ISO_IN + SETUP: Ignore +IN: Accept Isochronous IN token +OUT: Ignore + 7 + + + NAK_OUT + SETUP: Ignore +IN: Ignore +OUT: NAK + 8 + + + ACK_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept data and ACK if STALL=0, STALL otherwise. +Change to MODE=8 after one succesfull OUT token. + 9 + + + ACK_OUT_STATUS_IN + SETUP: Accept +IN: Respond with 0B data +OUT: Accept data + 11 + + + NAK_IN + SETUP: Ignore +IN: NAK +OUT: Ignore + 12 + + + ACK_IN + SETUP: Ignore +IN: Respond to IN with data if STALL=0, STALL otherwise +OUT: Ignore + 13 + + + ACK_IN_STATUS_OUT + SETUP: Accept +IN: Respond to IN with data +OUT: ACK 0B tokens, NAK others + 15 + + + + + ACKED_TXN + The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. + [4:4] + read-write + + + ACKED_NO + No ACK'd transactions since bit was last cleared. + 0 + + + ACKED_YES + Indicates a transaction ended with an ACK. + 1 + + + + + NAK_INT_EN + When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK. + [5:5] + read-write + + + ERR_IN_TXN + The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID +error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register. + [6:6] + read-write + + + STALL + When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes. + [7:7] + read-write + + + + + SIE_EP4_CNT0 + Non-control endpoint count register + 0xF0 + 32 + read-write + 0x0 + 0xC7 + + + DATA_COUNT_MSB + These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information. + [2:0] + read-write + + + DATA_VALID + This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. + [6:6] + read-write + + + DATA_ERROR + No ACK'd transactions since bit was last cleared. + 0 + + + DATA_VALID + Indicates a transaction ended with an ACK. + 1 + + + + + DATA_TOGGLE + This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. + [7:7] + read-write + + + + + SIE_EP4_CNT1 + Non-control endpoint count register + 0xF4 + 32 + read-write + 0x0 + 0xFF + + + DATA_COUNT + These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction. + [7:0] + read-write + + + + + SIE_EP4_CR0 + Non-control endpoint's control Register + 0xF8 + 32 + read-write + 0x0 + 0xFF + + + MODE + The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. + [3:0] + read-write + + + DISABLE + Ignore all USB traffic to this endpoint + 0 + + + NAK_INOUT + SETUP: Accept +IN: NAK +OUT: NAK + 1 + + + STATUS_OUT_ONLY + SETUP: Accept +IN: STALL +OUT: ACK 0B tokens, NAK others + 2 + + + STALL_INOUT + SETUP: Accept +IN: STALL +OUT: STALL + 3 + + + ISO_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept Isochronous OUT token + 5 + + + STATUS_IN_ONLY + SETUP: Accept +IN: Respond with 0B data +OUT: Stall + 6 + + + ISO_IN + SETUP: Ignore +IN: Accept Isochronous IN token +OUT: Ignore + 7 + + + NAK_OUT + SETUP: Ignore +IN: Ignore +OUT: NAK + 8 + + + ACK_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept data and ACK if STALL=0, STALL otherwise. +Change to MODE=8 after one succesfull OUT token. + 9 + + + ACK_OUT_STATUS_IN + SETUP: Accept +IN: Respond with 0B data +OUT: Accept data + 11 + + + NAK_IN + SETUP: Ignore +IN: NAK +OUT: Ignore + 12 + + + ACK_IN + SETUP: Ignore +IN: Respond to IN with data if STALL=0, STALL otherwise +OUT: Ignore + 13 + + + ACK_IN_STATUS_OUT + SETUP: Accept +IN: Respond to IN with data +OUT: ACK 0B tokens, NAK others + 15 + + + + + ACKED_TXN + The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. + [4:4] + read-write + + + ACKED_NO + No ACK'd transactions since bit was last cleared. + 0 + + + ACKED_YES + Indicates a transaction ended with an ACK. + 1 + + + + + NAK_INT_EN + When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK. + [5:5] + read-write + + + ERR_IN_TXN + The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID +error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register. + [6:6] + read-write + + + STALL + When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes. + [7:7] + read-write + + + + + SIE_EP5_CNT0 + Non-control endpoint count register + 0x130 + 32 + read-write + 0x0 + 0xC7 + + + DATA_COUNT_MSB + These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information. + [2:0] + read-write + + + DATA_VALID + This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. + [6:6] + read-write + + + DATA_ERROR + No ACK'd transactions since bit was last cleared. + 0 + + + DATA_VALID + Indicates a transaction ended with an ACK. + 1 + + + + + DATA_TOGGLE + This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. + [7:7] + read-write + + + + + SIE_EP5_CNT1 + Non-control endpoint count register + 0x134 + 32 + read-write + 0x0 + 0xFF + + + DATA_COUNT + These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction. + [7:0] + read-write + + + + + SIE_EP5_CR0 + Non-control endpoint's control Register + 0x138 + 32 + read-write + 0x0 + 0xFF + + + MODE + The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. + [3:0] + read-write + + + DISABLE + Ignore all USB traffic to this endpoint + 0 + + + NAK_INOUT + SETUP: Accept +IN: NAK +OUT: NAK + 1 + + + STATUS_OUT_ONLY + SETUP: Accept +IN: STALL +OUT: ACK 0B tokens, NAK others + 2 + + + STALL_INOUT + SETUP: Accept +IN: STALL +OUT: STALL + 3 + + + ISO_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept Isochronous OUT token + 5 + + + STATUS_IN_ONLY + SETUP: Accept +IN: Respond with 0B data +OUT: Stall + 6 + + + ISO_IN + SETUP: Ignore +IN: Accept Isochronous IN token +OUT: Ignore + 7 + + + NAK_OUT + SETUP: Ignore +IN: Ignore +OUT: NAK + 8 + + + ACK_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept data and ACK if STALL=0, STALL otherwise. +Change to MODE=8 after one succesfull OUT token. + 9 + + + ACK_OUT_STATUS_IN + SETUP: Accept +IN: Respond with 0B data +OUT: Accept data + 11 + + + NAK_IN + SETUP: Ignore +IN: NAK +OUT: Ignore + 12 + + + ACK_IN + SETUP: Ignore +IN: Respond to IN with data if STALL=0, STALL otherwise +OUT: Ignore + 13 + + + ACK_IN_STATUS_OUT + SETUP: Accept +IN: Respond to IN with data +OUT: ACK 0B tokens, NAK others + 15 + + + + + ACKED_TXN + The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. + [4:4] + read-write + + + ACKED_NO + No ACK'd transactions since bit was last cleared. + 0 + + + ACKED_YES + Indicates a transaction ended with an ACK. + 1 + + + + + NAK_INT_EN + When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK. + [5:5] + read-write + + + ERR_IN_TXN + The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID +error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register. + [6:6] + read-write + + + STALL + When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes. + [7:7] + read-write + + + + + SIE_EP6_CNT0 + Non-control endpoint count register + 0x170 + 32 + read-write + 0x0 + 0xC7 + + + DATA_COUNT_MSB + These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information. + [2:0] + read-write + + + DATA_VALID + This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. + [6:6] + read-write + + + DATA_ERROR + No ACK'd transactions since bit was last cleared. + 0 + + + DATA_VALID + Indicates a transaction ended with an ACK. + 1 + + + + + DATA_TOGGLE + This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. + [7:7] + read-write + + + + + SIE_EP6_CNT1 + Non-control endpoint count register + 0x174 + 32 + read-write + 0x0 + 0xFF + + + DATA_COUNT + These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction. + [7:0] + read-write + + + + + SIE_EP6_CR0 + Non-control endpoint's control Register + 0x178 + 32 + read-write + 0x0 + 0xFF + + + MODE + The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. + [3:0] + read-write + + + DISABLE + Ignore all USB traffic to this endpoint + 0 + + + NAK_INOUT + SETUP: Accept +IN: NAK +OUT: NAK + 1 + + + STATUS_OUT_ONLY + SETUP: Accept +IN: STALL +OUT: ACK 0B tokens, NAK others + 2 + + + STALL_INOUT + SETUP: Accept +IN: STALL +OUT: STALL + 3 + + + ISO_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept Isochronous OUT token + 5 + + + STATUS_IN_ONLY + SETUP: Accept +IN: Respond with 0B data +OUT: Stall + 6 + + + ISO_IN + SETUP: Ignore +IN: Accept Isochronous IN token +OUT: Ignore + 7 + + + NAK_OUT + SETUP: Ignore +IN: Ignore +OUT: NAK + 8 + + + ACK_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept data and ACK if STALL=0, STALL otherwise. +Change to MODE=8 after one succesfull OUT token. + 9 + + + ACK_OUT_STATUS_IN + SETUP: Accept +IN: Respond with 0B data +OUT: Accept data + 11 + + + NAK_IN + SETUP: Ignore +IN: NAK +OUT: Ignore + 12 + + + ACK_IN + SETUP: Ignore +IN: Respond to IN with data if STALL=0, STALL otherwise +OUT: Ignore + 13 + + + ACK_IN_STATUS_OUT + SETUP: Accept +IN: Respond to IN with data +OUT: ACK 0B tokens, NAK others + 15 + + + + + ACKED_TXN + The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. + [4:4] + read-write + + + ACKED_NO + No ACK'd transactions since bit was last cleared. + 0 + + + ACKED_YES + Indicates a transaction ended with an ACK. + 1 + + + + + NAK_INT_EN + When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK. + [5:5] + read-write + + + ERR_IN_TXN + The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID +error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register. + [6:6] + read-write + + + STALL + When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes. + [7:7] + read-write + + + + + SIE_EP7_CNT0 + Non-control endpoint count register + 0x1B0 + 32 + read-write + 0x0 + 0xC7 + + + DATA_COUNT_MSB + These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information. + [2:0] + read-write + + + DATA_VALID + This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. + [6:6] + read-write + + + DATA_ERROR + No ACK'd transactions since bit was last cleared. + 0 + + + DATA_VALID + Indicates a transaction ended with an ACK. + 1 + + + + + DATA_TOGGLE + This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. + [7:7] + read-write + + + + + SIE_EP7_CNT1 + Non-control endpoint count register + 0x1B4 + 32 + read-write + 0x0 + 0xFF + + + DATA_COUNT + These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction. + [7:0] + read-write + + + + + SIE_EP7_CR0 + Non-control endpoint's control Register + 0x1B8 + 32 + read-write + 0x0 + 0xFF + + + MODE + The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. + [3:0] + read-write + + + DISABLE + Ignore all USB traffic to this endpoint + 0 + + + NAK_INOUT + SETUP: Accept +IN: NAK +OUT: NAK + 1 + + + STATUS_OUT_ONLY + SETUP: Accept +IN: STALL +OUT: ACK 0B tokens, NAK others + 2 + + + STALL_INOUT + SETUP: Accept +IN: STALL +OUT: STALL + 3 + + + ISO_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept Isochronous OUT token + 5 + + + STATUS_IN_ONLY + SETUP: Accept +IN: Respond with 0B data +OUT: Stall + 6 + + + ISO_IN + SETUP: Ignore +IN: Accept Isochronous IN token +OUT: Ignore + 7 + + + NAK_OUT + SETUP: Ignore +IN: Ignore +OUT: NAK + 8 + + + ACK_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept data and ACK if STALL=0, STALL otherwise. +Change to MODE=8 after one succesfull OUT token. + 9 + + + ACK_OUT_STATUS_IN + SETUP: Accept +IN: Respond with 0B data +OUT: Accept data + 11 + + + NAK_IN + SETUP: Ignore +IN: NAK +OUT: Ignore + 12 + + + ACK_IN + SETUP: Ignore +IN: Respond to IN with data if STALL=0, STALL otherwise +OUT: Ignore + 13 + + + ACK_IN_STATUS_OUT + SETUP: Accept +IN: Respond to IN with data +OUT: ACK 0B tokens, NAK others + 15 + + + + + ACKED_TXN + The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. + [4:4] + read-write + + + ACKED_NO + No ACK'd transactions since bit was last cleared. + 0 + + + ACKED_YES + Indicates a transaction ended with an ACK. + 1 + + + + + NAK_INT_EN + When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK. + [5:5] + read-write + + + ERR_IN_TXN + The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID +error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register. + [6:6] + read-write + + + STALL + When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes. + [7:7] + read-write + + + + + SIE_EP8_CNT0 + Non-control endpoint count register + 0x1F0 + 32 + read-write + 0x0 + 0xC7 + + + DATA_COUNT_MSB + These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information. + [2:0] + read-write + + + DATA_VALID + This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. + [6:6] + read-write + + + DATA_ERROR + No ACK'd transactions since bit was last cleared. + 0 + + + DATA_VALID + Indicates a transaction ended with an ACK. + 1 + + + + + DATA_TOGGLE + This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. + [7:7] + read-write + + + + + SIE_EP8_CNT1 + Non-control endpoint count register + 0x1F4 + 32 + read-write + 0x0 + 0xFF + + + DATA_COUNT + These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction. + [7:0] + read-write + + + + + SIE_EP8_CR0 + Non-control endpoint's control Register + 0x1F8 + 32 + read-write + 0x0 + 0xFF + + + MODE + The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. + [3:0] + read-write + + + DISABLE + Ignore all USB traffic to this endpoint + 0 + + + NAK_INOUT + SETUP: Accept +IN: NAK +OUT: NAK + 1 + + + STATUS_OUT_ONLY + SETUP: Accept +IN: STALL +OUT: ACK 0B tokens, NAK others + 2 + + + STALL_INOUT + SETUP: Accept +IN: STALL +OUT: STALL + 3 + + + ISO_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept Isochronous OUT token + 5 + + + STATUS_IN_ONLY + SETUP: Accept +IN: Respond with 0B data +OUT: Stall + 6 + + + ISO_IN + SETUP: Ignore +IN: Accept Isochronous IN token +OUT: Ignore + 7 + + + NAK_OUT + SETUP: Ignore +IN: Ignore +OUT: NAK + 8 + + + ACK_OUT + SETUP: Ignore +IN: Ignore +OUT: Accept data and ACK if STALL=0, STALL otherwise. +Change to MODE=8 after one succesfull OUT token. + 9 + + + ACK_OUT_STATUS_IN + SETUP: Accept +IN: Respond with 0B data +OUT: Accept data + 11 + + + NAK_IN + SETUP: Ignore +IN: NAK +OUT: Ignore + 12 + + + ACK_IN + SETUP: Ignore +IN: Respond to IN with data if STALL=0, STALL otherwise +OUT: Ignore + 13 + + + ACK_IN_STATUS_OUT + SETUP: Accept +IN: Respond to IN with data +OUT: ACK 0B tokens, NAK others + 15 + + + + + ACKED_TXN + The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. + [4:4] + read-write + + + ACKED_NO + No ACK'd transactions since bit was last cleared. + 0 + + + ACKED_YES + Indicates a transaction ended with an ACK. + 1 + + + + + NAK_INT_EN + When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK. + [5:5] + read-write + + + ERR_IN_TXN + The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID +error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register. + [6:6] + read-write + + + STALL + When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes. + [7:7] + read-write + + + + + ARB_EP1_CFG + Endpoint Configuration Register *1 + 0x200 + 32 + read-write + 0x0 + 0xF + + + IN_DATA_RDY + Indication that Endpoint Packet Data is Ready in Main memory + [0:0] + read-write + + + DMA_REQ + Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated. + [1:1] + read-write + + + CRC_BYPASS + Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware + [2:2] + read-write + + + CRC_NORMAL + No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s + 0 + + + CRC_BYPASS + CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s + 1 + + + + + RESET_PTR + Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction. + [3:3] + read-write + + + RESET_KRYPTON + Do not Reset Pointer; Krypton Backward compatibility mode + 0 + + + RESET_NORMAL + Reset Pointer; recommended value for reduction of CPU Configuration Writes. + 1 + + + + + + + ARB_EP1_INT_EN + Endpoint Interrupt Enable Register *1 + 0x204 + 32 + read-write + 0x0 + 0x3F + + + IN_BUF_FULL_EN + IN Endpoint Local Buffer Full Enable + [0:0] + read-write + + + DMA_GNT_EN + Endpoint DMA Grant Enable + [1:1] + read-write + + + BUF_OVER_EN + Endpoint Buffer Overflow Enable + [2:2] + read-write + + + BUF_UNDER_EN + Endpoint Buffer Underflow Enable + [3:3] + read-write + + + ERR_INT_EN + Endpoint Error in Transaction Interrupt Enable + [4:4] + read-write + + + DMA_TERMIN_EN + Endpoint DMA Terminated Enable + [5:5] + read-write + + + + + ARB_EP1_SR + Endpoint Interrupt Enable Register *1 + 0x208 + 32 + read-write + 0x0 + 0x2F + + + IN_BUF_FULL + IN Endpoint Local Buffer Full Interrupt + [0:0] + read-write + + + DMA_GNT + Endpoint DMA Grant Interrupt + [1:1] + read-write + + + BUF_OVER + Endpoint Buffer Overflow Interrupt + [2:2] + read-write + + + BUF_UNDER + Endpoint Buffer Underflow Interrupt + [3:3] + read-write + + + DMA_TERMIN + Endpoint DMA Terminated Interrupt + [5:5] + read-write + + + + + ARB_RW1_WA + Endpoint Write Address value *1, *2 + 0x210 + 32 + read-write + 0x0 + 0xFF + + + WA + Write Address for EP + [7:0] + read-write + + + + + ARB_RW1_WA_MSB + Endpoint Write Address value *1, *2 + 0x214 + 32 + read-write + 0x0 + 0x1 + + + WA_MSB + Write Address for EP + [0:0] + read-write + + + + + ARB_RW1_RA + Endpoint Read Address value *1, *2 + 0x218 + 32 + read-write + 0x0 + 0xFF + + + RA + Read Address for EP + [7:0] + read-write + + + + + ARB_RW1_RA_MSB + Endpoint Read Address value *1, *2 + 0x21C + 32 + read-write + 0x0 + 0x1 + + + RA_MSB + Read Address for EP + [0:0] + read-write + + + + + ARB_RW1_DR + Endpoint Data Register + 0x220 + 32 + read-write + 0x0 + 0x0 + + + DR + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [7:0] + read-write + + + + + BUF_SIZE + Dedicated Endpoint Buffer Size Register *1 + 0x230 + 32 + read-write + 0x0 + 0xFF + + + IN_BUF + Buffer size for IN Endpoints. + [3:0] + read-write + + + OUT_BUF + Buffer size for OUT Endpoints. + [7:4] + read-write + + + + + EP_ACTIVE + Endpoint Active Indication Register *1 + 0x238 + 32 + read-write + 0x0 + 0xFF + + + EP1_ACT + Indicates that Endpoint is currently active. + [0:0] + read-write + + + EP2_ACT + Indicates that Endpoint is currently active. + [1:1] + read-write + + + EP3_ACT + Indicates that Endpoint is currently active. + [2:2] + read-write + + + EP4_ACT + Indicates that Endpoint is currently active. + [3:3] + read-write + + + EP5_ACT + Indicates that Endpoint is currently active. + [4:4] + read-write + + + EP6_ACT + Indicates that Endpoint is currently active. + [5:5] + read-write + + + EP7_ACT + Indicates that Endpoint is currently active. + [6:6] + read-write + + + EP8_ACT + Indicates that Endpoint is currently active. + [7:7] + read-write + + + + + EP_TYPE + Endpoint Type (IN/OUT) Indication *1 + 0x23C + 32 + read-write + 0x0 + 0xFF + + + EP1_TYP + Endpoint Type Indication. + [0:0] + read-write + + + EP_IN + IN outpoint + 0 + + + EP_OUT + OUT outpoint + 1 + + + + + EP2_TYP + Endpoint Type Indication. + [1:1] + read-write + + + EP_IN + IN outpoint + 0 + + + EP_OUT + OUT outpoint + 1 + + + + + EP3_TYP + Endpoint Type Indication. + [2:2] + read-write + + + EP_IN + IN outpoint + 0 + + + EP_OUT + OUT outpoint + 1 + + + + + EP4_TYP + Endpoint Type Indication. + [3:3] + read-write + + + EP_IN + IN outpoint + 0 + + + EP_OUT + OUT outpoint + 1 + + + + + EP5_TYP + Endpoint Type Indication. + [4:4] + read-write + + + EP_IN + IN outpoint + 0 + + + EP_OUT + OUT outpoint + 1 + + + + + EP6_TYP + Endpoint Type Indication. + [5:5] + read-write + + + EP_IN + IN outpoint + 0 + + + EP_OUT + OUT outpoint + 1 + + + + + EP7_TYP + Endpoint Type Indication. + [6:6] + read-write + + + EP_IN + IN outpoint + 0 + + + EP_OUT + OUT outpoint + 1 + + + + + EP8_TYP + Endpoint Type Indication. + [7:7] + read-write + + + EP_IN + IN outpoint + 0 + + + EP_OUT + OUT outpoint + 1 + + + + + + + ARB_EP2_CFG + Endpoint Configuration Register *1 + 0x240 + 32 + read-write + 0x0 + 0xF + + + IN_DATA_RDY + Indication that Endpoint Packet Data is Ready in Main memory + [0:0] + read-write + + + DMA_REQ + Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated. + [1:1] + read-write + + + CRC_BYPASS + Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware + [2:2] + read-write + + + CRC_NORMAL + No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s + 0 + + + CRC_BYPASS + CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s + 1 + + + + + RESET_PTR + Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction. + [3:3] + read-write + + + RESET_KRYPTON + Do not Reset Pointer; Krypton Backward compatibility mode + 0 + + + RESET_NORMAL + Reset Pointer; recommended value for reduction of CPU Configuration Writes. + 1 + + + + + + + ARB_EP2_INT_EN + Endpoint Interrupt Enable Register *1 + 0x244 + 32 + read-write + 0x0 + 0x3F + + + IN_BUF_FULL_EN + IN Endpoint Local Buffer Full Enable + [0:0] + read-write + + + DMA_GNT_EN + Endpoint DMA Grant Enable + [1:1] + read-write + + + BUF_OVER_EN + Endpoint Buffer Overflow Enable + [2:2] + read-write + + + BUF_UNDER_EN + Endpoint Buffer Underflow Enable + [3:3] + read-write + + + ERR_INT_EN + Endpoint Error in Transaction Interrupt Enable + [4:4] + read-write + + + DMA_TERMIN_EN + Endpoint DMA Terminated Enable + [5:5] + read-write + + + + + ARB_EP2_SR + Endpoint Interrupt Enable Register *1 + 0x248 + 32 + read-write + 0x0 + 0x2F + + + IN_BUF_FULL + IN Endpoint Local Buffer Full Interrupt + [0:0] + read-write + + + DMA_GNT + Endpoint DMA Grant Interrupt + [1:1] + read-write + + + BUF_OVER + Endpoint Buffer Overflow Interrupt + [2:2] + read-write + + + BUF_UNDER + Endpoint Buffer Underflow Interrupt + [3:3] + read-write + + + DMA_TERMIN + Endpoint DMA Terminated Interrupt + [5:5] + read-write + + + + + ARB_RW2_WA + Endpoint Write Address value *1, *2 + 0x250 + 32 + read-write + 0x0 + 0xFF + + + WA + Write Address for EP + [7:0] + read-write + + + + + ARB_RW2_WA_MSB + Endpoint Write Address value *1, *2 + 0x254 + 32 + read-write + 0x0 + 0x1 + + + WA_MSB + Write Address for EP + [0:0] + read-write + + + + + ARB_RW2_RA + Endpoint Read Address value *1, *2 + 0x258 + 32 + read-write + 0x0 + 0xFF + + + RA + Read Address for EP + [7:0] + read-write + + + + + ARB_RW2_RA_MSB + Endpoint Read Address value *1, *2 + 0x25C + 32 + read-write + 0x0 + 0x1 + + + RA_MSB + Read Address for EP + [0:0] + read-write + + + + + ARB_RW2_DR + Endpoint Data Register + 0x260 + 32 + read-write + 0x0 + 0x0 + + + DR + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [7:0] + read-write + + + + + ARB_CFG + Arbiter Configuration Register *1 + 0x270 + 32 + read-write + 0x0 + 0xF0 + + + AUTO_MEM + Enables Auto Memory Configuration. Manual memory configuration by default. + [4:4] + read-write + + + DMA_CFG + DMA Access Configuration. + [6:5] + read-write + + + DMA_NONE + No DMA + 0 + + + DMA_MANUAL + Manual DMA + 1 + + + DMA_AUTO + Auto DMA + 2 + + + + + CFG_CMP + Register Configuration Complete Indication. Posedge is detected on this bit. Hence a 0 to 1 transition is required. + [7:7] + read-write + + + + + USB_CLK_EN + USB Block Clock Enable Register + 0x274 + 32 + read-write + 0x0 + 0x1 + + + CSR_CLK_EN + Clock Enable for Core Logic clocked by AHB bus clock + [0:0] + read-write + + + + + ARB_INT_EN + Arbiter Interrupt Enable *1 + 0x278 + 32 + read-write + 0x0 + 0xFF + + + EP1_INTR_EN + Enables interrupt for EP1 + [0:0] + read-write + + + EP2_INTR_EN + Enables interrupt for EP2 + [1:1] + read-write + + + EP3_INTR_EN + Enables interrupt for EP3 + [2:2] + read-write + + + EP4_INTR_EN + Enables interrupt for EP4 + [3:3] + read-write + + + EP5_INTR_EN + Enables interrupt for EP5 + [4:4] + read-write + + + EP6_INTR_EN + Enables interrupt for EP6 + [5:5] + read-write + + + EP7_INTR_EN + Enables interrupt for EP7 + [6:6] + read-write + + + EP8_INTR_EN + Enables interrupt for EP8 + [7:7] + read-write + + + + + ARB_INT_SR + Arbiter Interrupt Status *1 + 0x27C + 32 + read-only + 0x0 + 0xFF + + + EP1_INTR + Interrupt status for EP1 + [0:0] + read-only + + + EP2_INTR + Interrupt status for EP2 + [1:1] + read-only + + + EP3_INTR + Interrupt status for EP3 + [2:2] + read-only + + + EP4_INTR + Interrupt status for EP4 + [3:3] + read-only + + + EP5_INTR + Interrupt status for EP5 + [4:4] + read-only + + + EP6_INTR + Interrupt status for EP6 + [5:5] + read-only + + + EP7_INTR + Interrupt status for EP7 + [6:6] + read-only + + + EP8_INTR + Interrupt status for EP8 + [7:7] + read-only + + + + + ARB_EP3_CFG + Endpoint Configuration Register *1 + 0x280 + 32 + read-write + 0x0 + 0xF + + + IN_DATA_RDY + Indication that Endpoint Packet Data is Ready in Main memory + [0:0] + read-write + + + DMA_REQ + Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated. + [1:1] + read-write + + + CRC_BYPASS + Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware + [2:2] + read-write + + + CRC_NORMAL + No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s + 0 + + + CRC_BYPASS + CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s + 1 + + + + + RESET_PTR + Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction. + [3:3] + read-write + + + RESET_KRYPTON + Do not Reset Pointer; Krypton Backward compatibility mode + 0 + + + RESET_NORMAL + Reset Pointer; recommended value for reduction of CPU Configuration Writes. + 1 + + + + + + + ARB_EP3_INT_EN + Endpoint Interrupt Enable Register *1 + 0x284 + 32 + read-write + 0x0 + 0x3F + + + IN_BUF_FULL_EN + IN Endpoint Local Buffer Full Enable + [0:0] + read-write + + + DMA_GNT_EN + Endpoint DMA Grant Enable + [1:1] + read-write + + + BUF_OVER_EN + Endpoint Buffer Overflow Enable + [2:2] + read-write + + + BUF_UNDER_EN + Endpoint Buffer Underflow Enable + [3:3] + read-write + + + ERR_INT_EN + Endpoint Error in Transaction Interrupt Enable + [4:4] + read-write + + + DMA_TERMIN_EN + Endpoint DMA Terminated Enable + [5:5] + read-write + + + + + ARB_EP3_SR + Endpoint Interrupt Enable Register *1 + 0x288 + 32 + read-write + 0x0 + 0x2F + + + IN_BUF_FULL + IN Endpoint Local Buffer Full Interrupt + [0:0] + read-write + + + DMA_GNT + Endpoint DMA Grant Interrupt + [1:1] + read-write + + + BUF_OVER + Endpoint Buffer Overflow Interrupt + [2:2] + read-write + + + BUF_UNDER + Endpoint Buffer Underflow Interrupt + [3:3] + read-write + + + DMA_TERMIN + Endpoint DMA Terminated Interrupt + [5:5] + read-write + + + + + ARB_RW3_WA + Endpoint Write Address value *1, *2 + 0x290 + 32 + read-write + 0x0 + 0xFF + + + WA + Write Address for EP + [7:0] + read-write + + + + + ARB_RW3_WA_MSB + Endpoint Write Address value *1, *2 + 0x294 + 32 + read-write + 0x0 + 0x1 + + + WA_MSB + Write Address for EP + [0:0] + read-write + + + + + ARB_RW3_RA + Endpoint Read Address value *1, *2 + 0x298 + 32 + read-write + 0x0 + 0xFF + + + RA + Read Address for EP + [7:0] + read-write + + + + + ARB_RW3_RA_MSB + Endpoint Read Address value *1, *2 + 0x29C + 32 + read-write + 0x0 + 0x1 + + + RA_MSB + Read Address for EP + [0:0] + read-write + + + + + ARB_RW3_DR + Endpoint Data Register + 0x2A0 + 32 + read-write + 0x0 + 0x0 + + + DR + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [7:0] + read-write + + + + + CWA + Common Area Write Address *1 + 0x2B0 + 32 + read-write + 0x0 + 0xFF + + + CWA + Write Address for Common Area + [7:0] + read-write + + + + + CWA_MSB + Endpoint Read Address value *1 + 0x2B4 + 32 + read-write + 0x0 + 0x1 + + + CWA_MSB + Write Address for Common Area + [0:0] + read-write + + + + + ARB_EP4_CFG + Endpoint Configuration Register *1 + 0x2C0 + 32 + read-write + 0x0 + 0xF + + + IN_DATA_RDY + Indication that Endpoint Packet Data is Ready in Main memory + [0:0] + read-write + + + DMA_REQ + Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated. + [1:1] + read-write + + + CRC_BYPASS + Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware + [2:2] + read-write + + + CRC_NORMAL + No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s + 0 + + + CRC_BYPASS + CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s + 1 + + + + + RESET_PTR + Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction. + [3:3] + read-write + + + RESET_KRYPTON + Do not Reset Pointer; Krypton Backward compatibility mode + 0 + + + RESET_NORMAL + Reset Pointer; recommended value for reduction of CPU Configuration Writes. + 1 + + + + + + + ARB_EP4_INT_EN + Endpoint Interrupt Enable Register *1 + 0x2C4 + 32 + read-write + 0x0 + 0x3F + + + IN_BUF_FULL_EN + IN Endpoint Local Buffer Full Enable + [0:0] + read-write + + + DMA_GNT_EN + Endpoint DMA Grant Enable + [1:1] + read-write + + + BUF_OVER_EN + Endpoint Buffer Overflow Enable + [2:2] + read-write + + + BUF_UNDER_EN + Endpoint Buffer Underflow Enable + [3:3] + read-write + + + ERR_INT_EN + Endpoint Error in Transaction Interrupt Enable + [4:4] + read-write + + + DMA_TERMIN_EN + Endpoint DMA Terminated Enable + [5:5] + read-write + + + + + ARB_EP4_SR + Endpoint Interrupt Enable Register *1 + 0x2C8 + 32 + read-write + 0x0 + 0x2F + + + IN_BUF_FULL + IN Endpoint Local Buffer Full Interrupt + [0:0] + read-write + + + DMA_GNT + Endpoint DMA Grant Interrupt + [1:1] + read-write + + + BUF_OVER + Endpoint Buffer Overflow Interrupt + [2:2] + read-write + + + BUF_UNDER + Endpoint Buffer Underflow Interrupt + [3:3] + read-write + + + DMA_TERMIN + Endpoint DMA Terminated Interrupt + [5:5] + read-write + + + + + ARB_RW4_WA + Endpoint Write Address value *1, *2 + 0x2D0 + 32 + read-write + 0x0 + 0xFF + + + WA + Write Address for EP + [7:0] + read-write + + + + + ARB_RW4_WA_MSB + Endpoint Write Address value *1, *2 + 0x2D4 + 32 + read-write + 0x0 + 0x1 + + + WA_MSB + Write Address for EP + [0:0] + read-write + + + + + ARB_RW4_RA + Endpoint Read Address value *1, *2 + 0x2D8 + 32 + read-write + 0x0 + 0xFF + + + RA + Read Address for EP + [7:0] + read-write + + + + + ARB_RW4_RA_MSB + Endpoint Read Address value *1, *2 + 0x2DC + 32 + read-write + 0x0 + 0x1 + + + RA_MSB + Read Address for EP + [0:0] + read-write + + + + + ARB_RW4_DR + Endpoint Data Register + 0x2E0 + 32 + read-write + 0x0 + 0x0 + + + DR + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [7:0] + read-write + + + + + DMA_THRES + DMA Burst / Threshold Configuration + 0x2F0 + 32 + read-write + 0x0 + 0xFF + + + DMA_THS + DMA Threshold count + [7:0] + read-write + + + + + DMA_THRES_MSB + DMA Burst / Threshold Configuration + 0x2F4 + 32 + read-write + 0x0 + 0x1 + + + DMA_THS_MSB + DMA Threshold count + [0:0] + read-write + + + + + ARB_EP5_CFG + Endpoint Configuration Register *1 + 0x300 + 32 + read-write + 0x0 + 0xF + + + IN_DATA_RDY + Indication that Endpoint Packet Data is Ready in Main memory + [0:0] + read-write + + + DMA_REQ + Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated. + [1:1] + read-write + + + CRC_BYPASS + Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware + [2:2] + read-write + + + CRC_NORMAL + No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s + 0 + + + CRC_BYPASS + CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s + 1 + + + + + RESET_PTR + Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction. + [3:3] + read-write + + + RESET_KRYPTON + Do not Reset Pointer; Krypton Backward compatibility mode + 0 + + + RESET_NORMAL + Reset Pointer; recommended value for reduction of CPU Configuration Writes. + 1 + + + + + + + ARB_EP5_INT_EN + Endpoint Interrupt Enable Register *1 + 0x304 + 32 + read-write + 0x0 + 0x3F + + + IN_BUF_FULL_EN + IN Endpoint Local Buffer Full Enable + [0:0] + read-write + + + DMA_GNT_EN + Endpoint DMA Grant Enable + [1:1] + read-write + + + BUF_OVER_EN + Endpoint Buffer Overflow Enable + [2:2] + read-write + + + BUF_UNDER_EN + Endpoint Buffer Underflow Enable + [3:3] + read-write + + + ERR_INT_EN + Endpoint Error in Transaction Interrupt Enable + [4:4] + read-write + + + DMA_TERMIN_EN + Endpoint DMA Terminated Enable + [5:5] + read-write + + + + + ARB_EP5_SR + Endpoint Interrupt Enable Register *1 + 0x308 + 32 + read-write + 0x0 + 0x2F + + + IN_BUF_FULL + IN Endpoint Local Buffer Full Interrupt + [0:0] + read-write + + + DMA_GNT + Endpoint DMA Grant Interrupt + [1:1] + read-write + + + BUF_OVER + Endpoint Buffer Overflow Interrupt + [2:2] + read-write + + + BUF_UNDER + Endpoint Buffer Underflow Interrupt + [3:3] + read-write + + + DMA_TERMIN + Endpoint DMA Terminated Interrupt + [5:5] + read-write + + + + + ARB_RW5_WA + Endpoint Write Address value *1, *2 + 0x310 + 32 + read-write + 0x0 + 0xFF + + + WA + Write Address for EP + [7:0] + read-write + + + + + ARB_RW5_WA_MSB + Endpoint Write Address value *1, *2 + 0x314 + 32 + read-write + 0x0 + 0x1 + + + WA_MSB + Write Address for EP + [0:0] + read-write + + + + + ARB_RW5_RA + Endpoint Read Address value *1, *2 + 0x318 + 32 + read-write + 0x0 + 0xFF + + + RA + Read Address for EP + [7:0] + read-write + + + + + ARB_RW5_RA_MSB + Endpoint Read Address value *1, *2 + 0x31C + 32 + read-write + 0x0 + 0x1 + + + RA_MSB + Read Address for EP + [0:0] + read-write + + + + + ARB_RW5_DR + Endpoint Data Register + 0x320 + 32 + read-write + 0x0 + 0x0 + + + DR + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [7:0] + read-write + + + + + BUS_RST_CNT + Bus Reset Count Register + 0x330 + 32 + read-write + 0xA + 0xF + + + BUS_RST_CNT + Bus Reset Count Length + [3:0] + read-write + + + + + ARB_EP6_CFG + Endpoint Configuration Register *1 + 0x340 + 32 + read-write + 0x0 + 0xF + + + IN_DATA_RDY + Indication that Endpoint Packet Data is Ready in Main memory + [0:0] + read-write + + + DMA_REQ + Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated. + [1:1] + read-write + + + CRC_BYPASS + Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware + [2:2] + read-write + + + CRC_NORMAL + No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s + 0 + + + CRC_BYPASS + CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s + 1 + + + + + RESET_PTR + Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction. + [3:3] + read-write + + + RESET_KRYPTON + Do not Reset Pointer; Krypton Backward compatibility mode + 0 + + + RESET_NORMAL + Reset Pointer; recommended value for reduction of CPU Configuration Writes. + 1 + + + + + + + ARB_EP6_INT_EN + Endpoint Interrupt Enable Register *1 + 0x344 + 32 + read-write + 0x0 + 0x3F + + + IN_BUF_FULL_EN + IN Endpoint Local Buffer Full Enable + [0:0] + read-write + + + DMA_GNT_EN + Endpoint DMA Grant Enable + [1:1] + read-write + + + BUF_OVER_EN + Endpoint Buffer Overflow Enable + [2:2] + read-write + + + BUF_UNDER_EN + Endpoint Buffer Underflow Enable + [3:3] + read-write + + + ERR_INT_EN + Endpoint Error in Transaction Interrupt Enable + [4:4] + read-write + + + DMA_TERMIN_EN + Endpoint DMA Terminated Enable + [5:5] + read-write + + + + + ARB_EP6_SR + Endpoint Interrupt Enable Register *1 + 0x348 + 32 + read-write + 0x0 + 0x2F + + + IN_BUF_FULL + IN Endpoint Local Buffer Full Interrupt + [0:0] + read-write + + + DMA_GNT + Endpoint DMA Grant Interrupt + [1:1] + read-write + + + BUF_OVER + Endpoint Buffer Overflow Interrupt + [2:2] + read-write + + + BUF_UNDER + Endpoint Buffer Underflow Interrupt + [3:3] + read-write + + + DMA_TERMIN + Endpoint DMA Terminated Interrupt + [5:5] + read-write + + + + + ARB_RW6_WA + Endpoint Write Address value *1, *2 + 0x350 + 32 + read-write + 0x0 + 0xFF + + + WA + Write Address for EP + [7:0] + read-write + + + + + ARB_RW6_WA_MSB + Endpoint Write Address value *1, *2 + 0x354 + 32 + read-write + 0x0 + 0x1 + + + WA_MSB + Write Address for EP + [0:0] + read-write + + + + + ARB_RW6_RA + Endpoint Read Address value *1, *2 + 0x358 + 32 + read-write + 0x0 + 0xFF + + + RA + Read Address for EP + [7:0] + read-write + + + + + ARB_RW6_RA_MSB + Endpoint Read Address value *1, *2 + 0x35C + 32 + read-write + 0x0 + 0x1 + + + RA_MSB + Read Address for EP + [0:0] + read-write + + + + + ARB_RW6_DR + Endpoint Data Register + 0x360 + 32 + read-write + 0x0 + 0x0 + + + DR + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [7:0] + read-write + + + + + ARB_EP7_CFG + Endpoint Configuration Register *1 + 0x380 + 32 + read-write + 0x0 + 0xF + + + IN_DATA_RDY + Indication that Endpoint Packet Data is Ready in Main memory + [0:0] + read-write + + + DMA_REQ + Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated. + [1:1] + read-write + + + CRC_BYPASS + Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware + [2:2] + read-write + + + CRC_NORMAL + No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s + 0 + + + CRC_BYPASS + CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s + 1 + + + + + RESET_PTR + Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction. + [3:3] + read-write + + + RESET_KRYPTON + Do not Reset Pointer; Krypton Backward compatibility mode + 0 + + + RESET_NORMAL + Reset Pointer; recommended value for reduction of CPU Configuration Writes. + 1 + + + + + + + ARB_EP7_INT_EN + Endpoint Interrupt Enable Register *1 + 0x384 + 32 + read-write + 0x0 + 0x3F + + + IN_BUF_FULL_EN + IN Endpoint Local Buffer Full Enable + [0:0] + read-write + + + DMA_GNT_EN + Endpoint DMA Grant Enable + [1:1] + read-write + + + BUF_OVER_EN + Endpoint Buffer Overflow Enable + [2:2] + read-write + + + BUF_UNDER_EN + Endpoint Buffer Underflow Enable + [3:3] + read-write + + + ERR_INT_EN + Endpoint Error in Transaction Interrupt Enable + [4:4] + read-write + + + DMA_TERMIN_EN + Endpoint DMA Terminated Enable + [5:5] + read-write + + + + + ARB_EP7_SR + Endpoint Interrupt Enable Register *1 + 0x388 + 32 + read-write + 0x0 + 0x2F + + + IN_BUF_FULL + IN Endpoint Local Buffer Full Interrupt + [0:0] + read-write + + + DMA_GNT + Endpoint DMA Grant Interrupt + [1:1] + read-write + + + BUF_OVER + Endpoint Buffer Overflow Interrupt + [2:2] + read-write + + + BUF_UNDER + Endpoint Buffer Underflow Interrupt + [3:3] + read-write + + + DMA_TERMIN + Endpoint DMA Terminated Interrupt + [5:5] + read-write + + + + + ARB_RW7_WA + Endpoint Write Address value *1, *2 + 0x390 + 32 + read-write + 0x0 + 0xFF + + + WA + Write Address for EP + [7:0] + read-write + + + + + ARB_RW7_WA_MSB + Endpoint Write Address value *1, *2 + 0x394 + 32 + read-write + 0x0 + 0x1 + + + WA_MSB + Write Address for EP + [0:0] + read-write + + + + + ARB_RW7_RA + Endpoint Read Address value *1, *2 + 0x398 + 32 + read-write + 0x0 + 0xFF + + + RA + Read Address for EP + [7:0] + read-write + + + + + ARB_RW7_RA_MSB + Endpoint Read Address value *1, *2 + 0x39C + 32 + read-write + 0x0 + 0x1 + + + RA_MSB + Read Address for EP + [0:0] + read-write + + + + + ARB_RW7_DR + Endpoint Data Register + 0x3A0 + 32 + read-write + 0x0 + 0x0 + + + DR + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [7:0] + read-write + + + + + ARB_EP8_CFG + Endpoint Configuration Register *1 + 0x3C0 + 32 + read-write + 0x0 + 0xF + + + IN_DATA_RDY + Indication that Endpoint Packet Data is Ready in Main memory + [0:0] + read-write + + + DMA_REQ + Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated. + [1:1] + read-write + + + CRC_BYPASS + Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware + [2:2] + read-write + + + CRC_NORMAL + No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s + 0 + + + CRC_BYPASS + CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s + 1 + + + + + RESET_PTR + Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction. + [3:3] + read-write + + + RESET_KRYPTON + Do not Reset Pointer; Krypton Backward compatibility mode + 0 + + + RESET_NORMAL + Reset Pointer; recommended value for reduction of CPU Configuration Writes. + 1 + + + + + + + ARB_EP8_INT_EN + Endpoint Interrupt Enable Register *1 + 0x3C4 + 32 + read-write + 0x0 + 0x3F + + + IN_BUF_FULL_EN + IN Endpoint Local Buffer Full Enable + [0:0] + read-write + + + DMA_GNT_EN + Endpoint DMA Grant Enable + [1:1] + read-write + + + BUF_OVER_EN + Endpoint Buffer Overflow Enable + [2:2] + read-write + + + BUF_UNDER_EN + Endpoint Buffer Underflow Enable + [3:3] + read-write + + + ERR_INT_EN + Endpoint Error in Transaction Interrupt Enable + [4:4] + read-write + + + DMA_TERMIN_EN + Endpoint DMA Terminated Enable + [5:5] + read-write + + + + + ARB_EP8_SR + Endpoint Interrupt Enable Register *1 + 0x3C8 + 32 + read-write + 0x0 + 0x2F + + + IN_BUF_FULL + IN Endpoint Local Buffer Full Interrupt + [0:0] + read-write + + + DMA_GNT + Endpoint DMA Grant Interrupt + [1:1] + read-write + + + BUF_OVER + Endpoint Buffer Overflow Interrupt + [2:2] + read-write + + + BUF_UNDER + Endpoint Buffer Underflow Interrupt + [3:3] + read-write + + + DMA_TERMIN + Endpoint DMA Terminated Interrupt + [5:5] + read-write + + + + + ARB_RW8_WA + Endpoint Write Address value *1, *2 + 0x3D0 + 32 + read-write + 0x0 + 0xFF + + + WA + Write Address for EP + [7:0] + read-write + + + + + ARB_RW8_WA_MSB + Endpoint Write Address value *1, *2 + 0x3D4 + 32 + read-write + 0x0 + 0x1 + + + WA_MSB + Write Address for EP + [0:0] + read-write + + + + + ARB_RW8_RA + Endpoint Read Address value *1, *2 + 0x3D8 + 32 + read-write + 0x0 + 0xFF + + + RA + Read Address for EP + [7:0] + read-write + + + + + ARB_RW8_RA_MSB + Endpoint Read Address value *1, *2 + 0x3DC + 32 + read-write + 0x0 + 0x1 + + + RA_MSB + Read Address for EP + [0:0] + read-write + + + + + ARB_RW8_DR + Endpoint Data Register + 0x3E0 + 32 + read-write + 0x0 + 0x0 + + + DR + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [7:0] + read-write + + + + + 512 + 4 + MEM_DATA[%s] + DATA + 0x400 + 32 + read-write + 0x0 + 0x0 + + + DR + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [7:0] + read-write + + + + + SOF16 + Start Of Frame Register + 0x1060 + 32 + read-only + 0x0 + 0x7FF + + + FRAME_NUMBER16 + The frame number (11b) + [10:0] + read-only + + + + + OSCLK_DR16 + Oscillator lock data register + 0x1080 + 32 + read-only + 0x0 + 0x0 + + + ADDER16 + These bits return the oscillator locking circuits adder output. + [14:0] + read-only + + + + + ARB_RW1_WA16 + Endpoint Write Address value *3 + 0x1210 + 32 + read-write + 0x0 + 0x1FF + + + WA16 + Write Address for EP + [8:0] + read-write + + + + + ARB_RW1_RA16 + Endpoint Read Address value *3 + 0x1218 + 32 + read-write + 0x0 + 0x1FF + + + RA16 + Read Address for EP + [8:0] + read-write + + + + + ARB_RW1_DR16 + Endpoint Data Register + 0x1220 + 32 + read-write + 0x0 + 0x0 + + + DR16 + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [15:0] + read-write + + + + + ARB_RW2_WA16 + Endpoint Write Address value *3 + 0x1250 + 32 + read-write + 0x0 + 0x1FF + + + WA16 + Write Address for EP + [8:0] + read-write + + + + + ARB_RW2_RA16 + Endpoint Read Address value *3 + 0x1258 + 32 + read-write + 0x0 + 0x1FF + + + RA16 + Read Address for EP + [8:0] + read-write + + + + + ARB_RW2_DR16 + Endpoint Data Register + 0x1260 + 32 + read-write + 0x0 + 0x0 + + + DR16 + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [15:0] + read-write + + + + + ARB_RW3_WA16 + Endpoint Write Address value *3 + 0x1290 + 32 + read-write + 0x0 + 0x1FF + + + WA16 + Write Address for EP + [8:0] + read-write + + + + + ARB_RW3_RA16 + Endpoint Read Address value *3 + 0x1298 + 32 + read-write + 0x0 + 0x1FF + + + RA16 + Read Address for EP + [8:0] + read-write + + + + + ARB_RW3_DR16 + Endpoint Data Register + 0x12A0 + 32 + read-write + 0x0 + 0x0 + + + DR16 + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [15:0] + read-write + + + + + CWA16 + Common Area Write Address + 0x12B0 + 32 + read-write + 0x0 + 0x1FF + + + CWA16 + Write Address for Common Area + [8:0] + read-write + + + + + ARB_RW4_WA16 + Endpoint Write Address value *3 + 0x12D0 + 32 + read-write + 0x0 + 0x1FF + + + WA16 + Write Address for EP + [8:0] + read-write + + + + + ARB_RW4_RA16 + Endpoint Read Address value *3 + 0x12D8 + 32 + read-write + 0x0 + 0x1FF + + + RA16 + Read Address for EP + [8:0] + read-write + + + + + ARB_RW4_DR16 + Endpoint Data Register + 0x12E0 + 32 + read-write + 0x0 + 0x0 + + + DR16 + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [15:0] + read-write + + + + + DMA_THRES16 + DMA Burst / Threshold Configuration + 0x12F0 + 32 + read-write + 0x0 + 0x1FF + + + DMA_THS16 + DMA Threshold count + [8:0] + read-write + + + + + ARB_RW5_WA16 + Endpoint Write Address value *3 + 0x1310 + 32 + read-write + 0x0 + 0x1FF + + + WA16 + Write Address for EP + [8:0] + read-write + + + + + ARB_RW5_RA16 + Endpoint Read Address value *3 + 0x1318 + 32 + read-write + 0x0 + 0x1FF + + + RA16 + Read Address for EP + [8:0] + read-write + + + + + ARB_RW5_DR16 + Endpoint Data Register + 0x1320 + 32 + read-write + 0x0 + 0x0 + + + DR16 + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [15:0] + read-write + + + + + ARB_RW6_WA16 + Endpoint Write Address value *3 + 0x1350 + 32 + read-write + 0x0 + 0x1FF + + + WA16 + Write Address for EP + [8:0] + read-write + + + + + ARB_RW6_RA16 + Endpoint Read Address value *3 + 0x1358 + 32 + read-write + 0x0 + 0x1FF + + + RA16 + Read Address for EP + [8:0] + read-write + + + + + ARB_RW6_DR16 + Endpoint Data Register + 0x1360 + 32 + read-write + 0x0 + 0x0 + + + DR16 + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [15:0] + read-write + + + + + ARB_RW7_WA16 + Endpoint Write Address value *3 + 0x1390 + 32 + read-write + 0x0 + 0x1FF + + + WA16 + Write Address for EP + [8:0] + read-write + + + + + ARB_RW7_RA16 + Endpoint Read Address value *3 + 0x1398 + 32 + read-write + 0x0 + 0x1FF + + + RA16 + Read Address for EP + [8:0] + read-write + + + + + ARB_RW7_DR16 + Endpoint Data Register + 0x13A0 + 32 + read-write + 0x0 + 0x0 + + + DR16 + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [15:0] + read-write + + + + + ARB_RW8_WA16 + Endpoint Write Address value *3 + 0x13D0 + 32 + read-write + 0x0 + 0x1FF + + + WA16 + Write Address for EP + [8:0] + read-write + + + + + ARB_RW8_RA16 + Endpoint Read Address value *3 + 0x13D8 + 32 + read-write + 0x0 + 0x1FF + + + RA16 + Read Address for EP + [8:0] + read-write + + + + + ARB_RW8_DR16 + Endpoint Data Register + 0x13E0 + 32 + read-write + 0x0 + 0x0 + + + DR16 + Data Register for EP ; This register is linked to the memory, hence reset value is undefined + [15:0] + read-write + + + + + + USBLPM + USB Device LPM and PHY Test + 0x00002000 + + POWER_CTL + Power Control Register + 0x0 + 32 + read-write + 0x0 + 0x303F0004 + + + SUSPEND + Put PHY into Suspend mode. If the PHY is enabled, this bit MUST be set before entering a low power mode (DeepSleep). +Note: +- This bit is invalid if the HOST bit of the Host Control 0 Register (HOST_CTL0) is '1'. + [2:2] + read-write + + + DP_UP_EN + Enables the pull up on the DP. +'0' : Disable. +'1' : Enable. + [16:16] + read-write + + + DP_BIG + Select the resister value if POWER_CTL.DP_EN='1'. This bit is valid in GPIO. +'0' : The resister value is from 900 to1575Ohmpull up on the DP. +'1' : The resister value is from 1425 to 3090Ohmpull up on the DP + [17:17] + read-write + + + DP_DOWN_EN + Enables the ~15k pull down on the DP. + [18:18] + read-write + + + DM_UP_EN + Enables the pull up on the DM. The bit is valid in GPIO. The pull up resistor is disabled in not GPIO. +'0' : Disable. +'1' : Enable. + [19:19] + read-write + + + DM_BIG + Select the resister value if POWER_CTL.DM_EN='1'. This bit is valid in GPIO. +'0' : The resister value is from 900 to1575Ohmpull up on the DM. +'1' : The resister value is from 1425 to 3090Ohmpull up on the DM + [20:20] + read-write + + + DM_DOWN_EN + Enables the ~15k pull down on the DP. + [21:21] + read-write + + + ENABLE_DPO + Enables the single ended receiver on D+. + [28:28] + read-write + + + ENABLE_DMO + Enables the signle ended receiver on D-. + [29:29] + read-write + + + + + USBIO_CTL + USB IO Control Register + 0x8 + 32 + read-write + 0x0 + 0x3F + + + DM_P + The GPIO Drive Mode for DP IO pad. This field only applies if USBIO_CR1.IOMODE =1. Data comes from the corresponding GPIO.DR register. + [2:0] + read-write + + + OFF + Mode 0: Output buffer off (high Z). Input buffer off. + 0 + + + INPUT + Mode 1: Output buffer off (high Z). Input buffer on. + +Other values, not supported. + 1 + + + + + DM_M + The GPIO Drive Mode for DM IO pad. + [5:3] + read-write + + + + + FLOW_CTL + Flow Control Register + 0xC + 32 + read-write + 0x0 + 0xFF + + + EP1_ERR_RESP + End Point 1 error response +0: do nothing (backward compatibility mode) +1: if this is an IN EP and an underflow occurs then cause a CRC error, if this is an OUT EP and an overflow occurs then send a NAK + [0:0] + read-write + + + EP2_ERR_RESP + End Point 2 error response + [1:1] + read-write + + + EP3_ERR_RESP + End Point 3 error response + [2:2] + read-write + + + EP4_ERR_RESP + End Point 4 error response + [3:3] + read-write + + + EP5_ERR_RESP + End Point 5 error response + [4:4] + read-write + + + EP6_ERR_RESP + End Point 6 error response + [5:5] + read-write + + + EP7_ERR_RESP + End Point 7 error response + [6:6] + read-write + + + EP8_ERR_RESP + End Point 8 error response + [7:7] + read-write + + + + + LPM_CTL + LPM Control Register + 0x10 + 32 + read-write + 0x0 + 0x17 + + + LPM_EN + LPM enable +0: Disabled, LPM token will not get a response (backward compatibility mode) +1: Enable, LPM token will get a handshake response (ACK, STALL, NYET or NAK) + A STALL will be sent if the bLinkState is not 0001b + A NYET, NAK or ACK response will be sent depending on the NYET_EN and LPM_ACK_RESP bits below + [0:0] + read-write + + + LPM_ACK_RESP + LPM ACK response enable (if LPM_EN=1), to allow firmware to refuse a low power request +0: a LPM token will get a NYET or NAK (depending on NYET_EN bit below) response and the device will NOT go to a low power mode +1: a LPM token will get an ACK response and the device will go to the requested low power mode + [1:1] + read-write + + + NYET_EN + Allow firmware to choose which response to use for an LPM token (LPM_EN=1) when the device is NOT ready to go to the requested low power mode (LPM_ACK_RESP=0). +0: a LPM token will get an NAK response (indicating a CRC error), the host is expected to repeat the LPM token. +1: a LPM token will get a NYET response + [2:2] + read-write + + + SUB_RESP + Enable a STALL response for all undefined SubPIDs, i.e. other than LPM (0011b). If not enabled then there will be no response (Error) for the undefined SubPIDs. + [4:4] + read-write + + + + + LPM_STAT + LPM Status register + 0x14 + 32 + read-only + 0x0 + 0x1F + + + LPM_BESL + Best Effort Service Latency +This value should match either the Baseline (DeepSleep) or Deep (Hibernate) BESL in the BOS descriptor. + [3:0] + read-only + + + LPM_REMOTEWAKE + 0: Device is prohibited from initiating a remote wake +1: Device is allow to wake the host + [4:4] + read-only + + + + + INTR_SIE + USB SOF, BUS RESET and EP0 Interrupt Status + 0x20 + 32 + read-write + 0x0 + 0x1F + + + SOF_INTR + Interrupt status for USB SOF + [0:0] + read-write + + + BUS_RESET_INTR + Interrupt status for BUS RESET + [1:1] + read-write + + + EP0_INTR + Interrupt status for EP0 + [2:2] + read-write + + + LPM_INTR + Interrupt status for LPM (Link Power Management, L1 entry) + [3:3] + read-write + + + RESUME_INTR + Interrupt status for Resume + [4:4] + read-write + + + + + INTR_SIE_SET + USB SOF, BUS RESET and EP0 Interrupt Set + 0x24 + 32 + read-write + 0x0 + 0x1F + + + SOF_INTR_SET + Write with '1' to set corresponding bit in interrupt request register. + [0:0] + read-write + + + BUS_RESET_INTR_SET + Write with '1' to set corresponding bit in interrupt request register. + [1:1] + read-write + + + EP0_INTR_SET + Write with '1' to set corresponding bit in interrupt request register. + [2:2] + read-write + + + LPM_INTR_SET + Write with '1' to set corresponding bit in interrupt request register. + [3:3] + read-write + + + RESUME_INTR_SET + Write with '1' to set corresponding bit in interrupt request register. + [4:4] + read-write + + + + + INTR_SIE_MASK + USB SOF, BUS RESET and EP0 Interrupt Mask + 0x28 + 32 + read-write + 0x0 + 0x1F + + + SOF_INTR_MASK + Set to 1 to enable interrupt corresponding to interrupt request register + [0:0] + read-write + + + BUS_RESET_INTR_MASK + Set to 1 to enable interrupt corresponding to interrupt request register + [1:1] + read-write + + + EP0_INTR_MASK + Set to 1 to enable interrupt corresponding to interrupt request register + [2:2] + read-write + + + LPM_INTR_MASK + Set to 1 to enable interrupt corresponding to interrupt request register + [3:3] + read-write + + + RESUME_INTR_MASK + Set to 1 to enable interrupt corresponding to interrupt request register + [4:4] + read-write + + + + + INTR_SIE_MASKED + USB SOF, BUS RESET and EP0 Interrupt Masked + 0x2C + 32 + read-only + 0x0 + 0x1F + + + SOF_INTR_MASKED + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + BUS_RESET_INTR_MASKED + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + EP0_INTR_MASKED + Logical and of corresponding request and mask bits. + [2:2] + read-only + + + LPM_INTR_MASKED + Logical and of corresponding request and mask bits. + [3:3] + read-only + + + RESUME_INTR_MASKED + Logical and of corresponding request and mask bits. + [4:4] + read-only + + + + + INTR_LVL_SEL + Select interrupt level for each interrupt source + 0x30 + 32 + read-write + 0x0 + 0xFFFFC3FF + + + SOF_LVL_SEL + USB SOF Interrupt level select + [1:0] + read-write + + + HI + High priority interrupt + 0 + + + MED + Medium priority interrupt + 1 + + + LO + Low priority interrupt + 2 + + + RSVD + illegal + 3 + + + + + BUS_RESET_LVL_SEL + BUS RESET Interrupt level select + [3:2] + read-write + + + EP0_LVL_SEL + EP0 Interrupt level select + [5:4] + read-write + + + LPM_LVL_SEL + LPM Interrupt level select + [7:6] + read-write + + + RESUME_LVL_SEL + Resume Interrupt level select + [9:8] + read-write + + + ARB_EP_LVL_SEL + Arbiter Endpoint Interrupt level select + [15:14] + read-write + + + EP1_LVL_SEL + EP1 Interrupt level select + [17:16] + read-write + + + EP2_LVL_SEL + EP2 Interrupt level select + [19:18] + read-write + + + EP3_LVL_SEL + EP3 Interrupt level select + [21:20] + read-write + + + EP4_LVL_SEL + EP4 Interrupt level select + [23:22] + read-write + + + EP5_LVL_SEL + EP5 Interrupt level select + [25:24] + read-write + + + EP6_LVL_SEL + EP6 Interrupt level select + [27:26] + read-write + + + EP7_LVL_SEL + EP7 Interrupt level select + [29:28] + read-write + + + EP8_LVL_SEL + EP8 Interrupt level select + [31:30] + read-write + + + + + INTR_CAUSE_HI + High priority interrupt Cause register + 0x34 + 32 + read-only + 0x0 + 0xFF9F + + + SOF_INTR + USB SOF Interrupt + [0:0] + read-only + + + BUS_RESET_INTR + BUS RESET Interrupt + [1:1] + read-only + + + EP0_INTR + EP0 Interrupt + [2:2] + read-only + + + LPM_INTR + LPM Interrupt + [3:3] + read-only + + + RESUME_INTR + Resume Interrupt + [4:4] + read-only + + + ARB_EP_INTR + Arbiter Endpoint Interrupt + [7:7] + read-only + + + EP1_INTR + EP1 Interrupt + [8:8] + read-only + + + EP2_INTR + EP2 Interrupt + [9:9] + read-only + + + EP3_INTR + EP3 Interrupt + [10:10] + read-only + + + EP4_INTR + EP4 Interrupt + [11:11] + read-only + + + EP5_INTR + EP5 Interrupt + [12:12] + read-only + + + EP6_INTR + EP6 Interrupt + [13:13] + read-only + + + EP7_INTR + EP7 Interrupt + [14:14] + read-only + + + EP8_INTR + EP8 Interrupt + [15:15] + read-only + + + + + INTR_CAUSE_MED + Medium priority interrupt Cause register + 0x38 + 32 + read-only + 0x0 + 0xFF9F + + + SOF_INTR + USB SOF Interrupt + [0:0] + read-only + + + BUS_RESET_INTR + BUS RESET Interrupt + [1:1] + read-only + + + EP0_INTR + EP0 Interrupt + [2:2] + read-only + + + LPM_INTR + LPM Interrupt + [3:3] + read-only + + + RESUME_INTR + Resume Interrupt + [4:4] + read-only + + + ARB_EP_INTR + Arbiter Endpoint Interrupt + [7:7] + read-only + + + EP1_INTR + EP1 Interrupt + [8:8] + read-only + + + EP2_INTR + EP2 Interrupt + [9:9] + read-only + + + EP3_INTR + EP3 Interrupt + [10:10] + read-only + + + EP4_INTR + EP4 Interrupt + [11:11] + read-only + + + EP5_INTR + EP5 Interrupt + [12:12] + read-only + + + EP6_INTR + EP6 Interrupt + [13:13] + read-only + + + EP7_INTR + EP7 Interrupt + [14:14] + read-only + + + EP8_INTR + EP8 Interrupt + [15:15] + read-only + + + + + INTR_CAUSE_LO + Low priority interrupt Cause register + 0x3C + 32 + read-only + 0x0 + 0xFF9F + + + SOF_INTR + USB SOF Interrupt + [0:0] + read-only + + + BUS_RESET_INTR + BUS RESET Interrupt + [1:1] + read-only + + + EP0_INTR + EP0 Interrupt + [2:2] + read-only + + + LPM_INTR + LPM Interrupt + [3:3] + read-only + + + RESUME_INTR + Resume Interrupt + [4:4] + read-only + + + ARB_EP_INTR + Arbiter Endpoint Interrupt + [7:7] + read-only + + + EP1_INTR + EP1 Interrupt + [8:8] + read-only + + + EP2_INTR + EP2 Interrupt + [9:9] + read-only + + + EP3_INTR + EP3 Interrupt + [10:10] + read-only + + + EP4_INTR + EP4 Interrupt + [11:11] + read-only + + + EP5_INTR + EP5 Interrupt + [12:12] + read-only + + + EP6_INTR + EP6 Interrupt + [13:13] + read-only + + + EP7_INTR + EP7 Interrupt + [14:14] + read-only + + + EP8_INTR + EP8 Interrupt + [15:15] + read-only + + + + + DFT_CTL + DFT control + 0x70 + 32 + read-write + 0x0 + 0x1F + + + DDFT_OUT_SEL + DDFT output select signal + [2:0] + read-write + + + OFF + Nothing connected, output 0 + 0 + + + DP_SE + Single Ended output of DP + 1 + + + DM_SE + Single Ended output of DM + 2 + + + TXOE + Output Enable + 3 + + + RCV_DF + Differential Receiver output + 4 + + + GPIO_DP_OUT + GPIO output of DP + 5 + + + GPIO_DM_OUT + GPIO output of DM + 6 + + + + + DDFT_IN_SEL + DDFT input select signal + [4:3] + read-write + + + OFF + Nothing connected, output 0 + 0 + + + GPIO_DP_IN + GPIO input of DP + 1 + + + GPIO_DM_IN + GPIO input of DM + 2 + + + + + + + + USBHOST + USB Host Controller + 0x00004000 + + HOST_CTL0 + Host Control 0 Register. + 0x0 + 32 + read-write + 0x0 + 0x80000001 + + + HOST + This bit selects an operating mode of this IP. +'0' : USB Device +'1' : USB Host +Notes: +- The operation mode does not transition to the required one immediately after it was changed using this bit. Read this bit to check that the operation mode has changed. +- This bit is initialized if ENABLE bit of the Host Control 0 Register (HOST_CTL0) changes from '1' to '0'.. +- Before changing from the USB Host to the USB Device, check that the following conditions are satisfied and also set the RST bit of the Host Control 1 Register (HOST_CTL1). to '1'. + * The SOFBUSY bit of the Host Status Register (HOST_STATUS) is set to '0'. + * The TKNEN bits of the Host Token Endpoint Register (HOST_TOKEN) is set to '000'. + * The SUSP bit of the Host Status Register (HOST_STATUS) is set to '0'. + [0:0] + read-write + + + ENABLE + This bit enables the operation of this IP. +'0' : Disable USB Host +'1' : Enable USB Host +Note: +- This bit doesn' affect the USB Device. + [31:31] + read-write + + + + + HOST_CTL1 + Host Control 1 Register. + 0x10 + 32 + read-write + 0x83 + 0x83 + + + CLKSEL + This bit selects the operating clock of USB Host. +'0' : Low-speed clock +'1' : Full-speed clock +Notes: +- This bit is initialized if ENABLE bit of the Host Control 0 Register (HOST_CTL0) changes from '1' to '0'. +- This bit must always be set to '1' in the USB Device mode. + [0:0] + read-write + + + USTP + This bit stops the clock for the USB Host operating unit. When this bit is '1', power consumption can be reduced by configuring this bit. +'0' : Normal mode. +'1' : Stops the clock for the USB Host operating unit. +Notes: +- If this bit is set to '1', the function of USB Host can't be used because internal clock is stopped. +- This bit is initialized if ENABLE bit of the Host Control 0 Register (HOST_CTL0) changes from '1' to '0'. + [1:1] + read-write + + + RST + This bit resets this IP. +'0' : Releases the reset for USB Host. +'1' : Resets USB Host. +Notes: +- This bit is initialized if ENABLE bit of the Host Control 0 Register changes from '1' to '0'. +- If this bit is set to '1', both the BFINI bits of the Host Endpoint 1 Control Register (HOST_EP1_CTL) and Host Endpoint 2 Control Register (HOST_EP2_CTL) are set to '1'. + [7:7] + read-write + + + + + HOST_CTL2 + Host Control 2 Register. + 0x100 + 32 + read-write + 0x1 + 0xFF + + + RETRY + If this bit is set to '1', the target token is retried if a NAK or error* occurs. Retry processing is performed during the time that is specified in the Host Retry Timer Setup Register (HOST_RTIMER). +* : HOST_ERR.RERR='1', HOST_ERR.TOUT='1', HOST_ERR.CRC='1', HOST_ERR.TGERR='1', HOST_ERR.STUFF='1' +'0' : Doesn't retry token sending. +'1' : Retries token sending +Note: +- This bit isn't initialized even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [0:0] + read-write + + + CANCEL + When this bit is set to '1', if the target token is written to the Host Token Endpoint Register (HOST_TOKEN) in the EOF area (specified in the Host EOF Setup Register), its sending is canceled. When this bit is set to '0', token sending is not canceled even if the target token is written to the register. The cancellation of token sending is detected by reading the TCAN bit of the Interrupt USB Host Register (INTR_USBHOST). +'0' : Continues a token. +'1' : Cancels a token. + [1:1] + read-write + + + SOFSTEP + If this bit is set to '1', the SOF interrupt flag (INTR_USBHOST.SOFIRQ) is set to '1' each time SOF is sent. +If this bit is set to '0', the set value of the Host SOF Interrupt Frame Compare Register (HOST_FCOMP) is compared with the low-order eight bits of the SOF frame number. If they match, the SOF interrupt flag (INTR_USBHOST.SOFIRQ) is set to '1'. +'0' : An interrupt occurred due to the HOST_HFCOMP setting. +'1' : An interrupt occurred. +Notes: +- If a SOF token (TKNEN='001') is sent by the setting of the Host Token Endpoint Register (HOST_TOKEN), the SOF interrupt flag (INTR_USBHOST.SOFIRQ) is not set to '1' regardless of the setting of this bit. + [2:2] + read-write + + + ALIVE + This bit is used to specify the keep-alive function in the low-speed mode. If this bit it set to '1' while the CLKSEL bit of the Host Control 1 Register (HOST_CTL1) is '0', SE0 is output instead of SOF. This bit is effective when the CLKSEL bit of the Host Conrtol 1 Register (HOST_CTL1) is '0'. If the CLKSEL bit is '1', SOF is output regardless of the setting of the ALIVE bit. +'0' : SOF output. +'1' : SE0 output (Keep alive) + [3:3] + read-write + + + RSVD_4 + N/A + [4:4] + read-write + + + RSVD_5 + N/A + [5:5] + read-write + + + TTEST + Timer Test. Set this bits to '00'. + [7:6] + read-write + + + + + HOST_ERR + Host Error Status Register. + 0x104 + 32 + read-write + 0x3 + 0xFF + + + HS + These flags indicate the status of a handshake packet to be sent or received. +These flags are set to 'NULL' when no handshake occurs due to an error or when a SOF token has been ended with the TKNEN bit of the Host Token Endpoint Register (HOST_TOKEN). +These bits are updated when sending or receiving has been ended. +HS bits change values '11' under the following condition. However, if HS bits are written except the following conditions, the values are ignored. +- HS bits indicate values except '11' and write the value '11' to HS bits. +Note: +This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [1:0] + read-write + + + ACK + Acknowledge Packet + 0 + + + NAK + Non-Acknowledge Packet + 1 + + + STALL + Stall Packet + 2 + + + NULL + Null Packet + 3 + + + + + STUFF + If this bit is set to '1', it means that a bit stuffing error is detected. When this bit is '0', it means that no stuffing error is detected. If a stuffing error is detected, bit5 (Timeout) of this register is also set to '1'. If this bit is written with '1', it is set to '0'. However, if this bit is written with '0', its value is ignored. +'0' : No stuffing error. +'1' : Stuffing error occurs. +Note: +- This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [2:2] + read-write + + + TGERR + If this bit is set to '1', it means that the data of this bit does not match the value of the received toggle data. When this bit is '0', it means that no toggle error is detected. If this bit is written with '1', it is set to '0'. However, if this bit is written with '0', its value is ignored. +'0' : No toggle error. +'1' : Toggle error occurs. +Note: +- This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [3:3] + read-write + + + CRC + If this bit is set to '1', it means that a CRC error is detected in the USB Host. When this bit is '0', it means that no CRC error is detected. If a CRC error is detected, bit5 (Timeout) of this register is also set to '1'. When this bit is '0', it means that no CRC error is detected. If this bit is written with '1', it is set to '0'. However, if this bit is written with '0', its value is ignored. +'0' : No CRC error. +'1' : CRC error occurs. +Note: +- This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [4:4] + read-write + + + TOUT + If this bit is set to '1', it means that no response is returned from the device within the specified time after a token has been sent in the USB Host. When this bit is '0', it means that no timeout is detected. When this bit is '0', it means that no error occurs. If this bit is written with '1', it is set to '0'. However, if this bit is written with '0', its value is ignored. +'0' : No timeout. +'1' : Timeout occurs. +Note: +- This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [5:5] + read-write + + + RERR + When this bit is set to '1', it means that the received data exceeds the specified maximum number of packets in the USB Host. If a receive error is detected, bit5 (Timeout) of this register is also set to '1'. When this bit is '0', it means that no error occurs. If this bit is written with '1', it is set to '0'. However, if this bit is written with '0', its value is ignored. +'0' : No receive error. +'1' : Maximum packet receive error. +- This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [6:6] + read-write + + + LSTSOF + If this bit is set to '1', it means that the SOF token can't be sent in the USB Host because other token is in process. When this bit is '0', it means that no lost SOF error is detected. If this bit is written with '1', it is set to '0'. However, if this bit is written with '0', its value is ignored. +'0' : Sends SOF. +'1' : SOF sending error. +Note: +- This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [7:7] + read-write + + + + + HOST_STATUS + Host Status Register. + 0x108 + 32 + read-write + 0xC2 + 0x1FF + + + CSTAT + When this bit is '1', it means that the device is connected. When this bit is '0', it means that the device is disconnected. +'0' : Device is disconnected. +'1' : Device is connected. +Notes: +- This bit is initialized if the RST bit of the Host Control 1 Register (Host_CTL1) is set to '1'. +- This bit takes time to be initialized by the RST bit of the Host Control 1 Resgiter (HOST_CTL1). + [0:0] + read-only + + + TMODE + If this bit is '1', it means that the device is connected in the full-speed mode. When this bit is '0', it means that the device is connected in the low-speed mode. This bit is valid when the CSTAT bit of the Host Status Register (HOST_STATUS) is '1'. +'0' : Low-speed. +'1' : Full-speed. +Notes: +- This bit is initialized if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. +- This bit takes time to be initialized by the RST bit of the Host Control 1 Resgiter (HOST_CTL1). + [1:1] + read-only + + + SUSP + If this bit is set to '1', the USB Host is placed into the suspend state. If this bit is set to '0' while it is '1' or the USB bus is placed into the k-state mode, the suspend state is released, and the RWIRQ bit of the Interrupt USB Host Register (INTR_USBHOST) is set to '1'. +Set to '1' : Suspend. +Set '0' while this bit is '1' : Resume. +Others : Holds the status. +Notes: +- This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. +- This bit takes time to be initialized by the RST bit of the Host Control 1 Resgiter (HOST_CTL1). +- If this bit is set to '1', this bit must not be set to '1' until the RWIRQ bit of the Interrupt USB Host Register (INTR_USBHOST) is set to '1'. +- Do not set this bit to '1' while the USB is active (during USB bus resetting, data transfer, or SOF timer running). +- If the value of this bit is changed, it is not immediately reflected on the state of the USB bus. To check whether or not the state is updated, read this bit. + [2:2] + read-write + + + SOFBUSY + When a SOF token is sent using the Host Token Endpoint Register (HOST_TOKEN), this bit is set to '1', which means that the SOF timer is active. When this bit is '0', it means that the SOF timer is under suspension. To stop the active SOF timer, write '0' to this bit. However, if this bit is written with '1', its value is ignored. +'0' : The SOF timer is stopped. +'1' : The SOF timer is active. +Notes: +- This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. +- This bit takes time to be initialized by the RST bit of the Host Control 1 Resgiter (HOST_CTL1). +- The SOF timer does not stop immediately after this bit has been set to '0' to stop the SOF timer. To check whether or not the SOF timer is stopped, read this bit. + [3:3] + read-write + + + URST + When this bit is set to '1', the USB bus is reset. This bit continues set to '1' during USB bus resetting, and changes to '0' when USB bus resetting is ended. If this bit is set to '0', no processing is performed. + [4:4] + read-write + + + RSVD_5 + N/A + [5:5] + read-only + + + RSTBUSY + This bit shows that USB Host is being reset internally. If the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1', this bit is set to '1'. +If the RST bit of Host Control 1 Register (HOST_CTL1) is set to '0', this bit is set to '0'. +'0' : USB Host isn't being reset. +'1' : USB Host is being reset. +Notes: +- If this bit is '1', the token must't be executed. +- This bit isn't set to '0' or '1' immediately evne if the RST bit of Host Control 1 Register (HOST_CTL1) is set to '0' or '1'. + [6:6] + read-only + + + CLKSEL_ST + This bit shows whether it is full-speed or not. If the CLKSEL bit of the Host Control 1 Register (HOST_CTL1) is set to '1', this bit is set to '1'. +'0' : Low speed +'1' : Full speed +Note: +- If this bit is different from the CLKSEL bit, The execution of the token and bus reset must be waited until the match. +- This bit takes time to be initialized by the RST bit of the Host Control 1 Resgiter (HOST_CTL1). + [7:7] + read-only + + + HOST_ST + This bit shows whether it is USB Host mode. If the HOST bit of the Host Control Register (HOST_CTL0) is set to '1', this bit is set to '1'. +'0' : USB Device +'1' : USB Host +Notes: +- If this bit is different from the CLKSEL bit, The execution of the token must be waited until the match. +- This bit takes time to be initialized by the RST bit of the Host Control 1 Resgiter (HOST_CTL1). + [8:8] + read-only + + + + + HOST_FCOMP + Host SOF Interrupt Frame Compare Register + 0x10C + 32 + read-write + 0x0 + 0xFF + + + FRAMECOMP + These bits are used to specify the data to be compared with the low-order eight bits of a frame number when sending a SOF token. +If the SOFSTEP bit of Host Control 2 Register (HOST_CTL2) is '0', the frame number of SOF is compared with the value of this register when sending a SOF token. If they match, the SOFIRQ bit of the Interrupt USB Host Register (INTR_USBHOST) is set to '1'. +The setting of this register is invalid when the SOFSTEP bit of Host Control 2 Register (HOST_CTL2) is '1'. +Note: +- This bit is not initialized even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [7:0] + read-write + + + + + HOST_RTIMER + Host Retry Timer Setup Register + 0x110 + 32 + read-write + 0x0 + 0x3FFFF + + + RTIMER + These bits are used to specify the retry time in this register. The retry timer is activated when token sending starts while the RETRY bit of Host Control 2 Register (HOST_CTL2) is '1'. The retry time is then decremented by one when a 1-bit transfer clock (12 MHz in the full-speed mode) is output. When the retry timer reaches 0, the target token is sent, and processing is ended. +If a token retry occurs in the EOF area, the retry timer is stopped until SOF sending is ended. After SOF sending has been completed, the retry timer restarts with the value that is set when the timer stopped. + [17:0] + read-write + + + + + HOST_ADDR + Host Address Register + 0x114 + 32 + read-write + 0x0 + 0x7F + + + ADDRESS + These bits are used to specify a token address. +Note: +- This bit is not initialized even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [6:0] + read-write + + + + + HOST_EOF + Host EOF Setup Register + 0x118 + 32 + read-write + 0x0 + 0x3FFF + + + EOF + These bits are used to specify the time to disable token sending before transferring SOF. Specify the time with a margin, which is longer than the one-packet length. The time unit is the 1-bit transfer time. +Setting example: MAXPKT = 64 bytes, full-speed mode + (Token_length + packet_length + header + CRC)*7/6 + Turn_around_time + =(34 bit + 546 bit)*7/6 + 36 bit = 712.7 bit + Therefore, set 0x2C9. +Note: +- This bit is not initialized even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [13:0] + read-write + + + + + HOST_FRAME + Host Frame Setup Register + 0x11C + 32 + read-write + 0x0 + 0x7FF + + + FRAME + These bits are used to specify a frame number of SOF. +Notes: +- This bit isn't initialized even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. +- Specify a frame number in this register before setting SOF in the TKNEN bit of the Host Token Endpoint Register (HOST_TOKEN). +- This register cannot be written while the SOFBUSY bit of the Host Status Register (HOST_STATUS) is '1' and a SOF token is in process. + [10:0] + read-write + + + + + HOST_TOKEN + Host Token Endpoint Register + 0x120 + 32 + read-write + 0x0 + 0x17F + + + ENDPT + These bits are used to specify an endpoint to send or receive data to or from the device. +Note: +- This bit isn't initialized even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [3:0] + read-write + + + TKNEN + These bits send a token according to the settings. After operation has been ended, the TKNEN bit is set to '000', and the CMPIRQ bit of the Interrupt USB Host Register (INTR_USBHOST) is set to '1'. +The settings of the TGGL and ENDPT bits are ignored when sending a SOF token. +Notes: +- This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. +- The PRE packet isn't supported. +- Do not set '100' to the TKNEN bit when the SOFBUSY bit of the Host Status Register (HOST_STATUS) is '1' +- Change the USB to the USB Host before writing data to this bit. +- When issuing a token again after the token interrupt flag (CMPIRQ) has been set to '1', wait for 3 cycles or more after a USB transfer clock (12 MHz in the full-speed mode, 1.5 MHz in the low-speed mode) was output, then write data to this bit. +- Read the value of TKNEN bit if a new value is written in it .Continue writing in this bit until a retrieved value equals a new value written in. During this checking process, it is needed to prevent any interrupt. +- Take the following steps when CMPIRQ bit of Interrupt USB Host Register (INTR_USBHOST) is set to '1' by finishing IN token or Isochronous IN token. +1. Read HS bit of Host Error Status Register (HOST_ERR), then set CMPIRQ bit to '0'. +2. Set EPn bit of Host DMA Enable Register (HOST_DMA_ENBL) (n=1 or 2) to '1' if HS bit of Host Error Status Register (HOST_ERR) is equal to '00' and wait until EPn bit of Host DMA Data Request Register (HOST_DMA_DREQ) changes to '1'. Finish the IN token processing if HS bit is not equal to '00'. +3. Read the received data if EPn bit of Host DMA Data Requet (HOST_DMA_DREQ) (n=1 or 2) changes to '1'. + [6:4] + read-write + + + NONE + Sends no data. + 0 + + + SETUP + Sends SETUP token. + 1 + + + IN + Sends IN token. + 2 + + + OUT + Sends OUT token. + 3 + + + SOF + Sends SOF token. + 4 + + + ISO_IN + Sends Isochronous IN. + 5 + + + ISO_OUT + Sends Isochronous OUT. + 6 + + + RSV + N/A + 7 + + + + + TGGL + This bit is used to set toggle data. Toggle data is sent depending on the setting of this bit. When receiving toggle data, received toggle data is compared with the toggle data of this bit to verify whether or not an error occurs. +'0' : DATA0 +'1' : DATA1 +Notes: +- This bit isn't initialized even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. +- Set this bit when the TKNEN bit of the Host Token Endpoint Register (HOST_TOKEN) is '000'. + [8:8] + read-write + + + + + HOST_EP1_CTL + Host Endpoint 1 Control Register + 0x400 + 32 + read-write + 0x8100 + 0x9DFF + + + PKS1 + This bit specifies the maximum size transferred by one packet. The configurable range is from 0x001 to 0x100. +- If automatic buffer transfer mode (DMEA='1') is used, this Endpoint must not set from 0 to 2. + [8:0] + read-write + + + NULLE + When a data transfer request in OUT the direction is transmitted while automatic buffer transfer mode is set (DMAE = 1), this bit sets a mode that transfers 0-byte data automatically upon the detection of the last packet transfer. +'0' : Releases the NULL automatic transfer mode. +'1' : Sets the NULL automatic transfer mode. +Note : +- For data transfer in the IN direction or when automatic buffer transfer mode is not set, the NULL bit configuration does not affect communication. + [10:10] + read-write + + + DMAE + This bit sets a mode that uses DMA for writing or reading transfer data to/from send/receive buffer, and automatically transfers the send/receive data synchronized with an data request in the IN or OUT direction. Until the data size set in the DMA is reached, the data is transferred. +'0' : Releases the automatic buffer transfer mode. +'1' : Sets the automatic buffer transfer mode. +Note : +- The CPU must not access the send/receive buffer while the DMAE bit is set to '1'. For data transfer in the IN direction, set the DMA transfer size to the multiples of that set in PKS bits of the Host EP1 Control Register (HOST_EP1_CTL) and Host EP2 Control Register (HOST_EP2_CTR). + [11:11] + read-write + + + DIR + This bit specifies the transfer direction the Endpoint support. +'0' : IN Endpoint. +'1' : OUT Endpoint +Note: +- This bit must be changed when INI_ST bit of the Host Endpoint 1 Status Register (HOST_EP1_STATUS) is '1'. + [12:12] + read-write + + + BFINI + This bit initializes the send/receive buffer of transfer data. The BFINI bit is also automatically set by setting the RST bit of the HOST Control 1 Register (HOST_CTL1). If the RST bit was used for resetting, therefore, set the RST bit to '0' before clearing the BFINI bit. +'0' : Clears the initialization. +'1' : Initializes the send/receive buffer +Note : +- The EP1 buffer has a double-buffer configuration. The BFINI bit initialization initializes the double buffers concurrently and also initializes the EP1DRQ and EP1SPK bits. + [15:15] + read-write + + + + + HOST_EP1_STATUS + Host Endpoint 1 Status Register + 0x404 + 32 + read-only + 0x60000 + 0x70000 + + + SIZE1 + These bits indicate the number of data bytes written to the receive buffer when IN packet transfer of EP1 has finished. +The indication range is from 0x000 to 0x100. +Note : +- These bits are set to the data size transferred in the IN direction and written to the buffer. Therefore, a value read during transfer in the OUT direction has no effect. + [8:0] + read-only + + + VAL_DATA + This bit shows that there is valid data in the EP1 buffer. +'0' : Invalid data in the buffer +'1' : Valid data in the buffer + [16:16] + read-only + + + INI_ST + This bit shows that EP1 is initialized. If the init bit of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is set to '1' and EP1 is initialized, this bit is to '1'. +'0' : Release of the initialization +'1' : Initialization +Note: +- This bit isn't set to '0' or '1' immediately evne if BFINI bit of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is set to '0' or '1'. + [17:17] + read-only + + + RSVD_18 + N/A + [18:18] + read-only + + + + + HOST_EP1_RW1_DR + Host Endpoint 1 Data 1-Byte Register + 0x408 + 32 + read-write + 0x0 + 0xFF + + + BFDT8 + Data Register for EP1. The 1-Byte data is valid. + [7:0] + read-write + + + + + HOST_EP1_RW2_DR + Host Endpoint 1 Data 2-Byte Register + 0x40C + 32 + read-write + 0x0 + 0xFFFF + + + BFDT16 + Data Register for EP1. The 2-Byte data is valid. + [15:0] + read-write + + + + + HOST_EP2_CTL + Host Endpoint 2 Control Register + 0x500 + 32 + read-write + 0x8040 + 0x9C7F + + + PKS2 + This bit specifies the maximum size transferred by one packet. The configurable range is from 0x001 to 0x40. +- If automatic buffer transfer mode (DMEA='1') is used, this Endpoint must not set from 0 to 2. + [6:0] + read-write + + + NULLE + When a data transfer request in OUT the direction is transmitted while automatic buffer transfer mode is set (DMAE = 1), this bit sets a mode that transfers 0-byte data automatically upon the detection of the last packet transfer. +'0' : Releases the NULL automatic transfer mode. +'1' : Sets the NULL automatic transfer mode. +Note : +- For data transfer in the IN direction or when automatic buffer transfer mode is not set, the NULL bit configuration does not affect communication. + [10:10] + read-write + + + DMAE + This bit sets a mode that uses DMA for writing or reading transfer data to/from send/receive buffer, and automatically transfers the send/receive data synchronized with an data request in the IN or OUT direction. Until the data size set in the DMA is reached, the data is transferred. +'0' : Releases the automatic buffer transfer mode. +'1' : Sets the automatic buffer transfer mode. +Note : +- The CPU must not access the send/receive buffer while the DMAE bit is set to '1'. For data transfer in the IN direction, set the DMA transfer size to the multiples of that set in PKS bits of the Host EP1 Control Register (HOST_EP1_CTL) and Host EP2 Control Register (HOST_EP2_CTR). + [11:11] + read-write + + + DIR + This bit specifies the transfer direction the Endpoint support. +'0' : IN Endpoint. +'1' : OUT Endpoint +Note: +- This bit must be changed when INI_ST bit of the Host Endpoint 2 Status Register (HOST_EP2_STATUS) is '1'. + [12:12] + read-write + + + BFINI + This bit initializes the send/receive buffer of transfer data. The BFINI bit is also automatically set by setting the RST bit of the HOST Control 1 Register (HOST_CTL1). If the RST bit was used for resetting, therefore, set the RST bit to '0' before clearing the BFINI bit. +'0' : Clears the initialization. +'1' : Initializes the send/receive buffer +Note : +- The EP2 buffer has a double-buffer configuration. The BFINI bit initialization initializes the double buffers concurrently and also initializes the EP2DRQ and EP2SPK bits. + [15:15] + read-write + + + + + HOST_EP2_STATUS + Host Endpoint 2 Status Register + 0x504 + 32 + read-only + 0x60000 + 0x70000 + + + SIZE2 + These bits indicate the number of data bytes written to the receive buffer when IN packet transfer of EP2 has finished. +The indication range is from 0x000 to 0x40. +Note : +- These bits are set to the data size transferred in the IN direction and written to the buffer. Therefore, a value read during transfer in the OUT direction has no effect. + [6:0] + read-only + + + VAL_DATA + This bit shows that there is valid data in the EP2 buffer. +'0' : Invalid data in the buffer +'1' : Valid data in the buffer + [16:16] + read-only + + + INI_ST + This bit shows that EP2 is initialized. If the BFINI bit of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is set to '1' and EP2 is initialized, this bit is to '1'. +'0' : Release of the initialization +'1' : Initialization +Note: +- This bit isn't set to '0' or '1' immediately evne if BFINI bit of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is set to '0' or '1'. + [17:17] + read-only + + + RSVD_18 + N/A + [18:18] + read-only + + + + + HOST_EP2_RW1_DR + Host Endpoint 2 Data 1-Byte Register + 0x508 + 32 + read-write + 0x0 + 0xFF + + + BFDT8 + Data Register for EP2. The 1-Byte data is valid. + [7:0] + read-write + + + + + HOST_EP2_RW2_DR + Host Endpoint 2 Data 2-Byte Register + 0x50C + 32 + read-write + 0x0 + 0xFFFF + + + BFDT16 + Data Register for EP2. The 2-Byte data is valid. + [15:0] + read-write + + + + + HOST_LVL1_SEL + Host Interrupt Level 1 Selection Register + 0x800 + 32 + read-write + 0x0 + 0xFFFF + + + SOFIRQ_SEL + These bits assign SOFIRQ interrupt flag to any interrupt signals. + [1:0] + read-write + + + HI + High priority interrupt + 0 + + + MED + Medium priority interrupt + 1 + + + LO + Low priority interrupt + 2 + + + RSVD + illegal + 3 + + + + + DIRQ_SEL + These bits assign DIRQ interrupt flag to any interrupt signals. + [3:2] + read-write + + + CNNIRQ_SEL + These bits assign CNNIRQ interrupt flag to any interrupt signals. + [5:4] + read-write + + + CMPIRQ_SEL + These bits assign URIRQ interrupt flag to any interrupt signals. + [7:6] + read-write + + + URIRQ_SEL + These bits assign URIRQ interrupt flag to any interrupt signals. + [9:8] + read-write + + + RWKIRQ_SEL + These bits assign RWKIRQ interrupt flag to any interrupt signals. + [11:10] + read-write + + + RSVD_13_12 + N/A + [13:12] + read-write + + + TCAN_SEL + These bits assign TCAN interrupt flag to any interrupt signals. + [15:14] + read-write + + + + + HOST_LVL2_SEL + Host Interrupt Level 2 Selection Register + 0x804 + 32 + read-write + 0x0 + 0xFF0 + + + EP1_DRQ_SEL + These bits assign EP1_DRQ interrupt flag to any interrupt signals. + [5:4] + read-write + + + HI + High priority interrupt + 0 + + + MED + Medium priority interrupt + 1 + + + LO + Low priority interrupt + 2 + + + RSVD + illegal + 3 + + + + + EP1_SPK_SEL + These bits assign EP1_SPK interrupt flag to any interrupt signals. + [7:6] + read-write + + + EP2_DRQ_SEL + These bits assign EP2_DRQ interrupt flag to any interrupt signals. + [9:8] + read-write + + + EP2_SPK_SEL + These bits assign EP2_SPK interrupt flag to any interrupt signals. + [11:10] + read-write + + + + + INTR_USBHOST_CAUSE_HI + Interrupt USB Host Cause High Register + 0x900 + 32 + read-only + 0x0 + 0xFF + + + SOFIRQ_INT + SOFIRQ interrupt + [0:0] + read-only + + + DIRQ_INT + DIRQ interrupt + [1:1] + read-only + + + CNNIRQ_INT + CNNIRQ interrupt + [2:2] + read-only + + + CMPIRQ_INT + CMPIRQ interrupt + [3:3] + read-only + + + URIRQ_INT + URIRQ interrupt + [4:4] + read-only + + + RWKIRQ_INT + RWKIRQ interrupt + [5:5] + read-only + + + RSVD_6 + N/A + [6:6] + read-only + + + TCAN_INT + TCAN interrupt + [7:7] + read-only + + + + + INTR_USBHOST_CAUSE_MED + Interrupt USB Host Cause Medium Register + 0x904 + 32 + read-only + 0x0 + 0xFF + + + SOFIRQ_INT + SOFIRQ interrupt + [0:0] + read-only + + + DIRQ_INT + DIRQ interrupt + [1:1] + read-only + + + CNNIRQ_INT + CNNIRQ interrupt + [2:2] + read-only + + + CMPIRQ_INT + CMPIRQ interrupt + [3:3] + read-only + + + URIRQ_INT + URIRQ interrupt + [4:4] + read-only + + + RWKIRQ_INT + RWKIRQ interrupt + [5:5] + read-only + + + RSVD_6 + N/A + [6:6] + read-only + + + TCAN_INT + TCAN interrupt + [7:7] + read-only + + + + + INTR_USBHOST_CAUSE_LO + Interrupt USB Host Cause Low Register + 0x908 + 32 + read-only + 0x0 + 0xFF + + + SOFIRQ_INT + SOFIRQ interrupt + [0:0] + read-only + + + DIRQ_INT + DIRQ interrupt + [1:1] + read-only + + + CNNIRQ_INT + CNNIRQ interrupt + [2:2] + read-only + + + CMPIRQ_INT + CMPIRQ interrupt + [3:3] + read-only + + + URIRQ_INT + URIRQ interrupt + [4:4] + read-only + + + RWKIRQ_INT + RWKIRQ interrupt + [5:5] + read-only + + + RSVD_6 + N/A + [6:6] + read-only + + + TCAN_INT + TCAN interrupt + [7:7] + read-only + + + + + INTR_HOST_EP_CAUSE_HI + Interrupt USB Host Endpoint Cause High Register + 0x920 + 32 + read-only + 0x0 + 0x3C + + + EP1DRQ_INT + EP1DRQ interrupt + [2:2] + read-only + + + EP1SPK_INT + EP1SPK interrupt + [3:3] + read-only + + + EP2DRQ_INT + EP2DRQ interrupt + [4:4] + read-only + + + EP2SPK_INT + EP2SPK interrupt + [5:5] + read-only + + + + + INTR_HOST_EP_CAUSE_MED + Interrupt USB Host Endpoint Cause Medium Register + 0x924 + 32 + read-only + 0x0 + 0x3C + + + EP1DRQ_INT + EP1DRQ interrupt + [2:2] + read-only + + + EP1SPK_INT + EP1SPK interrupt + [3:3] + read-only + + + EP2DRQ_INT + EP2DRQ interrupt + [4:4] + read-only + + + EP2SPK_INT + EP2SPK interrupt + [5:5] + read-only + + + + + INTR_HOST_EP_CAUSE_LO + Interrupt USB Host Endpoint Cause Low Register + 0x928 + 32 + read-only + 0x0 + 0x3C + + + EP1DRQ_INT + EP1DRQ interrupt + [2:2] + read-only + + + EP1SPK_INT + EP1SPK interrupt + [3:3] + read-only + + + EP2DRQ_INT + EP2DRQ interrupt + [4:4] + read-only + + + EP2SPK_INT + EP2SPK interrupt + [5:5] + read-only + + + + + INTR_USBHOST + Interrupt USB Host Register + 0x940 + 32 + read-write + 0x0 + 0xFF + + + SOFIRQ + If this bit is set to '1', it means that SOF token sending is started. When this bit is '0', it has no meaning. If this bit is written with '1', it is set to '0'. However, if this bit is written with '0', its value is ignored. +'0' : Does not issue an interrupt request by starting a SOF token. +'1' : Issues an interrupt request by starting a SOF token. +Note : +- This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [0:0] + read-write + + + DIRQ + If this bit is set to '1', it means that a device disconnection is detected. When this bit is '0', it has no meaning. If this bit is written with '1', it is set to '0'. However, if this bit is written with '0', its value is ignored. +'0' : Issues no interrupt request by detecting a device disconnection. +'1' : Issues an interrupt request by detecting a device disconnection. +Note : +- This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [1:1] + read-write + + + CNNIRQ + If this bit is set to '1', it means that a device connection is detected. When this bit is '0', it has no meaning. If this bit is written with '1', it is set to '0'. However, if this bit is written with '0', its value is ignored. +'0' : Issues no interrupt request by detecting a device connection. +'1' : Issues an interrupt request by detecting a device connection. +Note : +- This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [2:2] + read-write + + + CMPIRQ + If this bit is set to '1', it means that a token is completed. When this bit is '0', it has no meaning. If this bit is written with '1', it is set to '0'. However, if this bit is written with '0', its value is ignored. +'0' : Issues no interrupt request by token completion. +'1' : Issues an interrupt request by token completion. +Note : +- This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. +- This bit is not set to '1' even if the TCAN bit of the Interrupt USBHost Register (INTR_USBHOST) changes to '1'. +- Take the following steps when this bit is set to '1' by finishing IN token or Isochronous IN token. +1. Read HS bit of Host Error Status Register (HOST_ERR), then set CMPIRQ bit to '0'. +2. Set EPn bit of Host DMA Enable Register (HOST_DMA_ENBL) (n=1 or 2) to '1' if HS bit of Host Error Status Register (HOST_ERR) is equal to '00' and wait until EPn bit of Host DMA Data Request Register (HOST_DMA_DREQ) changes to '1'. Finish the IN token processing if HS bit is not equal to '00'. +3. Read the received data if EPn bit of Host DMA Data Requet (HOST_DMA_DREQ) (n=1 or 2) changes to '1'. + [3:3] + read-write + + + URIRQ + If this bit is set to '1', it means that USB bus resetting is ended. When this bit is '0', it has no meaning. If this bit is written with '1', it is set to '0'. However, if this bit is written with '0', its value is ignored. +'0' : Issues no interrupt request by USB bus resetting. +'1' : Issues an interrupt request by USB bus resetting. +Note : +- This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [4:4] + read-write + + + RWKIRQ + If this bit is set to '1', it means that remote Wake-up is ended. When this bit is '0', it has no meaning. If this bit is written with '1', it is set to '0'. However, if this bit is written with '0', its value is ignored. +'0' : Issues no interrupt request by restart. +'1' : Issues an interrupt request by restart. +Note : +- This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [5:5] + read-write + + + RSVD_6 + N/A + [6:6] + read-write + + + TCAN + If this bit is set to '1', it means that token sending is canceled based on the setting of the CANCEL bit of Host Control 2 Register (HOST_CTL2). When this bit is '0', it means that token sending is not canceled. If this bit is written with '1', it is set to '0'. However, if this bit is written with '0', its value is ignored. +'0' : Does not cancel token sending. +'1' : Cancels token sending. +Note : +- This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. + [7:7] + read-write + + + + + INTR_USBHOST_SET + Interrupt USB Host Set Register + 0x944 + 32 + read-write + 0x0 + 0xFF + + + SOFIRQS + This bit sets SOFIRQ bit. If this bit is written to '1', SOFIRQ is set to '1'. However, if this bit is written with '0', its value is ignored. + [0:0] + read-write + + + DIRQS + This bit sets DIRQ bit. If this bit is written to '1', DIRQ is set to '1'. However, if this bit is written with '0', its value is ignored. + [1:1] + read-write + + + CNNIRQS + This bit sets CNNIRQ bit. If this bit is written to '1', CNNIRQ is set to '1'. However, if this bit is written with '0', its value is ignored. + [2:2] + read-write + + + CMPIRQS + This bit sets CMPIRQ bit. If this bit is written to '1', CMPIRQ is set to '1'. However, if this bit is written with '0', its value is ignored. + [3:3] + read-write + + + URIRQS + This bit sets URIRQ bit. If this bit is written to '1', URIRQ is set to '1'. However, if this bit is written with '0', its value is ignored. + [4:4] + read-write + + + RWKIRQS + This bit sets RWKIRQ bit. If this bit is written to '1', RWKIRQ is set to '1'. However, if this bit is written with '0', its value is ignored. + [5:5] + read-write + + + RSVD_6 + BCNFTEST interrupt. This bit is test bit + [6:6] + read-write + + + TCANS + This bit sets TCAN bit. If this bit is written to '1', TCAN is set to '1'. However, if this bit is written with '0', its value is ignored. + [7:7] + read-write + + + + + INTR_USBHOST_MASK + Interrupt USB Host Mask Register + 0x948 + 32 + read-write + 0x0 + 0xFF + + + SOFIRQM + This bit masks the interrupt by SOF flag. +'0' : Disables +'1' : Enables + [0:0] + read-write + + + DIRQM + This bit masks the interrupt by DIRQ flag. +'0' : Disables +'1' : Enables + [1:1] + read-write + + + CNNIRQM + This bit masks the interrupt by CNNIRQ flag. +'0' : Disables +'1' : Enables + [2:2] + read-write + + + CMPIRQM + This bit masks the interrupt by CMPIRQ flag. +'0' : Disables +'1' : Enables + [3:3] + read-write + + + URIRQM + This bit masks the interrupt by URIRQ flag. +'0' : Disables +'1' : Enables + [4:4] + read-write + + + RWKIRQM + This bit masks the interrupt by RWKIRQ flag. +'0' : Disables +'1' : Enables + [5:5] + read-write + + + RSVD_6 + N/A + [6:6] + read-write + + + TCANM + This bit masks the interrupt by TCAN flag. +'0' : Disables +'1' : Enables + [7:7] + read-write + + + + + INTR_USBHOST_MASKED + Interrupt USB Host Masked Register + 0x94C + 32 + read-only + 0x0 + 0xFF + + + SOFIRQED + This bit indicates the interrupt by SOF flag. +'0' : Doesn't request the interrupt by SOF +'1' : Request the interrupt by SOF + [0:0] + read-only + + + DIRQED + This bit indicates the interrupt by DIRQ flag. +'0' : Doesn't request the interrupt by DIRQ +'1' : Request the interrupt by DIRQ + [1:1] + read-only + + + CNNIRQED + This bit indicates the interrupt by CNNIRQ flag. +'0' : Doesn't request the interrupt by CNNIRQ +'1' : Request the interrupt by CNNIRQ + [2:2] + read-only + + + CMPIRQED + This bit indicates the interrupt by CMPIRQ flag. +'0' : Doesn't request the interrupt by CMPIRQ +'1' : Request the interrupt by CMPIRQ + [3:3] + read-only + + + URIRQED + This bit indicates the interrupt by URIRQ flag. +'0' : Doesn't request the interrupt by URIRQ +'1' : Request the interrupt by URIRQ + [4:4] + read-only + + + RWKIRQED + This bit indicates the interrupt by RWKIRQ flag. +'0' : Doesn't request the interrupt by RWKIRQ +'1' : Request the interrupt by RWKIRQ + [5:5] + read-only + + + RSVD_6 + N/A + [6:6] + read-only + + + TCANED + This bit indicates the interrupt by TCAN flag. +'0' : Doesn't request the interrupt by TCAN +'1' : Request the interrupt by TCAN + [7:7] + read-only + + + + + INTR_HOST_EP + Interrupt USB Host Endpoint Register + 0xA00 + 32 + read-write + 0x0 + 0x3C + + + EP1DRQ + This bit indicates that the EP1 packet transfer has normally ended, and processing of the data is required. The DRQ bit is an interrupt cause, and writing '0' is ignored. Clear the DRQ bit by writing '1'. +'0' : Clears the interrupt cause +'1' : Packet transfer normally ended +Note : +- If automatic buffer transfer mode (DMAE = '1') is not used, '1' must be written to the DRQ bit after data has been written or read to/from the send/receive buffer. Switch the access buffers once the DRQ bit is cleared. That DRQ = '0' may not be read after the DRQ bit is cleared. If the transfer direction is set to OUT, and the DRQ bit is cleared without writing buffer data while the DRQ bit is '1', it implies that 0-byte data is set. If DIR of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is set to '1' at initial settings, the DRQ bit of corresponding Endpoint is set at the same time. Also while the DRQ bit is not set, '1' must not be written. + [2:2] + read-write + + + EP1SPK + This bit indicates that the data size transferred from the host does not satisfy the maximum packet size (including 0-byte) set by PKS in the Host Endpoint 1 Control Register (HOST_EP1_CTL) when the data has been received successfully. This bit is an interrupt cause, and writing '0' is ignored. Clear it by writing '1'. +'0' : Received data size satisfies the maximum packet size +'1' : Received data size does not satisfy the maximum packet size +Note : +- The SPK bit is not set during data transfer in the OUT direction. + [3:3] + read-write + + + EP2DRQ + This bit indicates that the EP2 packet transfer has normally ended, and processing of the data is required. The DRQ bit is an interrupt cause, and writing '0' is ignored. Clear the DRQ bit by writing '1'. +'0' : Clears the interrupt cause +'1' : Packet transfer normally ended +Note : +- If automatic buffer transfer mode (DMAE = '1') is not used, '1' must be written to the DRQ bit after data has been written or read to/from the send/receive buffer. Switch the access buffers once the DRQ bit is cleared. That DRQ = '0' may not be read after the DRQ bit is cleared. If the transfer direction is set to OUT, and the DRQ bit is cleared without writing buffer data while the DRQ bit is '1', it implies that 0-byte data is set. If DIR of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is set to '1' at initial settings, the DRQ bit of corresponding Endpoint is set at the same time. Also while the DRQ bit is not set, '1' must not be written. + [4:4] + read-write + + + EP2SPK + This bit indicates that the data size transferred from the host does not satisfy the maximum packet size (including 0-byte) set by PKS in the Host Endpoint 2 Control Register (HOST_EP2_CTL) when the data has been received successfully. This bit is an interrupt cause, and writing '0' is ignored. Clear it by writing '1'. +'0' : Received data size satisfies the maximum packet size +'1' : Received data size does not satisfy the maximum packet size +Note : +- The SPK bit is not set during data transfer in the OUT direction. + [5:5] + read-write + + + + + INTR_HOST_EP_SET + Interrupt USB Host Endpoint Set Register + 0xA04 + 32 + read-write + 0x0 + 0x3C + + + EP1DRQS + This bit sets EP1DRQ bit. If this bit is written to '1', EP1DRQ is set to '1'. However, if this bit is written with '0', its value is ignored. +Note: +If BFINI bit of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is '1', EP1DRQ can't be set to '1'. + [2:2] + read-write + + + EP1SPKS + This bit sets EP1SPK bit. If this bit is written to '1', EP1SPK is set to '1'. However, if this bit is written with '0', its value is ignored. +Note: +If BFINI bit of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is '1', EP1SPK can't be set to '1'. + [3:3] + read-write + + + EP2DRQS + This bit sets EP2DRQ bit. If this bit is written to '1', EP2DRQ is set to '1'. However, if this bit is written with '0', its value is ignored. +Note: +If BFINI bit of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is '1', EP2DRQ can't be set to '1'. + [4:4] + read-write + + + EP2SPKS + This bit sets EP2SPK bit. If this bit is written to '1', EP2SPK is set to '1'. However, if this bit is written with '0', its value is ignored. +Note: +If BFINI bit of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is '1', EP2SPK can't be set to '1'. + [5:5] + read-write + + + + + INTR_HOST_EP_MASK + Interrupt USB Host Endpoint Mask Register + 0xA08 + 32 + read-write + 0x0 + 0x3C + + + EP1DRQM + This bit masks the interrupt by EP1DRQ flag. +'0' : Disables +'1' : Enables + [2:2] + read-write + + + EP1SPKM + This bit masks the interrupt by EP1SPK flag. +'0' : Disables +'1' : Enables + [3:3] + read-write + + + EP2DRQM + This bit masks the interrupt by EP2DRQ flag. +'0' : Disables +'1' : Enables + [4:4] + read-write + + + EP2SPKM + This bit masks the interrupt by EP2SPK flag. +'0' : Disables +'1' : Enables + [5:5] + read-write + + + + + INTR_HOST_EP_MASKED + Interrupt USB Host Endpoint Masked Register + 0xA0C + 32 + read-only + 0x0 + 0x3C + + + EP1DRQED + This bit indicates the interrupt by EP1DRQ flag. +'0' : Doesn't request the interrupt by EP1DRQ +'1' : Request the interrupt by EP1DRQ + [2:2] + read-only + + + EP1SPKED + This bit indicates the interrupt by EP1SPK flag. +'0' : Doesn't request the interrupt by EP1SPK +'1' : Request the interrupt by EP1SPK + [3:3] + read-only + + + EP2DRQED + This bit indicates the interrupt by EP2DRQ flag. +'0' : Doesn't request the interrupt by EP2DRQ +'1' : Request the interrupt by EP2DRQ + [4:4] + read-only + + + EP2SPKED + This bit indicates the interrupt by EP2SPK flag. +'0' : Doesn't request the interrupt by EP2SPK +'1' : Request the interrupt by EP2SPK + [5:5] + read-only + + + + + HOST_DMA_ENBL + Host DMA Enable Register + 0xB00 + 32 + read-write + 0x0 + 0xC + + + DM_EP1DRQE + This bit enables DMA Request by EP1DRQ. +'0' : Disable +'1' : Enable + [2:2] + read-write + + + DM_EP2DRQE + This bit enables DMA Request by EP2DRQ. +'0' : Disable +'1' : Enable + [3:3] + read-write + + + + + HOST_EP1_BLK + Host Endpoint 1 Block Register + 0xB20 + 32 + read-write + 0x0 + 0xFFFF0000 + + + BLK_NUM + Set the total byte number for DMA transfer. If HOST_EP1_RW1_DR or HOST_EP1_RW2_DR is written, the block number counter is decrement when DMAE='1'. +- Set this bits before DMA transfer is enabled (HOST_DMA_ENBL.DM_DP1DRQE='1') + [31:16] + read-write + + + + + HOST_EP2_BLK + Host Endpoint 2 Block Register + 0xB30 + 32 + read-write + 0x0 + 0xFFFF0000 + + + BLK_NUM + Set the total byte number for DMA transfer. If HOST_EP2_RW1_DR or HOST_EP2_RW2_DR is written, the block number counter is decrement when DMAE='1'. +- Set this bits before DMA transfer is enabled (HOST_DMA_ENBL.DM_DP2DRQE='1') + [31:16] + read-write + + + + + + + + SMIF0 + Serial Memory Interface + SMIF + 0x40420000 + + 0 + 65536 + registers + + + + CTL + Control + 0x0 + 32 + read-write + 0x3000 + 0x81073001 + + + XIP_MODE + Mode of operation. + +Note: this field should only be changed when the IP is disabled or when STATUS.BUSY is '0' and SW should not be executing from the XIP interface or MMIO interface. + [0:0] + read-write + + + MMIO_MODE + '0': MMIO mode. Individual MMIO accesses to TX and RX FIFOs are used to generate a sequence of SPI transfers. This mode of operation allows for large flexibility in terms of the SPI transfers that can be generated. + 0 + + + XIP_MODE + 1': XIP mode. eXecute-In-Place mode: incoming read and write transfers over the AHB-Lite bus infrastructure are automatically translated in SPI transfers to read data from and write data to a device. This mode of operation allow for efficient device read and write operations. This mode is only supported in SPI_MODE. + 1 + + + + + CLOCK_IF_RX_SEL + Specifies device interface receiver clock 'clk_if_rx' source. MISO data is captured on the rising edge of 'clk_if_rx'. +'0': 'spi_clk_out' (internal clock) +'1': !'spi_clk_out' (internal clock) +'2': 'spi_clk_in' (feedback clock) +'3': !'spi_clk_in' (feedback clock) + +Note: the device interface transmitter clock 'clk_if_tx' is fixed and is 'spi_clk_out' MOSI data is driven on the falling edge of 'clk_if_tx'. + [13:12] + read-write + + + DESELECT_DELAY + Specifies the minimum duration of SPI deselection ('spi_select_out[]' is high/'1') in between SPI transfers: +'0': 1 interface clock cycle. +'1': 2 interface clock cycles. +'2': 3 interface clock cycles. +'3': 4 interface clock cycles. +'4': 5 interface clock cycles. +'5': 6 interface clock cycles. +'6': 7 interface clock cycles. +'7': 8 interface clock cycles. + +During SPI deselection, 'spi_select_out[]' are '1'/inactive, 'spi_data_out[]' are '1' and 'spi_clk_out' is '0'/inactive. + [18:16] + read-write + + + BLOCK + Specifies what happens for MMIO interface read accesses to an empty RX data FIFO or to a full TX format/data FIFO. Note: the FIFOs can only be accessed in MMIO_MODE. + +This field is not used for test controller accesses. + [24:24] + read-write + + + BUS_ERROR + 0': Generate an AHB-Lite bus error. This option is useful when SW decides to use polling on STATUS.TR_BUSY to determine if a interface transfer is no longer busy (transfer is completed). This option adds SW complexity, but limits the number of AHB-Lite wait states (and limits ISR latency). + 0 + + + WAIT_STATES + 1': Introduce wait states. This setting potentially locks up the AHB-Lite infrastructure and may increase the CPU interrupt latency.This option is useful when SW performs TX/RX data FIFO accesses immediately after a command is setup using the TX format FIFO. This option has low SW complexity, but may result in a significant number of AHB-Lite wait states (and may increase ISR latency). + 1 + + + + + ENABLED + IP enable: +'0': Disabled. All non-retention registers are reset to their default value when the IP is disabled. When the IP is disabled, the XIP accesses produce AHB-Lite bus errors. +'1': Enabled. + +Note: Before disabling the IP, SW should ensure that the IP is NOT busy (STATUS.BUSY is '0'), otherwise illegal interface transfers may occur. + [31:31] + read-write + + + DISABLED + N/A + 0 + + + ENABLED + N/A + 1 + + + + + + + STATUS + Status + 0x4 + 32 + read-only + 0x0 + 0x80000000 + + + BUSY + Cache, cryptography, XIP, device interface or any other logic busy in the IP: +'0': not busy +'1': busy +When BUSY is '0', the IP can be safely disabled without: +- the potential loss of transient write data. +- the potential risk of aborting an inflight SPI device interface transfer. +When BUSY is '0', the mode of operation (XIP_MODE or MMIO_MODE) can be safely changed. + [31:31] + read-only + + + + + TX_CMD_FIFO_STATUS + Transmitter command FIFO status + 0x44 + 32 + read-only + 0x0 + 0x7 + + + USED3 + Number of entries that are used in the TX command FIFO (available in both XIP_MODE and MMIO_MODE). Legal range: [0, 4]. + [2:0] + read-only + + + + + TX_CMD_FIFO_WR + Transmitter command FIFO write + 0x50 + 32 + write-only + 0x0 + 0xFFFFF + + + DATA20 + Command data. The higher two bits DATA[19:18] specify the specific command +'0'/TX: A SPI transfer always start with a TX command FIFO entry of the 'TX' format. +- DATA[17:16] specifies the width of the data transfer: + - '0': 1 bit/cycle (single data transfer). + - '1': 2 bits/cycle (dual data transfer). + - '2': 4 bits/cycle (quad data transfer). + - '3': 8 bits/cycle (octal data transfer). +- DATA[15]: specifies whether this is the last TX Byte; i.e. whether the 'spi_select_out[3:0]' IO output signals are de-activated after the transfer. +- DATA[11:8] specifies which of the four devices are selected. DATA[11:8] are directly mapped to 'spi_select_out[3:0]'. Two devices can be selected at the same time in dual-quad mode. + - '0': device deselected + - '1': device selected +- DATA[7:0] specifies the transmitted Byte. + +'1'/TX_COUNT: The 'TX_COUNT' command relies on the TX data FIFO to provide the transmitted bytes. The 'TX_COUNT' command is ALWAYS considered to be the last command of a SPI data transfers. +- DATA[17:16] specifies the width of the transfer. +- DATA[15:0] specifies the number of to be transmitted Bytes (minus 1) from the TX data FIFO. + +'2'/RX_COUNT: The 'RX_COUNT' command relies on the RX data FIFO to accept the received bytes. The 'RX_COUNT' command is ALWAYS considered to be the last command of a SPI data transfers. +- DATA[17:16] specifies the width of the transfer. +- DATA[15:0] specifies the number of to be transmitted Bytes (minus 1) to the RX data FIFO. + +'3'/DUMMY_COUNT: The 'DUMMY_COUNT' command conveys dummy cycles. Dummy cycles are used to implement a Turn-Around time in which the SPI master changes from a transmitter driving the data lines to a receiver receiving on the same data lines. The 'DUMMY_COUNT' command is ALWAYS considered to be NOT the last command of a SPI data transfers; i.e. it needs to be followed by another command. +- DATA[15:0] specifies the number of dummy cycles (minus 1). In dummy cycles, the data lines are not driven. + [19:0] + write-only + + + + + TX_DATA_FIFO_CTL + Transmitter data FIFO control + 0x80 + 32 + read-write + 0x0 + 0x7 + + + TRIGGER_LEVEL + Determines when the TX data FIFO 'tr_tx_req' trigger is activated (trigger activation requires MMIO_MODE, the trigger is NOT activated in XIP_MODE): +- Trigger is active when TX_DATA_FIFO_STATUS.USED <= TRIGGER_LEVEL. + [2:0] + read-write + + + + + TX_DATA_FIFO_STATUS + Transmitter data FIFO status + 0x84 + 32 + read-only + 0x0 + 0xF + + + USED4 + Number of entries that are used in the TX data FIFO (available in both XIP_MODE and MMIO_MODE). Legal range: [0, 8]. + [3:0] + read-only + + + + + TX_DATA_FIFO_WR1 + Transmitter data FIFO write + 0x90 + 32 + write-only + 0x0 + 0xFF + + + DATA0 + TX data (written to TX data FIFO). + [7:0] + write-only + + + + + TX_DATA_FIFO_WR2 + Transmitter data FIFO write + 0x94 + 32 + write-only + 0x0 + 0xFFFF + + + DATA0 + TX data (written to TX data FIFO, first byte). + [7:0] + write-only + + + DATA1 + TX data (written to TX data FIFO, second byte). + [15:8] + write-only + + + + + TX_DATA_FIFO_WR4 + Transmitter data FIFO write + 0x98 + 32 + write-only + 0x0 + 0xFFFFFFFF + + + DATA0 + TX data (written to TX data FIFO, first byte). + [7:0] + write-only + + + DATA1 + TX data (written to TX data FIFO, second byte). + [15:8] + write-only + + + DATA2 + TX data (written to TX data FIFO, third byte). + [23:16] + write-only + + + DATA3 + TX data (written to TX data FIFO, fourth byte). + [31:24] + write-only + + + + + RX_DATA_FIFO_CTL + Receiver data FIFO control + 0xC0 + 32 + read-write + 0x0 + 0x7 + + + TRIGGER_LEVEL + Determines when RX data FIFO 'tr_rx_req' trigger is activated (trigger activation requires MMIO_MODE, the trigger is NOT activated in XIP_MODE): +- Trigger is active when RX_DATA_FIFO_STATUS.USED > TRIGGER_LEVEL. + [2:0] + read-write + + + + + RX_DATA_FIFO_STATUS + Receiver data FIFO status + 0xC4 + 32 + read-only + 0x0 + 0xF + + + USED4 + Number of entries that are used in the RX data FIFO (available in both XIP_MODE and MMIO_MODE). Legal range: [0, 8]. + [3:0] + read-only + + + + + RX_DATA_FIFO_RD1 + Receiver data FIFO read + 0xD0 + 32 + read-only + 0x0 + 0xFF + + + DATA0 + RX data (read from RX data FIFO). + [7:0] + read-only + + + + + RX_DATA_FIFO_RD2 + Receiver data FIFO read + 0xD4 + 32 + read-only + 0x0 + 0xFFFF + + + DATA0 + RX data (read from RX data FIFO, first byte). + [7:0] + read-only + + + DATA1 + RX data (read from RX data FIFO, second byte). + [15:8] + read-only + + + + + RX_DATA_FIFO_RD4 + Receiver data FIFO read + 0xD8 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DATA0 + RX data (read from RX data FIFO, first byte). + [7:0] + read-only + + + DATA1 + RX data (read from RX data FIFO, second byte). + [15:8] + read-only + + + DATA2 + RX data (read from RX data FIFO, third byte). + [23:16] + read-only + + + DATA3 + RX data (read from RX data FIFO, fourth byte). + [31:24] + read-only + + + + + RX_DATA_FIFO_RD1_SILENT + Receiver data FIFO silent read + 0xE0 + 32 + read-only + 0x0 + 0xFF + + + DATA0 + RX data (read from RX data FIFO). + [7:0] + read-only + + + + + SLOW_CA_CTL + Slow cache control + 0x100 + 32 + read-write + 0xC0000000 + 0xC3030000 + + + WAY + this is for debug purpose only, and should be hidden to customers in technical document + [17:16] + read-write + + + SET_ADDR + this is for debug purpose only, and should be hidden to customers in technical document + [25:24] + read-write + + + PREF_EN + N/A + [30:30] + read-write + + + ENABLED + N/A + [31:31] + read-write + + + + + SLOW_CA_CMD + Slow cache command + 0x108 + 32 + read-write + 0x0 + 0x1 + + + INV + Cache and prefetch buffer invalidation. +SW writes a '1' to clear the cache and prefetch buffer. The cache's LRU structure is also reset to its default state. +Note, +A write access will invalidate the prefetch buffer automatically in hardware. +A write access should invalidate both fast and slow caches, by firmware. +Note, firmware should invalidate the cache and prefetch buffer only when STATUS.BUSY is '0'. + [0:0] + read-write + + + + + FAST_CA_CTL + Fast cache control + 0x180 + 32 + read-write + 0xC0000000 + 0xC3030000 + + + WAY + this is for debug purpose only, and should be hidden to customers in technical document + [17:16] + read-write + + + SET_ADDR + this is for debug purpose only, and should be hidden to customers in technical document + [25:24] + read-write + + + PREF_EN + N/A + [30:30] + read-write + + + ENABLED + N/A + [31:31] + read-write + + + + + FAST_CA_CMD + Fast cache command + 0x188 + 32 + read-write + 0x0 + 0x1 + + + INV + See SLOW_CA_CMD.INV. + [0:0] + read-write + + + + + CRYPTO_CMD + Cryptography Command + 0x200 + 32 + read-write + 0x0 + 0x1 + + + START + SW sets this field to '1' to start a AES-128 forward block cipher operation (on the address in CRYPTO_ADDR). HW sets this field to '0' to indicate that the operation has completed. Once completed, the result of the operation can be read from CRYPTO_RESULT0, ..., CRYPTO_RESULT3. + +The operation takes roughly 13 clk_hf clock cycles. + +Note: An operation can only be started in MMIO_MODE. + [0:0] + read-write + + + + + CRYPTO_INPUT0 + Cryptography input 0 + 0x220 + 32 + read-write + 0x0 + 0x0 + + + INPUT + Four Bytes of the plaintext PT[31:0] = CRYPTO_INPUT0.INPUT[31:0]. + [31:0] + read-write + + + + + CRYPTO_INPUT1 + Cryptography input 1 + 0x224 + 32 + read-write + 0x0 + 0x0 + + + INPUT + Four Bytes of the plaintext PT[63:32] = CRYPTO_INPUT1.INPUT[31:0]. + [31:0] + read-write + + + + + CRYPTO_INPUT2 + Cryptography input 2 + 0x228 + 32 + read-write + 0x0 + 0x0 + + + INPUT + Four Bytes of the plaintext PT[95:64] = CRYPTO_INPUT2.INPUT[31:0]. + [31:0] + read-write + + + + + CRYPTO_INPUT3 + Cryptography input 3 + 0x22C + 32 + read-write + 0x0 + 0x0 + + + INPUT + Four Bytes of the plaintext PT[127:96] = CRYPTO_INPUT3.INPUT[31:0]. + [31:0] + read-write + + + + + CRYPTO_KEY0 + Cryptography key 0 + 0x240 + 32 + write-only + 0x0 + 0x0 + + + KEY + Four Bytes of the key KEY[31:0] = CRYPTO_KEY0.KEY[31:0]. + [31:0] + write-only + + + + + CRYPTO_KEY1 + Cryptography key 1 + 0x244 + 32 + write-only + 0x0 + 0x0 + + + KEY + Four Bytes of the key KEY[63:32] = CRYPTO_KEY1.KEY[31:0]. + [31:0] + write-only + + + + + CRYPTO_KEY2 + Cryptography key 2 + 0x248 + 32 + write-only + 0x0 + 0x0 + + + KEY + Four Bytes of the key KEY[95:64] = CRYPTO_KEY2.KEY[31:0]. + [31:0] + write-only + + + + + CRYPTO_KEY3 + Cryptography key 3 + 0x24C + 32 + write-only + 0x0 + 0x0 + + + KEY + Four Bytes of the key KEY[127:96] = CRYPTO_KEY3.KEY[31:0]. + [31:0] + write-only + + + + + CRYPTO_OUTPUT0 + Cryptography output 0 + 0x260 + 32 + read-write + 0x0 + 0x0 + + + OUTPUT + Four Bytes of the ciphertext CT[31:0] = CRYPTO_OUTPUT0.OUTPUT[31:0]. + [31:0] + read-write + + + + + CRYPTO_OUTPUT1 + Cryptography output 1 + 0x264 + 32 + read-write + 0x0 + 0x0 + + + OUTPUT + Four Bytes of the ciphertext CT[63:32] = CRYPTO_OUTPUT1.OUTPUT[31:0]. + [31:0] + read-write + + + + + CRYPTO_OUTPUT2 + Cryptography output 2 + 0x268 + 32 + read-write + 0x0 + 0x0 + + + OUTPUT + Four Bytes of the ciphertext CT[95:64] = CRYPTO_OUTPUT2.OUTPUT[31:0]. + [31:0] + read-write + + + + + CRYPTO_OUTPUT3 + Cryptography output 3 + 0x26C + 32 + read-write + 0x0 + 0x0 + + + OUTPUT + Four Bytes of the ciphertext CT[127:96] = CRYPTO_OUTPUT3.OUTPUT[31:0]. + [31:0] + read-write + + + + + INTR + Interrupt register + 0x7C0 + 32 + read-write + 0x0 + 0x3F + + + TR_TX_REQ + Activated in MMIO mode, when a TX data FIFO trigger 'tr_tx_req' is activated. + [0:0] + read-write + + + TR_RX_REQ + Activated in MMIO mode, when a RX data FIFO trigger 'tr_rx_req' is activated. + [1:1] + read-write + + + XIP_ALIGNMENT_ERROR + Activated in XIP mode, if: +- The selected device's ADDR_CTL.DIV2 is '1' and the AHB-Lite bus transfer address is not a multiple of 2. +- The selected device's ADDR_CTL.DIV2 is '1' and the XIP transfer request is NOT for a multiple of 2 Bytes. + +Note: In dual-quad SPI mode (ADDR_CTL.DIV is '1'), each memory device contributes a 4-bit nibble for read data or write data. This is only possible if the request address is a multiple of 2 and the number of requested Bytes is a multiple of 2. + [2:2] + read-write + + + TX_CMD_FIFO_OVERFLOW + Activated in MMIO mode, on an AHB-Lite write transfer to the TX command FIFO (TX_CMD_FIFO_WR) with not enough free entries available. + [3:3] + read-write + + + TX_DATA_FIFO_OVERFLOW + Activated in MMIO mode, on an AHB-Lite write transfer to the TX data FIFO (TX_DATA_FIFO_WR1, TX_DATA_FIFO_WR2, TX_DATA_FIFO_WR4) with not enough free entries available. + [4:4] + read-write + + + RX_DATA_FIFO_UNDERFLOW + Activated in MMIO mode, on an AHB-Lite read transfer from the RX data FIFO (RX_DATA_FIFO_RD1, RX_DATA_FIFO_RD2, RX_DATA_FIFO_RD4) with not enough entries available. Only activated for NON test bus controller transfers. + [5:5] + read-write + + + + + INTR_SET + Interrupt set register + 0x7C4 + 32 + read-write + 0x0 + 0x3F + + + TR_TX_REQ + Write with '1' to set corresponding bit in interrupt request register. + [0:0] + read-write + + + TR_RX_REQ + Write with '1' to set corresponding bit in interrupt request register. + [1:1] + read-write + + + XIP_ALIGNMENT_ERROR + Write with '1' to set corresponding bit in interrupt request register. + [2:2] + read-write + + + TX_CMD_FIFO_OVERFLOW + Write with '1' to set corresponding bit in interrupt request register. + [3:3] + read-write + + + TX_DATA_FIFO_OVERFLOW + Write with '1' to set corresponding bit in interrupt request register. + [4:4] + read-write + + + RX_DATA_FIFO_UNDERFLOW + Write with '1' to set corresponding bit in interrupt request register. + [5:5] + read-write + + + + + INTR_MASK + Interrupt mask register + 0x7C8 + 32 + read-write + 0x0 + 0x3F + + + TR_TX_REQ + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + TR_RX_REQ + Mask bit for corresponding bit in interrupt request register. + [1:1] + read-write + + + XIP_ALIGNMENT_ERROR + Mask bit for corresponding bit in interrupt request register. + [2:2] + read-write + + + TX_CMD_FIFO_OVERFLOW + Mask bit for corresponding bit in interrupt request register. + [3:3] + read-write + + + TX_DATA_FIFO_OVERFLOW + Mask bit for corresponding bit in interrupt request register. + [4:4] + read-write + + + RX_DATA_FIFO_UNDERFLOW + Mask bit for corresponding bit in interrupt request register. + [5:5] + read-write + + + + + INTR_MASKED + Interrupt masked register + 0x7CC + 32 + read-only + 0x0 + 0x3F + + + TR_TX_REQ + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + TR_RX_REQ + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + XIP_ALIGNMENT_ERROR + Logical and of corresponding request and mask bits. + [2:2] + read-only + + + TX_CMD_FIFO_OVERFLOW + Logical and of corresponding request and mask bits. + [3:3] + read-only + + + TX_DATA_FIFO_OVERFLOW + Logical and of corresponding request and mask bits. + [4:4] + read-only + + + RX_DATA_FIFO_UNDERFLOW + Logical and of corresponding request and mask bits. + [5:5] + read-only + + + + + 3 + 128 + DEVICE[%s] + Device (only used in XIP mode) + 0x00000800 + + CTL + Control + 0x0 + 32 + read-write + 0x0 + 0x80030101 + + + WR_EN + Write enable: +'0': write transfers are not allowed to this device. An attempt to write to this device results in an AHB-Lite bus error. +'1': write transfers are allowed to this device. + [0:0] + read-write + + + CRYPTO_EN + Cryptography on read/write accesses: +'0': disabled. +'1': enabled. + [8:8] + read-write + + + DATA_SEL + Specifies the connection of the IP's data lines (spi_data[0], ..., spi_data[7]) to the device's data lines (SI/IO0, SO/IO1, IO2, IO3, IO4, IO5, IO6, IO7): +'0': spi_data[0] = IO0, spi_data[1] = IO1, ..., spi_data[7] = IO7. This value is allowed for single, dual, quad, dual quad and octal SPI modes. This value must be used for the first device in dual quad SPI mode. This value must be used for octal SPI mode. +'1': spi_data[2] = IO0, spi_data[3] = IO1. This value is only allowed for single and dual SPI modes. +'2': spi_data[4] = IO0, spi_data[5] = IO1, ..., spi_data[7] = IO3. This value is only allowed for single, dual, quad and dual quad SPI modes. In dual quad SPI mode, this value must be used for the second device. +'3': spi_data[6] = IO0, spi_data[7] = IO1. This value is only allowed for single and dual SPI modes. + [17:16] + read-write + + + ENABLED + Device enable: +'0': Disabled. +'1': Enabled. + [31:31] + read-write + + + + + ADDR + Device region base address + 0x8 + 32 + read-write + 0x0 + 0x0 + + + ADDR + Specifies the base address of the device region. If the device region is 2^m Bytes, ADDR MUST be a multiple of 2^m. + +In dual quad SPI data transfer, the two devices should have the same ADDR and MASK register settings. The device control information (ADDR_CTL, RD_CMD_CTL, etc.) are provided by the MMIO control registers of the device with the lowest index. + +The most significant bit fields are constants and set based on the SMIF_XIP_ADDR parameter. The most significant bits are identified on the SMIF_XIP_MASK parameter. E.g., if SMIF_XIP_MASK is 0xff00:0000 (16 MB XIP memory region), ADDR[31:24] = SMIF_XIP_ADDR[31:24]. + [31:8] + read-write + + + + + MASK + Device region mask + 0xC + 32 + read-write + 0x0 + 0x0 + + + MASK + Specifies the size of the device region. All '1' bits are used to compare the incoming transfer request address A[31:0] with the address as specified in ADDR.ADDR: Address A is in the device when (A[31:8] & MASK[31:8]) == ADDR.ADDR[31:8]. + +The most significant bit fields are constants and set to'1'. The most significant bits are identified on the SMIF_XIP_MASK parameter. E.g., if SMIF_XIP_MASK is 0xff00:0000 (16 MB XIP memory region), MASK[31:24] = 0xff. + +Note: a transfer request that is not in any device region results in an AHB-Lite bus error. + [31:8] + read-write + + + + + ADDR_CTL + Address control + 0x20 + 32 + read-write + 0x0 + 0x103 + + + SIZE2 + Specifies the size of the XIP device address in Bytes: +'0': 1 Byte address. +'1': 2 Byte address. +'2': 3 Byte address. +'3': 4 Byte address. +The lower significant address Bytes of the transfer request are used as XIP address to the external device. Note that for dual quad SPI data transfer, the transfer request address is divided by 2. Therefore, the transfer request address needs to be a multiple of 2. If the trasnfer requestaddress is NOT a multiple of 2, the XIP_ALIGNMENT_ERROR interrupt cause is activated. + [1:0] + read-write + + + DIV2 + Specifies if the AHB-Lite bus transfer address is divided by 2 or not: +'0': No divide by 2. +'1': Divide by 2. + +This functionality is used for read and write operation in XIP, dual quad SPI mode; i.e. this DIV2 must be set to '1' in dual quad SPI mode. If the transfer request address is NOT a multiple of 2 or the requested number of Bytes is not a multiple of 2, the XIP_ALIGNMENT_ERROR interrupt cause is activated. + [8:8] + read-write + + + + + RD_CMD_CTL + Read command control + 0x40 + 32 + read-write + 0x0 + 0x800300FF + + + CODE + Command byte code. + [7:0] + read-write + + + WIDTH + Width of data transfer: +'0': 1 bit/cycle (single data transfer). +'1': 2 bits/cycle (dual data transfer). +'2': 4 bits/cycle (quad data transfer). +'3': 8 bits/cycle (octal data transfer). + [17:16] + read-write + + + PRESENT + Presence of command field: +'0': not present +'1': present + [31:31] + read-write + + + + + RD_ADDR_CTL + Read address control + 0x44 + 32 + read-write + 0x0 + 0x30000 + + + WIDTH + Width of transfer. + [17:16] + read-write + + + + + RD_MODE_CTL + Read mode control + 0x48 + 32 + read-write + 0x0 + 0x800300FF + + + CODE + Mode byte code. + [7:0] + read-write + + + WIDTH + Width of transfer. + [17:16] + read-write + + + PRESENT + Presence of mode field: +'0': not present +'1': present + [31:31] + read-write + + + + + RD_DUMMY_CTL + Read dummy control + 0x4C + 32 + read-write + 0x0 + 0x8000001F + + + SIZE5 + Number of dummy cycles (minus 1): +'0': 1 cycles +... +'31': 32 cycles. + +Note: this field specifies dummy cycles, not dummy Bytes! + [4:0] + read-write + + + PRESENT + Presence of dummy cycles: +'0': not present +'1': present + [31:31] + read-write + + + + + RD_DATA_CTL + Read data control + 0x50 + 32 + read-write + 0x0 + 0x30000 + + + WIDTH + Width of transfer. + [17:16] + read-write + + + + + WR_CMD_CTL + Write command control + 0x60 + 32 + read-write + 0x0 + 0x800300FF + + + CODE + Command byte code. + [7:0] + read-write + + + WIDTH + Width of transfer. + [17:16] + read-write + + + PRESENT + Presence of command field: +'0': not present +'1': present + [31:31] + read-write + + + + + WR_ADDR_CTL + Write address control + 0x64 + 32 + read-write + 0x0 + 0x30000 + + + WIDTH + Width of transfer. + [17:16] + read-write + + + + + WR_MODE_CTL + Write mode control + 0x68 + 32 + read-write + 0x0 + 0x800300FF + + + CODE + Mode byte code. + [7:0] + read-write + + + WIDTH + Width of transfer. + [17:16] + read-write + + + PRESENT + Presence of mode field: +'0': not present +'1': present + [31:31] + read-write + + + + + WR_DUMMY_CTL + Write dummy control + 0x6C + 32 + read-write + 0x0 + 0x8000001F + + + SIZE5 + Number of dummy cycles (minus 1): +'0': 1 cycles +... +'31': 32 cycles. + [4:0] + read-write + + + PRESENT + Presence of dummy cycles: +'0': not present +'1': present + [31:31] + read-write + + + + + WR_DATA_CTL + Write data control + 0x70 + 32 + read-write + 0x0 + 0x30000 + + + WIDTH + Width of transfer. + [17:16] + read-write + + + + + + + + CANFD0 + CAN Controller + CANFD + 0x40520000 + + 0 + 131072 + registers + + + + CH + FIFO wrapper around M_TTCAN 3PIP, to enable DMA + 0x00000000 + + M_TTCAN + TTCAN 3PIP, includes FD + 0x00000000 + + CREL + Core Release Register + 0x0 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DAY + Time Stamp Day +Two digits, BCD-coded. This field is set by generic parameter on M_TTCAN synthesis. + [7:0] + read-only + + + MON + Time Stamp Month +Two digits, BCD-coded. This field is set by generic parameter on M_TTCAN synthesis. + [15:8] + read-only + + + YEAR + Time Stamp Year +One digit, BCD-coded. This field is set by generic parameter on M_TTCAN synthesis. + [19:16] + read-only + + + SUBSTEP + Sub-step of Core Release +One digit, BCD-coded. + [23:20] + read-only + + + STEP + Step of Core Release +One digit, BCD-coded. + [27:24] + read-only + + + REL + Core Release +One digit, BCD-coded. + [31:28] + read-only + + + + + ENDN + Endian Register + 0x4 + 32 + read-only + 0x87654321 + 0xFFFFFFFF + + + ETV + Endianness Test Value +The endianness test value is 0x87654321. + [31:0] + read-only + + + + + DBTP + Data Bit Timing & Prescaler Register + 0xC + 32 + read-write + 0xA33 + 0x9F1FFF + + + DSJW + Data (Re)Synchronization Jump Width +0x0-0xF Valid values are 0 to 15. The actual interpretation by the hardware of this value is +such that one more than the value programmed here is used. + [3:0] + read-write + + + DTSEG2 + Data time segment after sample point +0x0-0xF Valid values are 0 to 15. The actual interpretation by the hardware of this value is +such that one more than the programmed value is used. + [7:4] + read-write + + + DTSEG1 + Data time segment before sample point +0x00-0x1F Valid values are 0 to 31. The actual interpretation by the hardware of this value is +such that one more than the programmed value is used. + [12:8] + read-write + + + DBRP + Data Bit Rate Prescaler +0x00-0x1F The value by which the oscillator frequency is divided for generating the bit time +quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit +Rate Prescaler are 0 to 31. The actual interpretation by the hardware of this value is +such that one more than the value programmed here is used. + [20:16] + read-write + + + TDC + Transmitter Delay Compensation +0= Transmitter Delay Compensation disabled +1= Transmitter Delay Compensation enabled + [23:23] + read-write + + + + + TEST + Test Register + 0x10 + 32 + read-write + 0x0 + 0x7F + + + TAM + ASC is not supported by M_TTCAN +Test ASC Multiplexer Control +Controls output pin m_ttcan_ascm in test mode, ORed with the signal from the FSE +0= Level at pin m_ttcan_ascm controlled by FSE +1= Level at pin m_ttcan_ascm = '1' + [0:0] + read-write + + + TAT + ASC is not supported by M_TTCAN +Test ASC Transmit Control +Controls output pin m_ttcan_asct in test mode, ORed with the signal from the FSE +0= Level at pin m_ttcan_asct controlled by FSE +1= Level at pin m_ttcan_asct = '1' + [1:1] + read-write + + + CAM + ASC is not supported by M_TTCAN +Check ASC Multiplexer Control +Monitors level at output pin m_ttcan_ascm. +0= Output pin m_ttcan_ascm = '0' +1= Output pin m_ttcan_ascm = '1' + [2:2] + read-write + + + CAT + ASC is not supported by M_TTCAN +Check ASC Transmit Control +Monitors level at output pin m_ttcan_asct. +0= Output pin m_ttcan_asct = '0' + [3:3] + read-write + + + LBCK + Loop Back Mode +0= Reset value, Loop Back Mode is disabled +1= Loop Back Mode is enabled (see Section 3.1.9, Test Modes) + [4:4] + read-write + + + TX + Control of Transmit Pin +00 Reset value, m_ttcan_tx controlled by the CAN Core, updated at the end of the CAN bit time +01 Sample Point can be monitored at pin m_ttcan_tx +10 Dominant ('0') level at pin m_ttcan_tx +11 Recessive ('1') at pin m_ttcan_tx + [6:5] + read-write + + + RX + Receive Pin +Monitors the actual value of pin m_ttcan_rx +0= The CAN bus is dominant (m_ttcan_rx = '0') +1= The CAN bus is recessive (m_ttcan_rx = '1') + [7:7] + read-only + + + + + RWD + RAM Watchdog + 0x14 + 32 + read-write + 0x0 + 0xFFFF + + + WDC + Watchdog Configuration +Start value of the Message RAM Watchdog Counter. With the reset value of '00' the counter is +disabled. + [7:0] + read-write + + + WDV + Watchdog Value +Actual Message RAM Watchdog Counter Value. + [15:8] + read-only + + + + + CCCR + CC Control Register + 0x18 + 32 + read-write + 0x1 + 0xF3FF + + + INIT + Initialization +0= Normal Operation +1= Initialization is started + [0:0] + read-write + + + CCE + Configuration Change Enable +0= The CPU has no write access to the protected configuration registers +1= The CPU has write access to the protected configuration registers (while CCCR.INIT = '1') + [1:1] + read-write + + + ASM + Restricted Operation Mode +Bit ASM can only be set by the Host when both CCE and INIT are set to '1'. The bit can be reset by +the Host at any time. For a description of the Restricted Operation Mode see Section 3.1.5. +0= Normal CAN operation +1= Restricted Operation Mode active + [2:2] + read-write + + + CSA + Clock Stop Acknowledge +0= No clock stop acknowledged +1= M_TTCAN may be set in power down by stopping m_ttcan_hclk and m_ttcan_cclk + [3:3] + read-write + + + CSR + Clock Stop Request, not supported by M_TTCAN use CTL.STOP_REQ at the group level instead. +0= No clock stop is requested +1= Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after +all pending transfer requests have been completed and the CAN bus reached idle. + [4:4] + read-write + + + MON_ + Bus Monitoring Mode +Bit MON can only be set by the Host when both CCE and INIT are set to '1'. The bit can be reset by +the Host at any time. +0= Bus Monitoring Mode is disabled +1= Bus Monitoring Mode is enabled + [5:5] + read-write + + + DAR + Disable Automatic Retransmission +0= Automatic retransmission of messages not transmitted successfully enabled +1= Automatic retransmission disabled + [6:6] + read-write + + + TEST + Test Mode Enable +0= Normal operation, register TEST holds reset values +1= Test Mode, write access to register TEST enabled + [7:7] + read-write + + + FDOE + FD Operation Enable +0= FD operation disabled +1= FD operation enabled + [8:8] + read-write + + + BRSE + Bit Rate Switch Enable +0= Bit rate switching for transmissions disabled +1= Bit rate switching for transmissions enabled + [9:9] + read-write + + + PXHD + Protocol Exception Handling Disable +0= Protocol exception handling enabled +1= Protocol exception handling disabled + [12:12] + read-write + + + EFBI + Edge Filtering during Bus Integration +0= Edge filtering disabled +1= Two consecutive dominant tq required to detect an edge for hard synchronization + [13:13] + read-write + + + TXP + Transmit Pause +If this bit is set, the M_TTCAN pauses for two CAN bit times before starting the next transmission +after itself has successfully transmitted a frame (see Section 3.5). +0= Transmit pause disabled +1= Transmit pause enabled + [14:14] + read-write + + + NISO + Non ISO Operation +If this bit is set, the M_TTCAN uses the CAN FD frame format as specified by the Bosch CAN FD +Specification V1.0. +0= CAN FD frame format according to ISO 11898-1:2015 +1= CAN FD frame format according to Bosch CAN FD Specification V1.0 addressing the non-ISO CAN FD + [15:15] + read-write + + + + + NBTP + Nominal Bit Timing & Prescaler Register + 0x1C + 32 + read-write + 0x6000A03 + 0xFFFFFF7F + + + NTSEG2 + Nominal Time segment after sample point +0x01-0x7F Valid values are 1 to 127. The actual interpretation by the hardware of this value is +such that one more than the programmed value is used. + [6:0] + read-write + + + NTSEG1 + Nominal Time segment before sample point +0x01-0xFF Valid values are 1 to 255. The actual interpretation by the hardware of this value is +such that one more than the programmed value is used. + [15:8] + read-write + + + NBRP + Nominal Bit Rate Prescaler +0x000-0x1FFThe value by which the oscillator frequency is divided for generating the bit time +quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit +Rate Prescaler are 0 to 511. The actual interpretation by the hardware of this value is +such that one more than the value programmed here is used. + [24:16] + read-write + + + NSJW + Nominal (Re)Synchronization Jump Width +0x00-0x7F Valid values are 0 to 127. The actual interpretation by the hardware of this value is +such that one more than the value programmed here is used. + [31:25] + read-write + + + + + TSCC + Timestamp Counter Configuration + 0x20 + 32 + read-write + 0x0 + 0xF0003 + + + TSS + Timestamp Select, should always be set to external timestamp counter +00= Timestamp counter value always 0x0000 +01= Timestamp counter value incremented according to TCP +10= External timestamp counter value used +11= Same as '00' + [1:0] + read-write + + + TCP + Timestamp Counter Prescaler (still used for TOCC) +0x0-0xF Configures the timestamp and timeout counters time unit in multiples of CAN bit times +[1...16]. The actual interpretation by the hardware of this value is such that one more +than the value programmed here is used. + [19:16] + read-write + + + + + TSCV + Timestamp Counter Value + 0x24 + 32 + read-write + 0x0 + 0xFFFF + + + TSC + Timestamp Counter, not used for M_TTCAN +The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx). +When TSCC.TSS = '01', the Timestamp Counter is incremented in multiples of CAN bit times +[1...16] depending on the configuration of TSCC.TCP. A wrap around sets interrupt flag IR.TSW. +Write access resets the counter to zero. When TSCC.TSS = '10', TSC reflects the external +Timestamp Counter value. A write access has no impact. + [15:0] + read-write + + + + + TOCC + Timeout Counter Configuration + 0x28 + 32 + read-write + 0xFFFF0000 + 0xFFFF0007 + + + ETOC + Enable Timeout Counter +0= Timeout Counter disabled +1= Timeout Counter enabled + [0:0] + read-write + + + TOS + Timeout Select +When operating in Continuous mode, a write to TOCV presets the counter to the value configured +by TOCC.TOP and continues down-counting. When the Timeout Counter is controlled by one of the +FIFOs, an empty FIFO presets the counter to the value configured by TOCC.TOP. Down-counting +is started when the first FIFO element is stored. +00= Continuous operation +01= Timeout controlled by Tx Event FIFO +10= Timeout controlled by Rx FIFO 0 +11= Timeout controlled by Rx FIFO 1 + [2:1] + read-write + + + TOP + Timeout Period +Start value of the Timeout Counter (down-counter). Configures the Timeout Period. + [31:16] + read-write + + + + + TOCV + Timeout Counter Value + 0x2C + 32 + read-write + 0xFFFF + 0xFFFF + + + TOC + Timeout Counter +The Timeout Counter is decremented in multiples of CAN bit times [1...16] depending on the +configuration of TSCC.TCP. When decremented to zero, interrupt flag IR.TOO is set and the +Timeout Counter is stopped. Start and reset/restart conditions are configured via TOCC.TOS. + [15:0] + read-write + + + + + ECR + Error Counter Register + 0x40 + 32 + read-only + 0x0 + 0xFFFFFF + + + TEC + Transmit Error Counter +Actual state of the Transmit Error Counter, values between 0 and 255 + [7:0] + read-only + + + REC + Receive Error Counter +Actual state of the Receive Error Counter, values between 0 and 127 + [14:8] + read-only + + + RP + Receive Error Passive +0= The Receive Error Counter is below the error passive level of 128 +1= The Receive Error Counter has reached the error passive level of 128 + [15:15] + read-only + + + CEL + CAN Error Logging +The counter is incremented each time when a CAN protocol error causes the Transmit Error Counter +or the Receive Error Counter to be incremented. It is reset by read access to CEL. The counter stops +at 0xFF; the next increment of TEC or REC sets interrupt flag IR.ELO. + [23:16] + read-only + + + + + PSR + Protocol Status Register + 0x44 + 32 + read-only + 0x707 + 0x7F7FFF + + + LEC + Last Error Code, +Set on Read0 +The LEC indicates the type of the last error to occur on the CAN bus. This field will be cleared to '0' +when a message has been transferred (reception or transmission) without error. + +0= No Error: No error occurred since LEC has been reset by successful reception or transmission. +1= Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. +2= Form Error: A fixed format part of a received frame has the wrong format. +3= AckError: The message transmitted by the M_TTCAN was not acknowledged by another node. +4= Bit1Error: During the transmission of a message (with the exception of the arbitration field), +the device wanted to send a recessive level (bit of logical value '1'), but the monitored bus + value was dominant. +5= Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or +overload flag), the device wanted to send a dominant level (data or identifier bit logical value +0'), but the monitored bus value was recessive. During Bus_Off recovery this status is set +each time a sequence of 11 recessive bits has been monitored. This enables the CPU to +monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at +dominant or continuously disturbed). +6= CRCError: The CRC check sum of a received message was incorrect. The CRC of an incoming +message does not match with the CRC calculated from the received data. +7= NoChange: Any read access to the Protocol Status Register re-initializes the LEC to '7'. +When the LEC shows the value '7', no CAN bus event was detected since the last CPU read +access to the Protocol Status Register. + [2:0] + read-only + + + ACT + Activity +Monitors the module's CAN communication state. +00= Synchronizing - node is synchronizing on CAN communication +01= Idle - node is neither receiver nor transmitter +10= Receiver - node is operating as receiver +11= Transmitter - node is operating as transmitter + [4:3] + read-only + + + EP + Error Passive +0= The M_CAN is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected +1= The M_CAN is in the Error_Passive state + [5:5] + read-only + + + EW + Warning Status +0= Both error counters are below the Error_Warning limit of 96 +1= At least one of error counter has reached the Error_Warning limit of 96 + [6:6] + read-only + + + BO + Bus_Off Status +0= The M_CAN is not Bus_Off +1= The M_CAN is in Bus_Off state + [7:7] + read-only + + + DLEC + Data Phase Last Error Code +, Set on Read +Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. Coding is the same as for LEC. This field will be cleared to zero when a CAN FD format frame with its BRS flag set has been transferred (reception or transmission) without error. + [10:8] + read-only + + + RESI + ESI flag of last received CAN FD Message +, Reset on Read +This bit is set together with RFDF, independent of acceptance filtering. +0= Last received CAN FD message did not have its ESI flag set +1= Last received CAN FD message had its ESI flag set + [11:11] + read-only + + + RBRS + BRS flag of last received CAN FD Message +, Reset on Read +This bit is set together with RFDF, independent of acceptance filtering. +0= Last received CAN FD message did not have its BRS flag set +1= Last received CAN FD message had its BRS flag set + [12:12] + read-only + + + RFDF + Received a CAN FD Message +, Reset on Read +This bit is set independent of acceptance filtering. +0= Since this bit was reset by the CPU, no CAN FD message has been received +1= Message in CAN FD format with FDF flag set has been received + [13:13] + read-only + + + PXE + Protocol Exception Event +, Reset on Read +0= No protocol exception event occurred since last read access +1= Protocol exception event occurred + [14:14] + read-only + + + TDCV + Transmitter Delay Compensation Value +0x00-0x7F Position of the secondary sample point, defined by the sum of the measured delay from m_can_tx to m_can_rx and TDCR.TDCO. The SSP position is, in the data phase, the number of mtq between the start of the transmitted bit and the secondary sample point. Valid values are 0 to 127 mtq. + [22:16] + read-only + + + + + TDCR + Transmitter Delay Compensation Register + 0x48 + 32 + read-write + 0x0 + 0x7F7F + + + TDCF + Transmitter Delay Compensation Filter Window Length +0x00-0x7F Defines the minimum value for the SSP position, dominant edges on m_ttcan_rx +that would result in an earlier SSP position are ignored for transmitter delay measurement. +The feature is enabled when TDCF is configured to a value greater than +TDCO. Valid values are 0 to 127 mtq + [6:0] + read-write + + + TDCO + Transmitter Delay Compensation Offset +0x00-0x7F Offset value defining the distance between the measured delay from m_ttcan_tx to +m_ttcan_rx and the secondary sample point. Valid values are 0 to 127 mtq. + [14:8] + read-write + + + + + IR + Interrupt Register + 0x50 + 32 + read-write + 0x0 + 0x3FFFFFFF + + + RF0N + Rx FIFO 0 New Message +0= No new message written to Rx FIFO 0 +1= New message written to Rx FIFO 0 + [0:0] + read-write + + + RF0W + Rx FIFO 0 Watermark Reached +0= Rx FIFO 0 fill level below watermark +1= Rx FIFO 0 fill level reached watermark + [1:1] + read-write + + + RF0F + Rx FIFO 0 Full +0= Rx FIFO 0 not full +1= Rx FIFO 0 full + [2:2] + read-write + + + RF0L_ + Rx FIFO 0 Message Lost +0= No Rx FIFO 0 message lost +1= Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero + [3:3] + read-write + + + RF1N + Rx FIFO 1 New Message +0= No new message written to Rx FIFO 1 +1= New message written to Rx FIFO 1 + [4:4] + read-write + + + RF1W + Rx FIFO 1 Watermark Reached +0= Rx FIFO 1 fill level below watermark +1= Rx FIFO 1 fill level reached watermark + [5:5] + read-write + + + RF1F + Rx FIFO 1 Full +0= Rx FIFO 1 not full +1= Rx FIFO 1 full + [6:6] + read-write + + + RF1L_ + Rx FIFO 1 Message Lost +0= No Rx FIFO 1 message lost +1= Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero + [7:7] + read-write + + + HPM + High Priority Message +0= No high priority message received +1= High priority message received + [8:8] + read-write + + + TC + Transmission Completed +0= No transmission completed +1= Transmission completed + [9:9] + read-write + + + TCF + Transmission Cancellation Finished +0= No transmission cancellation finished +1= Transmission cancellation finished + [10:10] + read-write + + + TFE + Tx FIFO Empty +0= Tx FIFO non-empty +1= Tx FIFO empty + [11:11] + read-write + + + TEFN + Tx Event FIFO New Entry +0= Tx Event FIFO unchanged +1= Tx Handler wrote Tx Event FIFO element + [12:12] + read-write + + + TEFW + Tx Event FIFO Watermark Reached +0= Tx Event FIFO fill level below watermark +1= Tx Event FIFO fill level reached watermark + [13:13] + read-write + + + TEFF + Tx Event FIFO Full +0= Tx Event FIFO not full +1= Tx Event FIFO full + [14:14] + read-write + + + TEFL_ + Tx Event FIFO Element Lost +0= No Tx Event FIFO element lost +1= Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero + [15:15] + read-write + + + TSW + Timestamp Wraparound +0= No timestamp counter wrap-around +1= Timestamp counter wrapped around + [16:16] + read-write + + + MRAF + Message RAM Access Failure +The flag is set, when the Rx Handler +- has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or message storage is aborted and the Rx Handler starts processing of the following message. +- was not able to write a message to the Message RAM. In this case message storage is aborted. +In both cases the FIFO put index is not updated resp. the New Data flag for a dedicated Rx Buffer is not set, a partly stored message is overwritten when the next message is stored to this location. +The flag is also set when the Tx Handler was not able to read a message from the Message RAM +in time. In this case message transmission is aborted. In case of a Tx Handler access failure the +M_TTCAN is switched into Restricted Operation Mode (see Section 3.1.5). To leave Restricted +Operation Mode, the Host CPU has to reset CCCR.ASM. +0= No Message RAM access failure occurred +1= Message RAM access failure occurred + [17:17] + read-write + + + TOO + Timeout Occurred +0= No timeout +1= Timeout reached + [18:18] + read-write + + + DRX + Message stored to Dedicated Rx Buffer +The flag is set whenever a received message has been stored into a dedicated Rx Buffer. +0= No Rx Buffer updated +1= At least one received message stored into a Rx Buffer + [19:19] + read-write + + + BEC + M_TTCAN reports correctable ECC fault to the generic fault structure, this bit always reads as 0. +Bit Error Corrected +Message RAM bit error detected and corrected. Controlled by input signal m_ttcan_aeim_berr[0] +generated by an optional external parity / ECC logic attached to the Message RAM. +0= No bit error detected when reading from Message RAM +1= Bit error detected and corrected (e.g. ECC) + [20:20] + read-write + + + BEU + Bit Error Uncorrected +Message RAM bit error detected, uncorrected. Controlled by input signal m_ttcan_aeim_berr[1] +generated by an optional external parity / ECC logic attached to the Message RAM. An uncorrected +Message RAM bit error sets CCCR.INIT to '1'. This is done to avoid transmission of corrupted data. +0= No bit error detected when reading from Message RAM +1= Bit error detected, uncorrected (e.g. parity logic) + [21:21] + read-write + + + ELO + Error Logging Overflow +0= CAN Error Logging Counter did not overflow +1= Overflow of CAN Error Logging Counter occurred + [22:22] + read-write + + + EP_ + Error Passive +0= Error_Passive status unchanged +1= Error_Passive status changed + [23:23] + read-write + + + EW_ + Warning Status +0= Error_Warning status unchanged +1= Error_Warning status changed + [24:24] + read-write + + + BO_ + Bus_Off Status +0= Bus_Off status unchanged +1= Bus_Off status changed + [25:25] + read-write + + + WDI + Watchdog Interrupt +0= No Message RAM Watchdog event occurred +1= Message RAM Watchdog event due to missing READY + [26:26] + read-write + + + PEA + Protocol Error in Arbitration Phase (Nominal Bit Time is used) +0= No protocol error in arbitration phase +1= Protocol error in arbitration phase detected (PSR.LEC != 0,7) + [27:27] + read-write + + + PED + Protocol Error in Data Phase (Data Bit Time is used) +0= No protocol error in data phase +1= Protocol error in data phase detected (PSR.DLEC != 0,7) + [28:28] + read-write + + + ARA + N/A + [29:29] + read-write + + + + + IE + Interrupt Enable + 0x54 + 32 + read-write + 0x0 + 0x3FFFFFFF + + + RF0NE + Rx FIFO 0 New Message Interrupt Enable + [0:0] + read-write + + + RF0WE + Rx FIFO 0 Watermark Reached Interrupt Enable + [1:1] + read-write + + + RF0FE + Rx FIFO 0 Full Interrupt Enable + [2:2] + read-write + + + RF0LE + Rx FIFO 0 Message Lost Interrupt Enable + [3:3] + read-write + + + RF1NE + Rx FIFO 1 New Message Interrupt Enable + [4:4] + read-write + + + RF1WE + Rx FIFO 1 Watermark Reached Interrupt Enable + [5:5] + read-write + + + RF1FE + Rx FIFO 1 Full Interrupt Enable + [6:6] + read-write + + + RF1LE + Rx FIFO 1 Message Lost Interrupt Enable + [7:7] + read-write + + + HPME + High Priority Message Interrupt Enable + [8:8] + read-write + + + TCE + Transmission Completed Interrupt Enable + [9:9] + read-write + + + TCFE + Transmission Cancellation Finished Interrupt Enable + [10:10] + read-write + + + TFEE + Tx FIFO Empty Interrupt Enable + [11:11] + read-write + + + TEFNE + Tx Event FIDO New Entry Interrupt Enable + [12:12] + read-write + + + TEFWE + Tx Event FIFO Watermark Reached Interrupt Enable + [13:13] + read-write + + + TEFFE + Tx Event FIFO Full Interrupt Enable + [14:14] + read-write + + + TEFLE + Tx Event FIFO Event Lost Interrupt Enable + [15:15] + read-write + + + TSWE + Timestamp Wraparound Interrupt Enable + [16:16] + read-write + + + MRAFE + Message RAM Access Failure Interrupt Enable + [17:17] + read-write + + + TOOE + Timeout Occurred Interrupt Enable + [18:18] + read-write + + + DRXE + Message stored to Dedicated Rx Buffer Interrupt Enable + [19:19] + read-write + + + BECE + Bit Error Corrected Interrupt Enable (not used in M_TTCAN) + [20:20] + read-write + + + BEUE + Bit Error Uncorrected Interrupt Enable + [21:21] + read-write + + + ELOE + Error Logging Overflow Interrupt Enable + [22:22] + read-write + + + EPE + Error Passive Interrupt Enable + [23:23] + read-write + + + EWE + Warning Status Interrupt Enable + [24:24] + read-write + + + BOE + Bus_Off Status Interrupt Enable + [25:25] + read-write + + + WDIE + Watchdog Interrupt Enable + [26:26] + read-write + + + PEAE + Protocol Error in Arbitration Phase Enable + [27:27] + read-write + + + PEDE + Protocol Error in Data Phase Enable + [28:28] + read-write + + + ARAE + N/A + [29:29] + read-write + + + + + ILS + Interrupt Line Select + 0x58 + 32 + read-write + 0x0 + 0x3FFFFFFF + + + RF0NL + Rx FIFO 0 New Message Interrupt Line + [0:0] + read-write + + + RF0WL + Rx FIFO 0 Watermark Reached Interrupt Line + [1:1] + read-write + + + RF0FL + Rx FIFO 0 Full Interrupt Line + [2:2] + read-write + + + RF0LL + Rx FIFO 0 Message Lost Interrupt Line + [3:3] + read-write + + + RF1NL + Rx FIFO 1 New Message Interrupt Line + [4:4] + read-write + + + RF1WL + Rx FIFO 1 Watermark Reached Interrupt Line + [5:5] + read-write + + + RF1FL + Rx FIFO 1 Full Interrupt Line + [6:6] + read-write + + + RF1LL + Rx FIFO 1 Message Lost Interrupt Line + [7:7] + read-write + + + HPML + High Priority Message Interrupt Line + [8:8] + read-write + + + TCL + Transmission Completed Interrupt Line + [9:9] + read-write + + + TCFL + Transmission Cancellation Finished Interrupt Line + [10:10] + read-write + + + TFEL + Tx FIFO Empty Interrupt Line + [11:11] + read-write + + + TEFNL + Tx Event FIFO New Entry Interrupt Line + [12:12] + read-write + + + TEFWL + Tx Event FIFO Watermark Reached Interrupt Line + [13:13] + read-write + + + TEFFL + Tx Event FIFO Full Interrupt Line + [14:14] + read-write + + + TEFLL + Tx Event FIFO Event Lost Interrupt Line + [15:15] + read-write + + + TSWL + Timestamp Wraparound Interrupt Line + [16:16] + read-write + + + MRAFL + Message RAM Access Failure Interrupt Line + [17:17] + read-write + + + TOOL + Timeout Occurred Interrupt Line + [18:18] + read-write + + + DRXL + Message stored to Dedicated Rx Buffer Interrupt Line + [19:19] + read-write + + + BECL + Bit Error Corrected Interrupt Line (not used in M_TTCAN) + [20:20] + read-write + + + BEUL + Bit Error Uncorrected Interrupt Line + [21:21] + read-write + + + ELOL + Error Logging Overflow Interrupt Line + [22:22] + read-write + + + EPL + Error Passive Interrupt Line + [23:23] + read-write + + + EWL + Warning Status Interrupt Line + [24:24] + read-write + + + BOL + Bus_Off Status Interrupt Line + [25:25] + read-write + + + WDIL + Watchdog Interrupt Line + [26:26] + read-write + + + PEAL + Protocol Error in Arbitration Phase Line + [27:27] + read-write + + + PEDL + Protocol Error in Data Phase Line + [28:28] + read-write + + + ARAL + N/A + [29:29] + read-write + + + + + ILE + Interrupt Line Enable + 0x5C + 32 + read-write + 0x0 + 0x3 + + + EINT0 + Enable Interrupt Line 0 +0= Interrupt line m_ttcan_int0 disabled +1= Interrupt line m_ttcan_int0 enabled + [0:0] + read-write + + + EINT1 + Enable Interrupt Line 1 +0= Interrupt line m_ttcan_int1 disabled +1= Interrupt line m_ttcan_int1 enabled + [1:1] + read-write + + + + + GFC + Global Filter Configuration + 0x80 + 32 + read-write + 0x0 + 0x3F + + + RRFE + Reject Remote Frames Extended +0= Filter remote frames with 29-bit extended IDs +1= Reject all remote frames with 29-bit extended IDs + [0:0] + read-write + + + RRFS + Reject Remote Frames Standard +0= Filter remote frames with 11-bit standard IDs +1= Reject all remote frames with 11-bit standard IDs + [1:1] + read-write + + + ANFE + Accept Non-matching Frames Extended +Defines how received messages with 29-bit IDs that do not match any element of the filter list are +treated. +00= Accept in Rx FIFO 0 +01= Accept in Rx FIFO 1 +10= Reject +11= Reject + [3:2] + read-write + + + ANFS + Accept Non-matching Frames Standard +Defines how received messages with 11-bit IDs that do not match any element of the filter list are +treated. +00= Accept in Rx FIFO 0 +01= Accept in Rx FIFO 1 +10= Reject +11= Reject + [5:4] + read-write + + + + + SIDFC + Standard ID Filter Configuration + 0x84 + 32 + read-write + 0x0 + 0xFFFFFC + + + FLSSA + Filter List Standard Start Address +Start address of standard Message ID filter list (32-bit word address, see Figure 2). + [15:2] + read-write + + + LSS + List Size Standard +0= No standard Message ID filter +1-128= Number of standard Message ID filter elements +128= Values greater than 128 are interpreted as 128 + [23:16] + read-write + + + + + XIDFC + Extended ID Filter Configuration + 0x88 + 32 + read-write + 0x0 + 0x7FFFFC + + + FLESA + Filter List Extended Start Address +Start address of extended Message ID filter list (32-bit word address, see Figure 2). + [15:2] + read-write + + + LSE + List Size Extended +0= No extended Message ID filter +1-64= Number of extended Message ID filter elements +64= Values greater than 64 are interpreted as 64 + [22:16] + read-write + + + + + XIDAM + Extended ID AND Mask + 0x90 + 32 + read-write + 0x0 + 0x1FFFFFFF + + + EIDM + Extended ID Mask +For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message +ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all +bits set to one the mask is not active. + [28:0] + read-write + + + + + HPMS + High Priority Message Status + 0x94 + 32 + read-only + 0x0 + 0xFFFF + + + BIDX + Buffer Index +Index of Rx FIFO element to which the message was stored. Only valid when MSI[1] = '1'. + [5:0] + read-only + + + MSI + Message Storage Indicator +00= No FIFO selected +01= FIFO message lost +10= Message stored in FIFO 0 +11= Message stored in FIFO 1 + [7:6] + read-only + + + FIDX + Filter Index +Index of matching filter element. Range is 0 to SIDFC.LSS - 1 resp. XIDFC.LSE - 1. + [14:8] + read-only + + + FLST + Filter List +Indicates the filter list of the matching filter element. +0= Standard Filter List +1= Extended Filter List + [15:15] + read-only + + + + + NDAT1 + New Data 1 + 0x98 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + ND + New Data +The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective +Rx Buffer has been updated from a received frame. The flags remain set until the Host clears them. +A flag is cleared by writing a '1' to the corresponding bit position. Writing a '0' has no effect. A hard +reset will clear the register. +0= Rx Buffer not updated +1= Rx Buffer updated from new message + [31:0] + read-write + + + + + NDAT2 + New Data 2 + 0x9C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + ND + New Data +The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective +Rx Buffer has been updated from a received frame. The flags remain set until the Host clears them. +A flag is cleared by writing a '1' to the corresponding bit position. Writing a '0' has no effect. A hard +reset will clear the register. +0= Rx Buffer not updated +1= Rx Buffer updated from new message + [31:0] + read-write + + + + + RXF0C + Rx FIFO 0 Configuration + 0xA0 + 32 + read-write + 0x0 + 0xFF7FFFFC + + + F0SA + Rx FIFO 0 Start Address +Start address of Rx FIFO 0 in Message RAM (32-bit word address, see Figure 2). + [15:2] + read-write + + + F0S + Rx FIFO 0 Size +0= No Rx FIFO 0 +1-64= Number of Rx FIFO 0 elements +64= Values greater than 64 are interpreted as 64 +The Rx FIFO 0 elements are indexed from 0 to F0S-1 + [22:16] + read-write + + + F0WM + Rx FIFO 0 Watermark +0= Watermark interrupt disabled +1-64= Level for Rx FIFO 0 watermark interrupt (IR.RF0W) +64= Watermark interrupt disabled + [30:24] + read-write + + + F0OM + FIFO 0 Operation Mode +FIFO 0 can be operated in blocking or in overwrite mode (see Section 3.4.2). +0= FIFO 0 blocking mode +1= FIFO 0 overwrite mode + [31:31] + read-write + + + + + RXF0S + Rx FIFO 0 Status + 0xA4 + 32 + read-only + 0x0 + 0x33F3F7F + + + F0FL + Rx FIFO 0 Fill Level +Number of elements stored in Rx FIFO 0, range 0 to 64. + [6:0] + read-only + + + F0GI + Rx FIFO 0 Get Index +Rx FIFO 0 read index pointer, range 0 to 63. +This field is updated by the software writing to RxF0A.F0AI + [13:8] + read-only + + + F0PI + Rx FIFO 0 Put Index +Rx FIFO 0 write index pointer, range 0 to 63. + [21:16] + read-only + + + F0F + Rx FIFO 0 Full +0= Rx FIFO 0 not full +1= Rx FIFO 0 full + [24:24] + read-only + + + RF0L + Rx FIFO 0 Message Lost +This bit is a copy of interrupt flag IR.RF0L. When IR.RF0L is reset, this bit is also reset. +0= No Rx FIFO 0 message lost +1= Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero + [25:25] + read-only + + + + + RXF0A + Rx FIFO 0 Acknowledge + 0xA8 + 32 + read-write + 0x0 + 0x3F + + + F0AI + Rx FIFO 0 Acknowledge Index +After the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the + buffer index of the last element read from Rx FIFO 0 to F0AI. This will set the Rx FIFO 0 Get Index + RXF0S.F0GI to F0AI + 1 and update the FIFO 0 Fill Level RXF0S.F0FL. + [5:0] + read-write + + + + + RXBC + Rx Buffer Configuration + 0xAC + 32 + read-write + 0x0 + 0xFFFC + + + RBSA + Rx Buffer Start Address +Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address). +Also used to reference debug messages A,B,C. + [15:2] + read-write + + + + + RXF1C + Rx FIFO 1 Configuration + 0xB0 + 32 + read-write + 0x0 + 0xFF7FFFFC + + + F1SA + Rx FIFO 1 Start Address +Start address of Rx FIFO 1 in Message RAM (32-bit word address, see Figure 2). + [15:2] + read-write + + + F1S + Rx FIFO 1 Size +0= No Rx FIFO 1 +1-64= Number of Rx FIFO 1 elements +64= Values greater than 64 are interpreted as 64 +The Rx FIFO 1 elements are indexed from 0 to F1S - 1 + [22:16] + read-write + + + F1WM + Rx FIFO 1 Watermark +0= Watermark interrupt disabled +1-64= Level for Rx FIFO 1 watermark interrupt (IR.RF1W) +64= Watermark interrupt disabled + [30:24] + read-write + + + F1OM + FIFO 1 Operation Mode +FIFO 1 can be operated in blocking or in overwrite mode (see Section 3.4.2). +0= FIFO 1 blocking mode +1= FIFO 1 overwrite mode + [31:31] + read-write + + + + + RXF1S + Rx FIFO 1 Status + 0xB4 + 32 + read-only + 0x0 + 0xC33F3F7F + + + F1FL + Rx FIFO 1 Fill Level +Number of elements stored in Rx FIFO 1, range 0 to 64. + [6:0] + read-only + + + F1GI + Rx FIFO 1 Get Index +Rx FIFO 1 read index pointer, range 0 to 63. +This field is updated by the software writing to RxF1A.FAI + [13:8] + read-only + + + F1PI + Rx FIFO 1 Put Index +Rx FIFO 1 write index pointer, range 0 to 63. + [21:16] + read-only + + + F1F + Rx FIFO 1 Full +0= Rx FIFO 1 not full +1= Rx FIFO 1 full + [24:24] + read-only + + + RF1L + Rx FIFO 1 Message Lost +This bit is a copy of interrupt flag IR.RF1L. When IR.RF1L is reset, this bit is also reset. +0= No Rx FIFO 1 message lost +1= Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero + [25:25] + read-only + + + DMS + Debug Message Status +00= Idle state, wait for reception of debug messages, DMA request is cleared +01= Debug message A received +10= Debug messages A, B received +11= Debug messages A, B, C received, DMA request is set + [31:30] + read-only + + + + + RXF1A + Rx FIFO 1 Acknowledge + 0xB8 + 32 + read-write + 0x0 + 0x3F + + + F1AI + Rx FIFO 1 Acknowledge Index +After the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the + buffer index of the last element read from Rx FIFO 1 to F1AI. This will set the Rx FIFO 1 Get Index + RXF1S.F1GI to F1AI + 1 and update the FIFO 1 Fill Level RXF1S.F1FL. + [5:0] + read-write + + + + + RXESC + Rx Buffer / FIFO Element Size Configuration + 0xBC + 32 + read-write + 0x0 + 0x777 + + + F0DS + N/A + [2:0] + read-write + + + F1DS + Rx FIFO 1 Data Field Size +000= 8 byte data field +001= 12 byte data field +010= 16 byte data field +011= 20 byte data field +100= 24 byte data field +101= 32 byte data field +110= 48 byte data field +111= 64 byte data field + [6:4] + read-write + + + RBDS + Rx Buffer Data Field Size +000= 8 byte data field +001= 12 byte data field +010= 16 byte data field +011= 20 byte data field +100= 24 byte data field +101= 32 byte data field +110= 48 byte data field +111= 64 byte data field + [10:8] + read-write + + + + + TXBC + Tx Buffer Configuration + 0xC0 + 32 + read-write + 0x0 + 0x7F3FFFFC + + + TBSA + Tx Buffers Start Address +Start address of Tx Buffers section in Message RAM (32-bit word address, see Figure 2). + [15:2] + read-write + + + NDTB + Number of Dedicated Transmit Buffers +0= No Dedicated Tx Buffers +1-32= Number of Dedicated Tx Buffers +32= Values greater than 32 are interpreted as 32 + [21:16] + read-write + + + TFQS + Transmit FIFO/Queue Size +0= No Tx FIFO/Queue +1-32= Number of Tx Buffers used for Tx FIFO/Queue +32= Values greater than 32 are interpreted as 32 + [29:24] + read-write + + + TFQM + Tx FIFO/Queue Mode +0= Tx FIFO operation +1= Tx Queue operation + [30:30] + read-write + + + + + TXFQS + Tx FIFO/Queue Status + 0xC4 + 32 + read-only + 0x0 + 0x3F1F3F + + + TFFL + Tx FIFO Free Level +Number of consecutive free Tx FIFO elements starting from TFGI, range 0 to 32. Read as zero when +Tx Queue operation is configured (TXBC.TFQM = '1') + [5:0] + read-only + + + TFGI + Tx FIFO Get Index +Tx FIFO read index pointer, range 0 to 31. Read as zero when Tx Queue operation is configured +TXBC.TFQM = '1'). + [12:8] + read-only + + + TFQPI + Tx FIFO/Queue Put Index +Tx FIFO/Queue write index pointer, range 0 to 31. + [20:16] + read-only + + + TFQF + Tx FIFO/Queue Full +0= Tx FIFO/Queue not full +1= Tx FIFO/Queue full + [21:21] + read-only + + + + + TXESC + Tx Buffer Element Size Configuration + 0xC8 + 32 + read-write + 0x0 + 0x7 + + + TBDS + Tx Buffer Data Field Size +000= 8 byte data field +001= 12 byte data field +010= 16 byte data field +011= 20 byte data field +100= 24 byte data field +101= 32 byte data field +110= 48 byte data field +111= 64 byte data field + [2:0] + read-write + + + + + TXBRP + Tx Buffer Request Pending + 0xCC + 32 + read-only + 0x0 + 0xFFFFFFFF + + + TRP + Transmission Request Pending +Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via register TXBAR. +The bits are reset after a requested transmission has completed or has been cancelled via register +TXBCR. +TXBRP bits are set only for those Tx Buffers configured via TXBC. After a TXBRP bit has been set, +a Tx scan (see Section 3.5, Tx Handling) is started to check for the pending Tx request with the +highest priority (Tx Buffer with lowest Message ID). +A cancellation request resets the corresponding transmission request pending bit of register +TXBRP. In case a transmission has already been started when a cancellation is requested, this is +done at the end of the transmission, regardless whether the transmission was successful or not. The +cancellation request bits are reset directly after the corresponding TXBRP bit has been reset. +After a cancellation has been requested, a finished cancellation is signaled via TXBCF +after successful transmission together with the corresponding TXBTO bit +when the transmission has not yet been started at the point of cancellation +when the transmission has been aborted due to lost arbitration +when an error occurred during frame transmission +In DAR mode all transmissions are automatically cancelled if they are not successful. The +corresponding TXBCF bit is set for all unsuccessful transmissions. +0= No transmission request pending +1= Transmission request pending + [31:0] + read-only + + + + + TXBAR + Tx Buffer Add Request + 0xD0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + AR + Add Request +Each Tx Buffer has its own Add Request bit. Writing a '1' will set the corresponding Add Request +bit; writing a '0' has no impact. This enables the Host to set transmission requests for multiple Tx +Buffers with one write to TXBAR. TXBAR bits are set only for those Tx Buffers configured via TXBC. +When no Tx scan is running, the bits are reset immediately, else the bits remain set until the Tx scan +process has completed. +0= No transmission request added +1= Transmission requested added + [31:0] + read-write + + + + + TXBCR + Tx Buffer Cancellation Request + 0xD4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + CR + Cancellation Request +Each Tx Buffer has its own Cancellation Request bit. Writing a '1' will set the corresponding +Cancellation Request bit; writing a '0' has no impact. This enables the Host to set cancellation +requests for multiple Tx Buffers with one write to TXBCR. TXBCR bits are set only for those Tx +Buffers configured via TXBC. The bits remain set until the corresponding bit of TXBRP is reset. +0= No cancellation pending +1= Cancellation pending + [31:0] + read-write + + + + + TXBTO + Tx Buffer Transmission Occurred + 0xD8 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + TO + Transmission Occurred +Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding +TXBRP bit is cleared after a successful transmission. The bits are reset when a new transmission +is requested by writing a '1' to the corresponding bit of register TXBAR. +0= No transmission occurred +1= Transmission occurred + [31:0] + read-only + + + + + TXBCF + Tx Buffer Cancellation Finished + 0xDC + 32 + read-only + 0x0 + 0xFFFFFFFF + + + CF + Cancellation Finished +Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding +TXBRP bit is cleared after a cancellation was requested via TXBCR. In case the corresponding +TXBRP bit was not set at the point of cancellation, CF is set immediately. The bits are reset when a +new transmission is requested by writing a '1' to the corresponding bit of register TXBAR. +0= No transmit buffer cancellation +1= Transmit buffer cancellation finished + [31:0] + read-only + + + + + TXBTIE + Tx Buffer Transmission Interrupt Enable + 0xE0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + TIE + Transmission Interrupt Enable +Each Tx Buffer has its own Transmission Interrupt Enable bit. +0= Transmission interrupt disabled +1= Transmission interrupt enable + [31:0] + read-write + + + + + TXBCIE + Tx Buffer Cancellation Finished Interrupt Enable + 0xE4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + CFIE + Cancellation Finished Interrupt Enable +Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. +0= Cancellation finished interrupt disabled +1= Cancellation finished interrupt enabled + [31:0] + read-write + + + + + TXEFC + Tx Event FIFO Configuration + 0xF0 + 32 + read-write + 0x0 + 0x3F3FFFFC + + + EFSA + Event FIFO Start Address +Start address of Tx Event FIFO in Message RAM (32-bit word address, see Figure 2). + [15:2] + read-write + + + EFS + Event FIFO Size +0= Tx Event FIFO disabled +1-32= Number of Tx Event FIFO elements +32= Values greater than 32 are interpreted as 32 +The Tx Event FIFO elements are indexed from 0 to EFS-1 + [21:16] + read-write + + + EFWM + Event FIFO Watermark +0= Watermark interrupt disabled +1-32= Level for Tx Event FIFO watermark interrupt (IR.TEFW) +32= Watermark interrupt disabled + [29:24] + read-write + + + + + TXEFS + Tx Event FIFO Status + 0xF4 + 32 + read-only + 0x0 + 0x31F1F3F + + + EFFL + Event FIFO Fill Level +Number of elements stored in Tx Event FIFO, range 0 to 32. + [5:0] + read-only + + + EFGI + Event FIFO Get Index +Tx Event FIFO read index pointer, range 0 to 31. + [12:8] + read-only + + + EFPI + Event FIFO Put Index +Tx Event FIFO write index pointer, range 0 to 31. + [20:16] + read-only + + + EFF + Event FIFO Full +0= Tx Event FIFO not full +1= Tx Event FIFO full + [24:24] + read-only + + + TEFL + Tx Event FIFO Element Lost +This bit is a copy of interrupt flag IR.TEFL. When IR.TEFL is reset, this bit is also reset. +0= No Tx Event FIFO element lost +1= Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero. + [25:25] + read-only + + + + + TXEFA + Tx Event FIFO Acknowledge + 0xF8 + 32 + read-write + 0x0 + 0x1F + + + EFAI + Event FIFO Acknowledge Index +After the Host has read an element or a sequence of elements from the Tx Event FIFO it has to write +the index of the last element read from Tx Event FIFO to EFAI. This will set the Tx Event FIFO Get +Index TXEFS.EFGI to EFAI + 1 and update the Event FIFO Fill Level TXEFS.EFFL. + [4:0] + read-write + + + + + TTTMC + TT Trigger Memory Configuration + 0x100 + 32 + read-write + 0x0 + 0x7FFFFC + + + TMSA + Trigger Memory Start Address +Start address of Trigger Memory in Message RAM (32-bit word address, see Figure 2). + [15:2] + read-write + + + TME + Trigger Memory Elements +0= No Trigger Memory +1-64= Number of Trigger Memory elements +64= Values greater than 64 are interpreted as 64 + [22:16] + read-write + + + + + TTRMC + TT Reference Message Configuration + 0x104 + 32 + read-write + 0x0 + 0xDFFFFFFF + + + RID + Reference Identifier +Identifier transmitted with reference message and used for reference message filtering. Standard or +extended reference identifier depending on bit XTD. A standard identifier has to be written to +ID[28:18]. + [28:0] + read-write + + + XTD + Extended Identifier +0= 11-bit standard identifier +1= 29-bit extended identifier + [30:30] + read-write + + + RMPS + Reference Message Payload Select +Ignored in case of time slaves. +0= Reference message has no additional payload +1= The following elements are taken from Tx Buffer 0: +Message Marker MM, Event FIFO Control EFC, Data Length Code DLC, Data Bytes DB +Level 1: bytes 2-8, Level 0,2: bytes 5-8) + [31:31] + read-write + + + + + TTOCF + TT Operation Configuration + 0x108 + 32 + read-write + 0x10000 + 0x7FFFFFB + + + OM + Operation Mode +00= Event-driven CAN communication, default +01= TTCAN level 1 +10= TTCAN level 2 +11= TTCAN level 0 + [1:0] + read-write + + + GEN + Gap Enable +0= Strictly time-triggered operation +1= External event-synchronized time-triggered operation + [3:3] + read-write + + + TM + Time Master +0= Time Master function disabled +1= Potential Time Master + [4:4] + read-write + + + LDSDL + LD of Synchronization Deviation Limit +The Synchronization Deviation Limit SDL is configured by its dual logarithm LDSDL with SDL = +2(LDSDL + 5). It should not exceed the clock tolerance given by the CAN bit timing configuration. +0x0-7 LD of Synchronization Deviation Limit (SDL <= 32...4096) + [7:5] + read-write + + + IRTO + Initial Reference Trigger Offset +0x00-7F Positive offset, range from 0 to 127 + [14:8] + read-write + + + EECS + Enable External Clock Synchronization +If enabled, TUR configuration (TURCF.NCL only) may be updated during TTCAN operation. +0= External clock synchronization in TTCAN Level 0,2 disabled +1= External clock synchronization in TTCAN Level 0,2 enabled + [15:15] + read-write + + + AWL + Application Watchdog Limit +The application watchdog can be disabled by programming AWL to 0x00. +0x00-FF Maximum time after which the application has to serve the application watchdog. +The application watchdog is incremented once each 256 NTUs. + [23:16] + read-write + + + EGTF + Enable Global Time Filtering +0= Global time filtering in TTCAN Level 0,2 is disabled +1= Global time filtering in TTCAN Level 0,2 is enabled + [24:24] + read-write + + + ECC + Enable Clock Calibration +0= Automatic clock calibration in TTCAN Level 0,2 is disabled +1= Automatic clock calibration in TTCAN Level 0,2 is enabled + [25:25] + read-write + + + EVTP + Event Trigger Polarity +0= Rising edge trigger +1= Falling edge trigger + [26:26] + read-write + + + + + TTMLM + TT Matrix Limits + 0x10C + 32 + read-write + 0x0 + 0xFFF0FFF + + + CCM + N/A + [5:0] + read-write + + + CSS + N/A + [7:6] + read-write + + + TXEW + Tx Enable Window +0x0-F Length of Tx enable window, 1-16 NTU cycles + [11:8] + read-write + + + ENTT + Expected Number of Tx Triggers +0x000-FFF Expected number of Tx Triggers in one Matrix Cycle + [27:16] + read-write + + + + + TURCF + TUR Configuration + 0x110 + 32 + read-write + 0x10000000 + 0xBFFFFFFF + + + NCL + Numerator Configuration Low +Write access to the TUR Numerator Configuration Low is only possible during configuration with +TURCF.ELT = '0' or if TTOCF.EECS (external clock synchronization enabled) is set. When a new +value for NCL is written outside TT Configuration Mode, the new value takes effect when +TTOST.WECS is cleared to '0'. NCL is locked TTOST.WECS is '1'. +0x0000-FFFF Numerator Configuration Low + [15:0] + read-write + + + DC + Denominator Configuration +0x0000 Illegal value +0x0001-3FFF Denominator Configuration + [29:16] + read-write + + + ELT + Enable Local Time +0= Local time is stopped, default +1= Local time is enabled + [31:31] + read-write + + + + + TTOCN + TT Operation Control + 0x114 + 32 + read-write + 0x0 + 0xBFFF + + + SGT + Set Global time +Writing a '1' to SGT sets TTOST.WGDT if the node is the actual Time Master. SGT is reset after one +Host clock period. The global time preset takes effect when the node transmits the next reference +message with the Master_Ref_Mark modified by the preset value written to TTGTP. + [0:0] + read-write + + + ECS + External Clock Synchronization +Writing a '1' to ECS sets TTOST.WECS if the node is the actual Time Master. ECS is reset after one +Host clock period. The external clock synchronization takes effect at the start of the next basic cycle. + [1:1] + read-write + + + SWP + Stop Watch Polarity +0= Rising edge trigger +1= Falling edge trigger + [2:2] + read-write + + + SWS + Stop Watch Source +00= Stop Watch disabled +01= Actual value of cycle time is copied to TTCPT.SWV +10= Actual value of local time is copied to TTCPT.SWV +11= Actual value of global time is copied to TTCPT.SWV + [4:3] + read-write + + + RTIE + Register Time Mark Interrupt Pulse Enable +Register time mark interrupts are configured by register TTTMK. A register time mark interrupt pulse +with the length of one NTU is generated when the time referenced by TTOCN.TMC (cycle, local, or +global) equals TTTMK.TM, independent of the synchronization state. +0= Register Time Mark Interrupt output m_ttcan_rtp disabled +1= Register Time Mark Interrupt output m_ttcan_rtp enabled + [5:5] + read-write + + + TMC + Register Time Mark Compare +00= No Register Time Mark Interrupt generated +01= Register Time Mark Interrupt if Time Mark = cycle time +10= Register Time Mark Interrupt if Time Mark = local time +11= Register Time Mark Interrupt if Time Mark = global time + [7:6] + read-write + + + TTIE + Trigger Time Mark Interrupt Pulse Enable +External time mark events are configured by trigger memory element TMEX (see Section 2.4.7). A +trigger time mark interrupt pulse is generated when the trigger memory element becomes active, +and the M_TTCAN is in synchronization state In_Schedule or In_Gap. +0= Trigger Time Mark Interrupt output m_ttcan_tmp disabled +1= Trigger Time Mark Interrupt output m_ttcan_tmp enabled + [8:8] + read-write + + + GCS + Gap Control Select +0= Gap control independent from m_ttcan_evt +1= Gap control by input pin m_ttcan_evt + [9:9] + read-write + + + FGP + Finish Gap +Set by the CPU, reset by each reference message +0= No reference message requested +1= Application requested start of reference message + [10:10] + read-write + + + TMG + Time Mark Gap +0= Reset by each reference message +1= Next reference message started when Register Time Mark interrupt TTIR.RTMI is activated + [11:11] + read-write + + + NIG + Next is Gap +This bit can only be set when the M_TTCAN is the actual Time Master and when it is configured for +external event-synchronized time-triggered operation (TTOCF.GEN = '1') +0= No action, reset by reception of any reference message +1= Transmit next reference message with Next_is_Gap = '1' + [12:12] + read-write + + + ESCN + External Synchronization Control +If enabled the M_TTCAN synchronizes its cycle time phase to an external event signaled by a rising +edge at pin m_ttcan_evt (see Section 4.11). +0= External synchronization disabled +1= External synchronization enabled + [13:13] + read-write + + + LCKC + TT Operation Control Register Locked +Set by a write access to register TTOCN. Reset when the updated configuration has been +synchronized into the CAN clock domain. +0= Write access to TTOCN enabled +1= Write access to TTOCN locked + [15:15] + read-only + + + + + TTGTP + TT Global Time Preset + 0x118 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + TP + N/A + [15:0] + read-write + + + CTP + Cycle Time Target Phase +CTP is write-protected while TTOCN.ESCN or TTOST.SPL are set (see Section 4.11). +0x0000-FFFF Defines target value of cycle time when a rising edge of m_ttcan_evt is expected + [31:16] + read-write + + + + + TTTMK + TT Time Mark + 0x11C + 32 + read-write + 0x0 + 0x807FFFFF + + + TM_ + Time Mark +0x0000-FFFF Time Mark + [15:0] + read-write + + + TICC + Time Mark Cycle Code +Cycle count for which the time mark is valid. +0b000000x valid for all cycles +0b000001c valid every second cycle at cycle count mod2 = c +0b00001cc valid every fourth cycle at cycle count mod4 = cc +0b0001ccc valid every eighth cycle at cycle count mod8 = ccc +0b001cccc valid every sixteenth cycle at cycle count mod16 = cccc +0b01ccccc valid every thirty-second cycle at cycle count mod32 = ccccc +0b1cccccc valid every sixty-fourth cycle at cycle count mod64 = cccccc + [22:16] + read-write + + + LCKM + TT Time Mark Register Locked +Always set by a write access to registers TTOCN. Set by write access to register TTTMK when +TTOCN.TMC != '00'. Reset when the registers have been synchronized into the CAN clock domain. +0= Write access to TTTMK enabled +1= Write access to TTTMK locked + [31:31] + read-only + + + + + TTIR + TT Interrupt Register + 0x120 + 32 + read-write + 0x0 + 0x7FFFF + + + SBC + Start of Basic Cycle +0= No Basic Cycle started since bit has been reset +1= Basic Cycle started + [0:0] + read-write + + + SMC + Start of Matrix Cycle +0= No Matrix Cycle started since bit has been reset +1= Matrix Cycle started + [1:1] + read-write + + + CSM_ + Change of Synchronization Mode +0= No change in master to slave relation or schedule synchronization +1= Master to slave relation or schedule synchronization changed, +also set when TTOST.SPL is reset + [2:2] + read-write + + + SOG + Start of Gap +0= No reference message seen with Next_is_Gap bit set +1= Reference message with Next_is_Gap bit set becomes valid + [3:3] + read-write + + + RTMI + Register Time Mark Interrupt +Set when time referenced by TTOCN.TMC (cycle, local, or global) equals TTTMK.TM, independent +of the synchronization state. +0= Time mark not reached +1= Time mark reached + [4:4] + read-write + + + TTMI + Trigger Time Mark Event Internal +Internal time mark events are configured by trigger memory element TMIN (see Section 2.4.7). Set +when the trigger memory element becomes active, and the M_TTCAN is in synchronization state +In_Gap or In_Schedule. +0= Time mark not reached +1= Time mark reached (Level 0: cycle time TTOCF.IRTO * 0x200) + [5:5] + read-write + + + SWE + Stop Watch Event +0= No rising/falling edge at stop watch trigger pin m_ttcan_swt detected +1= Rising/falling edge at stop watch trigger pin m_ttcan_swt detected + [6:6] + read-write + + + GTW + Global Time Wrap +0= No global time wrap occurred +1= Global time wrap from 0xFFFF to 0x0000 occurred + [7:7] + read-write + + + GTD + Global Time Discontinuity +0= No discontinuity of global time +1= Discontinuity of global time + [8:8] + read-write + + + GTE + Global Time Error +Synchronization deviation SD exceeds limit specified by TTOCF.LDSDL, TTCAN Level 0,2 only. +0= Synchronization deviation within limit +1= Synchronization deviation exceeded limit + [9:9] + read-write + + + TXU + Tx Count Underflow +0= Number of Tx Trigger as expected +1= Less Tx trigger than expected in one matrix cycle + [10:10] + read-write + + + TXO + Tx Count Overflow +0= Number of Tx Trigger as expected +1= More Tx trigger than expected in one matrix cycle + [11:11] + read-write + + + SE1 + Scheduling Error 1 +0= No scheduling error 1 +1= Scheduling error 1 occurred + [12:12] + read-write + + + SE2 + Scheduling Error 2 +0= No scheduling error 2 +1= Scheduling error 2 occurred + [13:13] + read-write + + + ELC + Error Level Changed +Not set when error level changed during initialization. +0= No change in error level +1= Error level changed + [14:14] + read-write + + + IWT + Initialization Watch Trigger +The initialization is restarted by resetting IWT. +0= No missing reference message during system startup +1= No system startup due to missing reference message + [15:15] + read-write + + + WT + Watch Trigger +0= No missing reference message +1= Missing reference message (Level 0: cycle time 0xFF00) + [16:16] + read-write + + + AW + Application Watchdog +0= Application watchdog served in time +1= Application watchdog not served in time + [17:17] + read-write + + + CER + Configuration Error +Trigger out of order. +0= No error found in trigger list +1= Error found in trigger list + [18:18] + read-write + + + + + TTIE + TT Interrupt Enable + 0x124 + 32 + read-write + 0x0 + 0x7FFFF + + + SBCE + Start of Basic Cycle Interrupt Enable + [0:0] + read-write + + + SMCE + Start of Matrix Cycle Interrupt Enable + [1:1] + read-write + + + CSME + Change of Synchronization Mode Interrupt Enable + [2:2] + read-write + + + SOGE + Start of Gap Interrupt Enable + [3:3] + read-write + + + RTMIE + Register Time Mark Interrupt Enable + [4:4] + read-write + + + TTMIE + Trigger Time Mark Event Internal Enable + [5:5] + read-write + + + SWEE + Stop Watch Event Interrupt Enable + [6:6] + read-write + + + GTWE + Global Time Wrap Interrupt Enable + [7:7] + read-write + + + GTDE + Global Time Discontinuity Interrupt Enable + [8:8] + read-write + + + GTEE + Global Time Error Interrupt Enable + [9:9] + read-write + + + TXUE + Tx Count Underflow Interrupt Enable + [10:10] + read-write + + + TXOE + Tx Count Overflow Interrupt Enable + [11:11] + read-write + + + SE1E + Scheduling Error 1 Interrupt Enable + [12:12] + read-write + + + SE2E + Scheduling Error 2 Interrupt Enable + [13:13] + read-write + + + ELCE + Change Error Level Interrupt Enable + [14:14] + read-write + + + IWTE + Initialization Watch Trigger Interrupt Enable + [15:15] + read-write + + + WTE + Watch Trigger Interrupt Enable + [16:16] + read-write + + + AWE_ + Application Watchdog Interrupt Enable + [17:17] + read-write + + + CERE + Configuration Error Interrupt Enable + [18:18] + read-write + + + + + TTILS + TT Interrupt Line Select + 0x128 + 32 + read-write + 0x0 + 0x7FFFF + + + SBCL + Start of Basic Cycle Interrupt Line + [0:0] + read-write + + + SMCL + Start of Matrix Cycle Interrupt Line + [1:1] + read-write + + + CSML + Change of Synchronization Mode Interrupt Line + [2:2] + read-write + + + SOGL + Start of Gap Interrupt Line + [3:3] + read-write + + + RTMIL + Register Time Mark Interrupt Line + [4:4] + read-write + + + TTMIL + Trigger Time Mark Event Internal Line + [5:5] + read-write + + + SWEL + Stop Watch Event Interrupt Line + [6:6] + read-write + + + GTWL + Global Time Wrap Interrupt Line + [7:7] + read-write + + + GTDL + Global Time Discontinuity Interrupt Line + [8:8] + read-write + + + GTEL + Global Time Error Interrupt Line + [9:9] + read-write + + + TXUL + Tx Count Underflow Interrupt Line + [10:10] + read-write + + + TXOL + Tx Count Overflow Interrupt Line + [11:11] + read-write + + + SE1L + Scheduling Error 1 Interrupt Line + [12:12] + read-write + + + SE2L + Scheduling Error 2 Interrupt Line + [13:13] + read-write + + + ELCL + Change Error Level Interrupt Line + [14:14] + read-write + + + IWTL + Initialization Watch Trigger Interrupt Line + [15:15] + read-write + + + WTL + Watch Trigger Interrupt Line + [16:16] + read-write + + + AWL_ + Application Watchdog Interrupt Line + [17:17] + read-write + + + CERL + Configuration Error Interrupt Line + [18:18] + read-write + + + + + TTOST + TT Operation Status + 0x12C + 32 + read-only + 0x0 + 0xFFC0FFFF + + + EL + Error Level +00= Severity 0 - No Error +01= Severity 1 - Warning +10= Severity 2 - Error +11= Severity 3 - Severe Error + [1:0] + read-only + + + MS + Master State +00= Master_Off, no master properties relevant +01= Operating as Time Slave +10= Operating as Backup Time Master +11= Operating as current Time Master + [3:2] + read-only + + + SYS + Synchronization State +00= Out of Synchronization +01= Synchronizing to TTCAN communication +10= Schedule suspended by Gap (In_Gap) +11= Synchronized to schedule (In_Schedule) + [5:4] + read-only + + + QGTP + Quality of Global Time Phase +Only relevant in TTCAN Level 0 and Level 2, otherwise fixed to '0'. +0= Global time not valid +1= Global time in phase with Time Master + [6:6] + read-only + + + QCS + Quality of Clock Speed +Only relevant in TTCAN Level 0 and Level 2, otherwise fixed to '1'. +0= Local clock speed not synchronized to Time Master clock speed +1= Synchronization Deviation <= SDL + [7:7] + read-only + + + RTO + Reference Trigger Offset +The Reference Trigger Offset value is a signed integer with a range from -127 (0x81) to 127 (0x7F). +There is no notification when the lower limit of -127 is reached. In case the M_TTCAN becomes +Time Master (MS[1:0] = '11'), the reset of RTO is delayed due to synchronization between Host and +CAN clock domain. For time slaves the value configured by TTOCF.IRTO is read. +0x00-FF Actual Reference Trigger offset value + [15:8] + read-only + + + WGTD + Wait for Global Time Discontinuity +0= No global time preset pending +1= Node waits for the global time preset to take effect. The bit is reset when the node has transmitted +a reference message with Disc_Bit = '1' or after it received a reference message. + [22:22] + read-only + + + GFI + Gap Finished Indicator +Set when the CPU writes TTOCN.FGP, or by a time mark interrupt if TMG = '1', or via input pin +m_ttcan_evt if TTOCN.GCS = '1'. Not set by Ref_Trigger_Gap or when Gap is finished by another +node sending a reference message. +0= Reset at the end of each reference message +1= Gap finished by M_TTCAN + [23:23] + read-only + + + TMP + Time Master Priority +0x0-7 Priority of actual Time Master + [26:24] + read-only + + + GSI + Gap Started Indicator +0= No Gap in schedule, reset by each reference message and for all time slaves +1= Gap time after Basic Cycle has started + [27:27] + read-only + + + WFE + Wait for Event +0= No Gap announced, reset by a reference message with Next_is_Gap = '0' +1= Reference message with Next_is_Gap = '1' received + [28:28] + read-only + + + AWE + Application Watchdog Event +The application watchdog is served by reading TTOST. When the watchdog is not served in time, +bit AWE is set, all TTCAN communication is stopped, and the M_TTCAN is set into Bus Monitoring +Mode. +0= Application Watchdog served in time +1= Failed to serve Application Watchdog in time + [29:29] + read-only + + + WECS + Wait for External Clock Synchronization +0= No external clock synchronization pending +1= Node waits for external clock synchronization to take effect. The bit is reset at the start of the +next basic cycle. + [30:30] + read-only + + + SPL + Schedule Phase Lock +The bit is valid only when external synchronization is enabled (TTOCN.ESCN = '1'). In this case it +signals that the difference between cycle time configured by TTGTP.CTP and the cycle time at the +rising edge at pin m_ttcan_evt is less or equal 9 NTU (see Section 4.11). +0= Phase outside range +1= Phase inside range + [31:31] + read-only + + + + + TURNA + TUR Numerator Actual + 0x130 + 32 + read-only + 0x10000 + 0x3FFFF + + + NAV + N/A + [17:0] + read-only + + + + + TTLGT + TT Local & Global Time + 0x134 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + LT + Local Time +Non-fractional part of local time, incremented once each local NTU (see Section 4.5). +0x0000-FFFF Local time value of TTCAN node + [15:0] + read-only + + + GT + Global Time +Non-fractional part of the sum of the node's local time and its local offset (see Section 4.5). +0x0000-FFFF Global time value of TTCAN network + [31:16] + read-only + + + + + TTCTC + TT Cycle Time & Count + 0x138 + 32 + read-only + 0x3F0000 + 0x3FFFFF + + + CT + Cycle Time +Non-fractional part of the difference of the node's local time and Ref_Mark (see Section 4.5). +0x0000-FFFF Cycle time value of TTCAN Basic Cycle + [15:0] + read-only + + + CC + Cycle Count +0x00-3F Number of actual Basic Cycle in the System Matrix + [21:16] + read-only + + + + + TTCPT + TT Capture Time + 0x13C + 32 + read-only + 0x0 + 0xFFFF003F + + + CCV + Cycle Count Value +Cycle count value captured together with SWV. +0x00-3F Captured cycle count value + [5:0] + read-only + + + SWV + Stop Watch Value +On a rising/falling edge (as configured via TTOCN.SWP) at the Stop Watch Trigger pin m_ttcan_swt, when TTOCN.SWS is != '00' and TTIR.SWE is '0', the actual time value as selected +by TTOCN.SWS (cycle, local, global) is copied to SWV and TTIR.SWE will be set to '1'. Capturing of the next stop watch value is enabled by resetting TTIR.SWE. +0x0000-FFFF Captured Stop Watch value + [31:16] + read-only + + + + + TTCSM + TT Cycle Sync Mark + 0x140 + 32 + read-only + 0x0 + 0xFFFF + + + CSM + Cycle Sync Mark +The Cycle Sync Mark is measured + [15:0] + read-only + + + + + + RXFTOP_CTL + Receive FIFO Top control + 0x180 + 32 + read-write + 0x0 + 0x3 + + + F0TPE + FIFO 0 Top Pointer Enable. +This enables the FIFO top pointer logic to set the FIFO Top Address (FnTA) and message word counter. +This logic is also disabled when the IP is being reconfigured (CCCR.CCE=1). +When this logic is disabled a Read from RXFTOP0_DATA is undefined. + [0:0] + read-write + + + F1TPE + FIFO 1 Top Pointer Enable. + [1:1] + read-write + + + + + RXFTOP0_STAT + Receive FIFO 0 Top Status + 0x1A0 + 32 + read-only + 0x0 + 0xFFFF + + + F0TA + Current FIFO 0 Top Address. +This is a pointer to the next word in the message buffer defined by the FIFO Start Address (FnSA), Get Index (FnGI), the FIFO message size (FnDS) and the message word counter (FnMWC) +FnTA = FnSA + FnGI * msg_size[FnDS] + FnMWC + [15:0] + read-only + + + + + RXFTOP0_DATA + Receive FIFO 0 Top Data + 0x1A8 + 32 + read-only + 0x0 + 0x0 + + + F0TD + When enabled (F0TPE=1) read data from MRAM at location FnTA. This register can have a read side effect if the following conditions are met: +- M_TTCAN not being reconfigured (CCCR.CCE=0) +- FIFO Top Pointer logic is enabled (FnTPE=1) +- FIFO is not empty (FnFL!=0) +The read side effect is as follows: +- if FnMWC pointed to the last word of the message (as indicated by FnDS) then the corresponding message index (FnGI) is automatically acknowledge by a write to FnAI +- FnMWC is incremented (or restarted if FnMWC pointed to the last word of the message) +- the FIFO top address FnTA is incremented (with FIFO wrap around) +When this logic is disabled (F0TPE=0) a Read from this register returns undefined data. + [31:0] + read-only + + + + + RXFTOP1_STAT + Receive FIFO 1 Top Status + 0x1B0 + 32 + read-only + 0x0 + 0xFFFF + + + F1TA + See F0TA description + [15:0] + read-only + + + + + RXFTOP1_DATA + Receive FIFO 1 Top Data + 0x1B8 + 32 + read-only + 0x0 + 0x0 + + + F1TD + See F0TD description + [31:0] + read-only + + + + + + CTL + Global CAN control register + 0x1000 + 32 + read-write + 0x0 + 0x800000FF + + + STOP_REQ + Clock Stop Request for each TTCAN IP . +The m_ttcan_clkstop_req of each TTCAN IP is directly driven by these bits. + [7:0] + read-write + + + MRAM_OFF + MRAM off +'0': Default MRAM on (with MRAM retained in DeepSleep). +'1': Switch MRAM off (not retained) to save power. Before setting this bit all the CAN channels have to be powered down using the STOP_REQ/ACK bits. +When the MRAM is off any access attempt to it is considered an address error (as if MRAM_SIZE=0). +After switching the MRAM on again software needs to allow for a certain power up time before MRAM can be used, i.e. before STOP_REQ can be de-asserted. The power up time is equivalent to the system SRAM power up time specified in the CPUSS.RAM_PWR_DELAY_CTL register. + +To meet S8 platform requirements, MRAM_OFF should be set to 0 prior to transitioning to Hibernate mode. + [31:31] + read-write + + + + + STATUS + Global CAN status register + 0x1004 + 32 + read-only + 0x0 + 0xFF + + + STOP_ACK + Clock Stop Acknowledge for each TTCAN IP. +These bits are directly driven by m_ttcan_clkstop_ack of each TTCAN IP. +When this bit is set the corresponding TTCAN IP clocks will be gated off, except HCLK will enabled for each AHB write + [7:0] + read-only + + + + + INTR0_CAUSE + Consolidated interrupt0 cause register + 0x1010 + 32 + read-only + 0x0 + 0xFF + + + INT0 + Show pending m_ttcan_int0 of each channel + [7:0] + read-only + + + + + INTR1_CAUSE + Consolidated interrupt1 cause register + 0x1014 + 32 + read-only + 0x0 + 0xFF + + + INT1 + Show pending m_ttcan_int1 of each channel + [7:0] + read-only + + + + + TS_CTL + Time Stamp control register + 0x1020 + 32 + read-write + 0x0 + 0x8000FFFF + + + PRESCALE + Time Stamp counter prescale value. +When enabled divide the Host clock (HCLK) by PRESCALE+1 to create Time Stamp clock ticks. + [15:0] + read-write + + + ENABLED + Counter enable bit +0 = Count disabled. Stop counting up and keep the counter value +1 = Count enabled. Start counting up from the current value + [31:31] + read-write + + + + + TS_CNT + Time Stamp counter value + 0x1024 + 32 + read-write + 0x0 + 0xFFFF + + + VALUE + The counter value of the Time Stamp Counter. +When enabled this counter will count Time Stamp clock ticks from the pre-scaler. +When written this counter and the pre-scaler will reset to 0 (write data is ignored). + [15:0] + read-write + + + + + ECC_CTL + ECC control + 0x1080 + 32 + read-write + 0x0 + 0x10000 + + + ECC_EN + Enable ECC for CANFD SRAM +When disabled also all error injection functionality is disabled. + [16:16] + read-write + + + + + ECC_ERR_INJ + ECC error injection + 0x1084 + 32 + read-write + 0xFFFC + 0x7F10FFFC + + + ERR_ADDR + Specifies the address of the word where an error will be injected on write or an non-correctable error will be suppressed. +When the ERR_EN bit is set an error parity (ERR_PAR) is injected when any write, from bus or a CAN channel, is done to this address. +When the ERR_EN bit is set and the access address matches ERR_ADDR then a non-correctable ECC error or an Address error will NOT result in a bus error or CAN channel shutdown. +Note that error reporting to the fault structure cannot be suppressed. + [15:2] + read-write + + + ERR_EN + Enable error injection (ECC_EN must be 1). +When this bit is set the error parity (ERR_PAR) will be used when an AHB write is done to the ERR_ADDR address. +When the error word is read a single or double error will be reported to the fault structure just like for a real ECC error (even if this bit is no longer set). +When this bit is set (and ECC_EN=1) a non-correctable error (ECC or address error) for the ERR_ADDR will not be reported back to the CAN channel or AHB bus. + [20:20] + read-write + + + ERR_PAR + ECC Parity bits to use for ECC error injection at address ERR_ADDR. + [30:24] + read-write + + + + + + + SCB0 + Serial Communications Block (SPI/UART/I2C) + SCB + 0x40600000 + + 0 + 65536 + registers + + + + CTRL + Generic control + 0x0 + 32 + read-write + 0x300000F + 0x83031F0F + + + OVS + N/A + [3:0] + read-write + + + EC_AM_MODE + This field specifies the clocking for the address matching (I2C slave) or slave selection detection logic (SPI slave) +'0': Internally clocked mode +'1': Externally clocked mode + +In internally clocked mode the address detection(and slave selection detection) is done by clk_scb, and thus won't be done in deep sleep power mode as clk_scb isn't active. +In externally clocked mode the address detection is done by the I2C/SPI interface clock. This allows for the device to be awoken on I2C salve address match and SPI slave select assertion. + +The clocking for the rest of the logic is determined by CTRL.EC_OP_MODE. + +Externally clocked mode is only used for synchronous serial interface protocols (SPI and I2C) in slave mode. In SPI mode, only Motorola submode (all Motorola modes: 0, 1, 2, 3) is supported. + +In UART mode this field must be '0'. + [8:8] + read-write + + + EC_OP_MODE + This field specifies the clocking for the SCB block after the address phase +'0': Internally clocked mode +'1': externally clocked mode + +In internally clocked mode, the serial interface protocols run off the clk_scb. In externally clocked mode, the serial interface protocols run off the clock as provided by the serial interface. + +Externally clocked operation mode is only used for synchronous serial interface protocols (SPI and I2C) in slave mode. In SPI mode, only Motorola submode (all Motorola modes: 0, 1, 2, 3) is supported. + +In UART mode this field must be '0'. + [9:9] + read-write + + + EZ_MODE + This field determines if EZ mode is enabled or disabled for the SCB block +'0': EZ Mode Disabled +'1': EZ Mode Enabled + +In EZ mode, a meta protocol is applied to the serial interface protocol. This meta protocol adds meaning to the data frames transferred by the serial interface protocol: a data frame can represent a memory address, a write memory data element or a read memory data element. + +EZ mode can only be used for synchronous serial interface protocols (SPI and I2C) in slave mode. + +In SPI mode, only Motorola submode (all Motorola modes: 0, 1, 2, 3) is supported. The external master should use continuous data frames; i.e. data frames not seperated by slave deselection. + +In EZ mode, data frames should 8-bit in size and should be transmitted and received with the Most Significant Bit (MSB) first. + +In UART mode this field must be '0'. + [10:10] + read-write + + + BYTE_MODE + N/A + [11:11] + read-write + + + CMD_RESP_MODE + Determines CMD_RESP mode of operation: +'0': CMD_RESP mode disabled. +'1': CMD_RESP mode enabled (also requires EC_AM_MODE and EC_OP_MODE to be set to '1'). + +In CMD_RESP mode, a meta protocol is applied to the serial interface protocol. This meta protocol adds meaning to the data frames transferred by the serial interface protocol: a data frame can represent a write memory data element or a read memory data element. The difference from EZ mode is that the address is written by the CPU, not the interface master. + +CMD_RESP mode can only be used for synchronous serial interface protocols (SPI and I2C) in slave mode. + +In SPI mode, only Motorola submode (all Motorola modes: 0, 1, 2, 3) is supported. The external master should use continuous data frames; i.e. data frames not seperated by slave deselection. + +In CMD_RESP mode, data frames should 8-bit in size and should be transmitted and received with the Most Significant Bit (MSB) first. + +In UART mode this field must be '0'. + [12:12] + read-write + + + ADDR_ACCEPT + Determines whether a received matching address is accepted in the RX FIFO:. +'0': Matching address does not go in RX FIFO +'1': Match address does go in RX FIFO + +In I2C mode, this field is used to allow the slave to put the received slave address or general call address in the RX FIFO. Note that a received matching address is put in the RX FIFO when this bit is '1' for both I2C read and write transfers. + +In multi-processor UART receiver mode, this field is used to allow the receiver to put the received address in the RX FIFO. + +Note: non-matching addresses are never put in the RX FIFO. + +In SPI mode this field must be '0' + [16:16] + read-write + + + BLOCK + Only used in externally clocked mode. If the externally clocked logic and the CPU access the EZ memory at the same time this bit determines whether a CPU access should block and result in bus wait states +'0': Do not block, but ingore a write and return 0xffff:ffff for a read +'1': Block, resulting in CPU wait states. + +If BLOCK is '0' and the accesses collide, CPU read operations return 0xffff:ffff and CPU write operations are ignored. Colliding accesses are registered as interrupt causes: field BLOCKED of the INTR_TX and INTR_RX registers. + [17:17] + read-write + + + MODE + N/A + [25:24] + read-write + + + I2C + N/A + 0 + + + SPI + N/A + 1 + + + UART + N/A + 2 + + + + + ENABLED + 0': Block Disabled +'1': Block Enabled + +The proper order in which to initialize the SCB is as follows: +- Program protocol specific information using SPI_CTRL, UART_CTRL (and UART_TX_CTRL and UART_RX_CTRL) or I2C_CTRL. This includes selection of a submode, master/slave functionality and transmitter/receiver functionality when applicable. +- Program generic transmitter (TX_CTRL) and receiver (RX_CTRL) information. This includes enabling of the transmitter and receiver functionality. +- Program transmitter FIFO (TX_FIFO_CTRL) and receiver FIFO (RX_FIFO_CTRL) information. +- Program CTRL to enable SCB, select the specific operation mode and oversampling factor. +When the SCB is enabled, no control information should be changed. Changes must be made AFTER disabling the SCB, e.g. to modify the operation mode (from I2C to SPI) or to go from externally to internally clocked. The change takes effect after the SCB is re-enabled. Note that disabling the SCB will cause re-initialization of the design and associated state is lost (e.g. FIFO content). + [31:31] + read-write + + + + + STATUS + Generic status + 0x4 + 32 + read-only + 0x0 + 0x0 + + + EC_BUSY + Inidicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ and CMD_RESP mode). This bit can be used by SW to determine whether it is safe for the CPU to access the EZ memory (without bus wait states (a blocked CPU access) or bus errors being generated). Note that the INTR_TX.BLOCKED and INTR_RX.BLOCKED interrupt causes are used to indicate whether CPU access was actually blocked by externally clocked logic. + [0:0] + read-only + + + + + CMD_RESP_CTRL + Command/response control + 0x8 + 32 + read-write + 0x0 + 0x1FF01FF + + + BASE_RD_ADDR + I2C/SPI read base address for CMD_RESP mode. At the start of a read transfer this BASE_RD_ADDR is copied to CMD_RESP_STATUS.CURR_RD_ADDR. This field should not be modified during ongoing bus transfers. + [8:0] + read-write + + + BASE_WR_ADDR + I2C/SPI write base address for CMD_RESP mode. At the start of a write transfer this BASE_WR_ADDR is copied to CMD_RESP_STATUS.CURR_WR_ADDR. This field should not be modified during ongoing bus transfers. + [24:16] + read-write + + + + + CMD_RESP_STATUS + Command/response status + 0xC + 32 + read-only + 0x0 + 0x0 + + + CURR_RD_ADDR + I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However, when the last memory buffer address is reached, the address is NOT incremented (but remains at the maximim memory buffer address). + +The field is used to determine how many bytes have been read (# bytes = CURR_RD_ADDR - CMD_RESP_CTRL.BASE_RD_ADDR). + +This field is reliable when there is no bus transfer. This field is potentially unreliable when there is a ongoing bus transfer, i.e. when CMD_RESP_EC_BUSY is '0', the field is reliable. + [8:0] + read-only + + + CURR_WR_ADDR + I2C/SPI write current address for CMD_RESP mode. HW increments the field after a write access to the memory buffer. However, when the last memory buffer address is reached, the address is NOT incremented (but remains at the maximim memory buffer address). + +The field is used to determine how many bytes have been written (# bytes = CURR_WR_ADDR - CMD_RESP_CTRL.BASE_WR_ADDR). + +This field is reliable when there is no bus transfer. This field is potentially unreliable when there is a ongoing bus transfer, i.e when CMD_RESP_EC_BUSY is '0', the field is reliable. + [24:16] + read-only + + + CMD_RESP_EC_BUS_BUSY + Indicates whether there is an ongoing bus transfer to the SCB. +'0': no ongoing bus transfer. +'1': ongoing bus transfer. + +For SPI, the field is '1' when slave mode is selected. + +For I2C, the field is set to '1' at a I2C START/RESTART. In case of an address match, the field is set to '0' on a I2C STOP. In case of NO address match, the field is set to '0' after the failing address match. + [30:30] + read-only + + + CMD_RESP_EC_BUSY + N/A + [31:31] + read-only + + + + + SPI_CTRL + SPI control + 0x20 + 32 + read-write + 0x3000000 + 0x8F010F3F + + + SSEL_CONTINUOUS + Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode, both continuous and non-continuous SPI data transfers are supported independent of this field. + +When continuous transfers are enabled indiviual data transfers are NOT seperated by slave select deselection as long as there is data in the TX FIFO. If the TX FIFO becomes empty then the slave select will be deselected. + +When continuous transfers are not enabled individual data frame transfers are always seperated by slave select deselection: independent of the availability of TX FIFO data frames. + [0:0] + read-write + + + SELECT_PRECEDE + Only used in SPI Texas Instruments' submode. + +When '1', the data frame start indication is a pulse on the Slave SELECT line that precedes the transfer of the first data frame bit. + +When '0', the data frame start indication is a pulse on the Slave SELECT line that coincides with the transfer of the first data frame bit. + [1:1] + read-write + + + CPHA + N/A + [2:2] + read-write + + + CPOL + N/A + [3:3] + read-write + + + LATE_MISO_SAMPLE + Changes the SCLK edge on which MISO is captured. Only used in master mode. + +When '0', the default applies ( +for Motorola as determined by CPOL and CPHA, +for Texas Instruments on the falling edge of SCLK and +for National Semiconductors on the rising edge of SCLK). + +When '1', the alternate clock edge is used (which comes half a SPI SCLK period later). Late sampling addresses the round trip delay associated with transmitting SCLK from the master to the slave and transmitting MISO from the slave to the master. + [4:4] + read-write + + + SCLK_CONTINUOUS + N/A + [5:5] + read-write + + + SSEL_POLARITY0 + N/A + [8:8] + read-write + + + SSEL_POLARITY1 + N/A + [9:9] + read-write + + + SSEL_POLARITY2 + N/A + [10:10] + read-write + + + SSEL_POLARITY3 + N/A + [11:11] + read-write + + + LOOPBACK + Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode. +'0': No local loopback +'1': the SPI master MISO line is connected to the SPI master MOSI line. In other words, in loopback mode the SPI master receives on MISO what it transmits on MOSI. + [16:16] + read-write + + + MODE + N/A + [25:24] + read-write + + + SPI_MOTOROLA + SPI Motorola submode. + 0 + + + SPI_TI + SPI Texas Instruments submode. + 1 + + + SPI_NS + SPI National Semiconducturs submode. + 2 + + + + + SSEL + Selects one of the four incoming/outgoing SPI slave select signals: +- 0: Slave 0, SSEL[0]. +- 1: Slave 1, SSEL[1]. +- 2: Slave 2, SSEL[2]. +- 3: Slave 3, SSEL[3]. +The SCB should be disabled when changes are made to this field. + [27:26] + read-write + + + MASTER_MODE + N/A + [31:31] + read-write + + + + + SPI_STATUS + SPI status + 0x24 + 32 + read-only + 0x0 + 0x0 + + + BUS_BUSY + N/A + [0:0] + read-only + + + SPI_EC_BUSY + Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ and CMD_RESP mode). This bit can be used by the CPU to determine whether BASE_ADDR and CURR_ADDR are reliable. + [1:1] + read-only + + + CURR_EZ_ADDR + SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1'). + [15:8] + read-only + + + BASE_EZ_ADDR + SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable. + [23:16] + read-only + + + + + UART_CTRL + UART control + 0x40 + 32 + read-write + 0x3000000 + 0x3010000 + + + LOOPBACK + Local loopback control (does NOT affect the information on the pins). +0: Loopback is not enabled +1: UART_TX is connected to UART_RX. UART_RTS is connected to UART_CTS. +This allows a SCB UART transmitter to communicate with its receiver counterpart. + [16:16] + read-write + + + MODE + N/A + [25:24] + read-write + + + UART_STD + N/A + 0 + + + UART_SMARTCARD + N/A + 1 + + + UART_IRDA + N/A + 2 + + + + + + + UART_TX_CTRL + UART transmitter control + 0x44 + 32 + read-write + 0x2 + 0x137 + + + STOP_BITS + Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of half bit periods. Valid range is [1, 7]; i.e. a stop period should last at least one bit period. + [2:0] + read-write + + + PARITY + N/A + [4:4] + read-write + + + PARITY_ENABLED + N/A + [5:5] + read-write + + + RETRY_ON_NACK + N/A + [8:8] + read-write + + + + + UART_RX_CTRL + UART receiver control + 0x48 + 32 + read-write + 0xA0002 + 0xF3777 + + + STOP_BITS + Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of half bit periods. Valid range is [1, 7]; i.e. a stop period should last at least one bit period. + +If STOP_BITS is '1', stop bits error detection is NOT performed. If STOP_BITS is in [2, 7], stop bits error detection is performed and the associated interrupt cause INTR_RX.FRAME_ERROR is set to '1' if an error is detected. In other words, the receiver supports data frames with a 1 bit period stop bit sequence, but requires at least 1.5 bit period stop bit sequences to detect errors. + +Note that in case of a stop bits error, the successive data frames may get lost as the receiver needs to resynchronize its start bit detection. The amount of lost data frames depends on both the amount of stop bits, the idle time between data frames and the data frame value. + [2:0] + read-write + + + PARITY + N/A + [4:4] + read-write + + + PARITY_ENABLED + N/A + [5:5] + read-write + + + POLARITY + Inverts incoming RX line signal 'uart_rx_in'. Inversion is after local loopback. This functionality only works for IrDA receiver functionality. + [6:6] + read-write + + + DROP_ON_PARITY_ERROR + N/A + [8:8] + read-write + + + DROP_ON_FRAME_ERROR + Behaviour when an error is detected in a start or stop period. When '0', received data is sent to the RX FIFO. When '1', received data is dropped and lost. + [9:9] + read-write + + + MP_MODE + Multi-processor mode. When '1', multi-processor mode is enabled. In this mode, RX_CTRL.DATA_WIDTH must be 9 bits. In multi-processor mode, the 9th received bit of a data frame seperates addresses (bit is '1') from data (bit is '0'). A received address is matched with RX_MATCH.DATA and RX_MATCH.MASK. In the case of a match, subsequent received data is sent to the RX FIFO. In the case of NO match, subsequent received data is dropped. + [10:10] + read-write + + + LIN_MODE + Only applicable in standard UART submode. When '1', the receiver performs break detection and baud rate detection on the incoming data. First, break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies the minum required amount of bit periods. Successful break detection sets the INTR_RX.BREAK_DETECT interrupt cause to '1'. Second, baud rate detection counts the amount of peripheral clock periods that are use to receive the synchronization byte (0x55; least significant bit first). The count is available through UART_RX_STATUS.BR_COUNTER. Successful baud rate detection sets the INTR_RX.BAUD_DETECT interrupt cause to '1' (BR_COUNTER is reliable). This functionality is used to synchronize/refine the receiver clock to the transmitter clock. The receiver software can use the BR_COUNTER value to set the right clk_scb to guarantee successful receipt of the first LIN data frame (Protected Identifier Field) after the synchronization byte. + [12:12] + read-write + + + SKIP_START + Only applicable in standard UART submode. When '1', the receiver skips start bit detection for the first received data frame. Instead, it synchronizes on the first received data frame bit, which should be a '1'. + +This functionality is intended for wake up from DeepSleep when receiving a data frame. The transition from idle ('1') to START ('0') on the RX line is used to wake up the CPU. The transition detection (and the associated wake up functionality) is performed by the GPIO. + +The woken up CPU will enable the SCB's UART receiver functionality. Once enabled, it is assumed that the START bit is ongoing (the CPU wakeup and SCB enable time should be less than the START bit period). The SCB will then synchronize to a '0' to '1' transition, which indicates the first data frame bit is received (first data frame bit should be '1'). After synchronization to the first data frame bit, the SCB will resume normal UART functionality: subsequent data frames will be synchronized on the receipt of a START bit. + [13:13] + read-write + + + BREAK_WIDTH + Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. During a break the transmitted/received line value is '0'. This feature is useful for standard UART submode and LIN submode ('break field' detection). Once, the break is detected, the INTR_RX.BREAK_DETECT bit is set to '1'. + +Note for LIN the break detection precedes baud rate detection, which is used to synchronize/refine the receiver clock to the transmitter clock. As a result, break detection operates with an unsynchronized/unrefined receiver clock. Therefore, the receiver's definition of a bit period is imprecise and the setting of this field should take this imprecision into account. The LIN standard also accounts for this imprecision: a LIN start bit followed by 8 data bits allows for up to 9 consecutive '0' bit periods during regular transmission, whereas the LIN break detection should be at least 13 consecutive '0' bit periods. This provides for a margin of 4 bit periods. Therefore, the default value of this field is set to 10, representing a minimal break field with of 10+1 = 11 bit periods; a value in between the 9 consecutive bit periods of a regular transmission and the 13 consecutive bit periods of a break field. This provides for slight imprecisions of the receiver clock wrt. the transmitter clock. There should not be a need to program this field to any value other than its default value. + [19:16] + read-write + + + + + UART_RX_STATUS + UART receiver status + 0x4C + 32 + read-only + 0x0 + 0x0 + + + BR_COUNTER + For LIN: Amount of clk_scb periods that constitute the transmission of a 0x55 data frame (sent least signficant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of clk_scb periods that constitute a bit period. This field has valid data when INTR_RX.BAUD_DETECT is set to '1'. + [11:0] + read-only + + + + + UART_FLOW_CTRL + UART flow control + 0x50 + 32 + read-write + 0x0 + 0x30100FF + + + TRIGGER_LEVEL + Trigger level. When the receiver FIFO has less entries than the amount of this field, a Ready To Send (RTS) output signal is activated. By setting this field to '0', flow control is disabled + [7:0] + read-write + + + RTS_POLARITY + Polarity of the RTS output signal: +'0': RTS is active low; +'1': RTS is active high; + +During SCB reset (Hibernate system power mode), RTS output signal is '1'. This represents an inactive state assuming an active low polarity. + [16:16] + read-write + + + CTS_POLARITY + Polarity of the CTS input signal +'0': CTS is active low ; +'1': CTS is active high; + [24:24] + read-write + + + CTS_ENABLED + Enable use of CTS input signal by the UART transmitter: +'0': Disabled. The UART transmitter ignores the CTS input signal and transmits when a data frame is available for transmission in the TX FIFO or the TX shift register. +'1': Enabled. The UART transmitter uses CTS input signal to qualify the transmission of data. It transmits when CTS input signal is active and a data frame is available for transmission in the TX FIFO or the TX shift register. + +If UART_CTRL.LOOPBACK is '1', the CTS input signal is driven by the RTS output signal locally in SCB (both signals are subjected to signal polarity changes as indicated by RTS_POLARITY and CTS_POLARITY). + [25:25] + read-write + + + + + I2C_CTRL + I2C control + 0x60 + 32 + read-write + 0xFB88 + 0xC001FBFF + + + HIGH_PHASE_OVS + Serial I2C interface high phase oversampling factor. (HIGH_PHASE_OVS + 1) * clk_scb constitutes the high phase of a bit period. The valid range is [5, 15] with input signal median filtering and [4, 15] without input signal median filtering. + +The field is only used in master mode. In slave mode, the field is NOT used. See architecture TRM for information on slave data rate requirments. + [3:0] + read-write + + + LOW_PHASE_OVS + Serial I2C interface low phase oversampling factor. (LOW_PHASE_OVS + 1) * clk_scb constitutes the low phase of a bit period. The valid range is [7, 15] with input signal median filtering and [6, 15] without input signal median filtering. + +The field is only used in master mode. In slave mode, the field is NOT used. See architecture TRM for information on slave data rate requirments. + [7:4] + read-write + + + M_READY_DATA_ACK + When '1', a received data element by the master is immediately ACK'd when the RX FIFO is not full. When '0' the CPU is responsible for ACK/NACKing the received data frame using I2C_M_CMD.M_ACK or I2C_M_CMD.M_NACK + [8:8] + read-write + + + M_NOT_READY_DATA_NACK + When '1', a received data element by the master is immediately NACK'd when the RX FIFO is full. When '0', clock stretching is used instead (till the RX FIFO is no longer full). + [9:9] + read-write + + + S_GENERAL_IGNORE + When '1', a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address. This is useful for slaves that do not need any data supplied within the general call structure. +When '0' the general call address is accepted and follows S_READY_ADDR_ACK and S_NOT_READY_ADDR_NACK + [11:11] + read-write + + + S_READY_ADDR_ACK + When '1', a received (matching) slave address is immediately ACK'd when the RX FIFO is not full. In EZ and CMD_RESP mode, this field should be set to '1'. +When '0' the address must be ACK/NACK'd by the CPU using I2C_S_CMD.S_ACK or I2C_S_CMD.S_NACK + [12:12] + read-write + + + S_READY_DATA_ACK + When '1', a received data element by the slave is immediately ACK'd when the RX FIFO is not full. In EZ and CMD_RESP mode, this field should be set to '1'. +When '0' the data must be ACK/NACK'd by the CPU using I2C_S_CMD.S_ACK or I2C_S_CMD.S_NACK + [13:13] + read-write + + + S_NOT_READY_ADDR_NACK + Only used for FIFO mode, NOT EZ or CMD_RESP mode. + +Functionality is as follows: +- 1: In Active/Sleep mode a received (matching) slave address is immediately NACK'd when the RX FIFO is full +In DeepSleep power mode when EC_AM = '1' and EC_OP = '0' clk_scb is not avaliable, so the incoming address will be NACK'd until the clock is avaliable. Once clk_scb is avaliable the address ACK will follow S_READY_ADDR_ACK +- 0: in Active/Sleep mode clock stretching is performed when the RX FIFO is full, the strech is released when the RX FIFO is no longer full. +In DeepSleep power mode when EC_AM = '1' and EC_OP = '0' clk_scb is not avaliable, so the clocked will be streched on an incoming address until clk_scb is avaliable. After clk_scb is avalaible the address ACK will follow S_READY_ADDR_ACK + [14:14] + read-write + + + S_NOT_READY_DATA_NACK + Only used for FIFO mode, NOT EZ or CMD_RESP mode. + +Functionality is as follows: +- 1: a received data element byte the slave is immediately NACK'd when the receiver FIFO is full. +- 0: clock stretching is performed (till the receiver FIFO is no longer full). + [15:15] + read-write + + + LOOPBACK + Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode. +When '0', no loopback +When '1', loopback is enabled internally in the peripheral, and as a result unaffected by other I2C devices. This allows a SCB I2C peripheral to address itself. + [16:16] + read-write + + + SLAVE_MODE + N/A + [30:30] + read-write + + + MASTER_MODE + Master mode enabled ('1') or not ('0'). Note that both master and slave modes can be enabled at the same time. This allows the SCB to address itself. + [31:31] + read-write + + + + + I2C_STATUS + I2C status + 0x64 + 32 + read-only + 0x0 + 0x31 + + + BUS_BUSY + I2C bus is busy. The bus is considered busy ('1'), from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0'), from the time a STOP is detected. If the SCB is disabled, BUS_BUSY is '0'. After enabling the SCB, it takes time for the BUS_BUSY to detect a busy bus. This time is the maximum high time of the SCL line. For a 100 kHz interface frequency, this maximum high time may last roughly 5 us (half a bit period). + +For single master systems, BUS_BUSY does not have to be used to detect an idle bus before a master starts a transfer using I2C_M_CMD.M_START (no bus collisions). + +For multi-master systems, BUS_BUSY can be used to detect an idle bus before a master starts a transfer using I2C_M_CMD.M_START_ON_IDLE (to prevent bus collisions). + [0:0] + read-only + + + I2C_EC_BUSY + Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ and CMD_RESP mode). This bit can be used by the CPU to determine whether BASE_EZ_ADDR and CURR_EZ_ADDR are reliable. + [1:1] + read-only + + + S_READ + N/A + [4:4] + read-only + + + M_READ + N/A + [5:5] + read-only + + + CURR_EZ_ADDR + I2C slave current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when I2C_EC_BUSY is '1'). + [15:8] + read-only + + + BASE_EZ_ADDR + I2C slave base EZ address. Address as provided by an I2C write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable. + [23:16] + read-only + + + + + I2C_M_CMD + I2C master command + 0x68 + 32 + read-write + 0x0 + 0x1F + + + M_START + When '1', transmit a START or REPEATED START. + +Whether a START or REPEATED START is transmitted depends on the state of the master state machine. A START is only transmitted when the master state machine is in the default state. A REPEATED START is transmitted when the master state machine is not in the default state, but is working on an ongoing transaction. The REPEATED START can only be transmitted after a NACK or ACK has been received for a transmitted data element or after a NACK has been transmitted for a received data element. When this action is performed, the hardware sets this field to '0'. + [0:0] + read-write + + + M_START_ON_IDLE + When '1', transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0', note that BUSY has a default value of '0'). + +For bus idle detection the hardware relies on STOP detection. As a result, bus idle detection is only functional after at least one I2C bus transfer has been detected on the bus (default/reset value of BUSY is '0') . A START is only transmitted when the master state machine is in the default state. When this action is performed, the hardware sets this field to '0'. + [1:1] + read-write + + + M_ACK + N/A + [2:2] + read-write + + + M_NACK + N/A + [3:3] + read-write + + + M_STOP + N/A + [4:4] + read-write + + + + + I2C_S_CMD + I2C slave command + 0x6C + 32 + read-write + 0x0 + 0x3 + + + S_ACK + When '1', attempt to transmit an acknowledgement (ACK). When this action is performed, the hardware sets this field to '0'. In EZ and CMD_RESP mode, this field should be set to '0' (it is only to be used in FIFO mode). + [0:0] + read-write + + + S_NACK + When '1', attempt to transmit a negative acknowledgement (NACK). When this action is performed, the hardware sets this field to '0'. In EZ and CMD_RESP mode, this field should be set to '0' (it is only to be used in FIFO mode). This command has a higher priority than I2C_S_CMD.S_ACK, I2C_CTRL.S_READY_ADDR_ACK or I2C_CTRL.S_READY_DATA_ACK. + [1:1] + read-write + + + + + I2C_CFG + I2C configuration + 0x70 + 32 + read-write + 0x2A1013 + 0x303F1313 + + + SDA_IN_FILT_TRIM + Trim bits for 'i2c_sda_in' 50 ns filter. + +SDA_IN_FILT_TRIM[1] is used to enable I2CS_EC or SPIS_EC access to internal EZ memory. +1: enable clk_scb +0: disable clk_scb + +Before going to deepsleep this field should be set to 0. It should be re-enabled once the device is awoken and clk_hf[0] is at the desired frequency. + [1:0] + read-write + + + SDA_IN_FILT_SEL + N/A + [4:4] + read-write + + + SCL_IN_FILT_TRIM + Trim bits for 'i2c_scl_in' 50 ns filter. Not to be modified by the user + [9:8] + read-write + + + SCL_IN_FILT_SEL + N/A + [12:12] + read-write + + + SDA_OUT_FILT0_TRIM + Trim bits for 'i2c_sda_out' 50 ns filter 0. Not to be modified by the user + [17:16] + read-write + + + SDA_OUT_FILT1_TRIM + Trim bits for 'i2c_sda_out' 50 ns filter 1. Not to be modified by the user + [19:18] + read-write + + + SDA_OUT_FILT2_TRIM + Trim bits for 'i2c_sda_out' 50 ns filter 2. Not to be modified by the user + [21:20] + read-write + + + SDA_OUT_FILT_SEL + N/A + [29:28] + read-write + + + + + TX_CTRL + Transmitter control + 0x200 + 32 + read-write + 0x107 + 0x1010F + + + DATA_WIDTH + Dataframe width. DATA_WIDTH + 1 is the amount of bits in a transmitted data frame. This number does not include start, parity and stop bits. For UART mode, the valid range is [3, 8]. For SPI, the valid range is [3, 15]. For I2C the only valid value is 7. In EZ and CMD_RESP mode (for both SPI and I2C), the only valid value is 7. + [3:0] + read-write + + + MSB_FIRST + Least significant bit first ('0') or most significant bit first ('1'). For I2C, this field should be '1'. For EZ and CMD_RESP this field must be set to '1' + [8:8] + read-write + + + OPEN_DRAIN + Each IO cell 'xxx' has two associated SCB output signals 'xxx_out_en' and 'xxx_out'. This field determines how the SCB controls those two signals. Consult the GPIO chapter in the architecture TRM to understand how the pin drive modes behave when connected to SCBs. + +'0': Normal operation mode. In this operation mode 'xxx_out_en' output enable signal is typically constant '1' the 'xxx_out' output is the outputted value. In other words, in normal operation mode, the 'xxx_out' output is used to control the IO cell output value: 'xxx_out' is '0' to drive an IO cell output value of '0' and 'xxx_out' is '1' to drive an IO cell output value of '1'. + +'1': Open drain operation mode. In this operation mode 'xxx_out_en' output controls the outputted value. Typically the 'xxx_out' signal is a constant '0'. Thus when 'xxx_out_en' is '1' the line is driven low, but when 'xxx_out_en' is '0' the output is not driven. This requires that the line is driven high by an external device or pull-up resistor + +The open drain mode is supported for: +- I2C mode this field must be set. +- UART mode use this mode when a pull-up resistor is used on the TX line. +- SPI mode this field must be set if there are multiple slaves driving MISO. + [16:16] + read-write + + + + + TX_FIFO_CTRL + Transmitter FIFO control + 0x204 + 32 + read-write + 0x0 + 0x300FF + + + TRIGGER_LEVEL + N/A + [7:0] + read-write + + + CLEAR + N/A + [16:16] + read-write + + + FREEZE + N/A + [17:17] + read-write + + + + + TX_FIFO_STATUS + Transmitter FIFO status + 0x208 + 32 + read-only + 0x0 + 0xFFFF81FF + + + USED + N/A + [8:0] + read-only + + + SR_VALID + N/A + [15:15] + read-only + + + RD_PTR + N/A + [23:16] + read-only + + + WR_PTR + N/A + [31:24] + read-only + + + + + TX_FIFO_WR + Transmitter FIFO write + 0x240 + 32 + write-only + 0x0 + 0xFFFF + + + DATA + N/A + [15:0] + write-only + + + + + RX_CTRL + Receiver control + 0x300 + 32 + read-write + 0x107 + 0x30F + + + DATA_WIDTH + N/A + [3:0] + read-write + + + MSB_FIRST + Least significant bit first ('0') or most significant bit first ('1'). For I2C, this field should be '1'. For EZ and CMD_RESP this field must be set to '1' + [8:8] + read-write + + + MEDIAN + N/A + [9:9] + read-write + + + + + RX_FIFO_CTRL + Receiver FIFO control + 0x304 + 32 + read-write + 0x0 + 0x300FF + + + TRIGGER_LEVEL + N/A + [7:0] + read-write + + + CLEAR + N/A + [16:16] + read-write + + + FREEZE + N/A + [17:17] + read-write + + + + + RX_FIFO_STATUS + Receiver FIFO status + 0x308 + 32 + read-only + 0x0 + 0xFFFF81FF + + + USED + N/A + [8:0] + read-only + + + SR_VALID + N/A + [15:15] + read-only + + + RD_PTR + N/A + [23:16] + read-only + + + WR_PTR + N/A + [31:24] + read-only + + + + + RX_MATCH + Slave address and mask + 0x310 + 32 + read-write + 0x0 + 0xFF00FF + + + ADDR + N/A + [7:0] + read-write + + + MASK + N/A + [23:16] + read-write + + + + + RX_FIFO_RD + Receiver FIFO read + 0x340 + 32 + read-only + 0x0 + 0x0 + + + DATA + Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.BYTE_MODE is '1', only DATA[7:0] are used. + +When in debug mode a read from this register behaves as a read from the SCB_RX_FIFO_RD_SILENT register. That is data will not be removed from the FIFO + +A read from an empty RX FIFO sets INTR_RX.UNDERFLOW to '1'. + [15:0] + read-only + + + + + RX_FIFO_RD_SILENT + Receiver FIFO read silent + 0x344 + 32 + read-only + 0x0 + 0x0 + + + DATA + N/A + [15:0] + read-only + + + + + INTR_CAUSE + Active clocked interrupt signal + 0xE00 + 32 + read-only + 0x0 + 0x3F + + + M + Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0. + [0:0] + read-only + + + S + Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0. + [1:1] + read-only + + + TX + Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0. + [2:2] + read-only + + + RX + Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0. + [3:3] + read-only + + + I2C_EC + Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0. + [4:4] + read-only + + + SPI_EC + Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0. + [5:5] + read-only + + + + + INTR_I2C_EC + Externally clocked I2C interrupt request + 0xE80 + 32 + read-write + 0x0 + 0xF + + + WAKE_UP + Wake up request. Active on incoming slave request (with address match). + +Only set when EC_AM is '1'. + [0:0] + read-write + + + EZ_STOP + STOP detection. Activated on the end of a every transfer (I2C STOP). + +Only set for a slave request with an address match, in EZ and CMD_RESP modes, when EC_OP is '1'. + [1:1] + read-write + + + EZ_WRITE_STOP + STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address does NOT activate this event. + +Only set for a slave request with an address match, in EZ and CMD_RESP modes, when EC_OP is '1'. + [2:2] + read-write + + + EZ_READ_STOP + STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from. + +Only set for a slave request with an address match, in EZ and CMD_RESP modes, when EC_OP is '1'. + [3:3] + read-write + + + + + INTR_I2C_EC_MASK + Externally clocked I2C interrupt mask + 0xE88 + 32 + read-write + 0x0 + 0xF + + + WAKE_UP + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + EZ_STOP + Mask bit for corresponding bit in interrupt request register. + [1:1] + read-write + + + EZ_WRITE_STOP + Mask bit for corresponding bit in interrupt request register. + [2:2] + read-write + + + EZ_READ_STOP + Mask bit for corresponding bit in interrupt request register. + [3:3] + read-write + + + + + INTR_I2C_EC_MASKED + Externally clocked I2C interrupt masked + 0xE8C + 32 + read-only + 0x0 + 0xF + + + WAKE_UP + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + EZ_STOP + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + EZ_WRITE_STOP + Logical and of corresponding request and mask bits. + [2:2] + read-only + + + EZ_READ_STOP + Logical and of corresponding request and mask bits. + [3:3] + read-only + + + + + INTR_SPI_EC + Externally clocked SPI interrupt request + 0xEC0 + 32 + read-write + 0x0 + 0xF + + + WAKE_UP + Wake up request. Active on incoming slave request. + +Only set when EC_AM is '1'. + [0:0] + read-write + + + EZ_STOP + STOP detection. Activated on the end of a every transfer (SPI deselection). + +Only set in EZ and CMD_RESP mode and when EC_OP is '1'. + [1:1] + read-write + + + EZ_WRITE_STOP + STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address does NOT activate this event. + +Only set in EZ and CMD_RESP modes and when EC_OP is '1'. + [2:2] + read-write + + + EZ_READ_STOP + STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from. + +Only set in EZ and CMD_RESP modes and when EC_OP is '1'. + [3:3] + read-write + + + + + INTR_SPI_EC_MASK + Externally clocked SPI interrupt mask + 0xEC8 + 32 + read-write + 0x0 + 0xF + + + WAKE_UP + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + EZ_STOP + Mask bit for corresponding bit in interrupt request register. + [1:1] + read-write + + + EZ_WRITE_STOP + Mask bit for corresponding bit in interrupt request register. + [2:2] + read-write + + + EZ_READ_STOP + Mask bit for corresponding bit in interrupt request register. + [3:3] + read-write + + + + + INTR_SPI_EC_MASKED + Externally clocked SPI interrupt masked + 0xECC + 32 + read-only + 0x0 + 0xF + + + WAKE_UP + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + EZ_STOP + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + EZ_WRITE_STOP + Logical and of corresponding request and mask bits. + [2:2] + read-only + + + EZ_READ_STOP + Logical and of corresponding request and mask bits. + [3:3] + read-only + + + + + INTR_M + Master interrupt request + 0xF00 + 32 + read-write + 0x0 + 0x317 + + + I2C_ARB_LOST + N/A + [0:0] + read-write + + + I2C_NACK + N/A + [1:1] + read-write + + + I2C_ACK + N/A + [2:2] + read-write + + + I2C_STOP + N/A + [4:4] + read-write + + + I2C_BUS_ERROR + N/A + [8:8] + read-write + + + SPI_DONE + N/A + [9:9] + read-write + + + + + INTR_M_SET + Master interrupt set request + 0xF04 + 32 + read-write + 0x0 + 0x317 + + + I2C_ARB_LOST + Write with '1' to set corresponding bit in interrupt request register. + [0:0] + read-write + + + I2C_NACK + Write with '1' to set corresponding bit in interrupt request register. + [1:1] + read-write + + + I2C_ACK + Write with '1' to set corresponding bit in interrupt request register. + [2:2] + read-write + + + I2C_STOP + Write with '1' to set corresponding bit in interrupt request register. + [4:4] + read-write + + + I2C_BUS_ERROR + Write with '1' to set corresponding bit in interrupt request register. + [8:8] + read-write + + + SPI_DONE + Write with '1' to set corresponding bit in interrupt request register. + [9:9] + read-write + + + + + INTR_M_MASK + Master interrupt mask + 0xF08 + 32 + read-write + 0x0 + 0x317 + + + I2C_ARB_LOST + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + I2C_NACK + Mask bit for corresponding bit in interrupt request register. + [1:1] + read-write + + + I2C_ACK + Mask bit for corresponding bit in interrupt request register. + [2:2] + read-write + + + I2C_STOP + Mask bit for corresponding bit in interrupt request register. + [4:4] + read-write + + + I2C_BUS_ERROR + Mask bit for corresponding bit in interrupt request register. + [8:8] + read-write + + + SPI_DONE + Mask bit for corresponding bit in interrupt request register. + [9:9] + read-write + + + + + INTR_M_MASKED + Master interrupt masked request + 0xF0C + 32 + read-only + 0x0 + 0x317 + + + I2C_ARB_LOST + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + I2C_NACK + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + I2C_ACK + Logical and of corresponding request and mask bits. + [2:2] + read-only + + + I2C_STOP + Logical and of corresponding request and mask bits. + [4:4] + read-only + + + I2C_BUS_ERROR + Logical and of corresponding request and mask bits. + [8:8] + read-only + + + SPI_DONE + Logical and of corresponding request and mask bits. + [9:9] + read-only + + + + + INTR_S + Slave interrupt request + 0xF40 + 32 + read-write + 0x0 + 0xFFF + + + I2C_ARB_LOST + I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur, it represents erroneous I2C bus behavior. In case of lost arbitration, the I2C slave state machine aborts the ongoing transfer. SW may decide to clear the TX and RX FIFOs in case of this error. + [0:0] + read-write + + + I2C_NACK + N/A + [1:1] + read-write + + + I2C_ACK + N/A + [2:2] + read-write + + + I2C_WRITE_STOP + I2C STOP event for I2C write transfer intended for this slave (address matching is performed). Set to '1', when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C transfers separated by a REPEATED START can be distinguished and potentially treated separately by the firmware. Note that the second I2C transfer (after a REPEATED START) may be to a different slave address. + +Note that a I2C write address intended for the slave (address is matching and a it is a write transfer) will result in a I2C_WRITE_STOP event independent of whether the I2C address is ACK'd or NACK'd. + +In EZ mode, the event is detected only on I2C write transfers that have EZ data written to the memory structure (an I2C write transfer that only communicates an I2C address and EZ base address, will not result in this event being detected). + [3:3] + read-write + + + I2C_STOP + N/A + [4:4] + read-write + + + I2C_START + I2C slave START received. Set to '1', when START or REPEATED START event is detected. + +In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') AND clock stretching is performed (till the internally clocked logic takes over) (I2C_CTRL.S_NOT_READY_ADDR_NACK is '0'), this field is NOT set. Firmware should use INTR_S_EC.WAKE_UP, INTR_S.I2C_ADDR_MATCH and INTR_S.I2C_GENERAL. + [5:5] + read-write + + + I2C_ADDR_MATCH + N/A + [6:6] + read-write + + + I2C_GENERAL + I2C slave general call address received. If CTRL.ADDR_ACCEPT is set the received address 0x00 (including the R/W bit) is available in the RX FIFO. + +In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked operation (CTRL.EC_OP_MODE is '0'), this field is set when the event is detected. + [7:7] + read-write + + + I2C_BUS_ERROR + I2C slave bus error (unexpected detection of START or STOP condition). This should not occur, it represents erroneous I2C bus behavior. In case of a bus error, the I2C slave state machine abort the ongoing transfer. Firmware may decide to clear the TX and RX FIFOs in case of this error. + [8:8] + read-write + + + SPI_EZ_WRITE_STOP + N/A + [9:9] + read-write + + + SPI_EZ_STOP + N/A + [10:10] + read-write + + + SPI_BUS_ERROR + SPI slave deselected at an unexpected time in the SPI transfer. Firmware may decide to clear the TX and RX FIFOs in case of this error. + [11:11] + read-write + + + + + INTR_S_SET + Slave interrupt set request + 0xF44 + 32 + read-write + 0x0 + 0xFFF + + + I2C_ARB_LOST + Write with '1' to set corresponding bit in interrupt request register. + [0:0] + read-write + + + I2C_NACK + Write with '1' to set corresponding bit in interrupt request register. + [1:1] + read-write + + + I2C_ACK + Write with '1' to set corresponding bit in interrupt request register. + [2:2] + read-write + + + I2C_WRITE_STOP + Write with '1' to set corresponding bit in interrupt request register. + [3:3] + read-write + + + I2C_STOP + Write with '1' to set corresponding bit in interrupt request register. + [4:4] + read-write + + + I2C_START + Write with '1' to set corresponding bit in interrupt request register. + [5:5] + read-write + + + I2C_ADDR_MATCH + Write with '1' to set corresponding bit in interrupt request register. + [6:6] + read-write + + + I2C_GENERAL + Write with '1' to set corresponding bit in interrupt request register. + [7:7] + read-write + + + I2C_BUS_ERROR + Write with '1' to set corresponding bit in interrupt request register. + [8:8] + read-write + + + SPI_EZ_WRITE_STOP + Write with '1' to set corresponding bit in interrupt request register. + [9:9] + read-write + + + SPI_EZ_STOP + Write with '1' to set corresponding bit in interrupt request register. + [10:10] + read-write + + + SPI_BUS_ERROR + Write with '1' to set corresponding bit in interrupt request register. + [11:11] + read-write + + + + + INTR_S_MASK + Slave interrupt mask + 0xF48 + 32 + read-write + 0x0 + 0xFFF + + + I2C_ARB_LOST + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + I2C_NACK + Mask bit for corresponding bit in interrupt request register. + [1:1] + read-write + + + I2C_ACK + Mask bit for corresponding bit in interrupt request register. + [2:2] + read-write + + + I2C_WRITE_STOP + Mask bit for corresponding bit in interrupt request register. + [3:3] + read-write + + + I2C_STOP + Mask bit for corresponding bit in interrupt request register. + [4:4] + read-write + + + I2C_START + Mask bit for corresponding bit in interrupt request register. + [5:5] + read-write + + + I2C_ADDR_MATCH + Mask bit for corresponding bit in interrupt request register. + [6:6] + read-write + + + I2C_GENERAL + Mask bit for corresponding bit in interrupt request register. + [7:7] + read-write + + + I2C_BUS_ERROR + Mask bit for corresponding bit in interrupt request register. + [8:8] + read-write + + + SPI_EZ_WRITE_STOP + Mask bit for corresponding bit in interrupt request register. + [9:9] + read-write + + + SPI_EZ_STOP + Mask bit for corresponding bit in interrupt request register. + [10:10] + read-write + + + SPI_BUS_ERROR + Mask bit for corresponding bit in interrupt request register. + [11:11] + read-write + + + + + INTR_S_MASKED + Slave interrupt masked request + 0xF4C + 32 + read-only + 0x0 + 0xFFF + + + I2C_ARB_LOST + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + I2C_NACK + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + I2C_ACK + Logical and of corresponding request and mask bits. + [2:2] + read-only + + + I2C_WRITE_STOP + Logical and of corresponding request and mask bits. + [3:3] + read-only + + + I2C_STOP + Logical and of corresponding request and mask bits. + [4:4] + read-only + + + I2C_START + Logical and of corresponding request and mask bits. + [5:5] + read-only + + + I2C_ADDR_MATCH + Logical and of corresponding request and mask bits. + [6:6] + read-only + + + I2C_GENERAL + Logical and of corresponding request and mask bits. + [7:7] + read-only + + + I2C_BUS_ERROR + Logical and of corresponding request and mask bits. + [8:8] + read-only + + + SPI_EZ_WRITE_STOP + Logical and of corresponding request and mask bits. + [9:9] + read-only + + + SPI_EZ_STOP + Logical and of corresponding request and mask bits. + [10:10] + read-only + + + SPI_BUS_ERROR + Logical and of corresponding request and mask bits. + [11:11] + read-only + + + + + INTR_TX + Transmitter interrupt request + 0xF80 + 32 + read-write + 0x0 + 0x7F3 + + + TRIGGER + N/A + [0:0] + read-write + + + NOT_FULL + N/A + [1:1] + read-write + + + EMPTY + N/A + [4:4] + read-write + + + OVERFLOW + N/A + [5:5] + read-write + + + UNDERFLOW + Attempt to read from an empty TX FIFO. This happens when the SCB is ready to transfer data and EMPTY is '1'. + +Only used in FIFO mode. + [6:6] + read-write + + + BLOCKED + CPU write can not get access to the EZ memory (EZ data access), due to an externally clocked EZ access. + [7:7] + read-write + + + UART_NACK + N/A + [8:8] + read-write + + + UART_DONE + UART transmitter done event. This happens when the SCB is done transferring all data in the TX FIFO, and the last stop field is transmitted (both TX FIFO and transmit shifter register are empty). + [9:9] + read-write + + + UART_ARB_LOST + UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line. This condition event is usefull when transmitter and receiver share a TX/RX line. This is the case in LIN or SmartCard modes. + [10:10] + read-write + + + + + INTR_TX_SET + Transmitter interrupt set request + 0xF84 + 32 + read-write + 0x0 + 0x7F3 + + + TRIGGER + Write with '1' to set corresponding bit in interrupt request register. + [0:0] + read-write + + + NOT_FULL + Write with '1' to set corresponding bit in interrupt request register. + [1:1] + read-write + + + EMPTY + Write with '1' to set corresponding bit in interrupt request register. + [4:4] + read-write + + + OVERFLOW + Write with '1' to set corresponding bit in interrupt request register. + [5:5] + read-write + + + UNDERFLOW + Write with '1' to set corresponding bit in interrupt request register. + [6:6] + read-write + + + BLOCKED + Write with '1' to set corresponding bit in interrupt request register. + [7:7] + read-write + + + UART_NACK + Write with '1' to set corresponding bit in interrupt request register. + [8:8] + read-write + + + UART_DONE + Write with '1' to set corresponding bit in interrupt request register. + [9:9] + read-write + + + UART_ARB_LOST + Write with '1' to set corresponding bit in interrupt request register. + [10:10] + read-write + + + + + INTR_TX_MASK + Transmitter interrupt mask + 0xF88 + 32 + read-write + 0x0 + 0x7F3 + + + TRIGGER + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + NOT_FULL + Mask bit for corresponding bit in interrupt request register. + [1:1] + read-write + + + EMPTY + Mask bit for corresponding bit in interrupt request register. + [4:4] + read-write + + + OVERFLOW + Mask bit for corresponding bit in interrupt request register. + [5:5] + read-write + + + UNDERFLOW + Mask bit for corresponding bit in interrupt request register. + [6:6] + read-write + + + BLOCKED + Mask bit for corresponding bit in interrupt request register. + [7:7] + read-write + + + UART_NACK + Mask bit for corresponding bit in interrupt request register. + [8:8] + read-write + + + UART_DONE + Mask bit for corresponding bit in interrupt request register. + [9:9] + read-write + + + UART_ARB_LOST + Mask bit for corresponding bit in interrupt request register. + [10:10] + read-write + + + + + INTR_TX_MASKED + Transmitter interrupt masked request + 0xF8C + 32 + read-only + 0x0 + 0x7F3 + + + TRIGGER + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + NOT_FULL + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + EMPTY + Logical and of corresponding request and mask bits. + [4:4] + read-only + + + OVERFLOW + Logical and of corresponding request and mask bits. + [5:5] + read-only + + + UNDERFLOW + Logical and of corresponding request and mask bits. + [6:6] + read-only + + + BLOCKED + Logical and of corresponding request and mask bits. + [7:7] + read-only + + + UART_NACK + Logical and of corresponding request and mask bits. + [8:8] + read-only + + + UART_DONE + Logical and of corresponding request and mask bits. + [9:9] + read-only + + + UART_ARB_LOST + Logical and of corresponding request and mask bits. + [10:10] + read-only + + + + + INTR_RX + Receiver interrupt request + 0xFC0 + 32 + read-write + 0x0 + 0xFED + + + TRIGGER + N/A + [0:0] + read-write + + + NOT_EMPTY + N/A + [2:2] + read-write + + + FULL + N/A + [3:3] + read-write + + + OVERFLOW + N/A + [5:5] + read-write + + + UNDERFLOW + N/A + [6:6] + read-write + + + BLOCKED + CPU read transfer can not get access to the EZ memory (EZ_DATA accesses), due to an externally clocked EZ access. + [7:7] + read-write + + + FRAME_ERROR + UART Frame error in received data frame. +This can be either a start or stop bit(s) error: +Start bit error: after the detection of the beginning of a start bit period (RX line changes from '1' to '0'), the middle of the start bit period is sampled erroneously (RX line is '1'). Note: a start bit error is detected BEFORE a data frame is received. +Stop bit error: the RX line is sampled as '0', but a '1' was expected. Note: a stop bit error may result in failure to receive successive data frame(s). Note: a stop bit error is detected AFTER a data frame is received. + +A stop bit error is detected after a data frame is received, and the UART_RX_CTL.DROP_ON_FRAME_ERROR field specifies whether the received frame is dropped or send to the RX FIFO. If UART_RX_CTL.DROP_ON_FRAME_ERROR is '1', the received data frame is dropped. If UART_RX_CTL.DROP_ON_FRAME_ERROR is '0', the received data frame is send to the RX FIFO. Note that Firmware can only identify the erroneous data frame in the RX FIFO if it is fast enough to read the data frame before the hardware writes a next data frame into the RX FIFO; i.e. the RX FIFO does not have error flags to tag erroneous data frames. + [8:8] + read-write + + + PARITY_ERROR + UART Parity error in received data frame. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '1', the received frame is dropped. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '0', the received frame is send to the RX FIFO. In SmartCard submode, negatively acknowledged data frames generate a parity error. Note that Firmware can only identify the erroneous data frame in the RX FIFO if it is fast enough to read the data frame before the hardware writes a next data frame into the RX FIFO. + [9:9] + read-write + + + BAUD_DETECT + LIN baudrate detection is completed. The receiver software uses the UART_RX_STATUS.BR_COUNTER value to set the clk_scb to guarantee successful receipt of the first LIN data frame (Protected Identifier Field) after the synchronization byte. + [10:10] + read-write + + + BREAK_DETECT + Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period. Can occur at any time to address unanticipated break fields; i.e. 'break-in-data' is supported. This feature is supported for the UART standard and LIN submodes. For the UART standard submodes, ongoing receipt of data frames is NOT affected; i.e. Firmware is expected to take the proper action. For the LIN submode, possible ongoing receipt of a data frame is stopped and the (partially) received data frame is dropped and baud rate detection is started. Set to '1', when event is detected. Write with '1' to clear bit. + [11:11] + read-write + + + + + INTR_RX_SET + Receiver interrupt set request + 0xFC4 + 32 + read-write + 0x0 + 0xFED + + + TRIGGER + Write with '1' to set corresponding bit in interrupt request register. + [0:0] + read-write + + + NOT_EMPTY + Write with '1' to set corresponding bit in interrupt status register. + [2:2] + read-write + + + FULL + Write with '1' to set corresponding bit in interrupt status register. + [3:3] + read-write + + + OVERFLOW + Write with '1' to set corresponding bit in interrupt status register. + [5:5] + read-write + + + UNDERFLOW + Write with '1' to set corresponding bit in interrupt status register. + [6:6] + read-write + + + BLOCKED + Write with '1' to set corresponding bit in interrupt status register. + [7:7] + read-write + + + FRAME_ERROR + Write with '1' to set corresponding bit in interrupt status register. + [8:8] + read-write + + + PARITY_ERROR + Write with '1' to set corresponding bit in interrupt status register. + [9:9] + read-write + + + BAUD_DETECT + Write with '1' to set corresponding bit in interrupt status register. + [10:10] + read-write + + + BREAK_DETECT + Write with '1' to set corresponding bit in interrupt status register. + [11:11] + read-write + + + + + INTR_RX_MASK + Receiver interrupt mask + 0xFC8 + 32 + read-write + 0x0 + 0xFED + + + TRIGGER + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + NOT_EMPTY + Mask bit for corresponding bit in interrupt request register. + [2:2] + read-write + + + FULL + Mask bit for corresponding bit in interrupt request register. + [3:3] + read-write + + + OVERFLOW + Mask bit for corresponding bit in interrupt request register. + [5:5] + read-write + + + UNDERFLOW + Mask bit for corresponding bit in interrupt request register. + [6:6] + read-write + + + BLOCKED + Mask bit for corresponding bit in interrupt request register. + [7:7] + read-write + + + FRAME_ERROR + Mask bit for corresponding bit in interrupt request register. + [8:8] + read-write + + + PARITY_ERROR + Mask bit for corresponding bit in interrupt request register. + [9:9] + read-write + + + BAUD_DETECT + Mask bit for corresponding bit in interrupt request register. + [10:10] + read-write + + + BREAK_DETECT + Mask bit for corresponding bit in interrupt request register. + [11:11] + read-write + + + + + INTR_RX_MASKED + Receiver interrupt masked request + 0xFCC + 32 + read-only + 0x0 + 0xFED + + + TRIGGER + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + NOT_EMPTY + Logical and of corresponding request and mask bits. + [2:2] + read-only + + + FULL + Logical and of corresponding request and mask bits. + [3:3] + read-only + + + OVERFLOW + Logical and of corresponding request and mask bits. + [5:5] + read-only + + + UNDERFLOW + Logical and of corresponding request and mask bits. + [6:6] + read-only + + + BLOCKED + Logical and of corresponding request and mask bits. + [7:7] + read-only + + + FRAME_ERROR + Logical and of corresponding request and mask bits. + [8:8] + read-only + + + PARITY_ERROR + Logical and of corresponding request and mask bits. + [9:9] + read-only + + + BAUD_DETECT + Logical and of corresponding request and mask bits. + [10:10] + read-only + + + BREAK_DETECT + Logical and of corresponding request and mask bits. + [11:11] + read-only + + + + + + + SCB1 + 0x40610000 + + + SCB2 + 0x40620000 + + + SCB4 + 0x40640000 + + + SCB5 + 0x40650000 + + + SCB6 + 0x40660000 + + + CTBM0 + Continuous Time Block Mini + CTBM + 0x40900000 + + 0 + 65536 + registers + + + + CTB_CTRL + global CTB and power control + 0x0 + 32 + read-write + 0x0 + 0xC0000000 + + + DEEPSLEEP_ON + - 0: CTBm is disabled during DeepSleep power mode +- 1: CTBm remains enabled during DeepSleep power mode (if ENABLED=1) + [30:30] + read-write + + + ENABLED + - 0: CTBm disabled (put analog in power down, open all switches) +- 1: CTBm enabled + [31:31] + read-write + + + + + OA_RES0_CTRL + Opamp0 and resistor0 control + 0x4 + 32 + read-write + 0x0 + 0x1BFF + + + OA0_PWR_MODE + Opamp power level. Reduced power levels also reduce gain-bandwidth (GBW). See the 'Opamp Specifications' table in the device Datasheet for more details. + [2:0] + read-write + + + OFF + N/A + 0 + + + LOW + Power setting = Low (low current consumption and GBW) + 1 + + + MEDIUM + Power setting = Medium (moderate current consumption and GBW) + 2 + + + HIGH + Power setting = High (high current consumption and GBW) + 3 + + + RSVD + N/A + 4 + + + PS_LOW + Power setting = Power Saver Low (works in Deep Sleep system power mode, with charge pump off, and reduced input common mode volage range) + 5 + + + PS_MEDIUM + Power setting = Power Saver Medium (works in Deep Sleep system power mode, with charge pump off, and reduced input common mode volage range) + 6 + + + PS_HIGH + Power setting = Power Saver High (works in Deep Sleep system power mode, with charge pump off, and reduced input common mode volage range) + 7 + + + + + OA0_DRIVE_STR_SEL + Opamp output drive strength: 0=1x, 1=10x. See the device Datasheet for exact current ranges and related specifications.This setting sets specific requirements for OA0_BOOST_EN and OA0_COMP_TRIM. + [3:3] + read-write + + + OA0_COMP_EN + N/A + [4:4] + read-write + + + OA0_HYST_EN + Opamp hysteresis enable. See the device Datasheet for hysteresis specifications. + [5:5] + read-write + + + OA0_BYPASS_DSI_SYNC + Opamp bypass comparator output synchronization for trigger output: 0=synchronize (level or pulse), 1=bypass (asynchronous output). + [6:6] + read-write + + + OA0_DSI_LEVEL + Opamp comparator trigger output level : +0=pulse, each time an edge is detected (see OA0_COMPINT) a pulse is sent out on trigger +1=level, trigger output is a synchronized version of the comparator output + [7:7] + read-write + + + OA0_COMPINT + Opamp comparator edge detect for interrupt and pulse mode of trigger + [9:8] + read-write + + + DISABLE + N/A + 0 + + + RISING + N/A + 1 + + + FALLING + N/A + 2 + + + BOTH + N/A + 3 + + + + + OA0_PUMP_EN + N/A + [11:11] + read-write + + + OA0_BOOST_EN + N/A + [12:12] + read-write + + + + + OA_RES1_CTRL + Opamp1 and resistor1 control + 0x8 + 32 + read-write + 0x0 + 0x1BFF + + + OA1_PWR_MODE + Opamp power level. Reduced power levels also reduce gain-bandwidth (GBW). See the 'Opamp Specifications' table in the device Datasheet for more details. + [2:0] + read-write + + + OA1_DRIVE_STR_SEL + Opamp output drive strength: 0=1x, 1=10x. See the device Datasheet for exact current ranges and related specifications.This setting sets specific requirements for OA1_BOOST_EN and OA1_COMP_TRIM + [3:3] + read-write + + + OA1_COMP_EN + N/A + [4:4] + read-write + + + OA1_HYST_EN + Opamp hysteresis enable. See the device Datasheet for hysteresis specifications. + [5:5] + read-write + + + OA1_BYPASS_DSI_SYNC + Opamp bypass comparator output synchronization for trigger output: 0=synchronize (level or pulse), 1=bypass (asynchronous output). + [6:6] + read-write + + + OA1_DSI_LEVEL + Opamp comparator trigger output level : +0=pulse, each time an edge is detected (see OA1_COMPINT) a pulse is sent out on trigger +1=level, trigger output is a synchronized version of the comparator output + [7:7] + read-write + + + OA1_COMPINT + Opamp comparator edge detect for interrupt and pulse mode of trigger + [9:8] + read-write + + + DISABLE + N/A + 0 + + + RISING + N/A + 1 + + + FALLING + N/A + 2 + + + BOTH + N/A + 3 + + + + + OA1_PUMP_EN + N/A + [11:11] + read-write + + + OA1_BOOST_EN + N/A + [12:12] + read-write + + + + + COMP_STAT + Comparator status + 0xC + 32 + read-only + 0x0 + 0x10001 + + + OA0_COMP + Opamp0 current comparator status + [0:0] + read-only + + + OA1_COMP + Opamp1 current comparator status + [16:16] + read-only + + + + + INTR + Interrupt request register + 0x20 + 32 + read-write + 0x0 + 0x3 + + + COMP0 + Comparator 0 Interrupt: hardware sets this interrupt when comparator 0 triggers. Write with '1' to clear bit. + [0:0] + read-write + + + COMP1 + Comparator 1 Interrupt: hardware sets this interrupt when comparator 1 triggers. Write with '1' to clear bit. + [1:1] + read-write + + + + + INTR_SET + Interrupt request set register + 0x24 + 32 + read-write + 0x0 + 0x3 + + + COMP0_SET + Write with '1' to set corresponding bit in interrupt request register. + [0:0] + read-write + + + COMP1_SET + Write with '1' to set corresponding bit in interrupt request register. + [1:1] + read-write + + + + + INTR_MASK + Interrupt request mask + 0x28 + 32 + read-write + 0x0 + 0x3 + + + COMP0_MASK + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + COMP1_MASK + Mask bit for corresponding bit in interrupt request register. + [1:1] + read-write + + + + + INTR_MASKED + Interrupt request masked + 0x2C + 32 + read-only + 0x0 + 0x3 + + + COMP0_MASKED + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + COMP1_MASKED + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + + + OA0_SW + Opamp0 switch control + 0x80 + 32 + read-write + 0x0 + 0x24410D + + + OA0P_A00 + Switch that connects Opamp's non-inverting terminal to AMUXBUS A. + [0:0] + read-write + + + OA0P_A20 + Switch that connects Opamp's non-inverting terminal to pin 0 of CTBm port. See the device Datasheet for the location of CTBm port. + [2:2] + read-write + + + OA0P_A30 + Switch that connects Opamp's non-inverting terminal to pin 6 of CTBm port. Note that this bus can have additional connections to or from the CTDAC. See the Architecture TRM for details. + [3:3] + read-write + + + OA0M_A11 + Switch that connects Opamp's inverting terminal to pin 1 of CTBm port . + [8:8] + read-write + + + OA0M_A81 + Switch that connects Opamp's inverting terminal to Opamp's output for follower mode. + [14:14] + read-write + + + OA0O_D51 + Switch that connects Opamp's output to SARBUS 0. + [18:18] + read-write + + + OA0O_D81 + Switch that shorts Opamp's 1x and 10x outputs. + [21:21] + read-write + + + + + OA0_SW_CLEAR + Opamp0 switch control clear + 0x84 + 32 + read-write + 0x0 + 0x24410D + + + OA0P_A00 + see corresponding bit in OA0_SW + [0:0] + read-write + + + OA0P_A20 + see corresponding bit in OA0_SW + [2:2] + read-write + + + OA0P_A30 + see corresponding bit in OA0_SW + [3:3] + read-write + + + OA0M_A11 + see corresponding bit in OA0_SW + [8:8] + read-write + + + OA0M_A81 + see corresponding bit in OA0_SW + [14:14] + read-write + + + OA0O_D51 + see corresponding bit in OA0_SW + [18:18] + read-write + + + OA0O_D81 + see corresponding bit in OA0_SW + [21:21] + read-write + + + + + OA1_SW + Opamp1 switch control + 0x88 + 32 + read-write + 0x0 + 0x2C4193 + + + OA1P_A03 + Switch that connects Opamp's non-inverting terminal to AMUXBUS B. + [0:0] + read-write + + + OA1P_A13 + Switch that connects Opamp's non-inverting terminal to pin 5 of CTBm port. See the device Datasheet for the location of CTBm port. + [1:1] + read-write + + + OA1P_A43 + Switch that connects Opamp's non-inverting terminal to pin 7 of CTBm port. + [4:4] + read-write + + + OA1P_A73 + Switch that connects Opamp's non-inverting terminal to VREF. + [7:7] + read-write + + + OA1M_A22 + Switch that connects Opamp's inverting terminal to pin 4 of CTBm port. + [8:8] + read-write + + + OA1M_A82 + Switch that connects Opamp's inverting terminal to Opamp's output for follower mode. + [14:14] + read-write + + + OA1O_D52 + Switch that connects Opamp's output to SARBUS 0. + [18:18] + read-write + + + OA1O_D62 + Switch that connects Opamp's output to SARBUS 1. + [19:19] + read-write + + + OA1O_D82 + Switch that shorts Opamp's 1x and 10x outputs. + [21:21] + read-write + + + + + OA1_SW_CLEAR + Opamp1 switch control clear + 0x8C + 32 + read-write + 0x0 + 0x2C4193 + + + OA1P_A03 + see corresponding bit in OA1_SW + [0:0] + read-write + + + OA1P_A13 + see corresponding bit in OA1_SW + [1:1] + read-write + + + OA1P_A43 + see corresponding bit in OA1_SW + [4:4] + read-write + + + OA1P_A73 + see corresponding bit in OA1_SW + [7:7] + read-write + + + OA1M_A22 + see corresponding bit in OA1_SW + [8:8] + read-write + + + OA1M_A82 + see corresponding bit in OA1_SW + [14:14] + read-write + + + OA1O_D52 + see corresponding bit in OA1_SW + [18:18] + read-write + + + OA1O_D62 + see corresponding bit in OA1_SW + [19:19] + read-write + + + OA1O_D82 + see corresponding bit in OA1_SW + [21:21] + read-write + + + + + CTD_SW + CTDAC connection switch control + 0xA0 + 32 + read-write + 0x0 + 0xF732 + + + CTDD_CRD + Switch that connects Opamp1's output to ctdrefdrive (CTDAC Reference Drive). + [1:1] + read-write + + + CTDS_CRS + Switch that connects Opamp1's inverting input to ctdrefsense (CTDAC Reference Sense). + [4:4] + read-write + + + CTDS_COR + Switch that connects Opamp1's inverting input to ctdvout (CTDAC Vout). + [5:5] + read-write + + + CTDO_C6H + Switch that connects pin 6 of the CTBm port to ctdvout (CTDAC Vout). See the device Datasheet for the location of CTBm port. + [8:8] + read-write + + + CTDO_COS + Switch that connects ctdvout to the internal hold capacitor (Sampling Switch). Note this switch will temporarily be opened for deglitching if CTDAC.DEGLITCH_COS is set. + [9:9] + read-write + + + CTDH_COB + Switch that connects hold capacitor to Opamp0's output. Used during hold mode in Sample and Hold operation. + [10:10] + read-write + + + CTDH_CHD + N/A + [12:12] + read-write + + + CTDH_CA0 + Switch that connects hold capacitor to Opamp0's non-inverting input. + [13:13] + read-write + + + CTDH_CIS + Switch that isolates hold capacitor from other inputs connected to Opamp0's non-inverting input. + [14:14] + read-write + + + CTDH_ILR + Switch that shorts Opamp0's inverting and non-inverting inputs to reduce hold capacitor leakage. + [15:15] + read-write + + + + + CTD_SW_CLEAR + CTDAC connection switch control clear + 0xA4 + 32 + read-write + 0x0 + 0xF732 + + + CTDD_CRD + see corresponding bit in CTD_SW + [1:1] + read-write + + + CTDS_CRS + see corresponding bit in CTD_SW + [4:4] + read-write + + + CTDS_COR + see corresponding bit in CTD_SW + [5:5] + read-write + + + CTDO_C6H + see corresponding bit in CTD_SW + [8:8] + read-write + + + CTDO_COS + see corresponding bit in CTD_SW + [9:9] + read-write + + + CTDH_COB + see corresponding bit in CTD_SW + [10:10] + read-write + + + CTDH_CHD + see corresponding bit in CTD_SW + [12:12] + read-write + + + CTDH_CA0 + see corresponding bit in CTD_SW + [13:13] + read-write + + + CTDH_CIS + see corresponding bit in CTD_SW + [14:14] + read-write + + + CTDH_ILR + see corresponding bit in CTD_SW + [15:15] + read-write + + + + + CTB_SW_DS_CTRL + CTB bus switch control + 0xC0 + 32 + read-write + 0x0 + 0x80000C00 + + + P2_DS_CTRL23 + N/A + [10:10] + read-write + + + P3_DS_CTRL23 + N/A + [11:11] + read-write + + + CTD_COS_DS_CTRL + N/A + [31:31] + read-write + + + + + CTB_SW_SQ_CTRL + CTB bus switch Sar Sequencer control + 0xC4 + 32 + read-write + 0x0 + 0xC00 + + + P2_SQ_CTRL23 + for D51 + [10:10] + read-write + + + P3_SQ_CTRL23 + for D52, D62 + [11:11] + read-write + + + + + CTB_SW_STATUS + CTB bus switch control status + 0xC8 + 32 + read-only + 0x0 + 0xF0000000 + + + OA0O_D51_STAT + see OA0O_D51 bit in OA0_SW + [28:28] + read-only + + + OA1O_D52_STAT + see OA1O_D52 bit in OA1_SW + [29:29] + read-only + + + OA1O_D62_STAT + see OA1O_D62 bit in OA1_SW + [30:30] + read-only + + + CTD_COS_STAT + see COS bit in CTD_SW + [31:31] + read-only + + + + + + + CTDAC0 + Continuous Time DAC + CTDAC + 0x40940000 + + 0 + 65536 + registers + + + + CTDAC_CTRL + Global CTDAC control + 0x0 + 32 + read-write + 0x0 + 0xFBC0033F + + + DEGLITCH_CNT + To prevent glitches after VALUE changes from propagating the output switch can be opened for DEGLITCH_CNT+1 clk_peri clock cycles. + [5:0] + read-write + + + DEGLITCH_CO6 + Force CTDAC.CO6 switch open after each VALUE change for the set number of clock cycles. + [8:8] + read-write + + + DEGLITCH_COS + Force CTB.COS switch open after each VALUE change for the set number of clock cycles. + [9:9] + read-write + + + OUT_EN + Output enable, intended to be used during the Hold phase of the Sample and Hold when power cycling : +0: output disabled, the output is either: + - Tri-state (DISABLED_MODE=0) + - or Vssa (DISABLED_MODE=1 && CTDAC_RANGE=0) + - or Vref (DISABLED_MODE=1 && CTDAC_RANGE=1) +1: output enabled, CTDAC output drives the programmed VALUE + [22:22] + read-write + + + CTDAC_RANGE + By closing the bottom switch in the R2R network the output is lifted by one LSB, effectively adding 1 +0: Range is [0, 4095] * Vref / 4096 +1: Range is [1, 4096] * Vref / 4096 + [23:23] + read-write + + + CTDAC_MODE + DAC mode, this determines the Value decoding + [25:24] + read-write + + + UNSIGNED12 + Unsigned 12-bit VDAC, i.e. no value decoding. + 0 + + + VIRT_SIGNED12 + Virtual signed 12-bits' VDAC. Value decoding: +add 0x800 to the 12-bit Value (=invert MSB), to convert the lowest signed number 0x800 to the lowest unsigned number 0x000. This is the same as the SAR handles 12-bit 'virtual' signed numbers. + 1 + + + RSVD2 + N/A + 2 + + + RSVD3 + N/A + 3 + + + + + DISABLED_MODE + Select the output value when the output is disabled (OUT_EN=0) (for risk mitigation) +0: Tri-state CTDAC output when disabled +1: output Vssa or Vref when disabled (see OUT_EN description) + [27:27] + read-write + + + DSI_STROBE_EN + DSI strobe input Enable. This enables CTDAC updates to be further throttled by DSI. +0: Ignore DSI strobe input +1: Only do a CTDAC update if allowed by the DSI strobe (throttle), see below for level or edge + [28:28] + read-write + + + DSI_STROBE_LEVEL + Select level or edge detect for DSI strobe +- 0: DSI strobe signal is a pulse input, after a positive edge is detected on the DSI strobe signal the next DAC value update is done on the next CTDAC clock +- 1: DSI strobe signal is a level input, as long as the DSI strobe signal remains high the CTDAC will do a next DAC value update on each CTDAC clock. + [29:29] + read-write + + + DEEPSLEEP_ON + - 0: CTDAC IP disabled off during DeepSleep power mode +- 1: CTDAC IP remains enabled during DeepSleep power mode (if ENABLED=1) + [30:30] + read-write + + + ENABLED + 0: CTDAC IP disabled (put analog in power down, open all switches) +1: CTDAC IP enabled + [31:31] + read-write + + + + + INTR + Interrupt request register + 0x20 + 32 + read-write + 0x0 + 0x1 + + + VDAC_EMPTY + VDAC Interrupt: hardware sets this interrupt when VDAC next value field is empty, i.e. was copied to the current VALUE. Write with '1' to clear bit. + [0:0] + read-write + + + + + INTR_SET + Interrupt request set register + 0x24 + 32 + read-write + 0x0 + 0x1 + + + VDAC_EMPTY_SET + Write with '1' to set corresponding bit in interrupt request register. + [0:0] + read-write + + + + + INTR_MASK + Interrupt request mask + 0x28 + 32 + read-write + 0x0 + 0x1 + + + VDAC_EMPTY_MASK + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + + + INTR_MASKED + Interrupt request masked + 0x2C + 32 + read-only + 0x0 + 0x1 + + + VDAC_EMPTY_MASKED + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + + + CTDAC_SW + CTDAC switch control + 0xB0 + 32 + read-write + 0x0 + 0x101 + + + CTDD_CVD + VDDA supply to ctdrefdrive + [0:0] + read-write + + + CTDO_CO6 + ctdvout to P6 pin. Note this switch will temporarily be opened for deglitching if DEGLITCH_CO6 is set + [8:8] + read-write + + + + + CTDAC_SW_CLEAR + CTDAC switch control clear + 0xB4 + 32 + read-write + 0x0 + 0x101 + + + CTDD_CVD + see corresponding bit in CTD_SW + [0:0] + read-write + + + CTDO_CO6 + see corresponding bit in CTD_SW + [8:8] + read-write + + + + + CTDAC_VAL + DAC Value + 0x100 + 32 + read-write + 0x0 + 0xFFF + + + VALUE + Value, in CTDAC_MODE 1 this value is decoded + [11:0] + read-write + + + + + CTDAC_VAL_NXT + Next DAC value (double buffering) + 0x104 + 32 + read-write + 0x0 + 0xFFF + + + VALUE + Next value for CTDAC_VAL.VALUE + [11:0] + read-write + + + + + + + SAR0 + SAR ADC with Sequencer + SAR + 0x409D0000 + + 0 + 65536 + registers + + + + CTRL + Analog control register. + 0x0 + 32 + read-write + 0x10000000 + 0xFF3FEEF7 + + + PWR_CTRL_VREF + VREF buffer low power mode. + [2:0] + read-write + + + PWR_100 + N/A + 0 + + + PWR_80 + N/A + 1 + + + PWR_60 + Power = 60 percent, Use this for SAR Clock Frequency greater than 3.6 MHz up to 18MHz.(with bypass cap) + 2 + + + PWR_50 + N/A + 3 + + + PWR_40 + N/A + 4 + + + PWR_30 + Power = 30 percent, Use this for SAR Clock Frequency less than or equal to 3.6MHz (with or without bypass cap) + 5 + + + PWR_20 + N/A + 6 + + + PWR_10 + N/A + 7 + + + + + VREF_SEL + N/A + [6:4] + read-write + + + VREF0 + N/A + 0 + + + VREF1 + N/A + 1 + + + VREF2 + N/A + 2 + + + VREF_AROUTE + N/A + 3 + + + VBGR + 1.2V from AREF (VREF buffer on) + 4 + + + VREF_EXT + N/A + 5 + + + VDDA_DIV_2 + N/A + 6 + + + VDDA + N/A + 7 + + + + + VREF_BYP_CAP_EN + N/A + [7:7] + read-write + + + NEG_SEL + N/A + [11:9] + read-write + + + VSSA_KELVIN + N/A + 0 + + + ART_VSSA + N/A + 1 + + + P1 + N/A + 2 + + + P3 + N/A + 3 + + + P5 + N/A + 4 + + + P7 + N/A + 5 + + + ACORE + N/A + 6 + + + VREF + N/A + 7 + + + + + SAR_HW_CTRL_NEGVREF + N/A + [13:13] + read-write + + + COMP_DLY + N/A + [15:14] + read-write + + + D2P5 + N/A + 0 + + + D4 + N/A + 1 + + + D10 + N/A + 2 + + + D12 + 12nS delay + 3 + + + + + SPARE + N/A + [19:16] + read-write + + + BOOSTPUMP_EN + N/A + [20:20] + read-write + + + REFBUF_EN + N/A + [21:21] + read-write + + + COMP_PWR + Comparator power mode. + [26:24] + read-write + + + P100 + N/A + 0 + + + P80 + N/A + 1 + + + P60 + Power = 60 percent, Use this for SAR Clock Frequency greater than 1.8MHz up to 18MHz. + 2 + + + P50 + N/A + 3 + + + P40 + N/A + 4 + + + P30 + N/A + 5 + + + P20 + Power = 20 percent, Use this for SAR Clock Frequency less than or equal to 1.8MHz + 6 + + + P10 + N/A + 7 + + + + + DEEPSLEEP_ON + N/A + [27:27] + read-write + + + DSI_SYNC_CONFIG + N/A + [28:28] + read-write + + + DSI_MODE + SAR sequencer takes configuration from DSI signals (note this also has the same effect as SWITCH_DISABLE==1) +- 0: Normal mode, SAR sequencer operates according to CHAN_EN enables and CHAN_CONFIG channel configurations +- 1: CHAN_EN and channel configurations in CHAN_CONFIG are ignored + [29:29] + read-write + + + SWITCH_DISABLE + Disable SAR sequencer from enabling routing switches +- 0: Normal mode, SAR sequencer changes switches according to pin address in channel configurations +- 1: Switches disabled, SAR sequencer does not enable any switches. Other methods such as firmware control can be used to set the switches to route the signal to be converted through the SARMUX + [30:30] + read-write + + + ENABLED + - 0: SAR disabled (put analog in power down and stop clocks), also can clear FW_TRIGGER on write. +- 1: SAR IP enabled. + [31:31] + read-write + + + + + SAMPLE_CTRL + Sample control register. + 0x4 + 32 + read-write + 0x80008 + 0xDFCF01FE + + + LEFT_ALIGN + N/A + [1:1] + read-write + + + SINGLE_ENDED_SIGNED + N/A + [2:2] + read-write + + + UNSIGNED + N/A + 0 + + + SIGNED + N/A + 1 + + + + + DIFFERENTIAL_SIGNED + N/A + [3:3] + read-write + + + UNSIGNED + N/A + 0 + + + SIGNED + N/A + 1 + + + + + AVG_CNT + N/A + [6:4] + read-write + + + AVG_SHIFT + N/A + [7:7] + read-write + + + AVG_MODE + Averaging mode + [8:8] + read-write + + + ACCUNDUMP + N/A + 0 + + + INTERLEAVED + N/A + 1 + + + + + CONTINUOUS + N/A + [16:16] + read-write + + + DSI_TRIGGER_EN + - 0: firmware trigger only: disable hardware trigger tr_sar_in. +- 1: enable hardware trigger tr_sar_in (e.g. from TCPWM, GPIO etc) + [17:17] + read-write + + + DSI_TRIGGER_LEVEL + N/A + [18:18] + read-write + + + DSI_SYNC_TRIGGER + N/A + [19:19] + read-write + + + UAB_SCAN_MODE + N/A + [22:22] + read-write + + + UNSCHEDULED + N/A + 0 + + + SCHEDULED + N/A + 1 + + + + + REPEAT_INVALID + N/A + [23:23] + read-write + + + VALID_SEL + N/A + [26:24] + read-write + + + VALID_SEL_EN + N/A + [27:27] + read-write + + + VALID_IGNORE + N/A + [28:28] + read-write + + + TRIGGER_OUT_EN + N/A + [30:30] + read-write + + + EOS_DSI_OUT_EN + Enable to output EOS_INTR. When enabled each time EOS_INTR is set by the hardware also a trigger pulse is send on the tr_sar_out signal. + [31:31] + read-write + + + + + SAMPLE_TIME01 + Sample time specification ST0 and ST1 + 0x10 + 32 + read-write + 0x30003 + 0x3FF03FF + + + SAMPLE_TIME0 + Sample time0 (aperture) in ADC clock cycles. Note that actual sample time is one clock less than specified here. The minimum sample time is 167ns, which is 3.0 cycles (4 in this field) with an 18MHz clock. Minimum legal value in this register is 2. + [9:0] + read-write + + + SAMPLE_TIME1 + Sample time1 + [25:16] + read-write + + + + + SAMPLE_TIME23 + Sample time specification ST2 and ST3 + 0x14 + 32 + read-write + 0x30003 + 0x3FF03FF + + + SAMPLE_TIME2 + Sample time2 + [9:0] + read-write + + + SAMPLE_TIME3 + Sample time3 + [25:16] + read-write + + + + + RANGE_THRES + Global range detect threshold register. + 0x18 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + RANGE_LOW + Low threshold for range detect. + [15:0] + read-write + + + RANGE_HIGH + High threshold for range detect. + [31:16] + read-write + + + + + RANGE_COND + Global range detect mode register. + 0x1C + 32 + read-write + 0x0 + 0xC0000000 + + + RANGE_COND + Range condition select. + [31:30] + read-write + + + BELOW + result < RANGE_LOW + 0 + + + INSIDE + RANGE_LOW <= result < RANGE_HIGH + 1 + + + ABOVE + RANGE_HIGH <= result + 2 + + + OUTSIDE + result < RANGE_LOW || RANGE_HIGH <= result + 3 + + + + + + + CHAN_EN + Enable bits for the channels + 0x20 + 32 + read-write + 0x0 + 0xFFFF + + + CHAN_EN + Channel enable. +- 0: the corresponding channel is disabled. +- 1: the corresponding channel is enabled, it will be included in the next scan. + [15:0] + read-write + + + + + START_CTRL + Start control register (firmware trigger). + 0x24 + 32 + read-write + 0x0 + 0x1 + + + FW_TRIGGER + When firmware writes a 1 here it will trigger the next scan of enabled channels, hardware clears this bit when the scan started with this trigger is completed. If scanning continuously the trigger is ignored and hardware clears this bit after the next scan is done. This bit is also cleared when the SAR is disabled. + [0:0] + read-write + + + + + 16 + 4 + CHAN_CONFIG[%s] + Channel configuration register. + 0x80 + 32 + read-write + 0x0 + 0x81773577 + + + POS_PIN_ADDR + N/A + [2:0] + read-write + + + POS_PORT_ADDR + N/A + [6:4] + read-write + + + SARMUX + N/A + 0 + + + CTB0 + N/A + 1 + + + CTB1 + N/A + 2 + + + CTB2 + N/A + 3 + + + CTB3 + N/A + 4 + + + AROUTE_VIRT2 + N/A + 5 + + + AROUTE_VIRT1 + N/A + 6 + + + SARMUX_VIRT + N/A + 7 + + + + + DIFFERENTIAL_EN + N/A + [8:8] + read-write + + + AVG_EN + N/A + [10:10] + read-write + + + SAMPLE_TIME_SEL + N/A + [13:12] + read-write + + + NEG_PIN_ADDR + N/A + [18:16] + read-write + + + NEG_PORT_ADDR + N/A + [22:20] + read-write + + + SARMUX + N/A + 0 + + + AROUTE_VIRT2 + N/A + 5 + + + AROUTE_VIRT1 + N/A + 6 + + + SARMUX_VIRT + N/A + 7 + + + + + NEG_ADDR_EN + N/A + [24:24] + read-write + + + DSI_OUT_EN + N/A + [31:31] + read-write + + + + + 16 + 4 + CHAN_WORK[%s] + Channel working data register + 0x100 + 32 + read-only + 0x0 + 0x88000000 + + + WORK + SAR conversion working data of the channel. The data is written here right after sampling this channel. + [15:0] + read-only + + + CHAN_WORK_NEWVALUE_MIR + mirror bit of corresponding bit in SAR_CHAN_WORK_NEWVALUE register + [27:27] + read-only + + + CHAN_WORK_UPDATED_MIR + mirror bit of corresponding bit in SAR_CHAN_WORK_UPDATED register + [31:31] + read-only + + + + + 16 + 4 + CHAN_RESULT[%s] + Channel result data register + 0x180 + 32 + read-only + 0x0 + 0xE8000000 + + + RESULT + SAR conversion result of the channel. The data is copied here from the WORK field after all enabled channels in this scan have been sampled. + [15:0] + read-only + + + CHAN_RESULT_NEWVALUE_MIR + mirror bit of corresponding bit in SAR_CHAN_RESULT_NEWVALUE register + [27:27] + read-only + + + SATURATE_INTR_MIR + mirror bit of corresponding bit in SAR_SATURATE_INTR register + [29:29] + read-only + + + RANGE_INTR_MIR + mirror bit of corresponding bit in SAR_RANGE_INTR register + [30:30] + read-only + + + CHAN_RESULT_UPDATED_MIR + mirror bit of corresponding bit in SAR_CHAN_RESULT_UPDATED register + [31:31] + read-only + + + + + CHAN_WORK_UPDATED + Channel working data register 'updated' bits + 0x200 + 32 + read-only + 0x0 + 0xFFFF + + + CHAN_WORK_UPDATED + If set the corresponding WORK register was updated, i.e. was already sampled during the current scan and, in case of Interleaved averaging, reached the averaging count. If this bit is low then either the channel is not enabled or the averaging count is not yet reached for Interleaved averaging. + [15:0] + read-only + + + + + CHAN_RESULT_UPDATED + Channel result data register 'updated' bits + 0x204 + 32 + read-only + 0x0 + 0xFFFF + + + CHAN_RESULT_UPDATED + If set the corresponding RESULT register was updated, i.e. was sampled during the previous scan and, in case of Interleaved averaging, reached the averaging count. If this bit is low then either the channel is not enabled or the averaging count is not yet reached for Interleaved averaging. + [15:0] + read-only + + + + + CHAN_WORK_NEWVALUE + Channel working data register 'new value' bits + 0x208 + 32 + read-only + 0x0 + 0xFFFF + + + CHAN_WORK_NEWVALUE + If set the corresponding WORK data received a new value, i.e. was already sampled during the current scan and data was valid. +In case of a UAB this New Value bit reflects the value of UAB.valid output, for anything else the data is always valid. +In case of averaging this New Value bit is an OR of all the valid bits received by each conversion. + [15:0] + read-only + + + + + CHAN_RESULT_NEWVALUE + Channel result data register 'new value' bits + 0x20C + 32 + read-only + 0x0 + 0xFFFF + + + CHAN_RESULT_NEWVALUE + If set the corresponding RESULT data received a new value, i.e. was sampled during the last scan and data was valid. +In case of a UAB this New Value bit reflects the value of UAB.valid output, for anything else the data is always valid. +In case of averaging this New Value bit is an OR of all the valid bits received by each conversion. + [15:0] + read-only + + + + + INTR + Interrupt request register. + 0x210 + 32 + read-write + 0x0 + 0xFF + + + EOS_INTR + N/A + [0:0] + read-write + + + OVERFLOW_INTR + N/A + [1:1] + read-write + + + FW_COLLISION_INTR + N/A + [2:2] + read-write + + + DSI_COLLISION_INTR + This interrupt is set when a hardware trigger signal is asserted while the SAR is BUSY. Raising this interrupt is delayed to when the scan caused by the hardware trigger has been completed, i.e. not when the preceding scan with which this trigger collided is completed. When this interrupt is set it implies that the channels were sampled later than was intended (jitter). Write with '1' to clear bit. + [3:3] + read-write + + + INJ_EOC_INTR + N/A + [4:4] + read-write + + + INJ_SATURATE_INTR + N/A + [5:5] + read-write + + + INJ_RANGE_INTR + N/A + [6:6] + read-write + + + INJ_COLLISION_INTR + N/A + [7:7] + read-write + + + + + INTR_SET + Interrupt set request register + 0x214 + 32 + read-write + 0x0 + 0xFF + + + EOS_SET + N/A + [0:0] + read-write + + + OVERFLOW_SET + N/A + [1:1] + read-write + + + FW_COLLISION_SET + N/A + [2:2] + read-write + + + DSI_COLLISION_SET + N/A + [3:3] + read-write + + + INJ_EOC_SET + N/A + [4:4] + read-write + + + INJ_SATURATE_SET + N/A + [5:5] + read-write + + + INJ_RANGE_SET + N/A + [6:6] + read-write + + + INJ_COLLISION_SET + N/A + [7:7] + read-write + + + + + INTR_MASK + Interrupt mask register. + 0x218 + 32 + read-write + 0x0 + 0xFF + + + EOS_MASK + N/A + [0:0] + read-write + + + OVERFLOW_MASK + N/A + [1:1] + read-write + + + FW_COLLISION_MASK + N/A + [2:2] + read-write + + + DSI_COLLISION_MASK + N/A + [3:3] + read-write + + + INJ_EOC_MASK + N/A + [4:4] + read-write + + + INJ_SATURATE_MASK + N/A + [5:5] + read-write + + + INJ_RANGE_MASK + N/A + [6:6] + read-write + + + INJ_COLLISION_MASK + N/A + [7:7] + read-write + + + + + INTR_MASKED + Interrupt masked request register + 0x21C + 32 + read-only + 0x0 + 0xFF + + + EOS_MASKED + N/A + [0:0] + read-only + + + OVERFLOW_MASKED + N/A + [1:1] + read-only + + + FW_COLLISION_MASKED + N/A + [2:2] + read-only + + + DSI_COLLISION_MASKED + N/A + [3:3] + read-only + + + INJ_EOC_MASKED + N/A + [4:4] + read-only + + + INJ_SATURATE_MASKED + N/A + [5:5] + read-only + + + INJ_RANGE_MASKED + N/A + [6:6] + read-only + + + INJ_COLLISION_MASKED + N/A + [7:7] + read-only + + + + + SATURATE_INTR + Saturate interrupt request register. + 0x220 + 32 + read-write + 0x0 + 0xFFFF + + + SATURATE_INTR + Saturate Interrupt: hardware sets this interrupt for each channel if a conversion result (before averaging) of that channel is either 0x000 or 0xFFF, this is an indication that the ADC likely saturated. Write with '1' to clear bit. + [15:0] + read-write + + + + + SATURATE_INTR_SET + Saturate interrupt set request register + 0x224 + 32 + read-write + 0x0 + 0xFFFF + + + SATURATE_SET + Write with '1' to set corresponding bit in interrupt request register. + [15:0] + read-write + + + + + SATURATE_INTR_MASK + Saturate interrupt mask register. + 0x228 + 32 + read-write + 0x0 + 0xFFFF + + + SATURATE_MASK + Mask bit for corresponding bit in interrupt request register. + [15:0] + read-write + + + + + SATURATE_INTR_MASKED + Saturate interrupt masked request register + 0x22C + 32 + read-only + 0x0 + 0xFFFF + + + SATURATE_MASKED + Logical and of corresponding request and mask bits. + [15:0] + read-only + + + + + RANGE_INTR + Range detect interrupt request register. + 0x230 + 32 + read-write + 0x0 + 0xFFFF + + + RANGE_INTR + Range detect Interrupt: hardware sets this interrupt for each channel if the conversion result (after averaging) of that channel met the condition specified by the SAR_RANGE registers. Write with '1' to clear bit. + [15:0] + read-write + + + + + RANGE_INTR_SET + Range detect interrupt set request register + 0x234 + 32 + read-write + 0x0 + 0xFFFF + + + RANGE_SET + Write with '1' to set corresponding bit in interrupt request register. + [15:0] + read-write + + + + + RANGE_INTR_MASK + Range detect interrupt mask register. + 0x238 + 32 + read-write + 0x0 + 0xFFFF + + + RANGE_MASK + Mask bit for corresponding bit in interrupt request register. + [15:0] + read-write + + + + + RANGE_INTR_MASKED + Range interrupt masked request register + 0x23C + 32 + read-only + 0x0 + 0xFFFF + + + RANGE_MASKED + Logical and of corresponding request and mask bits. + [15:0] + read-only + + + + + INTR_CAUSE + Interrupt cause register + 0x240 + 32 + read-only + 0x0 + 0xC00000FF + + + EOS_MASKED_MIR + N/A + [0:0] + read-only + + + OVERFLOW_MASKED_MIR + N/A + [1:1] + read-only + + + FW_COLLISION_MASKED_MIR + N/A + [2:2] + read-only + + + DSI_COLLISION_MASKED_MIR + N/A + [3:3] + read-only + + + INJ_EOC_MASKED_MIR + N/A + [4:4] + read-only + + + INJ_SATURATE_MASKED_MIR + N/A + [5:5] + read-only + + + INJ_RANGE_MASKED_MIR + N/A + [6:6] + read-only + + + INJ_COLLISION_MASKED_MIR + N/A + [7:7] + read-only + + + SATURATE_MASKED_RED + N/A + [30:30] + read-only + + + RANGE_MASKED_RED + N/A + [31:31] + read-only + + + + + STATUS + Current status of internal SAR registers (mostly for debug) + 0x2A0 + 32 + read-only + 0x0 + 0xC000001F + + + CUR_CHAN + current channel being sampled (channel 16 indicates the injection channel), only valid if BUSY. + [4:0] + read-only + + + SW_VREF_NEG + the current switch status, including DSI and sequencer controls, of the switch in the SARADC that shorts NEG with VREF input (see NEG_SEL). + [30:30] + read-only + + + BUSY + If high then the SAR is busy with a conversion. This bit is always high when CONTINUOUS is set. Firmware should wait for this bit to be low before putting the SAR in power down. + [31:31] + read-only + + + + + AVG_STAT + Current averaging status (for debug) + 0x2A4 + 32 + read-only + 0x0 + 0xFF8FFFFF + + + CUR_AVG_ACCU + the current value of the averaging accumulator + [19:0] + read-only + + + INTRLV_BUSY + If high then the SAR is in the middle of Interleaved averaging spanning several scans. While this bit is high the Firmware should not make any changes to the configuration registers otherwise some results may be incorrect. Note that the CUR_AVG_CNT status register below gives an indication how many more scans need to be done to complete the Interleaved averaging. +This bit can be cleared by changing the averaging mode to ACCUNDUMP or by disabling the SAR. + [23:23] + read-only + + + CUR_AVG_CNT + the current value of the averaging counter. Note that the value shown is updated after the sampling time and therefore runs ahead of the accumulator update. + [31:24] + read-only + + + + + MUX_SWITCH0 + SARMUX Firmware switch controls + 0x300 + 32 + read-write + 0x0 + 0x3FFFFFFF + + + MUX_FW_P0_VPLUS + N/A + [0:0] + read-write + + + MUX_FW_P1_VPLUS + N/A + [1:1] + read-write + + + MUX_FW_P2_VPLUS + N/A + [2:2] + read-write + + + MUX_FW_P3_VPLUS + N/A + [3:3] + read-write + + + MUX_FW_P4_VPLUS + N/A + [4:4] + read-write + + + MUX_FW_P5_VPLUS + N/A + [5:5] + read-write + + + MUX_FW_P6_VPLUS + N/A + [6:6] + read-write + + + MUX_FW_P7_VPLUS + N/A + [7:7] + read-write + + + MUX_FW_P0_VMINUS + N/A + [8:8] + read-write + + + MUX_FW_P1_VMINUS + N/A + [9:9] + read-write + + + MUX_FW_P2_VMINUS + N/A + [10:10] + read-write + + + MUX_FW_P3_VMINUS + N/A + [11:11] + read-write + + + MUX_FW_P4_VMINUS + N/A + [12:12] + read-write + + + MUX_FW_P5_VMINUS + N/A + [13:13] + read-write + + + MUX_FW_P6_VMINUS + N/A + [14:14] + read-write + + + MUX_FW_P7_VMINUS + N/A + [15:15] + read-write + + + MUX_FW_VSSA_VMINUS + N/A + [16:16] + read-write + + + MUX_FW_TEMP_VPLUS + N/A + [17:17] + read-write + + + MUX_FW_AMUXBUSA_VPLUS + N/A + [18:18] + read-write + + + MUX_FW_AMUXBUSB_VPLUS + N/A + [19:19] + read-write + + + MUX_FW_AMUXBUSA_VMINUS + N/A + [20:20] + read-write + + + MUX_FW_AMUXBUSB_VMINUS + N/A + [21:21] + read-write + + + MUX_FW_SARBUS0_VPLUS + N/A + [22:22] + read-write + + + MUX_FW_SARBUS1_VPLUS + N/A + [23:23] + read-write + + + MUX_FW_SARBUS0_VMINUS + N/A + [24:24] + read-write + + + MUX_FW_SARBUS1_VMINUS + N/A + [25:25] + read-write + + + MUX_FW_P4_COREIO0 + N/A + [26:26] + read-write + + + MUX_FW_P5_COREIO1 + N/A + [27:27] + read-write + + + MUX_FW_P6_COREIO2 + N/A + [28:28] + read-write + + + MUX_FW_P7_COREIO3 + N/A + [29:29] + read-write + + + + + MUX_SWITCH_CLEAR0 + SARMUX Firmware switch control clear + 0x304 + 32 + read-write + 0x0 + 0x3FFFFFFF + + + MUX_FW_P0_VPLUS + N/A + [0:0] + read-write + + + MUX_FW_P1_VPLUS + N/A + [1:1] + read-write + + + MUX_FW_P2_VPLUS + N/A + [2:2] + read-write + + + MUX_FW_P3_VPLUS + N/A + [3:3] + read-write + + + MUX_FW_P4_VPLUS + N/A + [4:4] + read-write + + + MUX_FW_P5_VPLUS + N/A + [5:5] + read-write + + + MUX_FW_P6_VPLUS + N/A + [6:6] + read-write + + + MUX_FW_P7_VPLUS + N/A + [7:7] + read-write + + + MUX_FW_P0_VMINUS + N/A + [8:8] + read-write + + + MUX_FW_P1_VMINUS + N/A + [9:9] + read-write + + + MUX_FW_P2_VMINUS + N/A + [10:10] + read-write + + + MUX_FW_P3_VMINUS + N/A + [11:11] + read-write + + + MUX_FW_P4_VMINUS + N/A + [12:12] + read-write + + + MUX_FW_P5_VMINUS + N/A + [13:13] + read-write + + + MUX_FW_P6_VMINUS + N/A + [14:14] + read-write + + + MUX_FW_P7_VMINUS + N/A + [15:15] + read-write + + + MUX_FW_VSSA_VMINUS + N/A + [16:16] + read-write + + + MUX_FW_TEMP_VPLUS + N/A + [17:17] + read-write + + + MUX_FW_AMUXBUSA_VPLUS + N/A + [18:18] + read-write + + + MUX_FW_AMUXBUSB_VPLUS + N/A + [19:19] + read-write + + + MUX_FW_AMUXBUSA_VMINUS + N/A + [20:20] + read-write + + + MUX_FW_AMUXBUSB_VMINUS + N/A + [21:21] + read-write + + + MUX_FW_SARBUS0_VPLUS + N/A + [22:22] + read-write + + + MUX_FW_SARBUS1_VPLUS + N/A + [23:23] + read-write + + + MUX_FW_SARBUS0_VMINUS + N/A + [24:24] + read-write + + + MUX_FW_SARBUS1_VMINUS + N/A + [25:25] + read-write + + + MUX_FW_P4_COREIO0 + N/A + [26:26] + read-write + + + MUX_FW_P5_COREIO1 + N/A + [27:27] + read-write + + + MUX_FW_P6_COREIO2 + N/A + [28:28] + read-write + + + MUX_FW_P7_COREIO3 + N/A + [29:29] + read-write + + + + + MUX_SWITCH_SQ_CTRL + SARMUX switch Sar Sequencer control + 0x344 + 32 + read-write + 0x0 + 0xCF00FF + + + MUX_SQ_CTRL_P0 + for P0 switches + [0:0] + read-write + + + MUX_SQ_CTRL_P1 + for P1 switches + [1:1] + read-write + + + MUX_SQ_CTRL_P2 + for P2 switches + [2:2] + read-write + + + MUX_SQ_CTRL_P3 + for P3 switches + [3:3] + read-write + + + MUX_SQ_CTRL_P4 + for P4 switches + [4:4] + read-write + + + MUX_SQ_CTRL_P5 + for P5 switches + [5:5] + read-write + + + MUX_SQ_CTRL_P6 + for P6 switches + [6:6] + read-write + + + MUX_SQ_CTRL_P7 + for P7 switches + [7:7] + read-write + + + MUX_SQ_CTRL_VSSA + for vssa switch + [16:16] + read-write + + + MUX_SQ_CTRL_TEMP + for temp switch + [17:17] + read-write + + + MUX_SQ_CTRL_AMUXBUSA + for amuxbusa switch + [18:18] + read-write + + + MUX_SQ_CTRL_AMUXBUSB + for amuxbusb switches + [19:19] + read-write + + + MUX_SQ_CTRL_SARBUS0 + for sarbus0 switch + [22:22] + read-write + + + MUX_SQ_CTRL_SARBUS1 + for sarbus1 switch + [23:23] + read-write + + + + + MUX_SWITCH_STATUS + SARMUX switch status + 0x348 + 32 + read-only + 0x0 + 0x3FFFFFF + + + MUX_FW_P0_VPLUS + switch status of corresponding bit in MUX_SWITCH0 + [0:0] + read-only + + + MUX_FW_P1_VPLUS + switch status of corresponding bit in MUX_SWITCH0 + [1:1] + read-only + + + MUX_FW_P2_VPLUS + switch status of corresponding bit in MUX_SWITCH0 + [2:2] + read-only + + + MUX_FW_P3_VPLUS + switch status of corresponding bit in MUX_SWITCH0 + [3:3] + read-only + + + MUX_FW_P4_VPLUS + switch status of corresponding bit in MUX_SWITCH0 + [4:4] + read-only + + + MUX_FW_P5_VPLUS + switch status of corresponding bit in MUX_SWITCH0 + [5:5] + read-only + + + MUX_FW_P6_VPLUS + switch status of corresponding bit in MUX_SWITCH0 + [6:6] + read-only + + + MUX_FW_P7_VPLUS + switch status of corresponding bit in MUX_SWITCH0 + [7:7] + read-only + + + MUX_FW_P0_VMINUS + switch status of corresponding bit in MUX_SWITCH0 + [8:8] + read-only + + + MUX_FW_P1_VMINUS + switch status of corresponding bit in MUX_SWITCH0 + [9:9] + read-only + + + MUX_FW_P2_VMINUS + switch status of corresponding bit in MUX_SWITCH0 + [10:10] + read-only + + + MUX_FW_P3_VMINUS + switch status of corresponding bit in MUX_SWITCH0 + [11:11] + read-only + + + MUX_FW_P4_VMINUS + switch status of corresponding bit in MUX_SWITCH0 + [12:12] + read-only + + + MUX_FW_P5_VMINUS + switch status of corresponding bit in MUX_SWITCH0 + [13:13] + read-only + + + MUX_FW_P6_VMINUS + switch status of corresponding bit in MUX_SWITCH0 + [14:14] + read-only + + + MUX_FW_P7_VMINUS + switch status of corresponding bit in MUX_SWITCH0 + [15:15] + read-only + + + MUX_FW_VSSA_VMINUS + switch status of corresponding bit in MUX_SWITCH0 + [16:16] + read-only + + + MUX_FW_TEMP_VPLUS + switch status of corresponding bit in MUX_SWITCH0 + [17:17] + read-only + + + MUX_FW_AMUXBUSA_VPLUS + switch status of corresponding bit in MUX_SWITCH0 + [18:18] + read-only + + + MUX_FW_AMUXBUSB_VPLUS + switch status of corresponding bit in MUX_SWITCH0 + [19:19] + read-only + + + MUX_FW_AMUXBUSA_VMINUS + switch status of corresponding bit in MUX_SWITCH0 + [20:20] + read-only + + + MUX_FW_AMUXBUSB_VMINUS + switch status of corresponding bit in MUX_SWITCH0 + [21:21] + read-only + + + MUX_FW_SARBUS0_VPLUS + switch status of corresponding bit in MUX_SWITCH0 + [22:22] + read-only + + + MUX_FW_SARBUS1_VPLUS + switch status of corresponding bit in MUX_SWITCH0 + [23:23] + read-only + + + MUX_FW_SARBUS0_VMINUS + switch status of corresponding bit in MUX_SWITCH0 + [24:24] + read-only + + + MUX_FW_SARBUS1_VMINUS + switch status of corresponding bit in MUX_SWITCH0 + [25:25] + read-only + + + + + + + SAR1 + 0x409E0000 + + + PASS + PASS top-level MMIO (AREF, LPOSC, FIFO, INTR, Trigger) + 0x409F0000 + + 0 + 65536 + registers + + + + INTR_CAUSE + Interrupt cause register + 0x0 + 32 + read-only + 0x0 + 0xFFFF + + + CTB0_INT + CTB0 interrupt pending + [0:0] + read-only + + + CTB1_INT + CTB1 interrupt pending + [1:1] + read-only + + + CTB2_INT + CTB2 interrupt pending + [2:2] + read-only + + + CTB3_INT + CTB3 interrupt pending + [3:3] + read-only + + + CTDAC0_INT + CTDAC0 interrupt pending + [4:4] + read-only + + + CTDAC1_INT + CTDAC1 interrupt pending + [5:5] + read-only + + + CTDAC2_INT + CTDAC2 interrupt pending + [6:6] + read-only + + + CTDAC3_INT + CTDAC3 interrupt pending + [7:7] + read-only + + + SAR0_INT + SAR0 interrupt pending + [8:8] + read-only + + + SAR1_INT + SAR1 interrupt pending + [9:9] + read-only + + + SAR2_INT + SAR2 interrupt pending + [10:10] + read-only + + + SAR3_INT + SAR3 interrupt pending + [11:11] + read-only + + + FIFO0_INT + FIFO0 interrupt pending + [12:12] + read-only + + + FIFO1_INT + FIFO1 interrupt pending + [13:13] + read-only + + + FIFO2_INT + FIFO2 interrupt pending + [14:14] + read-only + + + FIFO3_INT + FIFO3 interrupt pending + [15:15] + read-only + + + + + DPSLP_CLOCK_SEL + Deepsleep clock select + 0x10 + 32 + read-write + 0x20 + 0x71 + + + DPSLP_CLOCK_SEL + Select source for PASS DPSLP Clock + [0:0] + read-write + + + CLK_LPOSC + CLK_DPSLP is set to CLK_LPOSC + 0 + + + CLK_MF + CLK_DPSLP is set to CLK_MF + 1 + + + + + DPSLP_CLOCK_DIV + CLK_DPSLP divider + [6:4] + read-write + + + NO_DIV + Transparent mode, feed through selected clock source w/o dividing. + 0 + + + DIV_BY_2 + Divide selected clock source by 2 + 1 + + + DIV_BY_4 + Divide selected clock source by 4 + 2 + + + DIV_BY_8 + Divide selected clock source by 8 + 3 + + + DIV_BY_16 + Divide selected clock source by 16 + 4 + + + RSVD_0 + N/A + 5 + + + RSVD_1 + N/A + 6 + + + RSVD_2 + N/A + 7 + + + + + + + PWR_WAKE_CTRL + Deepsleep wakeup control + 0x14 + 32 + read-write + 0x0 + 0x3F + + + WAKE_DELAY + Wakeup holdoff. Fastest wake time is achieved with a setting of 0. Additional delay can be added to allow for PASS settling. The delay is counted by CLK_DPSLP. + [5:0] + read-write + + + + + CTBM_CLOCK_SEL + Clock select for CTBm + 0x20 + 32 + read-write + 0x0 + 0x1 + + + PUMP_CLOCK_SEL + Select source for CTBm Pump Clock. + [0:0] + read-write + + + LEGACY + CTBm pump clock set by AREF.CTRL.CLOCK_PUMP_PERI_SEL (Legacy) + 0 + + + CLK_DPSLP + CTBm pump clock sourced from CLK_DPSLP + 1 + + + + + + + 2 + 4 + SAR_DPSLP_CTRL[%s] + Deepsleep control for SARv3 + 0x30 + 32 + read-write + 0x0 + 0x80000000 + + + ENABLED + enable for SAR deepsleep operation. SAR_DPSLP_CONFIG.DEEPSLEEP_ON must be set to 1 for this field to affect SAR operation. + +- 0: SAR deeepsleep operation disabled +- 1: SAR deepsleep operation enabled. + [31:31] + read-write + + + + + 2 + 4 + SAR_DPSLP_CONFIG[%s] + Deepsleep configuration for SARv3 + 0x40 + 32 + read-write + 0x0 + 0x40000000 + + + DEEPSLEEP_ON + SAR Deepsleep control bit + [30:30] + read-write + + + LEGACY + - 0: legacy: SAR operational in ACTIVE mode only + 0 + + + DEEPSLEEP_ENABLED + - 1: SAR operational in ACTIVE and DEEPSLEEP modes + 1 + + + + + + + SAR_HW_TR_SMP_CNT + SAR HW trigger sample control + 0x50 + 32 + read-write + 0x0 + 0x3F + + + SMP_CNT + SAR HW trigger sample counter. This field determines the number of samples a SAR will take when configured for level sensitive hardwire triggering. The number os samples is SMP_COUNT+1. + +This feature can be enabled for individual SARs by setting the appropriate bit of SAR_HW_TR_CTRL.HW_TR_SMP_CNT_SEL. + +This feature can be enabled for simultaneously sampled SARs by setting SAR_SIMULT_HW_TR_CTRL.SIMULT_HW_TR_SMP_CNT_SEL. + [5:0] + read-write + + + + + SAR_HW_TR_CTRL + SAR HW trigger override + 0x54 + 32 + read-write + 0x0 + 0xFF + + + HW_TR_TIMER_SEL + SAR hardware trigger source select (one bit per SAR) +-0: Legacy (tr_sar_in_<N>) +-1: Timer trigger + +<0>: HW Trigger source for SAR0 +<1>: HW Trigger source for SAR1 +<2>: HW Trigger source for SAR2 +<3>: HW Trigger source for SAR3 + [3:0] + read-write + + + HW_TR_SMP_CNT_SEL + SAR Hardware trigger sample select (one bit per SAR) +-0: Disabled +-1: Enabled, SAR takes SAR_HW_TR_SMP_CNT per hardware trigger + +<0>: HW trigger sample select for SAR0 +<1>: HW trigger sample select for SAR1 +<2>: HW trigger sample select for SAR2 +<3>: HW trigger sample select for SAR3 + [7:4] + read-write + + + + + SAR_SIMULT_HW_TR_CTRL + SAR simultaneous trigger control + 0x58 + 32 + read-write + 0x80000 + 0x1C013F + + + SIMULT_HW_TR_EN + SAR simultaneous hwardware triggering enable (one bit per SAR) +-0: disabled +-1: SAR trigger override enabled (SAR trigger set by SAR_SIMULT_TR_CTRL register) + +<0>: Simultaneuous sampling enable for SAR0 +<1>: Simultaneuous sampling enable for SAR1 +<2>: Simultaneuous sampling enable for SAR2 +<3>: Simultaneuous sampling enable for SAR3 + +Simultaneous sampling requires at least two bits in this field to be set. +If less than two bits are set, this register will not affect SAR operation. + [3:0] + read-write + + + SIMULT_HW_TR_SRC + Source for Simult Hardware trigger + [5:4] + read-write + + + SAR_TR_IN_0 + SAR 0 HW Trigger Input + 0 + + + SAR_TR_IN_1 + SAR 1 HW Trigger Input + 1 + + + SAR_TR_IN_2 + SAR 2 HW Trigger Input + 2 + + + SAR_TR_IN_3 + SAR 3 HW Trigger Input + 3 + + + + + SIMULT_HW_TR_TIMER_SEL + SAR hardware trigger source select +-0: SIMULT_HW_TR_SRC +-1: Timer trigger + [8:8] + read-write + + + SIMULT_HW_TR_LEVEL + - 0: trigger signal is a pulse input, a positive edge detected on the trigger signal triggers a new scan. +- 1: trigger signal is a level input, as long as the trigger signal remains high the SAR will do continuous scans. + [18:18] + read-write + + + SIMULT_HW_SYNC_TR + - 0: bypass clock domain synchronization of the Simult trigger signal. +- 1: synchronize the Simult trigger signal to the SAR clock domain, if needed an edge detect is done in the peripheral clock domain. + [19:19] + read-write + + + SIMULT_HW_TR_SMP_CNT_SEL + Simultaneous Hardware trigger sample select +-0: Disabled +-1: Enabled, SAR takes SAR_HW_TR_SMP_CNT per hardware trigger + [20:20] + read-write + + + + + SAR_SIMULT_FW_START_CTRL + SAR simultaneous start control + 0x5C + 32 + read-write + 0x0 + 0xF000F + + + FW_TRIGGER + This field is used to simultaneously FW trigger two or more SARs. + +<0>: Firmware trigger for SAR0 +<1>: Firmware trigger for SAR1 +<2>: Firmware trigger for SAR2 +<3>: Firmware trigger for SAR3 + +If less than two bits are set, this field has no effect. + [3:0] + read-write + + + CONTINUOUS + This field is used to configure two or more SARs for continuous operation. + +-0: Continuous mode disabled +-1: Continuously scan enabled channels, ignore triggers. + +<0>: Continuous Mode for SAR0 +<1>: Continuous Mode for SAR1 +<2>: Continuous Mode for SAR2 +<3>: Continuous Mode for SAR3 + +If less than two bits are set, this field has no effect. + [19:16] + read-write + + + + + SAR_TR_OUT_CTRL + SAR trigger out control + 0x60 + 32 + read-write + 0x0 + 0xF + + + SAR0_TR_OUT_SEL + SAR0 Trigger Out Source Select + [0:0] + read-write + + + LEGACY + sar output trigger is set by SAR.SAMPLE_CTRL.EOS_DSI_OUT_EN condition + 0 + + + BUFFER_TRIGGER_LEVEL + sar output trigger is set by FIFO.CTRL.FIFO_LEVEL condition + 1 + + + + + SAR1_TR_OUT_SEL + SAR1 Trigger Out Source Select + [1:1] + read-write + + + LEGACY + sar output trigger is set by SAR.SAMPLE_CTRL.EOS_DSI_OUT_EN condition + 0 + + + BUFFER_TRIGGER_LEVEL + sar output trigger is set by FIFO.CTRL.FIFO_LEVEL condition + 1 + + + + + SAR2_TR_OUT_SEL + SAR2 Trigger Out Source Select + [2:2] + read-write + + + LEGACY + sar output trigger is set by SAR.SAMPLE_CTRL.EOS_DSI_OUT_EN condition + 0 + + + BUFFER_TRIGGER_LEVEL + sar output trigger is set by FIFO.CTRL.FIFO_LEVEL condition + 1 + + + + + SAR3_TR_OUT_SEL + SAR3 Trigger Out Source Select + [3:3] + read-write + + + LEGACY + sar output trigger is set by SAR.SAMPLE_CTRL.EOS_DSI_OUT_EN condition + 0 + + + BUFFER_TRIGGER_LEVEL + sar output trigger is set by FIFO.CTRL.FIFO_LEVEL condition + 1 + + + + + + + TIMER + Programmable Analog Subsystem + 0x00000100 + + CTRL + Timer control register + 0x0 + 32 + read-write + 0x0 + 0x80000000 + + + ENABLED + 0=disabled, 1=enabled + [31:31] + read-write + + + + + CONFIG + Timer configuration register + 0x4 + 32 + read-write + 0x0 + 0x3 + + + CLOCK_SEL + Select Clock source of the Timer + [1:0] + read-write + + + CLK_PERI + Timer clocked from CLK_PERI + 0 + + + CLK_DPSLP + Timer clocked from CLK_DPSLP + 1 + + + CLK_LF + Timer clocked from CLK_LF + 2 + + + TBD + N/A + 3 + + + + + + + TIMER_PERIOD + Timer period register + 0x8 + 32 + read-write + 0x0 + 0xFFFF + + + PER_VAL + Actual timer period is PER_VAL+1 (1 to 65536) + [15:0] + read-write + + + + + + LPOSC + LPOSC configuration + 0x00000200 + + CTRL + Low Power Oscillator control + 0x0 + 32 + read-write + 0x0 + 0x80000000 + + + ENABLED + Master enable for LPOSC oscillator. This bit must be high at all times for all functions to work properly. Hardware will automatically disable the LPOSC during DEEPSLEEP (unless DEEPSLEEP_ON is set), HIBERNATE, and XRES. + [31:31] + read-write + + + + + CONFIG + Low Power Oscillator configuration register + 0x4 + 32 + read-write + 0x0 + 0x1 + + + DEEPSLEEP_MODE + LPOSC functionality while in DEEPSLEEP + [0:0] + read-write + + + DUTYCYCLED + LPOSC always on in deepsleep + 0 + + + ALWAYS_ON + LPOSC enabled by TIMER trigger + 1 + + + + + + + ADFT + Retention + 0x8 + 32 + read-write + 0x0 + 0x3 + + + ADFT_SEL + ADFT selection for LPOSC. +0: DFT disabled +1: Measure Vdo; expect ~1.15V +2: Measure Ibias_ptat; expect ~30nA +3: Measure Ibias_ctat; expect ~30nA + [1:0] + read-write + + + + + + 2 + 256 + FIFO[%s] + FIFO configuration + 0x00000300 + + CTRL + FIFO control register + 0x0 + 32 + read-write + 0x0 + 0x80000000 + + + ENABLED + Enable for SAR FIFO functionality: +- 0: FIFO disabled +- 1: FIFO enabled + [31:31] + read-write + + + + + CONFIG + FIFO configuration register + 0x4 + 32 + read-write + 0x0 + 0x3FF + + + LEVEL + FIFO level set. A trigger (and optional interrupt) event occurs when STATUS.USED >= LEVEL+1. + +If CHAIN_EN is disabled, the Max LEVEL is limited to 63. + +If CHAIN_EN is enabled, only FIFO[0].config.level should be configured and the Max LEVEL is set by the number of FIFOs in the chain. + [7:0] + read-write + + + CHAN_ID_EN + channel number (ID) enable bit + +-0: CHAN_ID field in RD_DATA is disabled. A read from RD_DATA will result in (4'b0,16'b RESULT) + +-1: CHAN_ID field in RD_DATA is enabled. A read from RD_DATA will result in (4'b CHAN_ID, 16'b RESULT) + + +If CHAIN_EN is enabled, only FIFO[0].config.chan_id_en should be configured and the other FIFOs in the chain will inherit the FIFO[0] config. + [8:8] + read-write + + + CHAIN_EN + Enable chaining of FIFOs. +- 0: FIFO chain disabled. FIFO operates independently (FIFO depth of 64) and only operates on result data from its associated SAR. +- 1: FIFO chain enabled. FIFO is part of a chain of FIFOs (effectively extending the FIFO depth beyond 64) and only operates on result data from SAR0. + [9:9] + read-write + + + + + STATUS + FIFO status register + 0x8 + 32 + read-only + 0x0 + 0xFFFF00FF + + + USED + Number of used/occupied entries in the FIFO. + +If CONFIG.CHAIN_EN is disabled, the field value is in the range [0, 64]. When '0', the FIFO is empty. When '64', the FIFO is full. + +If CONFIG.CHAIN_EN is enabled, only FIFO[0].STATUS.USED should be read to detemine the used status. + [7:0] + read-only + + + RD_PTR + FIFO read pointer: FIFO location from which a data is read. + +Note: This functionality is intended for debugging purposes. + +If CONFIG.CHAIN_EN is enabled, only FIFO[0].STATUS.RD_PTR should be read to detemine the read pointer location of the chained FIFO. + [23:16] + read-only + + + WR_PTR + FIFO write pointer: FIFO location at which a new data is written by the hardware. + +Note: This functionality is intended for debugging purposes. + +If CONFIG.CHAIN_EN is enabled, only FIFO[0].STATUS.WR_PTR should be read to detemine the write pointer location of the chained FIFO. + [31:24] + read-only + + + + + RD_DATA + FIFO read data register + 0xC + 32 + read-only + 0x0 + 0xFFFFF + + + RESULT + SAR result. Results from all enabled channels are stored in the buffer. + +If CONFIG.CHAIN_EN is enabled, only FIFO[0].RD_DATA.RESULT should be read. + [15:0] + read-only + + + CHAN_ID + Channel number for a given SAR result. Requires CTRL.CHAN_ID_EN to be set. + +If CONFIG.CHAIN_EN is enabled, only FIFO[0].RD_DATA.CHAN_ID should be read. + [19:16] + read-only + + + + + INTR + Interrupt register + 0x10 + 32 + read-write + 0x0 + 0x7 + + + FIFO_LEVEL + HW sets this field to '1', when STATUS.USED >= CTRL.LEVEL+1 + +If CONFIG.CHAIN_EN is enabled, only FIFO[0].INTR.FIFO_LEVEL is updated by hardware. + [0:0] + read-write + + + FIFO_OVERFLOW + HW sets this field to '1', when writing to a full FIFO (FIFO_STATUS.USED is '64'). + +If CONFIG.CHAIN_EN is enabled, only FIFO[0].INTR.FIFO_OVERFLOW is updated by hardware. + [1:1] + read-write + + + FIFO_UNDERFLOW + HW sets this field to '1', when reading from an empty FIFO. HW tracks underflow after FIFO is being written to and FIFO_CTL.ENABLE==1. + +If CONFIG.CHAIN_EN is enabled, only FIFO[0].INTR.FIFO_UNDERFLOW is updated by hardware. + [2:2] + read-write + + + + + INTR_SET + Interrupt set register + 0x14 + 32 + read-write + 0x0 + 0x7 + + + FIFO_LEVEL + Write this field with '1' to set corresponding INTR field (a write of '0' has no effect). + [0:0] + read-write + + + FIFO_OVERFLOW + Write this field with '1' to set corresponding INTR field (a write of '0' has no effect). + [1:1] + read-write + + + FIFO_UNDERFLOW + Write this field with '1' to set corresponding INTR field (a write of '0' has no effect). + [2:2] + read-write + + + + + INTR_MASK + Interrupt mask register + 0x18 + 32 + read-write + 0x0 + 0x7 + + + FIFO_LEVEL + Mask for corresponding field in INTR register. + +If CONFIG.CHAIN_EN is enabled, only FIFO[0].INTR_MASK.FIFO_LEVEL should be set. + [0:0] + read-write + + + FIFO_OVERFLOW + Mask for corresponding field in INTR register. + +If CONFIG.CHAIN_EN is enabled, only FIFO[0].INTR_MASK.FIFO_OVERFLOW should be set. + [1:1] + read-write + + + FIFO_UNDERFLOW + Mask for corresponding field in INTR register. + +If CONFIG.CHAIN_EN is enabled, only FIFO[0].INTR_MASK.FIFO_UNDERFLOW should be set. + [2:2] + read-write + + + + + INTR_MASKED + Interrupt masked register + 0x1C + 32 + read-only + 0x0 + 0x7 + + + FIFO_LEVEL + Logical AND of corresponding INTR and INTR_MASK fields. + [0:0] + read-only + + + FIFO_OVERFLOW + Logical AND of corresponding INTR and INTR_MASK fields. + [1:1] + read-only + + + FIFO_UNDERFLOW + Logical AND of corresponding INTR and INTR_MASK fields. + [2:2] + read-only + + + + + + AREFV2 + AREF configuration + 0x00000E00 + + AREF_CTRL + global AREF control + 0x0 + 32 + read-write + 0x0 + 0xF0F9FFFD + + + AREF_MODE + Control bit to trade off AREF settling and noise performance + [0:0] + read-write + + + NORMAL + Nominal noise normal startup mode (meets normal mode settling and noise specifications) + 0 + + + FAST_START + High noise fast startup mode (meets fast mode settling and noise specifications) + 1 + + + + + AREF_BIAS_SCALE + BIAS Current Control for all AREF Amplifiers. (These are risk mitigation bits that should not be touched by the customer: the impact on IDDA/noise/startup still needs to be characterized) +0: 125nA (reduced bias: reduction in total AREF IDDA, higher noise and longer startup times) +1: 250nA ('default' setting to meet bandgap performance (noise/startup) and IDDA specifications) +2: 375nA (increased bias: increase in total AREF IDDA, lower noise and shorter startup times) +3: 500nA (further increased bias: increase in total AREF IDDA, lower noise and shorter startup times) + [3:2] + read-write + + + AREF_RMB + AREF control signals (RMB). + +Bit 0: Manual VBG startup circuit enable + 0: normal VBG startup circuit operation + 1: VBG startup circuit is forced 'always on' + +Bit 1: Manual disable of IPTAT2 DAC + 0: normal IPTAT2 DAC operation + 1: PTAT2 DAC is disabled while VBG startup is active + +Bit 2: Manual enable of VBG offset correction DAC + 0: normal VBG offset correction DAC operation + 1: VBG offset correction DAC is enabled while VBG startup is active + [6:4] + read-write + + + CTB_IPTAT_SCALE + CTB IPTAT current scaler. This bit must be set in order to operate the CTB amplifiers in the lowest power mode. This bit is chip-wide (controls all CTB amplifiers). +0: 1uA +1: 100nA + [7:7] + read-write + + + CTB_IPTAT_REDIRECT + Re-direct the CTB IPTAT output current. This can be used to reduce amplifier bias glitches during power mode transitions (for PSoC4A/B DSAB backwards compatibility). +0: Opamp<n>.IPTAT = AREF.IPTAT and Opamp<n>.IZTAT= AREF.IZTAT +1: Opamp<n>.IPTAT = HiZ and Opamp<n>.IZTAT= AREF.IPTAT + +*Note that in Deep Sleep, the AREF IZTAT and/or IPTAT currents can be disabled and therefore the corresponding Opamp<n>.IZTAT/IPTAT will be HiZ. + [15:8] + read-write + + + IZTAT_SEL + iztat current select control + [16:16] + read-write + + + SRSS + Use 250nA IZTAT from SRSS + 0 + + + LOCAL + Use locally generated 250nA + 1 + + + + + CLOCK_PUMP_PERI_SEL + CTBm charge pump clock source select. This field has nothing to do with the AREF. +0: Use the dedicated pump clock from SRSS (default) +1: Use one of the CLK_PERI dividers + [19:19] + read-write + + + VREF_SEL + bandgap voltage select control + [21:20] + read-write + + + SRSS + Use 0.8V Vref from SRSS + 0 + + + LOCAL + Use locally generated Vref + 1 + + + EXTERNAL + Use externally supplied Vref (aref_ext_vref) + 2 + + + + + LP_VREF_EN + Enable low power voltage reference +0: low power voltage reference is disabled +1: low power voltage reference is enabled + [22:22] + read-write + + + IZTAT_SCALE + IZTAT current scaler. This bit must be set in order to operate the SAR in the lowest power mode. This bit is chip-wide (controls all AREF IZTAT references). +0: 1uA +1: 100nA + [23:23] + read-write + + + DEEPSLEEP_MODE + AREF DeepSleep Operation Modes (only applies if DEEPSLEEP_ON = 1) + [29:28] + read-write + + + OFF + All blocks 'OFF' in DeepSleep + 0 + + + IPTAT + IPTAT bias generator 'ON' in DeepSleep (used for fast AREF wakeup only: IPTAT outputs not available) + 1 + + + IPTAT_IZTAT + IPTAT bias generator and outputs 'ON' in DeepSleep (used for biasing the CTBm with a PTAT current only in deep sleep) + +*Note that this mode also requires that the CTB_IPTAT_REDIRECT be set if the CTBm opamp is to operate in DeepSleep + 2 + + + IPTAT_IZTAT_VREF + IPTAT, VREF, and IZTAT generators 'ON' in DeepSleep. This mode provides identical AREF functionality in DeepSleep as in the Active mode. + 3 + + + + + DEEPSLEEP_ON + - 0: AREF IP disabled/off during DeepSleep power mode +- 1: AREF IP remains enabled during DeepSleep power mode (if ENABLED=1) + [30:30] + read-write + + + ENABLED + Disable AREF + [31:31] + read-write + + + + + + VREF_TRIM0 + VREF Trim bits + 0xF00 + 32 + read-write + 0x0 + 0xFF + + + VREF_ABS_TRIM + N/A + [7:0] + read-write + + + + + VREF_TRIM1 + VREF Trim bits + 0xF04 + 32 + read-write + 0x0 + 0xFF + + + VREF_TEMPCO_TRIM + N/A + [7:0] + read-write + + + + + VREF_TRIM2 + VREF Trim bits + 0xF08 + 32 + read-write + 0x0 + 0xFF + + + VREF_CURV_TRIM + N/A + [7:0] + read-write + + + + + VREF_TRIM3 + VREF Trim bits + 0xF0C + 32 + read-write + 0x0 + 0xF + + + VREF_ATTEN_TRIM + Obsolete + [3:0] + read-write + + + + + IZTAT_TRIM0 + VREF Trim bits + 0xF10 + 32 + read-write + 0x0 + 0xFF + + + IZTAT_ABS_TRIM + N/A + [7:0] + read-write + + + + + IZTAT_TRIM1 + IZTAT Trim bits + 0xF14 + 32 + read-write + 0x0 + 0xFF + + + IZTAT_TC_TRIM + IZTAT temperature correction trim (RMB) +0x00 : No IZTAT temperature correction +0xFF : Maximum IZTAT temperature correction + +As this is a Risk Mitigation Register, it should be loaded with 0x08. + [7:0] + read-write + + + + + IPTAT_TRIM0 + IPTAT Trim bits + 0xF18 + 32 + read-write + 0x0 + 0xFF + + + IPTAT_CORE_TRIM + IPTAT trim +0x0 : Minimum IPTAT current (~150nA at room) +0xF : Maximum IPTAT current (~350nA at room) + [3:0] + read-write + + + IPTAT_CTBM_TRIM + CTMB PTAT Current Trim +0x0 : Minimum CTMB IPTAT Current (~875nA) +0xF : Maximum CTMB IPTAT Current (~1.1uA) + [7:4] + read-write + + + + + ICTAT_TRIM0 + ICTAT Trim bits + 0xF1C + 32 + read-write + 0x0 + 0xF + + + ICTAT_TRIM + ICTAT trim +0x00 : Minimum ICTAT current (~150nA at room) +0x0F : Maximum ICTAT current (~350nA at room) + [3:0] + read-write + + + + + + + \ No newline at end of file diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx4_cm0plus.sct b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx4_cm0plus.sct new file mode 100644 index 0000000..fc4df8c --- /dev/null +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx4_cm0plus.sct @@ -0,0 +1,311 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xx4_cm0plus.sct +;* \version 2.70.1 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2020 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +;* MBED_APP_START is being used by the bootloader build script and +;* will be calculate by the system. Without bootloader the MBED_APP_START +;* is equal to MBED_ROM_START +;* +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x80000 +#endif + +;* MBED_APP_SIZE is being used by the bootloader build script and +;* will be calculate by the system. Without bootloader the MBED_APP_SIZE +;* is equal to MBED_ROM_SIZE +;* +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08000000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x00010000 +#endif + +#if !defined(MBED_PUBLIC_RAM_SIZE) + #define MBED_PUBLIC_RAM_SIZE 0x200 +#endif + +; The size of the stack section at the end of CM0+ SRAM +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +#define STACK_SIZE MBED_BOOT_STACK_SIZE + +#if !defined(MBED_PUBLIC_RAM_START) + #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE) +#endif + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM0+ core. +; You can change the memory allocation by editing the RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'. +; RAM +#define RAM_START MBED_RAM_START +#define RAM_SIZE MBED_RAM_SIZE +; Public RAM +#define PUBLIC_RAM_START MBED_PUBLIC_RAM_START +#define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE +; Flash +#define FLASH_START MBED_APP_START +#define FLASH_SIZE MBED_APP_SIZE + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M0+ application flash area +LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000) +{ + .cy_app_header +0 + { + * (.cy_app_header) + } + + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + RW_IRAM2 PUBLIC_RAM_START UNINIT + { + * (.cy_sharedmem) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2) + { + } + + ; Stack region growing down + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE + { + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + .cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00040000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct index d9f2493..70210e6 100644 --- a/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xx5_cm0plus.sct -;* \version 2.70 +;* \version 2.70.1 ;* ;* Linker file for the ARMCC. ;* @@ -26,7 +26,7 @@ ;* ;******************************************************************************* ;* \copyright -;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* Copyright 2016-2020 Cypress Semiconductor Corporation ;* SPDX-License-Identifier: Apache-2.0 ;* ;* Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx6_cm0plus.sct b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx6_cm0plus.sct index eb63380..245518f 100644 --- a/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx6_cm0plus.sct +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx6_cm0plus.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xx6_cm0plus.sct -;* \version 2.70 +;* \version 2.70.1 ;* ;* Linker file for the ARMCC. ;* @@ -26,7 +26,7 @@ ;* ;******************************************************************************* ;* \copyright -;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* Copyright 2016-2020 Cypress Semiconductor Corporation ;* SPDX-License-Identifier: Apache-2.0 ;* ;* Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct index 4ff5ccb..7a99d7b 100644 --- a/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xx7_cm0plus.sct -;* \version 2.70 +;* \version 2.70.1 ;* ;* Linker file for the ARMCC. ;* @@ -26,7 +26,7 @@ ;* ;******************************************************************************* ;* \copyright -;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* Copyright 2016-2020 Cypress Semiconductor Corporation ;* SPDX-License-Identifier: Apache-2.0 ;* ;* Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx8_cm0plus.sct b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx8_cm0plus.sct index cf27334..57f0255 100644 --- a/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx8_cm0plus.sct +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx8_cm0plus.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xx8_cm0plus.sct -;* \version 2.70 +;* \version 2.70.1 ;* ;* Linker file for the ARMCC. ;* @@ -26,7 +26,7 @@ ;* ;******************************************************************************* ;* \copyright -;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* Copyright 2016-2020 Cypress Semiconductor Corporation ;* SPDX-License-Identifier: Apache-2.0 ;* ;* Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct index f5a9981..11f1574 100644 --- a/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xxa_cm0plus.sct -;* \version 2.70 +;* \version 2.70.1 ;* ;* Linker file for the ARMCC. ;* @@ -26,7 +26,7 @@ ;* ;******************************************************************************* ;* \copyright -;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* Copyright 2016-2020 Cypress Semiconductor Corporation ;* SPDX-License-Identifier: Apache-2.0 ;* ;* Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx5_cm0plus.sct b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx5_cm0plus.sct index 317c801..e6157d8 100644 --- a/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx5_cm0plus.sct +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx5_cm0plus.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cyb06xx5_cm0plus.sct -;* \version 2.70 +;* \version 2.70.1 ;* ;* Linker file for the ARMCC. ;* @@ -26,7 +26,7 @@ ;* ;******************************************************************************* ;* \copyright -;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* Copyright 2016-2020 Cypress Semiconductor Corporation ;* SPDX-License-Identifier: Apache-2.0 ;* ;* Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx7_cm0plus.sct b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx7_cm0plus.sct index 1a7e1db..1b90b6b 100644 --- a/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx7_cm0plus.sct +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx7_cm0plus.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cyb06xx7_cm0plus.sct -;* \version 2.70 +;* \version 2.70.1 ;* ;* Linker file for the ARMCC. ;* @@ -26,7 +26,7 @@ ;* ;******************************************************************************* ;* \copyright -;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* Copyright 2016-2020 Cypress Semiconductor Corporation ;* SPDX-License-Identifier: Apache-2.0 ;* ;* Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct index b16001c..7fbcad2 100644 --- a/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cyb06xxa_cm0plus.sct -;* \version 2.70 +;* \version 2.70.1 ;* ;* Linker file for the ARMCC. ;* @@ -26,7 +26,7 @@ ;* ;******************************************************************************* ;* \copyright -;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* Copyright 2016-2020 Cypress Semiconductor Corporation ;* SPDX-License-Identifier: Apache-2.0 ;* ;* Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_04_cm0plus.S b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_04_cm0plus.S new file mode 100644 index 0000000..9aaf9db --- /dev/null +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_04_cm0plus.S @@ -0,0 +1,213 @@ +;/**************************************************************************//** +; * @file startup_psoc6_04_cm0plus.S +; * @brief CMSIS Core Device Startup File for +; * ARMCM0plus Device Series +; * @version V5.00 +; * @date 02. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| + +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack + DCD Reset_Handler ; Reset Handler + + DCD 0x0000000D ; NMI Handler located at ROM code + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External interrupts Description + DCD NvicMux0_IRQHandler ; CPU User Interrupt #0 + DCD NvicMux1_IRQHandler ; CPU User Interrupt #1 + DCD NvicMux2_IRQHandler ; CPU User Interrupt #2 + DCD NvicMux3_IRQHandler ; CPU User Interrupt #3 + DCD NvicMux4_IRQHandler ; CPU User Interrupt #4 + DCD NvicMux5_IRQHandler ; CPU User Interrupt #5 + DCD NvicMux6_IRQHandler ; CPU User Interrupt #6 + DCD NvicMux7_IRQHandler ; CPU User Interrupt #7 + DCD Internal0_IRQHandler ; Internal SW Interrupt #0 + DCD Internal1_IRQHandler ; Internal SW Interrupt #1 + DCD Internal2_IRQHandler ; Internal SW Interrupt #2 + DCD Internal3_IRQHandler ; Internal SW Interrupt #3 + DCD Internal4_IRQHandler ; Internal SW Interrupt #4 + DCD Internal5_IRQHandler ; Internal SW Interrupt #5 + DCD Internal6_IRQHandler ; Internal SW Interrupt #6 + DCD Internal7_IRQHandler ; Internal SW Interrupt #7 + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + EXPORT __ramVectors + AREA RESET_RAM, READWRITE, NOINIT +__ramVectors SPACE __Vectors_Size + + + AREA |.text|, CODE, READONLY + + +; Weak function for startup customization +; +; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +; because this function is executed as the first instruction in the ResetHandler. +; The PDL is also not initialized to use the proper register offsets. +; The user of this function is responsible for initializing the PDL and resources before using them. +; +Cy_OnResetUser PROC + EXPORT Cy_OnResetUser [WEAK] + BX LR + ENDP + +; Reset Handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + + ; Define strong function for startup customization + BL Cy_OnResetUser + + ; Copy vectors from ROM to RAM + LDR r1, =__Vectors + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +Vectors_Copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE Vectors_Copy + + ; Update Vector Table Offset Register. */ + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb 0xF + + LDR R0, =__main + BLX R0 + + ; Should never get here + B . + + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +Cy_SysLib_FaultHandler PROC + EXPORT Cy_SysLib_FaultHandler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + bl L_API_call +L_MSP + mrs r0, MSP +L_API_call + bl Cy_SysLib_FaultHandler + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT Default_Handler [WEAK] + EXPORT NvicMux0_IRQHandler [WEAK] + EXPORT NvicMux1_IRQHandler [WEAK] + EXPORT NvicMux2_IRQHandler [WEAK] + EXPORT NvicMux3_IRQHandler [WEAK] + EXPORT NvicMux4_IRQHandler [WEAK] + EXPORT NvicMux5_IRQHandler [WEAK] + EXPORT NvicMux6_IRQHandler [WEAK] + EXPORT NvicMux7_IRQHandler [WEAK] + EXPORT Internal0_IRQHandler [WEAK] + EXPORT Internal1_IRQHandler [WEAK] + EXPORT Internal2_IRQHandler [WEAK] + EXPORT Internal3_IRQHandler [WEAK] + EXPORT Internal4_IRQHandler [WEAK] + EXPORT Internal5_IRQHandler [WEAK] + EXPORT Internal6_IRQHandler [WEAK] + EXPORT Internal7_IRQHandler [WEAK] + +NvicMux0_IRQHandler +NvicMux1_IRQHandler +NvicMux2_IRQHandler +NvicMux3_IRQHandler +NvicMux4_IRQHandler +NvicMux5_IRQHandler +NvicMux6_IRQHandler +NvicMux7_IRQHandler +Internal0_IRQHandler +Internal1_IRQHandler +Internal2_IRQHandler +Internal3_IRQHandler +Internal4_IRQHandler +Internal5_IRQHandler +Internal6_IRQHandler +Internal7_IRQHandler + + B . + ENDP + + ALIGN + + END + + +; [] END OF FILE diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx4_cm0plus.ld b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx4_cm0plus.ld new file mode 100644 index 0000000..45488cc --- /dev/null +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx4_cm0plus.ld @@ -0,0 +1,470 @@ +/***************************************************************************//** +* \file cy8c6xx4_cm0plus.ld +* \version 2.70.1 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +/* MBED_APP_START is being used by the bootloader build script and +* will be calculate by the system. Without bootloader the MBED_APP_START +* is equal to MBED_ROM_START +*/ +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x80000 +#endif + +/* MBED_APP_SIZE is being used by the bootloader build script and +* will be calculate by the system. Without bootloader the MBED_APP_SIZE +* is equal to MBED_ROM_SIZE +*/ +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08000000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x00010000 +#endif + +#if !defined(MBED_PUBLIC_RAM_SIZE) + #define MBED_PUBLIC_RAM_SIZE 0x200 +#endif + +/* The size of the stack section at the end of CM0+ SRAM */ +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +STACK_SIZE = MBED_BOOT_STACK_SIZE; + +#if !defined(MBED_PUBLIC_RAM_START) + #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE) +#endif + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM0+ core. + * You can change the memory allocation by editing the 'ram' and 'flash' regions. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding memory regions for the CM4 core in 'xx_cm4_dual.ld', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.ld'. + */ + ram (rwx) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE + public_ram (rw) : ORIGIN = MBED_PUBLIC_RAM_START, LENGTH = MBED_PUBLIC_RAM_SIZE + flash (rx) : ORIGIN = MBED_APP_START, LENGTH = (MBED_APP_SIZE - 0x8000) + + /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ + em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */ + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + .cy_app_header : + { + KEEP(*(.cy_app_header)) + } > flash + + /* Cortex-M0+ application flash area */ + .text : + { + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_04_cm0plus.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_04_cm0plus.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > ram + + + /* Public RAM */ + .cy_sharedmem (NOLOAD): + { + . = ALIGN(4); + KEEP(*(.cy_sharedmem)) + } > public_ram + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + .cy_xip : + { + KEEP(*(.cy_xip)) + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x00040000; +__cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +__cy_memory_1_start = 0x14000000; +__cy_memory_1_length = 0x8000; +__cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm0plus.ld b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm0plus.ld index 5611270..c4b744a 100644 --- a/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm0plus.ld +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm0plus.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx5_cm0plus.ld -* \version 2.70 +* \version 2.70.1 * * Linker file for the GNU C compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx6_cm0plus.ld b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx6_cm0plus.ld index f2586c3..2c86aed 100644 --- a/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx6_cm0plus.ld +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx6_cm0plus.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx6_cm0plus.ld -* \version 2.70 +* \version 2.70.1 * * Linker file for the GNU C compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld index a9d2857..b78effb 100644 --- a/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx7_cm0plus.ld -* \version 2.70 +* \version 2.70.1 * * Linker file for the GNU C compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx8_cm0plus.ld b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx8_cm0plus.ld index d1d65d4..f8f7d86 100644 --- a/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx8_cm0plus.ld +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx8_cm0plus.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx8_cm0plus.ld -* \version 2.70 +* \version 2.70.1 * * Linker file for the GNU C compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld index e6ab901..4556c88 100644 --- a/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xxa_cm0plus.ld -* \version 2.70 +* \version 2.70.1 * * Linker file for the GNU C compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xx5_cm0plus.ld b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xx5_cm0plus.ld index d3da953..e0ea1d7 100644 --- a/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xx5_cm0plus.ld +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xx5_cm0plus.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cyb06xx5_cm0plus.ld -* \version 2.70 +* \version 2.70.1 * * Linker file for the GNU C compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xx7_cm0plus.ld b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xx7_cm0plus.ld index c37386f..5629824 100644 --- a/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xx7_cm0plus.ld +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xx7_cm0plus.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cyb06xx7_cm0plus.ld -* \version 2.70 +* \version 2.70.1 * * Linker file for the GNU C compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xxa_cm0plus.ld b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xxa_cm0plus.ld index 15f6a88..a987e9b 100644 --- a/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xxa_cm0plus.ld +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xxa_cm0plus.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cyb06xxa_cm0plus.ld -* \version 2.70 +* \version 2.70.1 * * Linker file for the GNU C compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_04_cm0plus.S b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_04_cm0plus.S new file mode 100644 index 0000000..fb65f35 --- /dev/null +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_04_cm0plus.S @@ -0,0 +1,367 @@ +/**************************************************************************//** + * @file startup_psoc6_04_cm0plus.S + * @brief CMSIS Core Device Startup File for + * ARMCM0plus Device Series + * @version V5.00 + * @date 02. March 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + /* Address of the NMI handler */ + #define CY_NMI_HANLDER_ADDR 0x0000000D + + /* The CPU VTOR register */ + #define CY_CPU_VTOR_ADDR 0xE000ED08 + + /* Copy flash vectors and data section to RAM */ + #define __STARTUP_COPY_MULTIPLE + + /* Clear single BSS section */ + #define __STARTUP_CLEAR_BSS + + .syntax unified + .arch armv6-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x00001000 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x00000400 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .vectors + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long CY_NMI_HANLDER_ADDR /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts Description */ + .long NvicMux0_IRQHandler /* CPU User Interrupt #0 */ + .long NvicMux1_IRQHandler /* CPU User Interrupt #1 */ + .long NvicMux2_IRQHandler /* CPU User Interrupt #2 */ + .long NvicMux3_IRQHandler /* CPU User Interrupt #3 */ + .long NvicMux4_IRQHandler /* CPU User Interrupt #4 */ + .long NvicMux5_IRQHandler /* CPU User Interrupt #5 */ + .long NvicMux6_IRQHandler /* CPU User Interrupt #6 */ + .long NvicMux7_IRQHandler /* CPU User Interrupt #7 */ + .long Internal0_IRQHandler /* Internal SW Interrupt #0 */ + .long Internal1_IRQHandler /* Internal SW Interrupt #1 */ + .long Internal2_IRQHandler /* Internal SW Interrupt #2 */ + .long Internal3_IRQHandler /* Internal SW Interrupt #3 */ + .long Internal4_IRQHandler /* Internal SW Interrupt #4 */ + .long Internal5_IRQHandler /* Internal SW Interrupt #5 */ + .long Internal6_IRQHandler /* Internal SW Interrupt #6 */ + .long Internal7_IRQHandler /* Internal SW Interrupt #7 */ + + .size __Vectors, . - __Vectors + .equ __VectorsSize, . - __Vectors + + .section .ram_vectors + .align 2 + .globl __ramVectors +__ramVectors: + .space __VectorsSize + .size __ramVectors, . - __ramVectors + + + .text + .thumb + .thumb_func + .align 2 + + /* + * Device startup customization + * + * Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) + * because this function is executed as the first instruction in the ResetHandler. + * The PDL is also not initialized to use the proper register offsets. + * The user of this function is responsible for initializing the PDL and resources before using them. + */ + .weak Cy_OnResetUser + .func Cy_OnResetUser, Cy_OnResetUser + .type Cy_OnResetUser, %function + +Cy_OnResetUser: + bx lr + .size Cy_OnResetUser, . - Cy_OnResetUser + .endfunc + + /* Reset handler */ + .weak Reset_Handler + .type Reset_Handler, %function + +Reset_Handler: + bl Cy_OnResetUser + +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + blt .L_loop0_0_done + ldr r0, [r1, r3] + str r0, [r2, r3] + b .L_loop0_0 + +.L_loop0_0_done: + adds r4, #12 + b .L_loop0 + +.L_loop0_done: +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + + subs r3, r2 + ble .L_loop1_done + +.L_loop1: + subs r3, #4 + ldr r0, [r1,r3] + str r0, [r2,r3] + bgt .L_loop1 + +.L_loop1_done: +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + blt .L_loop2_0_done + str r0, [r1, r2] + b .L_loop2_0 +.L_loop2_0_done: + + adds r3, #8 + b .L_loop2 +.L_loop2_done: +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 + + subs r2, r1 + ble .L_loop3_done + +.L_loop3: + subs r2, #4 + str r0, [r1, r2] + bgt .L_loop3 +.L_loop3_done: +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + + /* Update Vector Table Offset Register. */ + ldr r0, =__ramVectors + ldr r1, =CY_CPU_VTOR_ADDR + str r0, [r1] + dsb 0xF + + bl _start + + /* Should never get here */ + b . + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak Default_Handler + .type Default_Handler, %function +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + .weak Cy_SysLib_FaultHandler + .type Cy_SysLib_FaultHandler, %function + +Cy_SysLib_FaultHandler: + b . + .size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler + .type Fault_Handler, %function + +Fault_Handler: + /* Storing LR content for Creator call stack trace */ + push {LR} + movs r0, #4 + mov r1, LR + tst r0, r1 + beq .L_MSP + mrs r0, PSP + b .L_API_call +.L_MSP: + mrs r0, MSP +.L_API_call: + /* Compensation of stack pointer address due to pushing 4 bytes of LR */ + adds r0, r0, #4 + bl Cy_SysLib_FaultHandler + b . + .size Fault_Handler, . - Fault_Handler + +.macro def_fault_Handler fault_handler_name + .weak \fault_handler_name + .set \fault_handler_name, Fault_Handler + .endm + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + + def_fault_Handler HardFault_Handler + + def_irq_handler SVC_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler NvicMux0_IRQHandler /* CPU User Interrupt #0 */ + def_irq_handler NvicMux1_IRQHandler /* CPU User Interrupt #1 */ + def_irq_handler NvicMux2_IRQHandler /* CPU User Interrupt #2 */ + def_irq_handler NvicMux3_IRQHandler /* CPU User Interrupt #3 */ + def_irq_handler NvicMux4_IRQHandler /* CPU User Interrupt #4 */ + def_irq_handler NvicMux5_IRQHandler /* CPU User Interrupt #5 */ + def_irq_handler NvicMux6_IRQHandler /* CPU User Interrupt #6 */ + def_irq_handler NvicMux7_IRQHandler /* CPU User Interrupt #7 */ + def_irq_handler Internal0_IRQHandler /* Internal SW Interrupt #0 */ + def_irq_handler Internal1_IRQHandler /* Internal SW Interrupt #1 */ + def_irq_handler Internal2_IRQHandler /* Internal SW Interrupt #2 */ + def_irq_handler Internal3_IRQHandler /* Internal SW Interrupt #3 */ + def_irq_handler Internal4_IRQHandler /* Internal SW Interrupt #4 */ + def_irq_handler Internal5_IRQHandler /* Internal SW Interrupt #5 */ + def_irq_handler Internal6_IRQHandler /* Internal SW Interrupt #6 */ + def_irq_handler Internal7_IRQHandler /* Internal SW Interrupt #7 */ + + .end + + +/* [] END OF FILE */ diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx4_cm0plus.icf b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx4_cm0plus.icf new file mode 100644 index 0000000..a0c60e6 --- /dev/null +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx4_cm0plus.icf @@ -0,0 +1,287 @@ +/******************************************************************************* +* \file cy8c6xx4_cm0plus.icf +* \version 2.70.1 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +if (!isdefinedsymbol(MBED_ROM_START)) { + define symbol MBED_ROM_START = 0x10000000; +} + +/* MBED_APP_START is being used by the bootloader build script and + * will be calculate by the system. Without bootloader the MBED_APP_START + * is equal to MBED_ROM_START + */ +if (!isdefinedsymbol(MBED_APP_START)) { + define symbol MBED_APP_START = MBED_ROM_START; +} + +if (!isdefinedsymbol(MBED_ROM_SIZE)) { + define symbol MBED_ROM_SIZE = 0x80000; +} + +/* MBED_APP_SIZE is being used by the bootloader build script and + * will be calculate by the system. Without bootloader the MBED_APP_SIZE + * is equal to MBED_ROM_SIZE + */ +if (!isdefinedsymbol(MBED_APP_SIZE)) { + define symbol MBED_APP_SIZE = MBED_ROM_SIZE; +} + +if (!isdefinedsymbol(MBED_RAM_START)) { + define symbol MBED_RAM_START = 0x08000000; +} + +if (!isdefinedsymbol(MBED_RAM_SIZE)) { + define symbol MBED_RAM_SIZE = 0x00010000; +} + +/*-Sizes-*/ +if (!isdefinedsymbol(MBED_PUBLIC_RAM_SIZE)) { + define symbol MBED_PUBLIC_RAM_SIZE = 0x200; +} +if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { + + if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol MBED_BOOT_STACK_SIZE = 0x0400; + } else { + define symbol MBED_BOOT_STACK_SIZE = __STACK_SIZE; + } +} + +define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; + +define symbol __ICFEDIT_size_proc_stack__ = 0x0; + +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} + +if (!isdefinedsymbol(MBED_PUBLIC_RAM_START)) { + define symbol MBED_PUBLIC_RAM_START = (MBED_RAM_START + MBED_RAM_SIZE - __ICFEDIT_size_cstack__ - MBED_PUBLIC_RAM_SIZE); +} + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM0+ core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding symbols for CM4 core in 'xx_cm4_dual.icf', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; +define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1); +/* Public RAM */ +define symbol __ICFEDIT_region_IRAM2_start__ = MBED_PUBLIC_RAM_START; +define symbol __ICFEDIT_region_IRAM2_end__ = (MBED_PUBLIC_RAM_START + MBED_PUBLIC_RAM_SIZE - 1); +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; +define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 0x8000 - 1); + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x160007FF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; +define region IRAM2_region = mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; + +define block RAM_DATA {readwrite section .data}; +define block RAM_OTHER {readwrite section * }; +define block RAM_NOINIT {readwrite section .noinit}; +define block RAM_BSS {readwrite section .bss}; +define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NOINIT, block RAM_BSS}; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; +define block RO {first section .intvec, readonly}; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M0+ application */ +".cy_app_header" : place at start of IROM1_region { section .cy_app_header }; +place in IROM1_region { block RO }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +".cy_xip" : place at start of EROM1_region { section .cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { block RAM}; +place in IRAM1_region { readwrite section .cy_ramfunc }; +place at end of IRAM1_region { block HSTACK }; + +/* Public RAM */ +place at start of IRAM2_region { section .cy_sharedmem }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_app_header, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00040000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx5_cm0plus.icf b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx5_cm0plus.icf index 68b322d..d943f2e 100644 --- a/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx5_cm0plus.icf +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx5_cm0plus.icf @@ -1,6 +1,6 @@ -/***************************************************************************//** +/******************************************************************************* * \file cy8c6xx5_cm0plus.icf -* \version 2.70 +* \version 2.70.1 * * Linker file for the IAR compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -114,13 +114,13 @@ if (!isdefinedsymbol(MBED_PUBLIC_RAM_START)) { */ /* RAM */ define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; -define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE); +define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1); /* Public RAM */ define symbol __ICFEDIT_region_IRAM2_start__ = MBED_PUBLIC_RAM_START; -define symbol __ICFEDIT_region_IRAM2_end__ = (MBED_PUBLIC_RAM_START + MBED_PUBLIC_RAM_SIZE); +define symbol __ICFEDIT_region_IRAM2_end__ = (MBED_PUBLIC_RAM_START + MBED_PUBLIC_RAM_SIZE - 1); /* Flash */ define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; -define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 0x8000); +define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 0x8000 - 1); /* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx6_cm0plus.icf b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx6_cm0plus.icf index 069cdcd..b9c5688 100644 --- a/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx6_cm0plus.icf +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx6_cm0plus.icf @@ -1,6 +1,6 @@ -/***************************************************************************//** +/******************************************************************************* * \file cy8c6xx6_cm0plus.icf -* \version 2.70 +* \version 2.70.1 * * Linker file for the IAR compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -114,13 +114,13 @@ if (!isdefinedsymbol(MBED_PUBLIC_RAM_START)) { */ /* RAM */ define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; -define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE); +define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1); /* Public RAM */ define symbol __ICFEDIT_region_IRAM2_start__ = MBED_PUBLIC_RAM_START; -define symbol __ICFEDIT_region_IRAM2_end__ = (MBED_PUBLIC_RAM_START + MBED_PUBLIC_RAM_SIZE); +define symbol __ICFEDIT_region_IRAM2_end__ = (MBED_PUBLIC_RAM_START + MBED_PUBLIC_RAM_SIZE - 1); /* Flash */ define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; -define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 0x8000); +define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 0x8000 - 1); /* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf index 3a0414e..61d4a4b 100644 --- a/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf @@ -1,6 +1,6 @@ -/***************************************************************************//** +/******************************************************************************* * \file cy8c6xx7_cm0plus.icf -* \version 2.70 +* \version 2.70.1 * * Linker file for the IAR compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -114,13 +114,13 @@ if (!isdefinedsymbol(MBED_PUBLIC_RAM_START)) { */ /* RAM */ define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; -define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE); +define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1); /* Public RAM */ define symbol __ICFEDIT_region_IRAM2_start__ = MBED_PUBLIC_RAM_START; -define symbol __ICFEDIT_region_IRAM2_end__ = (MBED_PUBLIC_RAM_START + MBED_PUBLIC_RAM_SIZE); +define symbol __ICFEDIT_region_IRAM2_end__ = (MBED_PUBLIC_RAM_START + MBED_PUBLIC_RAM_SIZE - 1); /* Flash */ define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; -define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 0x8000); +define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 0x8000 - 1); /* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx8_cm0plus.icf b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx8_cm0plus.icf index 5534a17..435d6d3 100644 --- a/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx8_cm0plus.icf +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx8_cm0plus.icf @@ -1,6 +1,6 @@ -/***************************************************************************//** +/******************************************************************************* * \file cy8c6xx8_cm0plus.icf -* \version 2.70 +* \version 2.70.1 * * Linker file for the IAR compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -114,13 +114,13 @@ if (!isdefinedsymbol(MBED_PUBLIC_RAM_START)) { */ /* RAM */ define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; -define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE); +define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1); /* Public RAM */ define symbol __ICFEDIT_region_IRAM2_start__ = MBED_PUBLIC_RAM_START; -define symbol __ICFEDIT_region_IRAM2_end__ = (MBED_PUBLIC_RAM_START + MBED_PUBLIC_RAM_SIZE); +define symbol __ICFEDIT_region_IRAM2_end__ = (MBED_PUBLIC_RAM_START + MBED_PUBLIC_RAM_SIZE - 1); /* Flash */ define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; -define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 0x8000); +define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 0x8000 - 1); /* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf index fea3f6e..f99cad4 100644 --- a/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf @@ -1,6 +1,6 @@ -/***************************************************************************//** +/******************************************************************************* * \file cy8c6xxa_cm0plus.icf -* \version 2.70 +* \version 2.70.1 * * Linker file for the IAR compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -114,13 +114,13 @@ if (!isdefinedsymbol(MBED_PUBLIC_RAM_START)) { */ /* RAM */ define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; -define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE); +define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1); /* Public RAM */ define symbol __ICFEDIT_region_IRAM2_start__ = MBED_PUBLIC_RAM_START; -define symbol __ICFEDIT_region_IRAM2_end__ = (MBED_PUBLIC_RAM_START + MBED_PUBLIC_RAM_SIZE); +define symbol __ICFEDIT_region_IRAM2_end__ = (MBED_PUBLIC_RAM_START + MBED_PUBLIC_RAM_SIZE - 1); /* Flash */ define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; -define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 0x8000); +define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 0x8000 - 1); /* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xx5_cm0plus.icf b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xx5_cm0plus.icf index 32e9a78..df273c7 100644 --- a/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xx5_cm0plus.icf +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xx5_cm0plus.icf @@ -1,6 +1,6 @@ -/***************************************************************************//** +/******************************************************************************* * \file cyb06xx5_cm0plus.icf -* \version 2.70 +* \version 2.70.1 * * Linker file for the IAR compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -112,13 +112,13 @@ if (!isdefinedsymbol(MBED_PUBLIC_RAM_START)) { */ /* RAM */ define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; -define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE); +define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1); /* Public RAM */ define symbol __ICFEDIT_region_IRAM2_start__ = MBED_PUBLIC_RAM_START; -define symbol __ICFEDIT_region_IRAM2_end__ = (MBED_PUBLIC_RAM_START + MBED_PUBLIC_RAM_SIZE); +define symbol __ICFEDIT_region_IRAM2_end__ = (MBED_PUBLIC_RAM_START + MBED_PUBLIC_RAM_SIZE - 1); /* Flash */ define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; -define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 0x8000); +define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 0x8000 - 1); /* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xx7_cm0plus.icf b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xx7_cm0plus.icf index f48b2e9..97d3a8c 100644 --- a/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xx7_cm0plus.icf +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xx7_cm0plus.icf @@ -1,6 +1,6 @@ -/***************************************************************************//** +/******************************************************************************* * \file cyb06xx7_cm0plus.icf -* \version 2.70 +* \version 2.70.1 * * Linker file for the IAR compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -112,13 +112,13 @@ if (!isdefinedsymbol(MBED_PUBLIC_RAM_START)) { */ /* RAM */ define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; -define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE); +define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1); /* Public RAM */ define symbol __ICFEDIT_region_IRAM2_start__ = MBED_PUBLIC_RAM_START; -define symbol __ICFEDIT_region_IRAM2_end__ = (MBED_PUBLIC_RAM_START + MBED_PUBLIC_RAM_SIZE); +define symbol __ICFEDIT_region_IRAM2_end__ = (MBED_PUBLIC_RAM_START + MBED_PUBLIC_RAM_SIZE - 1); /* Flash */ define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; -define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 0x8000); +define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 0x8000 - 1); /* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xxa_cm0plus.icf b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xxa_cm0plus.icf index 05bbaa0..fe9af7a 100644 --- a/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xxa_cm0plus.icf +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xxa_cm0plus.icf @@ -1,6 +1,6 @@ -/***************************************************************************//** +/******************************************************************************* * \file cyb06xxa_cm0plus.icf -* \version 2.70 +* \version 2.70.1 * * Linker file for the IAR compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -112,13 +112,13 @@ if (!isdefinedsymbol(MBED_PUBLIC_RAM_START)) { */ /* RAM */ define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; -define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE); +define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1); /* Public RAM */ define symbol __ICFEDIT_region_IRAM2_start__ = MBED_PUBLIC_RAM_START; -define symbol __ICFEDIT_region_IRAM2_end__ = (MBED_PUBLIC_RAM_START + MBED_PUBLIC_RAM_SIZE); +define symbol __ICFEDIT_region_IRAM2_end__ = (MBED_PUBLIC_RAM_START + MBED_PUBLIC_RAM_SIZE - 1); /* Flash */ define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; -define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 0x8000); +define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 0x8000 - 1); /* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_04_cm0plus.S b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_04_cm0plus.S new file mode 100644 index 0000000..e2adca7 --- /dev/null +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_04_cm0plus.S @@ -0,0 +1,317 @@ +;/**************************************************************************//** +; * @file startup_psoc6_04_cm0plus.S +; * @brief CMSIS Core Device Startup File for +; * ARMCM0plus Device Series +; * @version V5.00 +; * @date 08. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + SECTION .intvec_ram:DATA:NOROOT(2) + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + EXTERN __iar_data_init3 + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + PUBLIC __ramVectors + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD 0x0000000D ; NMI_Handler is defined in ROM code + DCD HardFault_Handler + DCD 0 + DCD 0 + DCD 0 +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD 0 + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External interrupts Description + DCD NvicMux0_IRQHandler ; CPU User Interrupt #0 + DCD NvicMux1_IRQHandler ; CPU User Interrupt #1 + DCD NvicMux2_IRQHandler ; CPU User Interrupt #2 + DCD NvicMux3_IRQHandler ; CPU User Interrupt #3 + DCD NvicMux4_IRQHandler ; CPU User Interrupt #4 + DCD NvicMux5_IRQHandler ; CPU User Interrupt #5 + DCD NvicMux6_IRQHandler ; CPU User Interrupt #6 + DCD NvicMux7_IRQHandler ; CPU User Interrupt #7 + DCD Internal0_IRQHandler ; Internal SW Interrupt #0 + DCD Internal1_IRQHandler ; Internal SW Interrupt #1 + DCD Internal2_IRQHandler ; Internal SW Interrupt #2 + DCD Internal3_IRQHandler ; Internal SW Interrupt #3 + DCD Internal4_IRQHandler ; Internal SW Interrupt #4 + DCD Internal5_IRQHandler ; Internal SW Interrupt #5 + DCD Internal6_IRQHandler ; Internal SW Interrupt #6 + DCD Internal7_IRQHandler ; Internal SW Interrupt #7 + +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + SECTION .intvec_ram:DATA:REORDER:NOROOT(2) +__ramVectors + DS32 __Vectors_Size + + + THUMB + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default handlers +;; + PUBWEAK Default_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Default_Handler + B Default_Handler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Weak function for startup customization +;; +;; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +;; because this function is executed as the first instruction in the ResetHandler. +;; The PDL is also not initialized to use the proper register offsets. +;; The user of this function is responsible for initializing the PDL and resources before using them. +;; + PUBWEAK Cy_OnResetUser + SECTION .text:CODE:REORDER:NOROOT(2) +Cy_OnResetUser + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Define strong version to return zero for +;; __iar_program_start to skip data sections +;; initialization. +;; + PUBLIC __low_level_init + SECTION .text:CODE:REORDER:NOROOT(2) +__low_level_init + MOVS R0, #0 + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + ; Define strong function for startup customization + LDR R0, =Cy_OnResetUser + BLX R0 + + ; Copy vectors from ROM to RAM + LDR r1, =__vector_table + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +intvec_copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE intvec_copy + + ; Update Vector Table Offset Register + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb + + LDR R0, =__iar_program_start + BLX R0 + +; Should never get here +Cy_Main_Exited + B Cy_Main_Exited + + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK Cy_SysLib_FaultHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Cy_SysLib_FaultHandler + B Cy_SysLib_FaultHandler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + IMPORT Cy_SysLib_FaultHandler + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + b L_API_call +L_MSP + mrs r0, MSP +L_API_call + ; Storing LR content for Creator call stack trace + push {LR} + bl Cy_SysLib_FaultHandler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + + ; External interrupts + PUBWEAK NvicMux0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux0_IRQHandler + B NvicMux0_IRQHandler + + PUBWEAK NvicMux1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux1_IRQHandler + B NvicMux1_IRQHandler + + PUBWEAK NvicMux2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux2_IRQHandler + B NvicMux2_IRQHandler + + PUBWEAK NvicMux3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux3_IRQHandler + B NvicMux3_IRQHandler + + PUBWEAK NvicMux4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux4_IRQHandler + B NvicMux4_IRQHandler + + PUBWEAK NvicMux5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux5_IRQHandler + B NvicMux5_IRQHandler + + PUBWEAK NvicMux6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux6_IRQHandler + B NvicMux6_IRQHandler + + PUBWEAK NvicMux7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux7_IRQHandler + B NvicMux7_IRQHandler + + PUBWEAK Internal0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal0_IRQHandler + B Internal0_IRQHandler + + PUBWEAK Internal1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal1_IRQHandler + B Internal1_IRQHandler + + PUBWEAK Internal2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal2_IRQHandler + B Internal2_IRQHandler + + PUBWEAK Internal3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal3_IRQHandler + B Internal3_IRQHandler + + PUBWEAK Internal4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal4_IRQHandler + B Internal4_IRQHandler + + PUBWEAK Internal5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal5_IRQHandler + B Internal5_IRQHandler + + PUBWEAK Internal6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal6_IRQHandler + B Internal6_IRQHandler + + PUBWEAK Internal7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal7_IRQHandler + B Internal7_IRQHandler + + + END + + +; [] END OF FILE diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/system_psoc6_cm0plus.c b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/system_psoc6_cm0plus.c index 18cc197..2e2b152 100644 --- a/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/system_psoc6_cm0plus.c +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM0P/system_psoc6_cm0plus.c @@ -1,12 +1,12 @@ /***************************************************************************//** * \file system_psoc6_cm0plus.c -* \version 2.70 +* \version 2.70.1 * * The device system-source file. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx4_cm4_dual.sct b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx4_cm4_dual.sct new file mode 100644 index 0000000..e5a6e7d --- /dev/null +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx4_cm4_dual.sct @@ -0,0 +1,314 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xx4_cm4_dual.sct +;* \version 2.70.1 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2020 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +; More about CM0+ prebuilt images, see here: +; https://github.com/cypresssemiconductorco/psoc6cm0p +; The size of the Cortex-M0+ application flash image +#define FLASH_CM0P_SIZE 0x2000 + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +;* MBED_APP_START is being used by the bootloader build script and +;* will be calculate by the system. In case if MBED_APP_START address is +;* customized by the bootloader config, the application image should not +;* include CM0p prebuilt image. +;* + +#if !defined(MBED_APP_START) + #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE) +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x00040000 +#endif + +;* MBED_APP_SIZE is being used by the bootloader build script and +;* will be calculate by the system. +;* +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE) +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08002000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x0001D800 +#endif + +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +; The size of the stack section at the end of CM4 SRAM +#define STACK_SIZE MBED_BOOT_STACK_SIZE + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; You can change the memory allocation by editing RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. +; RAM +#define RAM_START MBED_RAM_START +#define RAM_SIZE MBED_RAM_SIZE +; Flash +#define FLASH_START MBED_APP_START +#define FLASH_SIZE MBED_APP_SIZE + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M0+ application flash image area +LR_IROM MBED_ROM_START FLASH_CM0P_SIZE +{ + .cy_m0p_image +0 FLASH_CM0P_SIZE + { + * (.cy_m0p_image) + } +} + +; Cortex-M4 application flash area +LR_IROM1 FLASH_START FLASH_SIZE +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1) + { + } + + ; Stack region growing down + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + .cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00040000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct index 4f8eeea..f50a592 100644 --- a/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xx5_cm4_dual.sct -;* \version 2.70 +;* \version 2.70.1 ;* ;* Linker file for the ARMCC. ;* @@ -26,7 +26,7 @@ ;* ;******************************************************************************* ;* \copyright -;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* Copyright 2016-2020 Cypress Semiconductor Corporation ;* SPDX-License-Identifier: Apache-2.0 ;* ;* Licensed under the Apache License, Version 2.0 (the "License"); @@ -42,6 +42,9 @@ ;* limitations under the License. ;******************************************************************************/ +; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +; More about CM0+ prebuilt images, see here: +; https://github.com/cypresssemiconductorco/psoc6cm0p ; The size of the Cortex-M0+ application flash image #define FLASH_CM0P_SIZE 0x2000 diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx6_cm4_dual.sct b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx6_cm4_dual.sct index ae49aba..0a99566 100644 --- a/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx6_cm4_dual.sct +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx6_cm4_dual.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xx6_cm4_dual.sct -;* \version 2.70 +;* \version 2.70.1 ;* ;* Linker file for the ARMCC. ;* @@ -26,7 +26,7 @@ ;* ;******************************************************************************* ;* \copyright -;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* Copyright 2016-2020 Cypress Semiconductor Corporation ;* SPDX-License-Identifier: Apache-2.0 ;* ;* Licensed under the Apache License, Version 2.0 (the "License"); @@ -42,6 +42,9 @@ ;* limitations under the License. ;******************************************************************************/ +; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +; More about CM0+ prebuilt images, see here: +; https://github.com/cypresssemiconductorco/psoc6cm0p ; The size of the Cortex-M0+ application flash image #define FLASH_CM0P_SIZE 0x2000 diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct index 0f7f5fe..e9a6874 100644 --- a/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xx7_cm4_dual.sct -;* \version 2.70 +;* \version 2.70.1 ;* ;* Linker file for the ARMCC. ;* @@ -26,7 +26,7 @@ ;* ;******************************************************************************* ;* \copyright -;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* Copyright 2016-2020 Cypress Semiconductor Corporation ;* SPDX-License-Identifier: Apache-2.0 ;* ;* Licensed under the Apache License, Version 2.0 (the "License"); @@ -42,6 +42,9 @@ ;* limitations under the License. ;******************************************************************************/ +; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +; More about CM0+ prebuilt images, see here: +; https://github.com/cypresssemiconductorco/psoc6cm0p ; The size of the Cortex-M0+ application flash image #define FLASH_CM0P_SIZE 0x2000 diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx8_cm4_dual.sct b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx8_cm4_dual.sct index 05248f9..d04d5b8 100644 --- a/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx8_cm4_dual.sct +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx8_cm4_dual.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xx8_cm4_dual.sct -;* \version 2.70 +;* \version 2.70.1 ;* ;* Linker file for the ARMCC. ;* @@ -26,7 +26,7 @@ ;* ;******************************************************************************* ;* \copyright -;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* Copyright 2016-2020 Cypress Semiconductor Corporation ;* SPDX-License-Identifier: Apache-2.0 ;* ;* Licensed under the Apache License, Version 2.0 (the "License"); @@ -42,6 +42,9 @@ ;* limitations under the License. ;******************************************************************************/ +; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +; More about CM0+ prebuilt images, see here: +; https://github.com/cypresssemiconductorco/psoc6cm0p ; The size of the Cortex-M0+ application flash image #define FLASH_CM0P_SIZE 0x2000 diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct index 620923d..74bb3c8 100644 --- a/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xxa_cm4_dual.sct -;* \version 2.70 +;* \version 2.70.1 ;* ;* Linker file for the ARMCC. ;* @@ -26,7 +26,7 @@ ;* ;******************************************************************************* ;* \copyright -;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* Copyright 2016-2020 Cypress Semiconductor Corporation ;* SPDX-License-Identifier: Apache-2.0 ;* ;* Licensed under the Apache License, Version 2.0 (the "License"); @@ -42,6 +42,9 @@ ;* limitations under the License. ;******************************************************************************/ +; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +; More about CM0+ prebuilt images, see here: +; https://github.com/cypresssemiconductorco/psoc6cm0p ; The size of the Cortex-M0+ application flash image #define FLASH_CM0P_SIZE 0x2000 diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx5_cm4.sct b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx5_cm4.sct index 68059e1..8d5020d 100644 --- a/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx5_cm4.sct +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx5_cm4.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cyb06xx5_cm4.sct -;* \version 2.70 +;* \version 2.70.1 ;* ;* Linker file for the ARMCC. ;* @@ -26,7 +26,7 @@ ;* ;******************************************************************************* ;* \copyright -;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* Copyright 2016-2020 Cypress Semiconductor Corporation ;* SPDX-License-Identifier: Apache-2.0 ;* ;* Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4.sct b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4.sct index 77d3f71..37b32f0 100644 --- a/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4.sct +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cyb06xx7_cm4.sct -;* \version 2.70 +;* \version 2.70.1 ;* ;* Linker file for the ARMCC. ;* @@ -26,7 +26,7 @@ ;* ;******************************************************************************* ;* \copyright -;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* Copyright 2016-2020 Cypress Semiconductor Corporation ;* SPDX-License-Identifier: Apache-2.0 ;* ;* Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4.sct b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4.sct index 0a03d5c..8fd5a3d 100644 --- a/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4.sct +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cyb06xxa_cm4.sct -;* \version 2.70 +;* \version 2.70.1 ;* ;* Linker file for the ARMCC. ;* @@ -26,7 +26,7 @@ ;* ;******************************************************************************* ;* \copyright -;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* Copyright 2016-2020 Cypress Semiconductor Corporation ;* SPDX-License-Identifier: Apache-2.0 ;* ;* Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_04_cm4.S b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_04_cm4.S new file mode 100644 index 0000000..f281c83 --- /dev/null +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_04_cm4.S @@ -0,0 +1,652 @@ +;/**************************************************************************//** +; * @file startup_psoc6_04_cm4.S +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device Series +; * @version V5.00 +; * @date 02. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| + +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack + DCD Reset_Handler ; Reset Handler + + DCD 0x0000000D ; NMI Handler located at ROM code + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External interrupts Description + DCD ioss_interrupts_gpio_0_IRQHandler ; GPIO Port Interrupt #0 + DCD 0 ; Reserved + DCD ioss_interrupts_gpio_2_IRQHandler ; GPIO Port Interrupt #2 + DCD ioss_interrupts_gpio_3_IRQHandler ; GPIO Port Interrupt #3 + DCD 0 ; Reserved + DCD ioss_interrupts_gpio_5_IRQHandler ; GPIO Port Interrupt #5 + DCD ioss_interrupts_gpio_6_IRQHandler ; GPIO Port Interrupt #6 + DCD ioss_interrupts_gpio_7_IRQHandler ; GPIO Port Interrupt #7 + DCD ioss_interrupts_gpio_8_IRQHandler ; GPIO Port Interrupt #8 + DCD ioss_interrupts_gpio_9_IRQHandler ; GPIO Port Interrupt #9 + DCD ioss_interrupts_gpio_10_IRQHandler ; GPIO Port Interrupt #10 + DCD ioss_interrupts_gpio_11_IRQHandler ; GPIO Port Interrupt #11 + DCD ioss_interrupts_gpio_12_IRQHandler ; GPIO Port Interrupt #12 + DCD 0 ; Reserved + DCD ioss_interrupts_gpio_14_IRQHandler ; GPIO Port Interrupt #14 + DCD ioss_interrupt_gpio_IRQHandler ; GPIO All Ports + DCD ioss_interrupt_vdd_IRQHandler ; GPIO Supply Detect Interrupt + DCD lpcomp_interrupt_IRQHandler ; Low Power Comparator Interrupt + DCD scb_6_interrupt_IRQHandler ; Serial Communication Block #6 (DeepSleep capable) + DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt + DCD srss_interrupt_IRQHandler ; Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) + DCD cpuss_interrupts_ipc_0_IRQHandler ; CPUSS Inter Process Communication Interrupt #0 + DCD cpuss_interrupts_ipc_1_IRQHandler ; CPUSS Inter Process Communication Interrupt #1 + DCD cpuss_interrupts_ipc_2_IRQHandler ; CPUSS Inter Process Communication Interrupt #2 + DCD cpuss_interrupts_ipc_3_IRQHandler ; CPUSS Inter Process Communication Interrupt #3 + DCD cpuss_interrupts_ipc_4_IRQHandler ; CPUSS Inter Process Communication Interrupt #4 + DCD cpuss_interrupts_ipc_5_IRQHandler ; CPUSS Inter Process Communication Interrupt #5 + DCD cpuss_interrupts_ipc_6_IRQHandler ; CPUSS Inter Process Communication Interrupt #6 + DCD cpuss_interrupts_ipc_7_IRQHandler ; CPUSS Inter Process Communication Interrupt #7 + DCD cpuss_interrupts_ipc_8_IRQHandler ; CPUSS Inter Process Communication Interrupt #8 + DCD cpuss_interrupts_ipc_9_IRQHandler ; CPUSS Inter Process Communication Interrupt #9 + DCD cpuss_interrupts_ipc_10_IRQHandler ; CPUSS Inter Process Communication Interrupt #10 + DCD cpuss_interrupts_ipc_11_IRQHandler ; CPUSS Inter Process Communication Interrupt #11 + DCD cpuss_interrupts_ipc_12_IRQHandler ; CPUSS Inter Process Communication Interrupt #12 + DCD cpuss_interrupts_ipc_13_IRQHandler ; CPUSS Inter Process Communication Interrupt #13 + DCD cpuss_interrupts_ipc_14_IRQHandler ; CPUSS Inter Process Communication Interrupt #14 + DCD cpuss_interrupts_ipc_15_IRQHandler ; CPUSS Inter Process Communication Interrupt #15 + DCD pass_interrupt_sar_0_IRQHandler ; SAR ADC0 interrupt + DCD pass_interrupt_sar_1_IRQHandler ; SAR ADC1 interrupt + DCD pass_interrupt_ctb_IRQHandler ; individual interrupt per CTB + DCD 0 ; Reserved + DCD pass_interrupt_fifo_0_IRQHandler ; PASS FIFO0 + DCD pass_interrupt_fifo_1_IRQHandler ; PASS FIFO1 + DCD scb_0_interrupt_IRQHandler ; Serial Communication Block #0 + DCD scb_1_interrupt_IRQHandler ; Serial Communication Block #1 + DCD scb_2_interrupt_IRQHandler ; Serial Communication Block #2 + DCD 0 ; Reserved + DCD scb_4_interrupt_IRQHandler ; Serial Communication Block #4 + DCD scb_5_interrupt_IRQHandler ; Serial Communication Block #5 + DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt + DCD cpuss_interrupts_dmac_0_IRQHandler ; CPUSS DMAC, Channel #0 + DCD cpuss_interrupts_dmac_1_IRQHandler ; CPUSS DMAC, Channel #1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD cpuss_interrupts_dw0_0_IRQHandler ; CPUSS DataWire #0, Channel #0 + DCD cpuss_interrupts_dw0_1_IRQHandler ; CPUSS DataWire #0, Channel #1 + DCD cpuss_interrupts_dw0_2_IRQHandler ; CPUSS DataWire #0, Channel #2 + DCD cpuss_interrupts_dw0_3_IRQHandler ; CPUSS DataWire #0, Channel #3 + DCD cpuss_interrupts_dw0_4_IRQHandler ; CPUSS DataWire #0, Channel #4 + DCD cpuss_interrupts_dw0_5_IRQHandler ; CPUSS DataWire #0, Channel #5 + DCD cpuss_interrupts_dw0_6_IRQHandler ; CPUSS DataWire #0, Channel #6 + DCD cpuss_interrupts_dw0_7_IRQHandler ; CPUSS DataWire #0, Channel #7 + DCD cpuss_interrupts_dw0_8_IRQHandler ; CPUSS DataWire #0, Channel #8 + DCD cpuss_interrupts_dw0_9_IRQHandler ; CPUSS DataWire #0, Channel #9 + DCD cpuss_interrupts_dw0_10_IRQHandler ; CPUSS DataWire #0, Channel #10 + DCD cpuss_interrupts_dw0_11_IRQHandler ; CPUSS DataWire #0, Channel #11 + DCD cpuss_interrupts_dw0_12_IRQHandler ; CPUSS DataWire #0, Channel #12 + DCD cpuss_interrupts_dw0_13_IRQHandler ; CPUSS DataWire #0, Channel #13 + DCD cpuss_interrupts_dw0_14_IRQHandler ; CPUSS DataWire #0, Channel #14 + DCD cpuss_interrupts_dw0_15_IRQHandler ; CPUSS DataWire #0, Channel #15 + DCD cpuss_interrupts_dw0_16_IRQHandler ; CPUSS DataWire #0, Channel #16 + DCD cpuss_interrupts_dw0_17_IRQHandler ; CPUSS DataWire #0, Channel #17 + DCD cpuss_interrupts_dw0_18_IRQHandler ; CPUSS DataWire #0, Channel #18 + DCD cpuss_interrupts_dw0_19_IRQHandler ; CPUSS DataWire #0, Channel #19 + DCD cpuss_interrupts_dw0_20_IRQHandler ; CPUSS DataWire #0, Channel #20 + DCD cpuss_interrupts_dw0_21_IRQHandler ; CPUSS DataWire #0, Channel #21 + DCD cpuss_interrupts_dw0_22_IRQHandler ; CPUSS DataWire #0, Channel #22 + DCD cpuss_interrupts_dw0_23_IRQHandler ; CPUSS DataWire #0, Channel #23 + DCD cpuss_interrupts_dw0_24_IRQHandler ; CPUSS DataWire #0, Channel #24 + DCD cpuss_interrupts_dw0_25_IRQHandler ; CPUSS DataWire #0, Channel #25 + DCD cpuss_interrupts_dw0_26_IRQHandler ; CPUSS DataWire #0, Channel #26 + DCD cpuss_interrupts_dw0_27_IRQHandler ; CPUSS DataWire #0, Channel #27 + DCD cpuss_interrupts_dw0_28_IRQHandler ; CPUSS DataWire #0, Channel #28 + DCD cpuss_interrupts_dw1_0_IRQHandler ; CPUSS DataWire #1, Channel #0 + DCD cpuss_interrupts_dw1_1_IRQHandler ; CPUSS DataWire #1, Channel #1 + DCD cpuss_interrupts_dw1_2_IRQHandler ; CPUSS DataWire #1, Channel #2 + DCD cpuss_interrupts_dw1_3_IRQHandler ; CPUSS DataWire #1, Channel #3 + DCD cpuss_interrupts_dw1_4_IRQHandler ; CPUSS DataWire #1, Channel #4 + DCD cpuss_interrupts_dw1_5_IRQHandler ; CPUSS DataWire #1, Channel #5 + DCD cpuss_interrupts_dw1_6_IRQHandler ; CPUSS DataWire #1, Channel #6 + DCD cpuss_interrupts_dw1_7_IRQHandler ; CPUSS DataWire #1, Channel #7 + DCD cpuss_interrupts_dw1_8_IRQHandler ; CPUSS DataWire #1, Channel #8 + DCD cpuss_interrupts_dw1_9_IRQHandler ; CPUSS DataWire #1, Channel #9 + DCD cpuss_interrupts_dw1_10_IRQHandler ; CPUSS DataWire #1, Channel #10 + DCD cpuss_interrupts_dw1_11_IRQHandler ; CPUSS DataWire #1, Channel #11 + DCD cpuss_interrupts_dw1_12_IRQHandler ; CPUSS DataWire #1, Channel #12 + DCD cpuss_interrupts_dw1_13_IRQHandler ; CPUSS DataWire #1, Channel #13 + DCD cpuss_interrupts_dw1_14_IRQHandler ; CPUSS DataWire #1, Channel #14 + DCD cpuss_interrupts_dw1_15_IRQHandler ; CPUSS DataWire #1, Channel #15 + DCD cpuss_interrupts_dw1_16_IRQHandler ; CPUSS DataWire #1, Channel #16 + DCD cpuss_interrupts_dw1_17_IRQHandler ; CPUSS DataWire #1, Channel #17 + DCD cpuss_interrupts_dw1_18_IRQHandler ; CPUSS DataWire #1, Channel #18 + DCD cpuss_interrupts_dw1_19_IRQHandler ; CPUSS DataWire #1, Channel #19 + DCD cpuss_interrupts_dw1_20_IRQHandler ; CPUSS DataWire #1, Channel #20 + DCD cpuss_interrupts_dw1_21_IRQHandler ; CPUSS DataWire #1, Channel #21 + DCD cpuss_interrupts_dw1_22_IRQHandler ; CPUSS DataWire #1, Channel #22 + DCD cpuss_interrupts_dw1_23_IRQHandler ; CPUSS DataWire #1, Channel #23 + DCD cpuss_interrupts_dw1_24_IRQHandler ; CPUSS DataWire #1, Channel #24 + DCD cpuss_interrupts_dw1_25_IRQHandler ; CPUSS DataWire #1, Channel #25 + DCD cpuss_interrupts_dw1_26_IRQHandler ; CPUSS DataWire #1, Channel #26 + DCD cpuss_interrupts_dw1_27_IRQHandler ; CPUSS DataWire #1, Channel #27 + DCD cpuss_interrupts_dw1_28_IRQHandler ; CPUSS DataWire #1, Channel #28 + DCD cpuss_interrupts_fault_0_IRQHandler ; CPUSS Fault Structure Interrupt #0 + DCD cpuss_interrupts_fault_1_IRQHandler ; CPUSS Fault Structure Interrupt #1 + DCD cpuss_interrupt_crypto_IRQHandler ; CRYPTO Accelerator Interrupt + DCD cpuss_interrupt_fm_IRQHandler ; FLASH Macro Interrupt + DCD cpuss_interrupts_cm4_fp_IRQHandler ; Floating Point operation fault + DCD cpuss_interrupts_cm0_cti_0_IRQHandler ; CM0+ CTI #0 + DCD cpuss_interrupts_cm0_cti_1_IRQHandler ; CM0+ CTI #1 + DCD cpuss_interrupts_cm4_cti_0_IRQHandler ; CM4 CTI #0 + DCD cpuss_interrupts_cm4_cti_1_IRQHandler ; CM4 CTI #1 + DCD tcpwm_0_interrupts_0_IRQHandler ; TCPWM #0, Counter #0 + DCD tcpwm_0_interrupts_1_IRQHandler ; TCPWM #0, Counter #1 + DCD tcpwm_0_interrupts_2_IRQHandler ; TCPWM #0, Counter #2 + DCD tcpwm_0_interrupts_3_IRQHandler ; TCPWM #0, Counter #3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD tcpwm_0_interrupts_256_IRQHandler ; TCPWM #0, Counter #256 + DCD tcpwm_0_interrupts_257_IRQHandler ; TCPWM #0, Counter #257 + DCD tcpwm_0_interrupts_258_IRQHandler ; TCPWM #0, Counter #258 + DCD tcpwm_0_interrupts_259_IRQHandler ; TCPWM #0, Counter #259 + DCD tcpwm_0_interrupts_260_IRQHandler ; TCPWM #0, Counter #260 + DCD tcpwm_0_interrupts_261_IRQHandler ; TCPWM #0, Counter #261 + DCD tcpwm_0_interrupts_262_IRQHandler ; TCPWM #0, Counter #262 + DCD tcpwm_0_interrupts_263_IRQHandler ; TCPWM #0, Counter #263 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD pass_interrupt_dacs_IRQHandler ; Consolidated interrrupt for all DACs + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt + DCD usb_interrupt_hi_IRQHandler ; USB Interrupt + DCD usb_interrupt_med_IRQHandler ; USB Interrupt + DCD usb_interrupt_lo_IRQHandler ; USB Interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD canfd_0_interrupt0_IRQHandler ; Can #0, Consolidated interrupt #0 + DCD canfd_0_interrupts0_0_IRQHandler ; CAN #0, Interrupt #0, Channel #0 + DCD canfd_0_interrupts1_0_IRQHandler ; CAN #0, Interrupt #1, Channel #0 + DCD cpuss_interrupts_dw1_29_IRQHandler ; CPUSS DataWire #1, Channel #29 + DCD cpuss_interrupts_dw1_30_IRQHandler ; CPUSS DataWire #1, Channel #30 + DCD cpuss_interrupts_dw1_31_IRQHandler ; CPUSS DataWire #1, Channel #31 + DCD cpuss_interrupts_dw0_29_IRQHandler ; CPUSS DataWire #0, Channel #29 + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + EXPORT __ramVectors + AREA RESET_RAM, READWRITE, NOINIT +__ramVectors SPACE __Vectors_Size + + + AREA |.text|, CODE, READONLY + + +; Weak function for startup customization +; +; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +; because this function is executed as the first instruction in the ResetHandler. +; The PDL is also not initialized to use the proper register offsets. +; The user of this function is responsible for initializing the PDL and resources before using them. +; +Cy_OnResetUser PROC + EXPORT Cy_OnResetUser [WEAK] + BX LR + ENDP + +; Reset Handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT Cy_SystemInitFpuEnable + IMPORT __main + + ; Define strong function for startup customization + BL Cy_OnResetUser + + ; Disable global interrupts + CPSID I + + ; Copy vectors from ROM to RAM + LDR r1, =__Vectors + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +Vectors_Copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE Vectors_Copy + + ; Update Vector Table Offset Register. */ + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb 0xF + + ; Enable the FPU if used + LDR R0, =Cy_SystemInitFpuEnable + BLX R0 + + LDR R0, =__main + BLX R0 + + ; Should never get here + B . + + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +Cy_SysLib_FaultHandler PROC + EXPORT Cy_SysLib_FaultHandler [WEAK] + B . + ENDP +HardFault_Wrapper\ + PROC + EXPORT HardFault_Wrapper [WEAK] + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + bl L_API_call +L_MSP + mrs r0, MSP +L_API_call + bl Cy_SysLib_FaultHandler + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B HardFault_Wrapper + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B HardFault_Wrapper + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B HardFault_Wrapper + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B HardFault_Wrapper + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT Default_Handler [WEAK] + EXPORT ioss_interrupts_gpio_0_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_2_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_3_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_5_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_6_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_7_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_8_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_9_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_10_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_11_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_12_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_14_IRQHandler [WEAK] + EXPORT ioss_interrupt_gpio_IRQHandler [WEAK] + EXPORT ioss_interrupt_vdd_IRQHandler [WEAK] + EXPORT lpcomp_interrupt_IRQHandler [WEAK] + EXPORT scb_6_interrupt_IRQHandler [WEAK] + EXPORT srss_interrupt_mcwdt_0_IRQHandler [WEAK] + EXPORT srss_interrupt_mcwdt_1_IRQHandler [WEAK] + EXPORT srss_interrupt_backup_IRQHandler [WEAK] + EXPORT srss_interrupt_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_4_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_5_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_6_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_7_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_8_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_9_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_10_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_11_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_12_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_13_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_14_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_15_IRQHandler [WEAK] + EXPORT pass_interrupt_sar_0_IRQHandler [WEAK] + EXPORT pass_interrupt_sar_1_IRQHandler [WEAK] + EXPORT pass_interrupt_ctb_IRQHandler [WEAK] + EXPORT pass_interrupt_fifo_0_IRQHandler [WEAK] + EXPORT pass_interrupt_fifo_1_IRQHandler [WEAK] + EXPORT scb_0_interrupt_IRQHandler [WEAK] + EXPORT scb_1_interrupt_IRQHandler [WEAK] + EXPORT scb_2_interrupt_IRQHandler [WEAK] + EXPORT scb_4_interrupt_IRQHandler [WEAK] + EXPORT scb_5_interrupt_IRQHandler [WEAK] + EXPORT csd_interrupt_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dmac_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dmac_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_4_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_5_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_6_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_7_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_8_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_9_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_10_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_11_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_12_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_13_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_14_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_15_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_16_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_17_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_18_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_19_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_20_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_21_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_22_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_23_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_24_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_25_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_26_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_27_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_28_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_4_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_5_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_6_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_7_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_8_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_9_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_10_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_11_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_12_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_13_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_14_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_15_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_16_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_17_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_18_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_19_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_20_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_21_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_22_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_23_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_24_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_25_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_26_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_27_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_28_IRQHandler [WEAK] + EXPORT cpuss_interrupts_fault_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_fault_1_IRQHandler [WEAK] + EXPORT cpuss_interrupt_crypto_IRQHandler [WEAK] + EXPORT cpuss_interrupt_fm_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm4_fp_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm0_cti_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm0_cti_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm4_cti_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm4_cti_1_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_0_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_1_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_2_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_3_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_256_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_257_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_258_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_259_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_260_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_261_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_262_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_263_IRQHandler [WEAK] + EXPORT pass_interrupt_dacs_IRQHandler [WEAK] + EXPORT smif_interrupt_IRQHandler [WEAK] + EXPORT usb_interrupt_hi_IRQHandler [WEAK] + EXPORT usb_interrupt_med_IRQHandler [WEAK] + EXPORT usb_interrupt_lo_IRQHandler [WEAK] + EXPORT canfd_0_interrupt0_IRQHandler [WEAK] + EXPORT canfd_0_interrupts0_0_IRQHandler [WEAK] + EXPORT canfd_0_interrupts1_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_29_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_30_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_31_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_29_IRQHandler [WEAK] + +ioss_interrupts_gpio_0_IRQHandler +ioss_interrupts_gpio_2_IRQHandler +ioss_interrupts_gpio_3_IRQHandler +ioss_interrupts_gpio_5_IRQHandler +ioss_interrupts_gpio_6_IRQHandler +ioss_interrupts_gpio_7_IRQHandler +ioss_interrupts_gpio_8_IRQHandler +ioss_interrupts_gpio_9_IRQHandler +ioss_interrupts_gpio_10_IRQHandler +ioss_interrupts_gpio_11_IRQHandler +ioss_interrupts_gpio_12_IRQHandler +ioss_interrupts_gpio_14_IRQHandler +ioss_interrupt_gpio_IRQHandler +ioss_interrupt_vdd_IRQHandler +lpcomp_interrupt_IRQHandler +scb_6_interrupt_IRQHandler +srss_interrupt_mcwdt_0_IRQHandler +srss_interrupt_mcwdt_1_IRQHandler +srss_interrupt_backup_IRQHandler +srss_interrupt_IRQHandler +cpuss_interrupts_ipc_0_IRQHandler +cpuss_interrupts_ipc_1_IRQHandler +cpuss_interrupts_ipc_2_IRQHandler +cpuss_interrupts_ipc_3_IRQHandler +cpuss_interrupts_ipc_4_IRQHandler +cpuss_interrupts_ipc_5_IRQHandler +cpuss_interrupts_ipc_6_IRQHandler +cpuss_interrupts_ipc_7_IRQHandler +cpuss_interrupts_ipc_8_IRQHandler +cpuss_interrupts_ipc_9_IRQHandler +cpuss_interrupts_ipc_10_IRQHandler +cpuss_interrupts_ipc_11_IRQHandler +cpuss_interrupts_ipc_12_IRQHandler +cpuss_interrupts_ipc_13_IRQHandler +cpuss_interrupts_ipc_14_IRQHandler +cpuss_interrupts_ipc_15_IRQHandler +pass_interrupt_sar_0_IRQHandler +pass_interrupt_sar_1_IRQHandler +pass_interrupt_ctb_IRQHandler +pass_interrupt_fifo_0_IRQHandler +pass_interrupt_fifo_1_IRQHandler +scb_0_interrupt_IRQHandler +scb_1_interrupt_IRQHandler +scb_2_interrupt_IRQHandler +scb_4_interrupt_IRQHandler +scb_5_interrupt_IRQHandler +csd_interrupt_IRQHandler +cpuss_interrupts_dmac_0_IRQHandler +cpuss_interrupts_dmac_1_IRQHandler +cpuss_interrupts_dw0_0_IRQHandler +cpuss_interrupts_dw0_1_IRQHandler +cpuss_interrupts_dw0_2_IRQHandler +cpuss_interrupts_dw0_3_IRQHandler +cpuss_interrupts_dw0_4_IRQHandler +cpuss_interrupts_dw0_5_IRQHandler +cpuss_interrupts_dw0_6_IRQHandler +cpuss_interrupts_dw0_7_IRQHandler +cpuss_interrupts_dw0_8_IRQHandler +cpuss_interrupts_dw0_9_IRQHandler +cpuss_interrupts_dw0_10_IRQHandler +cpuss_interrupts_dw0_11_IRQHandler +cpuss_interrupts_dw0_12_IRQHandler +cpuss_interrupts_dw0_13_IRQHandler +cpuss_interrupts_dw0_14_IRQHandler +cpuss_interrupts_dw0_15_IRQHandler +cpuss_interrupts_dw0_16_IRQHandler +cpuss_interrupts_dw0_17_IRQHandler +cpuss_interrupts_dw0_18_IRQHandler +cpuss_interrupts_dw0_19_IRQHandler +cpuss_interrupts_dw0_20_IRQHandler +cpuss_interrupts_dw0_21_IRQHandler +cpuss_interrupts_dw0_22_IRQHandler +cpuss_interrupts_dw0_23_IRQHandler +cpuss_interrupts_dw0_24_IRQHandler +cpuss_interrupts_dw0_25_IRQHandler +cpuss_interrupts_dw0_26_IRQHandler +cpuss_interrupts_dw0_27_IRQHandler +cpuss_interrupts_dw0_28_IRQHandler +cpuss_interrupts_dw1_0_IRQHandler +cpuss_interrupts_dw1_1_IRQHandler +cpuss_interrupts_dw1_2_IRQHandler +cpuss_interrupts_dw1_3_IRQHandler +cpuss_interrupts_dw1_4_IRQHandler +cpuss_interrupts_dw1_5_IRQHandler +cpuss_interrupts_dw1_6_IRQHandler +cpuss_interrupts_dw1_7_IRQHandler +cpuss_interrupts_dw1_8_IRQHandler +cpuss_interrupts_dw1_9_IRQHandler +cpuss_interrupts_dw1_10_IRQHandler +cpuss_interrupts_dw1_11_IRQHandler +cpuss_interrupts_dw1_12_IRQHandler +cpuss_interrupts_dw1_13_IRQHandler +cpuss_interrupts_dw1_14_IRQHandler +cpuss_interrupts_dw1_15_IRQHandler +cpuss_interrupts_dw1_16_IRQHandler +cpuss_interrupts_dw1_17_IRQHandler +cpuss_interrupts_dw1_18_IRQHandler +cpuss_interrupts_dw1_19_IRQHandler +cpuss_interrupts_dw1_20_IRQHandler +cpuss_interrupts_dw1_21_IRQHandler +cpuss_interrupts_dw1_22_IRQHandler +cpuss_interrupts_dw1_23_IRQHandler +cpuss_interrupts_dw1_24_IRQHandler +cpuss_interrupts_dw1_25_IRQHandler +cpuss_interrupts_dw1_26_IRQHandler +cpuss_interrupts_dw1_27_IRQHandler +cpuss_interrupts_dw1_28_IRQHandler +cpuss_interrupts_fault_0_IRQHandler +cpuss_interrupts_fault_1_IRQHandler +cpuss_interrupt_crypto_IRQHandler +cpuss_interrupt_fm_IRQHandler +cpuss_interrupts_cm4_fp_IRQHandler +cpuss_interrupts_cm0_cti_0_IRQHandler +cpuss_interrupts_cm0_cti_1_IRQHandler +cpuss_interrupts_cm4_cti_0_IRQHandler +cpuss_interrupts_cm4_cti_1_IRQHandler +tcpwm_0_interrupts_0_IRQHandler +tcpwm_0_interrupts_1_IRQHandler +tcpwm_0_interrupts_2_IRQHandler +tcpwm_0_interrupts_3_IRQHandler +tcpwm_0_interrupts_256_IRQHandler +tcpwm_0_interrupts_257_IRQHandler +tcpwm_0_interrupts_258_IRQHandler +tcpwm_0_interrupts_259_IRQHandler +tcpwm_0_interrupts_260_IRQHandler +tcpwm_0_interrupts_261_IRQHandler +tcpwm_0_interrupts_262_IRQHandler +tcpwm_0_interrupts_263_IRQHandler +pass_interrupt_dacs_IRQHandler +smif_interrupt_IRQHandler +usb_interrupt_hi_IRQHandler +usb_interrupt_med_IRQHandler +usb_interrupt_lo_IRQHandler +canfd_0_interrupt0_IRQHandler +canfd_0_interrupts0_0_IRQHandler +canfd_0_interrupts1_0_IRQHandler +cpuss_interrupts_dw1_29_IRQHandler +cpuss_interrupts_dw1_30_IRQHandler +cpuss_interrupts_dw1_31_IRQHandler +cpuss_interrupts_dw0_29_IRQHandler + + B . + ENDP + + ALIGN + + END + + +; [] END OF FILE diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx4_cm4_dual.ld b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx4_cm4_dual.ld new file mode 100644 index 0000000..bcd1029 --- /dev/null +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx4_cm4_dual.ld @@ -0,0 +1,465 @@ +/***************************************************************************//** +* \file cy8c6xx4_cm4_dual.ld +* \version 2.70.1 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + +/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p +*/ +/* The size of the Cortex-M0+ application image at the start of FLASH */ +FLASH_CM0P_SIZE = 0x2000; + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +/* MBED_APP_START is being used by the bootloader build script and +* will be calculate by the system. In case if MBED_APP_START address is +* customized by the bootloader config, the application image should not +* include CM0p prebuilt image. +*/ +#if !defined(MBED_APP_START) + #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE) +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x00040000 +#endif + +/* MBED_APP_SIZE is being used by the bootloader build script and +* will be calculate by the system. +*/ +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE) +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08002000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x0001D800 +#endif + +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +/* The size of the stack section at the end of CM4 SRAM */ +STACK_SIZE = MBED_BOOT_STACK_SIZE; + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing the 'ram' and 'flash' regions. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'. + */ + ram (rwx) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE + cm0p_image (rx) : ORIGIN = MBED_ROM_START, LENGTH = FLASH_CM0P_SIZE + flash (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE + + /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ + em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */ + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + /* Cortex-M0+ application flash image area */ + .cy_m0p_image ORIGIN(cm0p_image) : + { + . = ALIGN(4); + __cy_m0p_code_start = . ; + KEEP(*(.cy_m0p_image)) + __cy_m0p_code_end = . ; + } > cm0p_image + + /* Cortex-M4 application flash area */ + .text ORIGIN(flash) : + { + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_04_cm4.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_04_cm4.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Used for the digital signature of the secure application and the Bootloader SDK application. + * The size of the section depends on the required data size. */ + .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 : + { + KEEP(*(.cy_app_signature)) + } > flash + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + .cy_xip : + { + KEEP(*(.cy_xip)) + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x00040000; +__cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +__cy_memory_1_start = 0x14000000; +__cy_memory_1_length = 0x8000; +__cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm4_dual.ld b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm4_dual.ld index f6fbe4a..c7170ad 100644 --- a/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm4_dual.ld +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm4_dual.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx5_cm4_dual.ld -* \version 2.70 +* \version 2.70.1 * * Linker file for the GNU C compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -40,6 +40,10 @@ SEARCH_DIR(.) GROUP(-lgcc -lc -lnosys) ENTRY(Reset_Handler) +/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p +*/ /* The size of the Cortex-M0+ application image at the start of FLASH */ FLASH_CM0P_SIZE = 0x2000; diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx6_cm4_dual.ld b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx6_cm4_dual.ld index 9de6a36..5da0981 100644 --- a/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx6_cm4_dual.ld +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx6_cm4_dual.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx6_cm4_dual.ld -* \version 2.70 +* \version 2.70.1 * * Linker file for the GNU C compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -40,6 +40,10 @@ SEARCH_DIR(.) GROUP(-lgcc -lc -lnosys) ENTRY(Reset_Handler) +/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p +*/ /* The size of the Cortex-M0+ application image at the start of FLASH */ FLASH_CM0P_SIZE = 0x2000; diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld index 9be3c4a..f0a3d74 100644 --- a/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx7_cm4_dual.ld -* \version 2.70 +* \version 2.70.1 * * Linker file for the GNU C compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -40,6 +40,10 @@ SEARCH_DIR(.) GROUP(-lgcc -lc -lnosys) ENTRY(Reset_Handler) +/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p +*/ /* The size of the Cortex-M0+ application image at the start of FLASH */ FLASH_CM0P_SIZE = 0x2000; diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx8_cm4_dual.ld b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx8_cm4_dual.ld index 0f94372..2d758d1 100644 --- a/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx8_cm4_dual.ld +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx8_cm4_dual.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx8_cm4_dual.ld -* \version 2.70 +* \version 2.70.1 * * Linker file for the GNU C compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -40,6 +40,10 @@ SEARCH_DIR(.) GROUP(-lgcc -lc -lnosys) ENTRY(Reset_Handler) +/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p +*/ /* The size of the Cortex-M0+ application image at the start of FLASH */ FLASH_CM0P_SIZE = 0x2000; diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld index ffbeca9..72e55e3 100644 --- a/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xxa_cm4_dual.ld -* \version 2.70 +* \version 2.70.1 * * Linker file for the GNU C compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -40,6 +40,10 @@ SEARCH_DIR(.) GROUP(-lgcc -lc -lnosys) ENTRY(Reset_Handler) +/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p +*/ /* The size of the Cortex-M0+ application image at the start of FLASH */ FLASH_CM0P_SIZE = 0x2000; diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx5_cm4.ld b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx5_cm4.ld index f5220a9..8a7b89a 100644 --- a/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx5_cm4.ld +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx5_cm4.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cyb06xx5_cm4.ld -* \version 2.70 +* \version 2.70.1 * * Linker file for the GNU C compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4.ld b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4.ld index da76487..7c8b13a 100644 --- a/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4.ld +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cyb06xx7_cm4.ld -* \version 2.70 +* \version 2.70.1 * * Linker file for the GNU C compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4.ld b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4.ld index 6bc500f..6b29f39 100644 --- a/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4.ld +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cyb06xxa_cm4.ld -* \version 2.70 +* \version 2.70.1 * * Linker file for the GNU C compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_04_cm4.S b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_04_cm4.S new file mode 100644 index 0000000..0dbbb24 --- /dev/null +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_04_cm4.S @@ -0,0 +1,652 @@ +/**************************************************************************//** + * @file startup_psoc6_04_cm4.S + * @brief CMSIS Core Device Startup File for + * ARMCM4 Device Series + * @version V5.00 + * @date 02. March 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + /* Address of the NMI handler */ + #define CY_NMI_HANLDER_ADDR 0x0000000D + + /* The CPU VTOR register */ + #define CY_CPU_VTOR_ADDR 0xE000ED08 + + /* Copy flash vectors and data section to RAM */ + #define __STARTUP_COPY_MULTIPLE + + /* Clear single BSS section */ + #define __STARTUP_CLEAR_BSS + + .syntax unified + .arch armv7-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x00001000 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x00000400 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .vectors + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long CY_NMI_HANLDER_ADDR /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts Description */ + .long ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ + .long 0 /* Reserved */ + .long ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ + .long ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ + .long 0 /* Reserved */ + .long ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ + .long ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ + .long ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ + .long ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ + .long ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ + .long ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ + .long ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ + .long ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ + .long 0 /* Reserved */ + .long ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ + .long ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ + .long ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ + .long lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ + .long scb_6_interrupt_IRQHandler /* Serial Communication Block #6 (DeepSleep capable) */ + .long srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + .long srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + .long srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ + .long srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + .long cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ + .long cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ + .long cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ + .long cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ + .long cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ + .long cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ + .long cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ + .long cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ + .long cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ + .long cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ + .long cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ + .long cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ + .long cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ + .long cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ + .long cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ + .long cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ + .long pass_interrupt_sar_0_IRQHandler /* SAR ADC0 interrupt */ + .long pass_interrupt_sar_1_IRQHandler /* SAR ADC1 interrupt */ + .long pass_interrupt_ctb_IRQHandler /* individual interrupt per CTB */ + .long 0 /* Reserved */ + .long pass_interrupt_fifo_0_IRQHandler /* PASS FIFO0 */ + .long pass_interrupt_fifo_1_IRQHandler /* PASS FIFO1 */ + .long scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ + .long scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ + .long scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ + .long 0 /* Reserved */ + .long scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ + .long scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ + .long csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ + .long cpuss_interrupts_dmac_0_IRQHandler /* CPUSS DMAC, Channel #0 */ + .long cpuss_interrupts_dmac_1_IRQHandler /* CPUSS DMAC, Channel #1 */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ + .long cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ + .long cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ + .long cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ + .long cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ + .long cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ + .long cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ + .long cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ + .long cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ + .long cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ + .long cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ + .long cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ + .long cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ + .long cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ + .long cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ + .long cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ + .long cpuss_interrupts_dw0_16_IRQHandler /* CPUSS DataWire #0, Channel #16 */ + .long cpuss_interrupts_dw0_17_IRQHandler /* CPUSS DataWire #0, Channel #17 */ + .long cpuss_interrupts_dw0_18_IRQHandler /* CPUSS DataWire #0, Channel #18 */ + .long cpuss_interrupts_dw0_19_IRQHandler /* CPUSS DataWire #0, Channel #19 */ + .long cpuss_interrupts_dw0_20_IRQHandler /* CPUSS DataWire #0, Channel #20 */ + .long cpuss_interrupts_dw0_21_IRQHandler /* CPUSS DataWire #0, Channel #21 */ + .long cpuss_interrupts_dw0_22_IRQHandler /* CPUSS DataWire #0, Channel #22 */ + .long cpuss_interrupts_dw0_23_IRQHandler /* CPUSS DataWire #0, Channel #23 */ + .long cpuss_interrupts_dw0_24_IRQHandler /* CPUSS DataWire #0, Channel #24 */ + .long cpuss_interrupts_dw0_25_IRQHandler /* CPUSS DataWire #0, Channel #25 */ + .long cpuss_interrupts_dw0_26_IRQHandler /* CPUSS DataWire #0, Channel #26 */ + .long cpuss_interrupts_dw0_27_IRQHandler /* CPUSS DataWire #0, Channel #27 */ + .long cpuss_interrupts_dw0_28_IRQHandler /* CPUSS DataWire #0, Channel #28 */ + .long cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ + .long cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ + .long cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ + .long cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ + .long cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ + .long cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ + .long cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ + .long cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ + .long cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ + .long cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ + .long cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ + .long cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ + .long cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ + .long cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ + .long cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ + .long cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ + .long cpuss_interrupts_dw1_16_IRQHandler /* CPUSS DataWire #1, Channel #16 */ + .long cpuss_interrupts_dw1_17_IRQHandler /* CPUSS DataWire #1, Channel #17 */ + .long cpuss_interrupts_dw1_18_IRQHandler /* CPUSS DataWire #1, Channel #18 */ + .long cpuss_interrupts_dw1_19_IRQHandler /* CPUSS DataWire #1, Channel #19 */ + .long cpuss_interrupts_dw1_20_IRQHandler /* CPUSS DataWire #1, Channel #20 */ + .long cpuss_interrupts_dw1_21_IRQHandler /* CPUSS DataWire #1, Channel #21 */ + .long cpuss_interrupts_dw1_22_IRQHandler /* CPUSS DataWire #1, Channel #22 */ + .long cpuss_interrupts_dw1_23_IRQHandler /* CPUSS DataWire #1, Channel #23 */ + .long cpuss_interrupts_dw1_24_IRQHandler /* CPUSS DataWire #1, Channel #24 */ + .long cpuss_interrupts_dw1_25_IRQHandler /* CPUSS DataWire #1, Channel #25 */ + .long cpuss_interrupts_dw1_26_IRQHandler /* CPUSS DataWire #1, Channel #26 */ + .long cpuss_interrupts_dw1_27_IRQHandler /* CPUSS DataWire #1, Channel #27 */ + .long cpuss_interrupts_dw1_28_IRQHandler /* CPUSS DataWire #1, Channel #28 */ + .long cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ + .long cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ + .long cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ + .long cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ + .long cpuss_interrupts_cm4_fp_IRQHandler /* Floating Point operation fault */ + .long cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ + .long cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ + .long cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ + .long cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ + .long tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ + .long tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ + .long tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ + .long tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long tcpwm_0_interrupts_256_IRQHandler /* TCPWM #0, Counter #256 */ + .long tcpwm_0_interrupts_257_IRQHandler /* TCPWM #0, Counter #257 */ + .long tcpwm_0_interrupts_258_IRQHandler /* TCPWM #0, Counter #258 */ + .long tcpwm_0_interrupts_259_IRQHandler /* TCPWM #0, Counter #259 */ + .long tcpwm_0_interrupts_260_IRQHandler /* TCPWM #0, Counter #260 */ + .long tcpwm_0_interrupts_261_IRQHandler /* TCPWM #0, Counter #261 */ + .long tcpwm_0_interrupts_262_IRQHandler /* TCPWM #0, Counter #262 */ + .long tcpwm_0_interrupts_263_IRQHandler /* TCPWM #0, Counter #263 */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long pass_interrupt_dacs_IRQHandler /* Consolidated interrrupt for all DACs */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ + .long usb_interrupt_hi_IRQHandler /* USB Interrupt */ + .long usb_interrupt_med_IRQHandler /* USB Interrupt */ + .long usb_interrupt_lo_IRQHandler /* USB Interrupt */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long canfd_0_interrupt0_IRQHandler /* Can #0, Consolidated interrupt #0 */ + .long canfd_0_interrupts0_0_IRQHandler /* CAN #0, Interrupt #0, Channel #0 */ + .long canfd_0_interrupts1_0_IRQHandler /* CAN #0, Interrupt #1, Channel #0 */ + .long cpuss_interrupts_dw1_29_IRQHandler /* CPUSS DataWire #1, Channel #29 */ + .long cpuss_interrupts_dw1_30_IRQHandler /* CPUSS DataWire #1, Channel #30 */ + .long cpuss_interrupts_dw1_31_IRQHandler /* CPUSS DataWire #1, Channel #31 */ + .long cpuss_interrupts_dw0_29_IRQHandler /* CPUSS DataWire #0, Channel #29 */ + + + .size __Vectors, . - __Vectors + .equ __VectorsSize, . - __Vectors + + .section .ram_vectors + .align 2 + .globl __ramVectors +__ramVectors: + .space __VectorsSize + .size __ramVectors, . - __ramVectors + + + .text + .thumb + .thumb_func + .align 2 + + /* + * Device startup customization + * + * Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) + * because this function is executed as the first instruction in the ResetHandler. + * The PDL is also not initialized to use the proper register offsets. + * The user of this function is responsible for initializing the PDL and resources before using them. + */ + .weak Cy_OnResetUser + .func Cy_OnResetUser, Cy_OnResetUser + .type Cy_OnResetUser, %function + +Cy_OnResetUser: + bx lr + .size Cy_OnResetUser, . - Cy_OnResetUser + .endfunc + + /* Reset handler */ + .weak Reset_Handler + .type Reset_Handler, %function + +Reset_Handler: + bl Cy_OnResetUser + cpsid i + +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + ittt ge + ldrge r0, [r1, r3] + strge r0, [r2, r3] + bge .L_loop0_0 + + adds r4, #12 + b .L_loop0 + +.L_loop0_done: +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +.L_loop1: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .L_loop1 +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + itt ge + strge r0, [r1, r2] + bge .L_loop2_0 + + adds r3, #8 + b .L_loop2 +.L_loop2_done: +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.L_loop3: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .L_loop3 +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + + /* Update Vector Table Offset Register. */ + ldr r0, =__ramVectors + ldr r1, =CY_CPU_VTOR_ADDR + str r0, [r1] + dsb 0xF + + /* Enable the FPU if used */ + bl Cy_SystemInitFpuEnable + + bl _start + + /* Should never get here */ + b . + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak Default_Handler + .type Default_Handler, %function + +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + + + .weak Cy_SysLib_FaultHandler + .type Cy_SysLib_FaultHandler, %function + +Cy_SysLib_FaultHandler: + b . + .size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler + .type Fault_Handler, %function + +Fault_Handler: + /* Storing LR content for Creator call stack trace */ + push {LR} + movs r0, #4 + mov r1, LR + tst r0, r1 + beq .L_MSP + mrs r0, PSP + b .L_API_call +.L_MSP: + mrs r0, MSP +.L_API_call: + /* Compensation of stack pointer address due to pushing 4 bytes of LR */ + adds r0, r0, #4 + bl Cy_SysLib_FaultHandler + b . + .size Fault_Handler, . - Fault_Handler + +.macro def_fault_Handler fault_handler_name + .weak \fault_handler_name + .set \fault_handler_name, Fault_Handler + .endm + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + + def_fault_Handler HardFault_Handler + def_fault_Handler MemManage_Handler + def_fault_Handler BusFault_Handler + def_fault_Handler UsageFault_Handler + + def_irq_handler SVC_Handler + def_irq_handler DebugMon_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ + def_irq_handler ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ + def_irq_handler ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ + def_irq_handler ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ + def_irq_handler ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ + def_irq_handler ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ + def_irq_handler ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ + def_irq_handler ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ + def_irq_handler ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ + def_irq_handler ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ + def_irq_handler ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ + def_irq_handler ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ + def_irq_handler ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ + def_irq_handler ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ + def_irq_handler lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ + def_irq_handler scb_6_interrupt_IRQHandler /* Serial Communication Block #6 (DeepSleep capable) */ + def_irq_handler srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + def_irq_handler srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + def_irq_handler srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ + def_irq_handler srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + def_irq_handler cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ + def_irq_handler cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ + def_irq_handler cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ + def_irq_handler cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ + def_irq_handler cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ + def_irq_handler cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ + def_irq_handler cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ + def_irq_handler cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ + def_irq_handler cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ + def_irq_handler cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ + def_irq_handler cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ + def_irq_handler cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ + def_irq_handler cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ + def_irq_handler cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ + def_irq_handler cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ + def_irq_handler cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ + def_irq_handler pass_interrupt_sar_0_IRQHandler /* SAR ADC0 interrupt */ + def_irq_handler pass_interrupt_sar_1_IRQHandler /* SAR ADC1 interrupt */ + def_irq_handler pass_interrupt_ctb_IRQHandler /* individual interrupt per CTB */ + def_irq_handler pass_interrupt_fifo_0_IRQHandler /* PASS FIFO0 */ + def_irq_handler pass_interrupt_fifo_1_IRQHandler /* PASS FIFO1 */ + def_irq_handler scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ + def_irq_handler scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ + def_irq_handler scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ + def_irq_handler scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ + def_irq_handler scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ + def_irq_handler csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ + def_irq_handler cpuss_interrupts_dmac_0_IRQHandler /* CPUSS DMAC, Channel #0 */ + def_irq_handler cpuss_interrupts_dmac_1_IRQHandler /* CPUSS DMAC, Channel #1 */ + def_irq_handler cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ + def_irq_handler cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ + def_irq_handler cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ + def_irq_handler cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ + def_irq_handler cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ + def_irq_handler cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ + def_irq_handler cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ + def_irq_handler cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ + def_irq_handler cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ + def_irq_handler cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ + def_irq_handler cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ + def_irq_handler cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ + def_irq_handler cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ + def_irq_handler cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ + def_irq_handler cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ + def_irq_handler cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ + def_irq_handler cpuss_interrupts_dw0_16_IRQHandler /* CPUSS DataWire #0, Channel #16 */ + def_irq_handler cpuss_interrupts_dw0_17_IRQHandler /* CPUSS DataWire #0, Channel #17 */ + def_irq_handler cpuss_interrupts_dw0_18_IRQHandler /* CPUSS DataWire #0, Channel #18 */ + def_irq_handler cpuss_interrupts_dw0_19_IRQHandler /* CPUSS DataWire #0, Channel #19 */ + def_irq_handler cpuss_interrupts_dw0_20_IRQHandler /* CPUSS DataWire #0, Channel #20 */ + def_irq_handler cpuss_interrupts_dw0_21_IRQHandler /* CPUSS DataWire #0, Channel #21 */ + def_irq_handler cpuss_interrupts_dw0_22_IRQHandler /* CPUSS DataWire #0, Channel #22 */ + def_irq_handler cpuss_interrupts_dw0_23_IRQHandler /* CPUSS DataWire #0, Channel #23 */ + def_irq_handler cpuss_interrupts_dw0_24_IRQHandler /* CPUSS DataWire #0, Channel #24 */ + def_irq_handler cpuss_interrupts_dw0_25_IRQHandler /* CPUSS DataWire #0, Channel #25 */ + def_irq_handler cpuss_interrupts_dw0_26_IRQHandler /* CPUSS DataWire #0, Channel #26 */ + def_irq_handler cpuss_interrupts_dw0_27_IRQHandler /* CPUSS DataWire #0, Channel #27 */ + def_irq_handler cpuss_interrupts_dw0_28_IRQHandler /* CPUSS DataWire #0, Channel #28 */ + def_irq_handler cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ + def_irq_handler cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ + def_irq_handler cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ + def_irq_handler cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ + def_irq_handler cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ + def_irq_handler cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ + def_irq_handler cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ + def_irq_handler cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ + def_irq_handler cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ + def_irq_handler cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ + def_irq_handler cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ + def_irq_handler cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ + def_irq_handler cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ + def_irq_handler cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ + def_irq_handler cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ + def_irq_handler cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ + def_irq_handler cpuss_interrupts_dw1_16_IRQHandler /* CPUSS DataWire #1, Channel #16 */ + def_irq_handler cpuss_interrupts_dw1_17_IRQHandler /* CPUSS DataWire #1, Channel #17 */ + def_irq_handler cpuss_interrupts_dw1_18_IRQHandler /* CPUSS DataWire #1, Channel #18 */ + def_irq_handler cpuss_interrupts_dw1_19_IRQHandler /* CPUSS DataWire #1, Channel #19 */ + def_irq_handler cpuss_interrupts_dw1_20_IRQHandler /* CPUSS DataWire #1, Channel #20 */ + def_irq_handler cpuss_interrupts_dw1_21_IRQHandler /* CPUSS DataWire #1, Channel #21 */ + def_irq_handler cpuss_interrupts_dw1_22_IRQHandler /* CPUSS DataWire #1, Channel #22 */ + def_irq_handler cpuss_interrupts_dw1_23_IRQHandler /* CPUSS DataWire #1, Channel #23 */ + def_irq_handler cpuss_interrupts_dw1_24_IRQHandler /* CPUSS DataWire #1, Channel #24 */ + def_irq_handler cpuss_interrupts_dw1_25_IRQHandler /* CPUSS DataWire #1, Channel #25 */ + def_irq_handler cpuss_interrupts_dw1_26_IRQHandler /* CPUSS DataWire #1, Channel #26 */ + def_irq_handler cpuss_interrupts_dw1_27_IRQHandler /* CPUSS DataWire #1, Channel #27 */ + def_irq_handler cpuss_interrupts_dw1_28_IRQHandler /* CPUSS DataWire #1, Channel #28 */ + def_irq_handler cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ + def_irq_handler cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ + def_irq_handler cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ + def_irq_handler cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ + def_irq_handler cpuss_interrupts_cm4_fp_IRQHandler /* Floating Point operation fault */ + def_irq_handler cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ + def_irq_handler cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ + def_irq_handler cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ + def_irq_handler cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ + def_irq_handler tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ + def_irq_handler tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ + def_irq_handler tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ + def_irq_handler tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ + def_irq_handler tcpwm_0_interrupts_256_IRQHandler /* TCPWM #0, Counter #256 */ + def_irq_handler tcpwm_0_interrupts_257_IRQHandler /* TCPWM #0, Counter #257 */ + def_irq_handler tcpwm_0_interrupts_258_IRQHandler /* TCPWM #0, Counter #258 */ + def_irq_handler tcpwm_0_interrupts_259_IRQHandler /* TCPWM #0, Counter #259 */ + def_irq_handler tcpwm_0_interrupts_260_IRQHandler /* TCPWM #0, Counter #260 */ + def_irq_handler tcpwm_0_interrupts_261_IRQHandler /* TCPWM #0, Counter #261 */ + def_irq_handler tcpwm_0_interrupts_262_IRQHandler /* TCPWM #0, Counter #262 */ + def_irq_handler tcpwm_0_interrupts_263_IRQHandler /* TCPWM #0, Counter #263 */ + def_irq_handler pass_interrupt_dacs_IRQHandler /* Consolidated interrrupt for all DACs */ + def_irq_handler smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ + def_irq_handler usb_interrupt_hi_IRQHandler /* USB Interrupt */ + def_irq_handler usb_interrupt_med_IRQHandler /* USB Interrupt */ + def_irq_handler usb_interrupt_lo_IRQHandler /* USB Interrupt */ + def_irq_handler canfd_0_interrupt0_IRQHandler /* Can #0, Consolidated interrupt #0 */ + def_irq_handler canfd_0_interrupts0_0_IRQHandler /* CAN #0, Interrupt #0, Channel #0 */ + def_irq_handler canfd_0_interrupts1_0_IRQHandler /* CAN #0, Interrupt #1, Channel #0 */ + def_irq_handler cpuss_interrupts_dw1_29_IRQHandler /* CPUSS DataWire #1, Channel #29 */ + def_irq_handler cpuss_interrupts_dw1_30_IRQHandler /* CPUSS DataWire #1, Channel #30 */ + def_irq_handler cpuss_interrupts_dw1_31_IRQHandler /* CPUSS DataWire #1, Channel #31 */ + def_irq_handler cpuss_interrupts_dw0_29_IRQHandler /* CPUSS DataWire #0, Channel #29 */ + + .end + + +/* [] END OF FILE */ diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx4_cm4_dual.icf b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx4_cm4_dual.icf new file mode 100644 index 0000000..e8f7b14 --- /dev/null +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx4_cm4_dual.icf @@ -0,0 +1,290 @@ +/******************************************************************************* +* \file cy8c6xx4_cm4_dual.icf +* \version 2.70.1 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. + * More about CM0+ prebuilt images, see here: + * https://github.com/cypresssemiconductorco/psoc6cm0p + */ +/* The size of the Cortex-M0+ application image */ +define symbol FLASH_CM0P_SIZE = 0x2000; + +if (!isdefinedsymbol(MBED_ROM_START)) { + define symbol MBED_ROM_START = 0x10000000; +} + +/* MBED_APP_START is being used by the bootloader build script and + * will be calculate by the system. In case if MBED_APP_START address is + * customized by the bootloader config, the application image should not + * include CM0p prebuilt image. + */ +if (!isdefinedsymbol(MBED_APP_START)) { + define symbol MBED_APP_START = (MBED_ROM_START + FLASH_CM0P_SIZE); +} + +if (!isdefinedsymbol(MBED_ROM_SIZE)) { + define symbol MBED_ROM_SIZE = 0x00040000; +} + +/* MBED_APP_SIZE is being used by the bootloader build script and + * will be calculate by the system. + */ +if (!isdefinedsymbol(MBED_APP_SIZE)) { + define symbol MBED_APP_SIZE = (MBED_ROM_SIZE - FLASH_CM0P_SIZE); +} + +if (!isdefinedsymbol(MBED_RAM_START)) { + define symbol MBED_RAM_START = 0x08002000; +} + +if (!isdefinedsymbol(MBED_RAM_SIZE)) { + define symbol MBED_RAM_SIZE = 0x0001D800; +} + +if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { + + if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol MBED_BOOT_STACK_SIZE = 0x0400; + } else { + define symbol MBED_BOOT_STACK_SIZE = __STACK_SIZE; + } +} + +define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; +define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1); +/* Flash */ +define symbol __ICFEDIT_region_IROM0_start__ = MBED_ROM_START; +define symbol __ICFEDIT_region_IROM0_end__ = (MBED_ROM_START + FLASH_CM0P_SIZE - 1); + +define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; +define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 1); + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x160007FF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/*-Sizes-*/ +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region IROM0_region = mem:[from __ICFEDIT_region_IROM0_start__ to __ICFEDIT_region_IROM0_end__]; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; + +define block RAM_DATA {readwrite section .data}; +define block RAM_OTHER {readwrite section * }; +define block RAM_NOINIT {readwrite section .noinit}; +define block RAM_BSS {readwrite section .bss}; +define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NOINIT, block RAM_BSS}; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; + +define block CM0P_RO with size = FLASH_CM0P_SIZE { readonly section .cy_m0p_image }; +define block RO {first section .intvec, readonly}; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M0+ application image */ +place at start of IROM0_region { block CM0P_RO }; + +/* Flash - Cortex-M4 application */ +place at start of IROM1_region { block RO }; + +/* Used for the digital signature of the secure application and the Bootloader SDK application. */ +".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +".cy_xip" : place at start of EROM1_region { section .cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { block RAM}; +place in IRAM1_region { block HEAP}; +place at end of IRAM1_region { block CSTACK }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_m0p_image, + section .cy_app_signature, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00040000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx5_cm4_dual.icf b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx5_cm4_dual.icf index 07f3242..f6e8888 100644 --- a/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx5_cm4_dual.icf +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx5_cm4_dual.icf @@ -1,6 +1,6 @@ -/***************************************************************************//** +/******************************************************************************* * \file cy8c6xx5_cm4_dual.icf -* \version 2.70 +* \version 2.70.1 * * Linker file for the IAR compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -41,6 +41,10 @@ /*-Specials-*/ define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. + * More about CM0+ prebuilt images, see here: + * https://github.com/cypresssemiconductorco/psoc6cm0p + */ /* The size of the Cortex-M0+ application image */ define symbol FLASH_CM0P_SIZE = 0x2000; @@ -100,13 +104,13 @@ define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; */ /* RAM */ define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; -define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE); +define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1); /* Flash */ define symbol __ICFEDIT_region_IROM0_start__ = MBED_ROM_START; -define symbol __ICFEDIT_region_IROM0_end__ = (MBED_ROM_START + FLASH_CM0P_SIZE); +define symbol __ICFEDIT_region_IROM0_end__ = (MBED_ROM_START + FLASH_CM0P_SIZE - 1); define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; -define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE); +define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 1); /* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx6_cm4_dual.icf b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx6_cm4_dual.icf index bd1a118..fe4cdae 100644 --- a/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx6_cm4_dual.icf +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx6_cm4_dual.icf @@ -1,6 +1,6 @@ -/***************************************************************************//** +/******************************************************************************* * \file cy8c6xx6_cm4_dual.icf -* \version 2.70 +* \version 2.70.1 * * Linker file for the IAR compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -41,6 +41,10 @@ /*-Specials-*/ define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. + * More about CM0+ prebuilt images, see here: + * https://github.com/cypresssemiconductorco/psoc6cm0p + */ /* The size of the Cortex-M0+ application image */ define symbol FLASH_CM0P_SIZE = 0x2000; @@ -100,13 +104,13 @@ define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; */ /* RAM */ define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; -define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE); +define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1); /* Flash */ define symbol __ICFEDIT_region_IROM0_start__ = MBED_ROM_START; -define symbol __ICFEDIT_region_IROM0_end__ = (MBED_ROM_START + FLASH_CM0P_SIZE); +define symbol __ICFEDIT_region_IROM0_end__ = (MBED_ROM_START + FLASH_CM0P_SIZE - 1); define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; -define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE); +define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 1); /* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf index b405a8b..51808a1 100644 --- a/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf @@ -1,6 +1,6 @@ -/***************************************************************************//** +/******************************************************************************* * \file cy8c6xx7_cm4_dual.icf -* \version 2.70 +* \version 2.70.1 * * Linker file for the IAR compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -41,6 +41,10 @@ /*-Specials-*/ define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. + * More about CM0+ prebuilt images, see here: + * https://github.com/cypresssemiconductorco/psoc6cm0p + */ /* The size of the Cortex-M0+ application image */ define symbol FLASH_CM0P_SIZE = 0x2000; @@ -100,13 +104,13 @@ define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; */ /* RAM */ define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; -define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE); +define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1); /* Flash */ define symbol __ICFEDIT_region_IROM0_start__ = MBED_ROM_START; -define symbol __ICFEDIT_region_IROM0_end__ = (MBED_ROM_START + FLASH_CM0P_SIZE); +define symbol __ICFEDIT_region_IROM0_end__ = (MBED_ROM_START + FLASH_CM0P_SIZE - 1); define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; -define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE); +define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 1); /* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx8_cm4_dual.icf b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx8_cm4_dual.icf index dfb32a4..e8347dd 100644 --- a/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx8_cm4_dual.icf +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx8_cm4_dual.icf @@ -1,6 +1,6 @@ -/***************************************************************************//** +/******************************************************************************* * \file cy8c6xx8_cm4_dual.icf -* \version 2.70 +* \version 2.70.1 * * Linker file for the IAR compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -41,6 +41,10 @@ /*-Specials-*/ define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. + * More about CM0+ prebuilt images, see here: + * https://github.com/cypresssemiconductorco/psoc6cm0p + */ /* The size of the Cortex-M0+ application image */ define symbol FLASH_CM0P_SIZE = 0x2000; @@ -100,13 +104,13 @@ define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; */ /* RAM */ define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; -define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE); +define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1); /* Flash */ define symbol __ICFEDIT_region_IROM0_start__ = MBED_ROM_START; -define symbol __ICFEDIT_region_IROM0_end__ = (MBED_ROM_START + FLASH_CM0P_SIZE); +define symbol __ICFEDIT_region_IROM0_end__ = (MBED_ROM_START + FLASH_CM0P_SIZE - 1); define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; -define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE); +define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 1); /* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf index 3080c25..dfb3fe3 100644 --- a/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf @@ -1,6 +1,6 @@ -/***************************************************************************//** +/******************************************************************************* * \file cy8c6xxa_cm4_dual.icf -* \version 2.70 +* \version 2.70.1 * * Linker file for the IAR compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -41,6 +41,10 @@ /*-Specials-*/ define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. + * More about CM0+ prebuilt images, see here: + * https://github.com/cypresssemiconductorco/psoc6cm0p + */ /* The size of the Cortex-M0+ application image */ define symbol FLASH_CM0P_SIZE = 0x2000; @@ -100,13 +104,13 @@ define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; */ /* RAM */ define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; -define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE); +define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1); /* Flash */ define symbol __ICFEDIT_region_IROM0_start__ = MBED_ROM_START; -define symbol __ICFEDIT_region_IROM0_end__ = (MBED_ROM_START + FLASH_CM0P_SIZE); +define symbol __ICFEDIT_region_IROM0_end__ = (MBED_ROM_START + FLASH_CM0P_SIZE - 1); define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; -define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE); +define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 1); /* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx5_cm4.icf b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx5_cm4.icf index b1e1283..e33ccd4 100644 --- a/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx5_cm4.icf +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx5_cm4.icf @@ -1,6 +1,6 @@ -/***************************************************************************//** +/******************************************************************************* * \file cyb06xx5_cm4.icf -* \version 2.70 +* \version 2.70.1 * * Linker file for the IAR compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -85,10 +85,10 @@ if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { */ /* RAM */ define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; -define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE); +define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1); /* Flash */ define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; -define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE); +define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 1); /* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx7_cm4.icf b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx7_cm4.icf index 076a8ff..42a971c 100644 --- a/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx7_cm4.icf +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx7_cm4.icf @@ -1,6 +1,6 @@ -/***************************************************************************//** +/******************************************************************************* * \file cyb06xx7_cm4.icf -* \version 2.70 +* \version 2.70.1 * * Linker file for the IAR compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -85,10 +85,10 @@ if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { */ /* RAM */ define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; -define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE); +define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1); /* Flash */ define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; -define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE); +define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 1); /* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xxa_cm4.icf b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xxa_cm4.icf index 22ac13a..397826c 100644 --- a/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xxa_cm4.icf +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xxa_cm4.icf @@ -1,6 +1,6 @@ -/***************************************************************************//** +/******************************************************************************* * \file cyb06xxa_cm4.icf -* \version 2.70 +* \version 2.70.1 * * Linker file for the IAR compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -85,10 +85,10 @@ if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { */ /* RAM */ define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; -define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE); +define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1); /* Flash */ define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; -define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE); +define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 1); /* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_04_cm4.S b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_04_cm4.S new file mode 100644 index 0000000..82a6c57 --- /dev/null +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_04_cm4.S @@ -0,0 +1,1130 @@ +;/**************************************************************************//** +; * @file startup_psoc6_04_cm4.S +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device Series +; * @version V5.00 +; * @date 08. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + SECTION .intvec_ram:DATA:NOROOT(2) + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + EXTERN Cy_SystemInitFpuEnable + EXTERN __iar_data_init3 + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + PUBLIC __ramVectors + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD 0x0000000D ; NMI_Handler is defined in ROM code + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External interrupts Description + DCD ioss_interrupts_gpio_0_IRQHandler ; GPIO Port Interrupt #0 + DCD 0 ; Reserved + DCD ioss_interrupts_gpio_2_IRQHandler ; GPIO Port Interrupt #2 + DCD ioss_interrupts_gpio_3_IRQHandler ; GPIO Port Interrupt #3 + DCD 0 ; Reserved + DCD ioss_interrupts_gpio_5_IRQHandler ; GPIO Port Interrupt #5 + DCD ioss_interrupts_gpio_6_IRQHandler ; GPIO Port Interrupt #6 + DCD ioss_interrupts_gpio_7_IRQHandler ; GPIO Port Interrupt #7 + DCD ioss_interrupts_gpio_8_IRQHandler ; GPIO Port Interrupt #8 + DCD ioss_interrupts_gpio_9_IRQHandler ; GPIO Port Interrupt #9 + DCD ioss_interrupts_gpio_10_IRQHandler ; GPIO Port Interrupt #10 + DCD ioss_interrupts_gpio_11_IRQHandler ; GPIO Port Interrupt #11 + DCD ioss_interrupts_gpio_12_IRQHandler ; GPIO Port Interrupt #12 + DCD 0 ; Reserved + DCD ioss_interrupts_gpio_14_IRQHandler ; GPIO Port Interrupt #14 + DCD ioss_interrupt_gpio_IRQHandler ; GPIO All Ports + DCD ioss_interrupt_vdd_IRQHandler ; GPIO Supply Detect Interrupt + DCD lpcomp_interrupt_IRQHandler ; Low Power Comparator Interrupt + DCD scb_6_interrupt_IRQHandler ; Serial Communication Block #6 (DeepSleep capable) + DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt + DCD srss_interrupt_IRQHandler ; Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) + DCD cpuss_interrupts_ipc_0_IRQHandler ; CPUSS Inter Process Communication Interrupt #0 + DCD cpuss_interrupts_ipc_1_IRQHandler ; CPUSS Inter Process Communication Interrupt #1 + DCD cpuss_interrupts_ipc_2_IRQHandler ; CPUSS Inter Process Communication Interrupt #2 + DCD cpuss_interrupts_ipc_3_IRQHandler ; CPUSS Inter Process Communication Interrupt #3 + DCD cpuss_interrupts_ipc_4_IRQHandler ; CPUSS Inter Process Communication Interrupt #4 + DCD cpuss_interrupts_ipc_5_IRQHandler ; CPUSS Inter Process Communication Interrupt #5 + DCD cpuss_interrupts_ipc_6_IRQHandler ; CPUSS Inter Process Communication Interrupt #6 + DCD cpuss_interrupts_ipc_7_IRQHandler ; CPUSS Inter Process Communication Interrupt #7 + DCD cpuss_interrupts_ipc_8_IRQHandler ; CPUSS Inter Process Communication Interrupt #8 + DCD cpuss_interrupts_ipc_9_IRQHandler ; CPUSS Inter Process Communication Interrupt #9 + DCD cpuss_interrupts_ipc_10_IRQHandler ; CPUSS Inter Process Communication Interrupt #10 + DCD cpuss_interrupts_ipc_11_IRQHandler ; CPUSS Inter Process Communication Interrupt #11 + DCD cpuss_interrupts_ipc_12_IRQHandler ; CPUSS Inter Process Communication Interrupt #12 + DCD cpuss_interrupts_ipc_13_IRQHandler ; CPUSS Inter Process Communication Interrupt #13 + DCD cpuss_interrupts_ipc_14_IRQHandler ; CPUSS Inter Process Communication Interrupt #14 + DCD cpuss_interrupts_ipc_15_IRQHandler ; CPUSS Inter Process Communication Interrupt #15 + DCD pass_interrupt_sar_0_IRQHandler ; SAR ADC0 interrupt + DCD pass_interrupt_sar_1_IRQHandler ; SAR ADC1 interrupt + DCD pass_interrupt_ctb_IRQHandler ; individual interrupt per CTB + DCD 0 ; Reserved + DCD pass_interrupt_fifo_0_IRQHandler ; PASS FIFO0 + DCD pass_interrupt_fifo_1_IRQHandler ; PASS FIFO1 + DCD scb_0_interrupt_IRQHandler ; Serial Communication Block #0 + DCD scb_1_interrupt_IRQHandler ; Serial Communication Block #1 + DCD scb_2_interrupt_IRQHandler ; Serial Communication Block #2 + DCD 0 ; Reserved + DCD scb_4_interrupt_IRQHandler ; Serial Communication Block #4 + DCD scb_5_interrupt_IRQHandler ; Serial Communication Block #5 + DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt + DCD cpuss_interrupts_dmac_0_IRQHandler ; CPUSS DMAC, Channel #0 + DCD cpuss_interrupts_dmac_1_IRQHandler ; CPUSS DMAC, Channel #1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD cpuss_interrupts_dw0_0_IRQHandler ; CPUSS DataWire #0, Channel #0 + DCD cpuss_interrupts_dw0_1_IRQHandler ; CPUSS DataWire #0, Channel #1 + DCD cpuss_interrupts_dw0_2_IRQHandler ; CPUSS DataWire #0, Channel #2 + DCD cpuss_interrupts_dw0_3_IRQHandler ; CPUSS DataWire #0, Channel #3 + DCD cpuss_interrupts_dw0_4_IRQHandler ; CPUSS DataWire #0, Channel #4 + DCD cpuss_interrupts_dw0_5_IRQHandler ; CPUSS DataWire #0, Channel #5 + DCD cpuss_interrupts_dw0_6_IRQHandler ; CPUSS DataWire #0, Channel #6 + DCD cpuss_interrupts_dw0_7_IRQHandler ; CPUSS DataWire #0, Channel #7 + DCD cpuss_interrupts_dw0_8_IRQHandler ; CPUSS DataWire #0, Channel #8 + DCD cpuss_interrupts_dw0_9_IRQHandler ; CPUSS DataWire #0, Channel #9 + DCD cpuss_interrupts_dw0_10_IRQHandler ; CPUSS DataWire #0, Channel #10 + DCD cpuss_interrupts_dw0_11_IRQHandler ; CPUSS DataWire #0, Channel #11 + DCD cpuss_interrupts_dw0_12_IRQHandler ; CPUSS DataWire #0, Channel #12 + DCD cpuss_interrupts_dw0_13_IRQHandler ; CPUSS DataWire #0, Channel #13 + DCD cpuss_interrupts_dw0_14_IRQHandler ; CPUSS DataWire #0, Channel #14 + DCD cpuss_interrupts_dw0_15_IRQHandler ; CPUSS DataWire #0, Channel #15 + DCD cpuss_interrupts_dw0_16_IRQHandler ; CPUSS DataWire #0, Channel #16 + DCD cpuss_interrupts_dw0_17_IRQHandler ; CPUSS DataWire #0, Channel #17 + DCD cpuss_interrupts_dw0_18_IRQHandler ; CPUSS DataWire #0, Channel #18 + DCD cpuss_interrupts_dw0_19_IRQHandler ; CPUSS DataWire #0, Channel #19 + DCD cpuss_interrupts_dw0_20_IRQHandler ; CPUSS DataWire #0, Channel #20 + DCD cpuss_interrupts_dw0_21_IRQHandler ; CPUSS DataWire #0, Channel #21 + DCD cpuss_interrupts_dw0_22_IRQHandler ; CPUSS DataWire #0, Channel #22 + DCD cpuss_interrupts_dw0_23_IRQHandler ; CPUSS DataWire #0, Channel #23 + DCD cpuss_interrupts_dw0_24_IRQHandler ; CPUSS DataWire #0, Channel #24 + DCD cpuss_interrupts_dw0_25_IRQHandler ; CPUSS DataWire #0, Channel #25 + DCD cpuss_interrupts_dw0_26_IRQHandler ; CPUSS DataWire #0, Channel #26 + DCD cpuss_interrupts_dw0_27_IRQHandler ; CPUSS DataWire #0, Channel #27 + DCD cpuss_interrupts_dw0_28_IRQHandler ; CPUSS DataWire #0, Channel #28 + DCD cpuss_interrupts_dw1_0_IRQHandler ; CPUSS DataWire #1, Channel #0 + DCD cpuss_interrupts_dw1_1_IRQHandler ; CPUSS DataWire #1, Channel #1 + DCD cpuss_interrupts_dw1_2_IRQHandler ; CPUSS DataWire #1, Channel #2 + DCD cpuss_interrupts_dw1_3_IRQHandler ; CPUSS DataWire #1, Channel #3 + DCD cpuss_interrupts_dw1_4_IRQHandler ; CPUSS DataWire #1, Channel #4 + DCD cpuss_interrupts_dw1_5_IRQHandler ; CPUSS DataWire #1, Channel #5 + DCD cpuss_interrupts_dw1_6_IRQHandler ; CPUSS DataWire #1, Channel #6 + DCD cpuss_interrupts_dw1_7_IRQHandler ; CPUSS DataWire #1, Channel #7 + DCD cpuss_interrupts_dw1_8_IRQHandler ; CPUSS DataWire #1, Channel #8 + DCD cpuss_interrupts_dw1_9_IRQHandler ; CPUSS DataWire #1, Channel #9 + DCD cpuss_interrupts_dw1_10_IRQHandler ; CPUSS DataWire #1, Channel #10 + DCD cpuss_interrupts_dw1_11_IRQHandler ; CPUSS DataWire #1, Channel #11 + DCD cpuss_interrupts_dw1_12_IRQHandler ; CPUSS DataWire #1, Channel #12 + DCD cpuss_interrupts_dw1_13_IRQHandler ; CPUSS DataWire #1, Channel #13 + DCD cpuss_interrupts_dw1_14_IRQHandler ; CPUSS DataWire #1, Channel #14 + DCD cpuss_interrupts_dw1_15_IRQHandler ; CPUSS DataWire #1, Channel #15 + DCD cpuss_interrupts_dw1_16_IRQHandler ; CPUSS DataWire #1, Channel #16 + DCD cpuss_interrupts_dw1_17_IRQHandler ; CPUSS DataWire #1, Channel #17 + DCD cpuss_interrupts_dw1_18_IRQHandler ; CPUSS DataWire #1, Channel #18 + DCD cpuss_interrupts_dw1_19_IRQHandler ; CPUSS DataWire #1, Channel #19 + DCD cpuss_interrupts_dw1_20_IRQHandler ; CPUSS DataWire #1, Channel #20 + DCD cpuss_interrupts_dw1_21_IRQHandler ; CPUSS DataWire #1, Channel #21 + DCD cpuss_interrupts_dw1_22_IRQHandler ; CPUSS DataWire #1, Channel #22 + DCD cpuss_interrupts_dw1_23_IRQHandler ; CPUSS DataWire #1, Channel #23 + DCD cpuss_interrupts_dw1_24_IRQHandler ; CPUSS DataWire #1, Channel #24 + DCD cpuss_interrupts_dw1_25_IRQHandler ; CPUSS DataWire #1, Channel #25 + DCD cpuss_interrupts_dw1_26_IRQHandler ; CPUSS DataWire #1, Channel #26 + DCD cpuss_interrupts_dw1_27_IRQHandler ; CPUSS DataWire #1, Channel #27 + DCD cpuss_interrupts_dw1_28_IRQHandler ; CPUSS DataWire #1, Channel #28 + DCD cpuss_interrupts_fault_0_IRQHandler ; CPUSS Fault Structure Interrupt #0 + DCD cpuss_interrupts_fault_1_IRQHandler ; CPUSS Fault Structure Interrupt #1 + DCD cpuss_interrupt_crypto_IRQHandler ; CRYPTO Accelerator Interrupt + DCD cpuss_interrupt_fm_IRQHandler ; FLASH Macro Interrupt + DCD cpuss_interrupts_cm4_fp_IRQHandler ; Floating Point operation fault + DCD cpuss_interrupts_cm0_cti_0_IRQHandler ; CM0+ CTI #0 + DCD cpuss_interrupts_cm0_cti_1_IRQHandler ; CM0+ CTI #1 + DCD cpuss_interrupts_cm4_cti_0_IRQHandler ; CM4 CTI #0 + DCD cpuss_interrupts_cm4_cti_1_IRQHandler ; CM4 CTI #1 + DCD tcpwm_0_interrupts_0_IRQHandler ; TCPWM #0, Counter #0 + DCD tcpwm_0_interrupts_1_IRQHandler ; TCPWM #0, Counter #1 + DCD tcpwm_0_interrupts_2_IRQHandler ; TCPWM #0, Counter #2 + DCD tcpwm_0_interrupts_3_IRQHandler ; TCPWM #0, Counter #3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD tcpwm_0_interrupts_256_IRQHandler ; TCPWM #0, Counter #256 + DCD tcpwm_0_interrupts_257_IRQHandler ; TCPWM #0, Counter #257 + DCD tcpwm_0_interrupts_258_IRQHandler ; TCPWM #0, Counter #258 + DCD tcpwm_0_interrupts_259_IRQHandler ; TCPWM #0, Counter #259 + DCD tcpwm_0_interrupts_260_IRQHandler ; TCPWM #0, Counter #260 + DCD tcpwm_0_interrupts_261_IRQHandler ; TCPWM #0, Counter #261 + DCD tcpwm_0_interrupts_262_IRQHandler ; TCPWM #0, Counter #262 + DCD tcpwm_0_interrupts_263_IRQHandler ; TCPWM #0, Counter #263 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD pass_interrupt_dacs_IRQHandler ; Consolidated interrrupt for all DACs + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt + DCD usb_interrupt_hi_IRQHandler ; USB Interrupt + DCD usb_interrupt_med_IRQHandler ; USB Interrupt + DCD usb_interrupt_lo_IRQHandler ; USB Interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD canfd_0_interrupt0_IRQHandler ; Can #0, Consolidated interrupt #0 + DCD canfd_0_interrupts0_0_IRQHandler ; CAN #0, Interrupt #0, Channel #0 + DCD canfd_0_interrupts1_0_IRQHandler ; CAN #0, Interrupt #1, Channel #0 + DCD cpuss_interrupts_dw1_29_IRQHandler ; CPUSS DataWire #1, Channel #29 + DCD cpuss_interrupts_dw1_30_IRQHandler ; CPUSS DataWire #1, Channel #30 + DCD cpuss_interrupts_dw1_31_IRQHandler ; CPUSS DataWire #1, Channel #31 + DCD cpuss_interrupts_dw0_29_IRQHandler ; CPUSS DataWire #0, Channel #29 + +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + SECTION .intvec_ram:DATA:REORDER:NOROOT(2) +__ramVectors + DS32 __Vectors_Size + + + THUMB + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default handlers +;; + PUBWEAK Default_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Default_Handler + B Default_Handler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Weak function for startup customization +;; +;; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +;; because this function is executed as the first instruction in the ResetHandler. +;; The PDL is also not initialized to use the proper register offsets. +;; The user of this function is responsible for initializing the PDL and resources before using them. +;; + PUBWEAK Cy_OnResetUser + SECTION .text:CODE:REORDER:NOROOT(2) +Cy_OnResetUser + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Define strong version to return zero for +;; __iar_program_start to skip data sections +;; initialization. +;; + PUBLIC __low_level_init + SECTION .text:CODE:REORDER:NOROOT(2) +__low_level_init + MOVS R0, #0 + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + ; Define strong function for startup customization + LDR R0, =Cy_OnResetUser + BLX R0 + + ; Disable global interrupts + CPSID I + + ; Copy vectors from ROM to RAM + LDR r1, =__vector_table + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +intvec_copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE intvec_copy + + ; Update Vector Table Offset Register + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb + + ; Initialize data sections + LDR R0, =__iar_data_init3 + BLX R0 + + LDR R0, =SystemInit + BLX R0 + + LDR R0, =__iar_program_start + BLX R0 + +; Should never get here +Cy_Main_Exited + B Cy_Main_Exited + + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK Cy_SysLib_FaultHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Cy_SysLib_FaultHandler + B Cy_SysLib_FaultHandler + + PUBWEAK HardFault_Wrapper + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Wrapper + IMPORT Cy_SysLib_FaultHandler + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + b L_API_call +L_MSP + mrs r0, MSP +L_API_call + ; Storing LR content for Creator call stack trace + push {LR} + bl Cy_SysLib_FaultHandler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Wrapper + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B HardFault_Wrapper + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B HardFault_Wrapper + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B HardFault_Wrapper + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + + ; External interrupts + PUBWEAK ioss_interrupts_gpio_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_0_IRQHandler + B ioss_interrupts_gpio_0_IRQHandler + + PUBWEAK ioss_interrupts_gpio_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_2_IRQHandler + B ioss_interrupts_gpio_2_IRQHandler + + PUBWEAK ioss_interrupts_gpio_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_3_IRQHandler + B ioss_interrupts_gpio_3_IRQHandler + + PUBWEAK ioss_interrupts_gpio_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_5_IRQHandler + B ioss_interrupts_gpio_5_IRQHandler + + PUBWEAK ioss_interrupts_gpio_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_6_IRQHandler + B ioss_interrupts_gpio_6_IRQHandler + + PUBWEAK ioss_interrupts_gpio_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_7_IRQHandler + B ioss_interrupts_gpio_7_IRQHandler + + PUBWEAK ioss_interrupts_gpio_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_8_IRQHandler + B ioss_interrupts_gpio_8_IRQHandler + + PUBWEAK ioss_interrupts_gpio_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_9_IRQHandler + B ioss_interrupts_gpio_9_IRQHandler + + PUBWEAK ioss_interrupts_gpio_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_10_IRQHandler + B ioss_interrupts_gpio_10_IRQHandler + + PUBWEAK ioss_interrupts_gpio_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_11_IRQHandler + B ioss_interrupts_gpio_11_IRQHandler + + PUBWEAK ioss_interrupts_gpio_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_12_IRQHandler + B ioss_interrupts_gpio_12_IRQHandler + + PUBWEAK ioss_interrupts_gpio_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_14_IRQHandler + B ioss_interrupts_gpio_14_IRQHandler + + PUBWEAK ioss_interrupt_gpio_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupt_gpio_IRQHandler + B ioss_interrupt_gpio_IRQHandler + + PUBWEAK ioss_interrupt_vdd_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupt_vdd_IRQHandler + B ioss_interrupt_vdd_IRQHandler + + PUBWEAK lpcomp_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +lpcomp_interrupt_IRQHandler + B lpcomp_interrupt_IRQHandler + + PUBWEAK scb_6_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_6_interrupt_IRQHandler + B scb_6_interrupt_IRQHandler + + PUBWEAK srss_interrupt_mcwdt_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_mcwdt_0_IRQHandler + B srss_interrupt_mcwdt_0_IRQHandler + + PUBWEAK srss_interrupt_mcwdt_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_mcwdt_1_IRQHandler + B srss_interrupt_mcwdt_1_IRQHandler + + PUBWEAK srss_interrupt_backup_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_backup_IRQHandler + B srss_interrupt_backup_IRQHandler + + PUBWEAK srss_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_IRQHandler + B srss_interrupt_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_0_IRQHandler + B cpuss_interrupts_ipc_0_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_1_IRQHandler + B cpuss_interrupts_ipc_1_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_2_IRQHandler + B cpuss_interrupts_ipc_2_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_3_IRQHandler + B cpuss_interrupts_ipc_3_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_4_IRQHandler + B cpuss_interrupts_ipc_4_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_5_IRQHandler + B cpuss_interrupts_ipc_5_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_6_IRQHandler + B cpuss_interrupts_ipc_6_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_7_IRQHandler + B cpuss_interrupts_ipc_7_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_8_IRQHandler + B cpuss_interrupts_ipc_8_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_9_IRQHandler + B cpuss_interrupts_ipc_9_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_10_IRQHandler + B cpuss_interrupts_ipc_10_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_11_IRQHandler + B cpuss_interrupts_ipc_11_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_12_IRQHandler + B cpuss_interrupts_ipc_12_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_13_IRQHandler + B cpuss_interrupts_ipc_13_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_14_IRQHandler + B cpuss_interrupts_ipc_14_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_15_IRQHandler + B cpuss_interrupts_ipc_15_IRQHandler + + PUBWEAK pass_interrupt_sar_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +pass_interrupt_sar_0_IRQHandler + B pass_interrupt_sar_0_IRQHandler + + PUBWEAK pass_interrupt_sar_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +pass_interrupt_sar_1_IRQHandler + B pass_interrupt_sar_1_IRQHandler + + PUBWEAK pass_interrupt_ctb_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +pass_interrupt_ctb_IRQHandler + B pass_interrupt_ctb_IRQHandler + + PUBWEAK pass_interrupt_fifo_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +pass_interrupt_fifo_0_IRQHandler + B pass_interrupt_fifo_0_IRQHandler + + PUBWEAK pass_interrupt_fifo_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +pass_interrupt_fifo_1_IRQHandler + B pass_interrupt_fifo_1_IRQHandler + + PUBWEAK scb_0_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_0_interrupt_IRQHandler + B scb_0_interrupt_IRQHandler + + PUBWEAK scb_1_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_1_interrupt_IRQHandler + B scb_1_interrupt_IRQHandler + + PUBWEAK scb_2_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_2_interrupt_IRQHandler + B scb_2_interrupt_IRQHandler + + PUBWEAK scb_4_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_4_interrupt_IRQHandler + B scb_4_interrupt_IRQHandler + + PUBWEAK scb_5_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_5_interrupt_IRQHandler + B scb_5_interrupt_IRQHandler + + PUBWEAK csd_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +csd_interrupt_IRQHandler + B csd_interrupt_IRQHandler + + PUBWEAK cpuss_interrupts_dmac_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dmac_0_IRQHandler + B cpuss_interrupts_dmac_0_IRQHandler + + PUBWEAK cpuss_interrupts_dmac_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dmac_1_IRQHandler + B cpuss_interrupts_dmac_1_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_0_IRQHandler + B cpuss_interrupts_dw0_0_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_1_IRQHandler + B cpuss_interrupts_dw0_1_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_2_IRQHandler + B cpuss_interrupts_dw0_2_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_3_IRQHandler + B cpuss_interrupts_dw0_3_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_4_IRQHandler + B cpuss_interrupts_dw0_4_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_5_IRQHandler + B cpuss_interrupts_dw0_5_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_6_IRQHandler + B cpuss_interrupts_dw0_6_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_7_IRQHandler + B cpuss_interrupts_dw0_7_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_8_IRQHandler + B cpuss_interrupts_dw0_8_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_9_IRQHandler + B cpuss_interrupts_dw0_9_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_10_IRQHandler + B cpuss_interrupts_dw0_10_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_11_IRQHandler + B cpuss_interrupts_dw0_11_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_12_IRQHandler + B cpuss_interrupts_dw0_12_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_13_IRQHandler + B cpuss_interrupts_dw0_13_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_14_IRQHandler + B cpuss_interrupts_dw0_14_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_15_IRQHandler + B cpuss_interrupts_dw0_15_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_16_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_16_IRQHandler + B cpuss_interrupts_dw0_16_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_17_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_17_IRQHandler + B cpuss_interrupts_dw0_17_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_18_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_18_IRQHandler + B cpuss_interrupts_dw0_18_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_19_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_19_IRQHandler + B cpuss_interrupts_dw0_19_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_20_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_20_IRQHandler + B cpuss_interrupts_dw0_20_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_21_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_21_IRQHandler + B cpuss_interrupts_dw0_21_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_22_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_22_IRQHandler + B cpuss_interrupts_dw0_22_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_23_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_23_IRQHandler + B cpuss_interrupts_dw0_23_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_24_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_24_IRQHandler + B cpuss_interrupts_dw0_24_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_25_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_25_IRQHandler + B cpuss_interrupts_dw0_25_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_26_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_26_IRQHandler + B cpuss_interrupts_dw0_26_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_27_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_27_IRQHandler + B cpuss_interrupts_dw0_27_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_28_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_28_IRQHandler + B cpuss_interrupts_dw0_28_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_0_IRQHandler + B cpuss_interrupts_dw1_0_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_1_IRQHandler + B cpuss_interrupts_dw1_1_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_2_IRQHandler + B cpuss_interrupts_dw1_2_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_3_IRQHandler + B cpuss_interrupts_dw1_3_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_4_IRQHandler + B cpuss_interrupts_dw1_4_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_5_IRQHandler + B cpuss_interrupts_dw1_5_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_6_IRQHandler + B cpuss_interrupts_dw1_6_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_7_IRQHandler + B cpuss_interrupts_dw1_7_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_8_IRQHandler + B cpuss_interrupts_dw1_8_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_9_IRQHandler + B cpuss_interrupts_dw1_9_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_10_IRQHandler + B cpuss_interrupts_dw1_10_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_11_IRQHandler + B cpuss_interrupts_dw1_11_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_12_IRQHandler + B cpuss_interrupts_dw1_12_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_13_IRQHandler + B cpuss_interrupts_dw1_13_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_14_IRQHandler + B cpuss_interrupts_dw1_14_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_15_IRQHandler + B cpuss_interrupts_dw1_15_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_16_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_16_IRQHandler + B cpuss_interrupts_dw1_16_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_17_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_17_IRQHandler + B cpuss_interrupts_dw1_17_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_18_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_18_IRQHandler + B cpuss_interrupts_dw1_18_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_19_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_19_IRQHandler + B cpuss_interrupts_dw1_19_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_20_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_20_IRQHandler + B cpuss_interrupts_dw1_20_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_21_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_21_IRQHandler + B cpuss_interrupts_dw1_21_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_22_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_22_IRQHandler + B cpuss_interrupts_dw1_22_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_23_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_23_IRQHandler + B cpuss_interrupts_dw1_23_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_24_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_24_IRQHandler + B cpuss_interrupts_dw1_24_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_25_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_25_IRQHandler + B cpuss_interrupts_dw1_25_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_26_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_26_IRQHandler + B cpuss_interrupts_dw1_26_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_27_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_27_IRQHandler + B cpuss_interrupts_dw1_27_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_28_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_28_IRQHandler + B cpuss_interrupts_dw1_28_IRQHandler + + PUBWEAK cpuss_interrupts_fault_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_fault_0_IRQHandler + B cpuss_interrupts_fault_0_IRQHandler + + PUBWEAK cpuss_interrupts_fault_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_fault_1_IRQHandler + B cpuss_interrupts_fault_1_IRQHandler + + PUBWEAK cpuss_interrupt_crypto_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupt_crypto_IRQHandler + B cpuss_interrupt_crypto_IRQHandler + + PUBWEAK cpuss_interrupt_fm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupt_fm_IRQHandler + B cpuss_interrupt_fm_IRQHandler + + PUBWEAK cpuss_interrupts_cm4_fp_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm4_fp_IRQHandler + B cpuss_interrupts_cm4_fp_IRQHandler + + PUBWEAK cpuss_interrupts_cm0_cti_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm0_cti_0_IRQHandler + B cpuss_interrupts_cm0_cti_0_IRQHandler + + PUBWEAK cpuss_interrupts_cm0_cti_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm0_cti_1_IRQHandler + B cpuss_interrupts_cm0_cti_1_IRQHandler + + PUBWEAK cpuss_interrupts_cm4_cti_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm4_cti_0_IRQHandler + B cpuss_interrupts_cm4_cti_0_IRQHandler + + PUBWEAK cpuss_interrupts_cm4_cti_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm4_cti_1_IRQHandler + B cpuss_interrupts_cm4_cti_1_IRQHandler + + PUBWEAK tcpwm_0_interrupts_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_0_IRQHandler + B tcpwm_0_interrupts_0_IRQHandler + + PUBWEAK tcpwm_0_interrupts_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_1_IRQHandler + B tcpwm_0_interrupts_1_IRQHandler + + PUBWEAK tcpwm_0_interrupts_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_2_IRQHandler + B tcpwm_0_interrupts_2_IRQHandler + + PUBWEAK tcpwm_0_interrupts_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_3_IRQHandler + B tcpwm_0_interrupts_3_IRQHandler + + PUBWEAK tcpwm_0_interrupts_256_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_256_IRQHandler + B tcpwm_0_interrupts_256_IRQHandler + + PUBWEAK tcpwm_0_interrupts_257_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_257_IRQHandler + B tcpwm_0_interrupts_257_IRQHandler + + PUBWEAK tcpwm_0_interrupts_258_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_258_IRQHandler + B tcpwm_0_interrupts_258_IRQHandler + + PUBWEAK tcpwm_0_interrupts_259_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_259_IRQHandler + B tcpwm_0_interrupts_259_IRQHandler + + PUBWEAK tcpwm_0_interrupts_260_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_260_IRQHandler + B tcpwm_0_interrupts_260_IRQHandler + + PUBWEAK tcpwm_0_interrupts_261_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_261_IRQHandler + B tcpwm_0_interrupts_261_IRQHandler + + PUBWEAK tcpwm_0_interrupts_262_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_262_IRQHandler + B tcpwm_0_interrupts_262_IRQHandler + + PUBWEAK tcpwm_0_interrupts_263_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_263_IRQHandler + B tcpwm_0_interrupts_263_IRQHandler + + PUBWEAK pass_interrupt_dacs_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +pass_interrupt_dacs_IRQHandler + B pass_interrupt_dacs_IRQHandler + + PUBWEAK smif_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +smif_interrupt_IRQHandler + B smif_interrupt_IRQHandler + + PUBWEAK usb_interrupt_hi_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +usb_interrupt_hi_IRQHandler + B usb_interrupt_hi_IRQHandler + + PUBWEAK usb_interrupt_med_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +usb_interrupt_med_IRQHandler + B usb_interrupt_med_IRQHandler + + PUBWEAK usb_interrupt_lo_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +usb_interrupt_lo_IRQHandler + B usb_interrupt_lo_IRQHandler + + PUBWEAK canfd_0_interrupt0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +canfd_0_interrupt0_IRQHandler + B canfd_0_interrupt0_IRQHandler + + PUBWEAK canfd_0_interrupts0_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +canfd_0_interrupts0_0_IRQHandler + B canfd_0_interrupts0_0_IRQHandler + + PUBWEAK canfd_0_interrupts1_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +canfd_0_interrupts1_0_IRQHandler + B canfd_0_interrupts1_0_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_29_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_29_IRQHandler + B cpuss_interrupts_dw1_29_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_30_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_30_IRQHandler + B cpuss_interrupts_dw1_30_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_31_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_31_IRQHandler + B cpuss_interrupts_dw1_31_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_29_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_29_IRQHandler + B cpuss_interrupts_dw0_29_IRQHandler + + + END + + +; [] END OF FILE diff --git a/devices/templates/COMPONENT_MBED/COMPONENT_CM4/system_psoc6_cm4.c b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/system_psoc6_cm4.c index 7800d6b..7e634e2 100644 --- a/devices/templates/COMPONENT_MBED/COMPONENT_CM4/system_psoc6_cm4.c +++ b/devices/templates/COMPONENT_MBED/COMPONENT_CM4/system_psoc6_cm4.c @@ -1,12 +1,12 @@ /***************************************************************************//** * \file system_psoc6_cm4.c -* \version 2.70 +* \version 2.70.1 * * The device system-source file. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/devices/templates/COMPONENT_MBED/system_psoc6.h b/devices/templates/COMPONENT_MBED/system_psoc6.h index 8dd97ff..0ad244b 100644 --- a/devices/templates/COMPONENT_MBED/system_psoc6.h +++ b/devices/templates/COMPONENT_MBED/system_psoc6.h @@ -1,12 +1,12 @@ /***************************************************************************//** * \file system_psoc6.h -* \version 2.70 +* \version 2.70.1 * * \brief Device system header file. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -36,7 +36,6 @@ * * \ref group_system_config_single_core_device_initialization * - \ref group_system_config_device_memory_definition * - \ref group_system_config_heap_stack_config -* - \ref group_system_config_merge_apps * - \ref group_system_config_default_handlers * - \ref group_system_config_device_vector_table * - \ref group_system_config_cm4_functions @@ -56,44 +55,58 @@ * warnings in your project, you can simply comment out or remove the relevant * code in the linker file. * +* \note For the PSoC 64 Secure MCUs devices, refer to the following page: +* https://www.cypress.com/documentation/software-and-drivers/psoc-64-secure-mcu-secure-boot-sdk-user-guide +* +* * ARM GCC\n * The flash and RAM sections for the CPU are defined in the linker files: * 'xx_yy.ld', where 'xx' is the device group, and 'yy' is the target CPU; for example, * 'cy8c6xx7_cm0plus.ld' and 'cy8c6xx7_cm4_dual.ld'. * \note If the start of the Cortex-M4 application image is changed, the value -* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The +* of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The * \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the * Cy_SysEnableCM4() function call. +* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p * * Change the flash and RAM sizes by editing the macros value in the * linker files for both CPUs: * - 'xx_cm0plus.ld', where 'xx' is the device group: * \code -* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x00080000 -* ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x00024000 +* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x2000 +* ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x2000 * \endcode * - 'xx_cm4_dual.ld', where 'xx' is the device group: * \code -* flash (rx) : ORIGIN = 0x10080000, LENGTH = 0x00080000 -* ram (rwx) : ORIGIN = 0x08024000, LENGTH = 0x00023800 +* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x100000 +* ram (rwx) : ORIGIN = 0x08002000, LENGTH = 0x45800 * \endcode * -* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the rom ORIGIN's -* value in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. Do this -* by either: +* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the ROM ORIGIN's +* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image +* of the Cortex-M0+ application should be the same value as the flash LENGTH in +* 'xx_cm0plus.ld') in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. +* Do this by either: * - Passing the following commands to the compiler:\n -* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode -* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where 'xx' is device family:\n -* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode +* or +* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where +* 'xx' is the device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode * -* ARM MDK\n +* ARM Compiler\n * The flash and RAM sections for the CPU are defined in the linker files: -* 'xx_yy.scat', where 'xx' is the device group, and 'yy' is the target CPU; for example, -* 'cy8c6xx7_cm0plus.scat' and 'cy8c6xx7_cm4_dual.scat'. +* 'xx_yy.sct', where 'xx' is the device group, and 'yy' is the target CPU; for +* example 'cy8c6xx7_cm0plus.sct' and 'cy8c6xx7_cm4_dual.sct'. * \note If the start of the Cortex-M4 application image is changed, the value * of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The * \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref * Cy_SysEnableCM4() function call. +* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p * * \note The linker files provided with the PDL are generic and handle all common * use cases. Your project may not use every section defined in the linker files. @@ -106,29 +119,32 @@ * * Change the flash and RAM sizes by editing the macros value in the * linker files for both CPUs: -* - 'xx_cm0plus.scat', where 'xx' is the device group: +* - 'xx_cm0plus.sct', where 'xx' is the device group: * \code * #define FLASH_START 0x10000000 -* #define FLASH_SIZE 0x00080000 +* #define FLASH_SIZE 0x00002000 * #define RAM_START 0x08000000 -* #define RAM_SIZE 0x00024000 +* #define RAM_SIZE 0x00002000 * \endcode -* - 'xx_cm4_dual.scat', where 'xx' is the device group: +* - 'xx_cm4_dual.sct', where 'xx' is the device group: * \code -* #define FLASH_START 0x10080000 -* #define FLASH_SIZE 0x00080000 -* #define RAM_START 0x08024000 -* #define RAM_SIZE 0x00023800 +* #define FLASH_START 0x10000000 +* #define FLASH_SIZE 0x00100000 +* #define RAM_START 0x08002000 +* #define RAM_SIZE 0x00045800 * \endcode * * Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the FLASH_START -* value in the 'xx_cm4_dual.scat' file, -* where 'xx' is the device group. Do this by either: +* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image +* of the Cortex-M0+ application should be the same value as the FLASH_SIZE in the +* 'xx_cm0plus.sct') in the 'xx_cm4_dual.sct' file, where 'xx' is the device group. +* Do this by either: * - Passing the following commands to the compiler:\n -* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode +* or * - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where -* 'xx' is device family:\n -* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode +* 'xx' is the device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode * * IAR\n * The flash and RAM sections for the CPU are defined in the linker files: @@ -138,32 +154,39 @@ * of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The * \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref * Cy_SysEnableCM4() function call. +* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p * * Change the flash and RAM sizes by editing the macros value in the * linker files for both CPUs: * - 'xx_cm0plus.icf', where 'xx' is the device group: * \code * define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; -* define symbol __ICFEDIT_region_IROM1_end__ = 0x10080000; +* define symbol __ICFEDIT_region_IROM1_end__ = 0x10001FFF; * define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; -* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08024000; +* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08001FFF; * \endcode * - 'xx_cm4_dual.icf', where 'xx' is the device group: * \code -* define symbol __ICFEDIT_region_IROM1_start__ = 0x10080000; -* define symbol __ICFEDIT_region_IROM1_end__ = 0x10100000; -* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08024000; -* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08047800; +* define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +* define symbol __ICFEDIT_region_IROM1_end__ = 0x100FFFFF; +* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000; +* define symbol __ICFEDIT_region_IRAM1_end__ = 0x080477FF; * \endcode * -* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the -* __ICFEDIT_region_IROM1_start__ value in the 'xx_cm4_dual.icf' file, where 'xx' -* is the device group. Do this by either: +* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the +* __ICFEDIT_region_IROM1_start__ value (0x10000000) + FLASH_CM0P_SIZE value +* (0x2000, the size of a flash image of the Cortex-M0+ application) in the +* 'xx_cm4_dual.icf' file, where 'xx' is the device group. The sum result +* should be the same as (__ICFEDIT_region_IROM1_end__ + 1) value in the +* 'xx_cm0plus.icf'. Do this by either: * - Passing the following commands to the compiler:\n -* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode +* or * - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where -* 'xx' is device family:\n -* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode +* 'xx' is the device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode * * \subsection group_system_config_device_initialization Device Initialization * After a power-on-reset (POR), the boot process is handled by the boot code @@ -189,7 +212,9 @@ * -# Editing source code files * -# Specifying via command line * -* By default, the stack size is set to 0x00001000 and the heap size is set to 0x00000400. +* By default, the stack size is set to 0x00001000 and the heap size is allocated +* dynamically to the whole available free memory up to stack memory and it +* is set to the 0x00000400 (for ARM GCC and IAR compilers) as minimal value. * * \subsubsection group_system_config_heap_stack_config_gcc ARM GCC * - Editing source code files\n @@ -198,28 +223,23 @@ * Change the heap and stack sizes by modifying the following lines:\n * \code .equ Stack_Size, 0x00001000 \endcode * \code .equ Heap_Size, 0x00000400 \endcode +* Also, the stack size is defined in the linker script files: 'xx_yy.ld', +* where 'xx' is the device family, and 'yy' is the target CPU; for example, +* cy8c6xx7_cm0plus.ld and cy8c6xx7_cm4_dual.ld. +* Change the stack size by modifying the following line:\n +* \code STACK_SIZE = 0x1000; \endcode * -* - Specifying via command line\n -* Change the heap and stack sizes passing the following commands to the compiler:\n -* \code -D __STACK_SIZE=0x000000400 \endcode -* \code -D __HEAP_SIZE=0x000000100 \endcode -* -* \subsubsection group_system_config_heap_stack_config_mdk ARM MDK +* \subsubsection group_system_config_heap_stack_config_mdk ARM Compiler * - Editing source code files\n -* The heap and stack sizes are defined in the assembler startup files -* (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). -* Change the heap and stack sizes by modifying the following lines:\n -* \code Stack_Size EQU 0x00001000 \endcode -* \code Heap_Size EQU 0x00000400 \endcode -* -* - Specifying via command line\n -* Change the heap and stack sizes passing the following commands to the assembler:\n -* \code "--predefine=___STACK_SIZE SETA 0x000000400" \endcode -* \code "--predefine=__HEAP_SIZE SETA 0x000000100" \endcode +* The stack size is defined in the linker script files: 'xx_yy.sct', +* where 'xx' is the device family, and 'yy' is the target CPU; for example, +* cy8c6xx7_cm0plus.sct and cy8c6xx7_cm4_dual.sct. +* Change the stack size by modifying the following line:\n +* \code STACK_SIZE = 0x1000; \endcode * * \subsubsection group_system_config_heap_stack_config_iar IAR * - Editing source code files\n -* The heap and stack sizes are defined in the linker scatter files: 'xx_yy.icf', +* The heap and stack sizes are defined in the linker script files: 'xx_yy.icf', * where 'xx' is the device family, and 'yy' is the target CPU; for example, * cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf. * Change the heap and stack sizes by modifying the following lines:\n @@ -232,21 +252,6 @@ * \code --define_symbol __STACK_SIZE=0x000000400 \endcode * \code --define_symbol __HEAP_SIZE=0x000000100 \endcode * -* \subsection group_system_config_merge_apps Merging CM0+ and CM4 Executables -* The CM0+ project and linker script build the CM0+ application image. Similarly, -* the CM4 linker script builds the CM4 application image. Each specifies -* locations, sizes, and contents of sections in memory. See -* \ref group_system_config_device_memory_definition for the symbols and default -* values. -* -* The cymcuelftool is invoked by a post-build command. The precise project -* setting is IDE-specific. -* -* The cymcuelftool combines the two executables. The tool examines the -* executables to ensure that memory regions either do not overlap, or contain -* identical bytes (shared). If there are no problems, it creates a new ELF file -* with the merged image, without changing any of the addresses or data. -* * \subsection group_system_config_default_handlers Default Interrupt Handlers Definition * The default interrupt handler functions are defined as weak functions to a dummy * handler in the startup file. The naming convention for the interrupt handler names @@ -273,10 +278,10 @@ * The vector table address (and the vector table itself) are defined in the * assembler startup files (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S). * The code in these files copies the vector table from Flash to RAM. -* \subsubsection group_system_config_device_vector_table_mdk ARM MDK -* The linker script file is 'xx_yy.scat', where 'xx' is the device family, -* and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.scat and -* cy8c6xx7_cm4_dual.scat. The linker script specifies that the vector table +* \subsubsection group_system_config_device_vector_table_mdk ARM Compiler +* The linker script file is 'xx_yy.sct', where 'xx' is the device family, +* and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.sct and +* cy8c6xx7_cm4_dual.sct. The linker script specifies that the vector table * (RESET_RAM) shall be first in the RAM section.\n * RESET_RAM represents the vector table. It is defined in the assembler startup * files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). @@ -291,10 +296,6 @@ * assembler startup files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). * The code in these files copies the vector table from Flash to RAM. * -* \section group_system_config_more_information More Information -* Refer to the PDL User Guide for the -* more details. -* * \section group_system_config_MISRA MISRA Compliance * * @@ -320,6 +321,11 @@ * * * +* +* +* +* +* * * * diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx4_cm0plus.sct b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx4_cm0plus.sct new file mode 100644 index 0000000..a3283de --- /dev/null +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx4_cm0plus.sct @@ -0,0 +1,259 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xx4_cm0plus.sct +;* \version 2.70.1 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2020 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM0+ core. +; You can change the memory allocation by editing the RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'. +; RAM +#define RAM_START 0x08000000 +#define RAM_SIZE 0x00002000 +; Flash +#define FLASH_START 0x10000000 +#define FLASH_SIZE 0x00002000 + +; The size of the stack section at the end of CM0+ SRAM +#define STACK_SIZE 0x00001000 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M0+ application flash area +LR_IROM1 FLASH_START FLASH_SIZE +{ + .cy_app_header +0 + { + * (.cy_app_header) + } + + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + .cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00040000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct index f936c20..9bc2bf5 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xx5_cm0plus.sct -;* \version 2.70 +;* \version 2.70.1 ;* ;* Linker file for the ARMCC. ;* @@ -26,7 +26,7 @@ ;* ;******************************************************************************* ;* \copyright -;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* Copyright 2016-2020 Cypress Semiconductor Corporation ;* SPDX-License-Identifier: Apache-2.0 ;* ;* Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx6_cm0plus.sct b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx6_cm0plus.sct index 9bd350d..50300cf 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx6_cm0plus.sct +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx6_cm0plus.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xx6_cm0plus.sct -;* \version 2.70 +;* \version 2.70.1 ;* ;* Linker file for the ARMCC. ;* @@ -26,7 +26,7 @@ ;* ;******************************************************************************* ;* \copyright -;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* Copyright 2016-2020 Cypress Semiconductor Corporation ;* SPDX-License-Identifier: Apache-2.0 ;* ;* Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct index 9e4e930..3c70be4 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xx7_cm0plus.sct -;* \version 2.70 +;* \version 2.70.1 ;* ;* Linker file for the ARMCC. ;* @@ -26,7 +26,7 @@ ;* ;******************************************************************************* ;* \copyright -;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* Copyright 2016-2020 Cypress Semiconductor Corporation ;* SPDX-License-Identifier: Apache-2.0 ;* ;* Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx8_cm0plus.sct b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx8_cm0plus.sct index 11dd0da..02ec1d3 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx8_cm0plus.sct +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx8_cm0plus.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xx8_cm0plus.sct -;* \version 2.70 +;* \version 2.70.1 ;* ;* Linker file for the ARMCC. ;* @@ -26,7 +26,7 @@ ;* ;******************************************************************************* ;* \copyright -;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* Copyright 2016-2020 Cypress Semiconductor Corporation ;* SPDX-License-Identifier: Apache-2.0 ;* ;* Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct index 68cfabe..775bdd4 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xxa_cm0plus.sct -;* \version 2.70 +;* \version 2.70.1 ;* ;* Linker file for the ARMCC. ;* @@ -26,7 +26,7 @@ ;* ;******************************************************************************* ;* \copyright -;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* Copyright 2016-2020 Cypress Semiconductor Corporation ;* SPDX-License-Identifier: Apache-2.0 ;* ;* Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx5_cm0plus.sct b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx5_cm0plus.sct index 784c7b6..06b9e85 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx5_cm0plus.sct +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx5_cm0plus.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cyb06xx5_cm0plus.sct -;* \version 2.70 +;* \version 2.70.1 ;* ;* Linker file for the ARMCC. ;* @@ -26,7 +26,7 @@ ;* ;******************************************************************************* ;* \copyright -;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* Copyright 2016-2020 Cypress Semiconductor Corporation ;* SPDX-License-Identifier: Apache-2.0 ;* ;* Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx7_cm0plus.sct b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx7_cm0plus.sct index 1b4b3ce..9ac47a0 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx7_cm0plus.sct +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx7_cm0plus.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cyb06xx7_cm0plus.sct -;* \version 2.70 +;* \version 2.70.1 ;* ;* Linker file for the ARMCC. ;* @@ -26,7 +26,7 @@ ;* ;******************************************************************************* ;* \copyright -;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* Copyright 2016-2020 Cypress Semiconductor Corporation ;* SPDX-License-Identifier: Apache-2.0 ;* ;* Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct index b06d119..9fb7441 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cyb06xxa_cm0plus.sct -;* \version 2.70 +;* \version 2.70.1 ;* ;* Linker file for the ARMCC. ;* @@ -26,7 +26,7 @@ ;* ;******************************************************************************* ;* \copyright -;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* Copyright 2016-2020 Cypress Semiconductor Corporation ;* SPDX-License-Identifier: Apache-2.0 ;* ;* Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_04_cm0plus.s b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_04_cm0plus.s new file mode 100644 index 0000000..0305d1e --- /dev/null +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_04_cm0plus.s @@ -0,0 +1,223 @@ +;/**************************************************************************//** +; * @file startup_psoc6_04_cm0plus.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM0plus Device Series +; * @version V5.00 +; * @date 02. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Base| + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Length| + +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Base| + |Image$$ARM_LIB_STACK$$ZI$$Length| ; Top of Stack + + DCD Reset_Handler ; Reset Handler + + DCD 0x0000000D ; NMI Handler located at ROM code + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External interrupts Description + DCD NvicMux0_IRQHandler ; CPU User Interrupt #0 + DCD NvicMux1_IRQHandler ; CPU User Interrupt #1 + DCD NvicMux2_IRQHandler ; CPU User Interrupt #2 + DCD NvicMux3_IRQHandler ; CPU User Interrupt #3 + DCD NvicMux4_IRQHandler ; CPU User Interrupt #4 + DCD NvicMux5_IRQHandler ; CPU User Interrupt #5 + DCD NvicMux6_IRQHandler ; CPU User Interrupt #6 + DCD NvicMux7_IRQHandler ; CPU User Interrupt #7 + DCD Internal0_IRQHandler ; Internal SW Interrupt #0 + DCD Internal1_IRQHandler ; Internal SW Interrupt #1 + DCD Internal2_IRQHandler ; Internal SW Interrupt #2 + DCD Internal3_IRQHandler ; Internal SW Interrupt #3 + DCD Internal4_IRQHandler ; Internal SW Interrupt #4 + DCD Internal5_IRQHandler ; Internal SW Interrupt #5 + DCD Internal6_IRQHandler ; Internal SW Interrupt #6 + DCD Internal7_IRQHandler ; Internal SW Interrupt #7 + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + EXPORT __ramVectors + AREA RESET_RAM, READWRITE, NOINIT +__ramVectors SPACE __Vectors_Size + + + AREA |.text|, CODE, READONLY + + +; Weak function for startup customization +; +; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +; because this function is executed as the first instruction in the ResetHandler. +; The PDL is also not initialized to use the proper register offsets. +; The user of this function is responsible for initializing the PDL and resources before using them. +; +Cy_OnResetUser PROC + EXPORT Cy_OnResetUser [WEAK] + BX LR + ENDP + +; Reset Handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + + ; Define strong function for startup customization + BL Cy_OnResetUser + + ; Disable global interrupts + CPSID I + + ; Copy vectors from ROM to RAM + LDR r1, =__Vectors + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +Vectors_Copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE Vectors_Copy + + ; Update Vector Table Offset Register. */ + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb 0xF + + LDR R0, =__main + BLX R0 + + ; Should never get here + B . + + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +Cy_SysLib_FaultHandler PROC + EXPORT Cy_SysLib_FaultHandler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + bl L_API_call +L_MSP + mrs r0, MSP +L_API_call + bl Cy_SysLib_FaultHandler + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT Default_Handler [WEAK] + EXPORT NvicMux0_IRQHandler [WEAK] + EXPORT NvicMux1_IRQHandler [WEAK] + EXPORT NvicMux2_IRQHandler [WEAK] + EXPORT NvicMux3_IRQHandler [WEAK] + EXPORT NvicMux4_IRQHandler [WEAK] + EXPORT NvicMux5_IRQHandler [WEAK] + EXPORT NvicMux6_IRQHandler [WEAK] + EXPORT NvicMux7_IRQHandler [WEAK] + EXPORT Internal0_IRQHandler [WEAK] + EXPORT Internal1_IRQHandler [WEAK] + EXPORT Internal2_IRQHandler [WEAK] + EXPORT Internal3_IRQHandler [WEAK] + EXPORT Internal4_IRQHandler [WEAK] + EXPORT Internal5_IRQHandler [WEAK] + EXPORT Internal6_IRQHandler [WEAK] + EXPORT Internal7_IRQHandler [WEAK] + +NvicMux0_IRQHandler +NvicMux1_IRQHandler +NvicMux2_IRQHandler +NvicMux3_IRQHandler +NvicMux4_IRQHandler +NvicMux5_IRQHandler +NvicMux6_IRQHandler +NvicMux7_IRQHandler +Internal0_IRQHandler +Internal1_IRQHandler +Internal2_IRQHandler +Internal3_IRQHandler +Internal4_IRQHandler +Internal5_IRQHandler +Internal6_IRQHandler +Internal7_IRQHandler + + B . + ENDP + + ALIGN + + +; User Initial Stack & Heap + IMPORT __use_two_region_memory + + END + + +; [] END OF FILE diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_A_Clang/startup_psoc6_04_cm0plus.S b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_A_Clang/startup_psoc6_04_cm0plus.S new file mode 100644 index 0000000..a192309 --- /dev/null +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_A_Clang/startup_psoc6_04_cm0plus.S @@ -0,0 +1,253 @@ +/**************************************************************************//** + * @file startup_psoc6_04_cm0plus.S + * @brief CMSIS Core Device Startup File for + * ARMCM0plus Device Series + * @version V5.00 + * @date 02. March 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + /* Address of the NMI handler */ + #define CY_NMI_HANLDER_ADDR 0x0000000D + + /* The CPU VTOR register */ + #define CY_CPU_VTOR_ADDR 0xE000ED08 + + .syntax unified + + .section __STACK, __stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x00001000 +#endif + .globl __StackTop + .globl __StackLimit + +__StackLimit: + .space Stack_Size + .equ __StackTop, . - Stack_Size + + .section __HEAP, __heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x00000400 +#endif + .globl __HeapBase +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + + .section __VECT, ___Vectors + .align 2 + .globl ___Vectors +___Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long CY_NMI_HANLDER_ADDR /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts Description */ + .long NvicMux0_IRQHandler /* CPU User Interrupt #0 */ + .long NvicMux1_IRQHandler /* CPU User Interrupt #1 */ + .long NvicMux2_IRQHandler /* CPU User Interrupt #2 */ + .long NvicMux3_IRQHandler /* CPU User Interrupt #3 */ + .long NvicMux4_IRQHandler /* CPU User Interrupt #4 */ + .long NvicMux5_IRQHandler /* CPU User Interrupt #5 */ + .long NvicMux6_IRQHandler /* CPU User Interrupt #6 */ + .long NvicMux7_IRQHandler /* CPU User Interrupt #7 */ + .long Internal0_IRQHandler /* Internal SW Interrupt #0 */ + .long Internal1_IRQHandler /* Internal SW Interrupt #1 */ + .long Internal2_IRQHandler /* Internal SW Interrupt #2 */ + .long Internal3_IRQHandler /* Internal SW Interrupt #3 */ + .long Internal4_IRQHandler /* Internal SW Interrupt #4 */ + .long Internal5_IRQHandler /* Internal SW Interrupt #5 */ + .long Internal6_IRQHandler /* Internal SW Interrupt #6 */ + .long Internal7_IRQHandler /* Internal SW Interrupt #7 */ + + .equ __VectorsSize, . - ___Vectors + + .section __RAMVECTORS, ___ramVectors + .align 2 + .globl ___ramVectors + +___ramVectors: + .space __VectorsSize + + + .text + .thumb_func + .align 2 + /* Reset handler */ + .globl Reset_Handler + +Reset_Handler: + bl Cy_OnResetUser + cpsid i + +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r0, =___ramVectors + ldr r1, =___Vectors + ldr r2, =__VectorsSize + bl _memcpy + + ldr r0, =segment$start$__DATA + ldr r1, =segment$end$__TEXT + ldr r2, =section$start$__DATA$__zerofill + sub r2, r0 + bl _memcpy + + ldr r0, =section$start$__DATA$__zerofill + eor r1, r1 + ldr r2, =section$end$__DATA$__zerofill + sub r2, r0 + bl _memset + + /* Update Vector Table Offset Register. */ + ldr r0, =___ramVectors + ldr r1, =CY_CPU_VTOR_ADDR + str r0, [r1] + dsb 0xF + + bl _HeapInit +#ifndef __NO_SYSTEM_INIT + bl _SystemInit +#endif + + bl _main + + /* Should never get here */ + b . + + .pool + + .text + .thumb + .thumb_func + .align 2 + + /* Device startup customization */ + .weak_definition Cy_OnResetUser + .global Cy_OnResetUser, Cy_OnResetUser +Cy_OnResetUser: + bx lr + + .text + .align 1 + .thumb_func + .weak_reference Default_Handler + +Default_Handler: + b . + + .text + .thumb_func + .align 2 + .weak_definition Cy_SysLib_FaultHandler + +Cy_SysLib_FaultHandler: + b . + + .text + .thumb_func + .align 2 + +Fault_Handler: + /* Storing LR content for Creator call stack trace */ + push {LR} + movs r0, #4 + mov r1, LR + tst r0, r1 + beq .L_MSP + mrs r0, PSP + b .L_API_call +.L_MSP: + mrs r0, MSP +.L_API_call: + /* Compensation of stack pointer address due to pushing 4 bytes of LR */ + adds r0, r0, #4 + bl Cy_SysLib_FaultHandler + b . + +.macro def_fault_Handler fault_handler_name + .weak_definition \fault_handler_name + .set \fault_handler_name, Fault_Handler + .endm + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak_definition \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + + def_fault_Handler HardFault_Handler + + def_irq_handler SVC_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler NvicMux0_IRQHandler /* CPU User Interrupt #0 */ + def_irq_handler NvicMux1_IRQHandler /* CPU User Interrupt #1 */ + def_irq_handler NvicMux2_IRQHandler /* CPU User Interrupt #2 */ + def_irq_handler NvicMux3_IRQHandler /* CPU User Interrupt #3 */ + def_irq_handler NvicMux4_IRQHandler /* CPU User Interrupt #4 */ + def_irq_handler NvicMux5_IRQHandler /* CPU User Interrupt #5 */ + def_irq_handler NvicMux6_IRQHandler /* CPU User Interrupt #6 */ + def_irq_handler NvicMux7_IRQHandler /* CPU User Interrupt #7 */ + def_irq_handler Internal0_IRQHandler /* Internal SW Interrupt #0 */ + def_irq_handler Internal1_IRQHandler /* Internal SW Interrupt #1 */ + def_irq_handler Internal2_IRQHandler /* Internal SW Interrupt #2 */ + def_irq_handler Internal3_IRQHandler /* Internal SW Interrupt #3 */ + def_irq_handler Internal4_IRQHandler /* Internal SW Interrupt #4 */ + def_irq_handler Internal5_IRQHandler /* Internal SW Interrupt #5 */ + def_irq_handler Internal6_IRQHandler /* Internal SW Interrupt #6 */ + def_irq_handler Internal7_IRQHandler /* Internal SW Interrupt #7 */ + + .end + + +/* [] END OF FILE */ diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx4_cm0plus.ld b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx4_cm0plus.ld new file mode 100644 index 0000000..3143c49 --- /dev/null +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx4_cm0plus.ld @@ -0,0 +1,418 @@ +/***************************************************************************//** +* \file cy8c6xx4_cm0plus.ld +* \version 2.70.1 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + +/* The size of the stack section at the end of CM0+ SRAM */ +STACK_SIZE = 0x1000; + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM0+ core. + * You can change the memory allocation by editing the 'ram' and 'flash' regions. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding memory regions for the CM4 core in 'xx_cm4_dual.ld', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.ld'. + */ + ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x2000 + flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x2000 + + /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ + em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */ + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + .cy_app_header : + { + KEEP(*(.cy_app_header)) + } > flash + + /* Cortex-M0+ application flash area */ + .text : + { + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_04_cm0plus.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_04_cm0plus.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > ram + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + .cy_xip : + { + KEEP(*(.cy_xip)) + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x00040000; +__cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +__cy_memory_1_start = 0x14000000; +__cy_memory_1_length = 0x8000; +__cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm0plus.ld b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm0plus.ld index 8822cbc..f83351d 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm0plus.ld +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm0plus.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx5_cm0plus.ld -* \version 2.70 +* \version 2.70.1 * * Linker file for the GNU C compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx6_cm0plus.ld b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx6_cm0plus.ld index 26518f0..ffdf781 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx6_cm0plus.ld +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx6_cm0plus.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx6_cm0plus.ld -* \version 2.70 +* \version 2.70.1 * * Linker file for the GNU C compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld index 93b42aa..1e40f15 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx7_cm0plus.ld -* \version 2.70 +* \version 2.70.1 * * Linker file for the GNU C compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx8_cm0plus.ld b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx8_cm0plus.ld index fcf5c75..30683ad 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx8_cm0plus.ld +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx8_cm0plus.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx8_cm0plus.ld -* \version 2.70 +* \version 2.70.1 * * Linker file for the GNU C compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld index 1f3a5a9..7fb39e7 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xxa_cm0plus.ld -* \version 2.70 +* \version 2.70.1 * * Linker file for the GNU C compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xx5_cm0plus.ld b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xx5_cm0plus.ld index da316b1..b7478cd 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xx5_cm0plus.ld +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xx5_cm0plus.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cyb06xx5_cm0plus.ld -* \version 2.70 +* \version 2.70.1 * * Linker file for the GNU C compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xx7_cm0plus.ld b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xx7_cm0plus.ld index 18233c2..20efcb1 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xx7_cm0plus.ld +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xx7_cm0plus.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cyb06xx7_cm0plus.ld -* \version 2.70 +* \version 2.70.1 * * Linker file for the GNU C compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xxa_cm0plus.ld b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xxa_cm0plus.ld index 062f5fd..14a330d 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xxa_cm0plus.ld +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xxa_cm0plus.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cyb06xxa_cm0plus.ld -* \version 2.70 +* \version 2.70.1 * * Linker file for the GNU C compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_04_cm0plus.S b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_04_cm0plus.S new file mode 100644 index 0000000..fbc1654 --- /dev/null +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_04_cm0plus.S @@ -0,0 +1,372 @@ +/**************************************************************************//** + * @file startup_psoc6_04_cm0plus.S + * @brief CMSIS Core Device Startup File for + * ARMCM0plus Device Series + * @version V5.00 + * @date 02. March 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + /* Address of the NMI handler */ + #define CY_NMI_HANLDER_ADDR 0x0000000D + + /* The CPU VTOR register */ + #define CY_CPU_VTOR_ADDR 0xE000ED08 + + /* Copy flash vectors and data section to RAM */ + #define __STARTUP_COPY_MULTIPLE + + /* Clear single BSS section */ + #define __STARTUP_CLEAR_BSS + + .syntax unified + .arch armv6-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x00001000 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x00000400 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .vectors + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long CY_NMI_HANLDER_ADDR /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts Description */ + .long NvicMux0_IRQHandler /* CPU User Interrupt #0 */ + .long NvicMux1_IRQHandler /* CPU User Interrupt #1 */ + .long NvicMux2_IRQHandler /* CPU User Interrupt #2 */ + .long NvicMux3_IRQHandler /* CPU User Interrupt #3 */ + .long NvicMux4_IRQHandler /* CPU User Interrupt #4 */ + .long NvicMux5_IRQHandler /* CPU User Interrupt #5 */ + .long NvicMux6_IRQHandler /* CPU User Interrupt #6 */ + .long NvicMux7_IRQHandler /* CPU User Interrupt #7 */ + .long Internal0_IRQHandler /* Internal SW Interrupt #0 */ + .long Internal1_IRQHandler /* Internal SW Interrupt #1 */ + .long Internal2_IRQHandler /* Internal SW Interrupt #2 */ + .long Internal3_IRQHandler /* Internal SW Interrupt #3 */ + .long Internal4_IRQHandler /* Internal SW Interrupt #4 */ + .long Internal5_IRQHandler /* Internal SW Interrupt #5 */ + .long Internal6_IRQHandler /* Internal SW Interrupt #6 */ + .long Internal7_IRQHandler /* Internal SW Interrupt #7 */ + + .size __Vectors, . - __Vectors + .equ __VectorsSize, . - __Vectors + + .section .ram_vectors + .align 2 + .globl __ramVectors +__ramVectors: + .space __VectorsSize + .size __ramVectors, . - __ramVectors + + + .text + .thumb + .thumb_func + .align 2 + + /* + * Device startup customization + * + * Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) + * because this function is executed as the first instruction in the ResetHandler. + * The PDL is also not initialized to use the proper register offsets. + * The user of this function is responsible for initializing the PDL and resources before using them. + */ + .weak Cy_OnResetUser + .func Cy_OnResetUser, Cy_OnResetUser + .type Cy_OnResetUser, %function + +Cy_OnResetUser: + bx lr + .size Cy_OnResetUser, . - Cy_OnResetUser + .endfunc + + /* Reset handler */ + .weak Reset_Handler + .type Reset_Handler, %function + +Reset_Handler: + bl Cy_OnResetUser + cpsid i + +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + blt .L_loop0_0_done + ldr r0, [r1, r3] + str r0, [r2, r3] + b .L_loop0_0 + +.L_loop0_0_done: + adds r4, #12 + b .L_loop0 + +.L_loop0_done: +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + + subs r3, r2 + ble .L_loop1_done + +.L_loop1: + subs r3, #4 + ldr r0, [r1,r3] + str r0, [r2,r3] + bgt .L_loop1 + +.L_loop1_done: +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + blt .L_loop2_0_done + str r0, [r1, r2] + b .L_loop2_0 +.L_loop2_0_done: + + adds r3, #8 + b .L_loop2 +.L_loop2_done: +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 + + subs r2, r1 + ble .L_loop3_done + +.L_loop3: + subs r2, #4 + str r0, [r1, r2] + bgt .L_loop3 +.L_loop3_done: +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + + /* Update Vector Table Offset Register. */ + ldr r0, =__ramVectors + ldr r1, =CY_CPU_VTOR_ADDR + str r0, [r1] + dsb 0xF + +#ifndef __NO_SYSTEM_INIT + bl SystemInit +#endif + + bl main + + /* Should never get here */ + b . + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak Default_Handler + .type Default_Handler, %function +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + .weak Cy_SysLib_FaultHandler + .type Cy_SysLib_FaultHandler, %function + +Cy_SysLib_FaultHandler: + b . + .size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler + .type Fault_Handler, %function + +Fault_Handler: + /* Storing LR content for Creator call stack trace */ + push {LR} + movs r0, #4 + mov r1, LR + tst r0, r1 + beq .L_MSP + mrs r0, PSP + b .L_API_call +.L_MSP: + mrs r0, MSP +.L_API_call: + /* Compensation of stack pointer address due to pushing 4 bytes of LR */ + adds r0, r0, #4 + bl Cy_SysLib_FaultHandler + b . + .size Fault_Handler, . - Fault_Handler + +.macro def_fault_Handler fault_handler_name + .weak \fault_handler_name + .set \fault_handler_name, Fault_Handler + .endm + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + + def_fault_Handler HardFault_Handler + + def_irq_handler SVC_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler NvicMux0_IRQHandler /* CPU User Interrupt #0 */ + def_irq_handler NvicMux1_IRQHandler /* CPU User Interrupt #1 */ + def_irq_handler NvicMux2_IRQHandler /* CPU User Interrupt #2 */ + def_irq_handler NvicMux3_IRQHandler /* CPU User Interrupt #3 */ + def_irq_handler NvicMux4_IRQHandler /* CPU User Interrupt #4 */ + def_irq_handler NvicMux5_IRQHandler /* CPU User Interrupt #5 */ + def_irq_handler NvicMux6_IRQHandler /* CPU User Interrupt #6 */ + def_irq_handler NvicMux7_IRQHandler /* CPU User Interrupt #7 */ + def_irq_handler Internal0_IRQHandler /* Internal SW Interrupt #0 */ + def_irq_handler Internal1_IRQHandler /* Internal SW Interrupt #1 */ + def_irq_handler Internal2_IRQHandler /* Internal SW Interrupt #2 */ + def_irq_handler Internal3_IRQHandler /* Internal SW Interrupt #3 */ + def_irq_handler Internal4_IRQHandler /* Internal SW Interrupt #4 */ + def_irq_handler Internal5_IRQHandler /* Internal SW Interrupt #5 */ + def_irq_handler Internal6_IRQHandler /* Internal SW Interrupt #6 */ + def_irq_handler Internal7_IRQHandler /* Internal SW Interrupt #7 */ + + .end + + +/* [] END OF FILE */ diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx4_cm0plus.icf b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx4_cm0plus.icf new file mode 100644 index 0000000..2d0adf0 --- /dev/null +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx4_cm0plus.icf @@ -0,0 +1,232 @@ +/******************************************************************************* +* \file cy8c6xx4_cm0plus.icf +* \version 2.70.1 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM0+ core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding symbols for CM4 core in 'xx_cm4_dual.icf', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x08001FFF; + +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x10001FFF; + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x160007FF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/*-Sizes-*/ +if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol __ICFEDIT_size_cstack__ = 0x1000; +} else { + define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; +} +define symbol __ICFEDIT_size_proc_stack__ = 0x0; + +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; +define block RO {first section .intvec, readonly}; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M0+ application */ +".cy_app_header" : place at start of IROM1_region { section .cy_app_header }; +place in IROM1_region { block RO }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +".cy_xip" : place at start of EROM1_region { section .cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { readwrite }; +place at end of IRAM1_region { block HSTACK }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_app_header, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00040000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx5_cm0plus.icf b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx5_cm0plus.icf index e57aae5..9859796 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx5_cm0plus.icf +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx5_cm0plus.icf @@ -1,6 +1,6 @@ -/***************************************************************************//** +/******************************************************************************* * \file cy8c6xx5_cm0plus.icf -* \version 2.70 +* \version 2.70.1 * * Linker file for the IAR compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -54,10 +54,11 @@ define symbol __ICFEDIT_intvec_start__ = 0x00000000; */ /* RAM */ define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; -define symbol __ICFEDIT_region_IRAM1_end__ = 0x08002000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x08001FFF; + /* Flash */ define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; -define symbol __ICFEDIT_region_IROM1_end__ = 0x10002000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x10001FFF; /* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx6_cm0plus.icf b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx6_cm0plus.icf index d7365c5..c353a72 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx6_cm0plus.icf +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx6_cm0plus.icf @@ -1,6 +1,6 @@ -/***************************************************************************//** +/******************************************************************************* * \file cy8c6xx6_cm0plus.icf -* \version 2.70 +* \version 2.70.1 * * Linker file for the IAR compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -54,10 +54,11 @@ define symbol __ICFEDIT_intvec_start__ = 0x00000000; */ /* RAM */ define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; -define symbol __ICFEDIT_region_IRAM1_end__ = 0x08002000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x08001FFF; + /* Flash */ define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; -define symbol __ICFEDIT_region_IROM1_end__ = 0x10002000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x10001FFF; /* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf index 0179139..3934087 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf @@ -1,6 +1,6 @@ -/***************************************************************************//** +/******************************************************************************* * \file cy8c6xx7_cm0plus.icf -* \version 2.70 +* \version 2.70.1 * * Linker file for the IAR compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -54,10 +54,11 @@ define symbol __ICFEDIT_intvec_start__ = 0x00000000; */ /* RAM */ define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; -define symbol __ICFEDIT_region_IRAM1_end__ = 0x08002000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x08001FFF; + /* Flash */ define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; -define symbol __ICFEDIT_region_IROM1_end__ = 0x10002000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x10001FFF; /* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx8_cm0plus.icf b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx8_cm0plus.icf index c331450..4165b94 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx8_cm0plus.icf +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx8_cm0plus.icf @@ -1,6 +1,6 @@ -/***************************************************************************//** +/******************************************************************************* * \file cy8c6xx8_cm0plus.icf -* \version 2.70 +* \version 2.70.1 * * Linker file for the IAR compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -54,10 +54,11 @@ define symbol __ICFEDIT_intvec_start__ = 0x00000000; */ /* RAM */ define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; -define symbol __ICFEDIT_region_IRAM1_end__ = 0x08002000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x08001FFF; + /* Flash */ define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; -define symbol __ICFEDIT_region_IROM1_end__ = 0x10002000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x10001FFF; /* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf index 9ccd5bd..47e9f70 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf @@ -1,6 +1,6 @@ -/***************************************************************************//** +/******************************************************************************* * \file cy8c6xxa_cm0plus.icf -* \version 2.70 +* \version 2.70.1 * * Linker file for the IAR compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -54,10 +54,11 @@ define symbol __ICFEDIT_intvec_start__ = 0x00000000; */ /* RAM */ define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; -define symbol __ICFEDIT_region_IRAM1_end__ = 0x08002000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x08001FFF; + /* Flash */ define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; -define symbol __ICFEDIT_region_IROM1_end__ = 0x10002000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x10001FFF; /* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xx5_cm0plus.icf b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xx5_cm0plus.icf index 23684ad..9220a1c 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xx5_cm0plus.icf +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xx5_cm0plus.icf @@ -1,6 +1,6 @@ -/***************************************************************************//** +/******************************************************************************* * \file cyb06xx5_cm0plus.icf -* \version 2.70 +* \version 2.70.1 * * Linker file for the IAR compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -52,10 +52,11 @@ define symbol __ICFEDIT_intvec_start__ = 0x00000000; */ /* RAM */ define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; -define symbol __ICFEDIT_region_IRAM1_end__ = 0x08010000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x0800FFFF; + /* Flash */ define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; -define symbol __ICFEDIT_region_IROM1_end__ = 0x10010000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x1000FFFF; /* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xx7_cm0plus.icf b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xx7_cm0plus.icf index fa3adff..198a7c3 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xx7_cm0plus.icf +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xx7_cm0plus.icf @@ -1,6 +1,6 @@ -/***************************************************************************//** +/******************************************************************************* * \file cyb06xx7_cm0plus.icf -* \version 2.70 +* \version 2.70.1 * * Linker file for the IAR compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -52,10 +52,11 @@ define symbol __ICFEDIT_intvec_start__ = 0x00000000; */ /* RAM */ define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; -define symbol __ICFEDIT_region_IRAM1_end__ = 0x08010000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x0800FFFF; + /* Flash */ define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; -define symbol __ICFEDIT_region_IROM1_end__ = 0x10020000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x1001FFFF; /* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xxa_cm0plus.icf b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xxa_cm0plus.icf index 4997407..f37758b 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xxa_cm0plus.icf +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xxa_cm0plus.icf @@ -1,6 +1,6 @@ -/***************************************************************************//** +/******************************************************************************* * \file cyb06xxa_cm0plus.icf -* \version 2.70 +* \version 2.70.1 * * Linker file for the IAR compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -52,10 +52,11 @@ define symbol __ICFEDIT_intvec_start__ = 0x00000000; */ /* RAM */ define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; -define symbol __ICFEDIT_region_IRAM1_end__ = 0x08040000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x0803FFFF; + /* Flash */ define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; -define symbol __ICFEDIT_region_IROM1_end__ = 0x10040000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x1003FFFF; /* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_04_cm0plus.s b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_04_cm0plus.s new file mode 100644 index 0000000..a520420 --- /dev/null +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_04_cm0plus.s @@ -0,0 +1,331 @@ +;/**************************************************************************//** +; * @file startup_psoc6_04_cm0plus.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM0plus Device Series +; * @version V5.00 +; * @date 08. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + SECTION .intvec_ram:DATA:NOROOT(2) + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + EXTERN __iar_data_init3 + EXTERN __iar_dynamic_initialization + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + PUBLIC __ramVectors + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD 0x0000000D ; NMI_Handler is defined in ROM code + DCD HardFault_Handler + DCD 0 + DCD 0 + DCD 0 +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD 0 + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External interrupts Description + DCD NvicMux0_IRQHandler ; CPU User Interrupt #0 + DCD NvicMux1_IRQHandler ; CPU User Interrupt #1 + DCD NvicMux2_IRQHandler ; CPU User Interrupt #2 + DCD NvicMux3_IRQHandler ; CPU User Interrupt #3 + DCD NvicMux4_IRQHandler ; CPU User Interrupt #4 + DCD NvicMux5_IRQHandler ; CPU User Interrupt #5 + DCD NvicMux6_IRQHandler ; CPU User Interrupt #6 + DCD NvicMux7_IRQHandler ; CPU User Interrupt #7 + DCD Internal0_IRQHandler ; Internal SW Interrupt #0 + DCD Internal1_IRQHandler ; Internal SW Interrupt #1 + DCD Internal2_IRQHandler ; Internal SW Interrupt #2 + DCD Internal3_IRQHandler ; Internal SW Interrupt #3 + DCD Internal4_IRQHandler ; Internal SW Interrupt #4 + DCD Internal5_IRQHandler ; Internal SW Interrupt #5 + DCD Internal6_IRQHandler ; Internal SW Interrupt #6 + DCD Internal7_IRQHandler ; Internal SW Interrupt #7 + +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + SECTION .intvec_ram:DATA:REORDER:NOROOT(2) +__ramVectors + DS32 __Vectors_Size + + + THUMB + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default handlers +;; + PUBWEAK Default_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Default_Handler + B Default_Handler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Weak function for startup customization +;; +;; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +;; because this function is executed as the first instruction in the ResetHandler. +;; The PDL is also not initialized to use the proper register offsets. +;; The user of this function is responsible for initializing the PDL and resources before using them. +;; + PUBWEAK Cy_OnResetUser + SECTION .text:CODE:REORDER:NOROOT(2) +Cy_OnResetUser + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Define strong version to return zero for +;; __iar_program_start to skip data sections +;; initialization. +;; + PUBLIC __low_level_init + SECTION .text:CODE:REORDER:NOROOT(2) +__low_level_init + MOVS R0, #0 + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + ; Define strong function for startup customization + LDR R0, =Cy_OnResetUser + BLX R0 + + ; Disable global interrupts + CPSID I + + ; Copy vectors from ROM to RAM + LDR r1, =__vector_table + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +intvec_copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE intvec_copy + + ; Update Vector Table Offset Register + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb + + ; Initialize data sections + LDR R0, =__iar_data_init3 + BLX R0 + + ; --manual_dynamic_initialization + BL __iar_dynamic_initialization + + LDR R0, =SystemInit + BLX R0 + + LDR R0, =__iar_program_start + BLX R0 + +; Should never get here +Cy_Main_Exited + B Cy_Main_Exited + + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK Cy_SysLib_FaultHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Cy_SysLib_FaultHandler + B Cy_SysLib_FaultHandler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + IMPORT Cy_SysLib_FaultHandler + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + b L_API_call +L_MSP + mrs r0, MSP +L_API_call + ; Storing LR content for Creator call stack trace + push {LR} + bl Cy_SysLib_FaultHandler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + + ; External interrupts + PUBWEAK NvicMux0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux0_IRQHandler + B NvicMux0_IRQHandler + + PUBWEAK NvicMux1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux1_IRQHandler + B NvicMux1_IRQHandler + + PUBWEAK NvicMux2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux2_IRQHandler + B NvicMux2_IRQHandler + + PUBWEAK NvicMux3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux3_IRQHandler + B NvicMux3_IRQHandler + + PUBWEAK NvicMux4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux4_IRQHandler + B NvicMux4_IRQHandler + + PUBWEAK NvicMux5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux5_IRQHandler + B NvicMux5_IRQHandler + + PUBWEAK NvicMux6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux6_IRQHandler + B NvicMux6_IRQHandler + + PUBWEAK NvicMux7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux7_IRQHandler + B NvicMux7_IRQHandler + + PUBWEAK Internal0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal0_IRQHandler + B Internal0_IRQHandler + + PUBWEAK Internal1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal1_IRQHandler + B Internal1_IRQHandler + + PUBWEAK Internal2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal2_IRQHandler + B Internal2_IRQHandler + + PUBWEAK Internal3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal3_IRQHandler + B Internal3_IRQHandler + + PUBWEAK Internal4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal4_IRQHandler + B Internal4_IRQHandler + + PUBWEAK Internal5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal5_IRQHandler + B Internal5_IRQHandler + + PUBWEAK Internal6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal6_IRQHandler + B Internal6_IRQHandler + + PUBWEAK Internal7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Internal7_IRQHandler + B Internal7_IRQHandler + + + END + + +; [] END OF FILE diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/system_psoc6_cm0plus.c b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/system_psoc6_cm0plus.c index 18cc197..2e2b152 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/system_psoc6_cm0plus.c +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/system_psoc6_cm0plus.c @@ -1,12 +1,12 @@ /***************************************************************************//** * \file system_psoc6_cm0plus.c -* \version 2.70 +* \version 2.70.1 * * The device system-source file. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx4_cm4_dual.sct b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx4_cm4_dual.sct new file mode 100644 index 0000000..25303a7 --- /dev/null +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx4_cm4_dual.sct @@ -0,0 +1,277 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xx4_cm4_dual.sct +;* \version 2.70.1 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2020 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; You can change the memory allocation by editing RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. +; RAM +#define RAM_START 0x08002000 +#define RAM_SIZE 0x0001D800 +; Flash +#define FLASH_START 0x10000000 +#define FLASH_SIZE 0x00040000 + +; The size of the stack section at the end of CM4 SRAM +#define STACK_SIZE 0x00001000 + +; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +; More about CM0+ prebuilt images, see here: +; https://github.com/cypresssemiconductorco/psoc6cm0p +; The size of the Cortex-M0+ application flash image +#define FLASH_CM0P_SIZE 0x2000 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M0+ application flash image area +LR_IROM FLASH_START FLASH_CM0P_SIZE +{ + .cy_m0p_image +0 FLASH_CM0P_SIZE + { + * (.cy_m0p_image) + } +} + +; Cortex-M4 application flash area +LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE) +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + .cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00040000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct index 47ed29d..4484738 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xx5_cm4_dual.sct -;* \version 2.70 +;* \version 2.70.1 ;* ;* Linker file for the ARMCC. ;* @@ -26,7 +26,7 @@ ;* ;******************************************************************************* ;* \copyright -;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* Copyright 2016-2020 Cypress Semiconductor Corporation ;* SPDX-License-Identifier: Apache-2.0 ;* ;* Licensed under the Apache License, Version 2.0 (the "License"); @@ -61,6 +61,9 @@ ; The size of the stack section at the end of CM4 SRAM #define STACK_SIZE 0x00001000 +; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +; More about CM0+ prebuilt images, see here: +; https://github.com/cypresssemiconductorco/psoc6cm0p ; The size of the Cortex-M0+ application flash image #define FLASH_CM0P_SIZE 0x2000 diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx6_cm4.sct b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx6_cm4.sct index f573555..a3a492c 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx6_cm4.sct +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx6_cm4.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xx6_cm4.sct -;* \version 2.70 +;* \version 2.70.1 ;* ;* Linker file for the ARMCC. ;* @@ -26,7 +26,7 @@ ;* ;******************************************************************************* ;* \copyright -;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* Copyright 2016-2020 Cypress Semiconductor Corporation ;* SPDX-License-Identifier: Apache-2.0 ;* ;* Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx6_cm4_dual.sct b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx6_cm4_dual.sct index 7bfcba9..2fec207 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx6_cm4_dual.sct +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx6_cm4_dual.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xx6_cm4_dual.sct -;* \version 2.70 +;* \version 2.70.1 ;* ;* Linker file for the ARMCC. ;* @@ -26,7 +26,7 @@ ;* ;******************************************************************************* ;* \copyright -;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* Copyright 2016-2020 Cypress Semiconductor Corporation ;* SPDX-License-Identifier: Apache-2.0 ;* ;* Licensed under the Apache License, Version 2.0 (the "License"); @@ -61,6 +61,9 @@ ; The size of the stack section at the end of CM4 SRAM #define STACK_SIZE 0x00001000 +; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +; More about CM0+ prebuilt images, see here: +; https://github.com/cypresssemiconductorco/psoc6cm0p ; The size of the Cortex-M0+ application flash image #define FLASH_CM0P_SIZE 0x2000 diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4.sct b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4.sct index 3c1a00e..4792967 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4.sct +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xx7_cm4.sct -;* \version 2.70 +;* \version 2.70.1 ;* ;* Linker file for the ARMCC. ;* @@ -26,7 +26,7 @@ ;* ;******************************************************************************* ;* \copyright -;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* Copyright 2016-2020 Cypress Semiconductor Corporation ;* SPDX-License-Identifier: Apache-2.0 ;* ;* Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct index 5efe315..e515fb3 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xx7_cm4_dual.sct -;* \version 2.70 +;* \version 2.70.1 ;* ;* Linker file for the ARMCC. ;* @@ -26,7 +26,7 @@ ;* ;******************************************************************************* ;* \copyright -;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* Copyright 2016-2020 Cypress Semiconductor Corporation ;* SPDX-License-Identifier: Apache-2.0 ;* ;* Licensed under the Apache License, Version 2.0 (the "License"); @@ -61,6 +61,9 @@ ; The size of the stack section at the end of CM4 SRAM #define STACK_SIZE 0x00001000 +; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +; More about CM0+ prebuilt images, see here: +; https://github.com/cypresssemiconductorco/psoc6cm0p ; The size of the Cortex-M0+ application flash image #define FLASH_CM0P_SIZE 0x2000 diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx8_cm4_dual.sct b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx8_cm4_dual.sct index 0327a2b..93546f9 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx8_cm4_dual.sct +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx8_cm4_dual.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xx8_cm4_dual.sct -;* \version 2.70 +;* \version 2.70.1 ;* ;* Linker file for the ARMCC. ;* @@ -26,7 +26,7 @@ ;* ;******************************************************************************* ;* \copyright -;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* Copyright 2016-2020 Cypress Semiconductor Corporation ;* SPDX-License-Identifier: Apache-2.0 ;* ;* Licensed under the Apache License, Version 2.0 (the "License"); @@ -61,6 +61,9 @@ ; The size of the stack section at the end of CM4 SRAM #define STACK_SIZE 0x00001000 +; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +; More about CM0+ prebuilt images, see here: +; https://github.com/cypresssemiconductorco/psoc6cm0p ; The size of the Cortex-M0+ application flash image #define FLASH_CM0P_SIZE 0x2000 diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct index 18abfff..b4b7402 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xxa_cm4_dual.sct -;* \version 2.70 +;* \version 2.70.1 ;* ;* Linker file for the ARMCC. ;* @@ -26,7 +26,7 @@ ;* ;******************************************************************************* ;* \copyright -;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* Copyright 2016-2020 Cypress Semiconductor Corporation ;* SPDX-License-Identifier: Apache-2.0 ;* ;* Licensed under the Apache License, Version 2.0 (the "License"); @@ -61,6 +61,9 @@ ; The size of the stack section at the end of CM4 SRAM #define STACK_SIZE 0x00001000 +; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +; More about CM0+ prebuilt images, see here: +; https://github.com/cypresssemiconductorco/psoc6cm0p ; The size of the Cortex-M0+ application flash image #define FLASH_CM0P_SIZE 0x2000 diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx5_cm4.sct b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx5_cm4.sct index 0a61404..60ea0f9 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx5_cm4.sct +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx5_cm4.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cyb06xx5_cm4.sct -;* \version 2.70 +;* \version 2.70.1 ;* ;* Linker file for the ARMCC. ;* @@ -26,7 +26,7 @@ ;* ;******************************************************************************* ;* \copyright -;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* Copyright 2016-2020 Cypress Semiconductor Corporation ;* SPDX-License-Identifier: Apache-2.0 ;* ;* Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx5_cm4_dual.sct b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx5_cm4_dual.sct index ba9834b..5ee78f3 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx5_cm4_dual.sct +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx5_cm4_dual.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cyb06xx5_cm4_dual.sct -;* \version 2.70 +;* \version 2.70.1 ;* ;* Linker file for the ARMCC. ;* @@ -26,7 +26,7 @@ ;* ;******************************************************************************* ;* \copyright -;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* Copyright 2016-2020 Cypress Semiconductor Corporation ;* SPDX-License-Identifier: Apache-2.0 ;* ;* Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4.sct b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4.sct index d0de70c..704301d 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4.sct +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cyb06xx7_cm4.sct -;* \version 2.70 +;* \version 2.70.1 ;* ;* Linker file for the ARMCC. ;* @@ -26,7 +26,7 @@ ;* ;******************************************************************************* ;* \copyright -;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* Copyright 2016-2020 Cypress Semiconductor Corporation ;* SPDX-License-Identifier: Apache-2.0 ;* ;* Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct index ed8c6d1..191381e 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cyb06xx7_cm4_dual.sct -;* \version 2.70 +;* \version 2.70.1 ;* ;* Linker file for the ARMCC. ;* @@ -26,7 +26,7 @@ ;* ;******************************************************************************* ;* \copyright -;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* Copyright 2016-2020 Cypress Semiconductor Corporation ;* SPDX-License-Identifier: Apache-2.0 ;* ;* Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4.sct b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4.sct index c95e2d4..7fbbd84 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4.sct +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cyb06xxa_cm4.sct -;* \version 2.70 +;* \version 2.70.1 ;* ;* Linker file for the ARMCC. ;* @@ -26,7 +26,7 @@ ;* ;******************************************************************************* ;* \copyright -;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* Copyright 2016-2020 Cypress Semiconductor Corporation ;* SPDX-License-Identifier: Apache-2.0 ;* ;* Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4_dual.sct b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4_dual.sct index f80d292..4e58279 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4_dual.sct +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4_dual.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cyb06xxa_cm4_dual.sct -;* \version 2.70 +;* \version 2.70.1 ;* ;* Linker file for the ARMCC. ;* @@ -26,7 +26,7 @@ ;* ;******************************************************************************* ;* \copyright -;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* Copyright 2016-2020 Cypress Semiconductor Corporation ;* SPDX-License-Identifier: Apache-2.0 ;* ;* Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_04_cm4.s b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_04_cm4.s new file mode 100644 index 0000000..27109e5 --- /dev/null +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_04_cm4.s @@ -0,0 +1,659 @@ +;/**************************************************************************//** +; * @file startup_psoc6_04_cm4.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device Series +; * @version V5.00 +; * @date 02. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Base| + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Length| + +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Base| + |Image$$ARM_LIB_STACK$$ZI$$Length| ; Top of Stack + + DCD Reset_Handler ; Reset Handler + + DCD 0x0000000D ; NMI Handler located at ROM code + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External interrupts Description + DCD ioss_interrupts_gpio_0_IRQHandler ; GPIO Port Interrupt #0 + DCD 0 ; Reserved + DCD ioss_interrupts_gpio_2_IRQHandler ; GPIO Port Interrupt #2 + DCD ioss_interrupts_gpio_3_IRQHandler ; GPIO Port Interrupt #3 + DCD 0 ; Reserved + DCD ioss_interrupts_gpio_5_IRQHandler ; GPIO Port Interrupt #5 + DCD ioss_interrupts_gpio_6_IRQHandler ; GPIO Port Interrupt #6 + DCD ioss_interrupts_gpio_7_IRQHandler ; GPIO Port Interrupt #7 + DCD ioss_interrupts_gpio_8_IRQHandler ; GPIO Port Interrupt #8 + DCD ioss_interrupts_gpio_9_IRQHandler ; GPIO Port Interrupt #9 + DCD ioss_interrupts_gpio_10_IRQHandler ; GPIO Port Interrupt #10 + DCD ioss_interrupts_gpio_11_IRQHandler ; GPIO Port Interrupt #11 + DCD ioss_interrupts_gpio_12_IRQHandler ; GPIO Port Interrupt #12 + DCD 0 ; Reserved + DCD ioss_interrupts_gpio_14_IRQHandler ; GPIO Port Interrupt #14 + DCD ioss_interrupt_gpio_IRQHandler ; GPIO All Ports + DCD ioss_interrupt_vdd_IRQHandler ; GPIO Supply Detect Interrupt + DCD lpcomp_interrupt_IRQHandler ; Low Power Comparator Interrupt + DCD scb_6_interrupt_IRQHandler ; Serial Communication Block #6 (DeepSleep capable) + DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt + DCD srss_interrupt_IRQHandler ; Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) + DCD cpuss_interrupts_ipc_0_IRQHandler ; CPUSS Inter Process Communication Interrupt #0 + DCD cpuss_interrupts_ipc_1_IRQHandler ; CPUSS Inter Process Communication Interrupt #1 + DCD cpuss_interrupts_ipc_2_IRQHandler ; CPUSS Inter Process Communication Interrupt #2 + DCD cpuss_interrupts_ipc_3_IRQHandler ; CPUSS Inter Process Communication Interrupt #3 + DCD cpuss_interrupts_ipc_4_IRQHandler ; CPUSS Inter Process Communication Interrupt #4 + DCD cpuss_interrupts_ipc_5_IRQHandler ; CPUSS Inter Process Communication Interrupt #5 + DCD cpuss_interrupts_ipc_6_IRQHandler ; CPUSS Inter Process Communication Interrupt #6 + DCD cpuss_interrupts_ipc_7_IRQHandler ; CPUSS Inter Process Communication Interrupt #7 + DCD cpuss_interrupts_ipc_8_IRQHandler ; CPUSS Inter Process Communication Interrupt #8 + DCD cpuss_interrupts_ipc_9_IRQHandler ; CPUSS Inter Process Communication Interrupt #9 + DCD cpuss_interrupts_ipc_10_IRQHandler ; CPUSS Inter Process Communication Interrupt #10 + DCD cpuss_interrupts_ipc_11_IRQHandler ; CPUSS Inter Process Communication Interrupt #11 + DCD cpuss_interrupts_ipc_12_IRQHandler ; CPUSS Inter Process Communication Interrupt #12 + DCD cpuss_interrupts_ipc_13_IRQHandler ; CPUSS Inter Process Communication Interrupt #13 + DCD cpuss_interrupts_ipc_14_IRQHandler ; CPUSS Inter Process Communication Interrupt #14 + DCD cpuss_interrupts_ipc_15_IRQHandler ; CPUSS Inter Process Communication Interrupt #15 + DCD pass_interrupt_sar_0_IRQHandler ; SAR ADC0 interrupt + DCD pass_interrupt_sar_1_IRQHandler ; SAR ADC1 interrupt + DCD pass_interrupt_ctb_IRQHandler ; individual interrupt per CTB + DCD 0 ; Reserved + DCD pass_interrupt_fifo_0_IRQHandler ; PASS FIFO0 + DCD pass_interrupt_fifo_1_IRQHandler ; PASS FIFO1 + DCD scb_0_interrupt_IRQHandler ; Serial Communication Block #0 + DCD scb_1_interrupt_IRQHandler ; Serial Communication Block #1 + DCD scb_2_interrupt_IRQHandler ; Serial Communication Block #2 + DCD 0 ; Reserved + DCD scb_4_interrupt_IRQHandler ; Serial Communication Block #4 + DCD scb_5_interrupt_IRQHandler ; Serial Communication Block #5 + DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt + DCD cpuss_interrupts_dmac_0_IRQHandler ; CPUSS DMAC, Channel #0 + DCD cpuss_interrupts_dmac_1_IRQHandler ; CPUSS DMAC, Channel #1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD cpuss_interrupts_dw0_0_IRQHandler ; CPUSS DataWire #0, Channel #0 + DCD cpuss_interrupts_dw0_1_IRQHandler ; CPUSS DataWire #0, Channel #1 + DCD cpuss_interrupts_dw0_2_IRQHandler ; CPUSS DataWire #0, Channel #2 + DCD cpuss_interrupts_dw0_3_IRQHandler ; CPUSS DataWire #0, Channel #3 + DCD cpuss_interrupts_dw0_4_IRQHandler ; CPUSS DataWire #0, Channel #4 + DCD cpuss_interrupts_dw0_5_IRQHandler ; CPUSS DataWire #0, Channel #5 + DCD cpuss_interrupts_dw0_6_IRQHandler ; CPUSS DataWire #0, Channel #6 + DCD cpuss_interrupts_dw0_7_IRQHandler ; CPUSS DataWire #0, Channel #7 + DCD cpuss_interrupts_dw0_8_IRQHandler ; CPUSS DataWire #0, Channel #8 + DCD cpuss_interrupts_dw0_9_IRQHandler ; CPUSS DataWire #0, Channel #9 + DCD cpuss_interrupts_dw0_10_IRQHandler ; CPUSS DataWire #0, Channel #10 + DCD cpuss_interrupts_dw0_11_IRQHandler ; CPUSS DataWire #0, Channel #11 + DCD cpuss_interrupts_dw0_12_IRQHandler ; CPUSS DataWire #0, Channel #12 + DCD cpuss_interrupts_dw0_13_IRQHandler ; CPUSS DataWire #0, Channel #13 + DCD cpuss_interrupts_dw0_14_IRQHandler ; CPUSS DataWire #0, Channel #14 + DCD cpuss_interrupts_dw0_15_IRQHandler ; CPUSS DataWire #0, Channel #15 + DCD cpuss_interrupts_dw0_16_IRQHandler ; CPUSS DataWire #0, Channel #16 + DCD cpuss_interrupts_dw0_17_IRQHandler ; CPUSS DataWire #0, Channel #17 + DCD cpuss_interrupts_dw0_18_IRQHandler ; CPUSS DataWire #0, Channel #18 + DCD cpuss_interrupts_dw0_19_IRQHandler ; CPUSS DataWire #0, Channel #19 + DCD cpuss_interrupts_dw0_20_IRQHandler ; CPUSS DataWire #0, Channel #20 + DCD cpuss_interrupts_dw0_21_IRQHandler ; CPUSS DataWire #0, Channel #21 + DCD cpuss_interrupts_dw0_22_IRQHandler ; CPUSS DataWire #0, Channel #22 + DCD cpuss_interrupts_dw0_23_IRQHandler ; CPUSS DataWire #0, Channel #23 + DCD cpuss_interrupts_dw0_24_IRQHandler ; CPUSS DataWire #0, Channel #24 + DCD cpuss_interrupts_dw0_25_IRQHandler ; CPUSS DataWire #0, Channel #25 + DCD cpuss_interrupts_dw0_26_IRQHandler ; CPUSS DataWire #0, Channel #26 + DCD cpuss_interrupts_dw0_27_IRQHandler ; CPUSS DataWire #0, Channel #27 + DCD cpuss_interrupts_dw0_28_IRQHandler ; CPUSS DataWire #0, Channel #28 + DCD cpuss_interrupts_dw1_0_IRQHandler ; CPUSS DataWire #1, Channel #0 + DCD cpuss_interrupts_dw1_1_IRQHandler ; CPUSS DataWire #1, Channel #1 + DCD cpuss_interrupts_dw1_2_IRQHandler ; CPUSS DataWire #1, Channel #2 + DCD cpuss_interrupts_dw1_3_IRQHandler ; CPUSS DataWire #1, Channel #3 + DCD cpuss_interrupts_dw1_4_IRQHandler ; CPUSS DataWire #1, Channel #4 + DCD cpuss_interrupts_dw1_5_IRQHandler ; CPUSS DataWire #1, Channel #5 + DCD cpuss_interrupts_dw1_6_IRQHandler ; CPUSS DataWire #1, Channel #6 + DCD cpuss_interrupts_dw1_7_IRQHandler ; CPUSS DataWire #1, Channel #7 + DCD cpuss_interrupts_dw1_8_IRQHandler ; CPUSS DataWire #1, Channel #8 + DCD cpuss_interrupts_dw1_9_IRQHandler ; CPUSS DataWire #1, Channel #9 + DCD cpuss_interrupts_dw1_10_IRQHandler ; CPUSS DataWire #1, Channel #10 + DCD cpuss_interrupts_dw1_11_IRQHandler ; CPUSS DataWire #1, Channel #11 + DCD cpuss_interrupts_dw1_12_IRQHandler ; CPUSS DataWire #1, Channel #12 + DCD cpuss_interrupts_dw1_13_IRQHandler ; CPUSS DataWire #1, Channel #13 + DCD cpuss_interrupts_dw1_14_IRQHandler ; CPUSS DataWire #1, Channel #14 + DCD cpuss_interrupts_dw1_15_IRQHandler ; CPUSS DataWire #1, Channel #15 + DCD cpuss_interrupts_dw1_16_IRQHandler ; CPUSS DataWire #1, Channel #16 + DCD cpuss_interrupts_dw1_17_IRQHandler ; CPUSS DataWire #1, Channel #17 + DCD cpuss_interrupts_dw1_18_IRQHandler ; CPUSS DataWire #1, Channel #18 + DCD cpuss_interrupts_dw1_19_IRQHandler ; CPUSS DataWire #1, Channel #19 + DCD cpuss_interrupts_dw1_20_IRQHandler ; CPUSS DataWire #1, Channel #20 + DCD cpuss_interrupts_dw1_21_IRQHandler ; CPUSS DataWire #1, Channel #21 + DCD cpuss_interrupts_dw1_22_IRQHandler ; CPUSS DataWire #1, Channel #22 + DCD cpuss_interrupts_dw1_23_IRQHandler ; CPUSS DataWire #1, Channel #23 + DCD cpuss_interrupts_dw1_24_IRQHandler ; CPUSS DataWire #1, Channel #24 + DCD cpuss_interrupts_dw1_25_IRQHandler ; CPUSS DataWire #1, Channel #25 + DCD cpuss_interrupts_dw1_26_IRQHandler ; CPUSS DataWire #1, Channel #26 + DCD cpuss_interrupts_dw1_27_IRQHandler ; CPUSS DataWire #1, Channel #27 + DCD cpuss_interrupts_dw1_28_IRQHandler ; CPUSS DataWire #1, Channel #28 + DCD cpuss_interrupts_fault_0_IRQHandler ; CPUSS Fault Structure Interrupt #0 + DCD cpuss_interrupts_fault_1_IRQHandler ; CPUSS Fault Structure Interrupt #1 + DCD cpuss_interrupt_crypto_IRQHandler ; CRYPTO Accelerator Interrupt + DCD cpuss_interrupt_fm_IRQHandler ; FLASH Macro Interrupt + DCD cpuss_interrupts_cm4_fp_IRQHandler ; Floating Point operation fault + DCD cpuss_interrupts_cm0_cti_0_IRQHandler ; CM0+ CTI #0 + DCD cpuss_interrupts_cm0_cti_1_IRQHandler ; CM0+ CTI #1 + DCD cpuss_interrupts_cm4_cti_0_IRQHandler ; CM4 CTI #0 + DCD cpuss_interrupts_cm4_cti_1_IRQHandler ; CM4 CTI #1 + DCD tcpwm_0_interrupts_0_IRQHandler ; TCPWM #0, Counter #0 + DCD tcpwm_0_interrupts_1_IRQHandler ; TCPWM #0, Counter #1 + DCD tcpwm_0_interrupts_2_IRQHandler ; TCPWM #0, Counter #2 + DCD tcpwm_0_interrupts_3_IRQHandler ; TCPWM #0, Counter #3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD tcpwm_0_interrupts_256_IRQHandler ; TCPWM #0, Counter #256 + DCD tcpwm_0_interrupts_257_IRQHandler ; TCPWM #0, Counter #257 + DCD tcpwm_0_interrupts_258_IRQHandler ; TCPWM #0, Counter #258 + DCD tcpwm_0_interrupts_259_IRQHandler ; TCPWM #0, Counter #259 + DCD tcpwm_0_interrupts_260_IRQHandler ; TCPWM #0, Counter #260 + DCD tcpwm_0_interrupts_261_IRQHandler ; TCPWM #0, Counter #261 + DCD tcpwm_0_interrupts_262_IRQHandler ; TCPWM #0, Counter #262 + DCD tcpwm_0_interrupts_263_IRQHandler ; TCPWM #0, Counter #263 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD pass_interrupt_dacs_IRQHandler ; Consolidated interrrupt for all DACs + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt + DCD usb_interrupt_hi_IRQHandler ; USB Interrupt + DCD usb_interrupt_med_IRQHandler ; USB Interrupt + DCD usb_interrupt_lo_IRQHandler ; USB Interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD canfd_0_interrupt0_IRQHandler ; Can #0, Consolidated interrupt #0 + DCD canfd_0_interrupts0_0_IRQHandler ; CAN #0, Interrupt #0, Channel #0 + DCD canfd_0_interrupts1_0_IRQHandler ; CAN #0, Interrupt #1, Channel #0 + DCD cpuss_interrupts_dw1_29_IRQHandler ; CPUSS DataWire #1, Channel #29 + DCD cpuss_interrupts_dw1_30_IRQHandler ; CPUSS DataWire #1, Channel #30 + DCD cpuss_interrupts_dw1_31_IRQHandler ; CPUSS DataWire #1, Channel #31 + DCD cpuss_interrupts_dw0_29_IRQHandler ; CPUSS DataWire #0, Channel #29 + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + EXPORT __ramVectors + AREA RESET_RAM, READWRITE, NOINIT +__ramVectors SPACE __Vectors_Size + + + AREA |.text|, CODE, READONLY + + +; Weak function for startup customization +; +; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +; because this function is executed as the first instruction in the ResetHandler. +; The PDL is also not initialized to use the proper register offsets. +; The user of this function is responsible for initializing the PDL and resources before using them. +; +Cy_OnResetUser PROC + EXPORT Cy_OnResetUser [WEAK] + BX LR + ENDP + +; Reset Handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT Cy_SystemInitFpuEnable + IMPORT __main + + ; Define strong function for startup customization + BL Cy_OnResetUser + + ; Disable global interrupts + CPSID I + + ; Copy vectors from ROM to RAM + LDR r1, =__Vectors + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +Vectors_Copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE Vectors_Copy + + ; Update Vector Table Offset Register. */ + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb 0xF + + ; Enable the FPU if used + LDR R0, =Cy_SystemInitFpuEnable + BLX R0 + + LDR R0, =__main + BLX R0 + + ; Should never get here + B . + + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +Cy_SysLib_FaultHandler PROC + EXPORT Cy_SysLib_FaultHandler [WEAK] + B . + ENDP +HardFault_Wrapper\ + PROC + EXPORT HardFault_Wrapper [WEAK] + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + bl L_API_call +L_MSP + mrs r0, MSP +L_API_call + bl Cy_SysLib_FaultHandler + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B HardFault_Wrapper + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B HardFault_Wrapper + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B HardFault_Wrapper + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B HardFault_Wrapper + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT Default_Handler [WEAK] + EXPORT ioss_interrupts_gpio_0_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_2_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_3_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_5_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_6_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_7_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_8_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_9_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_10_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_11_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_12_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_14_IRQHandler [WEAK] + EXPORT ioss_interrupt_gpio_IRQHandler [WEAK] + EXPORT ioss_interrupt_vdd_IRQHandler [WEAK] + EXPORT lpcomp_interrupt_IRQHandler [WEAK] + EXPORT scb_6_interrupt_IRQHandler [WEAK] + EXPORT srss_interrupt_mcwdt_0_IRQHandler [WEAK] + EXPORT srss_interrupt_mcwdt_1_IRQHandler [WEAK] + EXPORT srss_interrupt_backup_IRQHandler [WEAK] + EXPORT srss_interrupt_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_4_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_5_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_6_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_7_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_8_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_9_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_10_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_11_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_12_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_13_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_14_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_15_IRQHandler [WEAK] + EXPORT pass_interrupt_sar_0_IRQHandler [WEAK] + EXPORT pass_interrupt_sar_1_IRQHandler [WEAK] + EXPORT pass_interrupt_ctb_IRQHandler [WEAK] + EXPORT pass_interrupt_fifo_0_IRQHandler [WEAK] + EXPORT pass_interrupt_fifo_1_IRQHandler [WEAK] + EXPORT scb_0_interrupt_IRQHandler [WEAK] + EXPORT scb_1_interrupt_IRQHandler [WEAK] + EXPORT scb_2_interrupt_IRQHandler [WEAK] + EXPORT scb_4_interrupt_IRQHandler [WEAK] + EXPORT scb_5_interrupt_IRQHandler [WEAK] + EXPORT csd_interrupt_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dmac_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dmac_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_4_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_5_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_6_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_7_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_8_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_9_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_10_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_11_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_12_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_13_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_14_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_15_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_16_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_17_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_18_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_19_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_20_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_21_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_22_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_23_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_24_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_25_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_26_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_27_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_28_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_4_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_5_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_6_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_7_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_8_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_9_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_10_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_11_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_12_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_13_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_14_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_15_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_16_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_17_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_18_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_19_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_20_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_21_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_22_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_23_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_24_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_25_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_26_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_27_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_28_IRQHandler [WEAK] + EXPORT cpuss_interrupts_fault_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_fault_1_IRQHandler [WEAK] + EXPORT cpuss_interrupt_crypto_IRQHandler [WEAK] + EXPORT cpuss_interrupt_fm_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm4_fp_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm0_cti_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm0_cti_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm4_cti_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm4_cti_1_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_0_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_1_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_2_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_3_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_256_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_257_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_258_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_259_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_260_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_261_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_262_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_263_IRQHandler [WEAK] + EXPORT pass_interrupt_dacs_IRQHandler [WEAK] + EXPORT smif_interrupt_IRQHandler [WEAK] + EXPORT usb_interrupt_hi_IRQHandler [WEAK] + EXPORT usb_interrupt_med_IRQHandler [WEAK] + EXPORT usb_interrupt_lo_IRQHandler [WEAK] + EXPORT canfd_0_interrupt0_IRQHandler [WEAK] + EXPORT canfd_0_interrupts0_0_IRQHandler [WEAK] + EXPORT canfd_0_interrupts1_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_29_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_30_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_31_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_29_IRQHandler [WEAK] + +ioss_interrupts_gpio_0_IRQHandler +ioss_interrupts_gpio_2_IRQHandler +ioss_interrupts_gpio_3_IRQHandler +ioss_interrupts_gpio_5_IRQHandler +ioss_interrupts_gpio_6_IRQHandler +ioss_interrupts_gpio_7_IRQHandler +ioss_interrupts_gpio_8_IRQHandler +ioss_interrupts_gpio_9_IRQHandler +ioss_interrupts_gpio_10_IRQHandler +ioss_interrupts_gpio_11_IRQHandler +ioss_interrupts_gpio_12_IRQHandler +ioss_interrupts_gpio_14_IRQHandler +ioss_interrupt_gpio_IRQHandler +ioss_interrupt_vdd_IRQHandler +lpcomp_interrupt_IRQHandler +scb_6_interrupt_IRQHandler +srss_interrupt_mcwdt_0_IRQHandler +srss_interrupt_mcwdt_1_IRQHandler +srss_interrupt_backup_IRQHandler +srss_interrupt_IRQHandler +cpuss_interrupts_ipc_0_IRQHandler +cpuss_interrupts_ipc_1_IRQHandler +cpuss_interrupts_ipc_2_IRQHandler +cpuss_interrupts_ipc_3_IRQHandler +cpuss_interrupts_ipc_4_IRQHandler +cpuss_interrupts_ipc_5_IRQHandler +cpuss_interrupts_ipc_6_IRQHandler +cpuss_interrupts_ipc_7_IRQHandler +cpuss_interrupts_ipc_8_IRQHandler +cpuss_interrupts_ipc_9_IRQHandler +cpuss_interrupts_ipc_10_IRQHandler +cpuss_interrupts_ipc_11_IRQHandler +cpuss_interrupts_ipc_12_IRQHandler +cpuss_interrupts_ipc_13_IRQHandler +cpuss_interrupts_ipc_14_IRQHandler +cpuss_interrupts_ipc_15_IRQHandler +pass_interrupt_sar_0_IRQHandler +pass_interrupt_sar_1_IRQHandler +pass_interrupt_ctb_IRQHandler +pass_interrupt_fifo_0_IRQHandler +pass_interrupt_fifo_1_IRQHandler +scb_0_interrupt_IRQHandler +scb_1_interrupt_IRQHandler +scb_2_interrupt_IRQHandler +scb_4_interrupt_IRQHandler +scb_5_interrupt_IRQHandler +csd_interrupt_IRQHandler +cpuss_interrupts_dmac_0_IRQHandler +cpuss_interrupts_dmac_1_IRQHandler +cpuss_interrupts_dw0_0_IRQHandler +cpuss_interrupts_dw0_1_IRQHandler +cpuss_interrupts_dw0_2_IRQHandler +cpuss_interrupts_dw0_3_IRQHandler +cpuss_interrupts_dw0_4_IRQHandler +cpuss_interrupts_dw0_5_IRQHandler +cpuss_interrupts_dw0_6_IRQHandler +cpuss_interrupts_dw0_7_IRQHandler +cpuss_interrupts_dw0_8_IRQHandler +cpuss_interrupts_dw0_9_IRQHandler +cpuss_interrupts_dw0_10_IRQHandler +cpuss_interrupts_dw0_11_IRQHandler +cpuss_interrupts_dw0_12_IRQHandler +cpuss_interrupts_dw0_13_IRQHandler +cpuss_interrupts_dw0_14_IRQHandler +cpuss_interrupts_dw0_15_IRQHandler +cpuss_interrupts_dw0_16_IRQHandler +cpuss_interrupts_dw0_17_IRQHandler +cpuss_interrupts_dw0_18_IRQHandler +cpuss_interrupts_dw0_19_IRQHandler +cpuss_interrupts_dw0_20_IRQHandler +cpuss_interrupts_dw0_21_IRQHandler +cpuss_interrupts_dw0_22_IRQHandler +cpuss_interrupts_dw0_23_IRQHandler +cpuss_interrupts_dw0_24_IRQHandler +cpuss_interrupts_dw0_25_IRQHandler +cpuss_interrupts_dw0_26_IRQHandler +cpuss_interrupts_dw0_27_IRQHandler +cpuss_interrupts_dw0_28_IRQHandler +cpuss_interrupts_dw1_0_IRQHandler +cpuss_interrupts_dw1_1_IRQHandler +cpuss_interrupts_dw1_2_IRQHandler +cpuss_interrupts_dw1_3_IRQHandler +cpuss_interrupts_dw1_4_IRQHandler +cpuss_interrupts_dw1_5_IRQHandler +cpuss_interrupts_dw1_6_IRQHandler +cpuss_interrupts_dw1_7_IRQHandler +cpuss_interrupts_dw1_8_IRQHandler +cpuss_interrupts_dw1_9_IRQHandler +cpuss_interrupts_dw1_10_IRQHandler +cpuss_interrupts_dw1_11_IRQHandler +cpuss_interrupts_dw1_12_IRQHandler +cpuss_interrupts_dw1_13_IRQHandler +cpuss_interrupts_dw1_14_IRQHandler +cpuss_interrupts_dw1_15_IRQHandler +cpuss_interrupts_dw1_16_IRQHandler +cpuss_interrupts_dw1_17_IRQHandler +cpuss_interrupts_dw1_18_IRQHandler +cpuss_interrupts_dw1_19_IRQHandler +cpuss_interrupts_dw1_20_IRQHandler +cpuss_interrupts_dw1_21_IRQHandler +cpuss_interrupts_dw1_22_IRQHandler +cpuss_interrupts_dw1_23_IRQHandler +cpuss_interrupts_dw1_24_IRQHandler +cpuss_interrupts_dw1_25_IRQHandler +cpuss_interrupts_dw1_26_IRQHandler +cpuss_interrupts_dw1_27_IRQHandler +cpuss_interrupts_dw1_28_IRQHandler +cpuss_interrupts_fault_0_IRQHandler +cpuss_interrupts_fault_1_IRQHandler +cpuss_interrupt_crypto_IRQHandler +cpuss_interrupt_fm_IRQHandler +cpuss_interrupts_cm4_fp_IRQHandler +cpuss_interrupts_cm0_cti_0_IRQHandler +cpuss_interrupts_cm0_cti_1_IRQHandler +cpuss_interrupts_cm4_cti_0_IRQHandler +cpuss_interrupts_cm4_cti_1_IRQHandler +tcpwm_0_interrupts_0_IRQHandler +tcpwm_0_interrupts_1_IRQHandler +tcpwm_0_interrupts_2_IRQHandler +tcpwm_0_interrupts_3_IRQHandler +tcpwm_0_interrupts_256_IRQHandler +tcpwm_0_interrupts_257_IRQHandler +tcpwm_0_interrupts_258_IRQHandler +tcpwm_0_interrupts_259_IRQHandler +tcpwm_0_interrupts_260_IRQHandler +tcpwm_0_interrupts_261_IRQHandler +tcpwm_0_interrupts_262_IRQHandler +tcpwm_0_interrupts_263_IRQHandler +pass_interrupt_dacs_IRQHandler +smif_interrupt_IRQHandler +usb_interrupt_hi_IRQHandler +usb_interrupt_med_IRQHandler +usb_interrupt_lo_IRQHandler +canfd_0_interrupt0_IRQHandler +canfd_0_interrupts0_0_IRQHandler +canfd_0_interrupts1_0_IRQHandler +cpuss_interrupts_dw1_29_IRQHandler +cpuss_interrupts_dw1_30_IRQHandler +cpuss_interrupts_dw1_31_IRQHandler +cpuss_interrupts_dw0_29_IRQHandler + + B . + ENDP + + ALIGN + + +; User Initial Stack & Heap + IMPORT __use_two_region_memory + + END + + +; [] END OF FILE diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx4_cm4_dual.mk b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx4_cm4_dual.mk new file mode 100644 index 0000000..fef261f --- /dev/null +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx4_cm4_dual.mk @@ -0,0 +1,89 @@ +################################################################################ +# \file cy8c6xx4_cm4_dual.mk +# \version 2.70.1 +# +# \brief +# Specifies the starting address and the size of the segments in the output +# file. +# +# \note The section definitions in this file are generic and handle all common +# use cases. +# +################################################################################ +# \copyright +# Copyright 2018-2020 Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +################################################################################ + +### CM0P ### +export HEAP_SIZE_CM0P := 0x400 +export VECT_BASE_CM0P := 0x10000000 +export RAM_VECT_BASE_CM0P := 0x08000000 +export VECT_SIZE_CM0P := 0x00000080 +export TEXT_BASE_CM0P := 0x10000080 +export TEXT_SIZE_CM0P := 0x00002000 +export RAM_BASE_CM0P := 0x08000080 +export RAM_SIZE_CM0P := 0x00002000 +export CYMETA_BASE_CM0P := 0x90500000 +export STACK_SIZE_CM0P := 0x2000 + +STACK_ADDRESS_TOP_CM0P := $(shell printf "0x%x" $$(($(RAM_VECT_BASE_CM0P) + $(RAM_SIZE_CM0P)))) +STACK_ADDRESS_BOTTOM_CM0P := $(shell printf "0x%x" $$(($(STACK_ADDRESS_TOP_CM0P) - $(STACK_SIZE_CM0P)))) +TOOLCHAIN_VECT_BASE_CM0 := $(VECT_BASE_CM0P) + +SECTIONS_CM0P := \ + -segaddr __VECT $(VECT_BASE_CM0P) \ + -segaddr __TEXT $(TEXT_BASE_CM0P) \ + -segaddr __DATA $(RAM_BASE_CM0P) \ + -segaddr __RAMVECTORS $(RAM_VECT_BASE_CM0P) \ + -segaddr __CYMETA $(CYMETA_BASE_CM0P) \ + -segaddr __STACK $(STACK_ADDRESS_TOP_CM0P) + +### CM4 ### +export HEAP_SIZE_CM4 := 0x400 +export VECT_BASE_CM4 := 0x10002000 +export RAM_VECT_BASE_CM4 := 0x08002000 +export VECT_SIZE_CM4 := 0x000002FC +export TEXT_BASE_CM4 := 0x100022FC +export TEXT_SIZE_CM4 := 0x0003E000 +export RAM_BASE_CM4 := 0x080022FC +export RAM_SIZE_CM4 := 0x0001D800 +export CYMETA_BASE_CM4 := 0x90500000 +export STACK_SIZE_CM4 := 0x2000 +STACK_ADDRESS_TOP_CM4 := $(shell printf "0x%x" $$(($(RAM_VECT_BASE_CM4) + $(RAM_SIZE_CM4)))) +STACK_ADDRESS_BOTTOM_CM4 := $(shell printf "0x%x" $$(($(STACK_ADDRESS_TOP_CM4) - $(STACK_SIZE_CM4)))) +TOOLCHAIN_VECT_BASE_CM4 := $(VECT_BASE_CM4) + +SECTIONS_CM4 := \ + -segaddr __CY_M0P_IMAGE $(VECT_BASE_CM0P) \ + -segaddr __VECT $(VECT_BASE_CM4) \ + -segaddr __TEXT $(TEXT_BASE_CM4) \ + -segaddr __DATA $(RAM_BASE_CM4) \ + -segaddr __RAMVECTORS $(RAM_VECT_BASE_CM4) \ + -segaddr __CYMETA $(CYMETA_BASE_CM4) \ + -segaddr __STACK $(STACK_ADDRESS_TOP_CM4) + +# Pass section addresses to the linker +ifeq ($(CORE),CM4) +LDFLAGS += \ + -segalign 4 \ + $(SECTIONS_CM4) +else ifeq ($(CORE),CM0P) +LDFLAGS += \ + -segalign 4 \ + $(SECTIONS_CM0P) +endif + +# EOF diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx5_cm4_dual.mk b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx5_cm4_dual.mk index 3d54b9f..21ce6bc 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx5_cm4_dual.mk +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx5_cm4_dual.mk @@ -1,6 +1,6 @@ ################################################################################ # \file cy8c6xx5_cm4_dual.mk -# \version 2.70 +# \version 2.70.1 # # \brief # Specifies the starting address and the size of the segments in the output @@ -11,7 +11,7 @@ # ################################################################################ # \copyright -# Copyright 2018-2019 Cypress Semiconductor Corporation +# Copyright 2018-2020 Cypress Semiconductor Corporation # SPDX-License-Identifier: Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx6_cm4.mk b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx6_cm4.mk index fe29c43..c7ec81c 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx6_cm4.mk +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx6_cm4.mk @@ -1,6 +1,6 @@ ################################################################################ # \file cy8c6xx6_cm4.mk -# \version 2.70 +# \version 2.70.1 # # \brief # Specifies the starting address and the size of the segments in the output @@ -11,7 +11,7 @@ # ################################################################################ # \copyright -# Copyright 2018-2019 Cypress Semiconductor Corporation +# Copyright 2018-2020 Cypress Semiconductor Corporation # SPDX-License-Identifier: Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx6_cm4_dual.mk b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx6_cm4_dual.mk index 5c158bc..6596ec1 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx6_cm4_dual.mk +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx6_cm4_dual.mk @@ -1,6 +1,6 @@ ################################################################################ # \file cy8c6xx6_cm4_dual.mk -# \version 2.70 +# \version 2.70.1 # # \brief # Specifies the starting address and the size of the segments in the output @@ -11,7 +11,7 @@ # ################################################################################ # \copyright -# Copyright 2018-2019 Cypress Semiconductor Corporation +# Copyright 2018-2020 Cypress Semiconductor Corporation # SPDX-License-Identifier: Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx7_cm4.mk b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx7_cm4.mk index 8fa9337..f01d8ba 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx7_cm4.mk +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx7_cm4.mk @@ -1,6 +1,6 @@ ################################################################################ # \file cy8c6xx7_cm4.mk -# \version 2.70 +# \version 2.70.1 # # \brief # Specifies the starting address and the size of the segments in the output @@ -11,7 +11,7 @@ # ################################################################################ # \copyright -# Copyright 2018-2019 Cypress Semiconductor Corporation +# Copyright 2018-2020 Cypress Semiconductor Corporation # SPDX-License-Identifier: Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx7_cm4_dual.mk b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx7_cm4_dual.mk index 495c6ce..20b0085 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx7_cm4_dual.mk +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx7_cm4_dual.mk @@ -1,6 +1,6 @@ ################################################################################ # \file cy8c6xx7_cm4_dual.mk -# \version 2.70 +# \version 2.70.1 # # \brief # Specifies the starting address and the size of the segments in the output @@ -11,7 +11,7 @@ # ################################################################################ # \copyright -# Copyright 2018-2019 Cypress Semiconductor Corporation +# Copyright 2018-2020 Cypress Semiconductor Corporation # SPDX-License-Identifier: Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx8_cm4_dual.mk b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx8_cm4_dual.mk index 598c856..65cebd4 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx8_cm4_dual.mk +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xx8_cm4_dual.mk @@ -1,6 +1,6 @@ ################################################################################ # \file cy8c6xx8_cm4_dual.mk -# \version 2.70 +# \version 2.70.1 # # \brief # Specifies the starting address and the size of the segments in the output @@ -11,7 +11,7 @@ # ################################################################################ # \copyright -# Copyright 2018-2019 Cypress Semiconductor Corporation +# Copyright 2018-2020 Cypress Semiconductor Corporation # SPDX-License-Identifier: Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xxa_cm4_dual.mk b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xxa_cm4_dual.mk index 9fff442..0be43ea 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xxa_cm4_dual.mk +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/cy8c6xxa_cm4_dual.mk @@ -1,6 +1,6 @@ ################################################################################ # \file cy8c6xxa_cm4_dual.mk -# \version 2.70 +# \version 2.70.1 # # \brief # Specifies the starting address and the size of the segments in the output @@ -11,7 +11,7 @@ # ################################################################################ # \copyright -# Copyright 2018-2019 Cypress Semiconductor Corporation +# Copyright 2018-2020 Cypress Semiconductor Corporation # SPDX-License-Identifier: Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/startup_psoc6_04_cm4.S b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/startup_psoc6_04_cm4.S new file mode 100644 index 0000000..86f1f24 --- /dev/null +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_A_Clang/startup_psoc6_04_cm4.S @@ -0,0 +1,543 @@ +/**************************************************************************//** + * @file startup_psoc6_04_cm4.S + * @brief CMSIS Core Device Startup File for + * ARMCM4 Device Series + * @version V5.00 + * @date 02. March 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + /* Address of the NMI handler */ + #define CY_NMI_HANLDER_ADDR 0x0000000D + + /* The CPU VTOR register */ + #define CY_CPU_VTOR_ADDR 0xE000ED08 + + .syntax unified + .section __STACK , __stack + .align 3 + +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x00001000 +#endif + .globl __StackTop + .globl __StackLimit + +__StackLimit: + .space Stack_Size + .equ __StackTop, . - Stack_Size + + .section __HEAP, __heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x00000400 +#endif + .globl __HeapBase +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + + .section __VECT, ___Vectors + .align 2 + .globl ___Vectors +___Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long CY_NMI_HANLDER_ADDR /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts Description */ + .long ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ + .long 0 /* Reserved */ + .long ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ + .long ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ + .long 0 /* Reserved */ + .long ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ + .long ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ + .long ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ + .long ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ + .long ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ + .long ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ + .long ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ + .long ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ + .long 0 /* Reserved */ + .long ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ + .long ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ + .long ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ + .long lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ + .long scb_6_interrupt_IRQHandler /* Serial Communication Block #6 (DeepSleep capable) */ + .long srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + .long srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + .long srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ + .long srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + .long cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ + .long cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ + .long cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ + .long cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ + .long cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ + .long cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ + .long cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ + .long cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ + .long cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ + .long cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ + .long cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ + .long cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ + .long cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ + .long cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ + .long cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ + .long cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ + .long pass_interrupt_sar_0_IRQHandler /* SAR ADC0 interrupt */ + .long pass_interrupt_sar_1_IRQHandler /* SAR ADC1 interrupt */ + .long pass_interrupt_ctb_IRQHandler /* individual interrupt per CTB */ + .long 0 /* Reserved */ + .long pass_interrupt_fifo_0_IRQHandler /* PASS FIFO0 */ + .long pass_interrupt_fifo_1_IRQHandler /* PASS FIFO1 */ + .long scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ + .long scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ + .long scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ + .long 0 /* Reserved */ + .long scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ + .long scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ + .long csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ + .long cpuss_interrupts_dmac_0_IRQHandler /* CPUSS DMAC, Channel #0 */ + .long cpuss_interrupts_dmac_1_IRQHandler /* CPUSS DMAC, Channel #1 */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ + .long cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ + .long cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ + .long cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ + .long cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ + .long cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ + .long cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ + .long cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ + .long cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ + .long cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ + .long cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ + .long cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ + .long cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ + .long cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ + .long cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ + .long cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ + .long cpuss_interrupts_dw0_16_IRQHandler /* CPUSS DataWire #0, Channel #16 */ + .long cpuss_interrupts_dw0_17_IRQHandler /* CPUSS DataWire #0, Channel #17 */ + .long cpuss_interrupts_dw0_18_IRQHandler /* CPUSS DataWire #0, Channel #18 */ + .long cpuss_interrupts_dw0_19_IRQHandler /* CPUSS DataWire #0, Channel #19 */ + .long cpuss_interrupts_dw0_20_IRQHandler /* CPUSS DataWire #0, Channel #20 */ + .long cpuss_interrupts_dw0_21_IRQHandler /* CPUSS DataWire #0, Channel #21 */ + .long cpuss_interrupts_dw0_22_IRQHandler /* CPUSS DataWire #0, Channel #22 */ + .long cpuss_interrupts_dw0_23_IRQHandler /* CPUSS DataWire #0, Channel #23 */ + .long cpuss_interrupts_dw0_24_IRQHandler /* CPUSS DataWire #0, Channel #24 */ + .long cpuss_interrupts_dw0_25_IRQHandler /* CPUSS DataWire #0, Channel #25 */ + .long cpuss_interrupts_dw0_26_IRQHandler /* CPUSS DataWire #0, Channel #26 */ + .long cpuss_interrupts_dw0_27_IRQHandler /* CPUSS DataWire #0, Channel #27 */ + .long cpuss_interrupts_dw0_28_IRQHandler /* CPUSS DataWire #0, Channel #28 */ + .long cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ + .long cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ + .long cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ + .long cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ + .long cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ + .long cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ + .long cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ + .long cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ + .long cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ + .long cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ + .long cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ + .long cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ + .long cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ + .long cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ + .long cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ + .long cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ + .long cpuss_interrupts_dw1_16_IRQHandler /* CPUSS DataWire #1, Channel #16 */ + .long cpuss_interrupts_dw1_17_IRQHandler /* CPUSS DataWire #1, Channel #17 */ + .long cpuss_interrupts_dw1_18_IRQHandler /* CPUSS DataWire #1, Channel #18 */ + .long cpuss_interrupts_dw1_19_IRQHandler /* CPUSS DataWire #1, Channel #19 */ + .long cpuss_interrupts_dw1_20_IRQHandler /* CPUSS DataWire #1, Channel #20 */ + .long cpuss_interrupts_dw1_21_IRQHandler /* CPUSS DataWire #1, Channel #21 */ + .long cpuss_interrupts_dw1_22_IRQHandler /* CPUSS DataWire #1, Channel #22 */ + .long cpuss_interrupts_dw1_23_IRQHandler /* CPUSS DataWire #1, Channel #23 */ + .long cpuss_interrupts_dw1_24_IRQHandler /* CPUSS DataWire #1, Channel #24 */ + .long cpuss_interrupts_dw1_25_IRQHandler /* CPUSS DataWire #1, Channel #25 */ + .long cpuss_interrupts_dw1_26_IRQHandler /* CPUSS DataWire #1, Channel #26 */ + .long cpuss_interrupts_dw1_27_IRQHandler /* CPUSS DataWire #1, Channel #27 */ + .long cpuss_interrupts_dw1_28_IRQHandler /* CPUSS DataWire #1, Channel #28 */ + .long cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ + .long cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ + .long cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ + .long cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ + .long cpuss_interrupts_cm4_fp_IRQHandler /* Floating Point operation fault */ + .long cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ + .long cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ + .long cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ + .long cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ + .long tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ + .long tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ + .long tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ + .long tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long tcpwm_0_interrupts_256_IRQHandler /* TCPWM #0, Counter #256 */ + .long tcpwm_0_interrupts_257_IRQHandler /* TCPWM #0, Counter #257 */ + .long tcpwm_0_interrupts_258_IRQHandler /* TCPWM #0, Counter #258 */ + .long tcpwm_0_interrupts_259_IRQHandler /* TCPWM #0, Counter #259 */ + .long tcpwm_0_interrupts_260_IRQHandler /* TCPWM #0, Counter #260 */ + .long tcpwm_0_interrupts_261_IRQHandler /* TCPWM #0, Counter #261 */ + .long tcpwm_0_interrupts_262_IRQHandler /* TCPWM #0, Counter #262 */ + .long tcpwm_0_interrupts_263_IRQHandler /* TCPWM #0, Counter #263 */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long pass_interrupt_dacs_IRQHandler /* Consolidated interrrupt for all DACs */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ + .long usb_interrupt_hi_IRQHandler /* USB Interrupt */ + .long usb_interrupt_med_IRQHandler /* USB Interrupt */ + .long usb_interrupt_lo_IRQHandler /* USB Interrupt */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long canfd_0_interrupt0_IRQHandler /* Can #0, Consolidated interrupt #0 */ + .long canfd_0_interrupts0_0_IRQHandler /* CAN #0, Interrupt #0, Channel #0 */ + .long canfd_0_interrupts1_0_IRQHandler /* CAN #0, Interrupt #1, Channel #0 */ + .long cpuss_interrupts_dw1_29_IRQHandler /* CPUSS DataWire #1, Channel #29 */ + .long cpuss_interrupts_dw1_30_IRQHandler /* CPUSS DataWire #1, Channel #30 */ + .long cpuss_interrupts_dw1_31_IRQHandler /* CPUSS DataWire #1, Channel #31 */ + .long cpuss_interrupts_dw0_29_IRQHandler /* CPUSS DataWire #0, Channel #29 */ + + .equ __VectorsSize, . - ___Vectors + + .section __RAMVECTORS, ___ramVectors + .align 2 + .globl ___ramVectors + +___ramVectors: + .space __VectorsSize + + + .text + .thumb_func + .align 2 + /* Reset handler */ + .globl Reset_Handler + +Reset_Handler: + bl Cy_OnResetUser + cpsid i + +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r0, =___ramVectors + ldr r1, =___Vectors + ldr r2, =__VectorsSize + bl _memcpy + + ldr r0, =segment$start$__DATA + ldr r1, =segment$end$__TEXT + ldr r2, =section$start$__DATA$__zerofill + sub r2, r0 + bl _memcpy + + ldr r0, =section$start$__DATA$__zerofill + eor r1, r1 + ldr r2, =section$end$__DATA$__zerofill + sub r2, r0 + bl _memset + + /* Update Vector Table Offset Register. */ + ldr r0, =___ramVectors + ldr r1, =CY_CPU_VTOR_ADDR + str r0, [r1] + dsb 0xF + + /* Enable the FPU if used */ + bl _Cy_SystemInitFpuEnable + + bl _HeapInit +#ifndef __NO_SYSTEM_INIT + bl _SystemInit +#endif + + bl _main + + /* Should never get here */ + b . + + .pool + + .text + .thumb + .thumb_func + .align 2 + + /* Device startup customization */ + .weak_definition Cy_OnResetUser + .global Cy_OnResetUser, Cy_OnResetUser +Cy_OnResetUser: + bx lr + + .text + .align 1 + .thumb_func + .weak_reference Default_Handler + +Default_Handler: + b . + + .text + .thumb_func + .align 2 + .weak_definition Cy_SysLib_FaultHandler + +Cy_SysLib_FaultHandler: + b . + + .text + .thumb_func + .align 2 + +Fault_Handler: + /* Storing LR content for Creator call stack trace */ + push {LR} + movs r0, #4 + mov r1, LR + tst r0, r1 + beq .L_MSP + mrs r0, PSP + b .L_API_call +.L_MSP: + mrs r0, MSP +.L_API_call: + /* Compensation of stack pointer address due to pushing 4 bytes of LR */ + adds r0, r0, #4 + bl Cy_SysLib_FaultHandler + b . + +.macro def_fault_Handler fault_handler_name + .weak_definition \fault_handler_name + .set \fault_handler_name, Fault_Handler + .endm + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak_definition \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + + def_fault_Handler HardFault_Handler + def_fault_Handler MemManage_Handler + def_fault_Handler BusFault_Handler + def_fault_Handler UsageFault_Handler + + def_irq_handler SVC_Handler + def_irq_handler DebugMon_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ + def_irq_handler ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ + def_irq_handler ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ + def_irq_handler ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ + def_irq_handler ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ + def_irq_handler ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ + def_irq_handler ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ + def_irq_handler ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ + def_irq_handler ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ + def_irq_handler ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ + def_irq_handler ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ + def_irq_handler ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ + def_irq_handler ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ + def_irq_handler ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ + def_irq_handler lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ + def_irq_handler scb_6_interrupt_IRQHandler /* Serial Communication Block #6 (DeepSleep capable) */ + def_irq_handler srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + def_irq_handler srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + def_irq_handler srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ + def_irq_handler srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + def_irq_handler cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ + def_irq_handler cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ + def_irq_handler cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ + def_irq_handler cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ + def_irq_handler cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ + def_irq_handler cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ + def_irq_handler cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ + def_irq_handler cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ + def_irq_handler cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ + def_irq_handler cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ + def_irq_handler cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ + def_irq_handler cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ + def_irq_handler cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ + def_irq_handler cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ + def_irq_handler cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ + def_irq_handler cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ + def_irq_handler pass_interrupt_sar_0_IRQHandler /* SAR ADC0 interrupt */ + def_irq_handler pass_interrupt_sar_1_IRQHandler /* SAR ADC1 interrupt */ + def_irq_handler pass_interrupt_ctb_IRQHandler /* individual interrupt per CTB */ + def_irq_handler pass_interrupt_fifo_0_IRQHandler /* PASS FIFO0 */ + def_irq_handler pass_interrupt_fifo_1_IRQHandler /* PASS FIFO1 */ + def_irq_handler scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ + def_irq_handler scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ + def_irq_handler scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ + def_irq_handler scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ + def_irq_handler scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ + def_irq_handler csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ + def_irq_handler cpuss_interrupts_dmac_0_IRQHandler /* CPUSS DMAC, Channel #0 */ + def_irq_handler cpuss_interrupts_dmac_1_IRQHandler /* CPUSS DMAC, Channel #1 */ + def_irq_handler cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ + def_irq_handler cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ + def_irq_handler cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ + def_irq_handler cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ + def_irq_handler cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ + def_irq_handler cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ + def_irq_handler cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ + def_irq_handler cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ + def_irq_handler cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ + def_irq_handler cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ + def_irq_handler cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ + def_irq_handler cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ + def_irq_handler cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ + def_irq_handler cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ + def_irq_handler cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ + def_irq_handler cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ + def_irq_handler cpuss_interrupts_dw0_16_IRQHandler /* CPUSS DataWire #0, Channel #16 */ + def_irq_handler cpuss_interrupts_dw0_17_IRQHandler /* CPUSS DataWire #0, Channel #17 */ + def_irq_handler cpuss_interrupts_dw0_18_IRQHandler /* CPUSS DataWire #0, Channel #18 */ + def_irq_handler cpuss_interrupts_dw0_19_IRQHandler /* CPUSS DataWire #0, Channel #19 */ + def_irq_handler cpuss_interrupts_dw0_20_IRQHandler /* CPUSS DataWire #0, Channel #20 */ + def_irq_handler cpuss_interrupts_dw0_21_IRQHandler /* CPUSS DataWire #0, Channel #21 */ + def_irq_handler cpuss_interrupts_dw0_22_IRQHandler /* CPUSS DataWire #0, Channel #22 */ + def_irq_handler cpuss_interrupts_dw0_23_IRQHandler /* CPUSS DataWire #0, Channel #23 */ + def_irq_handler cpuss_interrupts_dw0_24_IRQHandler /* CPUSS DataWire #0, Channel #24 */ + def_irq_handler cpuss_interrupts_dw0_25_IRQHandler /* CPUSS DataWire #0, Channel #25 */ + def_irq_handler cpuss_interrupts_dw0_26_IRQHandler /* CPUSS DataWire #0, Channel #26 */ + def_irq_handler cpuss_interrupts_dw0_27_IRQHandler /* CPUSS DataWire #0, Channel #27 */ + def_irq_handler cpuss_interrupts_dw0_28_IRQHandler /* CPUSS DataWire #0, Channel #28 */ + def_irq_handler cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ + def_irq_handler cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ + def_irq_handler cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ + def_irq_handler cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ + def_irq_handler cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ + def_irq_handler cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ + def_irq_handler cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ + def_irq_handler cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ + def_irq_handler cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ + def_irq_handler cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ + def_irq_handler cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ + def_irq_handler cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ + def_irq_handler cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ + def_irq_handler cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ + def_irq_handler cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ + def_irq_handler cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ + def_irq_handler cpuss_interrupts_dw1_16_IRQHandler /* CPUSS DataWire #1, Channel #16 */ + def_irq_handler cpuss_interrupts_dw1_17_IRQHandler /* CPUSS DataWire #1, Channel #17 */ + def_irq_handler cpuss_interrupts_dw1_18_IRQHandler /* CPUSS DataWire #1, Channel #18 */ + def_irq_handler cpuss_interrupts_dw1_19_IRQHandler /* CPUSS DataWire #1, Channel #19 */ + def_irq_handler cpuss_interrupts_dw1_20_IRQHandler /* CPUSS DataWire #1, Channel #20 */ + def_irq_handler cpuss_interrupts_dw1_21_IRQHandler /* CPUSS DataWire #1, Channel #21 */ + def_irq_handler cpuss_interrupts_dw1_22_IRQHandler /* CPUSS DataWire #1, Channel #22 */ + def_irq_handler cpuss_interrupts_dw1_23_IRQHandler /* CPUSS DataWire #1, Channel #23 */ + def_irq_handler cpuss_interrupts_dw1_24_IRQHandler /* CPUSS DataWire #1, Channel #24 */ + def_irq_handler cpuss_interrupts_dw1_25_IRQHandler /* CPUSS DataWire #1, Channel #25 */ + def_irq_handler cpuss_interrupts_dw1_26_IRQHandler /* CPUSS DataWire #1, Channel #26 */ + def_irq_handler cpuss_interrupts_dw1_27_IRQHandler /* CPUSS DataWire #1, Channel #27 */ + def_irq_handler cpuss_interrupts_dw1_28_IRQHandler /* CPUSS DataWire #1, Channel #28 */ + def_irq_handler cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ + def_irq_handler cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ + def_irq_handler cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ + def_irq_handler cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ + def_irq_handler cpuss_interrupts_cm4_fp_IRQHandler /* Floating Point operation fault */ + def_irq_handler cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ + def_irq_handler cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ + def_irq_handler cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ + def_irq_handler cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ + def_irq_handler tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ + def_irq_handler tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ + def_irq_handler tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ + def_irq_handler tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ + def_irq_handler tcpwm_0_interrupts_256_IRQHandler /* TCPWM #0, Counter #256 */ + def_irq_handler tcpwm_0_interrupts_257_IRQHandler /* TCPWM #0, Counter #257 */ + def_irq_handler tcpwm_0_interrupts_258_IRQHandler /* TCPWM #0, Counter #258 */ + def_irq_handler tcpwm_0_interrupts_259_IRQHandler /* TCPWM #0, Counter #259 */ + def_irq_handler tcpwm_0_interrupts_260_IRQHandler /* TCPWM #0, Counter #260 */ + def_irq_handler tcpwm_0_interrupts_261_IRQHandler /* TCPWM #0, Counter #261 */ + def_irq_handler tcpwm_0_interrupts_262_IRQHandler /* TCPWM #0, Counter #262 */ + def_irq_handler tcpwm_0_interrupts_263_IRQHandler /* TCPWM #0, Counter #263 */ + def_irq_handler pass_interrupt_dacs_IRQHandler /* Consolidated interrrupt for all DACs */ + def_irq_handler smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ + def_irq_handler usb_interrupt_hi_IRQHandler /* USB Interrupt */ + def_irq_handler usb_interrupt_med_IRQHandler /* USB Interrupt */ + def_irq_handler usb_interrupt_lo_IRQHandler /* USB Interrupt */ + def_irq_handler canfd_0_interrupt0_IRQHandler /* Can #0, Consolidated interrupt #0 */ + def_irq_handler canfd_0_interrupts0_0_IRQHandler /* CAN #0, Interrupt #0, Channel #0 */ + def_irq_handler canfd_0_interrupts1_0_IRQHandler /* CAN #0, Interrupt #1, Channel #0 */ + def_irq_handler cpuss_interrupts_dw1_29_IRQHandler /* CPUSS DataWire #1, Channel #29 */ + def_irq_handler cpuss_interrupts_dw1_30_IRQHandler /* CPUSS DataWire #1, Channel #30 */ + def_irq_handler cpuss_interrupts_dw1_31_IRQHandler /* CPUSS DataWire #1, Channel #31 */ + def_irq_handler cpuss_interrupts_dw0_29_IRQHandler /* CPUSS DataWire #0, Channel #29 */ + + .end + + +/* [] END OF FILE */ diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx4_cm4_dual.ld b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx4_cm4_dual.ld new file mode 100644 index 0000000..2bf3299 --- /dev/null +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx4_cm4_dual.ld @@ -0,0 +1,440 @@ +/***************************************************************************//** +* \file cy8c6xx4_cm4_dual.ld +* \version 2.70.1 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + +/* The size of the stack section at the end of CM4 SRAM */ +STACK_SIZE = 0x1000; + +/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p +*/ +/* The size of the Cortex-M0+ application image at the start of FLASH */ +FLASH_CM0P_SIZE = 0x2000; + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing the 'ram' and 'flash' regions. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'. + */ + ram (rwx) : ORIGIN = 0x08002000, LENGTH = 0x1D800 + flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x40000 + + /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ + em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */ + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + /* Cortex-M0+ application flash image area */ + .cy_m0p_image ORIGIN(flash) : + { + . = ALIGN(4); + __cy_m0p_code_start = . ; + KEEP(*(.cy_m0p_image)) + __cy_m0p_code_end = . ; + } > flash + + /* Check if .cy_m0p_image size exceeds FLASH_CM0P_SIZE */ + ASSERT(__cy_m0p_code_end <= ORIGIN(flash) + FLASH_CM0P_SIZE, "CM0+ flash image overflows with CM4, increase FLASH_CM0P_SIZE") + + /* Cortex-M4 application flash area */ + .text ORIGIN(flash) + FLASH_CM0P_SIZE : + { + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_04_cm4.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_04_cm4.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > ram + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Used for the digital signature of the secure application and the Bootloader SDK application. + * The size of the section depends on the required data size. */ + .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 : + { + KEEP(*(.cy_app_signature)) + } > flash + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + .cy_xip : + { + KEEP(*(.cy_xip)) + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x00040000; +__cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +__cy_memory_1_start = 0x14000000; +__cy_memory_1_length = 0x8000; +__cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm4_dual.ld b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm4_dual.ld index 7b9ea66..9070b72 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm4_dual.ld +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm4_dual.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx5_cm4_dual.ld -* \version 2.70 +* \version 2.70.1 * * Linker file for the GNU C compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -43,6 +43,10 @@ ENTRY(Reset_Handler) /* The size of the stack section at the end of CM4 SRAM */ STACK_SIZE = 0x1000; +/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p +*/ /* The size of the Cortex-M0+ application image at the start of FLASH */ FLASH_CM0P_SIZE = 0x2000; diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx6_cm4.ld b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx6_cm4.ld index 1e41911..2efe8e2 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx6_cm4.ld +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx6_cm4.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx6_cm4.ld -* \version 2.70 +* \version 2.70.1 * * Linker file for the GNU C compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx6_cm4_dual.ld b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx6_cm4_dual.ld index 01382f8..95360f5 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx6_cm4_dual.ld +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx6_cm4_dual.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx6_cm4_dual.ld -* \version 2.70 +* \version 2.70.1 * * Linker file for the GNU C compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -43,6 +43,10 @@ ENTRY(Reset_Handler) /* The size of the stack section at the end of CM4 SRAM */ STACK_SIZE = 0x1000; +/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p +*/ /* The size of the Cortex-M0+ application image at the start of FLASH */ FLASH_CM0P_SIZE = 0x2000; diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4.ld b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4.ld index 825375f..a3f4455 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4.ld +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx7_cm4.ld -* \version 2.70 +* \version 2.70.1 * * Linker file for the GNU C compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld index 2d23d29..39b4f82 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx7_cm4_dual.ld -* \version 2.70 +* \version 2.70.1 * * Linker file for the GNU C compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -43,6 +43,10 @@ ENTRY(Reset_Handler) /* The size of the stack section at the end of CM4 SRAM */ STACK_SIZE = 0x1000; +/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p +*/ /* The size of the Cortex-M0+ application image at the start of FLASH */ FLASH_CM0P_SIZE = 0x2000; diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx8_cm4_dual.ld b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx8_cm4_dual.ld index bb27662..6d7c416 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx8_cm4_dual.ld +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx8_cm4_dual.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx8_cm4_dual.ld -* \version 2.70 +* \version 2.70.1 * * Linker file for the GNU C compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -43,6 +43,10 @@ ENTRY(Reset_Handler) /* The size of the stack section at the end of CM4 SRAM */ STACK_SIZE = 0x1000; +/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p +*/ /* The size of the Cortex-M0+ application image at the start of FLASH */ FLASH_CM0P_SIZE = 0x2000; diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld index ec70309..962ff9d 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xxa_cm4_dual.ld -* \version 2.70 +* \version 2.70.1 * * Linker file for the GNU C compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -43,6 +43,10 @@ ENTRY(Reset_Handler) /* The size of the stack section at the end of CM4 SRAM */ STACK_SIZE = 0x1000; +/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p +*/ /* The size of the Cortex-M0+ application image at the start of FLASH */ FLASH_CM0P_SIZE = 0x2000; diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx5_cm4.ld b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx5_cm4.ld index 8979753..e4b014f 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx5_cm4.ld +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx5_cm4.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cyb06xx5_cm4.ld -* \version 2.70 +* \version 2.70.1 * * Linker file for the GNU C compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx5_cm4_dual.ld b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx5_cm4_dual.ld index 594c705..0131584 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx5_cm4_dual.ld +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx5_cm4_dual.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cyb06xx5_cm4_dual.ld -* \version 2.70 +* \version 2.70.1 * * Linker file for the GNU C compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4.ld b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4.ld index 0726ab2..a23e73a 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4.ld +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cyb06xx7_cm4.ld -* \version 2.70 +* \version 2.70.1 * * Linker file for the GNU C compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4_dual.ld b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4_dual.ld index c2e2db4..2c786df 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4_dual.ld +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4_dual.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cyb06xx7_cm4_dual.ld -* \version 2.70 +* \version 2.70.1 * * Linker file for the GNU C compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4.ld b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4.ld index 6f35751..890c460 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4.ld +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cyb06xxa_cm4.ld -* \version 2.70 +* \version 2.70.1 * * Linker file for the GNU C compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4_dual.ld b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4_dual.ld index 926961d..c11e3bb 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4_dual.ld +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4_dual.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cyb06xxa_cm4_dual.ld -* \version 2.70 +* \version 2.70.1 * * Linker file for the GNU C compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_04_cm4.S b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_04_cm4.S new file mode 100644 index 0000000..b9d1083 --- /dev/null +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_04_cm4.S @@ -0,0 +1,676 @@ +/**************************************************************************//** + * @file startup_psoc6_04_cm4.S + * @brief CMSIS Core Device Startup File for + * ARMCM4 Device Series + * @version V5.00 + * @date 02. March 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + /* Address of the NMI handler */ + #define CY_NMI_HANLDER_ADDR 0x0000000D + + /* The CPU VTOR register */ + #define CY_CPU_VTOR_ADDR 0xE000ED08 + + /* Copy flash vectors and data section to RAM */ + #define __STARTUP_COPY_MULTIPLE + + /* Clear single BSS section */ + #define __STARTUP_CLEAR_BSS + + .syntax unified + .arch armv7-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x00001000 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x00000400 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .vectors + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long CY_NMI_HANLDER_ADDR /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts Description */ + .long ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ + .long 0 /* Reserved */ + .long ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ + .long ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ + .long 0 /* Reserved */ + .long ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ + .long ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ + .long ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ + .long ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ + .long ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ + .long ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ + .long ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ + .long ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ + .long 0 /* Reserved */ + .long ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ + .long ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ + .long ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ + .long lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ + .long scb_6_interrupt_IRQHandler /* Serial Communication Block #6 (DeepSleep capable) */ + .long srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + .long srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + .long srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ + .long srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + .long cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ + .long cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ + .long cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ + .long cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ + .long cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ + .long cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ + .long cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ + .long cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ + .long cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ + .long cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ + .long cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ + .long cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ + .long cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ + .long cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ + .long cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ + .long cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ + .long pass_interrupt_sar_0_IRQHandler /* SAR ADC0 interrupt */ + .long pass_interrupt_sar_1_IRQHandler /* SAR ADC1 interrupt */ + .long pass_interrupt_ctb_IRQHandler /* individual interrupt per CTB */ + .long 0 /* Reserved */ + .long pass_interrupt_fifo_0_IRQHandler /* PASS FIFO0 */ + .long pass_interrupt_fifo_1_IRQHandler /* PASS FIFO1 */ + .long scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ + .long scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ + .long scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ + .long 0 /* Reserved */ + .long scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ + .long scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ + .long csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ + .long cpuss_interrupts_dmac_0_IRQHandler /* CPUSS DMAC, Channel #0 */ + .long cpuss_interrupts_dmac_1_IRQHandler /* CPUSS DMAC, Channel #1 */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ + .long cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ + .long cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ + .long cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ + .long cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ + .long cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ + .long cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ + .long cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ + .long cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ + .long cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ + .long cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ + .long cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ + .long cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ + .long cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ + .long cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ + .long cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ + .long cpuss_interrupts_dw0_16_IRQHandler /* CPUSS DataWire #0, Channel #16 */ + .long cpuss_interrupts_dw0_17_IRQHandler /* CPUSS DataWire #0, Channel #17 */ + .long cpuss_interrupts_dw0_18_IRQHandler /* CPUSS DataWire #0, Channel #18 */ + .long cpuss_interrupts_dw0_19_IRQHandler /* CPUSS DataWire #0, Channel #19 */ + .long cpuss_interrupts_dw0_20_IRQHandler /* CPUSS DataWire #0, Channel #20 */ + .long cpuss_interrupts_dw0_21_IRQHandler /* CPUSS DataWire #0, Channel #21 */ + .long cpuss_interrupts_dw0_22_IRQHandler /* CPUSS DataWire #0, Channel #22 */ + .long cpuss_interrupts_dw0_23_IRQHandler /* CPUSS DataWire #0, Channel #23 */ + .long cpuss_interrupts_dw0_24_IRQHandler /* CPUSS DataWire #0, Channel #24 */ + .long cpuss_interrupts_dw0_25_IRQHandler /* CPUSS DataWire #0, Channel #25 */ + .long cpuss_interrupts_dw0_26_IRQHandler /* CPUSS DataWire #0, Channel #26 */ + .long cpuss_interrupts_dw0_27_IRQHandler /* CPUSS DataWire #0, Channel #27 */ + .long cpuss_interrupts_dw0_28_IRQHandler /* CPUSS DataWire #0, Channel #28 */ + .long cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ + .long cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ + .long cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ + .long cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ + .long cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ + .long cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ + .long cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ + .long cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ + .long cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ + .long cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ + .long cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ + .long cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ + .long cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ + .long cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ + .long cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ + .long cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ + .long cpuss_interrupts_dw1_16_IRQHandler /* CPUSS DataWire #1, Channel #16 */ + .long cpuss_interrupts_dw1_17_IRQHandler /* CPUSS DataWire #1, Channel #17 */ + .long cpuss_interrupts_dw1_18_IRQHandler /* CPUSS DataWire #1, Channel #18 */ + .long cpuss_interrupts_dw1_19_IRQHandler /* CPUSS DataWire #1, Channel #19 */ + .long cpuss_interrupts_dw1_20_IRQHandler /* CPUSS DataWire #1, Channel #20 */ + .long cpuss_interrupts_dw1_21_IRQHandler /* CPUSS DataWire #1, Channel #21 */ + .long cpuss_interrupts_dw1_22_IRQHandler /* CPUSS DataWire #1, Channel #22 */ + .long cpuss_interrupts_dw1_23_IRQHandler /* CPUSS DataWire #1, Channel #23 */ + .long cpuss_interrupts_dw1_24_IRQHandler /* CPUSS DataWire #1, Channel #24 */ + .long cpuss_interrupts_dw1_25_IRQHandler /* CPUSS DataWire #1, Channel #25 */ + .long cpuss_interrupts_dw1_26_IRQHandler /* CPUSS DataWire #1, Channel #26 */ + .long cpuss_interrupts_dw1_27_IRQHandler /* CPUSS DataWire #1, Channel #27 */ + .long cpuss_interrupts_dw1_28_IRQHandler /* CPUSS DataWire #1, Channel #28 */ + .long cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ + .long cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ + .long cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ + .long cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ + .long cpuss_interrupts_cm4_fp_IRQHandler /* Floating Point operation fault */ + .long cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ + .long cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ + .long cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ + .long cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ + .long tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ + .long tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ + .long tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ + .long tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long tcpwm_0_interrupts_256_IRQHandler /* TCPWM #0, Counter #256 */ + .long tcpwm_0_interrupts_257_IRQHandler /* TCPWM #0, Counter #257 */ + .long tcpwm_0_interrupts_258_IRQHandler /* TCPWM #0, Counter #258 */ + .long tcpwm_0_interrupts_259_IRQHandler /* TCPWM #0, Counter #259 */ + .long tcpwm_0_interrupts_260_IRQHandler /* TCPWM #0, Counter #260 */ + .long tcpwm_0_interrupts_261_IRQHandler /* TCPWM #0, Counter #261 */ + .long tcpwm_0_interrupts_262_IRQHandler /* TCPWM #0, Counter #262 */ + .long tcpwm_0_interrupts_263_IRQHandler /* TCPWM #0, Counter #263 */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long pass_interrupt_dacs_IRQHandler /* Consolidated interrrupt for all DACs */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ + .long usb_interrupt_hi_IRQHandler /* USB Interrupt */ + .long usb_interrupt_med_IRQHandler /* USB Interrupt */ + .long usb_interrupt_lo_IRQHandler /* USB Interrupt */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long canfd_0_interrupt0_IRQHandler /* Can #0, Consolidated interrupt #0 */ + .long canfd_0_interrupts0_0_IRQHandler /* CAN #0, Interrupt #0, Channel #0 */ + .long canfd_0_interrupts1_0_IRQHandler /* CAN #0, Interrupt #1, Channel #0 */ + .long cpuss_interrupts_dw1_29_IRQHandler /* CPUSS DataWire #1, Channel #29 */ + .long cpuss_interrupts_dw1_30_IRQHandler /* CPUSS DataWire #1, Channel #30 */ + .long cpuss_interrupts_dw1_31_IRQHandler /* CPUSS DataWire #1, Channel #31 */ + .long cpuss_interrupts_dw0_29_IRQHandler /* CPUSS DataWire #0, Channel #29 */ + + + .size __Vectors, . - __Vectors + .equ __VectorsSize, . - __Vectors + + .section .ram_vectors + .align 2 + .globl __ramVectors +__ramVectors: + .space __VectorsSize + .size __ramVectors, . - __ramVectors + + + .text + .thumb + .thumb_func + .align 2 + + /* + * Device startup customization + * + * Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) + * because this function is executed as the first instruction in the ResetHandler. + * The PDL is also not initialized to use the proper register offsets. + * The user of this function is responsible for initializing the PDL and resources before using them. + */ + .weak Cy_OnResetUser + .func Cy_OnResetUser, Cy_OnResetUser + .type Cy_OnResetUser, %function + +Cy_OnResetUser: + bx lr + .size Cy_OnResetUser, . - Cy_OnResetUser + .endfunc + + /* OS-specific low-level initialization */ + .weak cy_toolchain_init + .func cy_toolchain_init, cy_toolchain_init + .type cy_toolchain_init, %function + +cy_toolchain_init: + bx lr + .size cy_toolchain_init, . - cy_toolchain_init + .endfunc + + /* Reset handler */ + .weak Reset_Handler + .type Reset_Handler, %function + +Reset_Handler: + bl Cy_OnResetUser + cpsid i + +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + ittt ge + ldrge r0, [r1, r3] + strge r0, [r2, r3] + bge .L_loop0_0 + + adds r4, #12 + b .L_loop0 + +.L_loop0_done: +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +.L_loop1: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .L_loop1 +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + itt ge + strge r0, [r1, r2] + bge .L_loop2_0 + + adds r3, #8 + b .L_loop2 +.L_loop2_done: +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.L_loop3: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .L_loop3 +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + + /* Update Vector Table Offset Register. */ + ldr r0, =__ramVectors + ldr r1, =CY_CPU_VTOR_ADDR + str r0, [r1] + dsb 0xF + + /* Enable the FPU if used */ + bl Cy_SystemInitFpuEnable + +#ifndef __NO_SYSTEM_INIT + bl SystemInit +#endif + + /* OS-specific low-level initialization */ + bl cy_toolchain_init + + /* Call C/C++ static constructors */ + bl __libc_init_array + + /* Execute main application */ + bl main + + /* Call C/C++ static destructors */ + bl __libc_fini_array + + /* Should never get here */ + b . + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak Default_Handler + .type Default_Handler, %function + +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + + + .weak Cy_SysLib_FaultHandler + .type Cy_SysLib_FaultHandler, %function + +Cy_SysLib_FaultHandler: + b . + .size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler + .type Fault_Handler, %function + +Fault_Handler: + /* Storing LR content for Creator call stack trace */ + push {LR} + movs r0, #4 + mov r1, LR + tst r0, r1 + beq .L_MSP + mrs r0, PSP + b .L_API_call +.L_MSP: + mrs r0, MSP +.L_API_call: + /* Compensation of stack pointer address due to pushing 4 bytes of LR */ + adds r0, r0, #4 + bl Cy_SysLib_FaultHandler + b . + .size Fault_Handler, . - Fault_Handler + +.macro def_fault_Handler fault_handler_name + .weak \fault_handler_name + .set \fault_handler_name, Fault_Handler + .endm + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + + def_fault_Handler HardFault_Handler + def_fault_Handler MemManage_Handler + def_fault_Handler BusFault_Handler + def_fault_Handler UsageFault_Handler + + def_irq_handler SVC_Handler + def_irq_handler DebugMon_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ + def_irq_handler ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ + def_irq_handler ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ + def_irq_handler ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ + def_irq_handler ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ + def_irq_handler ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ + def_irq_handler ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ + def_irq_handler ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ + def_irq_handler ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ + def_irq_handler ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ + def_irq_handler ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ + def_irq_handler ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ + def_irq_handler ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ + def_irq_handler ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ + def_irq_handler lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ + def_irq_handler scb_6_interrupt_IRQHandler /* Serial Communication Block #6 (DeepSleep capable) */ + def_irq_handler srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + def_irq_handler srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + def_irq_handler srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ + def_irq_handler srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + def_irq_handler cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ + def_irq_handler cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ + def_irq_handler cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ + def_irq_handler cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ + def_irq_handler cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ + def_irq_handler cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ + def_irq_handler cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ + def_irq_handler cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ + def_irq_handler cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ + def_irq_handler cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ + def_irq_handler cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ + def_irq_handler cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ + def_irq_handler cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ + def_irq_handler cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ + def_irq_handler cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ + def_irq_handler cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ + def_irq_handler pass_interrupt_sar_0_IRQHandler /* SAR ADC0 interrupt */ + def_irq_handler pass_interrupt_sar_1_IRQHandler /* SAR ADC1 interrupt */ + def_irq_handler pass_interrupt_ctb_IRQHandler /* individual interrupt per CTB */ + def_irq_handler pass_interrupt_fifo_0_IRQHandler /* PASS FIFO0 */ + def_irq_handler pass_interrupt_fifo_1_IRQHandler /* PASS FIFO1 */ + def_irq_handler scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ + def_irq_handler scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ + def_irq_handler scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ + def_irq_handler scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ + def_irq_handler scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ + def_irq_handler csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ + def_irq_handler cpuss_interrupts_dmac_0_IRQHandler /* CPUSS DMAC, Channel #0 */ + def_irq_handler cpuss_interrupts_dmac_1_IRQHandler /* CPUSS DMAC, Channel #1 */ + def_irq_handler cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ + def_irq_handler cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ + def_irq_handler cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ + def_irq_handler cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ + def_irq_handler cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ + def_irq_handler cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ + def_irq_handler cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ + def_irq_handler cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ + def_irq_handler cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ + def_irq_handler cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ + def_irq_handler cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ + def_irq_handler cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ + def_irq_handler cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ + def_irq_handler cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ + def_irq_handler cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ + def_irq_handler cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ + def_irq_handler cpuss_interrupts_dw0_16_IRQHandler /* CPUSS DataWire #0, Channel #16 */ + def_irq_handler cpuss_interrupts_dw0_17_IRQHandler /* CPUSS DataWire #0, Channel #17 */ + def_irq_handler cpuss_interrupts_dw0_18_IRQHandler /* CPUSS DataWire #0, Channel #18 */ + def_irq_handler cpuss_interrupts_dw0_19_IRQHandler /* CPUSS DataWire #0, Channel #19 */ + def_irq_handler cpuss_interrupts_dw0_20_IRQHandler /* CPUSS DataWire #0, Channel #20 */ + def_irq_handler cpuss_interrupts_dw0_21_IRQHandler /* CPUSS DataWire #0, Channel #21 */ + def_irq_handler cpuss_interrupts_dw0_22_IRQHandler /* CPUSS DataWire #0, Channel #22 */ + def_irq_handler cpuss_interrupts_dw0_23_IRQHandler /* CPUSS DataWire #0, Channel #23 */ + def_irq_handler cpuss_interrupts_dw0_24_IRQHandler /* CPUSS DataWire #0, Channel #24 */ + def_irq_handler cpuss_interrupts_dw0_25_IRQHandler /* CPUSS DataWire #0, Channel #25 */ + def_irq_handler cpuss_interrupts_dw0_26_IRQHandler /* CPUSS DataWire #0, Channel #26 */ + def_irq_handler cpuss_interrupts_dw0_27_IRQHandler /* CPUSS DataWire #0, Channel #27 */ + def_irq_handler cpuss_interrupts_dw0_28_IRQHandler /* CPUSS DataWire #0, Channel #28 */ + def_irq_handler cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ + def_irq_handler cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ + def_irq_handler cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ + def_irq_handler cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ + def_irq_handler cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ + def_irq_handler cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ + def_irq_handler cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ + def_irq_handler cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ + def_irq_handler cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ + def_irq_handler cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ + def_irq_handler cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ + def_irq_handler cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ + def_irq_handler cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ + def_irq_handler cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ + def_irq_handler cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ + def_irq_handler cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ + def_irq_handler cpuss_interrupts_dw1_16_IRQHandler /* CPUSS DataWire #1, Channel #16 */ + def_irq_handler cpuss_interrupts_dw1_17_IRQHandler /* CPUSS DataWire #1, Channel #17 */ + def_irq_handler cpuss_interrupts_dw1_18_IRQHandler /* CPUSS DataWire #1, Channel #18 */ + def_irq_handler cpuss_interrupts_dw1_19_IRQHandler /* CPUSS DataWire #1, Channel #19 */ + def_irq_handler cpuss_interrupts_dw1_20_IRQHandler /* CPUSS DataWire #1, Channel #20 */ + def_irq_handler cpuss_interrupts_dw1_21_IRQHandler /* CPUSS DataWire #1, Channel #21 */ + def_irq_handler cpuss_interrupts_dw1_22_IRQHandler /* CPUSS DataWire #1, Channel #22 */ + def_irq_handler cpuss_interrupts_dw1_23_IRQHandler /* CPUSS DataWire #1, Channel #23 */ + def_irq_handler cpuss_interrupts_dw1_24_IRQHandler /* CPUSS DataWire #1, Channel #24 */ + def_irq_handler cpuss_interrupts_dw1_25_IRQHandler /* CPUSS DataWire #1, Channel #25 */ + def_irq_handler cpuss_interrupts_dw1_26_IRQHandler /* CPUSS DataWire #1, Channel #26 */ + def_irq_handler cpuss_interrupts_dw1_27_IRQHandler /* CPUSS DataWire #1, Channel #27 */ + def_irq_handler cpuss_interrupts_dw1_28_IRQHandler /* CPUSS DataWire #1, Channel #28 */ + def_irq_handler cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ + def_irq_handler cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ + def_irq_handler cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ + def_irq_handler cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ + def_irq_handler cpuss_interrupts_cm4_fp_IRQHandler /* Floating Point operation fault */ + def_irq_handler cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ + def_irq_handler cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ + def_irq_handler cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ + def_irq_handler cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ + def_irq_handler tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ + def_irq_handler tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ + def_irq_handler tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ + def_irq_handler tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ + def_irq_handler tcpwm_0_interrupts_256_IRQHandler /* TCPWM #0, Counter #256 */ + def_irq_handler tcpwm_0_interrupts_257_IRQHandler /* TCPWM #0, Counter #257 */ + def_irq_handler tcpwm_0_interrupts_258_IRQHandler /* TCPWM #0, Counter #258 */ + def_irq_handler tcpwm_0_interrupts_259_IRQHandler /* TCPWM #0, Counter #259 */ + def_irq_handler tcpwm_0_interrupts_260_IRQHandler /* TCPWM #0, Counter #260 */ + def_irq_handler tcpwm_0_interrupts_261_IRQHandler /* TCPWM #0, Counter #261 */ + def_irq_handler tcpwm_0_interrupts_262_IRQHandler /* TCPWM #0, Counter #262 */ + def_irq_handler tcpwm_0_interrupts_263_IRQHandler /* TCPWM #0, Counter #263 */ + def_irq_handler pass_interrupt_dacs_IRQHandler /* Consolidated interrrupt for all DACs */ + def_irq_handler smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ + def_irq_handler usb_interrupt_hi_IRQHandler /* USB Interrupt */ + def_irq_handler usb_interrupt_med_IRQHandler /* USB Interrupt */ + def_irq_handler usb_interrupt_lo_IRQHandler /* USB Interrupt */ + def_irq_handler canfd_0_interrupt0_IRQHandler /* Can #0, Consolidated interrupt #0 */ + def_irq_handler canfd_0_interrupts0_0_IRQHandler /* CAN #0, Interrupt #0, Channel #0 */ + def_irq_handler canfd_0_interrupts1_0_IRQHandler /* CAN #0, Interrupt #1, Channel #0 */ + def_irq_handler cpuss_interrupts_dw1_29_IRQHandler /* CPUSS DataWire #1, Channel #29 */ + def_irq_handler cpuss_interrupts_dw1_30_IRQHandler /* CPUSS DataWire #1, Channel #30 */ + def_irq_handler cpuss_interrupts_dw1_31_IRQHandler /* CPUSS DataWire #1, Channel #31 */ + def_irq_handler cpuss_interrupts_dw0_29_IRQHandler /* CPUSS DataWire #0, Channel #29 */ + + .end + + +/* [] END OF FILE */ diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx4_cm4_dual.icf b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx4_cm4_dual.icf new file mode 100644 index 0000000..344a5d0 --- /dev/null +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx4_cm4_dual.icf @@ -0,0 +1,245 @@ +/******************************************************************************* +* \file cy8c6xx4_cm4_dual.icf +* \version 2.70.1 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x0801F7FF; + +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x1003FFFF; + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x160007FF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/*-Sizes-*/ +if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol __ICFEDIT_size_cstack__ = 0x1000; +} else { + define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; +} +define symbol __ICFEDIT_size_proc_stack__ = 0x0; + +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} +/**** End of ICF editor section. ###ICF###*/ + +/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. + * More about CM0+ prebuilt images, see here: + * https://github.com/cypresssemiconductorco/psoc6cm0p + */ +/* The size of the Cortex-M0+ application image */ +define symbol FLASH_CM0P_SIZE = 0x2000; + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; +define block CM0P_RO with size = FLASH_CM0P_SIZE { readonly section .cy_m0p_image }; +define block RO {first section .intvec, readonly}; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M0+ application image */ +place at start of IROM1_region { block CM0P_RO }; + +/* Flash - Cortex-M4 application */ +place in IROM1_region { block RO }; + +/* Used for the digital signature of the secure application and the Bootloader SDK application. */ +".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +".cy_xip" : place at start of EROM1_region { section .cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { readwrite }; +place at end of IRAM1_region { block HSTACK }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_m0p_image, + section .cy_app_signature, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00040000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx5_cm4_dual.icf b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx5_cm4_dual.icf index def0b36..728c0fb 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx5_cm4_dual.icf +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx5_cm4_dual.icf @@ -1,6 +1,6 @@ -/***************************************************************************//** +/******************************************************************************* * \file cy8c6xx5_cm4_dual.icf -* \version 2.70 +* \version 2.70.1 * * Linker file for the IAR compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -54,10 +54,11 @@ define symbol __ICFEDIT_intvec_start__ = 0x00000000; */ /* RAM */ define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000; -define symbol __ICFEDIT_region_IRAM1_end__ = 0x0803F800; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x0803F7FF; + /* Flash */ define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; -define symbol __ICFEDIT_region_IROM1_end__ = 0x10080000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x1007FFFF; /* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. @@ -127,6 +128,10 @@ if (!isdefinedsymbol(__HEAP_SIZE)) { } /**** End of ICF editor section. ###ICF###*/ +/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. + * More about CM0+ prebuilt images, see here: + * https://github.com/cypresssemiconductorco/psoc6cm0p + */ /* The size of the Cortex-M0+ application image */ define symbol FLASH_CM0P_SIZE = 0x2000; diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx6_cm4.icf b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx6_cm4.icf index e433e16..f479e7c 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx6_cm4.icf +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx6_cm4.icf @@ -1,6 +1,6 @@ -/***************************************************************************//** +/******************************************************************************* * \file cy8c6xx6_cm4.icf -* \version 2.70 +* \version 2.70.1 * * Linker file for the IAR compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -49,10 +49,11 @@ define symbol __ICFEDIT_intvec_start__ = 0x00000000; /* RAM */ define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; -define symbol __ICFEDIT_region_IRAM1_end__ = 0x0801F780; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x0801F77F; + /* Flash */ define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; -define symbol __ICFEDIT_region_IROM1_end__ = 0x10080000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x1007FFFF; /* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx6_cm4_dual.icf b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx6_cm4_dual.icf index 60fd088..2ba8c87 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx6_cm4_dual.icf +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx6_cm4_dual.icf @@ -1,6 +1,6 @@ -/***************************************************************************//** +/******************************************************************************* * \file cy8c6xx6_cm4_dual.icf -* \version 2.70 +* \version 2.70.1 * * Linker file for the IAR compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -54,10 +54,11 @@ define symbol __ICFEDIT_intvec_start__ = 0x00000000; */ /* RAM */ define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000; -define symbol __ICFEDIT_region_IRAM1_end__ = 0x0801F800; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x0801F7FF; + /* Flash */ define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; -define symbol __ICFEDIT_region_IROM1_end__ = 0x10080000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x1007FFFF; /* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. @@ -127,6 +128,10 @@ if (!isdefinedsymbol(__HEAP_SIZE)) { } /**** End of ICF editor section. ###ICF###*/ +/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. + * More about CM0+ prebuilt images, see here: + * https://github.com/cypresssemiconductorco/psoc6cm0p + */ /* The size of the Cortex-M0+ application image */ define symbol FLASH_CM0P_SIZE = 0x2000; diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4.icf b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4.icf index 2f95bf9..4af89d8 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4.icf +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4.icf @@ -1,6 +1,6 @@ -/***************************************************************************//** +/******************************************************************************* * \file cy8c6xx7_cm4.icf -* \version 2.70 +* \version 2.70.1 * * Linker file for the IAR compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -49,10 +49,11 @@ define symbol __ICFEDIT_intvec_start__ = 0x00000000; /* RAM */ define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; -define symbol __ICFEDIT_region_IRAM1_end__ = 0x08047780; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x0804777F; + /* Flash */ define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; -define symbol __ICFEDIT_region_IROM1_end__ = 0x10100000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x100FFFFF; /* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf index 227f659..bb93cf4 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf @@ -1,6 +1,6 @@ -/***************************************************************************//** +/******************************************************************************* * \file cy8c6xx7_cm4_dual.icf -* \version 2.70 +* \version 2.70.1 * * Linker file for the IAR compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -54,10 +54,11 @@ define symbol __ICFEDIT_intvec_start__ = 0x00000000; */ /* RAM */ define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000; -define symbol __ICFEDIT_region_IRAM1_end__ = 0x08047800; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x080477FF; + /* Flash */ define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; -define symbol __ICFEDIT_region_IROM1_end__ = 0x10100000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x100FFFFF; /* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. @@ -127,6 +128,10 @@ if (!isdefinedsymbol(__HEAP_SIZE)) { } /**** End of ICF editor section. ###ICF###*/ +/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. + * More about CM0+ prebuilt images, see here: + * https://github.com/cypresssemiconductorco/psoc6cm0p + */ /* The size of the Cortex-M0+ application image */ define symbol FLASH_CM0P_SIZE = 0x2000; diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx8_cm4_dual.icf b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx8_cm4_dual.icf index 438512c..9a4a27d 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx8_cm4_dual.icf +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx8_cm4_dual.icf @@ -1,6 +1,6 @@ -/***************************************************************************//** +/******************************************************************************* * \file cy8c6xx8_cm4_dual.icf -* \version 2.70 +* \version 2.70.1 * * Linker file for the IAR compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -54,10 +54,11 @@ define symbol __ICFEDIT_intvec_start__ = 0x00000000; */ /* RAM */ define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000; -define symbol __ICFEDIT_region_IRAM1_end__ = 0x0807F800; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x0807F7FF; + /* Flash */ define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; -define symbol __ICFEDIT_region_IROM1_end__ = 0x10100000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x100FFFFF; /* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. @@ -127,6 +128,10 @@ if (!isdefinedsymbol(__HEAP_SIZE)) { } /**** End of ICF editor section. ###ICF###*/ +/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. + * More about CM0+ prebuilt images, see here: + * https://github.com/cypresssemiconductorco/psoc6cm0p + */ /* The size of the Cortex-M0+ application image */ define symbol FLASH_CM0P_SIZE = 0x2000; diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf index 52177fa..46bb06d 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf @@ -1,6 +1,6 @@ -/***************************************************************************//** +/******************************************************************************* * \file cy8c6xxa_cm4_dual.icf -* \version 2.70 +* \version 2.70.1 * * Linker file for the IAR compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -54,10 +54,11 @@ define symbol __ICFEDIT_intvec_start__ = 0x00000000; */ /* RAM */ define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000; -define symbol __ICFEDIT_region_IRAM1_end__ = 0x080FF800; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x080FF7FF; + /* Flash */ define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; -define symbol __ICFEDIT_region_IROM1_end__ = 0x10200000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x101FFFFF; /* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. @@ -127,6 +128,10 @@ if (!isdefinedsymbol(__HEAP_SIZE)) { } /**** End of ICF editor section. ###ICF###*/ +/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. + * More about CM0+ prebuilt images, see here: + * https://github.com/cypresssemiconductorco/psoc6cm0p + */ /* The size of the Cortex-M0+ application image */ define symbol FLASH_CM0P_SIZE = 0x2000; diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx5_cm4.icf b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx5_cm4.icf index 4205e23..625281d 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx5_cm4.icf +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx5_cm4.icf @@ -1,6 +1,6 @@ -/***************************************************************************//** +/******************************************************************************* * \file cyb06xx5_cm4.icf -* \version 2.70 +* \version 2.70.1 * * Linker file for the IAR compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -46,10 +46,11 @@ define symbol __ICFEDIT_intvec_start__ = 0x00000000; */ /* RAM */ define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; -define symbol __ICFEDIT_region_IRAM1_end__ = 0x0802A000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x08029FFF; + /* Flash */ define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; -define symbol __ICFEDIT_region_IROM1_end__ = 0x10060000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x1005FFFF; /* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx5_cm4_dual.icf b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx5_cm4_dual.icf index 3954305..a86e63b 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx5_cm4_dual.icf +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx5_cm4_dual.icf @@ -1,6 +1,6 @@ -/***************************************************************************//** +/******************************************************************************* * \file cyb06xx5_cm4_dual.icf -* \version 2.70 +* \version 2.70.1 * * Linker file for the IAR compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -52,10 +52,11 @@ define symbol __ICFEDIT_intvec_start__ = 0x00000000; */ /* RAM */ define symbol __ICFEDIT_region_IRAM1_start__ = 0x08010000; -define symbol __ICFEDIT_region_IRAM1_end__ = 0x0802A000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x08029FFF; + /* Flash */ define symbol __ICFEDIT_region_IROM1_start__ = 0x10010000; -define symbol __ICFEDIT_region_IROM1_end__ = 0x10030000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x1002FFFF; /* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx7_cm4.icf b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx7_cm4.icf index 3e7e32e..d7d385e 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx7_cm4.icf +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx7_cm4.icf @@ -1,6 +1,6 @@ -/***************************************************************************//** +/******************************************************************************* * \file cyb06xx7_cm4.icf -* \version 2.70 +* \version 2.70.1 * * Linker file for the IAR compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -46,10 +46,11 @@ define symbol __ICFEDIT_intvec_start__ = 0x00000000; */ /* RAM */ define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; -define symbol __ICFEDIT_region_IRAM1_end__ = 0x0802A000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x08029FFF; + /* Flash */ define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; -define symbol __ICFEDIT_region_IROM1_end__ = 0x100D0000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x100CFFFF; /* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx7_cm4_dual.icf b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx7_cm4_dual.icf index b19511f..17db8d6 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx7_cm4_dual.icf +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx7_cm4_dual.icf @@ -1,6 +1,6 @@ -/***************************************************************************//** +/******************************************************************************* * \file cyb06xx7_cm4_dual.icf -* \version 2.70 +* \version 2.70.1 * * Linker file for the IAR compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -52,10 +52,11 @@ define symbol __ICFEDIT_intvec_start__ = 0x00000000; */ /* RAM */ define symbol __ICFEDIT_region_IRAM1_start__ = 0x08010000; -define symbol __ICFEDIT_region_IRAM1_end__ = 0x0802A000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x08029FFF; + /* Flash */ define symbol __ICFEDIT_region_IROM1_start__ = 0x10020000; -define symbol __ICFEDIT_region_IROM1_end__ = 0x10060000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x1005FFFF; /* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xxa_cm4.icf b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xxa_cm4.icf index 7c69a32..972b2f4 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xxa_cm4.icf +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xxa_cm4.icf @@ -1,6 +1,6 @@ -/***************************************************************************//** +/******************************************************************************* * \file cyb06xxa_cm4.icf -* \version 2.70 +* \version 2.70.1 * * Linker file for the IAR compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -46,10 +46,11 @@ define symbol __ICFEDIT_intvec_start__ = 0x00000000; */ /* RAM */ define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; -define symbol __ICFEDIT_region_IRAM1_end__ = 0x080EA000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x080E9FFF; + /* Flash */ define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; -define symbol __ICFEDIT_region_IROM1_end__ = 0x101D0000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x101CFFFF; /* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xxa_cm4_dual.icf b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xxa_cm4_dual.icf index fef329b..5c1aa41 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xxa_cm4_dual.icf +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xxa_cm4_dual.icf @@ -1,6 +1,6 @@ -/***************************************************************************//** +/******************************************************************************* * \file cyb06xxa_cm4_dual.icf -* \version 2.70 +* \version 2.70.1 * * Linker file for the IAR compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -52,10 +52,11 @@ define symbol __ICFEDIT_intvec_start__ = 0x00000000; */ /* RAM */ define symbol __ICFEDIT_region_IRAM1_start__ = 0x08040000; -define symbol __ICFEDIT_region_IRAM1_end__ = 0x080EA000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x080E9FFF; + /* Flash */ define symbol __ICFEDIT_region_IROM1_start__ = 0x10040000; -define symbol __ICFEDIT_region_IROM1_end__ = 0x100E8000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x100E7FFF; /* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_04_cm4.s b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_04_cm4.s new file mode 100644 index 0000000..4d3f7f6 --- /dev/null +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_04_cm4.s @@ -0,0 +1,1147 @@ +;/**************************************************************************//** +; * @file startup_psoc6_04_cm4.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device Series +; * @version V5.00 +; * @date 08. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + SECTION .intvec_ram:DATA:NOROOT(2) + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + EXTERN Cy_SystemInitFpuEnable + EXTERN __iar_data_init3 + EXTERN __iar_dynamic_initialization + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + PUBLIC __ramVectors + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD 0x0000000D ; NMI_Handler is defined in ROM code + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External interrupts Description + DCD ioss_interrupts_gpio_0_IRQHandler ; GPIO Port Interrupt #0 + DCD 0 ; Reserved + DCD ioss_interrupts_gpio_2_IRQHandler ; GPIO Port Interrupt #2 + DCD ioss_interrupts_gpio_3_IRQHandler ; GPIO Port Interrupt #3 + DCD 0 ; Reserved + DCD ioss_interrupts_gpio_5_IRQHandler ; GPIO Port Interrupt #5 + DCD ioss_interrupts_gpio_6_IRQHandler ; GPIO Port Interrupt #6 + DCD ioss_interrupts_gpio_7_IRQHandler ; GPIO Port Interrupt #7 + DCD ioss_interrupts_gpio_8_IRQHandler ; GPIO Port Interrupt #8 + DCD ioss_interrupts_gpio_9_IRQHandler ; GPIO Port Interrupt #9 + DCD ioss_interrupts_gpio_10_IRQHandler ; GPIO Port Interrupt #10 + DCD ioss_interrupts_gpio_11_IRQHandler ; GPIO Port Interrupt #11 + DCD ioss_interrupts_gpio_12_IRQHandler ; GPIO Port Interrupt #12 + DCD 0 ; Reserved + DCD ioss_interrupts_gpio_14_IRQHandler ; GPIO Port Interrupt #14 + DCD ioss_interrupt_gpio_IRQHandler ; GPIO All Ports + DCD ioss_interrupt_vdd_IRQHandler ; GPIO Supply Detect Interrupt + DCD lpcomp_interrupt_IRQHandler ; Low Power Comparator Interrupt + DCD scb_6_interrupt_IRQHandler ; Serial Communication Block #6 (DeepSleep capable) + DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt + DCD srss_interrupt_IRQHandler ; Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) + DCD cpuss_interrupts_ipc_0_IRQHandler ; CPUSS Inter Process Communication Interrupt #0 + DCD cpuss_interrupts_ipc_1_IRQHandler ; CPUSS Inter Process Communication Interrupt #1 + DCD cpuss_interrupts_ipc_2_IRQHandler ; CPUSS Inter Process Communication Interrupt #2 + DCD cpuss_interrupts_ipc_3_IRQHandler ; CPUSS Inter Process Communication Interrupt #3 + DCD cpuss_interrupts_ipc_4_IRQHandler ; CPUSS Inter Process Communication Interrupt #4 + DCD cpuss_interrupts_ipc_5_IRQHandler ; CPUSS Inter Process Communication Interrupt #5 + DCD cpuss_interrupts_ipc_6_IRQHandler ; CPUSS Inter Process Communication Interrupt #6 + DCD cpuss_interrupts_ipc_7_IRQHandler ; CPUSS Inter Process Communication Interrupt #7 + DCD cpuss_interrupts_ipc_8_IRQHandler ; CPUSS Inter Process Communication Interrupt #8 + DCD cpuss_interrupts_ipc_9_IRQHandler ; CPUSS Inter Process Communication Interrupt #9 + DCD cpuss_interrupts_ipc_10_IRQHandler ; CPUSS Inter Process Communication Interrupt #10 + DCD cpuss_interrupts_ipc_11_IRQHandler ; CPUSS Inter Process Communication Interrupt #11 + DCD cpuss_interrupts_ipc_12_IRQHandler ; CPUSS Inter Process Communication Interrupt #12 + DCD cpuss_interrupts_ipc_13_IRQHandler ; CPUSS Inter Process Communication Interrupt #13 + DCD cpuss_interrupts_ipc_14_IRQHandler ; CPUSS Inter Process Communication Interrupt #14 + DCD cpuss_interrupts_ipc_15_IRQHandler ; CPUSS Inter Process Communication Interrupt #15 + DCD pass_interrupt_sar_0_IRQHandler ; SAR ADC0 interrupt + DCD pass_interrupt_sar_1_IRQHandler ; SAR ADC1 interrupt + DCD pass_interrupt_ctb_IRQHandler ; individual interrupt per CTB + DCD 0 ; Reserved + DCD pass_interrupt_fifo_0_IRQHandler ; PASS FIFO0 + DCD pass_interrupt_fifo_1_IRQHandler ; PASS FIFO1 + DCD scb_0_interrupt_IRQHandler ; Serial Communication Block #0 + DCD scb_1_interrupt_IRQHandler ; Serial Communication Block #1 + DCD scb_2_interrupt_IRQHandler ; Serial Communication Block #2 + DCD 0 ; Reserved + DCD scb_4_interrupt_IRQHandler ; Serial Communication Block #4 + DCD scb_5_interrupt_IRQHandler ; Serial Communication Block #5 + DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt + DCD cpuss_interrupts_dmac_0_IRQHandler ; CPUSS DMAC, Channel #0 + DCD cpuss_interrupts_dmac_1_IRQHandler ; CPUSS DMAC, Channel #1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD cpuss_interrupts_dw0_0_IRQHandler ; CPUSS DataWire #0, Channel #0 + DCD cpuss_interrupts_dw0_1_IRQHandler ; CPUSS DataWire #0, Channel #1 + DCD cpuss_interrupts_dw0_2_IRQHandler ; CPUSS DataWire #0, Channel #2 + DCD cpuss_interrupts_dw0_3_IRQHandler ; CPUSS DataWire #0, Channel #3 + DCD cpuss_interrupts_dw0_4_IRQHandler ; CPUSS DataWire #0, Channel #4 + DCD cpuss_interrupts_dw0_5_IRQHandler ; CPUSS DataWire #0, Channel #5 + DCD cpuss_interrupts_dw0_6_IRQHandler ; CPUSS DataWire #0, Channel #6 + DCD cpuss_interrupts_dw0_7_IRQHandler ; CPUSS DataWire #0, Channel #7 + DCD cpuss_interrupts_dw0_8_IRQHandler ; CPUSS DataWire #0, Channel #8 + DCD cpuss_interrupts_dw0_9_IRQHandler ; CPUSS DataWire #0, Channel #9 + DCD cpuss_interrupts_dw0_10_IRQHandler ; CPUSS DataWire #0, Channel #10 + DCD cpuss_interrupts_dw0_11_IRQHandler ; CPUSS DataWire #0, Channel #11 + DCD cpuss_interrupts_dw0_12_IRQHandler ; CPUSS DataWire #0, Channel #12 + DCD cpuss_interrupts_dw0_13_IRQHandler ; CPUSS DataWire #0, Channel #13 + DCD cpuss_interrupts_dw0_14_IRQHandler ; CPUSS DataWire #0, Channel #14 + DCD cpuss_interrupts_dw0_15_IRQHandler ; CPUSS DataWire #0, Channel #15 + DCD cpuss_interrupts_dw0_16_IRQHandler ; CPUSS DataWire #0, Channel #16 + DCD cpuss_interrupts_dw0_17_IRQHandler ; CPUSS DataWire #0, Channel #17 + DCD cpuss_interrupts_dw0_18_IRQHandler ; CPUSS DataWire #0, Channel #18 + DCD cpuss_interrupts_dw0_19_IRQHandler ; CPUSS DataWire #0, Channel #19 + DCD cpuss_interrupts_dw0_20_IRQHandler ; CPUSS DataWire #0, Channel #20 + DCD cpuss_interrupts_dw0_21_IRQHandler ; CPUSS DataWire #0, Channel #21 + DCD cpuss_interrupts_dw0_22_IRQHandler ; CPUSS DataWire #0, Channel #22 + DCD cpuss_interrupts_dw0_23_IRQHandler ; CPUSS DataWire #0, Channel #23 + DCD cpuss_interrupts_dw0_24_IRQHandler ; CPUSS DataWire #0, Channel #24 + DCD cpuss_interrupts_dw0_25_IRQHandler ; CPUSS DataWire #0, Channel #25 + DCD cpuss_interrupts_dw0_26_IRQHandler ; CPUSS DataWire #0, Channel #26 + DCD cpuss_interrupts_dw0_27_IRQHandler ; CPUSS DataWire #0, Channel #27 + DCD cpuss_interrupts_dw0_28_IRQHandler ; CPUSS DataWire #0, Channel #28 + DCD cpuss_interrupts_dw1_0_IRQHandler ; CPUSS DataWire #1, Channel #0 + DCD cpuss_interrupts_dw1_1_IRQHandler ; CPUSS DataWire #1, Channel #1 + DCD cpuss_interrupts_dw1_2_IRQHandler ; CPUSS DataWire #1, Channel #2 + DCD cpuss_interrupts_dw1_3_IRQHandler ; CPUSS DataWire #1, Channel #3 + DCD cpuss_interrupts_dw1_4_IRQHandler ; CPUSS DataWire #1, Channel #4 + DCD cpuss_interrupts_dw1_5_IRQHandler ; CPUSS DataWire #1, Channel #5 + DCD cpuss_interrupts_dw1_6_IRQHandler ; CPUSS DataWire #1, Channel #6 + DCD cpuss_interrupts_dw1_7_IRQHandler ; CPUSS DataWire #1, Channel #7 + DCD cpuss_interrupts_dw1_8_IRQHandler ; CPUSS DataWire #1, Channel #8 + DCD cpuss_interrupts_dw1_9_IRQHandler ; CPUSS DataWire #1, Channel #9 + DCD cpuss_interrupts_dw1_10_IRQHandler ; CPUSS DataWire #1, Channel #10 + DCD cpuss_interrupts_dw1_11_IRQHandler ; CPUSS DataWire #1, Channel #11 + DCD cpuss_interrupts_dw1_12_IRQHandler ; CPUSS DataWire #1, Channel #12 + DCD cpuss_interrupts_dw1_13_IRQHandler ; CPUSS DataWire #1, Channel #13 + DCD cpuss_interrupts_dw1_14_IRQHandler ; CPUSS DataWire #1, Channel #14 + DCD cpuss_interrupts_dw1_15_IRQHandler ; CPUSS DataWire #1, Channel #15 + DCD cpuss_interrupts_dw1_16_IRQHandler ; CPUSS DataWire #1, Channel #16 + DCD cpuss_interrupts_dw1_17_IRQHandler ; CPUSS DataWire #1, Channel #17 + DCD cpuss_interrupts_dw1_18_IRQHandler ; CPUSS DataWire #1, Channel #18 + DCD cpuss_interrupts_dw1_19_IRQHandler ; CPUSS DataWire #1, Channel #19 + DCD cpuss_interrupts_dw1_20_IRQHandler ; CPUSS DataWire #1, Channel #20 + DCD cpuss_interrupts_dw1_21_IRQHandler ; CPUSS DataWire #1, Channel #21 + DCD cpuss_interrupts_dw1_22_IRQHandler ; CPUSS DataWire #1, Channel #22 + DCD cpuss_interrupts_dw1_23_IRQHandler ; CPUSS DataWire #1, Channel #23 + DCD cpuss_interrupts_dw1_24_IRQHandler ; CPUSS DataWire #1, Channel #24 + DCD cpuss_interrupts_dw1_25_IRQHandler ; CPUSS DataWire #1, Channel #25 + DCD cpuss_interrupts_dw1_26_IRQHandler ; CPUSS DataWire #1, Channel #26 + DCD cpuss_interrupts_dw1_27_IRQHandler ; CPUSS DataWire #1, Channel #27 + DCD cpuss_interrupts_dw1_28_IRQHandler ; CPUSS DataWire #1, Channel #28 + DCD cpuss_interrupts_fault_0_IRQHandler ; CPUSS Fault Structure Interrupt #0 + DCD cpuss_interrupts_fault_1_IRQHandler ; CPUSS Fault Structure Interrupt #1 + DCD cpuss_interrupt_crypto_IRQHandler ; CRYPTO Accelerator Interrupt + DCD cpuss_interrupt_fm_IRQHandler ; FLASH Macro Interrupt + DCD cpuss_interrupts_cm4_fp_IRQHandler ; Floating Point operation fault + DCD cpuss_interrupts_cm0_cti_0_IRQHandler ; CM0+ CTI #0 + DCD cpuss_interrupts_cm0_cti_1_IRQHandler ; CM0+ CTI #1 + DCD cpuss_interrupts_cm4_cti_0_IRQHandler ; CM4 CTI #0 + DCD cpuss_interrupts_cm4_cti_1_IRQHandler ; CM4 CTI #1 + DCD tcpwm_0_interrupts_0_IRQHandler ; TCPWM #0, Counter #0 + DCD tcpwm_0_interrupts_1_IRQHandler ; TCPWM #0, Counter #1 + DCD tcpwm_0_interrupts_2_IRQHandler ; TCPWM #0, Counter #2 + DCD tcpwm_0_interrupts_3_IRQHandler ; TCPWM #0, Counter #3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD tcpwm_0_interrupts_256_IRQHandler ; TCPWM #0, Counter #256 + DCD tcpwm_0_interrupts_257_IRQHandler ; TCPWM #0, Counter #257 + DCD tcpwm_0_interrupts_258_IRQHandler ; TCPWM #0, Counter #258 + DCD tcpwm_0_interrupts_259_IRQHandler ; TCPWM #0, Counter #259 + DCD tcpwm_0_interrupts_260_IRQHandler ; TCPWM #0, Counter #260 + DCD tcpwm_0_interrupts_261_IRQHandler ; TCPWM #0, Counter #261 + DCD tcpwm_0_interrupts_262_IRQHandler ; TCPWM #0, Counter #262 + DCD tcpwm_0_interrupts_263_IRQHandler ; TCPWM #0, Counter #263 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD pass_interrupt_dacs_IRQHandler ; Consolidated interrrupt for all DACs + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt + DCD usb_interrupt_hi_IRQHandler ; USB Interrupt + DCD usb_interrupt_med_IRQHandler ; USB Interrupt + DCD usb_interrupt_lo_IRQHandler ; USB Interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD canfd_0_interrupt0_IRQHandler ; Can #0, Consolidated interrupt #0 + DCD canfd_0_interrupts0_0_IRQHandler ; CAN #0, Interrupt #0, Channel #0 + DCD canfd_0_interrupts1_0_IRQHandler ; CAN #0, Interrupt #1, Channel #0 + DCD cpuss_interrupts_dw1_29_IRQHandler ; CPUSS DataWire #1, Channel #29 + DCD cpuss_interrupts_dw1_30_IRQHandler ; CPUSS DataWire #1, Channel #30 + DCD cpuss_interrupts_dw1_31_IRQHandler ; CPUSS DataWire #1, Channel #31 + DCD cpuss_interrupts_dw0_29_IRQHandler ; CPUSS DataWire #0, Channel #29 + +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + SECTION .intvec_ram:DATA:REORDER:NOROOT(2) +__ramVectors + DS32 __Vectors_Size + + + THUMB + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default handlers +;; + PUBWEAK Default_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Default_Handler + B Default_Handler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Weak function for startup customization +;; +;; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +;; because this function is executed as the first instruction in the ResetHandler. +;; The PDL is also not initialized to use the proper register offsets. +;; The user of this function is responsible for initializing the PDL and resources before using them. +;; + PUBWEAK Cy_OnResetUser + SECTION .text:CODE:REORDER:NOROOT(2) +Cy_OnResetUser + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Weak function for OS-specific customization +;; + PUBWEAK cy_toolchain_init + SECTION .text:CODE:REORDER:NOROOT(2) +cy_toolchain_init + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Define strong version to return zero for +;; __iar_program_start to skip data sections +;; initialization. +;; + PUBLIC __low_level_init + SECTION .text:CODE:REORDER:NOROOT(2) +__low_level_init + MOVS R0, #0 + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + ; Define strong function for startup customization + LDR R0, =Cy_OnResetUser + BLX R0 + + ; Disable global interrupts + CPSID I + + ; Copy vectors from ROM to RAM + LDR r1, =__vector_table + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +intvec_copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE intvec_copy + + ; Update Vector Table Offset Register + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb + + ; Initialize data sections + LDR R0, =__iar_data_init3 + BLX R0 + + ; OS-specific low-level initialization + LDR R0, =cy_toolchain_init + BLX R0 + + ; --manual_dynamic_initialization + BL __iar_dynamic_initialization + + LDR R0, =SystemInit + BLX R0 + + LDR R0, =__iar_program_start + BLX R0 + +; Should never get here +Cy_Main_Exited + B Cy_Main_Exited + + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK Cy_SysLib_FaultHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Cy_SysLib_FaultHandler + B Cy_SysLib_FaultHandler + + PUBWEAK HardFault_Wrapper + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Wrapper + IMPORT Cy_SysLib_FaultHandler + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + b L_API_call +L_MSP + mrs r0, MSP +L_API_call + ; Storing LR content for Creator call stack trace + push {LR} + bl Cy_SysLib_FaultHandler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Wrapper + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B HardFault_Wrapper + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B HardFault_Wrapper + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B HardFault_Wrapper + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + + ; External interrupts + PUBWEAK ioss_interrupts_gpio_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_0_IRQHandler + B ioss_interrupts_gpio_0_IRQHandler + + PUBWEAK ioss_interrupts_gpio_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_2_IRQHandler + B ioss_interrupts_gpio_2_IRQHandler + + PUBWEAK ioss_interrupts_gpio_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_3_IRQHandler + B ioss_interrupts_gpio_3_IRQHandler + + PUBWEAK ioss_interrupts_gpio_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_5_IRQHandler + B ioss_interrupts_gpio_5_IRQHandler + + PUBWEAK ioss_interrupts_gpio_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_6_IRQHandler + B ioss_interrupts_gpio_6_IRQHandler + + PUBWEAK ioss_interrupts_gpio_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_7_IRQHandler + B ioss_interrupts_gpio_7_IRQHandler + + PUBWEAK ioss_interrupts_gpio_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_8_IRQHandler + B ioss_interrupts_gpio_8_IRQHandler + + PUBWEAK ioss_interrupts_gpio_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_9_IRQHandler + B ioss_interrupts_gpio_9_IRQHandler + + PUBWEAK ioss_interrupts_gpio_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_10_IRQHandler + B ioss_interrupts_gpio_10_IRQHandler + + PUBWEAK ioss_interrupts_gpio_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_11_IRQHandler + B ioss_interrupts_gpio_11_IRQHandler + + PUBWEAK ioss_interrupts_gpio_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_12_IRQHandler + B ioss_interrupts_gpio_12_IRQHandler + + PUBWEAK ioss_interrupts_gpio_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_14_IRQHandler + B ioss_interrupts_gpio_14_IRQHandler + + PUBWEAK ioss_interrupt_gpio_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupt_gpio_IRQHandler + B ioss_interrupt_gpio_IRQHandler + + PUBWEAK ioss_interrupt_vdd_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupt_vdd_IRQHandler + B ioss_interrupt_vdd_IRQHandler + + PUBWEAK lpcomp_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +lpcomp_interrupt_IRQHandler + B lpcomp_interrupt_IRQHandler + + PUBWEAK scb_6_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_6_interrupt_IRQHandler + B scb_6_interrupt_IRQHandler + + PUBWEAK srss_interrupt_mcwdt_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_mcwdt_0_IRQHandler + B srss_interrupt_mcwdt_0_IRQHandler + + PUBWEAK srss_interrupt_mcwdt_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_mcwdt_1_IRQHandler + B srss_interrupt_mcwdt_1_IRQHandler + + PUBWEAK srss_interrupt_backup_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_backup_IRQHandler + B srss_interrupt_backup_IRQHandler + + PUBWEAK srss_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_IRQHandler + B srss_interrupt_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_0_IRQHandler + B cpuss_interrupts_ipc_0_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_1_IRQHandler + B cpuss_interrupts_ipc_1_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_2_IRQHandler + B cpuss_interrupts_ipc_2_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_3_IRQHandler + B cpuss_interrupts_ipc_3_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_4_IRQHandler + B cpuss_interrupts_ipc_4_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_5_IRQHandler + B cpuss_interrupts_ipc_5_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_6_IRQHandler + B cpuss_interrupts_ipc_6_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_7_IRQHandler + B cpuss_interrupts_ipc_7_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_8_IRQHandler + B cpuss_interrupts_ipc_8_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_9_IRQHandler + B cpuss_interrupts_ipc_9_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_10_IRQHandler + B cpuss_interrupts_ipc_10_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_11_IRQHandler + B cpuss_interrupts_ipc_11_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_12_IRQHandler + B cpuss_interrupts_ipc_12_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_13_IRQHandler + B cpuss_interrupts_ipc_13_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_14_IRQHandler + B cpuss_interrupts_ipc_14_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_15_IRQHandler + B cpuss_interrupts_ipc_15_IRQHandler + + PUBWEAK pass_interrupt_sar_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +pass_interrupt_sar_0_IRQHandler + B pass_interrupt_sar_0_IRQHandler + + PUBWEAK pass_interrupt_sar_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +pass_interrupt_sar_1_IRQHandler + B pass_interrupt_sar_1_IRQHandler + + PUBWEAK pass_interrupt_ctb_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +pass_interrupt_ctb_IRQHandler + B pass_interrupt_ctb_IRQHandler + + PUBWEAK pass_interrupt_fifo_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +pass_interrupt_fifo_0_IRQHandler + B pass_interrupt_fifo_0_IRQHandler + + PUBWEAK pass_interrupt_fifo_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +pass_interrupt_fifo_1_IRQHandler + B pass_interrupt_fifo_1_IRQHandler + + PUBWEAK scb_0_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_0_interrupt_IRQHandler + B scb_0_interrupt_IRQHandler + + PUBWEAK scb_1_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_1_interrupt_IRQHandler + B scb_1_interrupt_IRQHandler + + PUBWEAK scb_2_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_2_interrupt_IRQHandler + B scb_2_interrupt_IRQHandler + + PUBWEAK scb_4_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_4_interrupt_IRQHandler + B scb_4_interrupt_IRQHandler + + PUBWEAK scb_5_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_5_interrupt_IRQHandler + B scb_5_interrupt_IRQHandler + + PUBWEAK csd_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +csd_interrupt_IRQHandler + B csd_interrupt_IRQHandler + + PUBWEAK cpuss_interrupts_dmac_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dmac_0_IRQHandler + B cpuss_interrupts_dmac_0_IRQHandler + + PUBWEAK cpuss_interrupts_dmac_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dmac_1_IRQHandler + B cpuss_interrupts_dmac_1_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_0_IRQHandler + B cpuss_interrupts_dw0_0_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_1_IRQHandler + B cpuss_interrupts_dw0_1_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_2_IRQHandler + B cpuss_interrupts_dw0_2_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_3_IRQHandler + B cpuss_interrupts_dw0_3_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_4_IRQHandler + B cpuss_interrupts_dw0_4_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_5_IRQHandler + B cpuss_interrupts_dw0_5_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_6_IRQHandler + B cpuss_interrupts_dw0_6_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_7_IRQHandler + B cpuss_interrupts_dw0_7_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_8_IRQHandler + B cpuss_interrupts_dw0_8_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_9_IRQHandler + B cpuss_interrupts_dw0_9_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_10_IRQHandler + B cpuss_interrupts_dw0_10_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_11_IRQHandler + B cpuss_interrupts_dw0_11_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_12_IRQHandler + B cpuss_interrupts_dw0_12_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_13_IRQHandler + B cpuss_interrupts_dw0_13_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_14_IRQHandler + B cpuss_interrupts_dw0_14_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_15_IRQHandler + B cpuss_interrupts_dw0_15_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_16_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_16_IRQHandler + B cpuss_interrupts_dw0_16_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_17_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_17_IRQHandler + B cpuss_interrupts_dw0_17_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_18_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_18_IRQHandler + B cpuss_interrupts_dw0_18_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_19_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_19_IRQHandler + B cpuss_interrupts_dw0_19_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_20_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_20_IRQHandler + B cpuss_interrupts_dw0_20_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_21_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_21_IRQHandler + B cpuss_interrupts_dw0_21_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_22_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_22_IRQHandler + B cpuss_interrupts_dw0_22_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_23_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_23_IRQHandler + B cpuss_interrupts_dw0_23_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_24_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_24_IRQHandler + B cpuss_interrupts_dw0_24_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_25_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_25_IRQHandler + B cpuss_interrupts_dw0_25_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_26_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_26_IRQHandler + B cpuss_interrupts_dw0_26_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_27_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_27_IRQHandler + B cpuss_interrupts_dw0_27_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_28_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_28_IRQHandler + B cpuss_interrupts_dw0_28_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_0_IRQHandler + B cpuss_interrupts_dw1_0_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_1_IRQHandler + B cpuss_interrupts_dw1_1_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_2_IRQHandler + B cpuss_interrupts_dw1_2_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_3_IRQHandler + B cpuss_interrupts_dw1_3_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_4_IRQHandler + B cpuss_interrupts_dw1_4_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_5_IRQHandler + B cpuss_interrupts_dw1_5_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_6_IRQHandler + B cpuss_interrupts_dw1_6_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_7_IRQHandler + B cpuss_interrupts_dw1_7_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_8_IRQHandler + B cpuss_interrupts_dw1_8_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_9_IRQHandler + B cpuss_interrupts_dw1_9_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_10_IRQHandler + B cpuss_interrupts_dw1_10_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_11_IRQHandler + B cpuss_interrupts_dw1_11_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_12_IRQHandler + B cpuss_interrupts_dw1_12_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_13_IRQHandler + B cpuss_interrupts_dw1_13_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_14_IRQHandler + B cpuss_interrupts_dw1_14_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_15_IRQHandler + B cpuss_interrupts_dw1_15_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_16_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_16_IRQHandler + B cpuss_interrupts_dw1_16_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_17_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_17_IRQHandler + B cpuss_interrupts_dw1_17_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_18_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_18_IRQHandler + B cpuss_interrupts_dw1_18_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_19_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_19_IRQHandler + B cpuss_interrupts_dw1_19_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_20_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_20_IRQHandler + B cpuss_interrupts_dw1_20_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_21_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_21_IRQHandler + B cpuss_interrupts_dw1_21_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_22_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_22_IRQHandler + B cpuss_interrupts_dw1_22_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_23_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_23_IRQHandler + B cpuss_interrupts_dw1_23_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_24_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_24_IRQHandler + B cpuss_interrupts_dw1_24_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_25_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_25_IRQHandler + B cpuss_interrupts_dw1_25_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_26_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_26_IRQHandler + B cpuss_interrupts_dw1_26_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_27_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_27_IRQHandler + B cpuss_interrupts_dw1_27_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_28_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_28_IRQHandler + B cpuss_interrupts_dw1_28_IRQHandler + + PUBWEAK cpuss_interrupts_fault_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_fault_0_IRQHandler + B cpuss_interrupts_fault_0_IRQHandler + + PUBWEAK cpuss_interrupts_fault_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_fault_1_IRQHandler + B cpuss_interrupts_fault_1_IRQHandler + + PUBWEAK cpuss_interrupt_crypto_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupt_crypto_IRQHandler + B cpuss_interrupt_crypto_IRQHandler + + PUBWEAK cpuss_interrupt_fm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupt_fm_IRQHandler + B cpuss_interrupt_fm_IRQHandler + + PUBWEAK cpuss_interrupts_cm4_fp_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm4_fp_IRQHandler + B cpuss_interrupts_cm4_fp_IRQHandler + + PUBWEAK cpuss_interrupts_cm0_cti_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm0_cti_0_IRQHandler + B cpuss_interrupts_cm0_cti_0_IRQHandler + + PUBWEAK cpuss_interrupts_cm0_cti_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm0_cti_1_IRQHandler + B cpuss_interrupts_cm0_cti_1_IRQHandler + + PUBWEAK cpuss_interrupts_cm4_cti_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm4_cti_0_IRQHandler + B cpuss_interrupts_cm4_cti_0_IRQHandler + + PUBWEAK cpuss_interrupts_cm4_cti_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm4_cti_1_IRQHandler + B cpuss_interrupts_cm4_cti_1_IRQHandler + + PUBWEAK tcpwm_0_interrupts_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_0_IRQHandler + B tcpwm_0_interrupts_0_IRQHandler + + PUBWEAK tcpwm_0_interrupts_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_1_IRQHandler + B tcpwm_0_interrupts_1_IRQHandler + + PUBWEAK tcpwm_0_interrupts_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_2_IRQHandler + B tcpwm_0_interrupts_2_IRQHandler + + PUBWEAK tcpwm_0_interrupts_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_3_IRQHandler + B tcpwm_0_interrupts_3_IRQHandler + + PUBWEAK tcpwm_0_interrupts_256_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_256_IRQHandler + B tcpwm_0_interrupts_256_IRQHandler + + PUBWEAK tcpwm_0_interrupts_257_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_257_IRQHandler + B tcpwm_0_interrupts_257_IRQHandler + + PUBWEAK tcpwm_0_interrupts_258_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_258_IRQHandler + B tcpwm_0_interrupts_258_IRQHandler + + PUBWEAK tcpwm_0_interrupts_259_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_259_IRQHandler + B tcpwm_0_interrupts_259_IRQHandler + + PUBWEAK tcpwm_0_interrupts_260_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_260_IRQHandler + B tcpwm_0_interrupts_260_IRQHandler + + PUBWEAK tcpwm_0_interrupts_261_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_261_IRQHandler + B tcpwm_0_interrupts_261_IRQHandler + + PUBWEAK tcpwm_0_interrupts_262_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_262_IRQHandler + B tcpwm_0_interrupts_262_IRQHandler + + PUBWEAK tcpwm_0_interrupts_263_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_263_IRQHandler + B tcpwm_0_interrupts_263_IRQHandler + + PUBWEAK pass_interrupt_dacs_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +pass_interrupt_dacs_IRQHandler + B pass_interrupt_dacs_IRQHandler + + PUBWEAK smif_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +smif_interrupt_IRQHandler + B smif_interrupt_IRQHandler + + PUBWEAK usb_interrupt_hi_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +usb_interrupt_hi_IRQHandler + B usb_interrupt_hi_IRQHandler + + PUBWEAK usb_interrupt_med_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +usb_interrupt_med_IRQHandler + B usb_interrupt_med_IRQHandler + + PUBWEAK usb_interrupt_lo_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +usb_interrupt_lo_IRQHandler + B usb_interrupt_lo_IRQHandler + + PUBWEAK canfd_0_interrupt0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +canfd_0_interrupt0_IRQHandler + B canfd_0_interrupt0_IRQHandler + + PUBWEAK canfd_0_interrupts0_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +canfd_0_interrupts0_0_IRQHandler + B canfd_0_interrupts0_0_IRQHandler + + PUBWEAK canfd_0_interrupts1_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +canfd_0_interrupts1_0_IRQHandler + B canfd_0_interrupts1_0_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_29_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_29_IRQHandler + B cpuss_interrupts_dw1_29_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_30_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_30_IRQHandler + B cpuss_interrupts_dw1_30_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_31_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_31_IRQHandler + B cpuss_interrupts_dw1_31_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_29_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_29_IRQHandler + B cpuss_interrupts_dw0_29_IRQHandler + + + END + + +; [] END OF FILE diff --git a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/system_psoc6_cm4.c b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/system_psoc6_cm4.c index 7800d6b..7e634e2 100644 --- a/devices/templates/COMPONENT_MTB/COMPONENT_CM4/system_psoc6_cm4.c +++ b/devices/templates/COMPONENT_MTB/COMPONENT_CM4/system_psoc6_cm4.c @@ -1,12 +1,12 @@ /***************************************************************************//** * \file system_psoc6_cm4.c -* \version 2.70 +* \version 2.70.1 * * The device system-source file. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/devices/templates/COMPONENT_MTB/system_psoc6.h b/devices/templates/COMPONENT_MTB/system_psoc6.h index 9af8a90..58550fa 100644 --- a/devices/templates/COMPONENT_MTB/system_psoc6.h +++ b/devices/templates/COMPONENT_MTB/system_psoc6.h @@ -1,12 +1,12 @@ /***************************************************************************//** * \file system_psoc6.h -* \version 2.70 +* \version 2.70.1 * * \brief Device system header file. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -36,7 +36,6 @@ * * \ref group_system_config_single_core_device_initialization * - \ref group_system_config_device_memory_definition * - \ref group_system_config_heap_stack_config -* - \ref group_system_config_merge_apps * - \ref group_system_config_default_handlers * - \ref group_system_config_device_vector_table * - \ref group_system_config_cm4_functions @@ -56,44 +55,58 @@ * warnings in your project, you can simply comment out or remove the relevant * code in the linker file. * +* \note For the PSoC 64 Secure MCUs devices, refer to the following page: +* https://www.cypress.com/documentation/software-and-drivers/psoc-64-secure-mcu-secure-boot-sdk-user-guide +* +* * ARM GCC\n * The flash and RAM sections for the CPU are defined in the linker files: * 'xx_yy.ld', where 'xx' is the device group, and 'yy' is the target CPU; for example, * 'cy8c6xx7_cm0plus.ld' and 'cy8c6xx7_cm4_dual.ld'. * \note If the start of the Cortex-M4 application image is changed, the value -* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The +* of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The * \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the * Cy_SysEnableCM4() function call. +* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p * * Change the flash and RAM sizes by editing the macros value in the * linker files for both CPUs: * - 'xx_cm0plus.ld', where 'xx' is the device group: * \code -* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x00080000 -* ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x00024000 +* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x2000 +* ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x2000 * \endcode * - 'xx_cm4_dual.ld', where 'xx' is the device group: * \code -* flash (rx) : ORIGIN = 0x10080000, LENGTH = 0x00080000 -* ram (rwx) : ORIGIN = 0x08024000, LENGTH = 0x00023800 +* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x100000 +* ram (rwx) : ORIGIN = 0x08002000, LENGTH = 0x45800 * \endcode * -* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the rom ORIGIN's -* value in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. Do this -* by either: +* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the ROM ORIGIN's +* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image +* of the Cortex-M0+ application should be the same value as the flash LENGTH in +* 'xx_cm0plus.ld') in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. +* Do this by either: * - Passing the following commands to the compiler:\n -* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode -* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where 'xx' is device family:\n -* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode +* or +* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where +* 'xx' is the device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode * -* ARM MDK\n +* ARM Compiler\n * The flash and RAM sections for the CPU are defined in the linker files: -* 'xx_yy.scat', where 'xx' is the device group, and 'yy' is the target CPU; for example, -* 'cy8c6xx7_cm0plus.scat' and 'cy8c6xx7_cm4_dual.scat'. +* 'xx_yy.sct', where 'xx' is the device group, and 'yy' is the target CPU; for +* example 'cy8c6xx7_cm0plus.sct' and 'cy8c6xx7_cm4_dual.sct'. * \note If the start of the Cortex-M4 application image is changed, the value * of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The * \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref * Cy_SysEnableCM4() function call. +* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p * * \note The linker files provided with the PDL are generic and handle all common * use cases. Your project may not use every section defined in the linker files. @@ -106,29 +119,32 @@ * * Change the flash and RAM sizes by editing the macros value in the * linker files for both CPUs: -* - 'xx_cm0plus.scat', where 'xx' is the device group: +* - 'xx_cm0plus.sct', where 'xx' is the device group: * \code * #define FLASH_START 0x10000000 -* #define FLASH_SIZE 0x00080000 +* #define FLASH_SIZE 0x00002000 * #define RAM_START 0x08000000 -* #define RAM_SIZE 0x00024000 +* #define RAM_SIZE 0x00002000 * \endcode -* - 'xx_cm4_dual.scat', where 'xx' is the device group: +* - 'xx_cm4_dual.sct', where 'xx' is the device group: * \code -* #define FLASH_START 0x10080000 -* #define FLASH_SIZE 0x00080000 -* #define RAM_START 0x08024000 -* #define RAM_SIZE 0x00023800 +* #define FLASH_START 0x10000000 +* #define FLASH_SIZE 0x00100000 +* #define RAM_START 0x08002000 +* #define RAM_SIZE 0x00045800 * \endcode * * Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the FLASH_START -* value in the 'xx_cm4_dual.scat' file, -* where 'xx' is the device group. Do this by either: +* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image +* of the Cortex-M0+ application should be the same value as the FLASH_SIZE in the +* 'xx_cm0plus.sct') in the 'xx_cm4_dual.sct' file, where 'xx' is the device group. +* Do this by either: * - Passing the following commands to the compiler:\n -* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode +* or * - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where -* 'xx' is device family:\n -* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode +* 'xx' is the device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode * * IAR\n * The flash and RAM sections for the CPU are defined in the linker files: @@ -138,32 +154,39 @@ * of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The * \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref * Cy_SysEnableCM4() function call. +* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p * * Change the flash and RAM sizes by editing the macros value in the * linker files for both CPUs: * - 'xx_cm0plus.icf', where 'xx' is the device group: * \code * define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; -* define symbol __ICFEDIT_region_IROM1_end__ = 0x10080000; +* define symbol __ICFEDIT_region_IROM1_end__ = 0x10001FFF; * define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; -* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08024000; +* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08001FFF; * \endcode * - 'xx_cm4_dual.icf', where 'xx' is the device group: * \code -* define symbol __ICFEDIT_region_IROM1_start__ = 0x10080000; -* define symbol __ICFEDIT_region_IROM1_end__ = 0x10100000; -* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08024000; -* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08047800; +* define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +* define symbol __ICFEDIT_region_IROM1_end__ = 0x100FFFFF; +* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000; +* define symbol __ICFEDIT_region_IRAM1_end__ = 0x080477FF; * \endcode * -* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the -* __ICFEDIT_region_IROM1_start__ value in the 'xx_cm4_dual.icf' file, where 'xx' -* is the device group. Do this by either: +* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the +* __ICFEDIT_region_IROM1_start__ value (0x10000000) + FLASH_CM0P_SIZE value +* (0x2000, the size of a flash image of the Cortex-M0+ application) in the +* 'xx_cm4_dual.icf' file, where 'xx' is the device group. The sum result +* should be the same as (__ICFEDIT_region_IROM1_end__ + 1) value in the +* 'xx_cm0plus.icf'. Do this by either: * - Passing the following commands to the compiler:\n -* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode +* or * - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where -* 'xx' is device family:\n -* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode +* 'xx' is the device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode * * \subsection group_system_config_device_initialization Device Initialization * After a power-on-reset (POR), the boot process is handled by the boot code @@ -189,7 +212,9 @@ * -# Editing source code files * -# Specifying via command line * -* By default, the stack size is set to 0x00001000 and the heap size is set to 0x00000400. +* By default, the stack size is set to 0x00001000 and the heap size is allocated +* dynamically to the whole available free memory up to stack memory and it +* is set to the 0x00000400 (for ARM GCC and IAR compilers) as minimal value. * * \subsubsection group_system_config_heap_stack_config_gcc ARM GCC * - Editing source code files\n @@ -198,28 +223,23 @@ * Change the heap and stack sizes by modifying the following lines:\n * \code .equ Stack_Size, 0x00001000 \endcode * \code .equ Heap_Size, 0x00000400 \endcode +* Also, the stack size is defined in the linker script files: 'xx_yy.ld', +* where 'xx' is the device family, and 'yy' is the target CPU; for example, +* cy8c6xx7_cm0plus.ld and cy8c6xx7_cm4_dual.ld. +* Change the stack size by modifying the following line:\n +* \code STACK_SIZE = 0x1000; \endcode * -* - Specifying via command line\n -* Change the heap and stack sizes passing the following commands to the compiler:\n -* \code -D __STACK_SIZE=0x000000400 \endcode -* \code -D __HEAP_SIZE=0x000000100 \endcode -* -* \subsubsection group_system_config_heap_stack_config_mdk ARM MDK +* \subsubsection group_system_config_heap_stack_config_mdk ARM Compiler * - Editing source code files\n -* The heap and stack sizes are defined in the assembler startup files -* (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). -* Change the heap and stack sizes by modifying the following lines:\n -* \code Stack_Size EQU 0x00001000 \endcode -* \code Heap_Size EQU 0x00000400 \endcode -* -* - Specifying via command line\n -* Change the heap and stack sizes passing the following commands to the assembler:\n -* \code "--predefine=___STACK_SIZE SETA 0x000000400" \endcode -* \code "--predefine=__HEAP_SIZE SETA 0x000000100" \endcode +* The stack size is defined in the linker script files: 'xx_yy.sct', +* where 'xx' is the device family, and 'yy' is the target CPU; for example, +* cy8c6xx7_cm0plus.sct and cy8c6xx7_cm4_dual.sct. +* Change the stack size by modifying the following line:\n +* \code STACK_SIZE = 0x1000; \endcode * * \subsubsection group_system_config_heap_stack_config_iar IAR * - Editing source code files\n -* The heap and stack sizes are defined in the linker scatter files: 'xx_yy.icf', +* The heap and stack sizes are defined in the linker script files: 'xx_yy.icf', * where 'xx' is the device family, and 'yy' is the target CPU; for example, * cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf. * Change the heap and stack sizes by modifying the following lines:\n @@ -232,21 +252,6 @@ * \code --define_symbol __STACK_SIZE=0x000000400 \endcode * \code --define_symbol __HEAP_SIZE=0x000000100 \endcode * -* \subsection group_system_config_merge_apps Merging CM0+ and CM4 Executables -* The CM0+ project and linker script build the CM0+ application image. Similarly, -* the CM4 linker script builds the CM4 application image. Each specifies -* locations, sizes, and contents of sections in memory. See -* \ref group_system_config_device_memory_definition for the symbols and default -* values. -* -* The cymcuelftool is invoked by a post-build command. The precise project -* setting is IDE-specific. -* -* The cymcuelftool combines the two executables. The tool examines the -* executables to ensure that memory regions either do not overlap, or contain -* identical bytes (shared). If there are no problems, it creates a new ELF file -* with the merged image, without changing any of the addresses or data. -* * \subsection group_system_config_default_handlers Default Interrupt Handlers Definition * The default interrupt handler functions are defined as weak functions to a dummy * handler in the startup file. The naming convention for the interrupt handler names @@ -273,10 +278,10 @@ * The vector table address (and the vector table itself) are defined in the * assembler startup files (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S). * The code in these files copies the vector table from Flash to RAM. -* \subsubsection group_system_config_device_vector_table_mdk ARM MDK -* The linker script file is 'xx_yy.scat', where 'xx' is the device family, -* and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.scat and -* cy8c6xx7_cm4_dual.scat. The linker script specifies that the vector table +* \subsubsection group_system_config_device_vector_table_mdk ARM Compiler +* The linker script file is 'xx_yy.sct', where 'xx' is the device family, +* and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.sct and +* cy8c6xx7_cm4_dual.sct. The linker script specifies that the vector table * (RESET_RAM) shall be first in the RAM section.\n * RESET_RAM represents the vector table. It is defined in the assembler startup * files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). @@ -291,10 +296,6 @@ * assembler startup files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). * The code in these files copies the vector table from Flash to RAM. * -* \section group_system_config_more_information More Information -* Refer to the PDL User Guide for the -* more details. -* * \section group_system_config_MISRA MISRA Compliance * *
Reason for Change
2.70.1Updated documentation for the better description of the existing startup implementation.User experience enhancement.
2.70Updated \ref SystemCoreClockUpdate() implementation - The SysClk API is reused.Code optimization.
@@ -320,6 +321,11 @@ * * * +* +* +* +* +* * * * diff --git a/docs/pdl_api_reference_manual/html/annotated.html b/docs/pdl_api_reference_manual/html/annotated.html index 27c7101..ecb863e 100644 --- a/docs/pdl_api_reference_manual/html/annotated.html +++ b/docs/pdl_api_reference_manual/html/annotated.html @@ -206,87 +206,88 @@ - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + - - - - - - - - - - - - - - - - diff --git a/docs/pdl_api_reference_manual/html/classes.html b/docs/pdl_api_reference_manual/html/classes.html index 2d85a25..4a9a8a9 100644 --- a/docs/pdl_api_reference_manual/html/classes.html +++ b/docs/pdl_api_reference_manual/html/classes.html @@ -87,49 +87,47 @@
c | d | g | i | l | m | p | s | t
Reason for Change
2.70.1Updated documentation for the better description of the existing startup implementation.User experience enhancement.
2.70Updated \ref SystemCoreClockUpdate() implementation - The SysClk API is reused.Code optimization.
 Ccy_stc_smif_block_config_tThis SMIF memory configuration structure is used to store the memory configuration for the memory mode of operation
 Ccy_stc_smif_config_tThe SMIF configuration structure
 Ccy_stc_smif_context_tThe SMIF internal context data
 Ccy_stc_smif_mem_cmd_tThis command structure is used to store the Read/Write command configuration
 Ccy_stc_smif_mem_config_tThis SMIF memory configuration structure is used to store the memory configuration for the memory mode of operation
 Ccy_stc_smif_mem_device_cfg_tThis configuration structure of the SMIF memory device is used to store device-specific parameters
 Ccy_stc_smpu_cfg_tConfiguration structure for SMPU struct initialization
 Ccy_stc_sysanalog_config_tStructure to configure the entire AREF block
 Ccy_stc_sysint_tInitialization configuration structure for a single interrupt channel
 Ccy_stc_syspm_backup_regs_tThis internal structure stores non-retained registers in the system Deep Sleep power mode
 Ccy_stc_syspm_callback_params_tThe structure contains syspm callback parameters
 Ccy_stc_syspm_callback_tStructure with syspm callback configuration elements
 Ccy_stc_tcpwm_counter_config_tCounter Timer configuration structure
 Ccy_stc_tcpwm_pwm_config_tPWM configuration structure
 Ccy_stc_tcpwm_quaddec_config_tQuadrature Decoder configuration structure
 Ccy_stc_usb_dev_ep_config_tData Endpoint Configuration Structure
 Ccy_stc_usbfs_dev_drv_config_tDriver Configuration Structure
 Ccy_stc_usbfs_dev_drv_context_tUSBFS Device context structure
 Ccy_stc_usbfs_dev_drv_dma_config_tDMA Channel Configuration Structure
 CCySCB_TypeThe struct type definition for the hardware register set contained in the block.
+
 Ccy_stc_smif_hybrid_region_info_tThis structure specifies data used for memory with hybrid sectors
 Ccy_stc_smif_mem_cmd_tThis command structure is used to store the Read/Write command configuration
 Ccy_stc_smif_mem_config_tThis SMIF memory configuration structure is used to store the memory configuration for the memory mode of operation
 Ccy_stc_smif_mem_device_cfg_tThis configuration structure of the SMIF memory device is used to store device-specific parameters
 Ccy_stc_smpu_cfg_tConfiguration structure for SMPU struct initialization
 Ccy_stc_sysanalog_config_tStructure to configure the entire AREF block
 Ccy_stc_sysint_tInitialization configuration structure for a single interrupt channel
 Ccy_stc_syspm_backup_regs_tThis internal structure stores non-retained registers in the system Deep Sleep power mode
 Ccy_stc_syspm_callback_params_tThe structure contains syspm callback parameters
 Ccy_stc_syspm_callback_tStructure with syspm callback configuration elements
 Ccy_stc_tcpwm_counter_config_tCounter Timer configuration structure
 Ccy_stc_tcpwm_pwm_config_tPWM configuration structure
 Ccy_stc_tcpwm_quaddec_config_tQuadrature Decoder configuration structure
 Ccy_stc_usb_dev_ep_config_tData Endpoint Configuration Structure
 Ccy_stc_usbfs_dev_drv_config_tDriver Configuration Structure
 Ccy_stc_usbfs_dev_drv_context_tUSBFS Device context structure
 Ccy_stc_usbfs_dev_drv_dma_config_tDMA Channel Configuration Structure
 CCySCB_TypeThe struct type definition for the hardware register set contained in the block.
The address of a variable of this type can be used as the base hardware address for register access. A device may support more than one instance of a peripheral block.
Refer to a device-specific header file, e.g. <PDL_DIR>/devices/include/cy8c637bzi_bld74.h for the list of block instances available on that device.
Refer to the device TRM for the block register descriptions.
 CDW_TypeThe struct type definition for the hardware register set contained in the block.
+
 CDW_TypeThe struct type definition for the hardware register set contained in the block.
The address of a variable of this type can be used as the base hardware address for register access. A device may support more than one instance of a peripheral block.
Refer to a device-specific header file, e.g. <PDL_DIR>/devices/include/cy8c637bzi_bld74.h for the list of block instances available on that device.
Refer to the device TRM for the block register descriptions.
 CGPIO_PRT_TypeThe struct type definition for the hardware register set contained in the block.
+
 CGPIO_PRT_TypeThe struct type definition for the hardware register set contained in the block.
The address of a variable of this type can be used as the base hardware address for register access. A device may support more than one instance of a peripheral block.
Refer to a device-specific header file, e.g. <PDL_DIR>/devices/include/cy8c637bzi_bld74.h for the list of block instances available on that device.
Refer to the device TRM for the block register descriptions.
 CI2S_TypeThe struct type definition for the hardware register set contained in the block.
+
 CI2S_TypeThe struct type definition for the hardware register set contained in the block.
The address of a variable of this type can be used as the base hardware address for register access. A device may support more than one instance of a peripheral block.
Refer to a device-specific header file, e.g. <PDL_DIR>/devices/include/cy8c637bzi_bld74.h for the list of block instances available on that device.
Refer to the device TRM for the block register descriptions.
 CIPC_STRUCT_TypeThe struct type definition for the hardware register set contained in the block.
+
 CIPC_STRUCT_TypeThe struct type definition for the hardware register set contained in the block.
The address of a variable of this type can be used as the base hardware address for register access. A device may support more than one instance of a peripheral block.
Refer to a device-specific header file, e.g. <PDL_DIR>/devices/include/cy8c637bzi_bld74.h for the list of block instances available on that device.
Refer to the device TRM for the block register descriptions.
 CLPCOMP_TypeThe struct type definition for the hardware register set contained in the block.
+
 CLPCOMP_TypeThe struct type definition for the hardware register set contained in the block.
The address of a variable of this type can be used as the base hardware address for register access. A device may support more than one instance of a peripheral block.
Refer to a device-specific header file, e.g. <PDL_DIR>/devices/include/cy8c637bzi_bld74.h for the list of block instances available on that device.
Refer to the device TRM for the block register descriptions.
 CMCWDT_STRUCT_TypeThe struct type definition for the hardware register set contained in the block.
+
 CMCWDT_STRUCT_TypeThe struct type definition for the hardware register set contained in the block.
The address of a variable of this type can be used as the base hardware address for register access. A device may support more than one instance of a peripheral block.
Refer to a device-specific header file, e.g. <PDL_DIR>/devices/include/cy8c637bzi_bld74.h for the list of block instances available on that device.
Refer to the device TRM for the block register descriptions.
 CPDM_TypeThe struct type definition for the hardware register set contained in the block.
+
 CPDM_TypeThe struct type definition for the hardware register set contained in the block.
The address of a variable of this type can be used as the base hardware address for register access. A device may support more than one instance of a peripheral block.
Refer to a device-specific header file, e.g. <PDL_DIR>/devices/include/cy8c637bzi_bld74.h for the list of block instances available on that device.
Refer to the device TRM for the block register descriptions.
 CPERI_GR_PPU_RG_TypeThe struct type definition for the hardware register set contained in the block.
+
 CPERI_GR_PPU_RG_TypeThe struct type definition for the hardware register set contained in the block.
The address of a variable of this type can be used as the base hardware address for register access. A device may support more than one instance of a peripheral block.
Refer to a device-specific header file, e.g. <PDL_DIR>/devices/include/cy8c637bzi_bld74.h for the list of block instances available on that device.
Refer to the device TRM for the block register descriptions.
 CPERI_GR_PPU_SL_TypeThe struct type definition for the hardware register set contained in the block.
+
 CPERI_GR_PPU_SL_TypeThe struct type definition for the hardware register set contained in the block.
The address of a variable of this type can be used as the base hardware address for register access. A device may support more than one instance of a peripheral block.
Refer to a device-specific header file, e.g. <PDL_DIR>/devices/include/cy8c637bzi_bld74.h for the list of block instances available on that device.
Refer to the device TRM for the block register descriptions.
 CPERI_PPU_GR_TypeThe struct type definition for the hardware register set contained in the block.
+
 CPERI_PPU_GR_TypeThe struct type definition for the hardware register set contained in the block.
The address of a variable of this type can be used as the base hardware address for register access. A device may support more than one instance of a peripheral block.
Refer to a device-specific header file, e.g. <PDL_DIR>/devices/include/cy8c637bzi_bld74.h for the list of block instances available on that device.
Refer to the device TRM for the block register descriptions.
 CPERI_PPU_PR_TypeThe struct type definition for the hardware register set contained in the block.
+
 CPERI_PPU_PR_TypeThe struct type definition for the hardware register set contained in the block.
The address of a variable of this type can be used as the base hardware address for register access. A device may support more than one instance of a peripheral block.
Refer to a device-specific header file, e.g. <PDL_DIR>/devices/include/cy8c637bzi_bld74.h for the list of block instances available on that device.
Refer to the device TRM for the block register descriptions.
 CPROT_MPU_MPU_STRUCT_TypeThe struct type definition for the hardware register set contained in the block.
+
 CPROT_MPU_MPU_STRUCT_TypeThe struct type definition for the hardware register set contained in the block.
The address of a variable of this type can be used as the base hardware address for register access. A device may support more than one instance of a peripheral block.
Refer to a device-specific header file, e.g. <PDL_DIR>/devices/include/cy8c637bzi_bld74.h for the list of block instances available on that device.
Refer to the device TRM for the block register descriptions.
 CPROT_SMPU_SMPU_STRUCT_TypeThe struct type definition for the hardware register set contained in the block.
+
 CPROT_SMPU_SMPU_STRUCT_TypeThe struct type definition for the hardware register set contained in the block.
The address of a variable of this type can be used as the base hardware address for register access. A device may support more than one instance of a peripheral block.
Refer to a device-specific header file, e.g. <PDL_DIR>/devices/include/cy8c637bzi_bld74.h for the list of block instances available on that device.
Refer to the device TRM for the block register descriptions.
 CSAR_TypeThe struct type definition for the hardware register set contained in the block.
+
 CSAR_TypeThe struct type definition for the hardware register set contained in the block.
The address of a variable of this type can be used as the base hardware address for register access. A device may support more than one instance of a peripheral block.
Refer to a device-specific header file, e.g. <PDL_DIR>/devices/include/cy8c637bzi_bld74.h for the list of block instances available on that device.
Refer to the device TRM for the block register descriptions.
 CSMIF_TypeThe struct type definition for the hardware register set contained in the block.
+
 CSMIF_TypeThe struct type definition for the hardware register set contained in the block.
The address of a variable of this type can be used as the base hardware address for register access. A device may support more than one instance of a peripheral block.
Refer to a device-specific header file, e.g. <PDL_DIR>/devices/include/cy8c637bzi_bld74.h for the list of block instances available on that device.
Refer to the device TRM for the block register descriptions.
 CTCPWM_TypeThe struct type definition for the hardware register set contained in the block.
+
 CTCPWM_TypeThe struct type definition for the hardware register set contained in the block.
The address of a variable of this type can be used as the base hardware address for register access. A device may support more than one instance of a peripheral block.
Refer to a device-specific header file, e.g. <PDL_DIR>/devices/include/cy8c637bzi_bld74.h for the list of block instances available on that device.
Refer to the device TRM for the block register descriptions.
- - + - - - + - - - + + + - - + - - - - - - - - + - - - - + + + + + + + + - - - - - - - - + + + + + + +
  c  
-		cy_stc_crypto_context_t   cy_stc_i2s_context_t   cy_stc_sd_host_cmd_config_t   
  g  
+		cy_stc_crypto_context_t   cy_stc_i2s_context_t   cy_stc_sd_host_cmd_config_t   
  d  
cy_stc_crypto_context_trng_t   cy_stc_id_filter_t   cy_stc_sd_host_context_t   
CTBM_Type   cy_stc_crypto_ecc_dp_type   cy_stc_ipc_pipe_config_t   cy_stc_sd_host_data_config_t   GPIO_PRT_Type   
CTDAC_Type   cy_stc_crypto_ecc_key   cy_stc_ipc_pipe_ep_config_t   cy_stc_sd_host_init_config_t   
  i  
+
CTBM_Type   cy_stc_crypto_ecc_dp_type   cy_stc_ipc_pipe_config_t   cy_stc_sd_host_data_config_t   DW_Type   
CTDAC_Type   cy_stc_crypto_ecc_key   cy_stc_ipc_pipe_ep_config_t   cy_stc_sd_host_init_config_t   
  g  
cy_en_canfd_fifo_config_t   cy_stc_crypto_ecc_point   cy_stc_ipc_pipe_ep_t   cy_stc_sd_host_sd_card_config_t   
cy_stc_canfd_bitrate_t   cy_stc_crypto_hw_error_t   cy_stc_ipc_sema_t   cy_stc_sd_host_write_read_config_t   I2S_Type   
cy_stc_canfd_config_t   cy_stc_crypto_rsa_pub_key_t   cy_stc_lpcomp_config_t   cy_stc_seglcd_config_t   IPC_STRUCT_Type   
cy_stc_canfd_context_t   cy_stc_crypto_server_context_t   cy_stc_mcwdt_config_t   cy_stc_seglcd_disp_t   
  l  
+
cy_stc_canfd_bitrate_t   cy_stc_crypto_hw_error_t   cy_stc_ipc_sema_t   cy_stc_sd_host_write_read_config_t   GPIO_PRT_Type   
cy_stc_canfd_config_t   cy_stc_crypto_rsa_pub_key_t   cy_stc_lpcomp_config_t   cy_stc_seglcd_config_t   
  i  
cy_stc_canfd_extid_filter_config_t   cy_stc_crypto_sha_state_t   cy_stc_mpu_cfg_t   cy_stc_seglcd_font_t   
cy_stc_canfd_f0_t   cy_stc_csd_config_t   cy_stc_pdm_pcm_config_t   cy_stc_smartio_config_t   LPCOMP_Type   
cy_stc_canfd_f1_t   cy_stc_csd_context_t   cy_stc_pll_config_t   cy_stc_smartio_ducfg_t   
  m  
+
cy_stc_canfd_context_t   cy_stc_crypto_server_context_t   cy_stc_mcwdt_config_t   cy_stc_seglcd_disp_t   
cy_stc_canfd_extid_filter_config_t   cy_stc_crypto_sha_state_t   cy_stc_mpu_cfg_t   cy_stc_seglcd_font_t   I2S_Type   
cy_stc_canfd_f0_t   cy_stc_csd_config_t   cy_stc_pdm_pcm_config_t   cy_stc_smartio_config_t   IPC_STRUCT_Type   
cy_stc_canfd_f1_t   cy_stc_csd_context_t   cy_stc_pll_config_t   cy_stc_smartio_ducfg_t   
  l  
cy_stc_canfd_global_filter_config_t   cy_stc_ctb_config_t   cy_stc_pll_manual_config_t   cy_stc_smartio_lutcfg_t   
cy_stc_canfd_interrupt_handling_t   cy_stc_ctb_fast_config_oa0_t   cy_stc_ppu_gr_cfg_t   cy_stc_smif_block_config_t   MCWDT_STRUCT_Type   
cy_stc_canfd_r0_t   cy_stc_ctb_fast_config_oa1_t   cy_stc_ppu_prog_cfg_t   cy_stc_smif_config_t   
  p  
+
cy_stc_canfd_interrupt_handling_t   cy_stc_ctb_fast_config_oa0_t   cy_stc_ppu_gr_cfg_t   cy_stc_smif_block_config_t   LPCOMP_Type   
cy_stc_canfd_r0_t   cy_stc_ctb_fast_config_oa1_t   cy_stc_ppu_prog_cfg_t   cy_stc_smif_config_t   
  m  
cy_stc_canfd_r1_t   cy_stc_ctb_opamp_config_t   cy_stc_ppu_rg_cfg_t   cy_stc_smif_context_t   
cy_stc_canfd_rx_buffer_t   cy_stc_ctdac_config_t   cy_stc_ppu_sl_cfg_t   cy_stc_smif_mem_cmd_t   PDM_Type   
cy_stc_canfd_sid_filter_config_t   cy_stc_ctdac_context_t   cy_stc_profile_ctr_ctl_t   cy_stc_smif_mem_config_t   PERI_GR_PPU_RG_Type   
cy_stc_canfd_t0_t   cy_stc_ctdac_fast_config_t   cy_stc_profile_ctr_t   cy_stc_smif_mem_device_cfg_t   PERI_GR_PPU_SL_Type   
cy_stc_canfd_t1_t   cy_stc_dma_channel_config_t   cy_stc_rtc_alarm_t   cy_stc_smpu_cfg_t   PERI_PPU_GR_Type   
cy_stc_canfd_transceiver_delay_compensation_t   cy_stc_dma_crc_config_t   cy_stc_rtc_config_t   cy_stc_sysanalog_config_t   PERI_PPU_PR_Type   
cy_stc_canfd_tx_buffer_t   cy_stc_dma_descriptor_config_t   cy_stc_rtc_dst_format_t   cy_stc_sysint_t   PROT_MPU_MPU_STRUCT_Type   
cy_stc_crypto_aes_buffers_t   cy_stc_dma_descriptor_t   cy_stc_rtc_dst_t   cy_stc_syspm_backup_regs_t   PROT_SMPU_SMPU_STRUCT_Type   
cy_stc_crypto_aes_state_t   cy_stc_dmac_channel_config_t   cy_stc_sar_config_t   cy_stc_syspm_callback_params_t   
  s  
+
cy_stc_canfd_rx_buffer_t   cy_stc_ctdac_config_t   cy_stc_ppu_sl_cfg_t   cy_stc_smif_hybrid_region_info_t   MCWDT_STRUCT_Type   
cy_stc_canfd_sid_filter_config_t   cy_stc_ctdac_context_t   cy_stc_profile_ctr_ctl_t   cy_stc_smif_mem_cmd_t   
  p  
cy_stc_crypto_config_t   cy_stc_dmac_descriptor_config_t   cy_stc_sar_state_backup_t   cy_stc_syspm_callback_t   
cy_stc_crypto_context_aes_t   cy_stc_dmac_descriptor_t   cy_stc_scb_ezi2c_config_t   cy_stc_tcpwm_counter_config_t   SAR_Type   
cy_stc_crypto_context_crc_t   cy_stc_efuse_data_t   cy_stc_scb_ezi2c_context_t   cy_stc_tcpwm_pwm_config_t   SMIF_Type   
cy_stc_crypto_context_des_t   cy_stc_extid_filter_t   cy_stc_scb_i2c_config_t   cy_stc_tcpwm_quaddec_config_t   
  t  
+
cy_stc_canfd_t0_t   cy_stc_ctdac_fast_config_t   cy_stc_profile_ctr_t   cy_stc_smif_mem_config_t   
cy_stc_canfd_t1_t   cy_stc_dma_channel_config_t   cy_stc_rtc_alarm_t   cy_stc_smif_mem_device_cfg_t   PDM_Type   
cy_stc_canfd_transceiver_delay_compensation_t   cy_stc_dma_crc_config_t   cy_stc_rtc_config_t   cy_stc_smpu_cfg_t   PERI_GR_PPU_RG_Type   
cy_stc_canfd_tx_buffer_t   cy_stc_dma_descriptor_config_t   cy_stc_rtc_dst_format_t   cy_stc_sysanalog_config_t   PERI_GR_PPU_SL_Type   
cy_stc_crypto_aes_buffers_t   cy_stc_dma_descriptor_t   cy_stc_rtc_dst_t   cy_stc_sysint_t   PERI_PPU_GR_Type   
cy_stc_crypto_aes_state_t   cy_stc_dmac_channel_config_t   cy_stc_sar_config_t   cy_stc_syspm_backup_regs_t   PERI_PPU_PR_Type   
cy_stc_crypto_config_t   cy_stc_dmac_descriptor_config_t   cy_stc_sar_state_backup_t   cy_stc_syspm_callback_params_t   PROT_MPU_MPU_STRUCT_Type   
cy_stc_crypto_context_aes_t   cy_stc_dmac_descriptor_t   cy_stc_scb_ezi2c_config_t   cy_stc_syspm_callback_t   PROT_SMPU_SMPU_STRUCT_Type   
cy_stc_crypto_context_crc_t   cy_stc_efuse_data_t   cy_stc_scb_ezi2c_context_t   cy_stc_tcpwm_counter_config_t   
  s  
cy_stc_crypto_context_ecc_t   cy_stc_fault_frame_t   cy_stc_scb_i2c_context_t   cy_stc_usb_dev_ep_config_t   
cy_stc_crypto_context_prng_t   cy_stc_flash_notify_t   cy_stc_scb_i2c_master_xfer_config_t   cy_stc_usbfs_dev_drv_config_t   TCPWM_Type   
cy_stc_crypto_context_rsa_t   cy_stc_fll_manual_config_t   cy_stc_scb_spi_config_t   cy_stc_usbfs_dev_drv_context_t   
cy_stc_crypto_context_rsa_ver_t   cy_stc_gpio_pin_config_t   cy_stc_scb_spi_context_t   cy_stc_usbfs_dev_drv_dma_config_t   
cy_stc_crypto_context_sha_t   cy_stc_gpio_prt_config_t   cy_stc_scb_uart_config_t   CySCB_Type   
cy_stc_crypto_context_str_t   cy_stc_i2s_config_t   cy_stc_scb_uart_context_t   
  d  
-
DW_Type   
cy_stc_crypto_context_des_t   cy_stc_extid_filter_t   cy_stc_scb_i2c_config_t   cy_stc_tcpwm_pwm_config_t   
cy_stc_crypto_context_ecc_t   cy_stc_fault_frame_t   cy_stc_scb_i2c_context_t   cy_stc_tcpwm_quaddec_config_t   SAR_Type   
cy_stc_crypto_context_prng_t   cy_stc_flash_notify_t   cy_stc_scb_i2c_master_xfer_config_t   cy_stc_usb_dev_ep_config_t   SMIF_Type   
cy_stc_crypto_context_rsa_t   cy_stc_fll_manual_config_t   cy_stc_scb_spi_config_t   cy_stc_usbfs_dev_drv_config_t   
  t  
+
cy_stc_crypto_context_rsa_ver_t   cy_stc_gpio_pin_config_t   cy_stc_scb_spi_context_t   cy_stc_usbfs_dev_drv_context_t   
cy_stc_crypto_context_sha_t   cy_stc_gpio_prt_config_t   cy_stc_scb_uart_config_t   cy_stc_usbfs_dev_drv_dma_config_t   TCPWM_Type   
cy_stc_crypto_context_str_t   cy_stc_i2s_config_t   cy_stc_scb_uart_context_t   CySCB_Type   
c | d | g | i | l | m | p | s | t
diff --git a/docs/pdl_api_reference_manual/html/functions_e.html b/docs/pdl_api_reference_manual/html/functions_e.html index 058b250..1e4a33e 100644 --- a/docs/pdl_api_reference_manual/html/functions_e.html +++ b/docs/pdl_api_reference_manual/html/functions_e.html @@ -212,13 +212,16 @@

- e -

    : cy_stc_ipc_pipe_ep_config_t
  • eraseCmd -: cy_stc_smif_mem_device_cfg_t +: cy_stc_smif_hybrid_region_info_t +, cy_stc_smif_mem_device_cfg_t
  • eraseSize -: cy_stc_smif_mem_device_cfg_t +: cy_stc_smif_hybrid_region_info_t +, cy_stc_smif_mem_device_cfg_t
  • eraseTime -: cy_stc_smif_mem_device_cfg_t +: cy_stc_smif_hybrid_region_info_t +, cy_stc_smif_mem_device_cfg_t
  • errorCallback : cy_stc_canfd_config_t diff --git a/docs/pdl_api_reference_manual/html/functions_h.html b/docs/pdl_api_reference_manual/html/functions_h.html index 1206cc0..1fe4a87 100644 --- a/docs/pdl_api_reference_manual/html/functions_h.html +++ b/docs/pdl_api_reference_manual/html/functions_h.html @@ -115,6 +115,12 @@

    - h -

    • hwEnabled : cy_stc_sar_state_backup_t
      • +
    • hybridRegionCount +: cy_stc_smif_mem_device_cfg_t +
      • +
    • hybridRegionInfo +: cy_stc_smif_mem_device_cfg_t +
    • hysteresis : cy_stc_lpcomp_config_t
      • diff --git a/docs/pdl_api_reference_manual/html/functions_r.html b/docs/pdl_api_reference_manual/html/functions_r.html index 4786822..490ad48 100644 --- a/docs/pdl_api_reference_manual/html/functions_r.html +++ b/docs/pdl_api_reference_manual/html/functions_r.html @@ -156,6 +156,9 @@

      - r -

        : cy_stc_ctdac_config_t , cy_stc_ctdac_fast_config_t +
      • regionAddress +: cy_stc_smif_hybrid_region_info_t +
      • regionSize : cy_stc_mpu_cfg_t , cy_stc_ppu_prog_cfg_t diff --git a/docs/pdl_api_reference_manual/html/functions_s.html b/docs/pdl_api_reference_manual/html/functions_s.html index 95a0dcb..c27fa24 100644 --- a/docs/pdl_api_reference_manual/html/functions_s.html +++ b/docs/pdl_api_reference_manual/html/functions_s.html @@ -105,6 +105,9 @@

        - s -

        • secEn : cy_stc_rtc_alarm_t
          • +
        • sectorsCount +: cy_stc_smif_hybrid_region_info_t +
        • secure : cy_stc_mpu_cfg_t , cy_stc_ppu_gr_cfg_t diff --git a/docs/pdl_api_reference_manual/html/functions_vars_e.html b/docs/pdl_api_reference_manual/html/functions_vars_e.html index f617826..7407c67 100644 --- a/docs/pdl_api_reference_manual/html/functions_vars_e.html +++ b/docs/pdl_api_reference_manual/html/functions_vars_e.html @@ -212,13 +212,16 @@

          - e -

            : cy_stc_ipc_pipe_ep_config_t
          • eraseCmd -: cy_stc_smif_mem_device_cfg_t +: cy_stc_smif_hybrid_region_info_t +, cy_stc_smif_mem_device_cfg_t
          • eraseSize -: cy_stc_smif_mem_device_cfg_t +: cy_stc_smif_hybrid_region_info_t +, cy_stc_smif_mem_device_cfg_t
          • eraseTime -: cy_stc_smif_mem_device_cfg_t +: cy_stc_smif_hybrid_region_info_t +, cy_stc_smif_mem_device_cfg_t
          • errorCallback : cy_stc_canfd_config_t diff --git a/docs/pdl_api_reference_manual/html/functions_vars_h.html b/docs/pdl_api_reference_manual/html/functions_vars_h.html index 46a7d34..a18d027 100644 --- a/docs/pdl_api_reference_manual/html/functions_vars_h.html +++ b/docs/pdl_api_reference_manual/html/functions_vars_h.html @@ -115,6 +115,12 @@

            - h -

            Some clock paths such as path 0 and path 1 have additional resources that can be utilized to provide a higher frequency clock. For example, path 0 source clock can be used as the reference clock for the FLL and path 1 source clock can be used as the reference clock for the PLL.

            diff --git a/docs/pdl_api_reference_manual/html/group__group__sysclk__path__src__funcs.html b/docs/pdl_api_reference_manual/html/group__group__sysclk__path__src__funcs.html index eef9863..ca71674 100644 --- a/docs/pdl_api_reference_manual/html/group__group__sysclk__path__src__funcs.html +++ b/docs/pdl_api_reference_manual/html/group__group__sysclk__path__src__funcs.html @@ -96,6 +96,12 @@ cy_en_clkpath_in_sources_t Cy_SysClk_ClkPathGetSource (uint32_t clkPath)  Reports which source is selected for the path mux. More...
              +uint32_t Cy_SysClk_ClkPathMuxGetFrequency (uint32_t clkPath) + Returns the output frequency of the clock path mux. More...
            +  +uint32_t Cy_SysClk_ClkPathGetFrequency (uint32_t clkPath) + Returns the output frequency of the clock path mux. More...
            + 

            Function Documentation

            @@ -140,7 +146,7 @@

            Cy_SysLib_SetWaitStates before calling this function if it affects the CLK_HF0 frequency and the frequency is increasing.
            Call Cy_SysLib_SetWaitStates after calling this function if it affects the CLK_HF0 frequency and the frequency is decreasing.
            -
            Function Usage
            /* Scenario: ECO needs to source HFCLK2 through Path 2. The ECO is
            configured through its function calls. */
            /* Set the clock path 2 mux to be sourced from ECO */
            if(CY_SYSCLK_SUCCESS != Cy_SysClk_ClkPathSetSource(2UL, CY_SYSCLK_CLKPATH_IN_ECO))
            {
            /* Perform error handling */
            }
            /* Set the HFCLK2 source to clock path 2 and enable HFCLK2 */
            (void)Cy_SysClk_ClkHfSetSource(2UL, CY_SYSCLK_CLKHF_IN_CLKPATH2);
            /* Enable HFCLK2 */
            (void)Cy_SysClk_ClkHfEnable(2UL);
            +
            Function Usage
            /* Scenario: ECO needs to source HFCLK2 through Path 2. The ECO is
            configured through its function calls. */
            #define CLKPATH2 (2UL)
            #define HFCLK2 (2UL)
            uint32_t clkPathMuxFreq = 0UL; /* Variable to store the Clock Path Mux output frequency */
            /* Set the clock path 2 mux to be sourced from ECO */
            if(CY_SYSCLK_SUCCESS == Cy_SysClk_ClkPathSetSource(CLKPATH2, CY_SYSCLK_CLKPATH_IN_ECO))
            {
            clkPathMuxFreq = Cy_SysClk_ClkPathMuxGetFrequency(CLKPATH2);
            /* Now clkPathMuxFreq contains the Clock Path Mux output frequency */
            }
            else
            {
            /* Perform error handling */
            }
            /* Set the HFCLK2 source to clock path 2 and enable HFCLK2 */
            (void)Cy_SysClk_ClkHfSetSource(HFCLK2, CY_SYSCLK_CLKHF_IN_CLKPATH2);
            /* Enable HFCLK2 */
            (void)Cy_SysClk_ClkHfEnable(HFCLK2);
            @@ -168,7 +174,61 @@

            Returns
            cy_en_clkpath_in_sources_t
            -
            Function Usage
            /* Scenario: A peripheral derived off of Path 1 clock is not clocking at the
            expected frequency and accuracy. Need to confirm that the source
            of the Path 1 mux is the ECO. */
            /* Get the source of the clock path 1 mux */
            if(CY_SYSCLK_CLKPATH_IN_ECO != Cy_SysClk_ClkPathGetSource(1UL))
            {
            /* Insert error handling */
            }
            +
            Function Usage
            /* Scenario: A peripheral derived off of Path 1 clock is not clocking at the
            expected frequency and accuracy. Need to confirm that the source
            of the Path 1 mux is the ECO. */
            /* Get the source of the clock path 1 mux */
            if(CY_SYSCLK_CLKPATH_IN_ECO != Cy_SysClk_ClkPathGetSource(1UL))
            {
            /* Insert error handling */
            }
            + + + + +

            ◆ Cy_SysClk_ClkPathMuxGetFrequency()

            + +
            +
            + + + + + + + + +
            uint32_t Cy_SysClk_ClkPathMuxGetFrequency (uint32_t clkPath)
            +
            + +

            Returns the output frequency of the clock path mux.

            +
            Returns
            The output frequency of the path mux.
            +
            Note
            If the return value equals zero, that means either:
              +
            • the selected path mux source signal frequency is unknown (e.g. dsi_out, etc.) or
              • +
            • the selected path mux source is not configured/enabled/stable (e.g. ECO, EXTCLK, etc.).
              • +
            +
            +
            Function Usage
            /* Scenario: ECO needs to source HFCLK2 through Path 2. The ECO is
            configured through its function calls. */
            #define CLKPATH2 (2UL)
            #define HFCLK2 (2UL)
            uint32_t clkPathMuxFreq = 0UL; /* Variable to store the Clock Path Mux output frequency */
            /* Set the clock path 2 mux to be sourced from ECO */
            if(CY_SYSCLK_SUCCESS == Cy_SysClk_ClkPathSetSource(CLKPATH2, CY_SYSCLK_CLKPATH_IN_ECO))
            {
            clkPathMuxFreq = Cy_SysClk_ClkPathMuxGetFrequency(CLKPATH2);
            /* Now clkPathMuxFreq contains the Clock Path Mux output frequency */
            }
            else
            {
            /* Perform error handling */
            }
            /* Set the HFCLK2 source to clock path 2 and enable HFCLK2 */
            (void)Cy_SysClk_ClkHfSetSource(HFCLK2, CY_SYSCLK_CLKHF_IN_CLKPATH2);
            /* Enable HFCLK2 */
            (void)Cy_SysClk_ClkHfEnable(HFCLK2);
            + +
            +
            + +

            ◆ Cy_SysClk_ClkPathGetFrequency()

            + +
            +
            + + + + + + + + +
            uint32_t Cy_SysClk_ClkPathGetFrequency (uint32_t clkPath)
            +
            + +

            Returns the output frequency of the clock path mux.

            +
            Returns
            The output frequency of the path mux.
            +
            Note
            If the return value equals zero, that means either:
              +
            • the selected path mux source signal frequency is unknown (e.g. dsi_out, etc.) or
              • +
            • the selected path mux source is not configured/enabled/stable (e.g. ECO, EXTCLK, etc.).
              • +
            +
            +
            Function Usage
            /* Scenario: FLL is configured and needs to be enabled within 2 ms */
            #define CLKPATH0 (0UL)
            uint32_t clkPathFreq = 0UL; /* Variable to store the Clock Path output frequency */
            /* Enable the FLL with a timeout of 2000 microseconds */
            if (CY_SYSCLK_SUCCESS == Cy_SysClk_FllEnable(2000UL))
            {
            clkPathFreq = Cy_SysClk_ClkPathGetFrequency(CLKPATH0);
            /* Now clkPathFreq contains an actual FLL frequency */
            }
            else
            {
            /* Insert error handling */
            }
            diff --git a/docs/pdl_api_reference_manual/html/group__group__sysclk__path__src__funcs.js b/docs/pdl_api_reference_manual/html/group__group__sysclk__path__src__funcs.js index 0df9ade..bbb546d 100644 --- a/docs/pdl_api_reference_manual/html/group__group__sysclk__path__src__funcs.js +++ b/docs/pdl_api_reference_manual/html/group__group__sysclk__path__src__funcs.js @@ -1,5 +1,7 @@ var group__group__sysclk__path__src__funcs = [ [ "Cy_SysClk_ClkPathSetSource", "group__group__sysclk__path__src__funcs.html#ga517f603266062d0013947ea950ed5b60", null ], - [ "Cy_SysClk_ClkPathGetSource", "group__group__sysclk__path__src__funcs.html#gab1c9f683f870696d41786c3df1eb331b", null ] + [ "Cy_SysClk_ClkPathGetSource", "group__group__sysclk__path__src__funcs.html#gab1c9f683f870696d41786c3df1eb331b", null ], + [ "Cy_SysClk_ClkPathMuxGetFrequency", "group__group__sysclk__path__src__funcs.html#ga1256c8a7290cecf2b9553a1df582e797", null ], + [ "Cy_SysClk_ClkPathGetFrequency", "group__group__sysclk__path__src__funcs.html#ga54c618c89782d227fb8f292d1dc15625", null ] ]; \ No newline at end of file diff --git a/docs/pdl_api_reference_manual/html/group__group__sysclk__pilo__funcs.html b/docs/pdl_api_reference_manual/html/group__group__sysclk__pilo__funcs.html index 2d0b1d2..ab9edf6 100644 --- a/docs/pdl_api_reference_manual/html/group__group__sysclk__pilo__funcs.html +++ b/docs/pdl_api_reference_manual/html/group__group__sysclk__pilo__funcs.html @@ -93,6 +93,9 @@ __STATIC_INLINE void Cy_SysClk_PiloEnable (void)  Enables the PILO. More...
              +__STATIC_INLINE bool Cy_SysClk_PiloIsEnabled (void) + Reports the Enabled/Disabled status of the PILO. More...
            +  __STATIC_INLINE void Cy_SysClk_PiloDisable (void)  Disables the PILO. More...
              @@ -122,7 +125,29 @@

            Note
            This function blocks for 1 millisecond between enabling the PILO and releasing the PILO reset.
            -
            Function Usage
            /* Scenario: PILO needs to source the LFCLK. All peripherals clocked by
            the LFCLK are disabled and the Watchdog timer (WDT) is unlocked. */
            /* Enable the PILO. Note: Blocks for 1 millisecond. */
            Cy_SysClk_PiloEnable();
            /* Set the LFCLK source to the PILO */
            Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_PILO);
            +
            Function Usage
            /* Scenario: PILO needs to source the LFCLK. All peripherals clocked by
            the LFCLK are disabled and the Watchdog timer (WDT) is unlocked. */
            /* Enable the PILO. Note: Blocks for 1 millisecond. */
            Cy_SysClk_PiloEnable();
            /* Set the LFCLK source to the PILO */
            Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_PILO);
            + + + + +

            ◆ Cy_SysClk_PiloIsEnabled()

            + +
            +
            + + + + + + + + +
            __STATIC_INLINE bool Cy_SysClk_PiloIsEnabled (void )
            +
            + +

            Reports the Enabled/Disabled status of the PILO.

            +
            Returns
            Boolean status of PILO: true - Enabled, false - Disabled.
            +
            Function Usage
            /* Scenario: LFCLK needs to be sourced by the ILO instead of the PILO. All
            peripherals clocked by the LFCLK are disabled and the Watchdog
            timer (WDT) is unlocked. */
            if (Cy_SysClk_PiloIsEnabled())
            {
            /* Disable the PILO */
            Cy_SysClk_PiloDisable();
            /* Enable the ILO */
            Cy_SysClk_IloEnable();
            /* Set the LFCLK source to the ILO */
            Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_ILO);
            }
            @@ -143,7 +168,7 @@

            Disables the PILO.

            -
            Function Usage
            /* Scenario: LFCLK needs to be sourced by the ILO instead of the PILO. All
            peripherals clocked by the LFCLK are disabled and the Watchdog
            timer (WDT) is unlocked. */
            /* Disable the PILO */
            Cy_SysClk_PiloDisable();
            /* Enable the ILO */
            Cy_SysClk_IloEnable();
            /* Set the LFCLK source to the ILO */
            Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_ILO);
            +
            Function Usage
            /* Scenario: LFCLK needs to be sourced by the ILO instead of the PILO. All
            peripherals clocked by the LFCLK are disabled and the Watchdog
            timer (WDT) is unlocked. */
            if (Cy_SysClk_PiloIsEnabled())
            {
            /* Disable the PILO */
            Cy_SysClk_PiloDisable();
            /* Enable the ILO */
            Cy_SysClk_IloEnable();
            /* Set the LFCLK source to the ILO */
            Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_ILO);
            }
            @@ -165,7 +190,7 @@

            Cy_SysClk_StartClkMeasurementCounters().

            -
            Function Usage
            /* Scenario: PILO needs to be trimmed to +/- 2% of nominal 32.768 kHz using
            the ECO as the source. */
            #define ECO_FREQ 24000000UL /* 24 MHz ECO */
            #define PILO_NOMINAL 32768UL /* 32.768 kHz PILO */
            #define PILO_ACCURACY 655UL /* PILO_NOMINAL * 0.02 */
            bool trimStatus = false;
            while(!trimStatus)
            {
            /* Start the PILO clock measurement using the IMO */
            (void)Cy_SysClk_StartClkMeasurementCounters(CY_SYSCLK_MEAS_CLK_PILO, /* Counter 1 clock = PILO */
            0x3FFUL, /* Counter 1 init value = 1024 */
            CY_SYSCLK_MEAS_CLK_ECO); /* Counter 2 clock = ECO */
            /* Wait for counter 1 to reach 0 */
            while (!Cy_SysClk_ClkMeasurementCountersDone()){};
            /* Measure clock 1 with the ECO clock cycles (counter 2) */
            uint32_t measuredFreq = Cy_SysClk_ClkMeasurementCountersGetFreq(false, ECO_FREQ);
            /* Increment/decrement the trim depending on the returned result */
            if ((PILO_NOMINAL + PILO_ACCURACY) < measuredFreq)
            {
            Cy_SysClk_PiloSetTrim(Cy_SysClk_PiloGetTrim() - 1UL);
            }
            else if (measuredFreq < (PILO_NOMINAL - PILO_ACCURACY))
            {
            Cy_SysClk_PiloSetTrim(Cy_SysClk_PiloGetTrim() + 1UL);
            }
            else
            {
            /* Trimmed within limits */
            trimStatus = true;
            }
            }
            +
            Function Usage
            /* Scenario: PILO needs to be trimmed to +/- 2% of nominal 32.768 kHz using
            the ECO as the source. */
            #define ECO_FREQ 24000000UL /* 24 MHz ECO */
            #define PILO_NOMINAL 32768UL /* 32.768 kHz PILO */
            #define PILO_ACCURACY 655UL /* PILO_NOMINAL * 0.02 */
            bool trimStatus = false;
            while(!trimStatus)
            {
            /* Start the PILO clock measurement using the IMO */
            (void)Cy_SysClk_StartClkMeasurementCounters(CY_SYSCLK_MEAS_CLK_PILO, /* Counter 1 clock = PILO */
            0x3FFUL, /* Counter 1 init value = 1024 */
            CY_SYSCLK_MEAS_CLK_ECO); /* Counter 2 clock = ECO */
            /* Wait for counter 1 to reach 0 */
            while (!Cy_SysClk_ClkMeasurementCountersDone()){};
            /* Measure clock 1 with the ECO clock cycles (counter 2) */
            uint32_t measuredFreq = Cy_SysClk_ClkMeasurementCountersGetFreq(false, ECO_FREQ);
            /* Increment/decrement the trim depending on the returned result */
            if ((PILO_NOMINAL + PILO_ACCURACY) < measuredFreq)
            {
            Cy_SysClk_PiloSetTrim(Cy_SysClk_PiloGetTrim() - 1UL);
            }
            else if (measuredFreq < (PILO_NOMINAL - PILO_ACCURACY))
            {
            Cy_SysClk_PiloSetTrim(Cy_SysClk_PiloGetTrim() + 1UL);
            }
            else
            {
            /* Trimmed within limits */
            trimStatus = true;
            }
            }
            @@ -186,7 +211,7 @@

            Reports the current PILO trim bits value.

            -
            Function Usage
            Refer to the Cy_SysClk_PiloSetTrim() function usage.
            +
            Function Usage
            /* Scenario: PILO needs to be trimmed to +/- 2% of nominal 32.768 kHz using
            the ECO as the source. */
            #define ECO_FREQ 24000000UL /* 24 MHz ECO */
            #define PILO_NOMINAL 32768UL /* 32.768 kHz PILO */
            #define PILO_ACCURACY 655UL /* PILO_NOMINAL * 0.02 */
            bool trimStatus = false;
            while(!trimStatus)
            {
            /* Start the PILO clock measurement using the IMO */
            (void)Cy_SysClk_StartClkMeasurementCounters(CY_SYSCLK_MEAS_CLK_PILO, /* Counter 1 clock = PILO */
            0x3FFUL, /* Counter 1 init value = 1024 */
            CY_SYSCLK_MEAS_CLK_ECO); /* Counter 2 clock = ECO */
            /* Wait for counter 1 to reach 0 */
            while (!Cy_SysClk_ClkMeasurementCountersDone()){};
            /* Measure clock 1 with the ECO clock cycles (counter 2) */
            uint32_t measuredFreq = Cy_SysClk_ClkMeasurementCountersGetFreq(false, ECO_FREQ);
            /* Increment/decrement the trim depending on the returned result */
            if ((PILO_NOMINAL + PILO_ACCURACY) < measuredFreq)
            {
            Cy_SysClk_PiloSetTrim(Cy_SysClk_PiloGetTrim() - 1UL);
            }
            else if (measuredFreq < (PILO_NOMINAL - PILO_ACCURACY))
            {
            Cy_SysClk_PiloSetTrim(Cy_SysClk_PiloGetTrim() + 1UL);
            }
            else
            {
            /* Trimmed within limits */
            trimStatus = true;
            }
            }
            diff --git a/docs/pdl_api_reference_manual/html/group__group__sysclk__pilo__funcs.js b/docs/pdl_api_reference_manual/html/group__group__sysclk__pilo__funcs.js index 8cb0d0b..16e2172 100644 --- a/docs/pdl_api_reference_manual/html/group__group__sysclk__pilo__funcs.js +++ b/docs/pdl_api_reference_manual/html/group__group__sysclk__pilo__funcs.js @@ -1,6 +1,7 @@ var group__group__sysclk__pilo__funcs = [ [ "Cy_SysClk_PiloEnable", "group__group__sysclk__pilo__funcs.html#ga4a6570666d4462b97d86e05f4e9fd492", null ], + [ "Cy_SysClk_PiloIsEnabled", "group__group__sysclk__pilo__funcs.html#ga5884a1be24c8d6680c80f4f857d31bb2", null ], [ "Cy_SysClk_PiloDisable", "group__group__sysclk__pilo__funcs.html#ga954f6432534797a063e1485f50d6db79", null ], [ "Cy_SysClk_PiloSetTrim", "group__group__sysclk__pilo__funcs.html#ga3ad33424ef17a1ee78ce67e12273d763", null ], [ "Cy_SysClk_PiloGetTrim", "group__group__sysclk__pilo__funcs.html#ga5847234c409635c28170eb61eb5ae20a", null ] diff --git a/docs/pdl_api_reference_manual/html/group__group__sysclk__pll__funcs.html b/docs/pdl_api_reference_manual/html/group__group__sysclk__pll__funcs.html index 8568c0d..4a22a95 100644 --- a/docs/pdl_api_reference_manual/html/group__group__sysclk__pll__funcs.html +++ b/docs/pdl_api_reference_manual/html/group__group__sysclk__pll__funcs.html @@ -164,7 +164,7 @@

            Cy_SysLib_SetWaitStates before calling this function if the PLL is the source of CLK_HF0 and the PLL frequency is increasing.
            Call Cy_SysLib_SetWaitStates after calling this function if the PLL is the source of CLK_HF0 and the PLL frequency is decreasing.
            -
            Function Usage
            /* Scenario: PLL needs to source HFCLK0, which must operate at 100 MHz.
            The IMO sources the PLL at 8MHz. Startup time is not an issue
            and manual configuration of the PLL is not needed. */
            cy_stc_pll_config_t pllConfig =
            {
            /*.inputFreq =*/ 8000000UL, /* PLL input: 8 MHz IMO */
            /*.outputFreq =*/ 100000000UL, /* PLL output: 100 MHz */
            /*.lfMode =*/ true, /* Enable low frequency mode (VCO = 170~200 MHz) */
            /*.outputMode =*/ CY_SYSCLK_FLLPLL_OUTPUT_AUTO /* Output 100 MHz when locked. Otherwise 8 MHz */
            };
            /* Set the PLL source (path 1 mux) to be the IMO.
            Note: Path 0 is not valid for PLL. */
            (void)Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_IMO);
            /* Configure Path 1 PLL with the settings in pllConfig struct */
            if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllConfigure(1UL, &pllConfig))
            {
            /* Insert error handling */
            }
            /* Enable the Path 1 PLL with 2000 microsecond timeout */
            if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(1UL, 2000UL))
            {
            /* Insert error handling */
            }
            /* Set the HFCLK0 source to clock path 1 */
            (void)Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH1);
            +
            Function Usage
            /* Scenario: PLL needs to source HFCLK0, which must operate at 100 MHz.
            The IMO sources the PLL at 8MHz. Startup time is not an issue
            and manual configuration of the PLL is not needed. */
            cy_stc_pll_config_t pllConfig =
            {
            /*.inputFreq =*/ 8000000UL, /* PLL input: 8 MHz IMO */
            /*.outputFreq =*/ 100000000UL, /* PLL output: 100 MHz */
            /*.lfMode =*/ true, /* Enable low frequency mode (VCO = 170~200 MHz) */
            /*.outputMode =*/ CY_SYSCLK_FLLPLL_OUTPUT_AUTO /* Output 100 MHz when locked. Otherwise 8 MHz */
            };
            /* Set the PLL source (path 1 mux) to be the IMO.
            Note: Path 0 is not valid for PLL. */
            (void)Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_IMO);
            /* Configure Path 1 PLL with the settings in pllConfig struct */
            if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllConfigure(1UL, &pllConfig))
            {
            /* Insert error handling */
            }
            /* Enable the Path 1 PLL with 2000 microsecond timeout */
            if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(1UL, 2000UL))
            {
            /* Insert error handling */
            }
            /* Set the HFCLK0 source to clock path 1 */
            (void)Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH1);
            @@ -215,7 +215,7 @@

            Cy_SysLib_SetWaitStates before calling this function if the PLL is the source of CLK_HF0 and the PLL frequency is increasing.
            Call Cy_SysLib_SetWaitStates after calling this function if the PLL is the source of CLK_HF0 and the PLL frequency is decreasing.
            -
            Function Usage
            /* Scenario: PLL needs to source HFCLK0, which must operate at 100 MHz.
            The IMO sources the PLL at 8MHz. The characteristics of the
            PLL lock parameters are already known and the startup time
            for the PLL configuration must be minimized. */
            /* Refer to the TRM for the full set of equations used to calculate the parameters */
            cy_stc_pll_manual_config_t pllConfig =
            {
            /*.feedbackDiv =*/ 25u, /* Feedback divider */
            /*.referenceDiv =*/ 1u, /* Reference divider */
            /*.outputDiv =*/ 2u, /* Output divider */
            /*.lfMode =*/ true, /* Enable low frequency mode (VCO = 170~200 MHz) */
            /*.outputMode =*/ CY_SYSCLK_FLLPLL_OUTPUT_AUTO /* Output 100 MHz when locked. Otherwise 8 MHz */
            };
            /* Set the PLL source (path 1 mux) to be the IMO.
            Note: Path 0 is not valid for PLL. */
            (void)Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_IMO);
            /* Configure Path 1 PLL with the settings in pllConfig struct */
            if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(1UL, &pllConfig))
            {
            /* Insert error handling */
            }
            /* Enable the path 1 PLL with 2000 microsecond timeout */
            if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(1UL, 2000UL))
            {
            /* Insert error handling */
            }
            /* Set the HFCLK0 source to clock path 1 */
            (void)Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH1);
            +
            Function Usage
            /* Scenario: PLL needs to source HFCLK0, which must operate at 100 MHz.
            The IMO sources the PLL at 8MHz. The characteristics of the
            PLL lock parameters are already known and the startup time
            for the PLL configuration must be minimized. */
            /* Refer to the TRM for the full set of equations used to calculate the parameters */
            cy_stc_pll_manual_config_t pllConfig =
            {
            /*.feedbackDiv =*/ 25u, /* Feedback divider */
            /*.referenceDiv =*/ 1u, /* Reference divider */
            /*.outputDiv =*/ 2u, /* Output divider */
            /*.lfMode =*/ true, /* Enable low frequency mode (VCO = 170~200 MHz) */
            /*.outputMode =*/ CY_SYSCLK_FLLPLL_OUTPUT_AUTO /* Output 100 MHz when locked. Otherwise 8 MHz */
            };
            /* Set the PLL source (path 1 mux) to be the IMO.
            Note: Path 0 is not valid for PLL. */
            (void)Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_IMO);
            /* Configure Path 1 PLL with the settings in pllConfig struct */
            if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(1UL, &pllConfig))
            {
            /* Insert error handling */
            }
            /* Enable the path 1 PLL with 2000 microsecond timeout */
            if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(1UL, 2000UL))
            {
            /* Insert error handling */
            }
            /* Set the HFCLK0 source to clock path 1 */
            (void)Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH1);
            @@ -256,7 +256,7 @@

            Returns
            Error / status code:
            CY_SYSCLK_SUCCESS - PLL data successfully reported
            CY_SYSCLK_BAD_PARAM - invalid clock path number
            -
            Function Usage
            /* Scenario: The calculated PLL parameters need to be checked. */
            cy_stc_pll_config_t autoPllConfig =
            {
            /*.inputFreq =*/ 8000000UL, /* PLL input: 8 MHz IMO */
            /*.outputFreq =*/ 100000000UL, /* PLL output: 100 MHz */
            /*.lfMode =*/ true, /* Enable low frequency mode (VCO = 170~200 MHz) */
            /*.outputMode =*/ CY_SYSCLK_FLLPLL_OUTPUT_AUTO /* Output 100 MHz when locked. Otherwise 8 MHz */
            };
            cy_stc_pll_manual_config_t getPllParams;
            /* Configure Path 1 PLL with the settings in pllConfig struct */
            if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllConfigure(1UL, &autoPllConfig))
            {
            /* Insert error handling */
            }
            /* Retrieve the calculated parameters of Path 1 PLL */
            (void)Cy_SysClk_PllGetConfiguration(1UL, &getPllParams);
            +
            Function Usage
            /* Scenario: The calculated PLL parameters need to be checked. */
            cy_stc_pll_config_t autoPllConfig =
            {
            /*.inputFreq =*/ 8000000UL, /* PLL input: 8 MHz IMO */
            /*.outputFreq =*/ 100000000UL, /* PLL output: 100 MHz */
            /*.lfMode =*/ true, /* Enable low frequency mode (VCO = 170~200 MHz) */
            /*.outputMode =*/ CY_SYSCLK_FLLPLL_OUTPUT_AUTO /* Output 100 MHz when locked. Otherwise 8 MHz */
            };
            cy_stc_pll_manual_config_t getPllParams;
            /* Configure Path 1 PLL with the settings in pllConfig struct */
            if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllConfigure(1UL, &autoPllConfig))
            {
            /* Insert error handling */
            }
            /* Retrieve the calculated parameters of Path 1 PLL */
            (void)Cy_SysClk_PllGetConfiguration(1UL, &getPllParams);
            @@ -304,7 +304,7 @@

            Cy_SysLib_SetWaitStates before calling this function if the PLL is the source of CLK_HF0 and the CLK_HF0 frequency is increasing.
            Call Cy_SysLib_SetWaitStates after calling this function if the PLL is the source of CLK_HF0 and the CLK_HF0 frequency is decreasing.
            -
            Function Usage
            /* Scenario: PLL is configured and needs to be enabled within 2 ms */
            /* Enable the Path 1 PLL with a timeout of 2000 microsecond */
            if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(1UL, 2000UL))
            {
            /* Insert error handling */
            }
            +
            Function Usage
            /* Scenario: PLL is configured and needs to be enabled within 2 ms */
            /* Enable the Path 1 PLL with a timeout of 2000 microsecond */
            if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(1UL, 2000UL))
            {
            /* Insert error handling */
            }
            @@ -333,7 +333,7 @@

            Returns
            false = not locked
            true = locked
            -
            Function Usage
            /* Scenario: PLL is configured and needs to be enabled in a non-blocking way */
            /* Enable the Path 1 PLL without timeout */
            (void)Cy_SysClk_PllEnable(1UL, 0UL);
            /* Check the status of the lock */
            while(Cy_SysClk_PllLocked(1UL))
            {
            /* Perform other actions while the PLL is locking */
            }
            /* PLL Locked. Proceed with further configuration */
            +
            Function Usage
            /* Scenario: PLL is configured and needs to be enabled in a non-blocking way */
            /* Enable the Path 1 PLL without timeout */
            (void)Cy_SysClk_PllEnable(1UL, 0UL);
            /* Check the status of the lock */
            while(Cy_SysClk_PllLocked(1UL))
            {
            /* Perform other actions while the PLL is locking */
            }
            /* PLL Locked. Proceed with further configuration */
            @@ -362,7 +362,7 @@

            Returns
            false = disabled
            true = enabled
            -
            Function Usage
            /* Scenario: Path 1 PLL failed to enable and must be reconfigured. Or the
            PLL is no longer used and hence needs to be disabled. */
            if (Cy_SysClk_PllIsEnabled(1UL))
            {
            if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllDisable(1UL))
            {
            /* Insert error handling */
            }
            }
            /* The clocks that relied on the PLL will now run off of the clock that
            was used to source the FLL (e.g. IMO or ECO). */
            +
            Function Usage
            /* Scenario: Path 1 PLL failed to enable and must be reconfigured. Or the
            PLL is no longer used and hence needs to be disabled. */
            if (Cy_SysClk_PllIsEnabled(1UL))
            {
            if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllDisable(1UL))
            {
            /* Insert error handling */
            }
            }
            /* The clocks that relied on the PLL will now run off of the clock that
            was used to source the FLL (e.g. IMO or ECO). */
            @@ -392,7 +392,7 @@

            Returns
            false = did not lose lock
            true = lost lock
            -
            Function Usage
            /* Scenario: Suspicious change in Path 1 clock frequency was encountered
            in the application. Check if the Path 1 PLL lost the lock. */
            if(Cy_SysClk_PllLostLock(1UL))
            {
            /* Insert error handling */
            }
            +
            Function Usage
            /* Scenario: Suspicious change in Path 1 clock frequency was encountered
            in the application. Check if the Path 1 PLL lost the lock. */
            if(Cy_SysClk_PllLostLock(1UL))
            {
            /* Insert error handling */
            }
            @@ -427,7 +427,7 @@

            Cy_SysLib_SetWaitStates before calling this function if the PLL is the source of CLK_HF0 and the CLK_HF0 frequency is increasing.
            Call Cy_SysLib_SetWaitStates after calling this function if the PLL is the source of CLK_HF0 and the CLK_HF0 frequency is decreasing.
            -
            Function Usage
            /* Scenario: Path 1 PLL failed to enable and must be reconfigured. Or the
            PLL is no longer used and hence needs to be disabled. */
            if (Cy_SysClk_PllIsEnabled(1UL))
            {
            if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllDisable(1UL))
            {
            /* Insert error handling */
            }
            }
            /* The clocks that relied on the PLL will now run off of the clock that
            was used to source the FLL (e.g. IMO or ECO). */
            +
            Function Usage
            /* Scenario: Path 1 PLL failed to enable and must be reconfigured. Or the
            PLL is no longer used and hence needs to be disabled. */
            if (Cy_SysClk_PllIsEnabled(1UL))
            {
            if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllDisable(1UL))
            {
            /* Insert error handling */
            }
            }
            /* The clocks that relied on the PLL will now run off of the clock that
            was used to source the FLL (e.g. IMO or ECO). */
            diff --git a/docs/pdl_api_reference_manual/html/group__group__sysclk__pm__funcs.html b/docs/pdl_api_reference_manual/html/group__group__sysclk__pm__funcs.html index a3eb40b..b5e484a 100644 --- a/docs/pdl_api_reference_manual/html/group__group__sysclk__pm__funcs.html +++ b/docs/pdl_api_reference_manual/html/group__group__sysclk__pm__funcs.html @@ -147,7 +147,7 @@

            Returns
            Error / status code; see cy_en_syspm_status_t. Pass if not doing a clock measurement, otherwise Fail. Timeout if timeout waiting for ECO, FLL or PLL to get stable / regain its frequency lock.
            -
            Function Usage
            /* Scenario: The application uses FLL/PLL sourced from the ECO. The device
            needs to enter chip Deep Sleep. The ECO and FLL/PLL must be
            suitably prepared before entering low power mode. */
            /* Register all the Deep Sleep callbacks for other peripherals.
            The SysClk callback is recommended to be registered last to minimize
            the low power mode entry and wakeup timings. */
            cy_stc_syspm_callback_params_t clkCallbackParams = {
            /*.base =*/ NULL,
            /*.context =*/ NULL
            };
            cy_stc_syspm_callback_t clkCallback = {
            /*.callback =*/ &Cy_SysClk_DeepSleepCallback,
            /*.type =*/ CY_SYSPM_DEEPSLEEP,
            /*.skipMode =*/ 0UL,
            /*.callbackParams =*/ &clkCallbackParams,
            /*.prevItm =*/ NULL,
            /*.nextItm =*/ NULL,
            /*.order =*/ 0
            };
            /* Register the clock callback */
            if(!Cy_SysPm_RegisterCallback(&clkCallback))
            {
            /* Could not register callback. Examine the number of registered callbacks */
            }
            /* Ensure that the clock measurement is not running and enter chip Deep Sleep */
            +
            Function Usage
            /* Scenario: The application uses FLL/PLL sourced from the ECO. The device
            needs to enter chip Deep Sleep. The ECO and FLL/PLL must be
            suitably prepared before entering low power mode. */
            /* Register all the Deep Sleep callbacks for other peripherals.
            The SysClk callback is recommended to be registered last to minimize
            the low power mode entry and wakeup timings. */
            cy_stc_syspm_callback_params_t clkCallbackParams = {
            /*.base =*/ NULL,
            /*.context =*/ NULL
            };
            cy_stc_syspm_callback_t clkCallback = {
            /*.callback =*/ &Cy_SysClk_DeepSleepCallback,
            /*.type =*/ CY_SYSPM_DEEPSLEEP,
            /*.skipMode =*/ 0UL,
            /*.callbackParams =*/ &clkCallbackParams,
            /*.prevItm =*/ NULL,
            /*.nextItm =*/ NULL,
            /*.order =*/ 0
            };
            /* Register the clock callback */
            if(!Cy_SysPm_RegisterCallback(&clkCallback))
            {
            /* Could not register callback. Examine the number of registered callbacks */
            }
            /* Ensure that the clock measurement is not running and enter chip Deep Sleep */
            diff --git a/docs/pdl_api_reference_manual/html/group__group__sysclk__trim__funcs.html b/docs/pdl_api_reference_manual/html/group__group__sysclk__trim__funcs.html index 1d13ad6..3cf3fe3 100644 --- a/docs/pdl_api_reference_manual/html/group__group__sysclk__trim__funcs.html +++ b/docs/pdl_api_reference_manual/html/group__group__sysclk__trim__funcs.html @@ -123,7 +123,7 @@

            Returns
            Change in trim value - 0 if done; that is, no change in trim value.
            Note
            The watchdog timer (WDT) must be unlocked before calling this function.
            -
            Function Usage
            /* Scenario: ILO needs to be trimmed to +/- 1.5% of nominal 32.768 kHz using
            the IMO. The WDT is unlocked and all peripherals clocked using
            the ILO are disabled. */
            #define IMO_FREQ 8000000UL /* 8 MHz IMO */
            /* Start the ILO clock measurement using the IMO */
            (void)Cy_SysClk_StartClkMeasurementCounters(CY_SYSCLK_MEAS_CLK_ILO, /* Counter 1 clock = ILO */
            0x7FUL, /* Counter 1 period = 128 */
            CY_SYSCLK_MEAS_CLK_IMO); /* Counter 2 clock = IMO */
            /* Wait for counter 1 to reach 0 */
            while(!Cy_SysClk_ClkMeasurementCountersDone()){};
            /* Measure clock 1 with the IMO clock cycles (counter 2) */
            uint32_t measuredFreq = Cy_SysClk_ClkMeasurementCountersGetFreq(false, IMO_FREQ);
            /* Attempt to trim the ILO by 1 iteration step */
            int32_t trimDelta = Cy_SysClk_IloTrim(measuredFreq);
            if(0 != trimDelta)
            {
            /* Not yet trimmed to 1.5% of nominal 32.768 kHz. Repeat measurement and trim. */
            }
            +
            Function Usage
            /* Scenario: ILO needs to be trimmed to +/- 1.5% of nominal 32.768 kHz using
            the IMO. The WDT is unlocked and all peripherals clocked using
            the ILO are disabled. */
            #define IMO_FREQ 8000000UL /* 8 MHz IMO */
            /* Start the ILO clock measurement using the IMO */
            (void)Cy_SysClk_StartClkMeasurementCounters(CY_SYSCLK_MEAS_CLK_ILO, /* Counter 1 clock = ILO */
            0x7FUL, /* Counter 1 period = 128 */
            CY_SYSCLK_MEAS_CLK_IMO); /* Counter 2 clock = IMO */
            /* Wait for counter 1 to reach 0 */
            while(!Cy_SysClk_ClkMeasurementCountersDone()){};
            /* Measure clock 1 with the IMO clock cycles (counter 2) */
            uint32_t measuredFreq = Cy_SysClk_ClkMeasurementCountersGetFreq(false, IMO_FREQ);
            /* Attempt to trim the ILO by 1 iteration step */
            int32_t trimDelta = Cy_SysClk_IloTrim(measuredFreq);
            if(0 != trimDelta)
            {
            /* Not yet trimmed to 1.5% of nominal 32.768 kHz. Repeat measurement and trim. */
            }
            @@ -151,7 +151,7 @@

            Returns
            Change in trim value; 0 if done, that is, no change in trim value.
            -
            Function Usage
            /* Scenario: PILO needs to be trimmed to +/-250 ppm of nominal 32.768 kHz using
            the ECO. All peripherals clocked using the PILO are disabled. */
            #define ECO_FREQ 24000000UL /* 24 MHz ECO */
            /* Start the PILO clock measurement using the ECO */
            (void)Cy_SysClk_StartClkMeasurementCounters(CY_SYSCLK_MEAS_CLK_PILO, /* Counter 1 clock = PILO */
            0x3FFUL, /* Counter 1 init value = 1024 */
            CY_SYSCLK_MEAS_CLK_ECO); /* COunter 2 clock = ECO */
            /* Wait for counter 1 to reach 0 */
            while (!Cy_SysClk_ClkMeasurementCountersDone()){};
            /* Measure clock 1 with the ECO clock cycles (counter 2) */
            uint32_t measuredFreq = Cy_SysClk_ClkMeasurementCountersGetFreq(false, ECO_FREQ);
            /* Attempt to trim the PILO by 1 iteration step */
            uint32_t trimDelta = Cy_SysClk_PiloTrim(measuredFreq);
            if(0UL != trimDelta)
            {
            /* Not yet trimmed to nominal 32.768 kHz. Repeat measurement and trim. */
            }
            +
            Function Usage
            /* Scenario: PILO needs to be trimmed to +/-250 ppm of nominal 32.768 kHz using
            the ECO. All peripherals clocked using the PILO are disabled. */
            #define ECO_FREQ 24000000UL /* 24 MHz ECO */
            /* Start the PILO clock measurement using the ECO */
            (void)Cy_SysClk_StartClkMeasurementCounters(CY_SYSCLK_MEAS_CLK_PILO, /* Counter 1 clock = PILO */
            0x3FFUL, /* Counter 1 init value = 1024 */
            CY_SYSCLK_MEAS_CLK_ECO); /* COunter 2 clock = ECO */
            /* Wait for counter 1 to reach 0 */
            while (!Cy_SysClk_ClkMeasurementCountersDone()){};
            /* Measure clock 1 with the ECO clock cycles (counter 2) */
            uint32_t measuredFreq = Cy_SysClk_ClkMeasurementCountersGetFreq(false, ECO_FREQ);
            /* Attempt to trim the PILO by 1 iteration step */
            uint32_t trimDelta = Cy_SysClk_PiloTrim(measuredFreq);
            if(0UL != trimDelta)
            {
            /* Not yet trimmed to nominal 32.768 kHz. Repeat measurement and trim. */
            }
            diff --git a/docs/pdl_api_reference_manual/html/group__group__sysclk__wco__funcs.html b/docs/pdl_api_reference_manual/html/group__group__sysclk__wco__funcs.html index 251a5d8..08ecb69 100644 --- a/docs/pdl_api_reference_manual/html/group__group__sysclk__wco__funcs.html +++ b/docs/pdl_api_reference_manual/html/group__group__sysclk__wco__funcs.html @@ -130,7 +130,7 @@

            Returns
            Error / status code:
            CY_SYSCLK_SUCCESS - WCO successfully enabled
            CY_SYSCLK_TIMEOUT - Timeout waiting for WCO to stabilize
            -
            Function Usage
            /* Scenario: The WCO needs to source the backup clock for the real-time clock
            operation. Timeout of 2ms is tolerable. The WCO pins are configured
            using the gpio driver(SRSS_WCO_IN_PIN, SRSS_WCO_OUT_PIN). */
            /* Enable the WCO with a timeout of 2000 microseconds */
            if(CY_SYSCLK_SUCCESS != Cy_SysClk_WcoEnable(2000))
            {
            /* Insert error handling */
            }
            /* Set the backup clock source to WCO */
            Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_WCO);
            +
            Function Usage
            /* Scenario: The WCO needs to source the backup clock for the real-time clock
            operation. Timeout of 2ms is tolerable. The WCO pins are configured
            using the gpio driver(SRSS_WCO_IN_PIN, SRSS_WCO_OUT_PIN). */
            /* Enable the WCO with a timeout of 2000 microseconds */
            if(CY_SYSCLK_SUCCESS != Cy_SysClk_WcoEnable(2000))
            {
            /* Insert error handling */
            }
            /* Set the backup clock source to WCO */
            Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_WCO);
            @@ -153,7 +153,7 @@

            Returns
            true = okay
            false = not okay
            -
            Function Usage
            /* Scenario: The WCO needs to source the backup clock for the real-time
            clock operation. It needs to be enabled in a non-blocking
            manner. The WCO pins are configured using the gpio driver
            (SRSS_WCO_IN_PIN, SRSS_WCO_OUT_PIN). */
            /* Enable the WCO without timeout */
            (void)Cy_SysClk_WcoEnable(0UL);
            while(!Cy_SysClk_WcoOkay())
            {
            /* WCO is not yet ready. Perform some other operation. */
            }
            /* Set the backup clock source to WCO */
            Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_WCO);
            +
            Function Usage
            /* Scenario: The WCO needs to source the backup clock for the real-time
            clock operation. It needs to be enabled in a non-blocking
            manner. The WCO pins are configured using the gpio driver
            (SRSS_WCO_IN_PIN, SRSS_WCO_OUT_PIN). */
            /* Enable the WCO without timeout */
            (void)Cy_SysClk_WcoEnable(0UL);
            while(!Cy_SysClk_WcoOkay())
            {
            /* WCO is not yet ready. Perform some other operation. */
            }
            /* Set the backup clock source to WCO */
            Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_WCO);
            @@ -174,7 +174,7 @@

            Disables the WCO.

            -
            Function Usage
            /* Scenario: LFCLK needs to be sourced by the PILO instead of the WCO. All
            peripherals clocked by the LFCLK are disabled and the Watchdog
            timer (WDT) is unlocked. */
            /* Disable the WCO */
            Cy_SysClk_WcoDisable();
            /* Enable the PILO */
            Cy_SysClk_PiloEnable();
            /* Set the LFCLK source to the PILO */
            Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_PILO);
            +
            Function Usage
            /* Scenario: LFCLK needs to be sourced by the PILO instead of the WCO. All
            peripherals clocked by the LFCLK are disabled and the Watchdog
            timer (WDT) is unlocked. */
            /* Disable the WCO */
            Cy_SysClk_WcoDisable();
            /* Enable the PILO */
            Cy_SysClk_PiloEnable();
            /* Set the LFCLK source to the PILO */
            Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_PILO);
            @@ -202,7 +202,7 @@

            Function Usage
            /* Scenario: An external watch crystal oscillator needs to be connected to
            the WCO pins instead of a watch crystal. This signal needs
            to source the backup clock for the real-time clock operation.
            The WCO pins are configured using the gpio driver
            (SRSS_WCO_IN_PIN, SRSS_WCO_OUT_PIN). */
            /* WCO bypassed mode - 32768 kHz square-wave supplied through SRSS_WCO_OUT_PIN pin */
            Cy_SysClk_WcoBypass(CY_SYSCLK_WCO_BYPASSED);
            /* Enable the WCO with a timeout of 2000 microsecond */
            if(CY_SYSCLK_SUCCESS != Cy_SysClk_WcoEnable(2000UL))
            {
            /* Insert error handling */
            }
            /* Set the backup clock source to WCO */
            Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_WCO);
            +
            Function Usage
            /* Scenario: An external watch crystal oscillator needs to be connected to
            the WCO pins instead of a watch crystal. This signal needs
            to source the backup clock for the real-time clock operation.
            The WCO pins are configured using the gpio driver
            (SRSS_WCO_IN_PIN, SRSS_WCO_OUT_PIN). */
            /* WCO bypassed mode - 32768 kHz square-wave supplied through SRSS_WCO_OUT_PIN pin */
            Cy_SysClk_WcoBypass(CY_SYSCLK_WCO_BYPASSED);
            /* Enable the WCO with a timeout of 2000 microsecond */
            if(CY_SYSCLK_SUCCESS != Cy_SysClk_WcoEnable(2000UL))
            {
            /* Insert error handling */
            }
            /* Set the backup clock source to WCO */
            Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_WCO);
            diff --git a/docs/pdl_api_reference_manual/html/group__group__syslib.html b/docs/pdl_api_reference_manual/html/group__group__syslib.html index bb1ee99..30f5b32 100644 --- a/docs/pdl_api_reference_manual/html/group__group__syslib.html +++ b/docs/pdl_api_reference_manual/html/group__group__syslib.html @@ -144,6 +144,8 @@

            VersionChangesReason for Change +2.50.1 Used the core library defines for the message codes forming. Improve PDL code base. + 2.50 Moved following macros to the core library: CY_LO8,CY_HI8,CY_LO16,CY_HI16,CY_SWAP_ENDIAN16,CY_SWAP_ENDIAN32, CY_SWAP_ENDIAN64,CY_GET_REG8,CY_SET_REG8,CY_GET_REG16,CY_SET_REG16, CY_GET_REG24,CY_SET_REG24,CY_GET_REG32,CY_SET_REG32,_CLR_SET_FLD32U, CY_REG32_CLR_SET,_CLR_SET_FLD16U,CY_REG16_CLR_SET,_CLR_SET_FLD8U, CY_REG8_CLR_SET,_BOOL2FLD,_FLD2BOOL,CY_SYSLIB_DIV_ROUND, CY_SYSLIB_DIV_ROUNDUP,CY_NOINIT,CY_SECTION,CY_UNUSED,CY_NOINLINE, CY_ALIGN,CY_RAMFUNC_BEGIN,CY_RAMFUNC_END. Use at least version 1.1 of the core library: https://github.com/cypresssemiconductorco/core-lib. Improve PDL code base. 2.40.1 Correct the CY_RAMFUNC_BEGIN macro for the IAR compiler. Removed the IAR compiler warning. diff --git a/docs/pdl_api_reference_manual/html/group__group__syslib__macros__status__codes.html b/docs/pdl_api_reference_manual/html/group__group__syslib__macros__status__codes.html index 69d4f31..62df643 100644 --- a/docs/pdl_api_reference_manual/html/group__group__syslib__macros__status__codes.html +++ b/docs/pdl_api_reference_manual/html/group__group__syslib__macros__status__codes.html @@ -92,31 +92,31 @@

            Macros

            -#define CY_PDL_STATUS_CODE_Pos   (0U) +#define CY_PDL_STATUS_CODE_Pos   (CY_RSLT_CODE_POSITION)  The module status code position in the status code.
              -#define CY_PDL_STATUS_TYPE_Pos   (16U) +#define CY_PDL_STATUS_TYPE_Pos   (CY_RSLT_TYPE_POSITION)  The status type position in the status code.
              -#define CY_PDL_MODULE_ID_Pos   (18U) +#define CY_PDL_MODULE_ID_Pos   (CY_RSLT_MODULE_POSITION)  The software module ID position in the status code.
              -#define CY_PDL_STATUS_INFO   (0UL << CY_PDL_STATUS_TYPE_Pos) +#define CY_PDL_STATUS_INFO   ((uint32_t)CY_RSLT_TYPE_INFO << CY_PDL_STATUS_TYPE_Pos)  The information status type.
              -#define CY_PDL_STATUS_WARNING   (1UL << CY_PDL_STATUS_TYPE_Pos) +#define CY_PDL_STATUS_WARNING   ((uint32_t)CY_RSLT_TYPE_WARNING << CY_PDL_STATUS_TYPE_Pos)  The warning status type.
              -#define CY_PDL_STATUS_ERROR   (2UL << CY_PDL_STATUS_TYPE_Pos) +#define CY_PDL_STATUS_ERROR   ((uint32_t)CY_RSLT_TYPE_ERROR << CY_PDL_STATUS_TYPE_Pos)  The error status type.
              -#define CY_PDL_MODULE_ID_Msk   (0x3FFFU) +#define CY_PDL_MODULE_ID_Msk   (CY_RSLT_MODULE_MASK)  The software module ID mask.
              diff --git a/docs/pdl_api_reference_manual/html/group__group__syspm.html b/docs/pdl_api_reference_manual/html/group__group__syspm.html index 1518852..7c1add9 100644 --- a/docs/pdl_api_reference_manual/html/group__group__syspm.html +++ b/docs/pdl_api_reference_manual/html/group__group__syspm.html @@ -383,6 +383,8 @@

            VersionChangesReason for Change +5.0 Updated the internal IsVoltageChangePossible() function (Cy_SysPm_LdoSetVoltage(), Cy_SysPm_BuckEnable(), Cy_SysPm_BuckSetVoltage1(), Cy_SysPm_SystemEnterUlp() and Cy_SysPm_SystemEnterLp() functions are affected). For all the devices except CY8C6xx6 and CY8C6xx7 added the check if modifying the RAM trim register is allowed. Protecting the system from a possible CPU hard-fault cause. If you are using PC > 0 in your project and you want to switch the power modes (LP<->ULP), you need to unprotect the CPUSS_TRIM_RAM_CTL and CPUSS_TRIM_ROM_CTL registers and can use a programmable PPU for that. + 4.50 Updated the Cy_SysPm_CpuEnterDeepSleep() function. Updated the mechanism for saving/restoring not retained UDB and clock registers in the Cy_SysPm_CpuEnterDeepSleep() function. Updated the Cy_SysPm_CpuEnterDeepSleep() function to use values stored into the variable instead of reading them directly from SFLASH memory. SFLASH memory can be unavailable to read the correct value after a Deep sleep state on the CY8C6xx6 and CY8C6xx7 devices. diff --git a/docs/pdl_api_reference_manual/html/group__group__syspm__functions__buck.html b/docs/pdl_api_reference_manual/html/group__group__syspm__functions__buck.html index 3619c1c..6d7a22b 100644 --- a/docs/pdl_api_reference_manual/html/group__group__syspm__functions__buck.html +++ b/docs/pdl_api_reference_manual/html/group__group__syspm__functions__buck.html @@ -167,7 +167,7 @@

            Returns
            diff --git a/docs/pdl_api_reference_manual/html/group__group__syspm__functions__power.html b/docs/pdl_api_reference_manual/html/group__group__syspm__functions__power.html index a2be424..4c98998 100644 --- a/docs/pdl_api_reference_manual/html/group__group__syspm__functions__power.html +++ b/docs/pdl_api_reference_manual/html/group__group__syspm__functions__power.html @@ -243,7 +243,7 @@

            Returns
              -
            • CY_SYSPM_SUCCESS - Entered the system LP mode.
              • +
            • CY_SYSPM_SUCCESS - Entered the system LP mode or the device is already in LP mode.
            • CY_SYSPM_INVALID_STATE - The system LP mode was not set. The system LP mode was not set because the protection context value is higher than zero (PC > 0) or the device revision does not support modifying registers (to enter LP mode) via syscall.
            • CY_SYSPM_CANCELED - Operation was canceled. Call the function again until the function returns CY_SYSPM_SUCCESS.
            • CY_SYSPM_FAIL - The system LP mode is not entered.
              • @@ -280,7 +280,7 @@

              Returns
                -
              • CY_SYSPM_SUCCESS - Entered system ULP mode.
                • +
              • CY_SYSPM_SUCCESS - Entered the system ULP mode or the device is already in ULP mode.
              • CY_SYSPM_INVALID_STATE - System ULP mode was not set. The ULP mode was not set because the protection context value is higher than zero (PC > 0) or the device revision does not support modifying registers (to enter system ULP mode) via syscall.
              • CY_SYSPM_CANCELED - Operation was canceled. Call the function again until the function returns CY_SYSPM_SUCCESS.
              • CY_SYSPM_FAIL - The system ULP mode is not entered.
                • diff --git a/docs/pdl_api_reference_manual/html/group__group__syspm__macros.html b/docs/pdl_api_reference_manual/html/group__group__syspm__macros.html index 6714c0a..ea0def7 100644 --- a/docs/pdl_api_reference_manual/html/group__group__syspm__macros.html +++ b/docs/pdl_api_reference_manual/html/group__group__syspm__macros.html @@ -101,11 +101,11 @@

                Macros

                -#define CY_SYSPM_DRV_VERSION_MAJOR   4 +#define CY_SYSPM_DRV_VERSION_MAJOR   5  Driver major version.
                  -#define CY_SYSPM_DRV_VERSION_MINOR   50 +#define CY_SYSPM_DRV_VERSION_MINOR   0  Driver minor version.
                  diff --git a/docs/pdl_api_reference_manual/html/group__group__system__config.html b/docs/pdl_api_reference_manual/html/group__group__system__config.html index af0fd4f..e4cc90f 100644 --- a/docs/pdl_api_reference_manual/html/group__group__system__config.html +++ b/docs/pdl_api_reference_manual/html/group__group__system__config.html @@ -96,7 +96,6 @@
              • Device Memory Definition
              • Heap and Stack Configuration
                • -
              • Merging CM0+ and CM4 Executables
              • Default Interrupt Handlers Definition
              • Vectors Table Copy from Flash to RAM
              • Cortex-M4 Control
                • @@ -106,44 +105,46 @@

                Device Memory Definition

                The flash and RAM allocation for each CPU is defined by the linker scripts. For dual-core devices, the physical flash and RAM memory is shared between the CPU cores. 2 KB of RAM (allocated at the end of RAM) are reserved for system use. For Single-Core devices the system reserves additional 80 bytes of RAM. Using the reserved memory area for other purposes will lead to unexpected behavior.

                -
                Note
                The linker files provided with the PDL are generic and handle all common use cases. Your project may not use every section defined in the linker files. In that case you may see warnings during the build process. To eliminate build warnings in your project, you can simply comment out or remove the relevant code in the linker file.
                +
                Note
                The linker files provided with the PDL are generic and handle all common use cases. Your project may not use every section defined in the linker files. In that case you may see warnings during the build process. To eliminate build warnings in your project, you can simply comment out or remove the relevant code in the linker file.
                +
                +For the PSoC 64 Secure MCUs devices, refer to the following page: https://www.cypress.com/documentation/software-and-drivers/psoc-64-secure-mcu-secure-boot-sdk-user-guide

                ARM GCC
                - The flash and RAM sections for the CPU are defined in the linker files: 'xx_yy.ld', where 'xx' is the device group, and 'yy' is the target CPU; for example, 'cy8c6xx7_cm0plus.ld' and 'cy8c6xx7_cm4_dual.ld'.

                Note
                If the start of the Cortex-M4 application image is changed, the value of the of the CY_CORTEX_M4_APPL_ADDR should also be changed. The CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the Cy_SysEnableCM4() function call.
                + The flash and RAM sections for the CPU are defined in the linker files: 'xx_yy.ld', where 'xx' is the device group, and 'yy' is the target CPU; for example, 'cy8c6xx7_cm0plus.ld' and 'cy8c6xx7_cm4_dual.ld'.

                Note
                If the start of the Cortex-M4 application image is changed, the value of the CY_CORTEX_M4_APPL_ADDR should also be changed. The CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the Cy_SysEnableCM4() function call. By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. More about CM0+ prebuilt images, see here: https://github.com/cypresssemiconductorco/psoc6cm0p

                Change the flash and RAM sizes by editing the macros value in the linker files for both CPUs:

                  -
                • 'xx_cm0plus.ld', where 'xx' is the device group:
                  flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x00080000
                  ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x00024000
                  • -
                • 'xx_cm4_dual.ld', where 'xx' is the device group:
                  flash (rx) : ORIGIN = 0x10080000, LENGTH = 0x00080000
                  ram (rwx) : ORIGIN = 0x08024000, LENGTH = 0x00023800
                  • +
                • 'xx_cm0plus.ld', where 'xx' is the device group:
                  flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x2000
                  ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x2000
                  • +
                • 'xx_cm4_dual.ld', where 'xx' is the device group:
                  flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x100000
                  ram (rwx) : ORIGIN = 0x08002000, LENGTH = 0x45800
                -

                Change the value of the CY_CORTEX_M4_APPL_ADDR macro to the rom ORIGIN's value in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. Do this by either:

                  +

                  Change the value of the CY_CORTEX_M4_APPL_ADDR macro to the ROM ORIGIN's value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image of the Cortex-M0+ application should be the same value as the flash LENGTH in 'xx_cm0plus.ld') in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. Do this by either:

                  -

                  ARM MDK
                  - The flash and RAM sections for the CPU are defined in the linker files: 'xx_yy.scat', where 'xx' is the device group, and 'yy' is the target CPU; for example, 'cy8c6xx7_cm0plus.scat' and 'cy8c6xx7_cm4_dual.scat'.

                  Note
                  If the start of the Cortex-M4 application image is changed, the value of the of the CY_CORTEX_M4_APPL_ADDR should also be changed. The CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the Cy_SysEnableCM4() function call.
                  +

                  ARM Compiler
                  + The flash and RAM sections for the CPU are defined in the linker files: 'xx_yy.sct', where 'xx' is the device group, and 'yy' is the target CPU; for example 'cy8c6xx7_cm0plus.sct' and 'cy8c6xx7_cm4_dual.sct'.

                  Note
                  If the start of the Cortex-M4 application image is changed, the value of the of the CY_CORTEX_M4_APPL_ADDR should also be changed. The CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the Cy_SysEnableCM4() function call. By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. More about CM0+ prebuilt images, see here: https://github.com/cypresssemiconductorco/psoc6cm0p
                  The linker files provided with the PDL are generic and handle all common use cases. Your project may not use every section defined in the linker files. In that case you may see the warnings during the build process: L6314W (no section matches pattern) and/or L6329W (pattern only matches removed unused sections). In your project, you can suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to the linker. You can also comment out or remove the relevant code in the linker file.

                  Change the flash and RAM sizes by editing the macros value in the linker files for both CPUs:

                    -
                  • 'xx_cm0plus.scat', where 'xx' is the device group:
                    #define FLASH_START 0x10000000
                    #define FLASH_SIZE 0x00080000
                    #define RAM_START 0x08000000
                    #define RAM_SIZE 0x00024000
                    • -
                  • 'xx_cm4_dual.scat', where 'xx' is the device group:
                    #define FLASH_START 0x10080000
                    #define FLASH_SIZE 0x00080000
                    #define RAM_START 0x08024000
                    #define RAM_SIZE 0x00023800
                    • +
                  • 'xx_cm0plus.sct', where 'xx' is the device group:
                    #define FLASH_START 0x10000000
                    #define FLASH_SIZE 0x00002000
                    #define RAM_START 0x08000000
                    #define RAM_SIZE 0x00002000
                    • +
                  • 'xx_cm4_dual.sct', where 'xx' is the device group:
                    #define FLASH_START 0x10000000
                    #define FLASH_SIZE 0x00100000
                    #define RAM_START 0x08002000
                    #define RAM_SIZE 0x00045800
                  -

                  Change the value of the CY_CORTEX_M4_APPL_ADDR macro to the FLASH_START value in the 'xx_cm4_dual.scat' file, where 'xx' is the device group. Do this by either:

                    +

                    Change the value of the CY_CORTEX_M4_APPL_ADDR macro to the FLASH_START value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image of the Cortex-M0+ application should be the same value as the FLASH_SIZE in the 'xx_cm0plus.sct') in the 'xx_cm4_dual.sct' file, where 'xx' is the device group. Do this by either:

                    • Passing the following commands to the compiler:
                      -
                      -D CY_CORTEX_M4_APPL_ADDR=0x10080000
                      • -
                    • Editing the CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where 'xx' is device family:
                      -
                      #define CY_CORTEX_M4_APPL_ADDR (0x10080000u)
                      • +
                      -D CY_CORTEX_M4_APPL_ADDR=0x10002000
                      or +
                    • Editing the CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where 'xx' is the device family:
                      +
                      #define CY_CORTEX_M4_APPL_ADDR (0x10002000u)

                    IAR
                    - The flash and RAM sections for the CPU are defined in the linker files: 'xx_yy.icf', where 'xx' is the device group, and 'yy' is the target CPU; for example, 'cy8c6xx7_cm0plus.icf' and 'cy8c6xx7_cm4_dual.icf'.

                    Note
                    If the start of the Cortex-M4 application image is changed, the value of the of the CY_CORTEX_M4_APPL_ADDR should also be changed. The CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the Cy_SysEnableCM4() function call.
                    + The flash and RAM sections for the CPU are defined in the linker files: 'xx_yy.icf', where 'xx' is the device group, and 'yy' is the target CPU; for example, 'cy8c6xx7_cm0plus.icf' and 'cy8c6xx7_cm4_dual.icf'.

                    Note
                    If the start of the Cortex-M4 application image is changed, the value of the of the CY_CORTEX_M4_APPL_ADDR should also be changed. The CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the Cy_SysEnableCM4() function call. By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. More about CM0+ prebuilt images, see here: https://github.com/cypresssemiconductorco/psoc6cm0p

                    Change the flash and RAM sizes by editing the macros value in the linker files for both CPUs:

                      -
                    • 'xx_cm0plus.icf', where 'xx' is the device group:
                      define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000;
                      define symbol __ICFEDIT_region_IROM1_end__ = 0x10080000;
                      define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000;
                      define symbol __ICFEDIT_region_IRAM1_end__ = 0x08024000;
                      • -
                    • 'xx_cm4_dual.icf', where 'xx' is the device group:
                      define symbol __ICFEDIT_region_IROM1_start__ = 0x10080000;
                      define symbol __ICFEDIT_region_IROM1_end__ = 0x10100000;
                      define symbol __ICFEDIT_region_IRAM1_start__ = 0x08024000;
                      define symbol __ICFEDIT_region_IRAM1_end__ = 0x08047800;
                      • +
                    • 'xx_cm0plus.icf', where 'xx' is the device group:
                      define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000;
                      define symbol __ICFEDIT_region_IROM1_end__ = 0x10001FFF;
                      define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000;
                      define symbol __ICFEDIT_region_IRAM1_end__ = 0x08001FFF;
                      • +
                    • 'xx_cm4_dual.icf', where 'xx' is the device group:
                      define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000;
                      define symbol __ICFEDIT_region_IROM1_end__ = 0x100FFFFF;
                      define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000;
                      define symbol __ICFEDIT_region_IRAM1_end__ = 0x080477FF;
                    -

                    Change the value of the CY_CORTEX_M4_APPL_ADDR macro to the ICFEDIT_region_IROM1_start value in the 'xx_cm4_dual.icf' file, where 'xx' is the device group. Do this by either:

                      +

                      Change the value of the CY_CORTEX_M4_APPL_ADDR macro to the ICFEDIT_region_IROM1_start value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image of the Cortex-M0+ application) in the 'xx_cm4_dual.icf' file, where 'xx' is the device group. The sum result should be the same as (ICFEDIT_region_IROM1_end + 1) value in the 'xx_cm0plus.icf'. Do this by either:

                      • Passing the following commands to the compiler:
                        -
                        -D CY_CORTEX_M4_APPL_ADDR=0x10080000
                        • -
                      • Editing the CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where 'xx' is device family:
                        -
                        #define CY_CORTEX_M4_APPL_ADDR (0x10080000u)
                        • +
                        -D CY_CORTEX_M4_APPL_ADDR=0x10002000
                        or +
                      • Editing the CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where 'xx' is the device family:
                        +
                        #define CY_CORTEX_M4_APPL_ADDR (0x10002000u)

                      Device Initialization

                      @@ -160,42 +161,32 @@

                    • Editing source code files
                    • Specifying via command line
                      • -

                      By default, the stack size is set to 0x00001000 and the heap size is set to 0x00000400.

                      +

                      By default, the stack size is set to 0x00001000 and the heap size is allocated dynamically to the whole available free memory up to stack memory and it is set to the 0x00000400 (for ARM GCC and IAR compilers) as minimal value.

                      ARM GCC

                      • Editing source code files
                        The heap and stack sizes are defined in the assembler startup files (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S). Change the heap and stack sizes by modifying the following lines:
                        -
                        .equ Stack_Size, 0x00001000
                        .equ Heap_Size, 0x00000400
                        • -
                      • Specifying via command line
                        - Change the heap and stack sizes passing the following commands to the compiler:
                        -
                        -D __STACK_SIZE=0x000000400
                        -D __HEAP_SIZE=0x000000100
                        • +
                        .equ Stack_Size, 0x00001000
                        .equ Heap_Size, 0x00000400
                        Also, the stack size is defined in the linker script files: 'xx_yy.ld', where 'xx' is the device family, and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.ld and cy8c6xx7_cm4_dual.ld. Change the stack size by modifying the following line:
                        +
                        STACK_SIZE = 0x1000;

                      -ARM MDK

                      +ARM Compiler

              • Editing source code files
                - The heap and stack sizes are defined in the assembler startup files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). Change the heap and stack sizes by modifying the following lines:
                -
                Stack_Size EQU 0x00001000
                Heap_Size EQU 0x00000400
                • -
              • Specifying via command line
                - Change the heap and stack sizes passing the following commands to the assembler:
                -
                "--predefine=___STACK_SIZE SETA 0x000000400"
                "--predefine=__HEAP_SIZE SETA 0x000000100"
                • + The stack size is defined in the linker script files: 'xx_yy.sct', where 'xx' is the device family, and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.sct and cy8c6xx7_cm4_dual.sct. Change the stack size by modifying the following line:
                +
                STACK_SIZE = 0x1000;

              IAR

              • Editing source code files
                - The heap and stack sizes are defined in the linker scatter files: 'xx_yy.icf', where 'xx' is the device family, and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf. Change the heap and stack sizes by modifying the following lines:
                + The heap and stack sizes are defined in the linker script files: 'xx_yy.icf', where 'xx' is the device family, and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf. Change the heap and stack sizes by modifying the following lines:
                Stack_Size EQU 0x00001000
                Heap_Size EQU 0x00000400
              • Specifying via command line
                Change the heap and stack sizes passing the following commands to the linker (including quotation marks):
                --define_symbol __STACK_SIZE=0x000000400
                --define_symbol __HEAP_SIZE=0x000000100
              -

              -Merging CM0+ and CM4 Executables

              -

              The CM0+ project and linker script build the CM0+ application image. Similarly, the CM4 linker script builds the CM4 application image. Each specifies locations, sizes, and contents of sections in memory. See Device Memory Definition for the symbols and default values.

              -

              The cymcuelftool is invoked by a post-build command. The precise project setting is IDE-specific.

              -

              The cymcuelftool combines the two executables. The tool examines the executables to ensure that memory regions either do not overlap, or contain identical bytes (shared). If there are no problems, it creates a new ELF file with the merged image, without changing any of the addresses or data.

              Default Interrupt Handlers Definition

              The default interrupt handler functions are defined as weak functions to a dummy handler in the startup file. The naming convention for the interrupt handler names is <interrupt_name>_IRQHandler. A default interrupt handler can be overwritten in user code by defining the handler function using the same name. For example:

              void scb_0_interrupt_IRQHandler(void)
              {
              ...
              }

              @@ -207,15 +198,12 @@

              Copy interrupt vectors from flash to RAM:
              From:

              LONG (__Vectors)

              To:

              LONG (__ram_vectors_start__)

              Size:

              LONG (__Vectors_End - __Vectors)

              The vector table address (and the vector table itself) are defined in the assembler startup files (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S). The code in these files copies the vector table from Flash to RAM.

              -ARM MDK

              -

              The linker script file is 'xx_yy.scat', where 'xx' is the device family, and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.scat and cy8c6xx7_cm4_dual.scat. The linker script specifies that the vector table (RESET_RAM) shall be first in the RAM section.
              +ARM Compiler

            +

            The linker script file is 'xx_yy.sct', where 'xx' is the device family, and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.sct and cy8c6xx7_cm4_dual.sct. The linker script specifies that the vector table (RESET_RAM) shall be first in the RAM section.
            RESET_RAM represents the vector table. It is defined in the assembler startup files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). The code in these files copies the vector table from Flash to RAM.

            IAR

            The linker script file is 'xx_yy.icf', where 'xx' is the device family, and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf. This file defines the .intvec_ram section and its location.

            place at start of IRAM1_region { readwrite section .intvec_ram};

            The vector table address (and the vector table itself) are defined in the assembler startup files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). The code in these files copies the vector table from Flash to RAM.

            -

            -More Information

            -

            Refer to the PDL User Guide for the more details.

            MISRA Compliance

            @@ -230,6 +218,8 @@

            + + diff --git a/docs/pdl_api_reference_manual/html/index.html b/docs/pdl_api_reference_manual/html/index.html index 4125f07..242e146 100644 --- a/docs/pdl_api_reference_manual/html/index.html +++ b/docs/pdl_api_reference_manual/html/index.html @@ -97,7 +97,7 @@

            The PDL conforms to the ANSI C99 standard.

            Copyright

            -

            Copyright 2016-2019 Cypress Semiconductor Corporation

            +

            Copyright 2016-2020 Cypress Semiconductor Corporation

            Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at

            http://www.apache.org/licenses/LICENSE-2.0

            Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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            Getting Started
            -

            Include cy_pdl.h in your source code to use the library.

            +

            PDL depends on the Cypress Core Library. Download it from https://github.com/cypresssemiconductorco/core-lib and add cy_utils.h to the include search path.

            +

            Include cy_pdl.h in your source code to use the library.

            To successfully develop software for the PSoC 6 family of devices, you must configure the peripherals to implement desired behavior. In addition, you must configure clocks, GPIO, and interrupts, as well as route signals from one peripheral to another.

            This introduction covers some high level concepts that help you understand and use the PDL to accomplish these tasks. The topics are:

            • PDL Overview
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b/docs/pdl_api_reference_manual/html/search/variables_8.js @@ -10,5 +10,7 @@ var searchData= ['hscmp',['hscmp',['../structcy__stc__csd__config__t.html#a6cda2035795ec00e3583d34dfc516411',1,'cy_stc_csd_config_t']]], ['hsiom',['hsiom',['../structcy__stc__gpio__pin__config__t.html#af8a4f6b10a8e655125dfafd511c7af6e',1,'cy_stc_gpio_pin_config_t']]], ['hwenabled',['hwEnabled',['../structcy__stc__sar__state__backup__t.html#a6ffea353bffaff5b3aff73a92c22d3d4',1,'cy_stc_sar_state_backup_t']]], + ['hybridregioncount',['hybridRegionCount',['../structcy__stc__smif__mem__device__cfg__t.html#af699412addf5631fb6e2d61ece8a89f0',1,'cy_stc_smif_mem_device_cfg_t']]], + ['hybridregioninfo',['hybridRegionInfo',['../structcy__stc__smif__mem__device__cfg__t.html#a989bd3b0d57035f44bd936d185afb7bf',1,'cy_stc_smif_mem_device_cfg_t']]], ['hysteresis',['hysteresis',['../structcy__stc__lpcomp__config__t.html#ad43e4f40af6d78d02b8c0a277cb10f96',1,'cy_stc_lpcomp_config_t']]] ]; diff --git a/docs/pdl_api_reference_manual/html/structcy__stc__smif__hybrid__region__info__t.html b/docs/pdl_api_reference_manual/html/structcy__stc__smif__hybrid__region__info__t.html new file mode 100644 index 0000000..cbef145 --- /dev/null +++ b/docs/pdl_api_reference_manual/html/structcy__stc__smif__hybrid__region__info__t.html @@ -0,0 +1,128 @@ + + + + + + + + +PSoC 6 Peripheral Driver Library: cy_stc_smif_hybrid_region_info_t Struct Reference + + + + + + + + + + + + + + +
              +
              +
            Version Changes Reason for Change
            2.70.1 Updated documentation for the better description of the existing startup implementation. User experience enhancement.
            2.70 Updated SystemCoreClockUpdate() implementation - The SysClk API is reused. Code optimization.
            Updated SystemInit() implementation - The IPC7 structure is initialized for both cores. Provided support for SysPM driver updates.
             ►SysInt (System Interrupt)The SysInt driver provides an API to configure the device peripheral interrupts
            + + + + + + +
            +
            PSoC 6 Peripheral Driver Library
            +
            + + + + + + + + + +
            + +
            +
            +
            + +
            + +
            +
            + + +
            + +
            + +
            +
            +Data Fields
            +
            +
            cy_stc_smif_hybrid_region_info_t Struct Reference
            SMIF (Serial Memory Interface) » Data Structures » SMIF Memory Description Structures
            +
            +
            +

            Description

            +

            This structure specifies data used for memory with hybrid sectors.

            +
            + + + + + + + + + + + + + + + + +

            +Data Fields

            +uint32_t regionAddress
             This specifies the address where a region starts.
             
            +uint32_t sectorsCount
             This specifies the number of sectors in the region.
             
            +uint32_t eraseCmd
             This specifies the region specific erase instruction.
             
            +uint32_t eraseSize
             This specifies the size of one sector.
             
            +uint32_t eraseTime
             Max time for sector erase type 1 cycle time in ms.
             
            +
            +
            + + + diff --git a/docs/pdl_api_reference_manual/html/structcy__stc__smif__mem__device__cfg__t.html b/docs/pdl_api_reference_manual/html/structcy__stc__smif__mem__device__cfg__t.html index 2b1886e..f3898e6 100644 --- a/docs/pdl_api_reference_manual/html/structcy__stc__smif__mem__device__cfg__t.html +++ b/docs/pdl_api_reference_manual/html/structcy__stc__smif__mem__device__cfg__t.html @@ -167,6 +167,14 @@ uint32_t programTime  Max time for page program cycle time in us.
              + +uint32_t hybridRegionCount + This specifies the number of regions for memory with hybrid sectors.
            +  + +cy_stc_smif_hybrid_region_info_t ** hybridRegionInfo + This specifies data for memory with hybrid sectors.
            + 

            Field Documentation

            diff --git a/drivers/include/cy_ble_clk.h b/drivers/include/cy_ble_clk.h index b75868e..c23e631 100644 --- a/drivers/include/cy_ble_clk.h +++ b/drivers/include/cy_ble_clk.h @@ -1,12 +1,12 @@ /***************************************************************************//** * \file cy_ble_clk.h -* \version 3.30 +* \version 3.40 * * The header file of the BLE ECO clock driver. * ******************************************************************************** * \copyright -* Copyright 2017-2019 Cypress Semiconductor Corporation +* Copyright 2017-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -70,6 +70,11 @@ * * * +* +* +* +* +* * * * @@ -127,7 +132,7 @@ extern "C" { #define CY_BLE_CLK_DRV_VERSION_MAJOR (3) /** Driver minor version */ -#define CY_BLE_CLK_DRV_VERSION_MINOR (20) +#define CY_BLE_CLK_DRV_VERSION_MINOR (40) /** Driver ID */ #define CY_BLE_CLK_ID (0x05UL << 18U) @@ -272,10 +277,28 @@ typedef struct * \{ */ cy_en_ble_eco_status_t Cy_BLE_EcoConfigure(cy_en_ble_eco_freq_t freq, - cy_en_ble_eco_sys_clk_div_t sysClkDiv, - uint32_t cLoad, uint32_t xtalStartUpTime, - cy_en_ble_eco_voltage_reg_t voltageReg); + cy_en_ble_eco_sys_clk_div_t sysClkDiv, + uint32_t cLoad, + uint32_t xtalStartUpTime, + cy_en_ble_eco_voltage_reg_t voltageReg); void Cy_BLE_EcoReset(void); +__STATIC_INLINE bool Cy_BLE_EcoIsEnabled(void); + + +/******************************************************************************* +* Function Name: Cy_BLE_EcoIsEnabled +****************************************************************************//** +* +* Reports the Enabled/Disabled BLE ECO status. +* +* \return Boolean status of BLE ECO: true - Enabled, false - Disabled. +* +*******************************************************************************/ +__STATIC_INLINE bool Cy_BLE_EcoIsEnabled(void) +{ + return (((BLE_BLESS_MT_CFG & BLE_BLESS_MT_CFG_ENABLE_BLERD_Msk) != 0u) && + ((BLE_BLESS_MT_STATUS & BLE_BLESS_MT_STATUS_BLESS_STATE_Msk) != 0u)); +} /** \} */ /** \cond INTERNAL */ diff --git a/drivers/include/cy_canfd.h b/drivers/include/cy_canfd.h index 09dd411..d551291 100644 --- a/drivers/include/cy_canfd.h +++ b/drivers/include/cy_canfd.h @@ -1,13 +1,13 @@ /***************************************************************************//** * \file cy_canfd.h -* \version 1.0.1 +* \version 1.10 * * This file provides constants and parameter values for * the CAN FD driver. * ******************************************************************************** * \copyright -* Copyright 2019 Cypress Semiconductor Corporation +* Copyright 2019-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -217,6 +217,11 @@ *
            VersionChangesReason of Change
            3.40A new API function \ref Cy_BLE_EcoIsEnabled() is added.API enhancement.
            3.30Updated the \ref Cy_BLE_EcoConfigure() to reuse the \ref Cy_SysClk_ClkPeriGetFrequency().API enhancement.
            * * +* +* +* +* +* * * * @@ -266,7 +271,7 @@ extern "C" { #define CY_CANFD_DRV_VERSION_MAJOR 1U /** Driver minor version */ -#define CY_CANFD_DRV_VERSION_MINOR 0U +#define CY_CANFD_DRV_VERSION_MINOR 10U /** CAN FD driver ID */ #define CY_CANFD_ID CY_PDL_DRV_ID (0x45U) diff --git a/drivers/include/cy_device.h b/drivers/include/cy_device.h index 1f2060b..d438e51 100644 --- a/drivers/include/cy_device.h +++ b/drivers/include/cy_device.h @@ -7,7 +7,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -200,6 +200,7 @@ typedef struct extern const cy_stc_device_t cy_deviceIpBlockCfgPSoC6_01; extern const cy_stc_device_t cy_deviceIpBlockCfgPSoC6_02; extern const cy_stc_device_t cy_deviceIpBlockCfgPSoC6_03; +extern const cy_stc_device_t cy_deviceIpBlockCfgPSoC6_04; extern const cy_stc_device_t * cy_device; @@ -1084,26 +1085,26 @@ void Cy_PDL_Init(const cy_stc_device_t * device); * BLE *******************************************************************************/ -#define BLE_RCB_INTR (((BLE_V1_Type *) BLE)->RCB.INTR) -#define BLE_RCB_TX_FIFO_WR (((BLE_V1_Type *) BLE)->RCB.TX_FIFO_WR) -#define BLE_RCB_RX_FIFO_RD (((BLE_V1_Type *) BLE)->RCB.RX_FIFO_RD) -#define BLE_RCB_CTRL (((BLE_V1_Type *) BLE)->RCB.CTRL) -#define BLE_RCB_RCBLL_CTRL (((BLE_V1_Type *) BLE)->RCB.RCBLL.CTRL) -#define BLE_BLESS_XTAL_CLK_DIV_CONFIG (((BLE_V1_Type *) BLE)->BLESS.XTAL_CLK_DIV_CONFIG) -#define BLE_BLESS_MT_CFG (((BLE_V1_Type *) BLE)->BLESS.MT_CFG) -#define BLE_BLESS_MT_STATUS (((BLE_V1_Type *) BLE)->BLESS.MT_STATUS) -#define BLE_BLESS_MT_DELAY_CFG (((BLE_V1_Type *) BLE)->BLESS.MT_DELAY_CFG) -#define BLE_BLESS_MT_DELAY_CFG2 (((BLE_V1_Type *) BLE)->BLESS.MT_DELAY_CFG2) -#define BLE_BLESS_MT_DELAY_CFG3 (((BLE_V1_Type *) BLE)->BLESS.MT_DELAY_CFG3) -#define BLE_BLESS_MT_VIO_CTRL (((BLE_V1_Type *) BLE)->BLESS.MT_VIO_CTRL) -#define BLE_BLESS_LL_CLK_EN (((BLE_V1_Type *) BLE)->BLESS.LL_CLK_EN) -#define BLE_BLESS_MISC_EN_CTRL (((BLE_V1_Type *) BLE)->BLESS.MISC_EN_CTRL) -#define BLE_BLESS_INTR_STAT (((BLE_V1_Type *) BLE)->BLESS.INTR_STAT) -#define BLE_BLELL_EVENT_INTR (((BLE_V1_Type *) BLE)->BLELL.EVENT_INTR) -#define BLE_BLELL_CONN_INTR (((BLE_V1_Type *) BLE)->BLELL.CONN_INTR) -#define BLE_BLELL_CONN_EXT_INTR (((BLE_V1_Type *) BLE)->BLELL.CONN_EXT_INTR) -#define BLE_BLELL_SCAN_INTR (((BLE_V1_Type *) BLE)->BLELL.SCAN_INTR) -#define BLE_BLELL_ADV_INTR (((BLE_V1_Type *) BLE)->BLELL.ADV_INTR) +#define BLE_RCB_INTR (((BLE_V1_Type *) BLE_BASE)->RCB.INTR) +#define BLE_RCB_TX_FIFO_WR (((BLE_V1_Type *) BLE_BASE)->RCB.TX_FIFO_WR) +#define BLE_RCB_RX_FIFO_RD (((BLE_V1_Type *) BLE_BASE)->RCB.RX_FIFO_RD) +#define BLE_RCB_CTRL (((BLE_V1_Type *) BLE_BASE)->RCB.CTRL) +#define BLE_RCB_RCBLL_CTRL (((BLE_V1_Type *) BLE_BASE)->RCB.RCBLL.CTRL) +#define BLE_BLESS_XTAL_CLK_DIV_CONFIG (((BLE_V1_Type *) BLE_BASE)->BLESS.XTAL_CLK_DIV_CONFIG) +#define BLE_BLESS_MT_CFG (((BLE_V1_Type *) BLE_BASE)->BLESS.MT_CFG) +#define BLE_BLESS_MT_STATUS (((BLE_V1_Type *) BLE_BASE)->BLESS.MT_STATUS) +#define BLE_BLESS_MT_DELAY_CFG (((BLE_V1_Type *) BLE_BASE)->BLESS.MT_DELAY_CFG) +#define BLE_BLESS_MT_DELAY_CFG2 (((BLE_V1_Type *) BLE_BASE)->BLESS.MT_DELAY_CFG2) +#define BLE_BLESS_MT_DELAY_CFG3 (((BLE_V1_Type *) BLE_BASE)->BLESS.MT_DELAY_CFG3) +#define BLE_BLESS_MT_VIO_CTRL (((BLE_V1_Type *) BLE_BASE)->BLESS.MT_VIO_CTRL) +#define BLE_BLESS_LL_CLK_EN (((BLE_V1_Type *) BLE_BASE)->BLESS.LL_CLK_EN) +#define BLE_BLESS_MISC_EN_CTRL (((BLE_V1_Type *) BLE_BASE)->BLESS.MISC_EN_CTRL) +#define BLE_BLESS_INTR_STAT (((BLE_V1_Type *) BLE_BASE)->BLESS.INTR_STAT) +#define BLE_BLELL_EVENT_INTR (((BLE_V1_Type *) BLE_BASE)->BLELL.EVENT_INTR) +#define BLE_BLELL_CONN_INTR (((BLE_V1_Type *) BLE_BASE)->BLELL.CONN_INTR) +#define BLE_BLELL_CONN_EXT_INTR (((BLE_V1_Type *) BLE_BASE)->BLELL.CONN_EXT_INTR) +#define BLE_BLELL_SCAN_INTR (((BLE_V1_Type *) BLE_BASE)->BLELL.SCAN_INTR) +#define BLE_BLELL_ADV_INTR (((BLE_V1_Type *) BLE_BASE)->BLELL.ADV_INTR) /******************************************************************************* diff --git a/drivers/include/cy_efuse.h b/drivers/include/cy_efuse.h index cb14d9c..caa6a62 100644 --- a/drivers/include/cy_efuse.h +++ b/drivers/include/cy_efuse.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_efuse.h -* \version 1.10.1 +* \version 1.10.2 * * Provides the API declarations of the eFuse driver. * @@ -85,6 +85,11 @@ *
            VersionChangesReason for Change
            1.10Updated of the \ref Cy_CANFD_Init() functionsAllow initing CANFD with 0 number of SID/XID filters
            1.0.1Updated description of the \ref Cy_CANFD_Init() and \ref Cy_CANFD_DeInit() functionsDocumentation update and clarification
            * * +* +* +* +* +* * * * diff --git a/drivers/include/cy_flash.h b/drivers/include/cy_flash.h index f39679c..582734b 100644 --- a/drivers/include/cy_flash.h +++ b/drivers/include/cy_flash.h @@ -1,12 +1,12 @@ /***************************************************************************//** * \file cy_flash.h -* \version 3.30.3 +* \version 3.30.4 * * Provides the API declarations of the Flash driver. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -42,8 +42,8 @@ * or modify the SROM code. The driver API requests the system call by acquiring * the Inter-processor communication (IPC) and writing the SROM function opcode * and parameters to its input registers. As a result, an NMI interrupt is invoked -* and the requested SROM API is executed. The operation status is returned to the -* driver context and a release interrupt is triggered. +* and the requested SROM function is executed. The operation status is returned +* to the driver context and a release interrupt is triggered. * * Writing to flash can take up to 20 milliseconds. During this time, * the device should not be reset (including XRES pin, software reset, and @@ -55,7 +55,7 @@ * in the same or neighboring (neighboring restriction is applicable just for the * CY8C6xx6, CY8C6xx7 devices) flash sector where the flash Write, Erase, or * Program operation is working. This violation may cause a HardFault exception. -* To avoid the Read while Write violation, the user must carefully split the +* To avoid the Read while Write violation, carefully split the * Read and Write operation on flash sectors which are not neighboring, * considering both cores in the multi-processor device. If the flash is divided * into four equal sectors, you may edit the linker script to place the code @@ -66,18 +66,18 @@ * * \subsection group_flash_config_intro Introduction: * The PSoC 6 MCU user-programmable Flash consists of: -* - User Flash sectors (from 4 to 8) - 256KB each. -* - EEPROM emulation sector - 32KB. +* - Application flash memory (from 2 to 8 sectors) - 128KB/256KB each. +* - EE emulation flash memory - 32KB. * -* Write operations are performed on a per-sector basis and may be done as -* Blocking or Partially Blocking, defined as follows: +* Write operation may be done as Blocking or Partially Blocking, +* defined as follows: * * \subsection group_flash_config_blocking Blocking: * In this case, the entire Flash block is not available for the duration of the * Write (∼16ms). Therefore, no Flash accesses (from any Bus Master) can * occur during that time. CPU execution can be performed from SRAM. All -* pre-fetching must be disabled. Application code execution from Flash is -* blocked for the Flash Write duration for both cores. +* pre-fetching must be disabled. Code execution from Flash is blocked for the +* Flash Write duration for both cores. * * \subsection group_flash_config_block_const Constraints for Blocking Flash operations: * -# During write to flash, the device should not be reset (including XRES pin, @@ -85,16 +85,16 @@ * of the flash. * -# The low-voltage detect circuits should be configured to generate an * interrupt instead of a reset. -* -# Flash write operation is allowed only in one of the following CM4 states: +* -# Flash rite operation is allowed only in one of the following CM4 states: * -# CM4 is Active and initialized:
            * call \ref Cy_SysEnableCM4 "Cy_SysEnableCM4(CY_CORTEX_M4_APPL_ADDR)". * Note: If desired user may put CM4 core in Deep Sleep any time * after calling Cy_SysEnableCM4(). -* -# CM4 is Off:
            +* -# CM4 is Off and disabled:
            * call Cy_SysDisableCM4(). Note: In this state Debug mode is not * supported. * . -* -# Flash write cannot be performed in ULP (core voltage 0.9V) mode. +* -# Flash Write cannot be performed in Ultra Low Power (core voltage 0.9V) mode. * -# Interrupts must be enabled on both active cores. Do not enter a critical * section during flash operation. * -# For the CY8C6xx6, CY8C6xx7 devices user must guarantee that system pipe @@ -115,8 +115,7 @@ * sequence used. * * For API sequence Cy_Flash_StartEraseRow() + Cy_Flash_StartProgram() there are -* four block-out regions during which the read is blocked using the software -* driver (PDL). See Figure 1. +* four block-out regions during which Read is blocked. See Figure 1. * *
            *
            VersionChangesReason for Change
            1.10.2Fix driver header path.Folder structure changed.
            1.10.1Added header guard CY_IP_MXEFUSE.To enable the PDL compilation with wounded out IP blocks.
            @@ -150,7 +149,7 @@ *
            * * -* This allows both cores to execute an application for about 80% of Flash Write +* This allows both cores to execute for about 80% of Flash Write * operation - see Figure 1. * This capability is important for communication protocols that rely on fast * response. @@ -167,9 +166,9 @@ * The core that performs read/execute is blocked identically to the previous * scenario - see Figure 1. * -* This allows the core that initiates Cy_Flash_StartWrite() to execute an -* application for about 20% of the Flash Write operation. The other core executes -* the application for about 80% of the Flash Write operation. +* This allows the core that initiates Cy_Flash_StartWrite() to execute for about +* 20% of Flash Write operation. The other core executes for about 80% of Flash +* Write operation. * * Some constraints must be planned for in the Partially Blocking mode which are * described in detail below. @@ -190,7 +189,7 @@ * call \ref Cy_SysEnableCM4 "Cy_SysEnableCM4(CY_CORTEX_M4_APPL_ADDR)". * Note: If desired user may put CM4 core in Deep Sleep any time * after calling Cy_SysEnableCM4(). -* -# CM4 is Off:
            +* -# CM4 is Off and disabled:
            * call Cy_SysDisableCM4(). Note: In this state Debug mode is not * supported. * . @@ -198,8 +197,8 @@ * read of any bus master: CM0+, CM4, DMA, Crypto, etc.) * -# Do not write to and read/execute from the same flash sector at the same * time. This is true for all sectors. -* -# Writing rules in User Flash (this restriction is applicable just for the -* CY8C6xx6, CY8C6xx7 devices): +* -# Writing rules in application flash (this restriction is applicable just +* for CY8C6xx6, CY8C6xx7 devices): * -# Any bus master can read/execute from UFLASH S0 and/or S1, during * flash write to UFLASH S2 or S3. * -# Any bus master can read/execute from UFLASH S2 and/or S3, during @@ -209,16 +208,13 @@ * code for CM4 in either S0 or S1. CM0+ code resides in S0. Write data * to S2 and S3 sections. * . -* -# Flash write cannot be performed in ULP mode (core voltage 0.9V). +* -# Flash Write cannot be performed in Ultra Low Power mode (core voltage 0.9V). * -# Interrupts must be enabled on both active cores. Do not enter a critical * section during flash operation. * -# For the CY8C6xx6, CY8C6xx7 devices user must guarantee that system pipe * interrupts (IPC interrupts 3 and 4) have the highest priority, or at * least that pipe interrupts are not interrupted or in a pending state * for more than 700 µs. -* -# User must guarantee that during flash write operation no flash read -* operations are performed by bus masters other than CM0+ and CM4 -* (DMA and Crypto). * -# If you do not use the default startup, perform the following steps * before any flash write/erase operations: * \snippet flash/snippet/main.c Flash Initialization @@ -260,6 +256,11 @@ * * * +* +* +* +* +* * * * diff --git a/drivers/include/cy_prot.h b/drivers/include/cy_prot.h index c51985c..b4ba383 100644 --- a/drivers/include/cy_prot.h +++ b/drivers/include/cy_prot.h @@ -1,13 +1,13 @@ /***************************************************************************//** * \file cy_prot.h -* \version 1.30.1 +* \version 1.30.2 * * \brief * Provides an API declaration of the Protection Unit driver * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -390,6 +390,12 @@ *
            VersionChangesReason for Change
            3.30.4Improved documentation.User experience enhancement.
            3.30.3Updated documentation to limit devices with the restrictions. Improved calculation of the CY_FLASH_DELAY_CORRECTIVE macro.User experience enhancement.
            * * +* +* +* +* +* * * * diff --git a/drivers/include/cy_rtc.h b/drivers/include/cy_rtc.h index 36cac15..f8b90ae 100644 --- a/drivers/include/cy_rtc.h +++ b/drivers/include/cy_rtc.h @@ -1,13 +1,13 @@ /***************************************************************************//** * \file cy_rtc.h -* \version 2.20.1 +* \version 2.30 * * This file provides constants and parameter values for the APIs for the * Real-Time Clock (RTC). * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -228,6 +228,18 @@ *
            VersionChangesReason for Change
            1.30.2Clarified the description of the next API functions: \ref Cy_Prot_ConfigPpuProgMasterAtt,\n +* \ref Cy_Prot_ConfigPpuProgSlaveAtt, \ref Cy_Prot_ConfigPpuFixedMasterAtt, \ref Cy_Prot_ConfigPpuFixedSlaveAtt.API enhancement based on usability feedback.
            1.30.1Snippet updated.Old snippet outdated.
            * * +* +* +* +* +* * * * @@ -326,7 +338,7 @@ extern "C" { #define CY_RTC_DRV_VERSION_MAJOR 2 /** Driver minor version */ -#define CY_RTC_DRV_VERSION_MINOR 20 +#define CY_RTC_DRV_VERSION_MINOR 30 /** \} group_rtc_macros */ /******************************************************************************* @@ -548,8 +560,6 @@ cy_en_rtc_status_t Cy_RTC_SetAlarmDateAndTimeDirect(uint32_t sec, uint32_t min, * \{ */ cy_en_rtc_status_t Cy_RTC_EnableDstTime(cy_stc_rtc_dst_t const *dstTime, cy_stc_rtc_config_t const *timeDate); -cy_en_rtc_status_t Cy_RTC_SetNextDstTime(cy_stc_rtc_dst_format_t const *nextDst); -bool Cy_RTC_GetDstStatus(cy_stc_rtc_dst_t const *dstTime, cy_stc_rtc_config_t const *timeDate); /** \} group_rtc_dst_functions */ /** @@ -594,6 +604,9 @@ __STATIC_INLINE bool Cy_RTC_IsExternalResetOccurred(void); __STATIC_INLINE void Cy_RTC_SyncToRtcAhbDateAndTime(uint32_t timeBcd, uint32_t dateBcd); __STATIC_INLINE void Cy_RTC_SyncToRtcAhbAlarm(uint32_t alarmTimeBcd, uint32_t alarmDateBcd, cy_en_rtc_alarm_t alarmIndex); + +cy_en_rtc_status_t Cy_RTC_SetNextDstTime(cy_stc_rtc_dst_format_t const *nextDst); +bool Cy_RTC_GetDstStatus(cy_stc_rtc_dst_t const *dstTime, cy_stc_rtc_config_t const *timeDate); /** \} group_rtc_low_level_functions */ /** \} group_rtc_functions */ diff --git a/drivers/include/cy_smif.h b/drivers/include/cy_smif.h index c109bac..606d820 100644 --- a/drivers/include/cy_smif.h +++ b/drivers/include/cy_smif.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_smif.h -* \version 1.40.1 +* \version 1.50 * * Provides an API declaration of the Cypress SMIF driver. * @@ -214,6 +214,15 @@ *
            VersionChangesReason for Change
            2.30 +* * Corrected the Cy_RTC_GetDstStatus() and Cy_RTC_SetNextDstTime() +* documentation. +* * Fixed the Cy_RTC_GetDstStatus() behaviour in the 'an hour before/after the DST stop event' period. +* +* * Collateral Review: user experience enhancement. +* * Bug fix. +*
            2.20.1Modified header guard CY_IP_MXS40SRSS_RTC.To enable the PDL compilation with wounded out IP blocks.
            * * +* +* +* +* +* * * * @@ -450,7 +459,7 @@ extern "C" { #define CY_SMIF_DRV_VERSION_MAJOR 1 /** The driver minor version */ -#define CY_SMIF_DRV_VERSION_MINOR 40 +#define CY_SMIF_DRV_VERSION_MINOR 50 /** One microsecond timeout for Cy_SMIF_TimeoutRun() */ #define CY_SMIF_WAIT_1_UNIT (1U) @@ -679,6 +688,8 @@ typedef enum CY_SMIF_NO_QE_BIT = CY_SMIF_ID |CY_PDL_STATUS_ERROR | 0x03U, CY_SMIF_BAD_PARAM = CY_SMIF_ID |CY_PDL_STATUS_ERROR | 0x04U, /**< The SMIF API received the wrong parameter */ CY_SMIF_NO_SFDP_SUPPORT = CY_SMIF_ID |CY_PDL_STATUS_ERROR | 0x05U, /**< The external memory does not support SFDP (JESD216B). */ + CY_SMIF_NOT_HYBRID_MEM = CY_SMIF_ID |CY_PDL_STATUS_ERROR | 0x06U, /**< The external memory is not hybrid */ + CY_SMIF_SFDP_CORRUPTED_TABLE = CY_SMIF_ID |CY_PDL_STATUS_ERROR | 0x07U, /**< The SFDP table is corrupted */ /** Failed to initialize the slave select 0 external memory by auto detection (SFDP). */ CY_SMIF_SFDP_SS0_FAILED = CY_SMIF_ID |CY_PDL_STATUS_ERROR | ((uint32_t)CY_SMIF_SFDP_FAIL << CY_SMIF_SFDP_FAIL_SS0_POS), diff --git a/drivers/include/cy_smif_memslot.h b/drivers/include/cy_smif_memslot.h index b4f1d27..69341a2 100644 --- a/drivers/include/cy_smif_memslot.h +++ b/drivers/include/cy_smif_memslot.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_smif_memslot.h -* \version 1.40.1 +* \version 1.50 * * \brief * This file provides the constants and parameter values for the memory-level @@ -201,11 +201,24 @@ extern "C" { #define CY_SMIF_SFDP_BFPT_BYTE_23 (0x23U) /**< The byte 0x23 of the JEDEC Basic Flash Parameter Table */ #define CY_SMIF_SFDP_BFPT_BYTE_28 (0x28U) /**< The byte 0x28 of the JEDEC Basic Flash Parameter Table */ #define CY_SMIF_SFDP_BFPT_BYTE_3A (0x3AU) /**< The byte 0x3A of the JEDEC Basic Flash Parameter Table */ +#define CY_SMIF_SFDP_BFPT_BYTE_3C (0x3CU) /**< The byte 0x3C of the JEDEC Basic Flash Parameter Table */ #define CY_SMIF_SFDP_BFPT_ERASE_BYTE (36U) /**< The byte 36 of the JEDEC Basic Flash Parameter Table */ #define CY_SMIF_JEDEC_BFPT_10TH_DWORD (9U) /**< Offset to JEDEC Basic Flash Parameter Table: 10th DWORD */ #define CY_SMIF_JEDEC_BFPT_11TH_DWORD (10U) /**< Offset to JEDEC Basic Flash Parameter Table: 11th DWORD */ + +#define CY_SMIF_SFDP_SECTOR_MAP_CMD_OFFSET (1UL) /**< The offset for the detection command instruction in the Sector Map command descriptor */ +#define CY_SMIF_SFDP_SECTOR_MAP_ADDR_CODE_OFFSET (2UL) /**< The offset for the detection command address length in the Sector Map command descriptor */ +#define CY_SMIF_SFDP_SECTOR_MAP_REG_MSK_OFFSET (3UL) /**< The offset for the read data mask in the Sector Map command descriptor */ +#define CY_SMIF_SFDP_SECTOR_MAP_REG_ADDR_OFFSET (4UL) /**< The offset for the detection command address in the Sector Map command descriptor */ +#define CY_SMIF_SFDP_SECTOR_MAP_REGION_COUNT_OFFSET (2UL) /**< The offset for the regions count in the Sector Map descriptor */ +#define CY_SMIF_SFDP_SECTOR_MAP_CONFIG_ID_OFFSET (2UL) /**< The offset for the configuration ID in the Sector Map descriptor */ +#define CY_SMIF_SFDP_SECTOR_MAP_SUPPORTED_ET_MASK (0xFU) /**< The mask for the supported erase type code in the Sector Map descriptor */ +#define CY_SMIF_SFDP_SECTOR_MAP_ADDR_BYTES_Msk (0xC0UL) /**< The mask for the configuration detection command address bytes in the Sector Map descriptor */ +#define CY_SMIF_SFDP_SECTOR_MAP_ADDR_BYTES_Pos (6UL) /**< The position of the configuration detection command address bytes in the Sector Map descriptor */ + + /* ---------------------------- 1st DWORD ---------------------------- */ #define CY_SMIF_SFDP_FAST_READ_1_1_4_Pos (6UL) /**< The SFDP 1-1-4 fast read support (Bit 6) */ #define CY_SMIF_SFDP_FAST_READ_1_1_4_Msk (0x40UL) /**< The SFDP 1-1-4 fast read support (Bitfield-Mask: 0x01) */ @@ -268,6 +281,14 @@ extern "C" { #define CY_SMIF_SFDP_QE_REQUIREMENTS_Pos (4UL) /**< The SFDP quad enable requirements field (Bit 4) */ #define CY_SMIF_SFDP_QE_REQUIREMENTS_Msk (0x70UL) /**< The SFDP quad enable requirements field (Bitfield-Mask: 0x07) */ + +/* ---------------------------- 16th DWORD --------------------------- */ +#define CY_SMIF_SFDP_ENTER_4_BYTE_METHOD_B7 (1U) /**< Issue 0xB7 instruction */ +#define CY_SMIF_SFDP_ENTER_4_BYTE_METHOD_WR_EN_B7 (2U) /**< Issue write enable instruction followed with 0xB7 */ +#define CY_SMIF_SFDP_ENTER_4_BYTE_METHOD_ALWAYS_4_BYTE (0x40U) /**< Memory always operates in 4-byte mode */ +#define CY_SMIF_SFDP_ENTER_4_BYTE_METHOD_B7_CMD (0xB7U) /**< The instruction required to enter 4-byte addressing mode */ + + /** \cond INTERNAL */ /******************************************************************************* * These are legacy constants and API. They are left here just @@ -327,6 +348,16 @@ typedef struct cy_en_smif_txfr_width_t dataWidth; /**< The width of the data transfer */ } cy_stc_smif_mem_cmd_t; +/** This structure specifies data used for memory with hybrid sectors */ +typedef struct +{ + uint32_t regionAddress; /**< This specifies the address where a region starts */ + uint32_t sectorsCount; /**< This specifies the number of sectors in the region */ + uint32_t eraseCmd; /**< This specifies the region specific erase instruction*/ + uint32_t eraseSize; /**< This specifies the size of one sector */ + uint32_t eraseTime; /**< Max time for sector erase type 1 cycle time in ms*/ +} cy_stc_smif_hybrid_region_info_t; + /** * @@ -337,31 +368,33 @@ typedef struct */ typedef struct { - uint32_t numOfAddrBytes; /**< This specifies the number of address bytes used by the - * memory slave device, valid values 1-4 */ - uint32_t memSize; /**< The memory size: For densities of 2 gigabits or less - the size in bytes; - * For densities 4 gigabits and above - bit-31 is set to 1b to define that - * this memory is 4 gigabits and above; and other 30:0 bits define N where - * the density is computed as 2^N bytes. - * For example, 0x80000021 corresponds to 2^30 = 1 gigabyte. - */ - cy_stc_smif_mem_cmd_t* readCmd; /**< This specifies the Read command */ - cy_stc_smif_mem_cmd_t* writeEnCmd; /**< This specifies the Write Enable command */ - cy_stc_smif_mem_cmd_t* writeDisCmd; /**< This specifies the Write Disable command */ - cy_stc_smif_mem_cmd_t* eraseCmd; /**< This specifies the Erase command */ - uint32_t eraseSize; /**< This specifies the sector size of each Erase */ - cy_stc_smif_mem_cmd_t* chipEraseCmd; /**< This specifies the Chip Erase command */ - cy_stc_smif_mem_cmd_t* programCmd; /**< This specifies the Program command */ - uint32_t programSize; /**< This specifies the page size for programming */ - cy_stc_smif_mem_cmd_t* readStsRegWipCmd; /**< This specifies the command to read the WIP-containing status register */ - cy_stc_smif_mem_cmd_t* readStsRegQeCmd; /**< This specifies the command to read the QE-containing status register */ - cy_stc_smif_mem_cmd_t* writeStsRegQeCmd; /**< This specifies the command to write into the QE-containing status register */ - cy_stc_smif_mem_cmd_t* readSfdpCmd; /**< This specifies the read SFDP command */ - uint32_t stsRegBusyMask; /**< The Busy mask for the status registers */ - uint32_t stsRegQuadEnableMask; /**< The QE mask for the status registers */ - uint32_t eraseTime; /**< Max time for erase type 1 cycle time in ms */ - uint32_t chipEraseTime; /**< Max time for chip erase cycle time in ms */ - uint32_t programTime; /**< Max time for page program cycle time in us */ + uint32_t numOfAddrBytes; /**< This specifies the number of address bytes used by the + * memory slave device, valid values 1-4 */ + uint32_t memSize; /**< The memory size: For densities of 2 gigabits or less - the size in bytes; + * For densities 4 gigabits and above - bit-31 is set to 1b to define that + * this memory is 4 gigabits and above; and other 30:0 bits define N where + * the density is computed as 2^N bytes. + * For example, 0x80000021 corresponds to 2^30 = 1 gigabyte. + */ + cy_stc_smif_mem_cmd_t* readCmd; /**< This specifies the Read command */ + cy_stc_smif_mem_cmd_t* writeEnCmd; /**< This specifies the Write Enable command */ + cy_stc_smif_mem_cmd_t* writeDisCmd; /**< This specifies the Write Disable command */ + cy_stc_smif_mem_cmd_t* eraseCmd; /**< This specifies the Erase command */ + uint32_t eraseSize; /**< This specifies the sector size of each Erase */ + cy_stc_smif_mem_cmd_t* chipEraseCmd; /**< This specifies the Chip Erase command */ + cy_stc_smif_mem_cmd_t* programCmd; /**< This specifies the Program command */ + uint32_t programSize; /**< This specifies the page size for programming */ + cy_stc_smif_mem_cmd_t* readStsRegWipCmd; /**< This specifies the command to read the WIP-containing status register */ + cy_stc_smif_mem_cmd_t* readStsRegQeCmd; /**< This specifies the command to read the QE-containing status register */ + cy_stc_smif_mem_cmd_t* writeStsRegQeCmd; /**< This specifies the command to write into the QE-containing status register */ + cy_stc_smif_mem_cmd_t* readSfdpCmd; /**< This specifies the read SFDP command */ + uint32_t stsRegBusyMask; /**< The Busy mask for the status registers */ + uint32_t stsRegQuadEnableMask; /**< The QE mask for the status registers */ + uint32_t eraseTime; /**< Max time for erase type 1 cycle time in ms */ + uint32_t chipEraseTime; /**< Max time for chip erase cycle time in ms */ + uint32_t programTime; /**< Max time for page program cycle time in us */ + uint32_t hybridRegionCount; /**< This specifies the number of regions for memory with hybrid sectors */ + cy_stc_smif_hybrid_region_info_t** hybridRegionInfo; /**< This specifies data for memory with hybrid sectors */ } cy_stc_smif_mem_device_cfg_t; @@ -490,7 +523,8 @@ cy_en_smif_status_t Cy_SMIF_MemEraseSector(SMIF_Type *base, cy_stc_smif_mem_conf cy_stc_smif_context_t const *context); cy_en_smif_status_t Cy_SMIF_MemEraseChip(SMIF_Type *base, cy_stc_smif_mem_config_t const *memConfig, cy_stc_smif_context_t const *context); - +cy_en_smif_status_t Cy_SMIF_MemLocateHybridRegion(cy_stc_smif_mem_config_t const *memDevice, + cy_stc_smif_hybrid_region_info_t** regionInfo, uint32_t address); /** \} group_smif_mem_slot_functions */ diff --git a/drivers/include/cy_sysclk.h b/drivers/include/cy_sysclk.h index f492640..9123dbc 100644 --- a/drivers/include/cy_sysclk.h +++ b/drivers/include/cy_sysclk.h @@ -1,12 +1,12 @@ /***************************************************************************//** * \file cy_sysclk.h -* \version 1.50 +* \version 1.60 * * Provides an API declaration of the sysclk driver. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -43,8 +43,8 @@ * clock system. * * The PDL defines clock system capabilities in:\n -* devices\//include\_config.h. (E.g. -* devices/psoc6/include/psoc6_01_config.h). +* devices/include/\_config.h. (E.g. +* devices/include/psoc6_01_config.h). * User-configurable clock speeds are defined in the file system_.h. * * As an illustration of the clocking system, the following diagram shows the @@ -104,6 +104,15 @@ *
            VersionChangesReason for Change
            1.50Added a new function: \ref Cy_SMIF_MemLocateHybridRegion.\n +* Added a new structure \ref cy_stc_smif_hybrid_region_info_t.\n +* Updated the \ref Cy_SMIF_MemEraseSector and \ref Cy_SMIF_MemCmdSectorErase functions.\n +* Updated the \ref Cy_SMIF_MemSfdpDetect function. \n +* Updated the \ref cy_stc_smif_mem_device_cfg_t structure.Support for memories with hybrid regions.
            1.40.1The \ref Cy_SMIF_MemInit is changed. Corrected a false assertion during initialization in SFDP mode.
            * * +* +* +* +* +* * * * @@ -277,7 +286,7 @@ * - IMO: 8 MHz Internal Main Oscillator (Default) * - EXTCLK: External clock (signal brought in through dedicated pins) * - ECO: External Crystal Oscillator (requires external crystal on dedicated pins) -* - ALTHF: Select on-chip signals (e.g. BLE ECO) +* - ALTHF: Select on-chip signals (e.g. \ref group_ble_clk) * - Digital Signal (DSI): Digital signal from a UDB source * * Some clock paths such as path 0 and path 1 have additional resources @@ -559,6 +568,13 @@ * ![](sysclk_slow.png) * * \defgroup group_sysclk_clk_slow_funcs Functions +* \} + * \defgroup group_sysclk_alt_hf Alternative High-Frequency Clock +* \{ +* In the BLE-enabled PSoC6 devices, the \ref group_ble_clk clock is +* connected to the system Alternative High-Frequency Clock input. +* +* \defgroup group_sysclk_alt_hf_funcs Functions * \} * \defgroup group_sysclk_clk_lf Low-Frequency Clock * \{ @@ -642,7 +658,7 @@ extern "C" { /** Driver major version */ #define CY_SYSCLK_DRV_VERSION_MAJOR 1 /** Driver minor version */ -#define CY_SYSCLK_DRV_VERSION_MINOR 40 +#define CY_SYSCLK_DRV_VERSION_MINOR 60 /** Sysclk driver identifier */ #define CY_SYSCLK_ID CY_PDL_DRV_ID(0x12U) @@ -685,6 +701,7 @@ typedef enum * \{ */ void Cy_SysClk_ExtClkSetFrequency(uint32_t freq); +uint32_t Cy_SysClk_ExtClkGetFrequency(void); /** \} group_sysclk_ext_funcs */ /* ========================================================================== */ @@ -719,6 +736,7 @@ void Cy_SysClk_ExtClkSetFrequency(uint32_t freq); */ cy_en_sysclk_status_t Cy_SysClk_EcoConfigure(uint32_t freq, uint32_t cLoad, uint32_t esr, uint32_t driveLevel); cy_en_sysclk_status_t Cy_SysClk_EcoEnable(uint32_t timeoutus); +uint32_t Cy_SysClk_EcoGetFrequency(void); __STATIC_INLINE void Cy_SysClk_EcoDisable(void); __STATIC_INLINE uint32_t Cy_SysClk_EcoGetStatus(void); @@ -802,6 +820,8 @@ typedef enum */ cy_en_sysclk_status_t Cy_SysClk_ClkPathSetSource(uint32_t clkPath, cy_en_clkpath_in_sources_t source); cy_en_clkpath_in_sources_t Cy_SysClk_ClkPathGetSource(uint32_t clkPath); +uint32_t Cy_SysClk_ClkPathMuxGetFrequency(uint32_t clkPath); +uint32_t Cy_SysClk_ClkPathGetFrequency(uint32_t clkPath); /** \} group_sysclk_path_src_funcs */ @@ -1121,9 +1141,11 @@ __STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_PllDisable(uint32_t clkPath) * \{ */ __STATIC_INLINE void Cy_SysClk_IloEnable(void); +__STATIC_INLINE bool Cy_SysClk_IloIsEnabled(void); __STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_IloDisable(void); __STATIC_INLINE void Cy_SysClk_IloHibernateOn(bool on); + /******************************************************************************* * Function Name: Cy_SysClk_IloEnable ****************************************************************************//** @@ -1142,6 +1164,24 @@ __STATIC_INLINE void Cy_SysClk_IloEnable(void) } +/******************************************************************************* +* Function Name: Cy_SysClk_IloIsEnabled +****************************************************************************//** +* +* Reports the Enabled/Disabled status of the ILO. +* +* \return Boolean status of ILO: true - Enabled, false - Disabled. +* +* \funcusage +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_IloDisable +* +*******************************************************************************/ +__STATIC_INLINE bool Cy_SysClk_IloIsEnabled(void) +{ + return (_FLD2BOOL(SRSS_CLK_ILO_CONFIG_ENABLE, SRSS_CLK_ILO_CONFIG)); +} + + /******************************************************************************* * Function Name: Cy_SysClk_IloDisable ****************************************************************************//** @@ -1204,6 +1244,7 @@ __STATIC_INLINE void Cy_SysClk_IloHibernateOn(bool on) * \{ */ __STATIC_INLINE void Cy_SysClk_PiloEnable(void); +__STATIC_INLINE bool Cy_SysClk_PiloIsEnabled(void); __STATIC_INLINE void Cy_SysClk_PiloDisable(void); __STATIC_INLINE void Cy_SysClk_PiloSetTrim(uint32_t trimVal); __STATIC_INLINE uint32_t Cy_SysClk_PiloGetTrim(void); @@ -1223,7 +1264,7 @@ __STATIC_INLINE uint32_t Cy_SysClk_PiloGetTrim(void); *******************************************************************************/ __STATIC_INLINE void Cy_SysClk_PiloEnable(void) { - SRSS_CLK_PILO_CONFIG |= _VAL2FLD(SRSS_CLK_PILO_CONFIG_PILO_EN, 1U); /* 1 = enable */ + SRSS_CLK_PILO_CONFIG |= SRSS_CLK_PILO_CONFIG_PILO_EN_Msk; /* 1 = enable */ Cy_SysLib_Delay(1U/*msec*/); /* release the reset and enable clock output */ SRSS_CLK_PILO_CONFIG |= SRSS_CLK_PILO_CONFIG_PILO_RESET_N_Msk | @@ -1231,6 +1272,24 @@ __STATIC_INLINE void Cy_SysClk_PiloEnable(void) } +/******************************************************************************* +* Function Name: Cy_SysClk_PiloIsEnabled +****************************************************************************//** +* +* Reports the Enabled/Disabled status of the PILO. +* +* \return Boolean status of PILO: true - Enabled, false - Disabled. +* +* \funcusage +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PiloDisable +* +*******************************************************************************/ +__STATIC_INLINE bool Cy_SysClk_PiloIsEnabled(void) +{ + return (_FLD2BOOL(SRSS_CLK_PILO_CONFIG_PILO_CLK_EN, SRSS_CLK_PILO_CONFIG)); +} + + /******************************************************************************* * Function Name: Cy_SysClk_PiloDisable ****************************************************************************//** @@ -1275,7 +1334,7 @@ __STATIC_INLINE void Cy_SysClk_PiloSetTrim(uint32_t trimVal) * Reports the current PILO trim bits value. * * \funcusage -* Refer to the Cy_SysClk_PiloSetTrim() function usage. +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PiloSetTrim * *******************************************************************************/ __STATIC_INLINE uint32_t Cy_SysClk_PiloGetTrim(void) @@ -1285,6 +1344,53 @@ __STATIC_INLINE uint32_t Cy_SysClk_PiloGetTrim(void) /** \} group_sysclk_pilo_funcs */ +/* ========================================================================== */ +/* ========================== ALTHF SECTION =========================== */ +/* ========================================================================== */ +/** +* \addtogroup group_sysclk_alt_hf_funcs +* \{ +*/ +__STATIC_INLINE uint32_t Cy_SysClk_AltHfGetFrequency(void); + + +/******************************************************************************* +* Function Name: Cy_SysClk_AltHfGetFrequency +****************************************************************************//** +* +* Reports the frequency of the Alternative High-Frequency Clock +* +* \funcusage +* \snippet bleclk/snippet/main.c BLE ECO clock API: Cy_BLE_EcoConfigure() +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_SysClk_AltHfGetFrequency(void) +{ + #if defined(CY_IP_MXBLESS) + return (cy_BleEcoClockFreqHz); + #else /* CY_IP_MXBLESS */ + return (0UL); + #endif /* CY_IP_MXBLESS */ +} +/** \} group_sysclk_alt_hf_funcs */ + + +/* ========================================================================== */ +/* ========================== ALTLF SECTION =========================== */ +/* ========================================================================== */ +/** \cond For future usage */ +__STATIC_INLINE uint32_t Cy_SysClk_AltLfGetFrequency(void) +{ + return (0UL); +} + +__STATIC_INLINE bool Cy_SysClk_AltLfIsEnabled(void) +{ + return (false); +} +/** \endcond */ + + /* ========================================================================== */ /* ==================== CLOCK MEASUREMENT SECTION ===================== */ /* ========================================================================== */ @@ -1845,6 +1951,7 @@ typedef struct * \{ */ __STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_ClkHfEnable(uint32_t clkHf); +__STATIC_INLINE bool Cy_SysClk_ClkHfIsEnabled(uint32_t clkHf); __STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_ClkHfDisable(uint32_t clkHf); __STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_ClkHfSetSource(uint32_t clkHf, cy_en_clkhf_in_sources_t source); __STATIC_INLINE cy_en_clkhf_in_sources_t Cy_SysClk_ClkHfGetSource(uint32_t clkHf); @@ -1879,6 +1986,31 @@ __STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_ClkHfEnable(uint32_t clkHf) } +/******************************************************************************* +* Function Name: Cy_SysClk_ClkHfIsEnabled +****************************************************************************//** +* +* Reports the Enabled/Disabled status of clkHf. +* +* \param clkHf Selects which clkHf to check. +* +* \return Boolean status of clkHf: true - Enabled, false - Disabled. +* +* \funcusage +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkHfDisable +* +*******************************************************************************/ +__STATIC_INLINE bool Cy_SysClk_ClkHfIsEnabled(uint32_t clkHf) +{ + bool retVal = false; + if (clkHf < CY_SRSS_NUM_HFROOT) + { + retVal = _FLD2BOOL(SRSS_CLK_ROOT_SELECT_ENABLE, SRSS_CLK_ROOT_SELECT[clkHf]); + } + return (retVal); +} + + /******************************************************************************* * Function Name: Cy_SysClk_ClkHfDisable ****************************************************************************//** @@ -2853,7 +2985,9 @@ __STATIC_INLINE cy_en_clktimer_in_sources_t Cy_SysClk_ClkTimerGetSource(void); __STATIC_INLINE void Cy_SysClk_ClkTimerSetDivider(uint8_t divider); __STATIC_INLINE uint8_t Cy_SysClk_ClkTimerGetDivider(void); __STATIC_INLINE void Cy_SysClk_ClkTimerEnable(void); +__STATIC_INLINE bool Cy_SysClk_ClkTimerIsEnabled(void); __STATIC_INLINE void Cy_SysClk_ClkTimerDisable(void); + uint32_t Cy_SysClk_ClkTimerGetFrequency(void); /******************************************************************************* * Function Name: Cy_SysClk_ClkTimerSetSource @@ -2953,6 +3087,24 @@ __STATIC_INLINE void Cy_SysClk_ClkTimerEnable(void) } +/******************************************************************************* +* Function Name: Cy_SysClk_ClkTimerIsEnabled +****************************************************************************//** +* +* Reports the Enabled/Disabled status of the Timer. +* +* \return Boolean status of Timer: true - Enabled, false - Disabled. +* +* \funcusage +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkTimerDisable +* +*******************************************************************************/ +__STATIC_INLINE bool Cy_SysClk_ClkTimerIsEnabled(void) +{ + return (_FLD2BOOL(SRSS_CLK_TIMER_CTL_ENABLE, SRSS_CLK_TIMER_CTL)); +} + + /******************************************************************************* * Function Name: Cy_SysClk_ClkTimerDisable ****************************************************************************//** @@ -2984,22 +3136,22 @@ __STATIC_INLINE void Cy_SysClk_ClkTimerDisable(void) */ typedef enum { - CY_SYSCLK_PUMP_IN_CLKPATH0, /**< Pump clock input is clock path 0 */ - CY_SYSCLK_PUMP_IN_CLKPATH1, /**< Pump clock input is clock path 1 */ - CY_SYSCLK_PUMP_IN_CLKPATH2, /**< Pump clock input is clock path 2 */ - CY_SYSCLK_PUMP_IN_CLKPATH3, /**< Pump clock input is clock path 3 */ - CY_SYSCLK_PUMP_IN_CLKPATH4, /**< Pump clock input is clock path 4 */ - CY_SYSCLK_PUMP_IN_CLKPATH5, /**< Pump clock input is clock path 5 */ - CY_SYSCLK_PUMP_IN_CLKPATH6, /**< Pump clock input is clock path 6 */ - CY_SYSCLK_PUMP_IN_CLKPATH7, /**< Pump clock input is clock path 7 */ - CY_SYSCLK_PUMP_IN_CLKPATH8, /**< Pump clock input is clock path 8 */ - CY_SYSCLK_PUMP_IN_CLKPATH9, /**< Pump clock input is clock path 9 */ - CY_SYSCLK_PUMP_IN_CLKPATH10, /**< Pump clock input is clock path 10 */ - CY_SYSCLK_PUMP_IN_CLKPATH11, /**< Pump clock input is clock path 11 */ - CY_SYSCLK_PUMP_IN_CLKPATH12, /**< Pump clock input is clock path 12 */ - CY_SYSCLK_PUMP_IN_CLKPATH13, /**< Pump clock input is clock path 13 */ - CY_SYSCLK_PUMP_IN_CLKPATH14, /**< Pump clock input is clock path 14 */ - CY_SYSCLK_PUMP_IN_CLKPATH15 /**< Pump clock input is clock path 15 */ + CY_SYSCLK_PUMP_IN_CLKPATH0 = 0UL, /**< Pump clock input is clock path 0 */ + CY_SYSCLK_PUMP_IN_CLKPATH1 = 1UL, /**< Pump clock input is clock path 1 */ + CY_SYSCLK_PUMP_IN_CLKPATH2 = 2UL, /**< Pump clock input is clock path 2 */ + CY_SYSCLK_PUMP_IN_CLKPATH3 = 3UL, /**< Pump clock input is clock path 3 */ + CY_SYSCLK_PUMP_IN_CLKPATH4 = 4UL, /**< Pump clock input is clock path 4 */ + CY_SYSCLK_PUMP_IN_CLKPATH5 = 5UL, /**< Pump clock input is clock path 5 */ + CY_SYSCLK_PUMP_IN_CLKPATH6 = 6UL, /**< Pump clock input is clock path 6 */ + CY_SYSCLK_PUMP_IN_CLKPATH7 = 7UL, /**< Pump clock input is clock path 7 */ + CY_SYSCLK_PUMP_IN_CLKPATH8 = 8UL, /**< Pump clock input is clock path 8 */ + CY_SYSCLK_PUMP_IN_CLKPATH9 = 9UL, /**< Pump clock input is clock path 9 */ + CY_SYSCLK_PUMP_IN_CLKPATH10 = 10UL, /**< Pump clock input is clock path 10 */ + CY_SYSCLK_PUMP_IN_CLKPATH11 = 11UL, /**< Pump clock input is clock path 11 */ + CY_SYSCLK_PUMP_IN_CLKPATH12 = 12UL, /**< Pump clock input is clock path 12 */ + CY_SYSCLK_PUMP_IN_CLKPATH13 = 13UL, /**< Pump clock input is clock path 13 */ + CY_SYSCLK_PUMP_IN_CLKPATH14 = 14UL, /**< Pump clock input is clock path 14 */ + CY_SYSCLK_PUMP_IN_CLKPATH15 = 15UL /**< Pump clock input is clock path 15 */ } cy_en_clkpump_in_sources_t; @@ -3035,7 +3187,9 @@ __STATIC_INLINE cy_en_clkpump_in_sources_t Cy_SysClk_ClkPumpGetSource(void); __STATIC_INLINE void Cy_SysClk_ClkPumpSetDivider(cy_en_clkpump_divide_t divider); __STATIC_INLINE cy_en_clkpump_divide_t Cy_SysClk_ClkPumpGetDivider(void); __STATIC_INLINE void Cy_SysClk_ClkPumpEnable(void); +__STATIC_INLINE bool Cy_SysClk_ClkPumpIsEnabled(void); __STATIC_INLINE void Cy_SysClk_ClkPumpDisable(void); +__STATIC_INLINE uint32_t Cy_SysClk_ClkPumpGetFrequency(void); /******************************************************************************* @@ -3136,6 +3290,24 @@ __STATIC_INLINE void Cy_SysClk_ClkPumpEnable(void) } +/******************************************************************************* +* Function Name: Cy_SysClk_ClkPumpIsEnabled +****************************************************************************//** +* +* Reports the Enabled/Disabled status of the ClkPump. +* +* \return Boolean status of ClkPump: true - Enabled, false - Disabled. +* +* \funcusage +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPumpDisable +* +*******************************************************************************/ +__STATIC_INLINE bool Cy_SysClk_ClkPumpIsEnabled(void) +{ + return (_FLD2BOOL(SRSS_CLK_SELECT_PUMP_ENABLE, SRSS_CLK_SELECT)); +} + + /******************************************************************************* * Function Name: Cy_SysClk_ClkPumpDisable ****************************************************************************//** @@ -3150,6 +3322,26 @@ __STATIC_INLINE void Cy_SysClk_ClkPumpDisable(void) { SRSS_CLK_SELECT &= ~SRSS_CLK_SELECT_PUMP_ENABLE_Msk; } + + +/******************************************************************************* +* Function Name: Cy_SysClk_ClkPumpGetFrequency +****************************************************************************//** +* +* Reports the frequency of the pump clock (clk_pump). +* \note If the the pump clock is not enabled - a zero frequency is reported. +* +* \funcusage +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPumpEnable +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_SysClk_ClkPumpGetFrequency(void) +{ + /* Divide the input frequency down and return the result */ + return (Cy_SysClk_ClkPumpIsEnabled() ? + (Cy_SysClk_ClkPathGetFrequency((uint32_t)Cy_SysClk_ClkPumpGetSource()) / + (1UL << (uint32_t)Cy_SysClk_ClkPumpGetDivider())) : 0UL); +} /** \} group_sysclk_clk_pump_funcs */ diff --git a/drivers/include/cy_syslib.h b/drivers/include/cy_syslib.h index 0d77778..2cc5353 100644 --- a/drivers/include/cy_syslib.h +++ b/drivers/include/cy_syslib.h @@ -1,12 +1,12 @@ /***************************************************************************//** * \file cy_syslib.h -* \version 2.50 +* \version 2.50.1 * * Provides an API declaration of the SysLib driver. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -139,6 +139,11 @@ *
            VersionChangesReason for Change
            1.60Added the following functions: \ref Cy_SysClk_ExtClkGetFrequency, \ref Cy_SysClk_EcoGetFrequency,\n +* \ref Cy_SysClk_ClkPathMuxGetFrequency, \ref Cy_SysClk_ClkPathGetFrequency, \ref Cy_SysClk_IloIsEnabled.\n +* \ref Cy_SysClk_PiloIsEnabled, \ref Cy_SysClk_AltHfGetFrequency, \ref Cy_SysClk_ClkHfIsEnabled,\n +* \ref Cy_SysClk_ClkTimerIsEnabled, \ref Cy_SysClk_ClkTimerGetFrequency, \ref Cy_SysClk_ClkPumpIsEnabled and\n +* \ref Cy_SysClk_ClkPumpGetFrequency.API enhancement.
            1.50\ref Cy_SysClk_ClkHfGetFrequency is updated to reuse the \ref cy_BleEcoClockFreqHz global system variable.API enhancement.
            * * +* +* +* +* * *
            VersionChangesReason for Change
            2.50.1Used the core library defines for the message codes forming. +* Improve PDL code base.
            2.50Moved following macros to the core library: * CY_LO8,CY_HI8,CY_LO16,CY_HI16,CY_SWAP_ENDIAN16,CY_SWAP_ENDIAN32, @@ -250,6 +255,7 @@ #include #include #include "cy_utils.h" +#include "cy_result.h" #include "cy_device.h" #include "cy_device_headers.h" @@ -290,13 +296,13 @@ extern "C" { * \{ * Function status type codes */ -#define CY_PDL_STATUS_CODE_Pos (0U) /**< The module status code position in the status code */ -#define CY_PDL_STATUS_TYPE_Pos (16U) /**< The status type position in the status code */ -#define CY_PDL_MODULE_ID_Pos (18U) /**< The software module ID position in the status code */ -#define CY_PDL_STATUS_INFO (0UL << CY_PDL_STATUS_TYPE_Pos) /**< The information status type */ -#define CY_PDL_STATUS_WARNING (1UL << CY_PDL_STATUS_TYPE_Pos) /**< The warning status type */ -#define CY_PDL_STATUS_ERROR (2UL << CY_PDL_STATUS_TYPE_Pos) /**< The error status type */ -#define CY_PDL_MODULE_ID_Msk (0x3FFFU) /**< The software module ID mask */ +#define CY_PDL_STATUS_CODE_Pos (CY_RSLT_CODE_POSITION) /**< The module status code position in the status code */ +#define CY_PDL_STATUS_TYPE_Pos (CY_RSLT_TYPE_POSITION) /**< The status type position in the status code */ +#define CY_PDL_MODULE_ID_Pos (CY_RSLT_MODULE_POSITION) /**< The software module ID position in the status code */ +#define CY_PDL_STATUS_INFO ((uint32_t)CY_RSLT_TYPE_INFO << CY_PDL_STATUS_TYPE_Pos) /**< The information status type */ +#define CY_PDL_STATUS_WARNING ((uint32_t)CY_RSLT_TYPE_WARNING << CY_PDL_STATUS_TYPE_Pos) /**< The warning status type */ +#define CY_PDL_STATUS_ERROR ((uint32_t)CY_RSLT_TYPE_ERROR << CY_PDL_STATUS_TYPE_Pos) /**< The error status type */ +#define CY_PDL_MODULE_ID_Msk (CY_RSLT_MODULE_MASK) /**< The software module ID mask */ /** Get the software PDL module ID */ #define CY_PDL_DRV_ID(id) ((uint32_t)((uint32_t)((id) & CY_PDL_MODULE_ID_Msk) << CY_PDL_MODULE_ID_Pos)) #define CY_SYSLIB_ID CY_PDL_DRV_ID(0x11U) /**< SYSLIB PDL ID */ diff --git a/drivers/include/cy_syspm.h b/drivers/include/cy_syspm.h index 85cd166..6d07177 100644 --- a/drivers/include/cy_syspm.h +++ b/drivers/include/cy_syspm.h @@ -1,12 +1,12 @@ /***************************************************************************//** * \file cy_syspm.h -* \version 4.50 +* \version 5.0 * * Provides the function definitions for the power management API. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -724,6 +724,23 @@ * * * +* +* +* +* +* * * *
            VersionChangesReason for Change
            5.0 +* Updated the internal IsVoltageChangePossible() function +* (\ref Cy_SysPm_LdoSetVoltage(), \ref Cy_SysPm_BuckEnable(), +* \ref Cy_SysPm_BuckSetVoltage1(), \ref Cy_SysPm_SystemEnterUlp() +* and \ref Cy_SysPm_SystemEnterLp() functions are affected). +* For all the devices except CY8C6xx6 and CY8C6xx7 added the check if +* modifying the RAM trim register is allowed. +* +* Protecting the system from a possible CPU hard-fault cause. If you +* are using PC > 0 in your project and you want to switch the power +* modes (LP<->ULP), you need to unprotect the CPUSS_TRIM_RAM_CTL and +* CPUSS_TRIM_ROM_CTL registers and can use a programmable PPU for that. +*
            4.50Updated the \ref Cy_SysPm_CpuEnterDeepSleep() function. @@ -1239,10 +1256,10 @@ extern "C" { */ /** Driver major version */ -#define CY_SYSPM_DRV_VERSION_MAJOR 4 +#define CY_SYSPM_DRV_VERSION_MAJOR 5 /** Driver minor version */ -#define CY_SYSPM_DRV_VERSION_MINOR 50 +#define CY_SYSPM_DRV_VERSION_MINOR 0 /** SysPm driver identifier */ #define CY_SYSPM_ID (CY_PDL_DRV_ID(0x10U)) diff --git a/drivers/source/TOOLCHAIN_ARM/cy_syslib_mdk.s b/drivers/source/TOOLCHAIN_ARM/cy_syslib_mdk.s index 16e71de..52069c4 100644 --- a/drivers/source/TOOLCHAIN_ARM/cy_syslib_mdk.s +++ b/drivers/source/TOOLCHAIN_ARM/cy_syslib_mdk.s @@ -1,11 +1,11 @@ ;------------------------------------------------------------------------------- ; \file cy_syslib_mdk.s -; \version 2.50 +; \version 2.50.1 ; ; \brief Assembly routines for ARMCC. ; ;------------------------------------------------------------------------------- -; Copyright 2016-2019 Cypress Semiconductor Corporation +; Copyright 2016-2020 Cypress Semiconductor Corporation ; SPDX-License-Identifier: Apache-2.0 ; ; Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/drivers/source/TOOLCHAIN_A_Clang/cy_syslib_a_clang.S b/drivers/source/TOOLCHAIN_A_Clang/cy_syslib_a_clang.S index 68249d7..62b526c 100644 --- a/drivers/source/TOOLCHAIN_A_Clang/cy_syslib_a_clang.S +++ b/drivers/source/TOOLCHAIN_A_Clang/cy_syslib_a_clang.S @@ -1,12 +1,12 @@ /***************************************************************************//** * \file cy_syslib_a_clang.S -* \version 2.50 +* \version 2.50.1 * * \brief Assembly routines for Apple Clang. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/drivers/source/TOOLCHAIN_GCC_ARM/cy_syslib_gcc.S b/drivers/source/TOOLCHAIN_GCC_ARM/cy_syslib_gcc.S index 1d6e16e..9af4ce1 100644 --- a/drivers/source/TOOLCHAIN_GCC_ARM/cy_syslib_gcc.S +++ b/drivers/source/TOOLCHAIN_GCC_ARM/cy_syslib_gcc.S @@ -1,12 +1,12 @@ /***************************************************************************//** * \file cy_syslib_gcc.S -* \version 2.50 +* \version 2.50.1 * * \brief Assembly routines for GNU GCC. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/drivers/source/TOOLCHAIN_IAR/cy_syslib_iar.s b/drivers/source/TOOLCHAIN_IAR/cy_syslib_iar.s index 8847749..ff7f89d 100644 --- a/drivers/source/TOOLCHAIN_IAR/cy_syslib_iar.s +++ b/drivers/source/TOOLCHAIN_IAR/cy_syslib_iar.s @@ -1,12 +1,12 @@ /***************************************************************************//** * \file cy_syslib_iar.s -* \version 2.50 +* \version 2.50.1 * * \brief Assembly routines for IAR Embedded Workbench IDE. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/drivers/source/cy_ble_clk.c b/drivers/source/cy_ble_clk.c index 8f92bd1..b9aefd8 100644 --- a/drivers/source/cy_ble_clk.c +++ b/drivers/source/cy_ble_clk.c @@ -1,13 +1,13 @@ /***************************************************************************//** * \file cy_ble_clk.c -* \version 3.30 +* \version 3.40 * * \brief * This driver provides the source code for API BLE ECO clock. * ******************************************************************************** * \copyright -* Copyright 2017-2019 Cypress Semiconductor Corporation +* Copyright 2017-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -235,8 +235,7 @@ cy_en_ble_eco_status_t Cy_BLE_EcoConfigure(cy_en_ble_eco_freq_t freq, cy_en_ble_ Cy_SysPm_IoUnfreeze(); } - if(((BLE_BLESS_MT_CFG & BLE_BLESS_MT_CFG_ENABLE_BLERD_Msk) != 0u) && - ((BLE_BLESS_MT_STATUS & BLE_BLESS_MT_STATUS_BLESS_STATE_Msk) != 0u)) + if(Cy_BLE_EcoIsEnabled()) { status = CY_BLE_ECO_ALREADY_STARTED; } diff --git a/drivers/source/cy_canfd.c b/drivers/source/cy_canfd.c index 4a8098f..1fd4028 100644 --- a/drivers/source/cy_canfd.c +++ b/drivers/source/cy_canfd.c @@ -1,13 +1,13 @@ /******************************************************************************* * \file cy_canfd.c -* \version 1.0.1 +* \version 1.10 * * \brief * Provides an API implementation of the CAN FD driver. * ******************************************************************************** * \copyright -* Copyright 2019 Cypress Semiconductor Corporation +* Copyright 2019-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -269,11 +269,8 @@ cy_en_canfd_status_t Cy_CANFD_Init(CANFD_Type *base, uint32_t chan, (NULL != config->bitrate) && (NULL != config->globalFilterConfig) && (NULL != config->rxFIFO0Config) && - (NULL != config->rxFIFO1Config) && - ((0U != config->sidFilterConfig->numberOfSIDFilters) && - (NULL != config->sidFilterConfig->sidFilter)) && - ((0U != config->extidFilterConfig->numberOfEXTIDFilters) && - (NULL != config->extidFilterConfig->extidFilter)) ) + (NULL != config->rxFIFO1Config) + ) { CY_ASSERT_L2(CY_CANFD_IS_CHANNEL_VALID(chan)); CY_ASSERT_L2(CY_CANFD_IS_NOM_PRESCALER_VALID(config->bitrate->prescaler)); @@ -318,25 +315,42 @@ cy_en_canfd_status_t Cy_CANFD_Init(CANFD_Type *base, uint32_t chan, context->messageRAMaddress = config->messageRAMaddress; context->messageRAMsize = config->messageRAMsize; - /* Configure a standard ID filter: - * The number of SID filters and Start address (word) of the SID filter - * configuration in Message RAM - */ - CANFD_SIDFC(base, chan) = - _VAL2FLD(CANFD_CH_M_TTCAN_SIDFC_LSS, config->sidFilterConfig->numberOfSIDFilters) | - _VAL2FLD(CANFD_CH_M_TTCAN_SIDFC_FLSSA, config->messageRAMaddress >> CY_CANFD_MRAM_SIGNIFICANT_BYTES_SHIFT); + if ((0U != config->sidFilterConfig->numberOfSIDFilters) && + (NULL != config->sidFilterConfig->sidFilter)) + { + /* Configure a standard ID filter: + * The number of SID filters and Start address (word) of the SID filter + * configuration in Message RAM + */ + CANFD_SIDFC(base, chan) = + _VAL2FLD(CANFD_CH_M_TTCAN_SIDFC_LSS, config->sidFilterConfig->numberOfSIDFilters) | + _VAL2FLD(CANFD_CH_M_TTCAN_SIDFC_FLSSA, config->messageRAMaddress >> CY_CANFD_MRAM_SIGNIFICANT_BYTES_SHIFT); + } + else + { + CANFD_SIDFC(base, chan) = 0U; + } - /* Configure an extended ID filter: - * The number of XID filters and start address (word) of the ext id - * filter configuration in Message RAM - */ - CANFD_XIDFC(base, chan) = - _VAL2FLD(CANFD_CH_M_TTCAN_XIDFC_LSE, config->extidFilterConfig->numberOfEXTIDFilters) | - _VAL2FLD(CANFD_CH_M_TTCAN_XIDFC_FLESA, _FLD2VAL(CANFD_CH_M_TTCAN_SIDFC_FLSSA, CANFD_SIDFC(base, chan)) + + if((0U != config->extidFilterConfig->numberOfEXTIDFilters) && + (NULL != config->extidFilterConfig->extidFilter)) + { + /* Configure an extended ID filter: + * The number of XID filters and start address (word) of the ext id + * filter configuration in Message RAM + */ + CANFD_XIDFC(base, chan) = + _VAL2FLD(CANFD_CH_M_TTCAN_XIDFC_LSE, config->extidFilterConfig->numberOfEXTIDFilters) | + _VAL2FLD(CANFD_CH_M_TTCAN_XIDFC_FLESA, _FLD2VAL(CANFD_CH_M_TTCAN_SIDFC_FLSSA, CANFD_SIDFC(base, chan)) + (config->sidFilterConfig->numberOfSIDFilters)); - /* Update the extended ID AND Mask */ - CANFD_XIDAM(base, chan) = _VAL2FLD(CANFD_CH_M_TTCAN_XIDAM_EIDM, config->extidFilterConfig->extIDANDMask); + /* Update the extended ID AND Mask */ + CANFD_XIDAM(base, chan) = _VAL2FLD(CANFD_CH_M_TTCAN_XIDAM_EIDM, config->extidFilterConfig->extIDANDMask); + } + else + { + CANFD_XIDFC(base, chan) = 0U; + CANFD_XIDAM(base, chan) = 0U; + } /* Configuration of Rx Buffer and Rx FIFO */ CANFD_RXESC(base, chan) = @@ -476,11 +490,17 @@ cy_en_canfd_status_t Cy_CANFD_Init(CANFD_Type *base, uint32_t chan, _VAL2FLD(CANFD_CH_M_TTCAN_GFC_RRFS, ((config->globalFilterConfig->rejectRemoteFramesStandard) ? 1UL : 0UL))| _VAL2FLD(CANFD_CH_M_TTCAN_GFC_RRFE, ((config->globalFilterConfig->rejectRemoteFramesExtended) ? 1UL : 0UL)); - /* Standard Message ID filters */ - Cy_CANFD_SidFiltersSetup(base, chan, config->sidFilterConfig, context); + if (0U != config->sidFilterConfig->numberOfSIDFilters) + { + /* Standard Message ID filters */ + Cy_CANFD_SidFiltersSetup(base, chan, config->sidFilterConfig, context); + } - /* Extended Message ID filters */ - Cy_CANFD_XidFiltersSetup(base, chan, config->extidFilterConfig, context); + if(0U != config->extidFilterConfig->numberOfEXTIDFilters) + { + /* Extended Message ID filters */ + Cy_CANFD_XidFiltersSetup(base, chan, config->extidFilterConfig, context); + } /* Configure the interrupt */ Cy_CANFD_SetInterruptMask(base, chan, CY_CANFD_INTERRUPT_ENABLE_DEFAULT); diff --git a/drivers/source/cy_device.c b/drivers/source/cy_device.c index c89104a..a3358e3 100644 --- a/drivers/source/cy_device.c +++ b/drivers/source/cy_device.c @@ -357,6 +357,113 @@ const cy_stc_device_t cy_deviceIpBlockCfgPSoC6_03 = /* ipcLockStatusOffset */ offsetof(IPC_STRUCT_V2_Type, LOCK_STATUS), }; +const cy_stc_device_t cy_deviceIpBlockCfgPSoC6_04 = +{ + /* Base HW addresses */ + /* cpussBase */ 0x40200000UL, + /* flashcBase */ 0x40240000UL, + /* periBase */ 0x40000000UL, + /* udbBase */ 0UL, + /* protBase */ 0x40230000UL, + /* hsiomBase */ 0x40300000UL, + /* gpioBase */ 0x40310000UL, + /* passBase */ 0x409F0000UL, + /* ipcBase */ 0x40220000UL, + /* cryptoBase */ 0x40100000UL, + + /* IP block versions [7:4] major, [3:0] minor */ + /* cpussVersion */ 0x20U, + /* cryptoVersion */ 0x20U, + /* dwVersion */ 0x20U, + /* ipcVersion */ 0x20U, + /* periVersion */ 0x20U, + /* srssVersion */ 0x13U, + + /* Parameters */ + /* cpussIpcNr */ 16U, + /* cpussIpcIrqNr */ 16U, + /* cpussDw0ChNr */ 30U, + /* cpussDw1ChNr */ 32U, + /* cpussFlashPaSize */ 128U, + /* cpussIpc0Irq */ 23, + /* cpussFmIrq */ 117, + /* cpussNotConnectedIrq */ 1023, + /* srssNumClkpath */ 5U, + /* srssNumPll */ 1U, + /* srssNumHfroot */ 4U, + /* periClockNr */ 28U, + /* smifDeviceNr */ 3U, + /* passSarChannels */ 16U, + /* epMonitorNr */ 0u, + /* udbPresent */ 0U, + /* sysPmSimoPresent */ 1U, + /* protBusMasterMask */ 0xC01FUL, + /* cryptoMemSize */ 1024u, + /* flashRwwRequired */ 0U, + /* flashPipeRequired */ 0U, + /* flashWriteDelay */ 0U, + /* flashProgramDelay */ 0U, + /* flashEraseDelay */ 0U, + /* flashCtlMainWs0Freq */ 25U, + /* flashCtlMainWs1Freq */ 50U, + /* flashCtlMainWs2Freq */ 75U, + /* flashCtlMainWs3Freq */ 100U, + /* flashCtlMainWs4Freq */ 125U, + + /* Peripheral register offsets */ + + /* DW registers */ + /* dwChOffset */ (uint16_t)offsetof(DW_V2_Type, CH_STRUCT), + /* dwChSize */ sizeof(DW_CH_STRUCT_V2_Type), + /* dwChCtlPrioPos */ (uint8_t)DW_CH_STRUCT_V2_CH_CTL_PRIO_Pos, + /* dwChCtlPreemptablePos */ (uint8_t)DW_CH_STRUCT_V2_CH_CTL_PREEMPTABLE_Pos, + /* dwStatusChIdxPos */ (uint8_t)DW_V2_STATUS_CH_IDX_Pos, + /* dwStatusChIdxMsk */ DW_V2_STATUS_CH_IDX_Msk, + + /* PERI registers */ + /* periTrCmdOffset */ (uint16_t)offsetof(PERI_V2_Type, TR_CMD), + /* periTrCmdGrSelMsk */ (uint16_t)PERI_V2_TR_CMD_GROUP_SEL_Msk, + /* periTrGrOffset */ (uint16_t)offsetof(PERI_V2_Type, TR_GR), + /* periTrGrSize */ sizeof(PERI_TR_GR_V2_Type), + + /* periDivCmdDivSelMsk */ (uint8_t)PERI_V2_DIV_CMD_DIV_SEL_Msk, + /* periDivCmdTypeSelPos */ (uint8_t)PERI_V2_DIV_CMD_TYPE_SEL_Pos, + /* periDivCmdPaDivSelPos */ (uint8_t)PERI_V2_DIV_CMD_PA_DIV_SEL_Pos, + /* periDivCmdPaTypeSelPos */ (uint8_t)PERI_V2_DIV_CMD_PA_TYPE_SEL_Pos, + + /* periDiv8CtlOffset */ (uint16_t)offsetof(PERI_V2_Type, DIV_8_CTL), + /* periDiv16CtlOffset */ (uint16_t)offsetof(PERI_V2_Type, DIV_16_CTL), + /* periDiv16_5CtlOffset */ (uint16_t)offsetof(PERI_V2_Type, DIV_16_5_CTL), + /* periDiv24_5CtlOffset */ (uint16_t)offsetof(PERI_V2_Type, DIV_24_5_CTL), + + /* GPIO registers */ + /* gpioPrtIntrCfgOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, INTR_CFG), + /* gpioPrtCfgOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, CFG), + /* gpioPrtCfgInOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, CFG_IN), + /* gpioPrtCfgOutOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, CFG_OUT), + /* gpioPrtCfgSioOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, CFG_SIO), + + /* CPUSS registers */ + /* cpussCm0ClockCtlOffset */ offsetof(CPUSS_V2_Type, CM0_CLOCK_CTL), + /* cpussCm4ClockCtlOffset */ offsetof(CPUSS_V2_Type, CM4_CLOCK_CTL), + /* cpussCm4StatusOffset */ offsetof(CPUSS_V2_Type, CM4_STATUS), + /* cpussCm0StatusOffset */ offsetof(CPUSS_V2_Type, CM0_STATUS), + /* cpussCm4PwrCtlOffset */ offsetof(CPUSS_V2_Type, CM4_PWR_CTL), + /* cpussTrimRamCtlOffset */ offsetof(CPUSS_V2_Type, TRIM_RAM_CTL), + /* cpussTrimRomCtlOffset */ offsetof(CPUSS_V2_Type, TRIM_ROM_CTL), + /* cpussSysTickCtlOffset */ offsetof(CPUSS_V2_Type, SYSTICK_CTL), + /* cpussCm0NmiCtlOffset */ (uint16_t)offsetof(CPUSS_V2_Type, CM0_NMI_CTL), + /* cpussCm4NmiCtlOffset */ (uint16_t)offsetof(CPUSS_V2_Type, CM4_NMI_CTL), + /* cpussRomCtl */ (uint16_t)offsetof(CPUSS_V2_Type, ROM_CTL), + /* cpussRam0Ctl0 */ (uint16_t)offsetof(CPUSS_V2_Type, RAM0_CTL0), + /* cpussRam1Ctl0 */ (uint16_t)offsetof(CPUSS_V2_Type, RAM1_CTL0), + /* cpussRam2Ctl0 */ (uint16_t)offsetof(CPUSS_V2_Type, RAM2_CTL0), + + /* IPC registers */ + /* ipcStructSize */ sizeof(IPC_STRUCT_V2_Type), + /* ipcLockStatusOffset */ offsetof(IPC_STRUCT_V2_Type, LOCK_STATUS), +}; + /****************************************************************************** * Function Name: Cy_PDL_Init diff --git a/drivers/source/cy_efuse.c b/drivers/source/cy_efuse.c index 3081663..55e985f 100644 --- a/drivers/source/cy_efuse.c +++ b/drivers/source/cy_efuse.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_efuse.c -* \version 1.10.1 +* \version 1.10.2 * * \brief * Provides API implementation of the eFuse driver. @@ -62,7 +62,7 @@ static cy_en_efuse_status_t ProcessOpcode(void); * - 8 is a number of fuse bits in the byte. * * The EFUSE_EFUSE_NR macro is defined in the series-specific header file, e.g -* \e \/devices/psoc6/include/psoc6_01_config.\e h +* \e \/devices/include/psoc6_01_config.\e h * * \param bitVal * The pointer to the location to store the bit value. @@ -119,7 +119,7 @@ cy_en_efuse_status_t Cy_EFUSE_GetEfuseBit(uint32_t bitNum, bool *bitVal) * - 32 is a number of fuse bytes in one efuse macro. * * The EFUSE_EFUSE_NR macro is defined in the series-specific header file, e.g -* \e \/devices/psoc6/include/psoc6_01_config.\e h +* \e \/devices/include/psoc6_01_config.\e h * * \param byteVal * The pointer to the location to store eFuse data. diff --git a/drivers/source/cy_flash.c b/drivers/source/cy_flash.c index f5bd30c..1911b97 100644 --- a/drivers/source/cy_flash.c +++ b/drivers/source/cy_flash.c @@ -1,13 +1,13 @@ /***************************************************************************//** * \file cy_flash.c -* \version 3.30.3 +* \version 3.30.4 * * \brief * Provides the public functions for the API for the PSoC 6 Flash Driver. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -668,8 +668,9 @@ cy_en_flashdrv_status_t Cy_Flash_EraseRow(uint32_t rowAddr) * XRES pin, a software reset, and watchdog reset sources. Also, the low-voltage * detect circuits should be configured to generate an interrupt instead of a reset. * Otherwise, portions of flash may undergo unexpected changes. -* \note Before reading data from previously programmed/erased flash rows, the -* user must clear the flash cache with the Cy_SysLib_ClearFlashCacheAndBuffer() +* \note To avoid situation of reading data from cache memory - before +* reading data from previously programmed/erased flash rows, the user must +* clear the flash cache with the Cy_SysLib_ClearFlashCacheAndBuffer() * function. * * \param rowAddr Address of the flash row number. @@ -719,7 +720,7 @@ cy_en_flashdrv_status_t Cy_Flash_StartEraseRow(uint32_t rowAddr) * Function Name: Cy_Flash_EraseSector ****************************************************************************//** * -* This function erases a 256KB sector of flash. Reports success or +* This function erases a sector of flash. Reports success or * a reason for failure. Does not return until the Erase operation is * complete. Returns immediately and reports a \ref CY_FLASH_DRV_IPC_BUSY error in * the case when another process is writing to flash or erasing the row. @@ -772,7 +773,7 @@ cy_en_flashdrv_status_t Cy_Flash_EraseSector(uint32_t sectorAddr) * Function Name: Cy_Flash_StartEraseSector ****************************************************************************//** * -* Starts erasing a 256KB sector of flash. Returns immediately +* Starts erasing a sector of flash. Returns immediately * and reports a successful start or reason for failure. * Reports a \ref CY_FLASH_DRV_IPC_BUSY error in the case when IPC structure is locked * by another process. User firmware should not enter the Hibernate or Deep Sleep mode until diff --git a/drivers/source/cy_prot.c b/drivers/source/cy_prot.c index 4731fa7..6ea05a0 100644 --- a/drivers/source/cy_prot.c +++ b/drivers/source/cy_prot.c @@ -1,13 +1,13 @@ /***************************************************************************//** * \file cy_prot.c -* \version 1.30.1 +* \version 1.30.2 * * \brief * Provides an API implementation of the Protection Unit driver * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -776,11 +776,12 @@ cy_en_prot_status_t Cy_Prot_GetSmpuStruct(PROT_SMPU_SMPU_STRUCT_Type** base, * The register to update attributes in. * * \param pcMask -* The protection context mask. This is a 16-bit value of the allowed contexts. -* It is an OR'ed (|) field of the * provided defines in cy_prot.h. -* For example: (CY_PROT_PCMASK1 | CY_PROT_PCMASK3 | CY_PROT_PCMASK4). -* \note The function accepts pcMask values from CY_PROT_PCMASK1 to CY_PROT_PCMASK5. -* But each device has its own number of available protection contexts. +* The protection context mask. It specifies the protection context or a set of +* multiple protection contexts to be configured. +* It is a value of OR'd (|) items of \ref cy_en_prot_pcmask_t. +* For example: (\ref CY_PROT_PCMASK1 | \ref CY_PROT_PCMASK3 | \ref CY_PROT_PCMASK4). +* \note The function accepts pcMask values from \ref CY_PROT_PCMASK1 to \ref CY_PROT_PCMASK15. +* But each device has its own number of available protection contexts. * That number is defined by PERI_PC_NR in the config file. * * \param userPermission @@ -888,11 +889,12 @@ static cy_en_prot_status_t Prot_ConfigPpuAtt(volatile uint32_t * reg, uint16_t p * The register base address of the protection structure is being configured. * * \param pcMask -* The protection context mask. This is a 16-bit value of the allowed contexts, -* it is an OR'ed (|) field of the * provided defines in cy_prot.h. -* For example: (CY_PROT_PCMASK1 | CY_PROT_PCMASK3 | CY_PROT_PCMASK4). -* \note The function accepts pcMask values from CY_PROT_PCMASK1 to CY_PROT_PCMASK15. -* But each device has its own number of available protection contexts. +* The protection context mask. It specifies the protection context or a set of +* multiple protection contexts to be configured. +* It is a value of OR'd (|) items of \ref cy_en_prot_pcmask_t. +* For example: (\ref CY_PROT_PCMASK1 | \ref CY_PROT_PCMASK3 | \ref CY_PROT_PCMASK4). +* \note The function accepts pcMask values from \ref CY_PROT_PCMASK1 to \ref CY_PROT_PCMASK15. +* But each device has its own number of available protection contexts. * That number is defined by PERI_PC_NR in the config file. * * \param userPermission @@ -1013,11 +1015,12 @@ cy_en_prot_status_t Cy_Prot_ConfigPpuProgSlaveAddr(PERI_MS_PPU_PR_Type* base, ui * The register base address of the protection structure is being configured. * * \param pcMask -* The protection context mask. This is a 16-bit value of the allowed contexts, -* it is an OR'ed (|) field of the * provided defines in cy_prot.h. -* For example: (CY_PROT_PCMASK1 | CY_PROT_PCMASK3 | CY_PROT_PCMASK4). -* \note The function accepts pcMask values from CY_PROT_PCMASK1 to CY_PROT_PCMASK15. -* But each device has its own number of available protection contexts. +* The protection context mask. It specifies the protection context or a set of +* multiple protection contexts to be configured. +* It is a value of OR'd (|) items of \ref cy_en_prot_pcmask_t. +* For example: (\ref CY_PROT_PCMASK1 | \ref CY_PROT_PCMASK3 | \ref CY_PROT_PCMASK4). +* \note The function accepts pcMask values from \ref CY_PROT_PCMASK1 to \ref CY_PROT_PCMASK15. +* But each device has its own number of available protection contexts. * That number is defined by PERI_PC_NR in the config file. * * \param userPermission @@ -1167,11 +1170,12 @@ cy_en_prot_status_t Cy_Prot_DisablePpuProgSlaveRegion(PERI_MS_PPU_PR_Type* base) * The register base address of the protection structure is being configured. * * \param pcMask -* The protection context mask. This is a 16-bit value of the allowed contexts, -* it is an OR'ed (|) field of the * provided defines in cy_prot.h. -* For example: (CY_PROT_PCMASK1 | CY_PROT_PCMASK3 | CY_PROT_PCMASK4). -* \note The function accepts pcMask values from CY_PROT_PCMASK1 to CY_PROT_PCMASK15. -* But each device has its own number of available protection contexts. +* The protection context mask. It specifies the protection context or a set of +* multiple protection contexts to be configured. +* It is a value of OR'd (|) items of \ref cy_en_prot_pcmask_t. +* For example: (\ref CY_PROT_PCMASK1 | \ref CY_PROT_PCMASK3 | \ref CY_PROT_PCMASK4). +* \note The function accepts pcMask values from \ref CY_PROT_PCMASK1 to \ref CY_PROT_PCMASK15. +* But each device has its own number of available protection contexts. * That number is defined by PERI_PC_NR in the config file. * * \param userPermission @@ -1232,11 +1236,12 @@ cy_en_prot_status_t Cy_Prot_ConfigPpuFixedMasterAtt(PERI_MS_PPU_FX_Type* base, u * The register base address of the protection structure is being configured. * * \param pcMask -* The protection context mask. This is a 16-bit value of the allowed contexts, -* it is an OR'ed (|) field of the * provided defines in cy_prot.h. -* For example: (CY_PROT_PCMASK1 | CY_PROT_PCMASK3 | CY_PROT_PCMASK4). -* \note The function accepts pcMask values from CY_PROT_PCMASK1 to CY_PROT_PCMASK15. -* But each device has its own number of available protection contexts. +* The protection context mask. It specifies the protection context or a set of +* multiple protection contexts to be configured. +* It is a value of OR'd (|) items of \ref cy_en_prot_pcmask_t. +* For example: (\ref CY_PROT_PCMASK1 | \ref CY_PROT_PCMASK3 | \ref CY_PROT_PCMASK4). +* \note The function accepts pcMask values from \ref CY_PROT_PCMASK1 to \ref CY_PROT_PCMASK15. +* But each device has its own number of available protection contexts. * That number is defined by PERI_PC_NR in the config file. * * \param userPermission diff --git a/drivers/source/cy_rtc.c b/drivers/source/cy_rtc.c index 3595166..8c9f953 100644 --- a/drivers/source/cy_rtc.c +++ b/drivers/source/cy_rtc.c @@ -1,12 +1,13 @@ /***************************************************************************//** * \file cy_rtc.c -* \version 2.20.1 +* \version 2.30 * * This file provides constants and parameter values for the APIs for the * Real-Time Clock (RTC). * ******************************************************************************** -* Copyright 2016-2019 Cypress Semiconductor Corporation +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -886,9 +887,10 @@ cy_en_rtc_status_t Cy_RTC_EnableDstTime(cy_stc_rtc_dst_t const *dstTime, cy_stc_ * Function Name: Cy_RTC_SetNextDstTime ****************************************************************************//** * -* Set the next time of the DST. This function sets the time to ALARM2 for a next -* DST event. If Cy_RTC_GetDSTStatus() is true(=1), the next DST event should be -* the DST stop, then this function should be called with the DST stop time. +* A low-level DST function sets ALARM2 for a next DST event. +* If Cy_RTC_GetDSTStatus() is true(=1), the next DST event should be +* the DST stop, then this function should be called with the DST stop time. +* Used by the \ref Cy_RTC_EnableDstTime and \ref Cy_RTC_DstInterrupt functions. * * If the time format(.format) is relative option(=0), the * RelativeToFixed() is called to convert to a fixed date. @@ -959,9 +961,11 @@ cy_en_rtc_status_t Cy_RTC_SetNextDstTime(cy_stc_rtc_dst_format_t const *nextDst) * Function Name: Cy_RTC_GetDstStatus ****************************************************************************//** * -* Returns the current DST status using given time information. This function -* is used in the initial state of a system. If the DST is enabled, the system -* sets the DST start or stop as a result of this function. +* A low-level DST function returns the current DST status using given time +* information. This function is used in the initial state of a system. +* If the DST is enabled, the system sets the DST start or stop as a result of +* this function. +* Used by the \ref Cy_RTC_EnableDstTime and \ref Cy_RTC_DstInterrupt functions. * * \param dstTime The DST configuration structure, see \ref cy_stc_rtc_dst_t. * @@ -981,6 +985,7 @@ bool Cy_RTC_GetDstStatus(cy_stc_rtc_dst_t const *dstTime, cy_stc_rtc_config_t co uint32_t dstStopTime; uint32_t dstStartDayOfMonth; uint32_t dstStopDayOfMonth; + bool status = false; CY_ASSERT_L1(NULL != dstTime); CY_ASSERT_L1(NULL != timeDate); @@ -1019,11 +1024,41 @@ bool Cy_RTC_GetDstStatus(cy_stc_rtc_dst_t const *dstTime, cy_stc_rtc_config_t co currentTime = ((uint32_t) (timeDate->month << CY_RTC_DST_MONTH_POSITION) | (timeDate->date << CY_RTC_DST_DAY_OF_MONTH_POSITION) | (timeDate->hour)); - + dstStopTime = ((uint32_t) (dstTime->stopDst.month << CY_RTC_DST_MONTH_POSITION) | (dstStopDayOfMonth << CY_RTC_DST_DAY_OF_MONTH_POSITION) | (dstTime->stopDst.hour)); - return((dstStartTime <= currentTime) && (dstStopTime > currentTime)); + if ((dstStartTime <= currentTime) && (dstStopTime > currentTime)) + { + status = true; + + if (1UL == (dstStopTime - currentTime)) /* Check for the 'an hour before/after stop DST event' period */ + { + cy_stc_rtc_alarm_t alarm; + uint32_t locDate = (CY_RTC_DST_FIXED != dstTime->startDst.format) ? RelativeToFixed(&dstTime->startDst) : dstTime->startDst.dayOfMonth; + Cy_RTC_GetAlarmDateAndTime(&alarm, CY_RTC_ALARM_2); + + /* If Alarm2 is set for the "Start DST" event - the "Stop DST" event is already passed: */ + if ((alarm.almEn == CY_RTC_ALARM_ENABLE ) && + (alarm.monthEn == CY_RTC_ALARM_ENABLE ) && + (alarm.month == dstTime->startDst.month) && + (alarm.dateEn == CY_RTC_ALARM_ENABLE ) && + (alarm.date == locDate ) && + (alarm.dayOfWeekEn == CY_RTC_ALARM_DISABLE ) && + (alarm.hourEn == CY_RTC_ALARM_ENABLE ) && + (alarm.hour == dstTime->startDst.hour ) && + (alarm.minEn == CY_RTC_ALARM_ENABLE ) && + (alarm.min == 0UL ) && + (alarm.secEn == CY_RTC_ALARM_ENABLE ) && + (alarm.sec == 0UL )) + { + status = false; + } + /* Otherwise, including the case when Alarm2 is not set at all (DST is not enabled yet) - return true. */ + } + } + + return (status); } diff --git a/drivers/source/cy_smif.c b/drivers/source/cy_smif.c index 30cad1e..875573a 100644 --- a/drivers/source/cy_smif.c +++ b/drivers/source/cy_smif.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_smif.c -* \version 1.40.1 +* \version 1.50 * * \brief * This file provides the source code for the SMIF driver APIs. diff --git a/drivers/source/cy_smif_memslot.c b/drivers/source/cy_smif_memslot.c index 114c5e5..5a28464 100644 --- a/drivers/source/cy_smif_memslot.c +++ b/drivers/source/cy_smif_memslot.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_smif_memslot.c -* \version 1.40.1 +* \version 1.50 * * \brief * This file provides the source code for the memory-level APIs of the SMIF driver. @@ -66,10 +66,15 @@ extern "C" { #define INSTRUCTION_NOT_SUPPORTED (0XFFU) /* The code for the not supported instruction */ #define BASIC_SPI_ID_LSB (0X00UL) /* The JEDEC SFDP Basic SPI Flash Parameter ID LSB */ #define BASIC_SPI_ID_MSB (0XFFUL) /* The JEDEC SFDP Basic SPI Flash Parameter ID MSB */ +#define SECTOR_MAP_ID_LSB (0x81UL) /* The JEDEC SFDP Sector Map ID LSB */ +#define SECTOR_MAP_ID_MSB (0xFFUL) /* The JEDEC SFDP Sector Map ID MSB */ +#define SECTOR_MAP_DESCRIPTOR_MASK (0x2U) /* The mask for the type bit of the Sector Map descriptor */ +#define SECTOR_MAP_COMAND_DESCRIPTOR_TYPE (0U) /* Code for the command descriptor type */ +#define SECTOR_MAP_REGION_SIZE_MULTIPLIER (256UL) /* The multiplier for region size units */ #define FOUR_BYTE_ADDR_ID_LSB (0X84UL) /* The 4-byte Address Instruction Table is assigned the ID LSB of 84h */ #define FOUR_BYTE_ADDR_ID_MSB (0XFFUL) /* The 4-byte Address Instruction Table is assigned the ID MSB of FFh */ -#define FOUR_BYTE_ADDR_ERASE_TYPE_1 (0X4UL) /* The Erase Type 1 offset in 4-byte Address Instruction Table */ -#define FOUR_BYTE_ADDR_ERASE_TYPE_4 (0X7UL) /* The Erase Type 4 offset in 4-byte Address Instruction Table */ +#define FOUR_BYTE_ADDR_ERASE_TYPE_1 (0X4UL) /* The Erase Type 1 offset in 4-byte Address Instruction Table */ +#define FOUR_BYTE_ADDR_ERASE_TYPE_4 (0X7UL) /* The Erase Type 4 offset in 4-byte Address Instruction Table */ #define ERASE_T_COUNT_Pos (0UL) /* Erase Type X Erase, Typical time: count (Bits 4:0) */ #define ERASE_T_COUNT_Msk (0x1FUL) /* Erase Type X Erase, Typical time: count (Bitfield-Mask) */ #define ERASE_T_UNITS_Pos (5UL) /* Erase Type X Erase, Typical time: units (Bits 6:5) */ @@ -178,6 +183,21 @@ typedef enum /** \endcond*/ +/*************************************** +* Internal Structures +***************************************/ + +/** +* This internal structure is used to store data for erase types. +*/ +typedef struct +{ + uint8_t eraseCmd; /**< The instruction used for erase transaction*/ + uint32_t eraseSize; /**< The number of bytes to be erased at one erase transaction*/ + uint32_t eraseTime; /**< The maximum erase time for one erase transaction */ +} cy_stc_smif_erase_type_t; + + /*************************************** * Internal Function Prototypes ***************************************/ @@ -214,7 +234,7 @@ static void SfdpGetReadFourBytesCmd(uint8_t const sfdpBuffer[], cy_en_smif_protocol_mode_t protocolMode, cy_stc_smif_mem_cmd_t* cmdRead); static uint32_t SfdpGetPageSize(uint8_t const sfdpBuffer[]); -static uint32_t SfdpGetEraseTime(uint32_t const eraseOffset, uint8_t const sfdpBuffer[]); +static uint32_t SfdpGetEraseTime(uint32_t const eraseOffset, uint8_t const sfdpBuffer[], cy_stc_smif_erase_type_t eraseType[]); static uint32_t SfdpGetChipEraseTime(uint8_t const sfdpBuffer[]); static uint32_t SfdpGetPageProgramTime(uint8_t const sfdpBuffer[]); static void SfdpSetWriteEnableCommand(cy_stc_smif_mem_cmd_t* cmdWriteEnable); @@ -230,11 +250,25 @@ static void SfdpGetQuadEnableParameters(cy_stc_smif_mem_device_cfg_t *device, uint8_t const sfdpBuffer[]); static void SfdpSetChipEraseCommand(cy_stc_smif_mem_cmd_t* cmdChipErase); static uint32_t SfdpGetSectorEraseCommand(cy_stc_smif_mem_device_cfg_t *device, - uint8_t const sfdpBuffer[]); + uint8_t const sfdpBuffer[], + cy_stc_smif_erase_type_t eraseTypeStc[]); +static cy_en_smif_status_t ReadAnyReg(SMIF_Type *base, cy_en_smif_slave_select_t slaveSelect, + uint8_t *value, uint8_t command, uint8_t const *address, + uint32_t addressSize, cy_stc_smif_context_t const *context); +static cy_en_smif_status_t SfdpEnterFourByteAddressing(SMIF_Type *base, uint8_t entryMethodByte, + cy_stc_smif_mem_device_cfg_t *device, + cy_en_smif_slave_select_t slaveSelect, + cy_stc_smif_context_t const *context); +static void SfdpGetEraseSizeAndCmd(uint8_t const sfdpBuffer[], cy_stc_smif_erase_type_t eraseType[]); +static cy_en_smif_status_t SfdpPopulateRegionInfo(SMIF_Type *base, uint8_t const sectorMapBuff[], + uint32_t const buffLength, cy_stc_smif_mem_device_cfg_t *device, + cy_en_smif_slave_select_t slaveSelect, const cy_stc_smif_context_t *context, + cy_stc_smif_erase_type_t eraseType[]); static void SfdpSetWipStatusRegisterCommand(cy_stc_smif_mem_cmd_t* readStsRegWipCmd); static cy_en_smif_status_t PollTransferStatus(SMIF_Type const *base, cy_en_smif_txfr_status_t transferStatus, cy_stc_smif_context_t const *context); static void ValueToByteArray(uint32_t value, uint8_t *byteArray, uint32_t startPos, uint32_t size); +static uint32_t ByteArrayToValue(uint8_t const *byteArray, uint32_t size); /******************************************************************************* * Function Name: Cy_SMIF_MemInit @@ -269,7 +303,10 @@ static void ValueToByteArray(uint32_t value, uint8_t *byteArray, uint32_t startP * mapped into the PSoC memory map. \ref cy_stc_smif_mem_config_t * * \param context -* The SMIF internal context structure of the block. +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. * * \return The memory slot initialization status. * - \ref CY_SMIF_SUCCESS @@ -496,7 +533,10 @@ void Cy_SMIF_MemDeInit(SMIF_Type *base) * The device to which the command is sent. * * \param context -* The internal SMIF context data. \ref cy_stc_smif_context_t +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. * * \return A status of the command transmission. * - \ref CY_SMIF_SUCCESS @@ -523,7 +563,7 @@ cy_en_smif_status_t Cy_SMIF_MemCmdWriteEnable(SMIF_Type *base, memDevice->slaveSelect, CY_SMIF_TX_LAST_BYTE, context); - } + } return result; } @@ -546,7 +586,10 @@ cy_en_smif_status_t Cy_SMIF_MemCmdWriteEnable(SMIF_Type *base, * The device to which the command is sent. * * \param context -* The internal SMIF context data. \ref cy_stc_smif_context_t +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. * * \return A status of the command transmission. * - \ref CY_SMIF_SUCCESS @@ -597,7 +640,10 @@ cy_en_smif_status_t Cy_SMIF_MemCmdWriteDisable(SMIF_Type *base, * The device to which the command is sent. * * \param context -* The internal SMIF context data. +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. * * \return A status of the memory device. * - True - The device is busy or a timeout occurs. @@ -647,7 +693,10 @@ bool Cy_SMIF_MemIsBusy(SMIF_Type *base, cy_stc_smif_mem_config_t const *memDevic * The device to which the command is sent. * * \param context -* The internal SMIF context data. +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. * * \return A status of the command. * - \ref CY_SMIF_SUCCESS @@ -750,7 +799,10 @@ cy_en_smif_status_t Cy_SMIF_MemQuadEnable(SMIF_Type *base, * The command required to read the status/configuration register. * * \param context -* The internal SMIF context data. +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. * * \return A status of the command reception. * - \ref CY_SMIF_SUCCESS @@ -809,7 +861,10 @@ cy_en_smif_status_t Cy_SMIF_MemCmdReadStatus(SMIF_Type *base, * The command to write into the status/configuration register. * * \param context -* The internal SMIF context data. \ref cy_stc_smif_context_t +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. * * \return A status of the command transmission. * - \ref CY_SMIF_SUCCESS @@ -863,7 +918,10 @@ cy_en_smif_status_t Cy_SMIF_MemCmdWriteStatus(SMIF_Type *base, * The device to which the command is sent * * \param context -* The internal SMIF context data. \ref cy_stc_smif_context_t +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. * * \return A status of the command transmission. * - \ref CY_SMIF_SUCCESS @@ -911,7 +969,10 @@ cy_en_smif_status_t Cy_SMIF_MemCmdChipErase(SMIF_Type *base, * The sector address to erase. * * \param context -* The internal SMIF context data. \ref cy_stc_smif_context_t +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. * * \return A status of the command transmission. * - \ref CY_SMIF_SUCCESS @@ -927,15 +988,21 @@ cy_en_smif_status_t Cy_SMIF_MemCmdSectorErase(SMIF_Type *base, { cy_en_smif_status_t result = CY_SMIF_BAD_PARAM; + CY_ASSERT_L1(NULL != memDevice); + if (NULL != sectorAddr) { - cy_stc_smif_mem_device_cfg_t *device = memDevice->deviceCfg; cy_stc_smif_mem_cmd_t *cmdErase = device->eraseCmd; - - if ((NULL != cmdErase) && (CY_SMIF_WIDTH_NA != cmdErase->cmdWidth)) + cy_stc_smif_hybrid_region_info_t* hybrInfo = NULL; + + result = Cy_SMIF_MemLocateHybridRegion(memDevice, &hybrInfo, + ByteArrayToValue(sectorAddr, device->numOfAddrBytes)); + + if ((NULL != cmdErase) && (CY_SMIF_WIDTH_NA != cmdErase->cmdWidth) && (result != CY_SMIF_BAD_PARAM)) { - result = Cy_SMIF_TransmitCommand( base, (uint8_t)cmdErase->command, + uint8_t eraseCommand = (uint8_t)((result == CY_SMIF_SUCCESS) ? (hybrInfo->eraseCmd) : (cmdErase->command)); + result = Cy_SMIF_TransmitCommand( base, eraseCommand, cmdErase->cmdWidth, sectorAddr, device->numOfAddrBytes, cmdErase->cmdWidth, memDevice->slaveSelect, CY_SMIF_TX_LAST_BYTE, context); @@ -987,7 +1054,10 @@ cy_en_smif_status_t Cy_SMIF_MemCmdSectorErase(SMIF_Type *base, * as no callback. * * \param context -* The internal SMIF context data. +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. * * \return A status of a transmission. * - \ref CY_SMIF_SUCCESS @@ -1092,7 +1162,10 @@ cy_en_smif_status_t Cy_SMIF_MemCmdProgram(SMIF_Type *base, * as no callback. * * \param context -* The internal SMIF context data. +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. * * \return A status of the transmission. * - \ref CY_SMIF_SUCCESS @@ -1160,6 +1233,72 @@ cy_en_smif_status_t Cy_SMIF_MemCmdRead(SMIF_Type *base, } +/******************************************************************************* +* Function Name: Cy_SMIF_MemLocateHybridRegion +****************************************************************************//** +* +* This function locates the region structure by the address which belongs to it. +* +* \note This function is valid for the memories with hybrid sectors. +* +* \param memDevice +* The memory device configuration. +* +* \param regionInfo +* Places a hybrid region configuration structure that contains the region +* specific parameters. See \ref cy_stc_smif_hybrid_region_info_t for +* reference. +* +* \param address +* The address for which a region is searched. +* +* \return A status of the region location. +* - \ref CY_SMIF_SUCCESS +* - \ref CY_SMIF_NOT_HYBRID_MEM +* - \ref CY_SMIF_BAD_PARAM +* +* \funcusage +* \snippet smif/snippet/main.c snippet_Cy_SMIF_MemLocateHybridRegion +* +*******************************************************************************/ +cy_en_smif_status_t Cy_SMIF_MemLocateHybridRegion(cy_stc_smif_mem_config_t const *memDevice, + cy_stc_smif_hybrid_region_info_t** regionInfo, + uint32_t address) +{ + cy_en_smif_status_t result = CY_SMIF_BAD_PARAM; + cy_stc_smif_hybrid_region_info_t* currInfo = NULL; + CY_ASSERT_L1(NULL != memDevice); + cy_stc_smif_mem_device_cfg_t *device = memDevice->deviceCfg; + + /* Check if the address exceeds the memory size */ + if(address <= device->memSize) + { + result = CY_SMIF_NOT_HYBRID_MEM; + /* Check if the memory is hybrid */ + if(NULL != device->hybridRegionInfo) + { + uint32_t idx; + uint32_t regionStartAddr; + uint32_t regionEndAddr; + for(idx = 0UL; idx < device->hybridRegionCount; idx++) + { + currInfo = device->hybridRegionInfo[idx]; + regionStartAddr = currInfo->regionAddress; + regionEndAddr = regionStartAddr + (currInfo->sectorsCount * currInfo->eraseSize); + if ((address >= regionStartAddr) && (address < regionEndAddr)) + { + *regionInfo = currInfo; + result = CY_SMIF_SUCCESS; + break; + } + } + } + } + + return result; +} + + /******************************************************************************* * Function Name: SfdpReadBuffer ****************************************************************************//** @@ -1192,7 +1331,10 @@ cy_en_smif_status_t Cy_SMIF_MemCmdRead(SMIF_Type *base, * The pointer to an array with the SDFP buffer. * * \param context -* Internal SMIF context data. +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. * * \return A status of the transmission. * - \ref CY_SMIF_SUCCESS @@ -1828,48 +1970,53 @@ static uint32_t SfdpGetPageSize(uint8_t const sfdpBuffer[]) * \param sfdpBuffer * The pointer to an array with the SDFP buffer. * -* \return Erase time in us. +* \param eraseTypeTime +* The pointer to an array with the erase time in us for different erase types. +* +* \return Default erase time in us. * *******************************************************************************/ -static uint32_t SfdpGetEraseTime(uint32_t const eraseOffset, uint8_t const sfdpBuffer[]) +static uint32_t SfdpGetEraseTime(uint32_t const eraseOffset, uint8_t const sfdpBuffer[], cy_stc_smif_erase_type_t eraseType[]) { /* Get the value of 10th DWORD from the JEDEC basic flash parameter table */ uint32_t readEraseTime = ((uint32_t*)sfdpBuffer)[CY_SMIF_JEDEC_BFPT_10TH_DWORD]; - uint32_t eraseTimeMax; - uint32_t eraseTimeIndex = (((eraseOffset - CY_SMIF_SFDP_BFPT_BYTE_1D) + TYPE_STEP) / TYPE_STEP); - uint32_t eraseUnits = _FLD2VAL(ERASE_T_UNITS, - (readEraseTime >> ((eraseTimeIndex - 1UL) * ERASE_T_LENGTH)) - >> ERASE_T_COUNT_OFFSET); - uint32_t eraseCount = _FLD2VAL(ERASE_T_COUNT, - (readEraseTime >> ((eraseTimeIndex - 1UL) * ERASE_T_LENGTH)) - >> ERASE_T_COUNT_OFFSET); + uint32_t eraseTimeDefaultIndex = (((eraseOffset - CY_SMIF_SFDP_BFPT_BYTE_1D) + TYPE_STEP) / TYPE_STEP); uint32_t eraseMul = _FLD2VAL(CY_SMIF_SFDP_ERASE_MUL_COUNT, readEraseTime); + uint32_t eraseUnits = 0UL; + uint32_t eraseCount = 0UL; uint32_t eraseMs = 0UL; + uint32_t eraseTypeTypicalTime; - switch (eraseUnits) - { - case CY_SMIF_SFDP_UNIT_0: - eraseMs = CY_SMIF_SFDP_ERASE_TIME_1MS; - break; - case CY_SMIF_SFDP_UNIT_1: - eraseMs = CY_SMIF_SFDP_ERASE_TIME_16MS; - break; - case CY_SMIF_SFDP_UNIT_2: - eraseMs = CY_SMIF_SFDP_ERASE_TIME_128MS; - break; - case CY_SMIF_SFDP_UNIT_3: - eraseMs = CY_SMIF_SFDP_ERASE_TIME_1S; - break; - default: - /* An unsupported SFDP value */ - break; + for (uint32_t idx = 0UL; idx < ERASE_TYPE_COUNT; idx++){ + eraseTypeTypicalTime = (readEraseTime >> (idx * ERASE_T_LENGTH))>> ERASE_T_COUNT_OFFSET; + eraseUnits = _FLD2VAL(ERASE_T_UNITS, eraseTypeTypicalTime); + eraseCount = _FLD2VAL(ERASE_T_COUNT, eraseTypeTypicalTime); + + switch (eraseUnits) + { + case CY_SMIF_SFDP_UNIT_0: + eraseMs = CY_SMIF_SFDP_ERASE_TIME_1MS; + break; + case CY_SMIF_SFDP_UNIT_1: + eraseMs = CY_SMIF_SFDP_ERASE_TIME_16MS; + break; + case CY_SMIF_SFDP_UNIT_2: + eraseMs = CY_SMIF_SFDP_ERASE_TIME_128MS; + break; + case CY_SMIF_SFDP_UNIT_3: + eraseMs = CY_SMIF_SFDP_ERASE_TIME_1S; + break; + default: + /* An unsupported SFDP value */ + break; + } + + /* Convert typical time to max time */ + eraseType[idx].eraseTime = ((eraseCount + 1UL) * eraseMs) * (2UL * (eraseMul + 1UL)); } - /* Convert typical time to max time */ - eraseTimeMax = ((eraseCount + 1UL) * eraseMs) * (2UL * (eraseMul + 1UL)); - - return(eraseTimeMax); + return(eraseType[eraseTimeDefaultIndex - 1UL].eraseTime); } @@ -2328,12 +2475,16 @@ static void SfdpSetChipEraseCommand(cy_stc_smif_mem_cmd_t* cmdChipErase) * \param sfdpBuffer * The pointer to an array with the SDFP buffer. * +* \param eraseTypeCmd +* The pointer to an array with the erase commands for different erase types. +* * \return The offset of the Sector Erase command in the SFDP buffer. * Returns 0 when the Sector Erase command is not found. * *******************************************************************************/ static uint32_t SfdpGetSectorEraseCommand(cy_stc_smif_mem_device_cfg_t *device, - uint8_t const sfdpBuffer[]) + uint8_t const sfdpBuffer[], + cy_stc_smif_erase_type_t eraseTypeStc[]) { uint32_t eraseOffset; if (FOUR_BYTE_ADDRESS == device->numOfAddrBytes) @@ -2364,6 +2515,11 @@ static uint32_t SfdpGetSectorEraseCommand(cy_stc_smif_mem_device_cfg_t *device, /* Calculate the offset for the sector Erase command in the 4-byte Address Instruction Table, DWORD 2 */ eraseOffset = FOUR_BYTE_ADDR_ERASE_TYPE_1 + eraseType; + /* Update all erase commands for 4-bytes*/ + for(uint32_t i = 0UL; i< ERASE_TYPE_COUNT; i++) + { + eraseTypeStc[i].eraseCmd = sfdpBuffer[FOUR_BYTE_ADDR_ERASE_TYPE_1 + i]; + } /* Get the sector Erase command * from the 4-byte Address Instruction Table, DWORD 2 */ @@ -2413,6 +2569,371 @@ static uint32_t SfdpGetSectorEraseCommand(cy_stc_smif_mem_device_cfg_t *device, } +/******************************************************************************* +* Function Name: ReadAnyReg +****************************************************************************//** +* +* This function reads any registers by address. This function is a blocking +* function, it will block the execution flow until the status register is read. +* +* \param base +* Holds the base address of the SMIF block registers. +* +* \param slaveSelect +* The slave select line for the device. +* +* \param value +* The value of the register. +* +* \param command +* The command required to read the status/configuration register. +* +* \param address +* The register address array. +* +* \param addressSize +* The size of the address array. +* +* \param context +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. +* +* \return A status of the command reception. +* - \ref CY_SMIF_SUCCESS +* - \ref CY_SMIF_CMD_FIFO_FULL +* - \ref CY_SMIF_EXCEED_TIMEOUT +* - \ref CY_SMIF_CMD_NOT_FOUND +* +*******************************************************************************/ +static cy_en_smif_status_t ReadAnyReg(SMIF_Type *base, + cy_en_smif_slave_select_t slaveSelect, + uint8_t *value, + uint8_t command, + uint8_t const *address, + uint32_t addressSize, + cy_stc_smif_context_t const *context) +{ + cy_en_smif_status_t result = CY_SMIF_CMD_NOT_FOUND; + + /* Read the memory register */ + result = Cy_SMIF_TransmitCommand(base, command, CY_SMIF_WIDTH_SINGLE, + address, addressSize, + CY_SMIF_WIDTH_SINGLE, slaveSelect, + CY_SMIF_TX_NOT_LAST_BYTE, context); + + if (CY_SMIF_SUCCESS == result) + { + result = Cy_SMIF_ReceiveDataBlocking( base, value, + CY_SMIF_READ_ONE_BYTE, CY_SMIF_WIDTH_SINGLE, context); + } + + return(result); +} + + +/******************************************************************************* +* Function Name: SfdpEnterFourByteAddressing +****************************************************************************//** +* +* This function sets 4-byte address mode for a memory device as defined in +* 16th DWORD of JEDEC Basic Flash Parameter Table. +* +* \note The entry methods which do not support the required +* operation of writing into the register. +* +* \param base +* Holds the base address of the SMIF block registers. +* +* \param entryMethodByte +* The byte which defines the supported method to enter 4-byte addressing mode. +* +* \param device +* The device structure instance declared by the user. This is where the detected +* parameters are stored and returned. +* +* \param slaveSelect +* The slave select line for the device. +* +* \param context +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. +* +* \return A status of 4-byte addressing mode command transmit. +* - \ref CY_SMIF_SUCCESS +* - \ref CY_SMIF_EXCEED_TIMEOUT +* - \ref CY_SMIF_CMD_NOT_FOUND +*******************************************************************************/ +static cy_en_smif_status_t SfdpEnterFourByteAddressing(SMIF_Type *base, uint8_t entryMethodByte, + cy_stc_smif_mem_device_cfg_t *device, + cy_en_smif_slave_select_t slaveSelect, + cy_stc_smif_context_t const *context) +{ + cy_en_smif_status_t result = CY_SMIF_CMD_NOT_FOUND; + if ((entryMethodByte & CY_SMIF_SFDP_ENTER_4_BYTE_METHOD_ALWAYS_4_BYTE) != 0U) + { + /* Memory always operates in 4-byte mode */ + result = CY_SMIF_SUCCESS; + } + if ((entryMethodByte & CY_SMIF_SFDP_ENTER_4_BYTE_METHOD_B7) != 0U) + { + if ((entryMethodByte & CY_SMIF_SFDP_ENTER_4_BYTE_METHOD_WR_EN_B7) != 0U) + { + /* To enter a 4-byte addressing write enable is required */ + cy_stc_smif_mem_cmd_t* writeEn = device->writeEnCmd; + if(NULL != writeEn) + { + result = Cy_SMIF_TransmitCommand(base, + (uint8_t) writeEn->command, + writeEn->cmdWidth, + CY_SMIF_CMD_WITHOUT_PARAM, + CY_SMIF_CMD_WITHOUT_PARAM, + CY_SMIF_WIDTH_NA, + slaveSelect, + CY_SMIF_TX_LAST_BYTE, + context); + } + } + if ((CY_SMIF_CMD_NOT_FOUND == result) || (CY_SMIF_SUCCESS == result)) + { + /* To enter a 4-byte addressing B7 instruction is required*/ + result = Cy_SMIF_TransmitCommand(base, + CY_SMIF_SFDP_ENTER_4_BYTE_METHOD_B7_CMD, + CY_SMIF_WIDTH_SINGLE, + CY_SMIF_CMD_WITHOUT_PARAM, + CY_SMIF_CMD_WITHOUT_PARAM, + CY_SMIF_WIDTH_NA, + slaveSelect, + CY_SMIF_TX_LAST_BYTE, + context); + } + } + + return result; +} + + +/******************************************************************************* +* Function Name: SfdpGetEraseSizeAndCmd +****************************************************************************//** +* +* Fills arrays with an erase size and cmd for all erase types. +* +* \param sfdpBuffer +* The pointer to an array with the Basic Flash Parameter table buffer. +* +* \param eraseTypeCmd +* The pointer to an array with the erase commands for all erase types. +* +* \param eraseTypeSize +* The pointer to an array with the erase size for all erase types. +* +*******************************************************************************/ +static void SfdpGetEraseSizeAndCmd(uint8_t const sfdpBuffer[], + cy_stc_smif_erase_type_t eraseType[]) +{ + uint32_t idx = 0UL; + for (uint32_t currET = 0UL; currET < ERASE_TYPE_COUNT; currET++) + { + /* The erase size in the SFDP buffer defined as power of two */ + eraseType[currET].eraseSize = 1UL << sfdpBuffer[CY_SMIF_SFDP_BFPT_BYTE_1C + idx]; + eraseType[currET].eraseCmd = sfdpBuffer[CY_SMIF_SFDP_BFPT_BYTE_1D + idx]; + idx += TYPE_STEP; + } +} + + +/******************************************************************************* +* Function Name: SfdpPopulateRegionInfo +****************************************************************************//** +* +* Reads the current configuration for regions and populates regionInfo +* structures. +* +* \param base +* Holds the base address of the SMIF block registers. +* +* \param sectorMapBuff +* The pointer to an array with the Sector Map Parameter Table buffer. +* +* \param device +* The device structure instance declared by the user. This is where the detected +* parameters are stored and returned. +* +* \param slaveSelect +* The slave select line for the device. +* +* \param context +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. +* +* \param eraseTypeSize +* The pointer to an array with the erase size for all erase types. +* +* \param eraseTypeCmd +* The pointer to an array with the erase commands for all erase types. +* +* \param eraseTypeTime +* The pointer to an array with the erase time for all erase types. +* +* \return A status of the Sector Map Parameter Table parsing. +* - \ref CY_SMIF_SUCCESS +* - \ref CY_SMIF_SFDP_CORRUPTED_TABLE +* - \ref CY_SMIF_NOT_HYBRID_MEM +* +*******************************************************************************/ +static cy_en_smif_status_t SfdpPopulateRegionInfo(SMIF_Type *base, + uint8_t const sectorMapBuff[], + uint32_t const buffLength, + cy_stc_smif_mem_device_cfg_t *device, + cy_en_smif_slave_select_t slaveSelect, + const cy_stc_smif_context_t *context, + cy_stc_smif_erase_type_t eraseType[]) +{ + uint8_t currCmd; + uint8_t regMask; + uint8_t regValue; + uint8_t currRegisterAddr[ERASE_TYPE_COUNT] = {0U}; + uint8_t regionInfoIdx = 0U; + uint32_t currTableIdx = 0UL; + uint32_t addrBytesNum = 0UL; + uint32_t addrCode = 0UL; + cy_en_smif_status_t result = CY_SMIF_NOT_HYBRID_MEM; + + /* Loop across all command descriptors to find current configuration */ + while(SECTOR_MAP_COMAND_DESCRIPTOR_TYPE == (sectorMapBuff[currTableIdx] & SECTOR_MAP_DESCRIPTOR_MASK)) + { + currCmd = sectorMapBuff[currTableIdx + CY_SMIF_SFDP_SECTOR_MAP_CMD_OFFSET]; + regMask = sectorMapBuff[currTableIdx + CY_SMIF_SFDP_SECTOR_MAP_REG_MSK_OFFSET]; + regValue = 0U; + + /* Get the address length for configuration detection */ + addrCode = _FLD2VAL(CY_SMIF_SFDP_SECTOR_MAP_ADDR_BYTES, sectorMapBuff[currTableIdx + CY_SMIF_SFDP_SECTOR_MAP_ADDR_CODE_OFFSET]); + switch(addrCode) + { + case CY_SMIF_SFDP_THREE_BYTES_ADDR_CODE: + /* No address cycle */ + addrBytesNum = 0UL; + break; + case CY_SMIF_SFDP_THREE_OR_FOUR_BYTES_ADDR_CODE: + addrBytesNum = CY_SMIF_THREE_BYTES_ADDR; + break; + case CY_SMIF_SFDP_FOUR_BYTES_ADDR_CODE: + addrBytesNum = CY_SMIF_FOUR_BYTES_ADDR; + break; + default: + /* Use the current settings */ + addrBytesNum = device->numOfAddrBytes; + break; + } + + /* Get the control register address */ + for(uint32_t i = 0UL; i < addrBytesNum; i++) + { + /* Offset for control register in SFDP has little-endian byte order, need to swap it */ + currRegisterAddr[i] = sectorMapBuff[(currTableIdx + CY_SMIF_SFDP_SECTOR_MAP_REG_ADDR_OFFSET + addrBytesNum) - i - 1UL]; + } + + /* Read the value of the register for the current configuration detection*/ + result = ReadAnyReg(base, slaveSelect, ®Value, currCmd, &currRegisterAddr[0], addrBytesNum, context); + + if (CY_SMIF_SUCCESS == result) + { + /* Set the bit of the region idx to 1 if the config matches */ + regionInfoIdx = ((uint8_t)(regionInfoIdx << 1U)) | (((regValue & regMask) == 0U)?(0U):(1U)); + } + + currTableIdx += HEADER_LENGTH; + if (currTableIdx > buffLength) + { + result = CY_SMIF_SFDP_CORRUPTED_TABLE; + break; + } + } + + if (CY_SMIF_SUCCESS == result) + { + /* Find the matching configuration map descriptor */ + while(regionInfoIdx != sectorMapBuff[currTableIdx + 1UL]) + { + /* Increment the table index to the next map */ + currTableIdx += (sectorMapBuff[currTableIdx + CY_SMIF_SFDP_SECTOR_MAP_CONFIG_ID_OFFSET] + 2UL) * BYTES_IN_DWORD; + if (currTableIdx > buffLength) + { + result = CY_SMIF_SFDP_CORRUPTED_TABLE; + break; + } + } + } + + if (CY_SMIF_SUCCESS == result) + { + /* Populate region data from the sector map */ + uint8_t numOfRegions = sectorMapBuff[currTableIdx + CY_SMIF_SFDP_SECTOR_MAP_REGION_COUNT_OFFSET] + 1U; + device->hybridRegionCount = (uint32_t) numOfRegions; + + if(numOfRegions <= 1U) + { + result = CY_SMIF_NOT_HYBRID_MEM; + } + else + { + uint8_t eraseTypeCode; + uint32_t currRegionAddr = 0UL; + uint32_t regionSize = 0UL; + uint8_t supportedEraseType; + uint8_t eraseTypeMask; + cy_stc_smif_hybrid_region_info_t *currRegionPtr; + for(uint8_t currRegion = 0U; currRegion< numOfRegions; currRegion++) + { + currRegionAddr = currRegionAddr + regionSize; + currTableIdx += BYTES_IN_DWORD; + + supportedEraseType = 0U; + eraseTypeMask = 1U; + eraseTypeCode = sectorMapBuff[currTableIdx] & CY_SMIF_SFDP_SECTOR_MAP_SUPPORTED_ET_MASK; + while(0U == (eraseTypeCode & eraseTypeMask)) + { + /* Erase type number defined as a bit position */ + eraseTypeMask = eraseTypeMask << 1; + supportedEraseType++; + if(supportedEraseType > ERASE_TYPE_COUNT) + { + result = CY_SMIF_SFDP_CORRUPTED_TABLE; + break; + } + } + + /* The region size as a zero-based count of 256 byte units */ + regionSize = ((*( (uint32_t*) §orMapBuff[currTableIdx]) >> BITS_IN_BYTE) + 1UL) * SECTOR_MAP_REGION_SIZE_MULTIPLIER; + currRegionPtr = device->hybridRegionInfo[currRegion]; + + currRegionPtr->regionAddress = currRegionAddr; + currRegionPtr->eraseCmd = (uint32_t)eraseType[supportedEraseType].eraseCmd; + currRegionPtr->eraseTime = eraseType[supportedEraseType].eraseTime; + if(regionSize < eraseType[supportedEraseType].eraseSize) + { + /* One region with a single sector */ + currRegionPtr->eraseSize = regionSize; + currRegionPtr->sectorsCount = 1UL; + } + else + { + currRegionPtr->eraseSize = eraseType[supportedEraseType].eraseSize; + currRegionPtr->sectorsCount = regionSize / eraseType[supportedEraseType].eraseSize; + } + } + } + } + return result; +} + + /******************************************************************************* * Function Name: Cy_SMIF_MemSfdpDetect ****************************************************************************//** @@ -2457,7 +2978,10 @@ static uint32_t SfdpGetSectorEraseCommand(cy_stc_smif_mem_device_cfg_t *device, * The data line selection options for a slave device. * * \param context -* Internal SMIF context data. +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. * * \return A status of the transmission. * - \ref CY_SMIF_SUCCESS @@ -2478,8 +3002,10 @@ cy_en_smif_status_t Cy_SMIF_MemSfdpDetect(SMIF_Type *base, uint8_t sfdpBuffer[CY_SMIF_SFDP_LENGTH]; uint8_t sfdpAddress[CY_SMIF_SFDP_ADDRESS_LENGTH] = {0x00U, 0x00U, 0x00U}; uint8_t addr4ByteAddress[CY_SMIF_SFDP_ADDRESS_LENGTH] = {0x00U, 0x00U, 0x00U}; + uint8_t sectorMapAddr[CY_SMIF_SFDP_ADDRESS_LENGTH] = {0x00U, 0x00U, 0x00U}; cy_en_smif_status_t result = CY_SMIF_NO_SFDP_SUPPORT; cy_stc_smif_mem_cmd_t *cmdSfdp = device->readSfdpCmd; + cy_stc_smif_erase_type_t eraseType[ERASE_TYPE_COUNT]; /* Initialize the SFDP buffer */ for (uint32_t i = 0U; i < CY_SMIF_SFDP_LENGTH; i++) @@ -2522,11 +3048,21 @@ cy_en_smif_status_t Cy_SMIF_MemSfdpDetect(SMIF_Type *base, uint32_t id = (FOUR_BYTE_ADDR_ID_MSB << BITS_IN_BYTE) | FOUR_BYTE_ADDR_ID_LSB; uint32_t addr4ByteTableLength = 0UL; result = SfdpFindParameterTableAddress(id, sfdpBuffer, addr4ByteAddress, &addr4ByteTableLength); - + + /* Find the Sector Map Parameter Header */ + id = (SECTOR_MAP_ID_MSB << BITS_IN_BYTE) | SECTOR_MAP_ID_LSB; + uint32_t sectorMapTableLength = 0UL; + result = SfdpFindParameterTableAddress(id, sfdpBuffer, sectorMapAddr, §orMapTableLength); + if (CY_SMIF_CMD_NOT_FOUND == result) + { + device->hybridRegionCount = 0UL; + device->hybridRegionInfo = NULL; + } + /* Find the JEDEC SFDP Basic SPI Flash Parameter Header */ id = (BASIC_SPI_ID_MSB << BITS_IN_BYTE) | BASIC_SPI_ID_LSB; uint32_t basicSpiTableLength = 0UL; - result = SfdpFindParameterTableAddress(id, sfdpBuffer, sfdpAddress, &basicSpiTableLength); + result = SfdpFindParameterTableAddress(id, sfdpBuffer, sfdpAddress, &basicSpiTableLength); if (CY_SMIF_SUCCESS == result) { @@ -2536,10 +3072,10 @@ cy_en_smif_status_t Cy_SMIF_MemSfdpDetect(SMIF_Type *base, CY_ASSERT_L1(NULL != device->eraseCmd); CY_ASSERT_L1(NULL != device->chipEraseCmd); CY_ASSERT_L1(NULL != device->programCmd); - CY_ASSERT_L1(NULL != device->readStsRegWipCmd); + CY_ASSERT_L1(NULL != device->readStsRegWipCmd); /* Get the JEDEC basic flash parameter table content into sfdpBuffer[] */ - result = SfdpReadBuffer(base, + result = SfdpReadBuffer(base, cmdSfdp, sfdpAddress, slaveSelect, @@ -2547,24 +3083,27 @@ cy_en_smif_status_t Cy_SMIF_MemSfdpDetect(SMIF_Type *base, sfdpBuffer, context); + /* The erase size and erase time for all 4 erase types */ + SfdpGetEraseSizeAndCmd(sfdpBuffer, eraseType); + /* The number of address bytes used by the memory slave device */ device->numOfAddrBytes = SfdpGetNumOfAddrBytes(sfdpBuffer); /* The external memory size */ device->memSize = SfdpGetMemoryDensity(sfdpBuffer); - + /* The page size */ device->programSize = SfdpGetPageSize(sfdpBuffer); /* The Write Enable command */ - SfdpSetWriteEnableCommand(device->writeEnCmd); + SfdpSetWriteEnableCommand(device->writeEnCmd); /* The Write Disable command */ SfdpSetWriteDisableCommand(device->writeDisCmd); /* The busy mask for the status registers */ device->stsRegBusyMask = CY_SMIF_STATUS_REG_BUSY_MASK; - + /* The command to read the WIP-containing status register */ SfdpSetWipStatusRegisterCommand(device->readStsRegWipCmd); @@ -2573,13 +3112,13 @@ cy_en_smif_status_t Cy_SMIF_MemSfdpDetect(SMIF_Type *base, /* Chip Erase command */ SfdpSetChipEraseCommand(device->chipEraseCmd); - + /* Chip Erase Time */ device->chipEraseTime = SfdpGetChipEraseTime(sfdpBuffer); /* Page Program Time */ device->programTime = SfdpGetPageProgramTime(sfdpBuffer); - + /* The Read command for 3-byte addressing. The preference order quad > dual > single SPI */ cy_stc_smif_mem_cmd_t *cmdRead = device->readCmd; cy_en_smif_protocol_mode_t pMode = SfdpGetReadCmdParams(sfdpBuffer, dataSelect, cmdRead); @@ -2588,11 +3127,15 @@ cy_en_smif_status_t Cy_SMIF_MemSfdpDetect(SMIF_Type *base, uint32_t eraseTypeOffset = 1UL; if (FOUR_BYTE_ADDRESS == device->numOfAddrBytes) { - /* Get the JEDEC 4-byte Address Instruction Table content into sfdpBuffer[] */ + /* Enter 4-byte addressing mode */ + result = SfdpEnterFourByteAddressing(base, sfdpBuffer[CY_SMIF_SFDP_BFPT_BYTE_3C], device, slaveSelect, context); uint8_t fourByteAddressBuffer[CY_SMIF_SFDP_LENGTH]; - result = SfdpReadBuffer(base, cmdSfdp, addr4ByteAddress, slaveSelect, - addr4ByteTableLength, fourByteAddressBuffer, context); - + if (CY_SMIF_SUCCESS == result) + { + /* Get the JEDEC 4-byte Address Instruction Table content into sfdpBuffer[] */ + result = SfdpReadBuffer(base, cmdSfdp, addr4ByteAddress, slaveSelect, + addr4ByteTableLength, fourByteAddressBuffer, context); + } if (CY_SMIF_SUCCESS == result) { /* Rewrite the Read command instruction for 4-byte addressing mode */ @@ -2601,8 +3144,8 @@ cy_en_smif_status_t Cy_SMIF_MemSfdpDetect(SMIF_Type *base, /* Get the Program command instruction for 4-byte addressing mode */ SfdpGetProgramFourBytesCmd(fourByteAddressBuffer, pMode, device->programCmd); - /* Find the sector Erase command type with 4-byte addressing */ - eraseTypeOffset = SfdpGetSectorEraseCommand(device, fourByteAddressBuffer); + /* Find the sector Erase command type with 4-byte addressing */ + eraseTypeOffset = SfdpGetSectorEraseCommand(device, fourByteAddressBuffer, eraseType); } } else @@ -2611,7 +3154,7 @@ cy_en_smif_status_t Cy_SMIF_MemSfdpDetect(SMIF_Type *base, SfdpSetProgramCommand_1_1_1(device->programCmd); /* Find the sector Erase command type with 3-byte addressing */ - eraseTypeOffset = SfdpGetSectorEraseCommand(device, sfdpBuffer); + eraseTypeOffset = SfdpGetSectorEraseCommand(device, sfdpBuffer, eraseType); } if (COMMAND_IS_NOT_FOUND != eraseTypeOffset) @@ -2620,7 +3163,24 @@ cy_en_smif_status_t Cy_SMIF_MemSfdpDetect(SMIF_Type *base, device->eraseSize = 0x01UL << sfdpBuffer[eraseTypeOffset - 1UL]; /* Erase Time Type (from the JEDEC basic flash parameter table) */ - device->eraseTime = SfdpGetEraseTime(eraseTypeOffset, sfdpBuffer); + device->eraseTime = SfdpGetEraseTime(eraseTypeOffset, sfdpBuffer, eraseType); + } + + if (NULL != device->hybridRegionInfo) + { + /* Get the Sector Map Parameter Table into sfdpBuffer[] */ + result = SfdpReadBuffer(base, cmdSfdp, sectorMapAddr, slaveSelect, + sectorMapTableLength, sfdpBuffer, context); + if (CY_SMIF_SUCCESS == result) + { + result = SfdpPopulateRegionInfo(base, sfdpBuffer, sectorMapTableLength, device, slaveSelect, context, eraseType); + if(result == CY_SMIF_NOT_HYBRID_MEM) + { + device->hybridRegionCount = 0UL; + device->hybridRegionInfo = NULL; + result = CY_SMIF_SUCCESS; + } + } } } } @@ -2653,8 +3213,10 @@ cy_en_smif_status_t Cy_SMIF_MemSfdpDetect(SMIF_Type *base, * The timeout value in microseconds to apply while polling the memory. * * \param context -* Passes a configuration structure that contains the transfer parameters of the -* SMIF block. +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. * * \return The status of the operation. * \ref CY_SMIF_SUCCESS - Memory is ready to accept new commands. @@ -2721,8 +3283,10 @@ cy_en_smif_status_t Cy_SMIF_MemIsReady(SMIF_Type *base, cy_stc_smif_mem_config_t * CY_SMIF_SUCCESS. * * \param context -* Passes a configuration structure that contains the transfer parameters of the -* SMIF block. +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. * * \return The status of the operation. See \ref cy_en_smif_status_t. * @@ -2771,8 +3335,10 @@ cy_en_smif_status_t Cy_SMIF_MemIsQuadEnabled(SMIF_Type *base, cy_stc_smif_mem_co * The timeout value in microseconds to apply while polling the memory. * * \param context -* Passes a configuration structure that contains the transfer parameters of the -* SMIF block. +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. * * \return The status of the operation. See \ref cy_en_smif_status_t. * @@ -2821,8 +3387,10 @@ cy_en_smif_status_t Cy_SMIF_MemEnableQuadMode(SMIF_Type *base, cy_stc_smif_mem_c * Transfer status value to be checked. * * \param context -* Passes a configuration structure that contains the transfer parameters of the -* SMIF block. +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. * * \return The status of the operation. * \ref CY_SMIF_SUCCESS - SMIF block has completed the transfer @@ -2881,6 +3449,36 @@ static void ValueToByteArray(uint32_t value, uint8_t *byteArray, uint32_t startP } +/******************************************************************************* +* Function Name: ByteArrayToValue +****************************************************************************//** +* +* Packs the byte array into a single value. +* +* \param byteArray +* The byte array to unpack. +* +* \param size +* The size of the array. +* +* \return +* The 4-byte value filled from the array. +* +* +*******************************************************************************/ +static uint32_t ByteArrayToValue(uint8_t const *byteArray, uint32_t size) +{ + uint32_t value = 0UL; + uint32_t idx = 0UL; + for (idx = 0UL; idx < size; idx++) + { + value <<= 8; + value |= ((uint32_t) byteArray[idx]); + } + return value; +} + + /******************************************************************************* * Function Name: Cy_SMIF_MemRead ****************************************************************************//** @@ -2906,8 +3504,10 @@ static void ValueToByteArray(uint32_t value, uint8_t *byteArray, uint32_t startP * The size of data to read. * * \param context -* Passes a configuration structure that contains the transfer parameters of the -* SMIF block. +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. * * \return The status of the operation. See \ref cy_en_smif_status_t. * @@ -2986,8 +3586,10 @@ cy_en_smif_status_t Cy_SMIF_MemRead(SMIF_Type *base, cy_stc_smif_mem_config_t co * The size of data to write. * * \param context -* Passes a configuration structure that contains the transfer parameters of the -* SMIF block. +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. * * \return The status of the operation. See \ref cy_en_smif_status_t. * @@ -3084,67 +3686,120 @@ cy_en_smif_status_t Cy_SMIF_MemWrite(SMIF_Type *base, cy_stc_smif_mem_config_t c * The size of data to erase. * * \param context -* Passes a configuration structure that contains the transfer parameters of the -* SMIF block. +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. * * \return The status of the operation. See \ref cy_en_smif_status_t. * +* \note The address should be aligned with the start address of the sector. \n +* The length should be equal to the sum of all erased sectors. +* * \funcusage * \snippet smif/snippet/main.c snippet_Cy_SMIF_MemEraseSector * *******************************************************************************/ -cy_en_smif_status_t Cy_SMIF_MemEraseSector(SMIF_Type *base, cy_stc_smif_mem_config_t const *memConfig, - uint32_t address, uint32_t length, +cy_en_smif_status_t Cy_SMIF_MemEraseSector(SMIF_Type *base, cy_stc_smif_mem_config_t const *memConfig, + uint32_t address, uint32_t length, cy_stc_smif_context_t const *context) { cy_en_smif_status_t status = CY_SMIF_BAD_PARAM; - uint32_t offset = 0UL; - uint32_t chunk = 0UL; + uint32_t endAddress = address + length; + uint32_t eraseEnd = 0UL; + uint32_t hybridRegionStart = 0UL; uint8_t addrArray[CY_SMIF_FOUR_BYTES_ADDR] = {0U}; + cy_stc_smif_hybrid_region_info_t* hybrInfo = NULL; CY_ASSERT_L1(NULL != memConfig); - uint32_t eraseSectorSize = memConfig->deviceCfg->eraseSize; + cy_stc_smif_mem_device_cfg_t *device = memConfig->deviceCfg; + uint32_t eraseSectorSize = device->eraseSize; + uint32_t maxEraseTime = device->eraseTime; - if(((address + length) <= memConfig->deviceCfg->memSize) && /* Check if the address exceeds the memory size */ - (0UL == (address % eraseSectorSize)) && /* Check if the start address and the sector size are aligned */ - (0UL == ((address + length) % eraseSectorSize))) /* Check if the end address and the sector size are aligned */ + /* In case of hybrid memory - update sector size and offset for first sector */ + status = Cy_SMIF_MemLocateHybridRegion(memConfig, &hybrInfo, address); + if (CY_SMIF_SUCCESS == status) { - while(length > 0UL) - { - /* Get the number of bytes which can be erase during one operation */ - offset = address % eraseSectorSize; - chunk = ((offset + length) < eraseSectorSize) ? length : (eraseSectorSize - offset); + hybridRegionStart = hybrInfo->regionAddress; + eraseSectorSize = hybrInfo->eraseSize; + eraseEnd = (hybrInfo->sectorsCount * eraseSectorSize) + hybridRegionStart; + } - /* The Write Enable bit may be cleared by the memory after every successful - * operation of write/erase operations. Therefore, it must be set for - * every loop. - */ - status = Cy_SMIF_MemCmdWriteEnable(base, memConfig, context); + /* Check if the end address not equal to start address */ + if(length == 0UL) + { + status = CY_SMIF_BAD_PARAM; + } - if(CY_SMIF_SUCCESS == status) + /* Check if the start address and the sector size are aligned */ + if((0UL == ((address - hybridRegionStart) % eraseSectorSize)) && (status != CY_SMIF_BAD_PARAM)) + { + /* If the memory is hybrid and there is more than one region to + * erase - update the sector size and offset for the last sector */ + if(endAddress < eraseEnd) + { + status = Cy_SMIF_MemLocateHybridRegion(memConfig, &hybrInfo, (endAddress - 1UL)); + if (CY_SMIF_SUCCESS == status) { - ValueToByteArray(address, &addrArray[0], 0UL, - memConfig->deviceCfg->numOfAddrBytes); + hybridRegionStart = hybrInfo->regionAddress; + eraseSectorSize = hybrInfo->eraseSize; + } + } - /* Send the command to erase one sector */ - status = Cy_SMIF_MemCmdSectorErase(base, (cy_stc_smif_mem_config_t* )memConfig, - (const uint8_t *)addrArray, context); + /* Check if the end address and the sector size are aligned */ + if((0UL == ((endAddress - hybridRegionStart) % eraseSectorSize)) && (status != CY_SMIF_BAD_PARAM)) + { + while(length > 0UL) + { + /* In case of hybrid memory - update erase size and time for current region */ + status = Cy_SMIF_MemLocateHybridRegion(memConfig, &hybrInfo, address); + if (CY_SMIF_SUCCESS == status) + { + maxEraseTime = hybrInfo->eraseTime; + eraseSectorSize = hybrInfo->eraseSize; + hybridRegionStart = hybrInfo->regionAddress; + eraseEnd = (hybrInfo->sectorsCount * eraseSectorSize) + hybridRegionStart; + if(endAddress < eraseEnd) + { + eraseEnd = endAddress; + } + } + else + { + eraseEnd = endAddress; + } - if(CY_SMIF_SUCCESS == status) + while (address < eraseEnd) { - /* Wait until the erase operation is completed or a timeout occurs. eraseTime is in milliseconds */ - status = Cy_SMIF_MemIsReady(base, memConfig, - (memConfig->deviceCfg->eraseTime * ONE_MILLI_IN_MICRO), context); + /* The Write Enable bit may be cleared by the memory after every successful + * operation of write/erase operations. Therefore, it must be set for + * every loop. + */ + status = Cy_SMIF_MemCmdWriteEnable(base, memConfig, context); + if(CY_SMIF_SUCCESS == status) + { + ValueToByteArray(address, &addrArray[0], 0UL, device->numOfAddrBytes); + + /* Send the command to erase one sector */ + status = Cy_SMIF_MemCmdSectorErase(base, (cy_stc_smif_mem_config_t* )memConfig, + (const uint8_t *)addrArray, context); + if(CY_SMIF_SUCCESS == status) + { + /* Wait until the erase operation is completed or a timeout occurs. + * Note: eraseTime is in milliseconds */ + status = Cy_SMIF_MemIsReady(base, memConfig, (maxEraseTime * ONE_MILLI_IN_MICRO), context); - /* Recalculate the next sector address offset */ - address += chunk; - length -= chunk; + /* Recalculate the next sector address offset */ + address += eraseSectorSize; + length -= eraseSectorSize; + } + } + + if(CY_SMIF_SUCCESS != status) + { + break; + } } } - - if(CY_SMIF_SUCCESS != status) - { - break; - } } } @@ -3167,8 +3822,10 @@ cy_en_smif_status_t Cy_SMIF_MemEraseSector(SMIF_Type *base, cy_stc_smif_mem_conf * The memory device configuration. * * \param context -* Passes a configuration structure that contains the transfer parameters of the -* SMIF block. +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. * * \return The status of the operation. See \ref cy_en_smif_status_t. * diff --git a/drivers/source/cy_sysclk.c b/drivers/source/cy_sysclk.c index 7368814..e1c6b4d 100644 --- a/drivers/source/cy_sysclk.c +++ b/drivers/source/cy_sysclk.c @@ -1,12 +1,12 @@ /***************************************************************************//** * \file cy_sysclk.c -* \version 1.50 +* \version 1.60 * * Provides an API implementation of the sysclk driver. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -63,6 +63,25 @@ void Cy_SysClk_ExtClkSetFrequency(uint32_t freq) extFreq = freq; } } + + +/******************************************************************************* +* Function Name: Cy_SysClk_ExtClkGetFrequency +****************************************************************************//** +* +* Returns the frequency of the External Clock Source (EXTCLK) from the +* internal storage. +* +* \return The frequency of the External Clock Source. +* +* \funcusage +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ExtClkSetFrequency +* +*******************************************************************************/ +uint32_t Cy_SysClk_ExtClkGetFrequency(void) +{ + return (extFreq); +} /** \} group_sysclk_ext_funcs */ @@ -280,6 +299,27 @@ cy_en_sysclk_status_t Cy_SysClk_EcoEnable(uint32_t timeoutus) return (retVal); } + + +/******************************************************************************* +* Function Name: Cy_SysClk_EcoGetFrequency +****************************************************************************//** +* +* Returns the frequency of the external crystal oscillator (ECO). +* +* \return The frequency of the ECO. +* +* \note If the ECO is not enabled or stable - a zero is returned. +* +* \funcusage +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_EcoEnable +* +*******************************************************************************/ +uint32_t Cy_SysClk_EcoGetFrequency(void) +{ + return ((CY_SYSCLK_ECOSTAT_STABLE == Cy_SysClk_EcoGetStatus()) ? ecoFreq : 0UL); +} + /** \} group_sysclk_eco_funcs */ @@ -372,6 +412,131 @@ cy_en_clkpath_in_sources_t Cy_SysClk_ClkPathGetSource(uint32_t clkPath) } return (retVal); } + + +/******************************************************************************* +* Function Name: Cy_SysClk_ClkPathMuxGetFrequency +****************************************************************************//** +* +* Returns the output frequency of the clock path mux. +* +* \return The output frequency of the path mux. +* +* \note If the return value equals zero, that means either: +* - the selected path mux source signal frequency is unknown (e.g. dsi_out, etc.) or +* - the selected path mux source is not configured/enabled/stable (e.g. ECO, EXTCLK, etc.). +* +* \funcusage +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPathSetSource +* +*******************************************************************************/ +uint32_t Cy_SysClk_ClkPathMuxGetFrequency(uint32_t clkPath) +{ + CY_ASSERT_L1(clkPath < CY_SRSS_NUM_CLKPATH); + + uint32_t freq = 0UL; /* The path mux output frequency in Hz, 0 = an unknown frequency */ + + /* Get the frequency of the source, i.e., the path mux input */ + switch(Cy_SysClk_ClkPathGetSource(clkPath)) + { + case CY_SYSCLK_CLKPATH_IN_IMO: /* The IMO frequency is fixed at 8 MHz */ + freq = CY_SYSCLK_IMO_FREQ; + break; + + case CY_SYSCLK_CLKPATH_IN_EXT: + freq = Cy_SysClk_ExtClkGetFrequency(); + break; + + case CY_SYSCLK_CLKPATH_IN_ECO: + freq = Cy_SysClk_EcoGetFrequency(); + break; + + case CY_SYSCLK_CLKPATH_IN_ALTHF: + freq = Cy_SysClk_AltHfGetFrequency(); + break; + + case CY_SYSCLK_CLKPATH_IN_ILO: + freq = (0UL != (SRSS_CLK_ILO_CONFIG & SRSS_CLK_ILO_CONFIG_ENABLE_Msk)) ? CY_SYSCLK_ILO_FREQ : 0UL; + break; + + case CY_SYSCLK_CLKPATH_IN_WCO: + freq = (Cy_SysClk_WcoOkay()) ? CY_SYSCLK_WCO_FREQ : 0UL; + break; + + case CY_SYSCLK_CLKPATH_IN_PILO: + freq = (0UL != (SRSS_CLK_PILO_CONFIG & SRSS_CLK_PILO_CONFIG_PILO_EN_Msk)) ? CY_SYSCLK_PILO_FREQ : 0UL; + break; + + case CY_SYSCLK_CLKPATH_IN_ALTLF: + freq = Cy_SysClk_AltLfGetFrequency(); + break; + + default: + /* Don't know the frequency of dsi_out, leave freq = 0UL */ + break; + } + + return (freq); +} + + +/******************************************************************************* +* Function Name: Cy_SysClk_ClkPathGetFrequency +****************************************************************************//** +* +* Returns the output frequency of the clock path mux. +* +* \return The output frequency of the path mux. +* +* \note If the return value equals zero, that means either: +* - the selected path mux source signal frequency is unknown (e.g. dsi_out, etc.) or +* - the selected path mux source is not configured/enabled/stable (e.g. ECO, EXTCLK, etc.). +* +* \funcusage +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_FllEnable +* +*******************************************************************************/ +uint32_t Cy_SysClk_ClkPathGetFrequency(uint32_t clkPath) +{ + CY_ASSERT_L1(clkPath < CY_SRSS_NUM_CLKPATH); + + uint32_t freq = Cy_SysClk_ClkPathMuxGetFrequency(clkPath); + uint32_t fDiv = 0UL; /* FLL/PLL multiplier/feedback divider */ + uint32_t rDiv = 0UL; /* FLL/PLL reference divider */ + uint32_t oDiv = 0UL; /* FLL/PLL output divider */ + bool enabled = false; /* FLL or PLL enable status; n/a for direct */ + + if (clkPath == (uint32_t)CY_SYSCLK_CLKHF_IN_CLKPATH0) /* FLL? (always path 0) */ + { + cy_stc_fll_manual_config_t fllCfg = {0UL,0U,CY_SYSCLK_FLL_CCO_RANGE0,false,0U,0U,0U,0U,CY_SYSCLK_FLLPLL_OUTPUT_AUTO,0U}; + Cy_SysClk_FllGetConfiguration(&fllCfg); + enabled = (Cy_SysClk_FllIsEnabled()) && (CY_SYSCLK_FLLPLL_OUTPUT_INPUT != fllCfg.outputMode); + fDiv = fllCfg.fllMult; + rDiv = fllCfg.refDiv; + oDiv = (fllCfg.enableOutputDiv) ? 2UL : 1UL; + } + else if (clkPath <= CY_SRSS_NUM_PLL) /* PLL? (always path 1...N)*/ + { + cy_stc_pll_manual_config_t pllcfg = {0U,0U,0U,false,CY_SYSCLK_FLLPLL_OUTPUT_AUTO}; + (void)Cy_SysClk_PllGetConfiguration(clkPath, &pllcfg); + enabled = (Cy_SysClk_PllIsEnabled(clkPath)) && (CY_SYSCLK_FLLPLL_OUTPUT_INPUT != pllcfg.outputMode); + fDiv = pllcfg.feedbackDiv; + rDiv = pllcfg.referenceDiv; + oDiv = pllcfg.outputDiv; + } + else + { + /* Do nothing with the path mux frequency */ + } + + if (enabled) /* If FLL or PLL is enabled and not bypassed */ + { + freq = (uint32_t)CY_SYSLIB_DIV_ROUND(((uint64_t)freq * (uint64_t)fDiv), + ((uint64_t)rDiv * (uint64_t)oDiv)); + } + + return (freq); +} /** \} group_sysclk_path_src_funcs */ @@ -1816,82 +1981,9 @@ cy_en_syspm_status_t Cy_SysClk_DeepSleepCallback(cy_stc_syspm_callback_params_t uint32_t Cy_SysClk_ClkHfGetFrequency(uint32_t clkHf) { /* variables holding intermediate clock frequencies, dividers and FLL/PLL settings */ - bool enabled = false; /* FLL or PLL enable status; n/a for direct */ - uint32_t freq = 0UL; /* path (FLL, PLL, or direct) frequency, in Hz, 0 = unknown frequency */ - uint32_t fDiv = 0UL; /* FLL/PLL multiplier/feedback divider */ - uint32_t rDiv = 0UL; /* FLL/PLL reference divider */ - uint32_t oDiv = 0UL; /* FLL/PLL output divider */ uint32_t pDiv = 1UL << (uint32_t)Cy_SysClk_ClkHfGetDivider(clkHf); /* root prescaler (1/2/4/8) */ uint32_t path = (uint32_t) Cy_SysClk_ClkHfGetSource(clkHf); /* path input for root 0 (clkHf[0]) */ - cy_en_clkpath_in_sources_t source = Cy_SysClk_ClkPathGetSource((uint32_t)path); /* source input for path (FLL, PLL, or direct) */ - - /* get the frequency of the source, i.e., the path mux input */ - switch(source) - { - case CY_SYSCLK_CLKPATH_IN_IMO: /* IMO frequency is fixed at 8 MHz */ - freq = CY_SYSCLK_IMO_FREQ; - break; - - case CY_SYSCLK_CLKPATH_IN_EXT: - freq = extFreq; - break; - - case CY_SYSCLK_CLKPATH_IN_ECO: - freq = (CY_SYSCLK_ECOSTAT_STABLE == Cy_SysClk_EcoGetStatus()) ? ecoFreq : 0UL; - break; - - #if defined(CY_IP_MXBLESS) - case CY_SYSCLK_CLKPATH_IN_ALTHF: - freq = cy_BleEcoClockFreqHz; - break; - #endif /* CY_IP_MXBLESS */ - - case CY_SYSCLK_CLKPATH_IN_ILO: - freq = (0UL != (SRSS_CLK_ILO_CONFIG & SRSS_CLK_ILO_CONFIG_ENABLE_Msk)) ? CY_SYSCLK_ILO_FREQ : 0UL; - break; - - case CY_SYSCLK_CLKPATH_IN_WCO: - freq = (Cy_SysClk_WcoOkay()) ? CY_SYSCLK_WCO_FREQ : 0UL; - break; - - case CY_SYSCLK_CLKPATH_IN_PILO: - freq = (0UL != (SRSS_CLK_PILO_CONFIG & SRSS_CLK_PILO_CONFIG_PILO_EN_Msk)) ? CY_SYSCLK_PILO_FREQ : 0UL; - break; - - default: - /* don't know the frequency of dsi_out, or clk_altlf */ - freq = 0UL; /* unknown frequency */ - break; - } - - if (path == (uint32_t)CY_SYSCLK_CLKHF_IN_CLKPATH0) /* FLL? (always path 0) */ - { - cy_stc_fll_manual_config_t fllCfg = {0UL,0U,CY_SYSCLK_FLL_CCO_RANGE0,false,0U,0U,0U,0U,CY_SYSCLK_FLLPLL_OUTPUT_AUTO,0U}; - Cy_SysClk_FllGetConfiguration(&fllCfg); - enabled = (Cy_SysClk_FllIsEnabled()) && (CY_SYSCLK_FLLPLL_OUTPUT_INPUT != fllCfg.outputMode); - fDiv = fllCfg.fllMult; - rDiv = fllCfg.refDiv; - oDiv = (fllCfg.enableOutputDiv) ? 2UL : 1UL; - } - else if (path <= CY_SRSS_NUM_PLL) /* PLL? (always path 1...N)*/ - { - cy_stc_pll_manual_config_t pllcfg = {0U,0U,0U,false,CY_SYSCLK_FLLPLL_OUTPUT_AUTO}; - (void)Cy_SysClk_PllGetConfiguration(path, &pllcfg); - enabled = (Cy_SysClk_PllIsEnabled(path)) && (CY_SYSCLK_FLLPLL_OUTPUT_INPUT != pllcfg.outputMode); - fDiv = pllcfg.feedbackDiv; - rDiv = pllcfg.referenceDiv; - oDiv = pllcfg.outputDiv; - } - else - { - /* Direct select path */ - } - - if (enabled) /* if FLL or PLL enabled and not bypassed */ - { - freq = (uint32_t)CY_SYSLIB_DIV_ROUND(((uint64_t)freq * (uint64_t)fDiv), - ((uint64_t)rDiv * (uint64_t)oDiv)); - } + uint32_t freq = Cy_SysClk_ClkPathGetFrequency(path); /* Divide the path input frequency down and return the result */ return (CY_SYSLIB_DIV_ROUND(freq, pDiv)); @@ -1900,7 +1992,6 @@ uint32_t Cy_SysClk_ClkHfGetFrequency(uint32_t clkHf) /** \} group_sysclk_clk_hf_funcs */ - /* ========================================================================== */ /* ===================== clk_peripherals SECTION ====================== */ /* ========================================================================== */ @@ -1971,4 +2062,63 @@ uint32_t Cy_SysClk_PeriphGetFrequency(cy_en_divider_types_t dividerType, uint32_ /** \} group_sysclk_clk_peripheral_funcs */ +/** +* \addtogroup group_sysclk_clk_timer_funcs +* \{ +*/ + + +/******************************************************************************* +* Function Name: Cy_SysClk_ClkTimerGetFrequency +****************************************************************************//** +* +* Reports the frequency of the timer clock (clk_timer). +* \note If the the timer clock is not enabled - a zero frequency is reported. +* +* \funcusage +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkTimerEnable +* +*******************************************************************************/ +uint32_t Cy_SysClk_ClkTimerGetFrequency(void) +{ + uint32_t freq = 0UL; + + if (Cy_SysClk_ClkTimerIsEnabled()) + { + freq = Cy_SysClk_ClkHfGetFrequency(0UL); + + switch (Cy_SysClk_ClkTimerGetSource()) + { + case CY_SYSCLK_CLKTIMER_IN_IMO: + freq = CY_SYSCLK_IMO_FREQ; + break; + + case CY_SYSCLK_CLKTIMER_IN_HF0_NODIV: + break; + + case CY_SYSCLK_CLKTIMER_IN_HF0_DIV2: + freq /= 2UL; + break; + + case CY_SYSCLK_CLKTIMER_IN_HF0_DIV4: + freq /= 4UL; + break; + + case CY_SYSCLK_CLKTIMER_IN_HF0_DIV8: + freq /= 8UL; + break; + + default: + freq = 0UL; + break; + } + } + + /* Divide the input frequency down and return the result */ + return (CY_SYSLIB_DIV_ROUND(freq, 1UL + (uint32_t)Cy_SysClk_ClkTimerGetDivider())); +} + +/** \} group_sysclk_clk_timer_funcs */ + + /* [] END OF FILE */ diff --git a/drivers/source/cy_syslib.c b/drivers/source/cy_syslib.c index f2a231f..3121c76 100644 --- a/drivers/source/cy_syslib.c +++ b/drivers/source/cy_syslib.c @@ -1,12 +1,12 @@ /***************************************************************************//** * \file cy_syslib.c -* \version 2.50 +* \version 2.50.1 * * Description: * Provides system API implementation for the SysLib driver. * ******************************************************************************** -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/drivers/source/cy_syspm.c b/drivers/source/cy_syspm.c index 828d53f..a2d7434 100644 --- a/drivers/source/cy_syspm.c +++ b/drivers/source/cy_syspm.c @@ -1,12 +1,12 @@ /***************************************************************************//** * \file cy_syspm.c -* \version 4.50 +* \version 5.0 * * This driver provides the source code for API power management. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -189,6 +189,9 @@ typedef void (*cy_cb_syspm_deep_sleep_t)(cy_en_syspm_waitfor_t waitFor, bool *wa /* Mask for the RAM read assist bits */ #define CPUSS_TRIM_RAM_CTL_RA_MASK ((uint32_t) 0x3U << 8U) +/* Mask for the RAM write check bits */ +#define CPUSS_TRIM_RAM_CTL_WC_MASK (0x3UL << 10U) + /* The define for SROM opcode to set the flash voltage bit */ #define FLASH_VOLTAGE_BIT_ULP_OPCODE (0x0C000003U) @@ -1057,7 +1060,7 @@ he LP mode * are registered. * * \return -* - CY_SYSPM_SUCCESS - Entered the system LP mode. +* - CY_SYSPM_SUCCESS - Entered the system LP mode or the device is already in LP mode. * - CY_SYSPM_INVALID_STATE - The system LP mode was not set. The system LP mode * was not set because the protection context value is higher than zero * (PC > 0) or the device revision does not support modifying registers @@ -1199,7 +1202,7 @@ cy_en_syspm_status_t Cy_SysPm_SystemEnterLp(void) * are registered. * * \return -* - CY_SYSPM_SUCCESS - Entered system ULP mode. +* - CY_SYSPM_SUCCESS - Entered the system ULP mode or the device is already in ULP mode. * - CY_SYSPM_INVALID_STATE - System ULP mode was not set. The ULP mode was not * set because the protection context value is higher than zero (PC > 0) or the * device revision does not support modifying registers (to enter system @@ -1687,7 +1690,8 @@ void Cy_SysPm_ClearHibernateWakeupSource(uint32_t wakeupSource) * See \ref cy_en_syspm_buck_voltage1_t. * * \return -* - CY_SYSPM_SUCCESS - The voltage is set. +* - CY_SYSPM_SUCCESS - The voltage is set as requested. +* (There is no change if the new voltage is the same as the previous voltage.) * - CY_SYSPM_INVALID_STATE - The voltage was not set. The voltage cannot be set * because the protection context value is higher than zero (PC > 0) or the * device revision does not support modifying registers via syscall. @@ -3143,7 +3147,9 @@ static void SetWriteAssistTrimLp(void) *******************************************************************************/ static bool IsVoltageChangePossible(void) { - bool retVal = true; + bool retVal = false; + uint32_t trimRamCheckVal = (CPUSS_TRIM_RAM_CTL & CPUSS_TRIM_RAM_CTL_WC_MASK); + if (Cy_SysLib_GetDevice() == CY_SYSLIB_DEVICE_PSOC6ABLE2) { @@ -3151,6 +3157,13 @@ static bool IsVoltageChangePossible(void) retVal = ((Cy_SysLib_GetDeviceRevision() > SYSPM_DEVICE_PSOC6ABLE2_REV_0B) || (curProtContext == 0U)); } + else + { + CPUSS_TRIM_RAM_CTL &= ~CPUSS_TRIM_RAM_CTL_WC_MASK; + CPUSS_TRIM_RAM_CTL |= ((~trimRamCheckVal) & CPUSS_TRIM_RAM_CTL_WC_MASK); + + retVal = (trimRamCheckVal != (CPUSS_TRIM_RAM_CTL & CPUSS_TRIM_RAM_CTL_WC_MASK)); + } return retVal; } diff --git a/personalities/.cymigration b/personalities/.cymigration index af97141..e7a0834 100644 --- a/personalities/.cymigration +++ b/personalities/.cymigration @@ -61,7 +61,7 @@ - + \ No newline at end of file diff --git a/personalities/peripheral/canfd-1.0.cypersonality b/personalities/peripheral/canfd-1.0.cypersonality index f0350f9..ef801e1 100644 --- a/personalities/peripheral/canfd-1.0.cypersonality +++ b/personalities/peripheral/canfd-1.0.cypersonality @@ -3,14 +3,14 @@ @@ -378,7 +381,7 @@ treated."> ((sfid2_10_9_SidFilter$idx << 9U) | sfid2_5_0_SidFilter$idx)}`U, \ .sfid1 = `${sfid1_SidFilter$idx}`U, \ .sfec = `${sfecSidFilter$idx}`, \ - .sft = `${sftSidFilter$idx}`, \ + .sft = `${sftSidFilterVal$idx}`, \ }" /> ((sfid2_10_9_SidFilter$idx << 9U) | sfid2_5_0_SidFilter$idx)}`U" /> - + diff --git a/personalities/peripheral/connectivity_wifi-1.0.cypersonality b/personalities/peripheral/connectivity_wifi-1.0.cypersonality index b6af777..766a225 100644 --- a/personalities/peripheral/connectivity_wifi-1.0.cypersonality +++ b/personalities/peripheral/connectivity_wifi-1.0.cypersonality @@ -3,14 +3,14 @@ + @@ -296,8 +297,9 @@ - - + + + @@ -335,7 +337,7 @@ - + diff --git a/personalities/peripheral/pdm_pcm-1.0.cypersonality b/personalities/peripheral/pdm_pcm-1.0.cypersonality index 99503b3..754a0f6 100644 --- a/personalities/peripheral/pdm_pcm-1.0.cypersonality +++ b/personalities/peripheral/pdm_pcm-1.0.cypersonality @@ -3,14 +3,14 @@ + @@ -192,8 +193,9 @@ - - + + + @@ -218,7 +220,7 @@ - + diff --git a/personalities/peripheral/seglcd-1.1.cypersonality b/personalities/peripheral/seglcd-1.1.cypersonality index 2b62857..8c5c631 100644 --- a/personalities/peripheral/seglcd-1.1.cypersonality +++ b/personalities/peripheral/seglcd-1.1.cypersonality @@ -3,14 +3,14 @@ - - + + diff --git a/personalities/peripheral/smif-1.1.cypersonality b/personalities/peripheral/smif-1.1.cypersonality index 4eacb68..9079ed4 100644 --- a/personalities/peripheral/smif-1.1.cypersonality +++ b/personalities/peripheral/smif-1.1.cypersonality @@ -3,14 +3,14 @@ - + @@ -70,7 +70,7 @@ - + @@ -78,7 +78,7 @@ - + @@ -86,7 +86,7 @@ - + @@ -94,7 +94,7 @@ - + @@ -102,7 +102,7 @@ - + @@ -110,7 +110,7 @@ - + @@ -118,7 +118,7 @@ - + @@ -128,7 +128,7 @@ - + @@ -136,7 +136,7 @@ - + @@ -144,7 +144,7 @@ - + @@ -152,7 +152,7 @@ - + diff --git a/personalities/platform/dma-1.0.cypersonality b/personalities/platform/dma-1.0.cypersonality index 14847f1..4014dd9 100644 --- a/personalities/platform/dma-1.0.cypersonality +++ b/personalities/platform/dma-1.0.cypersonality @@ -3,14 +3,14 @@ - + diff --git a/personalities/platform/sysclock-1.2.cypersonality b/personalities/platform/sysclock-1.2.cypersonality index 4e4b6e1..66c39e4 100644 --- a/personalities/platform/sysclock-1.2.cypersonality +++ b/personalities/platform/sysclock-1.2.cypersonality @@ -343,6 +343,7 @@ + diff --git a/udd/001-91989.revision b/udd/001-91989.revision new file mode 100644 index 0000000..b5f9103 --- /dev/null +++ b/udd/001-91989.revision @@ -0,0 +1 @@ +CG \ No newline at end of file diff --git a/udd/MXS40.revision b/udd/MXS40.revision new file mode 100644 index 0000000..3cafba3 --- /dev/null +++ b/udd/MXS40.revision @@ -0,0 +1 @@ +258628 diff --git a/udd/devices/Connectivity/43012C0/CYW43012C0WKWBG/base/view.xml b/udd/devices/Connectivity/43012C0/CYW43012C0WKWBG/base/view.xml new file mode 100644 index 0000000..f31188f --- /dev/null +++ b/udd/devices/Connectivity/43012C0/CYW43012C0WKWBG/base/view.xml @@ -0,0 +1,16 @@ + + + 0x00000000 + 0x000 + 0 + 0 + CortexM4 + Cypress + 0 + 1310720 + 251-WLCSP + 251 + 3200 + 4400 + The CYW43012C0WKWBG device. + \ No newline at end of file diff --git a/udd/devices/Connectivity/43012C0/CYW43012C0WKWBG/info.xml b/udd/devices/Connectivity/43012C0/CYW43012C0WKWBG/info.xml new file mode 100644 index 0000000..218dc5f --- /dev/null +++ b/udd/devices/Connectivity/43012C0/CYW43012C0WKWBG/info.xml @@ -0,0 +1,6 @@ + + + CYW43012C0WKWBG + The CYW43012C0WKWBG devices + true + \ No newline at end of file diff --git a/udd/devices/Connectivity/43012C0/CYW43012C0WKWBG/studio/presentation b/udd/devices/Connectivity/43012C0/CYW43012C0WKWBG/studio/presentation new file mode 100644 index 0000000..c4e8208 --- /dev/null +++ b/udd/devices/Connectivity/43012C0/CYW43012C0WKWBG/studio/presentation @@ -0,0 +1,2 @@ +Connectivity +43012 diff --git a/udd/devices/Connectivity/43012C0/CYW43012C0WKWBG/studio/view.xml b/udd/devices/Connectivity/43012C0/CYW43012C0WKWBG/studio/view.xml new file mode 100644 index 0000000..142f47b --- /dev/null +++ b/udd/devices/Connectivity/43012C0/CYW43012C0WKWBG/studio/view.xml @@ -0,0 +1,23 @@ + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/udd/devices/MXS40/PSoC6A256K/PSoC6A256K/base/view.xml b/udd/devices/MXS40/PSoC6A256K/PSoC6A256K/base/view.xml new file mode 100644 index 0000000..58b005d --- /dev/null +++ b/udd/devices/MXS40/PSoC6A256K/PSoC6A256K/base/view.xml @@ -0,0 +1,16 @@ + + + 0xFFFF + 0xFF + F + F + CortexM0p,CortexM4 + Cypress + 262144 + 131072 + 68-QFN + 68 + 1700 + 3600 + The PSoC6A256K device. + \ No newline at end of file diff --git a/udd/devices/MXS40/PSoC6A256K/PSoC6A256K/info.xml b/udd/devices/MXS40/PSoC6A256K/PSoC6A256K/info.xml new file mode 100644 index 0000000..54e2888 --- /dev/null +++ b/udd/devices/MXS40/PSoC6A256K/PSoC6A256K/info.xml @@ -0,0 +1,6 @@ + + + PSoC6A256K + The PSoC6A256K devices + true + \ No newline at end of file diff --git a/udd/devices/MXS40/PSoC6A256K/info.xml b/udd/devices/MXS40/PSoC6A256K/info.xml new file mode 100644 index 0000000..d9a8603 --- /dev/null +++ b/udd/devices/MXS40/PSoC6A256K/info.xml @@ -0,0 +1,5 @@ + + + PSoC6A256K + The PSoC6A256K devices + \ No newline at end of file diff --git a/udd/devices/MXS40/PSoC6A2M/CYB0644ABZI-S2D44/base/view.xml b/udd/devices/MXS40/PSoC6A2M/CYB0644ABZI-S2D44/base/view.xml index 6acd066..b22ae22 100644 --- a/udd/devices/MXS40/PSoC6A2M/CYB0644ABZI-S2D44/base/view.xml +++ b/udd/devices/MXS40/PSoC6A2M/CYB0644ABZI-S2D44/base/view.xml @@ -1,9 +1,9 @@  - 0xE430 + 0xE470 0x102 1 - 1 + 2 CortexM0p,CortexM4 Cypress 1900544 diff --git a/udd/devices/MXS40/PSoC6A2M/CYB0644ABZI-S2D44/studio/view.xml b/udd/devices/MXS40/PSoC6A2M/CYB0644ABZI-S2D44/studio/view.xml index d24fa62..59f13fc 100644 --- a/udd/devices/MXS40/PSoC6A2M/CYB0644ABZI-S2D44/studio/view.xml +++ b/udd/devices/MXS40/PSoC6A2M/CYB0644ABZI-S2D44/studio/view.xml @@ -49,7 +49,7 @@ - + diff --git a/udd/devices/MXS40/PSoC6A2M/CYS0644ABZI-S2D44/base/view.xml b/udd/devices/MXS40/PSoC6A2M/CYS0644ABZI-S2D44/base/view.xml new file mode 100644 index 0000000..0209df5 --- /dev/null +++ b/udd/devices/MXS40/PSoC6A2M/CYS0644ABZI-S2D44/base/view.xml @@ -0,0 +1,16 @@ + + + 0xE4A0 + 0x102 + 1 + 2 + CortexM0p,CortexM4 + Cypress + 1900544 + 1048576 + 124-BGA + 124 + 1700 + 3600 + The CYS0644ABZI-S2D44 device. + \ No newline at end of file diff --git a/udd/devices/MXS40/PSoC6A2M/CYS0644ABZI-S2D44/info.xml b/udd/devices/MXS40/PSoC6A2M/CYS0644ABZI-S2D44/info.xml new file mode 100644 index 0000000..41553d8 --- /dev/null +++ b/udd/devices/MXS40/PSoC6A2M/CYS0644ABZI-S2D44/info.xml @@ -0,0 +1,6 @@ + + + CYS0644ABZI-S2D44 + The CYS0644ABZI-S2D44 devices + true + \ No newline at end of file diff --git a/udd/devices/MXS40/PSoC6A2M/CYS0644ABZI-S2D44/studio/presentation b/udd/devices/MXS40/PSoC6A2M/CYS0644ABZI-S2D44/studio/presentation new file mode 100644 index 0000000..6cd2210 --- /dev/null +++ b/udd/devices/MXS40/PSoC6A2M/CYS0644ABZI-S2D44/studio/presentation @@ -0,0 +1,2 @@ +PSoC 6 +PSoC 64 diff --git a/udd/devices/MXS40/PSoC6A2M/CYS0644ABZI-S2D44/studio/view.xml b/udd/devices/MXS40/PSoC6A2M/CYS0644ABZI-S2D44/studio/view.xml new file mode 100644 index 0000000..b4c99c6 --- /dev/null +++ b/udd/devices/MXS40/PSoC6A2M/CYS0644ABZI-S2D44/studio/view.xml @@ -0,0 +1,59 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/udd/devices/MXS40/PSoC6A2M/studio/clocks.cysem b/udd/devices/MXS40/PSoC6A2M/studio/clocks.cysem index 44caf60..25ec63f 100644 --- a/udd/devices/MXS40/PSoC6A2M/studio/clocks.cysem +++ b/udd/devices/MXS40/PSoC6A2M/studio/clocks.cysem @@ -468,7 +468,7 @@ 2 - Watch Crystal Oscillator: This source is driven from an off-chip watch crystal that provides an extremely accurate source. This clock is stopped in the hibernate power mode. + Watch Crystal Oscillator: This source is driven from an off-chip watch crystal that provides an extremely accurate source. This clock runs in hibernate power mode. diff --git a/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D11/studio/view.xml b/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D11/studio/view.xml index 18baad8..1d6811e 100644 --- a/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D11/studio/view.xml +++ b/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D11/studio/view.xml @@ -33,7 +33,7 @@ - + diff --git a/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D41/studio/view.xml b/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D41/studio/view.xml index 0e24e5a..ffbdc96 100644 --- a/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D41/studio/view.xml +++ b/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D41/studio/view.xml @@ -33,7 +33,7 @@ - + diff --git a/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D71/studio/view.xml b/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D71/studio/view.xml index 3e24f6f..21424b2 100644 --- a/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D71/studio/view.xml +++ b/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D71/studio/view.xml @@ -33,7 +33,7 @@ - + diff --git a/udd/devices/MXS40/PSoC6A512K/studio/clocks.cysem b/udd/devices/MXS40/PSoC6A512K/studio/clocks.cysem index f160ae1..b8d28ed 100644 --- a/udd/devices/MXS40/PSoC6A512K/studio/clocks.cysem +++ b/udd/devices/MXS40/PSoC6A512K/studio/clocks.cysem @@ -433,7 +433,7 @@ 2 - Watch Crystal Oscillator: This source is driven from an off-chip watch crystal that provides an extremely accurate source. This clock is stopped in the hibernate power mode. + Watch Crystal Oscillator: This source is driven from an off-chip watch crystal that provides an extremely accurate source. This clock runs in hibernate power mode. diff --git a/udd/devices/MXS40/PSoC6ABLE2/studio/clocks.cysem b/udd/devices/MXS40/PSoC6ABLE2/studio/clocks.cysem index fa25ded..19d1b2f 100644 --- a/udd/devices/MXS40/PSoC6ABLE2/studio/clocks.cysem +++ b/udd/devices/MXS40/PSoC6ABLE2/studio/clocks.cysem @@ -1,5 +1,5 @@  - + @@ -1082,7 +1082,7 @@ SYS_TICK 2 - Watch Crystal Oscillator: This source is driven from an off-chip watch crystal that provides an extremely accurate source. This clock is stopped in the hibernate power mode. + Watch Crystal Oscillator: This source is driven from an off-chip watch crystal that provides an extremely accurate source. This clock runs in hibernate power mode. @@ -1628,8 +1628,8 @@ SYS_TICK - + @@ -1866,17 +1866,17 @@ SYS_TICK - + - - - + + - - + + + diff --git a/udd/devices/MXS40/PSoC6ABLE2/studio/clocks.cyvis b/udd/devices/MXS40/PSoC6ABLE2/studio/clocks.cyvis index 709240d..a0265f8 100644 --- a/udd/devices/MXS40/PSoC6ABLE2/studio/clocks.cyvis +++ b/udd/devices/MXS40/PSoC6ABLE2/studio/clocks.cyvis @@ -1,5 +1,5 @@  - + diff --git a/udd/devices/MXS40/studio/connectivity/mxprofile_v1.cydata b/udd/devices/MXS40/studio/connectivity/mxprofile_v1.cydata index 6b0476263f4494680beaa433b6983abef9266266..9f3fb6a694b5b06aecd2dd8b8c02f7cd29a2e18f 100644 GIT binary patch delta 281 zcmV+!0p|Xb1d{}i9e=HoQA@)x5Xay9DZ;(Gx;K$_W1vVuwBYs}N}8@=Z4&NowfXk8 zc5I-sq4V+XxZnSmBgwLF8_{Vb<7^7^*)0fdl`Dk1A}c*vfz_3C+a#Bpnk z$zJl!8pOLPN8KSb{?2e}Cy&zCpp0dWxc7Vx^SW7I;xJ0$0?%SD+k8@-|1IR_^Jp~E fJCfS|$F(WY9}a0rJpI~5^Z_+0w^`-_lOX}>){K#C delta 270 zcmV+p0rCEm1d{}i9e<^g!D_=W42JJ{3ZeU&^)^PFQrH-Qu?3c%LvWnNG_j4WX7SrE zSxO5Vw2U1kq3{0$N;YHP!Jx=%YXq)W_Xx^JTWhlyc;x2p0XJ!sY)Q6R4jh~k=*Tv@ zQwX*8uB$?6s(xxe8%6s7`7));*j3yL{0N>^kKikRTIk0!X@72BED$EEpSAG}x8|7a zE#DOgpSqrPr_lH}!^%T>mi`Y)8&*U|$Ja3LyW$pysq|dYRm^RhZ;Ew)g(UIv7ishb U5_}x8NCE%=0FyKU-;+QA83YxBWB>pF diff --git a/udd/devices/MXS40/studio/connectivity/mxs40srss_v1-power.cydata b/udd/devices/MXS40/studio/connectivity/mxs40srss_v1-power.cydata deleted file mode 100644 index a9be78bedbeaf80ba341cb45079b9769d4aa6e41..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 531 zcmWFt_IGv;a&-*x4{~t~adh+aagF&@QIuL-%)r7h_mX$^VFMn92i5hhA8S7|+4e5E zke9>qjblyf@ds9Ng1zz)r(WOJS8Q}j==q`%`70&y`0oX$Op>ou&nP(uut30GMiq2LJ#7 diff --git a/udd/devices/MXS40/studio/connectivity/mxs40srss_v1.cydata b/udd/devices/MXS40/studio/connectivity/mxs40srss_v1.cydata index 4c796d89b362855aeb5ef81ea1ac17fe10083624..6546bc53b448d2d736bb5f8310436d0e5bcec8a8 100644 GIT binary patch delta 1167 zcmV;A1aSMU5%&?0AAjF(;y4g~zWx=n(dyJn3zY6Yta>dgO1VAMQV`JXN!2Pfjwx1? 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