diff --git a/hardware/asic/README.md b/hardware/asic/README.md new file mode 100644 index 000000000..af52e6c14 --- /dev/null +++ b/hardware/asic/README.md @@ -0,0 +1,452 @@ + + --------------------------------- + # README FOR OPENLANE AND OPENRAM + --------------------------------- +## OpenLane Instructions +## Installation of Openlane and Skywater PDK 130 + +Minimal requirements for OpenLane: +1. Docker 19.03.12+ +2. GNU make +3. Python 3.6+ with PIP +4. Click,Pyyaml + +Setting up OPenLane +Clone OpenLane repository with Skywater PDK 130 as follows + +```bash + +git clone https://github.com/The-OpenROAD-Project/OpenLane.git +``` + +The default PDK installation directory is $PWD/pdks. If any other location is required then add the configuration variable to bashrc as follows +```bash +export PDK_ROOT=/usr/devel/pdks/ +``` + +Any other path can also be chosen for PDK installation. + +The default SCL to be installed is sky130_fd_sc_hd. +To change that, you can add this configuration variable: +```bash +export STD_CELL_LIBRARY= +``` +where the library name is one of: +1. sky130_fd_sc_hd +2. sky130_fd_sc_hs +3. sky130_fd_sc_ms +4. sky130_fd_sc_ls +5. sky130_fd_sc_hdll + + +For intallation of Skywater PDK and OpenLane use the OpenLane make utility just type make inside the cloned OpenLane repo or do +as following: +```bash + cd OpenLane/ + make openlane + ``` +This will clone the specific version of Skywater PDK and will pull and will build Docker Container. +If everything is properly installed by the makefile it will report the success. +In order to test the OpenLane flow and PDK installation just run + +```bash +make test +``` +This will run a 5 mins test that will verify the OpenLane and Skywater PDK installation and will report success if everything has been successfully installed. + +## OPENLANE FLOW FOR MACRO HARDENING FROM AN HDL DESIGN + +OpenLane Flow for Macro Hardening of a test design. + +1. Copy all HDL files in one folder and name it as 'src' folder. +2. Make a folder inside "OpenLane installation directory"/designs/. The name of the folder is the name of your design and it should be the same as the name of the top level module of your design. +3. Start Docker container of OpenLane by running + +```bash +make mount +``` + +in the terminal.After starting Docker container in the terminal run following tcl script in order to generate a design configuration of your design. +```bash +flow.tcl -design design1 -init_design_config +``` +4. This tcl script will generate a default tcl configutaion file of your design. This "config.tcl" file has following environment variables by default that can be modified. + +* Clock signal name. Make sure that this name matches the name of the clock signal in your top level module. + +* Design name. This should be the same as your top level module name is. + +* Verilog Files. This environment variable should point to all of your HDL files. e.g., set ::env(VERILOG_FILES) "src/*.vh src/*.v" + +* Standard Cell Library. + +5. After making necessary changes to config.tcl file. Run following tcl command. +```bash + flow.tcl -design design1 -tag first_run +``` +Tag here is the tag of the design run. +This will go through all the following steps inorder to generate GDSII file from HDL input files. + +**"Synthesis"** + +_yosys_ - Performs RTL synthesis +_abc_ - Performs technology mapping + +**"OpenSTA"** + +Performs static timing analysis on the resulting netlist to generate timing reports + +**"Floorplan and PDN"** + +_init_fp_ - Defines the core area for the macro as well as the rows (used for placement) and the tracks (used for routing) +_ioplacer_ - Places the macro input and output ports +_pdn_ - Generates the power distribution network +_tapcell_ - Inserts welltap and decap cells in the floorplan + +**"Placement"** + +_RePLace_ - Performs global placement +_Resizer_ - Performs optional optimizations on the design +_OpenDP_ - Perfroms detailed placement to legalize the globally placed components + +**"CTS"** + +_TritonCTS_ - Synthesizes the clock distribution network (the clock tree) + +**"Routing"** + +_FastRoute_ - Performs global routing to generate a guide file for the detailed router. + +_CU-GR_ - Another option for performing global routing. + +_TritonRoute_ - Performs detailed routing + +_SPEF-Extractor_ - Performs SPEF extraction. + +**"GDSII Generation"** + +_Magic_ - Streams out the final GDSII layout file from the routed def +_Klayout_ - Streams out the final GDSII layout file from the routed def as a back-up + +**"Checks"** + +_Magic_ - Performs DRC Checks & Antenna Checks + +_Klayout_ - Performs DRC Checks + +_Netgen_ - Performs LVS Checks + +_CVC_ - Performs Circuit Validity Checks + +After all the processes mentioned above are successfully completed without any fatal errors and warnings and GDSII is generated. Go to the runs/first_run/ folder. Here Reports and Results folders will have all reports and results generated by all of the above mentioned steps. + +## Interactive flow of OpenLane +OpenLane can be run in interactive mode. This can be done by following these steps. + +1. Intialize design configuration. Enter following the command line. +```bash +flow.tcl -design design1 -init_design_config +``` +2. Start interactive flow of OpenLane. Enter following in command line. +```bash +flow.tcl -interactive +``` +3. Prepare the design. Enter following in command line. +```bash +prep -design design1 +``` +where the design1 is your design. This command will prepare the design for OpenLane flow by creating one .lef file and one .tech file by merging all the tech and lef files from the library. +4. Run yosys. Enter following in command line. +```bash +run_yosys +``` +This will create a gate level netlist of the design and will perform technology independent optimizations to the design. + +5. Run STA. Enter the following in command line. +```bash +run_sta +``` +This will report the Total Negative Slack and Worst Negative Slack of the design. + +6. Run Floorplan. Enter the following in command line. +```bash +run_floorplan +``` +7. Run Placement step. Enter the following in command line. +```bash +run_placement_step +``` +8. Run CTS step. Enter the following in command line. +```bash +run_cts_step +``` +9. Run Routing step. Enter the following in command line. +```bash +run_routing_step +``` +10. Run Fake Diode Insertion step. Enter the following in command line. +```bash +run_diode_insertion_2_5_step +``` +11. Run Power Pin Insertion step. Enter the following in command line. +```bash +run_power_pins_insertion_step +``` +12. Run Magic. Enter the following in command line. +```bash +run_magic +``` +13. Run Klayout. Enter the following in command line. +```bash +run_klayout +``` +14. Run Klayout GDS XOR. Enter the following in command line. +```bash +run_klayout_gds_xor +``` +15. Run CVC. Enter the following in command line. +```bash +run_lef_cvc +``` +## Configuration of OpenLane + +Configuration parameters of the OpenLane can be changed by adding / changing the environment variables in config.tcl file in the designs/"name of design" folder. Some important parameters that can be used to define the design constraints include the following, + +1. Clock definition parameter. Clock Period definition parameter. +2. Synthesis strategy parameter. This parameter can be used to define the synthesis strategy. This defines if the design is optimized for area or for delay. +3. Set input delay as percent of clock period. +4. Parameter to report maximum and minimum delay paths, critical delay path and specific path for delay. +5. parameter to set different wire load models. + +Complete list of configuration parameters that can be used to define the design constraints can be found in OpenLane repository. OpenLane/configuration/Readme.md. + +------------------------------- +# OpenRAM Instructions + +## INSTALLATION OF OPENRAM + +Getting Openram: Requirements for Openram are the following, +1. Python 3.8.10 +2. Python numpy (pip3 install numpy) +3. Python scipy (pip3 install scipy) +4. Python sklearn (pip3 install sklearn) +5. Python Coverage(pip3 install coverage) +5. Magic 8.3.130 +6. Netgen 1.5.164 or newer + +Clone OpenRAM and set environment variables as followa: + +1. clone the git repository for openram +```bash +git clone https://github.com/VLSIDA/OpenRAM +``` +2. set following environment variables in bashrc + ```bash + export OPENRAM_HOME="$HOME/openram/compiler" + export OPENRAM_TECH="$HOME/openram/technology" + ``` +3. Also add OPENRAM_HOME to your PYTHONPATH +```bash +export PYTHONPATH="$PYTHONPATH:$OPENRAM_HOME" +``` +## Getting SKYWATER 130nm + +Getting skywater-pdk: + +```bash +git clone https://github.com/google/skywater-pdk +``` + +## Getting OpenPDK + +Getting open-pdk from open circuit design + +we will need OpenPDK to install & generate the required tech files for magic vlsi. +Get open pdk repository and checkout to new branch as follows: + +```bash + git clone git://opencircuitdesign.com/open_pdks + cd open_pdks + git checkout open_pdks-1.0 +``` +## Getting Magic_VLSI + +For requirements of magic vlsi: + +sudo apt update && sudo apt install m4 tcsh csh libx11-dev tcl-dev tk-dev + +sudo apt install libcairo2-dev libncurses-dev libglu1-mesa-dev freeglut3-dev mesa-common-dev + +Download and installation of Magic_vlsi. + +**Download** +```bash + git clone git://opencircuitdesign.com/magic + cd magic + git checkout magic-8.3 +``` +**Compile & Install** +```bash + sudo ./configure + sudo make + sudo make install +``` + and then exit to home directory + +## Skywater PDK Installation + +```bash +# cd into skywater repo + cd skywater-pdk +``` +```bash + # initialise pdk + git submodule init libraries/sky130_fd_pr/latest + git submodule init libraries/sky130_fd_sc_hd/latest + git submodule init libraries/sky130_fd_sc_hdll/latest + git submodule init libraries/sky130_fd_sc_hs/latest + git submodule init libraries/sky130_fd_sc_ms/latest + git submodule init libraries/sky130_fd_sc_ls/latest + git submodule init libraries/sky130_fd_sc_lp/latest + git submodule init libraries/sky130_fd_sc_hvl/latest + + git submodule update + sudo make timing + # exit skywater-pdk directory +``` +## Configuring Open PDK with Google Skywater + +cd into open-pdk repository and enter following +```bash + ./configure +--enable-sky130-pdk=/skywater-pdk/libraries --with-sky130-local-path= +``` + +**NOTE**: Skywater_root_dir = skywater repo and your_target_install_dir = your skywater130A runtime install directory. + +## Install Skywater +From open-pdk repository +```bash + cd sky130 # you should be in open_pdks root dir + make + sudo make install +``` +## Integrate Skywater into Magic + +As the skywater tech files are not installed in magic’s library, we need to create a symbolic link in order to use the tech files for drawing layout. + +So enter following for the symbolic links: +```bash +sudo ln -s /sky130A/libs.tech/magic/*../usr/local/lib/magic/sys/ +``` +In my case it was as follows: +```bash + sudo ln -s /home/c/open_pdks/sky130/sky130A/libs.tech/magic/*../usr/local/lib/magic/sys/ + ``` + +## Running Magic with Skywater + +Enter following in the terminal to check if the magic runs with skywater +```bash +tcsh +sudo magic -T sky130A +``` + +## Porting SKY130 to OpenRAM + +Last step is to port skywater 130 process node technology to Openram. The OpenRAM compiler is currently available for two technologies, namely - SCMOS and FreePDK45. For adding a new technology support to OpenRAM, a directory with name of process node should be created in technology directory of OpenRAM. + +Getting the Sky130 technology for Openram +```bash +git clone https://github.com/vsdip/vsdsram_sky130 +``` + +Copy the folder from (vsdsram_sky130/OpenRAM/sky130A) and paste it in the technology folder of openram repository (openram/technology). +## Netgen Installation + +Getting the git repo for netgen (tool used for LVS layout vs schemetic comparison) + +```bash +git clone git://opencircuitdesign.com/netgen +``` +For installation of this tool +```bash +cd netgen # repo of netgen +./configure +make +make install +``` +Finally, make a configuration python script ("myconfig_sky130.py" any name can be used). I used the following one + +```python +# Data word size +word_size = 32 + +# Number of words in the memory +num_words = 32 #1024 + +# Technology to use in $OPENRAM_TECH +tech_name = "sky130A" + +# You can use the technology nominal corner only +# nominal_corner_only = True + +process_corners = ["SS", "TT", "FF"] +# process_corners = ["TT"] + +# Voltage corners to characterize +supply_voltages = [ 1.8 ] +# supply_voltages = [ 3.0, 3.3, 3.5 ] + +# Temperature corners to characterize +# temperatures = [ 0, 25 100] + +# Output directory for the results +output_path = "temp" +# Output file base name +output_name = "sram_{0}_{1}_{2}".format(word_size,num_words,tech_name) + +# Disable analytical models for full characterization (WARNING: slow!) +# analytical_delay = False +``` + +Some example scripts are available inside the openram repository, +openram/compiler/example_configs. Finally,run the openram from the command line terminal as follows, +```bash +$ python3 $OPENRAM_HOME/openram.py myconfig_sky130.py +``` + +**REFERENCES:** + +[OpenCircuit](http://www.opencircuitdesign.com/open_pdks/install.html) + +[Magic_VLSI_Install_Guide](https://lootr5858.wordpress.com/2020/10/06/magic-vlsi-skywater-pdk-local-installation-guide/) + +[Github:Repo for Skywater130 tech](https://github.com/vsdip/vsdsram_sky130/tree/main/OpenRAM) + +[OpenRAM Repo](https://github.com/VLSIDA/OpenRAM) + +[Google Skywater](https://github.com/google/skywater-pdk) + + + + + + + + + + + + + + + + + + + + + + +