From 224090444984b10ed45bc0333a27174759d5b732 Mon Sep 17 00:00:00 2001
From: Joao D Lopes <joao.d.lopes91@gmail.com>
Date: Sat, 16 Oct 2021 16:29:16 +0100
Subject: [PATCH 1/4] fix targets for memory wrappers; change shell script
 permitions

---
 hardware/asic/asic.mk         | 8 ++++----
 hardware/asic/umc130/synth.sh | 0
 2 files changed, 4 insertions(+), 4 deletions(-)
 mode change 100644 => 100755 hardware/asic/umc130/synth.sh

diff --git a/hardware/asic/asic.mk b/hardware/asic/asic.mk
index b8b2cb27b..25d82e03f 100644
--- a/hardware/asic/asic.mk
+++ b/hardware/asic/asic.mk
@@ -37,11 +37,11 @@ bootrom: sw gen-bootrom
 
 sram: gen-sram
 
-rom.v: *$(CASE).lib
-	$(MEM_DIR)/software/python/memwrapper_make.py fsc0l_d sp $(BOOTROM_W) 32 1 > rom.v
+bootrom.v:
+	$(MEM_DIR)/software/python/memakerwrap.py fsc0l_d sp $(BOOTROM_W) 32 1 > $@
 
-sram.v: $(SRAM_DIR)/*$(CASE).lib
-	$(MEM_DIR)/software/python/memwrapper_make.py fsc0l_d sj 0 1 $(SRAM_W) 8 4 1 > sram.v
+sram.v:
+	$(MEM_DIR)/software/python/memakerwrap.py fsc0l_d sj 0 1 $(SRAM_W) 8 4 1 > $@
 
 #
 # Synthesis
diff --git a/hardware/asic/umc130/synth.sh b/hardware/asic/umc130/synth.sh
old mode 100644
new mode 100755

From 3894983014e2ece93d9e485176ce3af40f0a9c28 Mon Sep 17 00:00:00 2001
From: Joao D Lopes <joao.d.lopes91@gmail.com>
Date: Sat, 16 Oct 2021 19:46:35 +0100
Subject: [PATCH 2/4] fix sram.v generation for ASIC; improve asic.mk; cleanup
 datasheet files from ASIC memories; transfer ASIC reports from server to
 local machine; use CASE variable to filter libraries to use on synthesis for
 ASIC

---
 hardware/asic/asic.mk              | 17 ++++++++++-------
 hardware/asic/umc130/Makefile      |  4 +++-
 hardware/asic/umc130/synscript.tcl |  2 +-
 hardware/asic/umc130/synth.sh      |  2 +-
 4 files changed, 15 insertions(+), 10 deletions(-)

diff --git a/hardware/asic/asic.mk b/hardware/asic/asic.mk
index 25d82e03f..91913d247 100644
--- a/hardware/asic/asic.mk
+++ b/hardware/asic/asic.mk
@@ -1,12 +1,13 @@
 #DEFINES
+ASIC=1
+
+CASE=TC
 
 #ddr controller address width
-DEFINE+=$(defmacro)DDR_ADDR_W=24
+DDR_ADDR_W=24
 
 include $(ROOT_DIR)/hardware/hardware.mk
 
-CASE=TC
-
 # Memory sizes in log2
 BOOTROM_W:=$(shell echo '$(BOOTROM_ADDR_W)-2' | bc)
 SRAM_W:=$(shell echo '$(SRAM_ADDR_W)-2' | bc)
@@ -41,13 +42,16 @@ bootrom.v:
 	$(MEM_DIR)/software/python/memakerwrap.py fsc0l_d sp $(BOOTROM_W) 32 1 > $@
 
 sram.v:
-	$(MEM_DIR)/software/python/memakerwrap.py fsc0l_d sj 0 1 $(SRAM_W) 8 4 1 > $@
+	$(MEM_DIR)/software/python/memakerwrap.py fsc0l_d sj 0 1 $(SRAM_W) 8 4 16 > $@
 
 #
 # Synthesis
 #
 
 synth: system_synth.v
+ifneq ($(ASIC_SERVER),)
+	scp $(ASIC_USER)@$(ASIC_SERVER):$(REMOTE_ROOT_DIR)/hardware/asic/$(ASIC_NODE)/$(ASIC_REPORTS) .
+endif
 
 #
 # Testing
@@ -64,11 +68,10 @@ test1: clean
 #
 
 clean-remote: hw-clean
-	@rm -f $(ASIC_MEM_LEFS) $(ASIC_MEM_LIBS) $(ASIC_MEM_SIM_MODELS)
 ifneq ($(ASIC_SERVER),)
 	ssh $(ASIC_USER)@$(ASIC_SERVER) 'if [ ! -d $(REMOTE_ROOT_DIR) ]; then mkdir -p $(REMOTE_ROOT_DIR); fi'
 	rsync -avz --exclude .git $(ROOT_DIR) $(ASIC_USER)@$(ASIC_SERVER):$(REMOTE_ROOT_DIR)
-	ssh $(ASIC_USER)@$(ASIC_SERVER) 'cd $(REMOTE_ROOT_DIR)/hardware/asic/$(ASIC_NODE); make $@ ASIC_NODE=$(ASIC_NODE)'
+	ssh $(ASIC_USER)@$(ASIC_SERVER) 'cd $(REMOTE_ROOT_DIR)/hardware/asic/$(ASIC_NODE); make clean'
 endif
 
 #clean test log only when asic testing begins
@@ -77,7 +80,7 @@ clean-testlog:
 ifneq ($(ASIC_SERVER),)
 	ssh $(ASIC_USER)@$(ASIC_SERVER) 'if [ ! -d $(REMOTE_ROOT_DIR) ]; then mkdir -p $(REMOTE_ROOT_DIR); fi'
 	rsync -avz --exclude .git $(ROOT_DIR) $(ASIC_USER)@$(ASIC_SERVER):$(REMOTE_ROOT_DIR)
-	ssh $(ASIC_USER)@$(ASIC_SERVER) 'cd $(REMOTE_ROOT_DIR)/hardware/asic/$(ASIC_NODE); make $@ ASIC_NODE=$(ASIC_NODE)'
+	ssh $(ASIC_USER)@$(ASIC_SERVER) 'cd $(REMOTE_ROOT_DIR)/hardware/asic/$(ASIC_NODE); make $@'
 endif
 
 .PHONY: all \
diff --git a/hardware/asic/umc130/Makefile b/hardware/asic/umc130/Makefile
index cad4dad4d..8bf3f7d62 100644
--- a/hardware/asic/umc130/Makefile
+++ b/hardware/asic/umc130/Makefile
@@ -3,6 +3,7 @@ ROOT_DIR:=../../..
 ASIC_MEM_LEFS=*.lef
 ASIC_MEM_LIBS=*$(CASE).lib
 ASIC_MEM_SIM_MODELS=*LD130*.v
+ASIC_REPORTS=*.txt
 
 ASIC_SERVER=$(CADENCE_SERVER)
 ASIC_USER=$(CADENCE_USER)
@@ -54,6 +55,7 @@ ifeq ($(ASIC_SERVER),)
 	echo "set INCLUDE [list $(INCLUDE)]" > inc.tcl
 	echo "set DEFINE [list $(DEFINE)]" > defs.tcl
 	echo "set VSRC [glob $(VSRC)]" > vsrc.tcl
+	echo "set CASE $(CASE)" > case.tcl
 	./synth.sh
 else
 	ssh $(ASIC_USER)@$(ASIC_SERVER) 'if [ ! -d $(REMOTE_ROOT_DIR) ]; then mkdir -p $(REMOTE_ROOT_DIR); fi'
@@ -66,7 +68,7 @@ endif
 #
 
 clean: clean-remote
-	rm -rf *.txt rc.cmd* rc.* fv libscore_work *.sdc *.lib *.lef *.db
+	rm -rf *.txt rc.cmd* rc.* fv libscore_work *.sdc *.lib *.lef *.ds
 	find *.tcl -type f -not -name synscript.tcl -not -name powscript.tcl -delete
 
 .PHONY: gen-bootrom gen-sram \
diff --git a/hardware/asic/umc130/synscript.tcl b/hardware/asic/umc130/synscript.tcl
index 5871e708e..de8419b17 100644
--- a/hardware/asic/umc130/synscript.tcl
+++ b/hardware/asic/umc130/synscript.tcl
@@ -1,7 +1,7 @@
 #
 # library and hdl search paths
 set_attribute lib_search_path [list /opt/ic_tools/pdk/faraday/umc130/LL/fsc0l_d/2009Q2v3.0/GENERIC_CORE/FrontEnd/synopsys .]
-set libs [glob *.lib]
+set libs [glob *$CASE.lib]
 set_attribute library [list fsc0l_d_generic_core_tt1p2v25c.lib $libs]
 set_attribute hdl_search_path $INCLUDE
 #
diff --git a/hardware/asic/umc130/synth.sh b/hardware/asic/umc130/synth.sh
index 9719960f9..ec49e5f49 100755
--- a/hardware/asic/umc130/synth.sh
+++ b/hardware/asic/umc130/synth.sh
@@ -1,4 +1,4 @@
 #!/bin/bash
 source /opt/ic_tools/init/init-rc14_25_hf000
-echo "quit" | rc -files inc.tcl -files defs.tcl -files vsrc.tcl -files synscript.tcl
+echo "quit" | rc -files inc.tcl -files defs.tcl -files vsrc.tcl -files case.tcl -files synscript.tcl
 echo "quit"

From 9353966494f5135ba98aed8cfef3f5ff7d43f031 Mon Sep 17 00:00:00 2001
From: Joao D Lopes <joao.d.lopes91@gmail.com>
Date: Sun, 17 Oct 2021 18:59:54 +0100
Subject: [PATCH 3/4] update CACHE submodule; update sources according new
 submodule

---
 hardware/asic/asic.mk   |  4 ++--
 hardware/hardware.mk    | 16 ++++++++++------
 hardware/src/boot_ctr.v |  2 +-
 hardware/src/sram.v     |  4 ++--
 submodules/CACHE        |  2 +-
 5 files changed, 16 insertions(+), 12 deletions(-)

diff --git a/hardware/asic/asic.mk b/hardware/asic/asic.mk
index 91913d247..b58fabb23 100644
--- a/hardware/asic/asic.mk
+++ b/hardware/asic/asic.mk
@@ -39,10 +39,10 @@ bootrom: sw gen-bootrom
 sram: gen-sram
 
 bootrom.v:
-	$(MEM_DIR)/software/python/memakerwrap.py fsc0l_d sp $(BOOTROM_W) 32 1 > $@
+	$(MEM_DIR)/software/python/memakerwrap.py fsc0l_d iob_sp_rom sp $(BOOTROM_W) 32 1 > $@
 
 sram.v:
-	$(MEM_DIR)/software/python/memakerwrap.py fsc0l_d sj 0 1 $(SRAM_W) 8 4 16 > $@
+	$(MEM_DIR)/software/python/memakerwrap.py fsc0l_d iob_dp_ram_be sj 0 1 $(SRAM_W) 8 4 16 > $@
 
 #
 # Synthesis
diff --git a/hardware/hardware.mk b/hardware/hardware.mk
index 61ecf889c..939eb5a61 100644
--- a/hardware/hardware.mk
+++ b/hardware/hardware.mk
@@ -15,19 +15,26 @@ ifeq ($(USE_DDR),1)
 include $(CACHE_DIR)/hardware/hardware.mk
 endif
 
-ifneq ($(ASIC_MEM),1)
+ifneq ($(ASIC),1)
 #rom
+ifneq (SPROM,$(filter SPROM, $(SUBMODULES)))
 SUBMODULES+=SPROM
 SPROM_DIR:=$(MEM_DIR)/sp_rom
-VSRC+=$(SPROM_DIR)/sp_rom.v
+VSRC+=$(SPROM_DIR)/iob_sp_rom.v
+endif
+
 #ram
+ifneq (DPRAM,$(filter DPRAM, $(SUBMODULES)))
 SUBMODULES+=DPRAM
 DPRAM_DIR:=$(MEM_DIR)/dp_ram
 VSRC+=$(DPRAM_DIR)/iob_dp_ram.v
+endif
+ifneq (DPRAM_BE,$(filter DPRAM_BE, $(SUBMODULES)))
 SUBMODULES+=DPRAM_BE
 DPRAM_BE_DIR:=$(MEM_DIR)/dp_ram_be
 VSRC+=$(DPRAM_BE_DIR)/iob_dp_ram_be.v
 endif
+endif
 
 #peripherals
 $(foreach p, $(PERIPHERALS), $(eval include $(SUBMODULES_DIR)/$p/hardware/hardware.mk))
@@ -56,10 +63,7 @@ VSRC+=$(SRC_DIR)/ext_mem.v
 endif
 
 #system
-VSRC+=$(SRC_DIR)/boot_ctr.v $(SRC_DIR)/int_mem.v
-ifneq ($(ASIC_MEM),1)
-VSRC+=$(SRC_DIR)/sram.v
-endif
+VSRC+=$(SRC_DIR)/boot_ctr.v $(SRC_DIR)/int_mem.v $(SRC_DIR)/sram.v
 VSRC+=system.v
 
 IMAGES=boot.hex firmware.hex
diff --git a/hardware/src/boot_ctr.v b/hardware/src/boot_ctr.v
index aeeda4266..31bc8bf9a 100644
--- a/hardware/src/boot_ctr.v
+++ b/hardware/src/boot_ctr.v
@@ -104,7 +104,7 @@ module boot_ctr
    //
    //INSTANTIATE ROM
    //
-   sp_rom 
+   iob_sp_rom
      #(
        .DATA_W(`DATA_W),
        .ADDR_W(`BOOTROM_ADDR_W-2),
diff --git a/hardware/src/sram.v b/hardware/src/sram.v
index 8e1d078e4..cec873366 100644
--- a/hardware/src/sram.v
+++ b/hardware/src/sram.v
@@ -28,8 +28,8 @@ module sram #(
    iob_dp_ram_be
      #(
        .FILE(FILE),
-       .ADDR_WIDTH(`SRAM_ADDR_W-2),
-       .DATA_WIDTH(`DATA_W)
+       .ADDR_W(`SRAM_ADDR_W-2),
+       .DATA_W(`DATA_W)
        )
    main_mem_byte
      (
diff --git a/submodules/CACHE b/submodules/CACHE
index 8f23df42c..e3975c42c 160000
--- a/submodules/CACHE
+++ b/submodules/CACHE
@@ -1 +1 @@
-Subproject commit 8f23df42cbfd2024dccfb1039c71f834f369ba9c
+Subproject commit e3975c42c0bb4508e9eea6a3f4fbf425756cf8e5

From da68c6d97f0c55d96613ab6e8838f738fc98513c Mon Sep 17 00:00:00 2001
From: Joao D Lopes <joao.d.lopes91@gmail.com>
Date: Sun, 17 Oct 2021 19:07:18 +0100
Subject: [PATCH 4/4] rename XMSIM_SERVER and XMSIM_USER variables to
 CADENCE_SERVER and CADENCE_USER

---
 hardware/simulation/xcelium/Makefile | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hardware/simulation/xcelium/Makefile b/hardware/simulation/xcelium/Makefile
index 4dd9402e8..4d01673c6 100644
--- a/hardware/simulation/xcelium/Makefile
+++ b/hardware/simulation/xcelium/Makefile
@@ -4,8 +4,8 @@ defmacro:=-define
 incdir:=-incdir 
 
 SIMULATOR=xcelium
-SIM_SERVER ?=$(XMSIM_SERVER)
-SIM_USER ?=$(XMSIM_USER)
+SIM_SERVER=$(CADENCE_SERVER)
+SIM_USER=$(CADENCE_USER)
 SIM_PROC=xmsim
 
 include ../simulation.mk